Hardware Libraries  20.1
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alt_usb.h
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32 
33 /* Altera - ALT_USB_GLOB */
34 
35 #ifndef __ALT_SOCAL_USB_H__
36 #define __ALT_SOCAL_USB_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_USB_GLOB
50  *
51  */
52 /*
53  * Register : gotgctl
54  *
55  * OTG Control and Status Register
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :--------|:-------|:------|:----------------------------------
61  * [0] | R | 0x0 | ALT_USB_GLOB_GOTGCTL_SESREQSCS
62  * [1] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_SESREQ
63  * [2] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN
64  * [3] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL
65  * [4] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_AVALIDOVEN
66  * [5] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL
67  * [6] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_BVALIDOVEN
68  * [7] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL
69  * [8] | R | 0x0 | ALT_USB_GLOB_GOTGCTL_HSTNEGSCS
70  * [9] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_HNPREQ
71  * [10] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN
72  * [11] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_DEVHNPEN
73  * [13:12] | ??? | 0x0 | *UNDEFINED*
74  * [14] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_EHEN
75  * [15] | ??? | 0x0 | *UNDEFINED*
76  * [16] | R | 0x1 | ALT_USB_GLOB_GOTGCTL_CONIDSTS
77  * [17] | R | 0x0 | ALT_USB_GLOB_GOTGCTL_DBNCTIME
78  * [18] | R | 0x0 | ALT_USB_GLOB_GOTGCTL_ASESVLD
79  * [19] | R | 0x0 | ALT_USB_GLOB_GOTGCTL_BSESVLD
80  * [20] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_OTGVER
81  * [21] | R | 0x0 | ALT_USB_GLOB_GOTGCTL_CURMOD
82  * [31:22] | ??? | 0x0 | *UNDEFINED*
83  *
84  */
85 /*
86  * Field : sesreqscs
87  *
88  * Mode: Device only
89  *
90  * Session Request Success (SesReqScs)
91  *
92  * The core sets this bit when a session request initiation is
93  *
94  * successful.
95  *
96  * 1'b0: Session request failure
97  *
98  * 1'b1: Session request success
99  *
100  * Field Enumeration Values:
101  *
102  * Enum | Value | Description
103  * :-----------------------------------------|:------|:------------------------
104  * ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_FAIL | 0x0 | Session request failure
105  * ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_SUCCESS | 0x1 | Session request success
106  *
107  * Field Access Macros:
108  *
109  */
110 /*
111  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQSCS
112  *
113  * Session request failure
114  */
115 #define ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_FAIL 0x0
116 /*
117  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQSCS
118  *
119  * Session request success
120  */
121 #define ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_SUCCESS 0x1
122 
123 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */
124 #define ALT_USB_GLOB_GOTGCTL_SESREQSCS_LSB 0
125 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */
126 #define ALT_USB_GLOB_GOTGCTL_SESREQSCS_MSB 0
127 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */
128 #define ALT_USB_GLOB_GOTGCTL_SESREQSCS_WIDTH 1
129 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field value. */
130 #define ALT_USB_GLOB_GOTGCTL_SESREQSCS_SET_MSK 0x00000001
131 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field value. */
132 #define ALT_USB_GLOB_GOTGCTL_SESREQSCS_CLR_MSK 0xfffffffe
133 /* The reset value of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */
134 #define ALT_USB_GLOB_GOTGCTL_SESREQSCS_RESET 0x0
135 /* Extracts the ALT_USB_GLOB_GOTGCTL_SESREQSCS field value from a register. */
136 #define ALT_USB_GLOB_GOTGCTL_SESREQSCS_GET(value) (((value) & 0x00000001) >> 0)
137 /* Produces a ALT_USB_GLOB_GOTGCTL_SESREQSCS register field value suitable for setting the register. */
138 #define ALT_USB_GLOB_GOTGCTL_SESREQSCS_SET(value) (((value) << 0) & 0x00000001)
139 
140 /*
141  * Field : sesreq
142  *
143  * Mode: Device only
144  *
145  * Session Request (SesReq)
146  *
147  * The application sets this bit to initiate a session request on the
148  *
149  * USB. The application can clear this bit by writing a 0 when the
150  *
151  * Host Negotiation Success Status Change bit in the OTG
152  *
153  * Interrupt register (GOTGINT.HstNegSucStsChng) is SET. The
154  *
155  * core clears this bit when the HstNegSucStsChng bit is cleared.
156  *
157  * If you use the USB 1.1 Full-Speed Serial Transceiver interface to
158  *
159  * initiate the session request, the application must wait until the
160  *
161  * VBUS discharges to 0.2 V, after the B-Session Valid bit in this
162  *
163  * register (GOTGCTL.BSesVld) is cleared. This discharge time
164  *
165  * varies between different PHYs and can be obtained from the
166  *
167  * PHY vendor.
168  *
169  * 1'b0: No session request
170  *
171  * 1'b1: Session request
172  *
173  * Field Enumeration Values:
174  *
175  * Enum | Value | Description
176  * :----------------------------------------|:------|:-------------------
177  * ALT_USB_GLOB_GOTGCTL_SESREQ_E_NOREQUEST | 0x0 | No session request
178  * ALT_USB_GLOB_GOTGCTL_SESREQ_E_REQUEST | 0x1 | Session request
179  *
180  * Field Access Macros:
181  *
182  */
183 /*
184  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQ
185  *
186  * No session request
187  */
188 #define ALT_USB_GLOB_GOTGCTL_SESREQ_E_NOREQUEST 0x0
189 /*
190  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQ
191  *
192  * Session request
193  */
194 #define ALT_USB_GLOB_GOTGCTL_SESREQ_E_REQUEST 0x1
195 
196 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */
197 #define ALT_USB_GLOB_GOTGCTL_SESREQ_LSB 1
198 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */
199 #define ALT_USB_GLOB_GOTGCTL_SESREQ_MSB 1
200 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */
201 #define ALT_USB_GLOB_GOTGCTL_SESREQ_WIDTH 1
202 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_SESREQ register field value. */
203 #define ALT_USB_GLOB_GOTGCTL_SESREQ_SET_MSK 0x00000002
204 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_SESREQ register field value. */
205 #define ALT_USB_GLOB_GOTGCTL_SESREQ_CLR_MSK 0xfffffffd
206 /* The reset value of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */
207 #define ALT_USB_GLOB_GOTGCTL_SESREQ_RESET 0x0
208 /* Extracts the ALT_USB_GLOB_GOTGCTL_SESREQ field value from a register. */
209 #define ALT_USB_GLOB_GOTGCTL_SESREQ_GET(value) (((value) & 0x00000002) >> 1)
210 /* Produces a ALT_USB_GLOB_GOTGCTL_SESREQ register field value suitable for setting the register. */
211 #define ALT_USB_GLOB_GOTGCTL_SESREQ_SET(value) (((value) << 1) & 0x00000002)
212 
213 /*
214  * Field : vbvalidoven
215  *
216  * VBUS Valid Override Enable (VbvalidOvEn)
217  *
218  * This bit is used to enable/disable the software to
219  *
220  * override the Bvalid signal using the GOTGCTL.VbvalidOvVal.
221  *
222  * 1'b1 : Internally Bvalid received from the PHY is overridden with
223  * GOTGCTL.VbvalidOvVal.
224  *
225  * 1'b0 : Override is disabled and bvalid signal from the respective PHY selected
226  * is used
227  *
228  * internally by the core
229  *
230  * Field Enumeration Values:
231  *
232  * Enum | Value | Description
233  * :----------------------------------------|:------|:------------------------------------------------
234  * ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_DISD | 0x0 | Override is disabled and bvalid signal from the
235  * : | | respective PHY selected is used internally by
236  * : | | the force
237  * ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_END | 0x1 | The vbus-valid signal received from the PHY is
238  * : | | overridden with GOTGCTL.vbvalidOvVal
239  *
240  * Field Access Macros:
241  *
242  */
243 /*
244  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN
245  *
246  * Override is disabled and bvalid signal from the respective PHY selected is used
247  * internally by the force
248  */
249 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_DISD 0x0
250 /*
251  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN
252  *
253  * The vbus-valid signal received from the PHY is overridden with
254  * GOTGCTL.vbvalidOvVal
255  */
256 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_END 0x1
257 
258 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */
259 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_LSB 2
260 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */
261 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_MSB 2
262 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */
263 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_WIDTH 1
264 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field value. */
265 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_SET_MSK 0x00000004
266 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field value. */
267 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_CLR_MSK 0xfffffffb
268 /* The reset value of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */
269 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_RESET 0x0
270 /* Extracts the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN field value from a register. */
271 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_GET(value) (((value) & 0x00000004) >> 2)
272 /* Produces a ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field value suitable for setting the register. */
273 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_SET(value) (((value) << 2) & 0x00000004)
274 
275 /*
276  * Field : vbvalidovval
277  *
278  * VBUS Valid OverrideValue (VbvalidOvVal)
279  *
280  * This bit is used to set Override value for vbusvalid
281  *
282  * signal when GOTGCTL.VbvalidOvEn is set.
283  *
284  * 1'b0 : vbusvalid value is 1'b0 when GOTGCTL.VbvalidOvEn =1
285  *
286  * 1'b1 : vbusvalid value is 1'b1 when GOTGCTL.VbvalidOvEn =1
287  *
288  * Field Enumeration Values:
289  *
290  * Enum | Value | Description
291  * :-----------------------------------------|:------|:----------------------------------------------
292  * ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET0 | 0x0 | vbusvalid value when GOTGCTL.VbvalidOvEn = 1
293  * ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET1 | 0x1 | vbusvalid value when GOTGCTL.VbvalidOvEn is 1
294  *
295  * Field Access Macros:
296  *
297  */
298 /*
299  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL
300  *
301  * vbusvalid value when GOTGCTL.VbvalidOvEn = 1
302  */
303 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET0 0x0
304 /*
305  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL
306  *
307  * vbusvalid value when GOTGCTL.VbvalidOvEn is 1
308  */
309 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET1 0x1
310 
311 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */
312 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_LSB 3
313 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */
314 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_MSB 3
315 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */
316 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_WIDTH 1
317 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field value. */
318 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_SET_MSK 0x00000008
319 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field value. */
320 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_CLR_MSK 0xfffffff7
321 /* The reset value of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */
322 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_RESET 0x0
323 /* Extracts the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL field value from a register. */
324 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_GET(value) (((value) & 0x00000008) >> 3)
325 /* Produces a ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field value suitable for setting the register. */
326 #define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_SET(value) (((value) << 3) & 0x00000008)
327 
328 /*
329  * Field : avalidoven
330  *
331  * A-Peripheral Session Valid Override Enable (AvalidOvEn)
332  *
333  * This bit is used to enable/disable the software to
334  *
335  * override the Avalid signal using the GOTGCTL.AvalidOvVal.
336  *
337  * 1'b1 : Internally Avalid received from the PHY is overridden with
338  * GOTGCTL.AvalidOvVal.
339  *
340  * 1'b0 : Override is disabled and avalid signal from the respective PHY selected
341  * is used
342  *
343  * internally by the core
344  *
345  * Field Enumeration Values:
346  *
347  * Enum | Value | Description
348  * :---------------------------------------|:------|:------------------------------------------------
349  * ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_DISD | 0x0 | Override is disabled and Avalid signal from the
350  * : | | respective PHY is used internally by the core.
351  * ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_END | 0x1 | Internally Avalid received from the PHY is
352  * : | | overridden with GOTGCTL.AvalidOvVa
353  *
354  * Field Access Macros:
355  *
356  */
357 /*
358  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVEN
359  *
360  * Override is disabled and Avalid signal from the respective PHY is used
361  * internally by the core.
362  */
363 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_DISD 0x0
364 /*
365  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVEN
366  *
367  * Internally Avalid received from the PHY is overridden with GOTGCTL.AvalidOvVa
368  */
369 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_END 0x1
370 
371 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */
372 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_LSB 4
373 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */
374 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_MSB 4
375 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */
376 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_WIDTH 1
377 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field value. */
378 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_SET_MSK 0x00000010
379 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field value. */
380 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_CLR_MSK 0xffffffef
381 /* The reset value of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */
382 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_RESET 0x0
383 /* Extracts the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN field value from a register. */
384 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_GET(value) (((value) & 0x00000010) >> 4)
385 /* Produces a ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field value suitable for setting the register. */
386 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_SET(value) (((value) << 4) & 0x00000010)
387 
388 /*
389  * Field : avalidovval
390  *
391  * A-Peripheral Session Valid OverrideValue (AvalidOvVal)
392  *
393  * This bit is used to set Override value for Avalid signal
394  *
395  * when GOTGCTL.AvalidOvEn is set.
396  *
397  * 1'b0 : Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1
398  *
399  * 1'b1 : Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1
400  *
401  * Field Enumeration Values:
402  *
403  * Enum | Value | Description
404  * :------------------------------------------|:------|:------------------------------------------------
405  * ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE0 | 0x0 | Avalid value is 1'b0 when GOTGCTL.BvalidOvEn =1
406  * ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE1 | 0x1 | Avalid value is 1'b1 when GOTGCTL.BvalidOvEn =1
407  *
408  * Field Access Macros:
409  *
410  */
411 /*
412  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL
413  *
414  * Avalid value is 1'b0 when GOTGCTL.BvalidOvEn =1
415  */
416 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE0 0x0
417 /*
418  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL
419  *
420  * Avalid value is 1'b1 when GOTGCTL.BvalidOvEn =1
421  */
422 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE1 0x1
423 
424 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */
425 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_LSB 5
426 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */
427 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_MSB 5
428 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */
429 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_WIDTH 1
430 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field value. */
431 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_SET_MSK 0x00000020
432 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field value. */
433 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_CLR_MSK 0xffffffdf
434 /* The reset value of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */
435 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_RESET 0x0
436 /* Extracts the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL field value from a register. */
437 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_GET(value) (((value) & 0x00000020) >> 5)
438 /* Produces a ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field value suitable for setting the register. */
439 #define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_SET(value) (((value) << 5) & 0x00000020)
440 
441 /*
442  * Field : bvalidoven
443  *
444  * B-Peripheral Session Valid Override Enable (BvalidOvEn)
445  *
446  * This bit is used to enable/disable the software to
447  *
448  * override the Bvalid signal using the GOTGCTL.BvalidOvVal.
449  *
450  * 1'b1 : Internally Bvalid received from the PHY is overridden with
451  * GOTGCTL.BvalidOvVal.
452  *
453  * 1'b0 : Override is disabled and bvalid signal from the respective PHY selected
454  * is used
455  *
456  * internally by the force
457  *
458  * Field Enumeration Values:
459  *
460  * Enum | Value | Description
461  * :---------------------------------------|:------|:------------------------------------------------
462  * ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_DISD | 0x0 | Override is disabled and bvalid signal from the
463  * : | | respective PHY selected is used internally by
464  * : | | the core
465  * ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_END | 0x1 | Internally Bvalid received from the PHY is
466  * : | | overridden with GOTGCTL.BvalidOvVal
467  *
468  * Field Access Macros:
469  *
470  */
471 /*
472  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVEN
473  *
474  * Override is disabled and bvalid signal from the respective PHY selected is used
475  * internally by the core
476  */
477 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_DISD 0x0
478 /*
479  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVEN
480  *
481  * Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal
482  */
483 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_END 0x1
484 
485 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */
486 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_LSB 6
487 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */
488 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_MSB 6
489 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */
490 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_WIDTH 1
491 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field value. */
492 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_SET_MSK 0x00000040
493 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field value. */
494 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_CLR_MSK 0xffffffbf
495 /* The reset value of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */
496 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_RESET 0x0
497 /* Extracts the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN field value from a register. */
498 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_GET(value) (((value) & 0x00000040) >> 6)
499 /* Produces a ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field value suitable for setting the register. */
500 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_SET(value) (((value) << 6) & 0x00000040)
501 
502 /*
503  * Field : bvalidovval
504  *
505  * B-Peripheral Session Valid OverrideValue (BvalidOvVal)
506  *
507  * This bit is used to set Override value for Bvalid
508  *
509  * signal when GOTGCTL.BvalidOvEn is set.
510  *
511  * 1'b0 : Bvalid value is 1'b0 when GOTGCTL.BvalidOvEn =1
512  *
513  * 1'b1 : Bvalid value is 1'b1 when GOTGCTL.BvalidOvEn =1
514  *
515  * Field Enumeration Values:
516  *
517  * Enum | Value | Description
518  * :------------------------------------------|:------|:----------------------------------------
519  * ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE0 | 0x0 | Bvalid value when GOTGCTL.AvalidOvEn =1
520  * ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE1 | 0x1 | Bvalid value when GOTGCTL.AvalidOvEn =1
521  *
522  * Field Access Macros:
523  *
524  */
525 /*
526  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL
527  *
528  * Bvalid value when GOTGCTL.AvalidOvEn =1
529  */
530 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE0 0x0
531 /*
532  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL
533  *
534  * Bvalid value when GOTGCTL.AvalidOvEn =1
535  */
536 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE1 0x1
537 
538 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */
539 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_LSB 7
540 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */
541 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_MSB 7
542 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */
543 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_WIDTH 1
544 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field value. */
545 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_SET_MSK 0x00000080
546 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field value. */
547 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_CLR_MSK 0xffffff7f
548 /* The reset value of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */
549 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_RESET 0x0
550 /* Extracts the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL field value from a register. */
551 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_GET(value) (((value) & 0x00000080) >> 7)
552 /* Produces a ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field value suitable for setting the register. */
553 #define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_SET(value) (((value) << 7) & 0x00000080)
554 
555 /*
556  * Field : hstnegscs
557  *
558  * Mode: Device only
559  *
560  * Host Negotiation Success (HstNegScs)
561  *
562  * The core sets this bit when host negotiation is successful. The
563  *
564  * core clears this bit when the HNP Request (HNPReq) bit in this
565  *
566  * register is SET.
567  *
568  * 1'b0: Host negotiation failure
569  *
570  * 1'b1: Host negotiation success
571  *
572  * Field Enumeration Values:
573  *
574  * Enum | Value | Description
575  * :-----------------------------------------|:------|:-------------------------
576  * ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_FAIL | 0x0 | Host negotiation failure
577  * ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_SUCCESS | 0x1 | Host negotiation success
578  *
579  * Field Access Macros:
580  *
581  */
582 /*
583  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTNEGSCS
584  *
585  * Host negotiation failure
586  */
587 #define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_FAIL 0x0
588 /*
589  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTNEGSCS
590  *
591  * Host negotiation success
592  */
593 #define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_SUCCESS 0x1
594 
595 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */
596 #define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_LSB 8
597 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */
598 #define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_MSB 8
599 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */
600 #define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_WIDTH 1
601 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field value. */
602 #define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_SET_MSK 0x00000100
603 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field value. */
604 #define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_CLR_MSK 0xfffffeff
605 /* The reset value of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */
606 #define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_RESET 0x0
607 /* Extracts the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS field value from a register. */
608 #define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_GET(value) (((value) & 0x00000100) >> 8)
609 /* Produces a ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field value suitable for setting the register. */
610 #define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_SET(value) (((value) << 8) & 0x00000100)
611 
612 /*
613  * Field : hnpreq
614  *
615  * Mode: Device only
616  *
617  * HNP Request (HNPReq)
618  *
619  * The application sets this bit to initiate an HNP request to the
620  *
621  * connected USB host. The application can clear this bit by writing
622  *
623  * a 0 when the Host Negotiation Success Status Change bit in the
624  *
625  * OTG Interrupt register (GOTGINT.HstNegSucStsChng) is SET.
626  *
627  * The core clears this bit when the HstNegSucStsChng bit is
628  *
629  * cleared.
630  *
631  * 1'b0: No HNP request
632  *
633  * 1'b1: HNP request
634  *
635  * Field Enumeration Values:
636  *
637  * Enum | Value | Description
638  * :-----------------------------------|:------|:---------------
639  * ALT_USB_GLOB_GOTGCTL_HNPREQ_E_DISD | 0x0 | No HNP request
640  * ALT_USB_GLOB_GOTGCTL_HNPREQ_E_END | 0x1 | HNP request
641  *
642  * Field Access Macros:
643  *
644  */
645 /*
646  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HNPREQ
647  *
648  * No HNP request
649  */
650 #define ALT_USB_GLOB_GOTGCTL_HNPREQ_E_DISD 0x0
651 /*
652  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HNPREQ
653  *
654  * HNP request
655  */
656 #define ALT_USB_GLOB_GOTGCTL_HNPREQ_E_END 0x1
657 
658 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */
659 #define ALT_USB_GLOB_GOTGCTL_HNPREQ_LSB 9
660 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */
661 #define ALT_USB_GLOB_GOTGCTL_HNPREQ_MSB 9
662 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */
663 #define ALT_USB_GLOB_GOTGCTL_HNPREQ_WIDTH 1
664 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_HNPREQ register field value. */
665 #define ALT_USB_GLOB_GOTGCTL_HNPREQ_SET_MSK 0x00000200
666 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_HNPREQ register field value. */
667 #define ALT_USB_GLOB_GOTGCTL_HNPREQ_CLR_MSK 0xfffffdff
668 /* The reset value of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */
669 #define ALT_USB_GLOB_GOTGCTL_HNPREQ_RESET 0x0
670 /* Extracts the ALT_USB_GLOB_GOTGCTL_HNPREQ field value from a register. */
671 #define ALT_USB_GLOB_GOTGCTL_HNPREQ_GET(value) (((value) & 0x00000200) >> 9)
672 /* Produces a ALT_USB_GLOB_GOTGCTL_HNPREQ register field value suitable for setting the register. */
673 #define ALT_USB_GLOB_GOTGCTL_HNPREQ_SET(value) (((value) << 9) & 0x00000200)
674 
675 /*
676  * Field : hstsethnpen
677  *
678  * Mode: Host only
679  *
680  * Host Set HNP Enable (HstSetHNPEn)
681  *
682  * The application sets this bit when it has successfully enabled
683  *
684  * HNP (using the SetFeature.SetHNPEnable command) on the
685  *
686  * connected device.
687  *
688  * 1'b0: Host Set HNP is not enabled
689  *
690  * 1'b1: Host Set HNP is enabled
691  *
692  * Field Enumeration Values:
693  *
694  * Enum | Value | Description
695  * :----------------------------------------|:------|:----------------------------
696  * ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_DISD | 0x0 | Host Set HNP is not enabled
697  * ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_END | 0x1 | Host Set HNP is enabled
698  *
699  * Field Access Macros:
700  *
701  */
702 /*
703  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN
704  *
705  * Host Set HNP is not enabled
706  */
707 #define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_DISD 0x0
708 /*
709  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN
710  *
711  * Host Set HNP is enabled
712  */
713 #define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_END 0x1
714 
715 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */
716 #define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_LSB 10
717 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */
718 #define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_MSB 10
719 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */
720 #define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_WIDTH 1
721 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field value. */
722 #define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_SET_MSK 0x00000400
723 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field value. */
724 #define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_CLR_MSK 0xfffffbff
725 /* The reset value of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */
726 #define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_RESET 0x0
727 /* Extracts the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN field value from a register. */
728 #define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_GET(value) (((value) & 0x00000400) >> 10)
729 /* Produces a ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field value suitable for setting the register. */
730 #define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_SET(value) (((value) << 10) & 0x00000400)
731 
732 /*
733  * Field : devhnpen
734  *
735  * Mode: Device only
736  *
737  * Device HNP Enabled (DevHNPEn)
738  *
739  * The application sets this bit when it successfully receives a
740  *
741  * SetFeature.SetHNPEnable command from the connected USB
742  *
743  * host.
744  *
745  * 1'b0: HNP is not enabled in the application
746  *
747  * 1'b1: HNP is enabled in the application
748  *
749  * Field Enumeration Values:
750  *
751  * Enum | Value | Description
752  * :-------------------------------------|:------|:--------------------------------------
753  * ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_DISD | 0x0 | HNP is not enabled in the application
754  * ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_END | 0x1 | HNP Enabled
755  *
756  * Field Access Macros:
757  *
758  */
759 /*
760  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DEVHNPEN
761  *
762  * HNP is not enabled in the application
763  */
764 #define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_DISD 0x0
765 /*
766  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DEVHNPEN
767  *
768  * HNP Enabled
769  */
770 #define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_END 0x1
771 
772 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */
773 #define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_LSB 11
774 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */
775 #define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_MSB 11
776 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */
777 #define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_WIDTH 1
778 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field value. */
779 #define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_SET_MSK 0x00000800
780 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field value. */
781 #define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_CLR_MSK 0xfffff7ff
782 /* The reset value of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */
783 #define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_RESET 0x0
784 /* Extracts the ALT_USB_GLOB_GOTGCTL_DEVHNPEN field value from a register. */
785 #define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_GET(value) (((value) & 0x00000800) >> 11)
786 /* Produces a ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field value suitable for setting the register. */
787 #define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_SET(value) (((value) << 11) & 0x00000800)
788 
789 /*
790  * Field : ehen
791  *
792  * Mode: SRP Capable Host
793  *
794  * Embedded Host Enable (EHEn)
795  *
796  * 1'b1 : Enable Embedded Host Mode.
797  *
798  * 1'b0: Disable Embedded Host Mode.
799  *
800  * Field Access Macros:
801  *
802  */
803 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_EHEN register field. */
804 #define ALT_USB_GLOB_GOTGCTL_EHEN_LSB 14
805 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_EHEN register field. */
806 #define ALT_USB_GLOB_GOTGCTL_EHEN_MSB 14
807 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_EHEN register field. */
808 #define ALT_USB_GLOB_GOTGCTL_EHEN_WIDTH 1
809 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_EHEN register field value. */
810 #define ALT_USB_GLOB_GOTGCTL_EHEN_SET_MSK 0x00004000
811 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_EHEN register field value. */
812 #define ALT_USB_GLOB_GOTGCTL_EHEN_CLR_MSK 0xffffbfff
813 /* The reset value of the ALT_USB_GLOB_GOTGCTL_EHEN register field. */
814 #define ALT_USB_GLOB_GOTGCTL_EHEN_RESET 0x0
815 /* Extracts the ALT_USB_GLOB_GOTGCTL_EHEN field value from a register. */
816 #define ALT_USB_GLOB_GOTGCTL_EHEN_GET(value) (((value) & 0x00004000) >> 14)
817 /* Produces a ALT_USB_GLOB_GOTGCTL_EHEN register field value suitable for setting the register. */
818 #define ALT_USB_GLOB_GOTGCTL_EHEN_SET(value) (((value) << 14) & 0x00004000)
819 
820 /*
821  * Field : conidsts
822  *
823  * Mode: Host and Device
824  *
825  * Connector ID Status (ConIDSts)
826  *
827  * Indicates the connector ID status on a connect event.
828  *
829  * 1'b0: The DWC_otg core is in A-Device mode
830  *
831  * 1'b1: The DWC_otg core is in B-Device mode
832  *
833  * Field Enumeration Values:
834  *
835  * Enum | Value | Description
836  * :-------------------------------------|:------|:-------------------------------------
837  * ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODA | 0x0 | The DWC_otg core is in A-Device mode
838  * ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODB | 0x1 | The otg core is in B-Device mode
839  *
840  * Field Access Macros:
841  *
842  */
843 /*
844  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_CONIDSTS
845  *
846  * The DWC_otg core is in A-Device mode
847  */
848 #define ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODA 0x0
849 /*
850  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_CONIDSTS
851  *
852  * The otg core is in B-Device mode
853  */
854 #define ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODB 0x1
855 
856 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */
857 #define ALT_USB_GLOB_GOTGCTL_CONIDSTS_LSB 16
858 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */
859 #define ALT_USB_GLOB_GOTGCTL_CONIDSTS_MSB 16
860 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */
861 #define ALT_USB_GLOB_GOTGCTL_CONIDSTS_WIDTH 1
862 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field value. */
863 #define ALT_USB_GLOB_GOTGCTL_CONIDSTS_SET_MSK 0x00010000
864 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field value. */
865 #define ALT_USB_GLOB_GOTGCTL_CONIDSTS_CLR_MSK 0xfffeffff
866 /* The reset value of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */
867 #define ALT_USB_GLOB_GOTGCTL_CONIDSTS_RESET 0x1
868 /* Extracts the ALT_USB_GLOB_GOTGCTL_CONIDSTS field value from a register. */
869 #define ALT_USB_GLOB_GOTGCTL_CONIDSTS_GET(value) (((value) & 0x00010000) >> 16)
870 /* Produces a ALT_USB_GLOB_GOTGCTL_CONIDSTS register field value suitable for setting the register. */
871 #define ALT_USB_GLOB_GOTGCTL_CONIDSTS_SET(value) (((value) << 16) & 0x00010000)
872 
873 /*
874  * Field : dbnctime
875  *
876  * Mode: Host only
877  *
878  * Long/Short Debounce Time (DbncTime)
879  *
880  * Indicates the debounce time of a detected connection.
881  *
882  * 1'b0: Long debounce time, used FOR physical connections
883  *
884  * (100 ms + 2.5 micro-sec)
885  *
886  * 1'b1: Short debounce time, used FOR soft connections (2.5 micro-sec)
887  *
888  * Field Enumeration Values:
889  *
890  * Enum | Value | Description
891  * :--------------------------------------|:------|:-----------------------------------------------
892  * ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_LONG | 0x0 | Long debounce time, used FOR physical
893  * : | | connections (100 ms + 2.5 s)
894  * ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_SHORT | 0x1 | Short debounce time, used FOR soft connections
895  * : | | (2.5 s
896  *
897  * Field Access Macros:
898  *
899  */
900 /*
901  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DBNCTIME
902  *
903  * Long debounce time, used FOR physical connections (100 ms + 2.5 s)
904  */
905 #define ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_LONG 0x0
906 /*
907  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DBNCTIME
908  *
909  * Short debounce time, used FOR soft connections (2.5 s
910  */
911 #define ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_SHORT 0x1
912 
913 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */
914 #define ALT_USB_GLOB_GOTGCTL_DBNCTIME_LSB 17
915 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */
916 #define ALT_USB_GLOB_GOTGCTL_DBNCTIME_MSB 17
917 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */
918 #define ALT_USB_GLOB_GOTGCTL_DBNCTIME_WIDTH 1
919 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field value. */
920 #define ALT_USB_GLOB_GOTGCTL_DBNCTIME_SET_MSK 0x00020000
921 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field value. */
922 #define ALT_USB_GLOB_GOTGCTL_DBNCTIME_CLR_MSK 0xfffdffff
923 /* The reset value of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */
924 #define ALT_USB_GLOB_GOTGCTL_DBNCTIME_RESET 0x0
925 /* Extracts the ALT_USB_GLOB_GOTGCTL_DBNCTIME field value from a register. */
926 #define ALT_USB_GLOB_GOTGCTL_DBNCTIME_GET(value) (((value) & 0x00020000) >> 17)
927 /* Produces a ALT_USB_GLOB_GOTGCTL_DBNCTIME register field value suitable for setting the register. */
928 #define ALT_USB_GLOB_GOTGCTL_DBNCTIME_SET(value) (((value) << 17) & 0x00020000)
929 
930 /*
931  * Field : asesvld
932  *
933  * Mode: Host only
934  *
935  * A-Session Valid (ASesVld)
936  *
937  * Indicates the Host mode transceiver status.
938  *
939  * 1'b0: A-session is not valid
940  *
941  * 1'b1: A-session is valid
942  *
943  * Note: If you do not enabled OTG features (such as SRP and HNP), the
944  *
945  * read reset value will be 1.The vbus assigns the values internally for non-
946  *
947  * SRP or non-HNP configurations.
948  *
949  * Field Enumeration Values:
950  *
951  * Enum | Value | Description
952  * :----------------------------------------|:------|:-----------------------
953  * ALT_USB_GLOB_GOTGCTL_ASESVLD_E_VALID | 0x0 | A-session is not valid
954  * ALT_USB_GLOB_GOTGCTL_ASESVLD_E_NOTVALID | 0x1 | A-session is valid
955  *
956  * Field Access Macros:
957  *
958  */
959 /*
960  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_ASESVLD
961  *
962  * A-session is not valid
963  */
964 #define ALT_USB_GLOB_GOTGCTL_ASESVLD_E_VALID 0x0
965 /*
966  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_ASESVLD
967  *
968  * A-session is valid
969  */
970 #define ALT_USB_GLOB_GOTGCTL_ASESVLD_E_NOTVALID 0x1
971 
972 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */
973 #define ALT_USB_GLOB_GOTGCTL_ASESVLD_LSB 18
974 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */
975 #define ALT_USB_GLOB_GOTGCTL_ASESVLD_MSB 18
976 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */
977 #define ALT_USB_GLOB_GOTGCTL_ASESVLD_WIDTH 1
978 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_ASESVLD register field value. */
979 #define ALT_USB_GLOB_GOTGCTL_ASESVLD_SET_MSK 0x00040000
980 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_ASESVLD register field value. */
981 #define ALT_USB_GLOB_GOTGCTL_ASESVLD_CLR_MSK 0xfffbffff
982 /* The reset value of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */
983 #define ALT_USB_GLOB_GOTGCTL_ASESVLD_RESET 0x0
984 /* Extracts the ALT_USB_GLOB_GOTGCTL_ASESVLD field value from a register. */
985 #define ALT_USB_GLOB_GOTGCTL_ASESVLD_GET(value) (((value) & 0x00040000) >> 18)
986 /* Produces a ALT_USB_GLOB_GOTGCTL_ASESVLD register field value suitable for setting the register. */
987 #define ALT_USB_GLOB_GOTGCTL_ASESVLD_SET(value) (((value) << 18) & 0x00040000)
988 
989 /*
990  * Field : bsesvld
991  *
992  * Mode: Device only
993  *
994  * B-Session Valid (BSesVld)
995  *
996  * Indicates the Device mode transceiver status.
997  *
998  * 1'b0: B-session is not valid.
999  *
1000  * 1'b1: B-session is valid.
1001  *
1002  * In OTG mode, you can use this bit to determine IF the device is
1003  *
1004  * connected or disconnected.
1005  *
1006  * Note: If you do not enabled OTG features (such as SRP and HNP), the
1007  *
1008  * read reset value will be 1.The vbus assigns the values internally for non-
1009  *
1010  * SRP or non-HNP configurations.
1011  *
1012  * Field Enumeration Values:
1013  *
1014  * Enum | Value | Description
1015  * :----------------------------------------|:------|:-----------------------
1016  * ALT_USB_GLOB_GOTGCTL_BSESVLD_E_NOTVALID | 0x0 | B-session is not valid
1017  * ALT_USB_GLOB_GOTGCTL_BSESVLD_E_VALID | 0x1 | B-session is valid
1018  *
1019  * Field Access Macros:
1020  *
1021  */
1022 /*
1023  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BSESVLD
1024  *
1025  * B-session is not valid
1026  */
1027 #define ALT_USB_GLOB_GOTGCTL_BSESVLD_E_NOTVALID 0x0
1028 /*
1029  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BSESVLD
1030  *
1031  * B-session is valid
1032  */
1033 #define ALT_USB_GLOB_GOTGCTL_BSESVLD_E_VALID 0x1
1034 
1035 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */
1036 #define ALT_USB_GLOB_GOTGCTL_BSESVLD_LSB 19
1037 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */
1038 #define ALT_USB_GLOB_GOTGCTL_BSESVLD_MSB 19
1039 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */
1040 #define ALT_USB_GLOB_GOTGCTL_BSESVLD_WIDTH 1
1041 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_BSESVLD register field value. */
1042 #define ALT_USB_GLOB_GOTGCTL_BSESVLD_SET_MSK 0x00080000
1043 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_BSESVLD register field value. */
1044 #define ALT_USB_GLOB_GOTGCTL_BSESVLD_CLR_MSK 0xfff7ffff
1045 /* The reset value of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */
1046 #define ALT_USB_GLOB_GOTGCTL_BSESVLD_RESET 0x0
1047 /* Extracts the ALT_USB_GLOB_GOTGCTL_BSESVLD field value from a register. */
1048 #define ALT_USB_GLOB_GOTGCTL_BSESVLD_GET(value) (((value) & 0x00080000) >> 19)
1049 /* Produces a ALT_USB_GLOB_GOTGCTL_BSESVLD register field value suitable for setting the register. */
1050 #define ALT_USB_GLOB_GOTGCTL_BSESVLD_SET(value) (((value) << 19) & 0x00080000)
1051 
1052 /*
1053  * Field : otgver
1054  *
1055  * OTG Version (OTGVer)
1056  *
1057  * Indicates the OTG revision.
1058  *
1059  * 1'b0: OTG Version 1.3. In this version the core supports Data line
1060  *
1061  * pulsing and VBus pulsing for SRP.
1062  *
1063  * 1'b1: OTG Version 2.0. In this version the core supports only Data
1064  *
1065  * line pulsing for SRP.
1066  *
1067  * Field Enumeration Values:
1068  *
1069  * Enum | Value | Description
1070  * :------------------------------------|:------|:------------------------------------------
1071  * ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER13 | 0x0 | OTG Version 1.3. In this version the core
1072  * : | | supports Data line
1073  * ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER20 | 0x1 | OTG Version 2.0. In this version the core
1074  * : | | supports only Data line pulsing for SRP
1075  *
1076  * Field Access Macros:
1077  *
1078  */
1079 /*
1080  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_OTGVER
1081  *
1082  * OTG Version 1.3. In this version the core supports Data line
1083  */
1084 #define ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER13 0x0
1085 /*
1086  * Enumerated value for register field ALT_USB_GLOB_GOTGCTL_OTGVER
1087  *
1088  * OTG Version 2.0. In this version the core supports only Data line pulsing for
1089  * SRP
1090  */
1091 #define ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER20 0x1
1092 
1093 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */
1094 #define ALT_USB_GLOB_GOTGCTL_OTGVER_LSB 20
1095 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */
1096 #define ALT_USB_GLOB_GOTGCTL_OTGVER_MSB 20
1097 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */
1098 #define ALT_USB_GLOB_GOTGCTL_OTGVER_WIDTH 1
1099 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_OTGVER register field value. */
1100 #define ALT_USB_GLOB_GOTGCTL_OTGVER_SET_MSK 0x00100000
1101 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_OTGVER register field value. */
1102 #define ALT_USB_GLOB_GOTGCTL_OTGVER_CLR_MSK 0xffefffff
1103 /* The reset value of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */
1104 #define ALT_USB_GLOB_GOTGCTL_OTGVER_RESET 0x0
1105 /* Extracts the ALT_USB_GLOB_GOTGCTL_OTGVER field value from a register. */
1106 #define ALT_USB_GLOB_GOTGCTL_OTGVER_GET(value) (((value) & 0x00100000) >> 20)
1107 /* Produces a ALT_USB_GLOB_GOTGCTL_OTGVER register field value suitable for setting the register. */
1108 #define ALT_USB_GLOB_GOTGCTL_OTGVER_SET(value) (((value) << 20) & 0x00100000)
1109 
1110 /*
1111  * Field : curmod
1112  *
1113  * Mode: Host and Device
1114  *
1115  * Current Mode of Operation (CurMod)
1116  *
1117  * Indicates the current mode.
1118  *
1119  * 1'b0: Device mode
1120  *
1121  * 1'b1: Host mode
1122  *
1123  * Field Access Macros:
1124  *
1125  */
1126 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_CURMOD register field. */
1127 #define ALT_USB_GLOB_GOTGCTL_CURMOD_LSB 21
1128 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_CURMOD register field. */
1129 #define ALT_USB_GLOB_GOTGCTL_CURMOD_MSB 21
1130 /* The width in bits of the ALT_USB_GLOB_GOTGCTL_CURMOD register field. */
1131 #define ALT_USB_GLOB_GOTGCTL_CURMOD_WIDTH 1
1132 /* The mask used to set the ALT_USB_GLOB_GOTGCTL_CURMOD register field value. */
1133 #define ALT_USB_GLOB_GOTGCTL_CURMOD_SET_MSK 0x00200000
1134 /* The mask used to clear the ALT_USB_GLOB_GOTGCTL_CURMOD register field value. */
1135 #define ALT_USB_GLOB_GOTGCTL_CURMOD_CLR_MSK 0xffdfffff
1136 /* The reset value of the ALT_USB_GLOB_GOTGCTL_CURMOD register field. */
1137 #define ALT_USB_GLOB_GOTGCTL_CURMOD_RESET 0x0
1138 /* Extracts the ALT_USB_GLOB_GOTGCTL_CURMOD field value from a register. */
1139 #define ALT_USB_GLOB_GOTGCTL_CURMOD_GET(value) (((value) & 0x00200000) >> 21)
1140 /* Produces a ALT_USB_GLOB_GOTGCTL_CURMOD register field value suitable for setting the register. */
1141 #define ALT_USB_GLOB_GOTGCTL_CURMOD_SET(value) (((value) << 21) & 0x00200000)
1142 
1143 #ifndef __ASSEMBLY__
1144 /*
1145  * WARNING: The C register and register group struct declarations are provided for
1146  * convenience and illustrative purposes. They should, however, be used with
1147  * caution as the C language standard provides no guarantees about the alignment or
1148  * atomicity of device memory accesses. The recommended practice for writing
1149  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1150  * alt_write_word() functions.
1151  *
1152  * The struct declaration for register ALT_USB_GLOB_GOTGCTL.
1153  */
1154 struct ALT_USB_GLOB_GOTGCTL_s
1155 {
1156  const uint32_t sesreqscs : 1; /* ALT_USB_GLOB_GOTGCTL_SESREQSCS */
1157  uint32_t sesreq : 1; /* ALT_USB_GLOB_GOTGCTL_SESREQ */
1158  uint32_t vbvalidoven : 1; /* ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN */
1159  uint32_t vbvalidovval : 1; /* ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL */
1160  uint32_t avalidoven : 1; /* ALT_USB_GLOB_GOTGCTL_AVALIDOVEN */
1161  uint32_t avalidovval : 1; /* ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL */
1162  uint32_t bvalidoven : 1; /* ALT_USB_GLOB_GOTGCTL_BVALIDOVEN */
1163  uint32_t bvalidovval : 1; /* ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL */
1164  const uint32_t hstnegscs : 1; /* ALT_USB_GLOB_GOTGCTL_HSTNEGSCS */
1165  uint32_t hnpreq : 1; /* ALT_USB_GLOB_GOTGCTL_HNPREQ */
1166  uint32_t hstsethnpen : 1; /* ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN */
1167  uint32_t devhnpen : 1; /* ALT_USB_GLOB_GOTGCTL_DEVHNPEN */
1168  uint32_t : 2; /* *UNDEFINED* */
1169  uint32_t ehen : 1; /* ALT_USB_GLOB_GOTGCTL_EHEN */
1170  uint32_t : 1; /* *UNDEFINED* */
1171  const uint32_t conidsts : 1; /* ALT_USB_GLOB_GOTGCTL_CONIDSTS */
1172  const uint32_t dbnctime : 1; /* ALT_USB_GLOB_GOTGCTL_DBNCTIME */
1173  const uint32_t asesvld : 1; /* ALT_USB_GLOB_GOTGCTL_ASESVLD */
1174  const uint32_t bsesvld : 1; /* ALT_USB_GLOB_GOTGCTL_BSESVLD */
1175  uint32_t otgver : 1; /* ALT_USB_GLOB_GOTGCTL_OTGVER */
1176  const uint32_t curmod : 1; /* ALT_USB_GLOB_GOTGCTL_CURMOD */
1177  uint32_t : 10; /* *UNDEFINED* */
1178 };
1179 
1180 /* The typedef declaration for register ALT_USB_GLOB_GOTGCTL. */
1181 typedef volatile struct ALT_USB_GLOB_GOTGCTL_s ALT_USB_GLOB_GOTGCTL_t;
1182 #endif /* __ASSEMBLY__ */
1183 
1184 /* The reset value of the ALT_USB_GLOB_GOTGCTL register. */
1185 #define ALT_USB_GLOB_GOTGCTL_RESET 0x00010000
1186 /* The byte offset of the ALT_USB_GLOB_GOTGCTL register from the beginning of the component. */
1187 #define ALT_USB_GLOB_GOTGCTL_OFST 0x0
1188 /* The address of the ALT_USB_GLOB_GOTGCTL register. */
1189 #define ALT_USB_GLOB_GOTGCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GOTGCTL_OFST))
1190 
1191 /*
1192  * Register : gotgint
1193  *
1194  * OTG Interrupt Register
1195  *
1196  * Register Layout
1197  *
1198  * Bits | Access | Reset | Description
1199  * :--------|:-------|:------|:--------------------------------------
1200  * [1:0] | ??? | 0x0 | *UNDEFINED*
1201  * [2] | RW | 0x0 | ALT_USB_GLOB_GOTGINT_SESENDDET
1202  * [7:3] | ??? | 0x0 | *UNDEFINED*
1203  * [8] | RW | 0x0 | ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG
1204  * [9] | RW | 0x0 | ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG
1205  * [16:10] | ??? | 0x0 | *UNDEFINED*
1206  * [17] | RW | 0x0 | ALT_USB_GLOB_GOTGINT_HSTNEGDET
1207  * [18] | RW | 0x0 | ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG
1208  * [19] | RW | 0x0 | ALT_USB_GLOB_GOTGINT_DBNCEDONE
1209  * [31:20] | ??? | 0x0 | *UNDEFINED*
1210  *
1211  */
1212 /*
1213  * Field : sesenddet
1214  *
1215  * Mode:Host and Device
1216  *
1217  * Session End Detected (SesEndDet)
1218  *
1219  * The core sets this bit when the utmiotg_bvalid signal is
1220  *
1221  * deasserted.This bit can be set only by the core and the application should write
1222  * 1 to clear it.
1223  *
1224  * Field Enumeration Values:
1225  *
1226  * Enum | Value | Description
1227  * :---------------------------------------|:------|:---------------------------------------------
1228  * ALT_USB_GLOB_GOTGINT_SESENDDET_E_INACT | 0x0 | Non Active State
1229  * ALT_USB_GLOB_GOTGINT_SESENDDET_E_ACT | 0x1 | Set when utmisrp_bvalid signal is deasserted
1230  *
1231  * Field Access Macros:
1232  *
1233  */
1234 /*
1235  * Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESENDDET
1236  *
1237  * Non Active State
1238  */
1239 #define ALT_USB_GLOB_GOTGINT_SESENDDET_E_INACT 0x0
1240 /*
1241  * Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESENDDET
1242  *
1243  * Set when utmisrp_bvalid signal is deasserted
1244  */
1245 #define ALT_USB_GLOB_GOTGINT_SESENDDET_E_ACT 0x1
1246 
1247 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */
1248 #define ALT_USB_GLOB_GOTGINT_SESENDDET_LSB 2
1249 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */
1250 #define ALT_USB_GLOB_GOTGINT_SESENDDET_MSB 2
1251 /* The width in bits of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */
1252 #define ALT_USB_GLOB_GOTGINT_SESENDDET_WIDTH 1
1253 /* The mask used to set the ALT_USB_GLOB_GOTGINT_SESENDDET register field value. */
1254 #define ALT_USB_GLOB_GOTGINT_SESENDDET_SET_MSK 0x00000004
1255 /* The mask used to clear the ALT_USB_GLOB_GOTGINT_SESENDDET register field value. */
1256 #define ALT_USB_GLOB_GOTGINT_SESENDDET_CLR_MSK 0xfffffffb
1257 /* The reset value of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */
1258 #define ALT_USB_GLOB_GOTGINT_SESENDDET_RESET 0x0
1259 /* Extracts the ALT_USB_GLOB_GOTGINT_SESENDDET field value from a register. */
1260 #define ALT_USB_GLOB_GOTGINT_SESENDDET_GET(value) (((value) & 0x00000004) >> 2)
1261 /* Produces a ALT_USB_GLOB_GOTGINT_SESENDDET register field value suitable for setting the register. */
1262 #define ALT_USB_GLOB_GOTGINT_SESENDDET_SET(value) (((value) << 2) & 0x00000004)
1263 
1264 /*
1265  * Field : sesreqsucstschng
1266  *
1267  * Mode:Host and Device
1268  *
1269  * Session Request Success Status Change
1270  *
1271  * (SesReqSucStsChng)
1272  *
1273  * The core sets this bit on the success or failure of a session
1274  *
1275  * request. The application must read the Session Request
1276  *
1277  * Success bit in the OTG Control and Status register
1278  *
1279  * (GOTGCTL.SesReqScs) to check For success or failure.This bit can be set only by
1280  * the core and the application should write 1 to clear it.
1281  *
1282  * Field Enumeration Values:
1283  *
1284  * Enum | Value | Description
1285  * :----------------------------------------------|:------|:-----------------------
1286  * ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_INACT | 0x0 | No change
1287  * ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_ACT | 0x1 | Session Request Status
1288  *
1289  * Field Access Macros:
1290  *
1291  */
1292 /*
1293  * Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG
1294  *
1295  * No change
1296  */
1297 #define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_INACT 0x0
1298 /*
1299  * Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG
1300  *
1301  * Session Request Status
1302  */
1303 #define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_ACT 0x1
1304 
1305 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */
1306 #define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_LSB 8
1307 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */
1308 #define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_MSB 8
1309 /* The width in bits of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */
1310 #define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_WIDTH 1
1311 /* The mask used to set the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field value. */
1312 #define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_SET_MSK 0x00000100
1313 /* The mask used to clear the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field value. */
1314 #define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_CLR_MSK 0xfffffeff
1315 /* The reset value of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */
1316 #define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_RESET 0x0
1317 /* Extracts the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG field value from a register. */
1318 #define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_GET(value) (((value) & 0x00000100) >> 8)
1319 /* Produces a ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field value suitable for setting the register. */
1320 #define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_SET(value) (((value) << 8) & 0x00000100)
1321 
1322 /*
1323  * Field : hstnegsucstschng
1324  *
1325  * Mode:Host and Device
1326  *
1327  * Host Negotiation Success Status Change (HstNegSucStsChng)
1328  *
1329  * The core sets this bit on the success or failure of a USB host
1330  *
1331  * negotiation request. The application must read the Host
1332  *
1333  * Negotiation Success bit of the OTG Control and Status register
1334  *
1335  * (GOTGCTL.HstNegScs) to check For success or failure.This bit can be set only by
1336  * the core and the application should write 1 to clear it.
1337  *
1338  * Field Enumeration Values:
1339  *
1340  * Enum | Value | Description
1341  * :----------------------------------------------|:------|:-------------------------------
1342  * ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_INACT | 0x0 | No Change
1343  * ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_ACT | 0x1 | Host Negotiation Status Change
1344  *
1345  * Field Access Macros:
1346  *
1347  */
1348 /*
1349  * Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG
1350  *
1351  * No Change
1352  */
1353 #define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_INACT 0x0
1354 /*
1355  * Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG
1356  *
1357  * Host Negotiation Status Change
1358  */
1359 #define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_ACT 0x1
1360 
1361 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */
1362 #define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_LSB 9
1363 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */
1364 #define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_MSB 9
1365 /* The width in bits of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */
1366 #define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_WIDTH 1
1367 /* The mask used to set the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field value. */
1368 #define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_SET_MSK 0x00000200
1369 /* The mask used to clear the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field value. */
1370 #define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_CLR_MSK 0xfffffdff
1371 /* The reset value of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */
1372 #define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_RESET 0x0
1373 /* Extracts the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG field value from a register. */
1374 #define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_GET(value) (((value) & 0x00000200) >> 9)
1375 /* Produces a ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field value suitable for setting the register. */
1376 #define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_SET(value) (((value) << 9) & 0x00000200)
1377 
1378 /*
1379  * Field : hstnegdet
1380  *
1381  * Mode:Host and Device
1382  *
1383  * Host Negotiation Detected (HstNegDet)
1384  *
1385  * The core sets this bit when it detects a host negotiation request
1386  *
1387  * on the USB.This bit can be set only by the core and the application should write
1388  * 1 to clear it.
1389  *
1390  * Field Enumeration Values:
1391  *
1392  * Enum | Value | Description
1393  * :---------------------------------------|:------|:--------------------------
1394  * ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_INACT | 0x0 | No Change
1395  * ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_ACT | 0x1 | Host Negotiation Detected
1396  *
1397  * Field Access Macros:
1398  *
1399  */
1400 /*
1401  * Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGDET
1402  *
1403  * No Change
1404  */
1405 #define ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_INACT 0x0
1406 /*
1407  * Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGDET
1408  *
1409  * Host Negotiation Detected
1410  */
1411 #define ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_ACT 0x1
1412 
1413 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */
1414 #define ALT_USB_GLOB_GOTGINT_HSTNEGDET_LSB 17
1415 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */
1416 #define ALT_USB_GLOB_GOTGINT_HSTNEGDET_MSB 17
1417 /* The width in bits of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */
1418 #define ALT_USB_GLOB_GOTGINT_HSTNEGDET_WIDTH 1
1419 /* The mask used to set the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field value. */
1420 #define ALT_USB_GLOB_GOTGINT_HSTNEGDET_SET_MSK 0x00020000
1421 /* The mask used to clear the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field value. */
1422 #define ALT_USB_GLOB_GOTGINT_HSTNEGDET_CLR_MSK 0xfffdffff
1423 /* The reset value of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */
1424 #define ALT_USB_GLOB_GOTGINT_HSTNEGDET_RESET 0x0
1425 /* Extracts the ALT_USB_GLOB_GOTGINT_HSTNEGDET field value from a register. */
1426 #define ALT_USB_GLOB_GOTGINT_HSTNEGDET_GET(value) (((value) & 0x00020000) >> 17)
1427 /* Produces a ALT_USB_GLOB_GOTGINT_HSTNEGDET register field value suitable for setting the register. */
1428 #define ALT_USB_GLOB_GOTGINT_HSTNEGDET_SET(value) (((value) << 17) & 0x00020000)
1429 
1430 /*
1431  * Field : adevtoutchg
1432  *
1433  * Mode:Host and Device
1434  *
1435  * A-Device Timeout Change (ADevTOUTChg)
1436  *
1437  * The core sets this bit to indicate that the A-device has timed out
1438  *
1439  * WHILE waiting FOR the B-device to connect.This bit can be set only by the core
1440  * and the application should write 1 to clear it.
1441  *
1442  * Field Enumeration Values:
1443  *
1444  * Enum | Value | Description
1445  * :-----------------------------------------|:------|:-----------------
1446  * ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_INACT | 0x0 | No Change
1447  * ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_ACT | 0x1 | A-Device Timeout
1448  *
1449  * Field Access Macros:
1450  *
1451  */
1452 /*
1453  * Enumerated value for register field ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG
1454  *
1455  * No Change
1456  */
1457 #define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_INACT 0x0
1458 /*
1459  * Enumerated value for register field ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG
1460  *
1461  * A-Device Timeout
1462  */
1463 #define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_ACT 0x1
1464 
1465 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */
1466 #define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_LSB 18
1467 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */
1468 #define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_MSB 18
1469 /* The width in bits of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */
1470 #define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_WIDTH 1
1471 /* The mask used to set the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field value. */
1472 #define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_SET_MSK 0x00040000
1473 /* The mask used to clear the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field value. */
1474 #define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_CLR_MSK 0xfffbffff
1475 /* The reset value of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */
1476 #define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_RESET 0x0
1477 /* Extracts the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG field value from a register. */
1478 #define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_GET(value) (((value) & 0x00040000) >> 18)
1479 /* Produces a ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field value suitable for setting the register. */
1480 #define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_SET(value) (((value) << 18) & 0x00040000)
1481 
1482 /*
1483  * Field : dbncedone
1484  *
1485  * Mode: Host only
1486  *
1487  * Debounce Done (DbnceDone)
1488  *
1489  * The core sets this bit when the debounce is completed after the
1490  *
1491  * device connect. The application can start driving USB reset after
1492  *
1493  * seeing this interrupt. This bit is only valid when the HNP
1494  *
1495  * Capable or SRP Capable bit is SET in the Core USB
1496  *
1497  * Configuration register (GUSBCFG.HNPCap or
1498  *
1499  * GUSBCFG.SRPCap, respectively).This bit can be set only by the core and the
1500  * application should write 1 to clear it.
1501  *
1502  * Field Enumeration Values:
1503  *
1504  * Enum | Value | Description
1505  * :---------------------------------------|:------|:-------------------
1506  * ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_INACT | 0x0 | No Change
1507  * ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_ACT | 0x1 | Debounce completed
1508  *
1509  * Field Access Macros:
1510  *
1511  */
1512 /*
1513  * Enumerated value for register field ALT_USB_GLOB_GOTGINT_DBNCEDONE
1514  *
1515  * No Change
1516  */
1517 #define ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_INACT 0x0
1518 /*
1519  * Enumerated value for register field ALT_USB_GLOB_GOTGINT_DBNCEDONE
1520  *
1521  * Debounce completed
1522  */
1523 #define ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_ACT 0x1
1524 
1525 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */
1526 #define ALT_USB_GLOB_GOTGINT_DBNCEDONE_LSB 19
1527 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */
1528 #define ALT_USB_GLOB_GOTGINT_DBNCEDONE_MSB 19
1529 /* The width in bits of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */
1530 #define ALT_USB_GLOB_GOTGINT_DBNCEDONE_WIDTH 1
1531 /* The mask used to set the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field value. */
1532 #define ALT_USB_GLOB_GOTGINT_DBNCEDONE_SET_MSK 0x00080000
1533 /* The mask used to clear the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field value. */
1534 #define ALT_USB_GLOB_GOTGINT_DBNCEDONE_CLR_MSK 0xfff7ffff
1535 /* The reset value of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */
1536 #define ALT_USB_GLOB_GOTGINT_DBNCEDONE_RESET 0x0
1537 /* Extracts the ALT_USB_GLOB_GOTGINT_DBNCEDONE field value from a register. */
1538 #define ALT_USB_GLOB_GOTGINT_DBNCEDONE_GET(value) (((value) & 0x00080000) >> 19)
1539 /* Produces a ALT_USB_GLOB_GOTGINT_DBNCEDONE register field value suitable for setting the register. */
1540 #define ALT_USB_GLOB_GOTGINT_DBNCEDONE_SET(value) (((value) << 19) & 0x00080000)
1541 
1542 #ifndef __ASSEMBLY__
1543 /*
1544  * WARNING: The C register and register group struct declarations are provided for
1545  * convenience and illustrative purposes. They should, however, be used with
1546  * caution as the C language standard provides no guarantees about the alignment or
1547  * atomicity of device memory accesses. The recommended practice for writing
1548  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1549  * alt_write_word() functions.
1550  *
1551  * The struct declaration for register ALT_USB_GLOB_GOTGINT.
1552  */
1553 struct ALT_USB_GLOB_GOTGINT_s
1554 {
1555  uint32_t : 2; /* *UNDEFINED* */
1556  uint32_t sesenddet : 1; /* ALT_USB_GLOB_GOTGINT_SESENDDET */
1557  uint32_t : 5; /* *UNDEFINED* */
1558  uint32_t sesreqsucstschng : 1; /* ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG */
1559  uint32_t hstnegsucstschng : 1; /* ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG */
1560  uint32_t : 7; /* *UNDEFINED* */
1561  uint32_t hstnegdet : 1; /* ALT_USB_GLOB_GOTGINT_HSTNEGDET */
1562  uint32_t adevtoutchg : 1; /* ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG */
1563  uint32_t dbncedone : 1; /* ALT_USB_GLOB_GOTGINT_DBNCEDONE */
1564  uint32_t : 12; /* *UNDEFINED* */
1565 };
1566 
1567 /* The typedef declaration for register ALT_USB_GLOB_GOTGINT. */
1568 typedef volatile struct ALT_USB_GLOB_GOTGINT_s ALT_USB_GLOB_GOTGINT_t;
1569 #endif /* __ASSEMBLY__ */
1570 
1571 /* The reset value of the ALT_USB_GLOB_GOTGINT register. */
1572 #define ALT_USB_GLOB_GOTGINT_RESET 0x00000000
1573 /* The byte offset of the ALT_USB_GLOB_GOTGINT register from the beginning of the component. */
1574 #define ALT_USB_GLOB_GOTGINT_OFST 0x4
1575 /* The address of the ALT_USB_GLOB_GOTGINT register. */
1576 #define ALT_USB_GLOB_GOTGINT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GOTGINT_OFST))
1577 
1578 /*
1579  * Register : gahbcfg
1580  *
1581  * AHB Configuration Register
1582  *
1583  * Register Layout
1584  *
1585  * Bits | Access | Reset | Description
1586  * :--------|:-------|:------|:--------------------------------------
1587  * [0] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK
1588  * [4:1] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_HBSTLEN
1589  * [5] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_DMAEN
1590  * [6] | ??? | 0x0 | *UNDEFINED*
1591  * [7] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL
1592  * [8] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL
1593  * [20:9] | ??? | 0x0 | *UNDEFINED*
1594  * [21] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_REMMEMSUPP
1595  * [22] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT
1596  * [23] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_AHBSINGLE
1597  * [24] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS
1598  * [31:25] | ??? | 0x0 | *UNDEFINED*
1599  *
1600  */
1601 /*
1602  * Field : glblintrmsk
1603  *
1604  * Mode:Host and device
1605  *
1606  * Global Interrupt Mask (GlblIntrMsk)
1607  *
1608  * The application uses this bit to mask or unmask the interrupt line
1609  *
1610  * assertion to itself. Irrespective of this bit's setting, the interrupt
1611  *
1612  * status registers are updated by the core.
1613  *
1614  * 1'b0: Mask the interrupt assertion to the application.
1615  *
1616  * 1'b1: Unmask the interrupt assertion to the application.
1617  *
1618  * Field Enumeration Values:
1619  *
1620  * Enum | Value | Description
1621  * :-----------------------------------------|:------|:------------------------------------------------
1622  * ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_MSK | 0x0 | Mask the interrupt assertion to the application
1623  * ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_NOMSK | 0x1 | Unmask the interrupt assertion to the
1624  * : | | application.
1625  *
1626  * Field Access Macros:
1627  *
1628  */
1629 /*
1630  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK
1631  *
1632  * Mask the interrupt assertion to the application
1633  */
1634 #define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_MSK 0x0
1635 /*
1636  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK
1637  *
1638  * Unmask the interrupt assertion to the application.
1639  */
1640 #define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_NOMSK 0x1
1641 
1642 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */
1643 #define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_LSB 0
1644 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */
1645 #define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_MSB 0
1646 /* The width in bits of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */
1647 #define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_WIDTH 1
1648 /* The mask used to set the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field value. */
1649 #define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_SET_MSK 0x00000001
1650 /* The mask used to clear the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field value. */
1651 #define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_CLR_MSK 0xfffffffe
1652 /* The reset value of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */
1653 #define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_RESET 0x0
1654 /* Extracts the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK field value from a register. */
1655 #define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_GET(value) (((value) & 0x00000001) >> 0)
1656 /* Produces a ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field value suitable for setting the register. */
1657 #define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_SET(value) (((value) << 0) & 0x00000001)
1658 
1659 /*
1660  * Field : hbstlen
1661  *
1662  * Mode:Host and device
1663  *
1664  * Burst Length/Type (HBstLen)
1665  *
1666  * This field is used in both External and Internal DMA modes. In
1667  *
1668  * External DMA mode, these bits appear on dma_burst[3:0] ports,
1669  *
1670  * which can be used by an external wrapper to interface the
1671  *
1672  * External DMA Controller interface to Synopsys DW_ahb_dmac
1673  *
1674  * or ARM PrimeCell.
1675  *
1676  * External DMA Modedefines the DMA burst length in terms of
1677  *
1678  * 32-bit words:
1679  *
1680  * 4'b0000: 1 word
1681  *
1682  * 4'b0001: 4 words
1683  *
1684  * 4'b0010: 8 words
1685  *
1686  * 4'b0011: 16 words
1687  *
1688  * 4'b0100: 32 words
1689  *
1690  * 4'b0101: 64 word
1691  *
1692  * s
1693  *
1694  * 4'b0110: 128 words
1695  *
1696  * 4'b0111: 256 words
1697  *
1698  * Others: Reserved
1699  *
1700  * Internal DMA ModeAHB Master burst type:
1701  *
1702  * 4'b0000 Single
1703  *
1704  * 4'b0001 INCR
1705  *
1706  * 4'b0011 INCR4
1707  *
1708  * 4'b0101 INCR8
1709  *
1710  * 4'b0111 INCR16
1711  *
1712  * Others: Reserved
1713  *
1714  * Field Enumeration Values:
1715  *
1716  * Enum | Value | Description
1717  * :-----------------------------------------------|:------|:-------------------
1718  * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD1ORSINGLE | 0x0 | 1 word or single
1719  * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD4ORINCR | 0x1 | 4 word or incr
1720  * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD8 | 0x2 | 8 word
1721  * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD16ORINCR4 | 0x3 | 16 word or incr4
1722  * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD32 | 0x4 | 32 word
1723  * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD64ORINCR8 | 0x5 | 64 word or incr8
1724  * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD128 | 0x6 | 128 word
1725  * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD256ORINCR16 | 0x7 | 256 word or incr16
1726  * ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORDX | 0x8 | Others reserved
1727  *
1728  * Field Access Macros:
1729  *
1730  */
1731 /*
1732  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
1733  *
1734  * 1 word or single
1735  */
1736 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD1ORSINGLE 0x0
1737 /*
1738  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
1739  *
1740  * 4 word or incr
1741  */
1742 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD4ORINCR 0x1
1743 /*
1744  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
1745  *
1746  * 8 word
1747  */
1748 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD8 0x2
1749 /*
1750  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
1751  *
1752  * 16 word or incr4
1753  */
1754 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD16ORINCR4 0x3
1755 /*
1756  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
1757  *
1758  * 32 word
1759  */
1760 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD32 0x4
1761 /*
1762  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
1763  *
1764  * 64 word or incr8
1765  */
1766 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD64ORINCR8 0x5
1767 /*
1768  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
1769  *
1770  * 128 word
1771  */
1772 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD128 0x6
1773 /*
1774  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
1775  *
1776  * 256 word or incr16
1777  */
1778 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD256ORINCR16 0x7
1779 /*
1780  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
1781  *
1782  * Others reserved
1783  */
1784 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORDX 0x8
1785 
1786 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */
1787 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_LSB 1
1788 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */
1789 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_MSB 4
1790 /* The width in bits of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */
1791 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_WIDTH 4
1792 /* The mask used to set the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field value. */
1793 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_SET_MSK 0x0000001e
1794 /* The mask used to clear the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field value. */
1795 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_CLR_MSK 0xffffffe1
1796 /* The reset value of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */
1797 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_RESET 0x0
1798 /* Extracts the ALT_USB_GLOB_GAHBCFG_HBSTLEN field value from a register. */
1799 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_GET(value) (((value) & 0x0000001e) >> 1)
1800 /* Produces a ALT_USB_GLOB_GAHBCFG_HBSTLEN register field value suitable for setting the register. */
1801 #define ALT_USB_GLOB_GAHBCFG_HBSTLEN_SET(value) (((value) << 1) & 0x0000001e)
1802 
1803 /*
1804  * Field : dmaen
1805  *
1806  * Mode:Host and device
1807  *
1808  * DMA Enable (DMAEn)
1809  *
1810  * 1'b0: Core operates in Slave mode
1811  *
1812  * 1'b1: Core operates in a DMA mode
1813  *
1814  * This bit is always 0 when Slave-Only mode has been selected
1815  *
1816  * Field Enumeration Values:
1817  *
1818  * Enum | Value | Description
1819  * :------------------------------------|:------|:----------------------------
1820  * ALT_USB_GLOB_GAHBCFG_DMAEN_E_SLVMOD | 0x0 | Core operates in Slave mode
1821  * ALT_USB_GLOB_GAHBCFG_DMAEN_E_DMAMOD | 0x1 | Core operates in a DMA mode
1822  *
1823  * Field Access Macros:
1824  *
1825  */
1826 /*
1827  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_DMAEN
1828  *
1829  * Core operates in Slave mode
1830  */
1831 #define ALT_USB_GLOB_GAHBCFG_DMAEN_E_SLVMOD 0x0
1832 /*
1833  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_DMAEN
1834  *
1835  * Core operates in a DMA mode
1836  */
1837 #define ALT_USB_GLOB_GAHBCFG_DMAEN_E_DMAMOD 0x1
1838 
1839 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */
1840 #define ALT_USB_GLOB_GAHBCFG_DMAEN_LSB 5
1841 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */
1842 #define ALT_USB_GLOB_GAHBCFG_DMAEN_MSB 5
1843 /* The width in bits of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */
1844 #define ALT_USB_GLOB_GAHBCFG_DMAEN_WIDTH 1
1845 /* The mask used to set the ALT_USB_GLOB_GAHBCFG_DMAEN register field value. */
1846 #define ALT_USB_GLOB_GAHBCFG_DMAEN_SET_MSK 0x00000020
1847 /* The mask used to clear the ALT_USB_GLOB_GAHBCFG_DMAEN register field value. */
1848 #define ALT_USB_GLOB_GAHBCFG_DMAEN_CLR_MSK 0xffffffdf
1849 /* The reset value of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */
1850 #define ALT_USB_GLOB_GAHBCFG_DMAEN_RESET 0x0
1851 /* Extracts the ALT_USB_GLOB_GAHBCFG_DMAEN field value from a register. */
1852 #define ALT_USB_GLOB_GAHBCFG_DMAEN_GET(value) (((value) & 0x00000020) >> 5)
1853 /* Produces a ALT_USB_GLOB_GAHBCFG_DMAEN register field value suitable for setting the register. */
1854 #define ALT_USB_GLOB_GAHBCFG_DMAEN_SET(value) (((value) << 5) & 0x00000020)
1855 
1856 /*
1857  * Field : nptxfemplvl
1858  *
1859  * Mode:Host and device
1860  *
1861  * Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
1862  *
1863  * This bit is used only in Slave mode.
1864  *
1865  * In host mode and with Shared FIFO with device mode, this bit
1866  *
1867  * indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
1868  *
1869  * the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.
1870  *
1871  * With dedicated FIFO in device mode, this bit indicates when IN
1872  *
1873  * endpoint Transmit FIFO empty interrupt (DIEPINTn.TxFEmp) is
1874  *
1875  * triggered.
1876  *
1877  * Host mode and with Shared FIFO with device mode:-
1878  *
1879  * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
1880  *
1881  * Periodic TxFIFO is half empty
1882  *
1883  * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
1884  *
1885  * Periodic TxFIFO is completely empty
1886  *
1887  * Dedicated FIFO in device mode :-
1888  *
1889  * 1'b0: DIEPINTn.TxFEmp interrupt indicates that the IN
1890  *
1891  * Endpoint TxFIFO is half empty
1892  *
1893  * 1'b1: DIEPINTn.TxFEmp interrupt indicates that the IN
1894  *
1895  * Endpoint TxFIFO is completely empty
1896  *
1897  * Field Enumeration Values:
1898  *
1899  * Enum | Value | Description
1900  * :---------------------------------------------|:------|:-------------------------------------------------
1901  * ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_HALFEMPTY | 0x0 | DIEPINTn.TxFEmp interrupt indicates that the IN
1902  * : | | Endpoint TxFIFO is half empty or DIEPINTn.TxFEmp
1903  * : | | interrupt indicates that the IN Endpoint TxFIFO
1904  * : | | is half empty
1905  * ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_EMPTY | 0x1 | GINTSTS.NPTxFEmp interrupt indicates that the
1906  * : | | Non-Periodic TxFIFO is completely empty or
1907  * : | | DIEPINTn.TxFEmp interrupt indicates that the IN
1908  * : | | Endpoint TxFIFO is completely empty
1909  *
1910  * Field Access Macros:
1911  *
1912  */
1913 /*
1914  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL
1915  *
1916  * DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty or
1917  * DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty
1918  */
1919 #define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_HALFEMPTY 0x0
1920 /*
1921  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL
1922  *
1923  * GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely
1924  * empty or DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is
1925  * completely empty
1926  */
1927 #define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_EMPTY 0x1
1928 
1929 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */
1930 #define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_LSB 7
1931 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */
1932 #define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_MSB 7
1933 /* The width in bits of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */
1934 #define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_WIDTH 1
1935 /* The mask used to set the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field value. */
1936 #define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_SET_MSK 0x00000080
1937 /* The mask used to clear the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field value. */
1938 #define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_CLR_MSK 0xffffff7f
1939 /* The reset value of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */
1940 #define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_RESET 0x0
1941 /* Extracts the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL field value from a register. */
1942 #define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_GET(value) (((value) & 0x00000080) >> 7)
1943 /* Produces a ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field value suitable for setting the register. */
1944 #define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_SET(value) (((value) << 7) & 0x00000080)
1945 
1946 /*
1947  * Field : ptxfemplvl
1948  *
1949  * Mode:Host only
1950  *
1951  * Periodic TxFIFO Empty Level (PTxFEmpLvl)
1952  *
1953  * Indicates when the Periodic TxFIFO Empty Interrupt bit in the
1954  *
1955  * Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
1956  *
1957  * bit is used only in Slave mode.
1958  *
1959  * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the
1960  *
1961  * Periodic TxFIFO is half empty
1962  *
1963  * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the
1964  *
1965  * Periodic TxFIFO is completely empty
1966  *
1967  * Field Enumeration Values:
1968  *
1969  * Enum | Value | Description
1970  * :--------------------------------------------|:------|:---------------------------------------------
1971  * ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_HALFEMPTY | 0x0 | GINTSTS.PTxFEmp interrupt indicates that the
1972  * : | | Periodic TxFIFO is half empty
1973  * ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_EMPTY | 0x1 | GINTSTS.PTxFEmp interrupt indicates that the
1974  * : | | Periodic TxFIFO is completely empty
1975  *
1976  * Field Access Macros:
1977  *
1978  */
1979 /*
1980  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL
1981  *
1982  * GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty
1983  */
1984 #define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_HALFEMPTY 0x0
1985 /*
1986  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL
1987  *
1988  * GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty
1989  */
1990 #define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_EMPTY 0x1
1991 
1992 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */
1993 #define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_LSB 8
1994 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */
1995 #define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_MSB 8
1996 /* The width in bits of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */
1997 #define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_WIDTH 1
1998 /* The mask used to set the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field value. */
1999 #define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_SET_MSK 0x00000100
2000 /* The mask used to clear the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field value. */
2001 #define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_CLR_MSK 0xfffffeff
2002 /* The reset value of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */
2003 #define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_RESET 0x0
2004 /* Extracts the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL field value from a register. */
2005 #define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_GET(value) (((value) & 0x00000100) >> 8)
2006 /* Produces a ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field value suitable for setting the register. */
2007 #define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_SET(value) (((value) << 8) & 0x00000100)
2008 
2009 /*
2010  * Field : remmemsupp
2011  *
2012  * Remote Memory Support (RemMemSupp)
2013  *
2014  * This bit is programmed to enable the functionality to wait for the system DMA
2015  *
2016  * Done Signal for the DMA Write Transfers.
2017  *
2018  * GAHBCFG.RemMemSupp=1
2019  *
2020  * * The int_dma_req output signal is asserted when HSOTG DMA starts
2021  *
2022  * write transfer to the external memory. When the core is done with the
2023  *
2024  * Transfers it asserts int_dma_done signal to flag the completion of DMA
2025  *
2026  * writes from HSOTG. The core then waits for sys_dma_done signal from
2027  *
2028  * the system to proceed further and complete the Data Transfer
2029  *
2030  * corresponding to a particular Channel/Endpoint.
2031  *
2032  * GAHBCFG.RemMemSupp=0
2033  *
2034  * * The int_dma_req and int_dma_done signals are not asserted and the
2035  *
2036  * core proceeds with the assertion of the XferComp interrupt as soon as
2037  *
2038  * the DMA write transfer is done at the HSOTG Core Boundary and it
2039  *
2040  * doesn't wait for the sys_dma_done signal to complete the DATA transfers
2041  *
2042  * Field Enumeration Values:
2043  *
2044  * Enum | Value | Description
2045  * :---------------------------------------|:------|:-----------------------------------------------
2046  * ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_DISD | 0x0 | Disable wait for system DMA Done Signal
2047  * ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_END | 0x1 | Enable wait for the system DMA Done Signal for
2048  * : | | the DMA Write Transfers
2049  *
2050  * Field Access Macros:
2051  *
2052  */
2053 /*
2054  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_REMMEMSUPP
2055  *
2056  * Disable wait for system DMA Done Signal
2057  */
2058 #define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_DISD 0x0
2059 /*
2060  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_REMMEMSUPP
2061  *
2062  * Enable wait for the system DMA Done Signal for the DMA Write Transfers
2063  */
2064 #define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_END 0x1
2065 
2066 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */
2067 #define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_LSB 21
2068 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */
2069 #define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_MSB 21
2070 /* The width in bits of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */
2071 #define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_WIDTH 1
2072 /* The mask used to set the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field value. */
2073 #define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_SET_MSK 0x00200000
2074 /* The mask used to clear the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field value. */
2075 #define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_CLR_MSK 0xffdfffff
2076 /* The reset value of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */
2077 #define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_RESET 0x0
2078 /* Extracts the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP field value from a register. */
2079 #define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_GET(value) (((value) & 0x00200000) >> 21)
2080 /* Produces a ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field value suitable for setting the register. */
2081 #define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_SET(value) (((value) << 21) & 0x00200000)
2082 
2083 /*
2084  * Field : notialldmawrit
2085  *
2086  * Notify All Dma Write Transactions (NotiAllDmaWrit)
2087  *
2088  * This bit is programmed to enable the System DMA Done functionality for all
2089  *
2090  * the DMA write Transactions corresponding to the Channel/Endpoint. This bit
2091  *
2092  * is valid only when GAHBCFG.RemMemSupp is set to 1.
2093  *
2094  * GAHBCFG.NotiAllDmaWrit = 1
2095  *
2096  * * HSOTG core asserts int_dma_req for all the DMA write transactions on
2097  *
2098  * the AHB interface along with int_dma_done, chep_last_transact and
2099  *
2100  * chep_number signal informations. The core waits for sys_dma_done
2101  *
2102  * signal for all the DMA write transactions in order to complete the transfer
2103  *
2104  * of a particular Channel/Endpoint.
2105  *
2106  * GAHBCFG.NotiAllDmaWrit = 0
2107  *
2108  * * HSOTG core asserts int_dma_req signal only for the last transaction of
2109  *
2110  * DMA write transfer corresponding to a particular Channel/Endpoint.
2111  *
2112  * Similarly, the core waits for sys_dma_done signal only for that
2113  *
2114  * transaction of DMA write to complete the transfer of a particular
2115  *
2116  * Channel/Endpoint.
2117  *
2118  * Field Enumeration Values:
2119  *
2120  * Enum | Value | Description
2121  * :------------------------------------------------|:------|:-------------------------------------------------
2122  * ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_LASTTRANS | 0x0 | HSOTG core asserts int_dma_req signal only for
2123  * : | | the last transaction of DMA write transfer
2124  * : | | corresponding to a particular Channel/Endpoint.
2125  * : | | Similarly, the core waits for sys_dma_done
2126  * : | | signal only for that transaction of DMA write to
2127  * : | | complete the transfer of a particular
2128  * : | | Channel/Endpoint
2129  * ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_ALLTRANS | 0x1 | HSOTG core asserts int_dma_req for all the DMA
2130  * : | | write transactions on the AHB interface along
2131  * : | | with int_dma_done, chep_last_transact and
2132  * : | | chep_number signal informations. The core waits
2133  * : | | for sys_dma_done signal for all the DMA write
2134  * : | | transactions in order to complete the transfer
2135  * : | | of a particular Channel/Endpoint
2136  *
2137  * Field Access Macros:
2138  *
2139  */
2140 /*
2141  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT
2142  *
2143  * HSOTG core asserts int_dma_req signal only for the last transaction of DMA write
2144  * transfer corresponding to a particular Channel/Endpoint. Similarly, the core
2145  * waits for sys_dma_done signal only for that transaction of DMA write to complete
2146  * the transfer of a particular Channel/Endpoint
2147  */
2148 #define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_LASTTRANS 0x0
2149 /*
2150  * Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT
2151  *
2152  * HSOTG core asserts int_dma_req for all the DMA write transactions on the AHB
2153  * interface along with int_dma_done, chep_last_transact and chep_number signal
2154  * informations. The core waits for sys_dma_done signal for all the DMA write
2155  * transactions in order to complete the transfer of a particular Channel/Endpoint
2156  */
2157 #define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_ALLTRANS 0x1
2158 
2159 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */
2160 #define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_LSB 22
2161 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */
2162 #define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_MSB 22
2163 /* The width in bits of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */
2164 #define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_WIDTH 1
2165 /* The mask used to set the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field value. */
2166 #define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_SET_MSK 0x00400000
2167 /* The mask used to clear the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field value. */
2168 #define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_CLR_MSK 0xffbfffff
2169 /* The reset value of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */
2170 #define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_RESET 0x0
2171 /* Extracts the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT field value from a register. */
2172 #define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_GET(value) (((value) & 0x00400000) >> 22)
2173 /* Produces a ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field value suitable for setting the register. */
2174 #define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_SET(value) (((value) << 22) & 0x00400000)
2175 
2176 /*
2177  * Field : ahbsingle
2178  *
2179  * AHB Single Support (AHBSingle)
2180  *
2181  * This bit when programmed supports Single transfers for the remaining data in a
2182  *
2183  * transfer when the DWC_otg core is operating in DMA mode.
2184  *
2185  * 1'b0: This is the default mode. When this bit is set to 1'b0,
2186  *
2187  * the remaining data in the transfer is sent using INCR burst size.
2188  *
2189  * 1'b1: When set to 1'b1, the remaining data in a transfer is sent using Single
2190  *
2191  * burst size.
2192  *
2193  * Note: if this feature is enabled, the AHB RETRY and SPLIT transfers still have
2194  * INCR
2195  *
2196  * burst type. Enable this feature when the AHB Slave connected to the DWC_otg core
2197  * does
2198  *
2199  * not support INCR burst (and when Split, and Retry transactions are not being
2200  * used
2201  *
2202  * in the bus).
2203  *
2204  * Field Access Macros:
2205  *
2206  */
2207 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field. */
2208 #define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_LSB 23
2209 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field. */
2210 #define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_MSB 23
2211 /* The width in bits of the ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field. */
2212 #define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_WIDTH 1
2213 /* The mask used to set the ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field value. */
2214 #define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_SET_MSK 0x00800000
2215 /* The mask used to clear the ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field value. */
2216 #define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_CLR_MSK 0xff7fffff
2217 /* The reset value of the ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field. */
2218 #define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_RESET 0x0
2219 /* Extracts the ALT_USB_GLOB_GAHBCFG_AHBSINGLE field value from a register. */
2220 #define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_GET(value) (((value) & 0x00800000) >> 23)
2221 /* Produces a ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field value suitable for setting the register. */
2222 #define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_SET(value) (((value) << 23) & 0x00800000)
2223 
2224 /*
2225  * Field : invdescendianess
2226  *
2227  * Invert Descriptor Endianess (InvDescEndianess)
2228  *
2229  * 1'b0: Descriptor Endianness is same as AHB Master Endianness
2230  *
2231  * 1'b1: Descriptor Endianness is Little Endian if AHB Master Endianness is Big
2232  * Endian.
2233  *
2234  * Descriptor Endianness is Big Endian if AHB Master Endianness is Little Endian.
2235  *
2236  * Field Access Macros:
2237  *
2238  */
2239 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field. */
2240 #define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_LSB 24
2241 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field. */
2242 #define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_MSB 24
2243 /* The width in bits of the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field. */
2244 #define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_WIDTH 1
2245 /* The mask used to set the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field value. */
2246 #define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_SET_MSK 0x01000000
2247 /* The mask used to clear the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field value. */
2248 #define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_CLR_MSK 0xfeffffff
2249 /* The reset value of the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field. */
2250 #define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_RESET 0x0
2251 /* Extracts the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS field value from a register. */
2252 #define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_GET(value) (((value) & 0x01000000) >> 24)
2253 /* Produces a ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field value suitable for setting the register. */
2254 #define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_SET(value) (((value) << 24) & 0x01000000)
2255 
2256 #ifndef __ASSEMBLY__
2257 /*
2258  * WARNING: The C register and register group struct declarations are provided for
2259  * convenience and illustrative purposes. They should, however, be used with
2260  * caution as the C language standard provides no guarantees about the alignment or
2261  * atomicity of device memory accesses. The recommended practice for writing
2262  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2263  * alt_write_word() functions.
2264  *
2265  * The struct declaration for register ALT_USB_GLOB_GAHBCFG.
2266  */
2267 struct ALT_USB_GLOB_GAHBCFG_s
2268 {
2269  uint32_t glblintrmsk : 1; /* ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK */
2270  uint32_t hbstlen : 4; /* ALT_USB_GLOB_GAHBCFG_HBSTLEN */
2271  uint32_t dmaen : 1; /* ALT_USB_GLOB_GAHBCFG_DMAEN */
2272  uint32_t : 1; /* *UNDEFINED* */
2273  uint32_t nptxfemplvl : 1; /* ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL */
2274  uint32_t ptxfemplvl : 1; /* ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL */
2275  uint32_t : 12; /* *UNDEFINED* */
2276  uint32_t remmemsupp : 1; /* ALT_USB_GLOB_GAHBCFG_REMMEMSUPP */
2277  uint32_t notialldmawrit : 1; /* ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT */
2278  uint32_t ahbsingle : 1; /* ALT_USB_GLOB_GAHBCFG_AHBSINGLE */
2279  uint32_t invdescendianess : 1; /* ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS */
2280  uint32_t : 7; /* *UNDEFINED* */
2281 };
2282 
2283 /* The typedef declaration for register ALT_USB_GLOB_GAHBCFG. */
2284 typedef volatile struct ALT_USB_GLOB_GAHBCFG_s ALT_USB_GLOB_GAHBCFG_t;
2285 #endif /* __ASSEMBLY__ */
2286 
2287 /* The reset value of the ALT_USB_GLOB_GAHBCFG register. */
2288 #define ALT_USB_GLOB_GAHBCFG_RESET 0x00000000
2289 /* The byte offset of the ALT_USB_GLOB_GAHBCFG register from the beginning of the component. */
2290 #define ALT_USB_GLOB_GAHBCFG_OFST 0x8
2291 /* The address of the ALT_USB_GLOB_GAHBCFG register. */
2292 #define ALT_USB_GLOB_GAHBCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GAHBCFG_OFST))
2293 
2294 /*
2295  * Register : gusbcfg
2296  *
2297  * USB Configuration Register
2298  *
2299  * Register Layout
2300  *
2301  * Bits | Access | Reset | Description
2302  * :--------|:-------|:------|:------------------------------------------
2303  * [2:0] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_TOUTCAL
2304  * [3] | R | 0x0 | ALT_USB_GLOB_GUSBCFG_PHYIF
2305  * [4] | R | 0x1 | ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL
2306  * [5] | R | 0x0 | ALT_USB_GLOB_GUSBCFG_FSINTF
2307  * [6] | R | 0x0 | ALT_USB_GLOB_GUSBCFG_PHYSEL
2308  * [7] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_DDRSEL
2309  * [8] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_SRPCAP
2310  * [9] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_HNPCAP
2311  * [13:10] | RW | 0x5 | ALT_USB_GLOB_GUSBCFG_USBTRDTIM
2312  * [17:14] | ??? | 0x0 | *UNDEFINED*
2313  * [18] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_ULPIAUTORES
2314  * [19] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM
2315  * [20] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV
2316  * [21] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR
2317  * [22] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE
2318  * [23] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_COMPLEMENT
2319  * [24] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_INDICATOR
2320  * [25] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_ULPI
2321  * [26] | R | 0x0 | ALT_USB_GLOB_GUSBCFG_IC_USBCAP
2322  * [27] | ??? | 0x0 | *UNDEFINED*
2323  * [28] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_TXENDDELAY
2324  * [29] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD
2325  * [30] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD
2326  * [31] | W | 0x0 | ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT
2327  *
2328  */
2329 /*
2330  * Field : toutcal
2331  *
2332  * Mode:Host and Device
2333  *
2334  * HS/FS Timeout Calibration (TOutCal)
2335  *
2336  * The number of PHY clocks that the application programs in this
2337  *
2338  * field is added to the high-speed/full-speed interpacket timeout
2339  *
2340  * duration in the core to account For any additional delays
2341  *
2342  * introduced by the PHY. This can be required, because the delay
2343  *
2344  * introduced by the PHY in generating the linestate condition can
2345  *
2346  * vary from one PHY to another.
2347  *
2348  * The USB standard timeout value For high-speed operation is 736
2349  *
2350  * to 816 (inclusive) bit times. The USB standard timeout value For
2351  *
2352  * full-speed operation is 16 to 18 (inclusive) bit times. The
2353  *
2354  * application must program this field based on the speed of
2355  *
2356  * enumeration. The number of bit times added per PHY clock are:
2357  *
2358  * High-speed operation:
2359  *
2360  * One 30-MHz PHY clock = 16 bit times
2361  *
2362  * One 60-MHz PHY clock = 8 bit times
2363  *
2364  * Full-speed operation:
2365  *
2366  * One 30-MHz PHY clock = 0.4 bit times
2367  *
2368  * One 60-MHz PHY clock = 0.2 bit times
2369  *
2370  * One 48-MHz PHY clock = 0.25 bit times
2371  *
2372  * Field Access Macros:
2373  *
2374  */
2375 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */
2376 #define ALT_USB_GLOB_GUSBCFG_TOUTCAL_LSB 0
2377 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */
2378 #define ALT_USB_GLOB_GUSBCFG_TOUTCAL_MSB 2
2379 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */
2380 #define ALT_USB_GLOB_GUSBCFG_TOUTCAL_WIDTH 3
2381 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field value. */
2382 #define ALT_USB_GLOB_GUSBCFG_TOUTCAL_SET_MSK 0x00000007
2383 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field value. */
2384 #define ALT_USB_GLOB_GUSBCFG_TOUTCAL_CLR_MSK 0xfffffff8
2385 /* The reset value of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */
2386 #define ALT_USB_GLOB_GUSBCFG_TOUTCAL_RESET 0x0
2387 /* Extracts the ALT_USB_GLOB_GUSBCFG_TOUTCAL field value from a register. */
2388 #define ALT_USB_GLOB_GUSBCFG_TOUTCAL_GET(value) (((value) & 0x00000007) >> 0)
2389 /* Produces a ALT_USB_GLOB_GUSBCFG_TOUTCAL register field value suitable for setting the register. */
2390 #define ALT_USB_GLOB_GUSBCFG_TOUTCAL_SET(value) (((value) << 0) & 0x00000007)
2391 
2392 /*
2393  * Field : phyif
2394  *
2395  * Mode:Host and Device
2396  *
2397  * PHY Interface (PHYIf)
2398  *
2399  * The application uses this bit to configure the core To support a
2400  *
2401  * UTMI+ PHY with an 8- or 16-bit interface. When a ULPI PHY is
2402  *
2403  * chosen, this must be Set to 8-bit mode.
2404  *
2405  * 1'b0: 8 bits
2406  *
2407  * 1'b1: 16 bits
2408  *
2409  * This bit is writable only If UTMI+ and ULPI were selected
2410  *
2411  * Field Enumeration Values:
2412  *
2413  * Enum | Value | Description
2414  * :-----------------------------------|:------|:--------------
2415  * ALT_USB_GLOB_GUSBCFG_PHYIF_E_BITS8 | 0x0 | PHY 8bit Mode
2416  *
2417  * Field Access Macros:
2418  *
2419  */
2420 /*
2421  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_PHYIF
2422  *
2423  * PHY 8bit Mode
2424  */
2425 #define ALT_USB_GLOB_GUSBCFG_PHYIF_E_BITS8 0x0
2426 
2427 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */
2428 #define ALT_USB_GLOB_GUSBCFG_PHYIF_LSB 3
2429 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */
2430 #define ALT_USB_GLOB_GUSBCFG_PHYIF_MSB 3
2431 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */
2432 #define ALT_USB_GLOB_GUSBCFG_PHYIF_WIDTH 1
2433 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_PHYIF register field value. */
2434 #define ALT_USB_GLOB_GUSBCFG_PHYIF_SET_MSK 0x00000008
2435 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_PHYIF register field value. */
2436 #define ALT_USB_GLOB_GUSBCFG_PHYIF_CLR_MSK 0xfffffff7
2437 /* The reset value of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */
2438 #define ALT_USB_GLOB_GUSBCFG_PHYIF_RESET 0x0
2439 /* Extracts the ALT_USB_GLOB_GUSBCFG_PHYIF field value from a register. */
2440 #define ALT_USB_GLOB_GUSBCFG_PHYIF_GET(value) (((value) & 0x00000008) >> 3)
2441 /* Produces a ALT_USB_GLOB_GUSBCFG_PHYIF register field value suitable for setting the register. */
2442 #define ALT_USB_GLOB_GUSBCFG_PHYIF_SET(value) (((value) << 3) & 0x00000008)
2443 
2444 /*
2445  * Field : ulpi_utmi_sel
2446  *
2447  * Mode:Host and Device
2448  *
2449  * ULPI or UTMI+ Select (ULPI_UTMI_Sel)
2450  *
2451  * The application uses this bit to select either a UTMI+ interface or
2452  *
2453  * ULPI Interface.
2454  *
2455  * 1'b0: UTMI+ Interface
2456  *
2457  * 1'b1: ULPI Interface
2458  *
2459  * This bit is writable only If UTMI+ and ULPI was specified For
2460  *
2461  * High-Speed PHY Interface(s).
2462  *
2463  * Field Enumeration Values:
2464  *
2465  * Enum | Value | Description
2466  * :------------------------------------------|:------|:------------
2467  * ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_E_ULPI | 0x0 | ULPI PHY
2468  *
2469  * Field Access Macros:
2470  *
2471  */
2472 /*
2473  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL
2474  *
2475  * ULPI PHY
2476  */
2477 #define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_E_ULPI 0x0
2478 
2479 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */
2480 #define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_LSB 4
2481 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */
2482 #define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_MSB 4
2483 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */
2484 #define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_WIDTH 1
2485 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field value. */
2486 #define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_SET_MSK 0x00000010
2487 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field value. */
2488 #define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_CLR_MSK 0xffffffef
2489 /* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */
2490 #define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_RESET 0x1
2491 /* Extracts the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL field value from a register. */
2492 #define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_GET(value) (((value) & 0x00000010) >> 4)
2493 /* Produces a ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field value suitable for setting the register. */
2494 #define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_SET(value) (((value) << 4) & 0x00000010)
2495 
2496 /*
2497  * Field : fsintf
2498  *
2499  * Mode:Host and Device
2500  *
2501  * Full-Speed Serial Interface Select (FSIntf)
2502  *
2503  * The application uses this bit to select either a unidirectional or
2504  *
2505  * bidirectional USB 1.1 full-speed serial transceiver interface.
2506  *
2507  * 1'b0: 6-pin unidirectional full-speed serial interface
2508  *
2509  * 1'b1: 3-pin bidirectional full-speed serial interface
2510  *
2511  * If a USB 1.1 Full-Speed Serial Transceiver interface was not
2512  *
2513  * selected, this bit is always 0, with Write
2514  *
2515  * Only access. If a USB 1.1 FS interface was selected, Then the
2516  *
2517  * application can Set this bit to select between the 3- and 6-pin
2518  *
2519  * interfaces, and access is Read and Write.
2520  *
2521  * Field Enumeration Values:
2522  *
2523  * Enum | Value | Description
2524  * :-------------------------------------|:------|:-------------------------------------------------
2525  * ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS6PIN | 0x0 | 6-pin unidirectional full-speed serial interface
2526  * ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS3PIN | 0x1 | 3-pin bidirectional full-speed serial interface
2527  *
2528  * Field Access Macros:
2529  *
2530  */
2531 /*
2532  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FSINTF
2533  *
2534  * 6-pin unidirectional full-speed serial interface
2535  */
2536 #define ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS6PIN 0x0
2537 /*
2538  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FSINTF
2539  *
2540  * 3-pin bidirectional full-speed serial interface
2541  */
2542 #define ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS3PIN 0x1
2543 
2544 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */
2545 #define ALT_USB_GLOB_GUSBCFG_FSINTF_LSB 5
2546 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */
2547 #define ALT_USB_GLOB_GUSBCFG_FSINTF_MSB 5
2548 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */
2549 #define ALT_USB_GLOB_GUSBCFG_FSINTF_WIDTH 1
2550 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_FSINTF register field value. */
2551 #define ALT_USB_GLOB_GUSBCFG_FSINTF_SET_MSK 0x00000020
2552 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_FSINTF register field value. */
2553 #define ALT_USB_GLOB_GUSBCFG_FSINTF_CLR_MSK 0xffffffdf
2554 /* The reset value of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */
2555 #define ALT_USB_GLOB_GUSBCFG_FSINTF_RESET 0x0
2556 /* Extracts the ALT_USB_GLOB_GUSBCFG_FSINTF field value from a register. */
2557 #define ALT_USB_GLOB_GUSBCFG_FSINTF_GET(value) (((value) & 0x00000020) >> 5)
2558 /* Produces a ALT_USB_GLOB_GUSBCFG_FSINTF register field value suitable for setting the register. */
2559 #define ALT_USB_GLOB_GUSBCFG_FSINTF_SET(value) (((value) << 5) & 0x00000020)
2560 
2561 /*
2562  * Field : physel
2563  *
2564  * Mode:Host and Device
2565  *
2566  * USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
2567  *
2568  * Transceiver Select (PHYSel)
2569  *
2570  * The application uses this bit to select either a high-speed UTMI+
2571  *
2572  * or ULPI PHY, or a full-speed transceiver.
2573  *
2574  * 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY
2575  *
2576  * 1'b1: USB 1.1 full-speed serial transceiver
2577  *
2578  * If a USB 1.1 Full-Speed Serial Transceiver interface was not
2579  *
2580  * selected in, this bit is always 0, with Write Only access.
2581  *
2582  * If a high-speed PHY interface was not selected in,
2583  *
2584  * this bit is always 1, with Write Only access.
2585  *
2586  * If both interface types were selected (parameters have non-zero values),
2587  *
2588  * the application uses this bit to select which interface is active,
2589  *
2590  * and access is Read and Write.
2591  *
2592  * Field Enumeration Values:
2593  *
2594  * Enum | Value | Description
2595  * :------------------------------------|:------|:------------------------
2596  * ALT_USB_GLOB_GUSBCFG_PHYSEL_E_USB20 | 0x0 | USB 2.0 high-speed ULPI
2597  *
2598  * Field Access Macros:
2599  *
2600  */
2601 /*
2602  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_PHYSEL
2603  *
2604  * USB 2.0 high-speed ULPI
2605  */
2606 #define ALT_USB_GLOB_GUSBCFG_PHYSEL_E_USB20 0x0
2607 
2608 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */
2609 #define ALT_USB_GLOB_GUSBCFG_PHYSEL_LSB 6
2610 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */
2611 #define ALT_USB_GLOB_GUSBCFG_PHYSEL_MSB 6
2612 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */
2613 #define ALT_USB_GLOB_GUSBCFG_PHYSEL_WIDTH 1
2614 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_PHYSEL register field value. */
2615 #define ALT_USB_GLOB_GUSBCFG_PHYSEL_SET_MSK 0x00000040
2616 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_PHYSEL register field value. */
2617 #define ALT_USB_GLOB_GUSBCFG_PHYSEL_CLR_MSK 0xffffffbf
2618 /* The reset value of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */
2619 #define ALT_USB_GLOB_GUSBCFG_PHYSEL_RESET 0x0
2620 /* Extracts the ALT_USB_GLOB_GUSBCFG_PHYSEL field value from a register. */
2621 #define ALT_USB_GLOB_GUSBCFG_PHYSEL_GET(value) (((value) & 0x00000040) >> 6)
2622 /* Produces a ALT_USB_GLOB_GUSBCFG_PHYSEL register field value suitable for setting the register. */
2623 #define ALT_USB_GLOB_GUSBCFG_PHYSEL_SET(value) (((value) << 6) & 0x00000040)
2624 
2625 /*
2626  * Field : ddrsel
2627  *
2628  * Mode:Host and Device
2629  *
2630  * ULPI DDR Select (DDRSel)
2631  *
2632  * The application uses this bit to select a Single Data Rate (SDR)
2633  *
2634  * or Double Data Rate (DDR) or ULPI interface.
2635  *
2636  * 1'b0: Single Data Rate ULPI Interface, with 8-bit-wide data
2637  *
2638  * bus
2639  *
2640  * 1'b1: Double Data Rate ULPI Interface, with 4-bit-wide data
2641  *
2642  * bus
2643  *
2644  * Field Enumeration Values:
2645  *
2646  * Enum | Value | Description
2647  * :----------------------------------|:------|:-------------------------------------------------
2648  * ALT_USB_GLOB_GUSBCFG_DDRSEL_E_SDR | 0x0 | Single Data Rate ULPI Interfacewith 8-bit-wide
2649  * : | | data bus
2650  * ALT_USB_GLOB_GUSBCFG_DDRSEL_E_DDR | 0x1 | Double Data Rate ULPI Interface, with 4-bit-wide
2651  * : | | data bus
2652  *
2653  * Field Access Macros:
2654  *
2655  */
2656 /*
2657  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_DDRSEL
2658  *
2659  * Single Data Rate ULPI Interfacewith 8-bit-wide data bus
2660  */
2661 #define ALT_USB_GLOB_GUSBCFG_DDRSEL_E_SDR 0x0
2662 /*
2663  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_DDRSEL
2664  *
2665  * Double Data Rate ULPI Interface, with 4-bit-wide data bus
2666  */
2667 #define ALT_USB_GLOB_GUSBCFG_DDRSEL_E_DDR 0x1
2668 
2669 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */
2670 #define ALT_USB_GLOB_GUSBCFG_DDRSEL_LSB 7
2671 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */
2672 #define ALT_USB_GLOB_GUSBCFG_DDRSEL_MSB 7
2673 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */
2674 #define ALT_USB_GLOB_GUSBCFG_DDRSEL_WIDTH 1
2675 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_DDRSEL register field value. */
2676 #define ALT_USB_GLOB_GUSBCFG_DDRSEL_SET_MSK 0x00000080
2677 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_DDRSEL register field value. */
2678 #define ALT_USB_GLOB_GUSBCFG_DDRSEL_CLR_MSK 0xffffff7f
2679 /* The reset value of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */
2680 #define ALT_USB_GLOB_GUSBCFG_DDRSEL_RESET 0x0
2681 /* Extracts the ALT_USB_GLOB_GUSBCFG_DDRSEL field value from a register. */
2682 #define ALT_USB_GLOB_GUSBCFG_DDRSEL_GET(value) (((value) & 0x00000080) >> 7)
2683 /* Produces a ALT_USB_GLOB_GUSBCFG_DDRSEL register field value suitable for setting the register. */
2684 #define ALT_USB_GLOB_GUSBCFG_DDRSEL_SET(value) (((value) << 7) & 0x00000080)
2685 
2686 /*
2687  * Field : srpcap
2688  *
2689  * Mode:Host and Device
2690  *
2691  * SRP-Capable (SRPCap)
2692  *
2693  * The application uses this bit to control the DWC_otg core SRP
2694  *
2695  * capabilities. If the core operates as a non-SRP-capable
2696  *
2697  * B-device, it cannot request the connected A-device (host) to
2698  *
2699  * activate VBUS and start a session.
2700  *
2701  * 1'b0: SRP capability is not enabled.
2702  *
2703  * 1'b1: SRP capability is enabled.
2704  *
2705  * Field Enumeration Values:
2706  *
2707  * Enum | Value | Description
2708  * :-----------------------------------|:------|:------------------------------
2709  * ALT_USB_GLOB_GUSBCFG_SRPCAP_E_DISD | 0x0 | SRP capability is not enabled
2710  * ALT_USB_GLOB_GUSBCFG_SRPCAP_E_END | 0x1 | SRP capability is enabled
2711  *
2712  * Field Access Macros:
2713  *
2714  */
2715 /*
2716  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_SRPCAP
2717  *
2718  * SRP capability is not enabled
2719  */
2720 #define ALT_USB_GLOB_GUSBCFG_SRPCAP_E_DISD 0x0
2721 /*
2722  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_SRPCAP
2723  *
2724  * SRP capability is enabled
2725  */
2726 #define ALT_USB_GLOB_GUSBCFG_SRPCAP_E_END 0x1
2727 
2728 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */
2729 #define ALT_USB_GLOB_GUSBCFG_SRPCAP_LSB 8
2730 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */
2731 #define ALT_USB_GLOB_GUSBCFG_SRPCAP_MSB 8
2732 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */
2733 #define ALT_USB_GLOB_GUSBCFG_SRPCAP_WIDTH 1
2734 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_SRPCAP register field value. */
2735 #define ALT_USB_GLOB_GUSBCFG_SRPCAP_SET_MSK 0x00000100
2736 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_SRPCAP register field value. */
2737 #define ALT_USB_GLOB_GUSBCFG_SRPCAP_CLR_MSK 0xfffffeff
2738 /* The reset value of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */
2739 #define ALT_USB_GLOB_GUSBCFG_SRPCAP_RESET 0x0
2740 /* Extracts the ALT_USB_GLOB_GUSBCFG_SRPCAP field value from a register. */
2741 #define ALT_USB_GLOB_GUSBCFG_SRPCAP_GET(value) (((value) & 0x00000100) >> 8)
2742 /* Produces a ALT_USB_GLOB_GUSBCFG_SRPCAP register field value suitable for setting the register. */
2743 #define ALT_USB_GLOB_GUSBCFG_SRPCAP_SET(value) (((value) << 8) & 0x00000100)
2744 
2745 /*
2746  * Field : hnpcap
2747  *
2748  * Mode:Host and Device
2749  *
2750  * HNP-Capable (HNPCap)
2751  *
2752  * The application uses this bit to control the DWC_otg core's HNP
2753  *
2754  * capabilities.
2755  *
2756  * 1'b0: HNP capability is not enabled.
2757  *
2758  * 1'b1: HNP capability is enabled.
2759  *
2760  * Field Enumeration Values:
2761  *
2762  * Enum | Value | Description
2763  * :-----------------------------------|:------|:-------------------------------
2764  * ALT_USB_GLOB_GUSBCFG_HNPCAP_E_DISD | 0x0 | HNP capability is not enabled.
2765  * ALT_USB_GLOB_GUSBCFG_HNPCAP_E_END | 0x1 | HNP capability is enabled
2766  *
2767  * Field Access Macros:
2768  *
2769  */
2770 /*
2771  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_HNPCAP
2772  *
2773  * HNP capability is not enabled.
2774  */
2775 #define ALT_USB_GLOB_GUSBCFG_HNPCAP_E_DISD 0x0
2776 /*
2777  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_HNPCAP
2778  *
2779  * HNP capability is enabled
2780  */
2781 #define ALT_USB_GLOB_GUSBCFG_HNPCAP_E_END 0x1
2782 
2783 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */
2784 #define ALT_USB_GLOB_GUSBCFG_HNPCAP_LSB 9
2785 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */
2786 #define ALT_USB_GLOB_GUSBCFG_HNPCAP_MSB 9
2787 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */
2788 #define ALT_USB_GLOB_GUSBCFG_HNPCAP_WIDTH 1
2789 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_HNPCAP register field value. */
2790 #define ALT_USB_GLOB_GUSBCFG_HNPCAP_SET_MSK 0x00000200
2791 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_HNPCAP register field value. */
2792 #define ALT_USB_GLOB_GUSBCFG_HNPCAP_CLR_MSK 0xfffffdff
2793 /* The reset value of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */
2794 #define ALT_USB_GLOB_GUSBCFG_HNPCAP_RESET 0x0
2795 /* Extracts the ALT_USB_GLOB_GUSBCFG_HNPCAP field value from a register. */
2796 #define ALT_USB_GLOB_GUSBCFG_HNPCAP_GET(value) (((value) & 0x00000200) >> 9)
2797 /* Produces a ALT_USB_GLOB_GUSBCFG_HNPCAP register field value suitable for setting the register. */
2798 #define ALT_USB_GLOB_GUSBCFG_HNPCAP_SET(value) (((value) << 9) & 0x00000200)
2799 
2800 /*
2801  * Field : usbtrdtim
2802  *
2803  * Mode: Device only
2804  *
2805  * USB Turnaround Time (USBTrdTim)
2806  *
2807  * Sets the turnaround time in PHY clocks.
2808  *
2809  * Specifies the response time For a MAC request to the Packet
2810  *
2811  * FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM).
2812  *
2813  * This must be programmed to
2814  *
2815  * 4'h5: When the MAC interface is 16-bit UTMI+ .
2816  *
2817  * 4'h9: When the MAC interface is 8-bit UTMI+ .
2818  *
2819  * Note: The values above are calculated For the minimum AHB
2820  *
2821  * frequency of 30 MHz. USB turnaround time is critical For
2822  *
2823  * certification where long cables and 5-Hubs are used, so If you
2824  *
2825  * need the AHB to run at less than 30 MHz, and If USB turnaround
2826  *
2827  * time is not critical, these bits can be programmed to a larger
2828  *
2829  * value.
2830  *
2831  * Field Enumeration Values:
2832  *
2833  * Enum | Value | Description
2834  * :------------------------------------------|:------|:------------------------------
2835  * ALT_USB_GLOB_GUSBCFG_USBTRDTIM_E_TURNTIME | 0x9 | MAC interface is 8-bit UTMI+.
2836  *
2837  * Field Access Macros:
2838  *
2839  */
2840 /*
2841  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_USBTRDTIM
2842  *
2843  * MAC interface is 8-bit UTMI+.
2844  */
2845 #define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_E_TURNTIME 0x9
2846 
2847 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */
2848 #define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_LSB 10
2849 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */
2850 #define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_MSB 13
2851 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */
2852 #define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_WIDTH 4
2853 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field value. */
2854 #define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_SET_MSK 0x00003c00
2855 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field value. */
2856 #define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_CLR_MSK 0xffffc3ff
2857 /* The reset value of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */
2858 #define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_RESET 0x5
2859 /* Extracts the ALT_USB_GLOB_GUSBCFG_USBTRDTIM field value from a register. */
2860 #define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_GET(value) (((value) & 0x00003c00) >> 10)
2861 /* Produces a ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field value suitable for setting the register. */
2862 #define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_SET(value) (((value) << 10) & 0x00003c00)
2863 
2864 /*
2865  * Field : ulpiautores
2866  *
2867  * Mode:Host and Device
2868  *
2869  * ULPI Auto Resume (ULPIAutoRes)
2870  *
2871  * This bit sets the AutoResume bit in the Interface Control register
2872  *
2873  * on the ULPI PHY.
2874  *
2875  * 1'b0: PHY does not use AutoResume feature.
2876  *
2877  * 1'b1: PHY uses AutoResume feature.
2878  *
2879  * Field Enumeration Values:
2880  *
2881  * Enum | Value | Description
2882  * :----------------------------------------|:------|:------------------------------------
2883  * ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_DISD | 0x0 | PHY does not use AutoResume feature
2884  * ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_END | 0x1 | PHY uses AutoResume feature
2885  *
2886  * Field Access Macros:
2887  *
2888  */
2889 /*
2890  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIAUTORES
2891  *
2892  * PHY does not use AutoResume feature
2893  */
2894 #define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_DISD 0x0
2895 /*
2896  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIAUTORES
2897  *
2898  * PHY uses AutoResume feature
2899  */
2900 #define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_END 0x1
2901 
2902 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */
2903 #define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_LSB 18
2904 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */
2905 #define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_MSB 18
2906 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */
2907 #define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_WIDTH 1
2908 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field value. */
2909 #define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_SET_MSK 0x00040000
2910 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field value. */
2911 #define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_CLR_MSK 0xfffbffff
2912 /* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */
2913 #define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_RESET 0x0
2914 /* Extracts the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES field value from a register. */
2915 #define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_GET(value) (((value) & 0x00040000) >> 18)
2916 /* Produces a ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field value suitable for setting the register. */
2917 #define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_SET(value) (((value) << 18) & 0x00040000)
2918 
2919 /*
2920  * Field : ulpiclksusm
2921  *
2922  * Mode:Host and Device
2923  *
2924  * ULPI Clock SuspendM (ULPIClkSusM)
2925  *
2926  * This bit sets the ClockSuspendM bit in the Interface Control
2927  *
2928  * register on the ULPI PHY. This bit applies only in serial or carkit
2929  *
2930  * modes.
2931  *
2932  * 1'b0: PHY powers down internal clock during suspend.
2933  *
2934  * 1'b1: PHY does not power down internal clock.
2935  *
2936  * Field Enumeration Values:
2937  *
2938  * Enum | Value | Description
2939  * :---------------------------------------------|:------|:----------------------------------------------
2940  * ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_PWDCLK | 0x0 | PHY powers down internal clock during suspend
2941  * ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_NONPWDCLK | 0x1 | PHY does not power down internal clock
2942  *
2943  * Field Access Macros:
2944  *
2945  */
2946 /*
2947  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM
2948  *
2949  * PHY powers down internal clock during suspend
2950  */
2951 #define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_PWDCLK 0x0
2952 /*
2953  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM
2954  *
2955  * PHY does not power down internal clock
2956  */
2957 #define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_NONPWDCLK 0x1
2958 
2959 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */
2960 #define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_LSB 19
2961 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */
2962 #define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_MSB 19
2963 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */
2964 #define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_WIDTH 1
2965 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field value. */
2966 #define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_SET_MSK 0x00080000
2967 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field value. */
2968 #define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_CLR_MSK 0xfff7ffff
2969 /* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */
2970 #define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_RESET 0x0
2971 /* Extracts the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM field value from a register. */
2972 #define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_GET(value) (((value) & 0x00080000) >> 19)
2973 /* Produces a ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field value suitable for setting the register. */
2974 #define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_SET(value) (((value) << 19) & 0x00080000)
2975 
2976 /*
2977  * Field : ulpiextvbusdrv
2978  *
2979  * Mode:Host only
2980  *
2981  * ULPI External VBUS Drive (ULPIExtVbusDrv)
2982  *
2983  * This bit selects between internal or external supply to drive 5V
2984  *
2985  * on VBUS, in ULPI PHY.
2986  *
2987  * 1'b0: PHY drives VBUS using internal charge pump (Default).
2988  *
2989  * 1'b1: PHY drives VBUS using external supply.
2990  *
2991  * Field Enumeration Values:
2992  *
2993  * Enum | Value | Description
2994  * :---------------------------------------------|:------|:-------------------------------------------
2995  * ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_INTERN | 0x0 | PHY drives VBUS using internal charge pump
2996  * ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_EXTERN | 0x1 | PHY drives VBUS using external supply
2997  *
2998  * Field Access Macros:
2999  *
3000  */
3001 /*
3002  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV
3003  *
3004  * PHY drives VBUS using internal charge pump
3005  */
3006 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_INTERN 0x0
3007 /*
3008  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV
3009  *
3010  * PHY drives VBUS using external supply
3011  */
3012 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_EXTERN 0x1
3013 
3014 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */
3015 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_LSB 20
3016 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */
3017 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_MSB 20
3018 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */
3019 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_WIDTH 1
3020 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field value. */
3021 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_SET_MSK 0x00100000
3022 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field value. */
3023 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_CLR_MSK 0xffefffff
3024 /* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */
3025 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_RESET 0x0
3026 /* Extracts the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV field value from a register. */
3027 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_GET(value) (((value) & 0x00100000) >> 20)
3028 /* Produces a ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field value suitable for setting the register. */
3029 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_SET(value) (((value) << 20) & 0x00100000)
3030 
3031 /*
3032  * Field : ulpiextvbusindicator
3033  *
3034  * Mode:Host only
3035  *
3036  * ULPI External VBUS Indicator (ULPIExtVbusIndicator)
3037  *
3038  * This bit indicates to the ULPI PHY to use an external VBUS overcurrent
3039  *
3040  * indicator.
3041  *
3042  * 1'b0: PHY uses internal VBUS valid comparator.
3043  *
3044  * 1'b1: PHY uses external VBUS valid comparator.
3045  *
3046  * Field Enumeration Values:
3047  *
3048  * Enum | Value | Description
3049  * :---------------------------------------------------|:------|:----------------------------------------
3050  * ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_INTERN | 0x0 | PHY uses internal VBUS valid comparator
3051  * ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_EXTERN | 0x1 | PHY uses external VBUS valid comparator
3052  *
3053  * Field Access Macros:
3054  *
3055  */
3056 /*
3057  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR
3058  *
3059  * PHY uses internal VBUS valid comparator
3060  */
3061 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_INTERN 0x0
3062 /*
3063  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR
3064  *
3065  * PHY uses external VBUS valid comparator
3066  */
3067 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_EXTERN 0x1
3068 
3069 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */
3070 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_LSB 21
3071 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */
3072 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_MSB 21
3073 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */
3074 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_WIDTH 1
3075 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field value. */
3076 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_SET_MSK 0x00200000
3077 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field value. */
3078 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_CLR_MSK 0xffdfffff
3079 /* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */
3080 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_RESET 0x0
3081 /* Extracts the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR field value from a register. */
3082 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_GET(value) (((value) & 0x00200000) >> 21)
3083 /* Produces a ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field value suitable for setting the register. */
3084 #define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_SET(value) (((value) << 21) & 0x00200000)
3085 
3086 /*
3087  * Field : termseldlpulse
3088  *
3089  * Mode:Device only
3090  *
3091  * TermSel DLine Pulsing Selection (TermSelDLPulse)
3092  *
3093  * This bit selects utmi_termselect to drive data line pulse during
3094  *
3095  * SRP.
3096  *
3097  * 1'b0: Data line pulsing using utmi_txvalid (Default).
3098  *
3099  * 1'b1: Data line pulsing using utmi_termsel.
3100  *
3101  * Field Enumeration Values:
3102  *
3103  * Enum | Value | Description
3104  * :----------------------------------------------|:------|:-------------------------------------
3105  * ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TXVALID | 0x0 | Data line pulsing using utmi_txvalid
3106  * ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TERMSEL | 0x1 | Data line pulsing using utmi_termsel
3107  *
3108  * Field Access Macros:
3109  *
3110  */
3111 /*
3112  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE
3113  *
3114  * Data line pulsing using utmi_txvalid
3115  */
3116 #define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TXVALID 0x0
3117 /*
3118  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE
3119  *
3120  * Data line pulsing using utmi_termsel
3121  */
3122 #define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TERMSEL 0x1
3123 
3124 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */
3125 #define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_LSB 22
3126 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */
3127 #define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_MSB 22
3128 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */
3129 #define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_WIDTH 1
3130 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field value. */
3131 #define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_SET_MSK 0x00400000
3132 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field value. */
3133 #define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_CLR_MSK 0xffbfffff
3134 /* The reset value of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */
3135 #define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_RESET 0x0
3136 /* Extracts the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE field value from a register. */
3137 #define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_GET(value) (((value) & 0x00400000) >> 22)
3138 /* Produces a ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field value suitable for setting the register. */
3139 #define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_SET(value) (((value) << 22) & 0x00400000)
3140 
3141 /*
3142  * Field : complement
3143  *
3144  * Mode:Host only
3145  *
3146  * Indicator Complement
3147  *
3148  * Controls the PHY to invert the ExternalVbusIndicator input
3149  *
3150  * signal, generating the Complement
3151  *
3152  * Output. Please refer to the ULPI Spec For more detail
3153  *
3154  * 1'b0: PHY does not invert ExternalVbusIndicator signal
3155  *
3156  * 1'b1: PHY does invert ExternalVbusIndicator signal
3157  *
3158  * Field Enumeration Values:
3159  *
3160  * Enum | Value | Description
3161  * :--------------------------------------------|:------|:-------------------------------------------------
3162  * ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_NONINVERT | 0x0 | PHY does not invert ExternalVbusIndicator signal
3163  * ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_INVERT | 0x1 | PHY does invert ExternalVbusIndicator signal
3164  *
3165  * Field Access Macros:
3166  *
3167  */
3168 /*
3169  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_COMPLEMENT
3170  *
3171  * PHY does not invert ExternalVbusIndicator signal
3172  */
3173 #define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_NONINVERT 0x0
3174 /*
3175  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_COMPLEMENT
3176  *
3177  * PHY does invert ExternalVbusIndicator signal
3178  */
3179 #define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_INVERT 0x1
3180 
3181 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */
3182 #define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_LSB 23
3183 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */
3184 #define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_MSB 23
3185 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */
3186 #define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_WIDTH 1
3187 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field value. */
3188 #define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_SET_MSK 0x00800000
3189 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field value. */
3190 #define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_CLR_MSK 0xff7fffff
3191 /* The reset value of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */
3192 #define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_RESET 0x0
3193 /* Extracts the ALT_USB_GLOB_GUSBCFG_COMPLEMENT field value from a register. */
3194 #define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_GET(value) (((value) & 0x00800000) >> 23)
3195 /* Produces a ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field value suitable for setting the register. */
3196 #define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_SET(value) (((value) << 23) & 0x00800000)
3197 
3198 /*
3199  * Field : indicator
3200  *
3201  * Mode:Host only
3202  *
3203  * Indicator Pass Through
3204  *
3205  * Controls wether the Complement Output is qualified with the
3206  *
3207  * Internal Vbus Valid comparator before being used
3208  *
3209  * in the Vbus State in the RX CMD. Please refer to the ULPI Spec
3210  *
3211  * for more detail.
3212  *
3213  * 1'b0: Complement Output signal is qualified with the Internal
3214  *
3215  * VbusValid comparator.
3216  *
3217  * 1'b1: Complement Output signal is not qualified with the
3218  *
3219  * Internal VbusValid comparator.
3220  *
3221  * Field Enumeration Values:
3222  *
3223  * Enum | Value | Description
3224  * :----------------------------------------------|:------|:------------------------------------------------
3225  * ALT_USB_GLOB_GUSBCFG_INDICATOR_E_QUALIFIED | 0x0 | Complement Output signal is qualified with the
3226  * : | | Internal VbusValid comparator
3227  * ALT_USB_GLOB_GUSBCFG_INDICATOR_E_NONQUALIFIED | 0x1 | Complement Output signal is not qualified with
3228  * : | | the Internal VbusValid comparator
3229  *
3230  * Field Access Macros:
3231  *
3232  */
3233 /*
3234  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_INDICATOR
3235  *
3236  * Complement Output signal is qualified with the Internal VbusValid comparator
3237  */
3238 #define ALT_USB_GLOB_GUSBCFG_INDICATOR_E_QUALIFIED 0x0
3239 /*
3240  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_INDICATOR
3241  *
3242  * Complement Output signal is not qualified with the Internal VbusValid
3243  * comparator
3244  */
3245 #define ALT_USB_GLOB_GUSBCFG_INDICATOR_E_NONQUALIFIED 0x1
3246 
3247 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */
3248 #define ALT_USB_GLOB_GUSBCFG_INDICATOR_LSB 24
3249 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */
3250 #define ALT_USB_GLOB_GUSBCFG_INDICATOR_MSB 24
3251 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */
3252 #define ALT_USB_GLOB_GUSBCFG_INDICATOR_WIDTH 1
3253 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_INDICATOR register field value. */
3254 #define ALT_USB_GLOB_GUSBCFG_INDICATOR_SET_MSK 0x01000000
3255 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_INDICATOR register field value. */
3256 #define ALT_USB_GLOB_GUSBCFG_INDICATOR_CLR_MSK 0xfeffffff
3257 /* The reset value of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */
3258 #define ALT_USB_GLOB_GUSBCFG_INDICATOR_RESET 0x0
3259 /* Extracts the ALT_USB_GLOB_GUSBCFG_INDICATOR field value from a register. */
3260 #define ALT_USB_GLOB_GUSBCFG_INDICATOR_GET(value) (((value) & 0x01000000) >> 24)
3261 /* Produces a ALT_USB_GLOB_GUSBCFG_INDICATOR register field value suitable for setting the register. */
3262 #define ALT_USB_GLOB_GUSBCFG_INDICATOR_SET(value) (((value) << 24) & 0x01000000)
3263 
3264 /*
3265  * Field : ulpi
3266  *
3267  * Mode:Host only
3268  *
3269  * ULPI Interface Protect Disable
3270  *
3271  * Controls circuitry built into the PHY For protecting the ULPI
3272  *
3273  * interface when the link tri-states STP and data.
3274  *
3275  * Any pull-ups or pull-downs employed by this feature can be
3276  *
3277  * disabled. Please refer to the ULPI Specification For more detail.
3278  *
3279  * 1'b0: Enables the interface protect circuit
3280  *
3281  * 1'b1: Disables the interface protect circuit
3282  *
3283  * Field Enumeration Values:
3284  *
3285  * Enum | Value | Description
3286  * :---------------------------------|:------|:---------------------------------------
3287  * ALT_USB_GLOB_GUSBCFG_ULPI_E_END | 0x0 | Enables the interface protect circuit
3288  * ALT_USB_GLOB_GUSBCFG_ULPI_E_DISD | 0x1 | Disables the interface protect circuit
3289  *
3290  * Field Access Macros:
3291  *
3292  */
3293 /*
3294  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPI
3295  *
3296  * Enables the interface protect circuit
3297  */
3298 #define ALT_USB_GLOB_GUSBCFG_ULPI_E_END 0x0
3299 /*
3300  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPI
3301  *
3302  * Disables the interface protect circuit
3303  */
3304 #define ALT_USB_GLOB_GUSBCFG_ULPI_E_DISD 0x1
3305 
3306 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */
3307 #define ALT_USB_GLOB_GUSBCFG_ULPI_LSB 25
3308 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */
3309 #define ALT_USB_GLOB_GUSBCFG_ULPI_MSB 25
3310 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */
3311 #define ALT_USB_GLOB_GUSBCFG_ULPI_WIDTH 1
3312 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPI register field value. */
3313 #define ALT_USB_GLOB_GUSBCFG_ULPI_SET_MSK 0x02000000
3314 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPI register field value. */
3315 #define ALT_USB_GLOB_GUSBCFG_ULPI_CLR_MSK 0xfdffffff
3316 /* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */
3317 #define ALT_USB_GLOB_GUSBCFG_ULPI_RESET 0x0
3318 /* Extracts the ALT_USB_GLOB_GUSBCFG_ULPI field value from a register. */
3319 #define ALT_USB_GLOB_GUSBCFG_ULPI_GET(value) (((value) & 0x02000000) >> 25)
3320 /* Produces a ALT_USB_GLOB_GUSBCFG_ULPI register field value suitable for setting the register. */
3321 #define ALT_USB_GLOB_GUSBCFG_ULPI_SET(value) (((value) << 25) & 0x02000000)
3322 
3323 /*
3324  * Field : ic_usbcap
3325  *
3326  * IC_USB-Capable (IC_USBCap)
3327  *
3328  * The application uses this bit to control the DWC_otg core's IC_USB
3329  *
3330  * capabilities.
3331  *
3332  * 1'b0: IC_USB PHY Interface is not selected.
3333  *
3334  * 1'b1: IC_USB PHY Interface is selected.
3335  *
3336  * This bit is writable only if IC_USB is selected
3337  *
3338  * Field Access Macros:
3339  *
3340  */
3341 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field. */
3342 #define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_LSB 26
3343 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field. */
3344 #define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_MSB 26
3345 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field. */
3346 #define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_WIDTH 1
3347 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field value. */
3348 #define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_SET_MSK 0x04000000
3349 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field value. */
3350 #define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_CLR_MSK 0xfbffffff
3351 /* The reset value of the ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field. */
3352 #define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_RESET 0x0
3353 /* Extracts the ALT_USB_GLOB_GUSBCFG_IC_USBCAP field value from a register. */
3354 #define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_GET(value) (((value) & 0x04000000) >> 26)
3355 /* Produces a ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field value suitable for setting the register. */
3356 #define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_SET(value) (((value) << 26) & 0x04000000)
3357 
3358 /*
3359  * Field : txenddelay
3360  *
3361  * Mode: Device only
3362  *
3363  * Tx End Delay (TxEndDelay)
3364  *
3365  * Writing 1'b1 to this bit enables the core to follow the TxEndDelay timings as
3366  * per UTMI+ specification 1.05 section 4.1.5 for opmode signal during remote
3367  * wakeup.
3368  *
3369  * 1'b0 : Normal Mode.
3370  *
3371  * 1'b1 : Tx End delay.
3372  *
3373  * Field Enumeration Values:
3374  *
3375  * Enum | Value | Description
3376  * :---------------------------------------|:------|:------------
3377  * ALT_USB_GLOB_GUSBCFG_TXENDDELAY_E_DISD | 0x0 | Normal Mode
3378  *
3379  * Field Access Macros:
3380  *
3381  */
3382 /*
3383  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_TXENDDELAY
3384  *
3385  * Normal Mode
3386  */
3387 #define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_E_DISD 0x0
3388 
3389 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */
3390 #define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_LSB 28
3391 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */
3392 #define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_MSB 28
3393 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */
3394 #define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_WIDTH 1
3395 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field value. */
3396 #define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_SET_MSK 0x10000000
3397 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field value. */
3398 #define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_CLR_MSK 0xefffffff
3399 /* The reset value of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */
3400 #define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_RESET 0x0
3401 /* Extracts the ALT_USB_GLOB_GUSBCFG_TXENDDELAY field value from a register. */
3402 #define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_GET(value) (((value) & 0x10000000) >> 28)
3403 /* Produces a ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field value suitable for setting the register. */
3404 #define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_SET(value) (((value) << 28) & 0x10000000)
3405 
3406 /*
3407  * Field : forcehstmode
3408  *
3409  * Mode:Host and device
3410  *
3411  * Force Host Mode (ForceHstMode)
3412  *
3413  * Writing a 1 to this bit forces the core to host mode irrespective of
3414  *
3415  * utmiotg_iddig input pin.
3416  *
3417  * 1'b0 : Normal Mode.
3418  *
3419  * 1'b1 : Force Host Mode.
3420  *
3421  * After setting the force bit, the application must wait at least 25 ms before
3422  *
3423  * the change to take effect. When the simulation is in scale down mode,
3424  *
3425  * waiting for 500 micro sec is sufficient.
3426  *
3427  * Field Enumeration Values:
3428  *
3429  * Enum | Value | Description
3430  * :----------------------------------------|:------|:----------------
3431  * ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_DISD | 0x0 | Normal Mode
3432  * ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_END | 0x1 | Force Host Mode
3433  *
3434  * Field Access Macros:
3435  *
3436  */
3437 /*
3438  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD
3439  *
3440  * Normal Mode
3441  */
3442 #define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_DISD 0x0
3443 /*
3444  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD
3445  *
3446  * Force Host Mode
3447  */
3448 #define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_END 0x1
3449 
3450 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */
3451 #define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_LSB 29
3452 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */
3453 #define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_MSB 29
3454 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */
3455 #define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_WIDTH 1
3456 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field value. */
3457 #define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_SET_MSK 0x20000000
3458 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field value. */
3459 #define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_CLR_MSK 0xdfffffff
3460 /* The reset value of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */
3461 #define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_RESET 0x0
3462 /* Extracts the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD field value from a register. */
3463 #define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_GET(value) (((value) & 0x20000000) >> 29)
3464 /* Produces a ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field value suitable for setting the register. */
3465 #define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_SET(value) (((value) << 29) & 0x20000000)
3466 
3467 /*
3468  * Field : forcedevmode
3469  *
3470  * Mode:Host and device
3471  *
3472  * Force Device Mode (ForceDevMode)
3473  *
3474  * Writing a 1 to this bit forces the core to device mode irrespective
3475  *
3476  * of utmiotg_iddig input pin.
3477  *
3478  * 1'b0 : Normal Mode.
3479  *
3480  * 1'b1 : Force Device Mode.
3481  *
3482  * After setting the force bit, the application must wait at least 25 ms before
3483  *
3484  * the change to take effect. When the simulation is in scale down mode,
3485  *
3486  * waiting for 500 micro sec is sufficient.
3487  *
3488  * Field Enumeration Values:
3489  *
3490  * Enum | Value | Description
3491  * :----------------------------------------|:------|:------------------
3492  * ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_DISD | 0x0 | Normal Mode
3493  * ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_END | 0x1 | Force Device Mode
3494  *
3495  * Field Access Macros:
3496  *
3497  */
3498 /*
3499  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD
3500  *
3501  * Normal Mode
3502  */
3503 #define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_DISD 0x0
3504 /*
3505  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD
3506  *
3507  * Force Device Mode
3508  */
3509 #define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_END 0x1
3510 
3511 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */
3512 #define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_LSB 30
3513 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */
3514 #define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_MSB 30
3515 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */
3516 #define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_WIDTH 1
3517 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field value. */
3518 #define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_SET_MSK 0x40000000
3519 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field value. */
3520 #define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_CLR_MSK 0xbfffffff
3521 /* The reset value of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */
3522 #define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_RESET 0x0
3523 /* Extracts the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD field value from a register. */
3524 #define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_GET(value) (((value) & 0x40000000) >> 30)
3525 /* Produces a ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field value suitable for setting the register. */
3526 #define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_SET(value) (((value) << 30) & 0x40000000)
3527 
3528 /*
3529  * Field : corrupttxpkt
3530  *
3531  * Mode:Host and device
3532  *
3533  * Corrupt Tx packet
3534  *
3535  * This bit is FOr debug purposes only. Never Set this bit to 1.The application
3536  * should always write 1'b0 to this bit.
3537  *
3538  * Field Enumeration Values:
3539  *
3540  * Enum | Value | Description
3541  * :------------------------------------------|:------|:------------
3542  * ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_NODBG | 0x0 | Normal Mode
3543  * ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_DBG | 0x1 | Debug Mode
3544  *
3545  * Field Access Macros:
3546  *
3547  */
3548 /*
3549  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT
3550  *
3551  * Normal Mode
3552  */
3553 #define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_NODBG 0x0
3554 /*
3555  * Enumerated value for register field ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT
3556  *
3557  * Debug Mode
3558  */
3559 #define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_DBG 0x1
3560 
3561 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */
3562 #define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_LSB 31
3563 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */
3564 #define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_MSB 31
3565 /* The width in bits of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */
3566 #define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_WIDTH 1
3567 /* The mask used to set the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field value. */
3568 #define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_SET_MSK 0x80000000
3569 /* The mask used to clear the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field value. */
3570 #define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_CLR_MSK 0x7fffffff
3571 /* The reset value of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */
3572 #define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_RESET 0x0
3573 /* Extracts the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT field value from a register. */
3574 #define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_GET(value) (((value) & 0x80000000) >> 31)
3575 /* Produces a ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field value suitable for setting the register. */
3576 #define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_SET(value) (((value) << 31) & 0x80000000)
3577 
3578 #ifndef __ASSEMBLY__
3579 /*
3580  * WARNING: The C register and register group struct declarations are provided for
3581  * convenience and illustrative purposes. They should, however, be used with
3582  * caution as the C language standard provides no guarantees about the alignment or
3583  * atomicity of device memory accesses. The recommended practice for writing
3584  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3585  * alt_write_word() functions.
3586  *
3587  * The struct declaration for register ALT_USB_GLOB_GUSBCFG.
3588  */
3589 struct ALT_USB_GLOB_GUSBCFG_s
3590 {
3591  uint32_t toutcal : 3; /* ALT_USB_GLOB_GUSBCFG_TOUTCAL */
3592  const uint32_t phyif : 1; /* ALT_USB_GLOB_GUSBCFG_PHYIF */
3593  const uint32_t ulpi_utmi_sel : 1; /* ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL */
3594  const uint32_t fsintf : 1; /* ALT_USB_GLOB_GUSBCFG_FSINTF */
3595  const uint32_t physel : 1; /* ALT_USB_GLOB_GUSBCFG_PHYSEL */
3596  uint32_t ddrsel : 1; /* ALT_USB_GLOB_GUSBCFG_DDRSEL */
3597  uint32_t srpcap : 1; /* ALT_USB_GLOB_GUSBCFG_SRPCAP */
3598  uint32_t hnpcap : 1; /* ALT_USB_GLOB_GUSBCFG_HNPCAP */
3599  uint32_t usbtrdtim : 4; /* ALT_USB_GLOB_GUSBCFG_USBTRDTIM */
3600  uint32_t : 4; /* *UNDEFINED* */
3601  uint32_t ulpiautores : 1; /* ALT_USB_GLOB_GUSBCFG_ULPIAUTORES */
3602  uint32_t ulpiclksusm : 1; /* ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM */
3603  uint32_t ulpiextvbusdrv : 1; /* ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV */
3604  uint32_t ulpiextvbusindicator : 1; /* ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR */
3605  uint32_t termseldlpulse : 1; /* ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE */
3606  uint32_t complement : 1; /* ALT_USB_GLOB_GUSBCFG_COMPLEMENT */
3607  uint32_t indicator : 1; /* ALT_USB_GLOB_GUSBCFG_INDICATOR */
3608  uint32_t ulpi : 1; /* ALT_USB_GLOB_GUSBCFG_ULPI */
3609  const uint32_t ic_usbcap : 1; /* ALT_USB_GLOB_GUSBCFG_IC_USBCAP */
3610  uint32_t : 1; /* *UNDEFINED* */
3611  uint32_t txenddelay : 1; /* ALT_USB_GLOB_GUSBCFG_TXENDDELAY */
3612  uint32_t forcehstmode : 1; /* ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD */
3613  uint32_t forcedevmode : 1; /* ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD */
3614  uint32_t corrupttxpkt : 1; /* ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT */
3615 };
3616 
3617 /* The typedef declaration for register ALT_USB_GLOB_GUSBCFG. */
3618 typedef volatile struct ALT_USB_GLOB_GUSBCFG_s ALT_USB_GLOB_GUSBCFG_t;
3619 #endif /* __ASSEMBLY__ */
3620 
3621 /* The reset value of the ALT_USB_GLOB_GUSBCFG register. */
3622 #define ALT_USB_GLOB_GUSBCFG_RESET 0x00001410
3623 /* The byte offset of the ALT_USB_GLOB_GUSBCFG register from the beginning of the component. */
3624 #define ALT_USB_GLOB_GUSBCFG_OFST 0xc
3625 /* The address of the ALT_USB_GLOB_GUSBCFG register. */
3626 #define ALT_USB_GLOB_GUSBCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GUSBCFG_OFST))
3627 
3628 /*
3629  * Register : grstctl
3630  *
3631  * Reset Register
3632  *
3633  * Register Layout
3634  *
3635  * Bits | Access | Reset | Description
3636  * :--------|:---------|:------|:---------------------------------
3637  * [0] | R-W once | 0x0 | ALT_USB_GLOB_GRSTCTL_CSFTRST
3638  * [1] | R-W once | 0x0 | ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST
3639  * [2] | R-W once | 0x0 | ALT_USB_GLOB_GRSTCTL_FRMCNTRRST
3640  * [3] | ??? | 0x0 | *UNDEFINED*
3641  * [4] | R-W once | 0x0 | ALT_USB_GLOB_GRSTCTL_RXFFLSH
3642  * [5] | R-W once | 0x0 | ALT_USB_GLOB_GRSTCTL_TXFFLSH
3643  * [10:6] | RW | 0x0 | ALT_USB_GLOB_GRSTCTL_TXFNUM
3644  * [29:11] | ??? | 0x0 | *UNDEFINED*
3645  * [30] | R | 0x0 | ALT_USB_GLOB_GRSTCTL_DMAREQ
3646  * [31] | R | 0x1 | ALT_USB_GLOB_GRSTCTL_AHBIDLE
3647  *
3648  */
3649 /*
3650  * Field : csftrst
3651  *
3652  * Mode:Host and Device
3653  *
3654  * Core Soft Reset (CSftRst)
3655  *
3656  * Resets the hclk and phy_clock domains as follows:
3657  *
3658  * Clears the interrupts and all the CSR registers except the
3659  *
3660  * following register bits:
3661  *
3662  * * PCGCCTL.RstPdwnModule
3663  *
3664  * * PCGCCTL.GateHclk
3665  *
3666  * * PCGCCTL.PwrClmp
3667  *
3668  * * PCGCCTL.StopPPhyLPwrClkSelclk
3669  *
3670  * * GUSBCFG.PhyLPwrClkSel
3671  *
3672  * * GUSBCFG.DDRSel
3673  *
3674  * * GUSBCFG.PHYSel
3675  *
3676  * * GUSBCFG.FSIntf
3677  *
3678  * * GUSBCFG.ULPI_UTMI_Sel
3679  *
3680  * * GUSBCFG.PHYIf
3681  *
3682  * * GUSBCFG.TxEndDelay
3683  *
3684  * * GUSBCFG.TermSelDLPulse
3685  *
3686  * * GUSBCFG.ULPIClkSusM
3687  *
3688  * * GUSBCFG.ULPIAutoRes
3689  *
3690  * * GUSBCFG.ULPIFsLs
3691  *
3692  * * GGPIO
3693  *
3694  * * GPWRDN
3695  *
3696  * * GADPCTL
3697  *
3698  * * HCFG.FSLSPclkSel
3699  *
3700  * * DCFG.DevSpd
3701  *
3702  * * DCTL.SftDiscon
3703  *
3704  * * All module state machines
3705  *
3706  * All module state machines (except the AHB Slave Unit) are
3707  *
3708  * reset to the IDLE state, and all the transmit FIFOs and the
3709  *
3710  * receive FIFO are flushed.
3711  *
3712  * Any transactions on the AHB Master are terminated as soon
3713  *
3714  * as possible, after gracefully completing the last data phase of
3715  *
3716  * an AHB transfer. Any transactions on the USB are terminated
3717  *
3718  * immediately.
3719  *
3720  * When Hibernation or ADP feature is enabled, the PMU module is not
3721  *
3722  * reset by the Core Soft Reset.
3723  *
3724  * The application can write to this bit any time it wants to reset the
3725  *
3726  * core. This is a self-clearing bit and the core clears this bit after
3727  *
3728  * all the necessary logic is reset in the core, which can take
3729  *
3730  * several clocks, depending on the current state of the core. Once
3731  *
3732  * this bit is cleared software must wait at least 3 PHY clocks
3733  *
3734  * before doing any access to the PHY domain (synchronization
3735  *
3736  * delay). Software must also must check that bit 31 of this register
3737  *
3738  * is 1 (AHB Master is IDLE) before starting any operation.
3739  *
3740  * Typically software reset is used during software development
3741  *
3742  * and also when you dynamically change the PHY selection bits in
3743  *
3744  * the USB configuration registers listed above. When you change
3745  *
3746  * the PHY, the corresponding clock For the PHY is selected and
3747  *
3748  * used in the PHY domain. Once a new clock is selected, the PHY
3749  *
3750  * domain has to be reset for proper operation.
3751  *
3752  * Field Enumeration Values:
3753  *
3754  * Enum | Value | Description
3755  * :--------------------------------------|:------|:----------------------------------
3756  * ALT_USB_GLOB_GRSTCTL_CSFTRST_E_NOTACT | 0x0 | No reset
3757  * ALT_USB_GLOB_GRSTCTL_CSFTRST_E_ACT | 0x1 | Resets hclk and phy_clock domains
3758  *
3759  * Field Access Macros:
3760  *
3761  */
3762 /*
3763  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_CSFTRST
3764  *
3765  * No reset
3766  */
3767 #define ALT_USB_GLOB_GRSTCTL_CSFTRST_E_NOTACT 0x0
3768 /*
3769  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_CSFTRST
3770  *
3771  * Resets hclk and phy_clock domains
3772  */
3773 #define ALT_USB_GLOB_GRSTCTL_CSFTRST_E_ACT 0x1
3774 
3775 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */
3776 #define ALT_USB_GLOB_GRSTCTL_CSFTRST_LSB 0
3777 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */
3778 #define ALT_USB_GLOB_GRSTCTL_CSFTRST_MSB 0
3779 /* The width in bits of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */
3780 #define ALT_USB_GLOB_GRSTCTL_CSFTRST_WIDTH 1
3781 /* The mask used to set the ALT_USB_GLOB_GRSTCTL_CSFTRST register field value. */
3782 #define ALT_USB_GLOB_GRSTCTL_CSFTRST_SET_MSK 0x00000001
3783 /* The mask used to clear the ALT_USB_GLOB_GRSTCTL_CSFTRST register field value. */
3784 #define ALT_USB_GLOB_GRSTCTL_CSFTRST_CLR_MSK 0xfffffffe
3785 /* The reset value of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */
3786 #define ALT_USB_GLOB_GRSTCTL_CSFTRST_RESET 0x0
3787 /* Extracts the ALT_USB_GLOB_GRSTCTL_CSFTRST field value from a register. */
3788 #define ALT_USB_GLOB_GRSTCTL_CSFTRST_GET(value) (((value) & 0x00000001) >> 0)
3789 /* Produces a ALT_USB_GLOB_GRSTCTL_CSFTRST register field value suitable for setting the register. */
3790 #define ALT_USB_GLOB_GRSTCTL_CSFTRST_SET(value) (((value) << 0) & 0x00000001)
3791 
3792 /*
3793  * Field : piufssftrst
3794  *
3795  * Mode:Host and Device
3796  *
3797  * PIU FS Dedicated Controller Soft Reset (PIUFSSftRst)
3798  *
3799  * Resets the PIU FS Dedicated Controller
3800  *
3801  * All module state machines in FS Dedicated Controller of PIU are
3802  *
3803  * reset to the IDLE state. Used to reset the FS Dedicated controller in PIU in
3804  * case of any PHY Errors like Loss of activity or Babble Error resulting in the
3805  * PHY remaining in RX state for more than one frame boundary
3806  *
3807  * Field Access Macros:
3808  *
3809  */
3810 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field. */
3811 #define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_LSB 1
3812 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field. */
3813 #define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_MSB 1
3814 /* The width in bits of the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field. */
3815 #define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_WIDTH 1
3816 /* The mask used to set the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field value. */
3817 #define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_SET_MSK 0x00000002
3818 /* The mask used to clear the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field value. */
3819 #define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_CLR_MSK 0xfffffffd
3820 /* The reset value of the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field. */
3821 #define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_RESET 0x0
3822 /* Extracts the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST field value from a register. */
3823 #define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_GET(value) (((value) & 0x00000002) >> 1)
3824 /* Produces a ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field value suitable for setting the register. */
3825 #define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_SET(value) (((value) << 1) & 0x00000002)
3826 
3827 /*
3828  * Field : frmcntrrst
3829  *
3830  * Mode:Host only
3831  *
3832  * Host Frame Counter Reset (FrmCntrRst)
3833  *
3834  * The application writes this bit to reset the (micro)frame number
3835  *
3836  * counter inside the core. When the (micro)frame counter is reset,
3837  *
3838  * the subsequent SOF sent out by the core has a (micro)frame
3839  *
3840  * number of 0.When application writes 1 to the bit, it might not
3841  *
3842  * be able to read back the value as it will get cleared by the core in a few clock
3843  * cycles.
3844  *
3845  * Field Enumeration Values:
3846  *
3847  * Enum | Value | Description
3848  * :-----------------------------------------|:------|:-------------------------
3849  * ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_NOTACT | 0x0 | No reset
3850  * ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_ACT | 0x1 | Host Frame Counter Reset
3851  *
3852  * Field Access Macros:
3853  *
3854  */
3855 /*
3856  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_FRMCNTRRST
3857  *
3858  * No reset
3859  */
3860 #define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_NOTACT 0x0
3861 /*
3862  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_FRMCNTRRST
3863  *
3864  * Host Frame Counter Reset
3865  */
3866 #define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_ACT 0x1
3867 
3868 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */
3869 #define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_LSB 2
3870 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */
3871 #define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_MSB 2
3872 /* The width in bits of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */
3873 #define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_WIDTH 1
3874 /* The mask used to set the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value. */
3875 #define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_SET_MSK 0x00000004
3876 /* The mask used to clear the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value. */
3877 #define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_CLR_MSK 0xfffffffb
3878 /* The reset value of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */
3879 #define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_RESET 0x0
3880 /* Extracts the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST field value from a register. */
3881 #define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_GET(value) (((value) & 0x00000004) >> 2)
3882 /* Produces a ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value suitable for setting the register. */
3883 #define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_SET(value) (((value) << 2) & 0x00000004)
3884 
3885 /*
3886  * Field : rxfflsh
3887  *
3888  * Mode:Host and Device
3889  *
3890  * RxFIFO Flush (RxFFlsh)
3891  *
3892  * The application can flush the entire RxFIFO using this bit, but
3893  *
3894  * must first ensure that the core is not in the middle of a
3895  *
3896  * transaction.
3897  *
3898  * The application must only write to this bit after checking that the
3899  *
3900  * core is neither reading from the RxFIFO nor writing to the
3901  *
3902  * RxFIFO.
3903  *
3904  * The application must wait until the bit is cleared before
3905  *
3906  * performing any other operations. This bit requires 8 clocks
3907  *
3908  * (slowest of PHY or AHB clock) to clear.
3909  *
3910  * Field Enumeration Values:
3911  *
3912  * Enum | Value | Description
3913  * :-------------------------------------|:------|:---------------------------
3914  * ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_INACT | 0x0 | no flush the entire RxFIFO
3915  * ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_ACT | 0x1 | flush the entire RxFIFO
3916  *
3917  * Field Access Macros:
3918  *
3919  */
3920 /*
3921  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_RXFFLSH
3922  *
3923  * no flush the entire RxFIFO
3924  */
3925 #define ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_INACT 0x0
3926 /*
3927  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_RXFFLSH
3928  *
3929  * flush the entire RxFIFO
3930  */
3931 #define ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_ACT 0x1
3932 
3933 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */
3934 #define ALT_USB_GLOB_GRSTCTL_RXFFLSH_LSB 4
3935 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */
3936 #define ALT_USB_GLOB_GRSTCTL_RXFFLSH_MSB 4
3937 /* The width in bits of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */
3938 #define ALT_USB_GLOB_GRSTCTL_RXFFLSH_WIDTH 1
3939 /* The mask used to set the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value. */
3940 #define ALT_USB_GLOB_GRSTCTL_RXFFLSH_SET_MSK 0x00000010
3941 /* The mask used to clear the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value. */
3942 #define ALT_USB_GLOB_GRSTCTL_RXFFLSH_CLR_MSK 0xffffffef
3943 /* The reset value of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */
3944 #define ALT_USB_GLOB_GRSTCTL_RXFFLSH_RESET 0x0
3945 /* Extracts the ALT_USB_GLOB_GRSTCTL_RXFFLSH field value from a register. */
3946 #define ALT_USB_GLOB_GRSTCTL_RXFFLSH_GET(value) (((value) & 0x00000010) >> 4)
3947 /* Produces a ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value suitable for setting the register. */
3948 #define ALT_USB_GLOB_GRSTCTL_RXFFLSH_SET(value) (((value) << 4) & 0x00000010)
3949 
3950 /*
3951  * Field : txfflsh
3952  *
3953  * Mode:Host and Device
3954  *
3955  * TxFIFO Flush (TxFFlsh)
3956  *
3957  * This bit selectively flushes a single or all transmit FIFOs, but
3958  *
3959  * cannot do so If the core is in the midst of a transaction.
3960  *
3961  * The application must write this bit only after checking that the
3962  *
3963  * core is neither writing to the TxFIFO nor reading from the
3964  *
3965  * TxFIFO. Verify using these registers:
3966  *
3967  * ReadNAK Effective Interrupt ensures the core is not
3968  *
3969  * reading from the FIFO
3970  *
3971  * WriteGRSTCTL.AHBIdle ensures the core is not writing
3972  *
3973  * anything to the FIFO.
3974  *
3975  * Flushing is normally recommended when FIFOs are
3976  *
3977  * reconfigured or when switching between Shared FIFO and
3978  *
3979  * Dedicated Transmit FIFO operation. FIFO flushing is also
3980  *
3981  * recommended during device endpoint disable.
3982  *
3983  * The application must wait until the core clears this bit before
3984  *
3985  * performing any operations. This bit takes eight clocks to clear,
3986  *
3987  * using the slower clock of phy_clk or hclk.
3988  *
3989  * Field Enumeration Values:
3990  *
3991  * Enum | Value | Description
3992  * :-------------------------------------|:------|:---------------------------------------------
3993  * ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_INACT | 0x0 | No Flush
3994  * ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_ACT | 0x1 | selectively flushes a single or all transmit
3995  * : | | FIFOs
3996  *
3997  * Field Access Macros:
3998  *
3999  */
4000 /*
4001  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFFLSH
4002  *
4003  * No Flush
4004  */
4005 #define ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_INACT 0x0
4006 /*
4007  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFFLSH
4008  *
4009  * selectively flushes a single or all transmit FIFOs
4010  */
4011 #define ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_ACT 0x1
4012 
4013 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */
4014 #define ALT_USB_GLOB_GRSTCTL_TXFFLSH_LSB 5
4015 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */
4016 #define ALT_USB_GLOB_GRSTCTL_TXFFLSH_MSB 5
4017 /* The width in bits of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */
4018 #define ALT_USB_GLOB_GRSTCTL_TXFFLSH_WIDTH 1
4019 /* The mask used to set the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value. */
4020 #define ALT_USB_GLOB_GRSTCTL_TXFFLSH_SET_MSK 0x00000020
4021 /* The mask used to clear the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value. */
4022 #define ALT_USB_GLOB_GRSTCTL_TXFFLSH_CLR_MSK 0xffffffdf
4023 /* The reset value of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */
4024 #define ALT_USB_GLOB_GRSTCTL_TXFFLSH_RESET 0x0
4025 /* Extracts the ALT_USB_GLOB_GRSTCTL_TXFFLSH field value from a register. */
4026 #define ALT_USB_GLOB_GRSTCTL_TXFFLSH_GET(value) (((value) & 0x00000020) >> 5)
4027 /* Produces a ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value suitable for setting the register. */
4028 #define ALT_USB_GLOB_GRSTCTL_TXFFLSH_SET(value) (((value) << 5) & 0x00000020)
4029 
4030 /*
4031  * Field : txfnum
4032  *
4033  * Mode:Host and Device
4034  *
4035  * TxFIFO Number (TxFNum)
4036  *
4037  * This is the FIFO number that must be flushed using the TxFIFO
4038  *
4039  * Flush bit. This field must not be changed until the core clears the
4040  *
4041  * TxFIFO Flush bit.
4042  *
4043  * 5'h0:
4044  *
4045  * * Non-periodic TxFIFO flush in Host mode
4046  *
4047  * * Non-periodic TxFIFO flush in device mode when in shared
4048  *
4049  * FIFO operation
4050  *
4051  * * Tx FIFO 0 flush in device mode when in dedicated FIFO
4052  *
4053  * mode
4054  *
4055  * 5'h1:
4056  *
4057  * * Periodic TxFIFO flush in Host mode
4058  *
4059  * * Periodic TxFIFO 1 flush in Device mode when in shared
4060  *
4061  * FIFO operation
4062  *
4063  * * TXFIFO 1 flush in device mode when in dedicated FIFO
4064  *
4065  * mode
4066  *
4067  * 5'h2:
4068  *
4069  * * Periodic TxFIFO 2 flush in Device mode when in shared
4070  *
4071  * FIFO operation
4072  *
4073  * * TXFIFO 2 flush in device mode when in dedicated FIFO
4074  *
4075  * mode
4076  *
4077  * ...
4078  *
4079  * 5'hF:
4080  *
4081  * * Periodic TxFIFO 15 flush in Device mode when in shared
4082  *
4083  * FIFO operation
4084  *
4085  * * TXFIFO 15 flush in device mode when in dedicated FIFO
4086  *
4087  * mode
4088  *
4089  * 5'h10: Flush all the transmit FIFOs in device or host mode.
4090  *
4091  * Field Enumeration Values:
4092  *
4093  * Enum | Value | Description
4094  * :------------------------------------|:------|:-------------------------------------------------
4095  * ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF0 | 0x0 | - Non-periodic TxFIFO flush in Host mode - Non-
4096  * : | | periodic TxFIFO flush in device mode when in
4097  * : | | shared FIFO operation
4098  * ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF1 | 0x1 | - Periodic TxFIFO flush in Host mode - Periodic
4099  * : | | TxFIFO 1 flush in Device mode when in sharedFIFO
4100  * : | | operation
4101  * ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF2 | 0x2 | - Periodic TxFIFO 2 flush in Device mode when in
4102  * : | | sharedFIFO operation- TXFIFO 2 flush in device
4103  * : | | mode when in dedicated FIFO mode
4104  * ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF15 | 0xf | - Periodic TxFIFO 15 flush in Device mode when
4105  * : | | in shared FIFO operation - TXFIFO 15 flush in
4106  * : | | device mode when in dedicated FIFO mode
4107  * ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF16 | 0x10 | Flush all the transmit FIFOs in device or host
4108  * : | | mode.
4109  *
4110  * Field Access Macros:
4111  *
4112  */
4113 /*
4114  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
4115  *
4116  * * Non-periodic TxFIFO flush in Host mode
4117  *
4118  * * Non-periodic TxFIFO flush in device mode when in shared FIFO operation
4119  */
4120 #define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF0 0x0
4121 /*
4122  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
4123  *
4124  * * Periodic TxFIFO flush in Host mode
4125  *
4126  * * Periodic TxFIFO 1 flush in Device mode when in sharedFIFO operation
4127  */
4128 #define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF1 0x1
4129 /*
4130  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
4131  *
4132  * * Periodic TxFIFO 2 flush in Device mode when in sharedFIFO operation- TXFIFO 2
4133  * flush in device mode when in dedicated FIFO mode
4134  */
4135 #define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF2 0x2
4136 /*
4137  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
4138  *
4139  * * Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation
4140  *
4141  * * TXFIFO 15 flush in device mode when in dedicated FIFO mode
4142  */
4143 #define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF15 0xf
4144 /*
4145  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
4146  *
4147  * Flush all the transmit FIFOs in device or host mode.
4148  */
4149 #define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF16 0x10
4150 
4151 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */
4152 #define ALT_USB_GLOB_GRSTCTL_TXFNUM_LSB 6
4153 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */
4154 #define ALT_USB_GLOB_GRSTCTL_TXFNUM_MSB 10
4155 /* The width in bits of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */
4156 #define ALT_USB_GLOB_GRSTCTL_TXFNUM_WIDTH 5
4157 /* The mask used to set the ALT_USB_GLOB_GRSTCTL_TXFNUM register field value. */
4158 #define ALT_USB_GLOB_GRSTCTL_TXFNUM_SET_MSK 0x000007c0
4159 /* The mask used to clear the ALT_USB_GLOB_GRSTCTL_TXFNUM register field value. */
4160 #define ALT_USB_GLOB_GRSTCTL_TXFNUM_CLR_MSK 0xfffff83f
4161 /* The reset value of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */
4162 #define ALT_USB_GLOB_GRSTCTL_TXFNUM_RESET 0x0
4163 /* Extracts the ALT_USB_GLOB_GRSTCTL_TXFNUM field value from a register. */
4164 #define ALT_USB_GLOB_GRSTCTL_TXFNUM_GET(value) (((value) & 0x000007c0) >> 6)
4165 /* Produces a ALT_USB_GLOB_GRSTCTL_TXFNUM register field value suitable for setting the register. */
4166 #define ALT_USB_GLOB_GRSTCTL_TXFNUM_SET(value) (((value) << 6) & 0x000007c0)
4167 
4168 /*
4169  * Field : dmareq
4170  *
4171  * Mode:Host and Device
4172  *
4173  * DMA Request Signal (DMAReq)
4174  *
4175  * Indicates that the DMA request is in progress. Used For debug.
4176  *
4177  * Field Enumeration Values:
4178  *
4179  * Enum | Value | Description
4180  * :------------------------------------|:------|:---------------------------
4181  * ALT_USB_GLOB_GRSTCTL_DMAREQ_E_INACT | 0x0 | No DMA request
4182  * ALT_USB_GLOB_GRSTCTL_DMAREQ_E_ACT | 0x1 | DMA request is in progress
4183  *
4184  * Field Access Macros:
4185  *
4186  */
4187 /*
4188  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_DMAREQ
4189  *
4190  * No DMA request
4191  */
4192 #define ALT_USB_GLOB_GRSTCTL_DMAREQ_E_INACT 0x0
4193 /*
4194  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_DMAREQ
4195  *
4196  * DMA request is in progress
4197  */
4198 #define ALT_USB_GLOB_GRSTCTL_DMAREQ_E_ACT 0x1
4199 
4200 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */
4201 #define ALT_USB_GLOB_GRSTCTL_DMAREQ_LSB 30
4202 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */
4203 #define ALT_USB_GLOB_GRSTCTL_DMAREQ_MSB 30
4204 /* The width in bits of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */
4205 #define ALT_USB_GLOB_GRSTCTL_DMAREQ_WIDTH 1
4206 /* The mask used to set the ALT_USB_GLOB_GRSTCTL_DMAREQ register field value. */
4207 #define ALT_USB_GLOB_GRSTCTL_DMAREQ_SET_MSK 0x40000000
4208 /* The mask used to clear the ALT_USB_GLOB_GRSTCTL_DMAREQ register field value. */
4209 #define ALT_USB_GLOB_GRSTCTL_DMAREQ_CLR_MSK 0xbfffffff
4210 /* The reset value of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */
4211 #define ALT_USB_GLOB_GRSTCTL_DMAREQ_RESET 0x0
4212 /* Extracts the ALT_USB_GLOB_GRSTCTL_DMAREQ field value from a register. */
4213 #define ALT_USB_GLOB_GRSTCTL_DMAREQ_GET(value) (((value) & 0x40000000) >> 30)
4214 /* Produces a ALT_USB_GLOB_GRSTCTL_DMAREQ register field value suitable for setting the register. */
4215 #define ALT_USB_GLOB_GRSTCTL_DMAREQ_SET(value) (((value) << 30) & 0x40000000)
4216 
4217 /*
4218  * Field : ahbidle
4219  *
4220  * Mode:Host and Device
4221  *
4222  * AHB Master Idle (AHBIdle)
4223  *
4224  * Indicates that the AHB Master State Machine is in the IDLE
4225  *
4226  * condition.
4227  *
4228  * Field Enumeration Values:
4229  *
4230  * Enum | Value | Description
4231  * :-------------------------------------|:------|:----------------
4232  * ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_INACT | 0x0 | Not Idle
4233  * ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_ACT | 0x1 | AHB Master Idle
4234  *
4235  * Field Access Macros:
4236  *
4237  */
4238 /*
4239  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_AHBIDLE
4240  *
4241  * Not Idle
4242  */
4243 #define ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_INACT 0x0
4244 /*
4245  * Enumerated value for register field ALT_USB_GLOB_GRSTCTL_AHBIDLE
4246  *
4247  * AHB Master Idle
4248  */
4249 #define ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_ACT 0x1
4250 
4251 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */
4252 #define ALT_USB_GLOB_GRSTCTL_AHBIDLE_LSB 31
4253 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */
4254 #define ALT_USB_GLOB_GRSTCTL_AHBIDLE_MSB 31
4255 /* The width in bits of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */
4256 #define ALT_USB_GLOB_GRSTCTL_AHBIDLE_WIDTH 1
4257 /* The mask used to set the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value. */
4258 #define ALT_USB_GLOB_GRSTCTL_AHBIDLE_SET_MSK 0x80000000
4259 /* The mask used to clear the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value. */
4260 #define ALT_USB_GLOB_GRSTCTL_AHBIDLE_CLR_MSK 0x7fffffff
4261 /* The reset value of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */
4262 #define ALT_USB_GLOB_GRSTCTL_AHBIDLE_RESET 0x1
4263 /* Extracts the ALT_USB_GLOB_GRSTCTL_AHBIDLE field value from a register. */
4264 #define ALT_USB_GLOB_GRSTCTL_AHBIDLE_GET(value) (((value) & 0x80000000) >> 31)
4265 /* Produces a ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value suitable for setting the register. */
4266 #define ALT_USB_GLOB_GRSTCTL_AHBIDLE_SET(value) (((value) << 31) & 0x80000000)
4267 
4268 #ifndef __ASSEMBLY__
4269 /*
4270  * WARNING: The C register and register group struct declarations are provided for
4271  * convenience and illustrative purposes. They should, however, be used with
4272  * caution as the C language standard provides no guarantees about the alignment or
4273  * atomicity of device memory accesses. The recommended practice for writing
4274  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4275  * alt_write_word() functions.
4276  *
4277  * The struct declaration for register ALT_USB_GLOB_GRSTCTL.
4278  */
4279 struct ALT_USB_GLOB_GRSTCTL_s
4280 {
4281  uint32_t csftrst : 1; /* ALT_USB_GLOB_GRSTCTL_CSFTRST */
4282  uint32_t piufssftrst : 1; /* ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST */
4283  uint32_t frmcntrrst : 1; /* ALT_USB_GLOB_GRSTCTL_FRMCNTRRST */
4284  uint32_t : 1; /* *UNDEFINED* */
4285  uint32_t rxfflsh : 1; /* ALT_USB_GLOB_GRSTCTL_RXFFLSH */
4286  uint32_t txfflsh : 1; /* ALT_USB_GLOB_GRSTCTL_TXFFLSH */
4287  uint32_t txfnum : 5; /* ALT_USB_GLOB_GRSTCTL_TXFNUM */
4288  uint32_t : 19; /* *UNDEFINED* */
4289  const uint32_t dmareq : 1; /* ALT_USB_GLOB_GRSTCTL_DMAREQ */
4290  const uint32_t ahbidle : 1; /* ALT_USB_GLOB_GRSTCTL_AHBIDLE */
4291 };
4292 
4293 /* The typedef declaration for register ALT_USB_GLOB_GRSTCTL. */
4294 typedef volatile struct ALT_USB_GLOB_GRSTCTL_s ALT_USB_GLOB_GRSTCTL_t;
4295 #endif /* __ASSEMBLY__ */
4296 
4297 /* The reset value of the ALT_USB_GLOB_GRSTCTL register. */
4298 #define ALT_USB_GLOB_GRSTCTL_RESET 0x80000000
4299 /* The byte offset of the ALT_USB_GLOB_GRSTCTL register from the beginning of the component. */
4300 #define ALT_USB_GLOB_GRSTCTL_OFST 0x10
4301 /* The address of the ALT_USB_GLOB_GRSTCTL register. */
4302 #define ALT_USB_GLOB_GRSTCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRSTCTL_OFST))
4303 
4304 /*
4305  * Register : gintsts
4306  *
4307  * Interrupt Register
4308  *
4309  * Register Layout
4310  *
4311  * Bits | Access | Reset | Description
4312  * :------|:-------|:------|:----------------------------------
4313  * [0] | R | 0x0 | ALT_USB_GLOB_GINTSTS_CURMOD
4314  * [1] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_MODMIS
4315  * [2] | R | 0x0 | ALT_USB_GLOB_GINTSTS_OTGINT
4316  * [3] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_SOF
4317  * [4] | R | 0x0 | ALT_USB_GLOB_GINTSTS_RXFLVL
4318  * [5] | R | 0x1 | ALT_USB_GLOB_GINTSTS_NPTXFEMP
4319  * [6] | R | 0x0 | ALT_USB_GLOB_GINTSTS_GINNAKEFF
4320  * [7] | R | 0x0 | ALT_USB_GLOB_GINTSTS_GOUTNAKEFF
4321  * [9:8] | ??? | 0x0 | *UNDEFINED*
4322  * [10] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_ERLYSUSP
4323  * [11] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_USBSUSP
4324  * [12] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_USBRST
4325  * [13] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_ENUMDONE
4326  * [14] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_ISOOUTDROP
4327  * [15] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_EOPF
4328  * [16] | ??? | 0x0 | *UNDEFINED*
4329  * [17] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_EPMIS
4330  * [18] | R | 0x0 | ALT_USB_GLOB_GINTSTS_IEPINT
4331  * [19] | R | 0x0 | ALT_USB_GLOB_GINTSTS_OEPINT
4332  * [20] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_INCOMPISOIN
4333  * [21] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_INCOMPLP
4334  * [22] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_FETSUSP
4335  * [23] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_RSTDET
4336  * [24] | R | 0x0 | ALT_USB_GLOB_GINTSTS_PRTINT
4337  * [25] | R | 0x0 | ALT_USB_GLOB_GINTSTS_HCHINT
4338  * [26] | R | 0x1 | ALT_USB_GLOB_GINTSTS_PTXFEMP
4339  * [27] | ??? | 0x0 | *UNDEFINED*
4340  * [28] | RW | 0x1 | ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG
4341  * [29] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_DISCONNINT
4342  * [30] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_SESSREQINT
4343  * [31] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_WKUPINT
4344  *
4345  */
4346 /*
4347  * Field : curmod
4348  *
4349  * Mode: Host and Device
4350  *
4351  * Current Mode of Operation (CurMod)
4352  *
4353  * Indicates the current mode.
4354  *
4355  * 1'b0: Device mode
4356  *
4357  * 1'b1: Host mode
4358  *
4359  * Field Enumeration Values:
4360  *
4361  * Enum | Value | Description
4362  * :-------------------------------------|:------|:------------
4363  * ALT_USB_GLOB_GINTSTS_CURMOD_E_DEVICE | 0x0 | Device mode
4364  * ALT_USB_GLOB_GINTSTS_CURMOD_E_HOST | 0x1 | Host mode
4365  *
4366  * Field Access Macros:
4367  *
4368  */
4369 /*
4370  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_CURMOD
4371  *
4372  * Device mode
4373  */
4374 #define ALT_USB_GLOB_GINTSTS_CURMOD_E_DEVICE 0x0
4375 /*
4376  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_CURMOD
4377  *
4378  * Host mode
4379  */
4380 #define ALT_USB_GLOB_GINTSTS_CURMOD_E_HOST 0x1
4381 
4382 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */
4383 #define ALT_USB_GLOB_GINTSTS_CURMOD_LSB 0
4384 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */
4385 #define ALT_USB_GLOB_GINTSTS_CURMOD_MSB 0
4386 /* The width in bits of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */
4387 #define ALT_USB_GLOB_GINTSTS_CURMOD_WIDTH 1
4388 /* The mask used to set the ALT_USB_GLOB_GINTSTS_CURMOD register field value. */
4389 #define ALT_USB_GLOB_GINTSTS_CURMOD_SET_MSK 0x00000001
4390 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_CURMOD register field value. */
4391 #define ALT_USB_GLOB_GINTSTS_CURMOD_CLR_MSK 0xfffffffe
4392 /* The reset value of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */
4393 #define ALT_USB_GLOB_GINTSTS_CURMOD_RESET 0x0
4394 /* Extracts the ALT_USB_GLOB_GINTSTS_CURMOD field value from a register. */
4395 #define ALT_USB_GLOB_GINTSTS_CURMOD_GET(value) (((value) & 0x00000001) >> 0)
4396 /* Produces a ALT_USB_GLOB_GINTSTS_CURMOD register field value suitable for setting the register. */
4397 #define ALT_USB_GLOB_GINTSTS_CURMOD_SET(value) (((value) << 0) & 0x00000001)
4398 
4399 /*
4400  * Field : modemis
4401  *
4402  * Mode: Host and Device
4403  *
4404  * Mode Mismatch Interrupt (ModeMis)
4405  *
4406  * The core sets this bit when the application is trying to access:
4407  *
4408  * A Host mode register, when the core is operating in Device
4409  *
4410  * mode
4411  *
4412  * A Device mode register, when the core is operating in Host
4413  *
4414  * mode
4415  *
4416  * The register access is completed on the AHB with an OKAY
4417  *
4418  * response, but is ignored by the core internally and does not
4419  *
4420  * affect the operation of the core.This bit can be set only by the core and the
4421  * application should write 1 to clear
4422  *
4423  * it
4424  *
4425  * Field Enumeration Values:
4426  *
4427  * Enum | Value | Description
4428  * :------------------------------------|:------|:---------------------------
4429  * ALT_USB_GLOB_GINTSTS_MODMIS_E_INACT | 0x0 | No Mode Mismatch Interrupt
4430  * ALT_USB_GLOB_GINTSTS_MODMIS_E_ACT | 0x1 | Mode Mismatch Interrupt
4431  *
4432  * Field Access Macros:
4433  *
4434  */
4435 /*
4436  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_MODMIS
4437  *
4438  * No Mode Mismatch Interrupt
4439  */
4440 #define ALT_USB_GLOB_GINTSTS_MODMIS_E_INACT 0x0
4441 /*
4442  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_MODMIS
4443  *
4444  * Mode Mismatch Interrupt
4445  */
4446 #define ALT_USB_GLOB_GINTSTS_MODMIS_E_ACT 0x1
4447 
4448 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */
4449 #define ALT_USB_GLOB_GINTSTS_MODMIS_LSB 1
4450 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */
4451 #define ALT_USB_GLOB_GINTSTS_MODMIS_MSB 1
4452 /* The width in bits of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */
4453 #define ALT_USB_GLOB_GINTSTS_MODMIS_WIDTH 1
4454 /* The mask used to set the ALT_USB_GLOB_GINTSTS_MODMIS register field value. */
4455 #define ALT_USB_GLOB_GINTSTS_MODMIS_SET_MSK 0x00000002
4456 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_MODMIS register field value. */
4457 #define ALT_USB_GLOB_GINTSTS_MODMIS_CLR_MSK 0xfffffffd
4458 /* The reset value of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */
4459 #define ALT_USB_GLOB_GINTSTS_MODMIS_RESET 0x0
4460 /* Extracts the ALT_USB_GLOB_GINTSTS_MODMIS field value from a register. */
4461 #define ALT_USB_GLOB_GINTSTS_MODMIS_GET(value) (((value) & 0x00000002) >> 1)
4462 /* Produces a ALT_USB_GLOB_GINTSTS_MODMIS register field value suitable for setting the register. */
4463 #define ALT_USB_GLOB_GINTSTS_MODMIS_SET(value) (((value) << 1) & 0x00000002)
4464 
4465 /*
4466  * Field : otgint
4467  *
4468  * Mode: Host and Device
4469  *
4470  * OTG Interrupt (OTGInt)
4471  *
4472  * The core sets this bit to indicate an OTG protocol event. The
4473  *
4474  * application must read the OTG Interrupt Status (GOTGINT)
4475  *
4476  * register to determine the exact event that caused this interrupt.
4477  *
4478  * The application must clear the appropriate status bit in the
4479  *
4480  * GOTGINT register to clear this bit.
4481  *
4482  * Field Enumeration Values:
4483  *
4484  * Enum | Value | Description
4485  * :------------------------------------|:------|:--------------
4486  * ALT_USB_GLOB_GINTSTS_OTGINT_E_INACT | 0x0 | No Interrupt
4487  * ALT_USB_GLOB_GINTSTS_OTGINT_E_ACT | 0x1 | OTG Interrupt
4488  *
4489  * Field Access Macros:
4490  *
4491  */
4492 /*
4493  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_OTGINT
4494  *
4495  * No Interrupt
4496  */
4497 #define ALT_USB_GLOB_GINTSTS_OTGINT_E_INACT 0x0
4498 /*
4499  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_OTGINT
4500  *
4501  * OTG Interrupt
4502  */
4503 #define ALT_USB_GLOB_GINTSTS_OTGINT_E_ACT 0x1
4504 
4505 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */
4506 #define ALT_USB_GLOB_GINTSTS_OTGINT_LSB 2
4507 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */
4508 #define ALT_USB_GLOB_GINTSTS_OTGINT_MSB 2
4509 /* The width in bits of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */
4510 #define ALT_USB_GLOB_GINTSTS_OTGINT_WIDTH 1
4511 /* The mask used to set the ALT_USB_GLOB_GINTSTS_OTGINT register field value. */
4512 #define ALT_USB_GLOB_GINTSTS_OTGINT_SET_MSK 0x00000004
4513 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_OTGINT register field value. */
4514 #define ALT_USB_GLOB_GINTSTS_OTGINT_CLR_MSK 0xfffffffb
4515 /* The reset value of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */
4516 #define ALT_USB_GLOB_GINTSTS_OTGINT_RESET 0x0
4517 /* Extracts the ALT_USB_GLOB_GINTSTS_OTGINT field value from a register. */
4518 #define ALT_USB_GLOB_GINTSTS_OTGINT_GET(value) (((value) & 0x00000004) >> 2)
4519 /* Produces a ALT_USB_GLOB_GINTSTS_OTGINT register field value suitable for setting the register. */
4520 #define ALT_USB_GLOB_GINTSTS_OTGINT_SET(value) (((value) << 2) & 0x00000004)
4521 
4522 /*
4523  * Field : sof
4524  *
4525  * Mode: Host and Device
4526  *
4527  * Start of (micro)Frame (Sof)
4528  *
4529  * In Host mode, the core sets this bit to indicate that an SOF (FS),
4530  *
4531  * micro-SOF (HS), or Keep-Alive (LS) is transmitted on the USB.
4532  *
4533  * The application must write a 1 to this bit to clear the interrupt.
4534  *
4535  * In Device mode, in the core sets this bit to indicate that an SOF
4536  *
4537  * token has been received on the USB. The application can read
4538  *
4539  * the Device Status register to get the current (micro)Frame
4540  *
4541  * number. This interrupt is seen only when the core is operating at
4542  *
4543  * either HS or FS.
4544  *
4545  * Note: This register may return 1'b1 if read immediately after power on
4546  *
4547  * reset. If the register bit reads 1'b1 immediately after power on reset it does
4548  *
4549  * not indicate that an SOF has been sent (in case of host mode) or SOF has
4550  *
4551  * been received (in case of device mode). The read value of this interrupt is
4552  *
4553  * valid only after a valid connection between host and device is established. If
4554  *
4555  * the bit is set after power on reset the application can clear the bit.
4556  *
4557  * Field Enumeration Values:
4558  *
4559  * Enum | Value | Description
4560  * :----------------------------------|:------|:---------------
4561  * ALT_USB_GLOB_GINTSTS_SOF_E_INTACT | 0x0 | No sof
4562  * ALT_USB_GLOB_GINTSTS_SOF_E_ACT | 0x1 | Start of Frame
4563  *
4564  * Field Access Macros:
4565  *
4566  */
4567 /*
4568  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_SOF
4569  *
4570  * No sof
4571  */
4572 #define ALT_USB_GLOB_GINTSTS_SOF_E_INTACT 0x0
4573 /*
4574  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_SOF
4575  *
4576  * Start of Frame
4577  */
4578 #define ALT_USB_GLOB_GINTSTS_SOF_E_ACT 0x1
4579 
4580 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_SOF register field. */
4581 #define ALT_USB_GLOB_GINTSTS_SOF_LSB 3
4582 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_SOF register field. */
4583 #define ALT_USB_GLOB_GINTSTS_SOF_MSB 3
4584 /* The width in bits of the ALT_USB_GLOB_GINTSTS_SOF register field. */
4585 #define ALT_USB_GLOB_GINTSTS_SOF_WIDTH 1
4586 /* The mask used to set the ALT_USB_GLOB_GINTSTS_SOF register field value. */
4587 #define ALT_USB_GLOB_GINTSTS_SOF_SET_MSK 0x00000008
4588 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_SOF register field value. */
4589 #define ALT_USB_GLOB_GINTSTS_SOF_CLR_MSK 0xfffffff7
4590 /* The reset value of the ALT_USB_GLOB_GINTSTS_SOF register field. */
4591 #define ALT_USB_GLOB_GINTSTS_SOF_RESET 0x0
4592 /* Extracts the ALT_USB_GLOB_GINTSTS_SOF field value from a register. */
4593 #define ALT_USB_GLOB_GINTSTS_SOF_GET(value) (((value) & 0x00000008) >> 3)
4594 /* Produces a ALT_USB_GLOB_GINTSTS_SOF register field value suitable for setting the register. */
4595 #define ALT_USB_GLOB_GINTSTS_SOF_SET(value) (((value) << 3) & 0x00000008)
4596 
4597 /*
4598  * Field : rxflvl
4599  *
4600  * Mode: Host and Device
4601  *
4602  * RxFIFO Non-Empty (RxFLvl)
4603  *
4604  * Indicates that there is at least one packet pending to be read
4605  *
4606  * from the RxFIFO.
4607  *
4608  * Field Enumeration Values:
4609  *
4610  * Enum | Value | Description
4611  * :------------------------------------|:------|:------------------
4612  * ALT_USB_GLOB_GINTSTS_RXFLVL_E_INACT | 0x0 | Not Active
4613  * ALT_USB_GLOB_GINTSTS_RXFLVL_E_ACT | 0x1 | Rx Fifo Non Empty
4614  *
4615  * Field Access Macros:
4616  *
4617  */
4618 /*
4619  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_RXFLVL
4620  *
4621  * Not Active
4622  */
4623 #define ALT_USB_GLOB_GINTSTS_RXFLVL_E_INACT 0x0
4624 /*
4625  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_RXFLVL
4626  *
4627  * Rx Fifo Non Empty
4628  */
4629 #define ALT_USB_GLOB_GINTSTS_RXFLVL_E_ACT 0x1
4630 
4631 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */
4632 #define ALT_USB_GLOB_GINTSTS_RXFLVL_LSB 4
4633 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */
4634 #define ALT_USB_GLOB_GINTSTS_RXFLVL_MSB 4
4635 /* The width in bits of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */
4636 #define ALT_USB_GLOB_GINTSTS_RXFLVL_WIDTH 1
4637 /* The mask used to set the ALT_USB_GLOB_GINTSTS_RXFLVL register field value. */
4638 #define ALT_USB_GLOB_GINTSTS_RXFLVL_SET_MSK 0x00000010
4639 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_RXFLVL register field value. */
4640 #define ALT_USB_GLOB_GINTSTS_RXFLVL_CLR_MSK 0xffffffef
4641 /* The reset value of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */
4642 #define ALT_USB_GLOB_GINTSTS_RXFLVL_RESET 0x0
4643 /* Extracts the ALT_USB_GLOB_GINTSTS_RXFLVL field value from a register. */
4644 #define ALT_USB_GLOB_GINTSTS_RXFLVL_GET(value) (((value) & 0x00000010) >> 4)
4645 /* Produces a ALT_USB_GLOB_GINTSTS_RXFLVL register field value suitable for setting the register. */
4646 #define ALT_USB_GLOB_GINTSTS_RXFLVL_SET(value) (((value) << 4) & 0x00000010)
4647 
4648 /*
4649  * Field : nptxfemp
4650  *
4651  * Mode: Host and Device
4652  *
4653  * Non-periodic TxFIFO Empty (NPTxFEmp)
4654  *
4655  * This interrupt is asserted when the Non-periodic TxFIFO is
4656  *
4657  * either half or completely empty, and there is space For at least
4658  *
4659  * one Entry to be written to the Non-periodic Transmit Request
4660  *
4661  * Queue. The half or completely empty status is determined by
4662  *
4663  * the Non-periodic TxFIFO Empty Level bit in the Core AHB
4664  *
4665  * Configuration register (GAHBCFG.NPTxFEmpLvl).
4666  *
4667  * Field Access Macros:
4668  *
4669  */
4670 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_NPTXFEMP register field. */
4671 #define ALT_USB_GLOB_GINTSTS_NPTXFEMP_LSB 5
4672 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_NPTXFEMP register field. */
4673 #define ALT_USB_GLOB_GINTSTS_NPTXFEMP_MSB 5
4674 /* The width in bits of the ALT_USB_GLOB_GINTSTS_NPTXFEMP register field. */
4675 #define ALT_USB_GLOB_GINTSTS_NPTXFEMP_WIDTH 1
4676 /* The mask used to set the ALT_USB_GLOB_GINTSTS_NPTXFEMP register field value. */
4677 #define ALT_USB_GLOB_GINTSTS_NPTXFEMP_SET_MSK 0x00000020
4678 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_NPTXFEMP register field value. */
4679 #define ALT_USB_GLOB_GINTSTS_NPTXFEMP_CLR_MSK 0xffffffdf
4680 /* The reset value of the ALT_USB_GLOB_GINTSTS_NPTXFEMP register field. */
4681 #define ALT_USB_GLOB_GINTSTS_NPTXFEMP_RESET 0x1
4682 /* Extracts the ALT_USB_GLOB_GINTSTS_NPTXFEMP field value from a register. */
4683 #define ALT_USB_GLOB_GINTSTS_NPTXFEMP_GET(value) (((value) & 0x00000020) >> 5)
4684 /* Produces a ALT_USB_GLOB_GINTSTS_NPTXFEMP register field value suitable for setting the register. */
4685 #define ALT_USB_GLOB_GINTSTS_NPTXFEMP_SET(value) (((value) << 5) & 0x00000020)
4686 
4687 /*
4688  * Field : ginnakeff
4689  *
4690  * Mode: Device only
4691  *
4692  * Global IN Non-periodic NAK Effective (GINNakEff)
4693  *
4694  * Indicates that the Set Global Non-periodic IN NAK bit in the
4695  *
4696  * Device Control register (DCTL.SGNPInNak), Set by the
4697  *
4698  * application, has taken effect in the core. That is, the core has
4699  *
4700  * sampled the Global IN NAK bit Set by the application. This bit
4701  *
4702  * can be cleared by clearing the Clear Global Non-periodic IN
4703  *
4704  * NAK bit in the Device Control register (DCTL.CGNPInNak).
4705  *
4706  * This interrupt does not necessarily mean that a NAK handshake
4707  *
4708  * is sent out on the USB. The STALL bit takes precedence over
4709  *
4710  * the NAK bit.
4711  *
4712  * Field Enumeration Values:
4713  *
4714  * Enum | Value | Description
4715  * :---------------------------------------|:------|:----------------------------------
4716  * ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_INACT | 0x0 | Not active
4717  * ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_ACT | 0x1 | Set Global Non-periodic IN NAK bi
4718  *
4719  * Field Access Macros:
4720  *
4721  */
4722 /*
4723  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_GINNAKEFF
4724  *
4725  * Not active
4726  */
4727 #define ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_INACT 0x0
4728 /*
4729  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_GINNAKEFF
4730  *
4731  * Set Global Non-periodic IN NAK bi
4732  */
4733 #define ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_ACT 0x1
4734 
4735 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */
4736 #define ALT_USB_GLOB_GINTSTS_GINNAKEFF_LSB 6
4737 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */
4738 #define ALT_USB_GLOB_GINTSTS_GINNAKEFF_MSB 6
4739 /* The width in bits of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */
4740 #define ALT_USB_GLOB_GINTSTS_GINNAKEFF_WIDTH 1
4741 /* The mask used to set the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field value. */
4742 #define ALT_USB_GLOB_GINTSTS_GINNAKEFF_SET_MSK 0x00000040
4743 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field value. */
4744 #define ALT_USB_GLOB_GINTSTS_GINNAKEFF_CLR_MSK 0xffffffbf
4745 /* The reset value of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */
4746 #define ALT_USB_GLOB_GINTSTS_GINNAKEFF_RESET 0x0
4747 /* Extracts the ALT_USB_GLOB_GINTSTS_GINNAKEFF field value from a register. */
4748 #define ALT_USB_GLOB_GINTSTS_GINNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
4749 /* Produces a ALT_USB_GLOB_GINTSTS_GINNAKEFF register field value suitable for setting the register. */
4750 #define ALT_USB_GLOB_GINTSTS_GINNAKEFF_SET(value) (((value) << 6) & 0x00000040)
4751 
4752 /*
4753  * Field : goutnakeff
4754  *
4755  * Mode: Device only
4756  *
4757  * Global OUT NAK Effective (GOUTNakEff)
4758  *
4759  * Indicates that the Set Global OUT NAK bit in the Device Control
4760  *
4761  * register (DCTL.SGOUTNak), Set by the application, has taken
4762  *
4763  * effect in the core. This bit can be cleared by writing the Clear
4764  *
4765  * Global OUT NAK bit in the Device Control register
4766  *
4767  * (DCTL.CGOUTNak).
4768  *
4769  * Field Enumeration Values:
4770  *
4771  * Enum | Value | Description
4772  * :----------------------------------------|:------|:-------------------------
4773  * ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_INACT | 0x0 | No Active
4774  * ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_ACT | 0x1 | Global OUT NAK Effective
4775  *
4776  * Field Access Macros:
4777  *
4778  */
4779 /*
4780  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_GOUTNAKEFF
4781  *
4782  * No Active
4783  */
4784 #define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_INACT 0x0
4785 /*
4786  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_GOUTNAKEFF
4787  *
4788  * Global OUT NAK Effective
4789  */
4790 #define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_ACT 0x1
4791 
4792 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */
4793 #define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_LSB 7
4794 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */
4795 #define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_MSB 7
4796 /* The width in bits of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */
4797 #define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_WIDTH 1
4798 /* The mask used to set the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field value. */
4799 #define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_SET_MSK 0x00000080
4800 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field value. */
4801 #define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_CLR_MSK 0xffffff7f
4802 /* The reset value of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */
4803 #define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_RESET 0x0
4804 /* Extracts the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF field value from a register. */
4805 #define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_GET(value) (((value) & 0x00000080) >> 7)
4806 /* Produces a ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field value suitable for setting the register. */
4807 #define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_SET(value) (((value) << 7) & 0x00000080)
4808 
4809 /*
4810  * Field : erlysusp
4811  *
4812  * Mode: Device only
4813  *
4814  * Early Suspend (ErlySusp)
4815  *
4816  * The core sets this bit to indicate that an Idle state has been
4817  *
4818  * detected on the USB For 3 ms.
4819  *
4820  * Field Enumeration Values:
4821  *
4822  * Enum | Value | Description
4823  * :--------------------------------------|:------|:--------------------
4824  * ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_INACT | 0x0 | No Idle
4825  * ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_ACT | 0x1 | Idle state detecetd
4826  *
4827  * Field Access Macros:
4828  *
4829  */
4830 /*
4831  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ERLYSUSP
4832  *
4833  * No Idle
4834  */
4835 #define ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_INACT 0x0
4836 /*
4837  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ERLYSUSP
4838  *
4839  * Idle state detecetd
4840  */
4841 #define ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_ACT 0x1
4842 
4843 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */
4844 #define ALT_USB_GLOB_GINTSTS_ERLYSUSP_LSB 10
4845 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */
4846 #define ALT_USB_GLOB_GINTSTS_ERLYSUSP_MSB 10
4847 /* The width in bits of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */
4848 #define ALT_USB_GLOB_GINTSTS_ERLYSUSP_WIDTH 1
4849 /* The mask used to set the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field value. */
4850 #define ALT_USB_GLOB_GINTSTS_ERLYSUSP_SET_MSK 0x00000400
4851 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field value. */
4852 #define ALT_USB_GLOB_GINTSTS_ERLYSUSP_CLR_MSK 0xfffffbff
4853 /* The reset value of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */
4854 #define ALT_USB_GLOB_GINTSTS_ERLYSUSP_RESET 0x0
4855 /* Extracts the ALT_USB_GLOB_GINTSTS_ERLYSUSP field value from a register. */
4856 #define ALT_USB_GLOB_GINTSTS_ERLYSUSP_GET(value) (((value) & 0x00000400) >> 10)
4857 /* Produces a ALT_USB_GLOB_GINTSTS_ERLYSUSP register field value suitable for setting the register. */
4858 #define ALT_USB_GLOB_GINTSTS_ERLYSUSP_SET(value) (((value) << 10) & 0x00000400)
4859 
4860 /*
4861  * Field : usbsusp
4862  *
4863  * Mode: Device only
4864  *
4865  * USB Suspend (USBSusp)
4866  *
4867  * The core sets this bit to indicate that a suspend was detected on
4868  *
4869  * the USB. The core enters the Suspended state when there is no
4870  *
4871  * activity on the linestate signal For an extended period of
4872  *
4873  * time.
4874  *
4875  * Field Enumeration Values:
4876  *
4877  * Enum | Value | Description
4878  * :-------------------------------------|:------|:------------
4879  * ALT_USB_GLOB_GINTSTS_USBSUSP_E_INACT | 0x0 | Not Active
4880  * ALT_USB_GLOB_GINTSTS_USBSUSP_E_ACT | 0x1 | USB Suspend
4881  *
4882  * Field Access Macros:
4883  *
4884  */
4885 /*
4886  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBSUSP
4887  *
4888  * Not Active
4889  */
4890 #define ALT_USB_GLOB_GINTSTS_USBSUSP_E_INACT 0x0
4891 /*
4892  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBSUSP
4893  *
4894  * USB Suspend
4895  */
4896 #define ALT_USB_GLOB_GINTSTS_USBSUSP_E_ACT 0x1
4897 
4898 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */
4899 #define ALT_USB_GLOB_GINTSTS_USBSUSP_LSB 11
4900 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */
4901 #define ALT_USB_GLOB_GINTSTS_USBSUSP_MSB 11
4902 /* The width in bits of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */
4903 #define ALT_USB_GLOB_GINTSTS_USBSUSP_WIDTH 1
4904 /* The mask used to set the ALT_USB_GLOB_GINTSTS_USBSUSP register field value. */
4905 #define ALT_USB_GLOB_GINTSTS_USBSUSP_SET_MSK 0x00000800
4906 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_USBSUSP register field value. */
4907 #define ALT_USB_GLOB_GINTSTS_USBSUSP_CLR_MSK 0xfffff7ff
4908 /* The reset value of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */
4909 #define ALT_USB_GLOB_GINTSTS_USBSUSP_RESET 0x0
4910 /* Extracts the ALT_USB_GLOB_GINTSTS_USBSUSP field value from a register. */
4911 #define ALT_USB_GLOB_GINTSTS_USBSUSP_GET(value) (((value) & 0x00000800) >> 11)
4912 /* Produces a ALT_USB_GLOB_GINTSTS_USBSUSP register field value suitable for setting the register. */
4913 #define ALT_USB_GLOB_GINTSTS_USBSUSP_SET(value) (((value) << 11) & 0x00000800)
4914 
4915 /*
4916  * Field : usbrst
4917  *
4918  * Mode: Device only
4919  *
4920  * USB Reset (USBRst)
4921  *
4922  * The core sets this bit to indicate that a reset is detected on the
4923  *
4924  * USB.
4925  *
4926  * Field Enumeration Values:
4927  *
4928  * Enum | Value | Description
4929  * :------------------------------------|:------|:------------
4930  * ALT_USB_GLOB_GINTSTS_USBRST_E_INACT | 0x0 | Not active
4931  * ALT_USB_GLOB_GINTSTS_USBRST_E_ACT | 0x1 | USB Reset
4932  *
4933  * Field Access Macros:
4934  *
4935  */
4936 /*
4937  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBRST
4938  *
4939  * Not active
4940  */
4941 #define ALT_USB_GLOB_GINTSTS_USBRST_E_INACT 0x0
4942 /*
4943  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBRST
4944  *
4945  * USB Reset
4946  */
4947 #define ALT_USB_GLOB_GINTSTS_USBRST_E_ACT 0x1
4948 
4949 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_USBRST register field. */
4950 #define ALT_USB_GLOB_GINTSTS_USBRST_LSB 12
4951 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_USBRST register field. */
4952 #define ALT_USB_GLOB_GINTSTS_USBRST_MSB 12
4953 /* The width in bits of the ALT_USB_GLOB_GINTSTS_USBRST register field. */
4954 #define ALT_USB_GLOB_GINTSTS_USBRST_WIDTH 1
4955 /* The mask used to set the ALT_USB_GLOB_GINTSTS_USBRST register field value. */
4956 #define ALT_USB_GLOB_GINTSTS_USBRST_SET_MSK 0x00001000
4957 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_USBRST register field value. */
4958 #define ALT_USB_GLOB_GINTSTS_USBRST_CLR_MSK 0xffffefff
4959 /* The reset value of the ALT_USB_GLOB_GINTSTS_USBRST register field. */
4960 #define ALT_USB_GLOB_GINTSTS_USBRST_RESET 0x0
4961 /* Extracts the ALT_USB_GLOB_GINTSTS_USBRST field value from a register. */
4962 #define ALT_USB_GLOB_GINTSTS_USBRST_GET(value) (((value) & 0x00001000) >> 12)
4963 /* Produces a ALT_USB_GLOB_GINTSTS_USBRST register field value suitable for setting the register. */
4964 #define ALT_USB_GLOB_GINTSTS_USBRST_SET(value) (((value) << 12) & 0x00001000)
4965 
4966 /*
4967  * Field : enumdone
4968  *
4969  * Mode: Device only
4970  *
4971  * Enumeration Done (EnumDone)
4972  *
4973  * The core sets this bit to indicate that speed enumeration is
4974  *
4975  * complete. The application must read the Device Status (DSTS)
4976  *
4977  * register to obtain the enumerated speed.
4978  *
4979  * Field Enumeration Values:
4980  *
4981  * Enum | Value | Description
4982  * :--------------------------------------|:------|:-----------------
4983  * ALT_USB_GLOB_GINTSTS_ENUMDONE_E_INACT | 0x0 | Not active
4984  * ALT_USB_GLOB_GINTSTS_ENUMDONE_E_ACT | 0x1 | Enumeration Done
4985  *
4986  * Field Access Macros:
4987  *
4988  */
4989 /*
4990  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ENUMDONE
4991  *
4992  * Not active
4993  */
4994 #define ALT_USB_GLOB_GINTSTS_ENUMDONE_E_INACT 0x0
4995 /*
4996  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ENUMDONE
4997  *
4998  * Enumeration Done
4999  */
5000 #define ALT_USB_GLOB_GINTSTS_ENUMDONE_E_ACT 0x1
5001 
5002 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */
5003 #define ALT_USB_GLOB_GINTSTS_ENUMDONE_LSB 13
5004 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */
5005 #define ALT_USB_GLOB_GINTSTS_ENUMDONE_MSB 13
5006 /* The width in bits of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */
5007 #define ALT_USB_GLOB_GINTSTS_ENUMDONE_WIDTH 1
5008 /* The mask used to set the ALT_USB_GLOB_GINTSTS_ENUMDONE register field value. */
5009 #define ALT_USB_GLOB_GINTSTS_ENUMDONE_SET_MSK 0x00002000
5010 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_ENUMDONE register field value. */
5011 #define ALT_USB_GLOB_GINTSTS_ENUMDONE_CLR_MSK 0xffffdfff
5012 /* The reset value of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */
5013 #define ALT_USB_GLOB_GINTSTS_ENUMDONE_RESET 0x0
5014 /* Extracts the ALT_USB_GLOB_GINTSTS_ENUMDONE field value from a register. */
5015 #define ALT_USB_GLOB_GINTSTS_ENUMDONE_GET(value) (((value) & 0x00002000) >> 13)
5016 /* Produces a ALT_USB_GLOB_GINTSTS_ENUMDONE register field value suitable for setting the register. */
5017 #define ALT_USB_GLOB_GINTSTS_ENUMDONE_SET(value) (((value) << 13) & 0x00002000)
5018 
5019 /*
5020  * Field : isooutdrop
5021  *
5022  * Mode: Device only
5023  *
5024  * Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
5025  *
5026  * The core sets this bit when it fails to write an isochronous OUT
5027  *
5028  * packet into the RxFIFO because the RxFIFO does not have
5029  *
5030  * enough space to accommodate a maximum packet size packet
5031  *
5032  * for the isochronous OUT endpoint.
5033  *
5034  * Field Enumeration Values:
5035  *
5036  * Enum | Value | Description
5037  * :----------------------------------------|:------|:----------------------------------------
5038  * ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_INACT | 0x0 | Not active
5039  * ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_ACT | 0x1 | Isochronous OUT Packet Dropped Interrup
5040  *
5041  * Field Access Macros:
5042  *
5043  */
5044 /*
5045  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ISOOUTDROP
5046  *
5047  * Not active
5048  */
5049 #define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_INACT 0x0
5050 /*
5051  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_ISOOUTDROP
5052  *
5053  * Isochronous OUT Packet Dropped Interrup
5054  */
5055 #define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_ACT 0x1
5056 
5057 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */
5058 #define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_LSB 14
5059 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */
5060 #define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_MSB 14
5061 /* The width in bits of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */
5062 #define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_WIDTH 1
5063 /* The mask used to set the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field value. */
5064 #define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_SET_MSK 0x00004000
5065 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field value. */
5066 #define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_CLR_MSK 0xffffbfff
5067 /* The reset value of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */
5068 #define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_RESET 0x0
5069 /* Extracts the ALT_USB_GLOB_GINTSTS_ISOOUTDROP field value from a register. */
5070 #define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_GET(value) (((value) & 0x00004000) >> 14)
5071 /* Produces a ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field value suitable for setting the register. */
5072 #define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_SET(value) (((value) << 14) & 0x00004000)
5073 
5074 /*
5075  * Field : eopf
5076  *
5077  * Mode: Device only
5078  *
5079  * End of Periodic Frame Interrupt (EOPF)
5080  *
5081  * Indicates that the period specified in the Periodic Frame Interval
5082  *
5083  * field of the Device Configuration register (DCFG.PerFrInt) has
5084  *
5085  * been reached in the current microframe.
5086  *
5087  * Field Access Macros:
5088  *
5089  */
5090 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_EOPF register field. */
5091 #define ALT_USB_GLOB_GINTSTS_EOPF_LSB 15
5092 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_EOPF register field. */
5093 #define ALT_USB_GLOB_GINTSTS_EOPF_MSB 15
5094 /* The width in bits of the ALT_USB_GLOB_GINTSTS_EOPF register field. */
5095 #define ALT_USB_GLOB_GINTSTS_EOPF_WIDTH 1
5096 /* The mask used to set the ALT_USB_GLOB_GINTSTS_EOPF register field value. */
5097 #define ALT_USB_GLOB_GINTSTS_EOPF_SET_MSK 0x00008000
5098 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_EOPF register field value. */
5099 #define ALT_USB_GLOB_GINTSTS_EOPF_CLR_MSK 0xffff7fff
5100 /* The reset value of the ALT_USB_GLOB_GINTSTS_EOPF register field. */
5101 #define ALT_USB_GLOB_GINTSTS_EOPF_RESET 0x0
5102 /* Extracts the ALT_USB_GLOB_GINTSTS_EOPF field value from a register. */
5103 #define ALT_USB_GLOB_GINTSTS_EOPF_GET(value) (((value) & 0x00008000) >> 15)
5104 /* Produces a ALT_USB_GLOB_GINTSTS_EOPF register field value suitable for setting the register. */
5105 #define ALT_USB_GLOB_GINTSTS_EOPF_SET(value) (((value) << 15) & 0x00008000)
5106 
5107 /*
5108  * Field : epmis
5109  *
5110  * Mode: Device only
5111  *
5112  * Endpoint Mismatch Interrupt (EPMis)
5113  *
5114  * Note: This interrupt is valid only in shared FIFO operation.
5115  *
5116  * Indicates that an IN token has been received For a non-periodic
5117  *
5118  * endpoint, but the data For another endpoint is present in the top
5119  *
5120  * of the Non-periodic Transmit FIFO and the IN endpoint
5121  *
5122  * mismatch count programmed by the application has expired.
5123  *
5124  * Field Enumeration Values:
5125  *
5126  * Enum | Value | Description
5127  * :-----------------------------------|:------|:---------------------------
5128  * ALT_USB_GLOB_GINTSTS_EPMIS_E_INACT | 0x0 | Not active
5129  * ALT_USB_GLOB_GINTSTS_EPMIS_E_ACT | 0x1 | Endpoint Mismatch Interrup
5130  *
5131  * Field Access Macros:
5132  *
5133  */
5134 /*
5135  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_EPMIS
5136  *
5137  * Not active
5138  */
5139 #define ALT_USB_GLOB_GINTSTS_EPMIS_E_INACT 0x0
5140 /*
5141  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_EPMIS
5142  *
5143  * Endpoint Mismatch Interrup
5144  */
5145 #define ALT_USB_GLOB_GINTSTS_EPMIS_E_ACT 0x1
5146 
5147 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */
5148 #define ALT_USB_GLOB_GINTSTS_EPMIS_LSB 17
5149 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */
5150 #define ALT_USB_GLOB_GINTSTS_EPMIS_MSB 17
5151 /* The width in bits of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */
5152 #define ALT_USB_GLOB_GINTSTS_EPMIS_WIDTH 1
5153 /* The mask used to set the ALT_USB_GLOB_GINTSTS_EPMIS register field value. */
5154 #define ALT_USB_GLOB_GINTSTS_EPMIS_SET_MSK 0x00020000
5155 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_EPMIS register field value. */
5156 #define ALT_USB_GLOB_GINTSTS_EPMIS_CLR_MSK 0xfffdffff
5157 /* The reset value of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */
5158 #define ALT_USB_GLOB_GINTSTS_EPMIS_RESET 0x0
5159 /* Extracts the ALT_USB_GLOB_GINTSTS_EPMIS field value from a register. */
5160 #define ALT_USB_GLOB_GINTSTS_EPMIS_GET(value) (((value) & 0x00020000) >> 17)
5161 /* Produces a ALT_USB_GLOB_GINTSTS_EPMIS register field value suitable for setting the register. */
5162 #define ALT_USB_GLOB_GINTSTS_EPMIS_SET(value) (((value) << 17) & 0x00020000)
5163 
5164 /*
5165  * Field : iepint
5166  *
5167  * Mode: Device only
5168  *
5169  * IN Endpoints Interrupt (IEPInt)
5170  *
5171  * The core sets this bit to indicate that an interrupt is pending on
5172  *
5173  * one of the IN endpoints of the core (in Device mode). The
5174  *
5175  * application must read the Device All Endpoints Interrupt (DAINT)
5176  *
5177  * register to determine the exact number of the IN endpoint on
5178  *
5179  * Device IN Endpoint-n Interrupt (DIEPINTn) register to determine
5180  *
5181  * the exact cause of the interrupt. The application must clear the
5182  *
5183  * appropriate status bit in the corresponding DIEPINTn register to
5184  *
5185  * clear this bit.
5186  *
5187  * Field Enumeration Values:
5188  *
5189  * Enum | Value | Description
5190  * :------------------------------------|:------|:-----------------------
5191  * ALT_USB_GLOB_GINTSTS_IEPINT_E_INACT | 0x0 | Not active
5192  * ALT_USB_GLOB_GINTSTS_IEPINT_E_ACT | 0x1 | IN Endpoints Interrupt
5193  *
5194  * Field Access Macros:
5195  *
5196  */
5197 /*
5198  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_IEPINT
5199  *
5200  * Not active
5201  */
5202 #define ALT_USB_GLOB_GINTSTS_IEPINT_E_INACT 0x0
5203 /*
5204  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_IEPINT
5205  *
5206  * IN Endpoints Interrupt
5207  */
5208 #define ALT_USB_GLOB_GINTSTS_IEPINT_E_ACT 0x1
5209 
5210 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */
5211 #define ALT_USB_GLOB_GINTSTS_IEPINT_LSB 18
5212 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */
5213 #define ALT_USB_GLOB_GINTSTS_IEPINT_MSB 18
5214 /* The width in bits of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */
5215 #define ALT_USB_GLOB_GINTSTS_IEPINT_WIDTH 1
5216 /* The mask used to set the ALT_USB_GLOB_GINTSTS_IEPINT register field value. */
5217 #define ALT_USB_GLOB_GINTSTS_IEPINT_SET_MSK 0x00040000
5218 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_IEPINT register field value. */
5219 #define ALT_USB_GLOB_GINTSTS_IEPINT_CLR_MSK 0xfffbffff
5220 /* The reset value of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */
5221 #define ALT_USB_GLOB_GINTSTS_IEPINT_RESET 0x0
5222 /* Extracts the ALT_USB_GLOB_GINTSTS_IEPINT field value from a register. */
5223 #define ALT_USB_GLOB_GINTSTS_IEPINT_GET(value) (((value) & 0x00040000) >> 18)
5224 /* Produces a ALT_USB_GLOB_GINTSTS_IEPINT register field value suitable for setting the register. */
5225 #define ALT_USB_GLOB_GINTSTS_IEPINT_SET(value) (((value) << 18) & 0x00040000)
5226 
5227 /*
5228  * Field : oepint
5229  *
5230  * Mode: Device only
5231  *
5232  * OUT Endpoints Interrupt (OEPInt)
5233  *
5234  * The core sets this bit to indicate that an interrupt is pending on
5235  *
5236  * one of the OUT endpoints of the core (in Device mode). The
5237  *
5238  * application must read the Device All Endpoints Interrupt (DAINT)
5239  *
5240  * register to determine the exact number of the OUT endpoint on
5241  *
5242  * which the interrupt occurred, and Then read the corresponding
5243  *
5244  * Device OUT Endpoint-n Interrupt (DOEPINTn) register to
5245  *
5246  * determine the exact cause of the interrupt. The application must
5247  *
5248  * clear the appropriate status bit in the corresponding DOEPINTn
5249  *
5250  * register to clear this bit.
5251  *
5252  * Field Enumeration Values:
5253  *
5254  * Enum | Value | Description
5255  * :------------------------------------|:------|:------------------------
5256  * ALT_USB_GLOB_GINTSTS_OEPINT_E_INACT | 0x0 | Not active
5257  * ALT_USB_GLOB_GINTSTS_OEPINT_E_ACT | 0x1 | OUT Endpoints Interrupt
5258  *
5259  * Field Access Macros:
5260  *
5261  */
5262 /*
5263  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_OEPINT
5264  *
5265  * Not active
5266  */
5267 #define ALT_USB_GLOB_GINTSTS_OEPINT_E_INACT 0x0
5268 /*
5269  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_OEPINT
5270  *
5271  * OUT Endpoints Interrupt
5272  */
5273 #define ALT_USB_GLOB_GINTSTS_OEPINT_E_ACT 0x1
5274 
5275 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */
5276 #define ALT_USB_GLOB_GINTSTS_OEPINT_LSB 19
5277 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */
5278 #define ALT_USB_GLOB_GINTSTS_OEPINT_MSB 19
5279 /* The width in bits of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */
5280 #define ALT_USB_GLOB_GINTSTS_OEPINT_WIDTH 1
5281 /* The mask used to set the ALT_USB_GLOB_GINTSTS_OEPINT register field value. */
5282 #define ALT_USB_GLOB_GINTSTS_OEPINT_SET_MSK 0x00080000
5283 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_OEPINT register field value. */
5284 #define ALT_USB_GLOB_GINTSTS_OEPINT_CLR_MSK 0xfff7ffff
5285 /* The reset value of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */
5286 #define ALT_USB_GLOB_GINTSTS_OEPINT_RESET 0x0
5287 /* Extracts the ALT_USB_GLOB_GINTSTS_OEPINT field value from a register. */
5288 #define ALT_USB_GLOB_GINTSTS_OEPINT_GET(value) (((value) & 0x00080000) >> 19)
5289 /* Produces a ALT_USB_GLOB_GINTSTS_OEPINT register field value suitable for setting the register. */
5290 #define ALT_USB_GLOB_GINTSTS_OEPINT_SET(value) (((value) << 19) & 0x00080000)
5291 
5292 /*
5293  * Field : incompisoin
5294  *
5295  * Mode: Device only
5296  *
5297  * Incomplete Isochronous IN Transfer (incompISOIN)
5298  *
5299  * The core sets this interrupt to indicate that there is at least one
5300  *
5301  * isochronous IN endpoint on which the transfer is not completed
5302  *
5303  * in the current microframe. This interrupt is asserted along with
5304  *
5305  * the End of Periodic Frame Interrupt (EOPF) bit in this register.
5306  *
5307  * Note: This interrupt is not asserted in Scatter/Gather DMA
5308  *
5309  * mode.
5310  *
5311  * Field Enumeration Values:
5312  *
5313  * Enum | Value | Description
5314  * :-----------------------------------------|:------|:-----------------------------------
5315  * ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_INACT | 0x0 | Not active
5316  * ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_ACT | 0x1 | Incomplete Isochronous IN Transfer
5317  *
5318  * Field Access Macros:
5319  *
5320  */
5321 /*
5322  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPISOIN
5323  *
5324  * Not active
5325  */
5326 #define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_INACT 0x0
5327 /*
5328  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPISOIN
5329  *
5330  * Incomplete Isochronous IN Transfer
5331  */
5332 #define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_ACT 0x1
5333 
5334 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */
5335 #define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_LSB 20
5336 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */
5337 #define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_MSB 20
5338 /* The width in bits of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */
5339 #define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_WIDTH 1
5340 /* The mask used to set the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field value. */
5341 #define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_SET_MSK 0x00100000
5342 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field value. */
5343 #define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_CLR_MSK 0xffefffff
5344 /* The reset value of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */
5345 #define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_RESET 0x0
5346 /* Extracts the ALT_USB_GLOB_GINTSTS_INCOMPISOIN field value from a register. */
5347 #define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_GET(value) (((value) & 0x00100000) >> 20)
5348 /* Produces a ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field value suitable for setting the register. */
5349 #define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_SET(value) (((value) << 20) & 0x00100000)
5350 
5351 /*
5352  * Field : incomplp
5353  *
5354  * Incomplete Periodic Transfer (incomplP)
5355  *
5356  * In Host mode, the core sets this interrupt bit when there are
5357  *
5358  * incomplete periodic transactions still pending which are
5359  *
5360  * scheduled For the current microframe.
5361  *
5362  * Incomplete Isochronous OUT Transfer (incompISOOUT)
5363  *
5364  * The Device mode, the core sets this interrupt to indicate that
5365  *
5366  * there is at least one isochronous OUT endpoint on which the
5367  *
5368  * transfer is not completed in the current microframe. This
5369  *
5370  * interrupt is asserted along with the End of Periodic Frame
5371  *
5372  * Interrupt (EOPF) bit in this register.
5373  *
5374  * Field Enumeration Values:
5375  *
5376  * Enum | Value | Description
5377  * :--------------------------------------|:------|:-----------------------------
5378  * ALT_USB_GLOB_GINTSTS_INCOMPLP_E_INACT | 0x0 | Not active
5379  * ALT_USB_GLOB_GINTSTS_INCOMPLP_E_ACT | 0x1 | Incomplete Periodic Transfer
5380  *
5381  * Field Access Macros:
5382  *
5383  */
5384 /*
5385  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPLP
5386  *
5387  * Not active
5388  */
5389 #define ALT_USB_GLOB_GINTSTS_INCOMPLP_E_INACT 0x0
5390 /*
5391  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPLP
5392  *
5393  * Incomplete Periodic Transfer
5394  */
5395 #define ALT_USB_GLOB_GINTSTS_INCOMPLP_E_ACT 0x1
5396 
5397 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */
5398 #define ALT_USB_GLOB_GINTSTS_INCOMPLP_LSB 21
5399 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */
5400 #define ALT_USB_GLOB_GINTSTS_INCOMPLP_MSB 21
5401 /* The width in bits of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */
5402 #define ALT_USB_GLOB_GINTSTS_INCOMPLP_WIDTH 1
5403 /* The mask used to set the ALT_USB_GLOB_GINTSTS_INCOMPLP register field value. */
5404 #define ALT_USB_GLOB_GINTSTS_INCOMPLP_SET_MSK 0x00200000
5405 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_INCOMPLP register field value. */
5406 #define ALT_USB_GLOB_GINTSTS_INCOMPLP_CLR_MSK 0xffdfffff
5407 /* The reset value of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */
5408 #define ALT_USB_GLOB_GINTSTS_INCOMPLP_RESET 0x0
5409 /* Extracts the ALT_USB_GLOB_GINTSTS_INCOMPLP field value from a register. */
5410 #define ALT_USB_GLOB_GINTSTS_INCOMPLP_GET(value) (((value) & 0x00200000) >> 21)
5411 /* Produces a ALT_USB_GLOB_GINTSTS_INCOMPLP register field value suitable for setting the register. */
5412 #define ALT_USB_GLOB_GINTSTS_INCOMPLP_SET(value) (((value) << 21) & 0x00200000)
5413 
5414 /*
5415  * Field : fetsusp
5416  *
5417  * Mode: Device only
5418  *
5419  * Data Fetch Suspended (FetSusp)
5420  *
5421  * This interrupt is valid only in DMA mode. This interrupt indicates
5422  *
5423  * that the core has stopped fetching data For IN endpoints due to
5424  *
5425  * the unavailability of TxFIFO space or Request Queue space.
5426  *
5427  * This interrupt is used by the application For an endpoint
5428  *
5429  * mismatch algorithm.
5430  *
5431  * For example, after detecting an endpoint mismatch, the
5432  *
5433  * application:
5434  *
5435  * Sets a Global non-periodic IN NAK handshake
5436  *
5437  * Disables In endpoints
5438  *
5439  * Flushes the FIFO
5440  *
5441  * Determines the token sequence from the IN Token Sequence
5442  *
5443  * Learning Queue
5444  *
5445  * Re-enables the endpoints
5446  *
5447  * Clears the Global non-periodic IN NAK handshake
5448  *
5449  * If the Global non-periodic IN NAK is cleared, the core has not yet
5450  *
5451  * fetched data For the IN endpoint, and the IN token is received:
5452  *
5453  * the core generates an 'IN token received when FIFO empty'
5454  *
5455  * interrupt. The OTG Then sends the host a NAK response. To
5456  *
5457  * avoid this scenario, the application can check the
5458  *
5459  * GINTSTS.FetSusp interrupt, which ensures that the FIFO is full
5460  *
5461  * before clearing a Global NAK handshake.
5462  *
5463  * Alternatively, the application can mask the "IN token received
5464  *
5465  * when FIFO empty" interrupt when clearing a Global IN NAK
5466  *
5467  * handshake.
5468  *
5469  * Field Enumeration Values:
5470  *
5471  * Enum | Value | Description
5472  * :-------------------------------------|:------|:---------------------
5473  * ALT_USB_GLOB_GINTSTS_FETSUSP_E_INACT | 0x0 | Not active
5474  * ALT_USB_GLOB_GINTSTS_FETSUSP_E_ACT | 0x1 | Data Fetch Suspended
5475  *
5476  * Field Access Macros:
5477  *
5478  */
5479 /*
5480  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_FETSUSP
5481  *
5482  * Not active
5483  */
5484 #define ALT_USB_GLOB_GINTSTS_FETSUSP_E_INACT 0x0
5485 /*
5486  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_FETSUSP
5487  *
5488  * Data Fetch Suspended
5489  */
5490 #define ALT_USB_GLOB_GINTSTS_FETSUSP_E_ACT 0x1
5491 
5492 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */
5493 #define ALT_USB_GLOB_GINTSTS_FETSUSP_LSB 22
5494 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */
5495 #define ALT_USB_GLOB_GINTSTS_FETSUSP_MSB 22
5496 /* The width in bits of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */
5497 #define ALT_USB_GLOB_GINTSTS_FETSUSP_WIDTH 1
5498 /* The mask used to set the ALT_USB_GLOB_GINTSTS_FETSUSP register field value. */
5499 #define ALT_USB_GLOB_GINTSTS_FETSUSP_SET_MSK 0x00400000
5500 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_FETSUSP register field value. */
5501 #define ALT_USB_GLOB_GINTSTS_FETSUSP_CLR_MSK 0xffbfffff
5502 /* The reset value of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */
5503 #define ALT_USB_GLOB_GINTSTS_FETSUSP_RESET 0x0
5504 /* Extracts the ALT_USB_GLOB_GINTSTS_FETSUSP field value from a register. */
5505 #define ALT_USB_GLOB_GINTSTS_FETSUSP_GET(value) (((value) & 0x00400000) >> 22)
5506 /* Produces a ALT_USB_GLOB_GINTSTS_FETSUSP register field value suitable for setting the register. */
5507 #define ALT_USB_GLOB_GINTSTS_FETSUSP_SET(value) (((value) << 22) & 0x00400000)
5508 
5509 /*
5510  * Field : resetdet
5511  *
5512  * Mode: Device only
5513  *
5514  * Reset detected Interrupt (ResetDet)
5515  *
5516  * In Device mode, this interrupt is asserted when a reset is detected on the USB
5517  * in
5518  *
5519  * partial power-down mode when the device is in Suspend.
5520  *
5521  * In Host mode, this interrupt is not asserted.
5522  *
5523  * Field Enumeration Values:
5524  *
5525  * Enum | Value | Description
5526  * :------------------------------------|:------|:------------------------
5527  * ALT_USB_GLOB_GINTSTS_RSTDET_E_INACT | 0x0 | Not active
5528  * ALT_USB_GLOB_GINTSTS_RSTDET_E_ACT | 0x1 | Reset detected Interrup
5529  *
5530  * Field Access Macros:
5531  *
5532  */
5533 /*
5534  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_RSTDET
5535  *
5536  * Not active
5537  */
5538 #define ALT_USB_GLOB_GINTSTS_RSTDET_E_INACT 0x0
5539 /*
5540  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_RSTDET
5541  *
5542  * Reset detected Interrup
5543  */
5544 #define ALT_USB_GLOB_GINTSTS_RSTDET_E_ACT 0x1
5545 
5546 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */
5547 #define ALT_USB_GLOB_GINTSTS_RSTDET_LSB 23
5548 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */
5549 #define ALT_USB_GLOB_GINTSTS_RSTDET_MSB 23
5550 /* The width in bits of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */
5551 #define ALT_USB_GLOB_GINTSTS_RSTDET_WIDTH 1
5552 /* The mask used to set the ALT_USB_GLOB_GINTSTS_RSTDET register field value. */
5553 #define ALT_USB_GLOB_GINTSTS_RSTDET_SET_MSK 0x00800000
5554 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_RSTDET register field value. */
5555 #define ALT_USB_GLOB_GINTSTS_RSTDET_CLR_MSK 0xff7fffff
5556 /* The reset value of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */
5557 #define ALT_USB_GLOB_GINTSTS_RSTDET_RESET 0x0
5558 /* Extracts the ALT_USB_GLOB_GINTSTS_RSTDET field value from a register. */
5559 #define ALT_USB_GLOB_GINTSTS_RSTDET_GET(value) (((value) & 0x00800000) >> 23)
5560 /* Produces a ALT_USB_GLOB_GINTSTS_RSTDET register field value suitable for setting the register. */
5561 #define ALT_USB_GLOB_GINTSTS_RSTDET_SET(value) (((value) << 23) & 0x00800000)
5562 
5563 /*
5564  * Field : prtint
5565  *
5566  * Mode:Host only
5567  *
5568  * Host Port Interrupt (PrtInt)
5569  *
5570  * The core sets this bit to indicate a change in port status of one of
5571  *
5572  * the DWC_otg core ports in Host mode. The application must
5573  *
5574  * read the Host Port Control and Status (HPRT) register to
5575  *
5576  * determine the exact event that caused this interrupt. The
5577  *
5578  * application must clear the appropriate status bit in the Host Port
5579  *
5580  * Control and Status register to clear this bit.
5581  *
5582  * Field Enumeration Values:
5583  *
5584  * Enum | Value | Description
5585  * :------------------------------------|:------|:--------------------
5586  * ALT_USB_GLOB_GINTSTS_PRTINT_E_INACT | 0x0 |
5587  * ALT_USB_GLOB_GINTSTS_PRTINT_E_ACT | 0x1 | Host Port Interrupt
5588  *
5589  * Field Access Macros:
5590  *
5591  */
5592 /*
5593  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_PRTINT
5594  *
5595  */
5596 #define ALT_USB_GLOB_GINTSTS_PRTINT_E_INACT 0x0
5597 /*
5598  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_PRTINT
5599  *
5600  * Host Port Interrupt
5601  */
5602 #define ALT_USB_GLOB_GINTSTS_PRTINT_E_ACT 0x1
5603 
5604 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */
5605 #define ALT_USB_GLOB_GINTSTS_PRTINT_LSB 24
5606 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */
5607 #define ALT_USB_GLOB_GINTSTS_PRTINT_MSB 24
5608 /* The width in bits of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */
5609 #define ALT_USB_GLOB_GINTSTS_PRTINT_WIDTH 1
5610 /* The mask used to set the ALT_USB_GLOB_GINTSTS_PRTINT register field value. */
5611 #define ALT_USB_GLOB_GINTSTS_PRTINT_SET_MSK 0x01000000
5612 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_PRTINT register field value. */
5613 #define ALT_USB_GLOB_GINTSTS_PRTINT_CLR_MSK 0xfeffffff
5614 /* The reset value of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */
5615 #define ALT_USB_GLOB_GINTSTS_PRTINT_RESET 0x0
5616 /* Extracts the ALT_USB_GLOB_GINTSTS_PRTINT field value from a register. */
5617 #define ALT_USB_GLOB_GINTSTS_PRTINT_GET(value) (((value) & 0x01000000) >> 24)
5618 /* Produces a ALT_USB_GLOB_GINTSTS_PRTINT register field value suitable for setting the register. */
5619 #define ALT_USB_GLOB_GINTSTS_PRTINT_SET(value) (((value) << 24) & 0x01000000)
5620 
5621 /*
5622  * Field : hchint
5623  *
5624  * Mode:Host only
5625  *
5626  * Host Channels Interrupt (HChInt)
5627  *
5628  * The core sets this bit to indicate that an interrupt is pending on
5629  *
5630  * one of the channels of the core (in Host mode). The application
5631  *
5632  * must read the Host All Channels Interrupt (HAINT) register to
5633  *
5634  * determine the exact number of the channel on which the
5635  *
5636  * interrupt occurred, and Then read the corresponding Host
5637  *
5638  * Channel-n Interrupt (HCINTn) register to determine the exact
5639  *
5640  * cause of the interrupt. The application must clear the
5641  *
5642  * appropriate status bit in the HCINTn register to clear this bit.
5643  *
5644  * Field Enumeration Values:
5645  *
5646  * Enum | Value | Description
5647  * :------------------------------------|:------|:------------------------
5648  * ALT_USB_GLOB_GINTSTS_HCHINT_E_INACT | 0x0 | Not active
5649  * ALT_USB_GLOB_GINTSTS_HCHINT_E_ACT | 0x1 | Host Channels Interrupt
5650  *
5651  * Field Access Macros:
5652  *
5653  */
5654 /*
5655  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_HCHINT
5656  *
5657  * Not active
5658  */
5659 #define ALT_USB_GLOB_GINTSTS_HCHINT_E_INACT 0x0
5660 /*
5661  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_HCHINT
5662  *
5663  * Host Channels Interrupt
5664  */
5665 #define ALT_USB_GLOB_GINTSTS_HCHINT_E_ACT 0x1
5666 
5667 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */
5668 #define ALT_USB_GLOB_GINTSTS_HCHINT_LSB 25
5669 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */
5670 #define ALT_USB_GLOB_GINTSTS_HCHINT_MSB 25
5671 /* The width in bits of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */
5672 #define ALT_USB_GLOB_GINTSTS_HCHINT_WIDTH 1
5673 /* The mask used to set the ALT_USB_GLOB_GINTSTS_HCHINT register field value. */
5674 #define ALT_USB_GLOB_GINTSTS_HCHINT_SET_MSK 0x02000000
5675 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_HCHINT register field value. */
5676 #define ALT_USB_GLOB_GINTSTS_HCHINT_CLR_MSK 0xfdffffff
5677 /* The reset value of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */
5678 #define ALT_USB_GLOB_GINTSTS_HCHINT_RESET 0x0
5679 /* Extracts the ALT_USB_GLOB_GINTSTS_HCHINT field value from a register. */
5680 #define ALT_USB_GLOB_GINTSTS_HCHINT_GET(value) (((value) & 0x02000000) >> 25)
5681 /* Produces a ALT_USB_GLOB_GINTSTS_HCHINT register field value suitable for setting the register. */
5682 #define ALT_USB_GLOB_GINTSTS_HCHINT_SET(value) (((value) << 25) & 0x02000000)
5683 
5684 /*
5685  * Field : ptxfemp
5686  *
5687  * Mode:Host only
5688  *
5689  * Periodic TxFIFO Empty (PTxFEmp)
5690  *
5691  * This interrupt is asserted when the Periodic Transmit FIFO is either half or
5692  *
5693  * completely empty and there is space for at least one entry to be written in
5694  *
5695  * the Periodic Request Queue. The half or completely empty status is
5696  *
5697  * determined by the Periodic TxFIFO Empty Level bit in the Core AHB
5698  *
5699  * Configuration register (GAHBCFG.PTxFEmpLvl).
5700  *
5701  * Field Enumeration Values:
5702  *
5703  * Enum | Value | Description
5704  * :-------------------------------------|:------|:----------------------
5705  * ALT_USB_GLOB_GINTSTS_PTXFEMP_E_INACT | 0x0 | Not active
5706  * ALT_USB_GLOB_GINTSTS_PTXFEMP_E_ACT | 0x1 | Periodic TxFIFO Empty
5707  *
5708  * Field Access Macros:
5709  *
5710  */
5711 /*
5712  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_PTXFEMP
5713  *
5714  * Not active
5715  */
5716 #define ALT_USB_GLOB_GINTSTS_PTXFEMP_E_INACT 0x0
5717 /*
5718  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_PTXFEMP
5719  *
5720  * Periodic TxFIFO Empty
5721  */
5722 #define ALT_USB_GLOB_GINTSTS_PTXFEMP_E_ACT 0x1
5723 
5724 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */
5725 #define ALT_USB_GLOB_GINTSTS_PTXFEMP_LSB 26
5726 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */
5727 #define ALT_USB_GLOB_GINTSTS_PTXFEMP_MSB 26
5728 /* The width in bits of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */
5729 #define ALT_USB_GLOB_GINTSTS_PTXFEMP_WIDTH 1
5730 /* The mask used to set the ALT_USB_GLOB_GINTSTS_PTXFEMP register field value. */
5731 #define ALT_USB_GLOB_GINTSTS_PTXFEMP_SET_MSK 0x04000000
5732 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_PTXFEMP register field value. */
5733 #define ALT_USB_GLOB_GINTSTS_PTXFEMP_CLR_MSK 0xfbffffff
5734 /* The reset value of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */
5735 #define ALT_USB_GLOB_GINTSTS_PTXFEMP_RESET 0x1
5736 /* Extracts the ALT_USB_GLOB_GINTSTS_PTXFEMP field value from a register. */
5737 #define ALT_USB_GLOB_GINTSTS_PTXFEMP_GET(value) (((value) & 0x04000000) >> 26)
5738 /* Produces a ALT_USB_GLOB_GINTSTS_PTXFEMP register field value suitable for setting the register. */
5739 #define ALT_USB_GLOB_GINTSTS_PTXFEMP_SET(value) (((value) << 26) & 0x04000000)
5740 
5741 /*
5742  * Field : conidstschng
5743  *
5744  * Mode:Host and Device
5745  *
5746  * Connector ID Status Change (ConIDStsChng)
5747  *
5748  * The core sets this bit when there is a change in connector ID
5749  *
5750  * status.
5751  *
5752  * Field Enumeration Values:
5753  *
5754  * Enum | Value | Description
5755  * :------------------------------------------|:------|:---------------------------
5756  * ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_INACT | 0x0 | Not Active
5757  * ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_ACT | 0x1 | Connector ID Status Change
5758  *
5759  * Field Access Macros:
5760  *
5761  */
5762 /*
5763  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG
5764  *
5765  * Not Active
5766  */
5767 #define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_INACT 0x0
5768 /*
5769  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG
5770  *
5771  * Connector ID Status Change
5772  */
5773 #define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_ACT 0x1
5774 
5775 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */
5776 #define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_LSB 28
5777 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */
5778 #define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_MSB 28
5779 /* The width in bits of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */
5780 #define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_WIDTH 1
5781 /* The mask used to set the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field value. */
5782 #define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_SET_MSK 0x10000000
5783 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field value. */
5784 #define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_CLR_MSK 0xefffffff
5785 /* The reset value of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */
5786 #define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_RESET 0x1
5787 /* Extracts the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG field value from a register. */
5788 #define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_GET(value) (((value) & 0x10000000) >> 28)
5789 /* Produces a ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field value suitable for setting the register. */
5790 #define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_SET(value) (((value) << 28) & 0x10000000)
5791 
5792 /*
5793  * Field : disconnint
5794  *
5795  * Mode:Host only
5796  *
5797  * Disconnect Detected Interrupt (DisconnInt)
5798  *
5799  * Asserted when a device disconnect is detected.
5800  *
5801  * Field Enumeration Values:
5802  *
5803  * Enum | Value | Description
5804  * :----------------------------------------|:------|:------------------------------
5805  * ALT_USB_GLOB_GINTSTS_DISCONNINT_E_INACT | 0x0 | Not active
5806  * ALT_USB_GLOB_GINTSTS_DISCONNINT_E_ACT | 0x1 | Disconnect Detected Interrupt
5807  *
5808  * Field Access Macros:
5809  *
5810  */
5811 /*
5812  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_DISCONNINT
5813  *
5814  * Not active
5815  */
5816 #define ALT_USB_GLOB_GINTSTS_DISCONNINT_E_INACT 0x0
5817 /*
5818  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_DISCONNINT
5819  *
5820  * Disconnect Detected Interrupt
5821  */
5822 #define ALT_USB_GLOB_GINTSTS_DISCONNINT_E_ACT 0x1
5823 
5824 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */
5825 #define ALT_USB_GLOB_GINTSTS_DISCONNINT_LSB 29
5826 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */
5827 #define ALT_USB_GLOB_GINTSTS_DISCONNINT_MSB 29
5828 /* The width in bits of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */
5829 #define ALT_USB_GLOB_GINTSTS_DISCONNINT_WIDTH 1
5830 /* The mask used to set the ALT_USB_GLOB_GINTSTS_DISCONNINT register field value. */
5831 #define ALT_USB_GLOB_GINTSTS_DISCONNINT_SET_MSK 0x20000000
5832 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_DISCONNINT register field value. */
5833 #define ALT_USB_GLOB_GINTSTS_DISCONNINT_CLR_MSK 0xdfffffff
5834 /* The reset value of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */
5835 #define ALT_USB_GLOB_GINTSTS_DISCONNINT_RESET 0x0
5836 /* Extracts the ALT_USB_GLOB_GINTSTS_DISCONNINT field value from a register. */
5837 #define ALT_USB_GLOB_GINTSTS_DISCONNINT_GET(value) (((value) & 0x20000000) >> 29)
5838 /* Produces a ALT_USB_GLOB_GINTSTS_DISCONNINT register field value suitable for setting the register. */
5839 #define ALT_USB_GLOB_GINTSTS_DISCONNINT_SET(value) (((value) << 29) & 0x20000000)
5840 
5841 /*
5842  * Field : sessreqint
5843  *
5844  * Mode:Host and Device
5845  *
5846  * Session Request/New Session Detected Interrupt (SessReqInt)
5847  *
5848  * In Host mode, this interrupt is asserted when a session request is detected
5849  *
5850  * from the device. In Host mode, this interrupt is asserted when a session
5851  *
5852  * request is detected from the device.
5853  *
5854  * In Device mode, this interrupt is asserted when the utmisrp_bvalid signal
5855  *
5856  * goes high.
5857  *
5858  * For more information on how to use this interrupt, see 'Partial Power-Down
5859  *
5860  * and Clock Gating Programming Model'.
5861  *
5862  * Field Enumeration Values:
5863  *
5864  * Enum | Value | Description
5865  * :----------------------------------------|:------|:-----------------------------------------------
5866  * ALT_USB_GLOB_GINTSTS_SESSREQINT_E_INACT | 0x0 | Not active
5867  * ALT_USB_GLOB_GINTSTS_SESSREQINT_E_ACT | 0x1 | Session Request New Session Detected Interrupt
5868  *
5869  * Field Access Macros:
5870  *
5871  */
5872 /*
5873  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_SESSREQINT
5874  *
5875  * Not active
5876  */
5877 #define ALT_USB_GLOB_GINTSTS_SESSREQINT_E_INACT 0x0
5878 /*
5879  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_SESSREQINT
5880  *
5881  * Session Request New Session Detected Interrupt
5882  */
5883 #define ALT_USB_GLOB_GINTSTS_SESSREQINT_E_ACT 0x1
5884 
5885 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */
5886 #define ALT_USB_GLOB_GINTSTS_SESSREQINT_LSB 30
5887 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */
5888 #define ALT_USB_GLOB_GINTSTS_SESSREQINT_MSB 30
5889 /* The width in bits of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */
5890 #define ALT_USB_GLOB_GINTSTS_SESSREQINT_WIDTH 1
5891 /* The mask used to set the ALT_USB_GLOB_GINTSTS_SESSREQINT register field value. */
5892 #define ALT_USB_GLOB_GINTSTS_SESSREQINT_SET_MSK 0x40000000
5893 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_SESSREQINT register field value. */
5894 #define ALT_USB_GLOB_GINTSTS_SESSREQINT_CLR_MSK 0xbfffffff
5895 /* The reset value of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */
5896 #define ALT_USB_GLOB_GINTSTS_SESSREQINT_RESET 0x0
5897 /* Extracts the ALT_USB_GLOB_GINTSTS_SESSREQINT field value from a register. */
5898 #define ALT_USB_GLOB_GINTSTS_SESSREQINT_GET(value) (((value) & 0x40000000) >> 30)
5899 /* Produces a ALT_USB_GLOB_GINTSTS_SESSREQINT register field value suitable for setting the register. */
5900 #define ALT_USB_GLOB_GINTSTS_SESSREQINT_SET(value) (((value) << 30) & 0x40000000)
5901 
5902 /*
5903  * Field : wkupint
5904  *
5905  * Mode:Host and Device
5906  *
5907  * Resume/Remote Wakeup Detected Interrupt (WkUpInt)
5908  *
5909  * Wakeup Interrupt during Suspend(L2) or LPM(L1) state.
5910  *
5911  * During Suspend(L2):
5912  *
5913  * * Device Mode - This interrupt is asserted only when Host Initiated
5914  *
5915  * Resume is detected on USB.
5916  *
5917  * * Host Mode - This interrupt is asserted only when Device Initiated
5918  *
5919  * Remote Wakeup is detected on USB.
5920  *
5921  * For more information, see 'Partial Power-Down and Clock Gating
5922  *
5923  * Programming Model'.
5924  *
5925  * During LPM(L1):-
5926  *
5927  * * Device Mode - This interrupt is asserted for either Host Initiated
5928  *
5929  * Resume or Device Initiated Remote Wakeup on USB.
5930  *
5931  * * Host Mode - This interrupt is asserted for either Host Initiated Resume
5932  *
5933  * or Device Initiated Remote Wakeup on USB.
5934  *
5935  * For more information, see 'LPM Entry and Exit Programming Model'
5936  *
5937  * Field Enumeration Values:
5938  *
5939  * Enum | Value | Description
5940  * :-------------------------------------|:------|:----------------------------------------
5941  * ALT_USB_GLOB_GINTSTS_WKUPINT_E_INACT | 0x0 | Not active
5942  * ALT_USB_GLOB_GINTSTS_WKUPINT_E_ACT | 0x1 | Resume Remote Wakeup Detected Interrupt
5943  *
5944  * Field Access Macros:
5945  *
5946  */
5947 /*
5948  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_WKUPINT
5949  *
5950  * Not active
5951  */
5952 #define ALT_USB_GLOB_GINTSTS_WKUPINT_E_INACT 0x0
5953 /*
5954  * Enumerated value for register field ALT_USB_GLOB_GINTSTS_WKUPINT
5955  *
5956  * Resume Remote Wakeup Detected Interrupt
5957  */
5958 #define ALT_USB_GLOB_GINTSTS_WKUPINT_E_ACT 0x1
5959 
5960 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */
5961 #define ALT_USB_GLOB_GINTSTS_WKUPINT_LSB 31
5962 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */
5963 #define ALT_USB_GLOB_GINTSTS_WKUPINT_MSB 31
5964 /* The width in bits of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */
5965 #define ALT_USB_GLOB_GINTSTS_WKUPINT_WIDTH 1
5966 /* The mask used to set the ALT_USB_GLOB_GINTSTS_WKUPINT register field value. */
5967 #define ALT_USB_GLOB_GINTSTS_WKUPINT_SET_MSK 0x80000000
5968 /* The mask used to clear the ALT_USB_GLOB_GINTSTS_WKUPINT register field value. */
5969 #define ALT_USB_GLOB_GINTSTS_WKUPINT_CLR_MSK 0x7fffffff
5970 /* The reset value of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */
5971 #define ALT_USB_GLOB_GINTSTS_WKUPINT_RESET 0x0
5972 /* Extracts the ALT_USB_GLOB_GINTSTS_WKUPINT field value from a register. */
5973 #define ALT_USB_GLOB_GINTSTS_WKUPINT_GET(value) (((value) & 0x80000000) >> 31)
5974 /* Produces a ALT_USB_GLOB_GINTSTS_WKUPINT register field value suitable for setting the register. */
5975 #define ALT_USB_GLOB_GINTSTS_WKUPINT_SET(value) (((value) << 31) & 0x80000000)
5976 
5977 #ifndef __ASSEMBLY__
5978 /*
5979  * WARNING: The C register and register group struct declarations are provided for
5980  * convenience and illustrative purposes. They should, however, be used with
5981  * caution as the C language standard provides no guarantees about the alignment or
5982  * atomicity of device memory accesses. The recommended practice for writing
5983  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5984  * alt_write_word() functions.
5985  *
5986  * The struct declaration for register ALT_USB_GLOB_GINTSTS.
5987  */
5988 struct ALT_USB_GLOB_GINTSTS_s
5989 {
5990  const uint32_t curmod : 1; /* ALT_USB_GLOB_GINTSTS_CURMOD */
5991  uint32_t modemis : 1; /* ALT_USB_GLOB_GINTSTS_MODMIS */
5992  const uint32_t otgint : 1; /* ALT_USB_GLOB_GINTSTS_OTGINT */
5993  uint32_t sof : 1; /* ALT_USB_GLOB_GINTSTS_SOF */
5994  const uint32_t rxflvl : 1; /* ALT_USB_GLOB_GINTSTS_RXFLVL */
5995  const uint32_t nptxfemp : 1; /* ALT_USB_GLOB_GINTSTS_NPTXFEMP */
5996  const uint32_t ginnakeff : 1; /* ALT_USB_GLOB_GINTSTS_GINNAKEFF */
5997  const uint32_t goutnakeff : 1; /* ALT_USB_GLOB_GINTSTS_GOUTNAKEFF */
5998  uint32_t : 2; /* *UNDEFINED* */
5999  uint32_t erlysusp : 1; /* ALT_USB_GLOB_GINTSTS_ERLYSUSP */
6000  uint32_t usbsusp : 1; /* ALT_USB_GLOB_GINTSTS_USBSUSP */
6001  uint32_t usbrst : 1; /* ALT_USB_GLOB_GINTSTS_USBRST */
6002  uint32_t enumdone : 1; /* ALT_USB_GLOB_GINTSTS_ENUMDONE */
6003  uint32_t isooutdrop : 1; /* ALT_USB_GLOB_GINTSTS_ISOOUTDROP */
6004  uint32_t eopf : 1; /* ALT_USB_GLOB_GINTSTS_EOPF */
6005  uint32_t : 1; /* *UNDEFINED* */
6006  uint32_t epmis : 1; /* ALT_USB_GLOB_GINTSTS_EPMIS */
6007  const uint32_t iepint : 1; /* ALT_USB_GLOB_GINTSTS_IEPINT */
6008  const uint32_t oepint : 1; /* ALT_USB_GLOB_GINTSTS_OEPINT */
6009  uint32_t incompisoin : 1; /* ALT_USB_GLOB_GINTSTS_INCOMPISOIN */
6010  uint32_t incomplp : 1; /* ALT_USB_GLOB_GINTSTS_INCOMPLP */
6011  uint32_t fetsusp : 1; /* ALT_USB_GLOB_GINTSTS_FETSUSP */
6012  uint32_t resetdet : 1; /* ALT_USB_GLOB_GINTSTS_RSTDET */
6013  const uint32_t prtint : 1; /* ALT_USB_GLOB_GINTSTS_PRTINT */
6014  const uint32_t hchint : 1; /* ALT_USB_GLOB_GINTSTS_HCHINT */
6015  const uint32_t ptxfemp : 1; /* ALT_USB_GLOB_GINTSTS_PTXFEMP */
6016  uint32_t : 1; /* *UNDEFINED* */
6017  uint32_t conidstschng : 1; /* ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG */
6018  uint32_t disconnint : 1; /* ALT_USB_GLOB_GINTSTS_DISCONNINT */
6019  uint32_t sessreqint : 1; /* ALT_USB_GLOB_GINTSTS_SESSREQINT */
6020  uint32_t wkupint : 1; /* ALT_USB_GLOB_GINTSTS_WKUPINT */
6021 };
6022 
6023 /* The typedef declaration for register ALT_USB_GLOB_GINTSTS. */
6024 typedef volatile struct ALT_USB_GLOB_GINTSTS_s ALT_USB_GLOB_GINTSTS_t;
6025 #endif /* __ASSEMBLY__ */
6026 
6027 /* The reset value of the ALT_USB_GLOB_GINTSTS register. */
6028 #define ALT_USB_GLOB_GINTSTS_RESET 0x14000020
6029 /* The byte offset of the ALT_USB_GLOB_GINTSTS register from the beginning of the component. */
6030 #define ALT_USB_GLOB_GINTSTS_OFST 0x14
6031 /* The address of the ALT_USB_GLOB_GINTSTS register. */
6032 #define ALT_USB_GLOB_GINTSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GINTSTS_OFST))
6033 
6034 /*
6035  * Register : gintmsk
6036  *
6037  * Interrupt Mask Register
6038  *
6039  * Register Layout
6040  *
6041  * Bits | Access | Reset | Description
6042  * :------|:-------|:------|:-------------------------------------
6043  * [0] | ??? | 0x0 | *UNDEFINED*
6044  * [1] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_MODMISMSK
6045  * [2] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_OTGINTMSK
6046  * [3] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_SOFMSK
6047  * [4] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_RXFLVLMSK
6048  * [5] | ??? | 0x0 | *UNDEFINED*
6049  * [6] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK
6050  * [7] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK
6051  * [9:8] | ??? | 0x0 | *UNDEFINED*
6052  * [10] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK
6053  * [11] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_USBSUSPMSK
6054  * [12] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_USBRSTMSK
6055  * [13] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_ENUMDONEMSK
6056  * [14] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK
6057  * [15] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_EOPFMSK
6058  * [16] | ??? | 0x0 | *UNDEFINED*
6059  * [17] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_EPMISMSK
6060  * [18] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_IEPINTMSK
6061  * [19] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_OEPINTMSK
6062  * [20] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK
6063  * [21] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_INCOMPLPMSK
6064  * [22] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_FETSUSPMSK
6065  * [23] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_RSTDETMSK
6066  * [24] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_PRTINTMSK
6067  * [25] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_HCHINTMSK
6068  * [26] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_PTXFEMPMSK
6069  * [27] | ??? | 0x0 | *UNDEFINED*
6070  * [28] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK
6071  * [29] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_DISCONNINTMSK
6072  * [30] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_SESSREQINTMSK
6073  * [31] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_WKUPINTMSK
6074  *
6075  */
6076 /*
6077  * Field : modemismsk
6078  *
6079  * Mode: Host and Device
6080  *
6081  * Mode Mismatch Interrupt Mask (ModeMisMsk)
6082  *
6083  * Field Enumeration Values:
6084  *
6085  * Enum | Value | Description
6086  * :---------------------------------------|:------|:--------------------------------
6087  * ALT_USB_GLOB_GINTMSK_MODMISMSK_E_MSK | 0x0 | Mode Mismatch Interrupt Mask
6088  * ALT_USB_GLOB_GINTMSK_MODMISMSK_E_NOMSK | 0x1 | No Mask Mode Mismatch Interrupt
6089  *
6090  * Field Access Macros:
6091  *
6092  */
6093 /*
6094  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_MODMISMSK
6095  *
6096  * Mode Mismatch Interrupt Mask
6097  */
6098 #define ALT_USB_GLOB_GINTMSK_MODMISMSK_E_MSK 0x0
6099 /*
6100  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_MODMISMSK
6101  *
6102  * No Mask Mode Mismatch Interrupt
6103  */
6104 #define ALT_USB_GLOB_GINTMSK_MODMISMSK_E_NOMSK 0x1
6105 
6106 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */
6107 #define ALT_USB_GLOB_GINTMSK_MODMISMSK_LSB 1
6108 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */
6109 #define ALT_USB_GLOB_GINTMSK_MODMISMSK_MSB 1
6110 /* The width in bits of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */
6111 #define ALT_USB_GLOB_GINTMSK_MODMISMSK_WIDTH 1
6112 /* The mask used to set the ALT_USB_GLOB_GINTMSK_MODMISMSK register field value. */
6113 #define ALT_USB_GLOB_GINTMSK_MODMISMSK_SET_MSK 0x00000002
6114 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_MODMISMSK register field value. */
6115 #define ALT_USB_GLOB_GINTMSK_MODMISMSK_CLR_MSK 0xfffffffd
6116 /* The reset value of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */
6117 #define ALT_USB_GLOB_GINTMSK_MODMISMSK_RESET 0x0
6118 /* Extracts the ALT_USB_GLOB_GINTMSK_MODMISMSK field value from a register. */
6119 #define ALT_USB_GLOB_GINTMSK_MODMISMSK_GET(value) (((value) & 0x00000002) >> 1)
6120 /* Produces a ALT_USB_GLOB_GINTMSK_MODMISMSK register field value suitable for setting the register. */
6121 #define ALT_USB_GLOB_GINTMSK_MODMISMSK_SET(value) (((value) << 1) & 0x00000002)
6122 
6123 /*
6124  * Field : otgintmsk
6125  *
6126  * Mode: Host and Device
6127  *
6128  * OTG Interrupt Mask (OTGIntMsk)
6129  *
6130  * Field Enumeration Values:
6131  *
6132  * Enum | Value | Description
6133  * :---------------------------------------|:------|:----------------------
6134  * ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_MSK | 0x0 | OTG Interrupt Mask
6135  * ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_NOMSK | 0x1 | No mask OTG Interrupt
6136  *
6137  * Field Access Macros:
6138  *
6139  */
6140 /*
6141  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_OTGINTMSK
6142  *
6143  * OTG Interrupt Mask
6144  */
6145 #define ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_MSK 0x0
6146 /*
6147  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_OTGINTMSK
6148  *
6149  * No mask OTG Interrupt
6150  */
6151 #define ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_NOMSK 0x1
6152 
6153 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */
6154 #define ALT_USB_GLOB_GINTMSK_OTGINTMSK_LSB 2
6155 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */
6156 #define ALT_USB_GLOB_GINTMSK_OTGINTMSK_MSB 2
6157 /* The width in bits of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */
6158 #define ALT_USB_GLOB_GINTMSK_OTGINTMSK_WIDTH 1
6159 /* The mask used to set the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field value. */
6160 #define ALT_USB_GLOB_GINTMSK_OTGINTMSK_SET_MSK 0x00000004
6161 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field value. */
6162 #define ALT_USB_GLOB_GINTMSK_OTGINTMSK_CLR_MSK 0xfffffffb
6163 /* The reset value of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */
6164 #define ALT_USB_GLOB_GINTMSK_OTGINTMSK_RESET 0x0
6165 /* Extracts the ALT_USB_GLOB_GINTMSK_OTGINTMSK field value from a register. */
6166 #define ALT_USB_GLOB_GINTMSK_OTGINTMSK_GET(value) (((value) & 0x00000004) >> 2)
6167 /* Produces a ALT_USB_GLOB_GINTMSK_OTGINTMSK register field value suitable for setting the register. */
6168 #define ALT_USB_GLOB_GINTMSK_OTGINTMSK_SET(value) (((value) << 2) & 0x00000004)
6169 
6170 /*
6171  * Field : sofmsk
6172  *
6173  * Mode: Host and Device
6174  *
6175  * Start of (micro)Frame Mask (SofMsk)
6176  *
6177  * Field Enumeration Values:
6178  *
6179  * Enum | Value | Description
6180  * :------------------------------------|:------|:-----------------------
6181  * ALT_USB_GLOB_GINTMSK_SOFMSK_E_MSK | 0x0 | Start of Frame Mask
6182  * ALT_USB_GLOB_GINTMSK_SOFMSK_E_NOMSK | 0x1 | No Mask Start of Frame
6183  *
6184  * Field Access Macros:
6185  *
6186  */
6187 /*
6188  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_SOFMSK
6189  *
6190  * Start of Frame Mask
6191  */
6192 #define ALT_USB_GLOB_GINTMSK_SOFMSK_E_MSK 0x0
6193 /*
6194  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_SOFMSK
6195  *
6196  * No Mask Start of Frame
6197  */
6198 #define ALT_USB_GLOB_GINTMSK_SOFMSK_E_NOMSK 0x1
6199 
6200 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */
6201 #define ALT_USB_GLOB_GINTMSK_SOFMSK_LSB 3
6202 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */
6203 #define ALT_USB_GLOB_GINTMSK_SOFMSK_MSB 3
6204 /* The width in bits of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */
6205 #define ALT_USB_GLOB_GINTMSK_SOFMSK_WIDTH 1
6206 /* The mask used to set the ALT_USB_GLOB_GINTMSK_SOFMSK register field value. */
6207 #define ALT_USB_GLOB_GINTMSK_SOFMSK_SET_MSK 0x00000008
6208 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_SOFMSK register field value. */
6209 #define ALT_USB_GLOB_GINTMSK_SOFMSK_CLR_MSK 0xfffffff7
6210 /* The reset value of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */
6211 #define ALT_USB_GLOB_GINTMSK_SOFMSK_RESET 0x0
6212 /* Extracts the ALT_USB_GLOB_GINTMSK_SOFMSK field value from a register. */
6213 #define ALT_USB_GLOB_GINTMSK_SOFMSK_GET(value) (((value) & 0x00000008) >> 3)
6214 /* Produces a ALT_USB_GLOB_GINTMSK_SOFMSK register field value suitable for setting the register. */
6215 #define ALT_USB_GLOB_GINTMSK_SOFMSK_SET(value) (((value) << 3) & 0x00000008)
6216 
6217 /*
6218  * Field : rxflvlmsk
6219  *
6220  * Mode: Host and Device
6221  *
6222  * Receive FIFO Non-Empty Mask (RxFLvlMsk)
6223  *
6224  * Field Enumeration Values:
6225  *
6226  * Enum | Value | Description
6227  * :---------------------------------------|:------|:-------------------------------
6228  * ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_MSK | 0x0 | Receive FIFO Non-Empty Mask
6229  * ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_NOMSK | 0x1 | No maks Receive FIFO Non-Empty
6230  *
6231  * Field Access Macros:
6232  *
6233  */
6234 /*
6235  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_RXFLVLMSK
6236  *
6237  * Receive FIFO Non-Empty Mask
6238  */
6239 #define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_MSK 0x0
6240 /*
6241  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_RXFLVLMSK
6242  *
6243  * No maks Receive FIFO Non-Empty
6244  */
6245 #define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_NOMSK 0x1
6246 
6247 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */
6248 #define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_LSB 4
6249 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */
6250 #define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_MSB 4
6251 /* The width in bits of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */
6252 #define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_WIDTH 1
6253 /* The mask used to set the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field value. */
6254 #define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_SET_MSK 0x00000010
6255 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field value. */
6256 #define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_CLR_MSK 0xffffffef
6257 /* The reset value of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */
6258 #define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_RESET 0x0
6259 /* Extracts the ALT_USB_GLOB_GINTMSK_RXFLVLMSK field value from a register. */
6260 #define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_GET(value) (((value) & 0x00000010) >> 4)
6261 /* Produces a ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field value suitable for setting the register. */
6262 #define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_SET(value) (((value) << 4) & 0x00000010)
6263 
6264 /*
6265  * Field : ginnakeffmsk
6266  *
6267  * Mode: Device only
6268  *
6269  * Global Non-periodic IN NAK Effective Mask (GINNakEffMsk)
6270  *
6271  * Field Enumeration Values:
6272  *
6273  * Enum | Value | Description
6274  * :------------------------------------------|:------|:---------------------------------------------
6275  * ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_MSK | 0x0 | Global Non-periodic IN NAK Effective Mask
6276  * ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_NOMSK | 0x1 | No mask Global Non-periodic IN NAK Effective
6277  *
6278  * Field Access Macros:
6279  *
6280  */
6281 /*
6282  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK
6283  *
6284  * Global Non-periodic IN NAK Effective Mask
6285  */
6286 #define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_MSK 0x0
6287 /*
6288  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK
6289  *
6290  * No mask Global Non-periodic IN NAK Effective
6291  */
6292 #define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_NOMSK 0x1
6293 
6294 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */
6295 #define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_LSB 6
6296 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */
6297 #define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_MSB 6
6298 /* The width in bits of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */
6299 #define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_WIDTH 1
6300 /* The mask used to set the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field value. */
6301 #define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_SET_MSK 0x00000040
6302 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field value. */
6303 #define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_CLR_MSK 0xffffffbf
6304 /* The reset value of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */
6305 #define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_RESET 0x0
6306 /* Extracts the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK field value from a register. */
6307 #define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_GET(value) (((value) & 0x00000040) >> 6)
6308 /* Produces a ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field value suitable for setting the register. */
6309 #define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_SET(value) (((value) << 6) & 0x00000040)
6310 
6311 /*
6312  * Field : goutnakeffmsk
6313  *
6314  * Mode: Device only
6315  *
6316  * Global OUT NAK Effective Mask (GOUTNakEffMsk)
6317  *
6318  * Field Enumeration Values:
6319  *
6320  * Enum | Value | Description
6321  * :--------------------------------------------|:------|:---------------------------------
6322  * ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_MSK | 0x0 | Global OUT NAK Effective Mask
6323  * ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_NOMAKS | 0x1 | No mask Global OUT NAK Effective
6324  *
6325  * Field Access Macros:
6326  *
6327  */
6328 /*
6329  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK
6330  *
6331  * Global OUT NAK Effective Mask
6332  */
6333 #define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_MSK 0x0
6334 /*
6335  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK
6336  *
6337  * No mask Global OUT NAK Effective
6338  */
6339 #define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_NOMAKS 0x1
6340 
6341 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */
6342 #define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_LSB 7
6343 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */
6344 #define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_MSB 7
6345 /* The width in bits of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */
6346 #define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_WIDTH 1
6347 /* The mask used to set the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field value. */
6348 #define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_SET_MSK 0x00000080
6349 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field value. */
6350 #define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_CLR_MSK 0xffffff7f
6351 /* The reset value of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */
6352 #define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_RESET 0x0
6353 /* Extracts the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK field value from a register. */
6354 #define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_GET(value) (((value) & 0x00000080) >> 7)
6355 /* Produces a ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field value suitable for setting the register. */
6356 #define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_SET(value) (((value) << 7) & 0x00000080)
6357 
6358 /*
6359  * Field : erlysuspmsk
6360  *
6361  * Mode: Device only
6362  *
6363  * Early Suspend Mask (ErlySuspMsk)
6364  *
6365  * Field Enumeration Values:
6366  *
6367  * Enum | Value | Description
6368  * :-----------------------------------------|:------|:---------------------------
6369  * ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_MSK | 0x0 | Early Suspend Mask
6370  * ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_NOMSK | 0x1 | No mask Early Suspend Mask
6371  *
6372  * Field Access Macros:
6373  *
6374  */
6375 /*
6376  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK
6377  *
6378  * Early Suspend Mask
6379  */
6380 #define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_MSK 0x0
6381 /*
6382  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK
6383  *
6384  * No mask Early Suspend Mask
6385  */
6386 #define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_NOMSK 0x1
6387 
6388 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */
6389 #define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_LSB 10
6390 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */
6391 #define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_MSB 10
6392 /* The width in bits of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */
6393 #define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_WIDTH 1
6394 /* The mask used to set the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field value. */
6395 #define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_SET_MSK 0x00000400
6396 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field value. */
6397 #define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_CLR_MSK 0xfffffbff
6398 /* The reset value of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */
6399 #define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_RESET 0x0
6400 /* Extracts the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK field value from a register. */
6401 #define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_GET(value) (((value) & 0x00000400) >> 10)
6402 /* Produces a ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field value suitable for setting the register. */
6403 #define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_SET(value) (((value) << 10) & 0x00000400)
6404 
6405 /*
6406  * Field : usbsuspmsk
6407  *
6408  * Mode: Device only
6409  *
6410  * USB Suspend Mask (USBSuspMsk)
6411  *
6412  * Field Enumeration Values:
6413  *
6414  * Enum | Value | Description
6415  * :----------------------------------------|:------|:---------------------
6416  * ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_MSK | 0x0 | USB Suspend Mask
6417  * ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_NOMSK | 0x1 | No mask USB Suspend
6418  *
6419  * Field Access Macros:
6420  *
6421  */
6422 /*
6423  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBSUSPMSK
6424  *
6425  * USB Suspend Mask
6426  */
6427 #define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_MSK 0x0
6428 /*
6429  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBSUSPMSK
6430  *
6431  * No mask USB Suspend
6432  */
6433 #define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_NOMSK 0x1
6434 
6435 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */
6436 #define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_LSB 11
6437 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */
6438 #define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_MSB 11
6439 /* The width in bits of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */
6440 #define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_WIDTH 1
6441 /* The mask used to set the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field value. */
6442 #define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_SET_MSK 0x00000800
6443 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field value. */
6444 #define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_CLR_MSK 0xfffff7ff
6445 /* The reset value of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */
6446 #define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_RESET 0x0
6447 /* Extracts the ALT_USB_GLOB_GINTMSK_USBSUSPMSK field value from a register. */
6448 #define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_GET(value) (((value) & 0x00000800) >> 11)
6449 /* Produces a ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field value suitable for setting the register. */
6450 #define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_SET(value) (((value) << 11) & 0x00000800)
6451 
6452 /*
6453  * Field : usbrstmsk
6454  *
6455  * Mode: Device only
6456  *
6457  * USB Reset Mask (USBRstMsk)
6458  *
6459  * Field Enumeration Values:
6460  *
6461  * Enum | Value | Description
6462  * :---------------------------------------|:------|:------------------
6463  * ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_MSK | 0x0 | USB Reset Mask
6464  * ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_NOMSK | 0x1 | No mask USB Reset
6465  *
6466  * Field Access Macros:
6467  *
6468  */
6469 /*
6470  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBRSTMSK
6471  *
6472  * USB Reset Mask
6473  */
6474 #define ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_MSK 0x0
6475 /*
6476  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBRSTMSK
6477  *
6478  * No mask USB Reset
6479  */
6480 #define ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_NOMSK 0x1
6481 
6482 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */
6483 #define ALT_USB_GLOB_GINTMSK_USBRSTMSK_LSB 12
6484 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */
6485 #define ALT_USB_GLOB_GINTMSK_USBRSTMSK_MSB 12
6486 /* The width in bits of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */
6487 #define ALT_USB_GLOB_GINTMSK_USBRSTMSK_WIDTH 1
6488 /* The mask used to set the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field value. */
6489 #define ALT_USB_GLOB_GINTMSK_USBRSTMSK_SET_MSK 0x00001000
6490 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field value. */
6491 #define ALT_USB_GLOB_GINTMSK_USBRSTMSK_CLR_MSK 0xffffefff
6492 /* The reset value of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */
6493 #define ALT_USB_GLOB_GINTMSK_USBRSTMSK_RESET 0x0
6494 /* Extracts the ALT_USB_GLOB_GINTMSK_USBRSTMSK field value from a register. */
6495 #define ALT_USB_GLOB_GINTMSK_USBRSTMSK_GET(value) (((value) & 0x00001000) >> 12)
6496 /* Produces a ALT_USB_GLOB_GINTMSK_USBRSTMSK register field value suitable for setting the register. */
6497 #define ALT_USB_GLOB_GINTMSK_USBRSTMSK_SET(value) (((value) << 12) & 0x00001000)
6498 
6499 /*
6500  * Field : enumdonemsk
6501  *
6502  * Mode: Device only
6503  *
6504  * Enumeration Done Mask (EnumDoneMsk)
6505  *
6506  * Field Enumeration Values:
6507  *
6508  * Enum | Value | Description
6509  * :-----------------------------------------|:------|:-------------------------
6510  * ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_MSK | 0x0 | Enumeration Done Mask
6511  * ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_NOMSK | 0x1 | No mask Enumeration Done
6512  *
6513  * Field Access Macros:
6514  *
6515  */
6516 /*
6517  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ENUMDONEMSK
6518  *
6519  * Enumeration Done Mask
6520  */
6521 #define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_MSK 0x0
6522 /*
6523  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ENUMDONEMSK
6524  *
6525  * No mask Enumeration Done
6526  */
6527 #define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_NOMSK 0x1
6528 
6529 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */
6530 #define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_LSB 13
6531 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */
6532 #define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_MSB 13
6533 /* The width in bits of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */
6534 #define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_WIDTH 1
6535 /* The mask used to set the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field value. */
6536 #define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_SET_MSK 0x00002000
6537 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field value. */
6538 #define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_CLR_MSK 0xffffdfff
6539 /* The reset value of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */
6540 #define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_RESET 0x0
6541 /* Extracts the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK field value from a register. */
6542 #define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_GET(value) (((value) & 0x00002000) >> 13)
6543 /* Produces a ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field value suitable for setting the register. */
6544 #define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_SET(value) (((value) << 13) & 0x00002000)
6545 
6546 /*
6547  * Field : isooutdropmsk
6548  *
6549  * Mode: Device only
6550  *
6551  * Isochronous OUT Packet Dropped Interrupt Mask
6552  *
6553  * (ISOOutDropMsk)
6554  *
6555  * Field Enumeration Values:
6556  *
6557  * Enum | Value | Description
6558  * :-------------------------------------------|:------|:-------------------------------------------------
6559  * ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_MSK | 0x0 | Isochronous OUT Packet Dropped Interrupt Mask
6560  * ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_NOMSK | 0x1 | No mask Isochronous OUT Packet Dropped Interrupt
6561  *
6562  * Field Access Macros:
6563  *
6564  */
6565 /*
6566  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK
6567  *
6568  * Isochronous OUT Packet Dropped Interrupt Mask
6569  */
6570 #define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_MSK 0x0
6571 /*
6572  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK
6573  *
6574  * No mask Isochronous OUT Packet Dropped Interrupt
6575  */
6576 #define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_NOMSK 0x1
6577 
6578 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */
6579 #define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_LSB 14
6580 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */
6581 #define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_MSB 14
6582 /* The width in bits of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */
6583 #define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_WIDTH 1
6584 /* The mask used to set the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field value. */
6585 #define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_SET_MSK 0x00004000
6586 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field value. */
6587 #define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_CLR_MSK 0xffffbfff
6588 /* The reset value of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */
6589 #define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_RESET 0x0
6590 /* Extracts the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK field value from a register. */
6591 #define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_GET(value) (((value) & 0x00004000) >> 14)
6592 /* Produces a ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field value suitable for setting the register. */
6593 #define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_SET(value) (((value) << 14) & 0x00004000)
6594 
6595 /*
6596  * Field : eopfmsk
6597  *
6598  * Mode: Device only
6599  *
6600  * End of Periodic Frame Interrupt Mask (EOPFMsk)
6601  *
6602  * Field Enumeration Values:
6603  *
6604  * Enum | Value | Description
6605  * :-------------------------------------|:------|:----------------------------------------
6606  * ALT_USB_GLOB_GINTMSK_EOPFMSK_E_MSK | 0x0 | End of Periodic Frame Interrupt Mask
6607  * ALT_USB_GLOB_GINTMSK_EOPFMSK_E_NOMSK | 0x1 | No mask End of Periodic Frame Interrupt
6608  *
6609  * Field Access Macros:
6610  *
6611  */
6612 /*
6613  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_EOPFMSK
6614  *
6615  * End of Periodic Frame Interrupt Mask
6616  */
6617 #define ALT_USB_GLOB_GINTMSK_EOPFMSK_E_MSK 0x0
6618 /*
6619  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_EOPFMSK
6620  *
6621  * No mask End of Periodic Frame Interrupt
6622  */
6623 #define ALT_USB_GLOB_GINTMSK_EOPFMSK_E_NOMSK 0x1
6624 
6625 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */
6626 #define ALT_USB_GLOB_GINTMSK_EOPFMSK_LSB 15
6627 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */
6628 #define ALT_USB_GLOB_GINTMSK_EOPFMSK_MSB 15
6629 /* The width in bits of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */
6630 #define ALT_USB_GLOB_GINTMSK_EOPFMSK_WIDTH 1
6631 /* The mask used to set the ALT_USB_GLOB_GINTMSK_EOPFMSK register field value. */
6632 #define ALT_USB_GLOB_GINTMSK_EOPFMSK_SET_MSK 0x00008000
6633 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_EOPFMSK register field value. */
6634 #define ALT_USB_GLOB_GINTMSK_EOPFMSK_CLR_MSK 0xffff7fff
6635 /* The reset value of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */
6636 #define ALT_USB_GLOB_GINTMSK_EOPFMSK_RESET 0x0
6637 /* Extracts the ALT_USB_GLOB_GINTMSK_EOPFMSK field value from a register. */
6638 #define ALT_USB_GLOB_GINTMSK_EOPFMSK_GET(value) (((value) & 0x00008000) >> 15)
6639 /* Produces a ALT_USB_GLOB_GINTMSK_EOPFMSK register field value suitable for setting the register. */
6640 #define ALT_USB_GLOB_GINTMSK_EOPFMSK_SET(value) (((value) << 15) & 0x00008000)
6641 
6642 /*
6643  * Field : epmismsk
6644  *
6645  * Mode: Device only
6646  *
6647  * Endpoint Mismatch Interrupt Mask (EPMisMsk)
6648  *
6649  * Field Enumeration Values:
6650  *
6651  * Enum | Value | Description
6652  * :--------------------------------------|:------|:------------------------------------
6653  * ALT_USB_GLOB_GINTMSK_EPMISMSK_E_MSK | 0x0 | Endpoint Mismatch Interrupt Mask
6654  * ALT_USB_GLOB_GINTMSK_EPMISMSK_E_NOMSK | 0x1 | No mask Endpoint Mismatch Interrupt
6655  *
6656  * Field Access Macros:
6657  *
6658  */
6659 /*
6660  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_EPMISMSK
6661  *
6662  * Endpoint Mismatch Interrupt Mask
6663  */
6664 #define ALT_USB_GLOB_GINTMSK_EPMISMSK_E_MSK 0x0
6665 /*
6666  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_EPMISMSK
6667  *
6668  * No mask Endpoint Mismatch Interrupt
6669  */
6670 #define ALT_USB_GLOB_GINTMSK_EPMISMSK_E_NOMSK 0x1
6671 
6672 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */
6673 #define ALT_USB_GLOB_GINTMSK_EPMISMSK_LSB 17
6674 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */
6675 #define ALT_USB_GLOB_GINTMSK_EPMISMSK_MSB 17
6676 /* The width in bits of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */
6677 #define ALT_USB_GLOB_GINTMSK_EPMISMSK_WIDTH 1
6678 /* The mask used to set the ALT_USB_GLOB_GINTMSK_EPMISMSK register field value. */
6679 #define ALT_USB_GLOB_GINTMSK_EPMISMSK_SET_MSK 0x00020000
6680 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_EPMISMSK register field value. */
6681 #define ALT_USB_GLOB_GINTMSK_EPMISMSK_CLR_MSK 0xfffdffff
6682 /* The reset value of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */
6683 #define ALT_USB_GLOB_GINTMSK_EPMISMSK_RESET 0x0
6684 /* Extracts the ALT_USB_GLOB_GINTMSK_EPMISMSK field value from a register. */
6685 #define ALT_USB_GLOB_GINTMSK_EPMISMSK_GET(value) (((value) & 0x00020000) >> 17)
6686 /* Produces a ALT_USB_GLOB_GINTMSK_EPMISMSK register field value suitable for setting the register. */
6687 #define ALT_USB_GLOB_GINTMSK_EPMISMSK_SET(value) (((value) << 17) & 0x00020000)
6688 
6689 /*
6690  * Field : iepintmsk
6691  *
6692  * Mode: Device only
6693  *
6694  * IN Endpoints Interrupt Mask (IEPIntMsk)
6695  *
6696  * Field Enumeration Values:
6697  *
6698  * Enum | Value | Description
6699  * :----------------------------------------|:------|:-------------------------------
6700  * ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_MSK | 0x0 | IN Endpoints Interrupt Mask
6701  * ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_NOMAKS | 0x1 | No mask IN Endpoints Interrupt
6702  *
6703  * Field Access Macros:
6704  *
6705  */
6706 /*
6707  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_IEPINTMSK
6708  *
6709  * IN Endpoints Interrupt Mask
6710  */
6711 #define ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_MSK 0x0
6712 /*
6713  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_IEPINTMSK
6714  *
6715  * No mask IN Endpoints Interrupt
6716  */
6717 #define ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_NOMAKS 0x1
6718 
6719 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */
6720 #define ALT_USB_GLOB_GINTMSK_IEPINTMSK_LSB 18
6721 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */
6722 #define ALT_USB_GLOB_GINTMSK_IEPINTMSK_MSB 18
6723 /* The width in bits of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */
6724 #define ALT_USB_GLOB_GINTMSK_IEPINTMSK_WIDTH 1
6725 /* The mask used to set the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field value. */
6726 #define ALT_USB_GLOB_GINTMSK_IEPINTMSK_SET_MSK 0x00040000
6727 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field value. */
6728 #define ALT_USB_GLOB_GINTMSK_IEPINTMSK_CLR_MSK 0xfffbffff
6729 /* The reset value of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */
6730 #define ALT_USB_GLOB_GINTMSK_IEPINTMSK_RESET 0x0
6731 /* Extracts the ALT_USB_GLOB_GINTMSK_IEPINTMSK field value from a register. */
6732 #define ALT_USB_GLOB_GINTMSK_IEPINTMSK_GET(value) (((value) & 0x00040000) >> 18)
6733 /* Produces a ALT_USB_GLOB_GINTMSK_IEPINTMSK register field value suitable for setting the register. */
6734 #define ALT_USB_GLOB_GINTMSK_IEPINTMSK_SET(value) (((value) << 18) & 0x00040000)
6735 
6736 /*
6737  * Field : oepintmsk
6738  *
6739  * Mode: Device only
6740  *
6741  * OUT Endpoints Interrupt Mask (OEPIntMsk)
6742  *
6743  * Field Enumeration Values:
6744  *
6745  * Enum | Value | Description
6746  * :---------------------------------------|:------|:--------------------------------
6747  * ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_MSK | 0x0 | OUT Endpoints Interrupt Mask
6748  * ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_NOMSK | 0x1 | No mask OUT Endpoints Interrupt
6749  *
6750  * Field Access Macros:
6751  *
6752  */
6753 /*
6754  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_OEPINTMSK
6755  *
6756  * OUT Endpoints Interrupt Mask
6757  */
6758 #define ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_MSK 0x0
6759 /*
6760  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_OEPINTMSK
6761  *
6762  * No mask OUT Endpoints Interrupt
6763  */
6764 #define ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_NOMSK 0x1
6765 
6766 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */
6767 #define ALT_USB_GLOB_GINTMSK_OEPINTMSK_LSB 19
6768 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */
6769 #define ALT_USB_GLOB_GINTMSK_OEPINTMSK_MSB 19
6770 /* The width in bits of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */
6771 #define ALT_USB_GLOB_GINTMSK_OEPINTMSK_WIDTH 1
6772 /* The mask used to set the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field value. */
6773 #define ALT_USB_GLOB_GINTMSK_OEPINTMSK_SET_MSK 0x00080000
6774 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field value. */
6775 #define ALT_USB_GLOB_GINTMSK_OEPINTMSK_CLR_MSK 0xfff7ffff
6776 /* The reset value of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */
6777 #define ALT_USB_GLOB_GINTMSK_OEPINTMSK_RESET 0x0
6778 /* Extracts the ALT_USB_GLOB_GINTMSK_OEPINTMSK field value from a register. */
6779 #define ALT_USB_GLOB_GINTMSK_OEPINTMSK_GET(value) (((value) & 0x00080000) >> 19)
6780 /* Produces a ALT_USB_GLOB_GINTMSK_OEPINTMSK register field value suitable for setting the register. */
6781 #define ALT_USB_GLOB_GINTMSK_OEPINTMSK_SET(value) (((value) << 19) & 0x00080000)
6782 
6783 /*
6784  * Field : incompisoinmsk
6785  *
6786  * Mode: Device only
6787  *
6788  * Incomplete Isochronous IN Transfer Mask (incompISOINMsk)
6789  *
6790  * Field Enumeration Values:
6791  *
6792  * Enum | Value | Description
6793  * :--------------------------------------------|:------|:-------------------------------------------
6794  * ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_MSK | 0x0 | Incomplete Isochronous IN Transfer Mask
6795  * ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_NOMSK | 0x1 | No mask Incomplete Isochronous IN Transfer
6796  *
6797  * Field Access Macros:
6798  *
6799  */
6800 /*
6801  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK
6802  *
6803  * Incomplete Isochronous IN Transfer Mask
6804  */
6805 #define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_MSK 0x0
6806 /*
6807  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK
6808  *
6809  * No mask Incomplete Isochronous IN Transfer
6810  */
6811 #define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_NOMSK 0x1
6812 
6813 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */
6814 #define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_LSB 20
6815 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */
6816 #define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_MSB 20
6817 /* The width in bits of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */
6818 #define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_WIDTH 1
6819 /* The mask used to set the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field value. */
6820 #define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_SET_MSK 0x00100000
6821 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field value. */
6822 #define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_CLR_MSK 0xffefffff
6823 /* The reset value of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */
6824 #define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_RESET 0x0
6825 /* Extracts the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK field value from a register. */
6826 #define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_GET(value) (((value) & 0x00100000) >> 20)
6827 /* Produces a ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field value suitable for setting the register. */
6828 #define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_SET(value) (((value) << 20) & 0x00100000)
6829 
6830 /*
6831  * Field : incomplpmsk
6832  *
6833  * Mode: Host only
6834  *
6835  * Incomplete Periodic Transfer Mask (incomplPMsk)
6836  *
6837  * Mode: Device only
6838  *
6839  * Incomplete Isochronous OUT Transfer Interrupt Mask (incompISOOUTMsk)
6840  *
6841  * Field Enumeration Values:
6842  *
6843  * Enum | Value | Description
6844  * :-----------------------------------------|:------|:-------------------------------------
6845  * ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_MSK | 0x0 | Incomplete Periodic Transfer Mask
6846  * ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_NOMSK | 0x1 | No mask Incomplete Periodic Transfer
6847  *
6848  * Field Access Macros:
6849  *
6850  */
6851 /*
6852  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPLPMSK
6853  *
6854  * Incomplete Periodic Transfer Mask
6855  */
6856 #define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_MSK 0x0
6857 /*
6858  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPLPMSK
6859  *
6860  * No mask Incomplete Periodic Transfer
6861  */
6862 #define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_NOMSK 0x1
6863 
6864 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */
6865 #define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_LSB 21
6866 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */
6867 #define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_MSB 21
6868 /* The width in bits of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */
6869 #define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_WIDTH 1
6870 /* The mask used to set the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field value. */
6871 #define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_SET_MSK 0x00200000
6872 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field value. */
6873 #define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_CLR_MSK 0xffdfffff
6874 /* The reset value of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */
6875 #define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_RESET 0x0
6876 /* Extracts the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK field value from a register. */
6877 #define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_GET(value) (((value) & 0x00200000) >> 21)
6878 /* Produces a ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field value suitable for setting the register. */
6879 #define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_SET(value) (((value) << 21) & 0x00200000)
6880 
6881 /*
6882  * Field : fetsuspmsk
6883  *
6884  * Mode: Device only
6885  *
6886  * Data Fetch Suspended Mask (FetSuspMsk)
6887  *
6888  * Field Enumeration Values:
6889  *
6890  * Enum | Value | Description
6891  * :----------------------------------------|:------|:-----------------------------
6892  * ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_MSK | 0x0 | Data Fetch Suspended Mask
6893  * ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_NOMSK | 0x1 | No mask Data Fetch Suspended
6894  *
6895  * Field Access Macros:
6896  *
6897  */
6898 /*
6899  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_FETSUSPMSK
6900  *
6901  * Data Fetch Suspended Mask
6902  */
6903 #define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_MSK 0x0
6904 /*
6905  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_FETSUSPMSK
6906  *
6907  * No mask Data Fetch Suspended
6908  */
6909 #define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_NOMSK 0x1
6910 
6911 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */
6912 #define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_LSB 22
6913 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */
6914 #define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_MSB 22
6915 /* The width in bits of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */
6916 #define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_WIDTH 1
6917 /* The mask used to set the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field value. */
6918 #define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_SET_MSK 0x00400000
6919 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field value. */
6920 #define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_CLR_MSK 0xffbfffff
6921 /* The reset value of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */
6922 #define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_RESET 0x0
6923 /* Extracts the ALT_USB_GLOB_GINTMSK_FETSUSPMSK field value from a register. */
6924 #define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_GET(value) (((value) & 0x00400000) >> 22)
6925 /* Produces a ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field value suitable for setting the register. */
6926 #define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_SET(value) (((value) << 22) & 0x00400000)
6927 
6928 /*
6929  * Field : resetdetmsk
6930  *
6931  * Mode: Device only
6932  *
6933  * Reset detected Interrupt Mask (ResetDetMsk)
6934  *
6935  * Field Enumeration Values:
6936  *
6937  * Enum | Value | Description
6938  * :---------------------------------------|:------|:---------------------------------
6939  * ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_MSK | 0x0 | Reset detected Interrupt Mask
6940  * ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_NOMSK | 0x1 | No mask Reset detected Interrupt
6941  *
6942  * Field Access Macros:
6943  *
6944  */
6945 /*
6946  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_RSTDETMSK
6947  *
6948  * Reset detected Interrupt Mask
6949  */
6950 #define ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_MSK 0x0
6951 /*
6952  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_RSTDETMSK
6953  *
6954  * No mask Reset detected Interrupt
6955  */
6956 #define ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_NOMSK 0x1
6957 
6958 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */
6959 #define ALT_USB_GLOB_GINTMSK_RSTDETMSK_LSB 23
6960 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */
6961 #define ALT_USB_GLOB_GINTMSK_RSTDETMSK_MSB 23
6962 /* The width in bits of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */
6963 #define ALT_USB_GLOB_GINTMSK_RSTDETMSK_WIDTH 1
6964 /* The mask used to set the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field value. */
6965 #define ALT_USB_GLOB_GINTMSK_RSTDETMSK_SET_MSK 0x00800000
6966 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field value. */
6967 #define ALT_USB_GLOB_GINTMSK_RSTDETMSK_CLR_MSK 0xff7fffff
6968 /* The reset value of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */
6969 #define ALT_USB_GLOB_GINTMSK_RSTDETMSK_RESET 0x0
6970 /* Extracts the ALT_USB_GLOB_GINTMSK_RSTDETMSK field value from a register. */
6971 #define ALT_USB_GLOB_GINTMSK_RSTDETMSK_GET(value) (((value) & 0x00800000) >> 23)
6972 /* Produces a ALT_USB_GLOB_GINTMSK_RSTDETMSK register field value suitable for setting the register. */
6973 #define ALT_USB_GLOB_GINTMSK_RSTDETMSK_SET(value) (((value) << 23) & 0x00800000)
6974 
6975 /*
6976  * Field : prtintmsk
6977  *
6978  * Mode: Host only
6979  *
6980  * Host Port Interrupt Mask (PrtIntMsk)
6981  *
6982  * Field Enumeration Values:
6983  *
6984  * Enum | Value | Description
6985  * :---------------------------------------|:------|:----------------------------
6986  * ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_MSK | 0x0 | Host Port Interrupt Mask
6987  * ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_NOMSK | 0x1 | No mask Host Port Interrupt
6988  *
6989  * Field Access Macros:
6990  *
6991  */
6992 /*
6993  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_PRTINTMSK
6994  *
6995  * Host Port Interrupt Mask
6996  */
6997 #define ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_MSK 0x0
6998 /*
6999  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_PRTINTMSK
7000  *
7001  * No mask Host Port Interrupt
7002  */
7003 #define ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_NOMSK 0x1
7004 
7005 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */
7006 #define ALT_USB_GLOB_GINTMSK_PRTINTMSK_LSB 24
7007 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */
7008 #define ALT_USB_GLOB_GINTMSK_PRTINTMSK_MSB 24
7009 /* The width in bits of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */
7010 #define ALT_USB_GLOB_GINTMSK_PRTINTMSK_WIDTH 1
7011 /* The mask used to set the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field value. */
7012 #define ALT_USB_GLOB_GINTMSK_PRTINTMSK_SET_MSK 0x01000000
7013 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field value. */
7014 #define ALT_USB_GLOB_GINTMSK_PRTINTMSK_CLR_MSK 0xfeffffff
7015 /* The reset value of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */
7016 #define ALT_USB_GLOB_GINTMSK_PRTINTMSK_RESET 0x0
7017 /* Extracts the ALT_USB_GLOB_GINTMSK_PRTINTMSK field value from a register. */
7018 #define ALT_USB_GLOB_GINTMSK_PRTINTMSK_GET(value) (((value) & 0x01000000) >> 24)
7019 /* Produces a ALT_USB_GLOB_GINTMSK_PRTINTMSK register field value suitable for setting the register. */
7020 #define ALT_USB_GLOB_GINTMSK_PRTINTMSK_SET(value) (((value) << 24) & 0x01000000)
7021 
7022 /*
7023  * Field : hchintmsk
7024  *
7025  * Mode: Host only
7026  *
7027  * Host Channels Interrupt Mask (HChIntMsk)
7028  *
7029  * Field Enumeration Values:
7030  *
7031  * Enum | Value | Description
7032  * :---------------------------------------|:------|:--------------------------------
7033  * ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_MSK | 0x0 | Host Channels Interrupt Mask
7034  * ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_NOMSK | 0x1 | No mask Host Channels Interrupt
7035  *
7036  * Field Access Macros:
7037  *
7038  */
7039 /*
7040  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_HCHINTMSK
7041  *
7042  * Host Channels Interrupt Mask
7043  */
7044 #define ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_MSK 0x0
7045 /*
7046  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_HCHINTMSK
7047  *
7048  * No mask Host Channels Interrupt
7049  */
7050 #define ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_NOMSK 0x1
7051 
7052 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */
7053 #define ALT_USB_GLOB_GINTMSK_HCHINTMSK_LSB 25
7054 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */
7055 #define ALT_USB_GLOB_GINTMSK_HCHINTMSK_MSB 25
7056 /* The width in bits of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */
7057 #define ALT_USB_GLOB_GINTMSK_HCHINTMSK_WIDTH 1
7058 /* The mask used to set the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field value. */
7059 #define ALT_USB_GLOB_GINTMSK_HCHINTMSK_SET_MSK 0x02000000
7060 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field value. */
7061 #define ALT_USB_GLOB_GINTMSK_HCHINTMSK_CLR_MSK 0xfdffffff
7062 /* The reset value of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */
7063 #define ALT_USB_GLOB_GINTMSK_HCHINTMSK_RESET 0x0
7064 /* Extracts the ALT_USB_GLOB_GINTMSK_HCHINTMSK field value from a register. */
7065 #define ALT_USB_GLOB_GINTMSK_HCHINTMSK_GET(value) (((value) & 0x02000000) >> 25)
7066 /* Produces a ALT_USB_GLOB_GINTMSK_HCHINTMSK register field value suitable for setting the register. */
7067 #define ALT_USB_GLOB_GINTMSK_HCHINTMSK_SET(value) (((value) << 25) & 0x02000000)
7068 
7069 /*
7070  * Field : ptxfempmsk
7071  *
7072  * Mode: Host only
7073  *
7074  * Periodic TxFIFO Empty Mask (PTxFEmpMsk)
7075  *
7076  * Field Enumeration Values:
7077  *
7078  * Enum | Value | Description
7079  * :----------------------------------------|:------|:------------------------------
7080  * ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_MSK | 0x0 | Periodic TxFIFO Empty Mask
7081  * ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_NOMSK | 0x1 | No mask Periodic TxFIFO Empty
7082  *
7083  * Field Access Macros:
7084  *
7085  */
7086 /*
7087  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_PTXFEMPMSK
7088  *
7089  * Periodic TxFIFO Empty Mask
7090  */
7091 #define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_MSK 0x0
7092 /*
7093  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_PTXFEMPMSK
7094  *
7095  * No mask Periodic TxFIFO Empty
7096  */
7097 #define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_NOMSK 0x1
7098 
7099 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */
7100 #define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_LSB 26
7101 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */
7102 #define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_MSB 26
7103 /* The width in bits of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */
7104 #define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_WIDTH 1
7105 /* The mask used to set the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field value. */
7106 #define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_SET_MSK 0x04000000
7107 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field value. */
7108 #define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_CLR_MSK 0xfbffffff
7109 /* The reset value of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */
7110 #define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_RESET 0x0
7111 /* Extracts the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK field value from a register. */
7112 #define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_GET(value) (((value) & 0x04000000) >> 26)
7113 /* Produces a ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field value suitable for setting the register. */
7114 #define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_SET(value) (((value) << 26) & 0x04000000)
7115 
7116 /*
7117  * Field : conidstschngmsk
7118  *
7119  * Mode: Host and Device
7120  *
7121  * Connector ID Status Change Mask (ConIDStsChngMsk)
7122  *
7123  * Field Enumeration Values:
7124  *
7125  * Enum | Value | Description
7126  * :---------------------------------------------|:------|:-----------------------------------
7127  * ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_MSK | 0x0 | Connector ID Status Change Mask
7128  * ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_NOMSK | 0x1 | No mask Connector ID Status Change
7129  *
7130  * Field Access Macros:
7131  *
7132  */
7133 /*
7134  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK
7135  *
7136  * Connector ID Status Change Mask
7137  */
7138 #define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_MSK 0x0
7139 /*
7140  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK
7141  *
7142  * No mask Connector ID Status Change
7143  */
7144 #define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_NOMSK 0x1
7145 
7146 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */
7147 #define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_LSB 28
7148 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */
7149 #define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_MSB 28
7150 /* The width in bits of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */
7151 #define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_WIDTH 1
7152 /* The mask used to set the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field value. */
7153 #define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_SET_MSK 0x10000000
7154 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field value. */
7155 #define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_CLR_MSK 0xefffffff
7156 /* The reset value of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */
7157 #define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_RESET 0x0
7158 /* Extracts the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK field value from a register. */
7159 #define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_GET(value) (((value) & 0x10000000) >> 28)
7160 /* Produces a ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field value suitable for setting the register. */
7161 #define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_SET(value) (((value) << 28) & 0x10000000)
7162 
7163 /*
7164  * Field : disconnintmsk
7165  *
7166  * Mode: Host and Device
7167  *
7168  * Disconnect Detected Interrupt Mask (DisconnIntMsk)
7169  *
7170  * Field Enumeration Values:
7171  *
7172  * Enum | Value | Description
7173  * :-------------------------------------------|:------|:--------------------------------------
7174  * ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_MSK | 0x0 | Disconnect Detected Interrupt Mask
7175  * ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_NOMSK | 0x1 | No mask Disconnect Detected Interrupt
7176  *
7177  * Field Access Macros:
7178  *
7179  */
7180 /*
7181  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_DISCONNINTMSK
7182  *
7183  * Disconnect Detected Interrupt Mask
7184  */
7185 #define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_MSK 0x0
7186 /*
7187  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_DISCONNINTMSK
7188  *
7189  * No mask Disconnect Detected Interrupt
7190  */
7191 #define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_NOMSK 0x1
7192 
7193 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */
7194 #define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_LSB 29
7195 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */
7196 #define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_MSB 29
7197 /* The width in bits of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */
7198 #define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_WIDTH 1
7199 /* The mask used to set the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field value. */
7200 #define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_SET_MSK 0x20000000
7201 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field value. */
7202 #define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_CLR_MSK 0xdfffffff
7203 /* The reset value of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */
7204 #define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_RESET 0x0
7205 /* Extracts the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK field value from a register. */
7206 #define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_GET(value) (((value) & 0x20000000) >> 29)
7207 /* Produces a ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field value suitable for setting the register. */
7208 #define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_SET(value) (((value) << 29) & 0x20000000)
7209 
7210 /*
7211  * Field : sessreqintmsk
7212  *
7213  * Mode: Host and Device
7214  *
7215  * Session Request/New Session Detected Interrupt Mask
7216  *
7217  * (SessReqIntMsk)
7218  *
7219  * Field Enumeration Values:
7220  *
7221  * Enum | Value | Description
7222  * :-------------------------------------------|:------|:-----------------------------------------------
7223  * ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_MSK | 0x0 | Session Request New Session Detected Interrupt
7224  * : | | Mask
7225  * ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_NOMSK | 0x1 | No mask Session RequestNew Session Detected
7226  * : | | Interrupt
7227  *
7228  * Field Access Macros:
7229  *
7230  */
7231 /*
7232  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_SESSREQINTMSK
7233  *
7234  * Session Request New Session Detected Interrupt Mask
7235  */
7236 #define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_MSK 0x0
7237 /*
7238  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_SESSREQINTMSK
7239  *
7240  * No mask Session RequestNew Session Detected Interrupt
7241  */
7242 #define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_NOMSK 0x1
7243 
7244 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */
7245 #define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_LSB 30
7246 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */
7247 #define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_MSB 30
7248 /* The width in bits of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */
7249 #define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_WIDTH 1
7250 /* The mask used to set the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field value. */
7251 #define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_SET_MSK 0x40000000
7252 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field value. */
7253 #define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_CLR_MSK 0xbfffffff
7254 /* The reset value of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */
7255 #define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_RESET 0x0
7256 /* Extracts the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK field value from a register. */
7257 #define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_GET(value) (((value) & 0x40000000) >> 30)
7258 /* Produces a ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field value suitable for setting the register. */
7259 #define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_SET(value) (((value) << 30) & 0x40000000)
7260 
7261 /*
7262  * Field : wkupintmsk
7263  *
7264  * Mode: Host and Device
7265  *
7266  * Resume/Remote Wakeup Detected Interrupt Mask
7267  *
7268  * The WakeUp bit is used for LPM state wake up in a way similar to that of wake up
7269  * in suspend state.
7270  *
7271  * (WkUpIntMsk)
7272  *
7273  * Field Enumeration Values:
7274  *
7275  * Enum | Value | Description
7276  * :----------------------------------------|:------|:-----------------------------------------------
7277  * ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_MSK | 0x0 | Resume Remote Wakeup Detected Interrupt Mask
7278  * ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_NOMSK | 0x1 | No maskResume Remote Wakeup Detected Interrupt
7279  *
7280  * Field Access Macros:
7281  *
7282  */
7283 /*
7284  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_WKUPINTMSK
7285  *
7286  * Resume Remote Wakeup Detected Interrupt Mask
7287  */
7288 #define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_MSK 0x0
7289 /*
7290  * Enumerated value for register field ALT_USB_GLOB_GINTMSK_WKUPINTMSK
7291  *
7292  * No maskResume Remote Wakeup Detected Interrupt
7293  */
7294 #define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_NOMSK 0x1
7295 
7296 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */
7297 #define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_LSB 31
7298 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */
7299 #define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_MSB 31
7300 /* The width in bits of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */
7301 #define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_WIDTH 1
7302 /* The mask used to set the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field value. */
7303 #define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_SET_MSK 0x80000000
7304 /* The mask used to clear the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field value. */
7305 #define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_CLR_MSK 0x7fffffff
7306 /* The reset value of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */
7307 #define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_RESET 0x0
7308 /* Extracts the ALT_USB_GLOB_GINTMSK_WKUPINTMSK field value from a register. */
7309 #define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_GET(value) (((value) & 0x80000000) >> 31)
7310 /* Produces a ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field value suitable for setting the register. */
7311 #define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_SET(value) (((value) << 31) & 0x80000000)
7312 
7313 #ifndef __ASSEMBLY__
7314 /*
7315  * WARNING: The C register and register group struct declarations are provided for
7316  * convenience and illustrative purposes. They should, however, be used with
7317  * caution as the C language standard provides no guarantees about the alignment or
7318  * atomicity of device memory accesses. The recommended practice for writing
7319  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7320  * alt_write_word() functions.
7321  *
7322  * The struct declaration for register ALT_USB_GLOB_GINTMSK.
7323  */
7324 struct ALT_USB_GLOB_GINTMSK_s
7325 {
7326  uint32_t : 1; /* *UNDEFINED* */
7327  uint32_t modemismsk : 1; /* ALT_USB_GLOB_GINTMSK_MODMISMSK */
7328  uint32_t otgintmsk : 1; /* ALT_USB_GLOB_GINTMSK_OTGINTMSK */
7329  uint32_t sofmsk : 1; /* ALT_USB_GLOB_GINTMSK_SOFMSK */
7330  uint32_t rxflvlmsk : 1; /* ALT_USB_GLOB_GINTMSK_RXFLVLMSK */
7331  uint32_t : 1; /* *UNDEFINED* */
7332  uint32_t ginnakeffmsk : 1; /* ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK */
7333  uint32_t goutnakeffmsk : 1; /* ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK */
7334  uint32_t : 2; /* *UNDEFINED* */
7335  uint32_t erlysuspmsk : 1; /* ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK */
7336  uint32_t usbsuspmsk : 1; /* ALT_USB_GLOB_GINTMSK_USBSUSPMSK */
7337  uint32_t usbrstmsk : 1; /* ALT_USB_GLOB_GINTMSK_USBRSTMSK */
7338  uint32_t enumdonemsk : 1; /* ALT_USB_GLOB_GINTMSK_ENUMDONEMSK */
7339  uint32_t isooutdropmsk : 1; /* ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK */
7340  uint32_t eopfmsk : 1; /* ALT_USB_GLOB_GINTMSK_EOPFMSK */
7341  uint32_t : 1; /* *UNDEFINED* */
7342  uint32_t epmismsk : 1; /* ALT_USB_GLOB_GINTMSK_EPMISMSK */
7343  uint32_t iepintmsk : 1; /* ALT_USB_GLOB_GINTMSK_IEPINTMSK */
7344  uint32_t oepintmsk : 1; /* ALT_USB_GLOB_GINTMSK_OEPINTMSK */
7345  uint32_t incompisoinmsk : 1; /* ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK */
7346  uint32_t incomplpmsk : 1; /* ALT_USB_GLOB_GINTMSK_INCOMPLPMSK */
7347  uint32_t fetsuspmsk : 1; /* ALT_USB_GLOB_GINTMSK_FETSUSPMSK */
7348  uint32_t resetdetmsk : 1; /* ALT_USB_GLOB_GINTMSK_RSTDETMSK */
7349  uint32_t prtintmsk : 1; /* ALT_USB_GLOB_GINTMSK_PRTINTMSK */
7350  uint32_t hchintmsk : 1; /* ALT_USB_GLOB_GINTMSK_HCHINTMSK */
7351  uint32_t ptxfempmsk : 1; /* ALT_USB_GLOB_GINTMSK_PTXFEMPMSK */
7352  uint32_t : 1; /* *UNDEFINED* */
7353  uint32_t conidstschngmsk : 1; /* ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK */
7354  uint32_t disconnintmsk : 1; /* ALT_USB_GLOB_GINTMSK_DISCONNINTMSK */
7355  uint32_t sessreqintmsk : 1; /* ALT_USB_GLOB_GINTMSK_SESSREQINTMSK */
7356  uint32_t wkupintmsk : 1; /* ALT_USB_GLOB_GINTMSK_WKUPINTMSK */
7357 };
7358 
7359 /* The typedef declaration for register ALT_USB_GLOB_GINTMSK. */
7360 typedef volatile struct ALT_USB_GLOB_GINTMSK_s ALT_USB_GLOB_GINTMSK_t;
7361 #endif /* __ASSEMBLY__ */
7362 
7363 /* The reset value of the ALT_USB_GLOB_GINTMSK register. */
7364 #define ALT_USB_GLOB_GINTMSK_RESET 0x00000000
7365 /* The byte offset of the ALT_USB_GLOB_GINTMSK register from the beginning of the component. */
7366 #define ALT_USB_GLOB_GINTMSK_OFST 0x18
7367 /* The address of the ALT_USB_GLOB_GINTMSK register. */
7368 #define ALT_USB_GLOB_GINTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GINTMSK_OFST))
7369 
7370 /*
7371  * Register : grxstsr
7372  *
7373  * Receive Status Debug Read Register
7374  *
7375  * Register Layout
7376  *
7377  * Bits | Access | Reset | Description
7378  * :--------|:-------|:------|:----------------------------
7379  * [3:0] | R | 0x0 | ALT_USB_GLOB_GRXSTSR_CHNUM
7380  * [14:4] | R | 0x0 | ALT_USB_GLOB_GRXSTSR_BCNT
7381  * [16:15] | R | 0x0 | ALT_USB_GLOB_GRXSTSR_DPID
7382  * [20:17] | R | 0x0 | ALT_USB_GLOB_GRXSTSR_PKTSTS
7383  * [24:21] | R | 0x0 | ALT_USB_GLOB_GRXSTSR_FN
7384  * [31:25] | ??? | 0x0 | *UNDEFINED*
7385  *
7386  */
7387 /*
7388  * Field : chnum
7389  *
7390  * Mode: Host only
7391  *
7392  * Channel Number (ChNum)
7393  *
7394  * Indicates the channel number to which the current received
7395  *
7396  * packet belongs.
7397  *
7398  * Mode: Device only
7399  *
7400  * Endpoint Number (EPNum)
7401  *
7402  * Indicates the endpoint number to which the current received
7403  *
7404  * packet belongs.
7405  *
7406  * Field Access Macros:
7407  *
7408  */
7409 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */
7410 #define ALT_USB_GLOB_GRXSTSR_CHNUM_LSB 0
7411 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */
7412 #define ALT_USB_GLOB_GRXSTSR_CHNUM_MSB 3
7413 /* The width in bits of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */
7414 #define ALT_USB_GLOB_GRXSTSR_CHNUM_WIDTH 4
7415 /* The mask used to set the ALT_USB_GLOB_GRXSTSR_CHNUM register field value. */
7416 #define ALT_USB_GLOB_GRXSTSR_CHNUM_SET_MSK 0x0000000f
7417 /* The mask used to clear the ALT_USB_GLOB_GRXSTSR_CHNUM register field value. */
7418 #define ALT_USB_GLOB_GRXSTSR_CHNUM_CLR_MSK 0xfffffff0
7419 /* The reset value of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */
7420 #define ALT_USB_GLOB_GRXSTSR_CHNUM_RESET 0x0
7421 /* Extracts the ALT_USB_GLOB_GRXSTSR_CHNUM field value from a register. */
7422 #define ALT_USB_GLOB_GRXSTSR_CHNUM_GET(value) (((value) & 0x0000000f) >> 0)
7423 /* Produces a ALT_USB_GLOB_GRXSTSR_CHNUM register field value suitable for setting the register. */
7424 #define ALT_USB_GLOB_GRXSTSR_CHNUM_SET(value) (((value) << 0) & 0x0000000f)
7425 
7426 /*
7427  * Field : bcnt
7428  *
7429  * Mode: Host only
7430  *
7431  * Byte Count (BCnt)
7432  *
7433  * Indicates the byte count of the received IN data packet.
7434  *
7435  * Mode: Device only
7436  *
7437  * Byte Count (BCnt)
7438  *
7439  * Indicates the byte count of the received data packet.
7440  *
7441  * Field Access Macros:
7442  *
7443  */
7444 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */
7445 #define ALT_USB_GLOB_GRXSTSR_BCNT_LSB 4
7446 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */
7447 #define ALT_USB_GLOB_GRXSTSR_BCNT_MSB 14
7448 /* The width in bits of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */
7449 #define ALT_USB_GLOB_GRXSTSR_BCNT_WIDTH 11
7450 /* The mask used to set the ALT_USB_GLOB_GRXSTSR_BCNT register field value. */
7451 #define ALT_USB_GLOB_GRXSTSR_BCNT_SET_MSK 0x00007ff0
7452 /* The mask used to clear the ALT_USB_GLOB_GRXSTSR_BCNT register field value. */
7453 #define ALT_USB_GLOB_GRXSTSR_BCNT_CLR_MSK 0xffff800f
7454 /* The reset value of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */
7455 #define ALT_USB_GLOB_GRXSTSR_BCNT_RESET 0x0
7456 /* Extracts the ALT_USB_GLOB_GRXSTSR_BCNT field value from a register. */
7457 #define ALT_USB_GLOB_GRXSTSR_BCNT_GET(value) (((value) & 0x00007ff0) >> 4)
7458 /* Produces a ALT_USB_GLOB_GRXSTSR_BCNT register field value suitable for setting the register. */
7459 #define ALT_USB_GLOB_GRXSTSR_BCNT_SET(value) (((value) << 4) & 0x00007ff0)
7460 
7461 /*
7462  * Field : dpid
7463  *
7464  * Mode: Host only
7465  *
7466  * Data PID (DPID)
7467  *
7468  * Indicates the Data PID of the received packet
7469  *
7470  * 2'b00: DATA0
7471  *
7472  * 2'b10: DATA1
7473  *
7474  * 2'b01: DATA2
7475  *
7476  * 2'b11: MDATA
7477  *
7478  * Mode: Device only
7479  *
7480  * Data PID (DPID)
7481  *
7482  * Indicates the Data PID of the received OUT data packet
7483  *
7484  * 2'b00: DATA0
7485  *
7486  * 2'b10: DATA1
7487  *
7488  * 2'b01: DATA2
7489  *
7490  * 2'b11: MDATA
7491  *
7492  * Field Enumeration Values:
7493  *
7494  * Enum | Value | Description
7495  * :----------------------------------|:------|:------------
7496  * ALT_USB_GLOB_GRXSTSR_DPID_E_DATA0 | 0x0 | DATA0
7497  * ALT_USB_GLOB_GRXSTSR_DPID_E_DATA2 | 0x1 | DATA2
7498  * ALT_USB_GLOB_GRXSTSR_DPID_E_DATA1 | 0x2 | DATA1
7499  * ALT_USB_GLOB_GRXSTSR_DPID_E_MDATA | 0x3 | MDATA
7500  *
7501  * Field Access Macros:
7502  *
7503  */
7504 /*
7505  * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID
7506  *
7507  * DATA0
7508  */
7509 #define ALT_USB_GLOB_GRXSTSR_DPID_E_DATA0 0x0
7510 /*
7511  * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID
7512  *
7513  * DATA2
7514  */
7515 #define ALT_USB_GLOB_GRXSTSR_DPID_E_DATA2 0x1
7516 /*
7517  * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID
7518  *
7519  * DATA1
7520  */
7521 #define ALT_USB_GLOB_GRXSTSR_DPID_E_DATA1 0x2
7522 /*
7523  * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID
7524  *
7525  * MDATA
7526  */
7527 #define ALT_USB_GLOB_GRXSTSR_DPID_E_MDATA 0x3
7528 
7529 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_DPID register field. */
7530 #define ALT_USB_GLOB_GRXSTSR_DPID_LSB 15
7531 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_DPID register field. */
7532 #define ALT_USB_GLOB_GRXSTSR_DPID_MSB 16
7533 /* The width in bits of the ALT_USB_GLOB_GRXSTSR_DPID register field. */
7534 #define ALT_USB_GLOB_GRXSTSR_DPID_WIDTH 2
7535 /* The mask used to set the ALT_USB_GLOB_GRXSTSR_DPID register field value. */
7536 #define ALT_USB_GLOB_GRXSTSR_DPID_SET_MSK 0x00018000
7537 /* The mask used to clear the ALT_USB_GLOB_GRXSTSR_DPID register field value. */
7538 #define ALT_USB_GLOB_GRXSTSR_DPID_CLR_MSK 0xfffe7fff
7539 /* The reset value of the ALT_USB_GLOB_GRXSTSR_DPID register field. */
7540 #define ALT_USB_GLOB_GRXSTSR_DPID_RESET 0x0
7541 /* Extracts the ALT_USB_GLOB_GRXSTSR_DPID field value from a register. */
7542 #define ALT_USB_GLOB_GRXSTSR_DPID_GET(value) (((value) & 0x00018000) >> 15)
7543 /* Produces a ALT_USB_GLOB_GRXSTSR_DPID register field value suitable for setting the register. */
7544 #define ALT_USB_GLOB_GRXSTSR_DPID_SET(value) (((value) << 15) & 0x00018000)
7545 
7546 /*
7547  * Field : pktsts
7548  *
7549  * Mode: Host only
7550  *
7551  * Packet Status (PktSts)
7552  *
7553  * Indicates the status of the received packet
7554  *
7555  * 4'b0010: IN data packet received
7556  *
7557  * 4'b0011: IN transfer completed (triggers an interrupt)
7558  *
7559  * 4'b0101: Data toggle error (triggers an interrupt)
7560  *
7561  * 4'b0111: Channel halted (triggers an interrupt)
7562  *
7563  * Others: Reserved
7564  *
7565  * Mode: Device only
7566  *
7567  * Packet Status (PktSts)
7568  *
7569  * Indicates the status of the received packet
7570  *
7571  * 4'b0001: Global OUT NAK (triggers an interrupt)
7572  *
7573  * 4'b0010: OUT data packet received
7574  *
7575  * 4'b0011: OUT transfer completed (triggers an interrupt)
7576  *
7577  * 4'b0100: SETUP transaction completed (triggers an
7578  *
7579  * interrupt)
7580  *
7581  * 4'b0110: SETUP data packet received
7582  *
7583  * Others: Reserved
7584  *
7585  * Field Enumeration Values:
7586  *
7587  * Enum | Value | Description
7588  * :--------------------------------------|:------|:---------------------------------------------
7589  * ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INDPRX | 0x2 | IN data packet received
7590  * ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INTRCOM | 0x3 | IN transfer completed (triggers an interrupt
7591  * ALT_USB_GLOB_GRXSTSR_PKTSTS_E_DTTOG | 0x5 | Data toggle error (triggers an interrupt)
7592  * ALT_USB_GLOB_GRXSTSR_PKTSTS_E_CHHALT | 0x7 | Channel halted (triggers an interrupt)
7593  *
7594  * Field Access Macros:
7595  *
7596  */
7597 /*
7598  * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS
7599  *
7600  * IN data packet received
7601  */
7602 #define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INDPRX 0x2
7603 /*
7604  * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS
7605  *
7606  * IN transfer completed (triggers an interrupt
7607  */
7608 #define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INTRCOM 0x3
7609 /*
7610  * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS
7611  *
7612  * Data toggle error (triggers an interrupt)
7613  */
7614 #define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_DTTOG 0x5
7615 /*
7616  * Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS
7617  *
7618  * Channel halted (triggers an interrupt)
7619  */
7620 #define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_CHHALT 0x7
7621 
7622 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */
7623 #define ALT_USB_GLOB_GRXSTSR_PKTSTS_LSB 17
7624 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */
7625 #define ALT_USB_GLOB_GRXSTSR_PKTSTS_MSB 20
7626 /* The width in bits of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */
7627 #define ALT_USB_GLOB_GRXSTSR_PKTSTS_WIDTH 4
7628 /* The mask used to set the ALT_USB_GLOB_GRXSTSR_PKTSTS register field value. */
7629 #define ALT_USB_GLOB_GRXSTSR_PKTSTS_SET_MSK 0x001e0000
7630 /* The mask used to clear the ALT_USB_GLOB_GRXSTSR_PKTSTS register field value. */
7631 #define ALT_USB_GLOB_GRXSTSR_PKTSTS_CLR_MSK 0xffe1ffff
7632 /* The reset value of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */
7633 #define ALT_USB_GLOB_GRXSTSR_PKTSTS_RESET 0x0
7634 /* Extracts the ALT_USB_GLOB_GRXSTSR_PKTSTS field value from a register. */
7635 #define ALT_USB_GLOB_GRXSTSR_PKTSTS_GET(value) (((value) & 0x001e0000) >> 17)
7636 /* Produces a ALT_USB_GLOB_GRXSTSR_PKTSTS register field value suitable for setting the register. */
7637 #define ALT_USB_GLOB_GRXSTSR_PKTSTS_SET(value) (((value) << 17) & 0x001e0000)
7638 
7639 /*
7640  * Field : fn
7641  *
7642  * Mode: Device only
7643  *
7644  * Frame Number (FN)
7645  *
7646  * This is the least significant 4 bits of the (micro)Frame number in
7647  *
7648  * which the packet is received on the USB. This field is supported
7649  *
7650  * only when isochronous OUT endpoints are supported.
7651  *
7652  * Field Access Macros:
7653  *
7654  */
7655 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_FN register field. */
7656 #define ALT_USB_GLOB_GRXSTSR_FN_LSB 21
7657 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_FN register field. */
7658 #define ALT_USB_GLOB_GRXSTSR_FN_MSB 24
7659 /* The width in bits of the ALT_USB_GLOB_GRXSTSR_FN register field. */
7660 #define ALT_USB_GLOB_GRXSTSR_FN_WIDTH 4
7661 /* The mask used to set the ALT_USB_GLOB_GRXSTSR_FN register field value. */
7662 #define ALT_USB_GLOB_GRXSTSR_FN_SET_MSK 0x01e00000
7663 /* The mask used to clear the ALT_USB_GLOB_GRXSTSR_FN register field value. */
7664 #define ALT_USB_GLOB_GRXSTSR_FN_CLR_MSK 0xfe1fffff
7665 /* The reset value of the ALT_USB_GLOB_GRXSTSR_FN register field. */
7666 #define ALT_USB_GLOB_GRXSTSR_FN_RESET 0x0
7667 /* Extracts the ALT_USB_GLOB_GRXSTSR_FN field value from a register. */
7668 #define ALT_USB_GLOB_GRXSTSR_FN_GET(value) (((value) & 0x01e00000) >> 21)
7669 /* Produces a ALT_USB_GLOB_GRXSTSR_FN register field value suitable for setting the register. */
7670 #define ALT_USB_GLOB_GRXSTSR_FN_SET(value) (((value) << 21) & 0x01e00000)
7671 
7672 #ifndef __ASSEMBLY__
7673 /*
7674  * WARNING: The C register and register group struct declarations are provided for
7675  * convenience and illustrative purposes. They should, however, be used with
7676  * caution as the C language standard provides no guarantees about the alignment or
7677  * atomicity of device memory accesses. The recommended practice for writing
7678  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7679  * alt_write_word() functions.
7680  *
7681  * The struct declaration for register ALT_USB_GLOB_GRXSTSR.
7682  */
7683 struct ALT_USB_GLOB_GRXSTSR_s
7684 {
7685  const uint32_t chnum : 4; /* ALT_USB_GLOB_GRXSTSR_CHNUM */
7686  const uint32_t bcnt : 11; /* ALT_USB_GLOB_GRXSTSR_BCNT */
7687  const uint32_t dpid : 2; /* ALT_USB_GLOB_GRXSTSR_DPID */
7688  const uint32_t pktsts : 4; /* ALT_USB_GLOB_GRXSTSR_PKTSTS */
7689  const uint32_t fn : 4; /* ALT_USB_GLOB_GRXSTSR_FN */
7690  uint32_t : 7; /* *UNDEFINED* */
7691 };
7692 
7693 /* The typedef declaration for register ALT_USB_GLOB_GRXSTSR. */
7694 typedef volatile struct ALT_USB_GLOB_GRXSTSR_s ALT_USB_GLOB_GRXSTSR_t;
7695 #endif /* __ASSEMBLY__ */
7696 
7697 /* The reset value of the ALT_USB_GLOB_GRXSTSR register. */
7698 #define ALT_USB_GLOB_GRXSTSR_RESET 0x00000000
7699 /* The byte offset of the ALT_USB_GLOB_GRXSTSR register from the beginning of the component. */
7700 #define ALT_USB_GLOB_GRXSTSR_OFST 0x1c
7701 /* The address of the ALT_USB_GLOB_GRXSTSR register. */
7702 #define ALT_USB_GLOB_GRXSTSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRXSTSR_OFST))
7703 
7704 /*
7705  * Register : grxstsp
7706  *
7707  * Receive Status Read /Pop Register
7708  *
7709  * Register Layout
7710  *
7711  * Bits | Access | Reset | Description
7712  * :--------|:-------|:------|:----------------------------
7713  * [3:0] | R | 0x0 | ALT_USB_GLOB_GRXSTSP_CHNUM
7714  * [14:4] | R | 0x0 | ALT_USB_GLOB_GRXSTSP_BCNT
7715  * [16:15] | R | 0x0 | ALT_USB_GLOB_GRXSTSP_DPID
7716  * [20:17] | R | 0x0 | ALT_USB_GLOB_GRXSTSP_PKTSTS
7717  * [24:21] | R | 0x0 | ALT_USB_GLOB_GRXSTSP_FN
7718  * [31:25] | ??? | 0x0 | *UNDEFINED*
7719  *
7720  */
7721 /*
7722  * Field : chnum
7723  *
7724  * Mode: Host only
7725  *
7726  * Channel Number (ChNum)
7727  *
7728  * Indicates the channel number to which the current received
7729  *
7730  * packet belongs.
7731  *
7732  * Mode: Device only
7733  *
7734  * Endpoint Number (EPNum)
7735  *
7736  * Indicates the endpoint number to which the current received
7737  *
7738  * packet belongs.
7739  *
7740  * Field Access Macros:
7741  *
7742  */
7743 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */
7744 #define ALT_USB_GLOB_GRXSTSP_CHNUM_LSB 0
7745 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */
7746 #define ALT_USB_GLOB_GRXSTSP_CHNUM_MSB 3
7747 /* The width in bits of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */
7748 #define ALT_USB_GLOB_GRXSTSP_CHNUM_WIDTH 4
7749 /* The mask used to set the ALT_USB_GLOB_GRXSTSP_CHNUM register field value. */
7750 #define ALT_USB_GLOB_GRXSTSP_CHNUM_SET_MSK 0x0000000f
7751 /* The mask used to clear the ALT_USB_GLOB_GRXSTSP_CHNUM register field value. */
7752 #define ALT_USB_GLOB_GRXSTSP_CHNUM_CLR_MSK 0xfffffff0
7753 /* The reset value of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */
7754 #define ALT_USB_GLOB_GRXSTSP_CHNUM_RESET 0x0
7755 /* Extracts the ALT_USB_GLOB_GRXSTSP_CHNUM field value from a register. */
7756 #define ALT_USB_GLOB_GRXSTSP_CHNUM_GET(value) (((value) & 0x0000000f) >> 0)
7757 /* Produces a ALT_USB_GLOB_GRXSTSP_CHNUM register field value suitable for setting the register. */
7758 #define ALT_USB_GLOB_GRXSTSP_CHNUM_SET(value) (((value) << 0) & 0x0000000f)
7759 
7760 /*
7761  * Field : bcnt
7762  *
7763  * Mode: Host only
7764  *
7765  * Byte Count (BCnt)
7766  *
7767  * Indicates the byte count of the received IN data packet.
7768  *
7769  * Mode: Device only
7770  *
7771  * Byte Count (BCnt)
7772  *
7773  * Indicates the byte count of the received data packet.
7774  *
7775  * Field Access Macros:
7776  *
7777  */
7778 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */
7779 #define ALT_USB_GLOB_GRXSTSP_BCNT_LSB 4
7780 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */
7781 #define ALT_USB_GLOB_GRXSTSP_BCNT_MSB 14
7782 /* The width in bits of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */
7783 #define ALT_USB_GLOB_GRXSTSP_BCNT_WIDTH 11
7784 /* The mask used to set the ALT_USB_GLOB_GRXSTSP_BCNT register field value. */
7785 #define ALT_USB_GLOB_GRXSTSP_BCNT_SET_MSK 0x00007ff0
7786 /* The mask used to clear the ALT_USB_GLOB_GRXSTSP_BCNT register field value. */
7787 #define ALT_USB_GLOB_GRXSTSP_BCNT_CLR_MSK 0xffff800f
7788 /* The reset value of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */
7789 #define ALT_USB_GLOB_GRXSTSP_BCNT_RESET 0x0
7790 /* Extracts the ALT_USB_GLOB_GRXSTSP_BCNT field value from a register. */
7791 #define ALT_USB_GLOB_GRXSTSP_BCNT_GET(value) (((value) & 0x00007ff0) >> 4)
7792 /* Produces a ALT_USB_GLOB_GRXSTSP_BCNT register field value suitable for setting the register. */
7793 #define ALT_USB_GLOB_GRXSTSP_BCNT_SET(value) (((value) << 4) & 0x00007ff0)
7794 
7795 /*
7796  * Field : dpid
7797  *
7798  * Mode: Host only
7799  *
7800  * Data PID (DPID)
7801  *
7802  * Indicates the Data PID of the received packet
7803  *
7804  * 2'b00: DATA0
7805  *
7806  * 2'b10: DATA1
7807  *
7808  * 2'b01: DATA2
7809  *
7810  * 2'b11: MDATA
7811  *
7812  * Mode: Device only
7813  *
7814  * Data PID (DPID)
7815  *
7816  * Indicates the Data PID of the received OUT data packet
7817  *
7818  * 2'b00: DATA0
7819  *
7820  * 2'b10: DATA1
7821  *
7822  * 2'b01: DATA2
7823  *
7824  * 2'b11: MDATA
7825  *
7826  * Field Enumeration Values:
7827  *
7828  * Enum | Value | Description
7829  * :----------------------------------|:------|:------------
7830  * ALT_USB_GLOB_GRXSTSP_DPID_E_DATA0 | 0x0 | DATA0
7831  * ALT_USB_GLOB_GRXSTSP_DPID_E_DATA2 | 0x1 | DATA2
7832  * ALT_USB_GLOB_GRXSTSP_DPID_E_DATA1 | 0x2 | DATA1
7833  * ALT_USB_GLOB_GRXSTSP_DPID_E_MDATA | 0x3 | MDATA
7834  *
7835  * Field Access Macros:
7836  *
7837  */
7838 /*
7839  * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID
7840  *
7841  * DATA0
7842  */
7843 #define ALT_USB_GLOB_GRXSTSP_DPID_E_DATA0 0x0
7844 /*
7845  * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID
7846  *
7847  * DATA2
7848  */
7849 #define ALT_USB_GLOB_GRXSTSP_DPID_E_DATA2 0x1
7850 /*
7851  * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID
7852  *
7853  * DATA1
7854  */
7855 #define ALT_USB_GLOB_GRXSTSP_DPID_E_DATA1 0x2
7856 /*
7857  * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID
7858  *
7859  * MDATA
7860  */
7861 #define ALT_USB_GLOB_GRXSTSP_DPID_E_MDATA 0x3
7862 
7863 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_DPID register field. */
7864 #define ALT_USB_GLOB_GRXSTSP_DPID_LSB 15
7865 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_DPID register field. */
7866 #define ALT_USB_GLOB_GRXSTSP_DPID_MSB 16
7867 /* The width in bits of the ALT_USB_GLOB_GRXSTSP_DPID register field. */
7868 #define ALT_USB_GLOB_GRXSTSP_DPID_WIDTH 2
7869 /* The mask used to set the ALT_USB_GLOB_GRXSTSP_DPID register field value. */
7870 #define ALT_USB_GLOB_GRXSTSP_DPID_SET_MSK 0x00018000
7871 /* The mask used to clear the ALT_USB_GLOB_GRXSTSP_DPID register field value. */
7872 #define ALT_USB_GLOB_GRXSTSP_DPID_CLR_MSK 0xfffe7fff
7873 /* The reset value of the ALT_USB_GLOB_GRXSTSP_DPID register field. */
7874 #define ALT_USB_GLOB_GRXSTSP_DPID_RESET 0x0
7875 /* Extracts the ALT_USB_GLOB_GRXSTSP_DPID field value from a register. */
7876 #define ALT_USB_GLOB_GRXSTSP_DPID_GET(value) (((value) & 0x00018000) >> 15)
7877 /* Produces a ALT_USB_GLOB_GRXSTSP_DPID register field value suitable for setting the register. */
7878 #define ALT_USB_GLOB_GRXSTSP_DPID_SET(value) (((value) << 15) & 0x00018000)
7879 
7880 /*
7881  * Field : pktsts
7882  *
7883  * Mode: Host only
7884  *
7885  * Packet Status (PktSts)
7886  *
7887  * Indicates the status of the received packet
7888  *
7889  * 4'b0010: IN data packet received
7890  *
7891  * 4'b0011: IN transfer completed (triggers an interrupt)
7892  *
7893  * 4'b0101: Data toggle error (triggers an interrupt)
7894  *
7895  * 4'b0111: Channel halted (triggers an interrupt)
7896  *
7897  * Others: Reserved
7898  *
7899  * Mode: Device only
7900  *
7901  * Packet Status (PktSts)
7902  *
7903  * Indicates the status of the received packet
7904  *
7905  * 4'b0001: Global OUT NAK (triggers an interrupt)
7906  *
7907  * 4'b0010: OUT data packet received
7908  *
7909  * 4'b0011: OUT transfer completed (triggers an interrupt)
7910  *
7911  * 4'b0100: SETUP transaction completed (triggers an
7912  *
7913  * interrupt)
7914  *
7915  * 4'b0110: SETUP data packet received
7916  *
7917  * Others: Reserved
7918  *
7919  * Field Enumeration Values:
7920  *
7921  * Enum | Value | Description
7922  * :------------------------------------|:------|:------------
7923  * ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA0 | 0x0 | DATA0
7924  * ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA2 | 0x1 | DATA2
7925  * ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA1 | 0x2 | DATA1
7926  * ALT_USB_GLOB_GRXSTSP_PKTSTS_E_MDATA | 0x3 | MDATA
7927  *
7928  * Field Access Macros:
7929  *
7930  */
7931 /*
7932  * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS
7933  *
7934  * DATA0
7935  */
7936 #define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA0 0x0
7937 /*
7938  * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS
7939  *
7940  * DATA2
7941  */
7942 #define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA2 0x1
7943 /*
7944  * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS
7945  *
7946  * DATA1
7947  */
7948 #define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA1 0x2
7949 /*
7950  * Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS
7951  *
7952  * MDATA
7953  */
7954 #define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_MDATA 0x3
7955 
7956 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */
7957 #define ALT_USB_GLOB_GRXSTSP_PKTSTS_LSB 17
7958 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */
7959 #define ALT_USB_GLOB_GRXSTSP_PKTSTS_MSB 20
7960 /* The width in bits of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */
7961 #define ALT_USB_GLOB_GRXSTSP_PKTSTS_WIDTH 4
7962 /* The mask used to set the ALT_USB_GLOB_GRXSTSP_PKTSTS register field value. */
7963 #define ALT_USB_GLOB_GRXSTSP_PKTSTS_SET_MSK 0x001e0000
7964 /* The mask used to clear the ALT_USB_GLOB_GRXSTSP_PKTSTS register field value. */
7965 #define ALT_USB_GLOB_GRXSTSP_PKTSTS_CLR_MSK 0xffe1ffff
7966 /* The reset value of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */
7967 #define ALT_USB_GLOB_GRXSTSP_PKTSTS_RESET 0x0
7968 /* Extracts the ALT_USB_GLOB_GRXSTSP_PKTSTS field value from a register. */
7969 #define ALT_USB_GLOB_GRXSTSP_PKTSTS_GET(value) (((value) & 0x001e0000) >> 17)
7970 /* Produces a ALT_USB_GLOB_GRXSTSP_PKTSTS register field value suitable for setting the register. */
7971 #define ALT_USB_GLOB_GRXSTSP_PKTSTS_SET(value) (((value) << 17) & 0x001e0000)
7972 
7973 /*
7974  * Field : fn
7975  *
7976  * Mode: Device only
7977  *
7978  * Frame Number (FN)
7979  *
7980  * This is the least significant 4 bits of the (micro)Frame number in
7981  *
7982  * which the packet is received on the USB. This field is supported
7983  *
7984  * only when isochronous OUT endpoints are supported.
7985  *
7986  * Field Access Macros:
7987  *
7988  */
7989 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_FN register field. */
7990 #define ALT_USB_GLOB_GRXSTSP_FN_LSB 21
7991 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_FN register field. */
7992 #define ALT_USB_GLOB_GRXSTSP_FN_MSB 24
7993 /* The width in bits of the ALT_USB_GLOB_GRXSTSP_FN register field. */
7994 #define ALT_USB_GLOB_GRXSTSP_FN_WIDTH 4
7995 /* The mask used to set the ALT_USB_GLOB_GRXSTSP_FN register field value. */
7996 #define ALT_USB_GLOB_GRXSTSP_FN_SET_MSK 0x01e00000
7997 /* The mask used to clear the ALT_USB_GLOB_GRXSTSP_FN register field value. */
7998 #define ALT_USB_GLOB_GRXSTSP_FN_CLR_MSK 0xfe1fffff
7999 /* The reset value of the ALT_USB_GLOB_GRXSTSP_FN register field. */
8000 #define ALT_USB_GLOB_GRXSTSP_FN_RESET 0x0
8001 /* Extracts the ALT_USB_GLOB_GRXSTSP_FN field value from a register. */
8002 #define ALT_USB_GLOB_GRXSTSP_FN_GET(value) (((value) & 0x01e00000) >> 21)
8003 /* Produces a ALT_USB_GLOB_GRXSTSP_FN register field value suitable for setting the register. */
8004 #define ALT_USB_GLOB_GRXSTSP_FN_SET(value) (((value) << 21) & 0x01e00000)
8005 
8006 #ifndef __ASSEMBLY__
8007 /*
8008  * WARNING: The C register and register group struct declarations are provided for
8009  * convenience and illustrative purposes. They should, however, be used with
8010  * caution as the C language standard provides no guarantees about the alignment or
8011  * atomicity of device memory accesses. The recommended practice for writing
8012  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8013  * alt_write_word() functions.
8014  *
8015  * The struct declaration for register ALT_USB_GLOB_GRXSTSP.
8016  */
8017 struct ALT_USB_GLOB_GRXSTSP_s
8018 {
8019  const uint32_t chnum : 4; /* ALT_USB_GLOB_GRXSTSP_CHNUM */
8020  const uint32_t bcnt : 11; /* ALT_USB_GLOB_GRXSTSP_BCNT */
8021  const uint32_t dpid : 2; /* ALT_USB_GLOB_GRXSTSP_DPID */
8022  const uint32_t pktsts : 4; /* ALT_USB_GLOB_GRXSTSP_PKTSTS */
8023  const uint32_t fn : 4; /* ALT_USB_GLOB_GRXSTSP_FN */
8024  uint32_t : 7; /* *UNDEFINED* */
8025 };
8026 
8027 /* The typedef declaration for register ALT_USB_GLOB_GRXSTSP. */
8028 typedef volatile struct ALT_USB_GLOB_GRXSTSP_s ALT_USB_GLOB_GRXSTSP_t;
8029 #endif /* __ASSEMBLY__ */
8030 
8031 /* The reset value of the ALT_USB_GLOB_GRXSTSP register. */
8032 #define ALT_USB_GLOB_GRXSTSP_RESET 0x00000000
8033 /* The byte offset of the ALT_USB_GLOB_GRXSTSP register from the beginning of the component. */
8034 #define ALT_USB_GLOB_GRXSTSP_OFST 0x20
8035 /* The address of the ALT_USB_GLOB_GRXSTSP register. */
8036 #define ALT_USB_GLOB_GRXSTSP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRXSTSP_OFST))
8037 
8038 /*
8039  * Register : grxfsiz
8040  *
8041  * Receive FIFO Size Register
8042  *
8043  * Register Layout
8044  *
8045  * Bits | Access | Reset | Description
8046  * :--------|:-------|:-------|:----------------------------
8047  * [13:0] | RW | 0x2000 | ALT_USB_GLOB_GRXFSIZ_RXFDEP
8048  * [31:14] | ??? | 0x0 | *UNDEFINED*
8049  *
8050  */
8051 /*
8052  * Field : rxfdep
8053  *
8054  * Mode: Host and Device
8055  *
8056  * RxFIFO Depth (RxFDep)
8057  *
8058  * This value is in terms of 32-bit words.
8059  *
8060  * Minimum value is 16
8061  *
8062  * Maximum value is 32,768
8063  *
8064  * The power-on reset value of this register is specified as the
8065  *
8066  * Largest Rx Data FIFO Depth during configuration. If Enable Dynamic FIFO Sizing
8067  * was selected,
8068  *
8069  * you can write a new value in this field. Programmed values must not exceed the
8070  * power-on value
8071  *
8072  * Field Access Macros:
8073  *
8074  */
8075 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */
8076 #define ALT_USB_GLOB_GRXFSIZ_RXFDEP_LSB 0
8077 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */
8078 #define ALT_USB_GLOB_GRXFSIZ_RXFDEP_MSB 13
8079 /* The width in bits of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */
8080 #define ALT_USB_GLOB_GRXFSIZ_RXFDEP_WIDTH 14
8081 /* The mask used to set the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field value. */
8082 #define ALT_USB_GLOB_GRXFSIZ_RXFDEP_SET_MSK 0x00003fff
8083 /* The mask used to clear the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field value. */
8084 #define ALT_USB_GLOB_GRXFSIZ_RXFDEP_CLR_MSK 0xffffc000
8085 /* The reset value of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */
8086 #define ALT_USB_GLOB_GRXFSIZ_RXFDEP_RESET 0x2000
8087 /* Extracts the ALT_USB_GLOB_GRXFSIZ_RXFDEP field value from a register. */
8088 #define ALT_USB_GLOB_GRXFSIZ_RXFDEP_GET(value) (((value) & 0x00003fff) >> 0)
8089 /* Produces a ALT_USB_GLOB_GRXFSIZ_RXFDEP register field value suitable for setting the register. */
8090 #define ALT_USB_GLOB_GRXFSIZ_RXFDEP_SET(value) (((value) << 0) & 0x00003fff)
8091 
8092 #ifndef __ASSEMBLY__
8093 /*
8094  * WARNING: The C register and register group struct declarations are provided for
8095  * convenience and illustrative purposes. They should, however, be used with
8096  * caution as the C language standard provides no guarantees about the alignment or
8097  * atomicity of device memory accesses. The recommended practice for writing
8098  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8099  * alt_write_word() functions.
8100  *
8101  * The struct declaration for register ALT_USB_GLOB_GRXFSIZ.
8102  */
8103 struct ALT_USB_GLOB_GRXFSIZ_s
8104 {
8105  uint32_t rxfdep : 14; /* ALT_USB_GLOB_GRXFSIZ_RXFDEP */
8106  uint32_t : 18; /* *UNDEFINED* */
8107 };
8108 
8109 /* The typedef declaration for register ALT_USB_GLOB_GRXFSIZ. */
8110 typedef volatile struct ALT_USB_GLOB_GRXFSIZ_s ALT_USB_GLOB_GRXFSIZ_t;
8111 #endif /* __ASSEMBLY__ */
8112 
8113 /* The reset value of the ALT_USB_GLOB_GRXFSIZ register. */
8114 #define ALT_USB_GLOB_GRXFSIZ_RESET 0x00002000
8115 /* The byte offset of the ALT_USB_GLOB_GRXFSIZ register from the beginning of the component. */
8116 #define ALT_USB_GLOB_GRXFSIZ_OFST 0x24
8117 /* The address of the ALT_USB_GLOB_GRXFSIZ register. */
8118 #define ALT_USB_GLOB_GRXFSIZ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRXFSIZ_OFST))
8119 
8120 /*
8121  * Register : gnptxfsiz
8122  *
8123  * Non-periodic Transmit FIFO Size Register
8124  *
8125  * Register Layout
8126  *
8127  * Bits | Access | Reset | Description
8128  * :--------|:-------|:-------|:-----------------------------------
8129  * [15:0] | RW | 0x2000 | ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR
8130  * [31:16] | RW | 0x2000 | ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP
8131  *
8132  */
8133 /*
8134  * Field : nptxfstaddr
8135  *
8136  * Mode: Host only
8137  *
8138  * Non-periodic Transmit RAM Start Address (NPTxFStAddr)
8139  *
8140  * For host mode, this field is always valid. This field contains the memory start
8141  * address
8142  *
8143  * For Non-periodic Transmit FIFO RAM.
8144  *
8145  * Programmed values must not exceed the power-on value.
8146  *
8147  * Mode: Device only
8148  *
8149  * IN Endpoint FIFO0 Transmit RAM Start Address
8150  *
8151  * (INEPTxF0StAddr)
8152  *
8153  * This field contains the memory start address For IN Endpoint
8154  *
8155  * Transmit FIFO# 0.
8156  *
8157  * Programmed values must not exceed the power-on value.
8158  *
8159  * Field Access Macros:
8160  *
8161  */
8162 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */
8163 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_LSB 0
8164 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */
8165 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_MSB 15
8166 /* The width in bits of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */
8167 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_WIDTH 16
8168 /* The mask used to set the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field value. */
8169 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_SET_MSK 0x0000ffff
8170 /* The mask used to clear the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field value. */
8171 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_CLR_MSK 0xffff0000
8172 /* The reset value of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */
8173 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_RESET 0x2000
8174 /* Extracts the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR field value from a register. */
8175 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
8176 /* Produces a ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field value suitable for setting the register. */
8177 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
8178 
8179 /*
8180  * Field : nptxfdep
8181  *
8182  * Mode: Host only
8183  *
8184  * Non-periodic TxFIFO Depth (NPTxFDep)
8185  *
8186  * For host mode, this field is always valid.
8187  *
8188  * For Device mode, this field is valid for shared fifo
8189  *
8190  * This value is in terms of 32-bit words.
8191  *
8192  * Minimum value is 16
8193  *
8194  * Maximum value is 32,768
8195  *
8196  * Programmed values must not exceed the power-on value.
8197  *
8198  * Mode: Device only
8199  *
8200  * IN Endpoint TxFIFO 0 Depth (INEPTxF0Dep)
8201  *
8202  * This value is in terms of 32-bit words.
8203  *
8204  * Minimum value is 16
8205  *
8206  * Maximum value is 32,768
8207  *
8208  * This field is determined by Enable Dynamic FIFO Sizing
8209  *
8210  * Programmed values must not
8211  *
8212  * exceed the power-on value.
8213  *
8214  * Field Access Macros:
8215  *
8216  */
8217 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */
8218 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_LSB 16
8219 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */
8220 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_MSB 31
8221 /* The width in bits of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */
8222 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_WIDTH 16
8223 /* The mask used to set the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field value. */
8224 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_SET_MSK 0xffff0000
8225 /* The mask used to clear the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field value. */
8226 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_CLR_MSK 0x0000ffff
8227 /* The reset value of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */
8228 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_RESET 0x2000
8229 /* Extracts the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP field value from a register. */
8230 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_GET(value) (((value) & 0xffff0000) >> 16)
8231 /* Produces a ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field value suitable for setting the register. */
8232 #define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_SET(value) (((value) << 16) & 0xffff0000)
8233 
8234 #ifndef __ASSEMBLY__
8235 /*
8236  * WARNING: The C register and register group struct declarations are provided for
8237  * convenience and illustrative purposes. They should, however, be used with
8238  * caution as the C language standard provides no guarantees about the alignment or
8239  * atomicity of device memory accesses. The recommended practice for writing
8240  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8241  * alt_write_word() functions.
8242  *
8243  * The struct declaration for register ALT_USB_GLOB_GNPTXFSIZ.
8244  */
8245 struct ALT_USB_GLOB_GNPTXFSIZ_s
8246 {
8247  uint32_t nptxfstaddr : 16; /* ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR */
8248  uint32_t nptxfdep : 16; /* ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP */
8249 };
8250 
8251 /* The typedef declaration for register ALT_USB_GLOB_GNPTXFSIZ. */
8252 typedef volatile struct ALT_USB_GLOB_GNPTXFSIZ_s ALT_USB_GLOB_GNPTXFSIZ_t;
8253 #endif /* __ASSEMBLY__ */
8254 
8255 /* The reset value of the ALT_USB_GLOB_GNPTXFSIZ register. */
8256 #define ALT_USB_GLOB_GNPTXFSIZ_RESET 0x20002000
8257 /* The byte offset of the ALT_USB_GLOB_GNPTXFSIZ register from the beginning of the component. */
8258 #define ALT_USB_GLOB_GNPTXFSIZ_OFST 0x28
8259 /* The address of the ALT_USB_GLOB_GNPTXFSIZ register. */
8260 #define ALT_USB_GLOB_GNPTXFSIZ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GNPTXFSIZ_OFST))
8261 
8262 /*
8263  * Register : gnptxsts
8264  *
8265  * Non-periodic Transmit FIFO/Queue Status Register
8266  *
8267  * Register Layout
8268  *
8269  * Bits | Access | Reset | Description
8270  * :--------|:-------|:-------|:------------------------------------
8271  * [15:0] | R | 0x2000 | ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL
8272  * [23:16] | R | 0x8 | ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
8273  * [30:24] | R | 0x0 | ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
8274  * [31] | ??? | 0x0 | *UNDEFINED*
8275  *
8276  */
8277 /*
8278  * Field : nptxfspcavail
8279  *
8280  * Non-periodic TxFIFO Space Avail (NPTxFSpcAvail)
8281  *
8282  * Indicates the amount of free space available in the Non-periodic
8283  *
8284  * TxFIFO.
8285  *
8286  * Values are in terms of 32-bit words.
8287  *
8288  * 16'h0: Non-periodic TxFIFO is full
8289  *
8290  * 16'h1: 1 word available
8291  *
8292  * 16'h2: 2 words available
8293  *
8294  * 16'hn: n words available (where 0 <= n <= 32,768)
8295  *
8296  * 16'h8000: 32,768 words available
8297  *
8298  * Others: Reserved
8299  *
8300  * Field Access Macros:
8301  *
8302  */
8303 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */
8304 #define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_LSB 0
8305 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */
8306 #define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_MSB 15
8307 /* The width in bits of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */
8308 #define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_WIDTH 16
8309 /* The mask used to set the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field value. */
8310 #define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_SET_MSK 0x0000ffff
8311 /* The mask used to clear the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field value. */
8312 #define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_CLR_MSK 0xffff0000
8313 /* The reset value of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */
8314 #define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_RESET 0x2000
8315 /* Extracts the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL field value from a register. */
8316 #define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
8317 /* Produces a ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field value suitable for setting the register. */
8318 #define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
8319 
8320 /*
8321  * Field : nptxqspcavail
8322  *
8323  * Non-periodic Transmit Request Queue Space Available
8324  *
8325  * (NPTxQSpcAvail)
8326  *
8327  * Indicates the amount of free space available in the Non-periodic
8328  *
8329  * Transmit Request Queue. This queue holds both IN and OUT
8330  *
8331  * requests in Host mode. Device mode has only IN requests.
8332  *
8333  * 8'h0: Non-periodic Transmit Request Queue is full
8334  *
8335  * 8'h1: 1 location available
8336  *
8337  * 8'h2: 2 locations available
8338  *
8339  * n: n locations available (0 <= n <= 8)
8340  *
8341  * Others: Reserved
8342  *
8343  * Field Enumeration Values:
8344  *
8345  * Enum | Value | Description
8346  * :-------------------------------------------|:------|:--------------------------------------------
8347  * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_FULL | 0x0 | Non-periodic Transmit Request Queue is full
8348  * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE1 | 0x1 | 1 location available
8349  * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE2 | 0x2 | 2 locations available
8350  * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE3 | 0x3 | 3 locations available
8351  * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE4 | 0x4 | 4 locations available
8352  * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE5 | 0x5 | 5 locations available
8353  * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE6 | 0x6 | 6 locations available
8354  * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE7 | 0x7 | 7 locations available
8355  * ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE8 | 0x8 | 8 locations available
8356  *
8357  * Field Access Macros:
8358  *
8359  */
8360 /*
8361  * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
8362  *
8363  * Non-periodic Transmit Request Queue is full
8364  */
8365 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_FULL 0x0
8366 /*
8367  * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
8368  *
8369  * 1 location available
8370  */
8371 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE1 0x1
8372 /*
8373  * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
8374  *
8375  * 2 locations available
8376  */
8377 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE2 0x2
8378 /*
8379  * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
8380  *
8381  * 3 locations available
8382  */
8383 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE3 0x3
8384 /*
8385  * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
8386  *
8387  * 4 locations available
8388  */
8389 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE4 0x4
8390 /*
8391  * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
8392  *
8393  * 5 locations available
8394  */
8395 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE5 0x5
8396 /*
8397  * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
8398  *
8399  * 6 locations available
8400  */
8401 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE6 0x6
8402 /*
8403  * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
8404  *
8405  * 7 locations available
8406  */
8407 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE7 0x7
8408 /*
8409  * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
8410  *
8411  * 8 locations available
8412  */
8413 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE8 0x8
8414 
8415 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */
8416 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_LSB 16
8417 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */
8418 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_MSB 23
8419 /* The width in bits of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */
8420 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_WIDTH 8
8421 /* The mask used to set the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field value. */
8422 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_SET_MSK 0x00ff0000
8423 /* The mask used to clear the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field value. */
8424 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_CLR_MSK 0xff00ffff
8425 /* The reset value of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */
8426 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_RESET 0x8
8427 /* Extracts the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL field value from a register. */
8428 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_GET(value) (((value) & 0x00ff0000) >> 16)
8429 /* Produces a ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field value suitable for setting the register. */
8430 #define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_SET(value) (((value) << 16) & 0x00ff0000)
8431 
8432 /*
8433  * Field : nptxqtop
8434  *
8435  * Top of the Non-periodic Transmit Request Queue (NPTxQTop)
8436  *
8437  * Entry in the Non-periodic Tx Request Queue that is currently
8438  *
8439  * being processed by the MAC.
8440  *
8441  * Bits [30:27]: Channel/endpoint number
8442  *
8443  * Bits [26:25]:
8444  *
8445  * * 2'b00: IN/OUT token
8446  *
8447  * * 2'b01: Zero-length transmit packet (device IN/host OUT)
8448  *
8449  * * 2'b10: PING/CSPLIT token
8450  *
8451  * * 2'b11: Channel halt command
8452  *
8453  * Bit [24]: Terminate (last Entry For selected channel/endpoint)
8454  *
8455  * Field Enumeration Values:
8456  *
8457  * Enum | Value | Description
8458  * :--------------------------------------------|:------|:-------------------------------------------------
8459  * ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_INOUTTK | 0x0 | IN/OUT token
8460  * ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_ZEROTX | 0x1 | Zero-length transmit packet (device IN/host OUT)
8461  * ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_PINGCSPLIT | 0x2 | PING/CSPLIT token
8462  * ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_CHNHALT | 0x3 | Channel halt command
8463  *
8464  * Field Access Macros:
8465  *
8466  */
8467 /*
8468  * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
8469  *
8470  * IN/OUT token
8471  */
8472 #define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_INOUTTK 0x0
8473 /*
8474  * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
8475  *
8476  * Zero-length transmit packet (device IN/host OUT)
8477  */
8478 #define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_ZEROTX 0x1
8479 /*
8480  * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
8481  *
8482  * PING/CSPLIT token
8483  */
8484 #define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_PINGCSPLIT 0x2
8485 /*
8486  * Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
8487  *
8488  * Channel halt command
8489  */
8490 #define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_CHNHALT 0x3
8491 
8492 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */
8493 #define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_LSB 24
8494 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */
8495 #define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_MSB 30
8496 /* The width in bits of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */
8497 #define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_WIDTH 7
8498 /* The mask used to set the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field value. */
8499 #define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_SET_MSK 0x7f000000
8500 /* The mask used to clear the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field value. */
8501 #define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_CLR_MSK 0x80ffffff
8502 /* The reset value of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */
8503 #define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_RESET 0x0
8504 /* Extracts the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP field value from a register. */
8505 #define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_GET(value) (((value) & 0x7f000000) >> 24)
8506 /* Produces a ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field value suitable for setting the register. */
8507 #define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_SET(value) (((value) << 24) & 0x7f000000)
8508 
8509 #ifndef __ASSEMBLY__
8510 /*
8511  * WARNING: The C register and register group struct declarations are provided for
8512  * convenience and illustrative purposes. They should, however, be used with
8513  * caution as the C language standard provides no guarantees about the alignment or
8514  * atomicity of device memory accesses. The recommended practice for writing
8515  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8516  * alt_write_word() functions.
8517  *
8518  * The struct declaration for register ALT_USB_GLOB_GNPTXSTS.
8519  */
8520 struct ALT_USB_GLOB_GNPTXSTS_s
8521 {
8522  const uint32_t nptxfspcavail : 16; /* ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL */
8523  const uint32_t nptxqspcavail : 8; /* ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL */
8524  const uint32_t nptxqtop : 7; /* ALT_USB_GLOB_GNPTXSTS_NPTXQTOP */
8525  uint32_t : 1; /* *UNDEFINED* */
8526 };
8527 
8528 /* The typedef declaration for register ALT_USB_GLOB_GNPTXSTS. */
8529 typedef volatile struct ALT_USB_GLOB_GNPTXSTS_s ALT_USB_GLOB_GNPTXSTS_t;
8530 #endif /* __ASSEMBLY__ */
8531 
8532 /* The reset value of the ALT_USB_GLOB_GNPTXSTS register. */
8533 #define ALT_USB_GLOB_GNPTXSTS_RESET 0x00082000
8534 /* The byte offset of the ALT_USB_GLOB_GNPTXSTS register from the beginning of the component. */
8535 #define ALT_USB_GLOB_GNPTXSTS_OFST 0x2c
8536 /* The address of the ALT_USB_GLOB_GNPTXSTS register. */
8537 #define ALT_USB_GLOB_GNPTXSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GNPTXSTS_OFST))
8538 
8539 /*
8540  * Register : gpvndctl
8541  *
8542  * PHY Vendor Control Register
8543  *
8544  * Register Layout
8545  *
8546  * Bits | Access | Reset | Description
8547  * :--------|:---------|:------|:----------------------------------
8548  * [7:0] | RW | 0x0 | ALT_USB_GLOB_GPVNDCTL_REGDATA
8549  * [15:8] | RW | 0x0 | ALT_USB_GLOB_GPVNDCTL_VCTL
8550  * [21:16] | RW | 0x0 | ALT_USB_GLOB_GPVNDCTL_REGADDR
8551  * [22] | RW | 0x0 | ALT_USB_GLOB_GPVNDCTL_REGWR
8552  * [24:23] | ??? | 0x0 | *UNDEFINED*
8553  * [25] | R-W once | 0x0 | ALT_USB_GLOB_GPVNDCTL_NEWREGREQ
8554  * [26] | R | 0x0 | ALT_USB_GLOB_GPVNDCTL_VSTSBSY
8555  * [27] | RW | 0x0 | ALT_USB_GLOB_GPVNDCTL_VSTSDONE
8556  * [30:28] | ??? | 0x0 | *UNDEFINED*
8557  * [31] | R-W once | 0x0 | ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR
8558  *
8559  */
8560 /*
8561  * Field : regdata
8562  *
8563  * Register Data (RegData)
8564  *
8565  * Contains the write data For register write. Read data For
8566  *
8567  * register read, valid when VStatus Done is Set.
8568  *
8569  * Field Access Macros:
8570  *
8571  */
8572 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */
8573 #define ALT_USB_GLOB_GPVNDCTL_REGDATA_LSB 0
8574 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */
8575 #define ALT_USB_GLOB_GPVNDCTL_REGDATA_MSB 7
8576 /* The width in bits of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */
8577 #define ALT_USB_GLOB_GPVNDCTL_REGDATA_WIDTH 8
8578 /* The mask used to set the ALT_USB_GLOB_GPVNDCTL_REGDATA register field value. */
8579 #define ALT_USB_GLOB_GPVNDCTL_REGDATA_SET_MSK 0x000000ff
8580 /* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_REGDATA register field value. */
8581 #define ALT_USB_GLOB_GPVNDCTL_REGDATA_CLR_MSK 0xffffff00
8582 /* The reset value of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */
8583 #define ALT_USB_GLOB_GPVNDCTL_REGDATA_RESET 0x0
8584 /* Extracts the ALT_USB_GLOB_GPVNDCTL_REGDATA field value from a register. */
8585 #define ALT_USB_GLOB_GPVNDCTL_REGDATA_GET(value) (((value) & 0x000000ff) >> 0)
8586 /* Produces a ALT_USB_GLOB_GPVNDCTL_REGDATA register field value suitable for setting the register. */
8587 #define ALT_USB_GLOB_GPVNDCTL_REGDATA_SET(value) (((value) << 0) & 0x000000ff)
8588 
8589 /*
8590  * Field : vctrl
8591  *
8592  * UTMI+ Vendor Control Register Address (VCtrl)
8593  *
8594  * The 4-bit register address a vendor defined 4-bit parallel
8595  *
8596  * output bus. Bits 11:8 of this field are placed on
8597  *
8598  * utmi_vcontrol[3:0].
8599  *
8600  * ULPI Extended Register Address (ExtRegAddr)
8601  *
8602  * The 6-bit PHY extended register address.
8603  *
8604  * Field Access Macros:
8605  *
8606  */
8607 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */
8608 #define ALT_USB_GLOB_GPVNDCTL_VCTL_LSB 8
8609 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */
8610 #define ALT_USB_GLOB_GPVNDCTL_VCTL_MSB 15
8611 /* The width in bits of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */
8612 #define ALT_USB_GLOB_GPVNDCTL_VCTL_WIDTH 8
8613 /* The mask used to set the ALT_USB_GLOB_GPVNDCTL_VCTL register field value. */
8614 #define ALT_USB_GLOB_GPVNDCTL_VCTL_SET_MSK 0x0000ff00
8615 /* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_VCTL register field value. */
8616 #define ALT_USB_GLOB_GPVNDCTL_VCTL_CLR_MSK 0xffff00ff
8617 /* The reset value of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */
8618 #define ALT_USB_GLOB_GPVNDCTL_VCTL_RESET 0x0
8619 /* Extracts the ALT_USB_GLOB_GPVNDCTL_VCTL field value from a register. */
8620 #define ALT_USB_GLOB_GPVNDCTL_VCTL_GET(value) (((value) & 0x0000ff00) >> 8)
8621 /* Produces a ALT_USB_GLOB_GPVNDCTL_VCTL register field value suitable for setting the register. */
8622 #define ALT_USB_GLOB_GPVNDCTL_VCTL_SET(value) (((value) << 8) & 0x0000ff00)
8623 
8624 /*
8625  * Field : regaddr
8626  *
8627  * Register Address (RegAddr)
8628  *
8629  * The 6-bit PHY register address For immediate PHY Register
8630  *
8631  * Set access. Set to 6'h2F For Extended PHY Register Set
8632  *
8633  * access.
8634  *
8635  * Field Access Macros:
8636  *
8637  */
8638 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */
8639 #define ALT_USB_GLOB_GPVNDCTL_REGADDR_LSB 16
8640 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */
8641 #define ALT_USB_GLOB_GPVNDCTL_REGADDR_MSB 21
8642 /* The width in bits of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */
8643 #define ALT_USB_GLOB_GPVNDCTL_REGADDR_WIDTH 6
8644 /* The mask used to set the ALT_USB_GLOB_GPVNDCTL_REGADDR register field value. */
8645 #define ALT_USB_GLOB_GPVNDCTL_REGADDR_SET_MSK 0x003f0000
8646 /* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_REGADDR register field value. */
8647 #define ALT_USB_GLOB_GPVNDCTL_REGADDR_CLR_MSK 0xffc0ffff
8648 /* The reset value of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */
8649 #define ALT_USB_GLOB_GPVNDCTL_REGADDR_RESET 0x0
8650 /* Extracts the ALT_USB_GLOB_GPVNDCTL_REGADDR field value from a register. */
8651 #define ALT_USB_GLOB_GPVNDCTL_REGADDR_GET(value) (((value) & 0x003f0000) >> 16)
8652 /* Produces a ALT_USB_GLOB_GPVNDCTL_REGADDR register field value suitable for setting the register. */
8653 #define ALT_USB_GLOB_GPVNDCTL_REGADDR_SET(value) (((value) << 16) & 0x003f0000)
8654 
8655 /*
8656  * Field : regwr
8657  *
8658  * Register Write (RegWr)
8659  *
8660  * Set this bit For register writes, and clear it For register reads.
8661  *
8662  * Field Enumeration Values:
8663  *
8664  * Enum | Value | Description
8665  * :---------------------------------|:------|:---------------
8666  * ALT_USB_GLOB_GPVNDCTL_REGWR_E_RD | 0x0 | Register Write
8667  * ALT_USB_GLOB_GPVNDCTL_REGWR_E_WR | 0x1 | Register Write
8668  *
8669  * Field Access Macros:
8670  *
8671  */
8672 /*
8673  * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_REGWR
8674  *
8675  * Register Write
8676  */
8677 #define ALT_USB_GLOB_GPVNDCTL_REGWR_E_RD 0x0
8678 /*
8679  * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_REGWR
8680  *
8681  * Register Write
8682  */
8683 #define ALT_USB_GLOB_GPVNDCTL_REGWR_E_WR 0x1
8684 
8685 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */
8686 #define ALT_USB_GLOB_GPVNDCTL_REGWR_LSB 22
8687 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */
8688 #define ALT_USB_GLOB_GPVNDCTL_REGWR_MSB 22
8689 /* The width in bits of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */
8690 #define ALT_USB_GLOB_GPVNDCTL_REGWR_WIDTH 1
8691 /* The mask used to set the ALT_USB_GLOB_GPVNDCTL_REGWR register field value. */
8692 #define ALT_USB_GLOB_GPVNDCTL_REGWR_SET_MSK 0x00400000
8693 /* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_REGWR register field value. */
8694 #define ALT_USB_GLOB_GPVNDCTL_REGWR_CLR_MSK 0xffbfffff
8695 /* The reset value of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */
8696 #define ALT_USB_GLOB_GPVNDCTL_REGWR_RESET 0x0
8697 /* Extracts the ALT_USB_GLOB_GPVNDCTL_REGWR field value from a register. */
8698 #define ALT_USB_GLOB_GPVNDCTL_REGWR_GET(value) (((value) & 0x00400000) >> 22)
8699 /* Produces a ALT_USB_GLOB_GPVNDCTL_REGWR register field value suitable for setting the register. */
8700 #define ALT_USB_GLOB_GPVNDCTL_REGWR_SET(value) (((value) << 22) & 0x00400000)
8701 
8702 /*
8703  * Field : newregreq
8704  *
8705  * New Register Request (NewRegReq)
8706  *
8707  * The application sets this bit For a new vendor control
8708  *
8709  * access.
8710  *
8711  * Field Enumeration Values:
8712  *
8713  * Enum | Value | Description
8714  * :----------------------------------------|:------|:--------------------------------
8715  * ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_INACT | 0x0 | New Register Request not active
8716  * ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_ACT | 0x1 | New Register Request active
8717  *
8718  * Field Access Macros:
8719  *
8720  */
8721 /*
8722  * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_NEWREGREQ
8723  *
8724  * New Register Request not active
8725  */
8726 #define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_INACT 0x0
8727 /*
8728  * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_NEWREGREQ
8729  *
8730  * New Register Request active
8731  */
8732 #define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_ACT 0x1
8733 
8734 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */
8735 #define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_LSB 25
8736 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */
8737 #define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_MSB 25
8738 /* The width in bits of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */
8739 #define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_WIDTH 1
8740 /* The mask used to set the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field value. */
8741 #define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_SET_MSK 0x02000000
8742 /* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field value. */
8743 #define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_CLR_MSK 0xfdffffff
8744 /* The reset value of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */
8745 #define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_RESET 0x0
8746 /* Extracts the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ field value from a register. */
8747 #define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_GET(value) (((value) & 0x02000000) >> 25)
8748 /* Produces a ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field value suitable for setting the register. */
8749 #define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_SET(value) (((value) << 25) & 0x02000000)
8750 
8751 /*
8752  * Field : vstsbsy
8753  *
8754  * VStatus Busy (VStsBsy)
8755  *
8756  * The core sets this bit when the vendor control access is in
8757  *
8758  * progress and clears this bit when done.
8759  *
8760  * Field Enumeration Values:
8761  *
8762  * Enum | Value | Description
8763  * :--------------------------------------|:------|:----------------------
8764  * ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_INACT | 0x0 | VStatus Busy inactive
8765  * ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_ACT | 0x1 | VStatus Busy active
8766  *
8767  * Field Access Macros:
8768  *
8769  */
8770 /*
8771  * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSBSY
8772  *
8773  * VStatus Busy inactive
8774  */
8775 #define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_INACT 0x0
8776 /*
8777  * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSBSY
8778  *
8779  * VStatus Busy active
8780  */
8781 #define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_ACT 0x1
8782 
8783 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */
8784 #define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_LSB 26
8785 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */
8786 #define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_MSB 26
8787 /* The width in bits of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */
8788 #define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_WIDTH 1
8789 /* The mask used to set the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field value. */
8790 #define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_SET_MSK 0x04000000
8791 /* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field value. */
8792 #define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_CLR_MSK 0xfbffffff
8793 /* The reset value of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */
8794 #define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_RESET 0x0
8795 /* Extracts the ALT_USB_GLOB_GPVNDCTL_VSTSBSY field value from a register. */
8796 #define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_GET(value) (((value) & 0x04000000) >> 26)
8797 /* Produces a ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field value suitable for setting the register. */
8798 #define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_SET(value) (((value) << 26) & 0x04000000)
8799 
8800 /*
8801  * Field : vstsdone
8802  *
8803  * VStatus Done (VStsDone)
8804  *
8805  * The core sets this bit when the vendor control access is
8806  *
8807  * done.
8808  *
8809  * This bit is cleared by the core when the application sets the
8810  *
8811  * New Register Request bit (bit 25).
8812  *
8813  * Field Enumeration Values:
8814  *
8815  * Enum | Value | Description
8816  * :---------------------------------------|:------|:----------------------
8817  * ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_INACT | 0x0 | VStatus Done inactive
8818  * ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_ACT | 0x1 | VStatus Done active
8819  *
8820  * Field Access Macros:
8821  *
8822  */
8823 /*
8824  * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSDONE
8825  *
8826  * VStatus Done inactive
8827  */
8828 #define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_INACT 0x0
8829 /*
8830  * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSDONE
8831  *
8832  * VStatus Done active
8833  */
8834 #define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_ACT 0x1
8835 
8836 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */
8837 #define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_LSB 27
8838 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */
8839 #define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_MSB 27
8840 /* The width in bits of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */
8841 #define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_WIDTH 1
8842 /* The mask used to set the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field value. */
8843 #define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_SET_MSK 0x08000000
8844 /* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field value. */
8845 #define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_CLR_MSK 0xf7ffffff
8846 /* The reset value of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */
8847 #define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_RESET 0x0
8848 /* Extracts the ALT_USB_GLOB_GPVNDCTL_VSTSDONE field value from a register. */
8849 #define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_GET(value) (((value) & 0x08000000) >> 27)
8850 /* Produces a ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field value suitable for setting the register. */
8851 #define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_SET(value) (((value) << 27) & 0x08000000)
8852 
8853 /*
8854  * Field : disulpidrvr
8855  *
8856  * Disable ULPI Drivers (DisUlpiDrvr)
8857  *
8858  * The application sets this bit when it has finished processing
8859  *
8860  * the ULPI Carkit Interrupt (GINTSTS.ULPICKINT). When
8861  *
8862  * Set, the DWC_otg core disables drivers For output signals
8863  *
8864  * and masks input signal For the ULPI interface. DWC_otg
8865  *
8866  * clears this bit before enabling the ULPI interface.
8867  *
8868  * Field Enumeration Values:
8869  *
8870  * Enum | Value | Description
8871  * :-----------------------------------------|:------|:---------------------------
8872  * ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_END | 0x0 | ULPI ouput signals
8873  * ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_DISD | 0x1 | Disable ULPI ouput signals
8874  *
8875  * Field Access Macros:
8876  *
8877  */
8878 /*
8879  * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR
8880  *
8881  * ULPI ouput signals
8882  */
8883 #define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_END 0x0
8884 /*
8885  * Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR
8886  *
8887  * Disable ULPI ouput signals
8888  */
8889 #define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_DISD 0x1
8890 
8891 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */
8892 #define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_LSB 31
8893 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */
8894 #define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_MSB 31
8895 /* The width in bits of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */
8896 #define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_WIDTH 1
8897 /* The mask used to set the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field value. */
8898 #define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_SET_MSK 0x80000000
8899 /* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field value. */
8900 #define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_CLR_MSK 0x7fffffff
8901 /* The reset value of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */
8902 #define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_RESET 0x0
8903 /* Extracts the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR field value from a register. */
8904 #define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_GET(value) (((value) & 0x80000000) >> 31)
8905 /* Produces a ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field value suitable for setting the register. */
8906 #define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_SET(value) (((value) << 31) & 0x80000000)
8907 
8908 #ifndef __ASSEMBLY__
8909 /*
8910  * WARNING: The C register and register group struct declarations are provided for
8911  * convenience and illustrative purposes. They should, however, be used with
8912  * caution as the C language standard provides no guarantees about the alignment or
8913  * atomicity of device memory accesses. The recommended practice for writing
8914  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8915  * alt_write_word() functions.
8916  *
8917  * The struct declaration for register ALT_USB_GLOB_GPVNDCTL.
8918  */
8919 struct ALT_USB_GLOB_GPVNDCTL_s
8920 {
8921  uint32_t regdata : 8; /* ALT_USB_GLOB_GPVNDCTL_REGDATA */
8922  uint32_t vctrl : 8; /* ALT_USB_GLOB_GPVNDCTL_VCTL */
8923  uint32_t regaddr : 6; /* ALT_USB_GLOB_GPVNDCTL_REGADDR */
8924  uint32_t regwr : 1; /* ALT_USB_GLOB_GPVNDCTL_REGWR */
8925  uint32_t : 2; /* *UNDEFINED* */
8926  uint32_t newregreq : 1; /* ALT_USB_GLOB_GPVNDCTL_NEWREGREQ */
8927  const uint32_t vstsbsy : 1; /* ALT_USB_GLOB_GPVNDCTL_VSTSBSY */
8928  uint32_t vstsdone : 1; /* ALT_USB_GLOB_GPVNDCTL_VSTSDONE */
8929  uint32_t : 3; /* *UNDEFINED* */
8930  uint32_t disulpidrvr : 1; /* ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR */
8931 };
8932 
8933 /* The typedef declaration for register ALT_USB_GLOB_GPVNDCTL. */
8934 typedef volatile struct ALT_USB_GLOB_GPVNDCTL_s ALT_USB_GLOB_GPVNDCTL_t;
8935 #endif /* __ASSEMBLY__ */
8936 
8937 /* The reset value of the ALT_USB_GLOB_GPVNDCTL register. */
8938 #define ALT_USB_GLOB_GPVNDCTL_RESET 0x00000000
8939 /* The byte offset of the ALT_USB_GLOB_GPVNDCTL register from the beginning of the component. */
8940 #define ALT_USB_GLOB_GPVNDCTL_OFST 0x34
8941 /* The address of the ALT_USB_GLOB_GPVNDCTL register. */
8942 #define ALT_USB_GLOB_GPVNDCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GPVNDCTL_OFST))
8943 
8944 /*
8945  * Register : ggpio
8946  *
8947  * General Purpose Input/Output Register
8948  *
8949  * Register Layout
8950  *
8951  * Bits | Access | Reset | Description
8952  * :--------|:-------|:------|:-----------------------
8953  * [15:0] | R | 0x0 | ALT_USB_GLOB_GGPIO_GPI
8954  * [31:16] | RW | 0x0 | ALT_USB_GLOB_GGPIO_GPO
8955  *
8956  */
8957 /*
8958  * Field : gpi
8959  *
8960  * General Purpose Input (GPI)
8961  *
8962  * This field's read value reflects the gp_i[15:0] core input value.
8963  *
8964  * Field Access Macros:
8965  *
8966  */
8967 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GGPIO_GPI register field. */
8968 #define ALT_USB_GLOB_GGPIO_GPI_LSB 0
8969 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GGPIO_GPI register field. */
8970 #define ALT_USB_GLOB_GGPIO_GPI_MSB 15
8971 /* The width in bits of the ALT_USB_GLOB_GGPIO_GPI register field. */
8972 #define ALT_USB_GLOB_GGPIO_GPI_WIDTH 16
8973 /* The mask used to set the ALT_USB_GLOB_GGPIO_GPI register field value. */
8974 #define ALT_USB_GLOB_GGPIO_GPI_SET_MSK 0x0000ffff
8975 /* The mask used to clear the ALT_USB_GLOB_GGPIO_GPI register field value. */
8976 #define ALT_USB_GLOB_GGPIO_GPI_CLR_MSK 0xffff0000
8977 /* The reset value of the ALT_USB_GLOB_GGPIO_GPI register field. */
8978 #define ALT_USB_GLOB_GGPIO_GPI_RESET 0x0
8979 /* Extracts the ALT_USB_GLOB_GGPIO_GPI field value from a register. */
8980 #define ALT_USB_GLOB_GGPIO_GPI_GET(value) (((value) & 0x0000ffff) >> 0)
8981 /* Produces a ALT_USB_GLOB_GGPIO_GPI register field value suitable for setting the register. */
8982 #define ALT_USB_GLOB_GGPIO_GPI_SET(value) (((value) << 0) & 0x0000ffff)
8983 
8984 /*
8985  * Field : gpo
8986  *
8987  * General Purpose Output (GPO)
8988  *
8989  * This field is driven as an output from the core, gp_o[15:0]. The
8990  *
8991  * application can program this field to determine the
8992  *
8993  * corresponding value on the gp_o[15:0] output.
8994  *
8995  * Field Access Macros:
8996  *
8997  */
8998 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GGPIO_GPO register field. */
8999 #define ALT_USB_GLOB_GGPIO_GPO_LSB 16
9000 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GGPIO_GPO register field. */
9001 #define ALT_USB_GLOB_GGPIO_GPO_MSB 31
9002 /* The width in bits of the ALT_USB_GLOB_GGPIO_GPO register field. */
9003 #define ALT_USB_GLOB_GGPIO_GPO_WIDTH 16
9004 /* The mask used to set the ALT_USB_GLOB_GGPIO_GPO register field value. */
9005 #define ALT_USB_GLOB_GGPIO_GPO_SET_MSK 0xffff0000
9006 /* The mask used to clear the ALT_USB_GLOB_GGPIO_GPO register field value. */
9007 #define ALT_USB_GLOB_GGPIO_GPO_CLR_MSK 0x0000ffff
9008 /* The reset value of the ALT_USB_GLOB_GGPIO_GPO register field. */
9009 #define ALT_USB_GLOB_GGPIO_GPO_RESET 0x0
9010 /* Extracts the ALT_USB_GLOB_GGPIO_GPO field value from a register. */
9011 #define ALT_USB_GLOB_GGPIO_GPO_GET(value) (((value) & 0xffff0000) >> 16)
9012 /* Produces a ALT_USB_GLOB_GGPIO_GPO register field value suitable for setting the register. */
9013 #define ALT_USB_GLOB_GGPIO_GPO_SET(value) (((value) << 16) & 0xffff0000)
9014 
9015 #ifndef __ASSEMBLY__
9016 /*
9017  * WARNING: The C register and register group struct declarations are provided for
9018  * convenience and illustrative purposes. They should, however, be used with
9019  * caution as the C language standard provides no guarantees about the alignment or
9020  * atomicity of device memory accesses. The recommended practice for writing
9021  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9022  * alt_write_word() functions.
9023  *
9024  * The struct declaration for register ALT_USB_GLOB_GGPIO.
9025  */
9026 struct ALT_USB_GLOB_GGPIO_s
9027 {
9028  const uint32_t gpi : 16; /* ALT_USB_GLOB_GGPIO_GPI */
9029  uint32_t gpo : 16; /* ALT_USB_GLOB_GGPIO_GPO */
9030 };
9031 
9032 /* The typedef declaration for register ALT_USB_GLOB_GGPIO. */
9033 typedef volatile struct ALT_USB_GLOB_GGPIO_s ALT_USB_GLOB_GGPIO_t;
9034 #endif /* __ASSEMBLY__ */
9035 
9036 /* The reset value of the ALT_USB_GLOB_GGPIO register. */
9037 #define ALT_USB_GLOB_GGPIO_RESET 0x00000000
9038 /* The byte offset of the ALT_USB_GLOB_GGPIO register from the beginning of the component. */
9039 #define ALT_USB_GLOB_GGPIO_OFST 0x38
9040 /* The address of the ALT_USB_GLOB_GGPIO register. */
9041 #define ALT_USB_GLOB_GGPIO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GGPIO_OFST))
9042 
9043 /*
9044  * Register : guid
9045  *
9046  * User ID Register
9047  *
9048  * Register Layout
9049  *
9050  * Bits | Access | Reset | Description
9051  * :-------|:-------|:-----------|:-----------------------
9052  * [31:0] | R | 0x12345678 | ALT_USB_GLOB_GUID_GUID
9053  *
9054  */
9055 /*
9056  * Field : guid
9057  *
9058  * User ID (UserID)
9059  *
9060  * Application-programmable ID field.
9061  *
9062  * Reset: Configurable
9063  *
9064  * Field Access Macros:
9065  *
9066  */
9067 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUID_GUID register field. */
9068 #define ALT_USB_GLOB_GUID_GUID_LSB 0
9069 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUID_GUID register field. */
9070 #define ALT_USB_GLOB_GUID_GUID_MSB 31
9071 /* The width in bits of the ALT_USB_GLOB_GUID_GUID register field. */
9072 #define ALT_USB_GLOB_GUID_GUID_WIDTH 32
9073 /* The mask used to set the ALT_USB_GLOB_GUID_GUID register field value. */
9074 #define ALT_USB_GLOB_GUID_GUID_SET_MSK 0xffffffff
9075 /* The mask used to clear the ALT_USB_GLOB_GUID_GUID register field value. */
9076 #define ALT_USB_GLOB_GUID_GUID_CLR_MSK 0x00000000
9077 /* The reset value of the ALT_USB_GLOB_GUID_GUID register field. */
9078 #define ALT_USB_GLOB_GUID_GUID_RESET 0x12345678
9079 /* Extracts the ALT_USB_GLOB_GUID_GUID field value from a register. */
9080 #define ALT_USB_GLOB_GUID_GUID_GET(value) (((value) & 0xffffffff) >> 0)
9081 /* Produces a ALT_USB_GLOB_GUID_GUID register field value suitable for setting the register. */
9082 #define ALT_USB_GLOB_GUID_GUID_SET(value) (((value) << 0) & 0xffffffff)
9083 
9084 #ifndef __ASSEMBLY__
9085 /*
9086  * WARNING: The C register and register group struct declarations are provided for
9087  * convenience and illustrative purposes. They should, however, be used with
9088  * caution as the C language standard provides no guarantees about the alignment or
9089  * atomicity of device memory accesses. The recommended practice for writing
9090  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9091  * alt_write_word() functions.
9092  *
9093  * The struct declaration for register ALT_USB_GLOB_GUID.
9094  */
9095 struct ALT_USB_GLOB_GUID_s
9096 {
9097  const uint32_t guid : 32; /* ALT_USB_GLOB_GUID_GUID */
9098 };
9099 
9100 /* The typedef declaration for register ALT_USB_GLOB_GUID. */
9101 typedef volatile struct ALT_USB_GLOB_GUID_s ALT_USB_GLOB_GUID_t;
9102 #endif /* __ASSEMBLY__ */
9103 
9104 /* The reset value of the ALT_USB_GLOB_GUID register. */
9105 #define ALT_USB_GLOB_GUID_RESET 0x12345678
9106 /* The byte offset of the ALT_USB_GLOB_GUID register from the beginning of the component. */
9107 #define ALT_USB_GLOB_GUID_OFST 0x3c
9108 /* The address of the ALT_USB_GLOB_GUID register. */
9109 #define ALT_USB_GLOB_GUID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GUID_OFST))
9110 
9111 /*
9112  * Register : gsnpsid
9113  *
9114  * Synopsys ID Register
9115  *
9116  * Register Layout
9117  *
9118  * Bits | Access | Reset | Description
9119  * :-------|:-------|:-----------|:-----------------------------
9120  * [31:0] | R | 0x4f54320a | ALT_USB_GLOB_GSNPSID_GSNPSID
9121  *
9122  */
9123 /*
9124  * Field : gsnpsid
9125  *
9126  * Release number of the DWC_otg core being used is currently
9127  *
9128  * OTG
9129  *
9130  * Field Access Macros:
9131  *
9132  */
9133 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */
9134 #define ALT_USB_GLOB_GSNPSID_GSNPSID_LSB 0
9135 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */
9136 #define ALT_USB_GLOB_GSNPSID_GSNPSID_MSB 31
9137 /* The width in bits of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */
9138 #define ALT_USB_GLOB_GSNPSID_GSNPSID_WIDTH 32
9139 /* The mask used to set the ALT_USB_GLOB_GSNPSID_GSNPSID register field value. */
9140 #define ALT_USB_GLOB_GSNPSID_GSNPSID_SET_MSK 0xffffffff
9141 /* The mask used to clear the ALT_USB_GLOB_GSNPSID_GSNPSID register field value. */
9142 #define ALT_USB_GLOB_GSNPSID_GSNPSID_CLR_MSK 0x00000000
9143 /* The reset value of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */
9144 #define ALT_USB_GLOB_GSNPSID_GSNPSID_RESET 0x4f54320a
9145 /* Extracts the ALT_USB_GLOB_GSNPSID_GSNPSID field value from a register. */
9146 #define ALT_USB_GLOB_GSNPSID_GSNPSID_GET(value) (((value) & 0xffffffff) >> 0)
9147 /* Produces a ALT_USB_GLOB_GSNPSID_GSNPSID register field value suitable for setting the register. */
9148 #define ALT_USB_GLOB_GSNPSID_GSNPSID_SET(value) (((value) << 0) & 0xffffffff)
9149 
9150 #ifndef __ASSEMBLY__
9151 /*
9152  * WARNING: The C register and register group struct declarations are provided for
9153  * convenience and illustrative purposes. They should, however, be used with
9154  * caution as the C language standard provides no guarantees about the alignment or
9155  * atomicity of device memory accesses. The recommended practice for writing
9156  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9157  * alt_write_word() functions.
9158  *
9159  * The struct declaration for register ALT_USB_GLOB_GSNPSID.
9160  */
9161 struct ALT_USB_GLOB_GSNPSID_s
9162 {
9163  const uint32_t gsnpsid : 32; /* ALT_USB_GLOB_GSNPSID_GSNPSID */
9164 };
9165 
9166 /* The typedef declaration for register ALT_USB_GLOB_GSNPSID. */
9167 typedef volatile struct ALT_USB_GLOB_GSNPSID_s ALT_USB_GLOB_GSNPSID_t;
9168 #endif /* __ASSEMBLY__ */
9169 
9170 /* The reset value of the ALT_USB_GLOB_GSNPSID register. */
9171 #define ALT_USB_GLOB_GSNPSID_RESET 0x4f54320a
9172 /* The byte offset of the ALT_USB_GLOB_GSNPSID register from the beginning of the component. */
9173 #define ALT_USB_GLOB_GSNPSID_OFST 0x40
9174 /* The address of the ALT_USB_GLOB_GSNPSID register. */
9175 #define ALT_USB_GLOB_GSNPSID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GSNPSID_OFST))
9176 
9177 /*
9178  * Register : ghwcfg1
9179  *
9180  * User HW Config1 Register
9181  *
9182  * Register Layout
9183  *
9184  * Bits | Access | Reset | Description
9185  * :-------|:-------|:------|:-----------------------------
9186  * [31:0] | R | 0x0 | ALT_USB_GLOB_GHWCFG1_GHWCFG1
9187  *
9188  */
9189 /*
9190  * Field : ghwcfg1
9191  *
9192  * This 32-bit field uses two bits per
9193  *
9194  * endpoint to determine the endpoint direction.
9195  *
9196  * Endpoint
9197  *
9198  * Bits [31:30]: Endpoint 15 direction
9199  *
9200  * Bits [29:28]: Endpoint 14 direction
9201  *
9202  * ...
9203  *
9204  * Bits [3:2]: Endpoint 1 direction
9205  *
9206  * Bits[1:0]: Endpoint 0 direction (always BIDIR)
9207  *
9208  * Direction
9209  *
9210  * 2'b00: BIDIR (IN and OUT) endpoint
9211  *
9212  * 2'b01: IN endpoint
9213  *
9214  * 2'b10: OUT endpoint
9215  *
9216  * 2'b11: Reserved
9217  *
9218  * Field Enumeration Values:
9219  *
9220  * Enum | Value | Description
9221  * :----------------------------------------|:------|:----------------------------
9222  * ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_BDIR | 0x0 | BIDIR (IN and OUT) endpoint
9223  * ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_INENDPT | 0x1 | IN endpoint
9224  * ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_OUTENDPT | 0x2 | OUT endpoint
9225  * ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_RSVD | 0x3 | Reserved
9226  *
9227  * Field Access Macros:
9228  *
9229  */
9230 /*
9231  * Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1
9232  *
9233  * BIDIR (IN and OUT) endpoint
9234  */
9235 #define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_BDIR 0x0
9236 /*
9237  * Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1
9238  *
9239  * IN endpoint
9240  */
9241 #define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_INENDPT 0x1
9242 /*
9243  * Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1
9244  *
9245  * OUT endpoint
9246  */
9247 #define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_OUTENDPT 0x2
9248 /*
9249  * Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1
9250  *
9251  * Reserved
9252  */
9253 #define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_RSVD 0x3
9254 
9255 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */
9256 #define ALT_USB_GLOB_GHWCFG1_GHWCFG1_LSB 0
9257 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */
9258 #define ALT_USB_GLOB_GHWCFG1_GHWCFG1_MSB 31
9259 /* The width in bits of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */
9260 #define ALT_USB_GLOB_GHWCFG1_GHWCFG1_WIDTH 32
9261 /* The mask used to set the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field value. */
9262 #define ALT_USB_GLOB_GHWCFG1_GHWCFG1_SET_MSK 0xffffffff
9263 /* The mask used to clear the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field value. */
9264 #define ALT_USB_GLOB_GHWCFG1_GHWCFG1_CLR_MSK 0x00000000
9265 /* The reset value of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */
9266 #define ALT_USB_GLOB_GHWCFG1_GHWCFG1_RESET 0x0
9267 /* Extracts the ALT_USB_GLOB_GHWCFG1_GHWCFG1 field value from a register. */
9268 #define ALT_USB_GLOB_GHWCFG1_GHWCFG1_GET(value) (((value) & 0xffffffff) >> 0)
9269 /* Produces a ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field value suitable for setting the register. */
9270 #define ALT_USB_GLOB_GHWCFG1_GHWCFG1_SET(value) (((value) << 0) & 0xffffffff)
9271 
9272 #ifndef __ASSEMBLY__
9273 /*
9274  * WARNING: The C register and register group struct declarations are provided for
9275  * convenience and illustrative purposes. They should, however, be used with
9276  * caution as the C language standard provides no guarantees about the alignment or
9277  * atomicity of device memory accesses. The recommended practice for writing
9278  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9279  * alt_write_word() functions.
9280  *
9281  * The struct declaration for register ALT_USB_GLOB_GHWCFG1.
9282  */
9283 struct ALT_USB_GLOB_GHWCFG1_s
9284 {
9285  const uint32_t ghwcfg1 : 32; /* ALT_USB_GLOB_GHWCFG1_GHWCFG1 */
9286 };
9287 
9288 /* The typedef declaration for register ALT_USB_GLOB_GHWCFG1. */
9289 typedef volatile struct ALT_USB_GLOB_GHWCFG1_s ALT_USB_GLOB_GHWCFG1_t;
9290 #endif /* __ASSEMBLY__ */
9291 
9292 /* The reset value of the ALT_USB_GLOB_GHWCFG1 register. */
9293 #define ALT_USB_GLOB_GHWCFG1_RESET 0x00000000
9294 /* The byte offset of the ALT_USB_GLOB_GHWCFG1 register from the beginning of the component. */
9295 #define ALT_USB_GLOB_GHWCFG1_OFST 0x44
9296 /* The address of the ALT_USB_GLOB_GHWCFG1 register. */
9297 #define ALT_USB_GLOB_GHWCFG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG1_OFST))
9298 
9299 /*
9300  * Register : ghwcfg2
9301  *
9302  * User HW Config2 Register
9303  *
9304  * Register Layout
9305  *
9306  * Bits | Access | Reset | Description
9307  * :--------|:-------|:------|:-------------------------------------
9308  * [2:0] | R | 0x0 | ALT_USB_GLOB_GHWCFG2_OTGMOD
9309  * [4:3] | R | 0x2 | ALT_USB_GLOB_GHWCFG2_OTGARCH
9310  * [5] | R | 0x0 | ALT_USB_GLOB_GHWCFG2_SINGPNT
9311  * [7:6] | R | 0x2 | ALT_USB_GLOB_GHWCFG2_HSPHYTYPE
9312  * [9:8] | R | 0x0 | ALT_USB_GLOB_GHWCFG2_FSPHYTYPE
9313  * [13:10] | R | 0xf | ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9314  * [17:14] | R | 0xf | ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9315  * [18] | R | 0x1 | ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT
9316  * [19] | R | 0x1 | ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING
9317  * [20] | R | 0x0 | ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT
9318  * [21] | ??? | 0x0 | *UNDEFINED*
9319  * [23:22] | R | 0x2 | ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH
9320  * [25:24] | R | 0x0 | ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
9321  * [30:26] | R | 0x8 | ALT_USB_GLOB_GHWCFG2_TKNQDEPTH
9322  * [31] | ??? | 0x0 | *UNDEFINED*
9323  *
9324  */
9325 /*
9326  * Field : otgmode
9327  *
9328  * Mode of Operation (OtgMode)
9329  *
9330  * 3'b000: HNP- and SRP-Capable OTG (Host & Device)
9331  *
9332  * 3'b001: SRP-Capable OTG (Host & Device)
9333  *
9334  * 3'b010: Non-HNP and Non-SRP Capable OTG (Host &
9335  *
9336  * Device)
9337  *
9338  * 3'b011: SRP-Capable Device
9339  *
9340  * 3'b100: Non-OTG Device
9341  *
9342  * 3'b101: SRP-Capable Host
9343  *
9344  * 3'b110: Non-OTG Host
9345  *
9346  * Others: Reserved
9347  *
9348  * Field Enumeration Values:
9349  *
9350  * Enum | Value | Description
9351  * :---------------------------------------|:------|:------------------------------------------------
9352  * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_HNPSRP | 0x0 | HNP- and SRP-Capable OTG (Host & Device
9353  * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPOTG | 0x1 | SRP-Capable OTG (Host & Device)
9354  * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NHNPNSRP | 0x2 | Non-HNP and Non-SRP Capable OTG (Host & Device)
9355  * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPD | 0x3 | SRP-Capable Device
9356  * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGD | 0x4 | Non-OTG Device
9357  * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPH | 0x5 | SRP-Capable Host
9358  * ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGH | 0x6 | Non-OTG Host
9359  *
9360  * Field Access Macros:
9361  *
9362  */
9363 /*
9364  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
9365  *
9366  * HNP- and SRP-Capable OTG (Host & Device
9367  */
9368 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_HNPSRP 0x0
9369 /*
9370  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
9371  *
9372  * SRP-Capable OTG (Host & Device)
9373  */
9374 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPOTG 0x1
9375 /*
9376  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
9377  *
9378  * Non-HNP and Non-SRP Capable OTG (Host & Device)
9379  */
9380 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NHNPNSRP 0x2
9381 /*
9382  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
9383  *
9384  * SRP-Capable Device
9385  */
9386 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPD 0x3
9387 /*
9388  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
9389  *
9390  * Non-OTG Device
9391  */
9392 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGD 0x4
9393 /*
9394  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
9395  *
9396  * SRP-Capable Host
9397  */
9398 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPH 0x5
9399 /*
9400  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
9401  *
9402  * Non-OTG Host
9403  */
9404 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGH 0x6
9405 
9406 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */
9407 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_LSB 0
9408 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */
9409 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_MSB 2
9410 /* The width in bits of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */
9411 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_WIDTH 3
9412 /* The mask used to set the ALT_USB_GLOB_GHWCFG2_OTGMOD register field value. */
9413 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_SET_MSK 0x00000007
9414 /* The mask used to clear the ALT_USB_GLOB_GHWCFG2_OTGMOD register field value. */
9415 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_CLR_MSK 0xfffffff8
9416 /* The reset value of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */
9417 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_RESET 0x0
9418 /* Extracts the ALT_USB_GLOB_GHWCFG2_OTGMOD field value from a register. */
9419 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_GET(value) (((value) & 0x00000007) >> 0)
9420 /* Produces a ALT_USB_GLOB_GHWCFG2_OTGMOD register field value suitable for setting the register. */
9421 #define ALT_USB_GLOB_GHWCFG2_OTGMOD_SET(value) (((value) << 0) & 0x00000007)
9422 
9423 /*
9424  * Field : otgarch
9425  *
9426  * Architecture (OtgArch)
9427  *
9428  * 2'b00: Slave-Only
9429  *
9430  * 2'b01: External DMA
9431  *
9432  * 2'b10: Internal DMA
9433  *
9434  * Others: Reserved
9435  *
9436  * Field Enumeration Values:
9437  *
9438  * Enum | Value | Description
9439  * :--------------------------------------|:------|:-------------
9440  * ALT_USB_GLOB_GHWCFG2_OTGARCH_E_DMAMOD | 0x2 | Internal DMA
9441  *
9442  * Field Access Macros:
9443  *
9444  */
9445 /*
9446  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGARCH
9447  *
9448  * Internal DMA
9449  */
9450 #define ALT_USB_GLOB_GHWCFG2_OTGARCH_E_DMAMOD 0x2
9451 
9452 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */
9453 #define ALT_USB_GLOB_GHWCFG2_OTGARCH_LSB 3
9454 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */
9455 #define ALT_USB_GLOB_GHWCFG2_OTGARCH_MSB 4
9456 /* The width in bits of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */
9457 #define ALT_USB_GLOB_GHWCFG2_OTGARCH_WIDTH 2
9458 /* The mask used to set the ALT_USB_GLOB_GHWCFG2_OTGARCH register field value. */
9459 #define ALT_USB_GLOB_GHWCFG2_OTGARCH_SET_MSK 0x00000018
9460 /* The mask used to clear the ALT_USB_GLOB_GHWCFG2_OTGARCH register field value. */
9461 #define ALT_USB_GLOB_GHWCFG2_OTGARCH_CLR_MSK 0xffffffe7
9462 /* The reset value of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */
9463 #define ALT_USB_GLOB_GHWCFG2_OTGARCH_RESET 0x2
9464 /* Extracts the ALT_USB_GLOB_GHWCFG2_OTGARCH field value from a register. */
9465 #define ALT_USB_GLOB_GHWCFG2_OTGARCH_GET(value) (((value) & 0x00000018) >> 3)
9466 /* Produces a ALT_USB_GLOB_GHWCFG2_OTGARCH register field value suitable for setting the register. */
9467 #define ALT_USB_GLOB_GHWCFG2_OTGARCH_SET(value) (((value) << 3) & 0x00000018)
9468 
9469 /*
9470  * Field : singpnt
9471  *
9472  * Point-to-Point (SingPnt)
9473  *
9474  * 1'b0: Multi-point application (hub and split support)
9475  *
9476  * 1'b1: Single-point application (no hub and split support)
9477  *
9478  * Field Enumeration Values:
9479  *
9480  * Enum | Value | Description
9481  * :-------------------------------------------|:------|:------------------------
9482  * ALT_USB_GLOB_GHWCFG2_SINGPNT_E_SINGLEPOINT | 0x1 | Single-point applicatio
9483  *
9484  * Field Access Macros:
9485  *
9486  */
9487 /*
9488  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_SINGPNT
9489  *
9490  * Single-point applicatio
9491  */
9492 #define ALT_USB_GLOB_GHWCFG2_SINGPNT_E_SINGLEPOINT 0x1
9493 
9494 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */
9495 #define ALT_USB_GLOB_GHWCFG2_SINGPNT_LSB 5
9496 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */
9497 #define ALT_USB_GLOB_GHWCFG2_SINGPNT_MSB 5
9498 /* The width in bits of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */
9499 #define ALT_USB_GLOB_GHWCFG2_SINGPNT_WIDTH 1
9500 /* The mask used to set the ALT_USB_GLOB_GHWCFG2_SINGPNT register field value. */
9501 #define ALT_USB_GLOB_GHWCFG2_SINGPNT_SET_MSK 0x00000020
9502 /* The mask used to clear the ALT_USB_GLOB_GHWCFG2_SINGPNT register field value. */
9503 #define ALT_USB_GLOB_GHWCFG2_SINGPNT_CLR_MSK 0xffffffdf
9504 /* The reset value of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */
9505 #define ALT_USB_GLOB_GHWCFG2_SINGPNT_RESET 0x0
9506 /* Extracts the ALT_USB_GLOB_GHWCFG2_SINGPNT field value from a register. */
9507 #define ALT_USB_GLOB_GHWCFG2_SINGPNT_GET(value) (((value) & 0x00000020) >> 5)
9508 /* Produces a ALT_USB_GLOB_GHWCFG2_SINGPNT register field value suitable for setting the register. */
9509 #define ALT_USB_GLOB_GHWCFG2_SINGPNT_SET(value) (((value) << 5) & 0x00000020)
9510 
9511 /*
9512  * Field : hsphytype
9513  *
9514  * High-Speed PHY Interface Type (HSPhyType)
9515  *
9516  * 2'b00: High-Speed interface not supported
9517  *
9518  * 2'b01: UTMI+
9519  *
9520  * 2'b10: ULPI
9521  *
9522  * 2'b11: UTMI+ and ULPI
9523  *
9524  * Field Enumeration Values:
9525  *
9526  * Enum | Value | Description
9527  * :--------------------------------------|:------|:-----------------------------------
9528  * ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_NOHS | 0x0 | High-Speed interface not supported
9529  * ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_ULPI | 0x2 | ULPI
9530  *
9531  * Field Access Macros:
9532  *
9533  */
9534 /*
9535  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_HSPHYTYPE
9536  *
9537  * High-Speed interface not supported
9538  */
9539 #define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_NOHS 0x0
9540 /*
9541  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_HSPHYTYPE
9542  *
9543  * ULPI
9544  */
9545 #define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_ULPI 0x2
9546 
9547 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */
9548 #define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_LSB 6
9549 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */
9550 #define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_MSB 7
9551 /* The width in bits of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */
9552 #define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_WIDTH 2
9553 /* The mask used to set the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field value. */
9554 #define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_SET_MSK 0x000000c0
9555 /* The mask used to clear the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field value. */
9556 #define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_CLR_MSK 0xffffff3f
9557 /* The reset value of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */
9558 #define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_RESET 0x2
9559 /* Extracts the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE field value from a register. */
9560 #define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_GET(value) (((value) & 0x000000c0) >> 6)
9561 /* Produces a ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field value suitable for setting the register. */
9562 #define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_SET(value) (((value) << 6) & 0x000000c0)
9563 
9564 /*
9565  * Field : fsphytype
9566  *
9567  * Full-Speed PHY Interface Type (FSPhyType)
9568  *
9569  * 2'b00: Full-speed interface not supported
9570  *
9571  * 2'b01: Dedicated full-speed interface
9572  *
9573  * 2'b10: FS pins shared with UTMI+ pins
9574  *
9575  * 2'b11: FS pins shared with ULPI pins
9576  *
9577  * Field Enumeration Values:
9578  *
9579  * Enum | Value | Description
9580  * :-------------------------------------------|:------|:------------
9581  * ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_E_FULLSPEED | 0x2 | ULPI Type
9582  *
9583  * Field Access Macros:
9584  *
9585  */
9586 /*
9587  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_FSPHYTYPE
9588  *
9589  * ULPI Type
9590  */
9591 #define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_E_FULLSPEED 0x2
9592 
9593 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */
9594 #define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_LSB 8
9595 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */
9596 #define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_MSB 9
9597 /* The width in bits of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */
9598 #define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_WIDTH 2
9599 /* The mask used to set the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field value. */
9600 #define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_SET_MSK 0x00000300
9601 /* The mask used to clear the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field value. */
9602 #define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_CLR_MSK 0xfffffcff
9603 /* The reset value of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */
9604 #define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_RESET 0x0
9605 /* Extracts the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE field value from a register. */
9606 #define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_GET(value) (((value) & 0x00000300) >> 8)
9607 /* Produces a ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field value suitable for setting the register. */
9608 #define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_SET(value) (((value) << 8) & 0x00000300)
9609 
9610 /*
9611  * Field : numdeveps
9612  *
9613  * Number of Device Endpoints (NumDevEps)
9614  *
9615  * Indicates the number of device endpoints supported by the core
9616  *
9617  * in Device mode in addition to control endpoint 0. The range of
9618  *
9619  * this field is 1-15.
9620  *
9621  * Field Enumeration Values:
9622  *
9623  * Enum | Value | Description
9624  * :-----------------------------------------|:------|:--------------
9625  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT0 | 0x0 | End point 0
9626  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT1 | 0x1 | End point 1
9627  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT2 | 0x2 | End point 2
9628  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT3 | 0x3 | End point 3
9629  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT4 | 0x4 | End point 4
9630  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT5 | 0x5 | End point 5
9631  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT6 | 0x6 | End point 6
9632  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT7 | 0x7 | End point 7
9633  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT8 | 0x8 | End point 8
9634  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT9 | 0x9 | End point 9
9635  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT10 | 0xa | End point 10
9636  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT11 | 0xb | End point 11
9637  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT12 | 0xc | End point 12
9638  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT13 | 0xd | End point 13
9639  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT14 | 0xe | End point 14
9640  * ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT15 | 0xf | End point 15
9641  *
9642  * Field Access Macros:
9643  *
9644  */
9645 /*
9646  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9647  *
9648  * End point 0
9649  */
9650 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT0 0x0
9651 /*
9652  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9653  *
9654  * End point 1
9655  */
9656 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT1 0x1
9657 /*
9658  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9659  *
9660  * End point 2
9661  */
9662 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT2 0x2
9663 /*
9664  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9665  *
9666  * End point 3
9667  */
9668 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT3 0x3
9669 /*
9670  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9671  *
9672  * End point 4
9673  */
9674 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT4 0x4
9675 /*
9676  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9677  *
9678  * End point 5
9679  */
9680 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT5 0x5
9681 /*
9682  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9683  *
9684  * End point 6
9685  */
9686 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT6 0x6
9687 /*
9688  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9689  *
9690  * End point 7
9691  */
9692 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT7 0x7
9693 /*
9694  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9695  *
9696  * End point 8
9697  */
9698 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT8 0x8
9699 /*
9700  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9701  *
9702  * End point 9
9703  */
9704 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT9 0x9
9705 /*
9706  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9707  *
9708  * End point 10
9709  */
9710 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT10 0xa
9711 /*
9712  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9713  *
9714  * End point 11
9715  */
9716 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT11 0xb
9717 /*
9718  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9719  *
9720  * End point 12
9721  */
9722 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT12 0xc
9723 /*
9724  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9725  *
9726  * End point 13
9727  */
9728 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT13 0xd
9729 /*
9730  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9731  *
9732  * End point 14
9733  */
9734 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT14 0xe
9735 /*
9736  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
9737  *
9738  * End point 15
9739  */
9740 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT15 0xf
9741 
9742 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */
9743 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_LSB 10
9744 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */
9745 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_MSB 13
9746 /* The width in bits of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */
9747 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_WIDTH 4
9748 /* The mask used to set the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field value. */
9749 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_SET_MSK 0x00003c00
9750 /* The mask used to clear the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field value. */
9751 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_CLR_MSK 0xffffc3ff
9752 /* The reset value of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */
9753 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_RESET 0xf
9754 /* Extracts the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS field value from a register. */
9755 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_GET(value) (((value) & 0x00003c00) >> 10)
9756 /* Produces a ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field value suitable for setting the register. */
9757 #define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_SET(value) (((value) << 10) & 0x00003c00)
9758 
9759 /*
9760  * Field : numhstchnl
9761  *
9762  * Number of Host Channels (NumHstChnl)
9763  *
9764  * Indicates the number of host channels supported by the core in
9765  *
9766  * Host mode. The range of this field is 0-15: 0 specifies 1 channel,
9767  *
9768  * 15 specifies 16 channels.
9769  *
9770  * Field Enumeration Values:
9771  *
9772  * Enum | Value | Description
9773  * :-------------------------------------------|:------|:----------------
9774  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH0 | 0x0 | Host Channel 1
9775  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH1 | 0x1 | Host Channel 2
9776  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH2 | 0x2 | Host Channel 3
9777  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH3 | 0x3 | Host Channel 4
9778  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH4 | 0x4 | Host Channel 5
9779  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH5 | 0x5 | Host Channel 6
9780  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH6 | 0x6 | Host Channel 7
9781  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH7 | 0x7 | Host Channel 8
9782  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH8 | 0x8 | Host Channel 9
9783  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH9 | 0x9 | Host Channel 10
9784  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH10 | 0xa | Host Channel 11
9785  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH11 | 0xb | Host Channel 12
9786  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH12 | 0xc | Host Channel 13
9787  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH13 | 0xd | Host Channel 14
9788  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH14 | 0xe | Host Channel 15
9789  * ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH15 | 0xf | Host Channel 16
9790  *
9791  * Field Access Macros:
9792  *
9793  */
9794 /*
9795  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9796  *
9797  * Host Channel 1
9798  */
9799 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH0 0x0
9800 /*
9801  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9802  *
9803  * Host Channel 2
9804  */
9805 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH1 0x1
9806 /*
9807  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9808  *
9809  * Host Channel 3
9810  */
9811 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH2 0x2
9812 /*
9813  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9814  *
9815  * Host Channel 4
9816  */
9817 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH3 0x3
9818 /*
9819  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9820  *
9821  * Host Channel 5
9822  */
9823 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH4 0x4
9824 /*
9825  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9826  *
9827  * Host Channel 6
9828  */
9829 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH5 0x5
9830 /*
9831  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9832  *
9833  * Host Channel 7
9834  */
9835 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH6 0x6
9836 /*
9837  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9838  *
9839  * Host Channel 8
9840  */
9841 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH7 0x7
9842 /*
9843  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9844  *
9845  * Host Channel 9
9846  */
9847 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH8 0x8
9848 /*
9849  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9850  *
9851  * Host Channel 10
9852  */
9853 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH9 0x9
9854 /*
9855  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9856  *
9857  * Host Channel 11
9858  */
9859 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH10 0xa
9860 /*
9861  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9862  *
9863  * Host Channel 12
9864  */
9865 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH11 0xb
9866 /*
9867  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9868  *
9869  * Host Channel 13
9870  */
9871 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH12 0xc
9872 /*
9873  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9874  *
9875  * Host Channel 14
9876  */
9877 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH13 0xd
9878 /*
9879  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9880  *
9881  * Host Channel 15
9882  */
9883 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH14 0xe
9884 /*
9885  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
9886  *
9887  * Host Channel 16
9888  */
9889 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH15 0xf
9890 
9891 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */
9892 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_LSB 14
9893 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */
9894 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_MSB 17
9895 /* The width in bits of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */
9896 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_WIDTH 4
9897 /* The mask used to set the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field value. */
9898 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_SET_MSK 0x0003c000
9899 /* The mask used to clear the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field value. */
9900 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_CLR_MSK 0xfffc3fff
9901 /* The reset value of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */
9902 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_RESET 0xf
9903 /* Extracts the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL field value from a register. */
9904 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_GET(value) (((value) & 0x0003c000) >> 14)
9905 /* Produces a ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field value suitable for setting the register. */
9906 #define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_SET(value) (((value) << 14) & 0x0003c000)
9907 
9908 /*
9909  * Field : periosupport
9910  *
9911  * Periodic OUT Channels Supported in Host Mode (PerioSupport)
9912  *
9913  * 1'b0: No
9914  *
9915  * 1'b1: Yes
9916  *
9917  * Field Enumeration Values:
9918  *
9919  * Enum | Value | Description
9920  * :----------------------------------------|:------|:---------------------------------------------
9921  * ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_E_END | 0x1 | Periodic OUT Channels Supported in Host Mode
9922  * : | | Supported
9923  *
9924  * Field Access Macros:
9925  *
9926  */
9927 /*
9928  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT
9929  *
9930  * Periodic OUT Channels Supported in Host Mode Supported
9931  */
9932 #define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_E_END 0x1
9933 
9934 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */
9935 #define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_LSB 18
9936 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */
9937 #define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_MSB 18
9938 /* The width in bits of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */
9939 #define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_WIDTH 1
9940 /* The mask used to set the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field value. */
9941 #define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_SET_MSK 0x00040000
9942 /* The mask used to clear the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field value. */
9943 #define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_CLR_MSK 0xfffbffff
9944 /* The reset value of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */
9945 #define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_RESET 0x1
9946 /* Extracts the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT field value from a register. */
9947 #define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_GET(value) (((value) & 0x00040000) >> 18)
9948 /* Produces a ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field value suitable for setting the register. */
9949 #define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_SET(value) (((value) << 18) & 0x00040000)
9950 
9951 /*
9952  * Field : dynfifosizing
9953  *
9954  * Dynamic FIFO Sizing Enabled (DynFifoSizing)
9955  *
9956  * 1'b0: No
9957  *
9958  * 1'b1: Yes
9959  *
9960  * Field Enumeration Values:
9961  *
9962  * Enum | Value | Description
9963  * :-----------------------------------------|:------|:----------------------------
9964  * ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_E_END | 0x1 | Dynamic FIFO Sizing Enabled
9965  *
9966  * Field Access Macros:
9967  *
9968  */
9969 /*
9970  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING
9971  *
9972  * Dynamic FIFO Sizing Enabled
9973  */
9974 #define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_E_END 0x1
9975 
9976 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */
9977 #define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_LSB 19
9978 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */
9979 #define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_MSB 19
9980 /* The width in bits of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */
9981 #define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_WIDTH 1
9982 /* The mask used to set the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field value. */
9983 #define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_SET_MSK 0x00080000
9984 /* The mask used to clear the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field value. */
9985 #define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_CLR_MSK 0xfff7ffff
9986 /* The reset value of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */
9987 #define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_RESET 0x1
9988 /* Extracts the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING field value from a register. */
9989 #define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_GET(value) (((value) & 0x00080000) >> 19)
9990 /* Produces a ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field value suitable for setting the register. */
9991 #define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_SET(value) (((value) << 19) & 0x00080000)
9992 
9993 /*
9994  * Field : multiprocintrpt
9995  *
9996  * Multi Processor Interrupt Enabled (MultiProcIntrpt)
9997  *
9998  * 1'b0: No
9999  *
10000  * 1'b1: Yes
10001  *
10002  * Field Enumeration Values:
10003  *
10004  * Enum | Value | Description
10005  * :--------------------------------------------|:------|:-------------------------------------
10006  * ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_E_DISD | 0x0 | No Multi Processor Interrupt Enabled
10007  *
10008  * Field Access Macros:
10009  *
10010  */
10011 /*
10012  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT
10013  *
10014  * No Multi Processor Interrupt Enabled
10015  */
10016 #define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_E_DISD 0x0
10017 
10018 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */
10019 #define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_LSB 20
10020 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */
10021 #define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_MSB 20
10022 /* The width in bits of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */
10023 #define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_WIDTH 1
10024 /* The mask used to set the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field value. */
10025 #define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_SET_MSK 0x00100000
10026 /* The mask used to clear the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field value. */
10027 #define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_CLR_MSK 0xffefffff
10028 /* The reset value of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */
10029 #define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_RESET 0x0
10030 /* Extracts the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT field value from a register. */
10031 #define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_GET(value) (((value) & 0x00100000) >> 20)
10032 /* Produces a ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field value suitable for setting the register. */
10033 #define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_SET(value) (((value) << 20) & 0x00100000)
10034 
10035 /*
10036  * Field : nptxqdepth
10037  *
10038  * Non-periodic Request Queue Depth (NPTxQDepth)
10039  *
10040  * 2'b00: 2
10041  *
10042  * 2'b01: 4
10043  *
10044  * 2'b10: 8
10045  *
10046  * Others: Reserved
10047  *
10048  * Field Enumeration Values:
10049  *
10050  * Enum | Value | Description
10051  * :----------------------------------------|:------|:------------
10052  * ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_TWO | 0x0 | Que size 2
10053  * ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_FOUR | 0x1 | Que size 4
10054  * ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_EIGHT | 0x2 | Que size 8
10055  *
10056  * Field Access Macros:
10057  *
10058  */
10059 /*
10060  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH
10061  *
10062  * Que size 2
10063  */
10064 #define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_TWO 0x0
10065 /*
10066  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH
10067  *
10068  * Que size 4
10069  */
10070 #define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_FOUR 0x1
10071 /*
10072  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH
10073  *
10074  * Que size 8
10075  */
10076 #define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_EIGHT 0x2
10077 
10078 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */
10079 #define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_LSB 22
10080 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */
10081 #define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_MSB 23
10082 /* The width in bits of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */
10083 #define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_WIDTH 2
10084 /* The mask used to set the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field value. */
10085 #define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_SET_MSK 0x00c00000
10086 /* The mask used to clear the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field value. */
10087 #define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_CLR_MSK 0xff3fffff
10088 /* The reset value of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */
10089 #define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_RESET 0x2
10090 /* Extracts the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH field value from a register. */
10091 #define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_GET(value) (((value) & 0x00c00000) >> 22)
10092 /* Produces a ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field value suitable for setting the register. */
10093 #define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_SET(value) (((value) << 22) & 0x00c00000)
10094 
10095 /*
10096  * Field : ptxqdepth
10097  *
10098  * Host Mode Periodic Request Queue Depth (PTxQDepth)
10099  *
10100  * 2'b00: 2
10101  *
10102  * 2'b01: 4
10103  *
10104  * 2'b10: 8
10105  *
10106  * 2'b11:16
10107  *
10108  * Field Enumeration Values:
10109  *
10110  * Enum | Value | Description
10111  * :---------------------------------------|:------|:-------------
10112  * ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE2 | 0x0 | Que Depth 2
10113  * ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE4 | 0x1 | Que Depth 4
10114  * ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE8 | 0x2 | Que Depth 8
10115  * ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE16 | 0x3 | Que Depth 16
10116  *
10117  * Field Access Macros:
10118  *
10119  */
10120 /*
10121  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
10122  *
10123  * Que Depth 2
10124  */
10125 #define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE2 0x0
10126 /*
10127  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
10128  *
10129  * Que Depth 4
10130  */
10131 #define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE4 0x1
10132 /*
10133  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
10134  *
10135  * Que Depth 8
10136  */
10137 #define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE8 0x2
10138 /*
10139  * Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
10140  *
10141  * Que Depth 16
10142  */
10143 #define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE16 0x3
10144 
10145 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */
10146 #define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_LSB 24
10147 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */
10148 #define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_MSB 25
10149 /* The width in bits of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */
10150 #define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_WIDTH 2
10151 /* The mask used to set the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field value. */
10152 #define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_SET_MSK 0x03000000
10153 /* The mask used to clear the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field value. */
10154 #define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_CLR_MSK 0xfcffffff
10155 /* The reset value of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */
10156 #define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_RESET 0x0
10157 /* Extracts the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH field value from a register. */
10158 #define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_GET(value) (((value) & 0x03000000) >> 24)
10159 /* Produces a ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field value suitable for setting the register. */
10160 #define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_SET(value) (((value) << 24) & 0x03000000)
10161 
10162 /*
10163  * Field : tknqdepth
10164  *
10165  * Device Mode IN Token Sequence Learning Queue Depth
10166  *
10167  * (TknQDepth)
10168  *
10169  * Range: 0-30
10170  *
10171  * Field Access Macros:
10172  *
10173  */
10174 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */
10175 #define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_LSB 26
10176 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */
10177 #define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_MSB 30
10178 /* The width in bits of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */
10179 #define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_WIDTH 5
10180 /* The mask used to set the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field value. */
10181 #define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_SET_MSK 0x7c000000
10182 /* The mask used to clear the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field value. */
10183 #define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_CLR_MSK 0x83ffffff
10184 /* The reset value of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */
10185 #define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_RESET 0x8
10186 /* Extracts the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH field value from a register. */
10187 #define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_GET(value) (((value) & 0x7c000000) >> 26)
10188 /* Produces a ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field value suitable for setting the register. */
10189 #define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_SET(value) (((value) << 26) & 0x7c000000)
10190 
10191 #ifndef __ASSEMBLY__
10192 /*
10193  * WARNING: The C register and register group struct declarations are provided for
10194  * convenience and illustrative purposes. They should, however, be used with
10195  * caution as the C language standard provides no guarantees about the alignment or
10196  * atomicity of device memory accesses. The recommended practice for writing
10197  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10198  * alt_write_word() functions.
10199  *
10200  * The struct declaration for register ALT_USB_GLOB_GHWCFG2.
10201  */
10202 struct ALT_USB_GLOB_GHWCFG2_s
10203 {
10204  const uint32_t otgmode : 3; /* ALT_USB_GLOB_GHWCFG2_OTGMOD */
10205  const uint32_t otgarch : 2; /* ALT_USB_GLOB_GHWCFG2_OTGARCH */
10206  const uint32_t singpnt : 1; /* ALT_USB_GLOB_GHWCFG2_SINGPNT */
10207  const uint32_t hsphytype : 2; /* ALT_USB_GLOB_GHWCFG2_HSPHYTYPE */
10208  const uint32_t fsphytype : 2; /* ALT_USB_GLOB_GHWCFG2_FSPHYTYPE */
10209  const uint32_t numdeveps : 4; /* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS */
10210  const uint32_t numhstchnl : 4; /* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL */
10211  const uint32_t periosupport : 1; /* ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT */
10212  const uint32_t dynfifosizing : 1; /* ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING */
10213  const uint32_t multiprocintrpt : 1; /* ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT */
10214  uint32_t : 1; /* *UNDEFINED* */
10215  const uint32_t nptxqdepth : 2; /* ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH */
10216  const uint32_t ptxqdepth : 2; /* ALT_USB_GLOB_GHWCFG2_PTXQDEPTH */
10217  const uint32_t tknqdepth : 5; /* ALT_USB_GLOB_GHWCFG2_TKNQDEPTH */
10218  uint32_t : 1; /* *UNDEFINED* */
10219 };
10220 
10221 /* The typedef declaration for register ALT_USB_GLOB_GHWCFG2. */
10222 typedef volatile struct ALT_USB_GLOB_GHWCFG2_s ALT_USB_GLOB_GHWCFG2_t;
10223 #endif /* __ASSEMBLY__ */
10224 
10225 /* The reset value of the ALT_USB_GLOB_GHWCFG2 register. */
10226 #define ALT_USB_GLOB_GHWCFG2_RESET 0x208ffc90
10227 /* The byte offset of the ALT_USB_GLOB_GHWCFG2 register from the beginning of the component. */
10228 #define ALT_USB_GLOB_GHWCFG2_OFST 0x48
10229 /* The address of the ALT_USB_GLOB_GHWCFG2 register. */
10230 #define ALT_USB_GLOB_GHWCFG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG2_OFST))
10231 
10232 /*
10233  * Register : ghwcfg3
10234  *
10235  * User HW Config3 Register
10236  *
10237  * Register Layout
10238  *
10239  * Bits | Access | Reset | Description
10240  * :--------|:-------|:-------|:-----------------------------------
10241  * [3:0] | R | 0x8 | ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
10242  * [6:4] | R | 0x6 | ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
10243  * [7] | R | 0x1 | ALT_USB_GLOB_GHWCFG3_OTGEN
10244  * [8] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_I2CINTSEL
10245  * [9] | R | 0x1 | ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT
10246  * [10] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_OPTFEATURE
10247  * [11] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_RSTTYPE
10248  * [12] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_ADPSUPPORT
10249  * [13] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_HSICMOD
10250  * [14] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_BCSUPPORT
10251  * [15] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_LPMMOD
10252  * [31:16] | R | 0x1f80 | ALT_USB_GLOB_GHWCFG3_DFIFODEPTH
10253  *
10254  */
10255 /*
10256  * Field : xfersizewidth
10257  *
10258  * Width of Transfer Size Counters (XferSizeWidth)
10259  *
10260  * 4'b0000: 11 bits
10261  *
10262  * 4'b0001: 12 bits
10263  *
10264  * ...
10265  *
10266  * 4'b1000: 19 bits
10267  *
10268  * Others: Reserved
10269  *
10270  * Field Enumeration Values:
10271  *
10272  * Enum | Value | Description
10273  * :---------------------------------------------|:------|:---------------------------------------
10274  * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH11 | 0x0 | Width of Transfer Size Counter 11 bits
10275  * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH12 | 0x1 | Width of Transfer Size Counter 12 bits
10276  * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH13 | 0x2 | Width of Transfer Size Counter 13 bits
10277  * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH14 | 0x3 | Width of Transfer Size Counter 14 bits
10278  * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH15 | 0x4 | Width of Transfer Size Counter 15 bits
10279  * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH16 | 0x5 | Width of Transfer Size Counter 16 bits
10280  * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH17 | 0x6 | Width of Transfer Size Counter 17 bits
10281  * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH18 | 0x7 | Width of Transfer Size Counter 18 bits
10282  * ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH19 | 0x8 | Width of Transfer Size Counter 19 bits
10283  *
10284  * Field Access Macros:
10285  *
10286  */
10287 /*
10288  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
10289  *
10290  * Width of Transfer Size Counter 11 bits
10291  */
10292 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH11 0x0
10293 /*
10294  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
10295  *
10296  * Width of Transfer Size Counter 12 bits
10297  */
10298 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH12 0x1
10299 /*
10300  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
10301  *
10302  * Width of Transfer Size Counter 13 bits
10303  */
10304 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH13 0x2
10305 /*
10306  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
10307  *
10308  * Width of Transfer Size Counter 14 bits
10309  */
10310 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH14 0x3
10311 /*
10312  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
10313  *
10314  * Width of Transfer Size Counter 15 bits
10315  */
10316 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH15 0x4
10317 /*
10318  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
10319  *
10320  * Width of Transfer Size Counter 16 bits
10321  */
10322 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH16 0x5
10323 /*
10324  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
10325  *
10326  * Width of Transfer Size Counter 17 bits
10327  */
10328 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH17 0x6
10329 /*
10330  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
10331  *
10332  * Width of Transfer Size Counter 18 bits
10333  */
10334 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH18 0x7
10335 /*
10336  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
10337  *
10338  * Width of Transfer Size Counter 19 bits
10339  */
10340 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH19 0x8
10341 
10342 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */
10343 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_LSB 0
10344 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */
10345 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_MSB 3
10346 /* The width in bits of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */
10347 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_WIDTH 4
10348 /* The mask used to set the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field value. */
10349 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_SET_MSK 0x0000000f
10350 /* The mask used to clear the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field value. */
10351 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_CLR_MSK 0xfffffff0
10352 /* The reset value of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */
10353 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_RESET 0x8
10354 /* Extracts the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH field value from a register. */
10355 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_GET(value) (((value) & 0x0000000f) >> 0)
10356 /* Produces a ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field value suitable for setting the register. */
10357 #define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_SET(value) (((value) << 0) & 0x0000000f)
10358 
10359 /*
10360  * Field : pktsizewidth
10361  *
10362  * Width of Packet Size Counters (PktSizeWidth)
10363  *
10364  * 3'b000: 4 bits
10365  *
10366  * 3'b001: 5 bits
10367  *
10368  * 3'b010: 6 bits
10369  *
10370  * 3'b011: 7 bits
10371  *
10372  * 3'b100: 8 bits
10373  *
10374  * 3'b101: 9 bits
10375  *
10376  * 3'b110: 10 bits
10377  *
10378  * Others: Reserved
10379  *
10380  * Field Enumeration Values:
10381  *
10382  * Enum | Value | Description
10383  * :-------------------------------------------|:------|:--------------------------------
10384  * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS4 | 0x0 | Width of Packet Size Counter 4
10385  * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS5 | 0x1 | Width of Packet Size Counter 5
10386  * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS6 | 0x2 | Width of Packet Size Counter 6
10387  * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS7 | 0x3 | Width of Packet Size Counter 7
10388  * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS8 | 0x4 | Width of Packet Size Counter 8
10389  * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS9 | 0x5 | Width of Packet Size Counter 9
10390  * ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS10 | 0x6 | Width of Packet Size Counter 10
10391  *
10392  * Field Access Macros:
10393  *
10394  */
10395 /*
10396  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
10397  *
10398  * Width of Packet Size Counter 4
10399  */
10400 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS4 0x0
10401 /*
10402  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
10403  *
10404  * Width of Packet Size Counter 5
10405  */
10406 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS5 0x1
10407 /*
10408  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
10409  *
10410  * Width of Packet Size Counter 6
10411  */
10412 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS6 0x2
10413 /*
10414  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
10415  *
10416  * Width of Packet Size Counter 7
10417  */
10418 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS7 0x3
10419 /*
10420  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
10421  *
10422  * Width of Packet Size Counter 8
10423  */
10424 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS8 0x4
10425 /*
10426  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
10427  *
10428  * Width of Packet Size Counter 9
10429  */
10430 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS9 0x5
10431 /*
10432  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
10433  *
10434  * Width of Packet Size Counter 10
10435  */
10436 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS10 0x6
10437 
10438 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */
10439 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_LSB 4
10440 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */
10441 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_MSB 6
10442 /* The width in bits of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */
10443 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_WIDTH 3
10444 /* The mask used to set the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field value. */
10445 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_SET_MSK 0x00000070
10446 /* The mask used to clear the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field value. */
10447 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_CLR_MSK 0xffffff8f
10448 /* The reset value of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */
10449 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_RESET 0x6
10450 /* Extracts the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH field value from a register. */
10451 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_GET(value) (((value) & 0x00000070) >> 4)
10452 /* Produces a ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field value suitable for setting the register. */
10453 #define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_SET(value) (((value) << 4) & 0x00000070)
10454 
10455 /*
10456  * Field : otgen
10457  *
10458  * OTG Function Enabled (OtgEn)
10459  *
10460  * The application uses this bit to indicate the DWC_otg core's
10461  *
10462  * OTG capabilities.
10463  *
10464  * 1'b0: Not OTG capable
10465  *
10466  * 1'b1: OTG Capable
10467  *
10468  * Field Enumeration Values:
10469  *
10470  * Enum | Value | Description
10471  * :---------------------------------|:------|:------------
10472  * ALT_USB_GLOB_GHWCFG3_OTGEN_E_END | 0x1 | OTG Capable
10473  *
10474  * Field Access Macros:
10475  *
10476  */
10477 /*
10478  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_OTGEN
10479  *
10480  * OTG Capable
10481  */
10482 #define ALT_USB_GLOB_GHWCFG3_OTGEN_E_END 0x1
10483 
10484 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */
10485 #define ALT_USB_GLOB_GHWCFG3_OTGEN_LSB 7
10486 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */
10487 #define ALT_USB_GLOB_GHWCFG3_OTGEN_MSB 7
10488 /* The width in bits of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */
10489 #define ALT_USB_GLOB_GHWCFG3_OTGEN_WIDTH 1
10490 /* The mask used to set the ALT_USB_GLOB_GHWCFG3_OTGEN register field value. */
10491 #define ALT_USB_GLOB_GHWCFG3_OTGEN_SET_MSK 0x00000080
10492 /* The mask used to clear the ALT_USB_GLOB_GHWCFG3_OTGEN register field value. */
10493 #define ALT_USB_GLOB_GHWCFG3_OTGEN_CLR_MSK 0xffffff7f
10494 /* The reset value of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */
10495 #define ALT_USB_GLOB_GHWCFG3_OTGEN_RESET 0x1
10496 /* Extracts the ALT_USB_GLOB_GHWCFG3_OTGEN field value from a register. */
10497 #define ALT_USB_GLOB_GHWCFG3_OTGEN_GET(value) (((value) & 0x00000080) >> 7)
10498 /* Produces a ALT_USB_GLOB_GHWCFG3_OTGEN register field value suitable for setting the register. */
10499 #define ALT_USB_GLOB_GHWCFG3_OTGEN_SET(value) (((value) << 7) & 0x00000080)
10500 
10501 /*
10502  * Field : i2cintsel
10503  *
10504  * I2C Selection (I2CIntSel)
10505  *
10506  * 1'b0: I2C Interface is not available on the core.
10507  *
10508  * 1'b1: I2C Interface is available on the core.
10509  *
10510  * Field Enumeration Values:
10511  *
10512  * Enum | Value | Description
10513  * :--------------------------------------|:------|:--------------
10514  * ALT_USB_GLOB_GHWCFG3_I2CINTSEL_E_DISD | 0x0 | I2C Interface
10515  *
10516  * Field Access Macros:
10517  *
10518  */
10519 /*
10520  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_I2CINTSEL
10521  *
10522  * I2C Interface
10523  */
10524 #define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_E_DISD 0x0
10525 
10526 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */
10527 #define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_LSB 8
10528 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */
10529 #define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_MSB 8
10530 /* The width in bits of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */
10531 #define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_WIDTH 1
10532 /* The mask used to set the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field value. */
10533 #define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_SET_MSK 0x00000100
10534 /* The mask used to clear the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field value. */
10535 #define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_CLR_MSK 0xfffffeff
10536 /* The reset value of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */
10537 #define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_RESET 0x0
10538 /* Extracts the ALT_USB_GLOB_GHWCFG3_I2CINTSEL field value from a register. */
10539 #define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_GET(value) (((value) & 0x00000100) >> 8)
10540 /* Produces a ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field value suitable for setting the register. */
10541 #define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_SET(value) (((value) << 8) & 0x00000100)
10542 
10543 /*
10544  * Field : vndctlsupt
10545  *
10546  * Vendor Control Interface Support (VndctlSupt)
10547  *
10548  * 1'b0: Vendor Control Interface is not available on the core.
10549  *
10550  * 1'b1: Vendor Control Interface is available.
10551  *
10552  * Field Enumeration Values:
10553  *
10554  * Enum | Value | Description
10555  * :--------------------------------------|:------|:-------------------------------------------------
10556  * ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_E_END | 0x1 | Vendor Control Interface is not available on the
10557  *
10558  * Field Access Macros:
10559  *
10560  */
10561 /*
10562  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT
10563  *
10564  * Vendor Control Interface is not available on the
10565  */
10566 #define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_E_END 0x1
10567 
10568 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */
10569 #define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_LSB 9
10570 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */
10571 #define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_MSB 9
10572 /* The width in bits of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */
10573 #define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_WIDTH 1
10574 /* The mask used to set the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field value. */
10575 #define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_SET_MSK 0x00000200
10576 /* The mask used to clear the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field value. */
10577 #define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_CLR_MSK 0xfffffdff
10578 /* The reset value of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */
10579 #define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_RESET 0x1
10580 /* Extracts the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT field value from a register. */
10581 #define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_GET(value) (((value) & 0x00000200) >> 9)
10582 /* Produces a ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field value suitable for setting the register. */
10583 #define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_SET(value) (((value) << 9) & 0x00000200)
10584 
10585 /*
10586  * Field : optfeature
10587  *
10588  * Optional Features Removed (OptFeature)
10589  *
10590  * Indicates whether the User ID register, GPIO interface ports,
10591  *
10592  * and SOF toggle and counter ports were removed For gate count
10593  *
10594  * optimization by enabling Remove Optional Features.
10595  *
10596  * 1'b0: No
10597  *
10598  * 1'b1: Yes
10599  *
10600  * Field Enumeration Values:
10601  *
10602  * Enum | Value | Description
10603  * :---------------------------------------|:------|:---------------------
10604  * ALT_USB_GLOB_GHWCFG3_OPTFEATURE_E_DISD | 0x0 | No Optional features
10605  *
10606  * Field Access Macros:
10607  *
10608  */
10609 /*
10610  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_OPTFEATURE
10611  *
10612  * No Optional features
10613  */
10614 #define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_E_DISD 0x0
10615 
10616 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */
10617 #define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_LSB 10
10618 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */
10619 #define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_MSB 10
10620 /* The width in bits of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */
10621 #define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_WIDTH 1
10622 /* The mask used to set the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field value. */
10623 #define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_SET_MSK 0x00000400
10624 /* The mask used to clear the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field value. */
10625 #define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_CLR_MSK 0xfffffbff
10626 /* The reset value of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */
10627 #define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_RESET 0x0
10628 /* Extracts the ALT_USB_GLOB_GHWCFG3_OPTFEATURE field value from a register. */
10629 #define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_GET(value) (((value) & 0x00000400) >> 10)
10630 /* Produces a ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field value suitable for setting the register. */
10631 #define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_SET(value) (((value) << 10) & 0x00000400)
10632 
10633 /*
10634  * Field : rsttype
10635  *
10636  * Reset Style For Clocked always Blocks in RTL (RstType)
10637  *
10638  * 1'b0: Asynchronous reset is used in the core
10639  *
10640  * 1'b1: Synchronous reset is used in the core
10641  *
10642  * Field Enumeration Values:
10643  *
10644  * Enum | Value | Description
10645  * :-----------------------------------|:------|:---------------------------------------
10646  * ALT_USB_GLOB_GHWCFG3_RSTTYPE_E_END | 0x0 | Asynchronous reset is used in the core
10647  *
10648  * Field Access Macros:
10649  *
10650  */
10651 /*
10652  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_RSTTYPE
10653  *
10654  * Asynchronous reset is used in the core
10655  */
10656 #define ALT_USB_GLOB_GHWCFG3_RSTTYPE_E_END 0x0
10657 
10658 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */
10659 #define ALT_USB_GLOB_GHWCFG3_RSTTYPE_LSB 11
10660 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */
10661 #define ALT_USB_GLOB_GHWCFG3_RSTTYPE_MSB 11
10662 /* The width in bits of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */
10663 #define ALT_USB_GLOB_GHWCFG3_RSTTYPE_WIDTH 1
10664 /* The mask used to set the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field value. */
10665 #define ALT_USB_GLOB_GHWCFG3_RSTTYPE_SET_MSK 0x00000800
10666 /* The mask used to clear the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field value. */
10667 #define ALT_USB_GLOB_GHWCFG3_RSTTYPE_CLR_MSK 0xfffff7ff
10668 /* The reset value of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */
10669 #define ALT_USB_GLOB_GHWCFG3_RSTTYPE_RESET 0x0
10670 /* Extracts the ALT_USB_GLOB_GHWCFG3_RSTTYPE field value from a register. */
10671 #define ALT_USB_GLOB_GHWCFG3_RSTTYPE_GET(value) (((value) & 0x00000800) >> 11)
10672 /* Produces a ALT_USB_GLOB_GHWCFG3_RSTTYPE register field value suitable for setting the register. */
10673 #define ALT_USB_GLOB_GHWCFG3_RSTTYPE_SET(value) (((value) << 11) & 0x00000800)
10674 
10675 /*
10676  * Field : adpsupport
10677  *
10678  * This bit indicates whether ADP logic is present within or external to the HS OTG
10679  *
10680  * controller
10681  *
10682  * 0: No ADP logic present with HSOTG controller
10683  *
10684  * 1: ADP logic is present along with HSOTG controller.
10685  *
10686  * Field Enumeration Values:
10687  *
10688  * Enum | Value | Description
10689  * :--------------------------------------|:------|:-------------------------------------------------
10690  * ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_E_END | 0x1 | ADP logic is present along with HSOTG controller
10691  *
10692  * Field Access Macros:
10693  *
10694  */
10695 /*
10696  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_ADPSUPPORT
10697  *
10698  * ADP logic is present along with HSOTG controller
10699  */
10700 #define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_E_END 0x1
10701 
10702 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */
10703 #define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_LSB 12
10704 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */
10705 #define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_MSB 12
10706 /* The width in bits of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */
10707 #define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_WIDTH 1
10708 /* The mask used to set the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field value. */
10709 #define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_SET_MSK 0x00001000
10710 /* The mask used to clear the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field value. */
10711 #define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_CLR_MSK 0xffffefff
10712 /* The reset value of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */
10713 #define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_RESET 0x0
10714 /* Extracts the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT field value from a register. */
10715 #define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_GET(value) (((value) & 0x00001000) >> 12)
10716 /* Produces a ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field value suitable for setting the register. */
10717 #define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_SET(value) (((value) << 12) & 0x00001000)
10718 
10719 /*
10720  * Field : hsicmode
10721  *
10722  * HSIC mode specified for Mode of Operation
10723  *
10724  * Value Range: 0 - 1
10725  *
10726  * 1: HSIC-capable with shared UTMI PHY interface
10727  *
10728  * 0: Non-HSIC-capable
10729  *
10730  * Field Enumeration Values:
10731  *
10732  * Enum | Value | Description
10733  * :------------------------------------|:------|:-----------------
10734  * ALT_USB_GLOB_GHWCFG3_HSICMOD_E_DISD | 0x0 | Non-HSIC-capable
10735  *
10736  * Field Access Macros:
10737  *
10738  */
10739 /*
10740  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_HSICMOD
10741  *
10742  * Non-HSIC-capable
10743  */
10744 #define ALT_USB_GLOB_GHWCFG3_HSICMOD_E_DISD 0x0
10745 
10746 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */
10747 #define ALT_USB_GLOB_GHWCFG3_HSICMOD_LSB 13
10748 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */
10749 #define ALT_USB_GLOB_GHWCFG3_HSICMOD_MSB 13
10750 /* The width in bits of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */
10751 #define ALT_USB_GLOB_GHWCFG3_HSICMOD_WIDTH 1
10752 /* The mask used to set the ALT_USB_GLOB_GHWCFG3_HSICMOD register field value. */
10753 #define ALT_USB_GLOB_GHWCFG3_HSICMOD_SET_MSK 0x00002000
10754 /* The mask used to clear the ALT_USB_GLOB_GHWCFG3_HSICMOD register field value. */
10755 #define ALT_USB_GLOB_GHWCFG3_HSICMOD_CLR_MSK 0xffffdfff
10756 /* The reset value of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */
10757 #define ALT_USB_GLOB_GHWCFG3_HSICMOD_RESET 0x0
10758 /* Extracts the ALT_USB_GLOB_GHWCFG3_HSICMOD field value from a register. */
10759 #define ALT_USB_GLOB_GHWCFG3_HSICMOD_GET(value) (((value) & 0x00002000) >> 13)
10760 /* Produces a ALT_USB_GLOB_GHWCFG3_HSICMOD register field value suitable for setting the register. */
10761 #define ALT_USB_GLOB_GHWCFG3_HSICMOD_SET(value) (((value) << 13) & 0x00002000)
10762 
10763 /*
10764  * Field : bcsupport
10765  *
10766  * This bit indicates the HS OTG controller support for Battery Charger.
10767  *
10768  * 0 - No Battery Charger Support
10769  *
10770  * 1 - Battery Charger support present.
10771  *
10772  * Field Enumeration Values:
10773  *
10774  * Enum | Value | Description
10775  * :--------------------------------------|:------|:---------------------------
10776  * ALT_USB_GLOB_GHWCFG3_BCSUPPORT_E_DISD | 0x0 | No Battery Charger Support
10777  *
10778  * Field Access Macros:
10779  *
10780  */
10781 /*
10782  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_BCSUPPORT
10783  *
10784  * No Battery Charger Support
10785  */
10786 #define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_E_DISD 0x0
10787 
10788 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */
10789 #define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_LSB 14
10790 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */
10791 #define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_MSB 14
10792 /* The width in bits of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */
10793 #define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_WIDTH 1
10794 /* The mask used to set the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field value. */
10795 #define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_SET_MSK 0x00004000
10796 /* The mask used to clear the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field value. */
10797 #define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_CLR_MSK 0xffffbfff
10798 /* The reset value of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */
10799 #define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_RESET 0x0
10800 /* Extracts the ALT_USB_GLOB_GHWCFG3_BCSUPPORT field value from a register. */
10801 #define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_GET(value) (((value) & 0x00004000) >> 14)
10802 /* Produces a ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field value suitable for setting the register. */
10803 #define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_SET(value) (((value) << 14) & 0x00004000)
10804 
10805 /*
10806  * Field : lpmmode
10807  *
10808  * LPM mode specified for Mode of Operation.
10809  *
10810  * Field Enumeration Values:
10811  *
10812  * Enum | Value | Description
10813  * :-----------------------------------|:------|:-------------
10814  * ALT_USB_GLOB_GHWCFG3_LPMMOD_E_DISD | 0x0 | LPM disabled
10815  *
10816  * Field Access Macros:
10817  *
10818  */
10819 /*
10820  * Enumerated value for register field ALT_USB_GLOB_GHWCFG3_LPMMOD
10821  *
10822  * LPM disabled
10823  */
10824 #define ALT_USB_GLOB_GHWCFG3_LPMMOD_E_DISD 0x0
10825 
10826 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */
10827 #define ALT_USB_GLOB_GHWCFG3_LPMMOD_LSB 15
10828 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */
10829 #define ALT_USB_GLOB_GHWCFG3_LPMMOD_MSB 15
10830 /* The width in bits of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */
10831 #define ALT_USB_GLOB_GHWCFG3_LPMMOD_WIDTH 1
10832 /* The mask used to set the ALT_USB_GLOB_GHWCFG3_LPMMOD register field value. */
10833 #define ALT_USB_GLOB_GHWCFG3_LPMMOD_SET_MSK 0x00008000
10834 /* The mask used to clear the ALT_USB_GLOB_GHWCFG3_LPMMOD register field value. */
10835 #define ALT_USB_GLOB_GHWCFG3_LPMMOD_CLR_MSK 0xffff7fff
10836 /* The reset value of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */
10837 #define ALT_USB_GLOB_GHWCFG3_LPMMOD_RESET 0x0
10838 /* Extracts the ALT_USB_GLOB_GHWCFG3_LPMMOD field value from a register. */
10839 #define ALT_USB_GLOB_GHWCFG3_LPMMOD_GET(value) (((value) & 0x00008000) >> 15)
10840 /* Produces a ALT_USB_GLOB_GHWCFG3_LPMMOD register field value suitable for setting the register. */
10841 #define ALT_USB_GLOB_GHWCFG3_LPMMOD_SET(value) (((value) << 15) & 0x00008000)
10842 
10843 /*
10844  * Field : dfifodepth
10845  *
10846  * DFIFO Depth (DfifoDepth - EP_LOC_CNT)
10847  *
10848  * This value is in terms of 32-bit words.
10849  *
10850  * Minimum value is 32
10851  *
10852  * Maximum value is 32,768
10853  *
10854  * Field Access Macros:
10855  *
10856  */
10857 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */
10858 #define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_LSB 16
10859 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */
10860 #define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_MSB 31
10861 /* The width in bits of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */
10862 #define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_WIDTH 16
10863 /* The mask used to set the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field value. */
10864 #define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_SET_MSK 0xffff0000
10865 /* The mask used to clear the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field value. */
10866 #define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_CLR_MSK 0x0000ffff
10867 /* The reset value of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */
10868 #define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_RESET 0x1f80
10869 /* Extracts the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH field value from a register. */
10870 #define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_GET(value) (((value) & 0xffff0000) >> 16)
10871 /* Produces a ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field value suitable for setting the register. */
10872 #define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_SET(value) (((value) << 16) & 0xffff0000)
10873 
10874 #ifndef __ASSEMBLY__
10875 /*
10876  * WARNING: The C register and register group struct declarations are provided for
10877  * convenience and illustrative purposes. They should, however, be used with
10878  * caution as the C language standard provides no guarantees about the alignment or
10879  * atomicity of device memory accesses. The recommended practice for writing
10880  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10881  * alt_write_word() functions.
10882  *
10883  * The struct declaration for register ALT_USB_GLOB_GHWCFG3.
10884  */
10885 struct ALT_USB_GLOB_GHWCFG3_s
10886 {
10887  const uint32_t xfersizewidth : 4; /* ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH */
10888  const uint32_t pktsizewidth : 3; /* ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH */
10889  const uint32_t otgen : 1; /* ALT_USB_GLOB_GHWCFG3_OTGEN */
10890  const uint32_t i2cintsel : 1; /* ALT_USB_GLOB_GHWCFG3_I2CINTSEL */
10891  const uint32_t vndctlsupt : 1; /* ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT */
10892  const uint32_t optfeature : 1; /* ALT_USB_GLOB_GHWCFG3_OPTFEATURE */
10893  const uint32_t rsttype : 1; /* ALT_USB_GLOB_GHWCFG3_RSTTYPE */
10894  const uint32_t adpsupport : 1; /* ALT_USB_GLOB_GHWCFG3_ADPSUPPORT */
10895  const uint32_t hsicmode : 1; /* ALT_USB_GLOB_GHWCFG3_HSICMOD */
10896  const uint32_t bcsupport : 1; /* ALT_USB_GLOB_GHWCFG3_BCSUPPORT */
10897  const uint32_t lpmmode : 1; /* ALT_USB_GLOB_GHWCFG3_LPMMOD */
10898  const uint32_t dfifodepth : 16; /* ALT_USB_GLOB_GHWCFG3_DFIFODEPTH */
10899 };
10900 
10901 /* The typedef declaration for register ALT_USB_GLOB_GHWCFG3. */
10902 typedef volatile struct ALT_USB_GLOB_GHWCFG3_s ALT_USB_GLOB_GHWCFG3_t;
10903 #endif /* __ASSEMBLY__ */
10904 
10905 /* The reset value of the ALT_USB_GLOB_GHWCFG3 register. */
10906 #define ALT_USB_GLOB_GHWCFG3_RESET 0x1f8002e8
10907 /* The byte offset of the ALT_USB_GLOB_GHWCFG3 register from the beginning of the component. */
10908 #define ALT_USB_GLOB_GHWCFG3_OFST 0x4c
10909 /* The address of the ALT_USB_GLOB_GHWCFG3 register. */
10910 #define ALT_USB_GLOB_GHWCFG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG3_OFST))
10911 
10912 /*
10913  * Register : ghwcfg4
10914  *
10915  * User HW Config4 Register
10916  *
10917  * Register Layout
10918  *
10919  * Bits | Access | Reset | Description
10920  * :--------|:-------|:------|:-----------------------------------------
10921  * [3:0] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS
10922  * [4] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN
10923  * [5] | R | 0x1 | ALT_USB_GLOB_GHWCFG4_AHBFREQ
10924  * [6] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_HIBERNATION
10925  * [7] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION
10926  * [13:8] | ??? | 0x0 | *UNDEFINED*
10927  * [15:14] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH
10928  * [19:16] | R | 0xf | ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
10929  * [20] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_IDDGFLTR
10930  * [21] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR
10931  * [22] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_AVALIDFLTR
10932  * [23] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_BVALIDFLTR
10933  * [24] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_SESSENDFLTR
10934  * [25] | R | 0x1 | ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD
10935  * [29:26] | R | 0xf | ALT_USB_GLOB_GHWCFG4_INEPS
10936  * [30] | R | 0x1 | ALT_USB_GLOB_GHWCFG4_DMA_CFG
10937  * [31] | R | 0x1 | ALT_USB_GLOB_GHWCFG4_DMA
10938  *
10939  */
10940 /*
10941  * Field : numdevperioeps
10942  *
10943  * Number of Device Mode Periodic IN Endpoints
10944  *
10945  * (NumDevPerioEps)
10946  *
10947  * Range: 0-15
10948  *
10949  * Field Access Macros:
10950  *
10951  */
10952 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */
10953 #define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_LSB 0
10954 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */
10955 #define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_MSB 3
10956 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */
10957 #define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_WIDTH 4
10958 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field value. */
10959 #define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_SET_MSK 0x0000000f
10960 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field value. */
10961 #define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_CLR_MSK 0xfffffff0
10962 /* The reset value of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */
10963 #define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_RESET 0x0
10964 /* Extracts the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS field value from a register. */
10965 #define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_GET(value) (((value) & 0x0000000f) >> 0)
10966 /* Produces a ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field value suitable for setting the register. */
10967 #define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_SET(value) (((value) << 0) & 0x0000000f)
10968 
10969 /*
10970  * Field : partialpwrdn
10971  *
10972  * Enable Partial Power Down (PartialPwrDn)
10973  *
10974  * 1'b0: Partial Power Down Not Enabled
10975  *
10976  * 1'b1: Partial Power Down Enabled
10977  *
10978  * Field Enumeration Values:
10979  *
10980  * Enum | Value | Description
10981  * :-----------------------------------------|:------|:----------------------------
10982  * ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_E_DISD | 0x0 | Partial Power Down disabled
10983  *
10984  * Field Access Macros:
10985  *
10986  */
10987 /*
10988  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN
10989  *
10990  * Partial Power Down disabled
10991  */
10992 #define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_E_DISD 0x0
10993 
10994 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */
10995 #define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_LSB 4
10996 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */
10997 #define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_MSB 4
10998 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */
10999 #define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_WIDTH 1
11000 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field value. */
11001 #define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_SET_MSK 0x00000010
11002 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field value. */
11003 #define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_CLR_MSK 0xffffffef
11004 /* The reset value of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */
11005 #define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_RESET 0x0
11006 /* Extracts the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN field value from a register. */
11007 #define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_GET(value) (((value) & 0x00000010) >> 4)
11008 /* Produces a ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field value suitable for setting the register. */
11009 #define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_SET(value) (((value) << 4) & 0x00000010)
11010 
11011 /*
11012  * Field : ahbfreq
11013  *
11014  * Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
11015  *
11016  * 1'b0: No
11017  *
11018  * 1'b1: Yes
11019  *
11020  * Field Enumeration Values:
11021  *
11022  * Enum | Value | Description
11023  * :-----------------------------------|:------|:--------------------------------------
11024  * ALT_USB_GLOB_GHWCFG4_AHBFREQ_E_END | 0x1 | Minimum AHB Frequency Less Than 60 MH
11025  *
11026  * Field Access Macros:
11027  *
11028  */
11029 /*
11030  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_AHBFREQ
11031  *
11032  * Minimum AHB Frequency Less Than 60 MH
11033  */
11034 #define ALT_USB_GLOB_GHWCFG4_AHBFREQ_E_END 0x1
11035 
11036 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */
11037 #define ALT_USB_GLOB_GHWCFG4_AHBFREQ_LSB 5
11038 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */
11039 #define ALT_USB_GLOB_GHWCFG4_AHBFREQ_MSB 5
11040 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */
11041 #define ALT_USB_GLOB_GHWCFG4_AHBFREQ_WIDTH 1
11042 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field value. */
11043 #define ALT_USB_GLOB_GHWCFG4_AHBFREQ_SET_MSK 0x00000020
11044 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field value. */
11045 #define ALT_USB_GLOB_GHWCFG4_AHBFREQ_CLR_MSK 0xffffffdf
11046 /* The reset value of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */
11047 #define ALT_USB_GLOB_GHWCFG4_AHBFREQ_RESET 0x1
11048 /* Extracts the ALT_USB_GLOB_GHWCFG4_AHBFREQ field value from a register. */
11049 #define ALT_USB_GLOB_GHWCFG4_AHBFREQ_GET(value) (((value) & 0x00000020) >> 5)
11050 /* Produces a ALT_USB_GLOB_GHWCFG4_AHBFREQ register field value suitable for setting the register. */
11051 #define ALT_USB_GLOB_GHWCFG4_AHBFREQ_SET(value) (((value) << 5) & 0x00000020)
11052 
11053 /*
11054  * Field : hibernation
11055  *
11056  * Enable Hibernation (Hibernation)
11057  *
11058  * 1'b0: Hibernation feature not enabled
11059  *
11060  * 1'b1: Hibernation feature enabled
11061  *
11062  * Field Enumeration Values:
11063  *
11064  * Enum | Value | Description
11065  * :----------------------------------------|:------|:-----------------------------
11066  * ALT_USB_GLOB_GHWCFG4_HIBERNATION_E_DISD | 0x0 | Hibernation feature disabled
11067  *
11068  * Field Access Macros:
11069  *
11070  */
11071 /*
11072  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_HIBERNATION
11073  *
11074  * Hibernation feature disabled
11075  */
11076 #define ALT_USB_GLOB_GHWCFG4_HIBERNATION_E_DISD 0x0
11077 
11078 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */
11079 #define ALT_USB_GLOB_GHWCFG4_HIBERNATION_LSB 6
11080 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */
11081 #define ALT_USB_GLOB_GHWCFG4_HIBERNATION_MSB 6
11082 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */
11083 #define ALT_USB_GLOB_GHWCFG4_HIBERNATION_WIDTH 1
11084 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field value. */
11085 #define ALT_USB_GLOB_GHWCFG4_HIBERNATION_SET_MSK 0x00000040
11086 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field value. */
11087 #define ALT_USB_GLOB_GHWCFG4_HIBERNATION_CLR_MSK 0xffffffbf
11088 /* The reset value of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */
11089 #define ALT_USB_GLOB_GHWCFG4_HIBERNATION_RESET 0x0
11090 /* Extracts the ALT_USB_GLOB_GHWCFG4_HIBERNATION field value from a register. */
11091 #define ALT_USB_GLOB_GHWCFG4_HIBERNATION_GET(value) (((value) & 0x00000040) >> 6)
11092 /* Produces a ALT_USB_GLOB_GHWCFG4_HIBERNATION register field value suitable for setting the register. */
11093 #define ALT_USB_GLOB_GHWCFG4_HIBERNATION_SET(value) (((value) << 6) & 0x00000040)
11094 
11095 /*
11096  * Field : extendedhibernation
11097  *
11098  * Enable Hibernation
11099  *
11100  * 1'b0: Extended Hibernation feature not enabled
11101  *
11102  * 1'b1: Extended Hibernation feature enabled
11103  *
11104  * Field Access Macros:
11105  *
11106  */
11107 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field. */
11108 #define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_LSB 7
11109 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field. */
11110 #define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_MSB 7
11111 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field. */
11112 #define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_WIDTH 1
11113 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field value. */
11114 #define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_SET_MSK 0x00000080
11115 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field value. */
11116 #define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_CLR_MSK 0xffffff7f
11117 /* The reset value of the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field. */
11118 #define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_RESET 0x0
11119 /* Extracts the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION field value from a register. */
11120 #define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_GET(value) (((value) & 0x00000080) >> 7)
11121 /* Produces a ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field value suitable for setting the register. */
11122 #define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_SET(value) (((value) << 7) & 0x00000080)
11123 
11124 /*
11125  * Field : phydatawidth
11126  *
11127  * UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
11128  *
11129  * (PhyDataWidth)
11130  *
11131  * When a ULPI PHY is used, an internal wrapper converts ULPI to
11132  *
11133  * UTMI+ .
11134  *
11135  * 2'b00: 8 bits
11136  *
11137  * 2'b01: 16 bits
11138  *
11139  * 2'b10: 8/16 bits, software selectable
11140  *
11141  * Others: Reserved
11142  *
11143  * Field Access Macros:
11144  *
11145  */
11146 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */
11147 #define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_LSB 14
11148 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */
11149 #define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_MSB 15
11150 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */
11151 #define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_WIDTH 2
11152 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field value. */
11153 #define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_SET_MSK 0x0000c000
11154 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field value. */
11155 #define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_CLR_MSK 0xffff3fff
11156 /* The reset value of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */
11157 #define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_RESET 0x0
11158 /* Extracts the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH field value from a register. */
11159 #define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_GET(value) (((value) & 0x0000c000) >> 14)
11160 /* Produces a ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field value suitable for setting the register. */
11161 #define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_SET(value) (((value) << 14) & 0x0000c000)
11162 
11163 /*
11164  * Field : numctleps
11165  *
11166  * Number of Device Mode Control Endpoints in Addition to
11167  *
11168  * Endpoint 0 (NumCtlEps)
11169  *
11170  * Range: 0-15
11171  *
11172  * Field Enumeration Values:
11173  *
11174  * Enum | Value | Description
11175  * :-----------------------------------------|:------|:--------------
11176  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT0 | 0x0 | End point 0
11177  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT1 | 0x1 | End point 1
11178  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT2 | 0x2 | End point 2
11179  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT3 | 0x3 | End point 3
11180  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT4 | 0x4 | End point 4
11181  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT5 | 0x5 | End point 5
11182  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT6 | 0x6 | End point 6
11183  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT7 | 0x7 | End point 7
11184  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT8 | 0x8 | End point 8
11185  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT9 | 0x9 | End point 9
11186  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT10 | 0xa | End point 10
11187  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT11 | 0xb | End point 11
11188  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT12 | 0xc | End point 12
11189  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT13 | 0xd | End point 13
11190  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT14 | 0xe | End point 14
11191  * ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT15 | 0xf | End point 15
11192  *
11193  * Field Access Macros:
11194  *
11195  */
11196 /*
11197  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11198  *
11199  * End point 0
11200  */
11201 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT0 0x0
11202 /*
11203  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11204  *
11205  * End point 1
11206  */
11207 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT1 0x1
11208 /*
11209  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11210  *
11211  * End point 2
11212  */
11213 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT2 0x2
11214 /*
11215  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11216  *
11217  * End point 3
11218  */
11219 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT3 0x3
11220 /*
11221  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11222  *
11223  * End point 4
11224  */
11225 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT4 0x4
11226 /*
11227  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11228  *
11229  * End point 5
11230  */
11231 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT5 0x5
11232 /*
11233  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11234  *
11235  * End point 6
11236  */
11237 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT6 0x6
11238 /*
11239  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11240  *
11241  * End point 7
11242  */
11243 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT7 0x7
11244 /*
11245  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11246  *
11247  * End point 8
11248  */
11249 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT8 0x8
11250 /*
11251  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11252  *
11253  * End point 9
11254  */
11255 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT9 0x9
11256 /*
11257  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11258  *
11259  * End point 10
11260  */
11261 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT10 0xa
11262 /*
11263  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11264  *
11265  * End point 11
11266  */
11267 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT11 0xb
11268 /*
11269  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11270  *
11271  * End point 12
11272  */
11273 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT12 0xc
11274 /*
11275  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11276  *
11277  * End point 13
11278  */
11279 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT13 0xd
11280 /*
11281  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11282  *
11283  * End point 14
11284  */
11285 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT14 0xe
11286 /*
11287  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
11288  *
11289  * End point 15
11290  */
11291 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT15 0xf
11292 
11293 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */
11294 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_LSB 16
11295 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */
11296 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_MSB 19
11297 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */
11298 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_WIDTH 4
11299 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field value. */
11300 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_SET_MSK 0x000f0000
11301 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field value. */
11302 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_CLR_MSK 0xfff0ffff
11303 /* The reset value of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */
11304 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_RESET 0xf
11305 /* Extracts the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS field value from a register. */
11306 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_GET(value) (((value) & 0x000f0000) >> 16)
11307 /* Produces a ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field value suitable for setting the register. */
11308 #define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_SET(value) (((value) << 16) & 0x000f0000)
11309 
11310 /*
11311  * Field : iddgfltr
11312  *
11313  * IDDIG Filter Enable (IddgFltr)
11314  *
11315  * 1'b0: No filter
11316  *
11317  * 1'b1: Filter
11318  *
11319  * Field Enumeration Values:
11320  *
11321  * Enum | Value | Description
11322  * :-------------------------------------|:------|:----------------------
11323  * ALT_USB_GLOB_GHWCFG4_IDDGFLTR_E_DISD | 0x0 | Iddig Filter Disabled
11324  *
11325  * Field Access Macros:
11326  *
11327  */
11328 /*
11329  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_IDDGFLTR
11330  *
11331  * Iddig Filter Disabled
11332  */
11333 #define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_E_DISD 0x0
11334 
11335 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */
11336 #define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_LSB 20
11337 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */
11338 #define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_MSB 20
11339 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */
11340 #define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_WIDTH 1
11341 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field value. */
11342 #define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_SET_MSK 0x00100000
11343 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field value. */
11344 #define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_CLR_MSK 0xffefffff
11345 /* The reset value of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */
11346 #define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_RESET 0x0
11347 /* Extracts the ALT_USB_GLOB_GHWCFG4_IDDGFLTR field value from a register. */
11348 #define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_GET(value) (((value) & 0x00100000) >> 20)
11349 /* Produces a ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field value suitable for setting the register. */
11350 #define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_SET(value) (((value) << 20) & 0x00100000)
11351 
11352 /*
11353  * Field : vbusvalidfltr
11354  *
11355  * VBUS Valid Filter Enabled (VBusValidFltr)
11356  *
11357  * 1'b0: No filter
11358  *
11359  * 1'b1: Filter
11360  *
11361  * Field Enumeration Values:
11362  *
11363  * Enum | Value | Description
11364  * :------------------------------------------|:------|:---------------------------
11365  * ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_E_DISD | 0x0 | Vbus Valid Filter Disabled
11366  *
11367  * Field Access Macros:
11368  *
11369  */
11370 /*
11371  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR
11372  *
11373  * Vbus Valid Filter Disabled
11374  */
11375 #define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_E_DISD 0x0
11376 
11377 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */
11378 #define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_LSB 21
11379 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */
11380 #define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_MSB 21
11381 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */
11382 #define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_WIDTH 1
11383 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field value. */
11384 #define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_SET_MSK 0x00200000
11385 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field value. */
11386 #define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_CLR_MSK 0xffdfffff
11387 /* The reset value of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */
11388 #define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_RESET 0x0
11389 /* Extracts the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR field value from a register. */
11390 #define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_GET(value) (((value) & 0x00200000) >> 21)
11391 /* Produces a ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field value suitable for setting the register. */
11392 #define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_SET(value) (((value) << 21) & 0x00200000)
11393 
11394 /*
11395  * Field : avalidfltr
11396  *
11397  * a_valid Filter Enabled (AValidFltr)
11398  *
11399  * 1'b0: No filter
11400  *
11401  * 1'b1: Filter
11402  *
11403  * Field Enumeration Values:
11404  *
11405  * Enum | Value | Description
11406  * :---------------------------------------|:------|:------------
11407  * ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_E_DISD | 0x0 | No filter
11408  *
11409  * Field Access Macros:
11410  *
11411  */
11412 /*
11413  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_AVALIDFLTR
11414  *
11415  * No filter
11416  */
11417 #define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_E_DISD 0x0
11418 
11419 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */
11420 #define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_LSB 22
11421 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */
11422 #define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_MSB 22
11423 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */
11424 #define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_WIDTH 1
11425 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field value. */
11426 #define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_SET_MSK 0x00400000
11427 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field value. */
11428 #define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_CLR_MSK 0xffbfffff
11429 /* The reset value of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */
11430 #define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_RESET 0x0
11431 /* Extracts the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR field value from a register. */
11432 #define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_GET(value) (((value) & 0x00400000) >> 22)
11433 /* Produces a ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field value suitable for setting the register. */
11434 #define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_SET(value) (((value) << 22) & 0x00400000)
11435 
11436 /*
11437  * Field : bvalidfltr
11438  *
11439  * b_valid Filter Enabled (BValidFltr)
11440  *
11441  * 1'b0: No filter
11442  *
11443  * 1'b1: Filter
11444  *
11445  * Field Enumeration Values:
11446  *
11447  * Enum | Value | Description
11448  * :---------------------------------------|:------|:------------
11449  * ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_E_DISD | 0x0 | No Filter
11450  *
11451  * Field Access Macros:
11452  *
11453  */
11454 /*
11455  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_BVALIDFLTR
11456  *
11457  * No Filter
11458  */
11459 #define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_E_DISD 0x0
11460 
11461 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */
11462 #define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_LSB 23
11463 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */
11464 #define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_MSB 23
11465 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */
11466 #define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_WIDTH 1
11467 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field value. */
11468 #define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_SET_MSK 0x00800000
11469 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field value. */
11470 #define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_CLR_MSK 0xff7fffff
11471 /* The reset value of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */
11472 #define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_RESET 0x0
11473 /* Extracts the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR field value from a register. */
11474 #define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_GET(value) (((value) & 0x00800000) >> 23)
11475 /* Produces a ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field value suitable for setting the register. */
11476 #define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_SET(value) (((value) << 23) & 0x00800000)
11477 
11478 /*
11479  * Field : sessendfltr
11480  *
11481  * session_end Filter Enabled (SessEndFltr)
11482  *
11483  * 1'b0: No filter
11484  *
11485  * 1'b1: Filter
11486  *
11487  * Field Enumeration Values:
11488  *
11489  * Enum | Value | Description
11490  * :----------------------------------------|:------|:------------
11491  * ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_E_DISD | 0x0 | No filter
11492  *
11493  * Field Access Macros:
11494  *
11495  */
11496 /*
11497  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_SESSENDFLTR
11498  *
11499  * No filter
11500  */
11501 #define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_E_DISD 0x0
11502 
11503 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */
11504 #define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_LSB 24
11505 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */
11506 #define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_MSB 24
11507 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */
11508 #define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_WIDTH 1
11509 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field value. */
11510 #define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_SET_MSK 0x01000000
11511 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field value. */
11512 #define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_CLR_MSK 0xfeffffff
11513 /* The reset value of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */
11514 #define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_RESET 0x0
11515 /* Extracts the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR field value from a register. */
11516 #define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_GET(value) (((value) & 0x01000000) >> 24)
11517 /* Produces a ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field value suitable for setting the register. */
11518 #define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_SET(value) (((value) << 24) & 0x01000000)
11519 
11520 /*
11521  * Field : dedfifomode
11522  *
11523  * Enable Dedicated Transmit FIFO For device IN Endpoints
11524  *
11525  * (DedFifoMode)
11526  *
11527  * 1'b0 : Dedicated Transmit FIFO Operation not enabled.
11528  *
11529  * 1'b1 : Dedicated Transmit FIFO Operation enabled.
11530  *
11531  * Field Enumeration Values:
11532  *
11533  * Enum | Value | Description
11534  * :--------------------------------------|:------|:------------------------------------------
11535  * ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_E_END | 0x1 | Dedicated Transmit FIFO Operation enabled
11536  *
11537  * Field Access Macros:
11538  *
11539  */
11540 /*
11541  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD
11542  *
11543  * Dedicated Transmit FIFO Operation enabled
11544  */
11545 #define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_E_END 0x1
11546 
11547 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */
11548 #define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_LSB 25
11549 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */
11550 #define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_MSB 25
11551 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */
11552 #define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_WIDTH 1
11553 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field value. */
11554 #define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_SET_MSK 0x02000000
11555 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field value. */
11556 #define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_CLR_MSK 0xfdffffff
11557 /* The reset value of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */
11558 #define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_RESET 0x1
11559 /* Extracts the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD field value from a register. */
11560 #define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_GET(value) (((value) & 0x02000000) >> 25)
11561 /* Produces a ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field value suitable for setting the register. */
11562 #define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_SET(value) (((value) << 25) & 0x02000000)
11563 
11564 /*
11565  * Field : ineps
11566  *
11567  * Number of Device Mode IN Endpoints Including Control
11568  *
11569  * Endpoints (INEps)
11570  *
11571  * Range 0 -15
11572  *
11573  * 0 : 1 IN Endpoint
11574  *
11575  * 1 : 2 IN Endpoints
11576  *
11577  * ....
11578  *
11579  * 15 : 16 IN Endpoints
11580  *
11581  * Field Enumeration Values:
11582  *
11583  * Enum | Value | Description
11584  * :-------------------------------------|:------|:---------------
11585  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT1 | 0x0 | In Endpoint 1
11586  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT2 | 0x1 | In Endpoint 2
11587  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT3 | 0x2 | In Endpoint 3
11588  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT4 | 0x3 | In Endpoint 4
11589  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT5 | 0x4 | In Endpoint 5
11590  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT6 | 0x5 | In Endpoint 6
11591  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT7 | 0x6 | In Endpoint 7
11592  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT8 | 0x7 | In Endpoint 8
11593  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT9 | 0x8 | In Endpoint 9
11594  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT10 | 0x9 | In Endpoint 10
11595  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT11 | 0xa | In Endpoint 11
11596  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT12 | 0xb | In Endpoint 12
11597  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT13 | 0xc | In Endpoint 13
11598  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT14 | 0xd | In Endpoint 14
11599  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT15 | 0xe | In Endpoint 15
11600  * ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT16 | 0xf | In Endpoint 16
11601  *
11602  * Field Access Macros:
11603  *
11604  */
11605 /*
11606  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11607  *
11608  * In Endpoint 1
11609  */
11610 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT1 0x0
11611 /*
11612  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11613  *
11614  * In Endpoint 2
11615  */
11616 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT2 0x1
11617 /*
11618  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11619  *
11620  * In Endpoint 3
11621  */
11622 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT3 0x2
11623 /*
11624  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11625  *
11626  * In Endpoint 4
11627  */
11628 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT4 0x3
11629 /*
11630  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11631  *
11632  * In Endpoint 5
11633  */
11634 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT5 0x4
11635 /*
11636  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11637  *
11638  * In Endpoint 6
11639  */
11640 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT6 0x5
11641 /*
11642  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11643  *
11644  * In Endpoint 7
11645  */
11646 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT7 0x6
11647 /*
11648  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11649  *
11650  * In Endpoint 8
11651  */
11652 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT8 0x7
11653 /*
11654  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11655  *
11656  * In Endpoint 9
11657  */
11658 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT9 0x8
11659 /*
11660  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11661  *
11662  * In Endpoint 10
11663  */
11664 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT10 0x9
11665 /*
11666  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11667  *
11668  * In Endpoint 11
11669  */
11670 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT11 0xa
11671 /*
11672  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11673  *
11674  * In Endpoint 12
11675  */
11676 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT12 0xb
11677 /*
11678  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11679  *
11680  * In Endpoint 13
11681  */
11682 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT13 0xc
11683 /*
11684  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11685  *
11686  * In Endpoint 14
11687  */
11688 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT14 0xd
11689 /*
11690  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11691  *
11692  * In Endpoint 15
11693  */
11694 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT15 0xe
11695 /*
11696  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
11697  *
11698  * In Endpoint 16
11699  */
11700 #define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT16 0xf
11701 
11702 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */
11703 #define ALT_USB_GLOB_GHWCFG4_INEPS_LSB 26
11704 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */
11705 #define ALT_USB_GLOB_GHWCFG4_INEPS_MSB 29
11706 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */
11707 #define ALT_USB_GLOB_GHWCFG4_INEPS_WIDTH 4
11708 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_INEPS register field value. */
11709 #define ALT_USB_GLOB_GHWCFG4_INEPS_SET_MSK 0x3c000000
11710 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_INEPS register field value. */
11711 #define ALT_USB_GLOB_GHWCFG4_INEPS_CLR_MSK 0xc3ffffff
11712 /* The reset value of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */
11713 #define ALT_USB_GLOB_GHWCFG4_INEPS_RESET 0xf
11714 /* Extracts the ALT_USB_GLOB_GHWCFG4_INEPS field value from a register. */
11715 #define ALT_USB_GLOB_GHWCFG4_INEPS_GET(value) (((value) & 0x3c000000) >> 26)
11716 /* Produces a ALT_USB_GLOB_GHWCFG4_INEPS register field value suitable for setting the register. */
11717 #define ALT_USB_GLOB_GHWCFG4_INEPS_SET(value) (((value) << 26) & 0x3c000000)
11718 
11719 /*
11720  * Field : dma_configuration
11721  *
11722  * Scatter/Gather DMA configuration
11723  *
11724  * 1'b0: Non-Scatter/Gather DMA configuration
11725  *
11726  * 1'b1: Scatter/Gather DMA configuration
11727  *
11728  * Field Enumeration Values:
11729  *
11730  * Enum | Value | Description
11731  * :------------------------------------------|:------|:-------------------------------------
11732  * ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_NONSCATTER | 0x0 | Non-Scatter/Gather DMA configuration
11733  * ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_SCATTER | 0x1 | Scatter/Gather DMA configuration
11734  *
11735  * Field Access Macros:
11736  *
11737  */
11738 /*
11739  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DMA_CFG
11740  *
11741  * Non-Scatter/Gather DMA configuration
11742  */
11743 #define ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_NONSCATTER 0x0
11744 /*
11745  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DMA_CFG
11746  *
11747  * Scatter/Gather DMA configuration
11748  */
11749 #define ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_SCATTER 0x1
11750 
11751 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */
11752 #define ALT_USB_GLOB_GHWCFG4_DMA_CFG_LSB 30
11753 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */
11754 #define ALT_USB_GLOB_GHWCFG4_DMA_CFG_MSB 30
11755 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */
11756 #define ALT_USB_GLOB_GHWCFG4_DMA_CFG_WIDTH 1
11757 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field value. */
11758 #define ALT_USB_GLOB_GHWCFG4_DMA_CFG_SET_MSK 0x40000000
11759 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field value. */
11760 #define ALT_USB_GLOB_GHWCFG4_DMA_CFG_CLR_MSK 0xbfffffff
11761 /* The reset value of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */
11762 #define ALT_USB_GLOB_GHWCFG4_DMA_CFG_RESET 0x1
11763 /* Extracts the ALT_USB_GLOB_GHWCFG4_DMA_CFG field value from a register. */
11764 #define ALT_USB_GLOB_GHWCFG4_DMA_CFG_GET(value) (((value) & 0x40000000) >> 30)
11765 /* Produces a ALT_USB_GLOB_GHWCFG4_DMA_CFG register field value suitable for setting the register. */
11766 #define ALT_USB_GLOB_GHWCFG4_DMA_CFG_SET(value) (((value) << 30) & 0x40000000)
11767 
11768 /*
11769  * Field : dma
11770  *
11771  * Scatter/Gather DMA configuration
11772  *
11773  * 1'b0: Non Dynamic configuration
11774  *
11775  * 1'b1: Dynamic configuration
11776  *
11777  * Field Enumeration Values:
11778  *
11779  * Enum | Value | Description
11780  * :-------------------------------|:------|:----------------------
11781  * ALT_USB_GLOB_GHWCFG4_DMA_E_END | 0x1 | Dynamic configuration
11782  *
11783  * Field Access Macros:
11784  *
11785  */
11786 /*
11787  * Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DMA
11788  *
11789  * Dynamic configuration
11790  */
11791 #define ALT_USB_GLOB_GHWCFG4_DMA_E_END 0x1
11792 
11793 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_DMA register field. */
11794 #define ALT_USB_GLOB_GHWCFG4_DMA_LSB 31
11795 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_DMA register field. */
11796 #define ALT_USB_GLOB_GHWCFG4_DMA_MSB 31
11797 /* The width in bits of the ALT_USB_GLOB_GHWCFG4_DMA register field. */
11798 #define ALT_USB_GLOB_GHWCFG4_DMA_WIDTH 1
11799 /* The mask used to set the ALT_USB_GLOB_GHWCFG4_DMA register field value. */
11800 #define ALT_USB_GLOB_GHWCFG4_DMA_SET_MSK 0x80000000
11801 /* The mask used to clear the ALT_USB_GLOB_GHWCFG4_DMA register field value. */
11802 #define ALT_USB_GLOB_GHWCFG4_DMA_CLR_MSK 0x7fffffff
11803 /* The reset value of the ALT_USB_GLOB_GHWCFG4_DMA register field. */
11804 #define ALT_USB_GLOB_GHWCFG4_DMA_RESET 0x1
11805 /* Extracts the ALT_USB_GLOB_GHWCFG4_DMA field value from a register. */
11806 #define ALT_USB_GLOB_GHWCFG4_DMA_GET(value) (((value) & 0x80000000) >> 31)
11807 /* Produces a ALT_USB_GLOB_GHWCFG4_DMA register field value suitable for setting the register. */
11808 #define ALT_USB_GLOB_GHWCFG4_DMA_SET(value) (((value) << 31) & 0x80000000)
11809 
11810 #ifndef __ASSEMBLY__
11811 /*
11812  * WARNING: The C register and register group struct declarations are provided for
11813  * convenience and illustrative purposes. They should, however, be used with
11814  * caution as the C language standard provides no guarantees about the alignment or
11815  * atomicity of device memory accesses. The recommended practice for writing
11816  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11817  * alt_write_word() functions.
11818  *
11819  * The struct declaration for register ALT_USB_GLOB_GHWCFG4.
11820  */
11821 struct ALT_USB_GLOB_GHWCFG4_s
11822 {
11823  const uint32_t numdevperioeps : 4; /* ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS */
11824  const uint32_t partialpwrdn : 1; /* ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN */
11825  const uint32_t ahbfreq : 1; /* ALT_USB_GLOB_GHWCFG4_AHBFREQ */
11826  const uint32_t hibernation : 1; /* ALT_USB_GLOB_GHWCFG4_HIBERNATION */
11827  const uint32_t extendedhibernation : 1; /* ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION */
11828  uint32_t : 6; /* *UNDEFINED* */
11829  const uint32_t phydatawidth : 2; /* ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH */
11830  const uint32_t numctleps : 4; /* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS */
11831  const uint32_t iddgfltr : 1; /* ALT_USB_GLOB_GHWCFG4_IDDGFLTR */
11832  const uint32_t vbusvalidfltr : 1; /* ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR */
11833  const uint32_t avalidfltr : 1; /* ALT_USB_GLOB_GHWCFG4_AVALIDFLTR */
11834  const uint32_t bvalidfltr : 1; /* ALT_USB_GLOB_GHWCFG4_BVALIDFLTR */
11835  const uint32_t sessendfltr : 1; /* ALT_USB_GLOB_GHWCFG4_SESSENDFLTR */
11836  const uint32_t dedfifomode : 1; /* ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD */
11837  const uint32_t ineps : 4; /* ALT_USB_GLOB_GHWCFG4_INEPS */
11838  const uint32_t dma_configuration : 1; /* ALT_USB_GLOB_GHWCFG4_DMA_CFG */
11839  const uint32_t dma : 1; /* ALT_USB_GLOB_GHWCFG4_DMA */
11840 };
11841 
11842 /* The typedef declaration for register ALT_USB_GLOB_GHWCFG4. */
11843 typedef volatile struct ALT_USB_GLOB_GHWCFG4_s ALT_USB_GLOB_GHWCFG4_t;
11844 #endif /* __ASSEMBLY__ */
11845 
11846 /* The reset value of the ALT_USB_GLOB_GHWCFG4 register. */
11847 #define ALT_USB_GLOB_GHWCFG4_RESET 0xfe0f0020
11848 /* The byte offset of the ALT_USB_GLOB_GHWCFG4 register from the beginning of the component. */
11849 #define ALT_USB_GLOB_GHWCFG4_OFST 0x50
11850 /* The address of the ALT_USB_GLOB_GHWCFG4 register. */
11851 #define ALT_USB_GLOB_GHWCFG4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG4_OFST))
11852 
11853 /*
11854  * Register : gdfifocfg
11855  *
11856  * Global DFIFO Configuration Register
11857  *
11858  * Register Layout
11859  *
11860  * Bits | Access | Reset | Description
11861  * :--------|:-------|:-------|:--------------------------------------
11862  * [15:0] | RW | 0x2000 | ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG
11863  * [31:16] | RW | 0x1f80 | ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR
11864  *
11865  */
11866 /*
11867  * Field : gdfifocfg
11868  *
11869  * GDFIFOCfg
11870  *
11871  * This field is for dynamic programming of the DFIFO Size. This value takes effect
11872  *
11873  * only when the application programs a non zero value to this register. The
11874  *
11875  * value programmed must conform to the guidelines described in 'FIFO RAM
11876  *
11877  * Allocation'. The DWC_otg core does not have any corrective logic
11878  *
11879  * if the FIFO sizes are programmed incorrectly.
11880  *
11881  * Field Access Macros:
11882  *
11883  */
11884 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */
11885 #define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_LSB 0
11886 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */
11887 #define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_MSB 15
11888 /* The width in bits of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */
11889 #define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_WIDTH 16
11890 /* The mask used to set the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field value. */
11891 #define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_SET_MSK 0x0000ffff
11892 /* The mask used to clear the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field value. */
11893 #define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_CLR_MSK 0xffff0000
11894 /* The reset value of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */
11895 #define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_RESET 0x2000
11896 /* Extracts the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG field value from a register. */
11897 #define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_GET(value) (((value) & 0x0000ffff) >> 0)
11898 /* Produces a ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field value suitable for setting the register. */
11899 #define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_SET(value) (((value) << 0) & 0x0000ffff)
11900 
11901 /*
11902  * Field : epinfobaseaddr
11903  *
11904  * EPInfoBaseAddr
11905  *
11906  * This field provides the start address of the EP info controller.
11907  *
11908  * Field Access Macros:
11909  *
11910  */
11911 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */
11912 #define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_LSB 16
11913 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */
11914 #define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_MSB 31
11915 /* The width in bits of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */
11916 #define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_WIDTH 16
11917 /* The mask used to set the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field value. */
11918 #define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_SET_MSK 0xffff0000
11919 /* The mask used to clear the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field value. */
11920 #define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_CLR_MSK 0x0000ffff
11921 /* The reset value of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */
11922 #define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_RESET 0x1f80
11923 /* Extracts the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR field value from a register. */
11924 #define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_GET(value) (((value) & 0xffff0000) >> 16)
11925 /* Produces a ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field value suitable for setting the register. */
11926 #define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_SET(value) (((value) << 16) & 0xffff0000)
11927 
11928 #ifndef __ASSEMBLY__
11929 /*
11930  * WARNING: The C register and register group struct declarations are provided for
11931  * convenience and illustrative purposes. They should, however, be used with
11932  * caution as the C language standard provides no guarantees about the alignment or
11933  * atomicity of device memory accesses. The recommended practice for writing
11934  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11935  * alt_write_word() functions.
11936  *
11937  * The struct declaration for register ALT_USB_GLOB_GDFIFOCFG.
11938  */
11939 struct ALT_USB_GLOB_GDFIFOCFG_s
11940 {
11941  uint32_t gdfifocfg : 16; /* ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG */
11942  uint32_t epinfobaseaddr : 16; /* ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR */
11943 };
11944 
11945 /* The typedef declaration for register ALT_USB_GLOB_GDFIFOCFG. */
11946 typedef volatile struct ALT_USB_GLOB_GDFIFOCFG_s ALT_USB_GLOB_GDFIFOCFG_t;
11947 #endif /* __ASSEMBLY__ */
11948 
11949 /* The reset value of the ALT_USB_GLOB_GDFIFOCFG register. */
11950 #define ALT_USB_GLOB_GDFIFOCFG_RESET 0x1f802000
11951 /* The byte offset of the ALT_USB_GLOB_GDFIFOCFG register from the beginning of the component. */
11952 #define ALT_USB_GLOB_GDFIFOCFG_OFST 0x5c
11953 /* The address of the ALT_USB_GLOB_GDFIFOCFG register. */
11954 #define ALT_USB_GLOB_GDFIFOCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GDFIFOCFG_OFST))
11955 
11956 /*
11957  * Register : hptxfsiz
11958  *
11959  * Host Periodic Transmit FIFO Size Register
11960  *
11961  * Register Layout
11962  *
11963  * Bits | Access | Reset | Description
11964  * :--------|:-------|:-------|:---------------------------------
11965  * [14:0] | RW | 0x4000 | ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR
11966  * [15] | ??? | 0x0 | *UNDEFINED*
11967  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE
11968  * [31:30] | ??? | 0x0 | *UNDEFINED*
11969  *
11970  */
11971 /*
11972  * Field : ptxfstaddr
11973  *
11974  * Host Periodic TxFIFO Start Address (PTxFStAddr)
11975  *
11976  * The power-on reset value of this register is the sum of the Largest Rx Data
11977  *
11978  * FIFO Depth and Largest Non-periodic Tx Data FIFO Depth
11979  *
11980  * Programmed values must not exceed the power-on value
11981  *
11982  * Field Access Macros:
11983  *
11984  */
11985 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */
11986 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_LSB 0
11987 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */
11988 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_MSB 14
11989 /* The width in bits of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */
11990 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_WIDTH 15
11991 /* The mask used to set the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field value. */
11992 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_SET_MSK 0x00007fff
11993 /* The mask used to clear the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field value. */
11994 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_CLR_MSK 0xffff8000
11995 /* The reset value of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */
11996 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_RESET 0x4000
11997 /* Extracts the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR field value from a register. */
11998 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_GET(value) (((value) & 0x00007fff) >> 0)
11999 /* Produces a ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field value suitable for setting the register. */
12000 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_SET(value) (((value) << 0) & 0x00007fff)
12001 
12002 /*
12003  * Field : ptxfsize
12004  *
12005  * Host Periodic TxFIFO Depth (PTxFSize)
12006  *
12007  * This value is in terms of 32-bit words.
12008  *
12009  * Minimum value is 16
12010  *
12011  * Maximum value is 32,768
12012  *
12013  * The power-on reset value of this register is specified as the Largest Host
12014  *
12015  * Mode Periodic Tx Data FIFO Depth.
12016  *
12017  * Programmed values must not exceed the power-on value.
12018  *
12019  * Field Access Macros:
12020  *
12021  */
12022 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */
12023 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_LSB 16
12024 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */
12025 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_MSB 29
12026 /* The width in bits of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */
12027 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_WIDTH 14
12028 /* The mask used to set the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field value. */
12029 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_SET_MSK 0x3fff0000
12030 /* The mask used to clear the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field value. */
12031 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_CLR_MSK 0xc000ffff
12032 /* The reset value of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */
12033 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_RESET 0x2000
12034 /* Extracts the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE field value from a register. */
12035 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_GET(value) (((value) & 0x3fff0000) >> 16)
12036 /* Produces a ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field value suitable for setting the register. */
12037 #define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_SET(value) (((value) << 16) & 0x3fff0000)
12038 
12039 #ifndef __ASSEMBLY__
12040 /*
12041  * WARNING: The C register and register group struct declarations are provided for
12042  * convenience and illustrative purposes. They should, however, be used with
12043  * caution as the C language standard provides no guarantees about the alignment or
12044  * atomicity of device memory accesses. The recommended practice for writing
12045  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12046  * alt_write_word() functions.
12047  *
12048  * The struct declaration for register ALT_USB_GLOB_HPTXFSIZ.
12049  */
12050 struct ALT_USB_GLOB_HPTXFSIZ_s
12051 {
12052  uint32_t ptxfstaddr : 15; /* ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR */
12053  uint32_t : 1; /* *UNDEFINED* */
12054  uint32_t ptxfsize : 14; /* ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE */
12055  uint32_t : 2; /* *UNDEFINED* */
12056 };
12057 
12058 /* The typedef declaration for register ALT_USB_GLOB_HPTXFSIZ. */
12059 typedef volatile struct ALT_USB_GLOB_HPTXFSIZ_s ALT_USB_GLOB_HPTXFSIZ_t;
12060 #endif /* __ASSEMBLY__ */
12061 
12062 /* The reset value of the ALT_USB_GLOB_HPTXFSIZ register. */
12063 #define ALT_USB_GLOB_HPTXFSIZ_RESET 0x20004000
12064 /* The byte offset of the ALT_USB_GLOB_HPTXFSIZ register from the beginning of the component. */
12065 #define ALT_USB_GLOB_HPTXFSIZ_OFST 0x100
12066 /* The address of the ALT_USB_GLOB_HPTXFSIZ register. */
12067 #define ALT_USB_GLOB_HPTXFSIZ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_HPTXFSIZ_OFST))
12068 
12069 /*
12070  * Register : dieptxf1
12071  *
12072  * Device IN Endpoint Transmit FIFO Size Register 1
12073  *
12074  * Register Layout
12075  *
12076  * Bits | Access | Reset | Description
12077  * :--------|:-------|:-------|:-------------------------------------
12078  * [14:0] | RW | 0x4000 | ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR
12079  * [15] | ??? | 0x0 | *UNDEFINED*
12080  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP
12081  * [31:30] | ??? | 0x0 | *UNDEFINED*
12082  *
12083  */
12084 /*
12085  * Field : inepntxfstaddr
12086  *
12087  * IN Endpoint FIFOn Transmit RAM Start Address
12088  *
12089  * (INEPnTxFStAddr)
12090  *
12091  * This field contains the memory start address For IN endpoint
12092  *
12093  * Transmit FIFOn (0<n< = 15).
12094  *
12095  * The power-on reset value of this register is specified as the
12096  *
12097  * Largest Rx Data FIFO Depth
12098  *
12099  * Programmed values must not exceed the power-on value.
12100  *
12101  * Field Access Macros:
12102  *
12103  */
12104 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */
12105 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_LSB 0
12106 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */
12107 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_MSB 14
12108 /* The width in bits of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */
12109 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_WIDTH 15
12110 /* The mask used to set the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field value. */
12111 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_SET_MSK 0x00007fff
12112 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field value. */
12113 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_CLR_MSK 0xffff8000
12114 /* The reset value of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */
12115 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_RESET 0x4000
12116 /* Extracts the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR field value from a register. */
12117 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_GET(value) (((value) & 0x00007fff) >> 0)
12118 /* Produces a ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field value suitable for setting the register. */
12119 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x00007fff)
12120 
12121 /*
12122  * Field : inepntxfdep
12123  *
12124  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
12125  *
12126  * This value is in terms of 32-bit words.
12127  *
12128  * Minimum value is 16
12129  *
12130  * Maximum value is 32,768
12131  *
12132  * The power-on reset value of this register is specified as the
12133  *
12134  * Largest IN Endpoint FIFO number Depth
12135  *
12136  * Programmed values must not exceed the power-on value
12137  *
12138  * Field Access Macros:
12139  *
12140  */
12141 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */
12142 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_LSB 16
12143 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */
12144 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_MSB 29
12145 /* The width in bits of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */
12146 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_WIDTH 14
12147 /* The mask used to set the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field value. */
12148 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_SET_MSK 0x3fff0000
12149 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field value. */
12150 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_CLR_MSK 0xc000ffff
12151 /* The reset value of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */
12152 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_RESET 0x2000
12153 /* Extracts the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP field value from a register. */
12154 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
12155 /* Produces a ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field value suitable for setting the register. */
12156 #define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
12157 
12158 #ifndef __ASSEMBLY__
12159 /*
12160  * WARNING: The C register and register group struct declarations are provided for
12161  * convenience and illustrative purposes. They should, however, be used with
12162  * caution as the C language standard provides no guarantees about the alignment or
12163  * atomicity of device memory accesses. The recommended practice for writing
12164  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12165  * alt_write_word() functions.
12166  *
12167  * The struct declaration for register ALT_USB_GLOB_DIEPTXF1.
12168  */
12169 struct ALT_USB_GLOB_DIEPTXF1_s
12170 {
12171  uint32_t inepntxfstaddr : 15; /* ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR */
12172  uint32_t : 1; /* *UNDEFINED* */
12173  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP */
12174  uint32_t : 2; /* *UNDEFINED* */
12175 };
12176 
12177 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF1. */
12178 typedef volatile struct ALT_USB_GLOB_DIEPTXF1_s ALT_USB_GLOB_DIEPTXF1_t;
12179 #endif /* __ASSEMBLY__ */
12180 
12181 /* The reset value of the ALT_USB_GLOB_DIEPTXF1 register. */
12182 #define ALT_USB_GLOB_DIEPTXF1_RESET 0x20004000
12183 /* The byte offset of the ALT_USB_GLOB_DIEPTXF1 register from the beginning of the component. */
12184 #define ALT_USB_GLOB_DIEPTXF1_OFST 0x104
12185 /* The address of the ALT_USB_GLOB_DIEPTXF1 register. */
12186 #define ALT_USB_GLOB_DIEPTXF1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF1_OFST))
12187 
12188 /*
12189  * Register : dieptxf2
12190  *
12191  * Device IN Endpoint Transmit FIFO Size Register 2
12192  *
12193  * Register Layout
12194  *
12195  * Bits | Access | Reset | Description
12196  * :--------|:-------|:-------|:-------------------------------------
12197  * [14:0] | RW | 0x6000 | ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR
12198  * [15] | ??? | 0x0 | *UNDEFINED*
12199  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP
12200  * [31:30] | ??? | 0x0 | *UNDEFINED*
12201  *
12202  */
12203 /*
12204  * Field : inepntxfstaddr
12205  *
12206  * IN Endpoint FIFOn Transmit RAM Start Address
12207  *
12208  * (INEPnTxFStAddr)
12209  *
12210  * This field contains the memory start address For IN endpoint
12211  *
12212  * Transmit FIFOn (0<n< = 15).
12213  *
12214  * The power-on reset value of this register is specified as the
12215  *
12216  * Largest Rx Data FIFO Depth
12217  *
12218  * Programmed values must not exceed the power-on value.
12219  *
12220  * Field Access Macros:
12221  *
12222  */
12223 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */
12224 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_LSB 0
12225 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */
12226 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_MSB 14
12227 /* The width in bits of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */
12228 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_WIDTH 15
12229 /* The mask used to set the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field value. */
12230 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_SET_MSK 0x00007fff
12231 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field value. */
12232 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_CLR_MSK 0xffff8000
12233 /* The reset value of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */
12234 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_RESET 0x6000
12235 /* Extracts the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR field value from a register. */
12236 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_GET(value) (((value) & 0x00007fff) >> 0)
12237 /* Produces a ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field value suitable for setting the register. */
12238 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x00007fff)
12239 
12240 /*
12241  * Field : inepntxfdep
12242  *
12243  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
12244  *
12245  * This value is in terms of 32-bit words.
12246  *
12247  * Minimum value is 16
12248  *
12249  * Maximum value is 32,768
12250  *
12251  * The power-on reset value of this register is specified as the
12252  *
12253  * Largest IN Endpoint FIFO number Depth
12254  *
12255  * Programmed values must not exceed the power-on value
12256  *
12257  * Field Access Macros:
12258  *
12259  */
12260 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */
12261 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_LSB 16
12262 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */
12263 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_MSB 29
12264 /* The width in bits of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */
12265 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_WIDTH 14
12266 /* The mask used to set the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field value. */
12267 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_SET_MSK 0x3fff0000
12268 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field value. */
12269 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_CLR_MSK 0xc000ffff
12270 /* The reset value of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */
12271 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_RESET 0x2000
12272 /* Extracts the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP field value from a register. */
12273 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
12274 /* Produces a ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field value suitable for setting the register. */
12275 #define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
12276 
12277 #ifndef __ASSEMBLY__
12278 /*
12279  * WARNING: The C register and register group struct declarations are provided for
12280  * convenience and illustrative purposes. They should, however, be used with
12281  * caution as the C language standard provides no guarantees about the alignment or
12282  * atomicity of device memory accesses. The recommended practice for writing
12283  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12284  * alt_write_word() functions.
12285  *
12286  * The struct declaration for register ALT_USB_GLOB_DIEPTXF2.
12287  */
12288 struct ALT_USB_GLOB_DIEPTXF2_s
12289 {
12290  uint32_t inepntxfstaddr : 15; /* ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR */
12291  uint32_t : 1; /* *UNDEFINED* */
12292  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP */
12293  uint32_t : 2; /* *UNDEFINED* */
12294 };
12295 
12296 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF2. */
12297 typedef volatile struct ALT_USB_GLOB_DIEPTXF2_s ALT_USB_GLOB_DIEPTXF2_t;
12298 #endif /* __ASSEMBLY__ */
12299 
12300 /* The reset value of the ALT_USB_GLOB_DIEPTXF2 register. */
12301 #define ALT_USB_GLOB_DIEPTXF2_RESET 0x20006000
12302 /* The byte offset of the ALT_USB_GLOB_DIEPTXF2 register from the beginning of the component. */
12303 #define ALT_USB_GLOB_DIEPTXF2_OFST 0x108
12304 /* The address of the ALT_USB_GLOB_DIEPTXF2 register. */
12305 #define ALT_USB_GLOB_DIEPTXF2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF2_OFST))
12306 
12307 /*
12308  * Register : dieptxf3
12309  *
12310  * Device IN Endpoint Transmit FIFO Size Register 3
12311  *
12312  * Register Layout
12313  *
12314  * Bits | Access | Reset | Description
12315  * :--------|:-------|:-------|:-------------------------------------
12316  * [15:0] | RW | 0x8000 | ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR
12317  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP
12318  * [31:30] | ??? | 0x0 | *UNDEFINED*
12319  *
12320  */
12321 /*
12322  * Field : inepntxfstaddr
12323  *
12324  * IN Endpoint FIFOn Transmit RAM Start Address
12325  *
12326  * (INEPnTxFStAddr)
12327  *
12328  * This field contains the memory start address For IN endpoint
12329  *
12330  * Transmit FIFOn (0<n< = 15).
12331  *
12332  * The power-on reset value of this register is specified as the
12333  *
12334  * Largest Rx Data FIFO Depth
12335  *
12336  * Programmed values must not exceed the power-on value.
12337  *
12338  * Field Access Macros:
12339  *
12340  */
12341 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */
12342 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_LSB 0
12343 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */
12344 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_MSB 15
12345 /* The width in bits of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */
12346 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_WIDTH 16
12347 /* The mask used to set the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field value. */
12348 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_SET_MSK 0x0000ffff
12349 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field value. */
12350 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_CLR_MSK 0xffff0000
12351 /* The reset value of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */
12352 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_RESET 0x8000
12353 /* Extracts the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR field value from a register. */
12354 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
12355 /* Produces a ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field value suitable for setting the register. */
12356 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
12357 
12358 /*
12359  * Field : inepntxfdep
12360  *
12361  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
12362  *
12363  * This value is in terms of 32-bit words.
12364  *
12365  * Minimum value is 16
12366  *
12367  * Maximum value is 32,768
12368  *
12369  * The power-on reset value of this register is specified as the
12370  *
12371  * Largest IN Endpoint FIFO number Depth
12372  *
12373  * Programmed values must not exceed the power-on value
12374  *
12375  * Field Access Macros:
12376  *
12377  */
12378 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */
12379 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_LSB 16
12380 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */
12381 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_MSB 29
12382 /* The width in bits of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */
12383 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_WIDTH 14
12384 /* The mask used to set the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field value. */
12385 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_SET_MSK 0x3fff0000
12386 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field value. */
12387 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_CLR_MSK 0xc000ffff
12388 /* The reset value of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */
12389 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_RESET 0x2000
12390 /* Extracts the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP field value from a register. */
12391 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
12392 /* Produces a ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field value suitable for setting the register. */
12393 #define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
12394 
12395 #ifndef __ASSEMBLY__
12396 /*
12397  * WARNING: The C register and register group struct declarations are provided for
12398  * convenience and illustrative purposes. They should, however, be used with
12399  * caution as the C language standard provides no guarantees about the alignment or
12400  * atomicity of device memory accesses. The recommended practice for writing
12401  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12402  * alt_write_word() functions.
12403  *
12404  * The struct declaration for register ALT_USB_GLOB_DIEPTXF3.
12405  */
12406 struct ALT_USB_GLOB_DIEPTXF3_s
12407 {
12408  uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR */
12409  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP */
12410  uint32_t : 2; /* *UNDEFINED* */
12411 };
12412 
12413 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF3. */
12414 typedef volatile struct ALT_USB_GLOB_DIEPTXF3_s ALT_USB_GLOB_DIEPTXF3_t;
12415 #endif /* __ASSEMBLY__ */
12416 
12417 /* The reset value of the ALT_USB_GLOB_DIEPTXF3 register. */
12418 #define ALT_USB_GLOB_DIEPTXF3_RESET 0x20008000
12419 /* The byte offset of the ALT_USB_GLOB_DIEPTXF3 register from the beginning of the component. */
12420 #define ALT_USB_GLOB_DIEPTXF3_OFST 0x10c
12421 /* The address of the ALT_USB_GLOB_DIEPTXF3 register. */
12422 #define ALT_USB_GLOB_DIEPTXF3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF3_OFST))
12423 
12424 /*
12425  * Register : dieptxf4
12426  *
12427  * Device IN Endpoint Transmit FIFO Size Register 4
12428  *
12429  * Register Layout
12430  *
12431  * Bits | Access | Reset | Description
12432  * :--------|:-------|:-------|:-------------------------------------
12433  * [15:0] | RW | 0xa000 | ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR
12434  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP
12435  * [31:30] | ??? | 0x0 | *UNDEFINED*
12436  *
12437  */
12438 /*
12439  * Field : inepntxfstaddr
12440  *
12441  * IN Endpoint FIFOn Transmit RAM Start Address
12442  *
12443  * (INEPnTxFStAddr)
12444  *
12445  * This field contains the memory start address For IN endpoint
12446  *
12447  * Transmit FIFOn (0<n< = 15).
12448  *
12449  * The power-on reset value of this register is specified as the
12450  *
12451  * Largest Rx Data FIFO Depth
12452  *
12453  * Programmed values must not exceed the power-on value.
12454  *
12455  * Field Access Macros:
12456  *
12457  */
12458 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */
12459 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_LSB 0
12460 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */
12461 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_MSB 15
12462 /* The width in bits of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */
12463 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_WIDTH 16
12464 /* The mask used to set the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field value. */
12465 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_SET_MSK 0x0000ffff
12466 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field value. */
12467 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_CLR_MSK 0xffff0000
12468 /* The reset value of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */
12469 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_RESET 0xa000
12470 /* Extracts the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR field value from a register. */
12471 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
12472 /* Produces a ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field value suitable for setting the register. */
12473 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
12474 
12475 /*
12476  * Field : inepntxfdep
12477  *
12478  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
12479  *
12480  * This value is in terms of 32-bit words.
12481  *
12482  * Minimum value is 16
12483  *
12484  * Maximum value is 32,768
12485  *
12486  * The power-on reset value of this register is specified as the
12487  *
12488  * Largest IN Endpoint FIFO number Depth
12489  *
12490  * Programmed values must not exceed the power-on value
12491  *
12492  * Field Access Macros:
12493  *
12494  */
12495 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */
12496 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_LSB 16
12497 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */
12498 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_MSB 29
12499 /* The width in bits of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */
12500 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_WIDTH 14
12501 /* The mask used to set the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field value. */
12502 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_SET_MSK 0x3fff0000
12503 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field value. */
12504 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_CLR_MSK 0xc000ffff
12505 /* The reset value of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */
12506 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_RESET 0x2000
12507 /* Extracts the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP field value from a register. */
12508 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
12509 /* Produces a ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field value suitable for setting the register. */
12510 #define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
12511 
12512 #ifndef __ASSEMBLY__
12513 /*
12514  * WARNING: The C register and register group struct declarations are provided for
12515  * convenience and illustrative purposes. They should, however, be used with
12516  * caution as the C language standard provides no guarantees about the alignment or
12517  * atomicity of device memory accesses. The recommended practice for writing
12518  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12519  * alt_write_word() functions.
12520  *
12521  * The struct declaration for register ALT_USB_GLOB_DIEPTXF4.
12522  */
12523 struct ALT_USB_GLOB_DIEPTXF4_s
12524 {
12525  uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR */
12526  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP */
12527  uint32_t : 2; /* *UNDEFINED* */
12528 };
12529 
12530 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF4. */
12531 typedef volatile struct ALT_USB_GLOB_DIEPTXF4_s ALT_USB_GLOB_DIEPTXF4_t;
12532 #endif /* __ASSEMBLY__ */
12533 
12534 /* The reset value of the ALT_USB_GLOB_DIEPTXF4 register. */
12535 #define ALT_USB_GLOB_DIEPTXF4_RESET 0x2000a000
12536 /* The byte offset of the ALT_USB_GLOB_DIEPTXF4 register from the beginning of the component. */
12537 #define ALT_USB_GLOB_DIEPTXF4_OFST 0x110
12538 /* The address of the ALT_USB_GLOB_DIEPTXF4 register. */
12539 #define ALT_USB_GLOB_DIEPTXF4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF4_OFST))
12540 
12541 /*
12542  * Register : dieptxf5
12543  *
12544  * Device IN Endpoint Transmit FIFO Size Register 5
12545  *
12546  * Register Layout
12547  *
12548  * Bits | Access | Reset | Description
12549  * :--------|:-------|:-------|:-------------------------------------
12550  * [15:0] | RW | 0xc000 | ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR
12551  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP
12552  * [31:30] | ??? | 0x0 | *UNDEFINED*
12553  *
12554  */
12555 /*
12556  * Field : inepntxfstaddr
12557  *
12558  * IN Endpoint FIFOn Transmit RAM Start Address
12559  *
12560  * (INEPnTxFStAddr)
12561  *
12562  * This field contains the memory start address For IN endpoint
12563  *
12564  * Transmit FIFOn (0<n< = 15).
12565  *
12566  * The power-on reset value of this register is specified as the
12567  *
12568  * Largest Rx Data FIFO Depth
12569  *
12570  * Programmed values must not exceed the power-on value.
12571  *
12572  * Field Access Macros:
12573  *
12574  */
12575 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */
12576 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_LSB 0
12577 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */
12578 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_MSB 15
12579 /* The width in bits of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */
12580 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_WIDTH 16
12581 /* The mask used to set the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field value. */
12582 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_SET_MSK 0x0000ffff
12583 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field value. */
12584 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_CLR_MSK 0xffff0000
12585 /* The reset value of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */
12586 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_RESET 0xc000
12587 /* Extracts the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR field value from a register. */
12588 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
12589 /* Produces a ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field value suitable for setting the register. */
12590 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
12591 
12592 /*
12593  * Field : inepntxfdep
12594  *
12595  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
12596  *
12597  * This value is in terms of 32-bit words.
12598  *
12599  * Minimum value is 16
12600  *
12601  * Maximum value is 32,768
12602  *
12603  * The power-on reset value of this register is specified as the
12604  *
12605  * Largest IN Endpoint FIFO number Depth
12606  *
12607  * Programmed values must not exceed the power-on value
12608  *
12609  * Field Access Macros:
12610  *
12611  */
12612 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */
12613 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_LSB 16
12614 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */
12615 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_MSB 29
12616 /* The width in bits of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */
12617 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_WIDTH 14
12618 /* The mask used to set the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field value. */
12619 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_SET_MSK 0x3fff0000
12620 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field value. */
12621 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_CLR_MSK 0xc000ffff
12622 /* The reset value of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */
12623 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_RESET 0x2000
12624 /* Extracts the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP field value from a register. */
12625 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
12626 /* Produces a ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field value suitable for setting the register. */
12627 #define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
12628 
12629 #ifndef __ASSEMBLY__
12630 /*
12631  * WARNING: The C register and register group struct declarations are provided for
12632  * convenience and illustrative purposes. They should, however, be used with
12633  * caution as the C language standard provides no guarantees about the alignment or
12634  * atomicity of device memory accesses. The recommended practice for writing
12635  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12636  * alt_write_word() functions.
12637  *
12638  * The struct declaration for register ALT_USB_GLOB_DIEPTXF5.
12639  */
12640 struct ALT_USB_GLOB_DIEPTXF5_s
12641 {
12642  uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR */
12643  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP */
12644  uint32_t : 2; /* *UNDEFINED* */
12645 };
12646 
12647 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF5. */
12648 typedef volatile struct ALT_USB_GLOB_DIEPTXF5_s ALT_USB_GLOB_DIEPTXF5_t;
12649 #endif /* __ASSEMBLY__ */
12650 
12651 /* The reset value of the ALT_USB_GLOB_DIEPTXF5 register. */
12652 #define ALT_USB_GLOB_DIEPTXF5_RESET 0x2000c000
12653 /* The byte offset of the ALT_USB_GLOB_DIEPTXF5 register from the beginning of the component. */
12654 #define ALT_USB_GLOB_DIEPTXF5_OFST 0x114
12655 /* The address of the ALT_USB_GLOB_DIEPTXF5 register. */
12656 #define ALT_USB_GLOB_DIEPTXF5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF5_OFST))
12657 
12658 /*
12659  * Register : dieptxf6
12660  *
12661  * Device IN Endpoint Transmit FIFO Size Register 6
12662  *
12663  * Register Layout
12664  *
12665  * Bits | Access | Reset | Description
12666  * :--------|:-------|:-------|:-------------------------------------
12667  * [15:0] | RW | 0xe000 | ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR
12668  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP
12669  * [31:30] | ??? | 0x0 | *UNDEFINED*
12670  *
12671  */
12672 /*
12673  * Field : inepntxfstaddr
12674  *
12675  * IN Endpoint FIFOn Transmit RAM Start Address
12676  *
12677  * (INEPnTxFStAddr)
12678  *
12679  * This field contains the memory start address For IN endpoint
12680  *
12681  * Transmit FIFOn (0<n< = 15).
12682  *
12683  * The power-on reset value of this register is specified as the
12684  *
12685  * Largest Rx Data FIFO Depth
12686  *
12687  * Programmed values must not exceed the power-on value.
12688  *
12689  * Field Access Macros:
12690  *
12691  */
12692 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */
12693 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_LSB 0
12694 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */
12695 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_MSB 15
12696 /* The width in bits of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */
12697 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_WIDTH 16
12698 /* The mask used to set the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field value. */
12699 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_SET_MSK 0x0000ffff
12700 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field value. */
12701 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_CLR_MSK 0xffff0000
12702 /* The reset value of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */
12703 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_RESET 0xe000
12704 /* Extracts the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR field value from a register. */
12705 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
12706 /* Produces a ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field value suitable for setting the register. */
12707 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
12708 
12709 /*
12710  * Field : inepntxfdep
12711  *
12712  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
12713  *
12714  * This value is in terms of 32-bit words.
12715  *
12716  * Minimum value is 16
12717  *
12718  * Maximum value is 32,768
12719  *
12720  * The power-on reset value of this register is specified as the
12721  *
12722  * Largest IN Endpoint FIFO number Depth
12723  *
12724  * Programmed values must not exceed the power-on value
12725  *
12726  * Field Access Macros:
12727  *
12728  */
12729 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */
12730 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_LSB 16
12731 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */
12732 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_MSB 29
12733 /* The width in bits of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */
12734 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_WIDTH 14
12735 /* The mask used to set the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field value. */
12736 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_SET_MSK 0x3fff0000
12737 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field value. */
12738 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_CLR_MSK 0xc000ffff
12739 /* The reset value of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */
12740 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_RESET 0x2000
12741 /* Extracts the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP field value from a register. */
12742 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
12743 /* Produces a ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field value suitable for setting the register. */
12744 #define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
12745 
12746 #ifndef __ASSEMBLY__
12747 /*
12748  * WARNING: The C register and register group struct declarations are provided for
12749  * convenience and illustrative purposes. They should, however, be used with
12750  * caution as the C language standard provides no guarantees about the alignment or
12751  * atomicity of device memory accesses. The recommended practice for writing
12752  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12753  * alt_write_word() functions.
12754  *
12755  * The struct declaration for register ALT_USB_GLOB_DIEPTXF6.
12756  */
12757 struct ALT_USB_GLOB_DIEPTXF6_s
12758 {
12759  uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR */
12760  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP */
12761  uint32_t : 2; /* *UNDEFINED* */
12762 };
12763 
12764 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF6. */
12765 typedef volatile struct ALT_USB_GLOB_DIEPTXF6_s ALT_USB_GLOB_DIEPTXF6_t;
12766 #endif /* __ASSEMBLY__ */
12767 
12768 /* The reset value of the ALT_USB_GLOB_DIEPTXF6 register. */
12769 #define ALT_USB_GLOB_DIEPTXF6_RESET 0x2000e000
12770 /* The byte offset of the ALT_USB_GLOB_DIEPTXF6 register from the beginning of the component. */
12771 #define ALT_USB_GLOB_DIEPTXF6_OFST 0x118
12772 /* The address of the ALT_USB_GLOB_DIEPTXF6 register. */
12773 #define ALT_USB_GLOB_DIEPTXF6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF6_OFST))
12774 
12775 /*
12776  * Register : dieptxf7
12777  *
12778  * Device IN Endpoint Transmit FIFO Size Register 7
12779  *
12780  * Register Layout
12781  *
12782  * Bits | Access | Reset | Description
12783  * :--------|:-------|:-------|:-------------------------------------
12784  * [15:0] | RW | 0x0 | ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR
12785  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP
12786  * [31:30] | ??? | 0x0 | *UNDEFINED*
12787  *
12788  */
12789 /*
12790  * Field : inepntxfstaddr
12791  *
12792  * IN Endpoint FIFOn Transmit RAM Start Address
12793  *
12794  * (INEPnTxFStAddr)
12795  *
12796  * This field contains the memory start address For IN endpoint
12797  *
12798  * Transmit FIFOn (0<n< = 15).
12799  *
12800  * The power-on reset value of this register is specified as the
12801  *
12802  * Largest Rx Data FIFO Depth
12803  *
12804  * Programmed values must not exceed the power-on value.
12805  *
12806  * Field Access Macros:
12807  *
12808  */
12809 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */
12810 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_LSB 0
12811 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */
12812 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_MSB 15
12813 /* The width in bits of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */
12814 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_WIDTH 16
12815 /* The mask used to set the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field value. */
12816 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_SET_MSK 0x0000ffff
12817 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field value. */
12818 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_CLR_MSK 0xffff0000
12819 /* The reset value of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */
12820 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_RESET 0x0
12821 /* Extracts the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR field value from a register. */
12822 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
12823 /* Produces a ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field value suitable for setting the register. */
12824 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
12825 
12826 /*
12827  * Field : inepntxfdep
12828  *
12829  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
12830  *
12831  * This value is in terms of 32-bit words.
12832  *
12833  * Minimum value is 16
12834  *
12835  * Maximum value is 32,768
12836  *
12837  * The power-on reset value of this register is specified as the
12838  *
12839  * Largest IN Endpoint FIFO number Depth
12840  *
12841  * Programmed values must not exceed the power-on value
12842  *
12843  * Field Access Macros:
12844  *
12845  */
12846 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */
12847 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_LSB 16
12848 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */
12849 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_MSB 29
12850 /* The width in bits of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */
12851 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_WIDTH 14
12852 /* The mask used to set the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field value. */
12853 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_SET_MSK 0x3fff0000
12854 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field value. */
12855 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_CLR_MSK 0xc000ffff
12856 /* The reset value of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */
12857 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_RESET 0x2000
12858 /* Extracts the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP field value from a register. */
12859 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
12860 /* Produces a ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field value suitable for setting the register. */
12861 #define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
12862 
12863 #ifndef __ASSEMBLY__
12864 /*
12865  * WARNING: The C register and register group struct declarations are provided for
12866  * convenience and illustrative purposes. They should, however, be used with
12867  * caution as the C language standard provides no guarantees about the alignment or
12868  * atomicity of device memory accesses. The recommended practice for writing
12869  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12870  * alt_write_word() functions.
12871  *
12872  * The struct declaration for register ALT_USB_GLOB_DIEPTXF7.
12873  */
12874 struct ALT_USB_GLOB_DIEPTXF7_s
12875 {
12876  uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR */
12877  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP */
12878  uint32_t : 2; /* *UNDEFINED* */
12879 };
12880 
12881 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF7. */
12882 typedef volatile struct ALT_USB_GLOB_DIEPTXF7_s ALT_USB_GLOB_DIEPTXF7_t;
12883 #endif /* __ASSEMBLY__ */
12884 
12885 /* The reset value of the ALT_USB_GLOB_DIEPTXF7 register. */
12886 #define ALT_USB_GLOB_DIEPTXF7_RESET 0x20000000
12887 /* The byte offset of the ALT_USB_GLOB_DIEPTXF7 register from the beginning of the component. */
12888 #define ALT_USB_GLOB_DIEPTXF7_OFST 0x11c
12889 /* The address of the ALT_USB_GLOB_DIEPTXF7 register. */
12890 #define ALT_USB_GLOB_DIEPTXF7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF7_OFST))
12891 
12892 /*
12893  * Register : dieptxf8
12894  *
12895  * Device IN Endpoint Transmit FIFO Size Register 8
12896  *
12897  * Register Layout
12898  *
12899  * Bits | Access | Reset | Description
12900  * :--------|:-------|:-------|:-------------------------------------
12901  * [15:0] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR
12902  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP
12903  * [31:30] | ??? | 0x0 | *UNDEFINED*
12904  *
12905  */
12906 /*
12907  * Field : inepntxfstaddr
12908  *
12909  * IN Endpoint FIFOn Transmit RAM Start Address
12910  *
12911  * (INEPnTxFStAddr)
12912  *
12913  * This field contains the memory start address For IN endpoint
12914  *
12915  * Transmit FIFOn (0<n< = 15).
12916  *
12917  * The power-on reset value of this register is specified as the
12918  *
12919  * Largest Rx Data FIFO Depth
12920  *
12921  * Programmed values must not exceed the power-on value.
12922  *
12923  * Field Access Macros:
12924  *
12925  */
12926 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */
12927 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_LSB 0
12928 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */
12929 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_MSB 15
12930 /* The width in bits of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */
12931 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_WIDTH 16
12932 /* The mask used to set the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field value. */
12933 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_SET_MSK 0x0000ffff
12934 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field value. */
12935 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_CLR_MSK 0xffff0000
12936 /* The reset value of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */
12937 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_RESET 0x2000
12938 /* Extracts the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR field value from a register. */
12939 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
12940 /* Produces a ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field value suitable for setting the register. */
12941 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
12942 
12943 /*
12944  * Field : inepntxfdep
12945  *
12946  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
12947  *
12948  * This value is in terms of 32-bit words.
12949  *
12950  * Minimum value is 16
12951  *
12952  * Maximum value is 32,768
12953  *
12954  * The power-on reset value of this register is specified as the
12955  *
12956  * Largest IN Endpoint FIFO number Depth
12957  *
12958  * Programmed values must not exceed the power-on value
12959  *
12960  * Field Access Macros:
12961  *
12962  */
12963 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */
12964 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_LSB 16
12965 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */
12966 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_MSB 29
12967 /* The width in bits of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */
12968 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_WIDTH 14
12969 /* The mask used to set the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field value. */
12970 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_SET_MSK 0x3fff0000
12971 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field value. */
12972 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_CLR_MSK 0xc000ffff
12973 /* The reset value of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */
12974 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_RESET 0x2000
12975 /* Extracts the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP field value from a register. */
12976 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
12977 /* Produces a ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field value suitable for setting the register. */
12978 #define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
12979 
12980 #ifndef __ASSEMBLY__
12981 /*
12982  * WARNING: The C register and register group struct declarations are provided for
12983  * convenience and illustrative purposes. They should, however, be used with
12984  * caution as the C language standard provides no guarantees about the alignment or
12985  * atomicity of device memory accesses. The recommended practice for writing
12986  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12987  * alt_write_word() functions.
12988  *
12989  * The struct declaration for register ALT_USB_GLOB_DIEPTXF8.
12990  */
12991 struct ALT_USB_GLOB_DIEPTXF8_s
12992 {
12993  uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR */
12994  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP */
12995  uint32_t : 2; /* *UNDEFINED* */
12996 };
12997 
12998 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF8. */
12999 typedef volatile struct ALT_USB_GLOB_DIEPTXF8_s ALT_USB_GLOB_DIEPTXF8_t;
13000 #endif /* __ASSEMBLY__ */
13001 
13002 /* The reset value of the ALT_USB_GLOB_DIEPTXF8 register. */
13003 #define ALT_USB_GLOB_DIEPTXF8_RESET 0x20002000
13004 /* The byte offset of the ALT_USB_GLOB_DIEPTXF8 register from the beginning of the component. */
13005 #define ALT_USB_GLOB_DIEPTXF8_OFST 0x120
13006 /* The address of the ALT_USB_GLOB_DIEPTXF8 register. */
13007 #define ALT_USB_GLOB_DIEPTXF8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF8_OFST))
13008 
13009 /*
13010  * Register : dieptxf9
13011  *
13012  * Device IN Endpoint Transmit FIFO Size Register 9
13013  *
13014  * Register Layout
13015  *
13016  * Bits | Access | Reset | Description
13017  * :--------|:-------|:-------|:-------------------------------------
13018  * [15:0] | RW | 0x4000 | ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR
13019  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP
13020  * [31:30] | ??? | 0x0 | *UNDEFINED*
13021  *
13022  */
13023 /*
13024  * Field : inepntxfstaddr
13025  *
13026  * IN Endpoint FIFOn Transmit RAM Start Address
13027  *
13028  * (INEPnTxFStAddr)
13029  *
13030  * This field contains the memory start address For IN endpoint
13031  *
13032  * Transmit FIFOn (0<n< = 15).
13033  *
13034  * The power-on reset value of this register is specified as the
13035  *
13036  * Largest Rx Data FIFO Depth
13037  *
13038  * Programmed values must not exceed the power-on value.
13039  *
13040  * Field Access Macros:
13041  *
13042  */
13043 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */
13044 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_LSB 0
13045 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */
13046 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_MSB 15
13047 /* The width in bits of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */
13048 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_WIDTH 16
13049 /* The mask used to set the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field value. */
13050 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_SET_MSK 0x0000ffff
13051 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field value. */
13052 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_CLR_MSK 0xffff0000
13053 /* The reset value of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */
13054 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_RESET 0x4000
13055 /* Extracts the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR field value from a register. */
13056 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
13057 /* Produces a ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field value suitable for setting the register. */
13058 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
13059 
13060 /*
13061  * Field : inepntxfdep
13062  *
13063  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
13064  *
13065  * This value is in terms of 32-bit words.
13066  *
13067  * Minimum value is 16
13068  *
13069  * Maximum value is 32,768
13070  *
13071  * The power-on reset value of this register is specified as the
13072  *
13073  * Largest IN Endpoint FIFO number Depth
13074  *
13075  * Programmed values must not exceed the power-on value
13076  *
13077  * Field Access Macros:
13078  *
13079  */
13080 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */
13081 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_LSB 16
13082 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */
13083 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_MSB 29
13084 /* The width in bits of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */
13085 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_WIDTH 14
13086 /* The mask used to set the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field value. */
13087 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_SET_MSK 0x3fff0000
13088 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field value. */
13089 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_CLR_MSK 0xc000ffff
13090 /* The reset value of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */
13091 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_RESET 0x2000
13092 /* Extracts the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP field value from a register. */
13093 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
13094 /* Produces a ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field value suitable for setting the register. */
13095 #define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
13096 
13097 #ifndef __ASSEMBLY__
13098 /*
13099  * WARNING: The C register and register group struct declarations are provided for
13100  * convenience and illustrative purposes. They should, however, be used with
13101  * caution as the C language standard provides no guarantees about the alignment or
13102  * atomicity of device memory accesses. The recommended practice for writing
13103  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13104  * alt_write_word() functions.
13105  *
13106  * The struct declaration for register ALT_USB_GLOB_DIEPTXF9.
13107  */
13108 struct ALT_USB_GLOB_DIEPTXF9_s
13109 {
13110  uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR */
13111  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP */
13112  uint32_t : 2; /* *UNDEFINED* */
13113 };
13114 
13115 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF9. */
13116 typedef volatile struct ALT_USB_GLOB_DIEPTXF9_s ALT_USB_GLOB_DIEPTXF9_t;
13117 #endif /* __ASSEMBLY__ */
13118 
13119 /* The reset value of the ALT_USB_GLOB_DIEPTXF9 register. */
13120 #define ALT_USB_GLOB_DIEPTXF9_RESET 0x20004000
13121 /* The byte offset of the ALT_USB_GLOB_DIEPTXF9 register from the beginning of the component. */
13122 #define ALT_USB_GLOB_DIEPTXF9_OFST 0x124
13123 /* The address of the ALT_USB_GLOB_DIEPTXF9 register. */
13124 #define ALT_USB_GLOB_DIEPTXF9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF9_OFST))
13125 
13126 /*
13127  * Register : dieptxf10
13128  *
13129  * Device IN Endpoint Transmit FIFO Size Register 10
13130  *
13131  * Register Layout
13132  *
13133  * Bits | Access | Reset | Description
13134  * :--------|:-------|:-------|:--------------------------------------
13135  * [15:0] | RW | 0x6000 | ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR
13136  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP
13137  * [31:30] | ??? | 0x0 | *UNDEFINED*
13138  *
13139  */
13140 /*
13141  * Field : inepntxfstaddr
13142  *
13143  * IN Endpoint FIFOn Transmit RAM Start Address
13144  *
13145  * (INEPnTxFStAddr)
13146  *
13147  * This field contains the memory start address For IN endpoint
13148  *
13149  * Transmit FIFOn (0<n< = 15).
13150  *
13151  * The power-on reset value of this register is specified as the
13152  *
13153  * Largest Rx Data FIFO Depth
13154  *
13155  * Programmed values must not exceed the power-on value.
13156  *
13157  * Field Access Macros:
13158  *
13159  */
13160 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */
13161 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_LSB 0
13162 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */
13163 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_MSB 15
13164 /* The width in bits of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */
13165 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_WIDTH 16
13166 /* The mask used to set the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field value. */
13167 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_SET_MSK 0x0000ffff
13168 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field value. */
13169 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_CLR_MSK 0xffff0000
13170 /* The reset value of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */
13171 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_RESET 0x6000
13172 /* Extracts the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR field value from a register. */
13173 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
13174 /* Produces a ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field value suitable for setting the register. */
13175 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
13176 
13177 /*
13178  * Field : inepntxfdep
13179  *
13180  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
13181  *
13182  * This value is in terms of 32-bit words.
13183  *
13184  * Minimum value is 16
13185  *
13186  * Maximum value is 32,768
13187  *
13188  * The power-on reset value of this register is specified as the
13189  *
13190  * Largest IN Endpoint FIFO number Depth
13191  *
13192  * Programmed values must not exceed the power-on value
13193  *
13194  * Field Access Macros:
13195  *
13196  */
13197 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */
13198 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_LSB 16
13199 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */
13200 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_MSB 29
13201 /* The width in bits of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */
13202 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_WIDTH 14
13203 /* The mask used to set the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field value. */
13204 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_SET_MSK 0x3fff0000
13205 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field value. */
13206 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_CLR_MSK 0xc000ffff
13207 /* The reset value of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */
13208 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_RESET 0x2000
13209 /* Extracts the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP field value from a register. */
13210 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
13211 /* Produces a ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field value suitable for setting the register. */
13212 #define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
13213 
13214 #ifndef __ASSEMBLY__
13215 /*
13216  * WARNING: The C register and register group struct declarations are provided for
13217  * convenience and illustrative purposes. They should, however, be used with
13218  * caution as the C language standard provides no guarantees about the alignment or
13219  * atomicity of device memory accesses. The recommended practice for writing
13220  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13221  * alt_write_word() functions.
13222  *
13223  * The struct declaration for register ALT_USB_GLOB_DIEPTXF10.
13224  */
13225 struct ALT_USB_GLOB_DIEPTXF10_s
13226 {
13227  uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR */
13228  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP */
13229  uint32_t : 2; /* *UNDEFINED* */
13230 };
13231 
13232 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF10. */
13233 typedef volatile struct ALT_USB_GLOB_DIEPTXF10_s ALT_USB_GLOB_DIEPTXF10_t;
13234 #endif /* __ASSEMBLY__ */
13235 
13236 /* The reset value of the ALT_USB_GLOB_DIEPTXF10 register. */
13237 #define ALT_USB_GLOB_DIEPTXF10_RESET 0x20006000
13238 /* The byte offset of the ALT_USB_GLOB_DIEPTXF10 register from the beginning of the component. */
13239 #define ALT_USB_GLOB_DIEPTXF10_OFST 0x128
13240 /* The address of the ALT_USB_GLOB_DIEPTXF10 register. */
13241 #define ALT_USB_GLOB_DIEPTXF10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF10_OFST))
13242 
13243 /*
13244  * Register : dieptxf11
13245  *
13246  * Device IN Endpoint Transmit FIFO Size Register 11
13247  *
13248  * Register Layout
13249  *
13250  * Bits | Access | Reset | Description
13251  * :--------|:-------|:-------|:--------------------------------------
13252  * [15:0] | RW | 0x8000 | ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR
13253  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP
13254  * [31:30] | ??? | 0x0 | *UNDEFINED*
13255  *
13256  */
13257 /*
13258  * Field : inepntxfstaddr
13259  *
13260  * IN Endpoint FIFOn Transmit RAM Start Address
13261  *
13262  * (INEPnTxFStAddr)
13263  *
13264  * This field contains the memory start address For IN endpoint
13265  *
13266  * Transmit FIFOn (0<n< = 15).
13267  *
13268  * The power-on reset value of this register is specified as the
13269  *
13270  * Largest Rx Data FIFO Depth
13271  *
13272  * Programmed values must not exceed the power-on value.
13273  *
13274  * Field Access Macros:
13275  *
13276  */
13277 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */
13278 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_LSB 0
13279 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */
13280 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_MSB 15
13281 /* The width in bits of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */
13282 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_WIDTH 16
13283 /* The mask used to set the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field value. */
13284 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_SET_MSK 0x0000ffff
13285 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field value. */
13286 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_CLR_MSK 0xffff0000
13287 /* The reset value of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */
13288 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_RESET 0x8000
13289 /* Extracts the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR field value from a register. */
13290 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
13291 /* Produces a ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field value suitable for setting the register. */
13292 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
13293 
13294 /*
13295  * Field : inepntxfdep
13296  *
13297  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
13298  *
13299  * This value is in terms of 32-bit words.
13300  *
13301  * Minimum value is 16
13302  *
13303  * Maximum value is 32,768
13304  *
13305  * The power-on reset value of this register is specified as the
13306  *
13307  * Largest IN Endpoint FIFO number Depth
13308  *
13309  * Programmed values must not exceed the power-on value
13310  *
13311  * Field Access Macros:
13312  *
13313  */
13314 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */
13315 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_LSB 16
13316 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */
13317 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_MSB 29
13318 /* The width in bits of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */
13319 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_WIDTH 14
13320 /* The mask used to set the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field value. */
13321 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_SET_MSK 0x3fff0000
13322 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field value. */
13323 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_CLR_MSK 0xc000ffff
13324 /* The reset value of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */
13325 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_RESET 0x2000
13326 /* Extracts the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP field value from a register. */
13327 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
13328 /* Produces a ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field value suitable for setting the register. */
13329 #define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
13330 
13331 #ifndef __ASSEMBLY__
13332 /*
13333  * WARNING: The C register and register group struct declarations are provided for
13334  * convenience and illustrative purposes. They should, however, be used with
13335  * caution as the C language standard provides no guarantees about the alignment or
13336  * atomicity of device memory accesses. The recommended practice for writing
13337  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13338  * alt_write_word() functions.
13339  *
13340  * The struct declaration for register ALT_USB_GLOB_DIEPTXF11.
13341  */
13342 struct ALT_USB_GLOB_DIEPTXF11_s
13343 {
13344  uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR */
13345  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP */
13346  uint32_t : 2; /* *UNDEFINED* */
13347 };
13348 
13349 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF11. */
13350 typedef volatile struct ALT_USB_GLOB_DIEPTXF11_s ALT_USB_GLOB_DIEPTXF11_t;
13351 #endif /* __ASSEMBLY__ */
13352 
13353 /* The reset value of the ALT_USB_GLOB_DIEPTXF11 register. */
13354 #define ALT_USB_GLOB_DIEPTXF11_RESET 0x20008000
13355 /* The byte offset of the ALT_USB_GLOB_DIEPTXF11 register from the beginning of the component. */
13356 #define ALT_USB_GLOB_DIEPTXF11_OFST 0x12c
13357 /* The address of the ALT_USB_GLOB_DIEPTXF11 register. */
13358 #define ALT_USB_GLOB_DIEPTXF11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF11_OFST))
13359 
13360 /*
13361  * Register : dieptxf12
13362  *
13363  * Device IN Endpoint Transmit FIFO Size Register 12
13364  *
13365  * Register Layout
13366  *
13367  * Bits | Access | Reset | Description
13368  * :--------|:-------|:-------|:--------------------------------------
13369  * [15:0] | RW | 0xa000 | ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR
13370  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP
13371  * [31:30] | ??? | 0x0 | *UNDEFINED*
13372  *
13373  */
13374 /*
13375  * Field : inepntxfstaddr
13376  *
13377  * IN Endpoint FIFOn Transmit RAM Start Address
13378  *
13379  * (INEPnTxFStAddr)
13380  *
13381  * This field contains the memory start address For IN endpoint
13382  *
13383  * Transmit FIFOn (0<n< = 15).
13384  *
13385  * The power-on reset value of this register is specified as the
13386  *
13387  * Largest Rx Data FIFO Depth
13388  *
13389  * Programmed values must not exceed the power-on value.
13390  *
13391  * Field Access Macros:
13392  *
13393  */
13394 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */
13395 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_LSB 0
13396 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */
13397 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_MSB 15
13398 /* The width in bits of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */
13399 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_WIDTH 16
13400 /* The mask used to set the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field value. */
13401 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_SET_MSK 0x0000ffff
13402 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field value. */
13403 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_CLR_MSK 0xffff0000
13404 /* The reset value of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */
13405 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_RESET 0xa000
13406 /* Extracts the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR field value from a register. */
13407 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
13408 /* Produces a ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field value suitable for setting the register. */
13409 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
13410 
13411 /*
13412  * Field : inepntxfdep
13413  *
13414  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
13415  *
13416  * This value is in terms of 32-bit words.
13417  *
13418  * Minimum value is 16
13419  *
13420  * Maximum value is 32,768
13421  *
13422  * The power-on reset value of this register is specified as the
13423  *
13424  * Largest IN Endpoint FIFO number Depth
13425  *
13426  * Programmed values must not exceed the power-on value
13427  *
13428  * Field Access Macros:
13429  *
13430  */
13431 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */
13432 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_LSB 16
13433 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */
13434 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_MSB 29
13435 /* The width in bits of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */
13436 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_WIDTH 14
13437 /* The mask used to set the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field value. */
13438 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_SET_MSK 0x3fff0000
13439 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field value. */
13440 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_CLR_MSK 0xc000ffff
13441 /* The reset value of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */
13442 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_RESET 0x2000
13443 /* Extracts the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP field value from a register. */
13444 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
13445 /* Produces a ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field value suitable for setting the register. */
13446 #define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
13447 
13448 #ifndef __ASSEMBLY__
13449 /*
13450  * WARNING: The C register and register group struct declarations are provided for
13451  * convenience and illustrative purposes. They should, however, be used with
13452  * caution as the C language standard provides no guarantees about the alignment or
13453  * atomicity of device memory accesses. The recommended practice for writing
13454  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13455  * alt_write_word() functions.
13456  *
13457  * The struct declaration for register ALT_USB_GLOB_DIEPTXF12.
13458  */
13459 struct ALT_USB_GLOB_DIEPTXF12_s
13460 {
13461  uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR */
13462  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP */
13463  uint32_t : 2; /* *UNDEFINED* */
13464 };
13465 
13466 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF12. */
13467 typedef volatile struct ALT_USB_GLOB_DIEPTXF12_s ALT_USB_GLOB_DIEPTXF12_t;
13468 #endif /* __ASSEMBLY__ */
13469 
13470 /* The reset value of the ALT_USB_GLOB_DIEPTXF12 register. */
13471 #define ALT_USB_GLOB_DIEPTXF12_RESET 0x2000a000
13472 /* The byte offset of the ALT_USB_GLOB_DIEPTXF12 register from the beginning of the component. */
13473 #define ALT_USB_GLOB_DIEPTXF12_OFST 0x130
13474 /* The address of the ALT_USB_GLOB_DIEPTXF12 register. */
13475 #define ALT_USB_GLOB_DIEPTXF12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF12_OFST))
13476 
13477 /*
13478  * Register : dieptxf13
13479  *
13480  * Device IN Endpoint Transmit FIFO Size Register 13
13481  *
13482  * Register Layout
13483  *
13484  * Bits | Access | Reset | Description
13485  * :--------|:-------|:-------|:--------------------------------------
13486  * [15:0] | RW | 0xc000 | ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR
13487  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP
13488  * [31:30] | ??? | 0x0 | *UNDEFINED*
13489  *
13490  */
13491 /*
13492  * Field : inepntxfstaddr
13493  *
13494  * IN Endpoint FIFOn Transmit RAM Start Address
13495  *
13496  * (INEPnTxFStAddr)
13497  *
13498  * This field contains the memory start address For IN endpoint
13499  *
13500  * Transmit FIFOn (0<n< = 15).
13501  *
13502  * The power-on reset value of this register is specified as the
13503  *
13504  * Largest Rx Data FIFO Depth
13505  *
13506  * Programmed values must not exceed the power-on value.
13507  *
13508  * Field Access Macros:
13509  *
13510  */
13511 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */
13512 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_LSB 0
13513 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */
13514 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_MSB 15
13515 /* The width in bits of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */
13516 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_WIDTH 16
13517 /* The mask used to set the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field value. */
13518 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_SET_MSK 0x0000ffff
13519 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field value. */
13520 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_CLR_MSK 0xffff0000
13521 /* The reset value of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */
13522 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_RESET 0xc000
13523 /* Extracts the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR field value from a register. */
13524 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
13525 /* Produces a ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field value suitable for setting the register. */
13526 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
13527 
13528 /*
13529  * Field : inepntxfdep
13530  *
13531  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
13532  *
13533  * This value is in terms of 32-bit words.
13534  *
13535  * Minimum value is 16
13536  *
13537  * Maximum value is 32,768
13538  *
13539  * The power-on reset value of this register is specified as the
13540  *
13541  * Largest IN Endpoint FIFO number Depth
13542  *
13543  * Programmed values must not exceed the power-on value
13544  *
13545  * Field Access Macros:
13546  *
13547  */
13548 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */
13549 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_LSB 16
13550 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */
13551 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_MSB 29
13552 /* The width in bits of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */
13553 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_WIDTH 14
13554 /* The mask used to set the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field value. */
13555 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_SET_MSK 0x3fff0000
13556 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field value. */
13557 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_CLR_MSK 0xc000ffff
13558 /* The reset value of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */
13559 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_RESET 0x2000
13560 /* Extracts the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP field value from a register. */
13561 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
13562 /* Produces a ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field value suitable for setting the register. */
13563 #define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
13564 
13565 #ifndef __ASSEMBLY__
13566 /*
13567  * WARNING: The C register and register group struct declarations are provided for
13568  * convenience and illustrative purposes. They should, however, be used with
13569  * caution as the C language standard provides no guarantees about the alignment or
13570  * atomicity of device memory accesses. The recommended practice for writing
13571  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13572  * alt_write_word() functions.
13573  *
13574  * The struct declaration for register ALT_USB_GLOB_DIEPTXF13.
13575  */
13576 struct ALT_USB_GLOB_DIEPTXF13_s
13577 {
13578  uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR */
13579  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP */
13580  uint32_t : 2; /* *UNDEFINED* */
13581 };
13582 
13583 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF13. */
13584 typedef volatile struct ALT_USB_GLOB_DIEPTXF13_s ALT_USB_GLOB_DIEPTXF13_t;
13585 #endif /* __ASSEMBLY__ */
13586 
13587 /* The reset value of the ALT_USB_GLOB_DIEPTXF13 register. */
13588 #define ALT_USB_GLOB_DIEPTXF13_RESET 0x2000c000
13589 /* The byte offset of the ALT_USB_GLOB_DIEPTXF13 register from the beginning of the component. */
13590 #define ALT_USB_GLOB_DIEPTXF13_OFST 0x134
13591 /* The address of the ALT_USB_GLOB_DIEPTXF13 register. */
13592 #define ALT_USB_GLOB_DIEPTXF13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF13_OFST))
13593 
13594 /*
13595  * Register : dieptxf14
13596  *
13597  * Device IN Endpoint Transmit FIFO Size Register 14
13598  *
13599  * Register Layout
13600  *
13601  * Bits | Access | Reset | Description
13602  * :--------|:-------|:-------|:--------------------------------------
13603  * [15:0] | RW | 0xe000 | ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR
13604  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP
13605  * [31:30] | ??? | 0x0 | *UNDEFINED*
13606  *
13607  */
13608 /*
13609  * Field : inepntxfstaddr
13610  *
13611  * IN Endpoint FIFOn Transmit RAM Start Address
13612  *
13613  * (INEPnTxFStAddr)
13614  *
13615  * This field contains the memory start address For IN endpoint
13616  *
13617  * Transmit FIFOn (0<n< = 15).
13618  *
13619  * The power-on reset value of this register is specified as the
13620  *
13621  * Largest Rx Data FIFO Depth
13622  *
13623  * Programmed values must not exceed the power-on value.
13624  *
13625  * Field Access Macros:
13626  *
13627  */
13628 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */
13629 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_LSB 0
13630 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */
13631 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_MSB 15
13632 /* The width in bits of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */
13633 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_WIDTH 16
13634 /* The mask used to set the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field value. */
13635 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_SET_MSK 0x0000ffff
13636 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field value. */
13637 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_CLR_MSK 0xffff0000
13638 /* The reset value of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */
13639 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_RESET 0xe000
13640 /* Extracts the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR field value from a register. */
13641 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
13642 /* Produces a ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field value suitable for setting the register. */
13643 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
13644 
13645 /*
13646  * Field : inepntxfdep
13647  *
13648  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
13649  *
13650  * This value is in terms of 32-bit words.
13651  *
13652  * Minimum value is 16
13653  *
13654  * Maximum value is 32,768
13655  *
13656  * The power-on reset value of this register is specified as the
13657  *
13658  * Largest IN Endpoint FIFO number Depth
13659  *
13660  * Programmed values must not exceed the power-on value
13661  *
13662  * Field Access Macros:
13663  *
13664  */
13665 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */
13666 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_LSB 16
13667 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */
13668 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_MSB 29
13669 /* The width in bits of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */
13670 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_WIDTH 14
13671 /* The mask used to set the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field value. */
13672 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_SET_MSK 0x3fff0000
13673 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field value. */
13674 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_CLR_MSK 0xc000ffff
13675 /* The reset value of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */
13676 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_RESET 0x2000
13677 /* Extracts the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP field value from a register. */
13678 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
13679 /* Produces a ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field value suitable for setting the register. */
13680 #define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
13681 
13682 #ifndef __ASSEMBLY__
13683 /*
13684  * WARNING: The C register and register group struct declarations are provided for
13685  * convenience and illustrative purposes. They should, however, be used with
13686  * caution as the C language standard provides no guarantees about the alignment or
13687  * atomicity of device memory accesses. The recommended practice for writing
13688  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13689  * alt_write_word() functions.
13690  *
13691  * The struct declaration for register ALT_USB_GLOB_DIEPTXF14.
13692  */
13693 struct ALT_USB_GLOB_DIEPTXF14_s
13694 {
13695  uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR */
13696  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP */
13697  uint32_t : 2; /* *UNDEFINED* */
13698 };
13699 
13700 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF14. */
13701 typedef volatile struct ALT_USB_GLOB_DIEPTXF14_s ALT_USB_GLOB_DIEPTXF14_t;
13702 #endif /* __ASSEMBLY__ */
13703 
13704 /* The reset value of the ALT_USB_GLOB_DIEPTXF14 register. */
13705 #define ALT_USB_GLOB_DIEPTXF14_RESET 0x2000e000
13706 /* The byte offset of the ALT_USB_GLOB_DIEPTXF14 register from the beginning of the component. */
13707 #define ALT_USB_GLOB_DIEPTXF14_OFST 0x138
13708 /* The address of the ALT_USB_GLOB_DIEPTXF14 register. */
13709 #define ALT_USB_GLOB_DIEPTXF14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF14_OFST))
13710 
13711 /*
13712  * Register : dieptxf15
13713  *
13714  * Device IN Endpoint Transmit FIFO Size Register 15
13715  *
13716  * Register Layout
13717  *
13718  * Bits | Access | Reset | Description
13719  * :--------|:-------|:-------|:--------------------------------------
13720  * [15:0] | RW | 0x0 | ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR
13721  * [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP
13722  * [31:30] | ??? | 0x0 | *UNDEFINED*
13723  *
13724  */
13725 /*
13726  * Field : inepntxfstaddr
13727  *
13728  * IN Endpoint FIFOn Transmit RAM Start Address
13729  *
13730  * (INEPnTxFStAddr)
13731  *
13732  * This field contains the memory start address For IN endpoint
13733  *
13734  * Transmit FIFOn (0<n< = 15).
13735  *
13736  * The power-on reset value of this register is specified as the
13737  *
13738  * Largest Rx Data FIFO Depth
13739  *
13740  * Programmed values must not exceed the power-on value.
13741  *
13742  * Field Access Macros:
13743  *
13744  */
13745 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */
13746 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_LSB 0
13747 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */
13748 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_MSB 15
13749 /* The width in bits of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */
13750 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_WIDTH 16
13751 /* The mask used to set the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field value. */
13752 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_SET_MSK 0x0000ffff
13753 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field value. */
13754 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_CLR_MSK 0xffff0000
13755 /* The reset value of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */
13756 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_RESET 0x0
13757 /* Extracts the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR field value from a register. */
13758 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
13759 /* Produces a ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field value suitable for setting the register. */
13760 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
13761 
13762 /*
13763  * Field : inepntxfdep
13764  *
13765  * IN Endpoint TxFIFO Depth (INEPnTxFDep)
13766  *
13767  * This value is in terms of 32-bit words.
13768  *
13769  * Minimum value is 16
13770  *
13771  * Maximum value is 32,768
13772  *
13773  * The power-on reset value of this register is specified as the
13774  *
13775  * Largest IN Endpoint FIFO number Depth
13776  *
13777  * Programmed values must not exceed the power-on value
13778  *
13779  * Field Access Macros:
13780  *
13781  */
13782 /* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */
13783 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_LSB 16
13784 /* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */
13785 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_MSB 29
13786 /* The width in bits of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */
13787 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_WIDTH 14
13788 /* The mask used to set the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field value. */
13789 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_SET_MSK 0x3fff0000
13790 /* The mask used to clear the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field value. */
13791 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_CLR_MSK 0xc000ffff
13792 /* The reset value of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */
13793 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_RESET 0x2000
13794 /* Extracts the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP field value from a register. */
13795 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
13796 /* Produces a ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field value suitable for setting the register. */
13797 #define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
13798 
13799 #ifndef __ASSEMBLY__
13800 /*
13801  * WARNING: The C register and register group struct declarations are provided for
13802  * convenience and illustrative purposes. They should, however, be used with
13803  * caution as the C language standard provides no guarantees about the alignment or
13804  * atomicity of device memory accesses. The recommended practice for writing
13805  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13806  * alt_write_word() functions.
13807  *
13808  * The struct declaration for register ALT_USB_GLOB_DIEPTXF15.
13809  */
13810 struct ALT_USB_GLOB_DIEPTXF15_s
13811 {
13812  uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR */
13813  uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP */
13814  uint32_t : 2; /* *UNDEFINED* */
13815 };
13816 
13817 /* The typedef declaration for register ALT_USB_GLOB_DIEPTXF15. */
13818 typedef volatile struct ALT_USB_GLOB_DIEPTXF15_s ALT_USB_GLOB_DIEPTXF15_t;
13819 #endif /* __ASSEMBLY__ */
13820 
13821 /* The reset value of the ALT_USB_GLOB_DIEPTXF15 register. */
13822 #define ALT_USB_GLOB_DIEPTXF15_RESET 0x20000000
13823 /* The byte offset of the ALT_USB_GLOB_DIEPTXF15 register from the beginning of the component. */
13824 #define ALT_USB_GLOB_DIEPTXF15_OFST 0x13c
13825 /* The address of the ALT_USB_GLOB_DIEPTXF15 register. */
13826 #define ALT_USB_GLOB_DIEPTXF15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF15_OFST))
13827 
13828 #ifndef __ASSEMBLY__
13829 /*
13830  * WARNING: The C register and register group struct declarations are provided for
13831  * convenience and illustrative purposes. They should, however, be used with
13832  * caution as the C language standard provides no guarantees about the alignment or
13833  * atomicity of device memory accesses. The recommended practice for writing
13834  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13835  * alt_write_word() functions.
13836  *
13837  * The struct declaration for register group ALT_USB_GLOB.
13838  */
13839 struct ALT_USB_GLOB_s
13840 {
13841  ALT_USB_GLOB_GOTGCTL_t gotgctl; /* ALT_USB_GLOB_GOTGCTL */
13842  ALT_USB_GLOB_GOTGINT_t gotgint; /* ALT_USB_GLOB_GOTGINT */
13843  ALT_USB_GLOB_GAHBCFG_t gahbcfg; /* ALT_USB_GLOB_GAHBCFG */
13844  ALT_USB_GLOB_GUSBCFG_t gusbcfg; /* ALT_USB_GLOB_GUSBCFG */
13845  ALT_USB_GLOB_GRSTCTL_t grstctl; /* ALT_USB_GLOB_GRSTCTL */
13846  ALT_USB_GLOB_GINTSTS_t gintsts; /* ALT_USB_GLOB_GINTSTS */
13847  ALT_USB_GLOB_GINTMSK_t gintmsk; /* ALT_USB_GLOB_GINTMSK */
13848  ALT_USB_GLOB_GRXSTSR_t grxstsr; /* ALT_USB_GLOB_GRXSTSR */
13849  ALT_USB_GLOB_GRXSTSP_t grxstsp; /* ALT_USB_GLOB_GRXSTSP */
13850  ALT_USB_GLOB_GRXFSIZ_t grxfsiz; /* ALT_USB_GLOB_GRXFSIZ */
13851  ALT_USB_GLOB_GNPTXFSIZ_t gnptxfsiz; /* ALT_USB_GLOB_GNPTXFSIZ */
13852  ALT_USB_GLOB_GNPTXSTS_t gnptxsts; /* ALT_USB_GLOB_GNPTXSTS */
13853  volatile uint32_t _pad_0x30_0x33; /* *UNDEFINED* */
13854  ALT_USB_GLOB_GPVNDCTL_t gpvndctl; /* ALT_USB_GLOB_GPVNDCTL */
13855  ALT_USB_GLOB_GGPIO_t ggpio; /* ALT_USB_GLOB_GGPIO */
13856  ALT_USB_GLOB_GUID_t guid; /* ALT_USB_GLOB_GUID */
13857  ALT_USB_GLOB_GSNPSID_t gsnpsid; /* ALT_USB_GLOB_GSNPSID */
13858  ALT_USB_GLOB_GHWCFG1_t ghwcfg1; /* ALT_USB_GLOB_GHWCFG1 */
13859  ALT_USB_GLOB_GHWCFG2_t ghwcfg2; /* ALT_USB_GLOB_GHWCFG2 */
13860  ALT_USB_GLOB_GHWCFG3_t ghwcfg3; /* ALT_USB_GLOB_GHWCFG3 */
13861  ALT_USB_GLOB_GHWCFG4_t ghwcfg4; /* ALT_USB_GLOB_GHWCFG4 */
13862  volatile uint32_t _pad_0x54_0x5b[2]; /* *UNDEFINED* */
13863  ALT_USB_GLOB_GDFIFOCFG_t gdfifocfg; /* ALT_USB_GLOB_GDFIFOCFG */
13864  volatile uint32_t _pad_0x60_0xff[40]; /* *UNDEFINED* */
13865  ALT_USB_GLOB_HPTXFSIZ_t hptxfsiz; /* ALT_USB_GLOB_HPTXFSIZ */
13866  ALT_USB_GLOB_DIEPTXF1_t dieptxf1; /* ALT_USB_GLOB_DIEPTXF1 */
13867  ALT_USB_GLOB_DIEPTXF2_t dieptxf2; /* ALT_USB_GLOB_DIEPTXF2 */
13868  ALT_USB_GLOB_DIEPTXF3_t dieptxf3; /* ALT_USB_GLOB_DIEPTXF3 */
13869  ALT_USB_GLOB_DIEPTXF4_t dieptxf4; /* ALT_USB_GLOB_DIEPTXF4 */
13870  ALT_USB_GLOB_DIEPTXF5_t dieptxf5; /* ALT_USB_GLOB_DIEPTXF5 */
13871  ALT_USB_GLOB_DIEPTXF6_t dieptxf6; /* ALT_USB_GLOB_DIEPTXF6 */
13872  ALT_USB_GLOB_DIEPTXF7_t dieptxf7; /* ALT_USB_GLOB_DIEPTXF7 */
13873  ALT_USB_GLOB_DIEPTXF8_t dieptxf8; /* ALT_USB_GLOB_DIEPTXF8 */
13874  ALT_USB_GLOB_DIEPTXF9_t dieptxf9; /* ALT_USB_GLOB_DIEPTXF9 */
13875  ALT_USB_GLOB_DIEPTXF10_t dieptxf10; /* ALT_USB_GLOB_DIEPTXF10 */
13876  ALT_USB_GLOB_DIEPTXF11_t dieptxf11; /* ALT_USB_GLOB_DIEPTXF11 */
13877  ALT_USB_GLOB_DIEPTXF12_t dieptxf12; /* ALT_USB_GLOB_DIEPTXF12 */
13878  ALT_USB_GLOB_DIEPTXF13_t dieptxf13; /* ALT_USB_GLOB_DIEPTXF13 */
13879  ALT_USB_GLOB_DIEPTXF14_t dieptxf14; /* ALT_USB_GLOB_DIEPTXF14 */
13880  ALT_USB_GLOB_DIEPTXF15_t dieptxf15; /* ALT_USB_GLOB_DIEPTXF15 */
13881 };
13882 
13883 /* The typedef declaration for register group ALT_USB_GLOB. */
13884 typedef volatile struct ALT_USB_GLOB_s ALT_USB_GLOB_t;
13885 /* The struct declaration for the raw register contents of register group ALT_USB_GLOB. */
13886 struct ALT_USB_GLOB_raw_s
13887 {
13888  volatile uint32_t gotgctl; /* ALT_USB_GLOB_GOTGCTL */
13889  volatile uint32_t gotgint; /* ALT_USB_GLOB_GOTGINT */
13890  volatile uint32_t gahbcfg; /* ALT_USB_GLOB_GAHBCFG */
13891  volatile uint32_t gusbcfg; /* ALT_USB_GLOB_GUSBCFG */
13892  volatile uint32_t grstctl; /* ALT_USB_GLOB_GRSTCTL */
13893  volatile uint32_t gintsts; /* ALT_USB_GLOB_GINTSTS */
13894  volatile uint32_t gintmsk; /* ALT_USB_GLOB_GINTMSK */
13895  volatile uint32_t grxstsr; /* ALT_USB_GLOB_GRXSTSR */
13896  volatile uint32_t grxstsp; /* ALT_USB_GLOB_GRXSTSP */
13897  volatile uint32_t grxfsiz; /* ALT_USB_GLOB_GRXFSIZ */
13898  volatile uint32_t gnptxfsiz; /* ALT_USB_GLOB_GNPTXFSIZ */
13899  volatile uint32_t gnptxsts; /* ALT_USB_GLOB_GNPTXSTS */
13900  uint32_t _pad_0x30_0x33; /* *UNDEFINED* */
13901  volatile uint32_t gpvndctl; /* ALT_USB_GLOB_GPVNDCTL */
13902  volatile uint32_t ggpio; /* ALT_USB_GLOB_GGPIO */
13903  volatile uint32_t guid; /* ALT_USB_GLOB_GUID */
13904  volatile uint32_t gsnpsid; /* ALT_USB_GLOB_GSNPSID */
13905  volatile uint32_t ghwcfg1; /* ALT_USB_GLOB_GHWCFG1 */
13906  volatile uint32_t ghwcfg2; /* ALT_USB_GLOB_GHWCFG2 */
13907  volatile uint32_t ghwcfg3; /* ALT_USB_GLOB_GHWCFG3 */
13908  volatile uint32_t ghwcfg4; /* ALT_USB_GLOB_GHWCFG4 */
13909  uint32_t _pad_0x54_0x5b[2]; /* *UNDEFINED* */
13910  volatile uint32_t gdfifocfg; /* ALT_USB_GLOB_GDFIFOCFG */
13911  uint32_t _pad_0x60_0xff[40]; /* *UNDEFINED* */
13912  volatile uint32_t hptxfsiz; /* ALT_USB_GLOB_HPTXFSIZ */
13913  volatile uint32_t dieptxf1; /* ALT_USB_GLOB_DIEPTXF1 */
13914  volatile uint32_t dieptxf2; /* ALT_USB_GLOB_DIEPTXF2 */
13915  volatile uint32_t dieptxf3; /* ALT_USB_GLOB_DIEPTXF3 */
13916  volatile uint32_t dieptxf4; /* ALT_USB_GLOB_DIEPTXF4 */
13917  volatile uint32_t dieptxf5; /* ALT_USB_GLOB_DIEPTXF5 */
13918  volatile uint32_t dieptxf6; /* ALT_USB_GLOB_DIEPTXF6 */
13919  volatile uint32_t dieptxf7; /* ALT_USB_GLOB_DIEPTXF7 */
13920  volatile uint32_t dieptxf8; /* ALT_USB_GLOB_DIEPTXF8 */
13921  volatile uint32_t dieptxf9; /* ALT_USB_GLOB_DIEPTXF9 */
13922  volatile uint32_t dieptxf10; /* ALT_USB_GLOB_DIEPTXF10 */
13923  volatile uint32_t dieptxf11; /* ALT_USB_GLOB_DIEPTXF11 */
13924  volatile uint32_t dieptxf12; /* ALT_USB_GLOB_DIEPTXF12 */
13925  volatile uint32_t dieptxf13; /* ALT_USB_GLOB_DIEPTXF13 */
13926  volatile uint32_t dieptxf14; /* ALT_USB_GLOB_DIEPTXF14 */
13927  volatile uint32_t dieptxf15; /* ALT_USB_GLOB_DIEPTXF15 */
13928 };
13929 
13930 /* The typedef declaration for the raw register contents of register group ALT_USB_GLOB. */
13931 typedef volatile struct ALT_USB_GLOB_raw_s ALT_USB_GLOB_raw_t;
13932 #endif /* __ASSEMBLY__ */
13933 
13934 
13935 /*
13936  * Component : ALT_USB_HOST
13937  *
13938  */
13939 /*
13940  * Register : hcfg
13941  *
13942  * Host Configuration Register
13943  *
13944  * Register Layout
13945  *
13946  * Bits | Access | Reset | Description
13947  * :--------|:-------|:------|:------------------------------
13948  * [1:0] | RW | 0x0 | ALT_USB_HOST_HCFG_FSLSPCLKSEL
13949  * [2] | RW | 0x0 | ALT_USB_HOST_HCFG_FSLSSUPP
13950  * [6:3] | ??? | 0x0 | *UNDEFINED*
13951  * [7] | RW | 0x0 | ALT_USB_HOST_HCFG_ENA32KHZS
13952  * [15:8] | RW | 0x2 | ALT_USB_HOST_HCFG_RESVALID
13953  * [22:16] | ??? | 0x0 | *UNDEFINED*
13954  * [23] | RW | 0x0 | ALT_USB_HOST_HCFG_DESCDMA
13955  * [25:24] | RW | 0x0 | ALT_USB_HOST_HCFG_FRLISTEN
13956  * [26] | RW | 0x0 | ALT_USB_HOST_HCFG_PERSCHEDENA
13957  * [30:27] | ??? | 0x0 | *UNDEFINED*
13958  * [31] | RW | 0x0 | ALT_USB_HOST_HCFG_MODCHTIMEN
13959  *
13960  */
13961 /*
13962  * Field : fslspclksel
13963  *
13964  * FS/LS PHY Clock Select (FSLSPclkSel)
13965  *
13966  * When the core is in FS Host mode
13967  *
13968  * 2'b00: PHY clock is running at 30/60 MHz
13969  *
13970  * 2'b01: PHY clock is running at 48 MHz
13971  *
13972  * Others: Reserved
13973  *
13974  * When the core is in LS Host mode
13975  *
13976  * 2'b00: PHY clock is running at 30/60 MHz. When the
13977  *
13978  * UTMI+/ULPI PHY Low Power mode is not selected, use
13979  *
13980  * 30/60 MHz.
13981  *
13982  * 2'b01: PHY clock is running at 48 MHz. When the UTMI+
13983  *
13984  * PHY Low Power mode is selected, use 48MHz If the PHY
13985  *
13986  * supplies a 48 MHz clock during LS mode.
13987  *
13988  * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
13989  *
13990  * use 6 MHz when the UTMI+ PHY Low Power mode is
13991  *
13992  * selected and the PHY supplies a 6 MHz clock during LS
13993  *
13994  * mode. If you select a 6 MHz clock during LS mode, you must
13995  *
13996  * do a soft reset.
13997  *
13998  * 2'b11: Reserved
13999  *
14000  * Notes:
14001  *
14002  * When Core in FS mode, the internal and external clocks have the same frequency.
14003  *
14004  * When Core in LS mode,
14005  *
14006  * * If FSLSPclkSel = 2'b00: Internal and external clocks have the same frequency
14007  *
14008  * * If FSLSPclkSel = 2'b10: Internal clock is the divided by eight version of
14009  * external 48 MHz clock
14010  *
14011  * Field Enumeration Values:
14012  *
14013  * Enum | Value | Description
14014  * :----------------------------------------|:------|:----------------------------------
14015  * ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK3060 | 0x0 | PHY clock is running at 30/60 MHz
14016  * ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK48 | 0x1 | PHY clock is running at 48 MHz
14017  * ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK6 | 0x2 | PHY clock is running at 6 MHz
14018  *
14019  * Field Access Macros:
14020  *
14021  */
14022 /*
14023  * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSPCLKSEL
14024  *
14025  * PHY clock is running at 30/60 MHz
14026  */
14027 #define ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK3060 0x0
14028 /*
14029  * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSPCLKSEL
14030  *
14031  * PHY clock is running at 48 MHz
14032  */
14033 #define ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK48 0x1
14034 /*
14035  * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSPCLKSEL
14036  *
14037  * PHY clock is running at 6 MHz
14038  */
14039 #define ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK6 0x2
14040 
14041 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */
14042 #define ALT_USB_HOST_HCFG_FSLSPCLKSEL_LSB 0
14043 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */
14044 #define ALT_USB_HOST_HCFG_FSLSPCLKSEL_MSB 1
14045 /* The width in bits of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */
14046 #define ALT_USB_HOST_HCFG_FSLSPCLKSEL_WIDTH 2
14047 /* The mask used to set the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field value. */
14048 #define ALT_USB_HOST_HCFG_FSLSPCLKSEL_SET_MSK 0x00000003
14049 /* The mask used to clear the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field value. */
14050 #define ALT_USB_HOST_HCFG_FSLSPCLKSEL_CLR_MSK 0xfffffffc
14051 /* The reset value of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */
14052 #define ALT_USB_HOST_HCFG_FSLSPCLKSEL_RESET 0x0
14053 /* Extracts the ALT_USB_HOST_HCFG_FSLSPCLKSEL field value from a register. */
14054 #define ALT_USB_HOST_HCFG_FSLSPCLKSEL_GET(value) (((value) & 0x00000003) >> 0)
14055 /* Produces a ALT_USB_HOST_HCFG_FSLSPCLKSEL register field value suitable for setting the register. */
14056 #define ALT_USB_HOST_HCFG_FSLSPCLKSEL_SET(value) (((value) << 0) & 0x00000003)
14057 
14058 /*
14059  * Field : fslssupp
14060  *
14061  * FS- and LS-Only Support (FSLSSupp)
14062  *
14063  * The application uses this bit to control the core's enumeration
14064  *
14065  * speed. Using this bit, the application can make the core
14066  *
14067  * enumerate as a FS host, even If the connected device supports
14068  *
14069  * HS traffic. Do not make changes to this field after initial
14070  *
14071  * programming.
14072  *
14073  * 1'b0: HS/FS/LS, based on the maximum speed supported by
14074  *
14075  * the connected device
14076  *
14077  * 1'b1: FS/LS-only, even If the connected device can support
14078  *
14079  * HS
14080  *
14081  * Field Enumeration Values:
14082  *
14083  * Enum | Value | Description
14084  * :------------------------------------|:------|:-----------------------------------------------
14085  * ALT_USB_HOST_HCFG_FSLSSUPP_E_HSFSLS | 0x0 | HS/FS/LS, based on the maximum speed supported
14086  * : | | by the connected device
14087  * ALT_USB_HOST_HCFG_FSLSSUPP_E_FSLS | 0x1 | FS/LS-only, even if the connected device can
14088  * : | | support HS
14089  *
14090  * Field Access Macros:
14091  *
14092  */
14093 /*
14094  * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSSUPP
14095  *
14096  * HS/FS/LS, based on the maximum speed supported by the connected device
14097  */
14098 #define ALT_USB_HOST_HCFG_FSLSSUPP_E_HSFSLS 0x0
14099 /*
14100  * Enumerated value for register field ALT_USB_HOST_HCFG_FSLSSUPP
14101  *
14102  * FS/LS-only, even if the connected device can support HS
14103  */
14104 #define ALT_USB_HOST_HCFG_FSLSSUPP_E_FSLS 0x1
14105 
14106 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */
14107 #define ALT_USB_HOST_HCFG_FSLSSUPP_LSB 2
14108 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */
14109 #define ALT_USB_HOST_HCFG_FSLSSUPP_MSB 2
14110 /* The width in bits of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */
14111 #define ALT_USB_HOST_HCFG_FSLSSUPP_WIDTH 1
14112 /* The mask used to set the ALT_USB_HOST_HCFG_FSLSSUPP register field value. */
14113 #define ALT_USB_HOST_HCFG_FSLSSUPP_SET_MSK 0x00000004
14114 /* The mask used to clear the ALT_USB_HOST_HCFG_FSLSSUPP register field value. */
14115 #define ALT_USB_HOST_HCFG_FSLSSUPP_CLR_MSK 0xfffffffb
14116 /* The reset value of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */
14117 #define ALT_USB_HOST_HCFG_FSLSSUPP_RESET 0x0
14118 /* Extracts the ALT_USB_HOST_HCFG_FSLSSUPP field value from a register. */
14119 #define ALT_USB_HOST_HCFG_FSLSSUPP_GET(value) (((value) & 0x00000004) >> 2)
14120 /* Produces a ALT_USB_HOST_HCFG_FSLSSUPP register field value suitable for setting the register. */
14121 #define ALT_USB_HOST_HCFG_FSLSSUPP_SET(value) (((value) << 2) & 0x00000004)
14122 
14123 /*
14124  * Field : ena32khzs
14125  *
14126  * Enable 32 KHz Suspend mode (Ena32KHzS)
14127  *
14128  * This bit can be set only in FS PHY interface is selected.
14129  *
14130  * Else, this bit needs to be set to zero.
14131  *
14132  * When FS PHY interface is chosen and this bit is set,
14133  *
14134  * the core expects that the PHY clock during Suspend is switched
14135  *
14136  * from 48 MHz to 32 KHz.
14137  *
14138  * Field Enumeration Values:
14139  *
14140  * Enum | Value | Description
14141  * :-----------------------------------|:------|:------------------------------------------------
14142  * ALT_USB_HOST_HCFG_ENA32KHZS_E_DISD | 0x0 | USB 1.1 Full-Speed Not Selected
14143  * ALT_USB_HOST_HCFG_ENA32KHZS_E_END | 0x1 | USB 1.1 Full-Speed Serial Transceiver Interface
14144  * : | | selected
14145  *
14146  * Field Access Macros:
14147  *
14148  */
14149 /*
14150  * Enumerated value for register field ALT_USB_HOST_HCFG_ENA32KHZS
14151  *
14152  * USB 1.1 Full-Speed Not Selected
14153  */
14154 #define ALT_USB_HOST_HCFG_ENA32KHZS_E_DISD 0x0
14155 /*
14156  * Enumerated value for register field ALT_USB_HOST_HCFG_ENA32KHZS
14157  *
14158  * USB 1.1 Full-Speed Serial Transceiver Interface selected
14159  */
14160 #define ALT_USB_HOST_HCFG_ENA32KHZS_E_END 0x1
14161 
14162 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */
14163 #define ALT_USB_HOST_HCFG_ENA32KHZS_LSB 7
14164 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */
14165 #define ALT_USB_HOST_HCFG_ENA32KHZS_MSB 7
14166 /* The width in bits of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */
14167 #define ALT_USB_HOST_HCFG_ENA32KHZS_WIDTH 1
14168 /* The mask used to set the ALT_USB_HOST_HCFG_ENA32KHZS register field value. */
14169 #define ALT_USB_HOST_HCFG_ENA32KHZS_SET_MSK 0x00000080
14170 /* The mask used to clear the ALT_USB_HOST_HCFG_ENA32KHZS register field value. */
14171 #define ALT_USB_HOST_HCFG_ENA32KHZS_CLR_MSK 0xffffff7f
14172 /* The reset value of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */
14173 #define ALT_USB_HOST_HCFG_ENA32KHZS_RESET 0x0
14174 /* Extracts the ALT_USB_HOST_HCFG_ENA32KHZS field value from a register. */
14175 #define ALT_USB_HOST_HCFG_ENA32KHZS_GET(value) (((value) & 0x00000080) >> 7)
14176 /* Produces a ALT_USB_HOST_HCFG_ENA32KHZS register field value suitable for setting the register. */
14177 #define ALT_USB_HOST_HCFG_ENA32KHZS_SET(value) (((value) << 7) & 0x00000080)
14178 
14179 /*
14180  * Field : resvalid
14181  *
14182  * Resume Validation Period (ResValid)
14183  *
14184  * This field is effective only when HCFG.Ena32KHzS is set.
14185  *
14186  * It will control the resume period when the core resumes from suspend.
14187  *
14188  * The core counts for 'ResValid' number of clock cycles to detect a
14189  *
14190  * valid resume when this is set.
14191  *
14192  * Field Access Macros:
14193  *
14194  */
14195 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_RESVALID register field. */
14196 #define ALT_USB_HOST_HCFG_RESVALID_LSB 8
14197 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_RESVALID register field. */
14198 #define ALT_USB_HOST_HCFG_RESVALID_MSB 15
14199 /* The width in bits of the ALT_USB_HOST_HCFG_RESVALID register field. */
14200 #define ALT_USB_HOST_HCFG_RESVALID_WIDTH 8
14201 /* The mask used to set the ALT_USB_HOST_HCFG_RESVALID register field value. */
14202 #define ALT_USB_HOST_HCFG_RESVALID_SET_MSK 0x0000ff00
14203 /* The mask used to clear the ALT_USB_HOST_HCFG_RESVALID register field value. */
14204 #define ALT_USB_HOST_HCFG_RESVALID_CLR_MSK 0xffff00ff
14205 /* The reset value of the ALT_USB_HOST_HCFG_RESVALID register field. */
14206 #define ALT_USB_HOST_HCFG_RESVALID_RESET 0x2
14207 /* Extracts the ALT_USB_HOST_HCFG_RESVALID field value from a register. */
14208 #define ALT_USB_HOST_HCFG_RESVALID_GET(value) (((value) & 0x0000ff00) >> 8)
14209 /* Produces a ALT_USB_HOST_HCFG_RESVALID register field value suitable for setting the register. */
14210 #define ALT_USB_HOST_HCFG_RESVALID_SET(value) (((value) << 8) & 0x0000ff00)
14211 
14212 /*
14213  * Field : descdma
14214  *
14215  * Enable Scatter/gather DMA in Host mode (DescDMA).
14216  *
14217  * When the Scatter/Gather DMA option selected during configuration
14218  *
14219  * of the RTL, the application can set this bit during initialization
14220  *
14221  * to enable the Scatter/Gather DMA operation.
14222  *
14223  * NOTE: This bit must be modified only once after a reset.
14224  *
14225  * \The following combinations are available for programming:
14226  *
14227  * GAHBCFG.DMAEn=0,HCFG.DescDMA=0 => Slave mode
14228  *
14229  * GAHBCFG.DMAEn=0,HCFG.DescDMA=1 => Invalid
14230  *
14231  * GAHBCFG.DMAEn=1,HCFG.DescDMA=0 => Buffered DMA mode
14232  *
14233  * GAHBCFG.DMAEn=1,HCFG.DescDMA=1 => Scatter/Gather DMA mode
14234  *
14235  * Field Enumeration Values:
14236  *
14237  * Enum | Value | Description
14238  * :---------------------------------|:------|:----------------------------
14239  * ALT_USB_HOST_HCFG_DESCDMA_E_DISD | 0x0 | No Scatter/Gather DMA
14240  * ALT_USB_HOST_HCFG_DESCDMA_E_END | 0x1 | Scatter/Gather DMA selected
14241  *
14242  * Field Access Macros:
14243  *
14244  */
14245 /*
14246  * Enumerated value for register field ALT_USB_HOST_HCFG_DESCDMA
14247  *
14248  * No Scatter/Gather DMA
14249  */
14250 #define ALT_USB_HOST_HCFG_DESCDMA_E_DISD 0x0
14251 /*
14252  * Enumerated value for register field ALT_USB_HOST_HCFG_DESCDMA
14253  *
14254  * Scatter/Gather DMA selected
14255  */
14256 #define ALT_USB_HOST_HCFG_DESCDMA_E_END 0x1
14257 
14258 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_DESCDMA register field. */
14259 #define ALT_USB_HOST_HCFG_DESCDMA_LSB 23
14260 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_DESCDMA register field. */
14261 #define ALT_USB_HOST_HCFG_DESCDMA_MSB 23
14262 /* The width in bits of the ALT_USB_HOST_HCFG_DESCDMA register field. */
14263 #define ALT_USB_HOST_HCFG_DESCDMA_WIDTH 1
14264 /* The mask used to set the ALT_USB_HOST_HCFG_DESCDMA register field value. */
14265 #define ALT_USB_HOST_HCFG_DESCDMA_SET_MSK 0x00800000
14266 /* The mask used to clear the ALT_USB_HOST_HCFG_DESCDMA register field value. */
14267 #define ALT_USB_HOST_HCFG_DESCDMA_CLR_MSK 0xff7fffff
14268 /* The reset value of the ALT_USB_HOST_HCFG_DESCDMA register field. */
14269 #define ALT_USB_HOST_HCFG_DESCDMA_RESET 0x0
14270 /* Extracts the ALT_USB_HOST_HCFG_DESCDMA field value from a register. */
14271 #define ALT_USB_HOST_HCFG_DESCDMA_GET(value) (((value) & 0x00800000) >> 23)
14272 /* Produces a ALT_USB_HOST_HCFG_DESCDMA register field value suitable for setting the register. */
14273 #define ALT_USB_HOST_HCFG_DESCDMA_SET(value) (((value) << 23) & 0x00800000)
14274 
14275 /*
14276  * Field : frlisten
14277  *
14278  * Frame List Entries(FrListEn). The value in the register specifies the number
14279  *
14280  * of entries in the Frame list.
14281  *
14282  * This field is valid only in Scatter/Gather DMA mode.
14283  *
14284  * 2'b00: 8 Entries
14285  *
14286  * 2'b01: 16 Entries
14287  *
14288  * 2'b10: 32 Entries
14289  *
14290  * 2'b11: 63 Entries
14291  *
14292  * Field Enumeration Values:
14293  *
14294  * Enum | Value | Description
14295  * :-------------------------------------|:------|:------------
14296  * ALT_USB_HOST_HCFG_FRLISTEN_E_RSVD | 0x0 | Reserved
14297  * ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY8 | 0x1 | 8 Entries
14298  * ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY16 | 0x2 | 16 Entries
14299  * ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY32 | 0x3 | 32 Entries
14300  *
14301  * Field Access Macros:
14302  *
14303  */
14304 /*
14305  * Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN
14306  *
14307  * Reserved
14308  */
14309 #define ALT_USB_HOST_HCFG_FRLISTEN_E_RSVD 0x0
14310 /*
14311  * Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN
14312  *
14313  * 8 Entries
14314  */
14315 #define ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY8 0x1
14316 /*
14317  * Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN
14318  *
14319  * 16 Entries
14320  */
14321 #define ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY16 0x2
14322 /*
14323  * Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN
14324  *
14325  * 32 Entries
14326  */
14327 #define ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY32 0x3
14328 
14329 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_FRLISTEN register field. */
14330 #define ALT_USB_HOST_HCFG_FRLISTEN_LSB 24
14331 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_FRLISTEN register field. */
14332 #define ALT_USB_HOST_HCFG_FRLISTEN_MSB 25
14333 /* The width in bits of the ALT_USB_HOST_HCFG_FRLISTEN register field. */
14334 #define ALT_USB_HOST_HCFG_FRLISTEN_WIDTH 2
14335 /* The mask used to set the ALT_USB_HOST_HCFG_FRLISTEN register field value. */
14336 #define ALT_USB_HOST_HCFG_FRLISTEN_SET_MSK 0x03000000
14337 /* The mask used to clear the ALT_USB_HOST_HCFG_FRLISTEN register field value. */
14338 #define ALT_USB_HOST_HCFG_FRLISTEN_CLR_MSK 0xfcffffff
14339 /* The reset value of the ALT_USB_HOST_HCFG_FRLISTEN register field. */
14340 #define ALT_USB_HOST_HCFG_FRLISTEN_RESET 0x0
14341 /* Extracts the ALT_USB_HOST_HCFG_FRLISTEN field value from a register. */
14342 #define ALT_USB_HOST_HCFG_FRLISTEN_GET(value) (((value) & 0x03000000) >> 24)
14343 /* Produces a ALT_USB_HOST_HCFG_FRLISTEN register field value suitable for setting the register. */
14344 #define ALT_USB_HOST_HCFG_FRLISTEN_SET(value) (((value) << 24) & 0x03000000)
14345 
14346 /*
14347  * Field : perschedena
14348  *
14349  * Enable Periodic Scheduling (PerSchedEna):
14350  *
14351  * Applicable in host DDMA mode only.
14352  *
14353  * Enables periodic scheduling within the core. Initially, the bit is reset.
14354  *
14355  * The core will not process any periodic channels. As soon as this bit is set,
14356  *
14357  * the core will get ready to start scheduling periodic channels and
14358  *
14359  * sets HCFG.PerSchedStat. The setting of HCFG.PerSchedStat indicates the core
14360  *
14361  * has enabled periodic scheduling. Once HCFG.PerSchedEna is set,
14362  *
14363  * the application is not supposed to again reset the bit unless HCFG.PerSchedStat
14364  *
14365  * is set. As soon as this bit is reset, the core will get ready to
14366  *
14367  * stop scheduling periodic channels and resets HCFG.PerSchedStat.
14368  *
14369  * Field Enumeration Values:
14370  *
14371  * Enum | Value | Description
14372  * :-------------------------------------|:------|:---------------------------------------------
14373  * ALT_USB_HOST_HCFG_PERSCHEDENA_E_DISD | 0x0 | Disables periodic scheduling within the core
14374  * ALT_USB_HOST_HCFG_PERSCHEDENA_E_END | 0x1 | Enables periodic scheduling within the core
14375  *
14376  * Field Access Macros:
14377  *
14378  */
14379 /*
14380  * Enumerated value for register field ALT_USB_HOST_HCFG_PERSCHEDENA
14381  *
14382  * Disables periodic scheduling within the core
14383  */
14384 #define ALT_USB_HOST_HCFG_PERSCHEDENA_E_DISD 0x0
14385 /*
14386  * Enumerated value for register field ALT_USB_HOST_HCFG_PERSCHEDENA
14387  *
14388  * Enables periodic scheduling within the core
14389  */
14390 #define ALT_USB_HOST_HCFG_PERSCHEDENA_E_END 0x1
14391 
14392 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */
14393 #define ALT_USB_HOST_HCFG_PERSCHEDENA_LSB 26
14394 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */
14395 #define ALT_USB_HOST_HCFG_PERSCHEDENA_MSB 26
14396 /* The width in bits of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */
14397 #define ALT_USB_HOST_HCFG_PERSCHEDENA_WIDTH 1
14398 /* The mask used to set the ALT_USB_HOST_HCFG_PERSCHEDENA register field value. */
14399 #define ALT_USB_HOST_HCFG_PERSCHEDENA_SET_MSK 0x04000000
14400 /* The mask used to clear the ALT_USB_HOST_HCFG_PERSCHEDENA register field value. */
14401 #define ALT_USB_HOST_HCFG_PERSCHEDENA_CLR_MSK 0xfbffffff
14402 /* The reset value of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */
14403 #define ALT_USB_HOST_HCFG_PERSCHEDENA_RESET 0x0
14404 /* Extracts the ALT_USB_HOST_HCFG_PERSCHEDENA field value from a register. */
14405 #define ALT_USB_HOST_HCFG_PERSCHEDENA_GET(value) (((value) & 0x04000000) >> 26)
14406 /* Produces a ALT_USB_HOST_HCFG_PERSCHEDENA register field value suitable for setting the register. */
14407 #define ALT_USB_HOST_HCFG_PERSCHEDENA_SET(value) (((value) << 26) & 0x04000000)
14408 
14409 /*
14410  * Field : modechtimen
14411  *
14412  * Mode Change Ready Timer Enable (ModeChTimEn)
14413  *
14414  * This bit is used to enable/disable the Host core
14415  *
14416  * to wait 200 PHY clock cycles at the end of Resumeto change the opmode signal to
14417  * the PHY to 00
14418  *
14419  * after Suspend or LPM.
14420  *
14421  * 1'b0 : The Host core waits for either 200 PHY clock cycles or a linestate
14422  *
14423  * of SE0 at the end of resume to the change the opmode from 2'b10 to 2'b00
14424  *
14425  * 1'b1 : The Host core waits only for a linstate of SE0 at the end of resume
14426  *
14427  * to change the opmode from 2'b10 to 2'b00.
14428  *
14429  * Field Enumeration Values:
14430  *
14431  * Enum | Value | Description
14432  * :------------------------------------|:------|:------------------------------------------------
14433  * ALT_USB_HOST_HCFG_MODCHTIMEN_E_END | 0x0 | The Host core waits for either 200 PHY clock
14434  * : | | cycles or a linestate of SE0 at the end of
14435  * : | | resume to change the opmode from 0x2 to 0x0
14436  * ALT_USB_HOST_HCFG_MODCHTIMEN_E_DISD | 0x1 | The Host core waits only for a linestate of SE0
14437  * : | | at the end of resume to change the opmode from
14438  * : | | 0x2 to 0x0
14439  *
14440  * Field Access Macros:
14441  *
14442  */
14443 /*
14444  * Enumerated value for register field ALT_USB_HOST_HCFG_MODCHTIMEN
14445  *
14446  * The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the
14447  * end of resume to change the opmode from 0x2 to 0x0
14448  */
14449 #define ALT_USB_HOST_HCFG_MODCHTIMEN_E_END 0x0
14450 /*
14451  * Enumerated value for register field ALT_USB_HOST_HCFG_MODCHTIMEN
14452  *
14453  * The Host core waits only for a linestate of SE0 at the end of resume to change
14454  * the opmode from 0x2 to 0x0
14455  */
14456 #define ALT_USB_HOST_HCFG_MODCHTIMEN_E_DISD 0x1
14457 
14458 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */
14459 #define ALT_USB_HOST_HCFG_MODCHTIMEN_LSB 31
14460 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */
14461 #define ALT_USB_HOST_HCFG_MODCHTIMEN_MSB 31
14462 /* The width in bits of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */
14463 #define ALT_USB_HOST_HCFG_MODCHTIMEN_WIDTH 1
14464 /* The mask used to set the ALT_USB_HOST_HCFG_MODCHTIMEN register field value. */
14465 #define ALT_USB_HOST_HCFG_MODCHTIMEN_SET_MSK 0x80000000
14466 /* The mask used to clear the ALT_USB_HOST_HCFG_MODCHTIMEN register field value. */
14467 #define ALT_USB_HOST_HCFG_MODCHTIMEN_CLR_MSK 0x7fffffff
14468 /* The reset value of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */
14469 #define ALT_USB_HOST_HCFG_MODCHTIMEN_RESET 0x0
14470 /* Extracts the ALT_USB_HOST_HCFG_MODCHTIMEN field value from a register. */
14471 #define ALT_USB_HOST_HCFG_MODCHTIMEN_GET(value) (((value) & 0x80000000) >> 31)
14472 /* Produces a ALT_USB_HOST_HCFG_MODCHTIMEN register field value suitable for setting the register. */
14473 #define ALT_USB_HOST_HCFG_MODCHTIMEN_SET(value) (((value) << 31) & 0x80000000)
14474 
14475 #ifndef __ASSEMBLY__
14476 /*
14477  * WARNING: The C register and register group struct declarations are provided for
14478  * convenience and illustrative purposes. They should, however, be used with
14479  * caution as the C language standard provides no guarantees about the alignment or
14480  * atomicity of device memory accesses. The recommended practice for writing
14481  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14482  * alt_write_word() functions.
14483  *
14484  * The struct declaration for register ALT_USB_HOST_HCFG.
14485  */
14486 struct ALT_USB_HOST_HCFG_s
14487 {
14488  uint32_t fslspclksel : 2; /* ALT_USB_HOST_HCFG_FSLSPCLKSEL */
14489  uint32_t fslssupp : 1; /* ALT_USB_HOST_HCFG_FSLSSUPP */
14490  uint32_t : 4; /* *UNDEFINED* */
14491  uint32_t ena32khzs : 1; /* ALT_USB_HOST_HCFG_ENA32KHZS */
14492  uint32_t resvalid : 8; /* ALT_USB_HOST_HCFG_RESVALID */
14493  uint32_t : 7; /* *UNDEFINED* */
14494  uint32_t descdma : 1; /* ALT_USB_HOST_HCFG_DESCDMA */
14495  uint32_t frlisten : 2; /* ALT_USB_HOST_HCFG_FRLISTEN */
14496  uint32_t perschedena : 1; /* ALT_USB_HOST_HCFG_PERSCHEDENA */
14497  uint32_t : 4; /* *UNDEFINED* */
14498  uint32_t modechtimen : 1; /* ALT_USB_HOST_HCFG_MODCHTIMEN */
14499 };
14500 
14501 /* The typedef declaration for register ALT_USB_HOST_HCFG. */
14502 typedef volatile struct ALT_USB_HOST_HCFG_s ALT_USB_HOST_HCFG_t;
14503 #endif /* __ASSEMBLY__ */
14504 
14505 /* The reset value of the ALT_USB_HOST_HCFG register. */
14506 #define ALT_USB_HOST_HCFG_RESET 0x00000200
14507 /* The byte offset of the ALT_USB_HOST_HCFG register from the beginning of the component. */
14508 #define ALT_USB_HOST_HCFG_OFST 0x0
14509 /* The address of the ALT_USB_HOST_HCFG register. */
14510 #define ALT_USB_HOST_HCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCFG_OFST))
14511 
14512 /*
14513  * Register : hfir
14514  *
14515  * Host Frame Interval Register
14516  *
14517  * Register Layout
14518  *
14519  * Bits | Access | Reset | Description
14520  * :--------|:-------|:-------|:-----------------------------
14521  * [15:0] | RW | 0xea60 | ALT_USB_HOST_HFIR_FRINT
14522  * [16] | RW | 0x0 | ALT_USB_HOST_HFIR_HFIRRLDCTL
14523  * [31:17] | ??? | 0x0 | *UNDEFINED*
14524  *
14525  */
14526 /*
14527  * Field : frint
14528  *
14529  * Frame Interval (FrInt)
14530  *
14531  * The value that the application programs to this field specifies
14532  *
14533  * the interval between two consecutive SOFs (FS) or micro-
14534  *
14535  * SOFs (HS) or Keep-Alive tokens (HS). This field contains the
14536  *
14537  * number of PHY clocks that constitute the required frame
14538  *
14539  * interval. The Default value Set in this field For a FS operation
14540  *
14541  * when the PHY clock frequency is 60 MHz. The application can
14542  *
14543  * write a value to this register only after the Port Enable bit of the
14544  *
14545  * Host Port Control and Status register (HPRT.PrtEnaPort) has
14546  *
14547  * been Set. If no value is programmed, the core calculates the
14548  *
14549  * value based on the PHY clock specified in the FS/LS PHY
14550  *
14551  * Clock Select field of the Host Configuration register
14552  *
14553  * (HCFG.FSLSPclkSel). Do not change the value of this field
14554  *
14555  * after the initial configuration.
14556  *
14557  * 125 s * (PHY clock frequency For HS)
14558  *
14559  * 1 ms * (PHY clock frequency For FS/LS)
14560  *
14561  * Field Access Macros:
14562  *
14563  */
14564 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFIR_FRINT register field. */
14565 #define ALT_USB_HOST_HFIR_FRINT_LSB 0
14566 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFIR_FRINT register field. */
14567 #define ALT_USB_HOST_HFIR_FRINT_MSB 15
14568 /* The width in bits of the ALT_USB_HOST_HFIR_FRINT register field. */
14569 #define ALT_USB_HOST_HFIR_FRINT_WIDTH 16
14570 /* The mask used to set the ALT_USB_HOST_HFIR_FRINT register field value. */
14571 #define ALT_USB_HOST_HFIR_FRINT_SET_MSK 0x0000ffff
14572 /* The mask used to clear the ALT_USB_HOST_HFIR_FRINT register field value. */
14573 #define ALT_USB_HOST_HFIR_FRINT_CLR_MSK 0xffff0000
14574 /* The reset value of the ALT_USB_HOST_HFIR_FRINT register field. */
14575 #define ALT_USB_HOST_HFIR_FRINT_RESET 0xea60
14576 /* Extracts the ALT_USB_HOST_HFIR_FRINT field value from a register. */
14577 #define ALT_USB_HOST_HFIR_FRINT_GET(value) (((value) & 0x0000ffff) >> 0)
14578 /* Produces a ALT_USB_HOST_HFIR_FRINT register field value suitable for setting the register. */
14579 #define ALT_USB_HOST_HFIR_FRINT_SET(value) (((value) << 0) & 0x0000ffff)
14580 
14581 /*
14582  * Field : hfirrldctrl
14583  *
14584  * Reload Control (HFIRRldCtrl)
14585  *
14586  * This bit allows dynamic reloading of the HFIR register during run time.
14587  *
14588  * 1'b0 : The HFIR cannot be reloaded dynamically
14589  *
14590  * 1'b1: the HFIR can be dynamically reloaded during runtime.
14591  *
14592  * This bit needs to be programmed during initial configuration and its value
14593  * should not be changed during runtime.
14594  *
14595  * Field Enumeration Values:
14596  *
14597  * Enum | Value | Description
14598  * :------------------------------------|:------|:--------------------------------------------
14599  * ALT_USB_HOST_HFIR_HFIRRLDCTL_E_DISD | 0x0 | The HFIR cannot be reloaded dynamically
14600  * ALT_USB_HOST_HFIR_HFIRRLDCTL_E_END | 0x1 | The HFIR can be dynamically reloaded during
14601  * : | | runtime
14602  *
14603  * Field Access Macros:
14604  *
14605  */
14606 /*
14607  * Enumerated value for register field ALT_USB_HOST_HFIR_HFIRRLDCTL
14608  *
14609  * The HFIR cannot be reloaded dynamically
14610  */
14611 #define ALT_USB_HOST_HFIR_HFIRRLDCTL_E_DISD 0x0
14612 /*
14613  * Enumerated value for register field ALT_USB_HOST_HFIR_HFIRRLDCTL
14614  *
14615  * The HFIR can be dynamically reloaded during runtime
14616  */
14617 #define ALT_USB_HOST_HFIR_HFIRRLDCTL_E_END 0x1
14618 
14619 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */
14620 #define ALT_USB_HOST_HFIR_HFIRRLDCTL_LSB 16
14621 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */
14622 #define ALT_USB_HOST_HFIR_HFIRRLDCTL_MSB 16
14623 /* The width in bits of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */
14624 #define ALT_USB_HOST_HFIR_HFIRRLDCTL_WIDTH 1
14625 /* The mask used to set the ALT_USB_HOST_HFIR_HFIRRLDCTL register field value. */
14626 #define ALT_USB_HOST_HFIR_HFIRRLDCTL_SET_MSK 0x00010000
14627 /* The mask used to clear the ALT_USB_HOST_HFIR_HFIRRLDCTL register field value. */
14628 #define ALT_USB_HOST_HFIR_HFIRRLDCTL_CLR_MSK 0xfffeffff
14629 /* The reset value of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */
14630 #define ALT_USB_HOST_HFIR_HFIRRLDCTL_RESET 0x0
14631 /* Extracts the ALT_USB_HOST_HFIR_HFIRRLDCTL field value from a register. */
14632 #define ALT_USB_HOST_HFIR_HFIRRLDCTL_GET(value) (((value) & 0x00010000) >> 16)
14633 /* Produces a ALT_USB_HOST_HFIR_HFIRRLDCTL register field value suitable for setting the register. */
14634 #define ALT_USB_HOST_HFIR_HFIRRLDCTL_SET(value) (((value) << 16) & 0x00010000)
14635 
14636 #ifndef __ASSEMBLY__
14637 /*
14638  * WARNING: The C register and register group struct declarations are provided for
14639  * convenience and illustrative purposes. They should, however, be used with
14640  * caution as the C language standard provides no guarantees about the alignment or
14641  * atomicity of device memory accesses. The recommended practice for writing
14642  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14643  * alt_write_word() functions.
14644  *
14645  * The struct declaration for register ALT_USB_HOST_HFIR.
14646  */
14647 struct ALT_USB_HOST_HFIR_s
14648 {
14649  uint32_t frint : 16; /* ALT_USB_HOST_HFIR_FRINT */
14650  uint32_t hfirrldctrl : 1; /* ALT_USB_HOST_HFIR_HFIRRLDCTL */
14651  uint32_t : 15; /* *UNDEFINED* */
14652 };
14653 
14654 /* The typedef declaration for register ALT_USB_HOST_HFIR. */
14655 typedef volatile struct ALT_USB_HOST_HFIR_s ALT_USB_HOST_HFIR_t;
14656 #endif /* __ASSEMBLY__ */
14657 
14658 /* The reset value of the ALT_USB_HOST_HFIR register. */
14659 #define ALT_USB_HOST_HFIR_RESET 0x0000ea60
14660 /* The byte offset of the ALT_USB_HOST_HFIR register from the beginning of the component. */
14661 #define ALT_USB_HOST_HFIR_OFST 0x4
14662 /* The address of the ALT_USB_HOST_HFIR register. */
14663 #define ALT_USB_HOST_HFIR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HFIR_OFST))
14664 
14665 /*
14666  * Register : hfnum
14667  *
14668  * Host Frame Number/Frame Time Remaining Register
14669  *
14670  * Register Layout
14671  *
14672  * Bits | Access | Reset | Description
14673  * :--------|:-------|:-------|:-------------------------
14674  * [15:0] | R | 0x3fff | ALT_USB_HOST_HFNUM_FRNUM
14675  * [31:16] | R | 0x0 | ALT_USB_HOST_HFNUM_FRREM
14676  *
14677  */
14678 /*
14679  * Field : frnum
14680  *
14681  * Frame Number (FrNum)
14682  *
14683  * This field increments when a new SOF is transmitted on the
14684  *
14685  * USB, and is reset to 0 when it reaches 16'h3FFF.
14686  *
14687  * Field Enumeration Values:
14688  *
14689  * Enum | Value | Description
14690  * :---------------------------------|:------|:----------------------
14691  * ALT_USB_HOST_HFNUM_FRNUM_E_INACT | 0x0 | No SOF is transmitted
14692  * ALT_USB_HOST_HFNUM_FRNUM_E_ACT | 0x1 | SOF is transmitted
14693  *
14694  * Field Access Macros:
14695  *
14696  */
14697 /*
14698  * Enumerated value for register field ALT_USB_HOST_HFNUM_FRNUM
14699  *
14700  * No SOF is transmitted
14701  */
14702 #define ALT_USB_HOST_HFNUM_FRNUM_E_INACT 0x0
14703 /*
14704  * Enumerated value for register field ALT_USB_HOST_HFNUM_FRNUM
14705  *
14706  * SOF is transmitted
14707  */
14708 #define ALT_USB_HOST_HFNUM_FRNUM_E_ACT 0x1
14709 
14710 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFNUM_FRNUM register field. */
14711 #define ALT_USB_HOST_HFNUM_FRNUM_LSB 0
14712 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFNUM_FRNUM register field. */
14713 #define ALT_USB_HOST_HFNUM_FRNUM_MSB 15
14714 /* The width in bits of the ALT_USB_HOST_HFNUM_FRNUM register field. */
14715 #define ALT_USB_HOST_HFNUM_FRNUM_WIDTH 16
14716 /* The mask used to set the ALT_USB_HOST_HFNUM_FRNUM register field value. */
14717 #define ALT_USB_HOST_HFNUM_FRNUM_SET_MSK 0x0000ffff
14718 /* The mask used to clear the ALT_USB_HOST_HFNUM_FRNUM register field value. */
14719 #define ALT_USB_HOST_HFNUM_FRNUM_CLR_MSK 0xffff0000
14720 /* The reset value of the ALT_USB_HOST_HFNUM_FRNUM register field. */
14721 #define ALT_USB_HOST_HFNUM_FRNUM_RESET 0x3fff
14722 /* Extracts the ALT_USB_HOST_HFNUM_FRNUM field value from a register. */
14723 #define ALT_USB_HOST_HFNUM_FRNUM_GET(value) (((value) & 0x0000ffff) >> 0)
14724 /* Produces a ALT_USB_HOST_HFNUM_FRNUM register field value suitable for setting the register. */
14725 #define ALT_USB_HOST_HFNUM_FRNUM_SET(value) (((value) << 0) & 0x0000ffff)
14726 
14727 /*
14728  * Field : frrem
14729  *
14730  * Frame Time Remaining (FrRem)
14731  *
14732  * Indicates the amount of time remaining in the current
14733  *
14734  * microframe (HS) or Frame (FS/LS), in terms of PHY clocks. This
14735  *
14736  * field decrements on each PHY clock. When it reaches zero, this
14737  *
14738  * field is reloaded with the value in the Frame Interval register and
14739  *
14740  * a new SOF is transmitted on the USB.
14741  *
14742  * Field Access Macros:
14743  *
14744  */
14745 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFNUM_FRREM register field. */
14746 #define ALT_USB_HOST_HFNUM_FRREM_LSB 16
14747 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFNUM_FRREM register field. */
14748 #define ALT_USB_HOST_HFNUM_FRREM_MSB 31
14749 /* The width in bits of the ALT_USB_HOST_HFNUM_FRREM register field. */
14750 #define ALT_USB_HOST_HFNUM_FRREM_WIDTH 16
14751 /* The mask used to set the ALT_USB_HOST_HFNUM_FRREM register field value. */
14752 #define ALT_USB_HOST_HFNUM_FRREM_SET_MSK 0xffff0000
14753 /* The mask used to clear the ALT_USB_HOST_HFNUM_FRREM register field value. */
14754 #define ALT_USB_HOST_HFNUM_FRREM_CLR_MSK 0x0000ffff
14755 /* The reset value of the ALT_USB_HOST_HFNUM_FRREM register field. */
14756 #define ALT_USB_HOST_HFNUM_FRREM_RESET 0x0
14757 /* Extracts the ALT_USB_HOST_HFNUM_FRREM field value from a register. */
14758 #define ALT_USB_HOST_HFNUM_FRREM_GET(value) (((value) & 0xffff0000) >> 16)
14759 /* Produces a ALT_USB_HOST_HFNUM_FRREM register field value suitable for setting the register. */
14760 #define ALT_USB_HOST_HFNUM_FRREM_SET(value) (((value) << 16) & 0xffff0000)
14761 
14762 #ifndef __ASSEMBLY__
14763 /*
14764  * WARNING: The C register and register group struct declarations are provided for
14765  * convenience and illustrative purposes. They should, however, be used with
14766  * caution as the C language standard provides no guarantees about the alignment or
14767  * atomicity of device memory accesses. The recommended practice for writing
14768  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14769  * alt_write_word() functions.
14770  *
14771  * The struct declaration for register ALT_USB_HOST_HFNUM.
14772  */
14773 struct ALT_USB_HOST_HFNUM_s
14774 {
14775  const uint32_t frnum : 16; /* ALT_USB_HOST_HFNUM_FRNUM */
14776  const uint32_t frrem : 16; /* ALT_USB_HOST_HFNUM_FRREM */
14777 };
14778 
14779 /* The typedef declaration for register ALT_USB_HOST_HFNUM. */
14780 typedef volatile struct ALT_USB_HOST_HFNUM_s ALT_USB_HOST_HFNUM_t;
14781 #endif /* __ASSEMBLY__ */
14782 
14783 /* The reset value of the ALT_USB_HOST_HFNUM register. */
14784 #define ALT_USB_HOST_HFNUM_RESET 0x00003fff
14785 /* The byte offset of the ALT_USB_HOST_HFNUM register from the beginning of the component. */
14786 #define ALT_USB_HOST_HFNUM_OFST 0x8
14787 /* The address of the ALT_USB_HOST_HFNUM register. */
14788 #define ALT_USB_HOST_HFNUM_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HFNUM_OFST))
14789 
14790 /*
14791  * Register : hptxsts
14792  *
14793  * Host Periodic Transmit FIFO/Queue Status Register
14794  *
14795  * Register Layout
14796  *
14797  * Bits | Access | Reset | Description
14798  * :--------|:-------|:-------|:----------------------------------
14799  * [15:0] | R | 0x2000 | ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL
14800  * [23:16] | R | 0x10 | ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
14801  * [24] | R | 0x0 | Terminate
14802  * [26:25] | R | 0x0 | Type
14803  * [30:27] | R | 0x0 | Channel Endpoint Number
14804  * [31] | R | 0x0 | Odd Even Micro Frame
14805  *
14806  */
14807 /*
14808  * Field : ptxfspcavail
14809  *
14810  * Periodic Transmit Data FIFO Space Available
14811  *
14812  * (PTxFSpcAvail)
14813  *
14814  * Indicates the number of free locations available to be written to in the
14815  * Periodic
14816  *
14817  * TxFIFO.
14818  *
14819  * Values are in terms of 32-bit words
14820  *
14821  * 16'h0 : Periodic TxFIFO is full
14822  *
14823  * 16'h1 : 1 word available
14824  *
14825  * 16'h2 : 2 words available
14826  *
14827  * 16'hn : n words available (where 0 n 32,768)
14828  *
14829  * 16'h8000 : 32,768 words
14830  *
14831  * Others : Reserved
14832  *
14833  * Field Access Macros:
14834  *
14835  */
14836 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */
14837 #define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_LSB 0
14838 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */
14839 #define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_MSB 15
14840 /* The width in bits of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */
14841 #define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_WIDTH 16
14842 /* The mask used to set the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field value. */
14843 #define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_SET_MSK 0x0000ffff
14844 /* The mask used to clear the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field value. */
14845 #define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_CLR_MSK 0xffff0000
14846 /* The reset value of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */
14847 #define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_RESET 0x2000
14848 /* Extracts the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL field value from a register. */
14849 #define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
14850 /* Produces a ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field value suitable for setting the register. */
14851 #define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
14852 
14853 /*
14854  * Field : ptxqspcavail
14855  *
14856  * Periodic Transmit Request Queue Space Available
14857  *
14858  * (PTxQSpcAvail)
14859  *
14860  * Indicates the number of free locations available to be written in
14861  *
14862  * the Periodic Transmit Request Queue. This queue holds both IN
14863  *
14864  * and OUT requests.
14865  *
14866  * 8'h0: Periodic Transmit Request Queue is full
14867  *
14868  * 8'h1: 1 location available
14869  *
14870  * 8'h2: 2 locations available
14871  *
14872  * n: n locations available (0 <= n <= 16)
14873  *
14874  * Others: Reserved
14875  *
14876  * Field Enumeration Values:
14877  *
14878  * Enum | Value | Description
14879  * :------------------------------------------|:------|:----------------------------------------
14880  * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FULL | 0x0 | Periodic Transmit Request Queue is full
14881  * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE1 | 0x1 | 1 location available
14882  * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE2 | 0x2 | 2 location available
14883  * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE3 | 0x3 | 3 location available
14884  * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE4 | 0x4 | 4 location available
14885  * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE5 | 0x5 | 5 location available
14886  * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE6 | 0x6 | 6 location available
14887  * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE7 | 0x7 | 7 location available
14888  * ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE8 | 0x8 | 8 location available
14889  *
14890  * Field Access Macros:
14891  *
14892  */
14893 /*
14894  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
14895  *
14896  * Periodic Transmit Request Queue is full
14897  */
14898 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FULL 0x0
14899 /*
14900  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
14901  *
14902  * 1 location available
14903  */
14904 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE1 0x1
14905 /*
14906  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
14907  *
14908  * 2 location available
14909  */
14910 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE2 0x2
14911 /*
14912  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
14913  *
14914  * 3 location available
14915  */
14916 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE3 0x3
14917 /*
14918  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
14919  *
14920  * 4 location available
14921  */
14922 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE4 0x4
14923 /*
14924  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
14925  *
14926  * 5 location available
14927  */
14928 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE5 0x5
14929 /*
14930  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
14931  *
14932  * 6 location available
14933  */
14934 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE6 0x6
14935 /*
14936  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
14937  *
14938  * 7 location available
14939  */
14940 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE7 0x7
14941 /*
14942  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
14943  *
14944  * 8 location available
14945  */
14946 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE8 0x8
14947 
14948 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */
14949 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_LSB 16
14950 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */
14951 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_MSB 23
14952 /* The width in bits of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */
14953 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_WIDTH 8
14954 /* The mask used to set the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field value. */
14955 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_SET_MSK 0x00ff0000
14956 /* The mask used to clear the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field value. */
14957 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_CLR_MSK 0xff00ffff
14958 /* The reset value of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */
14959 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_RESET 0x10
14960 /* Extracts the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL field value from a register. */
14961 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_GET(value) (((value) & 0x00ff0000) >> 16)
14962 /* Produces a ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field value suitable for setting the register. */
14963 #define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_SET(value) (((value) << 16) & 0x00ff0000)
14964 
14965 /*
14966  * Field : Terminate - term
14967  *
14968  * Terminate last entry for selected channel/endpoint.
14969  *
14970  * Field Enumeration Values:
14971  *
14972  * Enum | Value | Description
14973  * :----------------------------------|:------|:----------------------------------
14974  * ALT_USB_HOST_HPTXSTS_TERM_E_INACT | 0x0 | No termination
14975  * ALT_USB_HOST_HPTXSTS_TERM_E_ACT | 0x1 | Terminate last entry for selected
14976  * : | | channel/endpoint
14977  *
14978  * Field Access Macros:
14979  *
14980  */
14981 /*
14982  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TERM
14983  *
14984  * No termination
14985  */
14986 #define ALT_USB_HOST_HPTXSTS_TERM_E_INACT 0x0
14987 /*
14988  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TERM
14989  *
14990  * Terminate last entry for selected channel/endpoint
14991  */
14992 #define ALT_USB_HOST_HPTXSTS_TERM_E_ACT 0x1
14993 
14994 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_TERM register field. */
14995 #define ALT_USB_HOST_HPTXSTS_TERM_LSB 24
14996 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_TERM register field. */
14997 #define ALT_USB_HOST_HPTXSTS_TERM_MSB 24
14998 /* The width in bits of the ALT_USB_HOST_HPTXSTS_TERM register field. */
14999 #define ALT_USB_HOST_HPTXSTS_TERM_WIDTH 1
15000 /* The mask used to set the ALT_USB_HOST_HPTXSTS_TERM register field value. */
15001 #define ALT_USB_HOST_HPTXSTS_TERM_SET_MSK 0x01000000
15002 /* The mask used to clear the ALT_USB_HOST_HPTXSTS_TERM register field value. */
15003 #define ALT_USB_HOST_HPTXSTS_TERM_CLR_MSK 0xfeffffff
15004 /* The reset value of the ALT_USB_HOST_HPTXSTS_TERM register field. */
15005 #define ALT_USB_HOST_HPTXSTS_TERM_RESET 0x0
15006 /* Extracts the ALT_USB_HOST_HPTXSTS_TERM field value from a register. */
15007 #define ALT_USB_HOST_HPTXSTS_TERM_GET(value) (((value) & 0x01000000) >> 24)
15008 /* Produces a ALT_USB_HOST_HPTXSTS_TERM register field value suitable for setting the register. */
15009 #define ALT_USB_HOST_HPTXSTS_TERM_SET(value) (((value) << 24) & 0x01000000)
15010 
15011 /*
15012  * Field : Type - type
15013  *
15014  * This indicates the Entry in the Periodic Tx Request Queue that is currently
15015  * being processes by the MAC.
15016  *
15017  * Field Enumeration Values:
15018  *
15019  * Enum | Value | Description
15020  * :--------------------------------------|:------|:------------------------
15021  * ALT_USB_HOST_HPTXSTS_TYPE_E_INOUT | 0x0 | IN/OUT type
15022  * ALT_USB_HOST_HPTXSTS_TYPE_E_ZEROLNGTH | 0x1 | Zero-length packet type
15023  * ALT_USB_HOST_HPTXSTS_TYPE_E_CSPLIT | 0x2 | CSPLIT type
15024  * ALT_USB_HOST_HPTXSTS_TYPE_E_DIS | 0x3 | Disable channel command
15025  *
15026  * Field Access Macros:
15027  *
15028  */
15029 /*
15030  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE
15031  *
15032  * IN/OUT type
15033  */
15034 #define ALT_USB_HOST_HPTXSTS_TYPE_E_INOUT 0x0
15035 /*
15036  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE
15037  *
15038  * Zero-length packet type
15039  */
15040 #define ALT_USB_HOST_HPTXSTS_TYPE_E_ZEROLNGTH 0x1
15041 /*
15042  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE
15043  *
15044  * CSPLIT type
15045  */
15046 #define ALT_USB_HOST_HPTXSTS_TYPE_E_CSPLIT 0x2
15047 /*
15048  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE
15049  *
15050  * Disable channel command
15051  */
15052 #define ALT_USB_HOST_HPTXSTS_TYPE_E_DIS 0x3
15053 
15054 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_TYPE register field. */
15055 #define ALT_USB_HOST_HPTXSTS_TYPE_LSB 25
15056 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_TYPE register field. */
15057 #define ALT_USB_HOST_HPTXSTS_TYPE_MSB 26
15058 /* The width in bits of the ALT_USB_HOST_HPTXSTS_TYPE register field. */
15059 #define ALT_USB_HOST_HPTXSTS_TYPE_WIDTH 2
15060 /* The mask used to set the ALT_USB_HOST_HPTXSTS_TYPE register field value. */
15061 #define ALT_USB_HOST_HPTXSTS_TYPE_SET_MSK 0x06000000
15062 /* The mask used to clear the ALT_USB_HOST_HPTXSTS_TYPE register field value. */
15063 #define ALT_USB_HOST_HPTXSTS_TYPE_CLR_MSK 0xf9ffffff
15064 /* The reset value of the ALT_USB_HOST_HPTXSTS_TYPE register field. */
15065 #define ALT_USB_HOST_HPTXSTS_TYPE_RESET 0x0
15066 /* Extracts the ALT_USB_HOST_HPTXSTS_TYPE field value from a register. */
15067 #define ALT_USB_HOST_HPTXSTS_TYPE_GET(value) (((value) & 0x06000000) >> 25)
15068 /* Produces a ALT_USB_HOST_HPTXSTS_TYPE register field value suitable for setting the register. */
15069 #define ALT_USB_HOST_HPTXSTS_TYPE_SET(value) (((value) << 25) & 0x06000000)
15070 
15071 /*
15072  * Field : Channel Endpoint Number - chanendpt
15073  *
15074  * This indicates the channel endpoint number that is currently being processes by
15075  * the MAC.
15076  *
15077  * Field Enumeration Values:
15078  *
15079  * Enum | Value | Description
15080  * :-----------------------------------------|:------|:--------------
15081  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT0 | 0x0 | End point 1
15082  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT1 | 0x1 | End point 2
15083  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT2 | 0x2 | End point 3
15084  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT3 | 0x3 | End point 4
15085  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT4 | 0x4 | End point 5
15086  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT5 | 0x5 | End point 6
15087  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT6 | 0x6 | End point 7
15088  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT7 | 0x7 | End point 8
15089  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT8 | 0x8 | End point 9
15090  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT9 | 0x9 | End point 10
15091  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT10 | 0xa | End point 11
15092  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT11 | 0xb | End point 12
15093  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT12 | 0xc | End point 13
15094  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT13 | 0xd | End point 14
15095  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT14 | 0xe | End point 15
15096  * ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT15 | 0xf | End point 16
15097  *
15098  * Field Access Macros:
15099  *
15100  */
15101 /*
15102  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15103  *
15104  * End point 1
15105  */
15106 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT0 0x0
15107 /*
15108  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15109  *
15110  * End point 2
15111  */
15112 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT1 0x1
15113 /*
15114  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15115  *
15116  * End point 3
15117  */
15118 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT2 0x2
15119 /*
15120  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15121  *
15122  * End point 4
15123  */
15124 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT3 0x3
15125 /*
15126  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15127  *
15128  * End point 5
15129  */
15130 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT4 0x4
15131 /*
15132  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15133  *
15134  * End point 6
15135  */
15136 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT5 0x5
15137 /*
15138  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15139  *
15140  * End point 7
15141  */
15142 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT6 0x6
15143 /*
15144  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15145  *
15146  * End point 8
15147  */
15148 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT7 0x7
15149 /*
15150  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15151  *
15152  * End point 9
15153  */
15154 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT8 0x8
15155 /*
15156  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15157  *
15158  * End point 10
15159  */
15160 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT9 0x9
15161 /*
15162  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15163  *
15164  * End point 11
15165  */
15166 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT10 0xa
15167 /*
15168  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15169  *
15170  * End point 12
15171  */
15172 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT11 0xb
15173 /*
15174  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15175  *
15176  * End point 13
15177  */
15178 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT12 0xc
15179 /*
15180  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15181  *
15182  * End point 14
15183  */
15184 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT13 0xd
15185 /*
15186  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15187  *
15188  * End point 15
15189  */
15190 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT14 0xe
15191 /*
15192  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
15193  *
15194  * End point 16
15195  */
15196 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT15 0xf
15197 
15198 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */
15199 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_LSB 27
15200 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */
15201 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_MSB 30
15202 /* The width in bits of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */
15203 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_WIDTH 4
15204 /* The mask used to set the ALT_USB_HOST_HPTXSTS_CHANENDPT register field value. */
15205 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_SET_MSK 0x78000000
15206 /* The mask used to clear the ALT_USB_HOST_HPTXSTS_CHANENDPT register field value. */
15207 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_CLR_MSK 0x87ffffff
15208 /* The reset value of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */
15209 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_RESET 0x0
15210 /* Extracts the ALT_USB_HOST_HPTXSTS_CHANENDPT field value from a register. */
15211 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_GET(value) (((value) & 0x78000000) >> 27)
15212 /* Produces a ALT_USB_HOST_HPTXSTS_CHANENDPT register field value suitable for setting the register. */
15213 #define ALT_USB_HOST_HPTXSTS_CHANENDPT_SET(value) (((value) << 27) & 0x78000000)
15214 
15215 /*
15216  * Field : Odd Even Micro Frame - oddevnmframe
15217  *
15218  * This indicates the odd/even micro frame that is currently being processes by the
15219  * MAC.
15220  *
15221  * Field Enumeration Values:
15222  *
15223  * Enum | Value | Description
15224  * :---------------------------------------|:------|:--------------------------
15225  * ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_EVEN | 0x0 | Send in even (micro)Frame
15226  * ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_ODD | 0x1 | Send in odd (micro)Frame
15227  *
15228  * Field Access Macros:
15229  *
15230  */
15231 /*
15232  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_ODDEVNMFRM
15233  *
15234  * Send in even (micro)Frame
15235  */
15236 #define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_EVEN 0x0
15237 /*
15238  * Enumerated value for register field ALT_USB_HOST_HPTXSTS_ODDEVNMFRM
15239  *
15240  * Send in odd (micro)Frame
15241  */
15242 #define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_ODD 0x1
15243 
15244 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */
15245 #define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_LSB 31
15246 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */
15247 #define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_MSB 31
15248 /* The width in bits of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */
15249 #define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_WIDTH 1
15250 /* The mask used to set the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field value. */
15251 #define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_SET_MSK 0x80000000
15252 /* The mask used to clear the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field value. */
15253 #define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_CLR_MSK 0x7fffffff
15254 /* The reset value of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */
15255 #define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_RESET 0x0
15256 /* Extracts the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM field value from a register. */
15257 #define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_GET(value) (((value) & 0x80000000) >> 31)
15258 /* Produces a ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field value suitable for setting the register. */
15259 #define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_SET(value) (((value) << 31) & 0x80000000)
15260 
15261 #ifndef __ASSEMBLY__
15262 /*
15263  * WARNING: The C register and register group struct declarations are provided for
15264  * convenience and illustrative purposes. They should, however, be used with
15265  * caution as the C language standard provides no guarantees about the alignment or
15266  * atomicity of device memory accesses. The recommended practice for writing
15267  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15268  * alt_write_word() functions.
15269  *
15270  * The struct declaration for register ALT_USB_HOST_HPTXSTS.
15271  */
15272 struct ALT_USB_HOST_HPTXSTS_s
15273 {
15274  const uint32_t ptxfspcavail : 16; /* ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL */
15275  const uint32_t ptxqspcavail : 8; /* ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL */
15276  const uint32_t term : 1; /* Terminate */
15277  const uint32_t type : 2; /* Type */
15278  const uint32_t chanendpt : 4; /* Channel Endpoint Number */
15279  const uint32_t oddevnmframe : 1; /* Odd Even Micro Frame */
15280 };
15281 
15282 /* The typedef declaration for register ALT_USB_HOST_HPTXSTS. */
15283 typedef volatile struct ALT_USB_HOST_HPTXSTS_s ALT_USB_HOST_HPTXSTS_t;
15284 #endif /* __ASSEMBLY__ */
15285 
15286 /* The reset value of the ALT_USB_HOST_HPTXSTS register. */
15287 #define ALT_USB_HOST_HPTXSTS_RESET 0x00102000
15288 /* The byte offset of the ALT_USB_HOST_HPTXSTS register from the beginning of the component. */
15289 #define ALT_USB_HOST_HPTXSTS_OFST 0x10
15290 /* The address of the ALT_USB_HOST_HPTXSTS register. */
15291 #define ALT_USB_HOST_HPTXSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HPTXSTS_OFST))
15292 
15293 /*
15294  * Register : haint
15295  *
15296  * Host All Channels Interrupt Register
15297  *
15298  * Register Layout
15299  *
15300  * Bits | Access | Reset | Description
15301  * :--------|:-------|:------|:-------------------------
15302  * [15:0] | R | 0x0 | ALT_USB_HOST_HAINT_HAINT
15303  * [31:16] | ??? | 0x0 | *UNDEFINED*
15304  *
15305  */
15306 /*
15307  * Field : haint
15308  *
15309  * Channel Interrupt for channel no.
15310  *
15311  * Field Access Macros:
15312  *
15313  */
15314 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HAINT_HAINT register field. */
15315 #define ALT_USB_HOST_HAINT_HAINT_LSB 0
15316 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HAINT_HAINT register field. */
15317 #define ALT_USB_HOST_HAINT_HAINT_MSB 15
15318 /* The width in bits of the ALT_USB_HOST_HAINT_HAINT register field. */
15319 #define ALT_USB_HOST_HAINT_HAINT_WIDTH 16
15320 /* The mask used to set the ALT_USB_HOST_HAINT_HAINT register field value. */
15321 #define ALT_USB_HOST_HAINT_HAINT_SET_MSK 0x0000ffff
15322 /* The mask used to clear the ALT_USB_HOST_HAINT_HAINT register field value. */
15323 #define ALT_USB_HOST_HAINT_HAINT_CLR_MSK 0xffff0000
15324 /* The reset value of the ALT_USB_HOST_HAINT_HAINT register field. */
15325 #define ALT_USB_HOST_HAINT_HAINT_RESET 0x0
15326 /* Extracts the ALT_USB_HOST_HAINT_HAINT field value from a register. */
15327 #define ALT_USB_HOST_HAINT_HAINT_GET(value) (((value) & 0x0000ffff) >> 0)
15328 /* Produces a ALT_USB_HOST_HAINT_HAINT register field value suitable for setting the register. */
15329 #define ALT_USB_HOST_HAINT_HAINT_SET(value) (((value) << 0) & 0x0000ffff)
15330 
15331 #ifndef __ASSEMBLY__
15332 /*
15333  * WARNING: The C register and register group struct declarations are provided for
15334  * convenience and illustrative purposes. They should, however, be used with
15335  * caution as the C language standard provides no guarantees about the alignment or
15336  * atomicity of device memory accesses. The recommended practice for writing
15337  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15338  * alt_write_word() functions.
15339  *
15340  * The struct declaration for register ALT_USB_HOST_HAINT.
15341  */
15342 struct ALT_USB_HOST_HAINT_s
15343 {
15344  const uint32_t haint : 16; /* ALT_USB_HOST_HAINT_HAINT */
15345  uint32_t : 16; /* *UNDEFINED* */
15346 };
15347 
15348 /* The typedef declaration for register ALT_USB_HOST_HAINT. */
15349 typedef volatile struct ALT_USB_HOST_HAINT_s ALT_USB_HOST_HAINT_t;
15350 #endif /* __ASSEMBLY__ */
15351 
15352 /* The reset value of the ALT_USB_HOST_HAINT register. */
15353 #define ALT_USB_HOST_HAINT_RESET 0x00000000
15354 /* The byte offset of the ALT_USB_HOST_HAINT register from the beginning of the component. */
15355 #define ALT_USB_HOST_HAINT_OFST 0x14
15356 /* The address of the ALT_USB_HOST_HAINT register. */
15357 #define ALT_USB_HOST_HAINT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HAINT_OFST))
15358 
15359 /*
15360  * Register : haintmsk
15361  *
15362  * Host All Channels Interrupt Mask Register
15363  *
15364  * Register Layout
15365  *
15366  * Bits | Access | Reset | Description
15367  * :--------|:-------|:------|:-------------------------------
15368  * [15:0] | RW | 0x0 | ALT_USB_HOST_HAINTMSK_HAINTMSK
15369  * [31:16] | ??? | 0x0 | *UNDEFINED*
15370  *
15371  */
15372 /*
15373  * Field : haintmsk
15374  *
15375  * Channel Interrupt Msk for channel
15376  *
15377  * Field Enumeration Values:
15378  *
15379  * Enum | Value | Description
15380  * :---------------------------------------|:------|:-----------------
15381  * ALT_USB_HOST_HAINTMSK_HAINTMSK_E_MSK | 0x0 | Mask interrupt
15382  * ALT_USB_HOST_HAINTMSK_HAINTMSK_E_NOMSK | 0x1 | Unmask interrupt
15383  *
15384  * Field Access Macros:
15385  *
15386  */
15387 /*
15388  * Enumerated value for register field ALT_USB_HOST_HAINTMSK_HAINTMSK
15389  *
15390  * Mask interrupt
15391  */
15392 #define ALT_USB_HOST_HAINTMSK_HAINTMSK_E_MSK 0x0
15393 /*
15394  * Enumerated value for register field ALT_USB_HOST_HAINTMSK_HAINTMSK
15395  *
15396  * Unmask interrupt
15397  */
15398 #define ALT_USB_HOST_HAINTMSK_HAINTMSK_E_NOMSK 0x1
15399 
15400 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */
15401 #define ALT_USB_HOST_HAINTMSK_HAINTMSK_LSB 0
15402 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */
15403 #define ALT_USB_HOST_HAINTMSK_HAINTMSK_MSB 15
15404 /* The width in bits of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */
15405 #define ALT_USB_HOST_HAINTMSK_HAINTMSK_WIDTH 16
15406 /* The mask used to set the ALT_USB_HOST_HAINTMSK_HAINTMSK register field value. */
15407 #define ALT_USB_HOST_HAINTMSK_HAINTMSK_SET_MSK 0x0000ffff
15408 /* The mask used to clear the ALT_USB_HOST_HAINTMSK_HAINTMSK register field value. */
15409 #define ALT_USB_HOST_HAINTMSK_HAINTMSK_CLR_MSK 0xffff0000
15410 /* The reset value of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */
15411 #define ALT_USB_HOST_HAINTMSK_HAINTMSK_RESET 0x0
15412 /* Extracts the ALT_USB_HOST_HAINTMSK_HAINTMSK field value from a register. */
15413 #define ALT_USB_HOST_HAINTMSK_HAINTMSK_GET(value) (((value) & 0x0000ffff) >> 0)
15414 /* Produces a ALT_USB_HOST_HAINTMSK_HAINTMSK register field value suitable for setting the register. */
15415 #define ALT_USB_HOST_HAINTMSK_HAINTMSK_SET(value) (((value) << 0) & 0x0000ffff)
15416 
15417 #ifndef __ASSEMBLY__
15418 /*
15419  * WARNING: The C register and register group struct declarations are provided for
15420  * convenience and illustrative purposes. They should, however, be used with
15421  * caution as the C language standard provides no guarantees about the alignment or
15422  * atomicity of device memory accesses. The recommended practice for writing
15423  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15424  * alt_write_word() functions.
15425  *
15426  * The struct declaration for register ALT_USB_HOST_HAINTMSK.
15427  */
15428 struct ALT_USB_HOST_HAINTMSK_s
15429 {
15430  uint32_t haintmsk : 16; /* ALT_USB_HOST_HAINTMSK_HAINTMSK */
15431  uint32_t : 16; /* *UNDEFINED* */
15432 };
15433 
15434 /* The typedef declaration for register ALT_USB_HOST_HAINTMSK. */
15435 typedef volatile struct ALT_USB_HOST_HAINTMSK_s ALT_USB_HOST_HAINTMSK_t;
15436 #endif /* __ASSEMBLY__ */
15437 
15438 /* The reset value of the ALT_USB_HOST_HAINTMSK register. */
15439 #define ALT_USB_HOST_HAINTMSK_RESET 0x00000000
15440 /* The byte offset of the ALT_USB_HOST_HAINTMSK register from the beginning of the component. */
15441 #define ALT_USB_HOST_HAINTMSK_OFST 0x18
15442 /* The address of the ALT_USB_HOST_HAINTMSK register. */
15443 #define ALT_USB_HOST_HAINTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HAINTMSK_OFST))
15444 
15445 /*
15446  * Register : hflbaddr
15447  *
15448  * Host Frame List Base Address Register
15449  *
15450  * Register Layout
15451  *
15452  * Bits | Access | Reset | Description
15453  * :-------|:-------|:------|:-------------------------------
15454  * [31:0] | RW | 0x0 | ALT_USB_HOST_HFLBADDR_HFLBADDR
15455  *
15456  */
15457 /*
15458  * Field : hflbaddr
15459  *
15460  * The starting address of the Frame list.
15461  *
15462  * This register is used only for Isochronous and Interrupt Channels.
15463  *
15464  * Field Access Macros:
15465  *
15466  */
15467 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */
15468 #define ALT_USB_HOST_HFLBADDR_HFLBADDR_LSB 0
15469 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */
15470 #define ALT_USB_HOST_HFLBADDR_HFLBADDR_MSB 31
15471 /* The width in bits of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */
15472 #define ALT_USB_HOST_HFLBADDR_HFLBADDR_WIDTH 32
15473 /* The mask used to set the ALT_USB_HOST_HFLBADDR_HFLBADDR register field value. */
15474 #define ALT_USB_HOST_HFLBADDR_HFLBADDR_SET_MSK 0xffffffff
15475 /* The mask used to clear the ALT_USB_HOST_HFLBADDR_HFLBADDR register field value. */
15476 #define ALT_USB_HOST_HFLBADDR_HFLBADDR_CLR_MSK 0x00000000
15477 /* The reset value of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */
15478 #define ALT_USB_HOST_HFLBADDR_HFLBADDR_RESET 0x0
15479 /* Extracts the ALT_USB_HOST_HFLBADDR_HFLBADDR field value from a register. */
15480 #define ALT_USB_HOST_HFLBADDR_HFLBADDR_GET(value) (((value) & 0xffffffff) >> 0)
15481 /* Produces a ALT_USB_HOST_HFLBADDR_HFLBADDR register field value suitable for setting the register. */
15482 #define ALT_USB_HOST_HFLBADDR_HFLBADDR_SET(value) (((value) << 0) & 0xffffffff)
15483 
15484 #ifndef __ASSEMBLY__
15485 /*
15486  * WARNING: The C register and register group struct declarations are provided for
15487  * convenience and illustrative purposes. They should, however, be used with
15488  * caution as the C language standard provides no guarantees about the alignment or
15489  * atomicity of device memory accesses. The recommended practice for writing
15490  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15491  * alt_write_word() functions.
15492  *
15493  * The struct declaration for register ALT_USB_HOST_HFLBADDR.
15494  */
15495 struct ALT_USB_HOST_HFLBADDR_s
15496 {
15497  uint32_t hflbaddr : 32; /* ALT_USB_HOST_HFLBADDR_HFLBADDR */
15498 };
15499 
15500 /* The typedef declaration for register ALT_USB_HOST_HFLBADDR. */
15501 typedef volatile struct ALT_USB_HOST_HFLBADDR_s ALT_USB_HOST_HFLBADDR_t;
15502 #endif /* __ASSEMBLY__ */
15503 
15504 /* The reset value of the ALT_USB_HOST_HFLBADDR register. */
15505 #define ALT_USB_HOST_HFLBADDR_RESET 0x00000000
15506 /* The byte offset of the ALT_USB_HOST_HFLBADDR register from the beginning of the component. */
15507 #define ALT_USB_HOST_HFLBADDR_OFST 0x1c
15508 /* The address of the ALT_USB_HOST_HFLBADDR register. */
15509 #define ALT_USB_HOST_HFLBADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HFLBADDR_OFST))
15510 
15511 /*
15512  * Register : hprt
15513  *
15514  * Host Port Control and Status Register
15515  *
15516  * Register Layout
15517  *
15518  * Bits | Access | Reset | Description
15519  * :--------|:---------|:------|:---------------------------------
15520  * [0] | R | 0x0 | ALT_USB_HOST_HPRT_PRTCONNSTS
15521  * [1] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTCONNDET
15522  * [2] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTENA
15523  * [3] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTENCHNG
15524  * [4] | R | 0x0 | ALT_USB_HOST_HPRT_PRTOVRCURRACT
15525  * [5] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTOVRCURRCHNG
15526  * [6] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTRES
15527  * [7] | R-W once | 0x0 | ALT_USB_HOST_HPRT_PRTSUSP
15528  * [8] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTRST
15529  * [9] | ??? | 0x0 | *UNDEFINED*
15530  * [11:10] | R | 0x0 | ALT_USB_HOST_HPRT_PRTLNSTS
15531  * [12] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTPWR
15532  * [16:13] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTTSTCTL
15533  * [18:17] | R | 0x0 | ALT_USB_HOST_HPRT_PRTSPD
15534  * [31:19] | ??? | 0x0 | *UNDEFINED*
15535  *
15536  */
15537 /*
15538  * Field : prtconnsts
15539  *
15540  * Port Connect Status (PrtConnSts)
15541  *
15542  * 0: No device is attached to the port.
15543  *
15544  * 1: A device is attached to the port.
15545  *
15546  * Field Enumeration Values:
15547  *
15548  * Enum | Value | Description
15549  * :-------------------------------------------|:------|:----------------------------------
15550  * ALT_USB_HOST_HPRT_PRTCONNSTS_E_NOTATTACHED | 0x0 | No device is attached to the port
15551  * ALT_USB_HOST_HPRT_PRTCONNSTS_E_ATTACHED | 0x1 | A device is attached to the port
15552  *
15553  * Field Access Macros:
15554  *
15555  */
15556 /*
15557  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNSTS
15558  *
15559  * No device is attached to the port
15560  */
15561 #define ALT_USB_HOST_HPRT_PRTCONNSTS_E_NOTATTACHED 0x0
15562 /*
15563  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNSTS
15564  *
15565  * A device is attached to the port
15566  */
15567 #define ALT_USB_HOST_HPRT_PRTCONNSTS_E_ATTACHED 0x1
15568 
15569 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */
15570 #define ALT_USB_HOST_HPRT_PRTCONNSTS_LSB 0
15571 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */
15572 #define ALT_USB_HOST_HPRT_PRTCONNSTS_MSB 0
15573 /* The width in bits of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */
15574 #define ALT_USB_HOST_HPRT_PRTCONNSTS_WIDTH 1
15575 /* The mask used to set the ALT_USB_HOST_HPRT_PRTCONNSTS register field value. */
15576 #define ALT_USB_HOST_HPRT_PRTCONNSTS_SET_MSK 0x00000001
15577 /* The mask used to clear the ALT_USB_HOST_HPRT_PRTCONNSTS register field value. */
15578 #define ALT_USB_HOST_HPRT_PRTCONNSTS_CLR_MSK 0xfffffffe
15579 /* The reset value of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */
15580 #define ALT_USB_HOST_HPRT_PRTCONNSTS_RESET 0x0
15581 /* Extracts the ALT_USB_HOST_HPRT_PRTCONNSTS field value from a register. */
15582 #define ALT_USB_HOST_HPRT_PRTCONNSTS_GET(value) (((value) & 0x00000001) >> 0)
15583 /* Produces a ALT_USB_HOST_HPRT_PRTCONNSTS register field value suitable for setting the register. */
15584 #define ALT_USB_HOST_HPRT_PRTCONNSTS_SET(value) (((value) << 0) & 0x00000001)
15585 
15586 /*
15587  * Field : prtconndet
15588  *
15589  * Port Connect Detected (PrtConnDet)
15590  *
15591  * The core sets this bit when a device connection is detected
15592  *
15593  * to trigger an interrupt to the application using the Host Port
15594  *
15595  * Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).This bit can be
15596  * set only by the core and the application should write 1 to clear it.The
15597  * application must write a 1 to this bit to clear the
15598  *
15599  * interrupt.
15600  *
15601  * Field Enumeration Values:
15602  *
15603  * Enum | Value | Description
15604  * :-------------------------------------|:------|:------------------------------
15605  * ALT_USB_HOST_HPRT_PRTCONNDET_E_ACT | 0x0 | Device connection detected
15606  * ALT_USB_HOST_HPRT_PRTCONNDET_E_INACT | 0x1 | No device connection detected
15607  *
15608  * Field Access Macros:
15609  *
15610  */
15611 /*
15612  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNDET
15613  *
15614  * Device connection detected
15615  */
15616 #define ALT_USB_HOST_HPRT_PRTCONNDET_E_ACT 0x0
15617 /*
15618  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNDET
15619  *
15620  * No device connection detected
15621  */
15622 #define ALT_USB_HOST_HPRT_PRTCONNDET_E_INACT 0x1
15623 
15624 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */
15625 #define ALT_USB_HOST_HPRT_PRTCONNDET_LSB 1
15626 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */
15627 #define ALT_USB_HOST_HPRT_PRTCONNDET_MSB 1
15628 /* The width in bits of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */
15629 #define ALT_USB_HOST_HPRT_PRTCONNDET_WIDTH 1
15630 /* The mask used to set the ALT_USB_HOST_HPRT_PRTCONNDET register field value. */
15631 #define ALT_USB_HOST_HPRT_PRTCONNDET_SET_MSK 0x00000002
15632 /* The mask used to clear the ALT_USB_HOST_HPRT_PRTCONNDET register field value. */
15633 #define ALT_USB_HOST_HPRT_PRTCONNDET_CLR_MSK 0xfffffffd
15634 /* The reset value of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */
15635 #define ALT_USB_HOST_HPRT_PRTCONNDET_RESET 0x0
15636 /* Extracts the ALT_USB_HOST_HPRT_PRTCONNDET field value from a register. */
15637 #define ALT_USB_HOST_HPRT_PRTCONNDET_GET(value) (((value) & 0x00000002) >> 1)
15638 /* Produces a ALT_USB_HOST_HPRT_PRTCONNDET register field value suitable for setting the register. */
15639 #define ALT_USB_HOST_HPRT_PRTCONNDET_SET(value) (((value) << 1) & 0x00000002)
15640 
15641 /*
15642  * Field : prtena
15643  *
15644  * Port Enable (PrtEna)
15645  *
15646  * A port is enabled only by the core after a reset sequence,
15647  *
15648  * and is disabled by an overcurrent condition, a disconnect
15649  *
15650  * condition, or by the application clearing this bit. The
15651  *
15652  * application cannot Set this bit by a register write. It can only
15653  *
15654  * clear it to disable the port by writing 1.. This bit does not trigger any
15655  *
15656  * interrupt to the application.
15657  *
15658  * 1'b0: Port disabled
15659  *
15660  * 1'b1: Port enabled
15661  *
15662  * Field Enumeration Values:
15663  *
15664  * Enum | Value | Description
15665  * :--------------------------------|:------|:--------------
15666  * ALT_USB_HOST_HPRT_PRTENA_E_DISD | 0x0 | Port disabled
15667  * ALT_USB_HOST_HPRT_PRTENA_E_END | 0x1 | Port enabled
15668  *
15669  * Field Access Macros:
15670  *
15671  */
15672 /*
15673  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTENA
15674  *
15675  * Port disabled
15676  */
15677 #define ALT_USB_HOST_HPRT_PRTENA_E_DISD 0x0
15678 /*
15679  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTENA
15680  *
15681  * Port enabled
15682  */
15683 #define ALT_USB_HOST_HPRT_PRTENA_E_END 0x1
15684 
15685 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTENA register field. */
15686 #define ALT_USB_HOST_HPRT_PRTENA_LSB 2
15687 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTENA register field. */
15688 #define ALT_USB_HOST_HPRT_PRTENA_MSB 2
15689 /* The width in bits of the ALT_USB_HOST_HPRT_PRTENA register field. */
15690 #define ALT_USB_HOST_HPRT_PRTENA_WIDTH 1
15691 /* The mask used to set the ALT_USB_HOST_HPRT_PRTENA register field value. */
15692 #define ALT_USB_HOST_HPRT_PRTENA_SET_MSK 0x00000004
15693 /* The mask used to clear the ALT_USB_HOST_HPRT_PRTENA register field value. */
15694 #define ALT_USB_HOST_HPRT_PRTENA_CLR_MSK 0xfffffffb
15695 /* The reset value of the ALT_USB_HOST_HPRT_PRTENA register field. */
15696 #define ALT_USB_HOST_HPRT_PRTENA_RESET 0x0
15697 /* Extracts the ALT_USB_HOST_HPRT_PRTENA field value from a register. */
15698 #define ALT_USB_HOST_HPRT_PRTENA_GET(value) (((value) & 0x00000004) >> 2)
15699 /* Produces a ALT_USB_HOST_HPRT_PRTENA register field value suitable for setting the register. */
15700 #define ALT_USB_HOST_HPRT_PRTENA_SET(value) (((value) << 2) & 0x00000004)
15701 
15702 /*
15703  * Field : prtenchng
15704  *
15705  * Port Enable/Disable Change (PrtEnChng)
15706  *
15707  * The core sets this bit when the status of the Port Enable bit
15708  *
15709  * [2] of this register changes.This bit can be set only by the core and the
15710  * application should write 1 to clear it.
15711  *
15712  * Field Enumeration Values:
15713  *
15714  * Enum | Value | Description
15715  * :------------------------------------|:------|:----------------------------
15716  * ALT_USB_HOST_HPRT_PRTENCHNG_E_INACT | 0x0 | Port Enable bit 2 no change
15717  * ALT_USB_HOST_HPRT_PRTENCHNG_E_ACT | 0x1 | Port Enable bit 2 changed
15718  *
15719  * Field Access Macros:
15720  *
15721  */
15722 /*
15723  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTENCHNG
15724  *
15725  * Port Enable bit 2 no change
15726  */
15727 #define ALT_USB_HOST_HPRT_PRTENCHNG_E_INACT 0x0
15728 /*
15729  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTENCHNG
15730  *
15731  * Port Enable bit 2 changed
15732  */
15733 #define ALT_USB_HOST_HPRT_PRTENCHNG_E_ACT 0x1
15734 
15735 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */
15736 #define ALT_USB_HOST_HPRT_PRTENCHNG_LSB 3
15737 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */
15738 #define ALT_USB_HOST_HPRT_PRTENCHNG_MSB 3
15739 /* The width in bits of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */
15740 #define ALT_USB_HOST_HPRT_PRTENCHNG_WIDTH 1
15741 /* The mask used to set the ALT_USB_HOST_HPRT_PRTENCHNG register field value. */
15742 #define ALT_USB_HOST_HPRT_PRTENCHNG_SET_MSK 0x00000008
15743 /* The mask used to clear the ALT_USB_HOST_HPRT_PRTENCHNG register field value. */
15744 #define ALT_USB_HOST_HPRT_PRTENCHNG_CLR_MSK 0xfffffff7
15745 /* The reset value of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */
15746 #define ALT_USB_HOST_HPRT_PRTENCHNG_RESET 0x0
15747 /* Extracts the ALT_USB_HOST_HPRT_PRTENCHNG field value from a register. */
15748 #define ALT_USB_HOST_HPRT_PRTENCHNG_GET(value) (((value) & 0x00000008) >> 3)
15749 /* Produces a ALT_USB_HOST_HPRT_PRTENCHNG register field value suitable for setting the register. */
15750 #define ALT_USB_HOST_HPRT_PRTENCHNG_SET(value) (((value) << 3) & 0x00000008)
15751 
15752 /*
15753  * Field : prtovrcurract
15754  *
15755  * Port Overcurrent Active (PrtOvrCurrAct)
15756  *
15757  * Indicates the overcurrent condition of the port.
15758  *
15759  * 1'b0: No overcurrent condition
15760  *
15761  * 1'b1: Overcurrent condition
15762  *
15763  * Field Enumeration Values:
15764  *
15765  * Enum | Value | Description
15766  * :----------------------------------------|:------|:-------------------------
15767  * ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_INACT | 0x0 | No overcurrent condition
15768  * ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_ACT | 0x1 | Overcurrent condition
15769  *
15770  * Field Access Macros:
15771  *
15772  */
15773 /*
15774  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRACT
15775  *
15776  * No overcurrent condition
15777  */
15778 #define ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_INACT 0x0
15779 /*
15780  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRACT
15781  *
15782  * Overcurrent condition
15783  */
15784 #define ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_ACT 0x1
15785 
15786 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */
15787 #define ALT_USB_HOST_HPRT_PRTOVRCURRACT_LSB 4
15788 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */
15789 #define ALT_USB_HOST_HPRT_PRTOVRCURRACT_MSB 4
15790 /* The width in bits of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */
15791 #define ALT_USB_HOST_HPRT_PRTOVRCURRACT_WIDTH 1
15792 /* The mask used to set the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field value. */
15793 #define ALT_USB_HOST_HPRT_PRTOVRCURRACT_SET_MSK 0x00000010
15794 /* The mask used to clear the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field value. */
15795 #define ALT_USB_HOST_HPRT_PRTOVRCURRACT_CLR_MSK 0xffffffef
15796 /* The reset value of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */
15797 #define ALT_USB_HOST_HPRT_PRTOVRCURRACT_RESET 0x0
15798 /* Extracts the ALT_USB_HOST_HPRT_PRTOVRCURRACT field value from a register. */
15799 #define ALT_USB_HOST_HPRT_PRTOVRCURRACT_GET(value) (((value) & 0x00000010) >> 4)
15800 /* Produces a ALT_USB_HOST_HPRT_PRTOVRCURRACT register field value suitable for setting the register. */
15801 #define ALT_USB_HOST_HPRT_PRTOVRCURRACT_SET(value) (((value) << 4) & 0x00000010)
15802 
15803 /*
15804  * Field : prtovrcurrchng
15805  *
15806  * Port Overcurrent Change (PrtOvrCurrChng)
15807  *
15808  * The core sets this bit when the status of the Port
15809  *
15810  * Overcurrent Active bit (bit 4) in this register changes.This bit can be set only
15811  * by the core and the application should write 1 to clear it
15812  *
15813  * Field Enumeration Values:
15814  *
15815  * Enum | Value | Description
15816  * :-----------------------------------------|:------|:-------------------------------------
15817  * ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_INACT | 0x0 | Status of port overcurrent no change
15818  * ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_ACT | 0x1 | Status of port overcurrent changed
15819  *
15820  * Field Access Macros:
15821  *
15822  */
15823 /*
15824  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRCHNG
15825  *
15826  * Status of port overcurrent no change
15827  */
15828 #define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_INACT 0x0
15829 /*
15830  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRCHNG
15831  *
15832  * Status of port overcurrent changed
15833  */
15834 #define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_ACT 0x1
15835 
15836 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */
15837 #define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_LSB 5
15838 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */
15839 #define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_MSB 5
15840 /* The width in bits of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */
15841 #define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_WIDTH 1
15842 /* The mask used to set the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field value. */
15843 #define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_SET_MSK 0x00000020
15844 /* The mask used to clear the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field value. */
15845 #define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_CLR_MSK 0xffffffdf
15846 /* The reset value of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */
15847 #define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_RESET 0x0
15848 /* Extracts the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG field value from a register. */
15849 #define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_GET(value) (((value) & 0x00000020) >> 5)
15850 /* Produces a ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field value suitable for setting the register. */
15851 #define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_SET(value) (((value) << 5) & 0x00000020)
15852 
15853 /*
15854  * Field : prtres
15855  *
15856  * Port Resume (PrtRes)
15857  *
15858  * The application sets this bit to drive resume signaling on the
15859  *
15860  * port. The core continues to drive the resume signal until the
15861  *
15862  * application clears this bit.
15863  *
15864  * If the core detects a USB remote wakeup sequence, as
15865  *
15866  * indicated by the Port Resume/Remote Wakeup Detected
15867  *
15868  * Interrupt bit of the Core Interrupt register
15869  *
15870  * (GINTSTS.WkUpInt), the core starts driving resume
15871  *
15872  * signaling without application intervention and clears this bit
15873  *
15874  * when it detects a disconnect condition. The read value of
15875  *
15876  * this bit indicates whether the core is currently driving
15877  *
15878  * resume signaling.
15879  *
15880  * 1'b0: No resume driven
15881  *
15882  * 1'b1: Resume driven
15883  *
15884  * When LPM is enabled, In L1 state the behavior of this bit is as follows:
15885  *
15886  * The application sets this bit to drive resume signaling on the port.
15887  *
15888  * The core continues to drive the resume signal until a pre-determined time
15889  *
15890  * specified in GLPMCFG.HIRD_Thres[3:0] field. If the core detects a USB remote
15891  *
15892  * wakeup sequence, as indicated by the Port L1Resume/Remote L1Wakeup Detected
15893  *
15894  * Interrupt bit of the Core Interrupt register (GINTSTS.L1WkUpInt),
15895  *
15896  * the core starts driving resume signaling without application intervention
15897  *
15898  * and clears this bit at the end of resume.This bit can be set by both core or
15899  * application
15900  *
15901  * and also cleared by core or application. This bit is cleared by the core even if
15902  * there is
15903  *
15904  * no device connected to the Host.
15905  *
15906  * Field Enumeration Values:
15907  *
15908  * Enum | Value | Description
15909  * :------------------------------------|:------|:-----------------
15910  * ALT_USB_HOST_HPRT_PRTRES_E_NORESUME | 0x0 | No resume driven
15911  * ALT_USB_HOST_HPRT_PRTRES_E_RESUME | 0x1 | Resume driven
15912  *
15913  * Field Access Macros:
15914  *
15915  */
15916 /*
15917  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTRES
15918  *
15919  * No resume driven
15920  */
15921 #define ALT_USB_HOST_HPRT_PRTRES_E_NORESUME 0x0
15922 /*
15923  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTRES
15924  *
15925  * Resume driven
15926  */
15927 #define ALT_USB_HOST_HPRT_PRTRES_E_RESUME 0x1
15928 
15929 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTRES register field. */
15930 #define ALT_USB_HOST_HPRT_PRTRES_LSB 6
15931 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTRES register field. */
15932 #define ALT_USB_HOST_HPRT_PRTRES_MSB 6
15933 /* The width in bits of the ALT_USB_HOST_HPRT_PRTRES register field. */
15934 #define ALT_USB_HOST_HPRT_PRTRES_WIDTH 1
15935 /* The mask used to set the ALT_USB_HOST_HPRT_PRTRES register field value. */
15936 #define ALT_USB_HOST_HPRT_PRTRES_SET_MSK 0x00000040
15937 /* The mask used to clear the ALT_USB_HOST_HPRT_PRTRES register field value. */
15938 #define ALT_USB_HOST_HPRT_PRTRES_CLR_MSK 0xffffffbf
15939 /* The reset value of the ALT_USB_HOST_HPRT_PRTRES register field. */
15940 #define ALT_USB_HOST_HPRT_PRTRES_RESET 0x0
15941 /* Extracts the ALT_USB_HOST_HPRT_PRTRES field value from a register. */
15942 #define ALT_USB_HOST_HPRT_PRTRES_GET(value) (((value) & 0x00000040) >> 6)
15943 /* Produces a ALT_USB_HOST_HPRT_PRTRES register field value suitable for setting the register. */
15944 #define ALT_USB_HOST_HPRT_PRTRES_SET(value) (((value) << 6) & 0x00000040)
15945 
15946 /*
15947  * Field : prtsusp
15948  *
15949  * Port Suspend (PrtSusp)
15950  *
15951  * The application sets this bit to put this port in Suspend
15952  *
15953  * mode. The core only stops sending SOFs when this is Set.
15954  *
15955  * To stop the PHY clock, the application must Set the Port
15956  *
15957  * Clock Stop bit, which asserts the suspend input pin of the
15958  *
15959  * PHY.
15960  *
15961  * The read value of this bit reflects the current suspend status
15962  *
15963  * of the port. This bit is cleared by the core after a remote
15964  *
15965  * wakeup signal is detected or the application sets the Port
15966  *
15967  * Reset bit or Port Resume bit in this register or the
15968  *
15969  * Resume/Remote Wakeup Detected Interrupt bit or
15970  *
15971  * Disconnect Detected Interrupt bit in the Core Interrupt
15972  *
15973  * register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,
15974  *
15975  * respectively).This bit is cleared by the core even if there is
15976  *
15977  * no device connected to the Host.
15978  *
15979  * 1'b0: Port not in Suspend mode
15980  *
15981  * 1'b1: Port in Suspend mode
15982  *
15983  * Field Enumeration Values:
15984  *
15985  * Enum | Value | Description
15986  * :----------------------------------|:------|:-------------------------
15987  * ALT_USB_HOST_HPRT_PRTSUSP_E_INACT | 0x0 | Port not in Suspend mode
15988  * ALT_USB_HOST_HPRT_PRTSUSP_E_ACT | 0x1 | Port in Suspend mode
15989  *
15990  * Field Access Macros:
15991  *
15992  */
15993 /*
15994  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSUSP
15995  *
15996  * Port not in Suspend mode
15997  */
15998 #define ALT_USB_HOST_HPRT_PRTSUSP_E_INACT 0x0
15999 /*
16000  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSUSP
16001  *
16002  * Port in Suspend mode
16003  */
16004 #define ALT_USB_HOST_HPRT_PRTSUSP_E_ACT 0x1
16005 
16006 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTSUSP register field. */
16007 #define ALT_USB_HOST_HPRT_PRTSUSP_LSB 7
16008 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTSUSP register field. */
16009 #define ALT_USB_HOST_HPRT_PRTSUSP_MSB 7
16010 /* The width in bits of the ALT_USB_HOST_HPRT_PRTSUSP register field. */
16011 #define ALT_USB_HOST_HPRT_PRTSUSP_WIDTH 1
16012 /* The mask used to set the ALT_USB_HOST_HPRT_PRTSUSP register field value. */
16013 #define ALT_USB_HOST_HPRT_PRTSUSP_SET_MSK 0x00000080
16014 /* The mask used to clear the ALT_USB_HOST_HPRT_PRTSUSP register field value. */
16015 #define ALT_USB_HOST_HPRT_PRTSUSP_CLR_MSK 0xffffff7f
16016 /* The reset value of the ALT_USB_HOST_HPRT_PRTSUSP register field. */
16017 #define ALT_USB_HOST_HPRT_PRTSUSP_RESET 0x0
16018 /* Extracts the ALT_USB_HOST_HPRT_PRTSUSP field value from a register. */
16019 #define ALT_USB_HOST_HPRT_PRTSUSP_GET(value) (((value) & 0x00000080) >> 7)
16020 /* Produces a ALT_USB_HOST_HPRT_PRTSUSP register field value suitable for setting the register. */
16021 #define ALT_USB_HOST_HPRT_PRTSUSP_SET(value) (((value) << 7) & 0x00000080)
16022 
16023 /*
16024  * Field : prtrst
16025  *
16026  * Port Reset (PrtRst)
16027  *
16028  * When the application sets this bit, a reset sequence is
16029  *
16030  * started on this port. The application must time the reset
16031  *
16032  * period and clear this bit after the reset sequence is
16033  *
16034  * complete.
16035  *
16036  * 1'b0: Port not in reset
16037  *
16038  * 1'b1: Port in reset
16039  *
16040  * The application must leave this bit Set For at least a
16041  *
16042  * minimum duration mentioned below to start a reset on the
16043  *
16044  * port. The application can leave it Set For another 10 ms in
16045  *
16046  * addition to the required minimum duration, before clearing
16047  *
16048  * the bit, even though there is no maximum limit Set by the
16049  *
16050  * USB standard.This bit is cleared by the core even if there is
16051  *
16052  * no device connected to the Host.
16053  *
16054  * High speed: 50 ms
16055  *
16056  * Full speed/Low speed: 10 ms
16057  *
16058  * Field Enumeration Values:
16059  *
16060  * Enum | Value | Description
16061  * :--------------------------------|:------|:------------------
16062  * ALT_USB_HOST_HPRT_PRTRST_E_DISD | 0x0 | Port not in reset
16063  * ALT_USB_HOST_HPRT_PRTRST_E_END | 0x1 | Port in reset
16064  *
16065  * Field Access Macros:
16066  *
16067  */
16068 /*
16069  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTRST
16070  *
16071  * Port not in reset
16072  */
16073 #define ALT_USB_HOST_HPRT_PRTRST_E_DISD 0x0
16074 /*
16075  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTRST
16076  *
16077  * Port in reset
16078  */
16079 #define ALT_USB_HOST_HPRT_PRTRST_E_END 0x1
16080 
16081 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTRST register field. */
16082 #define ALT_USB_HOST_HPRT_PRTRST_LSB 8
16083 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTRST register field. */
16084 #define ALT_USB_HOST_HPRT_PRTRST_MSB 8
16085 /* The width in bits of the ALT_USB_HOST_HPRT_PRTRST register field. */
16086 #define ALT_USB_HOST_HPRT_PRTRST_WIDTH 1
16087 /* The mask used to set the ALT_USB_HOST_HPRT_PRTRST register field value. */
16088 #define ALT_USB_HOST_HPRT_PRTRST_SET_MSK 0x00000100
16089 /* The mask used to clear the ALT_USB_HOST_HPRT_PRTRST register field value. */
16090 #define ALT_USB_HOST_HPRT_PRTRST_CLR_MSK 0xfffffeff
16091 /* The reset value of the ALT_USB_HOST_HPRT_PRTRST register field. */
16092 #define ALT_USB_HOST_HPRT_PRTRST_RESET 0x0
16093 /* Extracts the ALT_USB_HOST_HPRT_PRTRST field value from a register. */
16094 #define ALT_USB_HOST_HPRT_PRTRST_GET(value) (((value) & 0x00000100) >> 8)
16095 /* Produces a ALT_USB_HOST_HPRT_PRTRST register field value suitable for setting the register. */
16096 #define ALT_USB_HOST_HPRT_PRTRST_SET(value) (((value) << 8) & 0x00000100)
16097 
16098 /*
16099  * Field : prtlnsts
16100  *
16101  * Port Line Status (PrtLnSts)
16102  *
16103  * Indicates the current logic level USB data lines
16104  *
16105  * Bit [10]: Logic level of D+
16106  *
16107  * Bit [11]: Logic level of D-
16108  *
16109  * Field Enumeration Values:
16110  *
16111  * Enum | Value | Description
16112  * :------------------------------------|:------|:------------------
16113  * ALT_USB_HOST_HPRT_PRTLNSTS_E_PLUSD | 0x1 | Logic level of D+
16114  * ALT_USB_HOST_HPRT_PRTLNSTS_E_MINUSD | 0x2 | Logic level of D-
16115  *
16116  * Field Access Macros:
16117  *
16118  */
16119 /*
16120  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTLNSTS
16121  *
16122  * Logic level of D+
16123  */
16124 #define ALT_USB_HOST_HPRT_PRTLNSTS_E_PLUSD 0x1
16125 /*
16126  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTLNSTS
16127  *
16128  * Logic level of D-
16129  */
16130 #define ALT_USB_HOST_HPRT_PRTLNSTS_E_MINUSD 0x2
16131 
16132 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */
16133 #define ALT_USB_HOST_HPRT_PRTLNSTS_LSB 10
16134 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */
16135 #define ALT_USB_HOST_HPRT_PRTLNSTS_MSB 11
16136 /* The width in bits of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */
16137 #define ALT_USB_HOST_HPRT_PRTLNSTS_WIDTH 2
16138 /* The mask used to set the ALT_USB_HOST_HPRT_PRTLNSTS register field value. */
16139 #define ALT_USB_HOST_HPRT_PRTLNSTS_SET_MSK 0x00000c00
16140 /* The mask used to clear the ALT_USB_HOST_HPRT_PRTLNSTS register field value. */
16141 #define ALT_USB_HOST_HPRT_PRTLNSTS_CLR_MSK 0xfffff3ff
16142 /* The reset value of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */
16143 #define ALT_USB_HOST_HPRT_PRTLNSTS_RESET 0x0
16144 /* Extracts the ALT_USB_HOST_HPRT_PRTLNSTS field value from a register. */
16145 #define ALT_USB_HOST_HPRT_PRTLNSTS_GET(value) (((value) & 0x00000c00) >> 10)
16146 /* Produces a ALT_USB_HOST_HPRT_PRTLNSTS register field value suitable for setting the register. */
16147 #define ALT_USB_HOST_HPRT_PRTLNSTS_SET(value) (((value) << 10) & 0x00000c00)
16148 
16149 /*
16150  * Field : prtpwr
16151  *
16152  * Port Power (PrtPwr)
16153  *
16154  * The application uses this field to control power to this port (write 1'b1 to set
16155  * to 1'b1
16156  *
16157  * and write 1'b0 to set to 1'b0), and the core can clear this bit on an over
16158  * current
16159  *
16160  * condition.
16161  *
16162  * 1'b0: Power off
16163  *
16164  * 1'b1: Power on
16165  *
16166  * Field Enumeration Values:
16167  *
16168  * Enum | Value | Description
16169  * :-------------------------------|:------|:------------
16170  * ALT_USB_HOST_HPRT_PRTPWR_E_OFF | 0x0 | Power off
16171  * ALT_USB_HOST_HPRT_PRTPWR_E_ON | 0x1 | Power on
16172  *
16173  * Field Access Macros:
16174  *
16175  */
16176 /*
16177  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTPWR
16178  *
16179  * Power off
16180  */
16181 #define ALT_USB_HOST_HPRT_PRTPWR_E_OFF 0x0
16182 /*
16183  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTPWR
16184  *
16185  * Power on
16186  */
16187 #define ALT_USB_HOST_HPRT_PRTPWR_E_ON 0x1
16188 
16189 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTPWR register field. */
16190 #define ALT_USB_HOST_HPRT_PRTPWR_LSB 12
16191 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTPWR register field. */
16192 #define ALT_USB_HOST_HPRT_PRTPWR_MSB 12
16193 /* The width in bits of the ALT_USB_HOST_HPRT_PRTPWR register field. */
16194 #define ALT_USB_HOST_HPRT_PRTPWR_WIDTH 1
16195 /* The mask used to set the ALT_USB_HOST_HPRT_PRTPWR register field value. */
16196 #define ALT_USB_HOST_HPRT_PRTPWR_SET_MSK 0x00001000
16197 /* The mask used to clear the ALT_USB_HOST_HPRT_PRTPWR register field value. */
16198 #define ALT_USB_HOST_HPRT_PRTPWR_CLR_MSK 0xffffefff
16199 /* The reset value of the ALT_USB_HOST_HPRT_PRTPWR register field. */
16200 #define ALT_USB_HOST_HPRT_PRTPWR_RESET 0x0
16201 /* Extracts the ALT_USB_HOST_HPRT_PRTPWR field value from a register. */
16202 #define ALT_USB_HOST_HPRT_PRTPWR_GET(value) (((value) & 0x00001000) >> 12)
16203 /* Produces a ALT_USB_HOST_HPRT_PRTPWR register field value suitable for setting the register. */
16204 #define ALT_USB_HOST_HPRT_PRTPWR_SET(value) (((value) << 12) & 0x00001000)
16205 
16206 /*
16207  * Field : prttstctl
16208  *
16209  * Port Test Control (PrtTstCtl)
16210  *
16211  * The application writes a nonzero value to this field to put the
16212  *
16213  * port into a Test mode, and the corresponding pattern is
16214  *
16215  * signaled on the port.
16216  *
16217  * 4'b0000: Test mode disabled
16218  *
16219  * 4'b0001: Test_J mode
16220  *
16221  * 4'b0010: Test_K mode
16222  *
16223  * 4'b0011: Test_SE0_NAK mode
16224  *
16225  * 4'b0100: Test_Packet mode
16226  *
16227  * 4'b0101: Test_Force_Enable
16228  *
16229  * Others: Reserved
16230  *
16231  * Field Enumeration Values:
16232  *
16233  * Enum | Value | Description
16234  * :---------------------------------------|:------|:-------------------
16235  * ALT_USB_HOST_HPRT_PRTTSTCTL_E_DISD | 0x0 | Test mode disabled
16236  * ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTJ | 0x1 | Test_J mode
16237  * ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTK | 0x2 | Test_K mode
16238  * ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTSN | 0x3 | Test_SE0_NAK mode
16239  * ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTPM | 0x4 | Test_Packet mode
16240  * ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTFENB | 0x5 | Test_force_Enable
16241  *
16242  * Field Access Macros:
16243  *
16244  */
16245 /*
16246  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
16247  *
16248  * Test mode disabled
16249  */
16250 #define ALT_USB_HOST_HPRT_PRTTSTCTL_E_DISD 0x0
16251 /*
16252  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
16253  *
16254  * Test_J mode
16255  */
16256 #define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTJ 0x1
16257 /*
16258  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
16259  *
16260  * Test_K mode
16261  */
16262 #define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTK 0x2
16263 /*
16264  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
16265  *
16266  * Test_SE0_NAK mode
16267  */
16268 #define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTSN 0x3
16269 /*
16270  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
16271  *
16272  * Test_Packet mode
16273  */
16274 #define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTPM 0x4
16275 /*
16276  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
16277  *
16278  * Test_force_Enable
16279  */
16280 #define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTFENB 0x5
16281 
16282 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */
16283 #define ALT_USB_HOST_HPRT_PRTTSTCTL_LSB 13
16284 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */
16285 #define ALT_USB_HOST_HPRT_PRTTSTCTL_MSB 16
16286 /* The width in bits of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */
16287 #define ALT_USB_HOST_HPRT_PRTTSTCTL_WIDTH 4
16288 /* The mask used to set the ALT_USB_HOST_HPRT_PRTTSTCTL register field value. */
16289 #define ALT_USB_HOST_HPRT_PRTTSTCTL_SET_MSK 0x0001e000
16290 /* The mask used to clear the ALT_USB_HOST_HPRT_PRTTSTCTL register field value. */
16291 #define ALT_USB_HOST_HPRT_PRTTSTCTL_CLR_MSK 0xfffe1fff
16292 /* The reset value of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */
16293 #define ALT_USB_HOST_HPRT_PRTTSTCTL_RESET 0x0
16294 /* Extracts the ALT_USB_HOST_HPRT_PRTTSTCTL field value from a register. */
16295 #define ALT_USB_HOST_HPRT_PRTTSTCTL_GET(value) (((value) & 0x0001e000) >> 13)
16296 /* Produces a ALT_USB_HOST_HPRT_PRTTSTCTL register field value suitable for setting the register. */
16297 #define ALT_USB_HOST_HPRT_PRTTSTCTL_SET(value) (((value) << 13) & 0x0001e000)
16298 
16299 /*
16300  * Field : prtspd
16301  *
16302  * Port Speed (PrtSpd)
16303  *
16304  * Indicates the speed of the device attached to this port.
16305  *
16306  * 2'b00: High speed
16307  *
16308  * 2'b01: Full speed
16309  *
16310  * 2'b10: Low speed
16311  *
16312  * 2'b11: Reserved
16313  *
16314  * Field Enumeration Values:
16315  *
16316  * Enum | Value | Description
16317  * :-----------------------------------|:------|:------------
16318  * ALT_USB_HOST_HPRT_PRTSPD_E_HIGHSPD | 0x0 | High speed
16319  * ALT_USB_HOST_HPRT_PRTSPD_E_FULLSPD | 0x1 | Full speed
16320  * ALT_USB_HOST_HPRT_PRTSPD_E_LOWSPD | 0x2 | Low speed
16321  * ALT_USB_HOST_HPRT_PRTSPD_E_RSVD | 0x3 | Reserved
16322  *
16323  * Field Access Macros:
16324  *
16325  */
16326 /*
16327  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD
16328  *
16329  * High speed
16330  */
16331 #define ALT_USB_HOST_HPRT_PRTSPD_E_HIGHSPD 0x0
16332 /*
16333  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD
16334  *
16335  * Full speed
16336  */
16337 #define ALT_USB_HOST_HPRT_PRTSPD_E_FULLSPD 0x1
16338 /*
16339  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD
16340  *
16341  * Low speed
16342  */
16343 #define ALT_USB_HOST_HPRT_PRTSPD_E_LOWSPD 0x2
16344 /*
16345  * Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD
16346  *
16347  * Reserved
16348  */
16349 #define ALT_USB_HOST_HPRT_PRTSPD_E_RSVD 0x3
16350 
16351 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTSPD register field. */
16352 #define ALT_USB_HOST_HPRT_PRTSPD_LSB 17
16353 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTSPD register field. */
16354 #define ALT_USB_HOST_HPRT_PRTSPD_MSB 18
16355 /* The width in bits of the ALT_USB_HOST_HPRT_PRTSPD register field. */
16356 #define ALT_USB_HOST_HPRT_PRTSPD_WIDTH 2
16357 /* The mask used to set the ALT_USB_HOST_HPRT_PRTSPD register field value. */
16358 #define ALT_USB_HOST_HPRT_PRTSPD_SET_MSK 0x00060000
16359 /* The mask used to clear the ALT_USB_HOST_HPRT_PRTSPD register field value. */
16360 #define ALT_USB_HOST_HPRT_PRTSPD_CLR_MSK 0xfff9ffff
16361 /* The reset value of the ALT_USB_HOST_HPRT_PRTSPD register field. */
16362 #define ALT_USB_HOST_HPRT_PRTSPD_RESET 0x0
16363 /* Extracts the ALT_USB_HOST_HPRT_PRTSPD field value from a register. */
16364 #define ALT_USB_HOST_HPRT_PRTSPD_GET(value) (((value) & 0x00060000) >> 17)
16365 /* Produces a ALT_USB_HOST_HPRT_PRTSPD register field value suitable for setting the register. */
16366 #define ALT_USB_HOST_HPRT_PRTSPD_SET(value) (((value) << 17) & 0x00060000)
16367 
16368 #ifndef __ASSEMBLY__
16369 /*
16370  * WARNING: The C register and register group struct declarations are provided for
16371  * convenience and illustrative purposes. They should, however, be used with
16372  * caution as the C language standard provides no guarantees about the alignment or
16373  * atomicity of device memory accesses. The recommended practice for writing
16374  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16375  * alt_write_word() functions.
16376  *
16377  * The struct declaration for register ALT_USB_HOST_HPRT.
16378  */
16379 struct ALT_USB_HOST_HPRT_s
16380 {
16381  const uint32_t prtconnsts : 1; /* ALT_USB_HOST_HPRT_PRTCONNSTS */
16382  uint32_t prtconndet : 1; /* ALT_USB_HOST_HPRT_PRTCONNDET */
16383  uint32_t prtena : 1; /* ALT_USB_HOST_HPRT_PRTENA */
16384  uint32_t prtenchng : 1; /* ALT_USB_HOST_HPRT_PRTENCHNG */
16385  const uint32_t prtovrcurract : 1; /* ALT_USB_HOST_HPRT_PRTOVRCURRACT */
16386  uint32_t prtovrcurrchng : 1; /* ALT_USB_HOST_HPRT_PRTOVRCURRCHNG */
16387  uint32_t prtres : 1; /* ALT_USB_HOST_HPRT_PRTRES */
16388  uint32_t prtsusp : 1; /* ALT_USB_HOST_HPRT_PRTSUSP */
16389  uint32_t prtrst : 1; /* ALT_USB_HOST_HPRT_PRTRST */
16390  uint32_t : 1; /* *UNDEFINED* */
16391  const uint32_t prtlnsts : 2; /* ALT_USB_HOST_HPRT_PRTLNSTS */
16392  uint32_t prtpwr : 1; /* ALT_USB_HOST_HPRT_PRTPWR */
16393  uint32_t prttstctl : 4; /* ALT_USB_HOST_HPRT_PRTTSTCTL */
16394  const uint32_t prtspd : 2; /* ALT_USB_HOST_HPRT_PRTSPD */
16395  uint32_t : 13; /* *UNDEFINED* */
16396 };
16397 
16398 /* The typedef declaration for register ALT_USB_HOST_HPRT. */
16399 typedef volatile struct ALT_USB_HOST_HPRT_s ALT_USB_HOST_HPRT_t;
16400 #endif /* __ASSEMBLY__ */
16401 
16402 /* The reset value of the ALT_USB_HOST_HPRT register. */
16403 #define ALT_USB_HOST_HPRT_RESET 0x00000000
16404 /* The byte offset of the ALT_USB_HOST_HPRT register from the beginning of the component. */
16405 #define ALT_USB_HOST_HPRT_OFST 0x40
16406 /* The address of the ALT_USB_HOST_HPRT register. */
16407 #define ALT_USB_HOST_HPRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HPRT_OFST))
16408 
16409 /*
16410  * Register : hcchar0
16411  *
16412  * Host Channel 0 Characteristics Register
16413  *
16414  * Register Layout
16415  *
16416  * Bits | Access | Reset | Description
16417  * :--------|:---------|:------|:-----------------------------
16418  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_MPS
16419  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_EPNUM
16420  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_EPDIR
16421  * [16] | ??? | 0x0 | *UNDEFINED*
16422  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_LSPDDEV
16423  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_EPTYPE
16424  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_EC
16425  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_DEVADDR
16426  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_ODDFRM
16427  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR0_CHDIS
16428  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR0_CHENA
16429  *
16430  */
16431 /*
16432  * Field : mps
16433  *
16434  * Maximum Packet Size (MPS)
16435  *
16436  * Indicates the maximum packet size of the associated endpoint.
16437  *
16438  * Field Access Macros:
16439  *
16440  */
16441 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_MPS register field. */
16442 #define ALT_USB_HOST_HCCHAR0_MPS_LSB 0
16443 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_MPS register field. */
16444 #define ALT_USB_HOST_HCCHAR0_MPS_MSB 10
16445 /* The width in bits of the ALT_USB_HOST_HCCHAR0_MPS register field. */
16446 #define ALT_USB_HOST_HCCHAR0_MPS_WIDTH 11
16447 /* The mask used to set the ALT_USB_HOST_HCCHAR0_MPS register field value. */
16448 #define ALT_USB_HOST_HCCHAR0_MPS_SET_MSK 0x000007ff
16449 /* The mask used to clear the ALT_USB_HOST_HCCHAR0_MPS register field value. */
16450 #define ALT_USB_HOST_HCCHAR0_MPS_CLR_MSK 0xfffff800
16451 /* The reset value of the ALT_USB_HOST_HCCHAR0_MPS register field. */
16452 #define ALT_USB_HOST_HCCHAR0_MPS_RESET 0x0
16453 /* Extracts the ALT_USB_HOST_HCCHAR0_MPS field value from a register. */
16454 #define ALT_USB_HOST_HCCHAR0_MPS_GET(value) (((value) & 0x000007ff) >> 0)
16455 /* Produces a ALT_USB_HOST_HCCHAR0_MPS register field value suitable for setting the register. */
16456 #define ALT_USB_HOST_HCCHAR0_MPS_SET(value) (((value) << 0) & 0x000007ff)
16457 
16458 /*
16459  * Field : epnum
16460  *
16461  * Endpoint Number (EPNum)
16462  *
16463  * Indicates the endpoint number on the device serving as the data
16464  *
16465  * source or sink.
16466  *
16467  * Field Enumeration Values:
16468  *
16469  * Enum | Value | Description
16470  * :-------------------------------------|:------|:--------------
16471  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT0 | 0x0 | End point 0
16472  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT1 | 0x1 | End point 1
16473  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT2 | 0x2 | End point 2
16474  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT3 | 0x3 | End point 3
16475  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT4 | 0x4 | End point 4
16476  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT5 | 0x5 | End point 5
16477  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT6 | 0x6 | End point 6
16478  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT7 | 0x7 | End point 7
16479  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT8 | 0x8 | End point 8
16480  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT9 | 0x9 | End point 9
16481  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT10 | 0xa | End point 10
16482  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT11 | 0xb | End point 11
16483  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT12 | 0xc | End point 12
16484  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT13 | 0xd | End point 13
16485  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT14 | 0xe | End point 14
16486  * ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT15 | 0xf | End point 15
16487  *
16488  * Field Access Macros:
16489  *
16490  */
16491 /*
16492  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16493  *
16494  * End point 0
16495  */
16496 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT0 0x0
16497 /*
16498  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16499  *
16500  * End point 1
16501  */
16502 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT1 0x1
16503 /*
16504  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16505  *
16506  * End point 2
16507  */
16508 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT2 0x2
16509 /*
16510  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16511  *
16512  * End point 3
16513  */
16514 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT3 0x3
16515 /*
16516  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16517  *
16518  * End point 4
16519  */
16520 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT4 0x4
16521 /*
16522  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16523  *
16524  * End point 5
16525  */
16526 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT5 0x5
16527 /*
16528  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16529  *
16530  * End point 6
16531  */
16532 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT6 0x6
16533 /*
16534  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16535  *
16536  * End point 7
16537  */
16538 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT7 0x7
16539 /*
16540  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16541  *
16542  * End point 8
16543  */
16544 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT8 0x8
16545 /*
16546  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16547  *
16548  * End point 9
16549  */
16550 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT9 0x9
16551 /*
16552  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16553  *
16554  * End point 10
16555  */
16556 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT10 0xa
16557 /*
16558  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16559  *
16560  * End point 11
16561  */
16562 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT11 0xb
16563 /*
16564  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16565  *
16566  * End point 12
16567  */
16568 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT12 0xc
16569 /*
16570  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16571  *
16572  * End point 13
16573  */
16574 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT13 0xd
16575 /*
16576  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16577  *
16578  * End point 14
16579  */
16580 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT14 0xe
16581 /*
16582  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
16583  *
16584  * End point 15
16585  */
16586 #define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT15 0xf
16587 
16588 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */
16589 #define ALT_USB_HOST_HCCHAR0_EPNUM_LSB 11
16590 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */
16591 #define ALT_USB_HOST_HCCHAR0_EPNUM_MSB 14
16592 /* The width in bits of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */
16593 #define ALT_USB_HOST_HCCHAR0_EPNUM_WIDTH 4
16594 /* The mask used to set the ALT_USB_HOST_HCCHAR0_EPNUM register field value. */
16595 #define ALT_USB_HOST_HCCHAR0_EPNUM_SET_MSK 0x00007800
16596 /* The mask used to clear the ALT_USB_HOST_HCCHAR0_EPNUM register field value. */
16597 #define ALT_USB_HOST_HCCHAR0_EPNUM_CLR_MSK 0xffff87ff
16598 /* The reset value of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */
16599 #define ALT_USB_HOST_HCCHAR0_EPNUM_RESET 0x0
16600 /* Extracts the ALT_USB_HOST_HCCHAR0_EPNUM field value from a register. */
16601 #define ALT_USB_HOST_HCCHAR0_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
16602 /* Produces a ALT_USB_HOST_HCCHAR0_EPNUM register field value suitable for setting the register. */
16603 #define ALT_USB_HOST_HCCHAR0_EPNUM_SET(value) (((value) << 11) & 0x00007800)
16604 
16605 /*
16606  * Field : epdir
16607  *
16608  * Endpoint Direction (EPDir)
16609  *
16610  * Indicates whether the transaction is IN or OUT.
16611  *
16612  * 1'b0: OUT
16613  *
16614  * 1'b1: IN
16615  *
16616  * Field Enumeration Values:
16617  *
16618  * Enum | Value | Description
16619  * :------------------------------------|:------|:------------
16620  * ALT_USB_HOST_HCCHAR0_EPDIR_E_OUTDIR | 0x0 | OUT
16621  * ALT_USB_HOST_HCCHAR0_EPDIR_E_INDIR | 0x1 | IN
16622  *
16623  * Field Access Macros:
16624  *
16625  */
16626 /*
16627  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPDIR
16628  *
16629  * OUT
16630  */
16631 #define ALT_USB_HOST_HCCHAR0_EPDIR_E_OUTDIR 0x0
16632 /*
16633  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPDIR
16634  *
16635  * IN
16636  */
16637 #define ALT_USB_HOST_HCCHAR0_EPDIR_E_INDIR 0x1
16638 
16639 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */
16640 #define ALT_USB_HOST_HCCHAR0_EPDIR_LSB 15
16641 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */
16642 #define ALT_USB_HOST_HCCHAR0_EPDIR_MSB 15
16643 /* The width in bits of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */
16644 #define ALT_USB_HOST_HCCHAR0_EPDIR_WIDTH 1
16645 /* The mask used to set the ALT_USB_HOST_HCCHAR0_EPDIR register field value. */
16646 #define ALT_USB_HOST_HCCHAR0_EPDIR_SET_MSK 0x00008000
16647 /* The mask used to clear the ALT_USB_HOST_HCCHAR0_EPDIR register field value. */
16648 #define ALT_USB_HOST_HCCHAR0_EPDIR_CLR_MSK 0xffff7fff
16649 /* The reset value of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */
16650 #define ALT_USB_HOST_HCCHAR0_EPDIR_RESET 0x0
16651 /* Extracts the ALT_USB_HOST_HCCHAR0_EPDIR field value from a register. */
16652 #define ALT_USB_HOST_HCCHAR0_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
16653 /* Produces a ALT_USB_HOST_HCCHAR0_EPDIR register field value suitable for setting the register. */
16654 #define ALT_USB_HOST_HCCHAR0_EPDIR_SET(value) (((value) << 15) & 0x00008000)
16655 
16656 /*
16657  * Field : lspddev
16658  *
16659  * Low-Speed Device (LSpdDev)
16660  *
16661  * This field is Set by the application to indicate that this channel is
16662  *
16663  * communicating to a low-speed device.
16664  *
16665  * Field Enumeration Values:
16666  *
16667  * Enum | Value | Description
16668  * :-------------------------------------------|:------|:--------------------------------
16669  * ALT_USB_HOST_HCCHAR0_LSPDDEV_E_NONLOWSPEED | 0x0 | Communicating with non lowspeed
16670  * ALT_USB_HOST_HCCHAR0_LSPDDEV_E_LOWSPEED | 0x1 | Communicating with lowspeed
16671  *
16672  * Field Access Macros:
16673  *
16674  */
16675 /*
16676  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_LSPDDEV
16677  *
16678  * Communicating with non lowspeed
16679  */
16680 #define ALT_USB_HOST_HCCHAR0_LSPDDEV_E_NONLOWSPEED 0x0
16681 /*
16682  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_LSPDDEV
16683  *
16684  * Communicating with lowspeed
16685  */
16686 #define ALT_USB_HOST_HCCHAR0_LSPDDEV_E_LOWSPEED 0x1
16687 
16688 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */
16689 #define ALT_USB_HOST_HCCHAR0_LSPDDEV_LSB 17
16690 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */
16691 #define ALT_USB_HOST_HCCHAR0_LSPDDEV_MSB 17
16692 /* The width in bits of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */
16693 #define ALT_USB_HOST_HCCHAR0_LSPDDEV_WIDTH 1
16694 /* The mask used to set the ALT_USB_HOST_HCCHAR0_LSPDDEV register field value. */
16695 #define ALT_USB_HOST_HCCHAR0_LSPDDEV_SET_MSK 0x00020000
16696 /* The mask used to clear the ALT_USB_HOST_HCCHAR0_LSPDDEV register field value. */
16697 #define ALT_USB_HOST_HCCHAR0_LSPDDEV_CLR_MSK 0xfffdffff
16698 /* The reset value of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */
16699 #define ALT_USB_HOST_HCCHAR0_LSPDDEV_RESET 0x0
16700 /* Extracts the ALT_USB_HOST_HCCHAR0_LSPDDEV field value from a register. */
16701 #define ALT_USB_HOST_HCCHAR0_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
16702 /* Produces a ALT_USB_HOST_HCCHAR0_LSPDDEV register field value suitable for setting the register. */
16703 #define ALT_USB_HOST_HCCHAR0_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
16704 
16705 /*
16706  * Field : eptype
16707  *
16708  * Endpoint Type (EPType)
16709  *
16710  * Indicates the transfer type selected.
16711  *
16712  * 2'b00: Control
16713  *
16714  * 2'b01: Isochronous
16715  *
16716  * 2'b10: Bulk
16717  *
16718  * 2'b11: Interrupt
16719  *
16720  * Field Enumeration Values:
16721  *
16722  * Enum | Value | Description
16723  * :-------------------------------------|:------|:------------
16724  * ALT_USB_HOST_HCCHAR0_EPTYPE_E_CTL | 0x0 | Control
16725  * ALT_USB_HOST_HCCHAR0_EPTYPE_E_ISOC | 0x1 | Isochronous
16726  * ALT_USB_HOST_HCCHAR0_EPTYPE_E_BULK | 0x2 | Bulk
16727  * ALT_USB_HOST_HCCHAR0_EPTYPE_E_INTERR | 0x3 | Interrupt
16728  *
16729  * Field Access Macros:
16730  *
16731  */
16732 /*
16733  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE
16734  *
16735  * Control
16736  */
16737 #define ALT_USB_HOST_HCCHAR0_EPTYPE_E_CTL 0x0
16738 /*
16739  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE
16740  *
16741  * Isochronous
16742  */
16743 #define ALT_USB_HOST_HCCHAR0_EPTYPE_E_ISOC 0x1
16744 /*
16745  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE
16746  *
16747  * Bulk
16748  */
16749 #define ALT_USB_HOST_HCCHAR0_EPTYPE_E_BULK 0x2
16750 /*
16751  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE
16752  *
16753  * Interrupt
16754  */
16755 #define ALT_USB_HOST_HCCHAR0_EPTYPE_E_INTERR 0x3
16756 
16757 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */
16758 #define ALT_USB_HOST_HCCHAR0_EPTYPE_LSB 18
16759 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */
16760 #define ALT_USB_HOST_HCCHAR0_EPTYPE_MSB 19
16761 /* The width in bits of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */
16762 #define ALT_USB_HOST_HCCHAR0_EPTYPE_WIDTH 2
16763 /* The mask used to set the ALT_USB_HOST_HCCHAR0_EPTYPE register field value. */
16764 #define ALT_USB_HOST_HCCHAR0_EPTYPE_SET_MSK 0x000c0000
16765 /* The mask used to clear the ALT_USB_HOST_HCCHAR0_EPTYPE register field value. */
16766 #define ALT_USB_HOST_HCCHAR0_EPTYPE_CLR_MSK 0xfff3ffff
16767 /* The reset value of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */
16768 #define ALT_USB_HOST_HCCHAR0_EPTYPE_RESET 0x0
16769 /* Extracts the ALT_USB_HOST_HCCHAR0_EPTYPE field value from a register. */
16770 #define ALT_USB_HOST_HCCHAR0_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
16771 /* Produces a ALT_USB_HOST_HCCHAR0_EPTYPE register field value suitable for setting the register. */
16772 #define ALT_USB_HOST_HCCHAR0_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
16773 
16774 /*
16775  * Field : ec
16776  *
16777  * Multi Count (MC) / Error Count (EC)
16778  *
16779  * When the Split Enable bit of the Host Channel-n Split Control
16780  *
16781  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
16782  *
16783  * the host the number of transactions that must be executed per
16784  *
16785  * microframe For this periodic endpoint. For non periodic transfers,
16786  *
16787  * this field is used only in DMA mode, and specifies the number
16788  *
16789  * packets to be fetched For this channel before the internal DMA
16790  *
16791  * engine changes arbitration.
16792  *
16793  * 2'b00: Reserved This field yields undefined results.
16794  *
16795  * 2'b01: 1 transaction
16796  *
16797  * 2'b10: 2 transactions to be issued For this endpoint per
16798  *
16799  * microframe
16800  *
16801  * 2'b11: 3 transactions to be issued For this endpoint per
16802  *
16803  * microframe
16804  *
16805  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
16806  *
16807  * number of immediate retries to be performed For a periodic split
16808  *
16809  * transactions on transaction errors. This field must be Set to at
16810  *
16811  * least 2'b01.
16812  *
16813  * Field Enumeration Values:
16814  *
16815  * Enum | Value | Description
16816  * :-------------------------------------|:------|:----------------------------------------------
16817  * ALT_USB_HOST_HCCHAR0_EC_E_RSVD | 0x0 | Reserved This field yields undefined results
16818  * ALT_USB_HOST_HCCHAR0_EC_E_TRANSONE | 0x1 | 1 transaction
16819  * ALT_USB_HOST_HCCHAR0_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
16820  * : | | per microframe
16821  * ALT_USB_HOST_HCCHAR0_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
16822  * : | | per microframe
16823  *
16824  * Field Access Macros:
16825  *
16826  */
16827 /*
16828  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC
16829  *
16830  * Reserved This field yields undefined results
16831  */
16832 #define ALT_USB_HOST_HCCHAR0_EC_E_RSVD 0x0
16833 /*
16834  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC
16835  *
16836  * 1 transaction
16837  */
16838 #define ALT_USB_HOST_HCCHAR0_EC_E_TRANSONE 0x1
16839 /*
16840  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC
16841  *
16842  * 2 transactions to be issued for this endpoint per microframe
16843  */
16844 #define ALT_USB_HOST_HCCHAR0_EC_E_TRANSTWO 0x2
16845 /*
16846  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC
16847  *
16848  * 3 transactions to be issued for this endpoint per microframe
16849  */
16850 #define ALT_USB_HOST_HCCHAR0_EC_E_TRANSTHREE 0x3
16851 
16852 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EC register field. */
16853 #define ALT_USB_HOST_HCCHAR0_EC_LSB 20
16854 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EC register field. */
16855 #define ALT_USB_HOST_HCCHAR0_EC_MSB 21
16856 /* The width in bits of the ALT_USB_HOST_HCCHAR0_EC register field. */
16857 #define ALT_USB_HOST_HCCHAR0_EC_WIDTH 2
16858 /* The mask used to set the ALT_USB_HOST_HCCHAR0_EC register field value. */
16859 #define ALT_USB_HOST_HCCHAR0_EC_SET_MSK 0x00300000
16860 /* The mask used to clear the ALT_USB_HOST_HCCHAR0_EC register field value. */
16861 #define ALT_USB_HOST_HCCHAR0_EC_CLR_MSK 0xffcfffff
16862 /* The reset value of the ALT_USB_HOST_HCCHAR0_EC register field. */
16863 #define ALT_USB_HOST_HCCHAR0_EC_RESET 0x0
16864 /* Extracts the ALT_USB_HOST_HCCHAR0_EC field value from a register. */
16865 #define ALT_USB_HOST_HCCHAR0_EC_GET(value) (((value) & 0x00300000) >> 20)
16866 /* Produces a ALT_USB_HOST_HCCHAR0_EC register field value suitable for setting the register. */
16867 #define ALT_USB_HOST_HCCHAR0_EC_SET(value) (((value) << 20) & 0x00300000)
16868 
16869 /*
16870  * Field : devaddr
16871  *
16872  * Device Address (DevAddr)
16873  *
16874  * This field selects the specific device serving as the data source
16875  *
16876  * or sink.
16877  *
16878  * Field Access Macros:
16879  *
16880  */
16881 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */
16882 #define ALT_USB_HOST_HCCHAR0_DEVADDR_LSB 22
16883 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */
16884 #define ALT_USB_HOST_HCCHAR0_DEVADDR_MSB 28
16885 /* The width in bits of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */
16886 #define ALT_USB_HOST_HCCHAR0_DEVADDR_WIDTH 7
16887 /* The mask used to set the ALT_USB_HOST_HCCHAR0_DEVADDR register field value. */
16888 #define ALT_USB_HOST_HCCHAR0_DEVADDR_SET_MSK 0x1fc00000
16889 /* The mask used to clear the ALT_USB_HOST_HCCHAR0_DEVADDR register field value. */
16890 #define ALT_USB_HOST_HCCHAR0_DEVADDR_CLR_MSK 0xe03fffff
16891 /* The reset value of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */
16892 #define ALT_USB_HOST_HCCHAR0_DEVADDR_RESET 0x0
16893 /* Extracts the ALT_USB_HOST_HCCHAR0_DEVADDR field value from a register. */
16894 #define ALT_USB_HOST_HCCHAR0_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
16895 /* Produces a ALT_USB_HOST_HCCHAR0_DEVADDR register field value suitable for setting the register. */
16896 #define ALT_USB_HOST_HCCHAR0_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
16897 
16898 /*
16899  * Field : oddfrm
16900  *
16901  * Odd Frame (OddFrm)
16902  *
16903  * This field is set (reset) by the application to indicate that the OTG host must
16904  * perform
16905  *
16906  * a transfer in an odd (micro)frame. This field is applicable for only periodic
16907  *
16908  * (isochronous and interrupt) transactions.
16909  *
16910  * 1'b0: Even (micro)frame
16911  *
16912  * 1'b1: Odd (micro)frame
16913  *
16914  * Field Access Macros:
16915  *
16916  */
16917 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_ODDFRM register field. */
16918 #define ALT_USB_HOST_HCCHAR0_ODDFRM_LSB 29
16919 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_ODDFRM register field. */
16920 #define ALT_USB_HOST_HCCHAR0_ODDFRM_MSB 29
16921 /* The width in bits of the ALT_USB_HOST_HCCHAR0_ODDFRM register field. */
16922 #define ALT_USB_HOST_HCCHAR0_ODDFRM_WIDTH 1
16923 /* The mask used to set the ALT_USB_HOST_HCCHAR0_ODDFRM register field value. */
16924 #define ALT_USB_HOST_HCCHAR0_ODDFRM_SET_MSK 0x20000000
16925 /* The mask used to clear the ALT_USB_HOST_HCCHAR0_ODDFRM register field value. */
16926 #define ALT_USB_HOST_HCCHAR0_ODDFRM_CLR_MSK 0xdfffffff
16927 /* The reset value of the ALT_USB_HOST_HCCHAR0_ODDFRM register field. */
16928 #define ALT_USB_HOST_HCCHAR0_ODDFRM_RESET 0x0
16929 /* Extracts the ALT_USB_HOST_HCCHAR0_ODDFRM field value from a register. */
16930 #define ALT_USB_HOST_HCCHAR0_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
16931 /* Produces a ALT_USB_HOST_HCCHAR0_ODDFRM register field value suitable for setting the register. */
16932 #define ALT_USB_HOST_HCCHAR0_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
16933 
16934 /*
16935  * Field : chdis
16936  *
16937  * Channel Disable (ChDis)
16938  *
16939  * The application sets this bit to stop transmitting/receiving data
16940  *
16941  * on a channel, even before the transfer For that channel is
16942  *
16943  * complete. The application must wait For the Channel Disabled
16944  *
16945  * interrupt before treating the channel as disabled.
16946  *
16947  * Field Enumeration Values:
16948  *
16949  * Enum | Value | Description
16950  * :-----------------------------------|:------|:---------------------------------
16951  * ALT_USB_HOST_HCCHAR0_CHDIS_E_INACT | 0x0 | No activity
16952  * ALT_USB_HOST_HCCHAR0_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving data
16953  *
16954  * Field Access Macros:
16955  *
16956  */
16957 /*
16958  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHDIS
16959  *
16960  * No activity
16961  */
16962 #define ALT_USB_HOST_HCCHAR0_CHDIS_E_INACT 0x0
16963 /*
16964  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHDIS
16965  *
16966  * Stop transmitting/receiving data
16967  */
16968 #define ALT_USB_HOST_HCCHAR0_CHDIS_E_ACT 0x1
16969 
16970 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */
16971 #define ALT_USB_HOST_HCCHAR0_CHDIS_LSB 30
16972 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */
16973 #define ALT_USB_HOST_HCCHAR0_CHDIS_MSB 30
16974 /* The width in bits of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */
16975 #define ALT_USB_HOST_HCCHAR0_CHDIS_WIDTH 1
16976 /* The mask used to set the ALT_USB_HOST_HCCHAR0_CHDIS register field value. */
16977 #define ALT_USB_HOST_HCCHAR0_CHDIS_SET_MSK 0x40000000
16978 /* The mask used to clear the ALT_USB_HOST_HCCHAR0_CHDIS register field value. */
16979 #define ALT_USB_HOST_HCCHAR0_CHDIS_CLR_MSK 0xbfffffff
16980 /* The reset value of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */
16981 #define ALT_USB_HOST_HCCHAR0_CHDIS_RESET 0x0
16982 /* Extracts the ALT_USB_HOST_HCCHAR0_CHDIS field value from a register. */
16983 #define ALT_USB_HOST_HCCHAR0_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
16984 /* Produces a ALT_USB_HOST_HCCHAR0_CHDIS register field value suitable for setting the register. */
16985 #define ALT_USB_HOST_HCCHAR0_CHDIS_SET(value) (((value) << 30) & 0x40000000)
16986 
16987 /*
16988  * Field : chena
16989  *
16990  * Channel Enable (ChEna)
16991  *
16992  * When Scatter/Gather mode is enabled
16993  *
16994  * 1'b0: Indicates that the descriptor structure is not yet ready.
16995  *
16996  * 1'b1: Indicates that the descriptor structure and data buffer with
16997  *
16998  * data is setup and this channel can access the descriptor.
16999  *
17000  * When Scatter/Gather mode is disabled
17001  *
17002  * This field is set by the application and cleared by the OTG host.
17003  *
17004  * 1'b0: Channel disabled
17005  *
17006  * 1'b1: Channel enabled
17007  *
17008  * Field Enumeration Values:
17009  *
17010  * Enum | Value | Description
17011  * :------------------------------------|:------|:-------------------------------------------------
17012  * ALT_USB_HOST_HCCHAR0_CHENA_E_NOTRDY | 0x0 | Indicates that the descriptor structure is not
17013  * : | | yet ready
17014  * ALT_USB_HOST_HCCHAR0_CHENA_E_RDY | 0x1 | Indicates that the descriptor structure and data
17015  * : | | buffer with data is setup and this channel can
17016  * : | | access the descriptor
17017  *
17018  * Field Access Macros:
17019  *
17020  */
17021 /*
17022  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHENA
17023  *
17024  * Indicates that the descriptor structure is not yet ready
17025  */
17026 #define ALT_USB_HOST_HCCHAR0_CHENA_E_NOTRDY 0x0
17027 /*
17028  * Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHENA
17029  *
17030  * Indicates that the descriptor structure and data buffer with data is setup and
17031  * this channel can access the descriptor
17032  */
17033 #define ALT_USB_HOST_HCCHAR0_CHENA_E_RDY 0x1
17034 
17035 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_CHENA register field. */
17036 #define ALT_USB_HOST_HCCHAR0_CHENA_LSB 31
17037 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_CHENA register field. */
17038 #define ALT_USB_HOST_HCCHAR0_CHENA_MSB 31
17039 /* The width in bits of the ALT_USB_HOST_HCCHAR0_CHENA register field. */
17040 #define ALT_USB_HOST_HCCHAR0_CHENA_WIDTH 1
17041 /* The mask used to set the ALT_USB_HOST_HCCHAR0_CHENA register field value. */
17042 #define ALT_USB_HOST_HCCHAR0_CHENA_SET_MSK 0x80000000
17043 /* The mask used to clear the ALT_USB_HOST_HCCHAR0_CHENA register field value. */
17044 #define ALT_USB_HOST_HCCHAR0_CHENA_CLR_MSK 0x7fffffff
17045 /* The reset value of the ALT_USB_HOST_HCCHAR0_CHENA register field. */
17046 #define ALT_USB_HOST_HCCHAR0_CHENA_RESET 0x0
17047 /* Extracts the ALT_USB_HOST_HCCHAR0_CHENA field value from a register. */
17048 #define ALT_USB_HOST_HCCHAR0_CHENA_GET(value) (((value) & 0x80000000) >> 31)
17049 /* Produces a ALT_USB_HOST_HCCHAR0_CHENA register field value suitable for setting the register. */
17050 #define ALT_USB_HOST_HCCHAR0_CHENA_SET(value) (((value) << 31) & 0x80000000)
17051 
17052 #ifndef __ASSEMBLY__
17053 /*
17054  * WARNING: The C register and register group struct declarations are provided for
17055  * convenience and illustrative purposes. They should, however, be used with
17056  * caution as the C language standard provides no guarantees about the alignment or
17057  * atomicity of device memory accesses. The recommended practice for writing
17058  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17059  * alt_write_word() functions.
17060  *
17061  * The struct declaration for register ALT_USB_HOST_HCCHAR0.
17062  */
17063 struct ALT_USB_HOST_HCCHAR0_s
17064 {
17065  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR0_MPS */
17066  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR0_EPNUM */
17067  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR0_EPDIR */
17068  uint32_t : 1; /* *UNDEFINED* */
17069  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR0_LSPDDEV */
17070  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR0_EPTYPE */
17071  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR0_EC */
17072  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR0_DEVADDR */
17073  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR0_ODDFRM */
17074  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR0_CHDIS */
17075  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR0_CHENA */
17076 };
17077 
17078 /* The typedef declaration for register ALT_USB_HOST_HCCHAR0. */
17079 typedef volatile struct ALT_USB_HOST_HCCHAR0_s ALT_USB_HOST_HCCHAR0_t;
17080 #endif /* __ASSEMBLY__ */
17081 
17082 /* The reset value of the ALT_USB_HOST_HCCHAR0 register. */
17083 #define ALT_USB_HOST_HCCHAR0_RESET 0x00000000
17084 /* The byte offset of the ALT_USB_HOST_HCCHAR0 register from the beginning of the component. */
17085 #define ALT_USB_HOST_HCCHAR0_OFST 0x100
17086 /* The address of the ALT_USB_HOST_HCCHAR0 register. */
17087 #define ALT_USB_HOST_HCCHAR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR0_OFST))
17088 
17089 /*
17090  * Register : hcsplt0
17091  *
17092  * Host Channel 0 Split Control Register
17093  *
17094  * Register Layout
17095  *
17096  * Bits | Access | Reset | Description
17097  * :--------|:-------|:------|:------------------------------
17098  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT0_PRTADDR
17099  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT0_HUBADDR
17100  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT0_XACTPOS
17101  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT0_COMPSPLT
17102  * [30:17] | ??? | 0x0 | *UNDEFINED*
17103  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT0_SPLTENA
17104  *
17105  */
17106 /*
17107  * Field : prtaddr
17108  *
17109  * Port Address (PrtAddr)
17110  *
17111  * This field is the port number of the recipient transaction
17112  *
17113  * translator.
17114  *
17115  * Field Access Macros:
17116  *
17117  */
17118 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */
17119 #define ALT_USB_HOST_HCSPLT0_PRTADDR_LSB 0
17120 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */
17121 #define ALT_USB_HOST_HCSPLT0_PRTADDR_MSB 6
17122 /* The width in bits of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */
17123 #define ALT_USB_HOST_HCSPLT0_PRTADDR_WIDTH 7
17124 /* The mask used to set the ALT_USB_HOST_HCSPLT0_PRTADDR register field value. */
17125 #define ALT_USB_HOST_HCSPLT0_PRTADDR_SET_MSK 0x0000007f
17126 /* The mask used to clear the ALT_USB_HOST_HCSPLT0_PRTADDR register field value. */
17127 #define ALT_USB_HOST_HCSPLT0_PRTADDR_CLR_MSK 0xffffff80
17128 /* The reset value of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */
17129 #define ALT_USB_HOST_HCSPLT0_PRTADDR_RESET 0x0
17130 /* Extracts the ALT_USB_HOST_HCSPLT0_PRTADDR field value from a register. */
17131 #define ALT_USB_HOST_HCSPLT0_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
17132 /* Produces a ALT_USB_HOST_HCSPLT0_PRTADDR register field value suitable for setting the register. */
17133 #define ALT_USB_HOST_HCSPLT0_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
17134 
17135 /*
17136  * Field : hubaddr
17137  *
17138  * Hub Address (HubAddr)
17139  *
17140  * This field holds the device address of the transaction translator's
17141  *
17142  * hub.
17143  *
17144  * Field Access Macros:
17145  *
17146  */
17147 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */
17148 #define ALT_USB_HOST_HCSPLT0_HUBADDR_LSB 7
17149 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */
17150 #define ALT_USB_HOST_HCSPLT0_HUBADDR_MSB 13
17151 /* The width in bits of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */
17152 #define ALT_USB_HOST_HCSPLT0_HUBADDR_WIDTH 7
17153 /* The mask used to set the ALT_USB_HOST_HCSPLT0_HUBADDR register field value. */
17154 #define ALT_USB_HOST_HCSPLT0_HUBADDR_SET_MSK 0x00003f80
17155 /* The mask used to clear the ALT_USB_HOST_HCSPLT0_HUBADDR register field value. */
17156 #define ALT_USB_HOST_HCSPLT0_HUBADDR_CLR_MSK 0xffffc07f
17157 /* The reset value of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */
17158 #define ALT_USB_HOST_HCSPLT0_HUBADDR_RESET 0x0
17159 /* Extracts the ALT_USB_HOST_HCSPLT0_HUBADDR field value from a register. */
17160 #define ALT_USB_HOST_HCSPLT0_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
17161 /* Produces a ALT_USB_HOST_HCSPLT0_HUBADDR register field value suitable for setting the register. */
17162 #define ALT_USB_HOST_HCSPLT0_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
17163 
17164 /*
17165  * Field : xactpos
17166  *
17167  * Transaction Position (XactPos)
17168  *
17169  * This field is used to determine whether to send all, first, middle,
17170  *
17171  * or last payloads with each OUT transaction.
17172  *
17173  * 2'b11: All. This is the entire data payload is of this transaction
17174  *
17175  * (which is less than or equal to 188 bytes).
17176  *
17177  * 2'b10: Begin. This is the first data payload of this transaction
17178  *
17179  * (which is larger than 188 bytes).
17180  *
17181  * 2'b00: Mid. This is the middle payload of this transaction
17182  *
17183  * (which is larger than 188 bytes).
17184  *
17185  * 2'b01: End. This is the last payload of this transaction (which
17186  *
17187  * is larger than 188 bytes).
17188  *
17189  * Field Enumeration Values:
17190  *
17191  * Enum | Value | Description
17192  * :--------------------------------------|:------|:------------------------------------------------
17193  * ALT_USB_HOST_HCSPLT0_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
17194  * : | | transaction (which is larger than 188 bytes)
17195  * ALT_USB_HOST_HCSPLT0_XACTPOS_E_END | 0x1 | End. This is the last payload of this
17196  * : | | transaction (which is larger than 188 bytes)
17197  * ALT_USB_HOST_HCSPLT0_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
17198  * : | | transaction (which is larger than 188 bytes)
17199  * ALT_USB_HOST_HCSPLT0_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
17200  * : | | transaction (which is less than or equal to 188
17201  * : | | bytes)
17202  *
17203  * Field Access Macros:
17204  *
17205  */
17206 /*
17207  * Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS
17208  *
17209  * Mid. This is the middle payload of this transaction (which is larger than 188
17210  * bytes)
17211  */
17212 #define ALT_USB_HOST_HCSPLT0_XACTPOS_E_MIDDLE 0x0
17213 /*
17214  * Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS
17215  *
17216  * End. This is the last payload of this transaction (which is larger than 188
17217  * bytes)
17218  */
17219 #define ALT_USB_HOST_HCSPLT0_XACTPOS_E_END 0x1
17220 /*
17221  * Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS
17222  *
17223  * Begin. This is the first data payload of this transaction (which is larger than
17224  * 188 bytes)
17225  */
17226 #define ALT_USB_HOST_HCSPLT0_XACTPOS_E_BEGIN 0x2
17227 /*
17228  * Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS
17229  *
17230  * All. This is the entire data payload is of this transaction (which is less than
17231  * or equal to 188 bytes)
17232  */
17233 #define ALT_USB_HOST_HCSPLT0_XACTPOS_E_ALL 0x3
17234 
17235 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */
17236 #define ALT_USB_HOST_HCSPLT0_XACTPOS_LSB 14
17237 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */
17238 #define ALT_USB_HOST_HCSPLT0_XACTPOS_MSB 15
17239 /* The width in bits of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */
17240 #define ALT_USB_HOST_HCSPLT0_XACTPOS_WIDTH 2
17241 /* The mask used to set the ALT_USB_HOST_HCSPLT0_XACTPOS register field value. */
17242 #define ALT_USB_HOST_HCSPLT0_XACTPOS_SET_MSK 0x0000c000
17243 /* The mask used to clear the ALT_USB_HOST_HCSPLT0_XACTPOS register field value. */
17244 #define ALT_USB_HOST_HCSPLT0_XACTPOS_CLR_MSK 0xffff3fff
17245 /* The reset value of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */
17246 #define ALT_USB_HOST_HCSPLT0_XACTPOS_RESET 0x0
17247 /* Extracts the ALT_USB_HOST_HCSPLT0_XACTPOS field value from a register. */
17248 #define ALT_USB_HOST_HCSPLT0_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
17249 /* Produces a ALT_USB_HOST_HCSPLT0_XACTPOS register field value suitable for setting the register. */
17250 #define ALT_USB_HOST_HCSPLT0_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
17251 
17252 /*
17253  * Field : compsplt
17254  *
17255  * Do Complete Split (CompSplt)
17256  *
17257  * The application sets this field to request the OTG host to perform
17258  *
17259  * a complete split transaction.
17260  *
17261  * Field Enumeration Values:
17262  *
17263  * Enum | Value | Description
17264  * :----------------------------------------|:------|:---------------------
17265  * ALT_USB_HOST_HCSPLT0_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
17266  * ALT_USB_HOST_HCSPLT0_COMPSPLT_E_SPLIT | 0x1 | Split transaction
17267  *
17268  * Field Access Macros:
17269  *
17270  */
17271 /*
17272  * Enumerated value for register field ALT_USB_HOST_HCSPLT0_COMPSPLT
17273  *
17274  * No split transaction
17275  */
17276 #define ALT_USB_HOST_HCSPLT0_COMPSPLT_E_NOSPLIT 0x0
17277 /*
17278  * Enumerated value for register field ALT_USB_HOST_HCSPLT0_COMPSPLT
17279  *
17280  * Split transaction
17281  */
17282 #define ALT_USB_HOST_HCSPLT0_COMPSPLT_E_SPLIT 0x1
17283 
17284 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */
17285 #define ALT_USB_HOST_HCSPLT0_COMPSPLT_LSB 16
17286 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */
17287 #define ALT_USB_HOST_HCSPLT0_COMPSPLT_MSB 16
17288 /* The width in bits of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */
17289 #define ALT_USB_HOST_HCSPLT0_COMPSPLT_WIDTH 1
17290 /* The mask used to set the ALT_USB_HOST_HCSPLT0_COMPSPLT register field value. */
17291 #define ALT_USB_HOST_HCSPLT0_COMPSPLT_SET_MSK 0x00010000
17292 /* The mask used to clear the ALT_USB_HOST_HCSPLT0_COMPSPLT register field value. */
17293 #define ALT_USB_HOST_HCSPLT0_COMPSPLT_CLR_MSK 0xfffeffff
17294 /* The reset value of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */
17295 #define ALT_USB_HOST_HCSPLT0_COMPSPLT_RESET 0x0
17296 /* Extracts the ALT_USB_HOST_HCSPLT0_COMPSPLT field value from a register. */
17297 #define ALT_USB_HOST_HCSPLT0_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
17298 /* Produces a ALT_USB_HOST_HCSPLT0_COMPSPLT register field value suitable for setting the register. */
17299 #define ALT_USB_HOST_HCSPLT0_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
17300 
17301 /*
17302  * Field : spltena
17303  *
17304  * Split Enable (SpltEna)
17305  *
17306  * The application sets this field to indicate that this channel is
17307  *
17308  * enabled to perform split transactions.
17309  *
17310  * Field Enumeration Values:
17311  *
17312  * Enum | Value | Description
17313  * :------------------------------------|:------|:------------------
17314  * ALT_USB_HOST_HCSPLT0_SPLTENA_E_DISD | 0x0 | Split not enabled
17315  * ALT_USB_HOST_HCSPLT0_SPLTENA_E_END | 0x1 | Split enabled
17316  *
17317  * Field Access Macros:
17318  *
17319  */
17320 /*
17321  * Enumerated value for register field ALT_USB_HOST_HCSPLT0_SPLTENA
17322  *
17323  * Split not enabled
17324  */
17325 #define ALT_USB_HOST_HCSPLT0_SPLTENA_E_DISD 0x0
17326 /*
17327  * Enumerated value for register field ALT_USB_HOST_HCSPLT0_SPLTENA
17328  *
17329  * Split enabled
17330  */
17331 #define ALT_USB_HOST_HCSPLT0_SPLTENA_E_END 0x1
17332 
17333 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */
17334 #define ALT_USB_HOST_HCSPLT0_SPLTENA_LSB 31
17335 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */
17336 #define ALT_USB_HOST_HCSPLT0_SPLTENA_MSB 31
17337 /* The width in bits of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */
17338 #define ALT_USB_HOST_HCSPLT0_SPLTENA_WIDTH 1
17339 /* The mask used to set the ALT_USB_HOST_HCSPLT0_SPLTENA register field value. */
17340 #define ALT_USB_HOST_HCSPLT0_SPLTENA_SET_MSK 0x80000000
17341 /* The mask used to clear the ALT_USB_HOST_HCSPLT0_SPLTENA register field value. */
17342 #define ALT_USB_HOST_HCSPLT0_SPLTENA_CLR_MSK 0x7fffffff
17343 /* The reset value of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */
17344 #define ALT_USB_HOST_HCSPLT0_SPLTENA_RESET 0x0
17345 /* Extracts the ALT_USB_HOST_HCSPLT0_SPLTENA field value from a register. */
17346 #define ALT_USB_HOST_HCSPLT0_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
17347 /* Produces a ALT_USB_HOST_HCSPLT0_SPLTENA register field value suitable for setting the register. */
17348 #define ALT_USB_HOST_HCSPLT0_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
17349 
17350 #ifndef __ASSEMBLY__
17351 /*
17352  * WARNING: The C register and register group struct declarations are provided for
17353  * convenience and illustrative purposes. They should, however, be used with
17354  * caution as the C language standard provides no guarantees about the alignment or
17355  * atomicity of device memory accesses. The recommended practice for writing
17356  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17357  * alt_write_word() functions.
17358  *
17359  * The struct declaration for register ALT_USB_HOST_HCSPLT0.
17360  */
17361 struct ALT_USB_HOST_HCSPLT0_s
17362 {
17363  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT0_PRTADDR */
17364  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT0_HUBADDR */
17365  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT0_XACTPOS */
17366  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT0_COMPSPLT */
17367  uint32_t : 14; /* *UNDEFINED* */
17368  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT0_SPLTENA */
17369 };
17370 
17371 /* The typedef declaration for register ALT_USB_HOST_HCSPLT0. */
17372 typedef volatile struct ALT_USB_HOST_HCSPLT0_s ALT_USB_HOST_HCSPLT0_t;
17373 #endif /* __ASSEMBLY__ */
17374 
17375 /* The reset value of the ALT_USB_HOST_HCSPLT0 register. */
17376 #define ALT_USB_HOST_HCSPLT0_RESET 0x00000000
17377 /* The byte offset of the ALT_USB_HOST_HCSPLT0 register from the beginning of the component. */
17378 #define ALT_USB_HOST_HCSPLT0_OFST 0x104
17379 /* The address of the ALT_USB_HOST_HCSPLT0 register. */
17380 #define ALT_USB_HOST_HCSPLT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT0_OFST))
17381 
17382 /*
17383  * Register : hcint0
17384  *
17385  * Host Channel 0 Interrupt Register
17386  *
17387  * Register Layout
17388  *
17389  * Bits | Access | Reset | Description
17390  * :--------|:-------|:------|:--------------------------------------
17391  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT0_XFERCOMPL
17392  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT0_CHHLTD
17393  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT0_AHBERR
17394  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT0_STALL
17395  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT0_NAK
17396  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT0_ACK
17397  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT0_NYET
17398  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT0_XACTERR
17399  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT0_BBLERR
17400  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT0_FRMOVRUN
17401  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT0_DATATGLERR
17402  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT0_BNAINTR
17403  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT0_XCS_XACT_ERR
17404  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR
17405  * [31:14] | ??? | 0x0 | *UNDEFINED*
17406  *
17407  */
17408 /*
17409  * Field : xfercompl
17410  *
17411  * Transfer Completed (XferCompl)
17412  *
17413  * Transfer completed normally without any errors.This bit can be set only by the
17414  * core and the application should write 1 to clear it.
17415  *
17416  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
17417  *
17418  * completed with IOC bit set in its descriptor.
17419  *
17420  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
17421  * without
17422  *
17423  * any errors.
17424  *
17425  * Field Enumeration Values:
17426  *
17427  * Enum | Value | Description
17428  * :--------------------------------------|:------|:-----------------------------------------------
17429  * ALT_USB_HOST_HCINT0_XFERCOMPL_E_INACT | 0x0 | No transfer
17430  * ALT_USB_HOST_HCINT0_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
17431  *
17432  * Field Access Macros:
17433  *
17434  */
17435 /*
17436  * Enumerated value for register field ALT_USB_HOST_HCINT0_XFERCOMPL
17437  *
17438  * No transfer
17439  */
17440 #define ALT_USB_HOST_HCINT0_XFERCOMPL_E_INACT 0x0
17441 /*
17442  * Enumerated value for register field ALT_USB_HOST_HCINT0_XFERCOMPL
17443  *
17444  * Transfer completed normally without any errors
17445  */
17446 #define ALT_USB_HOST_HCINT0_XFERCOMPL_E_ACT 0x1
17447 
17448 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */
17449 #define ALT_USB_HOST_HCINT0_XFERCOMPL_LSB 0
17450 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */
17451 #define ALT_USB_HOST_HCINT0_XFERCOMPL_MSB 0
17452 /* The width in bits of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */
17453 #define ALT_USB_HOST_HCINT0_XFERCOMPL_WIDTH 1
17454 /* The mask used to set the ALT_USB_HOST_HCINT0_XFERCOMPL register field value. */
17455 #define ALT_USB_HOST_HCINT0_XFERCOMPL_SET_MSK 0x00000001
17456 /* The mask used to clear the ALT_USB_HOST_HCINT0_XFERCOMPL register field value. */
17457 #define ALT_USB_HOST_HCINT0_XFERCOMPL_CLR_MSK 0xfffffffe
17458 /* The reset value of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */
17459 #define ALT_USB_HOST_HCINT0_XFERCOMPL_RESET 0x0
17460 /* Extracts the ALT_USB_HOST_HCINT0_XFERCOMPL field value from a register. */
17461 #define ALT_USB_HOST_HCINT0_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
17462 /* Produces a ALT_USB_HOST_HCINT0_XFERCOMPL register field value suitable for setting the register. */
17463 #define ALT_USB_HOST_HCINT0_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
17464 
17465 /*
17466  * Field : chhltd
17467  *
17468  * Channel Halted (ChHltd)
17469  *
17470  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
17471  * either because of any USB transaction error or in response to disable request by
17472  * the application or because of a completed transfer.
17473  *
17474  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
17475  * the following
17476  *
17477  * . EOL being set in descriptor
17478  *
17479  * . AHB error
17480  *
17481  * . Excessive transaction errors
17482  *
17483  * . Babble
17484  *
17485  * . Stall
17486  *
17487  * Field Enumeration Values:
17488  *
17489  * Enum | Value | Description
17490  * :-----------------------------------|:------|:-------------------
17491  * ALT_USB_HOST_HCINT0_CHHLTD_E_INACT | 0x0 | Channel not halted
17492  * ALT_USB_HOST_HCINT0_CHHLTD_E_ACT | 0x1 | Channel Halted
17493  *
17494  * Field Access Macros:
17495  *
17496  */
17497 /*
17498  * Enumerated value for register field ALT_USB_HOST_HCINT0_CHHLTD
17499  *
17500  * Channel not halted
17501  */
17502 #define ALT_USB_HOST_HCINT0_CHHLTD_E_INACT 0x0
17503 /*
17504  * Enumerated value for register field ALT_USB_HOST_HCINT0_CHHLTD
17505  *
17506  * Channel Halted
17507  */
17508 #define ALT_USB_HOST_HCINT0_CHHLTD_E_ACT 0x1
17509 
17510 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_CHHLTD register field. */
17511 #define ALT_USB_HOST_HCINT0_CHHLTD_LSB 1
17512 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_CHHLTD register field. */
17513 #define ALT_USB_HOST_HCINT0_CHHLTD_MSB 1
17514 /* The width in bits of the ALT_USB_HOST_HCINT0_CHHLTD register field. */
17515 #define ALT_USB_HOST_HCINT0_CHHLTD_WIDTH 1
17516 /* The mask used to set the ALT_USB_HOST_HCINT0_CHHLTD register field value. */
17517 #define ALT_USB_HOST_HCINT0_CHHLTD_SET_MSK 0x00000002
17518 /* The mask used to clear the ALT_USB_HOST_HCINT0_CHHLTD register field value. */
17519 #define ALT_USB_HOST_HCINT0_CHHLTD_CLR_MSK 0xfffffffd
17520 /* The reset value of the ALT_USB_HOST_HCINT0_CHHLTD register field. */
17521 #define ALT_USB_HOST_HCINT0_CHHLTD_RESET 0x0
17522 /* Extracts the ALT_USB_HOST_HCINT0_CHHLTD field value from a register. */
17523 #define ALT_USB_HOST_HCINT0_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
17524 /* Produces a ALT_USB_HOST_HCINT0_CHHLTD register field value suitable for setting the register. */
17525 #define ALT_USB_HOST_HCINT0_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
17526 
17527 /*
17528  * Field : ahberr
17529  *
17530  * AHB Error (AHBErr)
17531  *
17532  * This is generated only in Internal DMA mode when there is an
17533  *
17534  * AHB error during AHB read/write. The application can read the
17535  *
17536  * corresponding channel's DMA address register to get the error
17537  *
17538  * address.
17539  *
17540  * Field Enumeration Values:
17541  *
17542  * Enum | Value | Description
17543  * :-----------------------------------|:------|:--------------------------------
17544  * ALT_USB_HOST_HCINT0_AHBERR_E_INACT | 0x0 | No AHB error
17545  * ALT_USB_HOST_HCINT0_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
17546  *
17547  * Field Access Macros:
17548  *
17549  */
17550 /*
17551  * Enumerated value for register field ALT_USB_HOST_HCINT0_AHBERR
17552  *
17553  * No AHB error
17554  */
17555 #define ALT_USB_HOST_HCINT0_AHBERR_E_INACT 0x0
17556 /*
17557  * Enumerated value for register field ALT_USB_HOST_HCINT0_AHBERR
17558  *
17559  * AHB error during AHB read/write
17560  */
17561 #define ALT_USB_HOST_HCINT0_AHBERR_E_ACT 0x1
17562 
17563 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_AHBERR register field. */
17564 #define ALT_USB_HOST_HCINT0_AHBERR_LSB 2
17565 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_AHBERR register field. */
17566 #define ALT_USB_HOST_HCINT0_AHBERR_MSB 2
17567 /* The width in bits of the ALT_USB_HOST_HCINT0_AHBERR register field. */
17568 #define ALT_USB_HOST_HCINT0_AHBERR_WIDTH 1
17569 /* The mask used to set the ALT_USB_HOST_HCINT0_AHBERR register field value. */
17570 #define ALT_USB_HOST_HCINT0_AHBERR_SET_MSK 0x00000004
17571 /* The mask used to clear the ALT_USB_HOST_HCINT0_AHBERR register field value. */
17572 #define ALT_USB_HOST_HCINT0_AHBERR_CLR_MSK 0xfffffffb
17573 /* The reset value of the ALT_USB_HOST_HCINT0_AHBERR register field. */
17574 #define ALT_USB_HOST_HCINT0_AHBERR_RESET 0x0
17575 /* Extracts the ALT_USB_HOST_HCINT0_AHBERR field value from a register. */
17576 #define ALT_USB_HOST_HCINT0_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
17577 /* Produces a ALT_USB_HOST_HCINT0_AHBERR register field value suitable for setting the register. */
17578 #define ALT_USB_HOST_HCINT0_AHBERR_SET(value) (((value) << 2) & 0x00000004)
17579 
17580 /*
17581  * Field : stall
17582  *
17583  * STALL Response Received Interrupt (STALL)
17584  *
17585  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
17586  *
17587  * in the core.This bit can be set only by the core and the application should
17588  * write 1 to clear
17589  *
17590  * it.
17591  *
17592  * Field Enumeration Values:
17593  *
17594  * Enum | Value | Description
17595  * :----------------------------------|:------|:-------------------
17596  * ALT_USB_HOST_HCINT0_STALL_E_INACT | 0x0 | No Stall Interrupt
17597  * ALT_USB_HOST_HCINT0_STALL_E_ACT | 0x1 | Stall Interrupt
17598  *
17599  * Field Access Macros:
17600  *
17601  */
17602 /*
17603  * Enumerated value for register field ALT_USB_HOST_HCINT0_STALL
17604  *
17605  * No Stall Interrupt
17606  */
17607 #define ALT_USB_HOST_HCINT0_STALL_E_INACT 0x0
17608 /*
17609  * Enumerated value for register field ALT_USB_HOST_HCINT0_STALL
17610  *
17611  * Stall Interrupt
17612  */
17613 #define ALT_USB_HOST_HCINT0_STALL_E_ACT 0x1
17614 
17615 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_STALL register field. */
17616 #define ALT_USB_HOST_HCINT0_STALL_LSB 3
17617 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_STALL register field. */
17618 #define ALT_USB_HOST_HCINT0_STALL_MSB 3
17619 /* The width in bits of the ALT_USB_HOST_HCINT0_STALL register field. */
17620 #define ALT_USB_HOST_HCINT0_STALL_WIDTH 1
17621 /* The mask used to set the ALT_USB_HOST_HCINT0_STALL register field value. */
17622 #define ALT_USB_HOST_HCINT0_STALL_SET_MSK 0x00000008
17623 /* The mask used to clear the ALT_USB_HOST_HCINT0_STALL register field value. */
17624 #define ALT_USB_HOST_HCINT0_STALL_CLR_MSK 0xfffffff7
17625 /* The reset value of the ALT_USB_HOST_HCINT0_STALL register field. */
17626 #define ALT_USB_HOST_HCINT0_STALL_RESET 0x0
17627 /* Extracts the ALT_USB_HOST_HCINT0_STALL field value from a register. */
17628 #define ALT_USB_HOST_HCINT0_STALL_GET(value) (((value) & 0x00000008) >> 3)
17629 /* Produces a ALT_USB_HOST_HCINT0_STALL register field value suitable for setting the register. */
17630 #define ALT_USB_HOST_HCINT0_STALL_SET(value) (((value) << 3) & 0x00000008)
17631 
17632 /*
17633  * Field : nak
17634  *
17635  * NAK Response Received Interrupt (NAK)
17636  *
17637  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
17638  *
17639  * in the core.This bit can be set only by the core and the application should
17640  * write 1 to clear
17641  *
17642  * it.
17643  *
17644  * Field Enumeration Values:
17645  *
17646  * Enum | Value | Description
17647  * :--------------------------------|:------|:-----------------------------------
17648  * ALT_USB_HOST_HCINT0_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
17649  * ALT_USB_HOST_HCINT0_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
17650  *
17651  * Field Access Macros:
17652  *
17653  */
17654 /*
17655  * Enumerated value for register field ALT_USB_HOST_HCINT0_NAK
17656  *
17657  * No NAK Response Received Interrupt
17658  */
17659 #define ALT_USB_HOST_HCINT0_NAK_E_INACT 0x0
17660 /*
17661  * Enumerated value for register field ALT_USB_HOST_HCINT0_NAK
17662  *
17663  * NAK Response Received Interrupt
17664  */
17665 #define ALT_USB_HOST_HCINT0_NAK_E_ACT 0x1
17666 
17667 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_NAK register field. */
17668 #define ALT_USB_HOST_HCINT0_NAK_LSB 4
17669 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_NAK register field. */
17670 #define ALT_USB_HOST_HCINT0_NAK_MSB 4
17671 /* The width in bits of the ALT_USB_HOST_HCINT0_NAK register field. */
17672 #define ALT_USB_HOST_HCINT0_NAK_WIDTH 1
17673 /* The mask used to set the ALT_USB_HOST_HCINT0_NAK register field value. */
17674 #define ALT_USB_HOST_HCINT0_NAK_SET_MSK 0x00000010
17675 /* The mask used to clear the ALT_USB_HOST_HCINT0_NAK register field value. */
17676 #define ALT_USB_HOST_HCINT0_NAK_CLR_MSK 0xffffffef
17677 /* The reset value of the ALT_USB_HOST_HCINT0_NAK register field. */
17678 #define ALT_USB_HOST_HCINT0_NAK_RESET 0x0
17679 /* Extracts the ALT_USB_HOST_HCINT0_NAK field value from a register. */
17680 #define ALT_USB_HOST_HCINT0_NAK_GET(value) (((value) & 0x00000010) >> 4)
17681 /* Produces a ALT_USB_HOST_HCINT0_NAK register field value suitable for setting the register. */
17682 #define ALT_USB_HOST_HCINT0_NAK_SET(value) (((value) << 4) & 0x00000010)
17683 
17684 /*
17685  * Field : ack
17686  *
17687  * ACK Response Received/Transmitted Interrupt (ACK)
17688  *
17689  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
17690  *
17691  * in the core.This bit can be set only by the core and the application should
17692  * write 1 to clear
17693  *
17694  * it.
17695  *
17696  * Field Enumeration Values:
17697  *
17698  * Enum | Value | Description
17699  * :--------------------------------|:------|:-----------------------------------------------
17700  * ALT_USB_HOST_HCINT0_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
17701  * ALT_USB_HOST_HCINT0_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
17702  *
17703  * Field Access Macros:
17704  *
17705  */
17706 /*
17707  * Enumerated value for register field ALT_USB_HOST_HCINT0_ACK
17708  *
17709  * No ACK Response Received Transmitted Interrupt
17710  */
17711 #define ALT_USB_HOST_HCINT0_ACK_E_INACT 0x0
17712 /*
17713  * Enumerated value for register field ALT_USB_HOST_HCINT0_ACK
17714  *
17715  * ACK Response Received Transmitted Interrup
17716  */
17717 #define ALT_USB_HOST_HCINT0_ACK_E_ACT 0x1
17718 
17719 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_ACK register field. */
17720 #define ALT_USB_HOST_HCINT0_ACK_LSB 5
17721 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_ACK register field. */
17722 #define ALT_USB_HOST_HCINT0_ACK_MSB 5
17723 /* The width in bits of the ALT_USB_HOST_HCINT0_ACK register field. */
17724 #define ALT_USB_HOST_HCINT0_ACK_WIDTH 1
17725 /* The mask used to set the ALT_USB_HOST_HCINT0_ACK register field value. */
17726 #define ALT_USB_HOST_HCINT0_ACK_SET_MSK 0x00000020
17727 /* The mask used to clear the ALT_USB_HOST_HCINT0_ACK register field value. */
17728 #define ALT_USB_HOST_HCINT0_ACK_CLR_MSK 0xffffffdf
17729 /* The reset value of the ALT_USB_HOST_HCINT0_ACK register field. */
17730 #define ALT_USB_HOST_HCINT0_ACK_RESET 0x0
17731 /* Extracts the ALT_USB_HOST_HCINT0_ACK field value from a register. */
17732 #define ALT_USB_HOST_HCINT0_ACK_GET(value) (((value) & 0x00000020) >> 5)
17733 /* Produces a ALT_USB_HOST_HCINT0_ACK register field value suitable for setting the register. */
17734 #define ALT_USB_HOST_HCINT0_ACK_SET(value) (((value) << 5) & 0x00000020)
17735 
17736 /*
17737  * Field : nyet
17738  *
17739  * NYET Response Received Interrupt (NYET)
17740  *
17741  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
17742  *
17743  * in the core.This bit can be set only by the core and the application should
17744  * write 1 to clear
17745  *
17746  * it.
17747  *
17748  * Field Enumeration Values:
17749  *
17750  * Enum | Value | Description
17751  * :---------------------------------|:------|:------------------------------------
17752  * ALT_USB_HOST_HCINT0_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
17753  * ALT_USB_HOST_HCINT0_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
17754  *
17755  * Field Access Macros:
17756  *
17757  */
17758 /*
17759  * Enumerated value for register field ALT_USB_HOST_HCINT0_NYET
17760  *
17761  * No NYET Response Received Interrupt
17762  */
17763 #define ALT_USB_HOST_HCINT0_NYET_E_INACT 0x0
17764 /*
17765  * Enumerated value for register field ALT_USB_HOST_HCINT0_NYET
17766  *
17767  * NYET Response Received Interrupt
17768  */
17769 #define ALT_USB_HOST_HCINT0_NYET_E_ACT 0x1
17770 
17771 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_NYET register field. */
17772 #define ALT_USB_HOST_HCINT0_NYET_LSB 6
17773 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_NYET register field. */
17774 #define ALT_USB_HOST_HCINT0_NYET_MSB 6
17775 /* The width in bits of the ALT_USB_HOST_HCINT0_NYET register field. */
17776 #define ALT_USB_HOST_HCINT0_NYET_WIDTH 1
17777 /* The mask used to set the ALT_USB_HOST_HCINT0_NYET register field value. */
17778 #define ALT_USB_HOST_HCINT0_NYET_SET_MSK 0x00000040
17779 /* The mask used to clear the ALT_USB_HOST_HCINT0_NYET register field value. */
17780 #define ALT_USB_HOST_HCINT0_NYET_CLR_MSK 0xffffffbf
17781 /* The reset value of the ALT_USB_HOST_HCINT0_NYET register field. */
17782 #define ALT_USB_HOST_HCINT0_NYET_RESET 0x0
17783 /* Extracts the ALT_USB_HOST_HCINT0_NYET field value from a register. */
17784 #define ALT_USB_HOST_HCINT0_NYET_GET(value) (((value) & 0x00000040) >> 6)
17785 /* Produces a ALT_USB_HOST_HCINT0_NYET register field value suitable for setting the register. */
17786 #define ALT_USB_HOST_HCINT0_NYET_SET(value) (((value) << 6) & 0x00000040)
17787 
17788 /*
17789  * Field : xacterr
17790  *
17791  * Transaction Error (XactErr)
17792  *
17793  * Indicates one of the following errors occurred on the USB.
17794  *
17795  * CRC check failure
17796  *
17797  * Timeout
17798  *
17799  * Bit stuff error
17800  *
17801  * False EOP
17802  *
17803  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
17804  *
17805  * in the core.This bit can be set only by the core and the application should
17806  * write 1 to clear
17807  *
17808  * it.
17809  *
17810  * Field Enumeration Values:
17811  *
17812  * Enum | Value | Description
17813  * :------------------------------------|:------|:---------------------
17814  * ALT_USB_HOST_HCINT0_XACTERR_E_INACT | 0x0 | No Transaction Error
17815  * ALT_USB_HOST_HCINT0_XACTERR_E_ACT | 0x1 | Transaction Error
17816  *
17817  * Field Access Macros:
17818  *
17819  */
17820 /*
17821  * Enumerated value for register field ALT_USB_HOST_HCINT0_XACTERR
17822  *
17823  * No Transaction Error
17824  */
17825 #define ALT_USB_HOST_HCINT0_XACTERR_E_INACT 0x0
17826 /*
17827  * Enumerated value for register field ALT_USB_HOST_HCINT0_XACTERR
17828  *
17829  * Transaction Error
17830  */
17831 #define ALT_USB_HOST_HCINT0_XACTERR_E_ACT 0x1
17832 
17833 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_XACTERR register field. */
17834 #define ALT_USB_HOST_HCINT0_XACTERR_LSB 7
17835 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_XACTERR register field. */
17836 #define ALT_USB_HOST_HCINT0_XACTERR_MSB 7
17837 /* The width in bits of the ALT_USB_HOST_HCINT0_XACTERR register field. */
17838 #define ALT_USB_HOST_HCINT0_XACTERR_WIDTH 1
17839 /* The mask used to set the ALT_USB_HOST_HCINT0_XACTERR register field value. */
17840 #define ALT_USB_HOST_HCINT0_XACTERR_SET_MSK 0x00000080
17841 /* The mask used to clear the ALT_USB_HOST_HCINT0_XACTERR register field value. */
17842 #define ALT_USB_HOST_HCINT0_XACTERR_CLR_MSK 0xffffff7f
17843 /* The reset value of the ALT_USB_HOST_HCINT0_XACTERR register field. */
17844 #define ALT_USB_HOST_HCINT0_XACTERR_RESET 0x0
17845 /* Extracts the ALT_USB_HOST_HCINT0_XACTERR field value from a register. */
17846 #define ALT_USB_HOST_HCINT0_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
17847 /* Produces a ALT_USB_HOST_HCINT0_XACTERR register field value suitable for setting the register. */
17848 #define ALT_USB_HOST_HCINT0_XACTERR_SET(value) (((value) << 7) & 0x00000080)
17849 
17850 /*
17851  * Field : bblerr
17852  *
17853  * Babble Error (BblErr)
17854  *
17855  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
17856  *
17857  * in the core..This bit can be set only by the core and the application should
17858  * write 1 to clear
17859  *
17860  * it.
17861  *
17862  * Field Enumeration Values:
17863  *
17864  * Enum | Value | Description
17865  * :-----------------------------------|:------|:----------------
17866  * ALT_USB_HOST_HCINT0_BBLERR_E_INACT | 0x0 | No Babble Error
17867  * ALT_USB_HOST_HCINT0_BBLERR_E_ACT | 0x1 | Babble Error
17868  *
17869  * Field Access Macros:
17870  *
17871  */
17872 /*
17873  * Enumerated value for register field ALT_USB_HOST_HCINT0_BBLERR
17874  *
17875  * No Babble Error
17876  */
17877 #define ALT_USB_HOST_HCINT0_BBLERR_E_INACT 0x0
17878 /*
17879  * Enumerated value for register field ALT_USB_HOST_HCINT0_BBLERR
17880  *
17881  * Babble Error
17882  */
17883 #define ALT_USB_HOST_HCINT0_BBLERR_E_ACT 0x1
17884 
17885 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_BBLERR register field. */
17886 #define ALT_USB_HOST_HCINT0_BBLERR_LSB 8
17887 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_BBLERR register field. */
17888 #define ALT_USB_HOST_HCINT0_BBLERR_MSB 8
17889 /* The width in bits of the ALT_USB_HOST_HCINT0_BBLERR register field. */
17890 #define ALT_USB_HOST_HCINT0_BBLERR_WIDTH 1
17891 /* The mask used to set the ALT_USB_HOST_HCINT0_BBLERR register field value. */
17892 #define ALT_USB_HOST_HCINT0_BBLERR_SET_MSK 0x00000100
17893 /* The mask used to clear the ALT_USB_HOST_HCINT0_BBLERR register field value. */
17894 #define ALT_USB_HOST_HCINT0_BBLERR_CLR_MSK 0xfffffeff
17895 /* The reset value of the ALT_USB_HOST_HCINT0_BBLERR register field. */
17896 #define ALT_USB_HOST_HCINT0_BBLERR_RESET 0x0
17897 /* Extracts the ALT_USB_HOST_HCINT0_BBLERR field value from a register. */
17898 #define ALT_USB_HOST_HCINT0_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
17899 /* Produces a ALT_USB_HOST_HCINT0_BBLERR register field value suitable for setting the register. */
17900 #define ALT_USB_HOST_HCINT0_BBLERR_SET(value) (((value) << 8) & 0x00000100)
17901 
17902 /*
17903  * Field : frmovrun
17904  *
17905  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
17906  * bit is masked
17907  *
17908  * in the core.This bit can be set only by the core and the application should
17909  * write 1 to clear
17910  *
17911  * it.
17912  *
17913  * Field Enumeration Values:
17914  *
17915  * Enum | Value | Description
17916  * :-------------------------------------|:------|:-----------------
17917  * ALT_USB_HOST_HCINT0_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
17918  * ALT_USB_HOST_HCINT0_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
17919  *
17920  * Field Access Macros:
17921  *
17922  */
17923 /*
17924  * Enumerated value for register field ALT_USB_HOST_HCINT0_FRMOVRUN
17925  *
17926  * No Frame Overrun
17927  */
17928 #define ALT_USB_HOST_HCINT0_FRMOVRUN_E_INACT 0x0
17929 /*
17930  * Enumerated value for register field ALT_USB_HOST_HCINT0_FRMOVRUN
17931  *
17932  * Frame Overrun
17933  */
17934 #define ALT_USB_HOST_HCINT0_FRMOVRUN_E_ACT 0x1
17935 
17936 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */
17937 #define ALT_USB_HOST_HCINT0_FRMOVRUN_LSB 9
17938 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */
17939 #define ALT_USB_HOST_HCINT0_FRMOVRUN_MSB 9
17940 /* The width in bits of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */
17941 #define ALT_USB_HOST_HCINT0_FRMOVRUN_WIDTH 1
17942 /* The mask used to set the ALT_USB_HOST_HCINT0_FRMOVRUN register field value. */
17943 #define ALT_USB_HOST_HCINT0_FRMOVRUN_SET_MSK 0x00000200
17944 /* The mask used to clear the ALT_USB_HOST_HCINT0_FRMOVRUN register field value. */
17945 #define ALT_USB_HOST_HCINT0_FRMOVRUN_CLR_MSK 0xfffffdff
17946 /* The reset value of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */
17947 #define ALT_USB_HOST_HCINT0_FRMOVRUN_RESET 0x0
17948 /* Extracts the ALT_USB_HOST_HCINT0_FRMOVRUN field value from a register. */
17949 #define ALT_USB_HOST_HCINT0_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
17950 /* Produces a ALT_USB_HOST_HCINT0_FRMOVRUN register field value suitable for setting the register. */
17951 #define ALT_USB_HOST_HCINT0_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
17952 
17953 /*
17954  * Field : datatglerr
17955  *
17956  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
17957  * application should write 1 to clear
17958  *
17959  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
17960  *
17961  * in the core.
17962  *
17963  * Field Enumeration Values:
17964  *
17965  * Enum | Value | Description
17966  * :---------------------------------------|:------|:---------------------
17967  * ALT_USB_HOST_HCINT0_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
17968  * ALT_USB_HOST_HCINT0_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
17969  *
17970  * Field Access Macros:
17971  *
17972  */
17973 /*
17974  * Enumerated value for register field ALT_USB_HOST_HCINT0_DATATGLERR
17975  *
17976  * No Data Toggle Error
17977  */
17978 #define ALT_USB_HOST_HCINT0_DATATGLERR_E_INACT 0x0
17979 /*
17980  * Enumerated value for register field ALT_USB_HOST_HCINT0_DATATGLERR
17981  *
17982  * Data Toggle Error
17983  */
17984 #define ALT_USB_HOST_HCINT0_DATATGLERR_E_ACT 0x1
17985 
17986 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */
17987 #define ALT_USB_HOST_HCINT0_DATATGLERR_LSB 10
17988 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */
17989 #define ALT_USB_HOST_HCINT0_DATATGLERR_MSB 10
17990 /* The width in bits of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */
17991 #define ALT_USB_HOST_HCINT0_DATATGLERR_WIDTH 1
17992 /* The mask used to set the ALT_USB_HOST_HCINT0_DATATGLERR register field value. */
17993 #define ALT_USB_HOST_HCINT0_DATATGLERR_SET_MSK 0x00000400
17994 /* The mask used to clear the ALT_USB_HOST_HCINT0_DATATGLERR register field value. */
17995 #define ALT_USB_HOST_HCINT0_DATATGLERR_CLR_MSK 0xfffffbff
17996 /* The reset value of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */
17997 #define ALT_USB_HOST_HCINT0_DATATGLERR_RESET 0x0
17998 /* Extracts the ALT_USB_HOST_HCINT0_DATATGLERR field value from a register. */
17999 #define ALT_USB_HOST_HCINT0_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
18000 /* Produces a ALT_USB_HOST_HCINT0_DATATGLERR register field value suitable for setting the register. */
18001 #define ALT_USB_HOST_HCINT0_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
18002 
18003 /*
18004  * Field : bnaintr
18005  *
18006  * BNA (Buffer Not Available) Interrupt (BNAIntr)
18007  *
18008  * This bit is valid only when Scatter/Gather DMA mode is enabled.
18009  *
18010  * The core generates this interrupt when the descriptor accessed
18011  *
18012  * is not ready for the Core to process. BNA will not be generated
18013  *
18014  * for Isochronous channels.
18015  *
18016  * For non Scatter/Gather DMA mode, this bit is reserved.
18017  *
18018  * Field Enumeration Values:
18019  *
18020  * Enum | Value | Description
18021  * :------------------------------------|:------|:-----------------
18022  * ALT_USB_HOST_HCINT0_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
18023  * ALT_USB_HOST_HCINT0_BNAINTR_E_ACT | 0x1 | BNA Interrupt
18024  *
18025  * Field Access Macros:
18026  *
18027  */
18028 /*
18029  * Enumerated value for register field ALT_USB_HOST_HCINT0_BNAINTR
18030  *
18031  * No BNA Interrupt
18032  */
18033 #define ALT_USB_HOST_HCINT0_BNAINTR_E_INACT 0x0
18034 /*
18035  * Enumerated value for register field ALT_USB_HOST_HCINT0_BNAINTR
18036  *
18037  * BNA Interrupt
18038  */
18039 #define ALT_USB_HOST_HCINT0_BNAINTR_E_ACT 0x1
18040 
18041 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_BNAINTR register field. */
18042 #define ALT_USB_HOST_HCINT0_BNAINTR_LSB 11
18043 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_BNAINTR register field. */
18044 #define ALT_USB_HOST_HCINT0_BNAINTR_MSB 11
18045 /* The width in bits of the ALT_USB_HOST_HCINT0_BNAINTR register field. */
18046 #define ALT_USB_HOST_HCINT0_BNAINTR_WIDTH 1
18047 /* The mask used to set the ALT_USB_HOST_HCINT0_BNAINTR register field value. */
18048 #define ALT_USB_HOST_HCINT0_BNAINTR_SET_MSK 0x00000800
18049 /* The mask used to clear the ALT_USB_HOST_HCINT0_BNAINTR register field value. */
18050 #define ALT_USB_HOST_HCINT0_BNAINTR_CLR_MSK 0xfffff7ff
18051 /* The reset value of the ALT_USB_HOST_HCINT0_BNAINTR register field. */
18052 #define ALT_USB_HOST_HCINT0_BNAINTR_RESET 0x0
18053 /* Extracts the ALT_USB_HOST_HCINT0_BNAINTR field value from a register. */
18054 #define ALT_USB_HOST_HCINT0_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
18055 /* Produces a ALT_USB_HOST_HCINT0_BNAINTR register field value suitable for setting the register. */
18056 #define ALT_USB_HOST_HCINT0_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
18057 
18058 /*
18059  * Field : xcs_xact_err
18060  *
18061  * Excessive Transaction Error (XCS_XACT_ERR)
18062  *
18063  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
18064  * this bit
18065  *
18066  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
18067  *
18068  * not be generated for Isochronous channels.
18069  *
18070  * For non Scatter/Gather DMA mode, this bit is reserved.
18071  *
18072  * Field Enumeration Values:
18073  *
18074  * Enum | Value | Description
18075  * :-------------------------------------------|:------|:-------------------------------
18076  * ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
18077  * ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
18078  *
18079  * Field Access Macros:
18080  *
18081  */
18082 /*
18083  * Enumerated value for register field ALT_USB_HOST_HCINT0_XCS_XACT_ERR
18084  *
18085  * No Excessive Transaction Error
18086  */
18087 #define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_INACT 0x0
18088 /*
18089  * Enumerated value for register field ALT_USB_HOST_HCINT0_XCS_XACT_ERR
18090  *
18091  * Excessive Transaction Error
18092  */
18093 #define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_ACVTIVE 0x1
18094 
18095 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */
18096 #define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_LSB 12
18097 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */
18098 #define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_MSB 12
18099 /* The width in bits of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */
18100 #define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_WIDTH 1
18101 /* The mask used to set the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field value. */
18102 #define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_SET_MSK 0x00001000
18103 /* The mask used to clear the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field value. */
18104 #define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_CLR_MSK 0xffffefff
18105 /* The reset value of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */
18106 #define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_RESET 0x0
18107 /* Extracts the ALT_USB_HOST_HCINT0_XCS_XACT_ERR field value from a register. */
18108 #define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
18109 /* Produces a ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field value suitable for setting the register. */
18110 #define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
18111 
18112 /*
18113  * Field : desc_lst_rollintr
18114  *
18115  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
18116  *
18117  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
18118  * this bit
18119  *
18120  * when the corresponding channel's descriptor list rolls over.
18121  *
18122  * For non Scatter/Gather DMA mode, this bit is reserved.
18123  *
18124  * Field Enumeration Values:
18125  *
18126  * Enum | Value | Description
18127  * :----------------------------------------------|:------|:---------------------------------
18128  * ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
18129  * ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
18130  *
18131  * Field Access Macros:
18132  *
18133  */
18134 /*
18135  * Enumerated value for register field ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR
18136  *
18137  * No Descriptor rollover interrupt
18138  */
18139 #define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_INACT 0x0
18140 /*
18141  * Enumerated value for register field ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR
18142  *
18143  * Descriptor rollover interrupt
18144  */
18145 #define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_ACT 0x1
18146 
18147 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */
18148 #define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_LSB 13
18149 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */
18150 #define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_MSB 13
18151 /* The width in bits of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */
18152 #define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_WIDTH 1
18153 /* The mask used to set the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field value. */
18154 #define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_SET_MSK 0x00002000
18155 /* The mask used to clear the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field value. */
18156 #define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
18157 /* The reset value of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */
18158 #define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_RESET 0x0
18159 /* Extracts the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR field value from a register. */
18160 #define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
18161 /* Produces a ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field value suitable for setting the register. */
18162 #define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
18163 
18164 #ifndef __ASSEMBLY__
18165 /*
18166  * WARNING: The C register and register group struct declarations are provided for
18167  * convenience and illustrative purposes. They should, however, be used with
18168  * caution as the C language standard provides no guarantees about the alignment or
18169  * atomicity of device memory accesses. The recommended practice for writing
18170  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18171  * alt_write_word() functions.
18172  *
18173  * The struct declaration for register ALT_USB_HOST_HCINT0.
18174  */
18175 struct ALT_USB_HOST_HCINT0_s
18176 {
18177  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT0_XFERCOMPL */
18178  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT0_CHHLTD */
18179  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT0_AHBERR */
18180  uint32_t stall : 1; /* ALT_USB_HOST_HCINT0_STALL */
18181  uint32_t nak : 1; /* ALT_USB_HOST_HCINT0_NAK */
18182  uint32_t ack : 1; /* ALT_USB_HOST_HCINT0_ACK */
18183  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT0_NYET */
18184  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT0_XACTERR */
18185  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT0_BBLERR */
18186  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT0_FRMOVRUN */
18187  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT0_DATATGLERR */
18188  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT0_BNAINTR */
18189  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT0_XCS_XACT_ERR */
18190  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR */
18191  uint32_t : 18; /* *UNDEFINED* */
18192 };
18193 
18194 /* The typedef declaration for register ALT_USB_HOST_HCINT0. */
18195 typedef volatile struct ALT_USB_HOST_HCINT0_s ALT_USB_HOST_HCINT0_t;
18196 #endif /* __ASSEMBLY__ */
18197 
18198 /* The reset value of the ALT_USB_HOST_HCINT0 register. */
18199 #define ALT_USB_HOST_HCINT0_RESET 0x00000000
18200 /* The byte offset of the ALT_USB_HOST_HCINT0 register from the beginning of the component. */
18201 #define ALT_USB_HOST_HCINT0_OFST 0x108
18202 /* The address of the ALT_USB_HOST_HCINT0 register. */
18203 #define ALT_USB_HOST_HCINT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT0_OFST))
18204 
18205 /*
18206  * Register : hcintmsk0
18207  *
18208  * Host Channel 0 Interrupt Mask Register
18209  *
18210  * Register Layout
18211  *
18212  * Bits | Access | Reset | Description
18213  * :--------|:-------|:------|:-------------------------------------------
18214  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK
18215  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_CHHLTDMSK
18216  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_AHBERRMSK
18217  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_STALLMSK
18218  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_NAKMSK
18219  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_ACKMSK
18220  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_NYETMSK
18221  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_XACTERRMSK
18222  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_BBLERRMSK
18223  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK
18224  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK
18225  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_BNAINTRMSK
18226  * [12] | ??? | 0x0 | *UNDEFINED*
18227  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK
18228  * [31:14] | ??? | 0x0 | *UNDEFINED*
18229  *
18230  */
18231 /*
18232  * Field : xfercomplmsk
18233  *
18234  * Transfer Completed Mask (XferComplMsk)
18235  *
18236  * Field Enumeration Values:
18237  *
18238  * Enum | Value | Description
18239  * :--------------------------------------------|:------|:------------
18240  * ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_MSK | 0x0 | Mask
18241  * ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
18242  *
18243  * Field Access Macros:
18244  *
18245  */
18246 /*
18247  * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK
18248  *
18249  * Mask
18250  */
18251 #define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_MSK 0x0
18252 /*
18253  * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK
18254  *
18255  * No mask
18256  */
18257 #define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_NOMSK 0x1
18258 
18259 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */
18260 #define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_LSB 0
18261 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */
18262 #define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_MSB 0
18263 /* The width in bits of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */
18264 #define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_WIDTH 1
18265 /* The mask used to set the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field value. */
18266 #define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_SET_MSK 0x00000001
18267 /* The mask used to clear the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field value. */
18268 #define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_CLR_MSK 0xfffffffe
18269 /* The reset value of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */
18270 #define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_RESET 0x0
18271 /* Extracts the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK field value from a register. */
18272 #define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
18273 /* Produces a ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field value suitable for setting the register. */
18274 #define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
18275 
18276 /*
18277  * Field : chhltdmsk
18278  *
18279  * Channel Halted Mask (ChHltdMsk)
18280  *
18281  * Field Enumeration Values:
18282  *
18283  * Enum | Value | Description
18284  * :-----------------------------------------|:------|:------------
18285  * ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_MSK | 0x0 | Mask
18286  * ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_NOMSK | 0x1 | No mask
18287  *
18288  * Field Access Macros:
18289  *
18290  */
18291 /*
18292  * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_CHHLTDMSK
18293  *
18294  * Mask
18295  */
18296 #define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_MSK 0x0
18297 /*
18298  * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_CHHLTDMSK
18299  *
18300  * No mask
18301  */
18302 #define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_NOMSK 0x1
18303 
18304 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */
18305 #define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_LSB 1
18306 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */
18307 #define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_MSB 1
18308 /* The width in bits of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */
18309 #define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_WIDTH 1
18310 /* The mask used to set the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field value. */
18311 #define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_SET_MSK 0x00000002
18312 /* The mask used to clear the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field value. */
18313 #define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_CLR_MSK 0xfffffffd
18314 /* The reset value of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */
18315 #define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_RESET 0x0
18316 /* Extracts the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK field value from a register. */
18317 #define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
18318 /* Produces a ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field value suitable for setting the register. */
18319 #define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
18320 
18321 /*
18322  * Field : ahberrmsk
18323  *
18324  * AHB Error Mask (AHBErrMsk)
18325  *
18326  * In scatter/gather DMA mode for host,
18327  *
18328  * interrupts will not be generated due to the corresponding bits set in
18329  *
18330  * HCINTn.
18331  *
18332  * Field Enumeration Values:
18333  *
18334  * Enum | Value | Description
18335  * :-----------------------------------------|:------|:------------
18336  * ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_MSK | 0x0 | Mask
18337  * ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_NOMSK | 0x1 | No mask
18338  *
18339  * Field Access Macros:
18340  *
18341  */
18342 /*
18343  * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_AHBERRMSK
18344  *
18345  * Mask
18346  */
18347 #define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_MSK 0x0
18348 /*
18349  * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_AHBERRMSK
18350  *
18351  * No mask
18352  */
18353 #define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_NOMSK 0x1
18354 
18355 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */
18356 #define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_LSB 2
18357 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */
18358 #define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_MSB 2
18359 /* The width in bits of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */
18360 #define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_WIDTH 1
18361 /* The mask used to set the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field value. */
18362 #define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_SET_MSK 0x00000004
18363 /* The mask used to clear the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field value. */
18364 #define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_CLR_MSK 0xfffffffb
18365 /* The reset value of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */
18366 #define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_RESET 0x0
18367 /* Extracts the ALT_USB_HOST_HCINTMSK0_AHBERRMSK field value from a register. */
18368 #define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
18369 /* Produces a ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field value suitable for setting the register. */
18370 #define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
18371 
18372 /*
18373  * Field : stallmsk
18374  *
18375  * STALL Response Received Interrupt Mask (StallMsk)
18376  *
18377  * In scatter/gather DMA mode for host,
18378  *
18379  * interrupts will not be generated due to the corresponding bits set in
18380  *
18381  * HCINTn.
18382  *
18383  * Field Access Macros:
18384  *
18385  */
18386 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_STALLMSK register field. */
18387 #define ALT_USB_HOST_HCINTMSK0_STALLMSK_LSB 3
18388 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_STALLMSK register field. */
18389 #define ALT_USB_HOST_HCINTMSK0_STALLMSK_MSB 3
18390 /* The width in bits of the ALT_USB_HOST_HCINTMSK0_STALLMSK register field. */
18391 #define ALT_USB_HOST_HCINTMSK0_STALLMSK_WIDTH 1
18392 /* The mask used to set the ALT_USB_HOST_HCINTMSK0_STALLMSK register field value. */
18393 #define ALT_USB_HOST_HCINTMSK0_STALLMSK_SET_MSK 0x00000008
18394 /* The mask used to clear the ALT_USB_HOST_HCINTMSK0_STALLMSK register field value. */
18395 #define ALT_USB_HOST_HCINTMSK0_STALLMSK_CLR_MSK 0xfffffff7
18396 /* The reset value of the ALT_USB_HOST_HCINTMSK0_STALLMSK register field. */
18397 #define ALT_USB_HOST_HCINTMSK0_STALLMSK_RESET 0x0
18398 /* Extracts the ALT_USB_HOST_HCINTMSK0_STALLMSK field value from a register. */
18399 #define ALT_USB_HOST_HCINTMSK0_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
18400 /* Produces a ALT_USB_HOST_HCINTMSK0_STALLMSK register field value suitable for setting the register. */
18401 #define ALT_USB_HOST_HCINTMSK0_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
18402 
18403 /*
18404  * Field : nakmsk
18405  *
18406  * NAK Response Received Interrupt Mask (NakMsk)
18407  *
18408  * In scatter/gather DMA mode for host,
18409  *
18410  * interrupts will not be generated due to the corresponding bits set in
18411  *
18412  * HCINTn.
18413  *
18414  * Field Access Macros:
18415  *
18416  */
18417 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_NAKMSK register field. */
18418 #define ALT_USB_HOST_HCINTMSK0_NAKMSK_LSB 4
18419 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_NAKMSK register field. */
18420 #define ALT_USB_HOST_HCINTMSK0_NAKMSK_MSB 4
18421 /* The width in bits of the ALT_USB_HOST_HCINTMSK0_NAKMSK register field. */
18422 #define ALT_USB_HOST_HCINTMSK0_NAKMSK_WIDTH 1
18423 /* The mask used to set the ALT_USB_HOST_HCINTMSK0_NAKMSK register field value. */
18424 #define ALT_USB_HOST_HCINTMSK0_NAKMSK_SET_MSK 0x00000010
18425 /* The mask used to clear the ALT_USB_HOST_HCINTMSK0_NAKMSK register field value. */
18426 #define ALT_USB_HOST_HCINTMSK0_NAKMSK_CLR_MSK 0xffffffef
18427 /* The reset value of the ALT_USB_HOST_HCINTMSK0_NAKMSK register field. */
18428 #define ALT_USB_HOST_HCINTMSK0_NAKMSK_RESET 0x0
18429 /* Extracts the ALT_USB_HOST_HCINTMSK0_NAKMSK field value from a register. */
18430 #define ALT_USB_HOST_HCINTMSK0_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
18431 /* Produces a ALT_USB_HOST_HCINTMSK0_NAKMSK register field value suitable for setting the register. */
18432 #define ALT_USB_HOST_HCINTMSK0_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
18433 
18434 /*
18435  * Field : ackmsk
18436  *
18437  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
18438  *
18439  * In scatter/gather DMA mode for host,
18440  *
18441  * interrupts will not be generated due to the corresponding bits set in
18442  *
18443  * HCINTn.
18444  *
18445  * Field Access Macros:
18446  *
18447  */
18448 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_ACKMSK register field. */
18449 #define ALT_USB_HOST_HCINTMSK0_ACKMSK_LSB 5
18450 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_ACKMSK register field. */
18451 #define ALT_USB_HOST_HCINTMSK0_ACKMSK_MSB 5
18452 /* The width in bits of the ALT_USB_HOST_HCINTMSK0_ACKMSK register field. */
18453 #define ALT_USB_HOST_HCINTMSK0_ACKMSK_WIDTH 1
18454 /* The mask used to set the ALT_USB_HOST_HCINTMSK0_ACKMSK register field value. */
18455 #define ALT_USB_HOST_HCINTMSK0_ACKMSK_SET_MSK 0x00000020
18456 /* The mask used to clear the ALT_USB_HOST_HCINTMSK0_ACKMSK register field value. */
18457 #define ALT_USB_HOST_HCINTMSK0_ACKMSK_CLR_MSK 0xffffffdf
18458 /* The reset value of the ALT_USB_HOST_HCINTMSK0_ACKMSK register field. */
18459 #define ALT_USB_HOST_HCINTMSK0_ACKMSK_RESET 0x0
18460 /* Extracts the ALT_USB_HOST_HCINTMSK0_ACKMSK field value from a register. */
18461 #define ALT_USB_HOST_HCINTMSK0_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
18462 /* Produces a ALT_USB_HOST_HCINTMSK0_ACKMSK register field value suitable for setting the register. */
18463 #define ALT_USB_HOST_HCINTMSK0_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
18464 
18465 /*
18466  * Field : nyetmsk
18467  *
18468  * NYET Response Received Interrupt Mask (NyetMsk)
18469  *
18470  * In scatter/gather DMA mode for host,
18471  *
18472  * interrupts will not be generated due to the corresponding bits set in
18473  *
18474  * HCINTn.
18475  *
18476  * Field Access Macros:
18477  *
18478  */
18479 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_NYETMSK register field. */
18480 #define ALT_USB_HOST_HCINTMSK0_NYETMSK_LSB 6
18481 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_NYETMSK register field. */
18482 #define ALT_USB_HOST_HCINTMSK0_NYETMSK_MSB 6
18483 /* The width in bits of the ALT_USB_HOST_HCINTMSK0_NYETMSK register field. */
18484 #define ALT_USB_HOST_HCINTMSK0_NYETMSK_WIDTH 1
18485 /* The mask used to set the ALT_USB_HOST_HCINTMSK0_NYETMSK register field value. */
18486 #define ALT_USB_HOST_HCINTMSK0_NYETMSK_SET_MSK 0x00000040
18487 /* The mask used to clear the ALT_USB_HOST_HCINTMSK0_NYETMSK register field value. */
18488 #define ALT_USB_HOST_HCINTMSK0_NYETMSK_CLR_MSK 0xffffffbf
18489 /* The reset value of the ALT_USB_HOST_HCINTMSK0_NYETMSK register field. */
18490 #define ALT_USB_HOST_HCINTMSK0_NYETMSK_RESET 0x0
18491 /* Extracts the ALT_USB_HOST_HCINTMSK0_NYETMSK field value from a register. */
18492 #define ALT_USB_HOST_HCINTMSK0_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
18493 /* Produces a ALT_USB_HOST_HCINTMSK0_NYETMSK register field value suitable for setting the register. */
18494 #define ALT_USB_HOST_HCINTMSK0_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
18495 
18496 /*
18497  * Field : xacterrmsk
18498  *
18499  * Transaction Error Mask (XactErrMsk)
18500  *
18501  * In scatter/gather DMA mode for host,
18502  *
18503  * interrupts will not be generated due to the corresponding bits set in
18504  *
18505  * HCINTn.
18506  *
18507  * Field Access Macros:
18508  *
18509  */
18510 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field. */
18511 #define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_LSB 7
18512 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field. */
18513 #define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_MSB 7
18514 /* The width in bits of the ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field. */
18515 #define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_WIDTH 1
18516 /* The mask used to set the ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field value. */
18517 #define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_SET_MSK 0x00000080
18518 /* The mask used to clear the ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field value. */
18519 #define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_CLR_MSK 0xffffff7f
18520 /* The reset value of the ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field. */
18521 #define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_RESET 0x0
18522 /* Extracts the ALT_USB_HOST_HCINTMSK0_XACTERRMSK field value from a register. */
18523 #define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
18524 /* Produces a ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field value suitable for setting the register. */
18525 #define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
18526 
18527 /*
18528  * Field : bblerrmsk
18529  *
18530  * Babble Error Mask (BblErrMsk)
18531  *
18532  * In scatter/gather DMA mode for host,
18533  *
18534  * interrupts will not be generated due to the corresponding bits set in
18535  *
18536  * HCINTn.
18537  *
18538  * Field Access Macros:
18539  *
18540  */
18541 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field. */
18542 #define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_LSB 8
18543 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field. */
18544 #define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_MSB 8
18545 /* The width in bits of the ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field. */
18546 #define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_WIDTH 1
18547 /* The mask used to set the ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field value. */
18548 #define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_SET_MSK 0x00000100
18549 /* The mask used to clear the ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field value. */
18550 #define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_CLR_MSK 0xfffffeff
18551 /* The reset value of the ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field. */
18552 #define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_RESET 0x0
18553 /* Extracts the ALT_USB_HOST_HCINTMSK0_BBLERRMSK field value from a register. */
18554 #define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
18555 /* Produces a ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field value suitable for setting the register. */
18556 #define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
18557 
18558 /*
18559  * Field : frmovrunmsk
18560  *
18561  * Frame Overrun Mask (FrmOvrunMsk)
18562  *
18563  * In scatter/gather DMA mode for host,
18564  *
18565  * interrupts will not be generated due to the corresponding bits set in
18566  *
18567  * HCINTn.
18568  *
18569  * Field Access Macros:
18570  *
18571  */
18572 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field. */
18573 #define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_LSB 9
18574 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field. */
18575 #define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_MSB 9
18576 /* The width in bits of the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field. */
18577 #define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_WIDTH 1
18578 /* The mask used to set the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field value. */
18579 #define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_SET_MSK 0x00000200
18580 /* The mask used to clear the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field value. */
18581 #define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_CLR_MSK 0xfffffdff
18582 /* The reset value of the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field. */
18583 #define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_RESET 0x0
18584 /* Extracts the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK field value from a register. */
18585 #define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
18586 /* Produces a ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field value suitable for setting the register. */
18587 #define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
18588 
18589 /*
18590  * Field : datatglerrmsk
18591  *
18592  * Data Toggle Error Mask (DataTglErrMsk)
18593  *
18594  * In scatter/gather DMA mode for host,
18595  *
18596  * interrupts will not be generated due to the corresponding bits set in
18597  *
18598  * HCINTn.
18599  *
18600  * Field Access Macros:
18601  *
18602  */
18603 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field. */
18604 #define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_LSB 10
18605 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field. */
18606 #define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_MSB 10
18607 /* The width in bits of the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field. */
18608 #define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_WIDTH 1
18609 /* The mask used to set the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field value. */
18610 #define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_SET_MSK 0x00000400
18611 /* The mask used to clear the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field value. */
18612 #define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_CLR_MSK 0xfffffbff
18613 /* The reset value of the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field. */
18614 #define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_RESET 0x0
18615 /* Extracts the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK field value from a register. */
18616 #define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
18617 /* Produces a ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field value suitable for setting the register. */
18618 #define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
18619 
18620 /*
18621  * Field : bnaintrmsk
18622  *
18623  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
18624  *
18625  * This bit is valid only when Scatter/Gather DMA mode is enabled.
18626  *
18627  * Field Enumeration Values:
18628  *
18629  * Enum | Value | Description
18630  * :------------------------------------------|:------|:------------
18631  * ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_MSK | 0x0 | Mask
18632  * ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_NOMSK | 0x1 | No mask
18633  *
18634  * Field Access Macros:
18635  *
18636  */
18637 /*
18638  * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_BNAINTRMSK
18639  *
18640  * Mask
18641  */
18642 #define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_MSK 0x0
18643 /*
18644  * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_BNAINTRMSK
18645  *
18646  * No mask
18647  */
18648 #define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_NOMSK 0x1
18649 
18650 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */
18651 #define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_LSB 11
18652 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */
18653 #define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_MSB 11
18654 /* The width in bits of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */
18655 #define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_WIDTH 1
18656 /* The mask used to set the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field value. */
18657 #define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_SET_MSK 0x00000800
18658 /* The mask used to clear the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field value. */
18659 #define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_CLR_MSK 0xfffff7ff
18660 /* The reset value of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */
18661 #define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_RESET 0x0
18662 /* Extracts the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK field value from a register. */
18663 #define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
18664 /* Produces a ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field value suitable for setting the register. */
18665 #define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
18666 
18667 /*
18668  * Field : frm_lst_rollintrmsk
18669  *
18670  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
18671  *
18672  * This bit is valid only when Scatter/Gather DMA mode is enabled.
18673  *
18674  * Field Enumeration Values:
18675  *
18676  * Enum | Value | Description
18677  * :---------------------------------------------------|:------|:------------
18678  * ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
18679  * ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
18680  *
18681  * Field Access Macros:
18682  *
18683  */
18684 /*
18685  * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK
18686  *
18687  * Mask
18688  */
18689 #define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_MSK 0x0
18690 /*
18691  * Enumerated value for register field ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK
18692  *
18693  * No mask
18694  */
18695 #define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
18696 
18697 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */
18698 #define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_LSB 13
18699 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */
18700 #define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_MSB 13
18701 /* The width in bits of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */
18702 #define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_WIDTH 1
18703 /* The mask used to set the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field value. */
18704 #define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
18705 /* The mask used to clear the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field value. */
18706 #define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
18707 /* The reset value of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */
18708 #define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_RESET 0x0
18709 /* Extracts the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK field value from a register. */
18710 #define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
18711 /* Produces a ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
18712 #define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
18713 
18714 #ifndef __ASSEMBLY__
18715 /*
18716  * WARNING: The C register and register group struct declarations are provided for
18717  * convenience and illustrative purposes. They should, however, be used with
18718  * caution as the C language standard provides no guarantees about the alignment or
18719  * atomicity of device memory accesses. The recommended practice for writing
18720  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18721  * alt_write_word() functions.
18722  *
18723  * The struct declaration for register ALT_USB_HOST_HCINTMSK0.
18724  */
18725 struct ALT_USB_HOST_HCINTMSK0_s
18726 {
18727  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK */
18728  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK0_CHHLTDMSK */
18729  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK0_AHBERRMSK */
18730  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK0_STALLMSK */
18731  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK0_NAKMSK */
18732  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK0_ACKMSK */
18733  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK0_NYETMSK */
18734  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK0_XACTERRMSK */
18735  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK0_BBLERRMSK */
18736  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK */
18737  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK */
18738  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK0_BNAINTRMSK */
18739  uint32_t : 1; /* *UNDEFINED* */
18740  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK */
18741  uint32_t : 18; /* *UNDEFINED* */
18742 };
18743 
18744 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK0. */
18745 typedef volatile struct ALT_USB_HOST_HCINTMSK0_s ALT_USB_HOST_HCINTMSK0_t;
18746 #endif /* __ASSEMBLY__ */
18747 
18748 /* The reset value of the ALT_USB_HOST_HCINTMSK0 register. */
18749 #define ALT_USB_HOST_HCINTMSK0_RESET 0x00000000
18750 /* The byte offset of the ALT_USB_HOST_HCINTMSK0 register from the beginning of the component. */
18751 #define ALT_USB_HOST_HCINTMSK0_OFST 0x10c
18752 /* The address of the ALT_USB_HOST_HCINTMSK0 register. */
18753 #define ALT_USB_HOST_HCINTMSK0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK0_OFST))
18754 
18755 /*
18756  * Register : hctsiz0
18757  *
18758  * Host Channel 0 Transfer Size Register
18759  *
18760  * Register Layout
18761  *
18762  * Bits | Access | Reset | Description
18763  * :--------|:-------|:------|:------------------------------
18764  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ0_XFERSIZE
18765  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ0_PKTCNT
18766  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ0_PID
18767  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ0_DOPNG
18768  *
18769  */
18770 /*
18771  * Field : xfersize
18772  *
18773  * Transfer Size (XferSize)
18774  *
18775  * For an OUT, this field is the number of data bytes the host sends
18776  *
18777  * during the transfer.
18778  *
18779  * For an IN, this field is the buffer size that the application has
18780  *
18781  * Reserved For the transfer. The application is expected to
18782  *
18783  * program this field as an integer multiple of the maximum packet
18784  *
18785  * size For IN transactions (periodic and non-periodic).
18786  *
18787  * The width of this counter is specified as Width of Transfer Size
18788  *
18789  * Counters
18790  *
18791  * Field Access Macros:
18792  *
18793  */
18794 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */
18795 #define ALT_USB_HOST_HCTSIZ0_XFERSIZE_LSB 0
18796 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */
18797 #define ALT_USB_HOST_HCTSIZ0_XFERSIZE_MSB 18
18798 /* The width in bits of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */
18799 #define ALT_USB_HOST_HCTSIZ0_XFERSIZE_WIDTH 19
18800 /* The mask used to set the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field value. */
18801 #define ALT_USB_HOST_HCTSIZ0_XFERSIZE_SET_MSK 0x0007ffff
18802 /* The mask used to clear the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field value. */
18803 #define ALT_USB_HOST_HCTSIZ0_XFERSIZE_CLR_MSK 0xfff80000
18804 /* The reset value of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */
18805 #define ALT_USB_HOST_HCTSIZ0_XFERSIZE_RESET 0x0
18806 /* Extracts the ALT_USB_HOST_HCTSIZ0_XFERSIZE field value from a register. */
18807 #define ALT_USB_HOST_HCTSIZ0_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
18808 /* Produces a ALT_USB_HOST_HCTSIZ0_XFERSIZE register field value suitable for setting the register. */
18809 #define ALT_USB_HOST_HCTSIZ0_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
18810 
18811 /*
18812  * Field : pktcnt
18813  *
18814  * Packet Count (PktCnt)
18815  *
18816  * This field is programmed by the application with the expected
18817  *
18818  * number of packets to be transmitted (OUT) or received (IN).
18819  *
18820  * The host decrements this count on every successful
18821  *
18822  * transmission or reception of an OUT/IN packet. Once this count
18823  *
18824  * reaches zero, the application is interrupted to indicate normal
18825  *
18826  * completion.
18827  *
18828  * The width of this counter is specified as Width of Packet
18829  *
18830  * Counters
18831  *
18832  * Field Access Macros:
18833  *
18834  */
18835 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */
18836 #define ALT_USB_HOST_HCTSIZ0_PKTCNT_LSB 19
18837 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */
18838 #define ALT_USB_HOST_HCTSIZ0_PKTCNT_MSB 28
18839 /* The width in bits of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */
18840 #define ALT_USB_HOST_HCTSIZ0_PKTCNT_WIDTH 10
18841 /* The mask used to set the ALT_USB_HOST_HCTSIZ0_PKTCNT register field value. */
18842 #define ALT_USB_HOST_HCTSIZ0_PKTCNT_SET_MSK 0x1ff80000
18843 /* The mask used to clear the ALT_USB_HOST_HCTSIZ0_PKTCNT register field value. */
18844 #define ALT_USB_HOST_HCTSIZ0_PKTCNT_CLR_MSK 0xe007ffff
18845 /* The reset value of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */
18846 #define ALT_USB_HOST_HCTSIZ0_PKTCNT_RESET 0x0
18847 /* Extracts the ALT_USB_HOST_HCTSIZ0_PKTCNT field value from a register. */
18848 #define ALT_USB_HOST_HCTSIZ0_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
18849 /* Produces a ALT_USB_HOST_HCTSIZ0_PKTCNT register field value suitable for setting the register. */
18850 #define ALT_USB_HOST_HCTSIZ0_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
18851 
18852 /*
18853  * Field : pid
18854  *
18855  * PID (Pid)
18856  *
18857  * The application programs this field with the type of PID to use For
18858  *
18859  * the initial transaction. The host maintains this field For the rest of
18860  *
18861  * the transfer.
18862  *
18863  * 2'b00: DATA0
18864  *
18865  * 2'b01: DATA2
18866  *
18867  * 2'b10: DATA1
18868  *
18869  * 2'b11: MDATA (non-control)/SETUP (control)
18870  *
18871  * Field Enumeration Values:
18872  *
18873  * Enum | Value | Description
18874  * :---------------------------------|:------|:------------------------------------
18875  * ALT_USB_HOST_HCTSIZ0_PID_E_DATA0 | 0x0 | DATA0
18876  * ALT_USB_HOST_HCTSIZ0_PID_E_DATA2 | 0x1 | DATA2
18877  * ALT_USB_HOST_HCTSIZ0_PID_E_DATA1 | 0x2 | DATA1
18878  * ALT_USB_HOST_HCTSIZ0_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
18879  *
18880  * Field Access Macros:
18881  *
18882  */
18883 /*
18884  * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID
18885  *
18886  * DATA0
18887  */
18888 #define ALT_USB_HOST_HCTSIZ0_PID_E_DATA0 0x0
18889 /*
18890  * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID
18891  *
18892  * DATA2
18893  */
18894 #define ALT_USB_HOST_HCTSIZ0_PID_E_DATA2 0x1
18895 /*
18896  * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID
18897  *
18898  * DATA1
18899  */
18900 #define ALT_USB_HOST_HCTSIZ0_PID_E_DATA1 0x2
18901 /*
18902  * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID
18903  *
18904  * MDATA (non-control)/SETUP (control)
18905  */
18906 #define ALT_USB_HOST_HCTSIZ0_PID_E_MDATA 0x3
18907 
18908 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_PID register field. */
18909 #define ALT_USB_HOST_HCTSIZ0_PID_LSB 29
18910 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_PID register field. */
18911 #define ALT_USB_HOST_HCTSIZ0_PID_MSB 30
18912 /* The width in bits of the ALT_USB_HOST_HCTSIZ0_PID register field. */
18913 #define ALT_USB_HOST_HCTSIZ0_PID_WIDTH 2
18914 /* The mask used to set the ALT_USB_HOST_HCTSIZ0_PID register field value. */
18915 #define ALT_USB_HOST_HCTSIZ0_PID_SET_MSK 0x60000000
18916 /* The mask used to clear the ALT_USB_HOST_HCTSIZ0_PID register field value. */
18917 #define ALT_USB_HOST_HCTSIZ0_PID_CLR_MSK 0x9fffffff
18918 /* The reset value of the ALT_USB_HOST_HCTSIZ0_PID register field. */
18919 #define ALT_USB_HOST_HCTSIZ0_PID_RESET 0x0
18920 /* Extracts the ALT_USB_HOST_HCTSIZ0_PID field value from a register. */
18921 #define ALT_USB_HOST_HCTSIZ0_PID_GET(value) (((value) & 0x60000000) >> 29)
18922 /* Produces a ALT_USB_HOST_HCTSIZ0_PID register field value suitable for setting the register. */
18923 #define ALT_USB_HOST_HCTSIZ0_PID_SET(value) (((value) << 29) & 0x60000000)
18924 
18925 /*
18926  * Field : dopng
18927  *
18928  * Do Ping (DoPng)
18929  *
18930  * This bit is used only For OUT transfers.
18931  *
18932  * Setting this field to 1 directs the host to do PING protocol.
18933  *
18934  * Note: Do not Set this bit For IN transfers. If this bit is Set For
18935  *
18936  * for IN transfers it disables the channel.
18937  *
18938  * Field Enumeration Values:
18939  *
18940  * Enum | Value | Description
18941  * :------------------------------------|:------|:-----------------
18942  * ALT_USB_HOST_HCTSIZ0_DOPNG_E_NOPING | 0x0 | No ping protocol
18943  * ALT_USB_HOST_HCTSIZ0_DOPNG_E_PING | 0x1 | Ping protocol
18944  *
18945  * Field Access Macros:
18946  *
18947  */
18948 /*
18949  * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_DOPNG
18950  *
18951  * No ping protocol
18952  */
18953 #define ALT_USB_HOST_HCTSIZ0_DOPNG_E_NOPING 0x0
18954 /*
18955  * Enumerated value for register field ALT_USB_HOST_HCTSIZ0_DOPNG
18956  *
18957  * Ping protocol
18958  */
18959 #define ALT_USB_HOST_HCTSIZ0_DOPNG_E_PING 0x1
18960 
18961 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */
18962 #define ALT_USB_HOST_HCTSIZ0_DOPNG_LSB 31
18963 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */
18964 #define ALT_USB_HOST_HCTSIZ0_DOPNG_MSB 31
18965 /* The width in bits of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */
18966 #define ALT_USB_HOST_HCTSIZ0_DOPNG_WIDTH 1
18967 /* The mask used to set the ALT_USB_HOST_HCTSIZ0_DOPNG register field value. */
18968 #define ALT_USB_HOST_HCTSIZ0_DOPNG_SET_MSK 0x80000000
18969 /* The mask used to clear the ALT_USB_HOST_HCTSIZ0_DOPNG register field value. */
18970 #define ALT_USB_HOST_HCTSIZ0_DOPNG_CLR_MSK 0x7fffffff
18971 /* The reset value of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */
18972 #define ALT_USB_HOST_HCTSIZ0_DOPNG_RESET 0x0
18973 /* Extracts the ALT_USB_HOST_HCTSIZ0_DOPNG field value from a register. */
18974 #define ALT_USB_HOST_HCTSIZ0_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
18975 /* Produces a ALT_USB_HOST_HCTSIZ0_DOPNG register field value suitable for setting the register. */
18976 #define ALT_USB_HOST_HCTSIZ0_DOPNG_SET(value) (((value) << 31) & 0x80000000)
18977 
18978 #ifndef __ASSEMBLY__
18979 /*
18980  * WARNING: The C register and register group struct declarations are provided for
18981  * convenience and illustrative purposes. They should, however, be used with
18982  * caution as the C language standard provides no guarantees about the alignment or
18983  * atomicity of device memory accesses. The recommended practice for writing
18984  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18985  * alt_write_word() functions.
18986  *
18987  * The struct declaration for register ALT_USB_HOST_HCTSIZ0.
18988  */
18989 struct ALT_USB_HOST_HCTSIZ0_s
18990 {
18991  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ0_XFERSIZE */
18992  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ0_PKTCNT */
18993  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ0_PID */
18994  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ0_DOPNG */
18995 };
18996 
18997 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ0. */
18998 typedef volatile struct ALT_USB_HOST_HCTSIZ0_s ALT_USB_HOST_HCTSIZ0_t;
18999 #endif /* __ASSEMBLY__ */
19000 
19001 /* The reset value of the ALT_USB_HOST_HCTSIZ0 register. */
19002 #define ALT_USB_HOST_HCTSIZ0_RESET 0x00000000
19003 /* The byte offset of the ALT_USB_HOST_HCTSIZ0 register from the beginning of the component. */
19004 #define ALT_USB_HOST_HCTSIZ0_OFST 0x110
19005 /* The address of the ALT_USB_HOST_HCTSIZ0 register. */
19006 #define ALT_USB_HOST_HCTSIZ0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ0_OFST))
19007 
19008 /*
19009  * Register : hcdma0
19010  *
19011  * Host Channel 0 DMA Address Register
19012  *
19013  * Register Layout
19014  *
19015  * Bits | Access | Reset | Description
19016  * :-------|:-------|:------|:---------------------------
19017  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA0_HCDMA0
19018  *
19019  */
19020 /*
19021  * Field : hcdma0
19022  *
19023  * Buffer DMA Mode:
19024  *
19025  * [31:0] DMA Address (DMAAddr)
19026  *
19027  * This field holds the start address in the external memory from which the data
19028  * for
19029  *
19030  * the endpoint must be fetched or to which it must be stored. This register is
19031  *
19032  * incremented on every AHB transaction.
19033  *
19034  * Scatter-Gather DMA (DescDMA) Mode:
19035  *
19036  * [31:9] (Non Isoc) Non-Isochronous:
19037  *
19038  * [31:N] (Isoc) Isochronous:
19039  *
19040  * This field holds the start address of the 512 bytes
19041  *
19042  * page. The first descriptor in the list should be located
19043  *
19044  * in this address. The first descriptor may be or may
19045  *
19046  * not be ready. The core starts processing the list from
19047  *
19048  * the CTD value.
19049  *
19050  * This field holds the address of the 2*(nTD+1) bytes of
19051  *
19052  * locations in which the isochronous descriptors are
19053  *
19054  * present where N is based on nTD as per Table below
19055  *
19056  * [31:N] Base Address
19057  *
19058  * [N-1:3] Offset
19059  *
19060  * [2:0] 000
19061  *
19062  * HS ISOC
19063  *
19064  * nTD N
19065  *
19066  * 7 6
19067  *
19068  * 15 7
19069  *
19070  * 31 8
19071  *
19072  * 63 9
19073  *
19074  * 127 10
19075  *
19076  * 255 11
19077  *
19078  * FS ISOC
19079  *
19080  * nTD N
19081  *
19082  * 1 4
19083  *
19084  * 3 5
19085  *
19086  * 7 6
19087  *
19088  * 15 7
19089  *
19090  * 31 8
19091  *
19092  * 63 9
19093  *
19094  * [N-1:3] (Isoc):
19095  *
19096  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
19097  *
19098  * Non Isochronous:
19099  *
19100  * This value is in terms of number of descriptors. The values can be from 0 to 63.
19101  *
19102  * 0 - 1 descriptor.
19103  *
19104  * 63 - 64 descriptors.
19105  *
19106  * This field indicates the current descriptor processed in the list. This field is
19107  * updated
19108  *
19109  * both by application and the core. For example, if the application enables the
19110  *
19111  * channel after programming CTD=5, then the core will start processing the 6th
19112  *
19113  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
19114  *
19115  * to DMAAddr.
19116  *
19117  * Isochronous:
19118  *
19119  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
19120  * set
19121  *
19122  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
19123  *
19124  * [31:9] (Non Isoc) Non-Isochronous:
19125  *
19126  * [31:N] (Isoc) Isochronous:
19127  *
19128  * This field holds the start address of the 512 bytes
19129  *
19130  * page. The first descriptor in the list should be located
19131  *
19132  * in this address. The first descriptor may be or may
19133  *
19134  * not be ready. The core starts processing the list from
19135  *
19136  * the CTD value.
19137  *
19138  * This field holds the address of the 2*(nTD+1) bytes of
19139  *
19140  * locations in which the isochronous descriptors are
19141  *
19142  * present where N is based on nTD as per Table below
19143  *
19144  * [31:N] Base Address
19145  *
19146  * [N-1:3] Offset
19147  *
19148  * [2:0] 000
19149  *
19150  * HS ISOC
19151  *
19152  * nTD N
19153  *
19154  * 7 6
19155  *
19156  * 15 7
19157  *
19158  * 31 8
19159  *
19160  * 63 9
19161  *
19162  * 127 10
19163  *
19164  * 255 11
19165  *
19166  * FS ISOC
19167  *
19168  * nTD N
19169  *
19170  * 1 4
19171  *
19172  * 3 5
19173  *
19174  * 7 6
19175  *
19176  * 15 7
19177  *
19178  * 31 8
19179  *
19180  * 63 9
19181  *
19182  * [N-1:3] (Isoc):
19183  *
19184  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
19185  *
19186  * Non Isochronous:
19187  *
19188  * This value is in terms of number of descriptors. The values can be from 0 to 63.
19189  *
19190  * 0 - 1 descriptor.
19191  *
19192  * 63 - 64 descriptors.
19193  *
19194  * This field indicates the current descriptor processed in the list. This field is
19195  * updated
19196  *
19197  * both by application and the core. For example, if the application enables the
19198  *
19199  * channel after programming CTD=5, then the core will start processing the 6th
19200  *
19201  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
19202  *
19203  * to DMAAddr.
19204  *
19205  * Isochronous:
19206  *
19207  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
19208  * set
19209  *
19210  * to zero by application.
19211  *
19212  * Field Access Macros:
19213  *
19214  */
19215 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */
19216 #define ALT_USB_HOST_HCDMA0_HCDMA0_LSB 0
19217 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */
19218 #define ALT_USB_HOST_HCDMA0_HCDMA0_MSB 31
19219 /* The width in bits of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */
19220 #define ALT_USB_HOST_HCDMA0_HCDMA0_WIDTH 32
19221 /* The mask used to set the ALT_USB_HOST_HCDMA0_HCDMA0 register field value. */
19222 #define ALT_USB_HOST_HCDMA0_HCDMA0_SET_MSK 0xffffffff
19223 /* The mask used to clear the ALT_USB_HOST_HCDMA0_HCDMA0 register field value. */
19224 #define ALT_USB_HOST_HCDMA0_HCDMA0_CLR_MSK 0x00000000
19225 /* The reset value of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */
19226 #define ALT_USB_HOST_HCDMA0_HCDMA0_RESET 0x0
19227 /* Extracts the ALT_USB_HOST_HCDMA0_HCDMA0 field value from a register. */
19228 #define ALT_USB_HOST_HCDMA0_HCDMA0_GET(value) (((value) & 0xffffffff) >> 0)
19229 /* Produces a ALT_USB_HOST_HCDMA0_HCDMA0 register field value suitable for setting the register. */
19230 #define ALT_USB_HOST_HCDMA0_HCDMA0_SET(value) (((value) << 0) & 0xffffffff)
19231 
19232 #ifndef __ASSEMBLY__
19233 /*
19234  * WARNING: The C register and register group struct declarations are provided for
19235  * convenience and illustrative purposes. They should, however, be used with
19236  * caution as the C language standard provides no guarantees about the alignment or
19237  * atomicity of device memory accesses. The recommended practice for writing
19238  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19239  * alt_write_word() functions.
19240  *
19241  * The struct declaration for register ALT_USB_HOST_HCDMA0.
19242  */
19243 struct ALT_USB_HOST_HCDMA0_s
19244 {
19245  uint32_t hcdma0 : 32; /* ALT_USB_HOST_HCDMA0_HCDMA0 */
19246 };
19247 
19248 /* The typedef declaration for register ALT_USB_HOST_HCDMA0. */
19249 typedef volatile struct ALT_USB_HOST_HCDMA0_s ALT_USB_HOST_HCDMA0_t;
19250 #endif /* __ASSEMBLY__ */
19251 
19252 /* The reset value of the ALT_USB_HOST_HCDMA0 register. */
19253 #define ALT_USB_HOST_HCDMA0_RESET 0x00000000
19254 /* The byte offset of the ALT_USB_HOST_HCDMA0 register from the beginning of the component. */
19255 #define ALT_USB_HOST_HCDMA0_OFST 0x114
19256 /* The address of the ALT_USB_HOST_HCDMA0 register. */
19257 #define ALT_USB_HOST_HCDMA0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA0_OFST))
19258 
19259 /*
19260  * Register : hcdmab0
19261  *
19262  * Host Channel 0 DMA Buffer Address Register
19263  *
19264  * Register Layout
19265  *
19266  * Bits | Access | Reset | Description
19267  * :-------|:-------|:------|:-----------------------------
19268  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB0_HCDMAB0
19269  *
19270  */
19271 /*
19272  * Field : hcdmab0
19273  *
19274  * Holds the current buffer address.
19275  *
19276  * This register is updated as and when the data transfer for the corresponding end
19277  * point
19278  *
19279  * is in progress. This register is present only in Scatter/Gather DMA mode.
19280  * Otherwise this
19281  *
19282  * field is reserved.
19283  *
19284  * Field Access Macros:
19285  *
19286  */
19287 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */
19288 #define ALT_USB_HOST_HCDMAB0_HCDMAB0_LSB 0
19289 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */
19290 #define ALT_USB_HOST_HCDMAB0_HCDMAB0_MSB 31
19291 /* The width in bits of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */
19292 #define ALT_USB_HOST_HCDMAB0_HCDMAB0_WIDTH 32
19293 /* The mask used to set the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field value. */
19294 #define ALT_USB_HOST_HCDMAB0_HCDMAB0_SET_MSK 0xffffffff
19295 /* The mask used to clear the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field value. */
19296 #define ALT_USB_HOST_HCDMAB0_HCDMAB0_CLR_MSK 0x00000000
19297 /* The reset value of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */
19298 #define ALT_USB_HOST_HCDMAB0_HCDMAB0_RESET 0x0
19299 /* Extracts the ALT_USB_HOST_HCDMAB0_HCDMAB0 field value from a register. */
19300 #define ALT_USB_HOST_HCDMAB0_HCDMAB0_GET(value) (((value) & 0xffffffff) >> 0)
19301 /* Produces a ALT_USB_HOST_HCDMAB0_HCDMAB0 register field value suitable for setting the register. */
19302 #define ALT_USB_HOST_HCDMAB0_HCDMAB0_SET(value) (((value) << 0) & 0xffffffff)
19303 
19304 #ifndef __ASSEMBLY__
19305 /*
19306  * WARNING: The C register and register group struct declarations are provided for
19307  * convenience and illustrative purposes. They should, however, be used with
19308  * caution as the C language standard provides no guarantees about the alignment or
19309  * atomicity of device memory accesses. The recommended practice for writing
19310  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19311  * alt_write_word() functions.
19312  *
19313  * The struct declaration for register ALT_USB_HOST_HCDMAB0.
19314  */
19315 struct ALT_USB_HOST_HCDMAB0_s
19316 {
19317  uint32_t hcdmab0 : 32; /* ALT_USB_HOST_HCDMAB0_HCDMAB0 */
19318 };
19319 
19320 /* The typedef declaration for register ALT_USB_HOST_HCDMAB0. */
19321 typedef volatile struct ALT_USB_HOST_HCDMAB0_s ALT_USB_HOST_HCDMAB0_t;
19322 #endif /* __ASSEMBLY__ */
19323 
19324 /* The reset value of the ALT_USB_HOST_HCDMAB0 register. */
19325 #define ALT_USB_HOST_HCDMAB0_RESET 0x00000000
19326 /* The byte offset of the ALT_USB_HOST_HCDMAB0 register from the beginning of the component. */
19327 #define ALT_USB_HOST_HCDMAB0_OFST 0x11c
19328 /* The address of the ALT_USB_HOST_HCDMAB0 register. */
19329 #define ALT_USB_HOST_HCDMAB0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB0_OFST))
19330 
19331 /*
19332  * Register : hcchar1
19333  *
19334  * Host Channel 1 Characteristics Register
19335  *
19336  * Register Layout
19337  *
19338  * Bits | Access | Reset | Description
19339  * :--------|:---------|:------|:-----------------------------
19340  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_MPS
19341  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_EPNUM
19342  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_EPDIR
19343  * [16] | ??? | 0x0 | *UNDEFINED*
19344  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_LSPDDEV
19345  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_EPTYPE
19346  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_EC
19347  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_DEVADDR
19348  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_ODDFRM
19349  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR1_CHDIS
19350  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR1_CHENA
19351  *
19352  */
19353 /*
19354  * Field : mps
19355  *
19356  * Maximum Packet Size (MPS)
19357  *
19358  * Indicates the maximum packet size of the associated endpoint.
19359  *
19360  * Field Access Macros:
19361  *
19362  */
19363 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_MPS register field. */
19364 #define ALT_USB_HOST_HCCHAR1_MPS_LSB 0
19365 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_MPS register field. */
19366 #define ALT_USB_HOST_HCCHAR1_MPS_MSB 10
19367 /* The width in bits of the ALT_USB_HOST_HCCHAR1_MPS register field. */
19368 #define ALT_USB_HOST_HCCHAR1_MPS_WIDTH 11
19369 /* The mask used to set the ALT_USB_HOST_HCCHAR1_MPS register field value. */
19370 #define ALT_USB_HOST_HCCHAR1_MPS_SET_MSK 0x000007ff
19371 /* The mask used to clear the ALT_USB_HOST_HCCHAR1_MPS register field value. */
19372 #define ALT_USB_HOST_HCCHAR1_MPS_CLR_MSK 0xfffff800
19373 /* The reset value of the ALT_USB_HOST_HCCHAR1_MPS register field. */
19374 #define ALT_USB_HOST_HCCHAR1_MPS_RESET 0x0
19375 /* Extracts the ALT_USB_HOST_HCCHAR1_MPS field value from a register. */
19376 #define ALT_USB_HOST_HCCHAR1_MPS_GET(value) (((value) & 0x000007ff) >> 0)
19377 /* Produces a ALT_USB_HOST_HCCHAR1_MPS register field value suitable for setting the register. */
19378 #define ALT_USB_HOST_HCCHAR1_MPS_SET(value) (((value) << 0) & 0x000007ff)
19379 
19380 /*
19381  * Field : epnum
19382  *
19383  * Endpoint Number (EPNum)
19384  *
19385  * Indicates the endpoint number on the device serving as the data
19386  *
19387  * source or sink.
19388  *
19389  * Field Enumeration Values:
19390  *
19391  * Enum | Value | Description
19392  * :-------------------------------------|:------|:--------------
19393  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT0 | 0x0 | End point 0
19394  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT1 | 0x1 | End point 1
19395  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT2 | 0x2 | End point 2
19396  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT3 | 0x3 | End point 3
19397  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT4 | 0x4 | End point 4
19398  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT5 | 0x5 | End point 5
19399  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT6 | 0x6 | End point 6
19400  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT7 | 0x7 | End point 7
19401  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT8 | 0x8 | End point 8
19402  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT9 | 0x9 | End point 9
19403  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT10 | 0xa | End point 10
19404  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT11 | 0xb | End point 11
19405  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT12 | 0xc | End point 12
19406  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT13 | 0xd | End point 13
19407  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT14 | 0xe | End point 14
19408  * ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT15 | 0xf | End point 15
19409  *
19410  * Field Access Macros:
19411  *
19412  */
19413 /*
19414  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19415  *
19416  * End point 0
19417  */
19418 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT0 0x0
19419 /*
19420  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19421  *
19422  * End point 1
19423  */
19424 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT1 0x1
19425 /*
19426  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19427  *
19428  * End point 2
19429  */
19430 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT2 0x2
19431 /*
19432  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19433  *
19434  * End point 3
19435  */
19436 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT3 0x3
19437 /*
19438  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19439  *
19440  * End point 4
19441  */
19442 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT4 0x4
19443 /*
19444  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19445  *
19446  * End point 5
19447  */
19448 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT5 0x5
19449 /*
19450  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19451  *
19452  * End point 6
19453  */
19454 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT6 0x6
19455 /*
19456  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19457  *
19458  * End point 7
19459  */
19460 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT7 0x7
19461 /*
19462  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19463  *
19464  * End point 8
19465  */
19466 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT8 0x8
19467 /*
19468  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19469  *
19470  * End point 9
19471  */
19472 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT9 0x9
19473 /*
19474  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19475  *
19476  * End point 10
19477  */
19478 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT10 0xa
19479 /*
19480  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19481  *
19482  * End point 11
19483  */
19484 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT11 0xb
19485 /*
19486  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19487  *
19488  * End point 12
19489  */
19490 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT12 0xc
19491 /*
19492  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19493  *
19494  * End point 13
19495  */
19496 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT13 0xd
19497 /*
19498  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19499  *
19500  * End point 14
19501  */
19502 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT14 0xe
19503 /*
19504  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
19505  *
19506  * End point 15
19507  */
19508 #define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT15 0xf
19509 
19510 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */
19511 #define ALT_USB_HOST_HCCHAR1_EPNUM_LSB 11
19512 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */
19513 #define ALT_USB_HOST_HCCHAR1_EPNUM_MSB 14
19514 /* The width in bits of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */
19515 #define ALT_USB_HOST_HCCHAR1_EPNUM_WIDTH 4
19516 /* The mask used to set the ALT_USB_HOST_HCCHAR1_EPNUM register field value. */
19517 #define ALT_USB_HOST_HCCHAR1_EPNUM_SET_MSK 0x00007800
19518 /* The mask used to clear the ALT_USB_HOST_HCCHAR1_EPNUM register field value. */
19519 #define ALT_USB_HOST_HCCHAR1_EPNUM_CLR_MSK 0xffff87ff
19520 /* The reset value of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */
19521 #define ALT_USB_HOST_HCCHAR1_EPNUM_RESET 0x0
19522 /* Extracts the ALT_USB_HOST_HCCHAR1_EPNUM field value from a register. */
19523 #define ALT_USB_HOST_HCCHAR1_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
19524 /* Produces a ALT_USB_HOST_HCCHAR1_EPNUM register field value suitable for setting the register. */
19525 #define ALT_USB_HOST_HCCHAR1_EPNUM_SET(value) (((value) << 11) & 0x00007800)
19526 
19527 /*
19528  * Field : epdir
19529  *
19530  * Endpoint Direction (EPDir)
19531  *
19532  * Indicates whether the transaction is IN or OUT.
19533  *
19534  * 1'b0: OUT
19535  *
19536  * 1'b1: IN
19537  *
19538  * Field Enumeration Values:
19539  *
19540  * Enum | Value | Description
19541  * :---------------------------------|:------|:--------------
19542  * ALT_USB_HOST_HCCHAR1_EPDIR_E_OUT | 0x0 | OUT Direction
19543  * ALT_USB_HOST_HCCHAR1_EPDIR_E_IN | 0x1 | IN Direction
19544  *
19545  * Field Access Macros:
19546  *
19547  */
19548 /*
19549  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPDIR
19550  *
19551  * OUT Direction
19552  */
19553 #define ALT_USB_HOST_HCCHAR1_EPDIR_E_OUT 0x0
19554 /*
19555  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPDIR
19556  *
19557  * IN Direction
19558  */
19559 #define ALT_USB_HOST_HCCHAR1_EPDIR_E_IN 0x1
19560 
19561 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */
19562 #define ALT_USB_HOST_HCCHAR1_EPDIR_LSB 15
19563 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */
19564 #define ALT_USB_HOST_HCCHAR1_EPDIR_MSB 15
19565 /* The width in bits of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */
19566 #define ALT_USB_HOST_HCCHAR1_EPDIR_WIDTH 1
19567 /* The mask used to set the ALT_USB_HOST_HCCHAR1_EPDIR register field value. */
19568 #define ALT_USB_HOST_HCCHAR1_EPDIR_SET_MSK 0x00008000
19569 /* The mask used to clear the ALT_USB_HOST_HCCHAR1_EPDIR register field value. */
19570 #define ALT_USB_HOST_HCCHAR1_EPDIR_CLR_MSK 0xffff7fff
19571 /* The reset value of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */
19572 #define ALT_USB_HOST_HCCHAR1_EPDIR_RESET 0x0
19573 /* Extracts the ALT_USB_HOST_HCCHAR1_EPDIR field value from a register. */
19574 #define ALT_USB_HOST_HCCHAR1_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
19575 /* Produces a ALT_USB_HOST_HCCHAR1_EPDIR register field value suitable for setting the register. */
19576 #define ALT_USB_HOST_HCCHAR1_EPDIR_SET(value) (((value) << 15) & 0x00008000)
19577 
19578 /*
19579  * Field : lspddev
19580  *
19581  * Low-Speed Device (LSpdDev)
19582  *
19583  * This field is Set by the application to indicate that this channel is
19584  *
19585  * communicating to a low-speed device.
19586  *
19587  * Field Enumeration Values:
19588  *
19589  * Enum | Value | Description
19590  * :------------------------------------|:------|:----------------------------------------
19591  * ALT_USB_HOST_HCCHAR1_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
19592  * ALT_USB_HOST_HCCHAR1_LSPDDEV_E_END | 0x1 | Communicating with low speed device
19593  *
19594  * Field Access Macros:
19595  *
19596  */
19597 /*
19598  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_LSPDDEV
19599  *
19600  * Not Communicating with low speed device
19601  */
19602 #define ALT_USB_HOST_HCCHAR1_LSPDDEV_E_DISD 0x0
19603 /*
19604  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_LSPDDEV
19605  *
19606  * Communicating with low speed device
19607  */
19608 #define ALT_USB_HOST_HCCHAR1_LSPDDEV_E_END 0x1
19609 
19610 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */
19611 #define ALT_USB_HOST_HCCHAR1_LSPDDEV_LSB 17
19612 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */
19613 #define ALT_USB_HOST_HCCHAR1_LSPDDEV_MSB 17
19614 /* The width in bits of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */
19615 #define ALT_USB_HOST_HCCHAR1_LSPDDEV_WIDTH 1
19616 /* The mask used to set the ALT_USB_HOST_HCCHAR1_LSPDDEV register field value. */
19617 #define ALT_USB_HOST_HCCHAR1_LSPDDEV_SET_MSK 0x00020000
19618 /* The mask used to clear the ALT_USB_HOST_HCCHAR1_LSPDDEV register field value. */
19619 #define ALT_USB_HOST_HCCHAR1_LSPDDEV_CLR_MSK 0xfffdffff
19620 /* The reset value of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */
19621 #define ALT_USB_HOST_HCCHAR1_LSPDDEV_RESET 0x0
19622 /* Extracts the ALT_USB_HOST_HCCHAR1_LSPDDEV field value from a register. */
19623 #define ALT_USB_HOST_HCCHAR1_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
19624 /* Produces a ALT_USB_HOST_HCCHAR1_LSPDDEV register field value suitable for setting the register. */
19625 #define ALT_USB_HOST_HCCHAR1_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
19626 
19627 /*
19628  * Field : eptype
19629  *
19630  * Endpoint Type (EPType)
19631  *
19632  * Indicates the transfer type selected.
19633  *
19634  * 2'b00: Control
19635  *
19636  * 2'b01: Isochronous
19637  *
19638  * 2'b10: Bulk
19639  *
19640  * 2'b11: Interrupt
19641  *
19642  * Field Enumeration Values:
19643  *
19644  * Enum | Value | Description
19645  * :-------------------------------------|:------|:------------
19646  * ALT_USB_HOST_HCCHAR1_EPTYPE_E_CTL | 0x0 | Control
19647  * ALT_USB_HOST_HCCHAR1_EPTYPE_E_ISOC | 0x1 | Isochronous
19648  * ALT_USB_HOST_HCCHAR1_EPTYPE_E_BULK | 0x2 | Bulk
19649  * ALT_USB_HOST_HCCHAR1_EPTYPE_E_INTERR | 0x3 | Interrupt
19650  *
19651  * Field Access Macros:
19652  *
19653  */
19654 /*
19655  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE
19656  *
19657  * Control
19658  */
19659 #define ALT_USB_HOST_HCCHAR1_EPTYPE_E_CTL 0x0
19660 /*
19661  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE
19662  *
19663  * Isochronous
19664  */
19665 #define ALT_USB_HOST_HCCHAR1_EPTYPE_E_ISOC 0x1
19666 /*
19667  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE
19668  *
19669  * Bulk
19670  */
19671 #define ALT_USB_HOST_HCCHAR1_EPTYPE_E_BULK 0x2
19672 /*
19673  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE
19674  *
19675  * Interrupt
19676  */
19677 #define ALT_USB_HOST_HCCHAR1_EPTYPE_E_INTERR 0x3
19678 
19679 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */
19680 #define ALT_USB_HOST_HCCHAR1_EPTYPE_LSB 18
19681 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */
19682 #define ALT_USB_HOST_HCCHAR1_EPTYPE_MSB 19
19683 /* The width in bits of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */
19684 #define ALT_USB_HOST_HCCHAR1_EPTYPE_WIDTH 2
19685 /* The mask used to set the ALT_USB_HOST_HCCHAR1_EPTYPE register field value. */
19686 #define ALT_USB_HOST_HCCHAR1_EPTYPE_SET_MSK 0x000c0000
19687 /* The mask used to clear the ALT_USB_HOST_HCCHAR1_EPTYPE register field value. */
19688 #define ALT_USB_HOST_HCCHAR1_EPTYPE_CLR_MSK 0xfff3ffff
19689 /* The reset value of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */
19690 #define ALT_USB_HOST_HCCHAR1_EPTYPE_RESET 0x0
19691 /* Extracts the ALT_USB_HOST_HCCHAR1_EPTYPE field value from a register. */
19692 #define ALT_USB_HOST_HCCHAR1_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
19693 /* Produces a ALT_USB_HOST_HCCHAR1_EPTYPE register field value suitable for setting the register. */
19694 #define ALT_USB_HOST_HCCHAR1_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
19695 
19696 /*
19697  * Field : ec
19698  *
19699  * Multi Count (MC) / Error Count (EC)
19700  *
19701  * When the Split Enable bit of the Host Channel-n Split Control
19702  *
19703  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
19704  *
19705  * the host the number of transactions that must be executed per
19706  *
19707  * microframe For this periodic endpoint. For non periodic transfers,
19708  *
19709  * this field is used only in DMA mode, and specifies the number
19710  *
19711  * packets to be fetched For this channel before the internal DMA
19712  *
19713  * engine changes arbitration.
19714  *
19715  * 2'b00: Reserved This field yields undefined results.
19716  *
19717  * 2'b01: 1 transaction
19718  *
19719  * 2'b10: 2 transactions to be issued For this endpoint per
19720  *
19721  * microframe
19722  *
19723  * 2'b11: 3 transactions to be issued For this endpoint per
19724  *
19725  * microframe
19726  *
19727  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
19728  *
19729  * number of immediate retries to be performed For a periodic split
19730  *
19731  * transactions on transaction errors. This field must be Set to at
19732  *
19733  * least 2'b01.
19734  *
19735  * Field Enumeration Values:
19736  *
19737  * Enum | Value | Description
19738  * :-------------------------------------|:------|:----------------------------------------------
19739  * ALT_USB_HOST_HCCHAR1_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
19740  * ALT_USB_HOST_HCCHAR1_EC_E_TRANSONE | 0x1 | 1 transaction
19741  * ALT_USB_HOST_HCCHAR1_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
19742  * : | | per microframe
19743  * ALT_USB_HOST_HCCHAR1_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
19744  * : | | per microframe
19745  *
19746  * Field Access Macros:
19747  *
19748  */
19749 /*
19750  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC
19751  *
19752  * Reserved This field yields undefined result
19753  */
19754 #define ALT_USB_HOST_HCCHAR1_EC_E_RSVD 0x0
19755 /*
19756  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC
19757  *
19758  * 1 transaction
19759  */
19760 #define ALT_USB_HOST_HCCHAR1_EC_E_TRANSONE 0x1
19761 /*
19762  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC
19763  *
19764  * 2 transactions to be issued for this endpoint per microframe
19765  */
19766 #define ALT_USB_HOST_HCCHAR1_EC_E_TRANSTWO 0x2
19767 /*
19768  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC
19769  *
19770  * 3 transactions to be issued for this endpoint per microframe
19771  */
19772 #define ALT_USB_HOST_HCCHAR1_EC_E_TRANSTHREE 0x3
19773 
19774 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EC register field. */
19775 #define ALT_USB_HOST_HCCHAR1_EC_LSB 20
19776 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EC register field. */
19777 #define ALT_USB_HOST_HCCHAR1_EC_MSB 21
19778 /* The width in bits of the ALT_USB_HOST_HCCHAR1_EC register field. */
19779 #define ALT_USB_HOST_HCCHAR1_EC_WIDTH 2
19780 /* The mask used to set the ALT_USB_HOST_HCCHAR1_EC register field value. */
19781 #define ALT_USB_HOST_HCCHAR1_EC_SET_MSK 0x00300000
19782 /* The mask used to clear the ALT_USB_HOST_HCCHAR1_EC register field value. */
19783 #define ALT_USB_HOST_HCCHAR1_EC_CLR_MSK 0xffcfffff
19784 /* The reset value of the ALT_USB_HOST_HCCHAR1_EC register field. */
19785 #define ALT_USB_HOST_HCCHAR1_EC_RESET 0x0
19786 /* Extracts the ALT_USB_HOST_HCCHAR1_EC field value from a register. */
19787 #define ALT_USB_HOST_HCCHAR1_EC_GET(value) (((value) & 0x00300000) >> 20)
19788 /* Produces a ALT_USB_HOST_HCCHAR1_EC register field value suitable for setting the register. */
19789 #define ALT_USB_HOST_HCCHAR1_EC_SET(value) (((value) << 20) & 0x00300000)
19790 
19791 /*
19792  * Field : devaddr
19793  *
19794  * Device Address (DevAddr)
19795  *
19796  * This field selects the specific device serving as the data source
19797  *
19798  * or sink.
19799  *
19800  * Field Access Macros:
19801  *
19802  */
19803 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */
19804 #define ALT_USB_HOST_HCCHAR1_DEVADDR_LSB 22
19805 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */
19806 #define ALT_USB_HOST_HCCHAR1_DEVADDR_MSB 28
19807 /* The width in bits of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */
19808 #define ALT_USB_HOST_HCCHAR1_DEVADDR_WIDTH 7
19809 /* The mask used to set the ALT_USB_HOST_HCCHAR1_DEVADDR register field value. */
19810 #define ALT_USB_HOST_HCCHAR1_DEVADDR_SET_MSK 0x1fc00000
19811 /* The mask used to clear the ALT_USB_HOST_HCCHAR1_DEVADDR register field value. */
19812 #define ALT_USB_HOST_HCCHAR1_DEVADDR_CLR_MSK 0xe03fffff
19813 /* The reset value of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */
19814 #define ALT_USB_HOST_HCCHAR1_DEVADDR_RESET 0x0
19815 /* Extracts the ALT_USB_HOST_HCCHAR1_DEVADDR field value from a register. */
19816 #define ALT_USB_HOST_HCCHAR1_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
19817 /* Produces a ALT_USB_HOST_HCCHAR1_DEVADDR register field value suitable for setting the register. */
19818 #define ALT_USB_HOST_HCCHAR1_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
19819 
19820 /*
19821  * Field : oddfrm
19822  *
19823  * Odd Frame (OddFrm)
19824  *
19825  * This field is set (reset) by the application to indicate that the OTG host must
19826  * perform
19827  *
19828  * a transfer in an odd (micro)frame. This field is applicable for only periodic
19829  *
19830  * (isochronous and interrupt) transactions.
19831  *
19832  * 1'b0: Even (micro)frame
19833  *
19834  * 1'b1: Odd (micro)frame
19835  *
19836  * Field Access Macros:
19837  *
19838  */
19839 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_ODDFRM register field. */
19840 #define ALT_USB_HOST_HCCHAR1_ODDFRM_LSB 29
19841 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_ODDFRM register field. */
19842 #define ALT_USB_HOST_HCCHAR1_ODDFRM_MSB 29
19843 /* The width in bits of the ALT_USB_HOST_HCCHAR1_ODDFRM register field. */
19844 #define ALT_USB_HOST_HCCHAR1_ODDFRM_WIDTH 1
19845 /* The mask used to set the ALT_USB_HOST_HCCHAR1_ODDFRM register field value. */
19846 #define ALT_USB_HOST_HCCHAR1_ODDFRM_SET_MSK 0x20000000
19847 /* The mask used to clear the ALT_USB_HOST_HCCHAR1_ODDFRM register field value. */
19848 #define ALT_USB_HOST_HCCHAR1_ODDFRM_CLR_MSK 0xdfffffff
19849 /* The reset value of the ALT_USB_HOST_HCCHAR1_ODDFRM register field. */
19850 #define ALT_USB_HOST_HCCHAR1_ODDFRM_RESET 0x0
19851 /* Extracts the ALT_USB_HOST_HCCHAR1_ODDFRM field value from a register. */
19852 #define ALT_USB_HOST_HCCHAR1_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
19853 /* Produces a ALT_USB_HOST_HCCHAR1_ODDFRM register field value suitable for setting the register. */
19854 #define ALT_USB_HOST_HCCHAR1_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
19855 
19856 /*
19857  * Field : chdis
19858  *
19859  * Channel Disable (ChDis)
19860  *
19861  * The application sets this bit to stop transmitting/receiving data
19862  *
19863  * on a channel, even before the transfer For that channel is
19864  *
19865  * complete. The application must wait For the Channel Disabled
19866  *
19867  * interrupt before treating the channel as disabled.
19868  *
19869  * Field Enumeration Values:
19870  *
19871  * Enum | Value | Description
19872  * :-----------------------------------|:------|:----------------------------
19873  * ALT_USB_HOST_HCCHAR1_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
19874  * ALT_USB_HOST_HCCHAR1_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
19875  *
19876  * Field Access Macros:
19877  *
19878  */
19879 /*
19880  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHDIS
19881  *
19882  * Transmit/Recieve normal
19883  */
19884 #define ALT_USB_HOST_HCCHAR1_CHDIS_E_INACT 0x0
19885 /*
19886  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHDIS
19887  *
19888  * Stop transmitting/receiving
19889  */
19890 #define ALT_USB_HOST_HCCHAR1_CHDIS_E_ACT 0x1
19891 
19892 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */
19893 #define ALT_USB_HOST_HCCHAR1_CHDIS_LSB 30
19894 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */
19895 #define ALT_USB_HOST_HCCHAR1_CHDIS_MSB 30
19896 /* The width in bits of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */
19897 #define ALT_USB_HOST_HCCHAR1_CHDIS_WIDTH 1
19898 /* The mask used to set the ALT_USB_HOST_HCCHAR1_CHDIS register field value. */
19899 #define ALT_USB_HOST_HCCHAR1_CHDIS_SET_MSK 0x40000000
19900 /* The mask used to clear the ALT_USB_HOST_HCCHAR1_CHDIS register field value. */
19901 #define ALT_USB_HOST_HCCHAR1_CHDIS_CLR_MSK 0xbfffffff
19902 /* The reset value of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */
19903 #define ALT_USB_HOST_HCCHAR1_CHDIS_RESET 0x0
19904 /* Extracts the ALT_USB_HOST_HCCHAR1_CHDIS field value from a register. */
19905 #define ALT_USB_HOST_HCCHAR1_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
19906 /* Produces a ALT_USB_HOST_HCCHAR1_CHDIS register field value suitable for setting the register. */
19907 #define ALT_USB_HOST_HCCHAR1_CHDIS_SET(value) (((value) << 30) & 0x40000000)
19908 
19909 /*
19910  * Field : chena
19911  *
19912  * Channel Enable (ChEna)
19913  *
19914  * When Scatter/Gather mode is enabled
19915  *
19916  * 1'b0: Indicates that the descriptor structure is not yet ready.
19917  *
19918  * 1'b1: Indicates that the descriptor structure and data buffer with
19919  *
19920  * data is setup and this channel can access the descriptor.
19921  *
19922  * When Scatter/Gather mode is disabled
19923  *
19924  * This field is set by the application and cleared by the OTG host.
19925  *
19926  * 1'b0: Channel disabled
19927  *
19928  * 1'b1: Channel enabled
19929  *
19930  * Field Enumeration Values:
19931  *
19932  * Enum | Value | Description
19933  * :-----------------------------------|:------|:-------------------------------------------------
19934  * ALT_USB_HOST_HCCHAR1_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
19935  * : | | yet ready
19936  * ALT_USB_HOST_HCCHAR1_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
19937  * : | | data buffer with data is setup and this
19938  * : | | channel can access the descriptor
19939  *
19940  * Field Access Macros:
19941  *
19942  */
19943 /*
19944  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHENA
19945  *
19946  * Indicates that the descriptor structure is not yet ready
19947  */
19948 #define ALT_USB_HOST_HCCHAR1_CHENA_E_INACT 0x0
19949 /*
19950  * Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHENA
19951  *
19952  * Indicates that the descriptor structure and data buffer with data is
19953  * setup and this channel can access the descriptor
19954  */
19955 #define ALT_USB_HOST_HCCHAR1_CHENA_E_ACT 0x1
19956 
19957 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_CHENA register field. */
19958 #define ALT_USB_HOST_HCCHAR1_CHENA_LSB 31
19959 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_CHENA register field. */
19960 #define ALT_USB_HOST_HCCHAR1_CHENA_MSB 31
19961 /* The width in bits of the ALT_USB_HOST_HCCHAR1_CHENA register field. */
19962 #define ALT_USB_HOST_HCCHAR1_CHENA_WIDTH 1
19963 /* The mask used to set the ALT_USB_HOST_HCCHAR1_CHENA register field value. */
19964 #define ALT_USB_HOST_HCCHAR1_CHENA_SET_MSK 0x80000000
19965 /* The mask used to clear the ALT_USB_HOST_HCCHAR1_CHENA register field value. */
19966 #define ALT_USB_HOST_HCCHAR1_CHENA_CLR_MSK 0x7fffffff
19967 /* The reset value of the ALT_USB_HOST_HCCHAR1_CHENA register field. */
19968 #define ALT_USB_HOST_HCCHAR1_CHENA_RESET 0x0
19969 /* Extracts the ALT_USB_HOST_HCCHAR1_CHENA field value from a register. */
19970 #define ALT_USB_HOST_HCCHAR1_CHENA_GET(value) (((value) & 0x80000000) >> 31)
19971 /* Produces a ALT_USB_HOST_HCCHAR1_CHENA register field value suitable for setting the register. */
19972 #define ALT_USB_HOST_HCCHAR1_CHENA_SET(value) (((value) << 31) & 0x80000000)
19973 
19974 #ifndef __ASSEMBLY__
19975 /*
19976  * WARNING: The C register and register group struct declarations are provided for
19977  * convenience and illustrative purposes. They should, however, be used with
19978  * caution as the C language standard provides no guarantees about the alignment or
19979  * atomicity of device memory accesses. The recommended practice for writing
19980  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19981  * alt_write_word() functions.
19982  *
19983  * The struct declaration for register ALT_USB_HOST_HCCHAR1.
19984  */
19985 struct ALT_USB_HOST_HCCHAR1_s
19986 {
19987  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR1_MPS */
19988  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR1_EPNUM */
19989  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR1_EPDIR */
19990  uint32_t : 1; /* *UNDEFINED* */
19991  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR1_LSPDDEV */
19992  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR1_EPTYPE */
19993  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR1_EC */
19994  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR1_DEVADDR */
19995  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR1_ODDFRM */
19996  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR1_CHDIS */
19997  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR1_CHENA */
19998 };
19999 
20000 /* The typedef declaration for register ALT_USB_HOST_HCCHAR1. */
20001 typedef volatile struct ALT_USB_HOST_HCCHAR1_s ALT_USB_HOST_HCCHAR1_t;
20002 #endif /* __ASSEMBLY__ */
20003 
20004 /* The reset value of the ALT_USB_HOST_HCCHAR1 register. */
20005 #define ALT_USB_HOST_HCCHAR1_RESET 0x00000000
20006 /* The byte offset of the ALT_USB_HOST_HCCHAR1 register from the beginning of the component. */
20007 #define ALT_USB_HOST_HCCHAR1_OFST 0x120
20008 /* The address of the ALT_USB_HOST_HCCHAR1 register. */
20009 #define ALT_USB_HOST_HCCHAR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR1_OFST))
20010 
20011 /*
20012  * Register : hcsplt1
20013  *
20014  * Host Channel 1 Split Control Register
20015  *
20016  * Register Layout
20017  *
20018  * Bits | Access | Reset | Description
20019  * :--------|:-------|:------|:------------------------------
20020  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT1_PRTADDR
20021  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT1_HUBADDR
20022  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT1_XACTPOS
20023  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT1_COMPSPLT
20024  * [30:17] | ??? | 0x0 | *UNDEFINED*
20025  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT1_SPLTENA
20026  *
20027  */
20028 /*
20029  * Field : prtaddr
20030  *
20031  * Port Address (PrtAddr)
20032  *
20033  * This field is the port number of the recipient transaction
20034  *
20035  * translator.
20036  *
20037  * Field Access Macros:
20038  *
20039  */
20040 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */
20041 #define ALT_USB_HOST_HCSPLT1_PRTADDR_LSB 0
20042 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */
20043 #define ALT_USB_HOST_HCSPLT1_PRTADDR_MSB 6
20044 /* The width in bits of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */
20045 #define ALT_USB_HOST_HCSPLT1_PRTADDR_WIDTH 7
20046 /* The mask used to set the ALT_USB_HOST_HCSPLT1_PRTADDR register field value. */
20047 #define ALT_USB_HOST_HCSPLT1_PRTADDR_SET_MSK 0x0000007f
20048 /* The mask used to clear the ALT_USB_HOST_HCSPLT1_PRTADDR register field value. */
20049 #define ALT_USB_HOST_HCSPLT1_PRTADDR_CLR_MSK 0xffffff80
20050 /* The reset value of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */
20051 #define ALT_USB_HOST_HCSPLT1_PRTADDR_RESET 0x0
20052 /* Extracts the ALT_USB_HOST_HCSPLT1_PRTADDR field value from a register. */
20053 #define ALT_USB_HOST_HCSPLT1_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
20054 /* Produces a ALT_USB_HOST_HCSPLT1_PRTADDR register field value suitable for setting the register. */
20055 #define ALT_USB_HOST_HCSPLT1_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
20056 
20057 /*
20058  * Field : hubaddr
20059  *
20060  * Hub Address (HubAddr)
20061  *
20062  * This field holds the device address of the transaction translator's
20063  *
20064  * hub.
20065  *
20066  * Field Access Macros:
20067  *
20068  */
20069 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */
20070 #define ALT_USB_HOST_HCSPLT1_HUBADDR_LSB 7
20071 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */
20072 #define ALT_USB_HOST_HCSPLT1_HUBADDR_MSB 13
20073 /* The width in bits of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */
20074 #define ALT_USB_HOST_HCSPLT1_HUBADDR_WIDTH 7
20075 /* The mask used to set the ALT_USB_HOST_HCSPLT1_HUBADDR register field value. */
20076 #define ALT_USB_HOST_HCSPLT1_HUBADDR_SET_MSK 0x00003f80
20077 /* The mask used to clear the ALT_USB_HOST_HCSPLT1_HUBADDR register field value. */
20078 #define ALT_USB_HOST_HCSPLT1_HUBADDR_CLR_MSK 0xffffc07f
20079 /* The reset value of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */
20080 #define ALT_USB_HOST_HCSPLT1_HUBADDR_RESET 0x0
20081 /* Extracts the ALT_USB_HOST_HCSPLT1_HUBADDR field value from a register. */
20082 #define ALT_USB_HOST_HCSPLT1_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
20083 /* Produces a ALT_USB_HOST_HCSPLT1_HUBADDR register field value suitable for setting the register. */
20084 #define ALT_USB_HOST_HCSPLT1_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
20085 
20086 /*
20087  * Field : xactpos
20088  *
20089  * Transaction Position (XactPos)
20090  *
20091  * This field is used to determine whether to send all, first, middle,
20092  *
20093  * or last payloads with each OUT transaction.
20094  *
20095  * 2'b11: All. This is the entire data payload is of this transaction
20096  *
20097  * (which is less than or equal to 188 bytes).
20098  *
20099  * 2'b10: Begin. This is the first data payload of this transaction
20100  *
20101  * (which is larger than 188 bytes).
20102  *
20103  * 2'b00: Mid. This is the middle payload of this transaction
20104  *
20105  * (which is larger than 188 bytes).
20106  *
20107  * 2'b01: End. This is the last payload of this transaction (which
20108  *
20109  * is larger than 188 bytes).
20110  *
20111  * Field Enumeration Values:
20112  *
20113  * Enum | Value | Description
20114  * :--------------------------------------|:------|:------------------------------------------------
20115  * ALT_USB_HOST_HCSPLT1_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
20116  * : | | transaction (which is larger than 188 bytes)
20117  * ALT_USB_HOST_HCSPLT1_XACTPOS_E_END | 0x1 | End. This is the last payload of this
20118  * : | | transaction (which is larger than 188 bytes)
20119  * ALT_USB_HOST_HCSPLT1_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
20120  * : | | transaction (which is larger than 188 bytes)
20121  * ALT_USB_HOST_HCSPLT1_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
20122  * : | | transaction (which is less than or equal to 188
20123  * : | | bytes)
20124  *
20125  * Field Access Macros:
20126  *
20127  */
20128 /*
20129  * Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS
20130  *
20131  * Mid. This is the middle payload of this transaction (which is larger than 188
20132  * bytes)
20133  */
20134 #define ALT_USB_HOST_HCSPLT1_XACTPOS_E_MIDDLE 0x0
20135 /*
20136  * Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS
20137  *
20138  * End. This is the last payload of this transaction (which is larger than 188
20139  * bytes)
20140  */
20141 #define ALT_USB_HOST_HCSPLT1_XACTPOS_E_END 0x1
20142 /*
20143  * Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS
20144  *
20145  * Begin. This is the first data payload of this transaction (which is larger than
20146  * 188 bytes)
20147  */
20148 #define ALT_USB_HOST_HCSPLT1_XACTPOS_E_BEGIN 0x2
20149 /*
20150  * Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS
20151  *
20152  * All. This is the entire data payload is of this transaction (which is less than
20153  * or equal to 188 bytes)
20154  */
20155 #define ALT_USB_HOST_HCSPLT1_XACTPOS_E_ALL 0x3
20156 
20157 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */
20158 #define ALT_USB_HOST_HCSPLT1_XACTPOS_LSB 14
20159 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */
20160 #define ALT_USB_HOST_HCSPLT1_XACTPOS_MSB 15
20161 /* The width in bits of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */
20162 #define ALT_USB_HOST_HCSPLT1_XACTPOS_WIDTH 2
20163 /* The mask used to set the ALT_USB_HOST_HCSPLT1_XACTPOS register field value. */
20164 #define ALT_USB_HOST_HCSPLT1_XACTPOS_SET_MSK 0x0000c000
20165 /* The mask used to clear the ALT_USB_HOST_HCSPLT1_XACTPOS register field value. */
20166 #define ALT_USB_HOST_HCSPLT1_XACTPOS_CLR_MSK 0xffff3fff
20167 /* The reset value of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */
20168 #define ALT_USB_HOST_HCSPLT1_XACTPOS_RESET 0x0
20169 /* Extracts the ALT_USB_HOST_HCSPLT1_XACTPOS field value from a register. */
20170 #define ALT_USB_HOST_HCSPLT1_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
20171 /* Produces a ALT_USB_HOST_HCSPLT1_XACTPOS register field value suitable for setting the register. */
20172 #define ALT_USB_HOST_HCSPLT1_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
20173 
20174 /*
20175  * Field : compsplt
20176  *
20177  * Do Complete Split (CompSplt)
20178  *
20179  * The application sets this field to request the OTG host to perform
20180  *
20181  * a complete split transaction.
20182  *
20183  * Field Enumeration Values:
20184  *
20185  * Enum | Value | Description
20186  * :----------------------------------------|:------|:---------------------
20187  * ALT_USB_HOST_HCSPLT1_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
20188  * ALT_USB_HOST_HCSPLT1_COMPSPLT_E_SPLIT | 0x1 | Split transaction
20189  *
20190  * Field Access Macros:
20191  *
20192  */
20193 /*
20194  * Enumerated value for register field ALT_USB_HOST_HCSPLT1_COMPSPLT
20195  *
20196  * No split transaction
20197  */
20198 #define ALT_USB_HOST_HCSPLT1_COMPSPLT_E_NOSPLIT 0x0
20199 /*
20200  * Enumerated value for register field ALT_USB_HOST_HCSPLT1_COMPSPLT
20201  *
20202  * Split transaction
20203  */
20204 #define ALT_USB_HOST_HCSPLT1_COMPSPLT_E_SPLIT 0x1
20205 
20206 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */
20207 #define ALT_USB_HOST_HCSPLT1_COMPSPLT_LSB 16
20208 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */
20209 #define ALT_USB_HOST_HCSPLT1_COMPSPLT_MSB 16
20210 /* The width in bits of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */
20211 #define ALT_USB_HOST_HCSPLT1_COMPSPLT_WIDTH 1
20212 /* The mask used to set the ALT_USB_HOST_HCSPLT1_COMPSPLT register field value. */
20213 #define ALT_USB_HOST_HCSPLT1_COMPSPLT_SET_MSK 0x00010000
20214 /* The mask used to clear the ALT_USB_HOST_HCSPLT1_COMPSPLT register field value. */
20215 #define ALT_USB_HOST_HCSPLT1_COMPSPLT_CLR_MSK 0xfffeffff
20216 /* The reset value of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */
20217 #define ALT_USB_HOST_HCSPLT1_COMPSPLT_RESET 0x0
20218 /* Extracts the ALT_USB_HOST_HCSPLT1_COMPSPLT field value from a register. */
20219 #define ALT_USB_HOST_HCSPLT1_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
20220 /* Produces a ALT_USB_HOST_HCSPLT1_COMPSPLT register field value suitable for setting the register. */
20221 #define ALT_USB_HOST_HCSPLT1_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
20222 
20223 /*
20224  * Field : spltena
20225  *
20226  * Split Enable (SpltEna)
20227  *
20228  * The application sets this field to indicate that this channel is
20229  *
20230  * enabled to perform split transactions.
20231  *
20232  * Field Enumeration Values:
20233  *
20234  * Enum | Value | Description
20235  * :------------------------------------|:------|:------------------
20236  * ALT_USB_HOST_HCSPLT1_SPLTENA_E_DISD | 0x0 | Split not enabled
20237  * ALT_USB_HOST_HCSPLT1_SPLTENA_E_END | 0x1 | Split enabled
20238  *
20239  * Field Access Macros:
20240  *
20241  */
20242 /*
20243  * Enumerated value for register field ALT_USB_HOST_HCSPLT1_SPLTENA
20244  *
20245  * Split not enabled
20246  */
20247 #define ALT_USB_HOST_HCSPLT1_SPLTENA_E_DISD 0x0
20248 /*
20249  * Enumerated value for register field ALT_USB_HOST_HCSPLT1_SPLTENA
20250  *
20251  * Split enabled
20252  */
20253 #define ALT_USB_HOST_HCSPLT1_SPLTENA_E_END 0x1
20254 
20255 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */
20256 #define ALT_USB_HOST_HCSPLT1_SPLTENA_LSB 31
20257 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */
20258 #define ALT_USB_HOST_HCSPLT1_SPLTENA_MSB 31
20259 /* The width in bits of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */
20260 #define ALT_USB_HOST_HCSPLT1_SPLTENA_WIDTH 1
20261 /* The mask used to set the ALT_USB_HOST_HCSPLT1_SPLTENA register field value. */
20262 #define ALT_USB_HOST_HCSPLT1_SPLTENA_SET_MSK 0x80000000
20263 /* The mask used to clear the ALT_USB_HOST_HCSPLT1_SPLTENA register field value. */
20264 #define ALT_USB_HOST_HCSPLT1_SPLTENA_CLR_MSK 0x7fffffff
20265 /* The reset value of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */
20266 #define ALT_USB_HOST_HCSPLT1_SPLTENA_RESET 0x0
20267 /* Extracts the ALT_USB_HOST_HCSPLT1_SPLTENA field value from a register. */
20268 #define ALT_USB_HOST_HCSPLT1_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
20269 /* Produces a ALT_USB_HOST_HCSPLT1_SPLTENA register field value suitable for setting the register. */
20270 #define ALT_USB_HOST_HCSPLT1_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
20271 
20272 #ifndef __ASSEMBLY__
20273 /*
20274  * WARNING: The C register and register group struct declarations are provided for
20275  * convenience and illustrative purposes. They should, however, be used with
20276  * caution as the C language standard provides no guarantees about the alignment or
20277  * atomicity of device memory accesses. The recommended practice for writing
20278  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20279  * alt_write_word() functions.
20280  *
20281  * The struct declaration for register ALT_USB_HOST_HCSPLT1.
20282  */
20283 struct ALT_USB_HOST_HCSPLT1_s
20284 {
20285  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT1_PRTADDR */
20286  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT1_HUBADDR */
20287  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT1_XACTPOS */
20288  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT1_COMPSPLT */
20289  uint32_t : 14; /* *UNDEFINED* */
20290  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT1_SPLTENA */
20291 };
20292 
20293 /* The typedef declaration for register ALT_USB_HOST_HCSPLT1. */
20294 typedef volatile struct ALT_USB_HOST_HCSPLT1_s ALT_USB_HOST_HCSPLT1_t;
20295 #endif /* __ASSEMBLY__ */
20296 
20297 /* The reset value of the ALT_USB_HOST_HCSPLT1 register. */
20298 #define ALT_USB_HOST_HCSPLT1_RESET 0x00000000
20299 /* The byte offset of the ALT_USB_HOST_HCSPLT1 register from the beginning of the component. */
20300 #define ALT_USB_HOST_HCSPLT1_OFST 0x124
20301 /* The address of the ALT_USB_HOST_HCSPLT1 register. */
20302 #define ALT_USB_HOST_HCSPLT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT1_OFST))
20303 
20304 /*
20305  * Register : hcint1
20306  *
20307  * Host Channel 1 Interrupt Register
20308  *
20309  * Register Layout
20310  *
20311  * Bits | Access | Reset | Description
20312  * :--------|:-------|:------|:--------------------------------------
20313  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT1_XFERCOMPL
20314  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT1_CHHLTD
20315  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT1_AHBERR
20316  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT1_STALL
20317  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT1_NAK
20318  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT1_ACK
20319  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT1_NYET
20320  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT1_XACTERR
20321  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT1_BBLERR
20322  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT1_FRMOVRUN
20323  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT1_DATATGLERR
20324  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT1_BNAINTR
20325  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT1_XCS_XACT_ERR
20326  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR
20327  * [31:14] | ??? | 0x0 | *UNDEFINED*
20328  *
20329  */
20330 /*
20331  * Field : xfercompl
20332  *
20333  * Transfer Completed (XferCompl)
20334  *
20335  * Transfer completed normally without any errors.This bit can be set only by the
20336  * core and the application should write 1 to clear it.
20337  *
20338  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
20339  *
20340  * completed with IOC bit set in its descriptor.
20341  *
20342  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
20343  * without
20344  *
20345  * any errors.
20346  *
20347  * Field Enumeration Values:
20348  *
20349  * Enum | Value | Description
20350  * :--------------------------------------|:------|:-----------------------------------------------
20351  * ALT_USB_HOST_HCINT1_XFERCOMPL_E_INACT | 0x0 | No transfer
20352  * ALT_USB_HOST_HCINT1_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
20353  *
20354  * Field Access Macros:
20355  *
20356  */
20357 /*
20358  * Enumerated value for register field ALT_USB_HOST_HCINT1_XFERCOMPL
20359  *
20360  * No transfer
20361  */
20362 #define ALT_USB_HOST_HCINT1_XFERCOMPL_E_INACT 0x0
20363 /*
20364  * Enumerated value for register field ALT_USB_HOST_HCINT1_XFERCOMPL
20365  *
20366  * Transfer completed normally without any errors
20367  */
20368 #define ALT_USB_HOST_HCINT1_XFERCOMPL_E_ACT 0x1
20369 
20370 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */
20371 #define ALT_USB_HOST_HCINT1_XFERCOMPL_LSB 0
20372 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */
20373 #define ALT_USB_HOST_HCINT1_XFERCOMPL_MSB 0
20374 /* The width in bits of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */
20375 #define ALT_USB_HOST_HCINT1_XFERCOMPL_WIDTH 1
20376 /* The mask used to set the ALT_USB_HOST_HCINT1_XFERCOMPL register field value. */
20377 #define ALT_USB_HOST_HCINT1_XFERCOMPL_SET_MSK 0x00000001
20378 /* The mask used to clear the ALT_USB_HOST_HCINT1_XFERCOMPL register field value. */
20379 #define ALT_USB_HOST_HCINT1_XFERCOMPL_CLR_MSK 0xfffffffe
20380 /* The reset value of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */
20381 #define ALT_USB_HOST_HCINT1_XFERCOMPL_RESET 0x0
20382 /* Extracts the ALT_USB_HOST_HCINT1_XFERCOMPL field value from a register. */
20383 #define ALT_USB_HOST_HCINT1_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
20384 /* Produces a ALT_USB_HOST_HCINT1_XFERCOMPL register field value suitable for setting the register. */
20385 #define ALT_USB_HOST_HCINT1_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
20386 
20387 /*
20388  * Field : chhltd
20389  *
20390  * Channel Halted (ChHltd)
20391  *
20392  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
20393  * either because of any USB transaction error or in response to disable request by
20394  * the application or because of a completed transfer.
20395  *
20396  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
20397  * the following
20398  *
20399  * . EOL being set in descriptor
20400  *
20401  * . AHB error
20402  *
20403  * . Excessive transaction errors
20404  *
20405  * . Babble
20406  *
20407  * . Stall
20408  *
20409  * Field Enumeration Values:
20410  *
20411  * Enum | Value | Description
20412  * :-----------------------------------|:------|:-------------------
20413  * ALT_USB_HOST_HCINT1_CHHLTD_E_INACT | 0x0 | Channel not halted
20414  * ALT_USB_HOST_HCINT1_CHHLTD_E_ACT | 0x1 | Channel Halted
20415  *
20416  * Field Access Macros:
20417  *
20418  */
20419 /*
20420  * Enumerated value for register field ALT_USB_HOST_HCINT1_CHHLTD
20421  *
20422  * Channel not halted
20423  */
20424 #define ALT_USB_HOST_HCINT1_CHHLTD_E_INACT 0x0
20425 /*
20426  * Enumerated value for register field ALT_USB_HOST_HCINT1_CHHLTD
20427  *
20428  * Channel Halted
20429  */
20430 #define ALT_USB_HOST_HCINT1_CHHLTD_E_ACT 0x1
20431 
20432 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_CHHLTD register field. */
20433 #define ALT_USB_HOST_HCINT1_CHHLTD_LSB 1
20434 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_CHHLTD register field. */
20435 #define ALT_USB_HOST_HCINT1_CHHLTD_MSB 1
20436 /* The width in bits of the ALT_USB_HOST_HCINT1_CHHLTD register field. */
20437 #define ALT_USB_HOST_HCINT1_CHHLTD_WIDTH 1
20438 /* The mask used to set the ALT_USB_HOST_HCINT1_CHHLTD register field value. */
20439 #define ALT_USB_HOST_HCINT1_CHHLTD_SET_MSK 0x00000002
20440 /* The mask used to clear the ALT_USB_HOST_HCINT1_CHHLTD register field value. */
20441 #define ALT_USB_HOST_HCINT1_CHHLTD_CLR_MSK 0xfffffffd
20442 /* The reset value of the ALT_USB_HOST_HCINT1_CHHLTD register field. */
20443 #define ALT_USB_HOST_HCINT1_CHHLTD_RESET 0x0
20444 /* Extracts the ALT_USB_HOST_HCINT1_CHHLTD field value from a register. */
20445 #define ALT_USB_HOST_HCINT1_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
20446 /* Produces a ALT_USB_HOST_HCINT1_CHHLTD register field value suitable for setting the register. */
20447 #define ALT_USB_HOST_HCINT1_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
20448 
20449 /*
20450  * Field : ahberr
20451  *
20452  * AHB Error (AHBErr)
20453  *
20454  * This is generated only in Internal DMA mode when there is an
20455  *
20456  * AHB error during AHB read/write. The application can read the
20457  *
20458  * corresponding channel's DMA address register to get the error
20459  *
20460  * address.
20461  *
20462  * Field Enumeration Values:
20463  *
20464  * Enum | Value | Description
20465  * :-----------------------------------|:------|:--------------------------------
20466  * ALT_USB_HOST_HCINT1_AHBERR_E_INACT | 0x0 | No AHB error
20467  * ALT_USB_HOST_HCINT1_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
20468  *
20469  * Field Access Macros:
20470  *
20471  */
20472 /*
20473  * Enumerated value for register field ALT_USB_HOST_HCINT1_AHBERR
20474  *
20475  * No AHB error
20476  */
20477 #define ALT_USB_HOST_HCINT1_AHBERR_E_INACT 0x0
20478 /*
20479  * Enumerated value for register field ALT_USB_HOST_HCINT1_AHBERR
20480  *
20481  * AHB error during AHB read/write
20482  */
20483 #define ALT_USB_HOST_HCINT1_AHBERR_E_ACT 0x1
20484 
20485 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_AHBERR register field. */
20486 #define ALT_USB_HOST_HCINT1_AHBERR_LSB 2
20487 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_AHBERR register field. */
20488 #define ALT_USB_HOST_HCINT1_AHBERR_MSB 2
20489 /* The width in bits of the ALT_USB_HOST_HCINT1_AHBERR register field. */
20490 #define ALT_USB_HOST_HCINT1_AHBERR_WIDTH 1
20491 /* The mask used to set the ALT_USB_HOST_HCINT1_AHBERR register field value. */
20492 #define ALT_USB_HOST_HCINT1_AHBERR_SET_MSK 0x00000004
20493 /* The mask used to clear the ALT_USB_HOST_HCINT1_AHBERR register field value. */
20494 #define ALT_USB_HOST_HCINT1_AHBERR_CLR_MSK 0xfffffffb
20495 /* The reset value of the ALT_USB_HOST_HCINT1_AHBERR register field. */
20496 #define ALT_USB_HOST_HCINT1_AHBERR_RESET 0x0
20497 /* Extracts the ALT_USB_HOST_HCINT1_AHBERR field value from a register. */
20498 #define ALT_USB_HOST_HCINT1_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
20499 /* Produces a ALT_USB_HOST_HCINT1_AHBERR register field value suitable for setting the register. */
20500 #define ALT_USB_HOST_HCINT1_AHBERR_SET(value) (((value) << 2) & 0x00000004)
20501 
20502 /*
20503  * Field : stall
20504  *
20505  * STALL Response Received Interrupt (STALL)
20506  *
20507  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
20508  *
20509  * in the core.This bit can be set only by the core and the application should
20510  * write 1 to clear
20511  *
20512  * it.
20513  *
20514  * Field Enumeration Values:
20515  *
20516  * Enum | Value | Description
20517  * :----------------------------------|:------|:-------------------
20518  * ALT_USB_HOST_HCINT1_STALL_E_INACT | 0x0 | No Stall Interrupt
20519  * ALT_USB_HOST_HCINT1_STALL_E_ACT | 0x1 | Stall Interrupt
20520  *
20521  * Field Access Macros:
20522  *
20523  */
20524 /*
20525  * Enumerated value for register field ALT_USB_HOST_HCINT1_STALL
20526  *
20527  * No Stall Interrupt
20528  */
20529 #define ALT_USB_HOST_HCINT1_STALL_E_INACT 0x0
20530 /*
20531  * Enumerated value for register field ALT_USB_HOST_HCINT1_STALL
20532  *
20533  * Stall Interrupt
20534  */
20535 #define ALT_USB_HOST_HCINT1_STALL_E_ACT 0x1
20536 
20537 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_STALL register field. */
20538 #define ALT_USB_HOST_HCINT1_STALL_LSB 3
20539 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_STALL register field. */
20540 #define ALT_USB_HOST_HCINT1_STALL_MSB 3
20541 /* The width in bits of the ALT_USB_HOST_HCINT1_STALL register field. */
20542 #define ALT_USB_HOST_HCINT1_STALL_WIDTH 1
20543 /* The mask used to set the ALT_USB_HOST_HCINT1_STALL register field value. */
20544 #define ALT_USB_HOST_HCINT1_STALL_SET_MSK 0x00000008
20545 /* The mask used to clear the ALT_USB_HOST_HCINT1_STALL register field value. */
20546 #define ALT_USB_HOST_HCINT1_STALL_CLR_MSK 0xfffffff7
20547 /* The reset value of the ALT_USB_HOST_HCINT1_STALL register field. */
20548 #define ALT_USB_HOST_HCINT1_STALL_RESET 0x0
20549 /* Extracts the ALT_USB_HOST_HCINT1_STALL field value from a register. */
20550 #define ALT_USB_HOST_HCINT1_STALL_GET(value) (((value) & 0x00000008) >> 3)
20551 /* Produces a ALT_USB_HOST_HCINT1_STALL register field value suitable for setting the register. */
20552 #define ALT_USB_HOST_HCINT1_STALL_SET(value) (((value) << 3) & 0x00000008)
20553 
20554 /*
20555  * Field : nak
20556  *
20557  * NAK Response Received Interrupt (NAK)
20558  *
20559  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
20560  *
20561  * in the core.This bit can be set only by the core and the application should
20562  * write 1 to clear
20563  *
20564  * it.
20565  *
20566  * Field Enumeration Values:
20567  *
20568  * Enum | Value | Description
20569  * :--------------------------------|:------|:-----------------------------------
20570  * ALT_USB_HOST_HCINT1_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
20571  * ALT_USB_HOST_HCINT1_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
20572  *
20573  * Field Access Macros:
20574  *
20575  */
20576 /*
20577  * Enumerated value for register field ALT_USB_HOST_HCINT1_NAK
20578  *
20579  * No NAK Response Received Interrupt
20580  */
20581 #define ALT_USB_HOST_HCINT1_NAK_E_INACT 0x0
20582 /*
20583  * Enumerated value for register field ALT_USB_HOST_HCINT1_NAK
20584  *
20585  * NAK Response Received Interrupt
20586  */
20587 #define ALT_USB_HOST_HCINT1_NAK_E_ACT 0x1
20588 
20589 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_NAK register field. */
20590 #define ALT_USB_HOST_HCINT1_NAK_LSB 4
20591 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_NAK register field. */
20592 #define ALT_USB_HOST_HCINT1_NAK_MSB 4
20593 /* The width in bits of the ALT_USB_HOST_HCINT1_NAK register field. */
20594 #define ALT_USB_HOST_HCINT1_NAK_WIDTH 1
20595 /* The mask used to set the ALT_USB_HOST_HCINT1_NAK register field value. */
20596 #define ALT_USB_HOST_HCINT1_NAK_SET_MSK 0x00000010
20597 /* The mask used to clear the ALT_USB_HOST_HCINT1_NAK register field value. */
20598 #define ALT_USB_HOST_HCINT1_NAK_CLR_MSK 0xffffffef
20599 /* The reset value of the ALT_USB_HOST_HCINT1_NAK register field. */
20600 #define ALT_USB_HOST_HCINT1_NAK_RESET 0x0
20601 /* Extracts the ALT_USB_HOST_HCINT1_NAK field value from a register. */
20602 #define ALT_USB_HOST_HCINT1_NAK_GET(value) (((value) & 0x00000010) >> 4)
20603 /* Produces a ALT_USB_HOST_HCINT1_NAK register field value suitable for setting the register. */
20604 #define ALT_USB_HOST_HCINT1_NAK_SET(value) (((value) << 4) & 0x00000010)
20605 
20606 /*
20607  * Field : ack
20608  *
20609  * ACK Response Received/Transmitted Interrupt (ACK)
20610  *
20611  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
20612  *
20613  * in the core.This bit can be set only by the core and the application should
20614  * write 1 to clear
20615  *
20616  * it.
20617  *
20618  * Field Enumeration Values:
20619  *
20620  * Enum | Value | Description
20621  * :--------------------------------|:------|:-----------------------------------------------
20622  * ALT_USB_HOST_HCINT1_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
20623  * ALT_USB_HOST_HCINT1_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
20624  *
20625  * Field Access Macros:
20626  *
20627  */
20628 /*
20629  * Enumerated value for register field ALT_USB_HOST_HCINT1_ACK
20630  *
20631  * No ACK Response Received Transmitted Interrupt
20632  */
20633 #define ALT_USB_HOST_HCINT1_ACK_E_INACT 0x0
20634 /*
20635  * Enumerated value for register field ALT_USB_HOST_HCINT1_ACK
20636  *
20637  * ACK Response Received Transmitted Interrup
20638  */
20639 #define ALT_USB_HOST_HCINT1_ACK_E_ACT 0x1
20640 
20641 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_ACK register field. */
20642 #define ALT_USB_HOST_HCINT1_ACK_LSB 5
20643 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_ACK register field. */
20644 #define ALT_USB_HOST_HCINT1_ACK_MSB 5
20645 /* The width in bits of the ALT_USB_HOST_HCINT1_ACK register field. */
20646 #define ALT_USB_HOST_HCINT1_ACK_WIDTH 1
20647 /* The mask used to set the ALT_USB_HOST_HCINT1_ACK register field value. */
20648 #define ALT_USB_HOST_HCINT1_ACK_SET_MSK 0x00000020
20649 /* The mask used to clear the ALT_USB_HOST_HCINT1_ACK register field value. */
20650 #define ALT_USB_HOST_HCINT1_ACK_CLR_MSK 0xffffffdf
20651 /* The reset value of the ALT_USB_HOST_HCINT1_ACK register field. */
20652 #define ALT_USB_HOST_HCINT1_ACK_RESET 0x0
20653 /* Extracts the ALT_USB_HOST_HCINT1_ACK field value from a register. */
20654 #define ALT_USB_HOST_HCINT1_ACK_GET(value) (((value) & 0x00000020) >> 5)
20655 /* Produces a ALT_USB_HOST_HCINT1_ACK register field value suitable for setting the register. */
20656 #define ALT_USB_HOST_HCINT1_ACK_SET(value) (((value) << 5) & 0x00000020)
20657 
20658 /*
20659  * Field : nyet
20660  *
20661  * NYET Response Received Interrupt (NYET)
20662  *
20663  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
20664  *
20665  * in the core.This bit can be set only by the core and the application should
20666  * write 1 to clear
20667  *
20668  * it.
20669  *
20670  * Field Enumeration Values:
20671  *
20672  * Enum | Value | Description
20673  * :---------------------------------|:------|:------------------------------------
20674  * ALT_USB_HOST_HCINT1_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
20675  * ALT_USB_HOST_HCINT1_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
20676  *
20677  * Field Access Macros:
20678  *
20679  */
20680 /*
20681  * Enumerated value for register field ALT_USB_HOST_HCINT1_NYET
20682  *
20683  * No NYET Response Received Interrupt
20684  */
20685 #define ALT_USB_HOST_HCINT1_NYET_E_INACT 0x0
20686 /*
20687  * Enumerated value for register field ALT_USB_HOST_HCINT1_NYET
20688  *
20689  * NYET Response Received Interrupt
20690  */
20691 #define ALT_USB_HOST_HCINT1_NYET_E_ACT 0x1
20692 
20693 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_NYET register field. */
20694 #define ALT_USB_HOST_HCINT1_NYET_LSB 6
20695 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_NYET register field. */
20696 #define ALT_USB_HOST_HCINT1_NYET_MSB 6
20697 /* The width in bits of the ALT_USB_HOST_HCINT1_NYET register field. */
20698 #define ALT_USB_HOST_HCINT1_NYET_WIDTH 1
20699 /* The mask used to set the ALT_USB_HOST_HCINT1_NYET register field value. */
20700 #define ALT_USB_HOST_HCINT1_NYET_SET_MSK 0x00000040
20701 /* The mask used to clear the ALT_USB_HOST_HCINT1_NYET register field value. */
20702 #define ALT_USB_HOST_HCINT1_NYET_CLR_MSK 0xffffffbf
20703 /* The reset value of the ALT_USB_HOST_HCINT1_NYET register field. */
20704 #define ALT_USB_HOST_HCINT1_NYET_RESET 0x0
20705 /* Extracts the ALT_USB_HOST_HCINT1_NYET field value from a register. */
20706 #define ALT_USB_HOST_HCINT1_NYET_GET(value) (((value) & 0x00000040) >> 6)
20707 /* Produces a ALT_USB_HOST_HCINT1_NYET register field value suitable for setting the register. */
20708 #define ALT_USB_HOST_HCINT1_NYET_SET(value) (((value) << 6) & 0x00000040)
20709 
20710 /*
20711  * Field : xacterr
20712  *
20713  * Transaction Error (XactErr)
20714  *
20715  * Indicates one of the following errors occurred on the USB.
20716  *
20717  * CRC check failure
20718  *
20719  * Timeout
20720  *
20721  * Bit stuff error
20722  *
20723  * False EOP
20724  *
20725  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
20726  *
20727  * in the core.This bit can be set only by the core and the application should
20728  * write 1 to clear
20729  *
20730  * it.
20731  *
20732  * Field Enumeration Values:
20733  *
20734  * Enum | Value | Description
20735  * :------------------------------------|:------|:---------------------
20736  * ALT_USB_HOST_HCINT1_XACTERR_E_INACT | 0x0 | No Transaction Error
20737  * ALT_USB_HOST_HCINT1_XACTERR_E_ACT | 0x1 | Transaction Error
20738  *
20739  * Field Access Macros:
20740  *
20741  */
20742 /*
20743  * Enumerated value for register field ALT_USB_HOST_HCINT1_XACTERR
20744  *
20745  * No Transaction Error
20746  */
20747 #define ALT_USB_HOST_HCINT1_XACTERR_E_INACT 0x0
20748 /*
20749  * Enumerated value for register field ALT_USB_HOST_HCINT1_XACTERR
20750  *
20751  * Transaction Error
20752  */
20753 #define ALT_USB_HOST_HCINT1_XACTERR_E_ACT 0x1
20754 
20755 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_XACTERR register field. */
20756 #define ALT_USB_HOST_HCINT1_XACTERR_LSB 7
20757 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_XACTERR register field. */
20758 #define ALT_USB_HOST_HCINT1_XACTERR_MSB 7
20759 /* The width in bits of the ALT_USB_HOST_HCINT1_XACTERR register field. */
20760 #define ALT_USB_HOST_HCINT1_XACTERR_WIDTH 1
20761 /* The mask used to set the ALT_USB_HOST_HCINT1_XACTERR register field value. */
20762 #define ALT_USB_HOST_HCINT1_XACTERR_SET_MSK 0x00000080
20763 /* The mask used to clear the ALT_USB_HOST_HCINT1_XACTERR register field value. */
20764 #define ALT_USB_HOST_HCINT1_XACTERR_CLR_MSK 0xffffff7f
20765 /* The reset value of the ALT_USB_HOST_HCINT1_XACTERR register field. */
20766 #define ALT_USB_HOST_HCINT1_XACTERR_RESET 0x0
20767 /* Extracts the ALT_USB_HOST_HCINT1_XACTERR field value from a register. */
20768 #define ALT_USB_HOST_HCINT1_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
20769 /* Produces a ALT_USB_HOST_HCINT1_XACTERR register field value suitable for setting the register. */
20770 #define ALT_USB_HOST_HCINT1_XACTERR_SET(value) (((value) << 7) & 0x00000080)
20771 
20772 /*
20773  * Field : bblerr
20774  *
20775  * Babble Error (BblErr)
20776  *
20777  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
20778  *
20779  * in the core..This bit can be set only by the core and the application should
20780  * write 1 to clear
20781  *
20782  * it.
20783  *
20784  * Field Enumeration Values:
20785  *
20786  * Enum | Value | Description
20787  * :-----------------------------------|:------|:----------------
20788  * ALT_USB_HOST_HCINT1_BBLERR_E_INACT | 0x0 | No Babble Error
20789  * ALT_USB_HOST_HCINT1_BBLERR_E_ACT | 0x1 | Babble Error
20790  *
20791  * Field Access Macros:
20792  *
20793  */
20794 /*
20795  * Enumerated value for register field ALT_USB_HOST_HCINT1_BBLERR
20796  *
20797  * No Babble Error
20798  */
20799 #define ALT_USB_HOST_HCINT1_BBLERR_E_INACT 0x0
20800 /*
20801  * Enumerated value for register field ALT_USB_HOST_HCINT1_BBLERR
20802  *
20803  * Babble Error
20804  */
20805 #define ALT_USB_HOST_HCINT1_BBLERR_E_ACT 0x1
20806 
20807 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_BBLERR register field. */
20808 #define ALT_USB_HOST_HCINT1_BBLERR_LSB 8
20809 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_BBLERR register field. */
20810 #define ALT_USB_HOST_HCINT1_BBLERR_MSB 8
20811 /* The width in bits of the ALT_USB_HOST_HCINT1_BBLERR register field. */
20812 #define ALT_USB_HOST_HCINT1_BBLERR_WIDTH 1
20813 /* The mask used to set the ALT_USB_HOST_HCINT1_BBLERR register field value. */
20814 #define ALT_USB_HOST_HCINT1_BBLERR_SET_MSK 0x00000100
20815 /* The mask used to clear the ALT_USB_HOST_HCINT1_BBLERR register field value. */
20816 #define ALT_USB_HOST_HCINT1_BBLERR_CLR_MSK 0xfffffeff
20817 /* The reset value of the ALT_USB_HOST_HCINT1_BBLERR register field. */
20818 #define ALT_USB_HOST_HCINT1_BBLERR_RESET 0x0
20819 /* Extracts the ALT_USB_HOST_HCINT1_BBLERR field value from a register. */
20820 #define ALT_USB_HOST_HCINT1_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
20821 /* Produces a ALT_USB_HOST_HCINT1_BBLERR register field value suitable for setting the register. */
20822 #define ALT_USB_HOST_HCINT1_BBLERR_SET(value) (((value) << 8) & 0x00000100)
20823 
20824 /*
20825  * Field : frmovrun
20826  *
20827  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
20828  * bit is masked
20829  *
20830  * in the core.This bit can be set only by the core and the application should
20831  * write 1 to clear
20832  *
20833  * it.
20834  *
20835  * Field Enumeration Values:
20836  *
20837  * Enum | Value | Description
20838  * :-------------------------------------|:------|:-----------------
20839  * ALT_USB_HOST_HCINT1_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
20840  * ALT_USB_HOST_HCINT1_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
20841  *
20842  * Field Access Macros:
20843  *
20844  */
20845 /*
20846  * Enumerated value for register field ALT_USB_HOST_HCINT1_FRMOVRUN
20847  *
20848  * No Frame Overrun
20849  */
20850 #define ALT_USB_HOST_HCINT1_FRMOVRUN_E_INACT 0x0
20851 /*
20852  * Enumerated value for register field ALT_USB_HOST_HCINT1_FRMOVRUN
20853  *
20854  * Frame Overrun
20855  */
20856 #define ALT_USB_HOST_HCINT1_FRMOVRUN_E_ACT 0x1
20857 
20858 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */
20859 #define ALT_USB_HOST_HCINT1_FRMOVRUN_LSB 9
20860 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */
20861 #define ALT_USB_HOST_HCINT1_FRMOVRUN_MSB 9
20862 /* The width in bits of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */
20863 #define ALT_USB_HOST_HCINT1_FRMOVRUN_WIDTH 1
20864 /* The mask used to set the ALT_USB_HOST_HCINT1_FRMOVRUN register field value. */
20865 #define ALT_USB_HOST_HCINT1_FRMOVRUN_SET_MSK 0x00000200
20866 /* The mask used to clear the ALT_USB_HOST_HCINT1_FRMOVRUN register field value. */
20867 #define ALT_USB_HOST_HCINT1_FRMOVRUN_CLR_MSK 0xfffffdff
20868 /* The reset value of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */
20869 #define ALT_USB_HOST_HCINT1_FRMOVRUN_RESET 0x0
20870 /* Extracts the ALT_USB_HOST_HCINT1_FRMOVRUN field value from a register. */
20871 #define ALT_USB_HOST_HCINT1_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
20872 /* Produces a ALT_USB_HOST_HCINT1_FRMOVRUN register field value suitable for setting the register. */
20873 #define ALT_USB_HOST_HCINT1_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
20874 
20875 /*
20876  * Field : datatglerr
20877  *
20878  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
20879  * application should write 1 to clear
20880  *
20881  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
20882  *
20883  * in the core.
20884  *
20885  * Field Enumeration Values:
20886  *
20887  * Enum | Value | Description
20888  * :---------------------------------------|:------|:---------------------
20889  * ALT_USB_HOST_HCINT1_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
20890  * ALT_USB_HOST_HCINT1_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
20891  *
20892  * Field Access Macros:
20893  *
20894  */
20895 /*
20896  * Enumerated value for register field ALT_USB_HOST_HCINT1_DATATGLERR
20897  *
20898  * No Data Toggle Error
20899  */
20900 #define ALT_USB_HOST_HCINT1_DATATGLERR_E_INACT 0x0
20901 /*
20902  * Enumerated value for register field ALT_USB_HOST_HCINT1_DATATGLERR
20903  *
20904  * Data Toggle Error
20905  */
20906 #define ALT_USB_HOST_HCINT1_DATATGLERR_E_ACT 0x1
20907 
20908 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */
20909 #define ALT_USB_HOST_HCINT1_DATATGLERR_LSB 10
20910 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */
20911 #define ALT_USB_HOST_HCINT1_DATATGLERR_MSB 10
20912 /* The width in bits of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */
20913 #define ALT_USB_HOST_HCINT1_DATATGLERR_WIDTH 1
20914 /* The mask used to set the ALT_USB_HOST_HCINT1_DATATGLERR register field value. */
20915 #define ALT_USB_HOST_HCINT1_DATATGLERR_SET_MSK 0x00000400
20916 /* The mask used to clear the ALT_USB_HOST_HCINT1_DATATGLERR register field value. */
20917 #define ALT_USB_HOST_HCINT1_DATATGLERR_CLR_MSK 0xfffffbff
20918 /* The reset value of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */
20919 #define ALT_USB_HOST_HCINT1_DATATGLERR_RESET 0x0
20920 /* Extracts the ALT_USB_HOST_HCINT1_DATATGLERR field value from a register. */
20921 #define ALT_USB_HOST_HCINT1_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
20922 /* Produces a ALT_USB_HOST_HCINT1_DATATGLERR register field value suitable for setting the register. */
20923 #define ALT_USB_HOST_HCINT1_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
20924 
20925 /*
20926  * Field : bnaintr
20927  *
20928  * BNA (Buffer Not Available) Interrupt (BNAIntr)
20929  *
20930  * This bit is valid only when Scatter/Gather DMA mode is enabled.
20931  *
20932  * The core generates this interrupt when the descriptor accessed
20933  *
20934  * is not ready for the Core to process. BNA will not be generated
20935  *
20936  * for Isochronous channels.
20937  *
20938  * For non Scatter/Gather DMA mode, this bit is reserved.
20939  *
20940  * Field Enumeration Values:
20941  *
20942  * Enum | Value | Description
20943  * :------------------------------------|:------|:-----------------
20944  * ALT_USB_HOST_HCINT1_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
20945  * ALT_USB_HOST_HCINT1_BNAINTR_E_ACT | 0x1 | BNA Interrupt
20946  *
20947  * Field Access Macros:
20948  *
20949  */
20950 /*
20951  * Enumerated value for register field ALT_USB_HOST_HCINT1_BNAINTR
20952  *
20953  * No BNA Interrupt
20954  */
20955 #define ALT_USB_HOST_HCINT1_BNAINTR_E_INACT 0x0
20956 /*
20957  * Enumerated value for register field ALT_USB_HOST_HCINT1_BNAINTR
20958  *
20959  * BNA Interrupt
20960  */
20961 #define ALT_USB_HOST_HCINT1_BNAINTR_E_ACT 0x1
20962 
20963 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_BNAINTR register field. */
20964 #define ALT_USB_HOST_HCINT1_BNAINTR_LSB 11
20965 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_BNAINTR register field. */
20966 #define ALT_USB_HOST_HCINT1_BNAINTR_MSB 11
20967 /* The width in bits of the ALT_USB_HOST_HCINT1_BNAINTR register field. */
20968 #define ALT_USB_HOST_HCINT1_BNAINTR_WIDTH 1
20969 /* The mask used to set the ALT_USB_HOST_HCINT1_BNAINTR register field value. */
20970 #define ALT_USB_HOST_HCINT1_BNAINTR_SET_MSK 0x00000800
20971 /* The mask used to clear the ALT_USB_HOST_HCINT1_BNAINTR register field value. */
20972 #define ALT_USB_HOST_HCINT1_BNAINTR_CLR_MSK 0xfffff7ff
20973 /* The reset value of the ALT_USB_HOST_HCINT1_BNAINTR register field. */
20974 #define ALT_USB_HOST_HCINT1_BNAINTR_RESET 0x0
20975 /* Extracts the ALT_USB_HOST_HCINT1_BNAINTR field value from a register. */
20976 #define ALT_USB_HOST_HCINT1_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
20977 /* Produces a ALT_USB_HOST_HCINT1_BNAINTR register field value suitable for setting the register. */
20978 #define ALT_USB_HOST_HCINT1_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
20979 
20980 /*
20981  * Field : xcs_xact_err
20982  *
20983  * Excessive Transaction Error (XCS_XACT_ERR)
20984  *
20985  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
20986  * this bit
20987  *
20988  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
20989  *
20990  * not be generated for Isochronous channels.
20991  *
20992  * For non Scatter/Gather DMA mode, this bit is reserved.
20993  *
20994  * Field Enumeration Values:
20995  *
20996  * Enum | Value | Description
20997  * :-------------------------------------------|:------|:-------------------------------
20998  * ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
20999  * ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
21000  *
21001  * Field Access Macros:
21002  *
21003  */
21004 /*
21005  * Enumerated value for register field ALT_USB_HOST_HCINT1_XCS_XACT_ERR
21006  *
21007  * No Excessive Transaction Error
21008  */
21009 #define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_INACT 0x0
21010 /*
21011  * Enumerated value for register field ALT_USB_HOST_HCINT1_XCS_XACT_ERR
21012  *
21013  * Excessive Transaction Error
21014  */
21015 #define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_ACVTIVE 0x1
21016 
21017 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */
21018 #define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_LSB 12
21019 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */
21020 #define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_MSB 12
21021 /* The width in bits of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */
21022 #define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_WIDTH 1
21023 /* The mask used to set the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field value. */
21024 #define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_SET_MSK 0x00001000
21025 /* The mask used to clear the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field value. */
21026 #define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_CLR_MSK 0xffffefff
21027 /* The reset value of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */
21028 #define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_RESET 0x0
21029 /* Extracts the ALT_USB_HOST_HCINT1_XCS_XACT_ERR field value from a register. */
21030 #define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
21031 /* Produces a ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field value suitable for setting the register. */
21032 #define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
21033 
21034 /*
21035  * Field : desc_lst_rollintr
21036  *
21037  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
21038  *
21039  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
21040  * this bit
21041  *
21042  * when the corresponding channel's descriptor list rolls over.
21043  *
21044  * For non Scatter/Gather DMA mode, this bit is reserved.
21045  *
21046  * Field Enumeration Values:
21047  *
21048  * Enum | Value | Description
21049  * :----------------------------------------------|:------|:---------------------------------
21050  * ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
21051  * ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
21052  *
21053  * Field Access Macros:
21054  *
21055  */
21056 /*
21057  * Enumerated value for register field ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR
21058  *
21059  * No Descriptor rollover interrupt
21060  */
21061 #define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_INACT 0x0
21062 /*
21063  * Enumerated value for register field ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR
21064  *
21065  * Descriptor rollover interrupt
21066  */
21067 #define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_ACT 0x1
21068 
21069 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */
21070 #define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_LSB 13
21071 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */
21072 #define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_MSB 13
21073 /* The width in bits of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */
21074 #define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_WIDTH 1
21075 /* The mask used to set the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field value. */
21076 #define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_SET_MSK 0x00002000
21077 /* The mask used to clear the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field value. */
21078 #define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
21079 /* The reset value of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */
21080 #define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_RESET 0x0
21081 /* Extracts the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR field value from a register. */
21082 #define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
21083 /* Produces a ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field value suitable for setting the register. */
21084 #define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
21085 
21086 #ifndef __ASSEMBLY__
21087 /*
21088  * WARNING: The C register and register group struct declarations are provided for
21089  * convenience and illustrative purposes. They should, however, be used with
21090  * caution as the C language standard provides no guarantees about the alignment or
21091  * atomicity of device memory accesses. The recommended practice for writing
21092  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21093  * alt_write_word() functions.
21094  *
21095  * The struct declaration for register ALT_USB_HOST_HCINT1.
21096  */
21097 struct ALT_USB_HOST_HCINT1_s
21098 {
21099  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT1_XFERCOMPL */
21100  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT1_CHHLTD */
21101  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT1_AHBERR */
21102  uint32_t stall : 1; /* ALT_USB_HOST_HCINT1_STALL */
21103  uint32_t nak : 1; /* ALT_USB_HOST_HCINT1_NAK */
21104  uint32_t ack : 1; /* ALT_USB_HOST_HCINT1_ACK */
21105  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT1_NYET */
21106  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT1_XACTERR */
21107  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT1_BBLERR */
21108  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT1_FRMOVRUN */
21109  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT1_DATATGLERR */
21110  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT1_BNAINTR */
21111  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT1_XCS_XACT_ERR */
21112  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR */
21113  uint32_t : 18; /* *UNDEFINED* */
21114 };
21115 
21116 /* The typedef declaration for register ALT_USB_HOST_HCINT1. */
21117 typedef volatile struct ALT_USB_HOST_HCINT1_s ALT_USB_HOST_HCINT1_t;
21118 #endif /* __ASSEMBLY__ */
21119 
21120 /* The reset value of the ALT_USB_HOST_HCINT1 register. */
21121 #define ALT_USB_HOST_HCINT1_RESET 0x00000000
21122 /* The byte offset of the ALT_USB_HOST_HCINT1 register from the beginning of the component. */
21123 #define ALT_USB_HOST_HCINT1_OFST 0x128
21124 /* The address of the ALT_USB_HOST_HCINT1 register. */
21125 #define ALT_USB_HOST_HCINT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT1_OFST))
21126 
21127 /*
21128  * Register : hcintmsk1
21129  *
21130  * Host Channel 1 Interrupt Mask Register
21131  *
21132  * Register Layout
21133  *
21134  * Bits | Access | Reset | Description
21135  * :--------|:-------|:------|:-------------------------------------------
21136  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK
21137  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_CHHLTDMSK
21138  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_AHBERRMSK
21139  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_STALLMSK
21140  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_NAKMSK
21141  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_ACKMSK
21142  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_NYETMSK
21143  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_XACTERRMSK
21144  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_BBLERRMSK
21145  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK
21146  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK
21147  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_BNAINTRMSK
21148  * [12] | ??? | 0x0 | *UNDEFINED*
21149  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK
21150  * [31:14] | ??? | 0x0 | *UNDEFINED*
21151  *
21152  */
21153 /*
21154  * Field : xfercomplmsk
21155  *
21156  * Transfer Completed Mask (XferComplMsk)
21157  *
21158  * Field Enumeration Values:
21159  *
21160  * Enum | Value | Description
21161  * :--------------------------------------------|:------|:------------
21162  * ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_MSK | 0x0 | Mask
21163  * ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
21164  *
21165  * Field Access Macros:
21166  *
21167  */
21168 /*
21169  * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK
21170  *
21171  * Mask
21172  */
21173 #define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_MSK 0x0
21174 /*
21175  * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK
21176  *
21177  * No mask
21178  */
21179 #define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_NOMSK 0x1
21180 
21181 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */
21182 #define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_LSB 0
21183 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */
21184 #define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_MSB 0
21185 /* The width in bits of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */
21186 #define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_WIDTH 1
21187 /* The mask used to set the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field value. */
21188 #define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_SET_MSK 0x00000001
21189 /* The mask used to clear the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field value. */
21190 #define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_CLR_MSK 0xfffffffe
21191 /* The reset value of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */
21192 #define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_RESET 0x0
21193 /* Extracts the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK field value from a register. */
21194 #define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
21195 /* Produces a ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field value suitable for setting the register. */
21196 #define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
21197 
21198 /*
21199  * Field : chhltdmsk
21200  *
21201  * Channel Halted Mask (ChHltdMsk)
21202  *
21203  * Field Enumeration Values:
21204  *
21205  * Enum | Value | Description
21206  * :-----------------------------------------|:------|:------------
21207  * ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_MSK | 0x0 | Mask
21208  * ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_NOMSK | 0x1 | No mask
21209  *
21210  * Field Access Macros:
21211  *
21212  */
21213 /*
21214  * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_CHHLTDMSK
21215  *
21216  * Mask
21217  */
21218 #define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_MSK 0x0
21219 /*
21220  * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_CHHLTDMSK
21221  *
21222  * No mask
21223  */
21224 #define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_NOMSK 0x1
21225 
21226 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */
21227 #define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_LSB 1
21228 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */
21229 #define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_MSB 1
21230 /* The width in bits of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */
21231 #define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_WIDTH 1
21232 /* The mask used to set the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field value. */
21233 #define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_SET_MSK 0x00000002
21234 /* The mask used to clear the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field value. */
21235 #define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_CLR_MSK 0xfffffffd
21236 /* The reset value of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */
21237 #define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_RESET 0x0
21238 /* Extracts the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK field value from a register. */
21239 #define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
21240 /* Produces a ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field value suitable for setting the register. */
21241 #define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
21242 
21243 /*
21244  * Field : ahberrmsk
21245  *
21246  * AHB Error Mask (AHBErrMsk)
21247  *
21248  * In scatter/gather DMA mode for host,
21249  *
21250  * interrupts will not be generated due to the corresponding bits set in
21251  *
21252  * HCINTn.
21253  *
21254  * Field Enumeration Values:
21255  *
21256  * Enum | Value | Description
21257  * :-----------------------------------------|:------|:------------
21258  * ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_MSK | 0x0 | Mask
21259  * ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_NOMSK | 0x1 | No mask
21260  *
21261  * Field Access Macros:
21262  *
21263  */
21264 /*
21265  * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_AHBERRMSK
21266  *
21267  * Mask
21268  */
21269 #define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_MSK 0x0
21270 /*
21271  * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_AHBERRMSK
21272  *
21273  * No mask
21274  */
21275 #define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_NOMSK 0x1
21276 
21277 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */
21278 #define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_LSB 2
21279 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */
21280 #define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_MSB 2
21281 /* The width in bits of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */
21282 #define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_WIDTH 1
21283 /* The mask used to set the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field value. */
21284 #define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_SET_MSK 0x00000004
21285 /* The mask used to clear the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field value. */
21286 #define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_CLR_MSK 0xfffffffb
21287 /* The reset value of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */
21288 #define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_RESET 0x0
21289 /* Extracts the ALT_USB_HOST_HCINTMSK1_AHBERRMSK field value from a register. */
21290 #define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
21291 /* Produces a ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field value suitable for setting the register. */
21292 #define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
21293 
21294 /*
21295  * Field : stallmsk
21296  *
21297  * STALL Response Received Interrupt Mask (StallMsk)
21298  *
21299  * In scatter/gather DMA mode for host,
21300  *
21301  * interrupts will not be generated due to the corresponding bits set in
21302  *
21303  * HCINTn.
21304  *
21305  * Field Access Macros:
21306  *
21307  */
21308 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_STALLMSK register field. */
21309 #define ALT_USB_HOST_HCINTMSK1_STALLMSK_LSB 3
21310 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_STALLMSK register field. */
21311 #define ALT_USB_HOST_HCINTMSK1_STALLMSK_MSB 3
21312 /* The width in bits of the ALT_USB_HOST_HCINTMSK1_STALLMSK register field. */
21313 #define ALT_USB_HOST_HCINTMSK1_STALLMSK_WIDTH 1
21314 /* The mask used to set the ALT_USB_HOST_HCINTMSK1_STALLMSK register field value. */
21315 #define ALT_USB_HOST_HCINTMSK1_STALLMSK_SET_MSK 0x00000008
21316 /* The mask used to clear the ALT_USB_HOST_HCINTMSK1_STALLMSK register field value. */
21317 #define ALT_USB_HOST_HCINTMSK1_STALLMSK_CLR_MSK 0xfffffff7
21318 /* The reset value of the ALT_USB_HOST_HCINTMSK1_STALLMSK register field. */
21319 #define ALT_USB_HOST_HCINTMSK1_STALLMSK_RESET 0x0
21320 /* Extracts the ALT_USB_HOST_HCINTMSK1_STALLMSK field value from a register. */
21321 #define ALT_USB_HOST_HCINTMSK1_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
21322 /* Produces a ALT_USB_HOST_HCINTMSK1_STALLMSK register field value suitable for setting the register. */
21323 #define ALT_USB_HOST_HCINTMSK1_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
21324 
21325 /*
21326  * Field : nakmsk
21327  *
21328  * NAK Response Received Interrupt Mask (NakMsk)
21329  *
21330  * In scatter/gather DMA mode for host,
21331  *
21332  * interrupts will not be generated due to the corresponding bits set in
21333  *
21334  * HCINTn.
21335  *
21336  * Field Access Macros:
21337  *
21338  */
21339 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_NAKMSK register field. */
21340 #define ALT_USB_HOST_HCINTMSK1_NAKMSK_LSB 4
21341 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_NAKMSK register field. */
21342 #define ALT_USB_HOST_HCINTMSK1_NAKMSK_MSB 4
21343 /* The width in bits of the ALT_USB_HOST_HCINTMSK1_NAKMSK register field. */
21344 #define ALT_USB_HOST_HCINTMSK1_NAKMSK_WIDTH 1
21345 /* The mask used to set the ALT_USB_HOST_HCINTMSK1_NAKMSK register field value. */
21346 #define ALT_USB_HOST_HCINTMSK1_NAKMSK_SET_MSK 0x00000010
21347 /* The mask used to clear the ALT_USB_HOST_HCINTMSK1_NAKMSK register field value. */
21348 #define ALT_USB_HOST_HCINTMSK1_NAKMSK_CLR_MSK 0xffffffef
21349 /* The reset value of the ALT_USB_HOST_HCINTMSK1_NAKMSK register field. */
21350 #define ALT_USB_HOST_HCINTMSK1_NAKMSK_RESET 0x0
21351 /* Extracts the ALT_USB_HOST_HCINTMSK1_NAKMSK field value from a register. */
21352 #define ALT_USB_HOST_HCINTMSK1_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
21353 /* Produces a ALT_USB_HOST_HCINTMSK1_NAKMSK register field value suitable for setting the register. */
21354 #define ALT_USB_HOST_HCINTMSK1_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
21355 
21356 /*
21357  * Field : ackmsk
21358  *
21359  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
21360  *
21361  * In scatter/gather DMA mode for host,
21362  *
21363  * interrupts will not be generated due to the corresponding bits set in
21364  *
21365  * HCINTn.
21366  *
21367  * Field Access Macros:
21368  *
21369  */
21370 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_ACKMSK register field. */
21371 #define ALT_USB_HOST_HCINTMSK1_ACKMSK_LSB 5
21372 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_ACKMSK register field. */
21373 #define ALT_USB_HOST_HCINTMSK1_ACKMSK_MSB 5
21374 /* The width in bits of the ALT_USB_HOST_HCINTMSK1_ACKMSK register field. */
21375 #define ALT_USB_HOST_HCINTMSK1_ACKMSK_WIDTH 1
21376 /* The mask used to set the ALT_USB_HOST_HCINTMSK1_ACKMSK register field value. */
21377 #define ALT_USB_HOST_HCINTMSK1_ACKMSK_SET_MSK 0x00000020
21378 /* The mask used to clear the ALT_USB_HOST_HCINTMSK1_ACKMSK register field value. */
21379 #define ALT_USB_HOST_HCINTMSK1_ACKMSK_CLR_MSK 0xffffffdf
21380 /* The reset value of the ALT_USB_HOST_HCINTMSK1_ACKMSK register field. */
21381 #define ALT_USB_HOST_HCINTMSK1_ACKMSK_RESET 0x0
21382 /* Extracts the ALT_USB_HOST_HCINTMSK1_ACKMSK field value from a register. */
21383 #define ALT_USB_HOST_HCINTMSK1_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
21384 /* Produces a ALT_USB_HOST_HCINTMSK1_ACKMSK register field value suitable for setting the register. */
21385 #define ALT_USB_HOST_HCINTMSK1_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
21386 
21387 /*
21388  * Field : nyetmsk
21389  *
21390  * NYET Response Received Interrupt Mask (NyetMsk)
21391  *
21392  * In scatter/gather DMA mode for host,
21393  *
21394  * interrupts will not be generated due to the corresponding bits set in
21395  *
21396  * HCINTn.
21397  *
21398  * Field Access Macros:
21399  *
21400  */
21401 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_NYETMSK register field. */
21402 #define ALT_USB_HOST_HCINTMSK1_NYETMSK_LSB 6
21403 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_NYETMSK register field. */
21404 #define ALT_USB_HOST_HCINTMSK1_NYETMSK_MSB 6
21405 /* The width in bits of the ALT_USB_HOST_HCINTMSK1_NYETMSK register field. */
21406 #define ALT_USB_HOST_HCINTMSK1_NYETMSK_WIDTH 1
21407 /* The mask used to set the ALT_USB_HOST_HCINTMSK1_NYETMSK register field value. */
21408 #define ALT_USB_HOST_HCINTMSK1_NYETMSK_SET_MSK 0x00000040
21409 /* The mask used to clear the ALT_USB_HOST_HCINTMSK1_NYETMSK register field value. */
21410 #define ALT_USB_HOST_HCINTMSK1_NYETMSK_CLR_MSK 0xffffffbf
21411 /* The reset value of the ALT_USB_HOST_HCINTMSK1_NYETMSK register field. */
21412 #define ALT_USB_HOST_HCINTMSK1_NYETMSK_RESET 0x0
21413 /* Extracts the ALT_USB_HOST_HCINTMSK1_NYETMSK field value from a register. */
21414 #define ALT_USB_HOST_HCINTMSK1_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
21415 /* Produces a ALT_USB_HOST_HCINTMSK1_NYETMSK register field value suitable for setting the register. */
21416 #define ALT_USB_HOST_HCINTMSK1_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
21417 
21418 /*
21419  * Field : xacterrmsk
21420  *
21421  * Transaction Error Mask (XactErrMsk)
21422  *
21423  * In scatter/gather DMA mode for host,
21424  *
21425  * interrupts will not be generated due to the corresponding bits set in
21426  *
21427  * HCINTn.
21428  *
21429  * Field Access Macros:
21430  *
21431  */
21432 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field. */
21433 #define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_LSB 7
21434 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field. */
21435 #define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_MSB 7
21436 /* The width in bits of the ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field. */
21437 #define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_WIDTH 1
21438 /* The mask used to set the ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field value. */
21439 #define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_SET_MSK 0x00000080
21440 /* The mask used to clear the ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field value. */
21441 #define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_CLR_MSK 0xffffff7f
21442 /* The reset value of the ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field. */
21443 #define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_RESET 0x0
21444 /* Extracts the ALT_USB_HOST_HCINTMSK1_XACTERRMSK field value from a register. */
21445 #define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
21446 /* Produces a ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field value suitable for setting the register. */
21447 #define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
21448 
21449 /*
21450  * Field : bblerrmsk
21451  *
21452  * Babble Error Mask (BblErrMsk)
21453  *
21454  * In scatter/gather DMA mode for host,
21455  *
21456  * interrupts will not be generated due to the corresponding bits set in
21457  *
21458  * HCINTn.
21459  *
21460  * Field Access Macros:
21461  *
21462  */
21463 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field. */
21464 #define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_LSB 8
21465 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field. */
21466 #define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_MSB 8
21467 /* The width in bits of the ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field. */
21468 #define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_WIDTH 1
21469 /* The mask used to set the ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field value. */
21470 #define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_SET_MSK 0x00000100
21471 /* The mask used to clear the ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field value. */
21472 #define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_CLR_MSK 0xfffffeff
21473 /* The reset value of the ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field. */
21474 #define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_RESET 0x0
21475 /* Extracts the ALT_USB_HOST_HCINTMSK1_BBLERRMSK field value from a register. */
21476 #define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
21477 /* Produces a ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field value suitable for setting the register. */
21478 #define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
21479 
21480 /*
21481  * Field : frmovrunmsk
21482  *
21483  * Frame Overrun Mask (FrmOvrunMsk)
21484  *
21485  * In scatter/gather DMA mode for host,
21486  *
21487  * interrupts will not be generated due to the corresponding bits set in
21488  *
21489  * HCINTn.
21490  *
21491  * Field Access Macros:
21492  *
21493  */
21494 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field. */
21495 #define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_LSB 9
21496 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field. */
21497 #define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_MSB 9
21498 /* The width in bits of the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field. */
21499 #define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_WIDTH 1
21500 /* The mask used to set the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field value. */
21501 #define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_SET_MSK 0x00000200
21502 /* The mask used to clear the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field value. */
21503 #define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_CLR_MSK 0xfffffdff
21504 /* The reset value of the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field. */
21505 #define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_RESET 0x0
21506 /* Extracts the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK field value from a register. */
21507 #define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
21508 /* Produces a ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field value suitable for setting the register. */
21509 #define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
21510 
21511 /*
21512  * Field : datatglerrmsk
21513  *
21514  * Data Toggle Error Mask (DataTglErrMsk)
21515  *
21516  * In scatter/gather DMA mode for host,
21517  *
21518  * interrupts will not be generated due to the corresponding bits set in
21519  *
21520  * HCINTn.
21521  *
21522  * Field Access Macros:
21523  *
21524  */
21525 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field. */
21526 #define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_LSB 10
21527 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field. */
21528 #define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_MSB 10
21529 /* The width in bits of the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field. */
21530 #define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_WIDTH 1
21531 /* The mask used to set the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field value. */
21532 #define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_SET_MSK 0x00000400
21533 /* The mask used to clear the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field value. */
21534 #define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_CLR_MSK 0xfffffbff
21535 /* The reset value of the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field. */
21536 #define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_RESET 0x0
21537 /* Extracts the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK field value from a register. */
21538 #define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
21539 /* Produces a ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field value suitable for setting the register. */
21540 #define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
21541 
21542 /*
21543  * Field : bnaintrmsk
21544  *
21545  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
21546  *
21547  * This bit is valid only when Scatter/Gather DMA mode is enabled.
21548  *
21549  * Field Enumeration Values:
21550  *
21551  * Enum | Value | Description
21552  * :------------------------------------------|:------|:------------
21553  * ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_MSK | 0x0 | Mask
21554  * ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_NOMSK | 0x1 | No mask
21555  *
21556  * Field Access Macros:
21557  *
21558  */
21559 /*
21560  * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_BNAINTRMSK
21561  *
21562  * Mask
21563  */
21564 #define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_MSK 0x0
21565 /*
21566  * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_BNAINTRMSK
21567  *
21568  * No mask
21569  */
21570 #define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_NOMSK 0x1
21571 
21572 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */
21573 #define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_LSB 11
21574 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */
21575 #define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_MSB 11
21576 /* The width in bits of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */
21577 #define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_WIDTH 1
21578 /* The mask used to set the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field value. */
21579 #define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_SET_MSK 0x00000800
21580 /* The mask used to clear the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field value. */
21581 #define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_CLR_MSK 0xfffff7ff
21582 /* The reset value of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */
21583 #define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_RESET 0x0
21584 /* Extracts the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK field value from a register. */
21585 #define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
21586 /* Produces a ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field value suitable for setting the register. */
21587 #define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
21588 
21589 /*
21590  * Field : frm_lst_rollintrmsk
21591  *
21592  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
21593  *
21594  * This bit is valid only when Scatter/Gather DMA mode is enabled.
21595  *
21596  * Field Enumeration Values:
21597  *
21598  * Enum | Value | Description
21599  * :---------------------------------------------------|:------|:------------
21600  * ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
21601  * ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
21602  *
21603  * Field Access Macros:
21604  *
21605  */
21606 /*
21607  * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK
21608  *
21609  * Mask
21610  */
21611 #define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_MSK 0x0
21612 /*
21613  * Enumerated value for register field ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK
21614  *
21615  * No mask
21616  */
21617 #define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
21618 
21619 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */
21620 #define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_LSB 13
21621 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */
21622 #define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_MSB 13
21623 /* The width in bits of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */
21624 #define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_WIDTH 1
21625 /* The mask used to set the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field value. */
21626 #define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
21627 /* The mask used to clear the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field value. */
21628 #define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
21629 /* The reset value of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */
21630 #define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_RESET 0x0
21631 /* Extracts the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK field value from a register. */
21632 #define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
21633 /* Produces a ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
21634 #define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
21635 
21636 #ifndef __ASSEMBLY__
21637 /*
21638  * WARNING: The C register and register group struct declarations are provided for
21639  * convenience and illustrative purposes. They should, however, be used with
21640  * caution as the C language standard provides no guarantees about the alignment or
21641  * atomicity of device memory accesses. The recommended practice for writing
21642  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21643  * alt_write_word() functions.
21644  *
21645  * The struct declaration for register ALT_USB_HOST_HCINTMSK1.
21646  */
21647 struct ALT_USB_HOST_HCINTMSK1_s
21648 {
21649  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK */
21650  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK1_CHHLTDMSK */
21651  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK1_AHBERRMSK */
21652  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK1_STALLMSK */
21653  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK1_NAKMSK */
21654  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK1_ACKMSK */
21655  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK1_NYETMSK */
21656  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK1_XACTERRMSK */
21657  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK1_BBLERRMSK */
21658  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK */
21659  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK */
21660  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK1_BNAINTRMSK */
21661  uint32_t : 1; /* *UNDEFINED* */
21662  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK */
21663  uint32_t : 18; /* *UNDEFINED* */
21664 };
21665 
21666 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK1. */
21667 typedef volatile struct ALT_USB_HOST_HCINTMSK1_s ALT_USB_HOST_HCINTMSK1_t;
21668 #endif /* __ASSEMBLY__ */
21669 
21670 /* The reset value of the ALT_USB_HOST_HCINTMSK1 register. */
21671 #define ALT_USB_HOST_HCINTMSK1_RESET 0x00000000
21672 /* The byte offset of the ALT_USB_HOST_HCINTMSK1 register from the beginning of the component. */
21673 #define ALT_USB_HOST_HCINTMSK1_OFST 0x12c
21674 /* The address of the ALT_USB_HOST_HCINTMSK1 register. */
21675 #define ALT_USB_HOST_HCINTMSK1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK1_OFST))
21676 
21677 /*
21678  * Register : hctsiz1
21679  *
21680  * Host Channel 1 Transfer Size Register
21681  *
21682  * Register Layout
21683  *
21684  * Bits | Access | Reset | Description
21685  * :--------|:-------|:------|:------------------------------
21686  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ1_XFERSIZE
21687  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ1_PKTCNT
21688  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ1_PID
21689  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ1_DOPNG
21690  *
21691  */
21692 /*
21693  * Field : xfersize
21694  *
21695  * Transfer Size (XferSize)
21696  *
21697  * For an OUT, this field is the number of data bytes the host sends
21698  *
21699  * during the transfer.
21700  *
21701  * For an IN, this field is the buffer size that the application has
21702  *
21703  * Reserved For the transfer. The application is expected to
21704  *
21705  * program this field as an integer multiple of the maximum packet
21706  *
21707  * size For IN transactions (periodic and non-periodic).
21708  *
21709  * The width of this counter is specified as Width of Transfer Size
21710  *
21711  * Counters
21712  *
21713  * Field Access Macros:
21714  *
21715  */
21716 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */
21717 #define ALT_USB_HOST_HCTSIZ1_XFERSIZE_LSB 0
21718 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */
21719 #define ALT_USB_HOST_HCTSIZ1_XFERSIZE_MSB 18
21720 /* The width in bits of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */
21721 #define ALT_USB_HOST_HCTSIZ1_XFERSIZE_WIDTH 19
21722 /* The mask used to set the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field value. */
21723 #define ALT_USB_HOST_HCTSIZ1_XFERSIZE_SET_MSK 0x0007ffff
21724 /* The mask used to clear the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field value. */
21725 #define ALT_USB_HOST_HCTSIZ1_XFERSIZE_CLR_MSK 0xfff80000
21726 /* The reset value of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */
21727 #define ALT_USB_HOST_HCTSIZ1_XFERSIZE_RESET 0x0
21728 /* Extracts the ALT_USB_HOST_HCTSIZ1_XFERSIZE field value from a register. */
21729 #define ALT_USB_HOST_HCTSIZ1_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
21730 /* Produces a ALT_USB_HOST_HCTSIZ1_XFERSIZE register field value suitable for setting the register. */
21731 #define ALT_USB_HOST_HCTSIZ1_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
21732 
21733 /*
21734  * Field : pktcnt
21735  *
21736  * Packet Count (PktCnt)
21737  *
21738  * This field is programmed by the application with the expected
21739  *
21740  * number of packets to be transmitted (OUT) or received (IN).
21741  *
21742  * The host decrements this count on every successful
21743  *
21744  * transmission or reception of an OUT/IN packet. Once this count
21745  *
21746  * reaches zero, the application is interrupted to indicate normal
21747  *
21748  * completion.
21749  *
21750  * The width of this counter is specified as Width of Packet
21751  *
21752  * Counters
21753  *
21754  * Field Access Macros:
21755  *
21756  */
21757 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */
21758 #define ALT_USB_HOST_HCTSIZ1_PKTCNT_LSB 19
21759 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */
21760 #define ALT_USB_HOST_HCTSIZ1_PKTCNT_MSB 28
21761 /* The width in bits of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */
21762 #define ALT_USB_HOST_HCTSIZ1_PKTCNT_WIDTH 10
21763 /* The mask used to set the ALT_USB_HOST_HCTSIZ1_PKTCNT register field value. */
21764 #define ALT_USB_HOST_HCTSIZ1_PKTCNT_SET_MSK 0x1ff80000
21765 /* The mask used to clear the ALT_USB_HOST_HCTSIZ1_PKTCNT register field value. */
21766 #define ALT_USB_HOST_HCTSIZ1_PKTCNT_CLR_MSK 0xe007ffff
21767 /* The reset value of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */
21768 #define ALT_USB_HOST_HCTSIZ1_PKTCNT_RESET 0x0
21769 /* Extracts the ALT_USB_HOST_HCTSIZ1_PKTCNT field value from a register. */
21770 #define ALT_USB_HOST_HCTSIZ1_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
21771 /* Produces a ALT_USB_HOST_HCTSIZ1_PKTCNT register field value suitable for setting the register. */
21772 #define ALT_USB_HOST_HCTSIZ1_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
21773 
21774 /*
21775  * Field : pid
21776  *
21777  * PID (Pid)
21778  *
21779  * The application programs this field with the type of PID to use For
21780  *
21781  * the initial transaction. The host maintains this field For the rest of
21782  *
21783  * the transfer.
21784  *
21785  * 2'b00: DATA0
21786  *
21787  * 2'b01: DATA2
21788  *
21789  * 2'b10: DATA1
21790  *
21791  * 2'b11: MDATA (non-control)/SETUP (control)
21792  *
21793  * Field Enumeration Values:
21794  *
21795  * Enum | Value | Description
21796  * :---------------------------------|:------|:------------------------------------
21797  * ALT_USB_HOST_HCTSIZ1_PID_E_DATA0 | 0x0 | DATA0
21798  * ALT_USB_HOST_HCTSIZ1_PID_E_DATA2 | 0x1 | DATA2
21799  * ALT_USB_HOST_HCTSIZ1_PID_E_DATA1 | 0x2 | DATA1
21800  * ALT_USB_HOST_HCTSIZ1_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
21801  *
21802  * Field Access Macros:
21803  *
21804  */
21805 /*
21806  * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID
21807  *
21808  * DATA0
21809  */
21810 #define ALT_USB_HOST_HCTSIZ1_PID_E_DATA0 0x0
21811 /*
21812  * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID
21813  *
21814  * DATA2
21815  */
21816 #define ALT_USB_HOST_HCTSIZ1_PID_E_DATA2 0x1
21817 /*
21818  * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID
21819  *
21820  * DATA1
21821  */
21822 #define ALT_USB_HOST_HCTSIZ1_PID_E_DATA1 0x2
21823 /*
21824  * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID
21825  *
21826  * MDATA (non-control)/SETUP (control)
21827  */
21828 #define ALT_USB_HOST_HCTSIZ1_PID_E_MDATA 0x3
21829 
21830 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_PID register field. */
21831 #define ALT_USB_HOST_HCTSIZ1_PID_LSB 29
21832 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_PID register field. */
21833 #define ALT_USB_HOST_HCTSIZ1_PID_MSB 30
21834 /* The width in bits of the ALT_USB_HOST_HCTSIZ1_PID register field. */
21835 #define ALT_USB_HOST_HCTSIZ1_PID_WIDTH 2
21836 /* The mask used to set the ALT_USB_HOST_HCTSIZ1_PID register field value. */
21837 #define ALT_USB_HOST_HCTSIZ1_PID_SET_MSK 0x60000000
21838 /* The mask used to clear the ALT_USB_HOST_HCTSIZ1_PID register field value. */
21839 #define ALT_USB_HOST_HCTSIZ1_PID_CLR_MSK 0x9fffffff
21840 /* The reset value of the ALT_USB_HOST_HCTSIZ1_PID register field. */
21841 #define ALT_USB_HOST_HCTSIZ1_PID_RESET 0x0
21842 /* Extracts the ALT_USB_HOST_HCTSIZ1_PID field value from a register. */
21843 #define ALT_USB_HOST_HCTSIZ1_PID_GET(value) (((value) & 0x60000000) >> 29)
21844 /* Produces a ALT_USB_HOST_HCTSIZ1_PID register field value suitable for setting the register. */
21845 #define ALT_USB_HOST_HCTSIZ1_PID_SET(value) (((value) << 29) & 0x60000000)
21846 
21847 /*
21848  * Field : dopng
21849  *
21850  * Do Ping (DoPng)
21851  *
21852  * This bit is used only For OUT transfers.
21853  *
21854  * Setting this field to 1 directs the host to do PING protocol.
21855  *
21856  * Note: Do not Set this bit For IN transfers. If this bit is Set For
21857  *
21858  * for IN transfers it disables the channel.
21859  *
21860  * Field Enumeration Values:
21861  *
21862  * Enum | Value | Description
21863  * :------------------------------------|:------|:-----------------
21864  * ALT_USB_HOST_HCTSIZ1_DOPNG_E_NOPING | 0x0 | No ping protocol
21865  * ALT_USB_HOST_HCTSIZ1_DOPNG_E_PING | 0x1 | Ping protocol
21866  *
21867  * Field Access Macros:
21868  *
21869  */
21870 /*
21871  * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_DOPNG
21872  *
21873  * No ping protocol
21874  */
21875 #define ALT_USB_HOST_HCTSIZ1_DOPNG_E_NOPING 0x0
21876 /*
21877  * Enumerated value for register field ALT_USB_HOST_HCTSIZ1_DOPNG
21878  *
21879  * Ping protocol
21880  */
21881 #define ALT_USB_HOST_HCTSIZ1_DOPNG_E_PING 0x1
21882 
21883 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */
21884 #define ALT_USB_HOST_HCTSIZ1_DOPNG_LSB 31
21885 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */
21886 #define ALT_USB_HOST_HCTSIZ1_DOPNG_MSB 31
21887 /* The width in bits of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */
21888 #define ALT_USB_HOST_HCTSIZ1_DOPNG_WIDTH 1
21889 /* The mask used to set the ALT_USB_HOST_HCTSIZ1_DOPNG register field value. */
21890 #define ALT_USB_HOST_HCTSIZ1_DOPNG_SET_MSK 0x80000000
21891 /* The mask used to clear the ALT_USB_HOST_HCTSIZ1_DOPNG register field value. */
21892 #define ALT_USB_HOST_HCTSIZ1_DOPNG_CLR_MSK 0x7fffffff
21893 /* The reset value of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */
21894 #define ALT_USB_HOST_HCTSIZ1_DOPNG_RESET 0x0
21895 /* Extracts the ALT_USB_HOST_HCTSIZ1_DOPNG field value from a register. */
21896 #define ALT_USB_HOST_HCTSIZ1_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
21897 /* Produces a ALT_USB_HOST_HCTSIZ1_DOPNG register field value suitable for setting the register. */
21898 #define ALT_USB_HOST_HCTSIZ1_DOPNG_SET(value) (((value) << 31) & 0x80000000)
21899 
21900 #ifndef __ASSEMBLY__
21901 /*
21902  * WARNING: The C register and register group struct declarations are provided for
21903  * convenience and illustrative purposes. They should, however, be used with
21904  * caution as the C language standard provides no guarantees about the alignment or
21905  * atomicity of device memory accesses. The recommended practice for writing
21906  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21907  * alt_write_word() functions.
21908  *
21909  * The struct declaration for register ALT_USB_HOST_HCTSIZ1.
21910  */
21911 struct ALT_USB_HOST_HCTSIZ1_s
21912 {
21913  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ1_XFERSIZE */
21914  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ1_PKTCNT */
21915  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ1_PID */
21916  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ1_DOPNG */
21917 };
21918 
21919 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ1. */
21920 typedef volatile struct ALT_USB_HOST_HCTSIZ1_s ALT_USB_HOST_HCTSIZ1_t;
21921 #endif /* __ASSEMBLY__ */
21922 
21923 /* The reset value of the ALT_USB_HOST_HCTSIZ1 register. */
21924 #define ALT_USB_HOST_HCTSIZ1_RESET 0x00000000
21925 /* The byte offset of the ALT_USB_HOST_HCTSIZ1 register from the beginning of the component. */
21926 #define ALT_USB_HOST_HCTSIZ1_OFST 0x130
21927 /* The address of the ALT_USB_HOST_HCTSIZ1 register. */
21928 #define ALT_USB_HOST_HCTSIZ1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ1_OFST))
21929 
21930 /*
21931  * Register : hcdma1
21932  *
21933  * Host Channel 1 DMA Address Register
21934  *
21935  * Register Layout
21936  *
21937  * Bits | Access | Reset | Description
21938  * :-------|:-------|:------|:---------------------------
21939  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA1_HCDMA1
21940  *
21941  */
21942 /*
21943  * Field : hcdma1
21944  *
21945  * Buffer DMA Mode:
21946  *
21947  * [31:0] DMA Address (DMAAddr)
21948  *
21949  * This field holds the start address in the external memory from which the data
21950  * for
21951  *
21952  * the endpoint must be fetched or to which it must be stored. This register is
21953  *
21954  * incremented on every AHB transaction.
21955  *
21956  * Scatter-Gather DMA (DescDMA) Mode:
21957  *
21958  * [31:9] (Non Isoc) Non-Isochronous:
21959  *
21960  * [31:N] (Isoc) Isochronous:
21961  *
21962  * This field holds the start address of the 512 bytes
21963  *
21964  * page. The first descriptor in the list should be located
21965  *
21966  * in this address. The first descriptor may be or may
21967  *
21968  * not be ready. The core starts processing the list from
21969  *
21970  * the CTD value.
21971  *
21972  * This field holds the address of the 2*(nTD+1) bytes of
21973  *
21974  * locations in which the isochronous descriptors are
21975  *
21976  * present where N is based on nTD as per Table below
21977  *
21978  * [31:N] Base Address
21979  *
21980  * [N-1:3] Offset
21981  *
21982  * [2:0] 000
21983  *
21984  * HS ISOC
21985  *
21986  * nTD N
21987  *
21988  * 7 6
21989  *
21990  * 15 7
21991  *
21992  * 31 8
21993  *
21994  * 63 9
21995  *
21996  * 127 10
21997  *
21998  * 255 11
21999  *
22000  * FS ISOC
22001  *
22002  * nTD N
22003  *
22004  * 1 4
22005  *
22006  * 3 5
22007  *
22008  * 7 6
22009  *
22010  * 15 7
22011  *
22012  * 31 8
22013  *
22014  * 63 9
22015  *
22016  * [N-1:3] (Isoc):
22017  *
22018  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
22019  *
22020  * Non Isochronous:
22021  *
22022  * This value is in terms of number of descriptors. The values can be from 0 to 63.
22023  *
22024  * 0 - 1 descriptor.
22025  *
22026  * 63 - 64 descriptors.
22027  *
22028  * This field indicates the current descriptor processed in the list. This field is
22029  * updated
22030  *
22031  * both by application and the core. For example, if the application enables the
22032  *
22033  * channel after programming CTD=5, then the core will start processing the 6th
22034  *
22035  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
22036  *
22037  * to DMAAddr.
22038  *
22039  * Isochronous:
22040  *
22041  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
22042  * set
22043  *
22044  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
22045  *
22046  * [31:9] (Non Isoc) Non-Isochronous:
22047  *
22048  * [31:N] (Isoc) Isochronous:
22049  *
22050  * This field holds the start address of the 512 bytes
22051  *
22052  * page. The first descriptor in the list should be located
22053  *
22054  * in this address. The first descriptor may be or may
22055  *
22056  * not be ready. The core starts processing the list from
22057  *
22058  * the CTD value.
22059  *
22060  * This field holds the address of the 2*(nTD+1) bytes of
22061  *
22062  * locations in which the isochronous descriptors are
22063  *
22064  * present where N is based on nTD as per Table below
22065  *
22066  * [31:N] Base Address
22067  *
22068  * [N-1:3] Offset
22069  *
22070  * [2:0] 000
22071  *
22072  * HS ISOC
22073  *
22074  * nTD N
22075  *
22076  * 7 6
22077  *
22078  * 15 7
22079  *
22080  * 31 8
22081  *
22082  * 63 9
22083  *
22084  * 127 10
22085  *
22086  * 255 11
22087  *
22088  * FS ISOC
22089  *
22090  * nTD N
22091  *
22092  * 1 4
22093  *
22094  * 3 5
22095  *
22096  * 7 6
22097  *
22098  * 15 7
22099  *
22100  * 31 8
22101  *
22102  * 63 9
22103  *
22104  * [N-1:3] (Isoc):
22105  *
22106  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
22107  *
22108  * Non Isochronous:
22109  *
22110  * This value is in terms of number of descriptors. The values can be from 0 to 63.
22111  *
22112  * 0 - 1 descriptor.
22113  *
22114  * 63 - 64 descriptors.
22115  *
22116  * This field indicates the current descriptor processed in the list. This field is
22117  * updated
22118  *
22119  * both by application and the core. For example, if the application enables the
22120  *
22121  * channel after programming CTD=5, then the core will start processing the 6th
22122  *
22123  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
22124  *
22125  * to DMAAddr.
22126  *
22127  * Isochronous:
22128  *
22129  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
22130  * set
22131  *
22132  * to zero by application.
22133  *
22134  * Field Access Macros:
22135  *
22136  */
22137 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */
22138 #define ALT_USB_HOST_HCDMA1_HCDMA1_LSB 0
22139 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */
22140 #define ALT_USB_HOST_HCDMA1_HCDMA1_MSB 31
22141 /* The width in bits of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */
22142 #define ALT_USB_HOST_HCDMA1_HCDMA1_WIDTH 32
22143 /* The mask used to set the ALT_USB_HOST_HCDMA1_HCDMA1 register field value. */
22144 #define ALT_USB_HOST_HCDMA1_HCDMA1_SET_MSK 0xffffffff
22145 /* The mask used to clear the ALT_USB_HOST_HCDMA1_HCDMA1 register field value. */
22146 #define ALT_USB_HOST_HCDMA1_HCDMA1_CLR_MSK 0x00000000
22147 /* The reset value of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */
22148 #define ALT_USB_HOST_HCDMA1_HCDMA1_RESET 0x0
22149 /* Extracts the ALT_USB_HOST_HCDMA1_HCDMA1 field value from a register. */
22150 #define ALT_USB_HOST_HCDMA1_HCDMA1_GET(value) (((value) & 0xffffffff) >> 0)
22151 /* Produces a ALT_USB_HOST_HCDMA1_HCDMA1 register field value suitable for setting the register. */
22152 #define ALT_USB_HOST_HCDMA1_HCDMA1_SET(value) (((value) << 0) & 0xffffffff)
22153 
22154 #ifndef __ASSEMBLY__
22155 /*
22156  * WARNING: The C register and register group struct declarations are provided for
22157  * convenience and illustrative purposes. They should, however, be used with
22158  * caution as the C language standard provides no guarantees about the alignment or
22159  * atomicity of device memory accesses. The recommended practice for writing
22160  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22161  * alt_write_word() functions.
22162  *
22163  * The struct declaration for register ALT_USB_HOST_HCDMA1.
22164  */
22165 struct ALT_USB_HOST_HCDMA1_s
22166 {
22167  uint32_t hcdma1 : 32; /* ALT_USB_HOST_HCDMA1_HCDMA1 */
22168 };
22169 
22170 /* The typedef declaration for register ALT_USB_HOST_HCDMA1. */
22171 typedef volatile struct ALT_USB_HOST_HCDMA1_s ALT_USB_HOST_HCDMA1_t;
22172 #endif /* __ASSEMBLY__ */
22173 
22174 /* The reset value of the ALT_USB_HOST_HCDMA1 register. */
22175 #define ALT_USB_HOST_HCDMA1_RESET 0x00000000
22176 /* The byte offset of the ALT_USB_HOST_HCDMA1 register from the beginning of the component. */
22177 #define ALT_USB_HOST_HCDMA1_OFST 0x134
22178 /* The address of the ALT_USB_HOST_HCDMA1 register. */
22179 #define ALT_USB_HOST_HCDMA1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA1_OFST))
22180 
22181 /*
22182  * Register : hcdmab1
22183  *
22184  * Host Channel 1 DMA Buffer Address Register
22185  *
22186  * Register Layout
22187  *
22188  * Bits | Access | Reset | Description
22189  * :-------|:-------|:------|:-----------------------------
22190  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB1_HCDMAB1
22191  *
22192  */
22193 /*
22194  * Field : hcdmab1
22195  *
22196  * Holds the current buffer address.
22197  *
22198  * This register is updated as and when the data transfer for the corresponding end
22199  * point
22200  *
22201  * is in progress. This register is present only in Scatter/Gather DMA mode.
22202  * Otherwise this
22203  *
22204  * field is reserved.
22205  *
22206  * Field Access Macros:
22207  *
22208  */
22209 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */
22210 #define ALT_USB_HOST_HCDMAB1_HCDMAB1_LSB 0
22211 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */
22212 #define ALT_USB_HOST_HCDMAB1_HCDMAB1_MSB 31
22213 /* The width in bits of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */
22214 #define ALT_USB_HOST_HCDMAB1_HCDMAB1_WIDTH 32
22215 /* The mask used to set the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field value. */
22216 #define ALT_USB_HOST_HCDMAB1_HCDMAB1_SET_MSK 0xffffffff
22217 /* The mask used to clear the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field value. */
22218 #define ALT_USB_HOST_HCDMAB1_HCDMAB1_CLR_MSK 0x00000000
22219 /* The reset value of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */
22220 #define ALT_USB_HOST_HCDMAB1_HCDMAB1_RESET 0x0
22221 /* Extracts the ALT_USB_HOST_HCDMAB1_HCDMAB1 field value from a register. */
22222 #define ALT_USB_HOST_HCDMAB1_HCDMAB1_GET(value) (((value) & 0xffffffff) >> 0)
22223 /* Produces a ALT_USB_HOST_HCDMAB1_HCDMAB1 register field value suitable for setting the register. */
22224 #define ALT_USB_HOST_HCDMAB1_HCDMAB1_SET(value) (((value) << 0) & 0xffffffff)
22225 
22226 #ifndef __ASSEMBLY__
22227 /*
22228  * WARNING: The C register and register group struct declarations are provided for
22229  * convenience and illustrative purposes. They should, however, be used with
22230  * caution as the C language standard provides no guarantees about the alignment or
22231  * atomicity of device memory accesses. The recommended practice for writing
22232  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22233  * alt_write_word() functions.
22234  *
22235  * The struct declaration for register ALT_USB_HOST_HCDMAB1.
22236  */
22237 struct ALT_USB_HOST_HCDMAB1_s
22238 {
22239  uint32_t hcdmab1 : 32; /* ALT_USB_HOST_HCDMAB1_HCDMAB1 */
22240 };
22241 
22242 /* The typedef declaration for register ALT_USB_HOST_HCDMAB1. */
22243 typedef volatile struct ALT_USB_HOST_HCDMAB1_s ALT_USB_HOST_HCDMAB1_t;
22244 #endif /* __ASSEMBLY__ */
22245 
22246 /* The reset value of the ALT_USB_HOST_HCDMAB1 register. */
22247 #define ALT_USB_HOST_HCDMAB1_RESET 0x00000000
22248 /* The byte offset of the ALT_USB_HOST_HCDMAB1 register from the beginning of the component. */
22249 #define ALT_USB_HOST_HCDMAB1_OFST 0x13c
22250 /* The address of the ALT_USB_HOST_HCDMAB1 register. */
22251 #define ALT_USB_HOST_HCDMAB1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB1_OFST))
22252 
22253 /*
22254  * Register : hcchar2
22255  *
22256  * Host Channel 2 Characteristics Register
22257  *
22258  * Register Layout
22259  *
22260  * Bits | Access | Reset | Description
22261  * :--------|:---------|:------|:-----------------------------
22262  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_MPS
22263  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_EPNUM
22264  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_EPDIR
22265  * [16] | ??? | 0x0 | *UNDEFINED*
22266  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_LSPDDEV
22267  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_EPTYPE
22268  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_EC
22269  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_DEVADDR
22270  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_ODDFRM
22271  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR2_CHDIS
22272  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR2_CHENA
22273  *
22274  */
22275 /*
22276  * Field : mps
22277  *
22278  * Maximum Packet Size (MPS)
22279  *
22280  * Indicates the maximum packet size of the associated endpoint.
22281  *
22282  * Field Access Macros:
22283  *
22284  */
22285 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_MPS register field. */
22286 #define ALT_USB_HOST_HCCHAR2_MPS_LSB 0
22287 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_MPS register field. */
22288 #define ALT_USB_HOST_HCCHAR2_MPS_MSB 10
22289 /* The width in bits of the ALT_USB_HOST_HCCHAR2_MPS register field. */
22290 #define ALT_USB_HOST_HCCHAR2_MPS_WIDTH 11
22291 /* The mask used to set the ALT_USB_HOST_HCCHAR2_MPS register field value. */
22292 #define ALT_USB_HOST_HCCHAR2_MPS_SET_MSK 0x000007ff
22293 /* The mask used to clear the ALT_USB_HOST_HCCHAR2_MPS register field value. */
22294 #define ALT_USB_HOST_HCCHAR2_MPS_CLR_MSK 0xfffff800
22295 /* The reset value of the ALT_USB_HOST_HCCHAR2_MPS register field. */
22296 #define ALT_USB_HOST_HCCHAR2_MPS_RESET 0x0
22297 /* Extracts the ALT_USB_HOST_HCCHAR2_MPS field value from a register. */
22298 #define ALT_USB_HOST_HCCHAR2_MPS_GET(value) (((value) & 0x000007ff) >> 0)
22299 /* Produces a ALT_USB_HOST_HCCHAR2_MPS register field value suitable for setting the register. */
22300 #define ALT_USB_HOST_HCCHAR2_MPS_SET(value) (((value) << 0) & 0x000007ff)
22301 
22302 /*
22303  * Field : epnum
22304  *
22305  * Endpoint Number (EPNum)
22306  *
22307  * Indicates the endpoint number on the device serving as the data
22308  *
22309  * source or sink.
22310  *
22311  * Field Enumeration Values:
22312  *
22313  * Enum | Value | Description
22314  * :-------------------------------------|:------|:--------------
22315  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT0 | 0x0 | End point 0
22316  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT1 | 0x1 | End point 1
22317  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT2 | 0x2 | End point 2
22318  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT3 | 0x3 | End point 3
22319  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT4 | 0x4 | End point 4
22320  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT5 | 0x5 | End point 5
22321  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT6 | 0x6 | End point 6
22322  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT7 | 0x7 | End point 7
22323  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT8 | 0x8 | End point 8
22324  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT9 | 0x9 | End point 9
22325  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT10 | 0xa | End point 10
22326  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT11 | 0xb | End point 11
22327  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT12 | 0xc | End point 12
22328  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT13 | 0xd | End point 13
22329  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT14 | 0xe | End point 14
22330  * ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT15 | 0xf | End point 15
22331  *
22332  * Field Access Macros:
22333  *
22334  */
22335 /*
22336  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22337  *
22338  * End point 0
22339  */
22340 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT0 0x0
22341 /*
22342  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22343  *
22344  * End point 1
22345  */
22346 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT1 0x1
22347 /*
22348  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22349  *
22350  * End point 2
22351  */
22352 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT2 0x2
22353 /*
22354  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22355  *
22356  * End point 3
22357  */
22358 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT3 0x3
22359 /*
22360  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22361  *
22362  * End point 4
22363  */
22364 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT4 0x4
22365 /*
22366  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22367  *
22368  * End point 5
22369  */
22370 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT5 0x5
22371 /*
22372  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22373  *
22374  * End point 6
22375  */
22376 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT6 0x6
22377 /*
22378  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22379  *
22380  * End point 7
22381  */
22382 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT7 0x7
22383 /*
22384  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22385  *
22386  * End point 8
22387  */
22388 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT8 0x8
22389 /*
22390  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22391  *
22392  * End point 9
22393  */
22394 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT9 0x9
22395 /*
22396  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22397  *
22398  * End point 10
22399  */
22400 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT10 0xa
22401 /*
22402  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22403  *
22404  * End point 11
22405  */
22406 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT11 0xb
22407 /*
22408  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22409  *
22410  * End point 12
22411  */
22412 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT12 0xc
22413 /*
22414  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22415  *
22416  * End point 13
22417  */
22418 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT13 0xd
22419 /*
22420  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22421  *
22422  * End point 14
22423  */
22424 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT14 0xe
22425 /*
22426  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
22427  *
22428  * End point 15
22429  */
22430 #define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT15 0xf
22431 
22432 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */
22433 #define ALT_USB_HOST_HCCHAR2_EPNUM_LSB 11
22434 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */
22435 #define ALT_USB_HOST_HCCHAR2_EPNUM_MSB 14
22436 /* The width in bits of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */
22437 #define ALT_USB_HOST_HCCHAR2_EPNUM_WIDTH 4
22438 /* The mask used to set the ALT_USB_HOST_HCCHAR2_EPNUM register field value. */
22439 #define ALT_USB_HOST_HCCHAR2_EPNUM_SET_MSK 0x00007800
22440 /* The mask used to clear the ALT_USB_HOST_HCCHAR2_EPNUM register field value. */
22441 #define ALT_USB_HOST_HCCHAR2_EPNUM_CLR_MSK 0xffff87ff
22442 /* The reset value of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */
22443 #define ALT_USB_HOST_HCCHAR2_EPNUM_RESET 0x0
22444 /* Extracts the ALT_USB_HOST_HCCHAR2_EPNUM field value from a register. */
22445 #define ALT_USB_HOST_HCCHAR2_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
22446 /* Produces a ALT_USB_HOST_HCCHAR2_EPNUM register field value suitable for setting the register. */
22447 #define ALT_USB_HOST_HCCHAR2_EPNUM_SET(value) (((value) << 11) & 0x00007800)
22448 
22449 /*
22450  * Field : epdir
22451  *
22452  * Endpoint Direction (EPDir)
22453  *
22454  * Indicates whether the transaction is IN or OUT.
22455  *
22456  * 1'b0: OUT
22457  *
22458  * 1'b1: IN
22459  *
22460  * Field Enumeration Values:
22461  *
22462  * Enum | Value | Description
22463  * :---------------------------------|:------|:--------------
22464  * ALT_USB_HOST_HCCHAR2_EPDIR_E_OUT | 0x0 | OUT Direction
22465  * ALT_USB_HOST_HCCHAR2_EPDIR_E_IN | 0x1 | IN Direction
22466  *
22467  * Field Access Macros:
22468  *
22469  */
22470 /*
22471  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPDIR
22472  *
22473  * OUT Direction
22474  */
22475 #define ALT_USB_HOST_HCCHAR2_EPDIR_E_OUT 0x0
22476 /*
22477  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPDIR
22478  *
22479  * IN Direction
22480  */
22481 #define ALT_USB_HOST_HCCHAR2_EPDIR_E_IN 0x1
22482 
22483 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */
22484 #define ALT_USB_HOST_HCCHAR2_EPDIR_LSB 15
22485 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */
22486 #define ALT_USB_HOST_HCCHAR2_EPDIR_MSB 15
22487 /* The width in bits of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */
22488 #define ALT_USB_HOST_HCCHAR2_EPDIR_WIDTH 1
22489 /* The mask used to set the ALT_USB_HOST_HCCHAR2_EPDIR register field value. */
22490 #define ALT_USB_HOST_HCCHAR2_EPDIR_SET_MSK 0x00008000
22491 /* The mask used to clear the ALT_USB_HOST_HCCHAR2_EPDIR register field value. */
22492 #define ALT_USB_HOST_HCCHAR2_EPDIR_CLR_MSK 0xffff7fff
22493 /* The reset value of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */
22494 #define ALT_USB_HOST_HCCHAR2_EPDIR_RESET 0x0
22495 /* Extracts the ALT_USB_HOST_HCCHAR2_EPDIR field value from a register. */
22496 #define ALT_USB_HOST_HCCHAR2_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
22497 /* Produces a ALT_USB_HOST_HCCHAR2_EPDIR register field value suitable for setting the register. */
22498 #define ALT_USB_HOST_HCCHAR2_EPDIR_SET(value) (((value) << 15) & 0x00008000)
22499 
22500 /*
22501  * Field : lspddev
22502  *
22503  * Low-Speed Device (LSpdDev)
22504  *
22505  * This field is Set by the application to indicate that this channel is
22506  *
22507  * communicating to a low-speed device.
22508  *
22509  * Field Enumeration Values:
22510  *
22511  * Enum | Value | Description
22512  * :------------------------------------|:------|:----------------------------------------
22513  * ALT_USB_HOST_HCCHAR2_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
22514  * ALT_USB_HOST_HCCHAR2_LSPDDEV_E_END | 0x1 | Communicating with low speed device
22515  *
22516  * Field Access Macros:
22517  *
22518  */
22519 /*
22520  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_LSPDDEV
22521  *
22522  * Not Communicating with low speed device
22523  */
22524 #define ALT_USB_HOST_HCCHAR2_LSPDDEV_E_DISD 0x0
22525 /*
22526  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_LSPDDEV
22527  *
22528  * Communicating with low speed device
22529  */
22530 #define ALT_USB_HOST_HCCHAR2_LSPDDEV_E_END 0x1
22531 
22532 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */
22533 #define ALT_USB_HOST_HCCHAR2_LSPDDEV_LSB 17
22534 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */
22535 #define ALT_USB_HOST_HCCHAR2_LSPDDEV_MSB 17
22536 /* The width in bits of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */
22537 #define ALT_USB_HOST_HCCHAR2_LSPDDEV_WIDTH 1
22538 /* The mask used to set the ALT_USB_HOST_HCCHAR2_LSPDDEV register field value. */
22539 #define ALT_USB_HOST_HCCHAR2_LSPDDEV_SET_MSK 0x00020000
22540 /* The mask used to clear the ALT_USB_HOST_HCCHAR2_LSPDDEV register field value. */
22541 #define ALT_USB_HOST_HCCHAR2_LSPDDEV_CLR_MSK 0xfffdffff
22542 /* The reset value of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */
22543 #define ALT_USB_HOST_HCCHAR2_LSPDDEV_RESET 0x0
22544 /* Extracts the ALT_USB_HOST_HCCHAR2_LSPDDEV field value from a register. */
22545 #define ALT_USB_HOST_HCCHAR2_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
22546 /* Produces a ALT_USB_HOST_HCCHAR2_LSPDDEV register field value suitable for setting the register. */
22547 #define ALT_USB_HOST_HCCHAR2_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
22548 
22549 /*
22550  * Field : eptype
22551  *
22552  * Endpoint Type (EPType)
22553  *
22554  * Indicates the transfer type selected.
22555  *
22556  * 2'b00: Control
22557  *
22558  * 2'b01: Isochronous
22559  *
22560  * 2'b10: Bulk
22561  *
22562  * 2'b11: Interrupt
22563  *
22564  * Field Enumeration Values:
22565  *
22566  * Enum | Value | Description
22567  * :-------------------------------------|:------|:------------
22568  * ALT_USB_HOST_HCCHAR2_EPTYPE_E_CTL | 0x0 | Control
22569  * ALT_USB_HOST_HCCHAR2_EPTYPE_E_ISOC | 0x1 | Isochronous
22570  * ALT_USB_HOST_HCCHAR2_EPTYPE_E_BULK | 0x2 | Bulk
22571  * ALT_USB_HOST_HCCHAR2_EPTYPE_E_INTERR | 0x3 | Interrupt
22572  *
22573  * Field Access Macros:
22574  *
22575  */
22576 /*
22577  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE
22578  *
22579  * Control
22580  */
22581 #define ALT_USB_HOST_HCCHAR2_EPTYPE_E_CTL 0x0
22582 /*
22583  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE
22584  *
22585  * Isochronous
22586  */
22587 #define ALT_USB_HOST_HCCHAR2_EPTYPE_E_ISOC 0x1
22588 /*
22589  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE
22590  *
22591  * Bulk
22592  */
22593 #define ALT_USB_HOST_HCCHAR2_EPTYPE_E_BULK 0x2
22594 /*
22595  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE
22596  *
22597  * Interrupt
22598  */
22599 #define ALT_USB_HOST_HCCHAR2_EPTYPE_E_INTERR 0x3
22600 
22601 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */
22602 #define ALT_USB_HOST_HCCHAR2_EPTYPE_LSB 18
22603 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */
22604 #define ALT_USB_HOST_HCCHAR2_EPTYPE_MSB 19
22605 /* The width in bits of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */
22606 #define ALT_USB_HOST_HCCHAR2_EPTYPE_WIDTH 2
22607 /* The mask used to set the ALT_USB_HOST_HCCHAR2_EPTYPE register field value. */
22608 #define ALT_USB_HOST_HCCHAR2_EPTYPE_SET_MSK 0x000c0000
22609 /* The mask used to clear the ALT_USB_HOST_HCCHAR2_EPTYPE register field value. */
22610 #define ALT_USB_HOST_HCCHAR2_EPTYPE_CLR_MSK 0xfff3ffff
22611 /* The reset value of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */
22612 #define ALT_USB_HOST_HCCHAR2_EPTYPE_RESET 0x0
22613 /* Extracts the ALT_USB_HOST_HCCHAR2_EPTYPE field value from a register. */
22614 #define ALT_USB_HOST_HCCHAR2_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
22615 /* Produces a ALT_USB_HOST_HCCHAR2_EPTYPE register field value suitable for setting the register. */
22616 #define ALT_USB_HOST_HCCHAR2_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
22617 
22618 /*
22619  * Field : ec
22620  *
22621  * Multi Count (MC) / Error Count (EC)
22622  *
22623  * When the Split Enable bit of the Host Channel-n Split Control
22624  *
22625  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
22626  *
22627  * the host the number of transactions that must be executed per
22628  *
22629  * microframe For this periodic endpoint. For non periodic transfers,
22630  *
22631  * this field is used only in DMA mode, and specifies the number
22632  *
22633  * packets to be fetched For this channel before the internal DMA
22634  *
22635  * engine changes arbitration.
22636  *
22637  * 2'b00: Reserved This field yields undefined results.
22638  *
22639  * 2'b01: 1 transaction
22640  *
22641  * 2'b10: 2 transactions to be issued For this endpoint per
22642  *
22643  * microframe
22644  *
22645  * 2'b11: 3 transactions to be issued For this endpoint per
22646  *
22647  * microframe
22648  *
22649  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
22650  *
22651  * number of immediate retries to be performed For a periodic split
22652  *
22653  * transactions on transaction errors. This field must be Set to at
22654  *
22655  * least 2'b01.
22656  *
22657  * Field Enumeration Values:
22658  *
22659  * Enum | Value | Description
22660  * :-------------------------------------|:------|:----------------------------------------------
22661  * ALT_USB_HOST_HCCHAR2_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
22662  * ALT_USB_HOST_HCCHAR2_EC_E_TRANSONE | 0x1 | 1 transaction
22663  * ALT_USB_HOST_HCCHAR2_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
22664  * : | | per microframe
22665  * ALT_USB_HOST_HCCHAR2_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
22666  * : | | per microframe
22667  *
22668  * Field Access Macros:
22669  *
22670  */
22671 /*
22672  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC
22673  *
22674  * Reserved This field yields undefined result
22675  */
22676 #define ALT_USB_HOST_HCCHAR2_EC_E_RSVD 0x0
22677 /*
22678  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC
22679  *
22680  * 1 transaction
22681  */
22682 #define ALT_USB_HOST_HCCHAR2_EC_E_TRANSONE 0x1
22683 /*
22684  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC
22685  *
22686  * 2 transactions to be issued for this endpoint per microframe
22687  */
22688 #define ALT_USB_HOST_HCCHAR2_EC_E_TRANSTWO 0x2
22689 /*
22690  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC
22691  *
22692  * 3 transactions to be issued for this endpoint per microframe
22693  */
22694 #define ALT_USB_HOST_HCCHAR2_EC_E_TRANSTHREE 0x3
22695 
22696 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EC register field. */
22697 #define ALT_USB_HOST_HCCHAR2_EC_LSB 20
22698 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EC register field. */
22699 #define ALT_USB_HOST_HCCHAR2_EC_MSB 21
22700 /* The width in bits of the ALT_USB_HOST_HCCHAR2_EC register field. */
22701 #define ALT_USB_HOST_HCCHAR2_EC_WIDTH 2
22702 /* The mask used to set the ALT_USB_HOST_HCCHAR2_EC register field value. */
22703 #define ALT_USB_HOST_HCCHAR2_EC_SET_MSK 0x00300000
22704 /* The mask used to clear the ALT_USB_HOST_HCCHAR2_EC register field value. */
22705 #define ALT_USB_HOST_HCCHAR2_EC_CLR_MSK 0xffcfffff
22706 /* The reset value of the ALT_USB_HOST_HCCHAR2_EC register field. */
22707 #define ALT_USB_HOST_HCCHAR2_EC_RESET 0x0
22708 /* Extracts the ALT_USB_HOST_HCCHAR2_EC field value from a register. */
22709 #define ALT_USB_HOST_HCCHAR2_EC_GET(value) (((value) & 0x00300000) >> 20)
22710 /* Produces a ALT_USB_HOST_HCCHAR2_EC register field value suitable for setting the register. */
22711 #define ALT_USB_HOST_HCCHAR2_EC_SET(value) (((value) << 20) & 0x00300000)
22712 
22713 /*
22714  * Field : devaddr
22715  *
22716  * Device Address (DevAddr)
22717  *
22718  * This field selects the specific device serving as the data source
22719  *
22720  * or sink.
22721  *
22722  * Field Access Macros:
22723  *
22724  */
22725 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */
22726 #define ALT_USB_HOST_HCCHAR2_DEVADDR_LSB 22
22727 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */
22728 #define ALT_USB_HOST_HCCHAR2_DEVADDR_MSB 28
22729 /* The width in bits of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */
22730 #define ALT_USB_HOST_HCCHAR2_DEVADDR_WIDTH 7
22731 /* The mask used to set the ALT_USB_HOST_HCCHAR2_DEVADDR register field value. */
22732 #define ALT_USB_HOST_HCCHAR2_DEVADDR_SET_MSK 0x1fc00000
22733 /* The mask used to clear the ALT_USB_HOST_HCCHAR2_DEVADDR register field value. */
22734 #define ALT_USB_HOST_HCCHAR2_DEVADDR_CLR_MSK 0xe03fffff
22735 /* The reset value of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */
22736 #define ALT_USB_HOST_HCCHAR2_DEVADDR_RESET 0x0
22737 /* Extracts the ALT_USB_HOST_HCCHAR2_DEVADDR field value from a register. */
22738 #define ALT_USB_HOST_HCCHAR2_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
22739 /* Produces a ALT_USB_HOST_HCCHAR2_DEVADDR register field value suitable for setting the register. */
22740 #define ALT_USB_HOST_HCCHAR2_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
22741 
22742 /*
22743  * Field : oddfrm
22744  *
22745  * Odd Frame (OddFrm)
22746  *
22747  * This field is set (reset) by the application to indicate that the OTG host must
22748  * perform
22749  *
22750  * a transfer in an odd (micro)frame. This field is applicable for only periodic
22751  *
22752  * (isochronous and interrupt) transactions.
22753  *
22754  * 1'b0: Even (micro)frame
22755  *
22756  * 1'b1: Odd (micro)frame
22757  *
22758  * Field Access Macros:
22759  *
22760  */
22761 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_ODDFRM register field. */
22762 #define ALT_USB_HOST_HCCHAR2_ODDFRM_LSB 29
22763 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_ODDFRM register field. */
22764 #define ALT_USB_HOST_HCCHAR2_ODDFRM_MSB 29
22765 /* The width in bits of the ALT_USB_HOST_HCCHAR2_ODDFRM register field. */
22766 #define ALT_USB_HOST_HCCHAR2_ODDFRM_WIDTH 1
22767 /* The mask used to set the ALT_USB_HOST_HCCHAR2_ODDFRM register field value. */
22768 #define ALT_USB_HOST_HCCHAR2_ODDFRM_SET_MSK 0x20000000
22769 /* The mask used to clear the ALT_USB_HOST_HCCHAR2_ODDFRM register field value. */
22770 #define ALT_USB_HOST_HCCHAR2_ODDFRM_CLR_MSK 0xdfffffff
22771 /* The reset value of the ALT_USB_HOST_HCCHAR2_ODDFRM register field. */
22772 #define ALT_USB_HOST_HCCHAR2_ODDFRM_RESET 0x0
22773 /* Extracts the ALT_USB_HOST_HCCHAR2_ODDFRM field value from a register. */
22774 #define ALT_USB_HOST_HCCHAR2_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
22775 /* Produces a ALT_USB_HOST_HCCHAR2_ODDFRM register field value suitable for setting the register. */
22776 #define ALT_USB_HOST_HCCHAR2_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
22777 
22778 /*
22779  * Field : chdis
22780  *
22781  * Channel Disable (ChDis)
22782  *
22783  * The application sets this bit to stop transmitting/receiving data
22784  *
22785  * on a channel, even before the transfer For that channel is
22786  *
22787  * complete. The application must wait For the Channel Disabled
22788  *
22789  * interrupt before treating the channel as disabled.
22790  *
22791  * Field Enumeration Values:
22792  *
22793  * Enum | Value | Description
22794  * :-----------------------------------|:------|:----------------------------
22795  * ALT_USB_HOST_HCCHAR2_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
22796  * ALT_USB_HOST_HCCHAR2_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
22797  *
22798  * Field Access Macros:
22799  *
22800  */
22801 /*
22802  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHDIS
22803  *
22804  * Transmit/Recieve normal
22805  */
22806 #define ALT_USB_HOST_HCCHAR2_CHDIS_E_INACT 0x0
22807 /*
22808  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHDIS
22809  *
22810  * Stop transmitting/receiving
22811  */
22812 #define ALT_USB_HOST_HCCHAR2_CHDIS_E_ACT 0x1
22813 
22814 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */
22815 #define ALT_USB_HOST_HCCHAR2_CHDIS_LSB 30
22816 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */
22817 #define ALT_USB_HOST_HCCHAR2_CHDIS_MSB 30
22818 /* The width in bits of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */
22819 #define ALT_USB_HOST_HCCHAR2_CHDIS_WIDTH 1
22820 /* The mask used to set the ALT_USB_HOST_HCCHAR2_CHDIS register field value. */
22821 #define ALT_USB_HOST_HCCHAR2_CHDIS_SET_MSK 0x40000000
22822 /* The mask used to clear the ALT_USB_HOST_HCCHAR2_CHDIS register field value. */
22823 #define ALT_USB_HOST_HCCHAR2_CHDIS_CLR_MSK 0xbfffffff
22824 /* The reset value of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */
22825 #define ALT_USB_HOST_HCCHAR2_CHDIS_RESET 0x0
22826 /* Extracts the ALT_USB_HOST_HCCHAR2_CHDIS field value from a register. */
22827 #define ALT_USB_HOST_HCCHAR2_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
22828 /* Produces a ALT_USB_HOST_HCCHAR2_CHDIS register field value suitable for setting the register. */
22829 #define ALT_USB_HOST_HCCHAR2_CHDIS_SET(value) (((value) << 30) & 0x40000000)
22830 
22831 /*
22832  * Field : chena
22833  *
22834  * Channel Enable (ChEna)
22835  *
22836  * When Scatter/Gather mode is enabled
22837  *
22838  * 1'b0: Indicates that the descriptor structure is not yet ready.
22839  *
22840  * 1'b1: Indicates that the descriptor structure and data buffer with
22841  *
22842  * data is setup and this channel can access the descriptor.
22843  *
22844  * When Scatter/Gather mode is disabled
22845  *
22846  * This field is set by the application and cleared by the OTG host.
22847  *
22848  * 1'b0: Channel disabled
22849  *
22850  * 1'b1: Channel enabled
22851  *
22852  * Field Enumeration Values:
22853  *
22854  * Enum | Value | Description
22855  * :-----------------------------------|:------|:-------------------------------------------------
22856  * ALT_USB_HOST_HCCHAR2_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
22857  * : | | yet ready
22858  * ALT_USB_HOST_HCCHAR2_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
22859  * : | | data buffer with data is setup and this
22860  * : | | channel can access the descriptor
22861  *
22862  * Field Access Macros:
22863  *
22864  */
22865 /*
22866  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHENA
22867  *
22868  * Indicates that the descriptor structure is not yet ready
22869  */
22870 #define ALT_USB_HOST_HCCHAR2_CHENA_E_INACT 0x0
22871 /*
22872  * Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHENA
22873  *
22874  * Indicates that the descriptor structure and data buffer with data is
22875  * setup and this channel can access the descriptor
22876  */
22877 #define ALT_USB_HOST_HCCHAR2_CHENA_E_ACT 0x1
22878 
22879 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_CHENA register field. */
22880 #define ALT_USB_HOST_HCCHAR2_CHENA_LSB 31
22881 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_CHENA register field. */
22882 #define ALT_USB_HOST_HCCHAR2_CHENA_MSB 31
22883 /* The width in bits of the ALT_USB_HOST_HCCHAR2_CHENA register field. */
22884 #define ALT_USB_HOST_HCCHAR2_CHENA_WIDTH 1
22885 /* The mask used to set the ALT_USB_HOST_HCCHAR2_CHENA register field value. */
22886 #define ALT_USB_HOST_HCCHAR2_CHENA_SET_MSK 0x80000000
22887 /* The mask used to clear the ALT_USB_HOST_HCCHAR2_CHENA register field value. */
22888 #define ALT_USB_HOST_HCCHAR2_CHENA_CLR_MSK 0x7fffffff
22889 /* The reset value of the ALT_USB_HOST_HCCHAR2_CHENA register field. */
22890 #define ALT_USB_HOST_HCCHAR2_CHENA_RESET 0x0
22891 /* Extracts the ALT_USB_HOST_HCCHAR2_CHENA field value from a register. */
22892 #define ALT_USB_HOST_HCCHAR2_CHENA_GET(value) (((value) & 0x80000000) >> 31)
22893 /* Produces a ALT_USB_HOST_HCCHAR2_CHENA register field value suitable for setting the register. */
22894 #define ALT_USB_HOST_HCCHAR2_CHENA_SET(value) (((value) << 31) & 0x80000000)
22895 
22896 #ifndef __ASSEMBLY__
22897 /*
22898  * WARNING: The C register and register group struct declarations are provided for
22899  * convenience and illustrative purposes. They should, however, be used with
22900  * caution as the C language standard provides no guarantees about the alignment or
22901  * atomicity of device memory accesses. The recommended practice for writing
22902  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22903  * alt_write_word() functions.
22904  *
22905  * The struct declaration for register ALT_USB_HOST_HCCHAR2.
22906  */
22907 struct ALT_USB_HOST_HCCHAR2_s
22908 {
22909  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR2_MPS */
22910  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR2_EPNUM */
22911  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR2_EPDIR */
22912  uint32_t : 1; /* *UNDEFINED* */
22913  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR2_LSPDDEV */
22914  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR2_EPTYPE */
22915  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR2_EC */
22916  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR2_DEVADDR */
22917  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR2_ODDFRM */
22918  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR2_CHDIS */
22919  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR2_CHENA */
22920 };
22921 
22922 /* The typedef declaration for register ALT_USB_HOST_HCCHAR2. */
22923 typedef volatile struct ALT_USB_HOST_HCCHAR2_s ALT_USB_HOST_HCCHAR2_t;
22924 #endif /* __ASSEMBLY__ */
22925 
22926 /* The reset value of the ALT_USB_HOST_HCCHAR2 register. */
22927 #define ALT_USB_HOST_HCCHAR2_RESET 0x00000000
22928 /* The byte offset of the ALT_USB_HOST_HCCHAR2 register from the beginning of the component. */
22929 #define ALT_USB_HOST_HCCHAR2_OFST 0x140
22930 /* The address of the ALT_USB_HOST_HCCHAR2 register. */
22931 #define ALT_USB_HOST_HCCHAR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR2_OFST))
22932 
22933 /*
22934  * Register : hcsplt2
22935  *
22936  * Host Channel 2 Split Control Register
22937  *
22938  * Register Layout
22939  *
22940  * Bits | Access | Reset | Description
22941  * :--------|:-------|:------|:------------------------------
22942  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT2_PRTADDR
22943  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT2_HUBADDR
22944  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT2_XACTPOS
22945  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT2_COMPSPLT
22946  * [30:17] | ??? | 0x0 | *UNDEFINED*
22947  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT2_SPLTENA
22948  *
22949  */
22950 /*
22951  * Field : prtaddr
22952  *
22953  * Port Address (PrtAddr)
22954  *
22955  * This field is the port number of the recipient transaction
22956  *
22957  * translator.
22958  *
22959  * Field Access Macros:
22960  *
22961  */
22962 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */
22963 #define ALT_USB_HOST_HCSPLT2_PRTADDR_LSB 0
22964 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */
22965 #define ALT_USB_HOST_HCSPLT2_PRTADDR_MSB 6
22966 /* The width in bits of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */
22967 #define ALT_USB_HOST_HCSPLT2_PRTADDR_WIDTH 7
22968 /* The mask used to set the ALT_USB_HOST_HCSPLT2_PRTADDR register field value. */
22969 #define ALT_USB_HOST_HCSPLT2_PRTADDR_SET_MSK 0x0000007f
22970 /* The mask used to clear the ALT_USB_HOST_HCSPLT2_PRTADDR register field value. */
22971 #define ALT_USB_HOST_HCSPLT2_PRTADDR_CLR_MSK 0xffffff80
22972 /* The reset value of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */
22973 #define ALT_USB_HOST_HCSPLT2_PRTADDR_RESET 0x0
22974 /* Extracts the ALT_USB_HOST_HCSPLT2_PRTADDR field value from a register. */
22975 #define ALT_USB_HOST_HCSPLT2_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
22976 /* Produces a ALT_USB_HOST_HCSPLT2_PRTADDR register field value suitable for setting the register. */
22977 #define ALT_USB_HOST_HCSPLT2_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
22978 
22979 /*
22980  * Field : hubaddr
22981  *
22982  * Hub Address (HubAddr)
22983  *
22984  * This field holds the device address of the transaction translator's
22985  *
22986  * hub.
22987  *
22988  * Field Access Macros:
22989  *
22990  */
22991 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */
22992 #define ALT_USB_HOST_HCSPLT2_HUBADDR_LSB 7
22993 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */
22994 #define ALT_USB_HOST_HCSPLT2_HUBADDR_MSB 13
22995 /* The width in bits of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */
22996 #define ALT_USB_HOST_HCSPLT2_HUBADDR_WIDTH 7
22997 /* The mask used to set the ALT_USB_HOST_HCSPLT2_HUBADDR register field value. */
22998 #define ALT_USB_HOST_HCSPLT2_HUBADDR_SET_MSK 0x00003f80
22999 /* The mask used to clear the ALT_USB_HOST_HCSPLT2_HUBADDR register field value. */
23000 #define ALT_USB_HOST_HCSPLT2_HUBADDR_CLR_MSK 0xffffc07f
23001 /* The reset value of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */
23002 #define ALT_USB_HOST_HCSPLT2_HUBADDR_RESET 0x0
23003 /* Extracts the ALT_USB_HOST_HCSPLT2_HUBADDR field value from a register. */
23004 #define ALT_USB_HOST_HCSPLT2_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
23005 /* Produces a ALT_USB_HOST_HCSPLT2_HUBADDR register field value suitable for setting the register. */
23006 #define ALT_USB_HOST_HCSPLT2_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
23007 
23008 /*
23009  * Field : xactpos
23010  *
23011  * Transaction Position (XactPos)
23012  *
23013  * This field is used to determine whether to send all, first, middle,
23014  *
23015  * or last payloads with each OUT transaction.
23016  *
23017  * 2'b11: All. This is the entire data payload is of this transaction
23018  *
23019  * (which is less than or equal to 188 bytes).
23020  *
23021  * 2'b10: Begin. This is the first data payload of this transaction
23022  *
23023  * (which is larger than 188 bytes).
23024  *
23025  * 2'b00: Mid. This is the middle payload of this transaction
23026  *
23027  * (which is larger than 188 bytes).
23028  *
23029  * 2'b01: End. This is the last payload of this transaction (which
23030  *
23031  * is larger than 188 bytes).
23032  *
23033  * Field Enumeration Values:
23034  *
23035  * Enum | Value | Description
23036  * :--------------------------------------|:------|:------------------------------------------------
23037  * ALT_USB_HOST_HCSPLT2_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
23038  * : | | transaction (which is larger than 188 bytes)
23039  * ALT_USB_HOST_HCSPLT2_XACTPOS_E_END | 0x1 | End. This is the last payload of this
23040  * : | | transaction (which is larger than 188 bytes)
23041  * ALT_USB_HOST_HCSPLT2_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
23042  * : | | transaction (which is larger than 188 bytes)
23043  * ALT_USB_HOST_HCSPLT2_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
23044  * : | | transaction (which is less than or equal to 188
23045  * : | | bytes)
23046  *
23047  * Field Access Macros:
23048  *
23049  */
23050 /*
23051  * Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS
23052  *
23053  * Mid. This is the middle payload of this transaction (which is larger than 188
23054  * bytes)
23055  */
23056 #define ALT_USB_HOST_HCSPLT2_XACTPOS_E_MIDDLE 0x0
23057 /*
23058  * Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS
23059  *
23060  * End. This is the last payload of this transaction (which is larger than 188
23061  * bytes)
23062  */
23063 #define ALT_USB_HOST_HCSPLT2_XACTPOS_E_END 0x1
23064 /*
23065  * Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS
23066  *
23067  * Begin. This is the first data payload of this transaction (which is larger than
23068  * 188 bytes)
23069  */
23070 #define ALT_USB_HOST_HCSPLT2_XACTPOS_E_BEGIN 0x2
23071 /*
23072  * Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS
23073  *
23074  * All. This is the entire data payload is of this transaction (which is less than
23075  * or equal to 188 bytes)
23076  */
23077 #define ALT_USB_HOST_HCSPLT2_XACTPOS_E_ALL 0x3
23078 
23079 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */
23080 #define ALT_USB_HOST_HCSPLT2_XACTPOS_LSB 14
23081 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */
23082 #define ALT_USB_HOST_HCSPLT2_XACTPOS_MSB 15
23083 /* The width in bits of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */
23084 #define ALT_USB_HOST_HCSPLT2_XACTPOS_WIDTH 2
23085 /* The mask used to set the ALT_USB_HOST_HCSPLT2_XACTPOS register field value. */
23086 #define ALT_USB_HOST_HCSPLT2_XACTPOS_SET_MSK 0x0000c000
23087 /* The mask used to clear the ALT_USB_HOST_HCSPLT2_XACTPOS register field value. */
23088 #define ALT_USB_HOST_HCSPLT2_XACTPOS_CLR_MSK 0xffff3fff
23089 /* The reset value of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */
23090 #define ALT_USB_HOST_HCSPLT2_XACTPOS_RESET 0x0
23091 /* Extracts the ALT_USB_HOST_HCSPLT2_XACTPOS field value from a register. */
23092 #define ALT_USB_HOST_HCSPLT2_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
23093 /* Produces a ALT_USB_HOST_HCSPLT2_XACTPOS register field value suitable for setting the register. */
23094 #define ALT_USB_HOST_HCSPLT2_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
23095 
23096 /*
23097  * Field : compsplt
23098  *
23099  * Do Complete Split (CompSplt)
23100  *
23101  * The application sets this field to request the OTG host to perform
23102  *
23103  * a complete split transaction.
23104  *
23105  * Field Enumeration Values:
23106  *
23107  * Enum | Value | Description
23108  * :----------------------------------------|:------|:---------------------
23109  * ALT_USB_HOST_HCSPLT2_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
23110  * ALT_USB_HOST_HCSPLT2_COMPSPLT_E_SPLIT | 0x1 | Split transaction
23111  *
23112  * Field Access Macros:
23113  *
23114  */
23115 /*
23116  * Enumerated value for register field ALT_USB_HOST_HCSPLT2_COMPSPLT
23117  *
23118  * No split transaction
23119  */
23120 #define ALT_USB_HOST_HCSPLT2_COMPSPLT_E_NOSPLIT 0x0
23121 /*
23122  * Enumerated value for register field ALT_USB_HOST_HCSPLT2_COMPSPLT
23123  *
23124  * Split transaction
23125  */
23126 #define ALT_USB_HOST_HCSPLT2_COMPSPLT_E_SPLIT 0x1
23127 
23128 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */
23129 #define ALT_USB_HOST_HCSPLT2_COMPSPLT_LSB 16
23130 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */
23131 #define ALT_USB_HOST_HCSPLT2_COMPSPLT_MSB 16
23132 /* The width in bits of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */
23133 #define ALT_USB_HOST_HCSPLT2_COMPSPLT_WIDTH 1
23134 /* The mask used to set the ALT_USB_HOST_HCSPLT2_COMPSPLT register field value. */
23135 #define ALT_USB_HOST_HCSPLT2_COMPSPLT_SET_MSK 0x00010000
23136 /* The mask used to clear the ALT_USB_HOST_HCSPLT2_COMPSPLT register field value. */
23137 #define ALT_USB_HOST_HCSPLT2_COMPSPLT_CLR_MSK 0xfffeffff
23138 /* The reset value of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */
23139 #define ALT_USB_HOST_HCSPLT2_COMPSPLT_RESET 0x0
23140 /* Extracts the ALT_USB_HOST_HCSPLT2_COMPSPLT field value from a register. */
23141 #define ALT_USB_HOST_HCSPLT2_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
23142 /* Produces a ALT_USB_HOST_HCSPLT2_COMPSPLT register field value suitable for setting the register. */
23143 #define ALT_USB_HOST_HCSPLT2_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
23144 
23145 /*
23146  * Field : spltena
23147  *
23148  * Split Enable (SpltEna)
23149  *
23150  * The application sets this field to indicate that this channel is
23151  *
23152  * enabled to perform split transactions.
23153  *
23154  * Field Enumeration Values:
23155  *
23156  * Enum | Value | Description
23157  * :------------------------------------|:------|:------------------
23158  * ALT_USB_HOST_HCSPLT2_SPLTENA_E_DISD | 0x0 | Split not enabled
23159  * ALT_USB_HOST_HCSPLT2_SPLTENA_E_END | 0x1 | Split enabled
23160  *
23161  * Field Access Macros:
23162  *
23163  */
23164 /*
23165  * Enumerated value for register field ALT_USB_HOST_HCSPLT2_SPLTENA
23166  *
23167  * Split not enabled
23168  */
23169 #define ALT_USB_HOST_HCSPLT2_SPLTENA_E_DISD 0x0
23170 /*
23171  * Enumerated value for register field ALT_USB_HOST_HCSPLT2_SPLTENA
23172  *
23173  * Split enabled
23174  */
23175 #define ALT_USB_HOST_HCSPLT2_SPLTENA_E_END 0x1
23176 
23177 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */
23178 #define ALT_USB_HOST_HCSPLT2_SPLTENA_LSB 31
23179 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */
23180 #define ALT_USB_HOST_HCSPLT2_SPLTENA_MSB 31
23181 /* The width in bits of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */
23182 #define ALT_USB_HOST_HCSPLT2_SPLTENA_WIDTH 1
23183 /* The mask used to set the ALT_USB_HOST_HCSPLT2_SPLTENA register field value. */
23184 #define ALT_USB_HOST_HCSPLT2_SPLTENA_SET_MSK 0x80000000
23185 /* The mask used to clear the ALT_USB_HOST_HCSPLT2_SPLTENA register field value. */
23186 #define ALT_USB_HOST_HCSPLT2_SPLTENA_CLR_MSK 0x7fffffff
23187 /* The reset value of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */
23188 #define ALT_USB_HOST_HCSPLT2_SPLTENA_RESET 0x0
23189 /* Extracts the ALT_USB_HOST_HCSPLT2_SPLTENA field value from a register. */
23190 #define ALT_USB_HOST_HCSPLT2_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
23191 /* Produces a ALT_USB_HOST_HCSPLT2_SPLTENA register field value suitable for setting the register. */
23192 #define ALT_USB_HOST_HCSPLT2_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
23193 
23194 #ifndef __ASSEMBLY__
23195 /*
23196  * WARNING: The C register and register group struct declarations are provided for
23197  * convenience and illustrative purposes. They should, however, be used with
23198  * caution as the C language standard provides no guarantees about the alignment or
23199  * atomicity of device memory accesses. The recommended practice for writing
23200  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23201  * alt_write_word() functions.
23202  *
23203  * The struct declaration for register ALT_USB_HOST_HCSPLT2.
23204  */
23205 struct ALT_USB_HOST_HCSPLT2_s
23206 {
23207  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT2_PRTADDR */
23208  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT2_HUBADDR */
23209  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT2_XACTPOS */
23210  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT2_COMPSPLT */
23211  uint32_t : 14; /* *UNDEFINED* */
23212  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT2_SPLTENA */
23213 };
23214 
23215 /* The typedef declaration for register ALT_USB_HOST_HCSPLT2. */
23216 typedef volatile struct ALT_USB_HOST_HCSPLT2_s ALT_USB_HOST_HCSPLT2_t;
23217 #endif /* __ASSEMBLY__ */
23218 
23219 /* The reset value of the ALT_USB_HOST_HCSPLT2 register. */
23220 #define ALT_USB_HOST_HCSPLT2_RESET 0x00000000
23221 /* The byte offset of the ALT_USB_HOST_HCSPLT2 register from the beginning of the component. */
23222 #define ALT_USB_HOST_HCSPLT2_OFST 0x144
23223 /* The address of the ALT_USB_HOST_HCSPLT2 register. */
23224 #define ALT_USB_HOST_HCSPLT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT2_OFST))
23225 
23226 /*
23227  * Register : hcint2
23228  *
23229  * Host Channel 2 Interrupt Register
23230  *
23231  * Register Layout
23232  *
23233  * Bits | Access | Reset | Description
23234  * :--------|:-------|:------|:--------------------------------------
23235  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT2_XFERCOMPL
23236  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT2_CHHLTD
23237  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT2_AHBERR
23238  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT2_STALL
23239  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT2_NAK
23240  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT2_ACK
23241  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT2_NYET
23242  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT2_XACTERR
23243  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT2_BBLERR
23244  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT2_FRMOVRUN
23245  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT2_DATATGLERR
23246  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT2_BNAINTR
23247  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT2_XCS_XACT_ERR
23248  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR
23249  * [31:14] | ??? | 0x0 | *UNDEFINED*
23250  *
23251  */
23252 /*
23253  * Field : xfercompl
23254  *
23255  * Transfer Completed (XferCompl)
23256  *
23257  * Transfer completed normally without any errors.This bit can be set only by the
23258  * core and the application should write 1 to clear it.
23259  *
23260  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
23261  *
23262  * completed with IOC bit set in its descriptor.
23263  *
23264  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
23265  * without
23266  *
23267  * any errors.
23268  *
23269  * Field Enumeration Values:
23270  *
23271  * Enum | Value | Description
23272  * :--------------------------------------|:------|:-----------------------------------------------
23273  * ALT_USB_HOST_HCINT2_XFERCOMPL_E_INACT | 0x0 | No transfer
23274  * ALT_USB_HOST_HCINT2_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
23275  *
23276  * Field Access Macros:
23277  *
23278  */
23279 /*
23280  * Enumerated value for register field ALT_USB_HOST_HCINT2_XFERCOMPL
23281  *
23282  * No transfer
23283  */
23284 #define ALT_USB_HOST_HCINT2_XFERCOMPL_E_INACT 0x0
23285 /*
23286  * Enumerated value for register field ALT_USB_HOST_HCINT2_XFERCOMPL
23287  *
23288  * Transfer completed normally without any errors
23289  */
23290 #define ALT_USB_HOST_HCINT2_XFERCOMPL_E_ACT 0x1
23291 
23292 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */
23293 #define ALT_USB_HOST_HCINT2_XFERCOMPL_LSB 0
23294 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */
23295 #define ALT_USB_HOST_HCINT2_XFERCOMPL_MSB 0
23296 /* The width in bits of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */
23297 #define ALT_USB_HOST_HCINT2_XFERCOMPL_WIDTH 1
23298 /* The mask used to set the ALT_USB_HOST_HCINT2_XFERCOMPL register field value. */
23299 #define ALT_USB_HOST_HCINT2_XFERCOMPL_SET_MSK 0x00000001
23300 /* The mask used to clear the ALT_USB_HOST_HCINT2_XFERCOMPL register field value. */
23301 #define ALT_USB_HOST_HCINT2_XFERCOMPL_CLR_MSK 0xfffffffe
23302 /* The reset value of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */
23303 #define ALT_USB_HOST_HCINT2_XFERCOMPL_RESET 0x0
23304 /* Extracts the ALT_USB_HOST_HCINT2_XFERCOMPL field value from a register. */
23305 #define ALT_USB_HOST_HCINT2_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
23306 /* Produces a ALT_USB_HOST_HCINT2_XFERCOMPL register field value suitable for setting the register. */
23307 #define ALT_USB_HOST_HCINT2_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
23308 
23309 /*
23310  * Field : chhltd
23311  *
23312  * Channel Halted (ChHltd)
23313  *
23314  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
23315  * either because of any USB transaction error or in response to disable request by
23316  * the application or because of a completed transfer.
23317  *
23318  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
23319  * the following
23320  *
23321  * . EOL being set in descriptor
23322  *
23323  * . AHB error
23324  *
23325  * . Excessive transaction errors
23326  *
23327  * . Babble
23328  *
23329  * . Stall
23330  *
23331  * Field Enumeration Values:
23332  *
23333  * Enum | Value | Description
23334  * :-----------------------------------|:------|:-------------------
23335  * ALT_USB_HOST_HCINT2_CHHLTD_E_INACT | 0x0 | Channel not halted
23336  * ALT_USB_HOST_HCINT2_CHHLTD_E_ACT | 0x1 | Channel Halted
23337  *
23338  * Field Access Macros:
23339  *
23340  */
23341 /*
23342  * Enumerated value for register field ALT_USB_HOST_HCINT2_CHHLTD
23343  *
23344  * Channel not halted
23345  */
23346 #define ALT_USB_HOST_HCINT2_CHHLTD_E_INACT 0x0
23347 /*
23348  * Enumerated value for register field ALT_USB_HOST_HCINT2_CHHLTD
23349  *
23350  * Channel Halted
23351  */
23352 #define ALT_USB_HOST_HCINT2_CHHLTD_E_ACT 0x1
23353 
23354 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_CHHLTD register field. */
23355 #define ALT_USB_HOST_HCINT2_CHHLTD_LSB 1
23356 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_CHHLTD register field. */
23357 #define ALT_USB_HOST_HCINT2_CHHLTD_MSB 1
23358 /* The width in bits of the ALT_USB_HOST_HCINT2_CHHLTD register field. */
23359 #define ALT_USB_HOST_HCINT2_CHHLTD_WIDTH 1
23360 /* The mask used to set the ALT_USB_HOST_HCINT2_CHHLTD register field value. */
23361 #define ALT_USB_HOST_HCINT2_CHHLTD_SET_MSK 0x00000002
23362 /* The mask used to clear the ALT_USB_HOST_HCINT2_CHHLTD register field value. */
23363 #define ALT_USB_HOST_HCINT2_CHHLTD_CLR_MSK 0xfffffffd
23364 /* The reset value of the ALT_USB_HOST_HCINT2_CHHLTD register field. */
23365 #define ALT_USB_HOST_HCINT2_CHHLTD_RESET 0x0
23366 /* Extracts the ALT_USB_HOST_HCINT2_CHHLTD field value from a register. */
23367 #define ALT_USB_HOST_HCINT2_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
23368 /* Produces a ALT_USB_HOST_HCINT2_CHHLTD register field value suitable for setting the register. */
23369 #define ALT_USB_HOST_HCINT2_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
23370 
23371 /*
23372  * Field : ahberr
23373  *
23374  * AHB Error (AHBErr)
23375  *
23376  * This is generated only in Internal DMA mode when there is an
23377  *
23378  * AHB error during AHB read/write. The application can read the
23379  *
23380  * corresponding channel's DMA address register to get the error
23381  *
23382  * address.
23383  *
23384  * Field Enumeration Values:
23385  *
23386  * Enum | Value | Description
23387  * :-----------------------------------|:------|:--------------------------------
23388  * ALT_USB_HOST_HCINT2_AHBERR_E_INACT | 0x0 | No AHB error
23389  * ALT_USB_HOST_HCINT2_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
23390  *
23391  * Field Access Macros:
23392  *
23393  */
23394 /*
23395  * Enumerated value for register field ALT_USB_HOST_HCINT2_AHBERR
23396  *
23397  * No AHB error
23398  */
23399 #define ALT_USB_HOST_HCINT2_AHBERR_E_INACT 0x0
23400 /*
23401  * Enumerated value for register field ALT_USB_HOST_HCINT2_AHBERR
23402  *
23403  * AHB error during AHB read/write
23404  */
23405 #define ALT_USB_HOST_HCINT2_AHBERR_E_ACT 0x1
23406 
23407 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_AHBERR register field. */
23408 #define ALT_USB_HOST_HCINT2_AHBERR_LSB 2
23409 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_AHBERR register field. */
23410 #define ALT_USB_HOST_HCINT2_AHBERR_MSB 2
23411 /* The width in bits of the ALT_USB_HOST_HCINT2_AHBERR register field. */
23412 #define ALT_USB_HOST_HCINT2_AHBERR_WIDTH 1
23413 /* The mask used to set the ALT_USB_HOST_HCINT2_AHBERR register field value. */
23414 #define ALT_USB_HOST_HCINT2_AHBERR_SET_MSK 0x00000004
23415 /* The mask used to clear the ALT_USB_HOST_HCINT2_AHBERR register field value. */
23416 #define ALT_USB_HOST_HCINT2_AHBERR_CLR_MSK 0xfffffffb
23417 /* The reset value of the ALT_USB_HOST_HCINT2_AHBERR register field. */
23418 #define ALT_USB_HOST_HCINT2_AHBERR_RESET 0x0
23419 /* Extracts the ALT_USB_HOST_HCINT2_AHBERR field value from a register. */
23420 #define ALT_USB_HOST_HCINT2_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
23421 /* Produces a ALT_USB_HOST_HCINT2_AHBERR register field value suitable for setting the register. */
23422 #define ALT_USB_HOST_HCINT2_AHBERR_SET(value) (((value) << 2) & 0x00000004)
23423 
23424 /*
23425  * Field : stall
23426  *
23427  * STALL Response Received Interrupt (STALL)
23428  *
23429  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
23430  *
23431  * in the core.This bit can be set only by the core and the application should
23432  * write 1 to clear
23433  *
23434  * it.
23435  *
23436  * Field Enumeration Values:
23437  *
23438  * Enum | Value | Description
23439  * :----------------------------------|:------|:-------------------
23440  * ALT_USB_HOST_HCINT2_STALL_E_INACT | 0x0 | No Stall Interrupt
23441  * ALT_USB_HOST_HCINT2_STALL_E_ACT | 0x1 | Stall Interrupt
23442  *
23443  * Field Access Macros:
23444  *
23445  */
23446 /*
23447  * Enumerated value for register field ALT_USB_HOST_HCINT2_STALL
23448  *
23449  * No Stall Interrupt
23450  */
23451 #define ALT_USB_HOST_HCINT2_STALL_E_INACT 0x0
23452 /*
23453  * Enumerated value for register field ALT_USB_HOST_HCINT2_STALL
23454  *
23455  * Stall Interrupt
23456  */
23457 #define ALT_USB_HOST_HCINT2_STALL_E_ACT 0x1
23458 
23459 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_STALL register field. */
23460 #define ALT_USB_HOST_HCINT2_STALL_LSB 3
23461 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_STALL register field. */
23462 #define ALT_USB_HOST_HCINT2_STALL_MSB 3
23463 /* The width in bits of the ALT_USB_HOST_HCINT2_STALL register field. */
23464 #define ALT_USB_HOST_HCINT2_STALL_WIDTH 1
23465 /* The mask used to set the ALT_USB_HOST_HCINT2_STALL register field value. */
23466 #define ALT_USB_HOST_HCINT2_STALL_SET_MSK 0x00000008
23467 /* The mask used to clear the ALT_USB_HOST_HCINT2_STALL register field value. */
23468 #define ALT_USB_HOST_HCINT2_STALL_CLR_MSK 0xfffffff7
23469 /* The reset value of the ALT_USB_HOST_HCINT2_STALL register field. */
23470 #define ALT_USB_HOST_HCINT2_STALL_RESET 0x0
23471 /* Extracts the ALT_USB_HOST_HCINT2_STALL field value from a register. */
23472 #define ALT_USB_HOST_HCINT2_STALL_GET(value) (((value) & 0x00000008) >> 3)
23473 /* Produces a ALT_USB_HOST_HCINT2_STALL register field value suitable for setting the register. */
23474 #define ALT_USB_HOST_HCINT2_STALL_SET(value) (((value) << 3) & 0x00000008)
23475 
23476 /*
23477  * Field : nak
23478  *
23479  * NAK Response Received Interrupt (NAK)
23480  *
23481  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
23482  *
23483  * in the core.This bit can be set only by the core and the application should
23484  * write 1 to clear
23485  *
23486  * it.
23487  *
23488  * Field Enumeration Values:
23489  *
23490  * Enum | Value | Description
23491  * :--------------------------------|:------|:-----------------------------------
23492  * ALT_USB_HOST_HCINT2_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
23493  * ALT_USB_HOST_HCINT2_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
23494  *
23495  * Field Access Macros:
23496  *
23497  */
23498 /*
23499  * Enumerated value for register field ALT_USB_HOST_HCINT2_NAK
23500  *
23501  * No NAK Response Received Interrupt
23502  */
23503 #define ALT_USB_HOST_HCINT2_NAK_E_INACT 0x0
23504 /*
23505  * Enumerated value for register field ALT_USB_HOST_HCINT2_NAK
23506  *
23507  * NAK Response Received Interrupt
23508  */
23509 #define ALT_USB_HOST_HCINT2_NAK_E_ACT 0x1
23510 
23511 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_NAK register field. */
23512 #define ALT_USB_HOST_HCINT2_NAK_LSB 4
23513 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_NAK register field. */
23514 #define ALT_USB_HOST_HCINT2_NAK_MSB 4
23515 /* The width in bits of the ALT_USB_HOST_HCINT2_NAK register field. */
23516 #define ALT_USB_HOST_HCINT2_NAK_WIDTH 1
23517 /* The mask used to set the ALT_USB_HOST_HCINT2_NAK register field value. */
23518 #define ALT_USB_HOST_HCINT2_NAK_SET_MSK 0x00000010
23519 /* The mask used to clear the ALT_USB_HOST_HCINT2_NAK register field value. */
23520 #define ALT_USB_HOST_HCINT2_NAK_CLR_MSK 0xffffffef
23521 /* The reset value of the ALT_USB_HOST_HCINT2_NAK register field. */
23522 #define ALT_USB_HOST_HCINT2_NAK_RESET 0x0
23523 /* Extracts the ALT_USB_HOST_HCINT2_NAK field value from a register. */
23524 #define ALT_USB_HOST_HCINT2_NAK_GET(value) (((value) & 0x00000010) >> 4)
23525 /* Produces a ALT_USB_HOST_HCINT2_NAK register field value suitable for setting the register. */
23526 #define ALT_USB_HOST_HCINT2_NAK_SET(value) (((value) << 4) & 0x00000010)
23527 
23528 /*
23529  * Field : ack
23530  *
23531  * ACK Response Received/Transmitted Interrupt (ACK)
23532  *
23533  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
23534  *
23535  * in the core.This bit can be set only by the core and the application should
23536  * write 1 to clear
23537  *
23538  * it.
23539  *
23540  * Field Enumeration Values:
23541  *
23542  * Enum | Value | Description
23543  * :--------------------------------|:------|:-----------------------------------------------
23544  * ALT_USB_HOST_HCINT2_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
23545  * ALT_USB_HOST_HCINT2_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
23546  *
23547  * Field Access Macros:
23548  *
23549  */
23550 /*
23551  * Enumerated value for register field ALT_USB_HOST_HCINT2_ACK
23552  *
23553  * No ACK Response Received Transmitted Interrupt
23554  */
23555 #define ALT_USB_HOST_HCINT2_ACK_E_INACT 0x0
23556 /*
23557  * Enumerated value for register field ALT_USB_HOST_HCINT2_ACK
23558  *
23559  * ACK Response Received Transmitted Interrup
23560  */
23561 #define ALT_USB_HOST_HCINT2_ACK_E_ACT 0x1
23562 
23563 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_ACK register field. */
23564 #define ALT_USB_HOST_HCINT2_ACK_LSB 5
23565 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_ACK register field. */
23566 #define ALT_USB_HOST_HCINT2_ACK_MSB 5
23567 /* The width in bits of the ALT_USB_HOST_HCINT2_ACK register field. */
23568 #define ALT_USB_HOST_HCINT2_ACK_WIDTH 1
23569 /* The mask used to set the ALT_USB_HOST_HCINT2_ACK register field value. */
23570 #define ALT_USB_HOST_HCINT2_ACK_SET_MSK 0x00000020
23571 /* The mask used to clear the ALT_USB_HOST_HCINT2_ACK register field value. */
23572 #define ALT_USB_HOST_HCINT2_ACK_CLR_MSK 0xffffffdf
23573 /* The reset value of the ALT_USB_HOST_HCINT2_ACK register field. */
23574 #define ALT_USB_HOST_HCINT2_ACK_RESET 0x0
23575 /* Extracts the ALT_USB_HOST_HCINT2_ACK field value from a register. */
23576 #define ALT_USB_HOST_HCINT2_ACK_GET(value) (((value) & 0x00000020) >> 5)
23577 /* Produces a ALT_USB_HOST_HCINT2_ACK register field value suitable for setting the register. */
23578 #define ALT_USB_HOST_HCINT2_ACK_SET(value) (((value) << 5) & 0x00000020)
23579 
23580 /*
23581  * Field : nyet
23582  *
23583  * NYET Response Received Interrupt (NYET)
23584  *
23585  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
23586  *
23587  * in the core.This bit can be set only by the core and the application should
23588  * write 1 to clear
23589  *
23590  * it.
23591  *
23592  * Field Enumeration Values:
23593  *
23594  * Enum | Value | Description
23595  * :---------------------------------|:------|:------------------------------------
23596  * ALT_USB_HOST_HCINT2_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
23597  * ALT_USB_HOST_HCINT2_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
23598  *
23599  * Field Access Macros:
23600  *
23601  */
23602 /*
23603  * Enumerated value for register field ALT_USB_HOST_HCINT2_NYET
23604  *
23605  * No NYET Response Received Interrupt
23606  */
23607 #define ALT_USB_HOST_HCINT2_NYET_E_INACT 0x0
23608 /*
23609  * Enumerated value for register field ALT_USB_HOST_HCINT2_NYET
23610  *
23611  * NYET Response Received Interrupt
23612  */
23613 #define ALT_USB_HOST_HCINT2_NYET_E_ACT 0x1
23614 
23615 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_NYET register field. */
23616 #define ALT_USB_HOST_HCINT2_NYET_LSB 6
23617 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_NYET register field. */
23618 #define ALT_USB_HOST_HCINT2_NYET_MSB 6
23619 /* The width in bits of the ALT_USB_HOST_HCINT2_NYET register field. */
23620 #define ALT_USB_HOST_HCINT2_NYET_WIDTH 1
23621 /* The mask used to set the ALT_USB_HOST_HCINT2_NYET register field value. */
23622 #define ALT_USB_HOST_HCINT2_NYET_SET_MSK 0x00000040
23623 /* The mask used to clear the ALT_USB_HOST_HCINT2_NYET register field value. */
23624 #define ALT_USB_HOST_HCINT2_NYET_CLR_MSK 0xffffffbf
23625 /* The reset value of the ALT_USB_HOST_HCINT2_NYET register field. */
23626 #define ALT_USB_HOST_HCINT2_NYET_RESET 0x0
23627 /* Extracts the ALT_USB_HOST_HCINT2_NYET field value from a register. */
23628 #define ALT_USB_HOST_HCINT2_NYET_GET(value) (((value) & 0x00000040) >> 6)
23629 /* Produces a ALT_USB_HOST_HCINT2_NYET register field value suitable for setting the register. */
23630 #define ALT_USB_HOST_HCINT2_NYET_SET(value) (((value) << 6) & 0x00000040)
23631 
23632 /*
23633  * Field : xacterr
23634  *
23635  * Transaction Error (XactErr)
23636  *
23637  * Indicates one of the following errors occurred on the USB.
23638  *
23639  * CRC check failure
23640  *
23641  * Timeout
23642  *
23643  * Bit stuff error
23644  *
23645  * False EOP
23646  *
23647  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
23648  *
23649  * in the core.This bit can be set only by the core and the application should
23650  * write 1 to clear
23651  *
23652  * it.
23653  *
23654  * Field Enumeration Values:
23655  *
23656  * Enum | Value | Description
23657  * :------------------------------------|:------|:---------------------
23658  * ALT_USB_HOST_HCINT2_XACTERR_E_INACT | 0x0 | No Transaction Error
23659  * ALT_USB_HOST_HCINT2_XACTERR_E_ACT | 0x1 | Transaction Error
23660  *
23661  * Field Access Macros:
23662  *
23663  */
23664 /*
23665  * Enumerated value for register field ALT_USB_HOST_HCINT2_XACTERR
23666  *
23667  * No Transaction Error
23668  */
23669 #define ALT_USB_HOST_HCINT2_XACTERR_E_INACT 0x0
23670 /*
23671  * Enumerated value for register field ALT_USB_HOST_HCINT2_XACTERR
23672  *
23673  * Transaction Error
23674  */
23675 #define ALT_USB_HOST_HCINT2_XACTERR_E_ACT 0x1
23676 
23677 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_XACTERR register field. */
23678 #define ALT_USB_HOST_HCINT2_XACTERR_LSB 7
23679 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_XACTERR register field. */
23680 #define ALT_USB_HOST_HCINT2_XACTERR_MSB 7
23681 /* The width in bits of the ALT_USB_HOST_HCINT2_XACTERR register field. */
23682 #define ALT_USB_HOST_HCINT2_XACTERR_WIDTH 1
23683 /* The mask used to set the ALT_USB_HOST_HCINT2_XACTERR register field value. */
23684 #define ALT_USB_HOST_HCINT2_XACTERR_SET_MSK 0x00000080
23685 /* The mask used to clear the ALT_USB_HOST_HCINT2_XACTERR register field value. */
23686 #define ALT_USB_HOST_HCINT2_XACTERR_CLR_MSK 0xffffff7f
23687 /* The reset value of the ALT_USB_HOST_HCINT2_XACTERR register field. */
23688 #define ALT_USB_HOST_HCINT2_XACTERR_RESET 0x0
23689 /* Extracts the ALT_USB_HOST_HCINT2_XACTERR field value from a register. */
23690 #define ALT_USB_HOST_HCINT2_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
23691 /* Produces a ALT_USB_HOST_HCINT2_XACTERR register field value suitable for setting the register. */
23692 #define ALT_USB_HOST_HCINT2_XACTERR_SET(value) (((value) << 7) & 0x00000080)
23693 
23694 /*
23695  * Field : bblerr
23696  *
23697  * Babble Error (BblErr)
23698  *
23699  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
23700  *
23701  * in the core..This bit can be set only by the core and the application should
23702  * write 1 to clear
23703  *
23704  * it.
23705  *
23706  * Field Enumeration Values:
23707  *
23708  * Enum | Value | Description
23709  * :-----------------------------------|:------|:----------------
23710  * ALT_USB_HOST_HCINT2_BBLERR_E_INACT | 0x0 | No Babble Error
23711  * ALT_USB_HOST_HCINT2_BBLERR_E_ACT | 0x1 | Babble Error
23712  *
23713  * Field Access Macros:
23714  *
23715  */
23716 /*
23717  * Enumerated value for register field ALT_USB_HOST_HCINT2_BBLERR
23718  *
23719  * No Babble Error
23720  */
23721 #define ALT_USB_HOST_HCINT2_BBLERR_E_INACT 0x0
23722 /*
23723  * Enumerated value for register field ALT_USB_HOST_HCINT2_BBLERR
23724  *
23725  * Babble Error
23726  */
23727 #define ALT_USB_HOST_HCINT2_BBLERR_E_ACT 0x1
23728 
23729 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_BBLERR register field. */
23730 #define ALT_USB_HOST_HCINT2_BBLERR_LSB 8
23731 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_BBLERR register field. */
23732 #define ALT_USB_HOST_HCINT2_BBLERR_MSB 8
23733 /* The width in bits of the ALT_USB_HOST_HCINT2_BBLERR register field. */
23734 #define ALT_USB_HOST_HCINT2_BBLERR_WIDTH 1
23735 /* The mask used to set the ALT_USB_HOST_HCINT2_BBLERR register field value. */
23736 #define ALT_USB_HOST_HCINT2_BBLERR_SET_MSK 0x00000100
23737 /* The mask used to clear the ALT_USB_HOST_HCINT2_BBLERR register field value. */
23738 #define ALT_USB_HOST_HCINT2_BBLERR_CLR_MSK 0xfffffeff
23739 /* The reset value of the ALT_USB_HOST_HCINT2_BBLERR register field. */
23740 #define ALT_USB_HOST_HCINT2_BBLERR_RESET 0x0
23741 /* Extracts the ALT_USB_HOST_HCINT2_BBLERR field value from a register. */
23742 #define ALT_USB_HOST_HCINT2_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
23743 /* Produces a ALT_USB_HOST_HCINT2_BBLERR register field value suitable for setting the register. */
23744 #define ALT_USB_HOST_HCINT2_BBLERR_SET(value) (((value) << 8) & 0x00000100)
23745 
23746 /*
23747  * Field : frmovrun
23748  *
23749  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
23750  * bit is masked
23751  *
23752  * in the core.This bit can be set only by the core and the application should
23753  * write 1 to clear
23754  *
23755  * it.
23756  *
23757  * Field Enumeration Values:
23758  *
23759  * Enum | Value | Description
23760  * :-------------------------------------|:------|:-----------------
23761  * ALT_USB_HOST_HCINT2_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
23762  * ALT_USB_HOST_HCINT2_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
23763  *
23764  * Field Access Macros:
23765  *
23766  */
23767 /*
23768  * Enumerated value for register field ALT_USB_HOST_HCINT2_FRMOVRUN
23769  *
23770  * No Frame Overrun
23771  */
23772 #define ALT_USB_HOST_HCINT2_FRMOVRUN_E_INACT 0x0
23773 /*
23774  * Enumerated value for register field ALT_USB_HOST_HCINT2_FRMOVRUN
23775  *
23776  * Frame Overrun
23777  */
23778 #define ALT_USB_HOST_HCINT2_FRMOVRUN_E_ACT 0x1
23779 
23780 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */
23781 #define ALT_USB_HOST_HCINT2_FRMOVRUN_LSB 9
23782 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */
23783 #define ALT_USB_HOST_HCINT2_FRMOVRUN_MSB 9
23784 /* The width in bits of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */
23785 #define ALT_USB_HOST_HCINT2_FRMOVRUN_WIDTH 1
23786 /* The mask used to set the ALT_USB_HOST_HCINT2_FRMOVRUN register field value. */
23787 #define ALT_USB_HOST_HCINT2_FRMOVRUN_SET_MSK 0x00000200
23788 /* The mask used to clear the ALT_USB_HOST_HCINT2_FRMOVRUN register field value. */
23789 #define ALT_USB_HOST_HCINT2_FRMOVRUN_CLR_MSK 0xfffffdff
23790 /* The reset value of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */
23791 #define ALT_USB_HOST_HCINT2_FRMOVRUN_RESET 0x0
23792 /* Extracts the ALT_USB_HOST_HCINT2_FRMOVRUN field value from a register. */
23793 #define ALT_USB_HOST_HCINT2_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
23794 /* Produces a ALT_USB_HOST_HCINT2_FRMOVRUN register field value suitable for setting the register. */
23795 #define ALT_USB_HOST_HCINT2_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
23796 
23797 /*
23798  * Field : datatglerr
23799  *
23800  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
23801  * application should write 1 to clear
23802  *
23803  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
23804  *
23805  * in the core.
23806  *
23807  * Field Enumeration Values:
23808  *
23809  * Enum | Value | Description
23810  * :---------------------------------------|:------|:---------------------
23811  * ALT_USB_HOST_HCINT2_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
23812  * ALT_USB_HOST_HCINT2_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
23813  *
23814  * Field Access Macros:
23815  *
23816  */
23817 /*
23818  * Enumerated value for register field ALT_USB_HOST_HCINT2_DATATGLERR
23819  *
23820  * No Data Toggle Error
23821  */
23822 #define ALT_USB_HOST_HCINT2_DATATGLERR_E_INACT 0x0
23823 /*
23824  * Enumerated value for register field ALT_USB_HOST_HCINT2_DATATGLERR
23825  *
23826  * Data Toggle Error
23827  */
23828 #define ALT_USB_HOST_HCINT2_DATATGLERR_E_ACT 0x1
23829 
23830 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */
23831 #define ALT_USB_HOST_HCINT2_DATATGLERR_LSB 10
23832 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */
23833 #define ALT_USB_HOST_HCINT2_DATATGLERR_MSB 10
23834 /* The width in bits of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */
23835 #define ALT_USB_HOST_HCINT2_DATATGLERR_WIDTH 1
23836 /* The mask used to set the ALT_USB_HOST_HCINT2_DATATGLERR register field value. */
23837 #define ALT_USB_HOST_HCINT2_DATATGLERR_SET_MSK 0x00000400
23838 /* The mask used to clear the ALT_USB_HOST_HCINT2_DATATGLERR register field value. */
23839 #define ALT_USB_HOST_HCINT2_DATATGLERR_CLR_MSK 0xfffffbff
23840 /* The reset value of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */
23841 #define ALT_USB_HOST_HCINT2_DATATGLERR_RESET 0x0
23842 /* Extracts the ALT_USB_HOST_HCINT2_DATATGLERR field value from a register. */
23843 #define ALT_USB_HOST_HCINT2_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
23844 /* Produces a ALT_USB_HOST_HCINT2_DATATGLERR register field value suitable for setting the register. */
23845 #define ALT_USB_HOST_HCINT2_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
23846 
23847 /*
23848  * Field : bnaintr
23849  *
23850  * BNA (Buffer Not Available) Interrupt (BNAIntr)
23851  *
23852  * This bit is valid only when Scatter/Gather DMA mode is enabled.
23853  *
23854  * The core generates this interrupt when the descriptor accessed
23855  *
23856  * is not ready for the Core to process. BNA will not be generated
23857  *
23858  * for Isochronous channels.
23859  *
23860  * For non Scatter/Gather DMA mode, this bit is reserved.
23861  *
23862  * Field Enumeration Values:
23863  *
23864  * Enum | Value | Description
23865  * :------------------------------------|:------|:-----------------
23866  * ALT_USB_HOST_HCINT2_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
23867  * ALT_USB_HOST_HCINT2_BNAINTR_E_ACT | 0x1 | BNA Interrupt
23868  *
23869  * Field Access Macros:
23870  *
23871  */
23872 /*
23873  * Enumerated value for register field ALT_USB_HOST_HCINT2_BNAINTR
23874  *
23875  * No BNA Interrupt
23876  */
23877 #define ALT_USB_HOST_HCINT2_BNAINTR_E_INACT 0x0
23878 /*
23879  * Enumerated value for register field ALT_USB_HOST_HCINT2_BNAINTR
23880  *
23881  * BNA Interrupt
23882  */
23883 #define ALT_USB_HOST_HCINT2_BNAINTR_E_ACT 0x1
23884 
23885 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_BNAINTR register field. */
23886 #define ALT_USB_HOST_HCINT2_BNAINTR_LSB 11
23887 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_BNAINTR register field. */
23888 #define ALT_USB_HOST_HCINT2_BNAINTR_MSB 11
23889 /* The width in bits of the ALT_USB_HOST_HCINT2_BNAINTR register field. */
23890 #define ALT_USB_HOST_HCINT2_BNAINTR_WIDTH 1
23891 /* The mask used to set the ALT_USB_HOST_HCINT2_BNAINTR register field value. */
23892 #define ALT_USB_HOST_HCINT2_BNAINTR_SET_MSK 0x00000800
23893 /* The mask used to clear the ALT_USB_HOST_HCINT2_BNAINTR register field value. */
23894 #define ALT_USB_HOST_HCINT2_BNAINTR_CLR_MSK 0xfffff7ff
23895 /* The reset value of the ALT_USB_HOST_HCINT2_BNAINTR register field. */
23896 #define ALT_USB_HOST_HCINT2_BNAINTR_RESET 0x0
23897 /* Extracts the ALT_USB_HOST_HCINT2_BNAINTR field value from a register. */
23898 #define ALT_USB_HOST_HCINT2_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
23899 /* Produces a ALT_USB_HOST_HCINT2_BNAINTR register field value suitable for setting the register. */
23900 #define ALT_USB_HOST_HCINT2_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
23901 
23902 /*
23903  * Field : xcs_xact_err
23904  *
23905  * Excessive Transaction Error (XCS_XACT_ERR)
23906  *
23907  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
23908  * this bit
23909  *
23910  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
23911  *
23912  * not be generated for Isochronous channels.
23913  *
23914  * For non Scatter/Gather DMA mode, this bit is reserved.
23915  *
23916  * Field Enumeration Values:
23917  *
23918  * Enum | Value | Description
23919  * :-------------------------------------------|:------|:-------------------------------
23920  * ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
23921  * ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
23922  *
23923  * Field Access Macros:
23924  *
23925  */
23926 /*
23927  * Enumerated value for register field ALT_USB_HOST_HCINT2_XCS_XACT_ERR
23928  *
23929  * No Excessive Transaction Error
23930  */
23931 #define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_INACT 0x0
23932 /*
23933  * Enumerated value for register field ALT_USB_HOST_HCINT2_XCS_XACT_ERR
23934  *
23935  * Excessive Transaction Error
23936  */
23937 #define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_ACVTIVE 0x1
23938 
23939 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */
23940 #define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_LSB 12
23941 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */
23942 #define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_MSB 12
23943 /* The width in bits of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */
23944 #define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_WIDTH 1
23945 /* The mask used to set the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field value. */
23946 #define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_SET_MSK 0x00001000
23947 /* The mask used to clear the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field value. */
23948 #define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_CLR_MSK 0xffffefff
23949 /* The reset value of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */
23950 #define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_RESET 0x0
23951 /* Extracts the ALT_USB_HOST_HCINT2_XCS_XACT_ERR field value from a register. */
23952 #define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
23953 /* Produces a ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field value suitable for setting the register. */
23954 #define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
23955 
23956 /*
23957  * Field : desc_lst_rollintr
23958  *
23959  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
23960  *
23961  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
23962  * this bit
23963  *
23964  * when the corresponding channel's descriptor list rolls over.
23965  *
23966  * For non Scatter/Gather DMA mode, this bit is reserved.
23967  *
23968  * Field Enumeration Values:
23969  *
23970  * Enum | Value | Description
23971  * :----------------------------------------------|:------|:---------------------------------
23972  * ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
23973  * ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
23974  *
23975  * Field Access Macros:
23976  *
23977  */
23978 /*
23979  * Enumerated value for register field ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR
23980  *
23981  * No Descriptor rollover interrupt
23982  */
23983 #define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_INACT 0x0
23984 /*
23985  * Enumerated value for register field ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR
23986  *
23987  * Descriptor rollover interrupt
23988  */
23989 #define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_ACT 0x1
23990 
23991 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */
23992 #define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_LSB 13
23993 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */
23994 #define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_MSB 13
23995 /* The width in bits of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */
23996 #define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_WIDTH 1
23997 /* The mask used to set the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field value. */
23998 #define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_SET_MSK 0x00002000
23999 /* The mask used to clear the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field value. */
24000 #define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
24001 /* The reset value of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */
24002 #define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_RESET 0x0
24003 /* Extracts the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR field value from a register. */
24004 #define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
24005 /* Produces a ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field value suitable for setting the register. */
24006 #define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
24007 
24008 #ifndef __ASSEMBLY__
24009 /*
24010  * WARNING: The C register and register group struct declarations are provided for
24011  * convenience and illustrative purposes. They should, however, be used with
24012  * caution as the C language standard provides no guarantees about the alignment or
24013  * atomicity of device memory accesses. The recommended practice for writing
24014  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24015  * alt_write_word() functions.
24016  *
24017  * The struct declaration for register ALT_USB_HOST_HCINT2.
24018  */
24019 struct ALT_USB_HOST_HCINT2_s
24020 {
24021  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT2_XFERCOMPL */
24022  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT2_CHHLTD */
24023  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT2_AHBERR */
24024  uint32_t stall : 1; /* ALT_USB_HOST_HCINT2_STALL */
24025  uint32_t nak : 1; /* ALT_USB_HOST_HCINT2_NAK */
24026  uint32_t ack : 1; /* ALT_USB_HOST_HCINT2_ACK */
24027  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT2_NYET */
24028  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT2_XACTERR */
24029  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT2_BBLERR */
24030  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT2_FRMOVRUN */
24031  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT2_DATATGLERR */
24032  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT2_BNAINTR */
24033  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT2_XCS_XACT_ERR */
24034  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR */
24035  uint32_t : 18; /* *UNDEFINED* */
24036 };
24037 
24038 /* The typedef declaration for register ALT_USB_HOST_HCINT2. */
24039 typedef volatile struct ALT_USB_HOST_HCINT2_s ALT_USB_HOST_HCINT2_t;
24040 #endif /* __ASSEMBLY__ */
24041 
24042 /* The reset value of the ALT_USB_HOST_HCINT2 register. */
24043 #define ALT_USB_HOST_HCINT2_RESET 0x00000000
24044 /* The byte offset of the ALT_USB_HOST_HCINT2 register from the beginning of the component. */
24045 #define ALT_USB_HOST_HCINT2_OFST 0x148
24046 /* The address of the ALT_USB_HOST_HCINT2 register. */
24047 #define ALT_USB_HOST_HCINT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT2_OFST))
24048 
24049 /*
24050  * Register : hcintmsk2
24051  *
24052  * Host Channel 2 Interrupt Mask Register
24053  *
24054  * Register Layout
24055  *
24056  * Bits | Access | Reset | Description
24057  * :--------|:-------|:------|:-------------------------------------------
24058  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK
24059  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_CHHLTDMSK
24060  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_AHBERRMSK
24061  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_STALLMSK
24062  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_NAKMSK
24063  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_ACKMSK
24064  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_NYETMSK
24065  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_XACTERRMSK
24066  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_BBLERRMSK
24067  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK
24068  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK
24069  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_BNAINTRMSK
24070  * [12] | ??? | 0x0 | *UNDEFINED*
24071  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK
24072  * [31:14] | ??? | 0x0 | *UNDEFINED*
24073  *
24074  */
24075 /*
24076  * Field : xfercomplmsk
24077  *
24078  * Transfer Completed Mask (XferComplMsk)
24079  *
24080  * Field Enumeration Values:
24081  *
24082  * Enum | Value | Description
24083  * :--------------------------------------------|:------|:------------
24084  * ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_MSK | 0x0 | Mask
24085  * ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
24086  *
24087  * Field Access Macros:
24088  *
24089  */
24090 /*
24091  * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK
24092  *
24093  * Mask
24094  */
24095 #define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_MSK 0x0
24096 /*
24097  * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK
24098  *
24099  * No mask
24100  */
24101 #define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_NOMSK 0x1
24102 
24103 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */
24104 #define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_LSB 0
24105 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */
24106 #define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_MSB 0
24107 /* The width in bits of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */
24108 #define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_WIDTH 1
24109 /* The mask used to set the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field value. */
24110 #define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_SET_MSK 0x00000001
24111 /* The mask used to clear the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field value. */
24112 #define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_CLR_MSK 0xfffffffe
24113 /* The reset value of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */
24114 #define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_RESET 0x0
24115 /* Extracts the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK field value from a register. */
24116 #define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
24117 /* Produces a ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field value suitable for setting the register. */
24118 #define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
24119 
24120 /*
24121  * Field : chhltdmsk
24122  *
24123  * Channel Halted Mask (ChHltdMsk)
24124  *
24125  * Field Enumeration Values:
24126  *
24127  * Enum | Value | Description
24128  * :-----------------------------------------|:------|:------------
24129  * ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_MSK | 0x0 | Mask
24130  * ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_NOMSK | 0x1 | No mask
24131  *
24132  * Field Access Macros:
24133  *
24134  */
24135 /*
24136  * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_CHHLTDMSK
24137  *
24138  * Mask
24139  */
24140 #define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_MSK 0x0
24141 /*
24142  * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_CHHLTDMSK
24143  *
24144  * No mask
24145  */
24146 #define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_NOMSK 0x1
24147 
24148 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */
24149 #define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_LSB 1
24150 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */
24151 #define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_MSB 1
24152 /* The width in bits of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */
24153 #define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_WIDTH 1
24154 /* The mask used to set the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field value. */
24155 #define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_SET_MSK 0x00000002
24156 /* The mask used to clear the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field value. */
24157 #define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_CLR_MSK 0xfffffffd
24158 /* The reset value of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */
24159 #define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_RESET 0x0
24160 /* Extracts the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK field value from a register. */
24161 #define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
24162 /* Produces a ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field value suitable for setting the register. */
24163 #define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
24164 
24165 /*
24166  * Field : ahberrmsk
24167  *
24168  * AHB Error Mask (AHBErrMsk)
24169  *
24170  * In scatter/gather DMA mode for host,
24171  *
24172  * interrupts will not be generated due to the corresponding bits set in
24173  *
24174  * HCINTn.
24175  *
24176  * Field Enumeration Values:
24177  *
24178  * Enum | Value | Description
24179  * :-----------------------------------------|:------|:------------
24180  * ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_MSK | 0x0 | Mask
24181  * ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_NOMSK | 0x1 | No mask
24182  *
24183  * Field Access Macros:
24184  *
24185  */
24186 /*
24187  * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_AHBERRMSK
24188  *
24189  * Mask
24190  */
24191 #define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_MSK 0x0
24192 /*
24193  * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_AHBERRMSK
24194  *
24195  * No mask
24196  */
24197 #define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_NOMSK 0x1
24198 
24199 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */
24200 #define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_LSB 2
24201 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */
24202 #define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_MSB 2
24203 /* The width in bits of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */
24204 #define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_WIDTH 1
24205 /* The mask used to set the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field value. */
24206 #define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_SET_MSK 0x00000004
24207 /* The mask used to clear the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field value. */
24208 #define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_CLR_MSK 0xfffffffb
24209 /* The reset value of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */
24210 #define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_RESET 0x0
24211 /* Extracts the ALT_USB_HOST_HCINTMSK2_AHBERRMSK field value from a register. */
24212 #define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
24213 /* Produces a ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field value suitable for setting the register. */
24214 #define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
24215 
24216 /*
24217  * Field : stallmsk
24218  *
24219  * STALL Response Received Interrupt Mask (StallMsk)
24220  *
24221  * In scatter/gather DMA mode for host,
24222  *
24223  * interrupts will not be generated due to the corresponding bits set in
24224  *
24225  * HCINTn.
24226  *
24227  * Field Access Macros:
24228  *
24229  */
24230 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_STALLMSK register field. */
24231 #define ALT_USB_HOST_HCINTMSK2_STALLMSK_LSB 3
24232 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_STALLMSK register field. */
24233 #define ALT_USB_HOST_HCINTMSK2_STALLMSK_MSB 3
24234 /* The width in bits of the ALT_USB_HOST_HCINTMSK2_STALLMSK register field. */
24235 #define ALT_USB_HOST_HCINTMSK2_STALLMSK_WIDTH 1
24236 /* The mask used to set the ALT_USB_HOST_HCINTMSK2_STALLMSK register field value. */
24237 #define ALT_USB_HOST_HCINTMSK2_STALLMSK_SET_MSK 0x00000008
24238 /* The mask used to clear the ALT_USB_HOST_HCINTMSK2_STALLMSK register field value. */
24239 #define ALT_USB_HOST_HCINTMSK2_STALLMSK_CLR_MSK 0xfffffff7
24240 /* The reset value of the ALT_USB_HOST_HCINTMSK2_STALLMSK register field. */
24241 #define ALT_USB_HOST_HCINTMSK2_STALLMSK_RESET 0x0
24242 /* Extracts the ALT_USB_HOST_HCINTMSK2_STALLMSK field value from a register. */
24243 #define ALT_USB_HOST_HCINTMSK2_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
24244 /* Produces a ALT_USB_HOST_HCINTMSK2_STALLMSK register field value suitable for setting the register. */
24245 #define ALT_USB_HOST_HCINTMSK2_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
24246 
24247 /*
24248  * Field : nakmsk
24249  *
24250  * NAK Response Received Interrupt Mask (NakMsk)
24251  *
24252  * In scatter/gather DMA mode for host,
24253  *
24254  * interrupts will not be generated due to the corresponding bits set in
24255  *
24256  * HCINTn.
24257  *
24258  * Field Access Macros:
24259  *
24260  */
24261 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_NAKMSK register field. */
24262 #define ALT_USB_HOST_HCINTMSK2_NAKMSK_LSB 4
24263 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_NAKMSK register field. */
24264 #define ALT_USB_HOST_HCINTMSK2_NAKMSK_MSB 4
24265 /* The width in bits of the ALT_USB_HOST_HCINTMSK2_NAKMSK register field. */
24266 #define ALT_USB_HOST_HCINTMSK2_NAKMSK_WIDTH 1
24267 /* The mask used to set the ALT_USB_HOST_HCINTMSK2_NAKMSK register field value. */
24268 #define ALT_USB_HOST_HCINTMSK2_NAKMSK_SET_MSK 0x00000010
24269 /* The mask used to clear the ALT_USB_HOST_HCINTMSK2_NAKMSK register field value. */
24270 #define ALT_USB_HOST_HCINTMSK2_NAKMSK_CLR_MSK 0xffffffef
24271 /* The reset value of the ALT_USB_HOST_HCINTMSK2_NAKMSK register field. */
24272 #define ALT_USB_HOST_HCINTMSK2_NAKMSK_RESET 0x0
24273 /* Extracts the ALT_USB_HOST_HCINTMSK2_NAKMSK field value from a register. */
24274 #define ALT_USB_HOST_HCINTMSK2_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
24275 /* Produces a ALT_USB_HOST_HCINTMSK2_NAKMSK register field value suitable for setting the register. */
24276 #define ALT_USB_HOST_HCINTMSK2_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
24277 
24278 /*
24279  * Field : ackmsk
24280  *
24281  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
24282  *
24283  * In scatter/gather DMA mode for host,
24284  *
24285  * interrupts will not be generated due to the corresponding bits set in
24286  *
24287  * HCINTn.
24288  *
24289  * Field Access Macros:
24290  *
24291  */
24292 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_ACKMSK register field. */
24293 #define ALT_USB_HOST_HCINTMSK2_ACKMSK_LSB 5
24294 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_ACKMSK register field. */
24295 #define ALT_USB_HOST_HCINTMSK2_ACKMSK_MSB 5
24296 /* The width in bits of the ALT_USB_HOST_HCINTMSK2_ACKMSK register field. */
24297 #define ALT_USB_HOST_HCINTMSK2_ACKMSK_WIDTH 1
24298 /* The mask used to set the ALT_USB_HOST_HCINTMSK2_ACKMSK register field value. */
24299 #define ALT_USB_HOST_HCINTMSK2_ACKMSK_SET_MSK 0x00000020
24300 /* The mask used to clear the ALT_USB_HOST_HCINTMSK2_ACKMSK register field value. */
24301 #define ALT_USB_HOST_HCINTMSK2_ACKMSK_CLR_MSK 0xffffffdf
24302 /* The reset value of the ALT_USB_HOST_HCINTMSK2_ACKMSK register field. */
24303 #define ALT_USB_HOST_HCINTMSK2_ACKMSK_RESET 0x0
24304 /* Extracts the ALT_USB_HOST_HCINTMSK2_ACKMSK field value from a register. */
24305 #define ALT_USB_HOST_HCINTMSK2_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
24306 /* Produces a ALT_USB_HOST_HCINTMSK2_ACKMSK register field value suitable for setting the register. */
24307 #define ALT_USB_HOST_HCINTMSK2_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
24308 
24309 /*
24310  * Field : nyetmsk
24311  *
24312  * NYET Response Received Interrupt Mask (NyetMsk)
24313  *
24314  * In scatter/gather DMA mode for host,
24315  *
24316  * interrupts will not be generated due to the corresponding bits set in
24317  *
24318  * HCINTn.
24319  *
24320  * Field Access Macros:
24321  *
24322  */
24323 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_NYETMSK register field. */
24324 #define ALT_USB_HOST_HCINTMSK2_NYETMSK_LSB 6
24325 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_NYETMSK register field. */
24326 #define ALT_USB_HOST_HCINTMSK2_NYETMSK_MSB 6
24327 /* The width in bits of the ALT_USB_HOST_HCINTMSK2_NYETMSK register field. */
24328 #define ALT_USB_HOST_HCINTMSK2_NYETMSK_WIDTH 1
24329 /* The mask used to set the ALT_USB_HOST_HCINTMSK2_NYETMSK register field value. */
24330 #define ALT_USB_HOST_HCINTMSK2_NYETMSK_SET_MSK 0x00000040
24331 /* The mask used to clear the ALT_USB_HOST_HCINTMSK2_NYETMSK register field value. */
24332 #define ALT_USB_HOST_HCINTMSK2_NYETMSK_CLR_MSK 0xffffffbf
24333 /* The reset value of the ALT_USB_HOST_HCINTMSK2_NYETMSK register field. */
24334 #define ALT_USB_HOST_HCINTMSK2_NYETMSK_RESET 0x0
24335 /* Extracts the ALT_USB_HOST_HCINTMSK2_NYETMSK field value from a register. */
24336 #define ALT_USB_HOST_HCINTMSK2_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
24337 /* Produces a ALT_USB_HOST_HCINTMSK2_NYETMSK register field value suitable for setting the register. */
24338 #define ALT_USB_HOST_HCINTMSK2_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
24339 
24340 /*
24341  * Field : xacterrmsk
24342  *
24343  * Transaction Error Mask (XactErrMsk)
24344  *
24345  * In scatter/gather DMA mode for host,
24346  *
24347  * interrupts will not be generated due to the corresponding bits set in
24348  *
24349  * HCINTn.
24350  *
24351  * Field Access Macros:
24352  *
24353  */
24354 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field. */
24355 #define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_LSB 7
24356 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field. */
24357 #define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_MSB 7
24358 /* The width in bits of the ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field. */
24359 #define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_WIDTH 1
24360 /* The mask used to set the ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field value. */
24361 #define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_SET_MSK 0x00000080
24362 /* The mask used to clear the ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field value. */
24363 #define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_CLR_MSK 0xffffff7f
24364 /* The reset value of the ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field. */
24365 #define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_RESET 0x0
24366 /* Extracts the ALT_USB_HOST_HCINTMSK2_XACTERRMSK field value from a register. */
24367 #define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
24368 /* Produces a ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field value suitable for setting the register. */
24369 #define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
24370 
24371 /*
24372  * Field : bblerrmsk
24373  *
24374  * Babble Error Mask (BblErrMsk)
24375  *
24376  * In scatter/gather DMA mode for host,
24377  *
24378  * interrupts will not be generated due to the corresponding bits set in
24379  *
24380  * HCINTn.
24381  *
24382  * Field Access Macros:
24383  *
24384  */
24385 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field. */
24386 #define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_LSB 8
24387 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field. */
24388 #define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_MSB 8
24389 /* The width in bits of the ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field. */
24390 #define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_WIDTH 1
24391 /* The mask used to set the ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field value. */
24392 #define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_SET_MSK 0x00000100
24393 /* The mask used to clear the ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field value. */
24394 #define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_CLR_MSK 0xfffffeff
24395 /* The reset value of the ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field. */
24396 #define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_RESET 0x0
24397 /* Extracts the ALT_USB_HOST_HCINTMSK2_BBLERRMSK field value from a register. */
24398 #define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
24399 /* Produces a ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field value suitable for setting the register. */
24400 #define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
24401 
24402 /*
24403  * Field : frmovrunmsk
24404  *
24405  * Frame Overrun Mask (FrmOvrunMsk)
24406  *
24407  * In scatter/gather DMA mode for host,
24408  *
24409  * interrupts will not be generated due to the corresponding bits set in
24410  *
24411  * HCINTn.
24412  *
24413  * Field Access Macros:
24414  *
24415  */
24416 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field. */
24417 #define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_LSB 9
24418 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field. */
24419 #define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_MSB 9
24420 /* The width in bits of the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field. */
24421 #define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_WIDTH 1
24422 /* The mask used to set the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field value. */
24423 #define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_SET_MSK 0x00000200
24424 /* The mask used to clear the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field value. */
24425 #define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_CLR_MSK 0xfffffdff
24426 /* The reset value of the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field. */
24427 #define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_RESET 0x0
24428 /* Extracts the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK field value from a register. */
24429 #define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
24430 /* Produces a ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field value suitable for setting the register. */
24431 #define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
24432 
24433 /*
24434  * Field : datatglerrmsk
24435  *
24436  * Data Toggle Error Mask (DataTglErrMsk)
24437  *
24438  * In scatter/gather DMA mode for host,
24439  *
24440  * interrupts will not be generated due to the corresponding bits set in
24441  *
24442  * HCINTn.
24443  *
24444  * Field Access Macros:
24445  *
24446  */
24447 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field. */
24448 #define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_LSB 10
24449 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field. */
24450 #define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_MSB 10
24451 /* The width in bits of the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field. */
24452 #define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_WIDTH 1
24453 /* The mask used to set the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field value. */
24454 #define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_SET_MSK 0x00000400
24455 /* The mask used to clear the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field value. */
24456 #define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_CLR_MSK 0xfffffbff
24457 /* The reset value of the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field. */
24458 #define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_RESET 0x0
24459 /* Extracts the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK field value from a register. */
24460 #define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
24461 /* Produces a ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field value suitable for setting the register. */
24462 #define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
24463 
24464 /*
24465  * Field : bnaintrmsk
24466  *
24467  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
24468  *
24469  * This bit is valid only when Scatter/Gather DMA mode is enabled.
24470  *
24471  * Field Enumeration Values:
24472  *
24473  * Enum | Value | Description
24474  * :------------------------------------------|:------|:------------
24475  * ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_MSK | 0x0 | Mask
24476  * ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_NOMSK | 0x1 | No mask
24477  *
24478  * Field Access Macros:
24479  *
24480  */
24481 /*
24482  * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_BNAINTRMSK
24483  *
24484  * Mask
24485  */
24486 #define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_MSK 0x0
24487 /*
24488  * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_BNAINTRMSK
24489  *
24490  * No mask
24491  */
24492 #define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_NOMSK 0x1
24493 
24494 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */
24495 #define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_LSB 11
24496 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */
24497 #define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_MSB 11
24498 /* The width in bits of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */
24499 #define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_WIDTH 1
24500 /* The mask used to set the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field value. */
24501 #define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_SET_MSK 0x00000800
24502 /* The mask used to clear the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field value. */
24503 #define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_CLR_MSK 0xfffff7ff
24504 /* The reset value of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */
24505 #define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_RESET 0x0
24506 /* Extracts the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK field value from a register. */
24507 #define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
24508 /* Produces a ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field value suitable for setting the register. */
24509 #define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
24510 
24511 /*
24512  * Field : frm_lst_rollintrmsk
24513  *
24514  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
24515  *
24516  * This bit is valid only when Scatter/Gather DMA mode is enabled.
24517  *
24518  * Field Enumeration Values:
24519  *
24520  * Enum | Value | Description
24521  * :---------------------------------------------------|:------|:------------
24522  * ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
24523  * ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
24524  *
24525  * Field Access Macros:
24526  *
24527  */
24528 /*
24529  * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK
24530  *
24531  * Mask
24532  */
24533 #define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_MSK 0x0
24534 /*
24535  * Enumerated value for register field ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK
24536  *
24537  * No mask
24538  */
24539 #define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
24540 
24541 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */
24542 #define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_LSB 13
24543 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */
24544 #define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_MSB 13
24545 /* The width in bits of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */
24546 #define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_WIDTH 1
24547 /* The mask used to set the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field value. */
24548 #define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
24549 /* The mask used to clear the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field value. */
24550 #define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
24551 /* The reset value of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */
24552 #define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_RESET 0x0
24553 /* Extracts the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK field value from a register. */
24554 #define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
24555 /* Produces a ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
24556 #define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
24557 
24558 #ifndef __ASSEMBLY__
24559 /*
24560  * WARNING: The C register and register group struct declarations are provided for
24561  * convenience and illustrative purposes. They should, however, be used with
24562  * caution as the C language standard provides no guarantees about the alignment or
24563  * atomicity of device memory accesses. The recommended practice for writing
24564  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24565  * alt_write_word() functions.
24566  *
24567  * The struct declaration for register ALT_USB_HOST_HCINTMSK2.
24568  */
24569 struct ALT_USB_HOST_HCINTMSK2_s
24570 {
24571  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK */
24572  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK2_CHHLTDMSK */
24573  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK2_AHBERRMSK */
24574  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK2_STALLMSK */
24575  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK2_NAKMSK */
24576  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK2_ACKMSK */
24577  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK2_NYETMSK */
24578  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK2_XACTERRMSK */
24579  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK2_BBLERRMSK */
24580  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK */
24581  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK */
24582  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK2_BNAINTRMSK */
24583  uint32_t : 1; /* *UNDEFINED* */
24584  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK */
24585  uint32_t : 18; /* *UNDEFINED* */
24586 };
24587 
24588 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK2. */
24589 typedef volatile struct ALT_USB_HOST_HCINTMSK2_s ALT_USB_HOST_HCINTMSK2_t;
24590 #endif /* __ASSEMBLY__ */
24591 
24592 /* The reset value of the ALT_USB_HOST_HCINTMSK2 register. */
24593 #define ALT_USB_HOST_HCINTMSK2_RESET 0x00000000
24594 /* The byte offset of the ALT_USB_HOST_HCINTMSK2 register from the beginning of the component. */
24595 #define ALT_USB_HOST_HCINTMSK2_OFST 0x14c
24596 /* The address of the ALT_USB_HOST_HCINTMSK2 register. */
24597 #define ALT_USB_HOST_HCINTMSK2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK2_OFST))
24598 
24599 /*
24600  * Register : hctsiz2
24601  *
24602  * Host Channel 2 Transfer Size Register
24603  *
24604  * Register Layout
24605  *
24606  * Bits | Access | Reset | Description
24607  * :--------|:-------|:------|:------------------------------
24608  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ2_XFERSIZE
24609  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ2_PKTCNT
24610  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ2_PID
24611  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ2_DOPNG
24612  *
24613  */
24614 /*
24615  * Field : xfersize
24616  *
24617  * Transfer Size (XferSize)
24618  *
24619  * For an OUT, this field is the number of data bytes the host sends
24620  *
24621  * during the transfer.
24622  *
24623  * For an IN, this field is the buffer size that the application has
24624  *
24625  * Reserved For the transfer. The application is expected to
24626  *
24627  * program this field as an integer multiple of the maximum packet
24628  *
24629  * size For IN transactions (periodic and non-periodic).
24630  *
24631  * The width of this counter is specified as Width of Transfer Size
24632  *
24633  * Counters
24634  *
24635  * Field Access Macros:
24636  *
24637  */
24638 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */
24639 #define ALT_USB_HOST_HCTSIZ2_XFERSIZE_LSB 0
24640 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */
24641 #define ALT_USB_HOST_HCTSIZ2_XFERSIZE_MSB 18
24642 /* The width in bits of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */
24643 #define ALT_USB_HOST_HCTSIZ2_XFERSIZE_WIDTH 19
24644 /* The mask used to set the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field value. */
24645 #define ALT_USB_HOST_HCTSIZ2_XFERSIZE_SET_MSK 0x0007ffff
24646 /* The mask used to clear the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field value. */
24647 #define ALT_USB_HOST_HCTSIZ2_XFERSIZE_CLR_MSK 0xfff80000
24648 /* The reset value of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */
24649 #define ALT_USB_HOST_HCTSIZ2_XFERSIZE_RESET 0x0
24650 /* Extracts the ALT_USB_HOST_HCTSIZ2_XFERSIZE field value from a register. */
24651 #define ALT_USB_HOST_HCTSIZ2_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
24652 /* Produces a ALT_USB_HOST_HCTSIZ2_XFERSIZE register field value suitable for setting the register. */
24653 #define ALT_USB_HOST_HCTSIZ2_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
24654 
24655 /*
24656  * Field : pktcnt
24657  *
24658  * Packet Count (PktCnt)
24659  *
24660  * This field is programmed by the application with the expected
24661  *
24662  * number of packets to be transmitted (OUT) or received (IN).
24663  *
24664  * The host decrements this count on every successful
24665  *
24666  * transmission or reception of an OUT/IN packet. Once this count
24667  *
24668  * reaches zero, the application is interrupted to indicate normal
24669  *
24670  * completion.
24671  *
24672  * The width of this counter is specified as Width of Packet
24673  *
24674  * Counters
24675  *
24676  * Field Access Macros:
24677  *
24678  */
24679 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */
24680 #define ALT_USB_HOST_HCTSIZ2_PKTCNT_LSB 19
24681 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */
24682 #define ALT_USB_HOST_HCTSIZ2_PKTCNT_MSB 28
24683 /* The width in bits of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */
24684 #define ALT_USB_HOST_HCTSIZ2_PKTCNT_WIDTH 10
24685 /* The mask used to set the ALT_USB_HOST_HCTSIZ2_PKTCNT register field value. */
24686 #define ALT_USB_HOST_HCTSIZ2_PKTCNT_SET_MSK 0x1ff80000
24687 /* The mask used to clear the ALT_USB_HOST_HCTSIZ2_PKTCNT register field value. */
24688 #define ALT_USB_HOST_HCTSIZ2_PKTCNT_CLR_MSK 0xe007ffff
24689 /* The reset value of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */
24690 #define ALT_USB_HOST_HCTSIZ2_PKTCNT_RESET 0x0
24691 /* Extracts the ALT_USB_HOST_HCTSIZ2_PKTCNT field value from a register. */
24692 #define ALT_USB_HOST_HCTSIZ2_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
24693 /* Produces a ALT_USB_HOST_HCTSIZ2_PKTCNT register field value suitable for setting the register. */
24694 #define ALT_USB_HOST_HCTSIZ2_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
24695 
24696 /*
24697  * Field : pid
24698  *
24699  * PID (Pid)
24700  *
24701  * The application programs this field with the type of PID to use For
24702  *
24703  * the initial transaction. The host maintains this field For the rest of
24704  *
24705  * the transfer.
24706  *
24707  * 2'b00: DATA0
24708  *
24709  * 2'b01: DATA2
24710  *
24711  * 2'b10: DATA1
24712  *
24713  * 2'b11: MDATA (non-control)/SETUP (control)
24714  *
24715  * Field Enumeration Values:
24716  *
24717  * Enum | Value | Description
24718  * :---------------------------------|:------|:------------------------------------
24719  * ALT_USB_HOST_HCTSIZ2_PID_E_DATA0 | 0x0 | DATA0
24720  * ALT_USB_HOST_HCTSIZ2_PID_E_DATA2 | 0x1 | DATA2
24721  * ALT_USB_HOST_HCTSIZ2_PID_E_DATA1 | 0x2 | DATA1
24722  * ALT_USB_HOST_HCTSIZ2_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
24723  *
24724  * Field Access Macros:
24725  *
24726  */
24727 /*
24728  * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID
24729  *
24730  * DATA0
24731  */
24732 #define ALT_USB_HOST_HCTSIZ2_PID_E_DATA0 0x0
24733 /*
24734  * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID
24735  *
24736  * DATA2
24737  */
24738 #define ALT_USB_HOST_HCTSIZ2_PID_E_DATA2 0x1
24739 /*
24740  * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID
24741  *
24742  * DATA1
24743  */
24744 #define ALT_USB_HOST_HCTSIZ2_PID_E_DATA1 0x2
24745 /*
24746  * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID
24747  *
24748  * MDATA (non-control)/SETUP (control)
24749  */
24750 #define ALT_USB_HOST_HCTSIZ2_PID_E_MDATA 0x3
24751 
24752 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_PID register field. */
24753 #define ALT_USB_HOST_HCTSIZ2_PID_LSB 29
24754 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_PID register field. */
24755 #define ALT_USB_HOST_HCTSIZ2_PID_MSB 30
24756 /* The width in bits of the ALT_USB_HOST_HCTSIZ2_PID register field. */
24757 #define ALT_USB_HOST_HCTSIZ2_PID_WIDTH 2
24758 /* The mask used to set the ALT_USB_HOST_HCTSIZ2_PID register field value. */
24759 #define ALT_USB_HOST_HCTSIZ2_PID_SET_MSK 0x60000000
24760 /* The mask used to clear the ALT_USB_HOST_HCTSIZ2_PID register field value. */
24761 #define ALT_USB_HOST_HCTSIZ2_PID_CLR_MSK 0x9fffffff
24762 /* The reset value of the ALT_USB_HOST_HCTSIZ2_PID register field. */
24763 #define ALT_USB_HOST_HCTSIZ2_PID_RESET 0x0
24764 /* Extracts the ALT_USB_HOST_HCTSIZ2_PID field value from a register. */
24765 #define ALT_USB_HOST_HCTSIZ2_PID_GET(value) (((value) & 0x60000000) >> 29)
24766 /* Produces a ALT_USB_HOST_HCTSIZ2_PID register field value suitable for setting the register. */
24767 #define ALT_USB_HOST_HCTSIZ2_PID_SET(value) (((value) << 29) & 0x60000000)
24768 
24769 /*
24770  * Field : dopng
24771  *
24772  * Do Ping (DoPng)
24773  *
24774  * This bit is used only For OUT transfers.
24775  *
24776  * Setting this field to 1 directs the host to do PING protocol.
24777  *
24778  * Note: Do not Set this bit For IN transfers. If this bit is Set For
24779  *
24780  * for IN transfers it disables the channel.
24781  *
24782  * Field Enumeration Values:
24783  *
24784  * Enum | Value | Description
24785  * :------------------------------------|:------|:-----------------
24786  * ALT_USB_HOST_HCTSIZ2_DOPNG_E_NOPING | 0x0 | No ping protocol
24787  * ALT_USB_HOST_HCTSIZ2_DOPNG_E_PING | 0x1 | Ping protocol
24788  *
24789  * Field Access Macros:
24790  *
24791  */
24792 /*
24793  * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_DOPNG
24794  *
24795  * No ping protocol
24796  */
24797 #define ALT_USB_HOST_HCTSIZ2_DOPNG_E_NOPING 0x0
24798 /*
24799  * Enumerated value for register field ALT_USB_HOST_HCTSIZ2_DOPNG
24800  *
24801  * Ping protocol
24802  */
24803 #define ALT_USB_HOST_HCTSIZ2_DOPNG_E_PING 0x1
24804 
24805 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */
24806 #define ALT_USB_HOST_HCTSIZ2_DOPNG_LSB 31
24807 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */
24808 #define ALT_USB_HOST_HCTSIZ2_DOPNG_MSB 31
24809 /* The width in bits of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */
24810 #define ALT_USB_HOST_HCTSIZ2_DOPNG_WIDTH 1
24811 /* The mask used to set the ALT_USB_HOST_HCTSIZ2_DOPNG register field value. */
24812 #define ALT_USB_HOST_HCTSIZ2_DOPNG_SET_MSK 0x80000000
24813 /* The mask used to clear the ALT_USB_HOST_HCTSIZ2_DOPNG register field value. */
24814 #define ALT_USB_HOST_HCTSIZ2_DOPNG_CLR_MSK 0x7fffffff
24815 /* The reset value of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */
24816 #define ALT_USB_HOST_HCTSIZ2_DOPNG_RESET 0x0
24817 /* Extracts the ALT_USB_HOST_HCTSIZ2_DOPNG field value from a register. */
24818 #define ALT_USB_HOST_HCTSIZ2_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
24819 /* Produces a ALT_USB_HOST_HCTSIZ2_DOPNG register field value suitable for setting the register. */
24820 #define ALT_USB_HOST_HCTSIZ2_DOPNG_SET(value) (((value) << 31) & 0x80000000)
24821 
24822 #ifndef __ASSEMBLY__
24823 /*
24824  * WARNING: The C register and register group struct declarations are provided for
24825  * convenience and illustrative purposes. They should, however, be used with
24826  * caution as the C language standard provides no guarantees about the alignment or
24827  * atomicity of device memory accesses. The recommended practice for writing
24828  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24829  * alt_write_word() functions.
24830  *
24831  * The struct declaration for register ALT_USB_HOST_HCTSIZ2.
24832  */
24833 struct ALT_USB_HOST_HCTSIZ2_s
24834 {
24835  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ2_XFERSIZE */
24836  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ2_PKTCNT */
24837  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ2_PID */
24838  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ2_DOPNG */
24839 };
24840 
24841 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ2. */
24842 typedef volatile struct ALT_USB_HOST_HCTSIZ2_s ALT_USB_HOST_HCTSIZ2_t;
24843 #endif /* __ASSEMBLY__ */
24844 
24845 /* The reset value of the ALT_USB_HOST_HCTSIZ2 register. */
24846 #define ALT_USB_HOST_HCTSIZ2_RESET 0x00000000
24847 /* The byte offset of the ALT_USB_HOST_HCTSIZ2 register from the beginning of the component. */
24848 #define ALT_USB_HOST_HCTSIZ2_OFST 0x150
24849 /* The address of the ALT_USB_HOST_HCTSIZ2 register. */
24850 #define ALT_USB_HOST_HCTSIZ2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ2_OFST))
24851 
24852 /*
24853  * Register : hcdma2
24854  *
24855  * Host Channel 2 DMA Address Register
24856  *
24857  * Register Layout
24858  *
24859  * Bits | Access | Reset | Description
24860  * :-------|:-------|:------|:---------------------------
24861  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA2_HCDMA2
24862  *
24863  */
24864 /*
24865  * Field : hcdma2
24866  *
24867  * Buffer DMA Mode:
24868  *
24869  * [31:0] DMA Address (DMAAddr)
24870  *
24871  * This field holds the start address in the external memory from which the data
24872  * for
24873  *
24874  * the endpoint must be fetched or to which it must be stored. This register is
24875  *
24876  * incremented on every AHB transaction.
24877  *
24878  * Scatter-Gather DMA (DescDMA) Mode:
24879  *
24880  * [31:9] (Non Isoc) Non-Isochronous:
24881  *
24882  * [31:N] (Isoc) Isochronous:
24883  *
24884  * This field holds the start address of the 512 bytes
24885  *
24886  * page. The first descriptor in the list should be located
24887  *
24888  * in this address. The first descriptor may be or may
24889  *
24890  * not be ready. The core starts processing the list from
24891  *
24892  * the CTD value.
24893  *
24894  * This field holds the address of the 2*(nTD+1) bytes of
24895  *
24896  * locations in which the isochronous descriptors are
24897  *
24898  * present where N is based on nTD as per Table below
24899  *
24900  * [31:N] Base Address
24901  *
24902  * [N-1:3] Offset
24903  *
24904  * [2:0] 000
24905  *
24906  * HS ISOC
24907  *
24908  * nTD N
24909  *
24910  * 7 6
24911  *
24912  * 15 7
24913  *
24914  * 31 8
24915  *
24916  * 63 9
24917  *
24918  * 127 10
24919  *
24920  * 255 11
24921  *
24922  * FS ISOC
24923  *
24924  * nTD N
24925  *
24926  * 1 4
24927  *
24928  * 3 5
24929  *
24930  * 7 6
24931  *
24932  * 15 7
24933  *
24934  * 31 8
24935  *
24936  * 63 9
24937  *
24938  * [N-1:3] (Isoc):
24939  *
24940  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
24941  *
24942  * Non Isochronous:
24943  *
24944  * This value is in terms of number of descriptors. The values can be from 0 to 63.
24945  *
24946  * 0 - 1 descriptor.
24947  *
24948  * 63 - 64 descriptors.
24949  *
24950  * This field indicates the current descriptor processed in the list. This field is
24951  * updated
24952  *
24953  * both by application and the core. For example, if the application enables the
24954  *
24955  * channel after programming CTD=5, then the core will start processing the 6th
24956  *
24957  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
24958  *
24959  * to DMAAddr.
24960  *
24961  * Isochronous:
24962  *
24963  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
24964  * set
24965  *
24966  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
24967  *
24968  * [31:9] (Non Isoc) Non-Isochronous:
24969  *
24970  * [31:N] (Isoc) Isochronous:
24971  *
24972  * This field holds the start address of the 512 bytes
24973  *
24974  * page. The first descriptor in the list should be located
24975  *
24976  * in this address. The first descriptor may be or may
24977  *
24978  * not be ready. The core starts processing the list from
24979  *
24980  * the CTD value.
24981  *
24982  * This field holds the address of the 2*(nTD+1) bytes of
24983  *
24984  * locations in which the isochronous descriptors are
24985  *
24986  * present where N is based on nTD as per Table below
24987  *
24988  * [31:N] Base Address
24989  *
24990  * [N-1:3] Offset
24991  *
24992  * [2:0] 000
24993  *
24994  * HS ISOC
24995  *
24996  * nTD N
24997  *
24998  * 7 6
24999  *
25000  * 15 7
25001  *
25002  * 31 8
25003  *
25004  * 63 9
25005  *
25006  * 127 10
25007  *
25008  * 255 11
25009  *
25010  * FS ISOC
25011  *
25012  * nTD N
25013  *
25014  * 1 4
25015  *
25016  * 3 5
25017  *
25018  * 7 6
25019  *
25020  * 15 7
25021  *
25022  * 31 8
25023  *
25024  * 63 9
25025  *
25026  * [N-1:3] (Isoc):
25027  *
25028  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
25029  *
25030  * Non Isochronous:
25031  *
25032  * This value is in terms of number of descriptors. The values can be from 0 to 63.
25033  *
25034  * 0 - 1 descriptor.
25035  *
25036  * 63 - 64 descriptors.
25037  *
25038  * This field indicates the current descriptor processed in the list. This field is
25039  * updated
25040  *
25041  * both by application and the core. For example, if the application enables the
25042  *
25043  * channel after programming CTD=5, then the core will start processing the 6th
25044  *
25045  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
25046  *
25047  * to DMAAddr.
25048  *
25049  * Isochronous:
25050  *
25051  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
25052  * set
25053  *
25054  * to zero by application.
25055  *
25056  * Field Access Macros:
25057  *
25058  */
25059 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */
25060 #define ALT_USB_HOST_HCDMA2_HCDMA2_LSB 0
25061 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */
25062 #define ALT_USB_HOST_HCDMA2_HCDMA2_MSB 31
25063 /* The width in bits of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */
25064 #define ALT_USB_HOST_HCDMA2_HCDMA2_WIDTH 32
25065 /* The mask used to set the ALT_USB_HOST_HCDMA2_HCDMA2 register field value. */
25066 #define ALT_USB_HOST_HCDMA2_HCDMA2_SET_MSK 0xffffffff
25067 /* The mask used to clear the ALT_USB_HOST_HCDMA2_HCDMA2 register field value. */
25068 #define ALT_USB_HOST_HCDMA2_HCDMA2_CLR_MSK 0x00000000
25069 /* The reset value of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */
25070 #define ALT_USB_HOST_HCDMA2_HCDMA2_RESET 0x0
25071 /* Extracts the ALT_USB_HOST_HCDMA2_HCDMA2 field value from a register. */
25072 #define ALT_USB_HOST_HCDMA2_HCDMA2_GET(value) (((value) & 0xffffffff) >> 0)
25073 /* Produces a ALT_USB_HOST_HCDMA2_HCDMA2 register field value suitable for setting the register. */
25074 #define ALT_USB_HOST_HCDMA2_HCDMA2_SET(value) (((value) << 0) & 0xffffffff)
25075 
25076 #ifndef __ASSEMBLY__
25077 /*
25078  * WARNING: The C register and register group struct declarations are provided for
25079  * convenience and illustrative purposes. They should, however, be used with
25080  * caution as the C language standard provides no guarantees about the alignment or
25081  * atomicity of device memory accesses. The recommended practice for writing
25082  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
25083  * alt_write_word() functions.
25084  *
25085  * The struct declaration for register ALT_USB_HOST_HCDMA2.
25086  */
25087 struct ALT_USB_HOST_HCDMA2_s
25088 {
25089  uint32_t hcdma2 : 32; /* ALT_USB_HOST_HCDMA2_HCDMA2 */
25090 };
25091 
25092 /* The typedef declaration for register ALT_USB_HOST_HCDMA2. */
25093 typedef volatile struct ALT_USB_HOST_HCDMA2_s ALT_USB_HOST_HCDMA2_t;
25094 #endif /* __ASSEMBLY__ */
25095 
25096 /* The reset value of the ALT_USB_HOST_HCDMA2 register. */
25097 #define ALT_USB_HOST_HCDMA2_RESET 0x00000000
25098 /* The byte offset of the ALT_USB_HOST_HCDMA2 register from the beginning of the component. */
25099 #define ALT_USB_HOST_HCDMA2_OFST 0x154
25100 /* The address of the ALT_USB_HOST_HCDMA2 register. */
25101 #define ALT_USB_HOST_HCDMA2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA2_OFST))
25102 
25103 /*
25104  * Register : hcdmab2
25105  *
25106  * Host Channel 2 DMA Buffer Address Register
25107  *
25108  * Register Layout
25109  *
25110  * Bits | Access | Reset | Description
25111  * :-------|:-------|:------|:-----------------------------
25112  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB2_HCDMAB2
25113  *
25114  */
25115 /*
25116  * Field : hcdmab2
25117  *
25118  * Holds the current buffer address.
25119  *
25120  * This register is updated as and when the data transfer for the corresponding end
25121  * point
25122  *
25123  * is in progress. This register is present only in Scatter/Gather DMA mode.
25124  * Otherwise this
25125  *
25126  * field is reserved.
25127  *
25128  * Field Access Macros:
25129  *
25130  */
25131 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */
25132 #define ALT_USB_HOST_HCDMAB2_HCDMAB2_LSB 0
25133 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */
25134 #define ALT_USB_HOST_HCDMAB2_HCDMAB2_MSB 31
25135 /* The width in bits of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */
25136 #define ALT_USB_HOST_HCDMAB2_HCDMAB2_WIDTH 32
25137 /* The mask used to set the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field value. */
25138 #define ALT_USB_HOST_HCDMAB2_HCDMAB2_SET_MSK 0xffffffff
25139 /* The mask used to clear the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field value. */
25140 #define ALT_USB_HOST_HCDMAB2_HCDMAB2_CLR_MSK 0x00000000
25141 /* The reset value of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */
25142 #define ALT_USB_HOST_HCDMAB2_HCDMAB2_RESET 0x0
25143 /* Extracts the ALT_USB_HOST_HCDMAB2_HCDMAB2 field value from a register. */
25144 #define ALT_USB_HOST_HCDMAB2_HCDMAB2_GET(value) (((value) & 0xffffffff) >> 0)
25145 /* Produces a ALT_USB_HOST_HCDMAB2_HCDMAB2 register field value suitable for setting the register. */
25146 #define ALT_USB_HOST_HCDMAB2_HCDMAB2_SET(value) (((value) << 0) & 0xffffffff)
25147 
25148 #ifndef __ASSEMBLY__
25149 /*
25150  * WARNING: The C register and register group struct declarations are provided for
25151  * convenience and illustrative purposes. They should, however, be used with
25152  * caution as the C language standard provides no guarantees about the alignment or
25153  * atomicity of device memory accesses. The recommended practice for writing
25154  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
25155  * alt_write_word() functions.
25156  *
25157  * The struct declaration for register ALT_USB_HOST_HCDMAB2.
25158  */
25159 struct ALT_USB_HOST_HCDMAB2_s
25160 {
25161  uint32_t hcdmab2 : 32; /* ALT_USB_HOST_HCDMAB2_HCDMAB2 */
25162 };
25163 
25164 /* The typedef declaration for register ALT_USB_HOST_HCDMAB2. */
25165 typedef volatile struct ALT_USB_HOST_HCDMAB2_s ALT_USB_HOST_HCDMAB2_t;
25166 #endif /* __ASSEMBLY__ */
25167 
25168 /* The reset value of the ALT_USB_HOST_HCDMAB2 register. */
25169 #define ALT_USB_HOST_HCDMAB2_RESET 0x00000000
25170 /* The byte offset of the ALT_USB_HOST_HCDMAB2 register from the beginning of the component. */
25171 #define ALT_USB_HOST_HCDMAB2_OFST 0x15c
25172 /* The address of the ALT_USB_HOST_HCDMAB2 register. */
25173 #define ALT_USB_HOST_HCDMAB2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB2_OFST))
25174 
25175 /*
25176  * Register : hcchar3
25177  *
25178  * Host Channel 3 Characteristics Register
25179  *
25180  * Register Layout
25181  *
25182  * Bits | Access | Reset | Description
25183  * :--------|:---------|:------|:-----------------------------
25184  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_MPS
25185  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_EPNUM
25186  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_EPDIR
25187  * [16] | ??? | 0x0 | *UNDEFINED*
25188  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_LSPDDEV
25189  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_EPTYPE
25190  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_EC
25191  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_DEVADDR
25192  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_ODDFRM
25193  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR3_CHDIS
25194  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR3_CHENA
25195  *
25196  */
25197 /*
25198  * Field : mps
25199  *
25200  * Maximum Packet Size (MPS)
25201  *
25202  * Indicates the maximum packet size of the associated endpoint.
25203  *
25204  * Field Access Macros:
25205  *
25206  */
25207 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_MPS register field. */
25208 #define ALT_USB_HOST_HCCHAR3_MPS_LSB 0
25209 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_MPS register field. */
25210 #define ALT_USB_HOST_HCCHAR3_MPS_MSB 10
25211 /* The width in bits of the ALT_USB_HOST_HCCHAR3_MPS register field. */
25212 #define ALT_USB_HOST_HCCHAR3_MPS_WIDTH 11
25213 /* The mask used to set the ALT_USB_HOST_HCCHAR3_MPS register field value. */
25214 #define ALT_USB_HOST_HCCHAR3_MPS_SET_MSK 0x000007ff
25215 /* The mask used to clear the ALT_USB_HOST_HCCHAR3_MPS register field value. */
25216 #define ALT_USB_HOST_HCCHAR3_MPS_CLR_MSK 0xfffff800
25217 /* The reset value of the ALT_USB_HOST_HCCHAR3_MPS register field. */
25218 #define ALT_USB_HOST_HCCHAR3_MPS_RESET 0x0
25219 /* Extracts the ALT_USB_HOST_HCCHAR3_MPS field value from a register. */
25220 #define ALT_USB_HOST_HCCHAR3_MPS_GET(value) (((value) & 0x000007ff) >> 0)
25221 /* Produces a ALT_USB_HOST_HCCHAR3_MPS register field value suitable for setting the register. */
25222 #define ALT_USB_HOST_HCCHAR3_MPS_SET(value) (((value) << 0) & 0x000007ff)
25223 
25224 /*
25225  * Field : epnum
25226  *
25227  * Endpoint Number (EPNum)
25228  *
25229  * Indicates the endpoint number on the device serving as the data
25230  *
25231  * source or sink.
25232  *
25233  * Field Enumeration Values:
25234  *
25235  * Enum | Value | Description
25236  * :-------------------------------------|:------|:--------------
25237  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT0 | 0x0 | End point 0
25238  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT1 | 0x1 | End point 1
25239  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT2 | 0x2 | End point 2
25240  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT3 | 0x3 | End point 3
25241  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT4 | 0x4 | End point 4
25242  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT5 | 0x5 | End point 5
25243  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT6 | 0x6 | End point 6
25244  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT7 | 0x7 | End point 7
25245  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT8 | 0x8 | End point 8
25246  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT9 | 0x9 | End point 9
25247  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT10 | 0xa | End point 10
25248  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT11 | 0xb | End point 11
25249  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT12 | 0xc | End point 12
25250  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT13 | 0xd | End point 13
25251  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT14 | 0xe | End point 14
25252  * ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT15 | 0xf | End point 15
25253  *
25254  * Field Access Macros:
25255  *
25256  */
25257 /*
25258  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25259  *
25260  * End point 0
25261  */
25262 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT0 0x0
25263 /*
25264  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25265  *
25266  * End point 1
25267  */
25268 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT1 0x1
25269 /*
25270  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25271  *
25272  * End point 2
25273  */
25274 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT2 0x2
25275 /*
25276  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25277  *
25278  * End point 3
25279  */
25280 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT3 0x3
25281 /*
25282  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25283  *
25284  * End point 4
25285  */
25286 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT4 0x4
25287 /*
25288  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25289  *
25290  * End point 5
25291  */
25292 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT5 0x5
25293 /*
25294  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25295  *
25296  * End point 6
25297  */
25298 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT6 0x6
25299 /*
25300  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25301  *
25302  * End point 7
25303  */
25304 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT7 0x7
25305 /*
25306  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25307  *
25308  * End point 8
25309  */
25310 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT8 0x8
25311 /*
25312  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25313  *
25314  * End point 9
25315  */
25316 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT9 0x9
25317 /*
25318  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25319  *
25320  * End point 10
25321  */
25322 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT10 0xa
25323 /*
25324  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25325  *
25326  * End point 11
25327  */
25328 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT11 0xb
25329 /*
25330  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25331  *
25332  * End point 12
25333  */
25334 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT12 0xc
25335 /*
25336  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25337  *
25338  * End point 13
25339  */
25340 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT13 0xd
25341 /*
25342  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25343  *
25344  * End point 14
25345  */
25346 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT14 0xe
25347 /*
25348  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
25349  *
25350  * End point 15
25351  */
25352 #define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT15 0xf
25353 
25354 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */
25355 #define ALT_USB_HOST_HCCHAR3_EPNUM_LSB 11
25356 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */
25357 #define ALT_USB_HOST_HCCHAR3_EPNUM_MSB 14
25358 /* The width in bits of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */
25359 #define ALT_USB_HOST_HCCHAR3_EPNUM_WIDTH 4
25360 /* The mask used to set the ALT_USB_HOST_HCCHAR3_EPNUM register field value. */
25361 #define ALT_USB_HOST_HCCHAR3_EPNUM_SET_MSK 0x00007800
25362 /* The mask used to clear the ALT_USB_HOST_HCCHAR3_EPNUM register field value. */
25363 #define ALT_USB_HOST_HCCHAR3_EPNUM_CLR_MSK 0xffff87ff
25364 /* The reset value of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */
25365 #define ALT_USB_HOST_HCCHAR3_EPNUM_RESET 0x0
25366 /* Extracts the ALT_USB_HOST_HCCHAR3_EPNUM field value from a register. */
25367 #define ALT_USB_HOST_HCCHAR3_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
25368 /* Produces a ALT_USB_HOST_HCCHAR3_EPNUM register field value suitable for setting the register. */
25369 #define ALT_USB_HOST_HCCHAR3_EPNUM_SET(value) (((value) << 11) & 0x00007800)
25370 
25371 /*
25372  * Field : epdir
25373  *
25374  * Endpoint Direction (EPDir)
25375  *
25376  * Indicates whether the transaction is IN or OUT.
25377  *
25378  * 1'b0: OUT
25379  *
25380  * 1'b1: IN
25381  *
25382  * Field Enumeration Values:
25383  *
25384  * Enum | Value | Description
25385  * :------------------------------------|:------|:------------
25386  * ALT_USB_HOST_HCCHAR3_EPDIR_E_OUTDIR | 0x0 | OUT
25387  * ALT_USB_HOST_HCCHAR3_EPDIR_E_INDIR | 0x1 | IN
25388  *
25389  * Field Access Macros:
25390  *
25391  */
25392 /*
25393  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPDIR
25394  *
25395  * OUT
25396  */
25397 #define ALT_USB_HOST_HCCHAR3_EPDIR_E_OUTDIR 0x0
25398 /*
25399  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPDIR
25400  *
25401  * IN
25402  */
25403 #define ALT_USB_HOST_HCCHAR3_EPDIR_E_INDIR 0x1
25404 
25405 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */
25406 #define ALT_USB_HOST_HCCHAR3_EPDIR_LSB 15
25407 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */
25408 #define ALT_USB_HOST_HCCHAR3_EPDIR_MSB 15
25409 /* The width in bits of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */
25410 #define ALT_USB_HOST_HCCHAR3_EPDIR_WIDTH 1
25411 /* The mask used to set the ALT_USB_HOST_HCCHAR3_EPDIR register field value. */
25412 #define ALT_USB_HOST_HCCHAR3_EPDIR_SET_MSK 0x00008000
25413 /* The mask used to clear the ALT_USB_HOST_HCCHAR3_EPDIR register field value. */
25414 #define ALT_USB_HOST_HCCHAR3_EPDIR_CLR_MSK 0xffff7fff
25415 /* The reset value of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */
25416 #define ALT_USB_HOST_HCCHAR3_EPDIR_RESET 0x0
25417 /* Extracts the ALT_USB_HOST_HCCHAR3_EPDIR field value from a register. */
25418 #define ALT_USB_HOST_HCCHAR3_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
25419 /* Produces a ALT_USB_HOST_HCCHAR3_EPDIR register field value suitable for setting the register. */
25420 #define ALT_USB_HOST_HCCHAR3_EPDIR_SET(value) (((value) << 15) & 0x00008000)
25421 
25422 /*
25423  * Field : lspddev
25424  *
25425  * Low-Speed Device (LSpdDev)
25426  *
25427  * This field is Set by the application to indicate that this channel is
25428  *
25429  * communicating to a low-speed device.
25430  *
25431  * Field Enumeration Values:
25432  *
25433  * Enum | Value | Description
25434  * :-------------------------------------------|:------|:--------------------------------
25435  * ALT_USB_HOST_HCCHAR3_LSPDDEV_E_NONLOWSPEED | 0x0 | Communicating with non lowspeed
25436  * ALT_USB_HOST_HCCHAR3_LSPDDEV_E_LOWSPEED | 0x1 | Communicating with lowspeed
25437  *
25438  * Field Access Macros:
25439  *
25440  */
25441 /*
25442  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_LSPDDEV
25443  *
25444  * Communicating with non lowspeed
25445  */
25446 #define ALT_USB_HOST_HCCHAR3_LSPDDEV_E_NONLOWSPEED 0x0
25447 /*
25448  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_LSPDDEV
25449  *
25450  * Communicating with lowspeed
25451  */
25452 #define ALT_USB_HOST_HCCHAR3_LSPDDEV_E_LOWSPEED 0x1
25453 
25454 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */
25455 #define ALT_USB_HOST_HCCHAR3_LSPDDEV_LSB 17
25456 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */
25457 #define ALT_USB_HOST_HCCHAR3_LSPDDEV_MSB 17
25458 /* The width in bits of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */
25459 #define ALT_USB_HOST_HCCHAR3_LSPDDEV_WIDTH 1
25460 /* The mask used to set the ALT_USB_HOST_HCCHAR3_LSPDDEV register field value. */
25461 #define ALT_USB_HOST_HCCHAR3_LSPDDEV_SET_MSK 0x00020000
25462 /* The mask used to clear the ALT_USB_HOST_HCCHAR3_LSPDDEV register field value. */
25463 #define ALT_USB_HOST_HCCHAR3_LSPDDEV_CLR_MSK 0xfffdffff
25464 /* The reset value of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */
25465 #define ALT_USB_HOST_HCCHAR3_LSPDDEV_RESET 0x0
25466 /* Extracts the ALT_USB_HOST_HCCHAR3_LSPDDEV field value from a register. */
25467 #define ALT_USB_HOST_HCCHAR3_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
25468 /* Produces a ALT_USB_HOST_HCCHAR3_LSPDDEV register field value suitable for setting the register. */
25469 #define ALT_USB_HOST_HCCHAR3_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
25470 
25471 /*
25472  * Field : eptype
25473  *
25474  * Endpoint Type (EPType)
25475  *
25476  * Indicates the transfer type selected.
25477  *
25478  * 2'b00: Control
25479  *
25480  * 2'b01: Isochronous
25481  *
25482  * 2'b10: Bulk
25483  *
25484  * 2'b11: Interrupt
25485  *
25486  * Field Enumeration Values:
25487  *
25488  * Enum | Value | Description
25489  * :-------------------------------------|:------|:------------
25490  * ALT_USB_HOST_HCCHAR3_EPTYPE_E_CTL | 0x0 | Control
25491  * ALT_USB_HOST_HCCHAR3_EPTYPE_E_ISOC | 0x1 | Isochronous
25492  * ALT_USB_HOST_HCCHAR3_EPTYPE_E_BULK | 0x2 | Bulk
25493  * ALT_USB_HOST_HCCHAR3_EPTYPE_E_INTERR | 0x3 | Interrupt
25494  *
25495  * Field Access Macros:
25496  *
25497  */
25498 /*
25499  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE
25500  *
25501  * Control
25502  */
25503 #define ALT_USB_HOST_HCCHAR3_EPTYPE_E_CTL 0x0
25504 /*
25505  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE
25506  *
25507  * Isochronous
25508  */
25509 #define ALT_USB_HOST_HCCHAR3_EPTYPE_E_ISOC 0x1
25510 /*
25511  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE
25512  *
25513  * Bulk
25514  */
25515 #define ALT_USB_HOST_HCCHAR3_EPTYPE_E_BULK 0x2
25516 /*
25517  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE
25518  *
25519  * Interrupt
25520  */
25521 #define ALT_USB_HOST_HCCHAR3_EPTYPE_E_INTERR 0x3
25522 
25523 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */
25524 #define ALT_USB_HOST_HCCHAR3_EPTYPE_LSB 18
25525 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */
25526 #define ALT_USB_HOST_HCCHAR3_EPTYPE_MSB 19
25527 /* The width in bits of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */
25528 #define ALT_USB_HOST_HCCHAR3_EPTYPE_WIDTH 2
25529 /* The mask used to set the ALT_USB_HOST_HCCHAR3_EPTYPE register field value. */
25530 #define ALT_USB_HOST_HCCHAR3_EPTYPE_SET_MSK 0x000c0000
25531 /* The mask used to clear the ALT_USB_HOST_HCCHAR3_EPTYPE register field value. */
25532 #define ALT_USB_HOST_HCCHAR3_EPTYPE_CLR_MSK 0xfff3ffff
25533 /* The reset value of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */
25534 #define ALT_USB_HOST_HCCHAR3_EPTYPE_RESET 0x0
25535 /* Extracts the ALT_USB_HOST_HCCHAR3_EPTYPE field value from a register. */
25536 #define ALT_USB_HOST_HCCHAR3_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
25537 /* Produces a ALT_USB_HOST_HCCHAR3_EPTYPE register field value suitable for setting the register. */
25538 #define ALT_USB_HOST_HCCHAR3_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
25539 
25540 /*
25541  * Field : ec
25542  *
25543  * Multi Count (MC) / Error Count (EC)
25544  *
25545  * When the Split Enable bit of the Host Channel-n Split Control
25546  *
25547  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
25548  *
25549  * the host the number of transactions that must be executed per
25550  *
25551  * microframe For this periodic endpoint. For non periodic transfers,
25552  *
25553  * this field is used only in DMA mode, and specifies the number
25554  *
25555  * packets to be fetched For this channel before the internal DMA
25556  *
25557  * engine changes arbitration.
25558  *
25559  * 2'b00: Reserved This field yields undefined results.
25560  *
25561  * 2'b01: 1 transaction
25562  *
25563  * 2'b10: 2 transactions to be issued For this endpoint per
25564  *
25565  * microframe
25566  *
25567  * 2'b11: 3 transactions to be issued For this endpoint per
25568  *
25569  * microframe
25570  *
25571  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
25572  *
25573  * number of immediate retries to be performed For a periodic split
25574  *
25575  * transactions on transaction errors. This field must be Set to at
25576  *
25577  * least 2'b01.
25578  *
25579  * Field Enumeration Values:
25580  *
25581  * Enum | Value | Description
25582  * :-------------------------------------|:------|:----------------------------------------------
25583  * ALT_USB_HOST_HCCHAR3_EC_E_RSVD | 0x0 | Reserved This field yields undefined results
25584  * ALT_USB_HOST_HCCHAR3_EC_E_TRANSONE | 0x1 | 1 transaction
25585  * ALT_USB_HOST_HCCHAR3_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
25586  * : | | per microframe
25587  * ALT_USB_HOST_HCCHAR3_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
25588  * : | | per microframe
25589  *
25590  * Field Access Macros:
25591  *
25592  */
25593 /*
25594  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC
25595  *
25596  * Reserved This field yields undefined results
25597  */
25598 #define ALT_USB_HOST_HCCHAR3_EC_E_RSVD 0x0
25599 /*
25600  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC
25601  *
25602  * 1 transaction
25603  */
25604 #define ALT_USB_HOST_HCCHAR3_EC_E_TRANSONE 0x1
25605 /*
25606  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC
25607  *
25608  * 2 transactions to be issued for this endpoint per microframe
25609  */
25610 #define ALT_USB_HOST_HCCHAR3_EC_E_TRANSTWO 0x2
25611 /*
25612  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC
25613  *
25614  * 3 transactions to be issued for this endpoint per microframe
25615  */
25616 #define ALT_USB_HOST_HCCHAR3_EC_E_TRANSTHREE 0x3
25617 
25618 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EC register field. */
25619 #define ALT_USB_HOST_HCCHAR3_EC_LSB 20
25620 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EC register field. */
25621 #define ALT_USB_HOST_HCCHAR3_EC_MSB 21
25622 /* The width in bits of the ALT_USB_HOST_HCCHAR3_EC register field. */
25623 #define ALT_USB_HOST_HCCHAR3_EC_WIDTH 2
25624 /* The mask used to set the ALT_USB_HOST_HCCHAR3_EC register field value. */
25625 #define ALT_USB_HOST_HCCHAR3_EC_SET_MSK 0x00300000
25626 /* The mask used to clear the ALT_USB_HOST_HCCHAR3_EC register field value. */
25627 #define ALT_USB_HOST_HCCHAR3_EC_CLR_MSK 0xffcfffff
25628 /* The reset value of the ALT_USB_HOST_HCCHAR3_EC register field. */
25629 #define ALT_USB_HOST_HCCHAR3_EC_RESET 0x0
25630 /* Extracts the ALT_USB_HOST_HCCHAR3_EC field value from a register. */
25631 #define ALT_USB_HOST_HCCHAR3_EC_GET(value) (((value) & 0x00300000) >> 20)
25632 /* Produces a ALT_USB_HOST_HCCHAR3_EC register field value suitable for setting the register. */
25633 #define ALT_USB_HOST_HCCHAR3_EC_SET(value) (((value) << 20) & 0x00300000)
25634 
25635 /*
25636  * Field : devaddr
25637  *
25638  * Device Address (DevAddr)
25639  *
25640  * This field selects the specific device serving as the data source
25641  *
25642  * or sink.
25643  *
25644  * Field Access Macros:
25645  *
25646  */
25647 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */
25648 #define ALT_USB_HOST_HCCHAR3_DEVADDR_LSB 22
25649 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */
25650 #define ALT_USB_HOST_HCCHAR3_DEVADDR_MSB 28
25651 /* The width in bits of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */
25652 #define ALT_USB_HOST_HCCHAR3_DEVADDR_WIDTH 7
25653 /* The mask used to set the ALT_USB_HOST_HCCHAR3_DEVADDR register field value. */
25654 #define ALT_USB_HOST_HCCHAR3_DEVADDR_SET_MSK 0x1fc00000
25655 /* The mask used to clear the ALT_USB_HOST_HCCHAR3_DEVADDR register field value. */
25656 #define ALT_USB_HOST_HCCHAR3_DEVADDR_CLR_MSK 0xe03fffff
25657 /* The reset value of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */
25658 #define ALT_USB_HOST_HCCHAR3_DEVADDR_RESET 0x0
25659 /* Extracts the ALT_USB_HOST_HCCHAR3_DEVADDR field value from a register. */
25660 #define ALT_USB_HOST_HCCHAR3_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
25661 /* Produces a ALT_USB_HOST_HCCHAR3_DEVADDR register field value suitable for setting the register. */
25662 #define ALT_USB_HOST_HCCHAR3_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
25663 
25664 /*
25665  * Field : oddfrm
25666  *
25667  * Odd Frame (OddFrm)
25668  *
25669  * This field is set (reset) by the application to indicate that the OTG host must
25670  * perform
25671  *
25672  * a transfer in an odd (micro)frame. This field is applicable for only periodic
25673  *
25674  * (isochronous and interrupt) transactions.
25675  *
25676  * 1'b0: Even (micro)frame
25677  *
25678  * 1'b1: Odd (micro)frame
25679  *
25680  * Field Access Macros:
25681  *
25682  */
25683 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_ODDFRM register field. */
25684 #define ALT_USB_HOST_HCCHAR3_ODDFRM_LSB 29
25685 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_ODDFRM register field. */
25686 #define ALT_USB_HOST_HCCHAR3_ODDFRM_MSB 29
25687 /* The width in bits of the ALT_USB_HOST_HCCHAR3_ODDFRM register field. */
25688 #define ALT_USB_HOST_HCCHAR3_ODDFRM_WIDTH 1
25689 /* The mask used to set the ALT_USB_HOST_HCCHAR3_ODDFRM register field value. */
25690 #define ALT_USB_HOST_HCCHAR3_ODDFRM_SET_MSK 0x20000000
25691 /* The mask used to clear the ALT_USB_HOST_HCCHAR3_ODDFRM register field value. */
25692 #define ALT_USB_HOST_HCCHAR3_ODDFRM_CLR_MSK 0xdfffffff
25693 /* The reset value of the ALT_USB_HOST_HCCHAR3_ODDFRM register field. */
25694 #define ALT_USB_HOST_HCCHAR3_ODDFRM_RESET 0x0
25695 /* Extracts the ALT_USB_HOST_HCCHAR3_ODDFRM field value from a register. */
25696 #define ALT_USB_HOST_HCCHAR3_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
25697 /* Produces a ALT_USB_HOST_HCCHAR3_ODDFRM register field value suitable for setting the register. */
25698 #define ALT_USB_HOST_HCCHAR3_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
25699 
25700 /*
25701  * Field : chdis
25702  *
25703  * Channel Disable (ChDis)
25704  *
25705  * The application sets this bit to stop transmitting/receiving data
25706  *
25707  * on a channel, even before the transfer For that channel is
25708  *
25709  * complete. The application must wait For the Channel Disabled
25710  *
25711  * interrupt before treating the channel as disabled.
25712  *
25713  * Field Enumeration Values:
25714  *
25715  * Enum | Value | Description
25716  * :-----------------------------------|:------|:---------------------------------
25717  * ALT_USB_HOST_HCCHAR3_CHDIS_E_INACT | 0x0 | No activity
25718  * ALT_USB_HOST_HCCHAR3_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving data
25719  *
25720  * Field Access Macros:
25721  *
25722  */
25723 /*
25724  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHDIS
25725  *
25726  * No activity
25727  */
25728 #define ALT_USB_HOST_HCCHAR3_CHDIS_E_INACT 0x0
25729 /*
25730  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHDIS
25731  *
25732  * Stop transmitting/receiving data
25733  */
25734 #define ALT_USB_HOST_HCCHAR3_CHDIS_E_ACT 0x1
25735 
25736 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */
25737 #define ALT_USB_HOST_HCCHAR3_CHDIS_LSB 30
25738 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */
25739 #define ALT_USB_HOST_HCCHAR3_CHDIS_MSB 30
25740 /* The width in bits of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */
25741 #define ALT_USB_HOST_HCCHAR3_CHDIS_WIDTH 1
25742 /* The mask used to set the ALT_USB_HOST_HCCHAR3_CHDIS register field value. */
25743 #define ALT_USB_HOST_HCCHAR3_CHDIS_SET_MSK 0x40000000
25744 /* The mask used to clear the ALT_USB_HOST_HCCHAR3_CHDIS register field value. */
25745 #define ALT_USB_HOST_HCCHAR3_CHDIS_CLR_MSK 0xbfffffff
25746 /* The reset value of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */
25747 #define ALT_USB_HOST_HCCHAR3_CHDIS_RESET 0x0
25748 /* Extracts the ALT_USB_HOST_HCCHAR3_CHDIS field value from a register. */
25749 #define ALT_USB_HOST_HCCHAR3_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
25750 /* Produces a ALT_USB_HOST_HCCHAR3_CHDIS register field value suitable for setting the register. */
25751 #define ALT_USB_HOST_HCCHAR3_CHDIS_SET(value) (((value) << 30) & 0x40000000)
25752 
25753 /*
25754  * Field : chena
25755  *
25756  * Channel Enable (ChEna)
25757  *
25758  * When Scatter/Gather mode is enabled
25759  *
25760  * 1'b0: Indicates that the descriptor structure is not yet ready.
25761  *
25762  * 1'b1: Indicates that the descriptor structure and data buffer with
25763  *
25764  * data is setup and this channel can access the descriptor.
25765  *
25766  * When Scatter/Gather mode is disabled
25767  *
25768  * This field is set by the application and cleared by the OTG host.
25769  *
25770  * 1'b0: Channel disabled
25771  *
25772  * 1'b1: Channel enabled
25773  *
25774  * Field Enumeration Values:
25775  *
25776  * Enum | Value | Description
25777  * :------------------------------------|:------|:-------------------------------------------------
25778  * ALT_USB_HOST_HCCHAR3_CHENA_E_NOTRDY | 0x0 | Indicates that the descriptor structure is not
25779  * : | | yet ready
25780  * ALT_USB_HOST_HCCHAR3_CHENA_E_RDY | 0x1 | Indicates that the descriptor structure and data
25781  * : | | buffer with data is setup and this channel can
25782  * : | | access the descriptor
25783  *
25784  * Field Access Macros:
25785  *
25786  */
25787 /*
25788  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHENA
25789  *
25790  * Indicates that the descriptor structure is not yet ready
25791  */
25792 #define ALT_USB_HOST_HCCHAR3_CHENA_E_NOTRDY 0x0
25793 /*
25794  * Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHENA
25795  *
25796  * Indicates that the descriptor structure and data buffer with data is setup and
25797  * this channel can access the descriptor
25798  */
25799 #define ALT_USB_HOST_HCCHAR3_CHENA_E_RDY 0x1
25800 
25801 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_CHENA register field. */
25802 #define ALT_USB_HOST_HCCHAR3_CHENA_LSB 31
25803 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_CHENA register field. */
25804 #define ALT_USB_HOST_HCCHAR3_CHENA_MSB 31
25805 /* The width in bits of the ALT_USB_HOST_HCCHAR3_CHENA register field. */
25806 #define ALT_USB_HOST_HCCHAR3_CHENA_WIDTH 1
25807 /* The mask used to set the ALT_USB_HOST_HCCHAR3_CHENA register field value. */
25808 #define ALT_USB_HOST_HCCHAR3_CHENA_SET_MSK 0x80000000
25809 /* The mask used to clear the ALT_USB_HOST_HCCHAR3_CHENA register field value. */
25810 #define ALT_USB_HOST_HCCHAR3_CHENA_CLR_MSK 0x7fffffff
25811 /* The reset value of the ALT_USB_HOST_HCCHAR3_CHENA register field. */
25812 #define ALT_USB_HOST_HCCHAR3_CHENA_RESET 0x0
25813 /* Extracts the ALT_USB_HOST_HCCHAR3_CHENA field value from a register. */
25814 #define ALT_USB_HOST_HCCHAR3_CHENA_GET(value) (((value) & 0x80000000) >> 31)
25815 /* Produces a ALT_USB_HOST_HCCHAR3_CHENA register field value suitable for setting the register. */
25816 #define ALT_USB_HOST_HCCHAR3_CHENA_SET(value) (((value) << 31) & 0x80000000)
25817 
25818 #ifndef __ASSEMBLY__
25819 /*
25820  * WARNING: The C register and register group struct declarations are provided for
25821  * convenience and illustrative purposes. They should, however, be used with
25822  * caution as the C language standard provides no guarantees about the alignment or
25823  * atomicity of device memory accesses. The recommended practice for writing
25824  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
25825  * alt_write_word() functions.
25826  *
25827  * The struct declaration for register ALT_USB_HOST_HCCHAR3.
25828  */
25829 struct ALT_USB_HOST_HCCHAR3_s
25830 {
25831  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR3_MPS */
25832  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR3_EPNUM */
25833  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR3_EPDIR */
25834  uint32_t : 1; /* *UNDEFINED* */
25835  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR3_LSPDDEV */
25836  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR3_EPTYPE */
25837  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR3_EC */
25838  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR3_DEVADDR */
25839  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR3_ODDFRM */
25840  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR3_CHDIS */
25841  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR3_CHENA */
25842 };
25843 
25844 /* The typedef declaration for register ALT_USB_HOST_HCCHAR3. */
25845 typedef volatile struct ALT_USB_HOST_HCCHAR3_s ALT_USB_HOST_HCCHAR3_t;
25846 #endif /* __ASSEMBLY__ */
25847 
25848 /* The reset value of the ALT_USB_HOST_HCCHAR3 register. */
25849 #define ALT_USB_HOST_HCCHAR3_RESET 0x00000000
25850 /* The byte offset of the ALT_USB_HOST_HCCHAR3 register from the beginning of the component. */
25851 #define ALT_USB_HOST_HCCHAR3_OFST 0x160
25852 /* The address of the ALT_USB_HOST_HCCHAR3 register. */
25853 #define ALT_USB_HOST_HCCHAR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR3_OFST))
25854 
25855 /*
25856  * Register : hcsplt3
25857  *
25858  * Host Channel 3 Split Control Register
25859  *
25860  * Register Layout
25861  *
25862  * Bits | Access | Reset | Description
25863  * :--------|:-------|:------|:------------------------------
25864  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT3_PRTADDR
25865  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT3_HUBADDR
25866  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT3_XACTPOS
25867  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT3_COMPSPLT
25868  * [30:17] | ??? | 0x0 | *UNDEFINED*
25869  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT3_SPLTENA
25870  *
25871  */
25872 /*
25873  * Field : prtaddr
25874  *
25875  * Port Address (PrtAddr)
25876  *
25877  * This field is the port number of the recipient transaction
25878  *
25879  * translator.
25880  *
25881  * Field Access Macros:
25882  *
25883  */
25884 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */
25885 #define ALT_USB_HOST_HCSPLT3_PRTADDR_LSB 0
25886 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */
25887 #define ALT_USB_HOST_HCSPLT3_PRTADDR_MSB 6
25888 /* The width in bits of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */
25889 #define ALT_USB_HOST_HCSPLT3_PRTADDR_WIDTH 7
25890 /* The mask used to set the ALT_USB_HOST_HCSPLT3_PRTADDR register field value. */
25891 #define ALT_USB_HOST_HCSPLT3_PRTADDR_SET_MSK 0x0000007f
25892 /* The mask used to clear the ALT_USB_HOST_HCSPLT3_PRTADDR register field value. */
25893 #define ALT_USB_HOST_HCSPLT3_PRTADDR_CLR_MSK 0xffffff80
25894 /* The reset value of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */
25895 #define ALT_USB_HOST_HCSPLT3_PRTADDR_RESET 0x0
25896 /* Extracts the ALT_USB_HOST_HCSPLT3_PRTADDR field value from a register. */
25897 #define ALT_USB_HOST_HCSPLT3_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
25898 /* Produces a ALT_USB_HOST_HCSPLT3_PRTADDR register field value suitable for setting the register. */
25899 #define ALT_USB_HOST_HCSPLT3_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
25900 
25901 /*
25902  * Field : hubaddr
25903  *
25904  * Hub Address (HubAddr)
25905  *
25906  * This field holds the device address of the transaction translator's
25907  *
25908  * hub.
25909  *
25910  * Field Access Macros:
25911  *
25912  */
25913 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */
25914 #define ALT_USB_HOST_HCSPLT3_HUBADDR_LSB 7
25915 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */
25916 #define ALT_USB_HOST_HCSPLT3_HUBADDR_MSB 13
25917 /* The width in bits of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */
25918 #define ALT_USB_HOST_HCSPLT3_HUBADDR_WIDTH 7
25919 /* The mask used to set the ALT_USB_HOST_HCSPLT3_HUBADDR register field value. */
25920 #define ALT_USB_HOST_HCSPLT3_HUBADDR_SET_MSK 0x00003f80
25921 /* The mask used to clear the ALT_USB_HOST_HCSPLT3_HUBADDR register field value. */
25922 #define ALT_USB_HOST_HCSPLT3_HUBADDR_CLR_MSK 0xffffc07f
25923 /* The reset value of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */
25924 #define ALT_USB_HOST_HCSPLT3_HUBADDR_RESET 0x0
25925 /* Extracts the ALT_USB_HOST_HCSPLT3_HUBADDR field value from a register. */
25926 #define ALT_USB_HOST_HCSPLT3_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
25927 /* Produces a ALT_USB_HOST_HCSPLT3_HUBADDR register field value suitable for setting the register. */
25928 #define ALT_USB_HOST_HCSPLT3_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
25929 
25930 /*
25931  * Field : xactpos
25932  *
25933  * Transaction Position (XactPos)
25934  *
25935  * This field is used to determine whether to send all, first, middle,
25936  *
25937  * or last payloads with each OUT transaction.
25938  *
25939  * 2'b11: All. This is the entire data payload is of this transaction
25940  *
25941  * (which is less than or equal to 188 bytes).
25942  *
25943  * 2'b10: Begin. This is the first data payload of this transaction
25944  *
25945  * (which is larger than 188 bytes).
25946  *
25947  * 2'b00: Mid. This is the middle payload of this transaction
25948  *
25949  * (which is larger than 188 bytes).
25950  *
25951  * 2'b01: End. This is the last payload of this transaction (which
25952  *
25953  * is larger than 188 bytes).
25954  *
25955  * Field Enumeration Values:
25956  *
25957  * Enum | Value | Description
25958  * :--------------------------------------|:------|:------------------------------------------------
25959  * ALT_USB_HOST_HCSPLT3_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
25960  * : | | transaction (which is larger than 188 bytes)
25961  * ALT_USB_HOST_HCSPLT3_XACTPOS_E_END | 0x1 | End. This is the last payload of this
25962  * : | | transaction (which is larger than 188 bytes)
25963  * ALT_USB_HOST_HCSPLT3_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
25964  * : | | transaction (which is larger than 188 bytes)
25965  * ALT_USB_HOST_HCSPLT3_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
25966  * : | | transaction (which is less than or equal to 188
25967  * : | | bytes)
25968  *
25969  * Field Access Macros:
25970  *
25971  */
25972 /*
25973  * Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS
25974  *
25975  * Mid. This is the middle payload of this transaction (which is larger than 188
25976  * bytes)
25977  */
25978 #define ALT_USB_HOST_HCSPLT3_XACTPOS_E_MIDDLE 0x0
25979 /*
25980  * Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS
25981  *
25982  * End. This is the last payload of this transaction (which is larger than 188
25983  * bytes)
25984  */
25985 #define ALT_USB_HOST_HCSPLT3_XACTPOS_E_END 0x1
25986 /*
25987  * Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS
25988  *
25989  * Begin. This is the first data payload of this transaction (which is larger than
25990  * 188 bytes)
25991  */
25992 #define ALT_USB_HOST_HCSPLT3_XACTPOS_E_BEGIN 0x2
25993 /*
25994  * Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS
25995  *
25996  * All. This is the entire data payload is of this transaction (which is less than
25997  * or equal to 188 bytes)
25998  */
25999 #define ALT_USB_HOST_HCSPLT3_XACTPOS_E_ALL 0x3
26000 
26001 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */
26002 #define ALT_USB_HOST_HCSPLT3_XACTPOS_LSB 14
26003 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */
26004 #define ALT_USB_HOST_HCSPLT3_XACTPOS_MSB 15
26005 /* The width in bits of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */
26006 #define ALT_USB_HOST_HCSPLT3_XACTPOS_WIDTH 2
26007 /* The mask used to set the ALT_USB_HOST_HCSPLT3_XACTPOS register field value. */
26008 #define ALT_USB_HOST_HCSPLT3_XACTPOS_SET_MSK 0x0000c000
26009 /* The mask used to clear the ALT_USB_HOST_HCSPLT3_XACTPOS register field value. */
26010 #define ALT_USB_HOST_HCSPLT3_XACTPOS_CLR_MSK 0xffff3fff
26011 /* The reset value of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */
26012 #define ALT_USB_HOST_HCSPLT3_XACTPOS_RESET 0x0
26013 /* Extracts the ALT_USB_HOST_HCSPLT3_XACTPOS field value from a register. */
26014 #define ALT_USB_HOST_HCSPLT3_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
26015 /* Produces a ALT_USB_HOST_HCSPLT3_XACTPOS register field value suitable for setting the register. */
26016 #define ALT_USB_HOST_HCSPLT3_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
26017 
26018 /*
26019  * Field : compsplt
26020  *
26021  * Do Complete Split (CompSplt)
26022  *
26023  * The application sets this field to request the OTG host to perform
26024  *
26025  * a complete split transaction.
26026  *
26027  * Field Enumeration Values:
26028  *
26029  * Enum | Value | Description
26030  * :----------------------------------------|:------|:---------------------
26031  * ALT_USB_HOST_HCSPLT3_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
26032  * ALT_USB_HOST_HCSPLT3_COMPSPLT_E_SPLIT | 0x1 | Split transaction
26033  *
26034  * Field Access Macros:
26035  *
26036  */
26037 /*
26038  * Enumerated value for register field ALT_USB_HOST_HCSPLT3_COMPSPLT
26039  *
26040  * No split transaction
26041  */
26042 #define ALT_USB_HOST_HCSPLT3_COMPSPLT_E_NOSPLIT 0x0
26043 /*
26044  * Enumerated value for register field ALT_USB_HOST_HCSPLT3_COMPSPLT
26045  *
26046  * Split transaction
26047  */
26048 #define ALT_USB_HOST_HCSPLT3_COMPSPLT_E_SPLIT 0x1
26049 
26050 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */
26051 #define ALT_USB_HOST_HCSPLT3_COMPSPLT_LSB 16
26052 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */
26053 #define ALT_USB_HOST_HCSPLT3_COMPSPLT_MSB 16
26054 /* The width in bits of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */
26055 #define ALT_USB_HOST_HCSPLT3_COMPSPLT_WIDTH 1
26056 /* The mask used to set the ALT_USB_HOST_HCSPLT3_COMPSPLT register field value. */
26057 #define ALT_USB_HOST_HCSPLT3_COMPSPLT_SET_MSK 0x00010000
26058 /* The mask used to clear the ALT_USB_HOST_HCSPLT3_COMPSPLT register field value. */
26059 #define ALT_USB_HOST_HCSPLT3_COMPSPLT_CLR_MSK 0xfffeffff
26060 /* The reset value of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */
26061 #define ALT_USB_HOST_HCSPLT3_COMPSPLT_RESET 0x0
26062 /* Extracts the ALT_USB_HOST_HCSPLT3_COMPSPLT field value from a register. */
26063 #define ALT_USB_HOST_HCSPLT3_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
26064 /* Produces a ALT_USB_HOST_HCSPLT3_COMPSPLT register field value suitable for setting the register. */
26065 #define ALT_USB_HOST_HCSPLT3_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
26066 
26067 /*
26068  * Field : spltena
26069  *
26070  * Split Enable (SpltEna)
26071  *
26072  * The application sets this field to indicate that this channel is
26073  *
26074  * enabled to perform split transactions.
26075  *
26076  * Field Enumeration Values:
26077  *
26078  * Enum | Value | Description
26079  * :------------------------------------|:------|:------------------
26080  * ALT_USB_HOST_HCSPLT3_SPLTENA_E_DISD | 0x0 | Split not enabled
26081  * ALT_USB_HOST_HCSPLT3_SPLTENA_E_END | 0x1 | Split enabled
26082  *
26083  * Field Access Macros:
26084  *
26085  */
26086 /*
26087  * Enumerated value for register field ALT_USB_HOST_HCSPLT3_SPLTENA
26088  *
26089  * Split not enabled
26090  */
26091 #define ALT_USB_HOST_HCSPLT3_SPLTENA_E_DISD 0x0
26092 /*
26093  * Enumerated value for register field ALT_USB_HOST_HCSPLT3_SPLTENA
26094  *
26095  * Split enabled
26096  */
26097 #define ALT_USB_HOST_HCSPLT3_SPLTENA_E_END 0x1
26098 
26099 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */
26100 #define ALT_USB_HOST_HCSPLT3_SPLTENA_LSB 31
26101 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */
26102 #define ALT_USB_HOST_HCSPLT3_SPLTENA_MSB 31
26103 /* The width in bits of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */
26104 #define ALT_USB_HOST_HCSPLT3_SPLTENA_WIDTH 1
26105 /* The mask used to set the ALT_USB_HOST_HCSPLT3_SPLTENA register field value. */
26106 #define ALT_USB_HOST_HCSPLT3_SPLTENA_SET_MSK 0x80000000
26107 /* The mask used to clear the ALT_USB_HOST_HCSPLT3_SPLTENA register field value. */
26108 #define ALT_USB_HOST_HCSPLT3_SPLTENA_CLR_MSK 0x7fffffff
26109 /* The reset value of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */
26110 #define ALT_USB_HOST_HCSPLT3_SPLTENA_RESET 0x0
26111 /* Extracts the ALT_USB_HOST_HCSPLT3_SPLTENA field value from a register. */
26112 #define ALT_USB_HOST_HCSPLT3_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
26113 /* Produces a ALT_USB_HOST_HCSPLT3_SPLTENA register field value suitable for setting the register. */
26114 #define ALT_USB_HOST_HCSPLT3_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
26115 
26116 #ifndef __ASSEMBLY__
26117 /*
26118  * WARNING: The C register and register group struct declarations are provided for
26119  * convenience and illustrative purposes. They should, however, be used with
26120  * caution as the C language standard provides no guarantees about the alignment or
26121  * atomicity of device memory accesses. The recommended practice for writing
26122  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26123  * alt_write_word() functions.
26124  *
26125  * The struct declaration for register ALT_USB_HOST_HCSPLT3.
26126  */
26127 struct ALT_USB_HOST_HCSPLT3_s
26128 {
26129  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT3_PRTADDR */
26130  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT3_HUBADDR */
26131  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT3_XACTPOS */
26132  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT3_COMPSPLT */
26133  uint32_t : 14; /* *UNDEFINED* */
26134  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT3_SPLTENA */
26135 };
26136 
26137 /* The typedef declaration for register ALT_USB_HOST_HCSPLT3. */
26138 typedef volatile struct ALT_USB_HOST_HCSPLT3_s ALT_USB_HOST_HCSPLT3_t;
26139 #endif /* __ASSEMBLY__ */
26140 
26141 /* The reset value of the ALT_USB_HOST_HCSPLT3 register. */
26142 #define ALT_USB_HOST_HCSPLT3_RESET 0x00000000
26143 /* The byte offset of the ALT_USB_HOST_HCSPLT3 register from the beginning of the component. */
26144 #define ALT_USB_HOST_HCSPLT3_OFST 0x164
26145 /* The address of the ALT_USB_HOST_HCSPLT3 register. */
26146 #define ALT_USB_HOST_HCSPLT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT3_OFST))
26147 
26148 /*
26149  * Register : hcint3
26150  *
26151  * Host Channel 3 Interrupt Register
26152  *
26153  * Register Layout
26154  *
26155  * Bits | Access | Reset | Description
26156  * :--------|:-------|:------|:--------------------------------------
26157  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT3_XFERCOMPL
26158  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT3_CHHLTD
26159  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT3_AHBERR
26160  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT3_STALL
26161  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT3_NAK
26162  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT3_ACK
26163  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT3_NYET
26164  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT3_XACTERR
26165  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT3_BBLERR
26166  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT3_FRMOVRUN
26167  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT3_DATATGLERR
26168  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT3_BNAINTR
26169  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT3_XCS_XACT_ERR
26170  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR
26171  * [31:14] | ??? | 0x0 | *UNDEFINED*
26172  *
26173  */
26174 /*
26175  * Field : xfercompl
26176  *
26177  * Transfer Completed (XferCompl)
26178  *
26179  * Transfer completed normally without any errors.This bit can be set only by the
26180  * core and the application should write 1 to clear it.
26181  *
26182  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
26183  *
26184  * completed with IOC bit set in its descriptor.
26185  *
26186  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
26187  * without
26188  *
26189  * any errors.
26190  *
26191  * Field Enumeration Values:
26192  *
26193  * Enum | Value | Description
26194  * :--------------------------------------|:------|:-----------------------------------------------
26195  * ALT_USB_HOST_HCINT3_XFERCOMPL_E_INACT | 0x0 | No transfer
26196  * ALT_USB_HOST_HCINT3_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
26197  *
26198  * Field Access Macros:
26199  *
26200  */
26201 /*
26202  * Enumerated value for register field ALT_USB_HOST_HCINT3_XFERCOMPL
26203  *
26204  * No transfer
26205  */
26206 #define ALT_USB_HOST_HCINT3_XFERCOMPL_E_INACT 0x0
26207 /*
26208  * Enumerated value for register field ALT_USB_HOST_HCINT3_XFERCOMPL
26209  *
26210  * Transfer completed normally without any errors
26211  */
26212 #define ALT_USB_HOST_HCINT3_XFERCOMPL_E_ACT 0x1
26213 
26214 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */
26215 #define ALT_USB_HOST_HCINT3_XFERCOMPL_LSB 0
26216 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */
26217 #define ALT_USB_HOST_HCINT3_XFERCOMPL_MSB 0
26218 /* The width in bits of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */
26219 #define ALT_USB_HOST_HCINT3_XFERCOMPL_WIDTH 1
26220 /* The mask used to set the ALT_USB_HOST_HCINT3_XFERCOMPL register field value. */
26221 #define ALT_USB_HOST_HCINT3_XFERCOMPL_SET_MSK 0x00000001
26222 /* The mask used to clear the ALT_USB_HOST_HCINT3_XFERCOMPL register field value. */
26223 #define ALT_USB_HOST_HCINT3_XFERCOMPL_CLR_MSK 0xfffffffe
26224 /* The reset value of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */
26225 #define ALT_USB_HOST_HCINT3_XFERCOMPL_RESET 0x0
26226 /* Extracts the ALT_USB_HOST_HCINT3_XFERCOMPL field value from a register. */
26227 #define ALT_USB_HOST_HCINT3_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
26228 /* Produces a ALT_USB_HOST_HCINT3_XFERCOMPL register field value suitable for setting the register. */
26229 #define ALT_USB_HOST_HCINT3_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
26230 
26231 /*
26232  * Field : chhltd
26233  *
26234  * Channel Halted (ChHltd)
26235  *
26236  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
26237  * either because of any USB transaction error or in response to disable request by
26238  * the application or because of a completed transfer.
26239  *
26240  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
26241  * the following
26242  *
26243  * . EOL being set in descriptor
26244  *
26245  * . AHB error
26246  *
26247  * . Excessive transaction errors
26248  *
26249  * . Babble
26250  *
26251  * . Stall
26252  *
26253  * Field Enumeration Values:
26254  *
26255  * Enum | Value | Description
26256  * :-----------------------------------|:------|:-------------------
26257  * ALT_USB_HOST_HCINT3_CHHLTD_E_INACT | 0x0 | Channel not halted
26258  * ALT_USB_HOST_HCINT3_CHHLTD_E_ACT | 0x1 | Channel Halted
26259  *
26260  * Field Access Macros:
26261  *
26262  */
26263 /*
26264  * Enumerated value for register field ALT_USB_HOST_HCINT3_CHHLTD
26265  *
26266  * Channel not halted
26267  */
26268 #define ALT_USB_HOST_HCINT3_CHHLTD_E_INACT 0x0
26269 /*
26270  * Enumerated value for register field ALT_USB_HOST_HCINT3_CHHLTD
26271  *
26272  * Channel Halted
26273  */
26274 #define ALT_USB_HOST_HCINT3_CHHLTD_E_ACT 0x1
26275 
26276 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_CHHLTD register field. */
26277 #define ALT_USB_HOST_HCINT3_CHHLTD_LSB 1
26278 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_CHHLTD register field. */
26279 #define ALT_USB_HOST_HCINT3_CHHLTD_MSB 1
26280 /* The width in bits of the ALT_USB_HOST_HCINT3_CHHLTD register field. */
26281 #define ALT_USB_HOST_HCINT3_CHHLTD_WIDTH 1
26282 /* The mask used to set the ALT_USB_HOST_HCINT3_CHHLTD register field value. */
26283 #define ALT_USB_HOST_HCINT3_CHHLTD_SET_MSK 0x00000002
26284 /* The mask used to clear the ALT_USB_HOST_HCINT3_CHHLTD register field value. */
26285 #define ALT_USB_HOST_HCINT3_CHHLTD_CLR_MSK 0xfffffffd
26286 /* The reset value of the ALT_USB_HOST_HCINT3_CHHLTD register field. */
26287 #define ALT_USB_HOST_HCINT3_CHHLTD_RESET 0x0
26288 /* Extracts the ALT_USB_HOST_HCINT3_CHHLTD field value from a register. */
26289 #define ALT_USB_HOST_HCINT3_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
26290 /* Produces a ALT_USB_HOST_HCINT3_CHHLTD register field value suitable for setting the register. */
26291 #define ALT_USB_HOST_HCINT3_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
26292 
26293 /*
26294  * Field : ahberr
26295  *
26296  * AHB Error (AHBErr)
26297  *
26298  * This is generated only in Internal DMA mode when there is an
26299  *
26300  * AHB error during AHB read/write. The application can read the
26301  *
26302  * corresponding channel's DMA address register to get the error
26303  *
26304  * address.
26305  *
26306  * Field Enumeration Values:
26307  *
26308  * Enum | Value | Description
26309  * :-----------------------------------|:------|:--------------------------------
26310  * ALT_USB_HOST_HCINT3_AHBERR_E_INACT | 0x0 | No AHB error
26311  * ALT_USB_HOST_HCINT3_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
26312  *
26313  * Field Access Macros:
26314  *
26315  */
26316 /*
26317  * Enumerated value for register field ALT_USB_HOST_HCINT3_AHBERR
26318  *
26319  * No AHB error
26320  */
26321 #define ALT_USB_HOST_HCINT3_AHBERR_E_INACT 0x0
26322 /*
26323  * Enumerated value for register field ALT_USB_HOST_HCINT3_AHBERR
26324  *
26325  * AHB error during AHB read/write
26326  */
26327 #define ALT_USB_HOST_HCINT3_AHBERR_E_ACT 0x1
26328 
26329 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_AHBERR register field. */
26330 #define ALT_USB_HOST_HCINT3_AHBERR_LSB 2
26331 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_AHBERR register field. */
26332 #define ALT_USB_HOST_HCINT3_AHBERR_MSB 2
26333 /* The width in bits of the ALT_USB_HOST_HCINT3_AHBERR register field. */
26334 #define ALT_USB_HOST_HCINT3_AHBERR_WIDTH 1
26335 /* The mask used to set the ALT_USB_HOST_HCINT3_AHBERR register field value. */
26336 #define ALT_USB_HOST_HCINT3_AHBERR_SET_MSK 0x00000004
26337 /* The mask used to clear the ALT_USB_HOST_HCINT3_AHBERR register field value. */
26338 #define ALT_USB_HOST_HCINT3_AHBERR_CLR_MSK 0xfffffffb
26339 /* The reset value of the ALT_USB_HOST_HCINT3_AHBERR register field. */
26340 #define ALT_USB_HOST_HCINT3_AHBERR_RESET 0x0
26341 /* Extracts the ALT_USB_HOST_HCINT3_AHBERR field value from a register. */
26342 #define ALT_USB_HOST_HCINT3_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
26343 /* Produces a ALT_USB_HOST_HCINT3_AHBERR register field value suitable for setting the register. */
26344 #define ALT_USB_HOST_HCINT3_AHBERR_SET(value) (((value) << 2) & 0x00000004)
26345 
26346 /*
26347  * Field : stall
26348  *
26349  * STALL Response Received Interrupt (STALL)
26350  *
26351  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
26352  *
26353  * in the core.This bit can be set only by the core and the application should
26354  * write 1 to clear
26355  *
26356  * it.
26357  *
26358  * Field Enumeration Values:
26359  *
26360  * Enum | Value | Description
26361  * :----------------------------------|:------|:-------------------
26362  * ALT_USB_HOST_HCINT3_STALL_E_INACT | 0x0 | No Stall Interrupt
26363  * ALT_USB_HOST_HCINT3_STALL_E_ACT | 0x1 | Stall Interrupt
26364  *
26365  * Field Access Macros:
26366  *
26367  */
26368 /*
26369  * Enumerated value for register field ALT_USB_HOST_HCINT3_STALL
26370  *
26371  * No Stall Interrupt
26372  */
26373 #define ALT_USB_HOST_HCINT3_STALL_E_INACT 0x0
26374 /*
26375  * Enumerated value for register field ALT_USB_HOST_HCINT3_STALL
26376  *
26377  * Stall Interrupt
26378  */
26379 #define ALT_USB_HOST_HCINT3_STALL_E_ACT 0x1
26380 
26381 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_STALL register field. */
26382 #define ALT_USB_HOST_HCINT3_STALL_LSB 3
26383 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_STALL register field. */
26384 #define ALT_USB_HOST_HCINT3_STALL_MSB 3
26385 /* The width in bits of the ALT_USB_HOST_HCINT3_STALL register field. */
26386 #define ALT_USB_HOST_HCINT3_STALL_WIDTH 1
26387 /* The mask used to set the ALT_USB_HOST_HCINT3_STALL register field value. */
26388 #define ALT_USB_HOST_HCINT3_STALL_SET_MSK 0x00000008
26389 /* The mask used to clear the ALT_USB_HOST_HCINT3_STALL register field value. */
26390 #define ALT_USB_HOST_HCINT3_STALL_CLR_MSK 0xfffffff7
26391 /* The reset value of the ALT_USB_HOST_HCINT3_STALL register field. */
26392 #define ALT_USB_HOST_HCINT3_STALL_RESET 0x0
26393 /* Extracts the ALT_USB_HOST_HCINT3_STALL field value from a register. */
26394 #define ALT_USB_HOST_HCINT3_STALL_GET(value) (((value) & 0x00000008) >> 3)
26395 /* Produces a ALT_USB_HOST_HCINT3_STALL register field value suitable for setting the register. */
26396 #define ALT_USB_HOST_HCINT3_STALL_SET(value) (((value) << 3) & 0x00000008)
26397 
26398 /*
26399  * Field : nak
26400  *
26401  * NAK Response Received Interrupt (NAK)
26402  *
26403  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
26404  *
26405  * in the core.This bit can be set only by the core and the application should
26406  * write 1 to clear
26407  *
26408  * it.
26409  *
26410  * Field Enumeration Values:
26411  *
26412  * Enum | Value | Description
26413  * :--------------------------------|:------|:-----------------------------------
26414  * ALT_USB_HOST_HCINT3_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
26415  * ALT_USB_HOST_HCINT3_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
26416  *
26417  * Field Access Macros:
26418  *
26419  */
26420 /*
26421  * Enumerated value for register field ALT_USB_HOST_HCINT3_NAK
26422  *
26423  * No NAK Response Received Interrupt
26424  */
26425 #define ALT_USB_HOST_HCINT3_NAK_E_INACT 0x0
26426 /*
26427  * Enumerated value for register field ALT_USB_HOST_HCINT3_NAK
26428  *
26429  * NAK Response Received Interrupt
26430  */
26431 #define ALT_USB_HOST_HCINT3_NAK_E_ACT 0x1
26432 
26433 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_NAK register field. */
26434 #define ALT_USB_HOST_HCINT3_NAK_LSB 4
26435 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_NAK register field. */
26436 #define ALT_USB_HOST_HCINT3_NAK_MSB 4
26437 /* The width in bits of the ALT_USB_HOST_HCINT3_NAK register field. */
26438 #define ALT_USB_HOST_HCINT3_NAK_WIDTH 1
26439 /* The mask used to set the ALT_USB_HOST_HCINT3_NAK register field value. */
26440 #define ALT_USB_HOST_HCINT3_NAK_SET_MSK 0x00000010
26441 /* The mask used to clear the ALT_USB_HOST_HCINT3_NAK register field value. */
26442 #define ALT_USB_HOST_HCINT3_NAK_CLR_MSK 0xffffffef
26443 /* The reset value of the ALT_USB_HOST_HCINT3_NAK register field. */
26444 #define ALT_USB_HOST_HCINT3_NAK_RESET 0x0
26445 /* Extracts the ALT_USB_HOST_HCINT3_NAK field value from a register. */
26446 #define ALT_USB_HOST_HCINT3_NAK_GET(value) (((value) & 0x00000010) >> 4)
26447 /* Produces a ALT_USB_HOST_HCINT3_NAK register field value suitable for setting the register. */
26448 #define ALT_USB_HOST_HCINT3_NAK_SET(value) (((value) << 4) & 0x00000010)
26449 
26450 /*
26451  * Field : ack
26452  *
26453  * ACK Response Received/Transmitted Interrupt (ACK)
26454  *
26455  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
26456  *
26457  * in the core.This bit can be set only by the core and the application should
26458  * write 1 to clear
26459  *
26460  * it.
26461  *
26462  * Field Enumeration Values:
26463  *
26464  * Enum | Value | Description
26465  * :--------------------------------|:------|:-----------------------------------------------
26466  * ALT_USB_HOST_HCINT3_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
26467  * ALT_USB_HOST_HCINT3_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
26468  *
26469  * Field Access Macros:
26470  *
26471  */
26472 /*
26473  * Enumerated value for register field ALT_USB_HOST_HCINT3_ACK
26474  *
26475  * No ACK Response Received Transmitted Interrupt
26476  */
26477 #define ALT_USB_HOST_HCINT3_ACK_E_INACT 0x0
26478 /*
26479  * Enumerated value for register field ALT_USB_HOST_HCINT3_ACK
26480  *
26481  * ACK Response Received Transmitted Interrup
26482  */
26483 #define ALT_USB_HOST_HCINT3_ACK_E_ACT 0x1
26484 
26485 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_ACK register field. */
26486 #define ALT_USB_HOST_HCINT3_ACK_LSB 5
26487 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_ACK register field. */
26488 #define ALT_USB_HOST_HCINT3_ACK_MSB 5
26489 /* The width in bits of the ALT_USB_HOST_HCINT3_ACK register field. */
26490 #define ALT_USB_HOST_HCINT3_ACK_WIDTH 1
26491 /* The mask used to set the ALT_USB_HOST_HCINT3_ACK register field value. */
26492 #define ALT_USB_HOST_HCINT3_ACK_SET_MSK 0x00000020
26493 /* The mask used to clear the ALT_USB_HOST_HCINT3_ACK register field value. */
26494 #define ALT_USB_HOST_HCINT3_ACK_CLR_MSK 0xffffffdf
26495 /* The reset value of the ALT_USB_HOST_HCINT3_ACK register field. */
26496 #define ALT_USB_HOST_HCINT3_ACK_RESET 0x0
26497 /* Extracts the ALT_USB_HOST_HCINT3_ACK field value from a register. */
26498 #define ALT_USB_HOST_HCINT3_ACK_GET(value) (((value) & 0x00000020) >> 5)
26499 /* Produces a ALT_USB_HOST_HCINT3_ACK register field value suitable for setting the register. */
26500 #define ALT_USB_HOST_HCINT3_ACK_SET(value) (((value) << 5) & 0x00000020)
26501 
26502 /*
26503  * Field : nyet
26504  *
26505  * NYET Response Received Interrupt (NYET)
26506  *
26507  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
26508  *
26509  * in the core.This bit can be set only by the core and the application should
26510  * write 1 to clear
26511  *
26512  * it.
26513  *
26514  * Field Enumeration Values:
26515  *
26516  * Enum | Value | Description
26517  * :---------------------------------|:------|:------------------------------------
26518  * ALT_USB_HOST_HCINT3_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
26519  * ALT_USB_HOST_HCINT3_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
26520  *
26521  * Field Access Macros:
26522  *
26523  */
26524 /*
26525  * Enumerated value for register field ALT_USB_HOST_HCINT3_NYET
26526  *
26527  * No NYET Response Received Interrupt
26528  */
26529 #define ALT_USB_HOST_HCINT3_NYET_E_INACT 0x0
26530 /*
26531  * Enumerated value for register field ALT_USB_HOST_HCINT3_NYET
26532  *
26533  * NYET Response Received Interrupt
26534  */
26535 #define ALT_USB_HOST_HCINT3_NYET_E_ACT 0x1
26536 
26537 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_NYET register field. */
26538 #define ALT_USB_HOST_HCINT3_NYET_LSB 6
26539 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_NYET register field. */
26540 #define ALT_USB_HOST_HCINT3_NYET_MSB 6
26541 /* The width in bits of the ALT_USB_HOST_HCINT3_NYET register field. */
26542 #define ALT_USB_HOST_HCINT3_NYET_WIDTH 1
26543 /* The mask used to set the ALT_USB_HOST_HCINT3_NYET register field value. */
26544 #define ALT_USB_HOST_HCINT3_NYET_SET_MSK 0x00000040
26545 /* The mask used to clear the ALT_USB_HOST_HCINT3_NYET register field value. */
26546 #define ALT_USB_HOST_HCINT3_NYET_CLR_MSK 0xffffffbf
26547 /* The reset value of the ALT_USB_HOST_HCINT3_NYET register field. */
26548 #define ALT_USB_HOST_HCINT3_NYET_RESET 0x0
26549 /* Extracts the ALT_USB_HOST_HCINT3_NYET field value from a register. */
26550 #define ALT_USB_HOST_HCINT3_NYET_GET(value) (((value) & 0x00000040) >> 6)
26551 /* Produces a ALT_USB_HOST_HCINT3_NYET register field value suitable for setting the register. */
26552 #define ALT_USB_HOST_HCINT3_NYET_SET(value) (((value) << 6) & 0x00000040)
26553 
26554 /*
26555  * Field : xacterr
26556  *
26557  * Transaction Error (XactErr)
26558  *
26559  * Indicates one of the following errors occurred on the USB.
26560  *
26561  * CRC check failure
26562  *
26563  * Timeout
26564  *
26565  * Bit stuff error
26566  *
26567  * False EOP
26568  *
26569  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
26570  *
26571  * in the core.This bit can be set only by the core and the application should
26572  * write 1 to clear
26573  *
26574  * it.
26575  *
26576  * Field Enumeration Values:
26577  *
26578  * Enum | Value | Description
26579  * :------------------------------------|:------|:---------------------
26580  * ALT_USB_HOST_HCINT3_XACTERR_E_INACT | 0x0 | No Transaction Error
26581  * ALT_USB_HOST_HCINT3_XACTERR_E_ACT | 0x1 | Transaction Error
26582  *
26583  * Field Access Macros:
26584  *
26585  */
26586 /*
26587  * Enumerated value for register field ALT_USB_HOST_HCINT3_XACTERR
26588  *
26589  * No Transaction Error
26590  */
26591 #define ALT_USB_HOST_HCINT3_XACTERR_E_INACT 0x0
26592 /*
26593  * Enumerated value for register field ALT_USB_HOST_HCINT3_XACTERR
26594  *
26595  * Transaction Error
26596  */
26597 #define ALT_USB_HOST_HCINT3_XACTERR_E_ACT 0x1
26598 
26599 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_XACTERR register field. */
26600 #define ALT_USB_HOST_HCINT3_XACTERR_LSB 7
26601 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_XACTERR register field. */
26602 #define ALT_USB_HOST_HCINT3_XACTERR_MSB 7
26603 /* The width in bits of the ALT_USB_HOST_HCINT3_XACTERR register field. */
26604 #define ALT_USB_HOST_HCINT3_XACTERR_WIDTH 1
26605 /* The mask used to set the ALT_USB_HOST_HCINT3_XACTERR register field value. */
26606 #define ALT_USB_HOST_HCINT3_XACTERR_SET_MSK 0x00000080
26607 /* The mask used to clear the ALT_USB_HOST_HCINT3_XACTERR register field value. */
26608 #define ALT_USB_HOST_HCINT3_XACTERR_CLR_MSK 0xffffff7f
26609 /* The reset value of the ALT_USB_HOST_HCINT3_XACTERR register field. */
26610 #define ALT_USB_HOST_HCINT3_XACTERR_RESET 0x0
26611 /* Extracts the ALT_USB_HOST_HCINT3_XACTERR field value from a register. */
26612 #define ALT_USB_HOST_HCINT3_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
26613 /* Produces a ALT_USB_HOST_HCINT3_XACTERR register field value suitable for setting the register. */
26614 #define ALT_USB_HOST_HCINT3_XACTERR_SET(value) (((value) << 7) & 0x00000080)
26615 
26616 /*
26617  * Field : bblerr
26618  *
26619  * Babble Error (BblErr)
26620  *
26621  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
26622  *
26623  * in the core..This bit can be set only by the core and the application should
26624  * write 1 to clear
26625  *
26626  * it.
26627  *
26628  * Field Enumeration Values:
26629  *
26630  * Enum | Value | Description
26631  * :-----------------------------------|:------|:----------------
26632  * ALT_USB_HOST_HCINT3_BBLERR_E_INACT | 0x0 | No Babble Error
26633  * ALT_USB_HOST_HCINT3_BBLERR_E_ACT | 0x1 | Babble Error
26634  *
26635  * Field Access Macros:
26636  *
26637  */
26638 /*
26639  * Enumerated value for register field ALT_USB_HOST_HCINT3_BBLERR
26640  *
26641  * No Babble Error
26642  */
26643 #define ALT_USB_HOST_HCINT3_BBLERR_E_INACT 0x0
26644 /*
26645  * Enumerated value for register field ALT_USB_HOST_HCINT3_BBLERR
26646  *
26647  * Babble Error
26648  */
26649 #define ALT_USB_HOST_HCINT3_BBLERR_E_ACT 0x1
26650 
26651 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_BBLERR register field. */
26652 #define ALT_USB_HOST_HCINT3_BBLERR_LSB 8
26653 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_BBLERR register field. */
26654 #define ALT_USB_HOST_HCINT3_BBLERR_MSB 8
26655 /* The width in bits of the ALT_USB_HOST_HCINT3_BBLERR register field. */
26656 #define ALT_USB_HOST_HCINT3_BBLERR_WIDTH 1
26657 /* The mask used to set the ALT_USB_HOST_HCINT3_BBLERR register field value. */
26658 #define ALT_USB_HOST_HCINT3_BBLERR_SET_MSK 0x00000100
26659 /* The mask used to clear the ALT_USB_HOST_HCINT3_BBLERR register field value. */
26660 #define ALT_USB_HOST_HCINT3_BBLERR_CLR_MSK 0xfffffeff
26661 /* The reset value of the ALT_USB_HOST_HCINT3_BBLERR register field. */
26662 #define ALT_USB_HOST_HCINT3_BBLERR_RESET 0x0
26663 /* Extracts the ALT_USB_HOST_HCINT3_BBLERR field value from a register. */
26664 #define ALT_USB_HOST_HCINT3_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
26665 /* Produces a ALT_USB_HOST_HCINT3_BBLERR register field value suitable for setting the register. */
26666 #define ALT_USB_HOST_HCINT3_BBLERR_SET(value) (((value) << 8) & 0x00000100)
26667 
26668 /*
26669  * Field : frmovrun
26670  *
26671  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
26672  * bit is masked
26673  *
26674  * in the core.This bit can be set only by the core and the application should
26675  * write 1 to clear
26676  *
26677  * it.
26678  *
26679  * Field Enumeration Values:
26680  *
26681  * Enum | Value | Description
26682  * :-------------------------------------|:------|:-----------------
26683  * ALT_USB_HOST_HCINT3_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
26684  * ALT_USB_HOST_HCINT3_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
26685  *
26686  * Field Access Macros:
26687  *
26688  */
26689 /*
26690  * Enumerated value for register field ALT_USB_HOST_HCINT3_FRMOVRUN
26691  *
26692  * No Frame Overrun
26693  */
26694 #define ALT_USB_HOST_HCINT3_FRMOVRUN_E_INACT 0x0
26695 /*
26696  * Enumerated value for register field ALT_USB_HOST_HCINT3_FRMOVRUN
26697  *
26698  * Frame Overrun
26699  */
26700 #define ALT_USB_HOST_HCINT3_FRMOVRUN_E_ACT 0x1
26701 
26702 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */
26703 #define ALT_USB_HOST_HCINT3_FRMOVRUN_LSB 9
26704 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */
26705 #define ALT_USB_HOST_HCINT3_FRMOVRUN_MSB 9
26706 /* The width in bits of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */
26707 #define ALT_USB_HOST_HCINT3_FRMOVRUN_WIDTH 1
26708 /* The mask used to set the ALT_USB_HOST_HCINT3_FRMOVRUN register field value. */
26709 #define ALT_USB_HOST_HCINT3_FRMOVRUN_SET_MSK 0x00000200
26710 /* The mask used to clear the ALT_USB_HOST_HCINT3_FRMOVRUN register field value. */
26711 #define ALT_USB_HOST_HCINT3_FRMOVRUN_CLR_MSK 0xfffffdff
26712 /* The reset value of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */
26713 #define ALT_USB_HOST_HCINT3_FRMOVRUN_RESET 0x0
26714 /* Extracts the ALT_USB_HOST_HCINT3_FRMOVRUN field value from a register. */
26715 #define ALT_USB_HOST_HCINT3_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
26716 /* Produces a ALT_USB_HOST_HCINT3_FRMOVRUN register field value suitable for setting the register. */
26717 #define ALT_USB_HOST_HCINT3_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
26718 
26719 /*
26720  * Field : datatglerr
26721  *
26722  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
26723  * application should write 1 to clear
26724  *
26725  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
26726  *
26727  * in the core.
26728  *
26729  * Field Enumeration Values:
26730  *
26731  * Enum | Value | Description
26732  * :---------------------------------------|:------|:---------------------
26733  * ALT_USB_HOST_HCINT3_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
26734  * ALT_USB_HOST_HCINT3_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
26735  *
26736  * Field Access Macros:
26737  *
26738  */
26739 /*
26740  * Enumerated value for register field ALT_USB_HOST_HCINT3_DATATGLERR
26741  *
26742  * No Data Toggle Error
26743  */
26744 #define ALT_USB_HOST_HCINT3_DATATGLERR_E_INACT 0x0
26745 /*
26746  * Enumerated value for register field ALT_USB_HOST_HCINT3_DATATGLERR
26747  *
26748  * Data Toggle Error
26749  */
26750 #define ALT_USB_HOST_HCINT3_DATATGLERR_E_ACT 0x1
26751 
26752 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */
26753 #define ALT_USB_HOST_HCINT3_DATATGLERR_LSB 10
26754 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */
26755 #define ALT_USB_HOST_HCINT3_DATATGLERR_MSB 10
26756 /* The width in bits of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */
26757 #define ALT_USB_HOST_HCINT3_DATATGLERR_WIDTH 1
26758 /* The mask used to set the ALT_USB_HOST_HCINT3_DATATGLERR register field value. */
26759 #define ALT_USB_HOST_HCINT3_DATATGLERR_SET_MSK 0x00000400
26760 /* The mask used to clear the ALT_USB_HOST_HCINT3_DATATGLERR register field value. */
26761 #define ALT_USB_HOST_HCINT3_DATATGLERR_CLR_MSK 0xfffffbff
26762 /* The reset value of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */
26763 #define ALT_USB_HOST_HCINT3_DATATGLERR_RESET 0x0
26764 /* Extracts the ALT_USB_HOST_HCINT3_DATATGLERR field value from a register. */
26765 #define ALT_USB_HOST_HCINT3_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
26766 /* Produces a ALT_USB_HOST_HCINT3_DATATGLERR register field value suitable for setting the register. */
26767 #define ALT_USB_HOST_HCINT3_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
26768 
26769 /*
26770  * Field : bnaintr
26771  *
26772  * BNA (Buffer Not Available) Interrupt (BNAIntr)
26773  *
26774  * This bit is valid only when Scatter/Gather DMA mode is enabled.
26775  *
26776  * The core generates this interrupt when the descriptor accessed
26777  *
26778  * is not ready for the Core to process. BNA will not be generated
26779  *
26780  * for Isochronous channels.
26781  *
26782  * For non Scatter/Gather DMA mode, this bit is reserved.
26783  *
26784  * Field Enumeration Values:
26785  *
26786  * Enum | Value | Description
26787  * :------------------------------------|:------|:-----------------
26788  * ALT_USB_HOST_HCINT3_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
26789  * ALT_USB_HOST_HCINT3_BNAINTR_E_ACT | 0x1 | BNA Interrupt
26790  *
26791  * Field Access Macros:
26792  *
26793  */
26794 /*
26795  * Enumerated value for register field ALT_USB_HOST_HCINT3_BNAINTR
26796  *
26797  * No BNA Interrupt
26798  */
26799 #define ALT_USB_HOST_HCINT3_BNAINTR_E_INACT 0x0
26800 /*
26801  * Enumerated value for register field ALT_USB_HOST_HCINT3_BNAINTR
26802  *
26803  * BNA Interrupt
26804  */
26805 #define ALT_USB_HOST_HCINT3_BNAINTR_E_ACT 0x1
26806 
26807 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_BNAINTR register field. */
26808 #define ALT_USB_HOST_HCINT3_BNAINTR_LSB 11
26809 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_BNAINTR register field. */
26810 #define ALT_USB_HOST_HCINT3_BNAINTR_MSB 11
26811 /* The width in bits of the ALT_USB_HOST_HCINT3_BNAINTR register field. */
26812 #define ALT_USB_HOST_HCINT3_BNAINTR_WIDTH 1
26813 /* The mask used to set the ALT_USB_HOST_HCINT3_BNAINTR register field value. */
26814 #define ALT_USB_HOST_HCINT3_BNAINTR_SET_MSK 0x00000800
26815 /* The mask used to clear the ALT_USB_HOST_HCINT3_BNAINTR register field value. */
26816 #define ALT_USB_HOST_HCINT3_BNAINTR_CLR_MSK 0xfffff7ff
26817 /* The reset value of the ALT_USB_HOST_HCINT3_BNAINTR register field. */
26818 #define ALT_USB_HOST_HCINT3_BNAINTR_RESET 0x0
26819 /* Extracts the ALT_USB_HOST_HCINT3_BNAINTR field value from a register. */
26820 #define ALT_USB_HOST_HCINT3_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
26821 /* Produces a ALT_USB_HOST_HCINT3_BNAINTR register field value suitable for setting the register. */
26822 #define ALT_USB_HOST_HCINT3_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
26823 
26824 /*
26825  * Field : xcs_xact_err
26826  *
26827  * Excessive Transaction Error (XCS_XACT_ERR)
26828  *
26829  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
26830  * this bit
26831  *
26832  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
26833  *
26834  * not be generated for Isochronous channels.
26835  *
26836  * For non Scatter/Gather DMA mode, this bit is reserved.
26837  *
26838  * Field Enumeration Values:
26839  *
26840  * Enum | Value | Description
26841  * :-------------------------------------------|:------|:-------------------------------
26842  * ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
26843  * ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
26844  *
26845  * Field Access Macros:
26846  *
26847  */
26848 /*
26849  * Enumerated value for register field ALT_USB_HOST_HCINT3_XCS_XACT_ERR
26850  *
26851  * No Excessive Transaction Error
26852  */
26853 #define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_INACT 0x0
26854 /*
26855  * Enumerated value for register field ALT_USB_HOST_HCINT3_XCS_XACT_ERR
26856  *
26857  * Excessive Transaction Error
26858  */
26859 #define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_ACVTIVE 0x1
26860 
26861 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */
26862 #define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_LSB 12
26863 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */
26864 #define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_MSB 12
26865 /* The width in bits of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */
26866 #define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_WIDTH 1
26867 /* The mask used to set the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field value. */
26868 #define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_SET_MSK 0x00001000
26869 /* The mask used to clear the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field value. */
26870 #define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_CLR_MSK 0xffffefff
26871 /* The reset value of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */
26872 #define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_RESET 0x0
26873 /* Extracts the ALT_USB_HOST_HCINT3_XCS_XACT_ERR field value from a register. */
26874 #define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
26875 /* Produces a ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field value suitable for setting the register. */
26876 #define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
26877 
26878 /*
26879  * Field : desc_lst_rollintr
26880  *
26881  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
26882  *
26883  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
26884  * this bit
26885  *
26886  * when the corresponding channel's descriptor list rolls over.
26887  *
26888  * For non Scatter/Gather DMA mode, this bit is reserved.
26889  *
26890  * Field Enumeration Values:
26891  *
26892  * Enum | Value | Description
26893  * :----------------------------------------------|:------|:---------------------------------
26894  * ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
26895  * ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
26896  *
26897  * Field Access Macros:
26898  *
26899  */
26900 /*
26901  * Enumerated value for register field ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR
26902  *
26903  * No Descriptor rollover interrupt
26904  */
26905 #define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_INACT 0x0
26906 /*
26907  * Enumerated value for register field ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR
26908  *
26909  * Descriptor rollover interrupt
26910  */
26911 #define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_ACT 0x1
26912 
26913 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */
26914 #define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_LSB 13
26915 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */
26916 #define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_MSB 13
26917 /* The width in bits of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */
26918 #define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_WIDTH 1
26919 /* The mask used to set the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field value. */
26920 #define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_SET_MSK 0x00002000
26921 /* The mask used to clear the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field value. */
26922 #define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
26923 /* The reset value of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */
26924 #define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_RESET 0x0
26925 /* Extracts the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR field value from a register. */
26926 #define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
26927 /* Produces a ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field value suitable for setting the register. */
26928 #define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
26929 
26930 #ifndef __ASSEMBLY__
26931 /*
26932  * WARNING: The C register and register group struct declarations are provided for
26933  * convenience and illustrative purposes. They should, however, be used with
26934  * caution as the C language standard provides no guarantees about the alignment or
26935  * atomicity of device memory accesses. The recommended practice for writing
26936  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26937  * alt_write_word() functions.
26938  *
26939  * The struct declaration for register ALT_USB_HOST_HCINT3.
26940  */
26941 struct ALT_USB_HOST_HCINT3_s
26942 {
26943  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT3_XFERCOMPL */
26944  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT3_CHHLTD */
26945  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT3_AHBERR */
26946  uint32_t stall : 1; /* ALT_USB_HOST_HCINT3_STALL */
26947  uint32_t nak : 1; /* ALT_USB_HOST_HCINT3_NAK */
26948  uint32_t ack : 1; /* ALT_USB_HOST_HCINT3_ACK */
26949  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT3_NYET */
26950  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT3_XACTERR */
26951  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT3_BBLERR */
26952  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT3_FRMOVRUN */
26953  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT3_DATATGLERR */
26954  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT3_BNAINTR */
26955  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT3_XCS_XACT_ERR */
26956  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR */
26957  uint32_t : 18; /* *UNDEFINED* */
26958 };
26959 
26960 /* The typedef declaration for register ALT_USB_HOST_HCINT3. */
26961 typedef volatile struct ALT_USB_HOST_HCINT3_s ALT_USB_HOST_HCINT3_t;
26962 #endif /* __ASSEMBLY__ */
26963 
26964 /* The reset value of the ALT_USB_HOST_HCINT3 register. */
26965 #define ALT_USB_HOST_HCINT3_RESET 0x00000000
26966 /* The byte offset of the ALT_USB_HOST_HCINT3 register from the beginning of the component. */
26967 #define ALT_USB_HOST_HCINT3_OFST 0x168
26968 /* The address of the ALT_USB_HOST_HCINT3 register. */
26969 #define ALT_USB_HOST_HCINT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT3_OFST))
26970 
26971 /*
26972  * Register : hcintmsk3
26973  *
26974  * Host Channel 3 Interrupt Mask Register
26975  *
26976  * Register Layout
26977  *
26978  * Bits | Access | Reset | Description
26979  * :--------|:-------|:------|:-------------------------------------------
26980  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK
26981  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_CHHLTDMSK
26982  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_AHBERRMSK
26983  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_STALLMSK
26984  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_NAKMSK
26985  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_ACKMSK
26986  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_NYETMSK
26987  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_XACTERRMSK
26988  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_BBLERRMSK
26989  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK
26990  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK
26991  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_BNAINTRMSK
26992  * [12] | ??? | 0x0 | *UNDEFINED*
26993  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK
26994  * [31:14] | ??? | 0x0 | *UNDEFINED*
26995  *
26996  */
26997 /*
26998  * Field : xfercomplmsk
26999  *
27000  * Transfer Completed Mask (XferComplMsk)
27001  *
27002  * Field Enumeration Values:
27003  *
27004  * Enum | Value | Description
27005  * :--------------------------------------------|:------|:------------
27006  * ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_MSK | 0x0 | Mask
27007  * ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
27008  *
27009  * Field Access Macros:
27010  *
27011  */
27012 /*
27013  * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK
27014  *
27015  * Mask
27016  */
27017 #define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_MSK 0x0
27018 /*
27019  * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK
27020  *
27021  * No mask
27022  */
27023 #define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_NOMSK 0x1
27024 
27025 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */
27026 #define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_LSB 0
27027 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */
27028 #define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_MSB 0
27029 /* The width in bits of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */
27030 #define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_WIDTH 1
27031 /* The mask used to set the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field value. */
27032 #define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_SET_MSK 0x00000001
27033 /* The mask used to clear the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field value. */
27034 #define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_CLR_MSK 0xfffffffe
27035 /* The reset value of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */
27036 #define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_RESET 0x0
27037 /* Extracts the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK field value from a register. */
27038 #define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
27039 /* Produces a ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field value suitable for setting the register. */
27040 #define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
27041 
27042 /*
27043  * Field : chhltdmsk
27044  *
27045  * Channel Halted Mask (ChHltdMsk)
27046  *
27047  * Field Enumeration Values:
27048  *
27049  * Enum | Value | Description
27050  * :-----------------------------------------|:------|:------------
27051  * ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_MSK | 0x0 | Mask
27052  * ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_NOMSK | 0x1 | No mask
27053  *
27054  * Field Access Macros:
27055  *
27056  */
27057 /*
27058  * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_CHHLTDMSK
27059  *
27060  * Mask
27061  */
27062 #define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_MSK 0x0
27063 /*
27064  * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_CHHLTDMSK
27065  *
27066  * No mask
27067  */
27068 #define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_NOMSK 0x1
27069 
27070 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */
27071 #define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_LSB 1
27072 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */
27073 #define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_MSB 1
27074 /* The width in bits of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */
27075 #define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_WIDTH 1
27076 /* The mask used to set the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field value. */
27077 #define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_SET_MSK 0x00000002
27078 /* The mask used to clear the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field value. */
27079 #define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_CLR_MSK 0xfffffffd
27080 /* The reset value of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */
27081 #define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_RESET 0x0
27082 /* Extracts the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK field value from a register. */
27083 #define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
27084 /* Produces a ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field value suitable for setting the register. */
27085 #define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
27086 
27087 /*
27088  * Field : ahberrmsk
27089  *
27090  * AHB Error Mask (AHBErrMsk)
27091  *
27092  * In scatter/gather DMA mode for host,
27093  *
27094  * interrupts will not be generated due to the corresponding bits set in
27095  *
27096  * HCINTn.
27097  *
27098  * Field Enumeration Values:
27099  *
27100  * Enum | Value | Description
27101  * :-----------------------------------------|:------|:------------
27102  * ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_MSK | 0x0 | Mask
27103  * ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_NOMSK | 0x1 | No mask
27104  *
27105  * Field Access Macros:
27106  *
27107  */
27108 /*
27109  * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_AHBERRMSK
27110  *
27111  * Mask
27112  */
27113 #define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_MSK 0x0
27114 /*
27115  * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_AHBERRMSK
27116  *
27117  * No mask
27118  */
27119 #define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_NOMSK 0x1
27120 
27121 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */
27122 #define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_LSB 2
27123 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */
27124 #define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_MSB 2
27125 /* The width in bits of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */
27126 #define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_WIDTH 1
27127 /* The mask used to set the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field value. */
27128 #define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_SET_MSK 0x00000004
27129 /* The mask used to clear the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field value. */
27130 #define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_CLR_MSK 0xfffffffb
27131 /* The reset value of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */
27132 #define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_RESET 0x0
27133 /* Extracts the ALT_USB_HOST_HCINTMSK3_AHBERRMSK field value from a register. */
27134 #define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
27135 /* Produces a ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field value suitable for setting the register. */
27136 #define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
27137 
27138 /*
27139  * Field : stallmsk
27140  *
27141  * STALL Response Received Interrupt Mask (StallMsk)
27142  *
27143  * In scatter/gather DMA mode for host,
27144  *
27145  * interrupts will not be generated due to the corresponding bits set in
27146  *
27147  * HCINTn.
27148  *
27149  * Field Access Macros:
27150  *
27151  */
27152 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_STALLMSK register field. */
27153 #define ALT_USB_HOST_HCINTMSK3_STALLMSK_LSB 3
27154 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_STALLMSK register field. */
27155 #define ALT_USB_HOST_HCINTMSK3_STALLMSK_MSB 3
27156 /* The width in bits of the ALT_USB_HOST_HCINTMSK3_STALLMSK register field. */
27157 #define ALT_USB_HOST_HCINTMSK3_STALLMSK_WIDTH 1
27158 /* The mask used to set the ALT_USB_HOST_HCINTMSK3_STALLMSK register field value. */
27159 #define ALT_USB_HOST_HCINTMSK3_STALLMSK_SET_MSK 0x00000008
27160 /* The mask used to clear the ALT_USB_HOST_HCINTMSK3_STALLMSK register field value. */
27161 #define ALT_USB_HOST_HCINTMSK3_STALLMSK_CLR_MSK 0xfffffff7
27162 /* The reset value of the ALT_USB_HOST_HCINTMSK3_STALLMSK register field. */
27163 #define ALT_USB_HOST_HCINTMSK3_STALLMSK_RESET 0x0
27164 /* Extracts the ALT_USB_HOST_HCINTMSK3_STALLMSK field value from a register. */
27165 #define ALT_USB_HOST_HCINTMSK3_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
27166 /* Produces a ALT_USB_HOST_HCINTMSK3_STALLMSK register field value suitable for setting the register. */
27167 #define ALT_USB_HOST_HCINTMSK3_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
27168 
27169 /*
27170  * Field : nakmsk
27171  *
27172  * NAK Response Received Interrupt Mask (NakMsk)
27173  *
27174  * In scatter/gather DMA mode for host,
27175  *
27176  * interrupts will not be generated due to the corresponding bits set in
27177  *
27178  * HCINTn.
27179  *
27180  * Field Access Macros:
27181  *
27182  */
27183 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_NAKMSK register field. */
27184 #define ALT_USB_HOST_HCINTMSK3_NAKMSK_LSB 4
27185 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_NAKMSK register field. */
27186 #define ALT_USB_HOST_HCINTMSK3_NAKMSK_MSB 4
27187 /* The width in bits of the ALT_USB_HOST_HCINTMSK3_NAKMSK register field. */
27188 #define ALT_USB_HOST_HCINTMSK3_NAKMSK_WIDTH 1
27189 /* The mask used to set the ALT_USB_HOST_HCINTMSK3_NAKMSK register field value. */
27190 #define ALT_USB_HOST_HCINTMSK3_NAKMSK_SET_MSK 0x00000010
27191 /* The mask used to clear the ALT_USB_HOST_HCINTMSK3_NAKMSK register field value. */
27192 #define ALT_USB_HOST_HCINTMSK3_NAKMSK_CLR_MSK 0xffffffef
27193 /* The reset value of the ALT_USB_HOST_HCINTMSK3_NAKMSK register field. */
27194 #define ALT_USB_HOST_HCINTMSK3_NAKMSK_RESET 0x0
27195 /* Extracts the ALT_USB_HOST_HCINTMSK3_NAKMSK field value from a register. */
27196 #define ALT_USB_HOST_HCINTMSK3_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
27197 /* Produces a ALT_USB_HOST_HCINTMSK3_NAKMSK register field value suitable for setting the register. */
27198 #define ALT_USB_HOST_HCINTMSK3_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
27199 
27200 /*
27201  * Field : ackmsk
27202  *
27203  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
27204  *
27205  * In scatter/gather DMA mode for host,
27206  *
27207  * interrupts will not be generated due to the corresponding bits set in
27208  *
27209  * HCINTn.
27210  *
27211  * Field Access Macros:
27212  *
27213  */
27214 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_ACKMSK register field. */
27215 #define ALT_USB_HOST_HCINTMSK3_ACKMSK_LSB 5
27216 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_ACKMSK register field. */
27217 #define ALT_USB_HOST_HCINTMSK3_ACKMSK_MSB 5
27218 /* The width in bits of the ALT_USB_HOST_HCINTMSK3_ACKMSK register field. */
27219 #define ALT_USB_HOST_HCINTMSK3_ACKMSK_WIDTH 1
27220 /* The mask used to set the ALT_USB_HOST_HCINTMSK3_ACKMSK register field value. */
27221 #define ALT_USB_HOST_HCINTMSK3_ACKMSK_SET_MSK 0x00000020
27222 /* The mask used to clear the ALT_USB_HOST_HCINTMSK3_ACKMSK register field value. */
27223 #define ALT_USB_HOST_HCINTMSK3_ACKMSK_CLR_MSK 0xffffffdf
27224 /* The reset value of the ALT_USB_HOST_HCINTMSK3_ACKMSK register field. */
27225 #define ALT_USB_HOST_HCINTMSK3_ACKMSK_RESET 0x0
27226 /* Extracts the ALT_USB_HOST_HCINTMSK3_ACKMSK field value from a register. */
27227 #define ALT_USB_HOST_HCINTMSK3_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
27228 /* Produces a ALT_USB_HOST_HCINTMSK3_ACKMSK register field value suitable for setting the register. */
27229 #define ALT_USB_HOST_HCINTMSK3_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
27230 
27231 /*
27232  * Field : nyetmsk
27233  *
27234  * NYET Response Received Interrupt Mask (NyetMsk)
27235  *
27236  * In scatter/gather DMA mode for host,
27237  *
27238  * interrupts will not be generated due to the corresponding bits set in
27239  *
27240  * HCINTn.
27241  *
27242  * Field Access Macros:
27243  *
27244  */
27245 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_NYETMSK register field. */
27246 #define ALT_USB_HOST_HCINTMSK3_NYETMSK_LSB 6
27247 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_NYETMSK register field. */
27248 #define ALT_USB_HOST_HCINTMSK3_NYETMSK_MSB 6
27249 /* The width in bits of the ALT_USB_HOST_HCINTMSK3_NYETMSK register field. */
27250 #define ALT_USB_HOST_HCINTMSK3_NYETMSK_WIDTH 1
27251 /* The mask used to set the ALT_USB_HOST_HCINTMSK3_NYETMSK register field value. */
27252 #define ALT_USB_HOST_HCINTMSK3_NYETMSK_SET_MSK 0x00000040
27253 /* The mask used to clear the ALT_USB_HOST_HCINTMSK3_NYETMSK register field value. */
27254 #define ALT_USB_HOST_HCINTMSK3_NYETMSK_CLR_MSK 0xffffffbf
27255 /* The reset value of the ALT_USB_HOST_HCINTMSK3_NYETMSK register field. */
27256 #define ALT_USB_HOST_HCINTMSK3_NYETMSK_RESET 0x0
27257 /* Extracts the ALT_USB_HOST_HCINTMSK3_NYETMSK field value from a register. */
27258 #define ALT_USB_HOST_HCINTMSK3_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
27259 /* Produces a ALT_USB_HOST_HCINTMSK3_NYETMSK register field value suitable for setting the register. */
27260 #define ALT_USB_HOST_HCINTMSK3_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
27261 
27262 /*
27263  * Field : xacterrmsk
27264  *
27265  * Transaction Error Mask (XactErrMsk)
27266  *
27267  * In scatter/gather DMA mode for host,
27268  *
27269  * interrupts will not be generated due to the corresponding bits set in
27270  *
27271  * HCINTn.
27272  *
27273  * Field Access Macros:
27274  *
27275  */
27276 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field. */
27277 #define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_LSB 7
27278 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field. */
27279 #define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_MSB 7
27280 /* The width in bits of the ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field. */
27281 #define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_WIDTH 1
27282 /* The mask used to set the ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field value. */
27283 #define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_SET_MSK 0x00000080
27284 /* The mask used to clear the ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field value. */
27285 #define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_CLR_MSK 0xffffff7f
27286 /* The reset value of the ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field. */
27287 #define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_RESET 0x0
27288 /* Extracts the ALT_USB_HOST_HCINTMSK3_XACTERRMSK field value from a register. */
27289 #define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
27290 /* Produces a ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field value suitable for setting the register. */
27291 #define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
27292 
27293 /*
27294  * Field : bblerrmsk
27295  *
27296  * Babble Error Mask (BblErrMsk)
27297  *
27298  * In scatter/gather DMA mode for host,
27299  *
27300  * interrupts will not be generated due to the corresponding bits set in
27301  *
27302  * HCINTn.
27303  *
27304  * Field Access Macros:
27305  *
27306  */
27307 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field. */
27308 #define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_LSB 8
27309 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field. */
27310 #define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_MSB 8
27311 /* The width in bits of the ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field. */
27312 #define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_WIDTH 1
27313 /* The mask used to set the ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field value. */
27314 #define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_SET_MSK 0x00000100
27315 /* The mask used to clear the ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field value. */
27316 #define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_CLR_MSK 0xfffffeff
27317 /* The reset value of the ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field. */
27318 #define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_RESET 0x0
27319 /* Extracts the ALT_USB_HOST_HCINTMSK3_BBLERRMSK field value from a register. */
27320 #define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
27321 /* Produces a ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field value suitable for setting the register. */
27322 #define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
27323 
27324 /*
27325  * Field : frmovrunmsk
27326  *
27327  * Frame Overrun Mask (FrmOvrunMsk)
27328  *
27329  * In scatter/gather DMA mode for host,
27330  *
27331  * interrupts will not be generated due to the corresponding bits set in
27332  *
27333  * HCINTn.
27334  *
27335  * Field Access Macros:
27336  *
27337  */
27338 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field. */
27339 #define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_LSB 9
27340 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field. */
27341 #define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_MSB 9
27342 /* The width in bits of the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field. */
27343 #define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_WIDTH 1
27344 /* The mask used to set the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field value. */
27345 #define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_SET_MSK 0x00000200
27346 /* The mask used to clear the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field value. */
27347 #define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_CLR_MSK 0xfffffdff
27348 /* The reset value of the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field. */
27349 #define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_RESET 0x0
27350 /* Extracts the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK field value from a register. */
27351 #define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
27352 /* Produces a ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field value suitable for setting the register. */
27353 #define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
27354 
27355 /*
27356  * Field : datatglerrmsk
27357  *
27358  * Data Toggle Error Mask (DataTglErrMsk)
27359  *
27360  * In scatter/gather DMA mode for host,
27361  *
27362  * interrupts will not be generated due to the corresponding bits set in
27363  *
27364  * HCINTn.
27365  *
27366  * Field Access Macros:
27367  *
27368  */
27369 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field. */
27370 #define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_LSB 10
27371 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field. */
27372 #define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_MSB 10
27373 /* The width in bits of the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field. */
27374 #define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_WIDTH 1
27375 /* The mask used to set the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field value. */
27376 #define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_SET_MSK 0x00000400
27377 /* The mask used to clear the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field value. */
27378 #define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_CLR_MSK 0xfffffbff
27379 /* The reset value of the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field. */
27380 #define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_RESET 0x0
27381 /* Extracts the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK field value from a register. */
27382 #define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
27383 /* Produces a ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field value suitable for setting the register. */
27384 #define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
27385 
27386 /*
27387  * Field : bnaintrmsk
27388  *
27389  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
27390  *
27391  * This bit is valid only when Scatter/Gather DMA mode is enabled.
27392  *
27393  * Field Enumeration Values:
27394  *
27395  * Enum | Value | Description
27396  * :------------------------------------------|:------|:------------
27397  * ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_MSK | 0x0 | Mask
27398  * ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_NOMSK | 0x1 | No mask
27399  *
27400  * Field Access Macros:
27401  *
27402  */
27403 /*
27404  * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_BNAINTRMSK
27405  *
27406  * Mask
27407  */
27408 #define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_MSK 0x0
27409 /*
27410  * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_BNAINTRMSK
27411  *
27412  * No mask
27413  */
27414 #define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_NOMSK 0x1
27415 
27416 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */
27417 #define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_LSB 11
27418 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */
27419 #define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_MSB 11
27420 /* The width in bits of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */
27421 #define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_WIDTH 1
27422 /* The mask used to set the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field value. */
27423 #define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_SET_MSK 0x00000800
27424 /* The mask used to clear the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field value. */
27425 #define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_CLR_MSK 0xfffff7ff
27426 /* The reset value of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */
27427 #define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_RESET 0x0
27428 /* Extracts the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK field value from a register. */
27429 #define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
27430 /* Produces a ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field value suitable for setting the register. */
27431 #define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
27432 
27433 /*
27434  * Field : frm_lst_rollintrmsk
27435  *
27436  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
27437  *
27438  * This bit is valid only when Scatter/Gather DMA mode is enabled.
27439  *
27440  * Field Enumeration Values:
27441  *
27442  * Enum | Value | Description
27443  * :---------------------------------------------------|:------|:------------
27444  * ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
27445  * ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
27446  *
27447  * Field Access Macros:
27448  *
27449  */
27450 /*
27451  * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK
27452  *
27453  * Mask
27454  */
27455 #define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_MSK 0x0
27456 /*
27457  * Enumerated value for register field ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK
27458  *
27459  * No mask
27460  */
27461 #define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
27462 
27463 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */
27464 #define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_LSB 13
27465 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */
27466 #define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_MSB 13
27467 /* The width in bits of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */
27468 #define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_WIDTH 1
27469 /* The mask used to set the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field value. */
27470 #define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
27471 /* The mask used to clear the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field value. */
27472 #define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
27473 /* The reset value of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */
27474 #define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_RESET 0x0
27475 /* Extracts the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK field value from a register. */
27476 #define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
27477 /* Produces a ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
27478 #define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
27479 
27480 #ifndef __ASSEMBLY__
27481 /*
27482  * WARNING: The C register and register group struct declarations are provided for
27483  * convenience and illustrative purposes. They should, however, be used with
27484  * caution as the C language standard provides no guarantees about the alignment or
27485  * atomicity of device memory accesses. The recommended practice for writing
27486  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27487  * alt_write_word() functions.
27488  *
27489  * The struct declaration for register ALT_USB_HOST_HCINTMSK3.
27490  */
27491 struct ALT_USB_HOST_HCINTMSK3_s
27492 {
27493  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK */
27494  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK3_CHHLTDMSK */
27495  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK3_AHBERRMSK */
27496  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK3_STALLMSK */
27497  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK3_NAKMSK */
27498  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK3_ACKMSK */
27499  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK3_NYETMSK */
27500  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK3_XACTERRMSK */
27501  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK3_BBLERRMSK */
27502  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK */
27503  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK */
27504  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK3_BNAINTRMSK */
27505  uint32_t : 1; /* *UNDEFINED* */
27506  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK */
27507  uint32_t : 18; /* *UNDEFINED* */
27508 };
27509 
27510 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK3. */
27511 typedef volatile struct ALT_USB_HOST_HCINTMSK3_s ALT_USB_HOST_HCINTMSK3_t;
27512 #endif /* __ASSEMBLY__ */
27513 
27514 /* The reset value of the ALT_USB_HOST_HCINTMSK3 register. */
27515 #define ALT_USB_HOST_HCINTMSK3_RESET 0x00000000
27516 /* The byte offset of the ALT_USB_HOST_HCINTMSK3 register from the beginning of the component. */
27517 #define ALT_USB_HOST_HCINTMSK3_OFST 0x16c
27518 /* The address of the ALT_USB_HOST_HCINTMSK3 register. */
27519 #define ALT_USB_HOST_HCINTMSK3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK3_OFST))
27520 
27521 /*
27522  * Register : hctsiz3
27523  *
27524  * Host Channel 3 Transfer Size Register
27525  *
27526  * Register Layout
27527  *
27528  * Bits | Access | Reset | Description
27529  * :--------|:-------|:------|:------------------------------
27530  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ3_XFERSIZE
27531  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ3_PKTCNT
27532  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ3_PID
27533  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ3_DOPNG
27534  *
27535  */
27536 /*
27537  * Field : xfersize
27538  *
27539  * Transfer Size (XferSize)
27540  *
27541  * For an OUT, this field is the number of data bytes the host sends
27542  *
27543  * during the transfer.
27544  *
27545  * For an IN, this field is the buffer size that the application has
27546  *
27547  * Reserved For the transfer. The application is expected to
27548  *
27549  * program this field as an integer multiple of the maximum packet
27550  *
27551  * size For IN transactions (periodic and non-periodic).
27552  *
27553  * The width of this counter is specified as Width of Transfer Size
27554  *
27555  * Counters
27556  *
27557  * Field Access Macros:
27558  *
27559  */
27560 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */
27561 #define ALT_USB_HOST_HCTSIZ3_XFERSIZE_LSB 0
27562 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */
27563 #define ALT_USB_HOST_HCTSIZ3_XFERSIZE_MSB 18
27564 /* The width in bits of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */
27565 #define ALT_USB_HOST_HCTSIZ3_XFERSIZE_WIDTH 19
27566 /* The mask used to set the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field value. */
27567 #define ALT_USB_HOST_HCTSIZ3_XFERSIZE_SET_MSK 0x0007ffff
27568 /* The mask used to clear the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field value. */
27569 #define ALT_USB_HOST_HCTSIZ3_XFERSIZE_CLR_MSK 0xfff80000
27570 /* The reset value of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */
27571 #define ALT_USB_HOST_HCTSIZ3_XFERSIZE_RESET 0x0
27572 /* Extracts the ALT_USB_HOST_HCTSIZ3_XFERSIZE field value from a register. */
27573 #define ALT_USB_HOST_HCTSIZ3_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
27574 /* Produces a ALT_USB_HOST_HCTSIZ3_XFERSIZE register field value suitable for setting the register. */
27575 #define ALT_USB_HOST_HCTSIZ3_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
27576 
27577 /*
27578  * Field : pktcnt
27579  *
27580  * Packet Count (PktCnt)
27581  *
27582  * This field is programmed by the application with the expected
27583  *
27584  * number of packets to be transmitted (OUT) or received (IN).
27585  *
27586  * The host decrements this count on every successful
27587  *
27588  * transmission or reception of an OUT/IN packet. Once this count
27589  *
27590  * reaches zero, the application is interrupted to indicate normal
27591  *
27592  * completion.
27593  *
27594  * The width of this counter is specified as Width of Packet
27595  *
27596  * Counters
27597  *
27598  * Field Access Macros:
27599  *
27600  */
27601 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */
27602 #define ALT_USB_HOST_HCTSIZ3_PKTCNT_LSB 19
27603 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */
27604 #define ALT_USB_HOST_HCTSIZ3_PKTCNT_MSB 28
27605 /* The width in bits of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */
27606 #define ALT_USB_HOST_HCTSIZ3_PKTCNT_WIDTH 10
27607 /* The mask used to set the ALT_USB_HOST_HCTSIZ3_PKTCNT register field value. */
27608 #define ALT_USB_HOST_HCTSIZ3_PKTCNT_SET_MSK 0x1ff80000
27609 /* The mask used to clear the ALT_USB_HOST_HCTSIZ3_PKTCNT register field value. */
27610 #define ALT_USB_HOST_HCTSIZ3_PKTCNT_CLR_MSK 0xe007ffff
27611 /* The reset value of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */
27612 #define ALT_USB_HOST_HCTSIZ3_PKTCNT_RESET 0x0
27613 /* Extracts the ALT_USB_HOST_HCTSIZ3_PKTCNT field value from a register. */
27614 #define ALT_USB_HOST_HCTSIZ3_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
27615 /* Produces a ALT_USB_HOST_HCTSIZ3_PKTCNT register field value suitable for setting the register. */
27616 #define ALT_USB_HOST_HCTSIZ3_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
27617 
27618 /*
27619  * Field : pid
27620  *
27621  * PID (Pid)
27622  *
27623  * The application programs this field with the type of PID to use For
27624  *
27625  * the initial transaction. The host maintains this field For the rest of
27626  *
27627  * the transfer.
27628  *
27629  * 2'b00: DATA0
27630  *
27631  * 2'b01: DATA2
27632  *
27633  * 2'b10: DATA1
27634  *
27635  * 2'b11: MDATA (non-control)/SETUP (control)
27636  *
27637  * Field Enumeration Values:
27638  *
27639  * Enum | Value | Description
27640  * :---------------------------------|:------|:------------------------------------
27641  * ALT_USB_HOST_HCTSIZ3_PID_E_DATA0 | 0x0 | DATA0
27642  * ALT_USB_HOST_HCTSIZ3_PID_E_DATA2 | 0x1 | DATA2
27643  * ALT_USB_HOST_HCTSIZ3_PID_E_DATA1 | 0x2 | DATA1
27644  * ALT_USB_HOST_HCTSIZ3_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
27645  *
27646  * Field Access Macros:
27647  *
27648  */
27649 /*
27650  * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID
27651  *
27652  * DATA0
27653  */
27654 #define ALT_USB_HOST_HCTSIZ3_PID_E_DATA0 0x0
27655 /*
27656  * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID
27657  *
27658  * DATA2
27659  */
27660 #define ALT_USB_HOST_HCTSIZ3_PID_E_DATA2 0x1
27661 /*
27662  * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID
27663  *
27664  * DATA1
27665  */
27666 #define ALT_USB_HOST_HCTSIZ3_PID_E_DATA1 0x2
27667 /*
27668  * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID
27669  *
27670  * MDATA (non-control)/SETUP (control)
27671  */
27672 #define ALT_USB_HOST_HCTSIZ3_PID_E_MDATA 0x3
27673 
27674 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_PID register field. */
27675 #define ALT_USB_HOST_HCTSIZ3_PID_LSB 29
27676 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_PID register field. */
27677 #define ALT_USB_HOST_HCTSIZ3_PID_MSB 30
27678 /* The width in bits of the ALT_USB_HOST_HCTSIZ3_PID register field. */
27679 #define ALT_USB_HOST_HCTSIZ3_PID_WIDTH 2
27680 /* The mask used to set the ALT_USB_HOST_HCTSIZ3_PID register field value. */
27681 #define ALT_USB_HOST_HCTSIZ3_PID_SET_MSK 0x60000000
27682 /* The mask used to clear the ALT_USB_HOST_HCTSIZ3_PID register field value. */
27683 #define ALT_USB_HOST_HCTSIZ3_PID_CLR_MSK 0x9fffffff
27684 /* The reset value of the ALT_USB_HOST_HCTSIZ3_PID register field. */
27685 #define ALT_USB_HOST_HCTSIZ3_PID_RESET 0x0
27686 /* Extracts the ALT_USB_HOST_HCTSIZ3_PID field value from a register. */
27687 #define ALT_USB_HOST_HCTSIZ3_PID_GET(value) (((value) & 0x60000000) >> 29)
27688 /* Produces a ALT_USB_HOST_HCTSIZ3_PID register field value suitable for setting the register. */
27689 #define ALT_USB_HOST_HCTSIZ3_PID_SET(value) (((value) << 29) & 0x60000000)
27690 
27691 /*
27692  * Field : dopng
27693  *
27694  * Do Ping (DoPng)
27695  *
27696  * This bit is used only For OUT transfers.
27697  *
27698  * Setting this field to 1 directs the host to do PING protocol.
27699  *
27700  * Note: Do not Set this bit For IN transfers. If this bit is Set For
27701  *
27702  * for IN transfers it disables the channel.
27703  *
27704  * Field Enumeration Values:
27705  *
27706  * Enum | Value | Description
27707  * :------------------------------------|:------|:-----------------
27708  * ALT_USB_HOST_HCTSIZ3_DOPNG_E_NOPING | 0x0 | No ping protocol
27709  * ALT_USB_HOST_HCTSIZ3_DOPNG_E_PING | 0x1 | Ping protocol
27710  *
27711  * Field Access Macros:
27712  *
27713  */
27714 /*
27715  * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_DOPNG
27716  *
27717  * No ping protocol
27718  */
27719 #define ALT_USB_HOST_HCTSIZ3_DOPNG_E_NOPING 0x0
27720 /*
27721  * Enumerated value for register field ALT_USB_HOST_HCTSIZ3_DOPNG
27722  *
27723  * Ping protocol
27724  */
27725 #define ALT_USB_HOST_HCTSIZ3_DOPNG_E_PING 0x1
27726 
27727 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */
27728 #define ALT_USB_HOST_HCTSIZ3_DOPNG_LSB 31
27729 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */
27730 #define ALT_USB_HOST_HCTSIZ3_DOPNG_MSB 31
27731 /* The width in bits of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */
27732 #define ALT_USB_HOST_HCTSIZ3_DOPNG_WIDTH 1
27733 /* The mask used to set the ALT_USB_HOST_HCTSIZ3_DOPNG register field value. */
27734 #define ALT_USB_HOST_HCTSIZ3_DOPNG_SET_MSK 0x80000000
27735 /* The mask used to clear the ALT_USB_HOST_HCTSIZ3_DOPNG register field value. */
27736 #define ALT_USB_HOST_HCTSIZ3_DOPNG_CLR_MSK 0x7fffffff
27737 /* The reset value of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */
27738 #define ALT_USB_HOST_HCTSIZ3_DOPNG_RESET 0x0
27739 /* Extracts the ALT_USB_HOST_HCTSIZ3_DOPNG field value from a register. */
27740 #define ALT_USB_HOST_HCTSIZ3_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
27741 /* Produces a ALT_USB_HOST_HCTSIZ3_DOPNG register field value suitable for setting the register. */
27742 #define ALT_USB_HOST_HCTSIZ3_DOPNG_SET(value) (((value) << 31) & 0x80000000)
27743 
27744 #ifndef __ASSEMBLY__
27745 /*
27746  * WARNING: The C register and register group struct declarations are provided for
27747  * convenience and illustrative purposes. They should, however, be used with
27748  * caution as the C language standard provides no guarantees about the alignment or
27749  * atomicity of device memory accesses. The recommended practice for writing
27750  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27751  * alt_write_word() functions.
27752  *
27753  * The struct declaration for register ALT_USB_HOST_HCTSIZ3.
27754  */
27755 struct ALT_USB_HOST_HCTSIZ3_s
27756 {
27757  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ3_XFERSIZE */
27758  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ3_PKTCNT */
27759  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ3_PID */
27760  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ3_DOPNG */
27761 };
27762 
27763 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ3. */
27764 typedef volatile struct ALT_USB_HOST_HCTSIZ3_s ALT_USB_HOST_HCTSIZ3_t;
27765 #endif /* __ASSEMBLY__ */
27766 
27767 /* The reset value of the ALT_USB_HOST_HCTSIZ3 register. */
27768 #define ALT_USB_HOST_HCTSIZ3_RESET 0x00000000
27769 /* The byte offset of the ALT_USB_HOST_HCTSIZ3 register from the beginning of the component. */
27770 #define ALT_USB_HOST_HCTSIZ3_OFST 0x170
27771 /* The address of the ALT_USB_HOST_HCTSIZ3 register. */
27772 #define ALT_USB_HOST_HCTSIZ3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ3_OFST))
27773 
27774 /*
27775  * Register : hcdma3
27776  *
27777  * Host Channel 3 DMA Address Register
27778  *
27779  * Register Layout
27780  *
27781  * Bits | Access | Reset | Description
27782  * :-------|:-------|:------|:---------------------------
27783  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA3_HCDMA3
27784  *
27785  */
27786 /*
27787  * Field : hcdma3
27788  *
27789  * Buffer DMA Mode:
27790  *
27791  * [31:0] DMA Address (DMAAddr)
27792  *
27793  * This field holds the start address in the external memory from which the data
27794  * for
27795  *
27796  * the endpoint must be fetched or to which it must be stored. This register is
27797  *
27798  * incremented on every AHB transaction.
27799  *
27800  * Scatter-Gather DMA (DescDMA) Mode:
27801  *
27802  * [31:9] (Non Isoc) Non-Isochronous:
27803  *
27804  * [31:N] (Isoc) Isochronous:
27805  *
27806  * This field holds the start address of the 512 bytes
27807  *
27808  * page. The first descriptor in the list should be located
27809  *
27810  * in this address. The first descriptor may be or may
27811  *
27812  * not be ready. The core starts processing the list from
27813  *
27814  * the CTD value.
27815  *
27816  * This field holds the address of the 2*(nTD+1) bytes of
27817  *
27818  * locations in which the isochronous descriptors are
27819  *
27820  * present where N is based on nTD as per Table below
27821  *
27822  * [31:N] Base Address
27823  *
27824  * [N-1:3] Offset
27825  *
27826  * [2:0] 000
27827  *
27828  * HS ISOC
27829  *
27830  * nTD N
27831  *
27832  * 7 6
27833  *
27834  * 15 7
27835  *
27836  * 31 8
27837  *
27838  * 63 9
27839  *
27840  * 127 10
27841  *
27842  * 255 11
27843  *
27844  * FS ISOC
27845  *
27846  * nTD N
27847  *
27848  * 1 4
27849  *
27850  * 3 5
27851  *
27852  * 7 6
27853  *
27854  * 15 7
27855  *
27856  * 31 8
27857  *
27858  * 63 9
27859  *
27860  * [N-1:3] (Isoc):
27861  *
27862  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
27863  *
27864  * Non Isochronous:
27865  *
27866  * This value is in terms of number of descriptors. The values can be from 0 to 63.
27867  *
27868  * 0 - 1 descriptor.
27869  *
27870  * 63 - 64 descriptors.
27871  *
27872  * This field indicates the current descriptor processed in the list. This field is
27873  * updated
27874  *
27875  * both by application and the core. For example, if the application enables the
27876  *
27877  * channel after programming CTD=5, then the core will start processing the 6th
27878  *
27879  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
27880  *
27881  * to DMAAddr.
27882  *
27883  * Isochronous:
27884  *
27885  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
27886  * set
27887  *
27888  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
27889  *
27890  * [31:9] (Non Isoc) Non-Isochronous:
27891  *
27892  * [31:N] (Isoc) Isochronous:
27893  *
27894  * This field holds the start address of the 512 bytes
27895  *
27896  * page. The first descriptor in the list should be located
27897  *
27898  * in this address. The first descriptor may be or may
27899  *
27900  * not be ready. The core starts processing the list from
27901  *
27902  * the CTD value.
27903  *
27904  * This field holds the address of the 2*(nTD+1) bytes of
27905  *
27906  * locations in which the isochronous descriptors are
27907  *
27908  * present where N is based on nTD as per Table below
27909  *
27910  * [31:N] Base Address
27911  *
27912  * [N-1:3] Offset
27913  *
27914  * [2:0] 000
27915  *
27916  * HS ISOC
27917  *
27918  * nTD N
27919  *
27920  * 7 6
27921  *
27922  * 15 7
27923  *
27924  * 31 8
27925  *
27926  * 63 9
27927  *
27928  * 127 10
27929  *
27930  * 255 11
27931  *
27932  * FS ISOC
27933  *
27934  * nTD N
27935  *
27936  * 1 4
27937  *
27938  * 3 5
27939  *
27940  * 7 6
27941  *
27942  * 15 7
27943  *
27944  * 31 8
27945  *
27946  * 63 9
27947  *
27948  * [N-1:3] (Isoc):
27949  *
27950  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
27951  *
27952  * Non Isochronous:
27953  *
27954  * This value is in terms of number of descriptors. The values can be from 0 to 63.
27955  *
27956  * 0 - 1 descriptor.
27957  *
27958  * 63 - 64 descriptors.
27959  *
27960  * This field indicates the current descriptor processed in the list. This field is
27961  * updated
27962  *
27963  * both by application and the core. For example, if the application enables the
27964  *
27965  * channel after programming CTD=5, then the core will start processing the 6th
27966  *
27967  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
27968  *
27969  * to DMAAddr.
27970  *
27971  * Isochronous:
27972  *
27973  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
27974  * set
27975  *
27976  * to zero by application.
27977  *
27978  * Field Access Macros:
27979  *
27980  */
27981 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */
27982 #define ALT_USB_HOST_HCDMA3_HCDMA3_LSB 0
27983 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */
27984 #define ALT_USB_HOST_HCDMA3_HCDMA3_MSB 31
27985 /* The width in bits of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */
27986 #define ALT_USB_HOST_HCDMA3_HCDMA3_WIDTH 32
27987 /* The mask used to set the ALT_USB_HOST_HCDMA3_HCDMA3 register field value. */
27988 #define ALT_USB_HOST_HCDMA3_HCDMA3_SET_MSK 0xffffffff
27989 /* The mask used to clear the ALT_USB_HOST_HCDMA3_HCDMA3 register field value. */
27990 #define ALT_USB_HOST_HCDMA3_HCDMA3_CLR_MSK 0x00000000
27991 /* The reset value of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */
27992 #define ALT_USB_HOST_HCDMA3_HCDMA3_RESET 0x0
27993 /* Extracts the ALT_USB_HOST_HCDMA3_HCDMA3 field value from a register. */
27994 #define ALT_USB_HOST_HCDMA3_HCDMA3_GET(value) (((value) & 0xffffffff) >> 0)
27995 /* Produces a ALT_USB_HOST_HCDMA3_HCDMA3 register field value suitable for setting the register. */
27996 #define ALT_USB_HOST_HCDMA3_HCDMA3_SET(value) (((value) << 0) & 0xffffffff)
27997 
27998 #ifndef __ASSEMBLY__
27999 /*
28000  * WARNING: The C register and register group struct declarations are provided for
28001  * convenience and illustrative purposes. They should, however, be used with
28002  * caution as the C language standard provides no guarantees about the alignment or
28003  * atomicity of device memory accesses. The recommended practice for writing
28004  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28005  * alt_write_word() functions.
28006  *
28007  * The struct declaration for register ALT_USB_HOST_HCDMA3.
28008  */
28009 struct ALT_USB_HOST_HCDMA3_s
28010 {
28011  uint32_t hcdma3 : 32; /* ALT_USB_HOST_HCDMA3_HCDMA3 */
28012 };
28013 
28014 /* The typedef declaration for register ALT_USB_HOST_HCDMA3. */
28015 typedef volatile struct ALT_USB_HOST_HCDMA3_s ALT_USB_HOST_HCDMA3_t;
28016 #endif /* __ASSEMBLY__ */
28017 
28018 /* The reset value of the ALT_USB_HOST_HCDMA3 register. */
28019 #define ALT_USB_HOST_HCDMA3_RESET 0x00000000
28020 /* The byte offset of the ALT_USB_HOST_HCDMA3 register from the beginning of the component. */
28021 #define ALT_USB_HOST_HCDMA3_OFST 0x174
28022 /* The address of the ALT_USB_HOST_HCDMA3 register. */
28023 #define ALT_USB_HOST_HCDMA3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA3_OFST))
28024 
28025 /*
28026  * Register : hcdmab3
28027  *
28028  * Host Channel 3 DMA Buffer Address Register
28029  *
28030  * Register Layout
28031  *
28032  * Bits | Access | Reset | Description
28033  * :-------|:-------|:------|:-----------------------------
28034  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB3_HCDMAB3
28035  *
28036  */
28037 /*
28038  * Field : hcdmab3
28039  *
28040  * Holds the current buffer address.
28041  *
28042  * This register is updated as and when the data transfer for the corresponding end
28043  * point
28044  *
28045  * is in progress. This register is present only in Scatter/Gather DMA mode.
28046  * Otherwise this
28047  *
28048  * field is reserved.
28049  *
28050  * Field Access Macros:
28051  *
28052  */
28053 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */
28054 #define ALT_USB_HOST_HCDMAB3_HCDMAB3_LSB 0
28055 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */
28056 #define ALT_USB_HOST_HCDMAB3_HCDMAB3_MSB 31
28057 /* The width in bits of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */
28058 #define ALT_USB_HOST_HCDMAB3_HCDMAB3_WIDTH 32
28059 /* The mask used to set the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field value. */
28060 #define ALT_USB_HOST_HCDMAB3_HCDMAB3_SET_MSK 0xffffffff
28061 /* The mask used to clear the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field value. */
28062 #define ALT_USB_HOST_HCDMAB3_HCDMAB3_CLR_MSK 0x00000000
28063 /* The reset value of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */
28064 #define ALT_USB_HOST_HCDMAB3_HCDMAB3_RESET 0x0
28065 /* Extracts the ALT_USB_HOST_HCDMAB3_HCDMAB3 field value from a register. */
28066 #define ALT_USB_HOST_HCDMAB3_HCDMAB3_GET(value) (((value) & 0xffffffff) >> 0)
28067 /* Produces a ALT_USB_HOST_HCDMAB3_HCDMAB3 register field value suitable for setting the register. */
28068 #define ALT_USB_HOST_HCDMAB3_HCDMAB3_SET(value) (((value) << 0) & 0xffffffff)
28069 
28070 #ifndef __ASSEMBLY__
28071 /*
28072  * WARNING: The C register and register group struct declarations are provided for
28073  * convenience and illustrative purposes. They should, however, be used with
28074  * caution as the C language standard provides no guarantees about the alignment or
28075  * atomicity of device memory accesses. The recommended practice for writing
28076  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28077  * alt_write_word() functions.
28078  *
28079  * The struct declaration for register ALT_USB_HOST_HCDMAB3.
28080  */
28081 struct ALT_USB_HOST_HCDMAB3_s
28082 {
28083  uint32_t hcdmab3 : 32; /* ALT_USB_HOST_HCDMAB3_HCDMAB3 */
28084 };
28085 
28086 /* The typedef declaration for register ALT_USB_HOST_HCDMAB3. */
28087 typedef volatile struct ALT_USB_HOST_HCDMAB3_s ALT_USB_HOST_HCDMAB3_t;
28088 #endif /* __ASSEMBLY__ */
28089 
28090 /* The reset value of the ALT_USB_HOST_HCDMAB3 register. */
28091 #define ALT_USB_HOST_HCDMAB3_RESET 0x00000000
28092 /* The byte offset of the ALT_USB_HOST_HCDMAB3 register from the beginning of the component. */
28093 #define ALT_USB_HOST_HCDMAB3_OFST 0x17c
28094 /* The address of the ALT_USB_HOST_HCDMAB3 register. */
28095 #define ALT_USB_HOST_HCDMAB3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB3_OFST))
28096 
28097 /*
28098  * Register : hcchar4
28099  *
28100  * Host Channel 4 Characteristics Register
28101  *
28102  * Register Layout
28103  *
28104  * Bits | Access | Reset | Description
28105  * :-------|:-------|:------|:----------------------------------
28106  * [31:0] | RW | 0x0 | Host Channel 0 DMA Buffer Address
28107  *
28108  */
28109 /*
28110  * Field : Host Channel 0 DMA Buffer Address - hcdmab4
28111  *
28112  * These registers are present only in case of Scatter/Gather DMA. These
28113  * registers are implemented in RAM instead of flop-based implementation. Holds
28114  * the current buffer address. This register is updated as and when the data
28115  * transfer for the corresponding end point is in progress. This register is
28116  * present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
28117  *
28118  * Field Access Macros:
28119  *
28120  */
28121 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */
28122 #define ALT_USB_HOST_HCCHAR4_HCDMAB4_LSB 0
28123 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */
28124 #define ALT_USB_HOST_HCCHAR4_HCDMAB4_MSB 31
28125 /* The width in bits of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */
28126 #define ALT_USB_HOST_HCCHAR4_HCDMAB4_WIDTH 32
28127 /* The mask used to set the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field value. */
28128 #define ALT_USB_HOST_HCCHAR4_HCDMAB4_SET_MSK 0xffffffff
28129 /* The mask used to clear the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field value. */
28130 #define ALT_USB_HOST_HCCHAR4_HCDMAB4_CLR_MSK 0x00000000
28131 /* The reset value of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */
28132 #define ALT_USB_HOST_HCCHAR4_HCDMAB4_RESET 0x0
28133 /* Extracts the ALT_USB_HOST_HCCHAR4_HCDMAB4 field value from a register. */
28134 #define ALT_USB_HOST_HCCHAR4_HCDMAB4_GET(value) (((value) & 0xffffffff) >> 0)
28135 /* Produces a ALT_USB_HOST_HCCHAR4_HCDMAB4 register field value suitable for setting the register. */
28136 #define ALT_USB_HOST_HCCHAR4_HCDMAB4_SET(value) (((value) << 0) & 0xffffffff)
28137 
28138 #ifndef __ASSEMBLY__
28139 /*
28140  * WARNING: The C register and register group struct declarations are provided for
28141  * convenience and illustrative purposes. They should, however, be used with
28142  * caution as the C language standard provides no guarantees about the alignment or
28143  * atomicity of device memory accesses. The recommended practice for writing
28144  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28145  * alt_write_word() functions.
28146  *
28147  * The struct declaration for register ALT_USB_HOST_HCCHAR4.
28148  */
28149 struct ALT_USB_HOST_HCCHAR4_s
28150 {
28151  uint32_t hcdmab4 : 32; /* Host Channel 0 DMA Buffer Address */
28152 };
28153 
28154 /* The typedef declaration for register ALT_USB_HOST_HCCHAR4. */
28155 typedef volatile struct ALT_USB_HOST_HCCHAR4_s ALT_USB_HOST_HCCHAR4_t;
28156 #endif /* __ASSEMBLY__ */
28157 
28158 /* The reset value of the ALT_USB_HOST_HCCHAR4 register. */
28159 #define ALT_USB_HOST_HCCHAR4_RESET 0x00000000
28160 /* The byte offset of the ALT_USB_HOST_HCCHAR4 register from the beginning of the component. */
28161 #define ALT_USB_HOST_HCCHAR4_OFST 0x180
28162 /* The address of the ALT_USB_HOST_HCCHAR4 register. */
28163 #define ALT_USB_HOST_HCCHAR4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR4_OFST))
28164 
28165 /*
28166  * Register : hcsplt4
28167  *
28168  * Host Channel 4 Split Control Register
28169  *
28170  * Register Layout
28171  *
28172  * Bits | Access | Reset | Description
28173  * :--------|:-------|:------|:------------------------------
28174  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT4_PRTADDR
28175  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT4_HUBADDR
28176  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT4_XACTPOS
28177  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT4_COMPSPLT
28178  * [30:17] | ??? | 0x0 | *UNDEFINED*
28179  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT4_SPLTENA
28180  *
28181  */
28182 /*
28183  * Field : prtaddr
28184  *
28185  * Port Address (PrtAddr)
28186  *
28187  * This field is the port number of the recipient transaction
28188  *
28189  * translator.
28190  *
28191  * Field Access Macros:
28192  *
28193  */
28194 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */
28195 #define ALT_USB_HOST_HCSPLT4_PRTADDR_LSB 0
28196 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */
28197 #define ALT_USB_HOST_HCSPLT4_PRTADDR_MSB 6
28198 /* The width in bits of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */
28199 #define ALT_USB_HOST_HCSPLT4_PRTADDR_WIDTH 7
28200 /* The mask used to set the ALT_USB_HOST_HCSPLT4_PRTADDR register field value. */
28201 #define ALT_USB_HOST_HCSPLT4_PRTADDR_SET_MSK 0x0000007f
28202 /* The mask used to clear the ALT_USB_HOST_HCSPLT4_PRTADDR register field value. */
28203 #define ALT_USB_HOST_HCSPLT4_PRTADDR_CLR_MSK 0xffffff80
28204 /* The reset value of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */
28205 #define ALT_USB_HOST_HCSPLT4_PRTADDR_RESET 0x0
28206 /* Extracts the ALT_USB_HOST_HCSPLT4_PRTADDR field value from a register. */
28207 #define ALT_USB_HOST_HCSPLT4_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
28208 /* Produces a ALT_USB_HOST_HCSPLT4_PRTADDR register field value suitable for setting the register. */
28209 #define ALT_USB_HOST_HCSPLT4_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
28210 
28211 /*
28212  * Field : hubaddr
28213  *
28214  * Hub Address (HubAddr)
28215  *
28216  * This field holds the device address of the transaction translator's
28217  *
28218  * hub.
28219  *
28220  * Field Access Macros:
28221  *
28222  */
28223 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */
28224 #define ALT_USB_HOST_HCSPLT4_HUBADDR_LSB 7
28225 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */
28226 #define ALT_USB_HOST_HCSPLT4_HUBADDR_MSB 13
28227 /* The width in bits of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */
28228 #define ALT_USB_HOST_HCSPLT4_HUBADDR_WIDTH 7
28229 /* The mask used to set the ALT_USB_HOST_HCSPLT4_HUBADDR register field value. */
28230 #define ALT_USB_HOST_HCSPLT4_HUBADDR_SET_MSK 0x00003f80
28231 /* The mask used to clear the ALT_USB_HOST_HCSPLT4_HUBADDR register field value. */
28232 #define ALT_USB_HOST_HCSPLT4_HUBADDR_CLR_MSK 0xffffc07f
28233 /* The reset value of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */
28234 #define ALT_USB_HOST_HCSPLT4_HUBADDR_RESET 0x0
28235 /* Extracts the ALT_USB_HOST_HCSPLT4_HUBADDR field value from a register. */
28236 #define ALT_USB_HOST_HCSPLT4_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
28237 /* Produces a ALT_USB_HOST_HCSPLT4_HUBADDR register field value suitable for setting the register. */
28238 #define ALT_USB_HOST_HCSPLT4_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
28239 
28240 /*
28241  * Field : xactpos
28242  *
28243  * Transaction Position (XactPos)
28244  *
28245  * This field is used to determine whether to send all, first, middle,
28246  *
28247  * or last payloads with each OUT transaction.
28248  *
28249  * 2'b11: All. This is the entire data payload is of this transaction
28250  *
28251  * (which is less than or equal to 188 bytes).
28252  *
28253  * 2'b10: Begin. This is the first data payload of this transaction
28254  *
28255  * (which is larger than 188 bytes).
28256  *
28257  * 2'b00: Mid. This is the middle payload of this transaction
28258  *
28259  * (which is larger than 188 bytes).
28260  *
28261  * 2'b01: End. This is the last payload of this transaction (which
28262  *
28263  * is larger than 188 bytes).
28264  *
28265  * Field Enumeration Values:
28266  *
28267  * Enum | Value | Description
28268  * :--------------------------------------|:------|:------------------------------------------------
28269  * ALT_USB_HOST_HCSPLT4_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
28270  * : | | transaction (which is larger than 188 bytes)
28271  * ALT_USB_HOST_HCSPLT4_XACTPOS_E_END | 0x1 | End. This is the last payload of this
28272  * : | | transaction (which is larger than 188 bytes)
28273  * ALT_USB_HOST_HCSPLT4_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
28274  * : | | transaction (which is larger than 188 bytes)
28275  * ALT_USB_HOST_HCSPLT4_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
28276  * : | | transaction (which is less than or equal to 188
28277  * : | | bytes)
28278  *
28279  * Field Access Macros:
28280  *
28281  */
28282 /*
28283  * Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS
28284  *
28285  * Mid. This is the middle payload of this transaction (which is larger than 188
28286  * bytes)
28287  */
28288 #define ALT_USB_HOST_HCSPLT4_XACTPOS_E_MIDDLE 0x0
28289 /*
28290  * Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS
28291  *
28292  * End. This is the last payload of this transaction (which is larger than 188
28293  * bytes)
28294  */
28295 #define ALT_USB_HOST_HCSPLT4_XACTPOS_E_END 0x1
28296 /*
28297  * Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS
28298  *
28299  * Begin. This is the first data payload of this transaction (which is larger than
28300  * 188 bytes)
28301  */
28302 #define ALT_USB_HOST_HCSPLT4_XACTPOS_E_BEGIN 0x2
28303 /*
28304  * Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS
28305  *
28306  * All. This is the entire data payload is of this transaction (which is less than
28307  * or equal to 188 bytes)
28308  */
28309 #define ALT_USB_HOST_HCSPLT4_XACTPOS_E_ALL 0x3
28310 
28311 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */
28312 #define ALT_USB_HOST_HCSPLT4_XACTPOS_LSB 14
28313 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */
28314 #define ALT_USB_HOST_HCSPLT4_XACTPOS_MSB 15
28315 /* The width in bits of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */
28316 #define ALT_USB_HOST_HCSPLT4_XACTPOS_WIDTH 2
28317 /* The mask used to set the ALT_USB_HOST_HCSPLT4_XACTPOS register field value. */
28318 #define ALT_USB_HOST_HCSPLT4_XACTPOS_SET_MSK 0x0000c000
28319 /* The mask used to clear the ALT_USB_HOST_HCSPLT4_XACTPOS register field value. */
28320 #define ALT_USB_HOST_HCSPLT4_XACTPOS_CLR_MSK 0xffff3fff
28321 /* The reset value of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */
28322 #define ALT_USB_HOST_HCSPLT4_XACTPOS_RESET 0x0
28323 /* Extracts the ALT_USB_HOST_HCSPLT4_XACTPOS field value from a register. */
28324 #define ALT_USB_HOST_HCSPLT4_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
28325 /* Produces a ALT_USB_HOST_HCSPLT4_XACTPOS register field value suitable for setting the register. */
28326 #define ALT_USB_HOST_HCSPLT4_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
28327 
28328 /*
28329  * Field : compsplt
28330  *
28331  * Do Complete Split (CompSplt)
28332  *
28333  * The application sets this field to request the OTG host to perform
28334  *
28335  * a complete split transaction.
28336  *
28337  * Field Enumeration Values:
28338  *
28339  * Enum | Value | Description
28340  * :----------------------------------------|:------|:---------------------
28341  * ALT_USB_HOST_HCSPLT4_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
28342  * ALT_USB_HOST_HCSPLT4_COMPSPLT_E_SPLIT | 0x1 | Split transaction
28343  *
28344  * Field Access Macros:
28345  *
28346  */
28347 /*
28348  * Enumerated value for register field ALT_USB_HOST_HCSPLT4_COMPSPLT
28349  *
28350  * No split transaction
28351  */
28352 #define ALT_USB_HOST_HCSPLT4_COMPSPLT_E_NOSPLIT 0x0
28353 /*
28354  * Enumerated value for register field ALT_USB_HOST_HCSPLT4_COMPSPLT
28355  *
28356  * Split transaction
28357  */
28358 #define ALT_USB_HOST_HCSPLT4_COMPSPLT_E_SPLIT 0x1
28359 
28360 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */
28361 #define ALT_USB_HOST_HCSPLT4_COMPSPLT_LSB 16
28362 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */
28363 #define ALT_USB_HOST_HCSPLT4_COMPSPLT_MSB 16
28364 /* The width in bits of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */
28365 #define ALT_USB_HOST_HCSPLT4_COMPSPLT_WIDTH 1
28366 /* The mask used to set the ALT_USB_HOST_HCSPLT4_COMPSPLT register field value. */
28367 #define ALT_USB_HOST_HCSPLT4_COMPSPLT_SET_MSK 0x00010000
28368 /* The mask used to clear the ALT_USB_HOST_HCSPLT4_COMPSPLT register field value. */
28369 #define ALT_USB_HOST_HCSPLT4_COMPSPLT_CLR_MSK 0xfffeffff
28370 /* The reset value of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */
28371 #define ALT_USB_HOST_HCSPLT4_COMPSPLT_RESET 0x0
28372 /* Extracts the ALT_USB_HOST_HCSPLT4_COMPSPLT field value from a register. */
28373 #define ALT_USB_HOST_HCSPLT4_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
28374 /* Produces a ALT_USB_HOST_HCSPLT4_COMPSPLT register field value suitable for setting the register. */
28375 #define ALT_USB_HOST_HCSPLT4_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
28376 
28377 /*
28378  * Field : spltena
28379  *
28380  * Split Enable (SpltEna)
28381  *
28382  * The application sets this field to indicate that this channel is
28383  *
28384  * enabled to perform split transactions.
28385  *
28386  * Field Enumeration Values:
28387  *
28388  * Enum | Value | Description
28389  * :------------------------------------|:------|:------------------
28390  * ALT_USB_HOST_HCSPLT4_SPLTENA_E_DISD | 0x0 | Split not enabled
28391  * ALT_USB_HOST_HCSPLT4_SPLTENA_E_END | 0x1 | Split enabled
28392  *
28393  * Field Access Macros:
28394  *
28395  */
28396 /*
28397  * Enumerated value for register field ALT_USB_HOST_HCSPLT4_SPLTENA
28398  *
28399  * Split not enabled
28400  */
28401 #define ALT_USB_HOST_HCSPLT4_SPLTENA_E_DISD 0x0
28402 /*
28403  * Enumerated value for register field ALT_USB_HOST_HCSPLT4_SPLTENA
28404  *
28405  * Split enabled
28406  */
28407 #define ALT_USB_HOST_HCSPLT4_SPLTENA_E_END 0x1
28408 
28409 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */
28410 #define ALT_USB_HOST_HCSPLT4_SPLTENA_LSB 31
28411 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */
28412 #define ALT_USB_HOST_HCSPLT4_SPLTENA_MSB 31
28413 /* The width in bits of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */
28414 #define ALT_USB_HOST_HCSPLT4_SPLTENA_WIDTH 1
28415 /* The mask used to set the ALT_USB_HOST_HCSPLT4_SPLTENA register field value. */
28416 #define ALT_USB_HOST_HCSPLT4_SPLTENA_SET_MSK 0x80000000
28417 /* The mask used to clear the ALT_USB_HOST_HCSPLT4_SPLTENA register field value. */
28418 #define ALT_USB_HOST_HCSPLT4_SPLTENA_CLR_MSK 0x7fffffff
28419 /* The reset value of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */
28420 #define ALT_USB_HOST_HCSPLT4_SPLTENA_RESET 0x0
28421 /* Extracts the ALT_USB_HOST_HCSPLT4_SPLTENA field value from a register. */
28422 #define ALT_USB_HOST_HCSPLT4_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
28423 /* Produces a ALT_USB_HOST_HCSPLT4_SPLTENA register field value suitable for setting the register. */
28424 #define ALT_USB_HOST_HCSPLT4_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
28425 
28426 #ifndef __ASSEMBLY__
28427 /*
28428  * WARNING: The C register and register group struct declarations are provided for
28429  * convenience and illustrative purposes. They should, however, be used with
28430  * caution as the C language standard provides no guarantees about the alignment or
28431  * atomicity of device memory accesses. The recommended practice for writing
28432  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28433  * alt_write_word() functions.
28434  *
28435  * The struct declaration for register ALT_USB_HOST_HCSPLT4.
28436  */
28437 struct ALT_USB_HOST_HCSPLT4_s
28438 {
28439  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT4_PRTADDR */
28440  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT4_HUBADDR */
28441  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT4_XACTPOS */
28442  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT4_COMPSPLT */
28443  uint32_t : 14; /* *UNDEFINED* */
28444  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT4_SPLTENA */
28445 };
28446 
28447 /* The typedef declaration for register ALT_USB_HOST_HCSPLT4. */
28448 typedef volatile struct ALT_USB_HOST_HCSPLT4_s ALT_USB_HOST_HCSPLT4_t;
28449 #endif /* __ASSEMBLY__ */
28450 
28451 /* The reset value of the ALT_USB_HOST_HCSPLT4 register. */
28452 #define ALT_USB_HOST_HCSPLT4_RESET 0x00000000
28453 /* The byte offset of the ALT_USB_HOST_HCSPLT4 register from the beginning of the component. */
28454 #define ALT_USB_HOST_HCSPLT4_OFST 0x184
28455 /* The address of the ALT_USB_HOST_HCSPLT4 register. */
28456 #define ALT_USB_HOST_HCSPLT4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT4_OFST))
28457 
28458 /*
28459  * Register : hcint4
28460  *
28461  * Host Channel 4 Interrupt Register
28462  *
28463  * Register Layout
28464  *
28465  * Bits | Access | Reset | Description
28466  * :--------|:-------|:------|:--------------------------------------
28467  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT4_XFERCOMPL
28468  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT4_CHHLTD
28469  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT4_AHBERR
28470  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT4_STALL
28471  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT4_NAK
28472  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT4_ACK
28473  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT4_NYET
28474  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT4_XACTERR
28475  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT4_BBLERR
28476  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT4_FRMOVRUN
28477  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT4_DATATGLERR
28478  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT4_BNAINTR
28479  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT4_XCS_XACT_ERR
28480  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR
28481  * [31:14] | ??? | 0x0 | *UNDEFINED*
28482  *
28483  */
28484 /*
28485  * Field : xfercompl
28486  *
28487  * Transfer Completed (XferCompl)
28488  *
28489  * Transfer completed normally without any errors.This bit can be set only by the
28490  * core and the application should write 1 to clear it.
28491  *
28492  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
28493  *
28494  * completed with IOC bit set in its descriptor.
28495  *
28496  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
28497  * without
28498  *
28499  * any errors.
28500  *
28501  * Field Enumeration Values:
28502  *
28503  * Enum | Value | Description
28504  * :--------------------------------------|:------|:-----------------------------------------------
28505  * ALT_USB_HOST_HCINT4_XFERCOMPL_E_INACT | 0x0 | No transfer
28506  * ALT_USB_HOST_HCINT4_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
28507  *
28508  * Field Access Macros:
28509  *
28510  */
28511 /*
28512  * Enumerated value for register field ALT_USB_HOST_HCINT4_XFERCOMPL
28513  *
28514  * No transfer
28515  */
28516 #define ALT_USB_HOST_HCINT4_XFERCOMPL_E_INACT 0x0
28517 /*
28518  * Enumerated value for register field ALT_USB_HOST_HCINT4_XFERCOMPL
28519  *
28520  * Transfer completed normally without any errors
28521  */
28522 #define ALT_USB_HOST_HCINT4_XFERCOMPL_E_ACT 0x1
28523 
28524 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */
28525 #define ALT_USB_HOST_HCINT4_XFERCOMPL_LSB 0
28526 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */
28527 #define ALT_USB_HOST_HCINT4_XFERCOMPL_MSB 0
28528 /* The width in bits of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */
28529 #define ALT_USB_HOST_HCINT4_XFERCOMPL_WIDTH 1
28530 /* The mask used to set the ALT_USB_HOST_HCINT4_XFERCOMPL register field value. */
28531 #define ALT_USB_HOST_HCINT4_XFERCOMPL_SET_MSK 0x00000001
28532 /* The mask used to clear the ALT_USB_HOST_HCINT4_XFERCOMPL register field value. */
28533 #define ALT_USB_HOST_HCINT4_XFERCOMPL_CLR_MSK 0xfffffffe
28534 /* The reset value of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */
28535 #define ALT_USB_HOST_HCINT4_XFERCOMPL_RESET 0x0
28536 /* Extracts the ALT_USB_HOST_HCINT4_XFERCOMPL field value from a register. */
28537 #define ALT_USB_HOST_HCINT4_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
28538 /* Produces a ALT_USB_HOST_HCINT4_XFERCOMPL register field value suitable for setting the register. */
28539 #define ALT_USB_HOST_HCINT4_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
28540 
28541 /*
28542  * Field : chhltd
28543  *
28544  * Channel Halted (ChHltd)
28545  *
28546  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
28547  * either because of any USB transaction error or in response to disable request by
28548  * the application or because of a completed transfer.
28549  *
28550  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
28551  * the following
28552  *
28553  * . EOL being set in descriptor
28554  *
28555  * . AHB error
28556  *
28557  * . Excessive transaction errors
28558  *
28559  * . Babble
28560  *
28561  * . Stall
28562  *
28563  * Field Enumeration Values:
28564  *
28565  * Enum | Value | Description
28566  * :-----------------------------------|:------|:-------------------
28567  * ALT_USB_HOST_HCINT4_CHHLTD_E_INACT | 0x0 | Channel not halted
28568  * ALT_USB_HOST_HCINT4_CHHLTD_E_ACT | 0x1 | Channel Halted
28569  *
28570  * Field Access Macros:
28571  *
28572  */
28573 /*
28574  * Enumerated value for register field ALT_USB_HOST_HCINT4_CHHLTD
28575  *
28576  * Channel not halted
28577  */
28578 #define ALT_USB_HOST_HCINT4_CHHLTD_E_INACT 0x0
28579 /*
28580  * Enumerated value for register field ALT_USB_HOST_HCINT4_CHHLTD
28581  *
28582  * Channel Halted
28583  */
28584 #define ALT_USB_HOST_HCINT4_CHHLTD_E_ACT 0x1
28585 
28586 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_CHHLTD register field. */
28587 #define ALT_USB_HOST_HCINT4_CHHLTD_LSB 1
28588 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_CHHLTD register field. */
28589 #define ALT_USB_HOST_HCINT4_CHHLTD_MSB 1
28590 /* The width in bits of the ALT_USB_HOST_HCINT4_CHHLTD register field. */
28591 #define ALT_USB_HOST_HCINT4_CHHLTD_WIDTH 1
28592 /* The mask used to set the ALT_USB_HOST_HCINT4_CHHLTD register field value. */
28593 #define ALT_USB_HOST_HCINT4_CHHLTD_SET_MSK 0x00000002
28594 /* The mask used to clear the ALT_USB_HOST_HCINT4_CHHLTD register field value. */
28595 #define ALT_USB_HOST_HCINT4_CHHLTD_CLR_MSK 0xfffffffd
28596 /* The reset value of the ALT_USB_HOST_HCINT4_CHHLTD register field. */
28597 #define ALT_USB_HOST_HCINT4_CHHLTD_RESET 0x0
28598 /* Extracts the ALT_USB_HOST_HCINT4_CHHLTD field value from a register. */
28599 #define ALT_USB_HOST_HCINT4_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
28600 /* Produces a ALT_USB_HOST_HCINT4_CHHLTD register field value suitable for setting the register. */
28601 #define ALT_USB_HOST_HCINT4_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
28602 
28603 /*
28604  * Field : ahberr
28605  *
28606  * AHB Error (AHBErr)
28607  *
28608  * This is generated only in Internal DMA mode when there is an
28609  *
28610  * AHB error during AHB read/write. The application can read the
28611  *
28612  * corresponding channel's DMA address register to get the error
28613  *
28614  * address.
28615  *
28616  * Field Enumeration Values:
28617  *
28618  * Enum | Value | Description
28619  * :-----------------------------------|:------|:--------------------------------
28620  * ALT_USB_HOST_HCINT4_AHBERR_E_INACT | 0x0 | No AHB error
28621  * ALT_USB_HOST_HCINT4_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
28622  *
28623  * Field Access Macros:
28624  *
28625  */
28626 /*
28627  * Enumerated value for register field ALT_USB_HOST_HCINT4_AHBERR
28628  *
28629  * No AHB error
28630  */
28631 #define ALT_USB_HOST_HCINT4_AHBERR_E_INACT 0x0
28632 /*
28633  * Enumerated value for register field ALT_USB_HOST_HCINT4_AHBERR
28634  *
28635  * AHB error during AHB read/write
28636  */
28637 #define ALT_USB_HOST_HCINT4_AHBERR_E_ACT 0x1
28638 
28639 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_AHBERR register field. */
28640 #define ALT_USB_HOST_HCINT4_AHBERR_LSB 2
28641 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_AHBERR register field. */
28642 #define ALT_USB_HOST_HCINT4_AHBERR_MSB 2
28643 /* The width in bits of the ALT_USB_HOST_HCINT4_AHBERR register field. */
28644 #define ALT_USB_HOST_HCINT4_AHBERR_WIDTH 1
28645 /* The mask used to set the ALT_USB_HOST_HCINT4_AHBERR register field value. */
28646 #define ALT_USB_HOST_HCINT4_AHBERR_SET_MSK 0x00000004
28647 /* The mask used to clear the ALT_USB_HOST_HCINT4_AHBERR register field value. */
28648 #define ALT_USB_HOST_HCINT4_AHBERR_CLR_MSK 0xfffffffb
28649 /* The reset value of the ALT_USB_HOST_HCINT4_AHBERR register field. */
28650 #define ALT_USB_HOST_HCINT4_AHBERR_RESET 0x0
28651 /* Extracts the ALT_USB_HOST_HCINT4_AHBERR field value from a register. */
28652 #define ALT_USB_HOST_HCINT4_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
28653 /* Produces a ALT_USB_HOST_HCINT4_AHBERR register field value suitable for setting the register. */
28654 #define ALT_USB_HOST_HCINT4_AHBERR_SET(value) (((value) << 2) & 0x00000004)
28655 
28656 /*
28657  * Field : stall
28658  *
28659  * STALL Response Received Interrupt (STALL)
28660  *
28661  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
28662  *
28663  * in the core.This bit can be set only by the core and the application should
28664  * write 1 to clear
28665  *
28666  * it.
28667  *
28668  * Field Enumeration Values:
28669  *
28670  * Enum | Value | Description
28671  * :----------------------------------|:------|:-------------------
28672  * ALT_USB_HOST_HCINT4_STALL_E_INACT | 0x0 | No Stall Interrupt
28673  * ALT_USB_HOST_HCINT4_STALL_E_ACT | 0x1 | Stall Interrupt
28674  *
28675  * Field Access Macros:
28676  *
28677  */
28678 /*
28679  * Enumerated value for register field ALT_USB_HOST_HCINT4_STALL
28680  *
28681  * No Stall Interrupt
28682  */
28683 #define ALT_USB_HOST_HCINT4_STALL_E_INACT 0x0
28684 /*
28685  * Enumerated value for register field ALT_USB_HOST_HCINT4_STALL
28686  *
28687  * Stall Interrupt
28688  */
28689 #define ALT_USB_HOST_HCINT4_STALL_E_ACT 0x1
28690 
28691 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_STALL register field. */
28692 #define ALT_USB_HOST_HCINT4_STALL_LSB 3
28693 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_STALL register field. */
28694 #define ALT_USB_HOST_HCINT4_STALL_MSB 3
28695 /* The width in bits of the ALT_USB_HOST_HCINT4_STALL register field. */
28696 #define ALT_USB_HOST_HCINT4_STALL_WIDTH 1
28697 /* The mask used to set the ALT_USB_HOST_HCINT4_STALL register field value. */
28698 #define ALT_USB_HOST_HCINT4_STALL_SET_MSK 0x00000008
28699 /* The mask used to clear the ALT_USB_HOST_HCINT4_STALL register field value. */
28700 #define ALT_USB_HOST_HCINT4_STALL_CLR_MSK 0xfffffff7
28701 /* The reset value of the ALT_USB_HOST_HCINT4_STALL register field. */
28702 #define ALT_USB_HOST_HCINT4_STALL_RESET 0x0
28703 /* Extracts the ALT_USB_HOST_HCINT4_STALL field value from a register. */
28704 #define ALT_USB_HOST_HCINT4_STALL_GET(value) (((value) & 0x00000008) >> 3)
28705 /* Produces a ALT_USB_HOST_HCINT4_STALL register field value suitable for setting the register. */
28706 #define ALT_USB_HOST_HCINT4_STALL_SET(value) (((value) << 3) & 0x00000008)
28707 
28708 /*
28709  * Field : nak
28710  *
28711  * NAK Response Received Interrupt (NAK)
28712  *
28713  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
28714  *
28715  * in the core.This bit can be set only by the core and the application should
28716  * write 1 to clear
28717  *
28718  * it.
28719  *
28720  * Field Enumeration Values:
28721  *
28722  * Enum | Value | Description
28723  * :--------------------------------|:------|:-----------------------------------
28724  * ALT_USB_HOST_HCINT4_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
28725  * ALT_USB_HOST_HCINT4_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
28726  *
28727  * Field Access Macros:
28728  *
28729  */
28730 /*
28731  * Enumerated value for register field ALT_USB_HOST_HCINT4_NAK
28732  *
28733  * No NAK Response Received Interrupt
28734  */
28735 #define ALT_USB_HOST_HCINT4_NAK_E_INACT 0x0
28736 /*
28737  * Enumerated value for register field ALT_USB_HOST_HCINT4_NAK
28738  *
28739  * NAK Response Received Interrupt
28740  */
28741 #define ALT_USB_HOST_HCINT4_NAK_E_ACT 0x1
28742 
28743 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_NAK register field. */
28744 #define ALT_USB_HOST_HCINT4_NAK_LSB 4
28745 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_NAK register field. */
28746 #define ALT_USB_HOST_HCINT4_NAK_MSB 4
28747 /* The width in bits of the ALT_USB_HOST_HCINT4_NAK register field. */
28748 #define ALT_USB_HOST_HCINT4_NAK_WIDTH 1
28749 /* The mask used to set the ALT_USB_HOST_HCINT4_NAK register field value. */
28750 #define ALT_USB_HOST_HCINT4_NAK_SET_MSK 0x00000010
28751 /* The mask used to clear the ALT_USB_HOST_HCINT4_NAK register field value. */
28752 #define ALT_USB_HOST_HCINT4_NAK_CLR_MSK 0xffffffef
28753 /* The reset value of the ALT_USB_HOST_HCINT4_NAK register field. */
28754 #define ALT_USB_HOST_HCINT4_NAK_RESET 0x0
28755 /* Extracts the ALT_USB_HOST_HCINT4_NAK field value from a register. */
28756 #define ALT_USB_HOST_HCINT4_NAK_GET(value) (((value) & 0x00000010) >> 4)
28757 /* Produces a ALT_USB_HOST_HCINT4_NAK register field value suitable for setting the register. */
28758 #define ALT_USB_HOST_HCINT4_NAK_SET(value) (((value) << 4) & 0x00000010)
28759 
28760 /*
28761  * Field : ack
28762  *
28763  * ACK Response Received/Transmitted Interrupt (ACK)
28764  *
28765  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
28766  *
28767  * in the core.This bit can be set only by the core and the application should
28768  * write 1 to clear
28769  *
28770  * it.
28771  *
28772  * Field Enumeration Values:
28773  *
28774  * Enum | Value | Description
28775  * :--------------------------------|:------|:-----------------------------------------------
28776  * ALT_USB_HOST_HCINT4_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
28777  * ALT_USB_HOST_HCINT4_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
28778  *
28779  * Field Access Macros:
28780  *
28781  */
28782 /*
28783  * Enumerated value for register field ALT_USB_HOST_HCINT4_ACK
28784  *
28785  * No ACK Response Received Transmitted Interrupt
28786  */
28787 #define ALT_USB_HOST_HCINT4_ACK_E_INACT 0x0
28788 /*
28789  * Enumerated value for register field ALT_USB_HOST_HCINT4_ACK
28790  *
28791  * ACK Response Received Transmitted Interrup
28792  */
28793 #define ALT_USB_HOST_HCINT4_ACK_E_ACT 0x1
28794 
28795 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_ACK register field. */
28796 #define ALT_USB_HOST_HCINT4_ACK_LSB 5
28797 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_ACK register field. */
28798 #define ALT_USB_HOST_HCINT4_ACK_MSB 5
28799 /* The width in bits of the ALT_USB_HOST_HCINT4_ACK register field. */
28800 #define ALT_USB_HOST_HCINT4_ACK_WIDTH 1
28801 /* The mask used to set the ALT_USB_HOST_HCINT4_ACK register field value. */
28802 #define ALT_USB_HOST_HCINT4_ACK_SET_MSK 0x00000020
28803 /* The mask used to clear the ALT_USB_HOST_HCINT4_ACK register field value. */
28804 #define ALT_USB_HOST_HCINT4_ACK_CLR_MSK 0xffffffdf
28805 /* The reset value of the ALT_USB_HOST_HCINT4_ACK register field. */
28806 #define ALT_USB_HOST_HCINT4_ACK_RESET 0x0
28807 /* Extracts the ALT_USB_HOST_HCINT4_ACK field value from a register. */
28808 #define ALT_USB_HOST_HCINT4_ACK_GET(value) (((value) & 0x00000020) >> 5)
28809 /* Produces a ALT_USB_HOST_HCINT4_ACK register field value suitable for setting the register. */
28810 #define ALT_USB_HOST_HCINT4_ACK_SET(value) (((value) << 5) & 0x00000020)
28811 
28812 /*
28813  * Field : nyet
28814  *
28815  * NYET Response Received Interrupt (NYET)
28816  *
28817  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
28818  *
28819  * in the core.This bit can be set only by the core and the application should
28820  * write 1 to clear
28821  *
28822  * it.
28823  *
28824  * Field Enumeration Values:
28825  *
28826  * Enum | Value | Description
28827  * :---------------------------------|:------|:------------------------------------
28828  * ALT_USB_HOST_HCINT4_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
28829  * ALT_USB_HOST_HCINT4_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
28830  *
28831  * Field Access Macros:
28832  *
28833  */
28834 /*
28835  * Enumerated value for register field ALT_USB_HOST_HCINT4_NYET
28836  *
28837  * No NYET Response Received Interrupt
28838  */
28839 #define ALT_USB_HOST_HCINT4_NYET_E_INACT 0x0
28840 /*
28841  * Enumerated value for register field ALT_USB_HOST_HCINT4_NYET
28842  *
28843  * NYET Response Received Interrupt
28844  */
28845 #define ALT_USB_HOST_HCINT4_NYET_E_ACT 0x1
28846 
28847 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_NYET register field. */
28848 #define ALT_USB_HOST_HCINT4_NYET_LSB 6
28849 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_NYET register field. */
28850 #define ALT_USB_HOST_HCINT4_NYET_MSB 6
28851 /* The width in bits of the ALT_USB_HOST_HCINT4_NYET register field. */
28852 #define ALT_USB_HOST_HCINT4_NYET_WIDTH 1
28853 /* The mask used to set the ALT_USB_HOST_HCINT4_NYET register field value. */
28854 #define ALT_USB_HOST_HCINT4_NYET_SET_MSK 0x00000040
28855 /* The mask used to clear the ALT_USB_HOST_HCINT4_NYET register field value. */
28856 #define ALT_USB_HOST_HCINT4_NYET_CLR_MSK 0xffffffbf
28857 /* The reset value of the ALT_USB_HOST_HCINT4_NYET register field. */
28858 #define ALT_USB_HOST_HCINT4_NYET_RESET 0x0
28859 /* Extracts the ALT_USB_HOST_HCINT4_NYET field value from a register. */
28860 #define ALT_USB_HOST_HCINT4_NYET_GET(value) (((value) & 0x00000040) >> 6)
28861 /* Produces a ALT_USB_HOST_HCINT4_NYET register field value suitable for setting the register. */
28862 #define ALT_USB_HOST_HCINT4_NYET_SET(value) (((value) << 6) & 0x00000040)
28863 
28864 /*
28865  * Field : xacterr
28866  *
28867  * Transaction Error (XactErr)
28868  *
28869  * Indicates one of the following errors occurred on the USB.
28870  *
28871  * CRC check failure
28872  *
28873  * Timeout
28874  *
28875  * Bit stuff error
28876  *
28877  * False EOP
28878  *
28879  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
28880  *
28881  * in the core.This bit can be set only by the core and the application should
28882  * write 1 to clear
28883  *
28884  * it.
28885  *
28886  * Field Enumeration Values:
28887  *
28888  * Enum | Value | Description
28889  * :------------------------------------|:------|:---------------------
28890  * ALT_USB_HOST_HCINT4_XACTERR_E_INACT | 0x0 | No Transaction Error
28891  * ALT_USB_HOST_HCINT4_XACTERR_E_ACT | 0x1 | Transaction Error
28892  *
28893  * Field Access Macros:
28894  *
28895  */
28896 /*
28897  * Enumerated value for register field ALT_USB_HOST_HCINT4_XACTERR
28898  *
28899  * No Transaction Error
28900  */
28901 #define ALT_USB_HOST_HCINT4_XACTERR_E_INACT 0x0
28902 /*
28903  * Enumerated value for register field ALT_USB_HOST_HCINT4_XACTERR
28904  *
28905  * Transaction Error
28906  */
28907 #define ALT_USB_HOST_HCINT4_XACTERR_E_ACT 0x1
28908 
28909 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_XACTERR register field. */
28910 #define ALT_USB_HOST_HCINT4_XACTERR_LSB 7
28911 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_XACTERR register field. */
28912 #define ALT_USB_HOST_HCINT4_XACTERR_MSB 7
28913 /* The width in bits of the ALT_USB_HOST_HCINT4_XACTERR register field. */
28914 #define ALT_USB_HOST_HCINT4_XACTERR_WIDTH 1
28915 /* The mask used to set the ALT_USB_HOST_HCINT4_XACTERR register field value. */
28916 #define ALT_USB_HOST_HCINT4_XACTERR_SET_MSK 0x00000080
28917 /* The mask used to clear the ALT_USB_HOST_HCINT4_XACTERR register field value. */
28918 #define ALT_USB_HOST_HCINT4_XACTERR_CLR_MSK 0xffffff7f
28919 /* The reset value of the ALT_USB_HOST_HCINT4_XACTERR register field. */
28920 #define ALT_USB_HOST_HCINT4_XACTERR_RESET 0x0
28921 /* Extracts the ALT_USB_HOST_HCINT4_XACTERR field value from a register. */
28922 #define ALT_USB_HOST_HCINT4_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
28923 /* Produces a ALT_USB_HOST_HCINT4_XACTERR register field value suitable for setting the register. */
28924 #define ALT_USB_HOST_HCINT4_XACTERR_SET(value) (((value) << 7) & 0x00000080)
28925 
28926 /*
28927  * Field : bblerr
28928  *
28929  * Babble Error (BblErr)
28930  *
28931  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
28932  *
28933  * in the core..This bit can be set only by the core and the application should
28934  * write 1 to clear
28935  *
28936  * it.
28937  *
28938  * Field Enumeration Values:
28939  *
28940  * Enum | Value | Description
28941  * :-----------------------------------|:------|:----------------
28942  * ALT_USB_HOST_HCINT4_BBLERR_E_INACT | 0x0 | No Babble Error
28943  * ALT_USB_HOST_HCINT4_BBLERR_E_ACT | 0x1 | Babble Error
28944  *
28945  * Field Access Macros:
28946  *
28947  */
28948 /*
28949  * Enumerated value for register field ALT_USB_HOST_HCINT4_BBLERR
28950  *
28951  * No Babble Error
28952  */
28953 #define ALT_USB_HOST_HCINT4_BBLERR_E_INACT 0x0
28954 /*
28955  * Enumerated value for register field ALT_USB_HOST_HCINT4_BBLERR
28956  *
28957  * Babble Error
28958  */
28959 #define ALT_USB_HOST_HCINT4_BBLERR_E_ACT 0x1
28960 
28961 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_BBLERR register field. */
28962 #define ALT_USB_HOST_HCINT4_BBLERR_LSB 8
28963 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_BBLERR register field. */
28964 #define ALT_USB_HOST_HCINT4_BBLERR_MSB 8
28965 /* The width in bits of the ALT_USB_HOST_HCINT4_BBLERR register field. */
28966 #define ALT_USB_HOST_HCINT4_BBLERR_WIDTH 1
28967 /* The mask used to set the ALT_USB_HOST_HCINT4_BBLERR register field value. */
28968 #define ALT_USB_HOST_HCINT4_BBLERR_SET_MSK 0x00000100
28969 /* The mask used to clear the ALT_USB_HOST_HCINT4_BBLERR register field value. */
28970 #define ALT_USB_HOST_HCINT4_BBLERR_CLR_MSK 0xfffffeff
28971 /* The reset value of the ALT_USB_HOST_HCINT4_BBLERR register field. */
28972 #define ALT_USB_HOST_HCINT4_BBLERR_RESET 0x0
28973 /* Extracts the ALT_USB_HOST_HCINT4_BBLERR field value from a register. */
28974 #define ALT_USB_HOST_HCINT4_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
28975 /* Produces a ALT_USB_HOST_HCINT4_BBLERR register field value suitable for setting the register. */
28976 #define ALT_USB_HOST_HCINT4_BBLERR_SET(value) (((value) << 8) & 0x00000100)
28977 
28978 /*
28979  * Field : frmovrun
28980  *
28981  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
28982  * bit is masked
28983  *
28984  * in the core.This bit can be set only by the core and the application should
28985  * write 1 to clear
28986  *
28987  * it.
28988  *
28989  * Field Enumeration Values:
28990  *
28991  * Enum | Value | Description
28992  * :-------------------------------------|:------|:-----------------
28993  * ALT_USB_HOST_HCINT4_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
28994  * ALT_USB_HOST_HCINT4_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
28995  *
28996  * Field Access Macros:
28997  *
28998  */
28999 /*
29000  * Enumerated value for register field ALT_USB_HOST_HCINT4_FRMOVRUN
29001  *
29002  * No Frame Overrun
29003  */
29004 #define ALT_USB_HOST_HCINT4_FRMOVRUN_E_INACT 0x0
29005 /*
29006  * Enumerated value for register field ALT_USB_HOST_HCINT4_FRMOVRUN
29007  *
29008  * Frame Overrun
29009  */
29010 #define ALT_USB_HOST_HCINT4_FRMOVRUN_E_ACT 0x1
29011 
29012 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */
29013 #define ALT_USB_HOST_HCINT4_FRMOVRUN_LSB 9
29014 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */
29015 #define ALT_USB_HOST_HCINT4_FRMOVRUN_MSB 9
29016 /* The width in bits of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */
29017 #define ALT_USB_HOST_HCINT4_FRMOVRUN_WIDTH 1
29018 /* The mask used to set the ALT_USB_HOST_HCINT4_FRMOVRUN register field value. */
29019 #define ALT_USB_HOST_HCINT4_FRMOVRUN_SET_MSK 0x00000200
29020 /* The mask used to clear the ALT_USB_HOST_HCINT4_FRMOVRUN register field value. */
29021 #define ALT_USB_HOST_HCINT4_FRMOVRUN_CLR_MSK 0xfffffdff
29022 /* The reset value of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */
29023 #define ALT_USB_HOST_HCINT4_FRMOVRUN_RESET 0x0
29024 /* Extracts the ALT_USB_HOST_HCINT4_FRMOVRUN field value from a register. */
29025 #define ALT_USB_HOST_HCINT4_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
29026 /* Produces a ALT_USB_HOST_HCINT4_FRMOVRUN register field value suitable for setting the register. */
29027 #define ALT_USB_HOST_HCINT4_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
29028 
29029 /*
29030  * Field : datatglerr
29031  *
29032  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
29033  * application should write 1 to clear
29034  *
29035  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
29036  *
29037  * in the core.
29038  *
29039  * Field Enumeration Values:
29040  *
29041  * Enum | Value | Description
29042  * :---------------------------------------|:------|:---------------------
29043  * ALT_USB_HOST_HCINT4_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
29044  * ALT_USB_HOST_HCINT4_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
29045  *
29046  * Field Access Macros:
29047  *
29048  */
29049 /*
29050  * Enumerated value for register field ALT_USB_HOST_HCINT4_DATATGLERR
29051  *
29052  * No Data Toggle Error
29053  */
29054 #define ALT_USB_HOST_HCINT4_DATATGLERR_E_INACT 0x0
29055 /*
29056  * Enumerated value for register field ALT_USB_HOST_HCINT4_DATATGLERR
29057  *
29058  * Data Toggle Error
29059  */
29060 #define ALT_USB_HOST_HCINT4_DATATGLERR_E_ACT 0x1
29061 
29062 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */
29063 #define ALT_USB_HOST_HCINT4_DATATGLERR_LSB 10
29064 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */
29065 #define ALT_USB_HOST_HCINT4_DATATGLERR_MSB 10
29066 /* The width in bits of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */
29067 #define ALT_USB_HOST_HCINT4_DATATGLERR_WIDTH 1
29068 /* The mask used to set the ALT_USB_HOST_HCINT4_DATATGLERR register field value. */
29069 #define ALT_USB_HOST_HCINT4_DATATGLERR_SET_MSK 0x00000400
29070 /* The mask used to clear the ALT_USB_HOST_HCINT4_DATATGLERR register field value. */
29071 #define ALT_USB_HOST_HCINT4_DATATGLERR_CLR_MSK 0xfffffbff
29072 /* The reset value of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */
29073 #define ALT_USB_HOST_HCINT4_DATATGLERR_RESET 0x0
29074 /* Extracts the ALT_USB_HOST_HCINT4_DATATGLERR field value from a register. */
29075 #define ALT_USB_HOST_HCINT4_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
29076 /* Produces a ALT_USB_HOST_HCINT4_DATATGLERR register field value suitable for setting the register. */
29077 #define ALT_USB_HOST_HCINT4_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
29078 
29079 /*
29080  * Field : bnaintr
29081  *
29082  * BNA (Buffer Not Available) Interrupt (BNAIntr)
29083  *
29084  * This bit is valid only when Scatter/Gather DMA mode is enabled.
29085  *
29086  * The core generates this interrupt when the descriptor accessed
29087  *
29088  * is not ready for the Core to process. BNA will not be generated
29089  *
29090  * for Isochronous channels.
29091  *
29092  * For non Scatter/Gather DMA mode, this bit is reserved.
29093  *
29094  * Field Enumeration Values:
29095  *
29096  * Enum | Value | Description
29097  * :------------------------------------|:------|:-----------------
29098  * ALT_USB_HOST_HCINT4_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
29099  * ALT_USB_HOST_HCINT4_BNAINTR_E_ACT | 0x1 | BNA Interrupt
29100  *
29101  * Field Access Macros:
29102  *
29103  */
29104 /*
29105  * Enumerated value for register field ALT_USB_HOST_HCINT4_BNAINTR
29106  *
29107  * No BNA Interrupt
29108  */
29109 #define ALT_USB_HOST_HCINT4_BNAINTR_E_INACT 0x0
29110 /*
29111  * Enumerated value for register field ALT_USB_HOST_HCINT4_BNAINTR
29112  *
29113  * BNA Interrupt
29114  */
29115 #define ALT_USB_HOST_HCINT4_BNAINTR_E_ACT 0x1
29116 
29117 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_BNAINTR register field. */
29118 #define ALT_USB_HOST_HCINT4_BNAINTR_LSB 11
29119 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_BNAINTR register field. */
29120 #define ALT_USB_HOST_HCINT4_BNAINTR_MSB 11
29121 /* The width in bits of the ALT_USB_HOST_HCINT4_BNAINTR register field. */
29122 #define ALT_USB_HOST_HCINT4_BNAINTR_WIDTH 1
29123 /* The mask used to set the ALT_USB_HOST_HCINT4_BNAINTR register field value. */
29124 #define ALT_USB_HOST_HCINT4_BNAINTR_SET_MSK 0x00000800
29125 /* The mask used to clear the ALT_USB_HOST_HCINT4_BNAINTR register field value. */
29126 #define ALT_USB_HOST_HCINT4_BNAINTR_CLR_MSK 0xfffff7ff
29127 /* The reset value of the ALT_USB_HOST_HCINT4_BNAINTR register field. */
29128 #define ALT_USB_HOST_HCINT4_BNAINTR_RESET 0x0
29129 /* Extracts the ALT_USB_HOST_HCINT4_BNAINTR field value from a register. */
29130 #define ALT_USB_HOST_HCINT4_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
29131 /* Produces a ALT_USB_HOST_HCINT4_BNAINTR register field value suitable for setting the register. */
29132 #define ALT_USB_HOST_HCINT4_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
29133 
29134 /*
29135  * Field : xcs_xact_err
29136  *
29137  * Excessive Transaction Error (XCS_XACT_ERR)
29138  *
29139  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
29140  * this bit
29141  *
29142  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
29143  *
29144  * not be generated for Isochronous channels.
29145  *
29146  * For non Scatter/Gather DMA mode, this bit is reserved.
29147  *
29148  * Field Enumeration Values:
29149  *
29150  * Enum | Value | Description
29151  * :-------------------------------------------|:------|:-------------------------------
29152  * ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
29153  * ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
29154  *
29155  * Field Access Macros:
29156  *
29157  */
29158 /*
29159  * Enumerated value for register field ALT_USB_HOST_HCINT4_XCS_XACT_ERR
29160  *
29161  * No Excessive Transaction Error
29162  */
29163 #define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_INACT 0x0
29164 /*
29165  * Enumerated value for register field ALT_USB_HOST_HCINT4_XCS_XACT_ERR
29166  *
29167  * Excessive Transaction Error
29168  */
29169 #define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_ACVTIVE 0x1
29170 
29171 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */
29172 #define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_LSB 12
29173 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */
29174 #define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_MSB 12
29175 /* The width in bits of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */
29176 #define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_WIDTH 1
29177 /* The mask used to set the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field value. */
29178 #define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_SET_MSK 0x00001000
29179 /* The mask used to clear the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field value. */
29180 #define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_CLR_MSK 0xffffefff
29181 /* The reset value of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */
29182 #define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_RESET 0x0
29183 /* Extracts the ALT_USB_HOST_HCINT4_XCS_XACT_ERR field value from a register. */
29184 #define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
29185 /* Produces a ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field value suitable for setting the register. */
29186 #define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
29187 
29188 /*
29189  * Field : desc_lst_rollintr
29190  *
29191  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
29192  *
29193  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
29194  * this bit
29195  *
29196  * when the corresponding channel's descriptor list rolls over.
29197  *
29198  * For non Scatter/Gather DMA mode, this bit is reserved.
29199  *
29200  * Field Enumeration Values:
29201  *
29202  * Enum | Value | Description
29203  * :----------------------------------------------|:------|:---------------------------------
29204  * ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
29205  * ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
29206  *
29207  * Field Access Macros:
29208  *
29209  */
29210 /*
29211  * Enumerated value for register field ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR
29212  *
29213  * No Descriptor rollover interrupt
29214  */
29215 #define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_INACT 0x0
29216 /*
29217  * Enumerated value for register field ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR
29218  *
29219  * Descriptor rollover interrupt
29220  */
29221 #define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_ACT 0x1
29222 
29223 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */
29224 #define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_LSB 13
29225 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */
29226 #define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_MSB 13
29227 /* The width in bits of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */
29228 #define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_WIDTH 1
29229 /* The mask used to set the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field value. */
29230 #define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_SET_MSK 0x00002000
29231 /* The mask used to clear the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field value. */
29232 #define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
29233 /* The reset value of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */
29234 #define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_RESET 0x0
29235 /* Extracts the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR field value from a register. */
29236 #define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
29237 /* Produces a ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field value suitable for setting the register. */
29238 #define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
29239 
29240 #ifndef __ASSEMBLY__
29241 /*
29242  * WARNING: The C register and register group struct declarations are provided for
29243  * convenience and illustrative purposes. They should, however, be used with
29244  * caution as the C language standard provides no guarantees about the alignment or
29245  * atomicity of device memory accesses. The recommended practice for writing
29246  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29247  * alt_write_word() functions.
29248  *
29249  * The struct declaration for register ALT_USB_HOST_HCINT4.
29250  */
29251 struct ALT_USB_HOST_HCINT4_s
29252 {
29253  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT4_XFERCOMPL */
29254  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT4_CHHLTD */
29255  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT4_AHBERR */
29256  uint32_t stall : 1; /* ALT_USB_HOST_HCINT4_STALL */
29257  uint32_t nak : 1; /* ALT_USB_HOST_HCINT4_NAK */
29258  uint32_t ack : 1; /* ALT_USB_HOST_HCINT4_ACK */
29259  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT4_NYET */
29260  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT4_XACTERR */
29261  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT4_BBLERR */
29262  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT4_FRMOVRUN */
29263  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT4_DATATGLERR */
29264  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT4_BNAINTR */
29265  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT4_XCS_XACT_ERR */
29266  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR */
29267  uint32_t : 18; /* *UNDEFINED* */
29268 };
29269 
29270 /* The typedef declaration for register ALT_USB_HOST_HCINT4. */
29271 typedef volatile struct ALT_USB_HOST_HCINT4_s ALT_USB_HOST_HCINT4_t;
29272 #endif /* __ASSEMBLY__ */
29273 
29274 /* The reset value of the ALT_USB_HOST_HCINT4 register. */
29275 #define ALT_USB_HOST_HCINT4_RESET 0x00000000
29276 /* The byte offset of the ALT_USB_HOST_HCINT4 register from the beginning of the component. */
29277 #define ALT_USB_HOST_HCINT4_OFST 0x188
29278 /* The address of the ALT_USB_HOST_HCINT4 register. */
29279 #define ALT_USB_HOST_HCINT4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT4_OFST))
29280 
29281 /*
29282  * Register : hcintmsk4
29283  *
29284  * Host Channel 4 Interrupt Mask Register
29285  *
29286  * Register Layout
29287  *
29288  * Bits | Access | Reset | Description
29289  * :--------|:-------|:------|:-------------------------------------------
29290  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK
29291  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_CHHLTDMSK
29292  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_AHBERRMSK
29293  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_STALLMSK
29294  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_NAKMSK
29295  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_ACKMSK
29296  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_NYETMSK
29297  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_XACTERRMSK
29298  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_BBLERRMSK
29299  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK
29300  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK
29301  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_BNAINTRMSK
29302  * [12] | ??? | 0x0 | *UNDEFINED*
29303  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK
29304  * [31:14] | ??? | 0x0 | *UNDEFINED*
29305  *
29306  */
29307 /*
29308  * Field : xfercomplmsk
29309  *
29310  * Transfer Completed Mask (XferComplMsk)
29311  *
29312  * Field Enumeration Values:
29313  *
29314  * Enum | Value | Description
29315  * :--------------------------------------------|:------|:------------
29316  * ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_MSK | 0x0 | Mask
29317  * ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
29318  *
29319  * Field Access Macros:
29320  *
29321  */
29322 /*
29323  * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK
29324  *
29325  * Mask
29326  */
29327 #define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_MSK 0x0
29328 /*
29329  * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK
29330  *
29331  * No mask
29332  */
29333 #define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_NOMSK 0x1
29334 
29335 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */
29336 #define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_LSB 0
29337 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */
29338 #define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_MSB 0
29339 /* The width in bits of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */
29340 #define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_WIDTH 1
29341 /* The mask used to set the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field value. */
29342 #define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_SET_MSK 0x00000001
29343 /* The mask used to clear the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field value. */
29344 #define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_CLR_MSK 0xfffffffe
29345 /* The reset value of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */
29346 #define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_RESET 0x0
29347 /* Extracts the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK field value from a register. */
29348 #define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
29349 /* Produces a ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field value suitable for setting the register. */
29350 #define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
29351 
29352 /*
29353  * Field : chhltdmsk
29354  *
29355  * Channel Halted Mask (ChHltdMsk)
29356  *
29357  * Field Enumeration Values:
29358  *
29359  * Enum | Value | Description
29360  * :-----------------------------------------|:------|:------------
29361  * ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_MSK | 0x0 | Mask
29362  * ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_NOMSK | 0x1 | No mask
29363  *
29364  * Field Access Macros:
29365  *
29366  */
29367 /*
29368  * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_CHHLTDMSK
29369  *
29370  * Mask
29371  */
29372 #define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_MSK 0x0
29373 /*
29374  * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_CHHLTDMSK
29375  *
29376  * No mask
29377  */
29378 #define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_NOMSK 0x1
29379 
29380 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */
29381 #define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_LSB 1
29382 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */
29383 #define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_MSB 1
29384 /* The width in bits of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */
29385 #define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_WIDTH 1
29386 /* The mask used to set the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field value. */
29387 #define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_SET_MSK 0x00000002
29388 /* The mask used to clear the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field value. */
29389 #define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_CLR_MSK 0xfffffffd
29390 /* The reset value of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */
29391 #define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_RESET 0x0
29392 /* Extracts the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK field value from a register. */
29393 #define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
29394 /* Produces a ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field value suitable for setting the register. */
29395 #define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
29396 
29397 /*
29398  * Field : ahberrmsk
29399  *
29400  * AHB Error Mask (AHBErrMsk)
29401  *
29402  * In scatter/gather DMA mode for host,
29403  *
29404  * interrupts will not be generated due to the corresponding bits set in
29405  *
29406  * HCINTn.
29407  *
29408  * Field Enumeration Values:
29409  *
29410  * Enum | Value | Description
29411  * :-----------------------------------------|:------|:------------
29412  * ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_MSK | 0x0 | Mask
29413  * ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_NOMSK | 0x1 | No mask
29414  *
29415  * Field Access Macros:
29416  *
29417  */
29418 /*
29419  * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_AHBERRMSK
29420  *
29421  * Mask
29422  */
29423 #define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_MSK 0x0
29424 /*
29425  * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_AHBERRMSK
29426  *
29427  * No mask
29428  */
29429 #define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_NOMSK 0x1
29430 
29431 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */
29432 #define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_LSB 2
29433 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */
29434 #define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_MSB 2
29435 /* The width in bits of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */
29436 #define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_WIDTH 1
29437 /* The mask used to set the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field value. */
29438 #define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_SET_MSK 0x00000004
29439 /* The mask used to clear the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field value. */
29440 #define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_CLR_MSK 0xfffffffb
29441 /* The reset value of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */
29442 #define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_RESET 0x0
29443 /* Extracts the ALT_USB_HOST_HCINTMSK4_AHBERRMSK field value from a register. */
29444 #define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
29445 /* Produces a ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field value suitable for setting the register. */
29446 #define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
29447 
29448 /*
29449  * Field : stallmsk
29450  *
29451  * STALL Response Received Interrupt Mask (StallMsk)
29452  *
29453  * In scatter/gather DMA mode for host,
29454  *
29455  * interrupts will not be generated due to the corresponding bits set in
29456  *
29457  * HCINTn.
29458  *
29459  * Field Access Macros:
29460  *
29461  */
29462 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_STALLMSK register field. */
29463 #define ALT_USB_HOST_HCINTMSK4_STALLMSK_LSB 3
29464 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_STALLMSK register field. */
29465 #define ALT_USB_HOST_HCINTMSK4_STALLMSK_MSB 3
29466 /* The width in bits of the ALT_USB_HOST_HCINTMSK4_STALLMSK register field. */
29467 #define ALT_USB_HOST_HCINTMSK4_STALLMSK_WIDTH 1
29468 /* The mask used to set the ALT_USB_HOST_HCINTMSK4_STALLMSK register field value. */
29469 #define ALT_USB_HOST_HCINTMSK4_STALLMSK_SET_MSK 0x00000008
29470 /* The mask used to clear the ALT_USB_HOST_HCINTMSK4_STALLMSK register field value. */
29471 #define ALT_USB_HOST_HCINTMSK4_STALLMSK_CLR_MSK 0xfffffff7
29472 /* The reset value of the ALT_USB_HOST_HCINTMSK4_STALLMSK register field. */
29473 #define ALT_USB_HOST_HCINTMSK4_STALLMSK_RESET 0x0
29474 /* Extracts the ALT_USB_HOST_HCINTMSK4_STALLMSK field value from a register. */
29475 #define ALT_USB_HOST_HCINTMSK4_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
29476 /* Produces a ALT_USB_HOST_HCINTMSK4_STALLMSK register field value suitable for setting the register. */
29477 #define ALT_USB_HOST_HCINTMSK4_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
29478 
29479 /*
29480  * Field : nakmsk
29481  *
29482  * NAK Response Received Interrupt Mask (NakMsk)
29483  *
29484  * In scatter/gather DMA mode for host,
29485  *
29486  * interrupts will not be generated due to the corresponding bits set in
29487  *
29488  * HCINTn.
29489  *
29490  * Field Access Macros:
29491  *
29492  */
29493 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_NAKMSK register field. */
29494 #define ALT_USB_HOST_HCINTMSK4_NAKMSK_LSB 4
29495 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_NAKMSK register field. */
29496 #define ALT_USB_HOST_HCINTMSK4_NAKMSK_MSB 4
29497 /* The width in bits of the ALT_USB_HOST_HCINTMSK4_NAKMSK register field. */
29498 #define ALT_USB_HOST_HCINTMSK4_NAKMSK_WIDTH 1
29499 /* The mask used to set the ALT_USB_HOST_HCINTMSK4_NAKMSK register field value. */
29500 #define ALT_USB_HOST_HCINTMSK4_NAKMSK_SET_MSK 0x00000010
29501 /* The mask used to clear the ALT_USB_HOST_HCINTMSK4_NAKMSK register field value. */
29502 #define ALT_USB_HOST_HCINTMSK4_NAKMSK_CLR_MSK 0xffffffef
29503 /* The reset value of the ALT_USB_HOST_HCINTMSK4_NAKMSK register field. */
29504 #define ALT_USB_HOST_HCINTMSK4_NAKMSK_RESET 0x0
29505 /* Extracts the ALT_USB_HOST_HCINTMSK4_NAKMSK field value from a register. */
29506 #define ALT_USB_HOST_HCINTMSK4_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
29507 /* Produces a ALT_USB_HOST_HCINTMSK4_NAKMSK register field value suitable for setting the register. */
29508 #define ALT_USB_HOST_HCINTMSK4_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
29509 
29510 /*
29511  * Field : ackmsk
29512  *
29513  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
29514  *
29515  * In scatter/gather DMA mode for host,
29516  *
29517  * interrupts will not be generated due to the corresponding bits set in
29518  *
29519  * HCINTn.
29520  *
29521  * Field Access Macros:
29522  *
29523  */
29524 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_ACKMSK register field. */
29525 #define ALT_USB_HOST_HCINTMSK4_ACKMSK_LSB 5
29526 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_ACKMSK register field. */
29527 #define ALT_USB_HOST_HCINTMSK4_ACKMSK_MSB 5
29528 /* The width in bits of the ALT_USB_HOST_HCINTMSK4_ACKMSK register field. */
29529 #define ALT_USB_HOST_HCINTMSK4_ACKMSK_WIDTH 1
29530 /* The mask used to set the ALT_USB_HOST_HCINTMSK4_ACKMSK register field value. */
29531 #define ALT_USB_HOST_HCINTMSK4_ACKMSK_SET_MSK 0x00000020
29532 /* The mask used to clear the ALT_USB_HOST_HCINTMSK4_ACKMSK register field value. */
29533 #define ALT_USB_HOST_HCINTMSK4_ACKMSK_CLR_MSK 0xffffffdf
29534 /* The reset value of the ALT_USB_HOST_HCINTMSK4_ACKMSK register field. */
29535 #define ALT_USB_HOST_HCINTMSK4_ACKMSK_RESET 0x0
29536 /* Extracts the ALT_USB_HOST_HCINTMSK4_ACKMSK field value from a register. */
29537 #define ALT_USB_HOST_HCINTMSK4_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
29538 /* Produces a ALT_USB_HOST_HCINTMSK4_ACKMSK register field value suitable for setting the register. */
29539 #define ALT_USB_HOST_HCINTMSK4_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
29540 
29541 /*
29542  * Field : nyetmsk
29543  *
29544  * NYET Response Received Interrupt Mask (NyetMsk)
29545  *
29546  * In scatter/gather DMA mode for host,
29547  *
29548  * interrupts will not be generated due to the corresponding bits set in
29549  *
29550  * HCINTn.
29551  *
29552  * Field Access Macros:
29553  *
29554  */
29555 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_NYETMSK register field. */
29556 #define ALT_USB_HOST_HCINTMSK4_NYETMSK_LSB 6
29557 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_NYETMSK register field. */
29558 #define ALT_USB_HOST_HCINTMSK4_NYETMSK_MSB 6
29559 /* The width in bits of the ALT_USB_HOST_HCINTMSK4_NYETMSK register field. */
29560 #define ALT_USB_HOST_HCINTMSK4_NYETMSK_WIDTH 1
29561 /* The mask used to set the ALT_USB_HOST_HCINTMSK4_NYETMSK register field value. */
29562 #define ALT_USB_HOST_HCINTMSK4_NYETMSK_SET_MSK 0x00000040
29563 /* The mask used to clear the ALT_USB_HOST_HCINTMSK4_NYETMSK register field value. */
29564 #define ALT_USB_HOST_HCINTMSK4_NYETMSK_CLR_MSK 0xffffffbf
29565 /* The reset value of the ALT_USB_HOST_HCINTMSK4_NYETMSK register field. */
29566 #define ALT_USB_HOST_HCINTMSK4_NYETMSK_RESET 0x0
29567 /* Extracts the ALT_USB_HOST_HCINTMSK4_NYETMSK field value from a register. */
29568 #define ALT_USB_HOST_HCINTMSK4_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
29569 /* Produces a ALT_USB_HOST_HCINTMSK4_NYETMSK register field value suitable for setting the register. */
29570 #define ALT_USB_HOST_HCINTMSK4_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
29571 
29572 /*
29573  * Field : xacterrmsk
29574  *
29575  * Transaction Error Mask (XactErrMsk)
29576  *
29577  * In scatter/gather DMA mode for host,
29578  *
29579  * interrupts will not be generated due to the corresponding bits set in
29580  *
29581  * HCINTn.
29582  *
29583  * Field Access Macros:
29584  *
29585  */
29586 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field. */
29587 #define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_LSB 7
29588 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field. */
29589 #define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_MSB 7
29590 /* The width in bits of the ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field. */
29591 #define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_WIDTH 1
29592 /* The mask used to set the ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field value. */
29593 #define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_SET_MSK 0x00000080
29594 /* The mask used to clear the ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field value. */
29595 #define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_CLR_MSK 0xffffff7f
29596 /* The reset value of the ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field. */
29597 #define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_RESET 0x0
29598 /* Extracts the ALT_USB_HOST_HCINTMSK4_XACTERRMSK field value from a register. */
29599 #define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
29600 /* Produces a ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field value suitable for setting the register. */
29601 #define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
29602 
29603 /*
29604  * Field : bblerrmsk
29605  *
29606  * Babble Error Mask (BblErrMsk)
29607  *
29608  * In scatter/gather DMA mode for host,
29609  *
29610  * interrupts will not be generated due to the corresponding bits set in
29611  *
29612  * HCINTn.
29613  *
29614  * Field Access Macros:
29615  *
29616  */
29617 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field. */
29618 #define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_LSB 8
29619 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field. */
29620 #define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_MSB 8
29621 /* The width in bits of the ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field. */
29622 #define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_WIDTH 1
29623 /* The mask used to set the ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field value. */
29624 #define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_SET_MSK 0x00000100
29625 /* The mask used to clear the ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field value. */
29626 #define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_CLR_MSK 0xfffffeff
29627 /* The reset value of the ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field. */
29628 #define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_RESET 0x0
29629 /* Extracts the ALT_USB_HOST_HCINTMSK4_BBLERRMSK field value from a register. */
29630 #define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
29631 /* Produces a ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field value suitable for setting the register. */
29632 #define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
29633 
29634 /*
29635  * Field : frmovrunmsk
29636  *
29637  * Frame Overrun Mask (FrmOvrunMsk)
29638  *
29639  * In scatter/gather DMA mode for host,
29640  *
29641  * interrupts will not be generated due to the corresponding bits set in
29642  *
29643  * HCINTn.
29644  *
29645  * Field Access Macros:
29646  *
29647  */
29648 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field. */
29649 #define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_LSB 9
29650 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field. */
29651 #define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_MSB 9
29652 /* The width in bits of the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field. */
29653 #define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_WIDTH 1
29654 /* The mask used to set the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field value. */
29655 #define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_SET_MSK 0x00000200
29656 /* The mask used to clear the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field value. */
29657 #define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_CLR_MSK 0xfffffdff
29658 /* The reset value of the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field. */
29659 #define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_RESET 0x0
29660 /* Extracts the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK field value from a register. */
29661 #define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
29662 /* Produces a ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field value suitable for setting the register. */
29663 #define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
29664 
29665 /*
29666  * Field : datatglerrmsk
29667  *
29668  * Data Toggle Error Mask (DataTglErrMsk)
29669  *
29670  * In scatter/gather DMA mode for host,
29671  *
29672  * interrupts will not be generated due to the corresponding bits set in
29673  *
29674  * HCINTn.
29675  *
29676  * Field Access Macros:
29677  *
29678  */
29679 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field. */
29680 #define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_LSB 10
29681 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field. */
29682 #define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_MSB 10
29683 /* The width in bits of the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field. */
29684 #define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_WIDTH 1
29685 /* The mask used to set the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field value. */
29686 #define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_SET_MSK 0x00000400
29687 /* The mask used to clear the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field value. */
29688 #define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_CLR_MSK 0xfffffbff
29689 /* The reset value of the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field. */
29690 #define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_RESET 0x0
29691 /* Extracts the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK field value from a register. */
29692 #define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
29693 /* Produces a ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field value suitable for setting the register. */
29694 #define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
29695 
29696 /*
29697  * Field : bnaintrmsk
29698  *
29699  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
29700  *
29701  * This bit is valid only when Scatter/Gather DMA mode is enabled.
29702  *
29703  * Field Enumeration Values:
29704  *
29705  * Enum | Value | Description
29706  * :------------------------------------------|:------|:------------
29707  * ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_MSK | 0x0 | Mask
29708  * ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_NOMSK | 0x1 | No mask
29709  *
29710  * Field Access Macros:
29711  *
29712  */
29713 /*
29714  * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_BNAINTRMSK
29715  *
29716  * Mask
29717  */
29718 #define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_MSK 0x0
29719 /*
29720  * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_BNAINTRMSK
29721  *
29722  * No mask
29723  */
29724 #define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_NOMSK 0x1
29725 
29726 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */
29727 #define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_LSB 11
29728 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */
29729 #define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_MSB 11
29730 /* The width in bits of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */
29731 #define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_WIDTH 1
29732 /* The mask used to set the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field value. */
29733 #define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_SET_MSK 0x00000800
29734 /* The mask used to clear the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field value. */
29735 #define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_CLR_MSK 0xfffff7ff
29736 /* The reset value of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */
29737 #define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_RESET 0x0
29738 /* Extracts the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK field value from a register. */
29739 #define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
29740 /* Produces a ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field value suitable for setting the register. */
29741 #define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
29742 
29743 /*
29744  * Field : frm_lst_rollintrmsk
29745  *
29746  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
29747  *
29748  * This bit is valid only when Scatter/Gather DMA mode is enabled.
29749  *
29750  * Field Enumeration Values:
29751  *
29752  * Enum | Value | Description
29753  * :---------------------------------------------------|:------|:------------
29754  * ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
29755  * ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
29756  *
29757  * Field Access Macros:
29758  *
29759  */
29760 /*
29761  * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK
29762  *
29763  * Mask
29764  */
29765 #define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_MSK 0x0
29766 /*
29767  * Enumerated value for register field ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK
29768  *
29769  * No mask
29770  */
29771 #define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
29772 
29773 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */
29774 #define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_LSB 13
29775 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */
29776 #define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_MSB 13
29777 /* The width in bits of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */
29778 #define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_WIDTH 1
29779 /* The mask used to set the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field value. */
29780 #define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
29781 /* The mask used to clear the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field value. */
29782 #define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
29783 /* The reset value of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */
29784 #define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_RESET 0x0
29785 /* Extracts the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK field value from a register. */
29786 #define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
29787 /* Produces a ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
29788 #define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
29789 
29790 #ifndef __ASSEMBLY__
29791 /*
29792  * WARNING: The C register and register group struct declarations are provided for
29793  * convenience and illustrative purposes. They should, however, be used with
29794  * caution as the C language standard provides no guarantees about the alignment or
29795  * atomicity of device memory accesses. The recommended practice for writing
29796  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29797  * alt_write_word() functions.
29798  *
29799  * The struct declaration for register ALT_USB_HOST_HCINTMSK4.
29800  */
29801 struct ALT_USB_HOST_HCINTMSK4_s
29802 {
29803  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK */
29804  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK4_CHHLTDMSK */
29805  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK4_AHBERRMSK */
29806  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK4_STALLMSK */
29807  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK4_NAKMSK */
29808  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK4_ACKMSK */
29809  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK4_NYETMSK */
29810  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK4_XACTERRMSK */
29811  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK4_BBLERRMSK */
29812  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK */
29813  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK */
29814  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK4_BNAINTRMSK */
29815  uint32_t : 1; /* *UNDEFINED* */
29816  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK */
29817  uint32_t : 18; /* *UNDEFINED* */
29818 };
29819 
29820 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK4. */
29821 typedef volatile struct ALT_USB_HOST_HCINTMSK4_s ALT_USB_HOST_HCINTMSK4_t;
29822 #endif /* __ASSEMBLY__ */
29823 
29824 /* The reset value of the ALT_USB_HOST_HCINTMSK4 register. */
29825 #define ALT_USB_HOST_HCINTMSK4_RESET 0x00000000
29826 /* The byte offset of the ALT_USB_HOST_HCINTMSK4 register from the beginning of the component. */
29827 #define ALT_USB_HOST_HCINTMSK4_OFST 0x18c
29828 /* The address of the ALT_USB_HOST_HCINTMSK4 register. */
29829 #define ALT_USB_HOST_HCINTMSK4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK4_OFST))
29830 
29831 /*
29832  * Register : hctsiz4
29833  *
29834  * Host Channel 4 Transfer Size Register
29835  *
29836  * Register Layout
29837  *
29838  * Bits | Access | Reset | Description
29839  * :--------|:-------|:------|:------------------------------
29840  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ4_XFERSIZE
29841  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ4_PKTCNT
29842  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ4_PID
29843  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ4_DOPNG
29844  *
29845  */
29846 /*
29847  * Field : xfersize
29848  *
29849  * Transfer Size (XferSize)
29850  *
29851  * For an OUT, this field is the number of data bytes the host sends
29852  *
29853  * during the transfer.
29854  *
29855  * For an IN, this field is the buffer size that the application has
29856  *
29857  * Reserved For the transfer. The application is expected to
29858  *
29859  * program this field as an integer multiple of the maximum packet
29860  *
29861  * size For IN transactions (periodic and non-periodic).
29862  *
29863  * The width of this counter is specified as Width of Transfer Size
29864  *
29865  * Counters
29866  *
29867  * Field Access Macros:
29868  *
29869  */
29870 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */
29871 #define ALT_USB_HOST_HCTSIZ4_XFERSIZE_LSB 0
29872 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */
29873 #define ALT_USB_HOST_HCTSIZ4_XFERSIZE_MSB 18
29874 /* The width in bits of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */
29875 #define ALT_USB_HOST_HCTSIZ4_XFERSIZE_WIDTH 19
29876 /* The mask used to set the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field value. */
29877 #define ALT_USB_HOST_HCTSIZ4_XFERSIZE_SET_MSK 0x0007ffff
29878 /* The mask used to clear the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field value. */
29879 #define ALT_USB_HOST_HCTSIZ4_XFERSIZE_CLR_MSK 0xfff80000
29880 /* The reset value of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */
29881 #define ALT_USB_HOST_HCTSIZ4_XFERSIZE_RESET 0x0
29882 /* Extracts the ALT_USB_HOST_HCTSIZ4_XFERSIZE field value from a register. */
29883 #define ALT_USB_HOST_HCTSIZ4_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
29884 /* Produces a ALT_USB_HOST_HCTSIZ4_XFERSIZE register field value suitable for setting the register. */
29885 #define ALT_USB_HOST_HCTSIZ4_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
29886 
29887 /*
29888  * Field : pktcnt
29889  *
29890  * Packet Count (PktCnt)
29891  *
29892  * This field is programmed by the application with the expected
29893  *
29894  * number of packets to be transmitted (OUT) or received (IN).
29895  *
29896  * The host decrements this count on every successful
29897  *
29898  * transmission or reception of an OUT/IN packet. Once this count
29899  *
29900  * reaches zero, the application is interrupted to indicate normal
29901  *
29902  * completion.
29903  *
29904  * The width of this counter is specified as Width of Packet
29905  *
29906  * Counters
29907  *
29908  * Field Access Macros:
29909  *
29910  */
29911 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */
29912 #define ALT_USB_HOST_HCTSIZ4_PKTCNT_LSB 19
29913 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */
29914 #define ALT_USB_HOST_HCTSIZ4_PKTCNT_MSB 28
29915 /* The width in bits of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */
29916 #define ALT_USB_HOST_HCTSIZ4_PKTCNT_WIDTH 10
29917 /* The mask used to set the ALT_USB_HOST_HCTSIZ4_PKTCNT register field value. */
29918 #define ALT_USB_HOST_HCTSIZ4_PKTCNT_SET_MSK 0x1ff80000
29919 /* The mask used to clear the ALT_USB_HOST_HCTSIZ4_PKTCNT register field value. */
29920 #define ALT_USB_HOST_HCTSIZ4_PKTCNT_CLR_MSK 0xe007ffff
29921 /* The reset value of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */
29922 #define ALT_USB_HOST_HCTSIZ4_PKTCNT_RESET 0x0
29923 /* Extracts the ALT_USB_HOST_HCTSIZ4_PKTCNT field value from a register. */
29924 #define ALT_USB_HOST_HCTSIZ4_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
29925 /* Produces a ALT_USB_HOST_HCTSIZ4_PKTCNT register field value suitable for setting the register. */
29926 #define ALT_USB_HOST_HCTSIZ4_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
29927 
29928 /*
29929  * Field : pid
29930  *
29931  * PID (Pid)
29932  *
29933  * The application programs this field with the type of PID to use For
29934  *
29935  * the initial transaction. The host maintains this field For the rest of
29936  *
29937  * the transfer.
29938  *
29939  * 2'b00: DATA0
29940  *
29941  * 2'b01: DATA2
29942  *
29943  * 2'b10: DATA1
29944  *
29945  * 2'b11: MDATA (non-control)/SETUP (control)
29946  *
29947  * Field Enumeration Values:
29948  *
29949  * Enum | Value | Description
29950  * :---------------------------------|:------|:------------------------------------
29951  * ALT_USB_HOST_HCTSIZ4_PID_E_DATA0 | 0x0 | DATA0
29952  * ALT_USB_HOST_HCTSIZ4_PID_E_DATA2 | 0x1 | DATA2
29953  * ALT_USB_HOST_HCTSIZ4_PID_E_DATA1 | 0x2 | DATA1
29954  * ALT_USB_HOST_HCTSIZ4_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
29955  *
29956  * Field Access Macros:
29957  *
29958  */
29959 /*
29960  * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID
29961  *
29962  * DATA0
29963  */
29964 #define ALT_USB_HOST_HCTSIZ4_PID_E_DATA0 0x0
29965 /*
29966  * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID
29967  *
29968  * DATA2
29969  */
29970 #define ALT_USB_HOST_HCTSIZ4_PID_E_DATA2 0x1
29971 /*
29972  * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID
29973  *
29974  * DATA1
29975  */
29976 #define ALT_USB_HOST_HCTSIZ4_PID_E_DATA1 0x2
29977 /*
29978  * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID
29979  *
29980  * MDATA (non-control)/SETUP (control)
29981  */
29982 #define ALT_USB_HOST_HCTSIZ4_PID_E_MDATA 0x3
29983 
29984 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_PID register field. */
29985 #define ALT_USB_HOST_HCTSIZ4_PID_LSB 29
29986 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_PID register field. */
29987 #define ALT_USB_HOST_HCTSIZ4_PID_MSB 30
29988 /* The width in bits of the ALT_USB_HOST_HCTSIZ4_PID register field. */
29989 #define ALT_USB_HOST_HCTSIZ4_PID_WIDTH 2
29990 /* The mask used to set the ALT_USB_HOST_HCTSIZ4_PID register field value. */
29991 #define ALT_USB_HOST_HCTSIZ4_PID_SET_MSK 0x60000000
29992 /* The mask used to clear the ALT_USB_HOST_HCTSIZ4_PID register field value. */
29993 #define ALT_USB_HOST_HCTSIZ4_PID_CLR_MSK 0x9fffffff
29994 /* The reset value of the ALT_USB_HOST_HCTSIZ4_PID register field. */
29995 #define ALT_USB_HOST_HCTSIZ4_PID_RESET 0x0
29996 /* Extracts the ALT_USB_HOST_HCTSIZ4_PID field value from a register. */
29997 #define ALT_USB_HOST_HCTSIZ4_PID_GET(value) (((value) & 0x60000000) >> 29)
29998 /* Produces a ALT_USB_HOST_HCTSIZ4_PID register field value suitable for setting the register. */
29999 #define ALT_USB_HOST_HCTSIZ4_PID_SET(value) (((value) << 29) & 0x60000000)
30000 
30001 /*
30002  * Field : dopng
30003  *
30004  * Do Ping (DoPng)
30005  *
30006  * This bit is used only For OUT transfers.
30007  *
30008  * Setting this field to 1 directs the host to do PING protocol.
30009  *
30010  * Note: Do not Set this bit For IN transfers. If this bit is Set For
30011  *
30012  * for IN transfers it disables the channel.
30013  *
30014  * Field Enumeration Values:
30015  *
30016  * Enum | Value | Description
30017  * :------------------------------------|:------|:-----------------
30018  * ALT_USB_HOST_HCTSIZ4_DOPNG_E_NOPING | 0x0 | No ping protocol
30019  * ALT_USB_HOST_HCTSIZ4_DOPNG_E_PING | 0x1 | Ping protocol
30020  *
30021  * Field Access Macros:
30022  *
30023  */
30024 /*
30025  * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_DOPNG
30026  *
30027  * No ping protocol
30028  */
30029 #define ALT_USB_HOST_HCTSIZ4_DOPNG_E_NOPING 0x0
30030 /*
30031  * Enumerated value for register field ALT_USB_HOST_HCTSIZ4_DOPNG
30032  *
30033  * Ping protocol
30034  */
30035 #define ALT_USB_HOST_HCTSIZ4_DOPNG_E_PING 0x1
30036 
30037 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */
30038 #define ALT_USB_HOST_HCTSIZ4_DOPNG_LSB 31
30039 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */
30040 #define ALT_USB_HOST_HCTSIZ4_DOPNG_MSB 31
30041 /* The width in bits of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */
30042 #define ALT_USB_HOST_HCTSIZ4_DOPNG_WIDTH 1
30043 /* The mask used to set the ALT_USB_HOST_HCTSIZ4_DOPNG register field value. */
30044 #define ALT_USB_HOST_HCTSIZ4_DOPNG_SET_MSK 0x80000000
30045 /* The mask used to clear the ALT_USB_HOST_HCTSIZ4_DOPNG register field value. */
30046 #define ALT_USB_HOST_HCTSIZ4_DOPNG_CLR_MSK 0x7fffffff
30047 /* The reset value of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */
30048 #define ALT_USB_HOST_HCTSIZ4_DOPNG_RESET 0x0
30049 /* Extracts the ALT_USB_HOST_HCTSIZ4_DOPNG field value from a register. */
30050 #define ALT_USB_HOST_HCTSIZ4_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
30051 /* Produces a ALT_USB_HOST_HCTSIZ4_DOPNG register field value suitable for setting the register. */
30052 #define ALT_USB_HOST_HCTSIZ4_DOPNG_SET(value) (((value) << 31) & 0x80000000)
30053 
30054 #ifndef __ASSEMBLY__
30055 /*
30056  * WARNING: The C register and register group struct declarations are provided for
30057  * convenience and illustrative purposes. They should, however, be used with
30058  * caution as the C language standard provides no guarantees about the alignment or
30059  * atomicity of device memory accesses. The recommended practice for writing
30060  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30061  * alt_write_word() functions.
30062  *
30063  * The struct declaration for register ALT_USB_HOST_HCTSIZ4.
30064  */
30065 struct ALT_USB_HOST_HCTSIZ4_s
30066 {
30067  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ4_XFERSIZE */
30068  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ4_PKTCNT */
30069  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ4_PID */
30070  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ4_DOPNG */
30071 };
30072 
30073 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ4. */
30074 typedef volatile struct ALT_USB_HOST_HCTSIZ4_s ALT_USB_HOST_HCTSIZ4_t;
30075 #endif /* __ASSEMBLY__ */
30076 
30077 /* The reset value of the ALT_USB_HOST_HCTSIZ4 register. */
30078 #define ALT_USB_HOST_HCTSIZ4_RESET 0x00000000
30079 /* The byte offset of the ALT_USB_HOST_HCTSIZ4 register from the beginning of the component. */
30080 #define ALT_USB_HOST_HCTSIZ4_OFST 0x190
30081 /* The address of the ALT_USB_HOST_HCTSIZ4 register. */
30082 #define ALT_USB_HOST_HCTSIZ4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ4_OFST))
30083 
30084 /*
30085  * Register : hcdma4
30086  *
30087  * Host Channel 4 DMA Address Register
30088  *
30089  * Register Layout
30090  *
30091  * Bits | Access | Reset | Description
30092  * :-------|:-------|:------|:---------------------------
30093  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA4_HCDMA4
30094  *
30095  */
30096 /*
30097  * Field : hcdma4
30098  *
30099  * Buffer DMA Mode:
30100  *
30101  * [31:0] DMA Address (DMAAddr)
30102  *
30103  * This field holds the start address in the external memory from which the data
30104  * for
30105  *
30106  * the endpoint must be fetched or to which it must be stored. This register is
30107  *
30108  * incremented on every AHB transaction.
30109  *
30110  * Scatter-Gather DMA (DescDMA) Mode:
30111  *
30112  * [31:9] (Non Isoc) Non-Isochronous:
30113  *
30114  * [31:N] (Isoc) Isochronous:
30115  *
30116  * This field holds the start address of the 512 bytes
30117  *
30118  * page. The first descriptor in the list should be located
30119  *
30120  * in this address. The first descriptor may be or may
30121  *
30122  * not be ready. The core starts processing the list from
30123  *
30124  * the CTD value.
30125  *
30126  * This field holds the address of the 2*(nTD+1) bytes of
30127  *
30128  * locations in which the isochronous descriptors are
30129  *
30130  * present where N is based on nTD as per Table below
30131  *
30132  * [31:N] Base Address
30133  *
30134  * [N-1:3] Offset
30135  *
30136  * [2:0] 000
30137  *
30138  * HS ISOC
30139  *
30140  * nTD N
30141  *
30142  * 7 6
30143  *
30144  * 15 7
30145  *
30146  * 31 8
30147  *
30148  * 63 9
30149  *
30150  * 127 10
30151  *
30152  * 255 11
30153  *
30154  * FS ISOC
30155  *
30156  * nTD N
30157  *
30158  * 1 4
30159  *
30160  * 3 5
30161  *
30162  * 7 6
30163  *
30164  * 15 7
30165  *
30166  * 31 8
30167  *
30168  * 63 9
30169  *
30170  * [N-1:3] (Isoc):
30171  *
30172  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
30173  *
30174  * Non Isochronous:
30175  *
30176  * This value is in terms of number of descriptors. The values can be from 0 to 63.
30177  *
30178  * 0 - 1 descriptor.
30179  *
30180  * 63 - 64 descriptors.
30181  *
30182  * This field indicates the current descriptor processed in the list. This field is
30183  * updated
30184  *
30185  * both by application and the core. For example, if the application enables the
30186  *
30187  * channel after programming CTD=5, then the core will start processing the 6th
30188  *
30189  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
30190  *
30191  * to DMAAddr.
30192  *
30193  * Isochronous:
30194  *
30195  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
30196  * set
30197  *
30198  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
30199  *
30200  * [31:9] (Non Isoc) Non-Isochronous:
30201  *
30202  * [31:N] (Isoc) Isochronous:
30203  *
30204  * This field holds the start address of the 512 bytes
30205  *
30206  * page. The first descriptor in the list should be located
30207  *
30208  * in this address. The first descriptor may be or may
30209  *
30210  * not be ready. The core starts processing the list from
30211  *
30212  * the CTD value.
30213  *
30214  * This field holds the address of the 2*(nTD+1) bytes of
30215  *
30216  * locations in which the isochronous descriptors are
30217  *
30218  * present where N is based on nTD as per Table below
30219  *
30220  * [31:N] Base Address
30221  *
30222  * [N-1:3] Offset
30223  *
30224  * [2:0] 000
30225  *
30226  * HS ISOC
30227  *
30228  * nTD N
30229  *
30230  * 7 6
30231  *
30232  * 15 7
30233  *
30234  * 31 8
30235  *
30236  * 63 9
30237  *
30238  * 127 10
30239  *
30240  * 255 11
30241  *
30242  * FS ISOC
30243  *
30244  * nTD N
30245  *
30246  * 1 4
30247  *
30248  * 3 5
30249  *
30250  * 7 6
30251  *
30252  * 15 7
30253  *
30254  * 31 8
30255  *
30256  * 63 9
30257  *
30258  * [N-1:3] (Isoc):
30259  *
30260  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
30261  *
30262  * Non Isochronous:
30263  *
30264  * This value is in terms of number of descriptors. The values can be from 0 to 63.
30265  *
30266  * 0 - 1 descriptor.
30267  *
30268  * 63 - 64 descriptors.
30269  *
30270  * This field indicates the current descriptor processed in the list. This field is
30271  * updated
30272  *
30273  * both by application and the core. For example, if the application enables the
30274  *
30275  * channel after programming CTD=5, then the core will start processing the 6th
30276  *
30277  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
30278  *
30279  * to DMAAddr.
30280  *
30281  * Isochronous:
30282  *
30283  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
30284  * set
30285  *
30286  * to zero by application.
30287  *
30288  * Field Access Macros:
30289  *
30290  */
30291 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */
30292 #define ALT_USB_HOST_HCDMA4_HCDMA4_LSB 0
30293 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */
30294 #define ALT_USB_HOST_HCDMA4_HCDMA4_MSB 31
30295 /* The width in bits of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */
30296 #define ALT_USB_HOST_HCDMA4_HCDMA4_WIDTH 32
30297 /* The mask used to set the ALT_USB_HOST_HCDMA4_HCDMA4 register field value. */
30298 #define ALT_USB_HOST_HCDMA4_HCDMA4_SET_MSK 0xffffffff
30299 /* The mask used to clear the ALT_USB_HOST_HCDMA4_HCDMA4 register field value. */
30300 #define ALT_USB_HOST_HCDMA4_HCDMA4_CLR_MSK 0x00000000
30301 /* The reset value of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */
30302 #define ALT_USB_HOST_HCDMA4_HCDMA4_RESET 0x0
30303 /* Extracts the ALT_USB_HOST_HCDMA4_HCDMA4 field value from a register. */
30304 #define ALT_USB_HOST_HCDMA4_HCDMA4_GET(value) (((value) & 0xffffffff) >> 0)
30305 /* Produces a ALT_USB_HOST_HCDMA4_HCDMA4 register field value suitable for setting the register. */
30306 #define ALT_USB_HOST_HCDMA4_HCDMA4_SET(value) (((value) << 0) & 0xffffffff)
30307 
30308 #ifndef __ASSEMBLY__
30309 /*
30310  * WARNING: The C register and register group struct declarations are provided for
30311  * convenience and illustrative purposes. They should, however, be used with
30312  * caution as the C language standard provides no guarantees about the alignment or
30313  * atomicity of device memory accesses. The recommended practice for writing
30314  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30315  * alt_write_word() functions.
30316  *
30317  * The struct declaration for register ALT_USB_HOST_HCDMA4.
30318  */
30319 struct ALT_USB_HOST_HCDMA4_s
30320 {
30321  uint32_t hcdma4 : 32; /* ALT_USB_HOST_HCDMA4_HCDMA4 */
30322 };
30323 
30324 /* The typedef declaration for register ALT_USB_HOST_HCDMA4. */
30325 typedef volatile struct ALT_USB_HOST_HCDMA4_s ALT_USB_HOST_HCDMA4_t;
30326 #endif /* __ASSEMBLY__ */
30327 
30328 /* The reset value of the ALT_USB_HOST_HCDMA4 register. */
30329 #define ALT_USB_HOST_HCDMA4_RESET 0x00000000
30330 /* The byte offset of the ALT_USB_HOST_HCDMA4 register from the beginning of the component. */
30331 #define ALT_USB_HOST_HCDMA4_OFST 0x194
30332 /* The address of the ALT_USB_HOST_HCDMA4 register. */
30333 #define ALT_USB_HOST_HCDMA4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA4_OFST))
30334 
30335 /*
30336  * Register : hcdmab4
30337  *
30338  * Host Channel 4 DMA Buffer Address Register
30339  *
30340  * Register Layout
30341  *
30342  * Bits | Access | Reset | Description
30343  * :-------|:-------|:------|:-----------------------------
30344  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB4_HCDMAB4
30345  *
30346  */
30347 /*
30348  * Field : hcdmab4
30349  *
30350  * Holds the current buffer address.
30351  *
30352  * This register is updated as and when the data transfer for the corresponding end
30353  * point
30354  *
30355  * is in progress. This register is present only in Scatter/Gather DMA mode.
30356  * Otherwise this
30357  *
30358  * field is reserved.
30359  *
30360  * Field Access Macros:
30361  *
30362  */
30363 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */
30364 #define ALT_USB_HOST_HCDMAB4_HCDMAB4_LSB 0
30365 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */
30366 #define ALT_USB_HOST_HCDMAB4_HCDMAB4_MSB 31
30367 /* The width in bits of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */
30368 #define ALT_USB_HOST_HCDMAB4_HCDMAB4_WIDTH 32
30369 /* The mask used to set the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field value. */
30370 #define ALT_USB_HOST_HCDMAB4_HCDMAB4_SET_MSK 0xffffffff
30371 /* The mask used to clear the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field value. */
30372 #define ALT_USB_HOST_HCDMAB4_HCDMAB4_CLR_MSK 0x00000000
30373 /* The reset value of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */
30374 #define ALT_USB_HOST_HCDMAB4_HCDMAB4_RESET 0x0
30375 /* Extracts the ALT_USB_HOST_HCDMAB4_HCDMAB4 field value from a register. */
30376 #define ALT_USB_HOST_HCDMAB4_HCDMAB4_GET(value) (((value) & 0xffffffff) >> 0)
30377 /* Produces a ALT_USB_HOST_HCDMAB4_HCDMAB4 register field value suitable for setting the register. */
30378 #define ALT_USB_HOST_HCDMAB4_HCDMAB4_SET(value) (((value) << 0) & 0xffffffff)
30379 
30380 #ifndef __ASSEMBLY__
30381 /*
30382  * WARNING: The C register and register group struct declarations are provided for
30383  * convenience and illustrative purposes. They should, however, be used with
30384  * caution as the C language standard provides no guarantees about the alignment or
30385  * atomicity of device memory accesses. The recommended practice for writing
30386  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30387  * alt_write_word() functions.
30388  *
30389  * The struct declaration for register ALT_USB_HOST_HCDMAB4.
30390  */
30391 struct ALT_USB_HOST_HCDMAB4_s
30392 {
30393  uint32_t hcdmab4 : 32; /* ALT_USB_HOST_HCDMAB4_HCDMAB4 */
30394 };
30395 
30396 /* The typedef declaration for register ALT_USB_HOST_HCDMAB4. */
30397 typedef volatile struct ALT_USB_HOST_HCDMAB4_s ALT_USB_HOST_HCDMAB4_t;
30398 #endif /* __ASSEMBLY__ */
30399 
30400 /* The reset value of the ALT_USB_HOST_HCDMAB4 register. */
30401 #define ALT_USB_HOST_HCDMAB4_RESET 0x00000000
30402 /* The byte offset of the ALT_USB_HOST_HCDMAB4 register from the beginning of the component. */
30403 #define ALT_USB_HOST_HCDMAB4_OFST 0x19c
30404 /* The address of the ALT_USB_HOST_HCDMAB4 register. */
30405 #define ALT_USB_HOST_HCDMAB4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB4_OFST))
30406 
30407 /*
30408  * Register : hcchar5
30409  *
30410  * Host Channel 5 Characteristics Register
30411  *
30412  * Register Layout
30413  *
30414  * Bits | Access | Reset | Description
30415  * :--------|:---------|:------|:-----------------------------
30416  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_MPS
30417  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_EPNUM
30418  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_EPDIR
30419  * [16] | ??? | 0x0 | *UNDEFINED*
30420  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_LSPDDEV
30421  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_EPTYPE
30422  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_EC
30423  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_DEVADDR
30424  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_ODDFRM
30425  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR5_CHDIS
30426  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR5_CHENA
30427  *
30428  */
30429 /*
30430  * Field : mps
30431  *
30432  * Maximum Packet Size (MPS)
30433  *
30434  * Indicates the maximum packet size of the associated endpoint.
30435  *
30436  * Field Access Macros:
30437  *
30438  */
30439 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_MPS register field. */
30440 #define ALT_USB_HOST_HCCHAR5_MPS_LSB 0
30441 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_MPS register field. */
30442 #define ALT_USB_HOST_HCCHAR5_MPS_MSB 10
30443 /* The width in bits of the ALT_USB_HOST_HCCHAR5_MPS register field. */
30444 #define ALT_USB_HOST_HCCHAR5_MPS_WIDTH 11
30445 /* The mask used to set the ALT_USB_HOST_HCCHAR5_MPS register field value. */
30446 #define ALT_USB_HOST_HCCHAR5_MPS_SET_MSK 0x000007ff
30447 /* The mask used to clear the ALT_USB_HOST_HCCHAR5_MPS register field value. */
30448 #define ALT_USB_HOST_HCCHAR5_MPS_CLR_MSK 0xfffff800
30449 /* The reset value of the ALT_USB_HOST_HCCHAR5_MPS register field. */
30450 #define ALT_USB_HOST_HCCHAR5_MPS_RESET 0x0
30451 /* Extracts the ALT_USB_HOST_HCCHAR5_MPS field value from a register. */
30452 #define ALT_USB_HOST_HCCHAR5_MPS_GET(value) (((value) & 0x000007ff) >> 0)
30453 /* Produces a ALT_USB_HOST_HCCHAR5_MPS register field value suitable for setting the register. */
30454 #define ALT_USB_HOST_HCCHAR5_MPS_SET(value) (((value) << 0) & 0x000007ff)
30455 
30456 /*
30457  * Field : epnum
30458  *
30459  * Endpoint Number (EPNum)
30460  *
30461  * Indicates the endpoint number on the device serving as the data
30462  *
30463  * source or sink.
30464  *
30465  * Field Enumeration Values:
30466  *
30467  * Enum | Value | Description
30468  * :-------------------------------------|:------|:--------------
30469  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT0 | 0x0 | End point 0
30470  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT1 | 0x1 | End point 1
30471  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT2 | 0x2 | End point 2
30472  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT3 | 0x3 | End point 3
30473  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT4 | 0x4 | End point 4
30474  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT5 | 0x5 | End point 5
30475  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT6 | 0x6 | End point 6
30476  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT7 | 0x7 | End point 7
30477  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT8 | 0x8 | End point 8
30478  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT9 | 0x9 | End point 9
30479  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT10 | 0xa | End point 10
30480  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT11 | 0xb | End point 11
30481  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT12 | 0xc | End point 12
30482  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT13 | 0xd | End point 13
30483  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT14 | 0xe | End point 14
30484  * ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT15 | 0xf | End point 15
30485  *
30486  * Field Access Macros:
30487  *
30488  */
30489 /*
30490  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30491  *
30492  * End point 0
30493  */
30494 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT0 0x0
30495 /*
30496  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30497  *
30498  * End point 1
30499  */
30500 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT1 0x1
30501 /*
30502  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30503  *
30504  * End point 2
30505  */
30506 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT2 0x2
30507 /*
30508  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30509  *
30510  * End point 3
30511  */
30512 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT3 0x3
30513 /*
30514  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30515  *
30516  * End point 4
30517  */
30518 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT4 0x4
30519 /*
30520  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30521  *
30522  * End point 5
30523  */
30524 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT5 0x5
30525 /*
30526  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30527  *
30528  * End point 6
30529  */
30530 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT6 0x6
30531 /*
30532  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30533  *
30534  * End point 7
30535  */
30536 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT7 0x7
30537 /*
30538  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30539  *
30540  * End point 8
30541  */
30542 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT8 0x8
30543 /*
30544  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30545  *
30546  * End point 9
30547  */
30548 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT9 0x9
30549 /*
30550  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30551  *
30552  * End point 10
30553  */
30554 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT10 0xa
30555 /*
30556  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30557  *
30558  * End point 11
30559  */
30560 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT11 0xb
30561 /*
30562  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30563  *
30564  * End point 12
30565  */
30566 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT12 0xc
30567 /*
30568  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30569  *
30570  * End point 13
30571  */
30572 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT13 0xd
30573 /*
30574  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30575  *
30576  * End point 14
30577  */
30578 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT14 0xe
30579 /*
30580  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
30581  *
30582  * End point 15
30583  */
30584 #define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT15 0xf
30585 
30586 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */
30587 #define ALT_USB_HOST_HCCHAR5_EPNUM_LSB 11
30588 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */
30589 #define ALT_USB_HOST_HCCHAR5_EPNUM_MSB 14
30590 /* The width in bits of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */
30591 #define ALT_USB_HOST_HCCHAR5_EPNUM_WIDTH 4
30592 /* The mask used to set the ALT_USB_HOST_HCCHAR5_EPNUM register field value. */
30593 #define ALT_USB_HOST_HCCHAR5_EPNUM_SET_MSK 0x00007800
30594 /* The mask used to clear the ALT_USB_HOST_HCCHAR5_EPNUM register field value. */
30595 #define ALT_USB_HOST_HCCHAR5_EPNUM_CLR_MSK 0xffff87ff
30596 /* The reset value of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */
30597 #define ALT_USB_HOST_HCCHAR5_EPNUM_RESET 0x0
30598 /* Extracts the ALT_USB_HOST_HCCHAR5_EPNUM field value from a register. */
30599 #define ALT_USB_HOST_HCCHAR5_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
30600 /* Produces a ALT_USB_HOST_HCCHAR5_EPNUM register field value suitable for setting the register. */
30601 #define ALT_USB_HOST_HCCHAR5_EPNUM_SET(value) (((value) << 11) & 0x00007800)
30602 
30603 /*
30604  * Field : epdir
30605  *
30606  * Endpoint Direction (EPDir)
30607  *
30608  * Indicates whether the transaction is IN or OUT.
30609  *
30610  * 1'b0: OUT
30611  *
30612  * 1'b1: IN
30613  *
30614  * Field Enumeration Values:
30615  *
30616  * Enum | Value | Description
30617  * :------------------------------------|:------|:------------
30618  * ALT_USB_HOST_HCCHAR5_EPDIR_E_OUTDIR | 0x0 | OUT
30619  * ALT_USB_HOST_HCCHAR5_EPDIR_E_INDIR | 0x1 | IN
30620  *
30621  * Field Access Macros:
30622  *
30623  */
30624 /*
30625  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPDIR
30626  *
30627  * OUT
30628  */
30629 #define ALT_USB_HOST_HCCHAR5_EPDIR_E_OUTDIR 0x0
30630 /*
30631  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPDIR
30632  *
30633  * IN
30634  */
30635 #define ALT_USB_HOST_HCCHAR5_EPDIR_E_INDIR 0x1
30636 
30637 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */
30638 #define ALT_USB_HOST_HCCHAR5_EPDIR_LSB 15
30639 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */
30640 #define ALT_USB_HOST_HCCHAR5_EPDIR_MSB 15
30641 /* The width in bits of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */
30642 #define ALT_USB_HOST_HCCHAR5_EPDIR_WIDTH 1
30643 /* The mask used to set the ALT_USB_HOST_HCCHAR5_EPDIR register field value. */
30644 #define ALT_USB_HOST_HCCHAR5_EPDIR_SET_MSK 0x00008000
30645 /* The mask used to clear the ALT_USB_HOST_HCCHAR5_EPDIR register field value. */
30646 #define ALT_USB_HOST_HCCHAR5_EPDIR_CLR_MSK 0xffff7fff
30647 /* The reset value of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */
30648 #define ALT_USB_HOST_HCCHAR5_EPDIR_RESET 0x0
30649 /* Extracts the ALT_USB_HOST_HCCHAR5_EPDIR field value from a register. */
30650 #define ALT_USB_HOST_HCCHAR5_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
30651 /* Produces a ALT_USB_HOST_HCCHAR5_EPDIR register field value suitable for setting the register. */
30652 #define ALT_USB_HOST_HCCHAR5_EPDIR_SET(value) (((value) << 15) & 0x00008000)
30653 
30654 /*
30655  * Field : lspddev
30656  *
30657  * Low-Speed Device (LSpdDev)
30658  *
30659  * This field is Set by the application to indicate that this channel is
30660  *
30661  * communicating to a low-speed device.
30662  *
30663  * Field Enumeration Values:
30664  *
30665  * Enum | Value | Description
30666  * :-------------------------------------------|:------|:--------------------------------
30667  * ALT_USB_HOST_HCCHAR5_LSPDDEV_E_NONLOWSPEED | 0x0 | Communicating with non lowspeed
30668  * ALT_USB_HOST_HCCHAR5_LSPDDEV_E_LOWSPEED | 0x1 | Communicating with lowspeed
30669  *
30670  * Field Access Macros:
30671  *
30672  */
30673 /*
30674  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_LSPDDEV
30675  *
30676  * Communicating with non lowspeed
30677  */
30678 #define ALT_USB_HOST_HCCHAR5_LSPDDEV_E_NONLOWSPEED 0x0
30679 /*
30680  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_LSPDDEV
30681  *
30682  * Communicating with lowspeed
30683  */
30684 #define ALT_USB_HOST_HCCHAR5_LSPDDEV_E_LOWSPEED 0x1
30685 
30686 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */
30687 #define ALT_USB_HOST_HCCHAR5_LSPDDEV_LSB 17
30688 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */
30689 #define ALT_USB_HOST_HCCHAR5_LSPDDEV_MSB 17
30690 /* The width in bits of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */
30691 #define ALT_USB_HOST_HCCHAR5_LSPDDEV_WIDTH 1
30692 /* The mask used to set the ALT_USB_HOST_HCCHAR5_LSPDDEV register field value. */
30693 #define ALT_USB_HOST_HCCHAR5_LSPDDEV_SET_MSK 0x00020000
30694 /* The mask used to clear the ALT_USB_HOST_HCCHAR5_LSPDDEV register field value. */
30695 #define ALT_USB_HOST_HCCHAR5_LSPDDEV_CLR_MSK 0xfffdffff
30696 /* The reset value of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */
30697 #define ALT_USB_HOST_HCCHAR5_LSPDDEV_RESET 0x0
30698 /* Extracts the ALT_USB_HOST_HCCHAR5_LSPDDEV field value from a register. */
30699 #define ALT_USB_HOST_HCCHAR5_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
30700 /* Produces a ALT_USB_HOST_HCCHAR5_LSPDDEV register field value suitable for setting the register. */
30701 #define ALT_USB_HOST_HCCHAR5_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
30702 
30703 /*
30704  * Field : eptype
30705  *
30706  * Endpoint Type (EPType)
30707  *
30708  * Indicates the transfer type selected.
30709  *
30710  * 2'b00: Control
30711  *
30712  * 2'b01: Isochronous
30713  *
30714  * 2'b10: Bulk
30715  *
30716  * 2'b11: Interrupt
30717  *
30718  * Field Enumeration Values:
30719  *
30720  * Enum | Value | Description
30721  * :-------------------------------------|:------|:------------
30722  * ALT_USB_HOST_HCCHAR5_EPTYPE_E_CTL | 0x0 | Control
30723  * ALT_USB_HOST_HCCHAR5_EPTYPE_E_ISOC | 0x1 | Isochronous
30724  * ALT_USB_HOST_HCCHAR5_EPTYPE_E_BULK | 0x2 | Bulk
30725  * ALT_USB_HOST_HCCHAR5_EPTYPE_E_INTERR | 0x3 | Interrupt
30726  *
30727  * Field Access Macros:
30728  *
30729  */
30730 /*
30731  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE
30732  *
30733  * Control
30734  */
30735 #define ALT_USB_HOST_HCCHAR5_EPTYPE_E_CTL 0x0
30736 /*
30737  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE
30738  *
30739  * Isochronous
30740  */
30741 #define ALT_USB_HOST_HCCHAR5_EPTYPE_E_ISOC 0x1
30742 /*
30743  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE
30744  *
30745  * Bulk
30746  */
30747 #define ALT_USB_HOST_HCCHAR5_EPTYPE_E_BULK 0x2
30748 /*
30749  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE
30750  *
30751  * Interrupt
30752  */
30753 #define ALT_USB_HOST_HCCHAR5_EPTYPE_E_INTERR 0x3
30754 
30755 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */
30756 #define ALT_USB_HOST_HCCHAR5_EPTYPE_LSB 18
30757 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */
30758 #define ALT_USB_HOST_HCCHAR5_EPTYPE_MSB 19
30759 /* The width in bits of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */
30760 #define ALT_USB_HOST_HCCHAR5_EPTYPE_WIDTH 2
30761 /* The mask used to set the ALT_USB_HOST_HCCHAR5_EPTYPE register field value. */
30762 #define ALT_USB_HOST_HCCHAR5_EPTYPE_SET_MSK 0x000c0000
30763 /* The mask used to clear the ALT_USB_HOST_HCCHAR5_EPTYPE register field value. */
30764 #define ALT_USB_HOST_HCCHAR5_EPTYPE_CLR_MSK 0xfff3ffff
30765 /* The reset value of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */
30766 #define ALT_USB_HOST_HCCHAR5_EPTYPE_RESET 0x0
30767 /* Extracts the ALT_USB_HOST_HCCHAR5_EPTYPE field value from a register. */
30768 #define ALT_USB_HOST_HCCHAR5_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
30769 /* Produces a ALT_USB_HOST_HCCHAR5_EPTYPE register field value suitable for setting the register. */
30770 #define ALT_USB_HOST_HCCHAR5_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
30771 
30772 /*
30773  * Field : ec
30774  *
30775  * Multi Count (MC) / Error Count (EC)
30776  *
30777  * When the Split Enable bit of the Host Channel-n Split Control
30778  *
30779  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
30780  *
30781  * the host the number of transactions that must be executed per
30782  *
30783  * microframe For this periodic endpoint. For non periodic transfers,
30784  *
30785  * this field is used only in DMA mode, and specifies the number
30786  *
30787  * packets to be fetched For this channel before the internal DMA
30788  *
30789  * engine changes arbitration.
30790  *
30791  * 2'b00: Reserved This field yields undefined results.
30792  *
30793  * 2'b01: 1 transaction
30794  *
30795  * 2'b10: 2 transactions to be issued For this endpoint per
30796  *
30797  * microframe
30798  *
30799  * 2'b11: 3 transactions to be issued For this endpoint per
30800  *
30801  * microframe
30802  *
30803  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
30804  *
30805  * number of immediate retries to be performed For a periodic split
30806  *
30807  * transactions on transaction errors. This field must be Set to at
30808  *
30809  * least 2'b01.
30810  *
30811  * Field Enumeration Values:
30812  *
30813  * Enum | Value | Description
30814  * :-------------------------------------|:------|:----------------------------------------------
30815  * ALT_USB_HOST_HCCHAR5_EC_E_RSVD | 0x0 | Reserved This field yields undefined results
30816  * ALT_USB_HOST_HCCHAR5_EC_E_TRANSONE | 0x1 | 1 transaction
30817  * ALT_USB_HOST_HCCHAR5_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
30818  * : | | per microframe
30819  * ALT_USB_HOST_HCCHAR5_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
30820  * : | | per microframe
30821  *
30822  * Field Access Macros:
30823  *
30824  */
30825 /*
30826  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC
30827  *
30828  * Reserved This field yields undefined results
30829  */
30830 #define ALT_USB_HOST_HCCHAR5_EC_E_RSVD 0x0
30831 /*
30832  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC
30833  *
30834  * 1 transaction
30835  */
30836 #define ALT_USB_HOST_HCCHAR5_EC_E_TRANSONE 0x1
30837 /*
30838  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC
30839  *
30840  * 2 transactions to be issued for this endpoint per microframe
30841  */
30842 #define ALT_USB_HOST_HCCHAR5_EC_E_TRANSTWO 0x2
30843 /*
30844  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC
30845  *
30846  * 3 transactions to be issued for this endpoint per microframe
30847  */
30848 #define ALT_USB_HOST_HCCHAR5_EC_E_TRANSTHREE 0x3
30849 
30850 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EC register field. */
30851 #define ALT_USB_HOST_HCCHAR5_EC_LSB 20
30852 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EC register field. */
30853 #define ALT_USB_HOST_HCCHAR5_EC_MSB 21
30854 /* The width in bits of the ALT_USB_HOST_HCCHAR5_EC register field. */
30855 #define ALT_USB_HOST_HCCHAR5_EC_WIDTH 2
30856 /* The mask used to set the ALT_USB_HOST_HCCHAR5_EC register field value. */
30857 #define ALT_USB_HOST_HCCHAR5_EC_SET_MSK 0x00300000
30858 /* The mask used to clear the ALT_USB_HOST_HCCHAR5_EC register field value. */
30859 #define ALT_USB_HOST_HCCHAR5_EC_CLR_MSK 0xffcfffff
30860 /* The reset value of the ALT_USB_HOST_HCCHAR5_EC register field. */
30861 #define ALT_USB_HOST_HCCHAR5_EC_RESET 0x0
30862 /* Extracts the ALT_USB_HOST_HCCHAR5_EC field value from a register. */
30863 #define ALT_USB_HOST_HCCHAR5_EC_GET(value) (((value) & 0x00300000) >> 20)
30864 /* Produces a ALT_USB_HOST_HCCHAR5_EC register field value suitable for setting the register. */
30865 #define ALT_USB_HOST_HCCHAR5_EC_SET(value) (((value) << 20) & 0x00300000)
30866 
30867 /*
30868  * Field : devaddr
30869  *
30870  * Device Address (DevAddr)
30871  *
30872  * This field selects the specific device serving as the data source
30873  *
30874  * or sink.
30875  *
30876  * Field Access Macros:
30877  *
30878  */
30879 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */
30880 #define ALT_USB_HOST_HCCHAR5_DEVADDR_LSB 22
30881 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */
30882 #define ALT_USB_HOST_HCCHAR5_DEVADDR_MSB 28
30883 /* The width in bits of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */
30884 #define ALT_USB_HOST_HCCHAR5_DEVADDR_WIDTH 7
30885 /* The mask used to set the ALT_USB_HOST_HCCHAR5_DEVADDR register field value. */
30886 #define ALT_USB_HOST_HCCHAR5_DEVADDR_SET_MSK 0x1fc00000
30887 /* The mask used to clear the ALT_USB_HOST_HCCHAR5_DEVADDR register field value. */
30888 #define ALT_USB_HOST_HCCHAR5_DEVADDR_CLR_MSK 0xe03fffff
30889 /* The reset value of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */
30890 #define ALT_USB_HOST_HCCHAR5_DEVADDR_RESET 0x0
30891 /* Extracts the ALT_USB_HOST_HCCHAR5_DEVADDR field value from a register. */
30892 #define ALT_USB_HOST_HCCHAR5_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
30893 /* Produces a ALT_USB_HOST_HCCHAR5_DEVADDR register field value suitable for setting the register. */
30894 #define ALT_USB_HOST_HCCHAR5_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
30895 
30896 /*
30897  * Field : oddfrm
30898  *
30899  * Odd Frame (OddFrm)
30900  *
30901  * This field is set (reset) by the application to indicate that the OTG host must
30902  * perform
30903  *
30904  * a transfer in an odd (micro)frame. This field is applicable for only periodic
30905  *
30906  * (isochronous and interrupt) transactions.
30907  *
30908  * 1'b0: Even (micro)frame
30909  *
30910  * 1'b1: Odd (micro)frame
30911  *
30912  * Field Access Macros:
30913  *
30914  */
30915 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_ODDFRM register field. */
30916 #define ALT_USB_HOST_HCCHAR5_ODDFRM_LSB 29
30917 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_ODDFRM register field. */
30918 #define ALT_USB_HOST_HCCHAR5_ODDFRM_MSB 29
30919 /* The width in bits of the ALT_USB_HOST_HCCHAR5_ODDFRM register field. */
30920 #define ALT_USB_HOST_HCCHAR5_ODDFRM_WIDTH 1
30921 /* The mask used to set the ALT_USB_HOST_HCCHAR5_ODDFRM register field value. */
30922 #define ALT_USB_HOST_HCCHAR5_ODDFRM_SET_MSK 0x20000000
30923 /* The mask used to clear the ALT_USB_HOST_HCCHAR5_ODDFRM register field value. */
30924 #define ALT_USB_HOST_HCCHAR5_ODDFRM_CLR_MSK 0xdfffffff
30925 /* The reset value of the ALT_USB_HOST_HCCHAR5_ODDFRM register field. */
30926 #define ALT_USB_HOST_HCCHAR5_ODDFRM_RESET 0x0
30927 /* Extracts the ALT_USB_HOST_HCCHAR5_ODDFRM field value from a register. */
30928 #define ALT_USB_HOST_HCCHAR5_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
30929 /* Produces a ALT_USB_HOST_HCCHAR5_ODDFRM register field value suitable for setting the register. */
30930 #define ALT_USB_HOST_HCCHAR5_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
30931 
30932 /*
30933  * Field : chdis
30934  *
30935  * Channel Disable (ChDis)
30936  *
30937  * The application sets this bit to stop transmitting/receiving data
30938  *
30939  * on a channel, even before the transfer For that channel is
30940  *
30941  * complete. The application must wait For the Channel Disabled
30942  *
30943  * interrupt before treating the channel as disabled.
30944  *
30945  * Field Enumeration Values:
30946  *
30947  * Enum | Value | Description
30948  * :-----------------------------------|:------|:---------------------------------
30949  * ALT_USB_HOST_HCCHAR5_CHDIS_E_INACT | 0x0 | No activity
30950  * ALT_USB_HOST_HCCHAR5_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving data
30951  *
30952  * Field Access Macros:
30953  *
30954  */
30955 /*
30956  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHDIS
30957  *
30958  * No activity
30959  */
30960 #define ALT_USB_HOST_HCCHAR5_CHDIS_E_INACT 0x0
30961 /*
30962  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHDIS
30963  *
30964  * Stop transmitting/receiving data
30965  */
30966 #define ALT_USB_HOST_HCCHAR5_CHDIS_E_ACT 0x1
30967 
30968 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */
30969 #define ALT_USB_HOST_HCCHAR5_CHDIS_LSB 30
30970 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */
30971 #define ALT_USB_HOST_HCCHAR5_CHDIS_MSB 30
30972 /* The width in bits of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */
30973 #define ALT_USB_HOST_HCCHAR5_CHDIS_WIDTH 1
30974 /* The mask used to set the ALT_USB_HOST_HCCHAR5_CHDIS register field value. */
30975 #define ALT_USB_HOST_HCCHAR5_CHDIS_SET_MSK 0x40000000
30976 /* The mask used to clear the ALT_USB_HOST_HCCHAR5_CHDIS register field value. */
30977 #define ALT_USB_HOST_HCCHAR5_CHDIS_CLR_MSK 0xbfffffff
30978 /* The reset value of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */
30979 #define ALT_USB_HOST_HCCHAR5_CHDIS_RESET 0x0
30980 /* Extracts the ALT_USB_HOST_HCCHAR5_CHDIS field value from a register. */
30981 #define ALT_USB_HOST_HCCHAR5_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
30982 /* Produces a ALT_USB_HOST_HCCHAR5_CHDIS register field value suitable for setting the register. */
30983 #define ALT_USB_HOST_HCCHAR5_CHDIS_SET(value) (((value) << 30) & 0x40000000)
30984 
30985 /*
30986  * Field : chena
30987  *
30988  * Channel Enable (ChEna)
30989  *
30990  * When Scatter/Gather mode is enabled
30991  *
30992  * 1'b0: Indicates that the descriptor structure is not yet ready.
30993  *
30994  * 1'b1: Indicates that the descriptor structure and data buffer with
30995  *
30996  * data is setup and this channel can access the descriptor.
30997  *
30998  * When Scatter/Gather mode is disabled
30999  *
31000  * This field is set by the application and cleared by the OTG host.
31001  *
31002  * 1'b0: Channel disabled
31003  *
31004  * 1'b1: Channel enabled
31005  *
31006  * Field Enumeration Values:
31007  *
31008  * Enum | Value | Description
31009  * :------------------------------------|:------|:-------------------------------------------------
31010  * ALT_USB_HOST_HCCHAR5_CHENA_E_NOTRDY | 0x0 | Indicates that the descriptor structure is not
31011  * : | | yet ready
31012  * ALT_USB_HOST_HCCHAR5_CHENA_E_RDY | 0x1 | Indicates that the descriptor structure and data
31013  * : | | buffer with data is setup and this channel can
31014  * : | | access the descriptor
31015  *
31016  * Field Access Macros:
31017  *
31018  */
31019 /*
31020  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHENA
31021  *
31022  * Indicates that the descriptor structure is not yet ready
31023  */
31024 #define ALT_USB_HOST_HCCHAR5_CHENA_E_NOTRDY 0x0
31025 /*
31026  * Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHENA
31027  *
31028  * Indicates that the descriptor structure and data buffer with data is setup and
31029  * this channel can access the descriptor
31030  */
31031 #define ALT_USB_HOST_HCCHAR5_CHENA_E_RDY 0x1
31032 
31033 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_CHENA register field. */
31034 #define ALT_USB_HOST_HCCHAR5_CHENA_LSB 31
31035 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_CHENA register field. */
31036 #define ALT_USB_HOST_HCCHAR5_CHENA_MSB 31
31037 /* The width in bits of the ALT_USB_HOST_HCCHAR5_CHENA register field. */
31038 #define ALT_USB_HOST_HCCHAR5_CHENA_WIDTH 1
31039 /* The mask used to set the ALT_USB_HOST_HCCHAR5_CHENA register field value. */
31040 #define ALT_USB_HOST_HCCHAR5_CHENA_SET_MSK 0x80000000
31041 /* The mask used to clear the ALT_USB_HOST_HCCHAR5_CHENA register field value. */
31042 #define ALT_USB_HOST_HCCHAR5_CHENA_CLR_MSK 0x7fffffff
31043 /* The reset value of the ALT_USB_HOST_HCCHAR5_CHENA register field. */
31044 #define ALT_USB_HOST_HCCHAR5_CHENA_RESET 0x0
31045 /* Extracts the ALT_USB_HOST_HCCHAR5_CHENA field value from a register. */
31046 #define ALT_USB_HOST_HCCHAR5_CHENA_GET(value) (((value) & 0x80000000) >> 31)
31047 /* Produces a ALT_USB_HOST_HCCHAR5_CHENA register field value suitable for setting the register. */
31048 #define ALT_USB_HOST_HCCHAR5_CHENA_SET(value) (((value) << 31) & 0x80000000)
31049 
31050 #ifndef __ASSEMBLY__
31051 /*
31052  * WARNING: The C register and register group struct declarations are provided for
31053  * convenience and illustrative purposes. They should, however, be used with
31054  * caution as the C language standard provides no guarantees about the alignment or
31055  * atomicity of device memory accesses. The recommended practice for writing
31056  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31057  * alt_write_word() functions.
31058  *
31059  * The struct declaration for register ALT_USB_HOST_HCCHAR5.
31060  */
31061 struct ALT_USB_HOST_HCCHAR5_s
31062 {
31063  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR5_MPS */
31064  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR5_EPNUM */
31065  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR5_EPDIR */
31066  uint32_t : 1; /* *UNDEFINED* */
31067  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR5_LSPDDEV */
31068  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR5_EPTYPE */
31069  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR5_EC */
31070  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR5_DEVADDR */
31071  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR5_ODDFRM */
31072  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR5_CHDIS */
31073  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR5_CHENA */
31074 };
31075 
31076 /* The typedef declaration for register ALT_USB_HOST_HCCHAR5. */
31077 typedef volatile struct ALT_USB_HOST_HCCHAR5_s ALT_USB_HOST_HCCHAR5_t;
31078 #endif /* __ASSEMBLY__ */
31079 
31080 /* The reset value of the ALT_USB_HOST_HCCHAR5 register. */
31081 #define ALT_USB_HOST_HCCHAR5_RESET 0x00000000
31082 /* The byte offset of the ALT_USB_HOST_HCCHAR5 register from the beginning of the component. */
31083 #define ALT_USB_HOST_HCCHAR5_OFST 0x1a0
31084 /* The address of the ALT_USB_HOST_HCCHAR5 register. */
31085 #define ALT_USB_HOST_HCCHAR5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR5_OFST))
31086 
31087 /*
31088  * Register : hcsplt5
31089  *
31090  * Host Channel 5 Split Control Register
31091  *
31092  * Register Layout
31093  *
31094  * Bits | Access | Reset | Description
31095  * :--------|:-------|:------|:------------------------------
31096  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT5_PRTADDR
31097  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT5_HUBADDR
31098  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT5_XACTPOS
31099  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT5_COMPSPLT
31100  * [30:17] | ??? | 0x0 | *UNDEFINED*
31101  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT5_SPLTENA
31102  *
31103  */
31104 /*
31105  * Field : prtaddr
31106  *
31107  * Port Address (PrtAddr)
31108  *
31109  * This field is the port number of the recipient transaction
31110  *
31111  * translator.
31112  *
31113  * Field Access Macros:
31114  *
31115  */
31116 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */
31117 #define ALT_USB_HOST_HCSPLT5_PRTADDR_LSB 0
31118 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */
31119 #define ALT_USB_HOST_HCSPLT5_PRTADDR_MSB 6
31120 /* The width in bits of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */
31121 #define ALT_USB_HOST_HCSPLT5_PRTADDR_WIDTH 7
31122 /* The mask used to set the ALT_USB_HOST_HCSPLT5_PRTADDR register field value. */
31123 #define ALT_USB_HOST_HCSPLT5_PRTADDR_SET_MSK 0x0000007f
31124 /* The mask used to clear the ALT_USB_HOST_HCSPLT5_PRTADDR register field value. */
31125 #define ALT_USB_HOST_HCSPLT5_PRTADDR_CLR_MSK 0xffffff80
31126 /* The reset value of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */
31127 #define ALT_USB_HOST_HCSPLT5_PRTADDR_RESET 0x0
31128 /* Extracts the ALT_USB_HOST_HCSPLT5_PRTADDR field value from a register. */
31129 #define ALT_USB_HOST_HCSPLT5_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
31130 /* Produces a ALT_USB_HOST_HCSPLT5_PRTADDR register field value suitable for setting the register. */
31131 #define ALT_USB_HOST_HCSPLT5_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
31132 
31133 /*
31134  * Field : hubaddr
31135  *
31136  * Hub Address (HubAddr)
31137  *
31138  * This field holds the device address of the transaction translator's
31139  *
31140  * hub.
31141  *
31142  * Field Access Macros:
31143  *
31144  */
31145 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */
31146 #define ALT_USB_HOST_HCSPLT5_HUBADDR_LSB 7
31147 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */
31148 #define ALT_USB_HOST_HCSPLT5_HUBADDR_MSB 13
31149 /* The width in bits of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */
31150 #define ALT_USB_HOST_HCSPLT5_HUBADDR_WIDTH 7
31151 /* The mask used to set the ALT_USB_HOST_HCSPLT5_HUBADDR register field value. */
31152 #define ALT_USB_HOST_HCSPLT5_HUBADDR_SET_MSK 0x00003f80
31153 /* The mask used to clear the ALT_USB_HOST_HCSPLT5_HUBADDR register field value. */
31154 #define ALT_USB_HOST_HCSPLT5_HUBADDR_CLR_MSK 0xffffc07f
31155 /* The reset value of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */
31156 #define ALT_USB_HOST_HCSPLT5_HUBADDR_RESET 0x0
31157 /* Extracts the ALT_USB_HOST_HCSPLT5_HUBADDR field value from a register. */
31158 #define ALT_USB_HOST_HCSPLT5_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
31159 /* Produces a ALT_USB_HOST_HCSPLT5_HUBADDR register field value suitable for setting the register. */
31160 #define ALT_USB_HOST_HCSPLT5_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
31161 
31162 /*
31163  * Field : xactpos
31164  *
31165  * Transaction Position (XactPos)
31166  *
31167  * This field is used to determine whether to send all, first, middle,
31168  *
31169  * or last payloads with each OUT transaction.
31170  *
31171  * 2'b11: All. This is the entire data payload is of this transaction
31172  *
31173  * (which is less than or equal to 188 bytes).
31174  *
31175  * 2'b10: Begin. This is the first data payload of this transaction
31176  *
31177  * (which is larger than 188 bytes).
31178  *
31179  * 2'b00: Mid. This is the middle payload of this transaction
31180  *
31181  * (which is larger than 188 bytes).
31182  *
31183  * 2'b01: End. This is the last payload of this transaction (which
31184  *
31185  * is larger than 188 bytes).
31186  *
31187  * Field Enumeration Values:
31188  *
31189  * Enum | Value | Description
31190  * :--------------------------------------|:------|:------------------------------------------------
31191  * ALT_USB_HOST_HCSPLT5_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
31192  * : | | transaction (which is larger than 188 bytes)
31193  * ALT_USB_HOST_HCSPLT5_XACTPOS_E_END | 0x1 | End. This is the last payload of this
31194  * : | | transaction (which is larger than 188 bytes)
31195  * ALT_USB_HOST_HCSPLT5_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
31196  * : | | transaction (which is larger than 188 bytes)
31197  * ALT_USB_HOST_HCSPLT5_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
31198  * : | | transaction (which is less than or equal to 188
31199  * : | | bytes)
31200  *
31201  * Field Access Macros:
31202  *
31203  */
31204 /*
31205  * Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS
31206  *
31207  * Mid. This is the middle payload of this transaction (which is larger than 188
31208  * bytes)
31209  */
31210 #define ALT_USB_HOST_HCSPLT5_XACTPOS_E_MIDDLE 0x0
31211 /*
31212  * Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS
31213  *
31214  * End. This is the last payload of this transaction (which is larger than 188
31215  * bytes)
31216  */
31217 #define ALT_USB_HOST_HCSPLT5_XACTPOS_E_END 0x1
31218 /*
31219  * Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS
31220  *
31221  * Begin. This is the first data payload of this transaction (which is larger than
31222  * 188 bytes)
31223  */
31224 #define ALT_USB_HOST_HCSPLT5_XACTPOS_E_BEGIN 0x2
31225 /*
31226  * Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS
31227  *
31228  * All. This is the entire data payload is of this transaction (which is less than
31229  * or equal to 188 bytes)
31230  */
31231 #define ALT_USB_HOST_HCSPLT5_XACTPOS_E_ALL 0x3
31232 
31233 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */
31234 #define ALT_USB_HOST_HCSPLT5_XACTPOS_LSB 14
31235 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */
31236 #define ALT_USB_HOST_HCSPLT5_XACTPOS_MSB 15
31237 /* The width in bits of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */
31238 #define ALT_USB_HOST_HCSPLT5_XACTPOS_WIDTH 2
31239 /* The mask used to set the ALT_USB_HOST_HCSPLT5_XACTPOS register field value. */
31240 #define ALT_USB_HOST_HCSPLT5_XACTPOS_SET_MSK 0x0000c000
31241 /* The mask used to clear the ALT_USB_HOST_HCSPLT5_XACTPOS register field value. */
31242 #define ALT_USB_HOST_HCSPLT5_XACTPOS_CLR_MSK 0xffff3fff
31243 /* The reset value of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */
31244 #define ALT_USB_HOST_HCSPLT5_XACTPOS_RESET 0x0
31245 /* Extracts the ALT_USB_HOST_HCSPLT5_XACTPOS field value from a register. */
31246 #define ALT_USB_HOST_HCSPLT5_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
31247 /* Produces a ALT_USB_HOST_HCSPLT5_XACTPOS register field value suitable for setting the register. */
31248 #define ALT_USB_HOST_HCSPLT5_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
31249 
31250 /*
31251  * Field : compsplt
31252  *
31253  * Do Complete Split (CompSplt)
31254  *
31255  * The application sets this field to request the OTG host to perform
31256  *
31257  * a complete split transaction.
31258  *
31259  * Field Enumeration Values:
31260  *
31261  * Enum | Value | Description
31262  * :----------------------------------------|:------|:---------------------
31263  * ALT_USB_HOST_HCSPLT5_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
31264  * ALT_USB_HOST_HCSPLT5_COMPSPLT_E_SPLIT | 0x1 | Split transaction
31265  *
31266  * Field Access Macros:
31267  *
31268  */
31269 /*
31270  * Enumerated value for register field ALT_USB_HOST_HCSPLT5_COMPSPLT
31271  *
31272  * No split transaction
31273  */
31274 #define ALT_USB_HOST_HCSPLT5_COMPSPLT_E_NOSPLIT 0x0
31275 /*
31276  * Enumerated value for register field ALT_USB_HOST_HCSPLT5_COMPSPLT
31277  *
31278  * Split transaction
31279  */
31280 #define ALT_USB_HOST_HCSPLT5_COMPSPLT_E_SPLIT 0x1
31281 
31282 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */
31283 #define ALT_USB_HOST_HCSPLT5_COMPSPLT_LSB 16
31284 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */
31285 #define ALT_USB_HOST_HCSPLT5_COMPSPLT_MSB 16
31286 /* The width in bits of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */
31287 #define ALT_USB_HOST_HCSPLT5_COMPSPLT_WIDTH 1
31288 /* The mask used to set the ALT_USB_HOST_HCSPLT5_COMPSPLT register field value. */
31289 #define ALT_USB_HOST_HCSPLT5_COMPSPLT_SET_MSK 0x00010000
31290 /* The mask used to clear the ALT_USB_HOST_HCSPLT5_COMPSPLT register field value. */
31291 #define ALT_USB_HOST_HCSPLT5_COMPSPLT_CLR_MSK 0xfffeffff
31292 /* The reset value of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */
31293 #define ALT_USB_HOST_HCSPLT5_COMPSPLT_RESET 0x0
31294 /* Extracts the ALT_USB_HOST_HCSPLT5_COMPSPLT field value from a register. */
31295 #define ALT_USB_HOST_HCSPLT5_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
31296 /* Produces a ALT_USB_HOST_HCSPLT5_COMPSPLT register field value suitable for setting the register. */
31297 #define ALT_USB_HOST_HCSPLT5_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
31298 
31299 /*
31300  * Field : spltena
31301  *
31302  * Split Enable (SpltEna)
31303  *
31304  * The application sets this field to indicate that this channel is
31305  *
31306  * enabled to perform split transactions.
31307  *
31308  * Field Enumeration Values:
31309  *
31310  * Enum | Value | Description
31311  * :------------------------------------|:------|:------------------
31312  * ALT_USB_HOST_HCSPLT5_SPLTENA_E_DISD | 0x0 | Split not enabled
31313  * ALT_USB_HOST_HCSPLT5_SPLTENA_E_END | 0x1 | Split enabled
31314  *
31315  * Field Access Macros:
31316  *
31317  */
31318 /*
31319  * Enumerated value for register field ALT_USB_HOST_HCSPLT5_SPLTENA
31320  *
31321  * Split not enabled
31322  */
31323 #define ALT_USB_HOST_HCSPLT5_SPLTENA_E_DISD 0x0
31324 /*
31325  * Enumerated value for register field ALT_USB_HOST_HCSPLT5_SPLTENA
31326  *
31327  * Split enabled
31328  */
31329 #define ALT_USB_HOST_HCSPLT5_SPLTENA_E_END 0x1
31330 
31331 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */
31332 #define ALT_USB_HOST_HCSPLT5_SPLTENA_LSB 31
31333 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */
31334 #define ALT_USB_HOST_HCSPLT5_SPLTENA_MSB 31
31335 /* The width in bits of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */
31336 #define ALT_USB_HOST_HCSPLT5_SPLTENA_WIDTH 1
31337 /* The mask used to set the ALT_USB_HOST_HCSPLT5_SPLTENA register field value. */
31338 #define ALT_USB_HOST_HCSPLT5_SPLTENA_SET_MSK 0x80000000
31339 /* The mask used to clear the ALT_USB_HOST_HCSPLT5_SPLTENA register field value. */
31340 #define ALT_USB_HOST_HCSPLT5_SPLTENA_CLR_MSK 0x7fffffff
31341 /* The reset value of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */
31342 #define ALT_USB_HOST_HCSPLT5_SPLTENA_RESET 0x0
31343 /* Extracts the ALT_USB_HOST_HCSPLT5_SPLTENA field value from a register. */
31344 #define ALT_USB_HOST_HCSPLT5_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
31345 /* Produces a ALT_USB_HOST_HCSPLT5_SPLTENA register field value suitable for setting the register. */
31346 #define ALT_USB_HOST_HCSPLT5_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
31347 
31348 #ifndef __ASSEMBLY__
31349 /*
31350  * WARNING: The C register and register group struct declarations are provided for
31351  * convenience and illustrative purposes. They should, however, be used with
31352  * caution as the C language standard provides no guarantees about the alignment or
31353  * atomicity of device memory accesses. The recommended practice for writing
31354  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31355  * alt_write_word() functions.
31356  *
31357  * The struct declaration for register ALT_USB_HOST_HCSPLT5.
31358  */
31359 struct ALT_USB_HOST_HCSPLT5_s
31360 {
31361  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT5_PRTADDR */
31362  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT5_HUBADDR */
31363  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT5_XACTPOS */
31364  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT5_COMPSPLT */
31365  uint32_t : 14; /* *UNDEFINED* */
31366  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT5_SPLTENA */
31367 };
31368 
31369 /* The typedef declaration for register ALT_USB_HOST_HCSPLT5. */
31370 typedef volatile struct ALT_USB_HOST_HCSPLT5_s ALT_USB_HOST_HCSPLT5_t;
31371 #endif /* __ASSEMBLY__ */
31372 
31373 /* The reset value of the ALT_USB_HOST_HCSPLT5 register. */
31374 #define ALT_USB_HOST_HCSPLT5_RESET 0x00000000
31375 /* The byte offset of the ALT_USB_HOST_HCSPLT5 register from the beginning of the component. */
31376 #define ALT_USB_HOST_HCSPLT5_OFST 0x1a4
31377 /* The address of the ALT_USB_HOST_HCSPLT5 register. */
31378 #define ALT_USB_HOST_HCSPLT5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT5_OFST))
31379 
31380 /*
31381  * Register : hcint5
31382  *
31383  * Host Channel 5 Interrupt Register
31384  *
31385  * Register Layout
31386  *
31387  * Bits | Access | Reset | Description
31388  * :--------|:-------|:------|:--------------------------------------
31389  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT5_XFERCOMPL
31390  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT5_CHHLTD
31391  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT5_AHBERR
31392  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT5_STALL
31393  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT5_NAK
31394  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT5_ACK
31395  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT5_NYET
31396  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT5_XACTERR
31397  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT5_BBLERR
31398  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT5_FRMOVRUN
31399  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT5_DATATGLERR
31400  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT5_BNAINTR
31401  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT5_XCS_XACT_ERR
31402  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR
31403  * [31:14] | ??? | 0x0 | *UNDEFINED*
31404  *
31405  */
31406 /*
31407  * Field : xfercompl
31408  *
31409  * Transfer Completed (XferCompl)
31410  *
31411  * Transfer completed normally without any errors.This bit can be set only by the
31412  * core and the application should write 1 to clear it.
31413  *
31414  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
31415  *
31416  * completed with IOC bit set in its descriptor.
31417  *
31418  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
31419  * without
31420  *
31421  * any errors.
31422  *
31423  * Field Enumeration Values:
31424  *
31425  * Enum | Value | Description
31426  * :--------------------------------------|:------|:-----------------------------------------------
31427  * ALT_USB_HOST_HCINT5_XFERCOMPL_E_INACT | 0x0 | No transfer
31428  * ALT_USB_HOST_HCINT5_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
31429  *
31430  * Field Access Macros:
31431  *
31432  */
31433 /*
31434  * Enumerated value for register field ALT_USB_HOST_HCINT5_XFERCOMPL
31435  *
31436  * No transfer
31437  */
31438 #define ALT_USB_HOST_HCINT5_XFERCOMPL_E_INACT 0x0
31439 /*
31440  * Enumerated value for register field ALT_USB_HOST_HCINT5_XFERCOMPL
31441  *
31442  * Transfer completed normally without any errors
31443  */
31444 #define ALT_USB_HOST_HCINT5_XFERCOMPL_E_ACT 0x1
31445 
31446 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */
31447 #define ALT_USB_HOST_HCINT5_XFERCOMPL_LSB 0
31448 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */
31449 #define ALT_USB_HOST_HCINT5_XFERCOMPL_MSB 0
31450 /* The width in bits of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */
31451 #define ALT_USB_HOST_HCINT5_XFERCOMPL_WIDTH 1
31452 /* The mask used to set the ALT_USB_HOST_HCINT5_XFERCOMPL register field value. */
31453 #define ALT_USB_HOST_HCINT5_XFERCOMPL_SET_MSK 0x00000001
31454 /* The mask used to clear the ALT_USB_HOST_HCINT5_XFERCOMPL register field value. */
31455 #define ALT_USB_HOST_HCINT5_XFERCOMPL_CLR_MSK 0xfffffffe
31456 /* The reset value of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */
31457 #define ALT_USB_HOST_HCINT5_XFERCOMPL_RESET 0x0
31458 /* Extracts the ALT_USB_HOST_HCINT5_XFERCOMPL field value from a register. */
31459 #define ALT_USB_HOST_HCINT5_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
31460 /* Produces a ALT_USB_HOST_HCINT5_XFERCOMPL register field value suitable for setting the register. */
31461 #define ALT_USB_HOST_HCINT5_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
31462 
31463 /*
31464  * Field : chhltd
31465  *
31466  * Channel Halted (ChHltd)
31467  *
31468  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
31469  * either because of any USB transaction error or in response to disable request by
31470  * the application or because of a completed transfer.
31471  *
31472  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
31473  * the following
31474  *
31475  * . EOL being set in descriptor
31476  *
31477  * . AHB error
31478  *
31479  * . Excessive transaction errors
31480  *
31481  * . Babble
31482  *
31483  * . Stall
31484  *
31485  * Field Enumeration Values:
31486  *
31487  * Enum | Value | Description
31488  * :-----------------------------------|:------|:-------------------
31489  * ALT_USB_HOST_HCINT5_CHHLTD_E_INACT | 0x0 | Channel not halted
31490  * ALT_USB_HOST_HCINT5_CHHLTD_E_ACT | 0x1 | Channel Halted
31491  *
31492  * Field Access Macros:
31493  *
31494  */
31495 /*
31496  * Enumerated value for register field ALT_USB_HOST_HCINT5_CHHLTD
31497  *
31498  * Channel not halted
31499  */
31500 #define ALT_USB_HOST_HCINT5_CHHLTD_E_INACT 0x0
31501 /*
31502  * Enumerated value for register field ALT_USB_HOST_HCINT5_CHHLTD
31503  *
31504  * Channel Halted
31505  */
31506 #define ALT_USB_HOST_HCINT5_CHHLTD_E_ACT 0x1
31507 
31508 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_CHHLTD register field. */
31509 #define ALT_USB_HOST_HCINT5_CHHLTD_LSB 1
31510 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_CHHLTD register field. */
31511 #define ALT_USB_HOST_HCINT5_CHHLTD_MSB 1
31512 /* The width in bits of the ALT_USB_HOST_HCINT5_CHHLTD register field. */
31513 #define ALT_USB_HOST_HCINT5_CHHLTD_WIDTH 1
31514 /* The mask used to set the ALT_USB_HOST_HCINT5_CHHLTD register field value. */
31515 #define ALT_USB_HOST_HCINT5_CHHLTD_SET_MSK 0x00000002
31516 /* The mask used to clear the ALT_USB_HOST_HCINT5_CHHLTD register field value. */
31517 #define ALT_USB_HOST_HCINT5_CHHLTD_CLR_MSK 0xfffffffd
31518 /* The reset value of the ALT_USB_HOST_HCINT5_CHHLTD register field. */
31519 #define ALT_USB_HOST_HCINT5_CHHLTD_RESET 0x0
31520 /* Extracts the ALT_USB_HOST_HCINT5_CHHLTD field value from a register. */
31521 #define ALT_USB_HOST_HCINT5_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
31522 /* Produces a ALT_USB_HOST_HCINT5_CHHLTD register field value suitable for setting the register. */
31523 #define ALT_USB_HOST_HCINT5_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
31524 
31525 /*
31526  * Field : ahberr
31527  *
31528  * AHB Error (AHBErr)
31529  *
31530  * This is generated only in Internal DMA mode when there is an
31531  *
31532  * AHB error during AHB read/write. The application can read the
31533  *
31534  * corresponding channel's DMA address register to get the error
31535  *
31536  * address.
31537  *
31538  * Field Enumeration Values:
31539  *
31540  * Enum | Value | Description
31541  * :-----------------------------------|:------|:--------------------------------
31542  * ALT_USB_HOST_HCINT5_AHBERR_E_INACT | 0x0 | No AHB error
31543  * ALT_USB_HOST_HCINT5_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
31544  *
31545  * Field Access Macros:
31546  *
31547  */
31548 /*
31549  * Enumerated value for register field ALT_USB_HOST_HCINT5_AHBERR
31550  *
31551  * No AHB error
31552  */
31553 #define ALT_USB_HOST_HCINT5_AHBERR_E_INACT 0x0
31554 /*
31555  * Enumerated value for register field ALT_USB_HOST_HCINT5_AHBERR
31556  *
31557  * AHB error during AHB read/write
31558  */
31559 #define ALT_USB_HOST_HCINT5_AHBERR_E_ACT 0x1
31560 
31561 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_AHBERR register field. */
31562 #define ALT_USB_HOST_HCINT5_AHBERR_LSB 2
31563 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_AHBERR register field. */
31564 #define ALT_USB_HOST_HCINT5_AHBERR_MSB 2
31565 /* The width in bits of the ALT_USB_HOST_HCINT5_AHBERR register field. */
31566 #define ALT_USB_HOST_HCINT5_AHBERR_WIDTH 1
31567 /* The mask used to set the ALT_USB_HOST_HCINT5_AHBERR register field value. */
31568 #define ALT_USB_HOST_HCINT5_AHBERR_SET_MSK 0x00000004
31569 /* The mask used to clear the ALT_USB_HOST_HCINT5_AHBERR register field value. */
31570 #define ALT_USB_HOST_HCINT5_AHBERR_CLR_MSK 0xfffffffb
31571 /* The reset value of the ALT_USB_HOST_HCINT5_AHBERR register field. */
31572 #define ALT_USB_HOST_HCINT5_AHBERR_RESET 0x0
31573 /* Extracts the ALT_USB_HOST_HCINT5_AHBERR field value from a register. */
31574 #define ALT_USB_HOST_HCINT5_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
31575 /* Produces a ALT_USB_HOST_HCINT5_AHBERR register field value suitable for setting the register. */
31576 #define ALT_USB_HOST_HCINT5_AHBERR_SET(value) (((value) << 2) & 0x00000004)
31577 
31578 /*
31579  * Field : stall
31580  *
31581  * STALL Response Received Interrupt (STALL)
31582  *
31583  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
31584  *
31585  * in the core.This bit can be set only by the core and the application should
31586  * write 1 to clear
31587  *
31588  * it.
31589  *
31590  * Field Enumeration Values:
31591  *
31592  * Enum | Value | Description
31593  * :----------------------------------|:------|:-------------------
31594  * ALT_USB_HOST_HCINT5_STALL_E_INACT | 0x0 | No Stall Interrupt
31595  * ALT_USB_HOST_HCINT5_STALL_E_ACT | 0x1 | Stall Interrupt
31596  *
31597  * Field Access Macros:
31598  *
31599  */
31600 /*
31601  * Enumerated value for register field ALT_USB_HOST_HCINT5_STALL
31602  *
31603  * No Stall Interrupt
31604  */
31605 #define ALT_USB_HOST_HCINT5_STALL_E_INACT 0x0
31606 /*
31607  * Enumerated value for register field ALT_USB_HOST_HCINT5_STALL
31608  *
31609  * Stall Interrupt
31610  */
31611 #define ALT_USB_HOST_HCINT5_STALL_E_ACT 0x1
31612 
31613 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_STALL register field. */
31614 #define ALT_USB_HOST_HCINT5_STALL_LSB 3
31615 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_STALL register field. */
31616 #define ALT_USB_HOST_HCINT5_STALL_MSB 3
31617 /* The width in bits of the ALT_USB_HOST_HCINT5_STALL register field. */
31618 #define ALT_USB_HOST_HCINT5_STALL_WIDTH 1
31619 /* The mask used to set the ALT_USB_HOST_HCINT5_STALL register field value. */
31620 #define ALT_USB_HOST_HCINT5_STALL_SET_MSK 0x00000008
31621 /* The mask used to clear the ALT_USB_HOST_HCINT5_STALL register field value. */
31622 #define ALT_USB_HOST_HCINT5_STALL_CLR_MSK 0xfffffff7
31623 /* The reset value of the ALT_USB_HOST_HCINT5_STALL register field. */
31624 #define ALT_USB_HOST_HCINT5_STALL_RESET 0x0
31625 /* Extracts the ALT_USB_HOST_HCINT5_STALL field value from a register. */
31626 #define ALT_USB_HOST_HCINT5_STALL_GET(value) (((value) & 0x00000008) >> 3)
31627 /* Produces a ALT_USB_HOST_HCINT5_STALL register field value suitable for setting the register. */
31628 #define ALT_USB_HOST_HCINT5_STALL_SET(value) (((value) << 3) & 0x00000008)
31629 
31630 /*
31631  * Field : nak
31632  *
31633  * NAK Response Received Interrupt (NAK)
31634  *
31635  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
31636  *
31637  * in the core.This bit can be set only by the core and the application should
31638  * write 1 to clear
31639  *
31640  * it.
31641  *
31642  * Field Enumeration Values:
31643  *
31644  * Enum | Value | Description
31645  * :--------------------------------|:------|:-----------------------------------
31646  * ALT_USB_HOST_HCINT5_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
31647  * ALT_USB_HOST_HCINT5_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
31648  *
31649  * Field Access Macros:
31650  *
31651  */
31652 /*
31653  * Enumerated value for register field ALT_USB_HOST_HCINT5_NAK
31654  *
31655  * No NAK Response Received Interrupt
31656  */
31657 #define ALT_USB_HOST_HCINT5_NAK_E_INACT 0x0
31658 /*
31659  * Enumerated value for register field ALT_USB_HOST_HCINT5_NAK
31660  *
31661  * NAK Response Received Interrupt
31662  */
31663 #define ALT_USB_HOST_HCINT5_NAK_E_ACT 0x1
31664 
31665 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_NAK register field. */
31666 #define ALT_USB_HOST_HCINT5_NAK_LSB 4
31667 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_NAK register field. */
31668 #define ALT_USB_HOST_HCINT5_NAK_MSB 4
31669 /* The width in bits of the ALT_USB_HOST_HCINT5_NAK register field. */
31670 #define ALT_USB_HOST_HCINT5_NAK_WIDTH 1
31671 /* The mask used to set the ALT_USB_HOST_HCINT5_NAK register field value. */
31672 #define ALT_USB_HOST_HCINT5_NAK_SET_MSK 0x00000010
31673 /* The mask used to clear the ALT_USB_HOST_HCINT5_NAK register field value. */
31674 #define ALT_USB_HOST_HCINT5_NAK_CLR_MSK 0xffffffef
31675 /* The reset value of the ALT_USB_HOST_HCINT5_NAK register field. */
31676 #define ALT_USB_HOST_HCINT5_NAK_RESET 0x0
31677 /* Extracts the ALT_USB_HOST_HCINT5_NAK field value from a register. */
31678 #define ALT_USB_HOST_HCINT5_NAK_GET(value) (((value) & 0x00000010) >> 4)
31679 /* Produces a ALT_USB_HOST_HCINT5_NAK register field value suitable for setting the register. */
31680 #define ALT_USB_HOST_HCINT5_NAK_SET(value) (((value) << 4) & 0x00000010)
31681 
31682 /*
31683  * Field : ack
31684  *
31685  * ACK Response Received/Transmitted Interrupt (ACK)
31686  *
31687  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
31688  *
31689  * in the core.This bit can be set only by the core and the application should
31690  * write 1 to clear
31691  *
31692  * it.
31693  *
31694  * Field Enumeration Values:
31695  *
31696  * Enum | Value | Description
31697  * :--------------------------------|:------|:-----------------------------------------------
31698  * ALT_USB_HOST_HCINT5_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
31699  * ALT_USB_HOST_HCINT5_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
31700  *
31701  * Field Access Macros:
31702  *
31703  */
31704 /*
31705  * Enumerated value for register field ALT_USB_HOST_HCINT5_ACK
31706  *
31707  * No ACK Response Received Transmitted Interrupt
31708  */
31709 #define ALT_USB_HOST_HCINT5_ACK_E_INACT 0x0
31710 /*
31711  * Enumerated value for register field ALT_USB_HOST_HCINT5_ACK
31712  *
31713  * ACK Response Received Transmitted Interrup
31714  */
31715 #define ALT_USB_HOST_HCINT5_ACK_E_ACT 0x1
31716 
31717 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_ACK register field. */
31718 #define ALT_USB_HOST_HCINT5_ACK_LSB 5
31719 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_ACK register field. */
31720 #define ALT_USB_HOST_HCINT5_ACK_MSB 5
31721 /* The width in bits of the ALT_USB_HOST_HCINT5_ACK register field. */
31722 #define ALT_USB_HOST_HCINT5_ACK_WIDTH 1
31723 /* The mask used to set the ALT_USB_HOST_HCINT5_ACK register field value. */
31724 #define ALT_USB_HOST_HCINT5_ACK_SET_MSK 0x00000020
31725 /* The mask used to clear the ALT_USB_HOST_HCINT5_ACK register field value. */
31726 #define ALT_USB_HOST_HCINT5_ACK_CLR_MSK 0xffffffdf
31727 /* The reset value of the ALT_USB_HOST_HCINT5_ACK register field. */
31728 #define ALT_USB_HOST_HCINT5_ACK_RESET 0x0
31729 /* Extracts the ALT_USB_HOST_HCINT5_ACK field value from a register. */
31730 #define ALT_USB_HOST_HCINT5_ACK_GET(value) (((value) & 0x00000020) >> 5)
31731 /* Produces a ALT_USB_HOST_HCINT5_ACK register field value suitable for setting the register. */
31732 #define ALT_USB_HOST_HCINT5_ACK_SET(value) (((value) << 5) & 0x00000020)
31733 
31734 /*
31735  * Field : nyet
31736  *
31737  * NYET Response Received Interrupt (NYET)
31738  *
31739  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
31740  *
31741  * in the core.This bit can be set only by the core and the application should
31742  * write 1 to clear
31743  *
31744  * it.
31745  *
31746  * Field Enumeration Values:
31747  *
31748  * Enum | Value | Description
31749  * :---------------------------------|:------|:------------------------------------
31750  * ALT_USB_HOST_HCINT5_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
31751  * ALT_USB_HOST_HCINT5_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
31752  *
31753  * Field Access Macros:
31754  *
31755  */
31756 /*
31757  * Enumerated value for register field ALT_USB_HOST_HCINT5_NYET
31758  *
31759  * No NYET Response Received Interrupt
31760  */
31761 #define ALT_USB_HOST_HCINT5_NYET_E_INACT 0x0
31762 /*
31763  * Enumerated value for register field ALT_USB_HOST_HCINT5_NYET
31764  *
31765  * NYET Response Received Interrupt
31766  */
31767 #define ALT_USB_HOST_HCINT5_NYET_E_ACT 0x1
31768 
31769 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_NYET register field. */
31770 #define ALT_USB_HOST_HCINT5_NYET_LSB 6
31771 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_NYET register field. */
31772 #define ALT_USB_HOST_HCINT5_NYET_MSB 6
31773 /* The width in bits of the ALT_USB_HOST_HCINT5_NYET register field. */
31774 #define ALT_USB_HOST_HCINT5_NYET_WIDTH 1
31775 /* The mask used to set the ALT_USB_HOST_HCINT5_NYET register field value. */
31776 #define ALT_USB_HOST_HCINT5_NYET_SET_MSK 0x00000040
31777 /* The mask used to clear the ALT_USB_HOST_HCINT5_NYET register field value. */
31778 #define ALT_USB_HOST_HCINT5_NYET_CLR_MSK 0xffffffbf
31779 /* The reset value of the ALT_USB_HOST_HCINT5_NYET register field. */
31780 #define ALT_USB_HOST_HCINT5_NYET_RESET 0x0
31781 /* Extracts the ALT_USB_HOST_HCINT5_NYET field value from a register. */
31782 #define ALT_USB_HOST_HCINT5_NYET_GET(value) (((value) & 0x00000040) >> 6)
31783 /* Produces a ALT_USB_HOST_HCINT5_NYET register field value suitable for setting the register. */
31784 #define ALT_USB_HOST_HCINT5_NYET_SET(value) (((value) << 6) & 0x00000040)
31785 
31786 /*
31787  * Field : xacterr
31788  *
31789  * Transaction Error (XactErr)
31790  *
31791  * Indicates one of the following errors occurred on the USB.
31792  *
31793  * CRC check failure
31794  *
31795  * Timeout
31796  *
31797  * Bit stuff error
31798  *
31799  * False EOP
31800  *
31801  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
31802  *
31803  * in the core.This bit can be set only by the core and the application should
31804  * write 1 to clear
31805  *
31806  * it.
31807  *
31808  * Field Enumeration Values:
31809  *
31810  * Enum | Value | Description
31811  * :------------------------------------|:------|:---------------------
31812  * ALT_USB_HOST_HCINT5_XACTERR_E_INACT | 0x0 | No Transaction Error
31813  * ALT_USB_HOST_HCINT5_XACTERR_E_ACT | 0x1 | Transaction Error
31814  *
31815  * Field Access Macros:
31816  *
31817  */
31818 /*
31819  * Enumerated value for register field ALT_USB_HOST_HCINT5_XACTERR
31820  *
31821  * No Transaction Error
31822  */
31823 #define ALT_USB_HOST_HCINT5_XACTERR_E_INACT 0x0
31824 /*
31825  * Enumerated value for register field ALT_USB_HOST_HCINT5_XACTERR
31826  *
31827  * Transaction Error
31828  */
31829 #define ALT_USB_HOST_HCINT5_XACTERR_E_ACT 0x1
31830 
31831 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_XACTERR register field. */
31832 #define ALT_USB_HOST_HCINT5_XACTERR_LSB 7
31833 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_XACTERR register field. */
31834 #define ALT_USB_HOST_HCINT5_XACTERR_MSB 7
31835 /* The width in bits of the ALT_USB_HOST_HCINT5_XACTERR register field. */
31836 #define ALT_USB_HOST_HCINT5_XACTERR_WIDTH 1
31837 /* The mask used to set the ALT_USB_HOST_HCINT5_XACTERR register field value. */
31838 #define ALT_USB_HOST_HCINT5_XACTERR_SET_MSK 0x00000080
31839 /* The mask used to clear the ALT_USB_HOST_HCINT5_XACTERR register field value. */
31840 #define ALT_USB_HOST_HCINT5_XACTERR_CLR_MSK 0xffffff7f
31841 /* The reset value of the ALT_USB_HOST_HCINT5_XACTERR register field. */
31842 #define ALT_USB_HOST_HCINT5_XACTERR_RESET 0x0
31843 /* Extracts the ALT_USB_HOST_HCINT5_XACTERR field value from a register. */
31844 #define ALT_USB_HOST_HCINT5_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
31845 /* Produces a ALT_USB_HOST_HCINT5_XACTERR register field value suitable for setting the register. */
31846 #define ALT_USB_HOST_HCINT5_XACTERR_SET(value) (((value) << 7) & 0x00000080)
31847 
31848 /*
31849  * Field : bblerr
31850  *
31851  * Babble Error (BblErr)
31852  *
31853  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
31854  *
31855  * in the core..This bit can be set only by the core and the application should
31856  * write 1 to clear
31857  *
31858  * it.
31859  *
31860  * Field Enumeration Values:
31861  *
31862  * Enum | Value | Description
31863  * :-----------------------------------|:------|:----------------
31864  * ALT_USB_HOST_HCINT5_BBLERR_E_INACT | 0x0 | No Babble Error
31865  * ALT_USB_HOST_HCINT5_BBLERR_E_ACT | 0x1 | Babble Error
31866  *
31867  * Field Access Macros:
31868  *
31869  */
31870 /*
31871  * Enumerated value for register field ALT_USB_HOST_HCINT5_BBLERR
31872  *
31873  * No Babble Error
31874  */
31875 #define ALT_USB_HOST_HCINT5_BBLERR_E_INACT 0x0
31876 /*
31877  * Enumerated value for register field ALT_USB_HOST_HCINT5_BBLERR
31878  *
31879  * Babble Error
31880  */
31881 #define ALT_USB_HOST_HCINT5_BBLERR_E_ACT 0x1
31882 
31883 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_BBLERR register field. */
31884 #define ALT_USB_HOST_HCINT5_BBLERR_LSB 8
31885 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_BBLERR register field. */
31886 #define ALT_USB_HOST_HCINT5_BBLERR_MSB 8
31887 /* The width in bits of the ALT_USB_HOST_HCINT5_BBLERR register field. */
31888 #define ALT_USB_HOST_HCINT5_BBLERR_WIDTH 1
31889 /* The mask used to set the ALT_USB_HOST_HCINT5_BBLERR register field value. */
31890 #define ALT_USB_HOST_HCINT5_BBLERR_SET_MSK 0x00000100
31891 /* The mask used to clear the ALT_USB_HOST_HCINT5_BBLERR register field value. */
31892 #define ALT_USB_HOST_HCINT5_BBLERR_CLR_MSK 0xfffffeff
31893 /* The reset value of the ALT_USB_HOST_HCINT5_BBLERR register field. */
31894 #define ALT_USB_HOST_HCINT5_BBLERR_RESET 0x0
31895 /* Extracts the ALT_USB_HOST_HCINT5_BBLERR field value from a register. */
31896 #define ALT_USB_HOST_HCINT5_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
31897 /* Produces a ALT_USB_HOST_HCINT5_BBLERR register field value suitable for setting the register. */
31898 #define ALT_USB_HOST_HCINT5_BBLERR_SET(value) (((value) << 8) & 0x00000100)
31899 
31900 /*
31901  * Field : frmovrun
31902  *
31903  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
31904  * bit is masked
31905  *
31906  * in the core.This bit can be set only by the core and the application should
31907  * write 1 to clear
31908  *
31909  * it.
31910  *
31911  * Field Enumeration Values:
31912  *
31913  * Enum | Value | Description
31914  * :-------------------------------------|:------|:-----------------
31915  * ALT_USB_HOST_HCINT5_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
31916  * ALT_USB_HOST_HCINT5_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
31917  *
31918  * Field Access Macros:
31919  *
31920  */
31921 /*
31922  * Enumerated value for register field ALT_USB_HOST_HCINT5_FRMOVRUN
31923  *
31924  * No Frame Overrun
31925  */
31926 #define ALT_USB_HOST_HCINT5_FRMOVRUN_E_INACT 0x0
31927 /*
31928  * Enumerated value for register field ALT_USB_HOST_HCINT5_FRMOVRUN
31929  *
31930  * Frame Overrun
31931  */
31932 #define ALT_USB_HOST_HCINT5_FRMOVRUN_E_ACT 0x1
31933 
31934 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */
31935 #define ALT_USB_HOST_HCINT5_FRMOVRUN_LSB 9
31936 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */
31937 #define ALT_USB_HOST_HCINT5_FRMOVRUN_MSB 9
31938 /* The width in bits of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */
31939 #define ALT_USB_HOST_HCINT5_FRMOVRUN_WIDTH 1
31940 /* The mask used to set the ALT_USB_HOST_HCINT5_FRMOVRUN register field value. */
31941 #define ALT_USB_HOST_HCINT5_FRMOVRUN_SET_MSK 0x00000200
31942 /* The mask used to clear the ALT_USB_HOST_HCINT5_FRMOVRUN register field value. */
31943 #define ALT_USB_HOST_HCINT5_FRMOVRUN_CLR_MSK 0xfffffdff
31944 /* The reset value of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */
31945 #define ALT_USB_HOST_HCINT5_FRMOVRUN_RESET 0x0
31946 /* Extracts the ALT_USB_HOST_HCINT5_FRMOVRUN field value from a register. */
31947 #define ALT_USB_HOST_HCINT5_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
31948 /* Produces a ALT_USB_HOST_HCINT5_FRMOVRUN register field value suitable for setting the register. */
31949 #define ALT_USB_HOST_HCINT5_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
31950 
31951 /*
31952  * Field : datatglerr
31953  *
31954  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
31955  * application should write 1 to clear
31956  *
31957  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
31958  *
31959  * in the core.
31960  *
31961  * Field Enumeration Values:
31962  *
31963  * Enum | Value | Description
31964  * :---------------------------------------|:------|:---------------------
31965  * ALT_USB_HOST_HCINT5_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
31966  * ALT_USB_HOST_HCINT5_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
31967  *
31968  * Field Access Macros:
31969  *
31970  */
31971 /*
31972  * Enumerated value for register field ALT_USB_HOST_HCINT5_DATATGLERR
31973  *
31974  * No Data Toggle Error
31975  */
31976 #define ALT_USB_HOST_HCINT5_DATATGLERR_E_INACT 0x0
31977 /*
31978  * Enumerated value for register field ALT_USB_HOST_HCINT5_DATATGLERR
31979  *
31980  * Data Toggle Error
31981  */
31982 #define ALT_USB_HOST_HCINT5_DATATGLERR_E_ACT 0x1
31983 
31984 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */
31985 #define ALT_USB_HOST_HCINT5_DATATGLERR_LSB 10
31986 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */
31987 #define ALT_USB_HOST_HCINT5_DATATGLERR_MSB 10
31988 /* The width in bits of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */
31989 #define ALT_USB_HOST_HCINT5_DATATGLERR_WIDTH 1
31990 /* The mask used to set the ALT_USB_HOST_HCINT5_DATATGLERR register field value. */
31991 #define ALT_USB_HOST_HCINT5_DATATGLERR_SET_MSK 0x00000400
31992 /* The mask used to clear the ALT_USB_HOST_HCINT5_DATATGLERR register field value. */
31993 #define ALT_USB_HOST_HCINT5_DATATGLERR_CLR_MSK 0xfffffbff
31994 /* The reset value of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */
31995 #define ALT_USB_HOST_HCINT5_DATATGLERR_RESET 0x0
31996 /* Extracts the ALT_USB_HOST_HCINT5_DATATGLERR field value from a register. */
31997 #define ALT_USB_HOST_HCINT5_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
31998 /* Produces a ALT_USB_HOST_HCINT5_DATATGLERR register field value suitable for setting the register. */
31999 #define ALT_USB_HOST_HCINT5_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
32000 
32001 /*
32002  * Field : bnaintr
32003  *
32004  * BNA (Buffer Not Available) Interrupt (BNAIntr)
32005  *
32006  * This bit is valid only when Scatter/Gather DMA mode is enabled.
32007  *
32008  * The core generates this interrupt when the descriptor accessed
32009  *
32010  * is not ready for the Core to process. BNA will not be generated
32011  *
32012  * for Isochronous channels.
32013  *
32014  * For non Scatter/Gather DMA mode, this bit is reserved.
32015  *
32016  * Field Enumeration Values:
32017  *
32018  * Enum | Value | Description
32019  * :------------------------------------|:------|:-----------------
32020  * ALT_USB_HOST_HCINT5_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
32021  * ALT_USB_HOST_HCINT5_BNAINTR_E_ACT | 0x1 | BNA Interrupt
32022  *
32023  * Field Access Macros:
32024  *
32025  */
32026 /*
32027  * Enumerated value for register field ALT_USB_HOST_HCINT5_BNAINTR
32028  *
32029  * No BNA Interrupt
32030  */
32031 #define ALT_USB_HOST_HCINT5_BNAINTR_E_INACT 0x0
32032 /*
32033  * Enumerated value for register field ALT_USB_HOST_HCINT5_BNAINTR
32034  *
32035  * BNA Interrupt
32036  */
32037 #define ALT_USB_HOST_HCINT5_BNAINTR_E_ACT 0x1
32038 
32039 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_BNAINTR register field. */
32040 #define ALT_USB_HOST_HCINT5_BNAINTR_LSB 11
32041 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_BNAINTR register field. */
32042 #define ALT_USB_HOST_HCINT5_BNAINTR_MSB 11
32043 /* The width in bits of the ALT_USB_HOST_HCINT5_BNAINTR register field. */
32044 #define ALT_USB_HOST_HCINT5_BNAINTR_WIDTH 1
32045 /* The mask used to set the ALT_USB_HOST_HCINT5_BNAINTR register field value. */
32046 #define ALT_USB_HOST_HCINT5_BNAINTR_SET_MSK 0x00000800
32047 /* The mask used to clear the ALT_USB_HOST_HCINT5_BNAINTR register field value. */
32048 #define ALT_USB_HOST_HCINT5_BNAINTR_CLR_MSK 0xfffff7ff
32049 /* The reset value of the ALT_USB_HOST_HCINT5_BNAINTR register field. */
32050 #define ALT_USB_HOST_HCINT5_BNAINTR_RESET 0x0
32051 /* Extracts the ALT_USB_HOST_HCINT5_BNAINTR field value from a register. */
32052 #define ALT_USB_HOST_HCINT5_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
32053 /* Produces a ALT_USB_HOST_HCINT5_BNAINTR register field value suitable for setting the register. */
32054 #define ALT_USB_HOST_HCINT5_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
32055 
32056 /*
32057  * Field : xcs_xact_err
32058  *
32059  * Excessive Transaction Error (XCS_XACT_ERR)
32060  *
32061  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
32062  * this bit
32063  *
32064  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
32065  *
32066  * not be generated for Isochronous channels.
32067  *
32068  * For non Scatter/Gather DMA mode, this bit is reserved.
32069  *
32070  * Field Enumeration Values:
32071  *
32072  * Enum | Value | Description
32073  * :-------------------------------------------|:------|:-------------------------------
32074  * ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
32075  * ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
32076  *
32077  * Field Access Macros:
32078  *
32079  */
32080 /*
32081  * Enumerated value for register field ALT_USB_HOST_HCINT5_XCS_XACT_ERR
32082  *
32083  * No Excessive Transaction Error
32084  */
32085 #define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_INACT 0x0
32086 /*
32087  * Enumerated value for register field ALT_USB_HOST_HCINT5_XCS_XACT_ERR
32088  *
32089  * Excessive Transaction Error
32090  */
32091 #define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_ACVTIVE 0x1
32092 
32093 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */
32094 #define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_LSB 12
32095 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */
32096 #define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_MSB 12
32097 /* The width in bits of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */
32098 #define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_WIDTH 1
32099 /* The mask used to set the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field value. */
32100 #define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_SET_MSK 0x00001000
32101 /* The mask used to clear the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field value. */
32102 #define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_CLR_MSK 0xffffefff
32103 /* The reset value of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */
32104 #define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_RESET 0x0
32105 /* Extracts the ALT_USB_HOST_HCINT5_XCS_XACT_ERR field value from a register. */
32106 #define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
32107 /* Produces a ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field value suitable for setting the register. */
32108 #define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
32109 
32110 /*
32111  * Field : desc_lst_rollintr
32112  *
32113  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
32114  *
32115  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
32116  * this bit
32117  *
32118  * when the corresponding channel's descriptor list rolls over.
32119  *
32120  * For non Scatter/Gather DMA mode, this bit is reserved.
32121  *
32122  * Field Enumeration Values:
32123  *
32124  * Enum | Value | Description
32125  * :----------------------------------------------|:------|:---------------------------------
32126  * ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
32127  * ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
32128  *
32129  * Field Access Macros:
32130  *
32131  */
32132 /*
32133  * Enumerated value for register field ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR
32134  *
32135  * No Descriptor rollover interrupt
32136  */
32137 #define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_INACT 0x0
32138 /*
32139  * Enumerated value for register field ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR
32140  *
32141  * Descriptor rollover interrupt
32142  */
32143 #define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_ACT 0x1
32144 
32145 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */
32146 #define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_LSB 13
32147 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */
32148 #define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_MSB 13
32149 /* The width in bits of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */
32150 #define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_WIDTH 1
32151 /* The mask used to set the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field value. */
32152 #define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_SET_MSK 0x00002000
32153 /* The mask used to clear the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field value. */
32154 #define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
32155 /* The reset value of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */
32156 #define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_RESET 0x0
32157 /* Extracts the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR field value from a register. */
32158 #define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
32159 /* Produces a ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field value suitable for setting the register. */
32160 #define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
32161 
32162 #ifndef __ASSEMBLY__
32163 /*
32164  * WARNING: The C register and register group struct declarations are provided for
32165  * convenience and illustrative purposes. They should, however, be used with
32166  * caution as the C language standard provides no guarantees about the alignment or
32167  * atomicity of device memory accesses. The recommended practice for writing
32168  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32169  * alt_write_word() functions.
32170  *
32171  * The struct declaration for register ALT_USB_HOST_HCINT5.
32172  */
32173 struct ALT_USB_HOST_HCINT5_s
32174 {
32175  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT5_XFERCOMPL */
32176  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT5_CHHLTD */
32177  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT5_AHBERR */
32178  uint32_t stall : 1; /* ALT_USB_HOST_HCINT5_STALL */
32179  uint32_t nak : 1; /* ALT_USB_HOST_HCINT5_NAK */
32180  uint32_t ack : 1; /* ALT_USB_HOST_HCINT5_ACK */
32181  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT5_NYET */
32182  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT5_XACTERR */
32183  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT5_BBLERR */
32184  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT5_FRMOVRUN */
32185  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT5_DATATGLERR */
32186  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT5_BNAINTR */
32187  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT5_XCS_XACT_ERR */
32188  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR */
32189  uint32_t : 18; /* *UNDEFINED* */
32190 };
32191 
32192 /* The typedef declaration for register ALT_USB_HOST_HCINT5. */
32193 typedef volatile struct ALT_USB_HOST_HCINT5_s ALT_USB_HOST_HCINT5_t;
32194 #endif /* __ASSEMBLY__ */
32195 
32196 /* The reset value of the ALT_USB_HOST_HCINT5 register. */
32197 #define ALT_USB_HOST_HCINT5_RESET 0x00000000
32198 /* The byte offset of the ALT_USB_HOST_HCINT5 register from the beginning of the component. */
32199 #define ALT_USB_HOST_HCINT5_OFST 0x1a8
32200 /* The address of the ALT_USB_HOST_HCINT5 register. */
32201 #define ALT_USB_HOST_HCINT5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT5_OFST))
32202 
32203 /*
32204  * Register : hcintmsk5
32205  *
32206  * Host Channel 5 Interrupt Mask Register
32207  *
32208  * Register Layout
32209  *
32210  * Bits | Access | Reset | Description
32211  * :--------|:-------|:------|:-------------------------------------------
32212  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK
32213  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_CHHLTDMSK
32214  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_AHBERRMSK
32215  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_STALLMSK
32216  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_NAKMSK
32217  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_ACKMSK
32218  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_NYETMSK
32219  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_XACTERRMSK
32220  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_BBLERRMSK
32221  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK
32222  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK
32223  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_BNAINTRMSK
32224  * [12] | ??? | 0x0 | *UNDEFINED*
32225  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK
32226  * [31:14] | ??? | 0x0 | *UNDEFINED*
32227  *
32228  */
32229 /*
32230  * Field : xfercomplmsk
32231  *
32232  * Transfer Completed Mask (XferComplMsk)
32233  *
32234  * Field Enumeration Values:
32235  *
32236  * Enum | Value | Description
32237  * :--------------------------------------------|:------|:------------
32238  * ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_MSK | 0x0 | Mask
32239  * ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
32240  *
32241  * Field Access Macros:
32242  *
32243  */
32244 /*
32245  * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK
32246  *
32247  * Mask
32248  */
32249 #define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_MSK 0x0
32250 /*
32251  * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK
32252  *
32253  * No mask
32254  */
32255 #define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_NOMSK 0x1
32256 
32257 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */
32258 #define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_LSB 0
32259 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */
32260 #define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_MSB 0
32261 /* The width in bits of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */
32262 #define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_WIDTH 1
32263 /* The mask used to set the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field value. */
32264 #define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_SET_MSK 0x00000001
32265 /* The mask used to clear the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field value. */
32266 #define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_CLR_MSK 0xfffffffe
32267 /* The reset value of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */
32268 #define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_RESET 0x0
32269 /* Extracts the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK field value from a register. */
32270 #define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
32271 /* Produces a ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field value suitable for setting the register. */
32272 #define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
32273 
32274 /*
32275  * Field : chhltdmsk
32276  *
32277  * Channel Halted Mask (ChHltdMsk)
32278  *
32279  * Field Enumeration Values:
32280  *
32281  * Enum | Value | Description
32282  * :-----------------------------------------|:------|:------------
32283  * ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_MSK | 0x0 | Mask
32284  * ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_NOMSK | 0x1 | No mask
32285  *
32286  * Field Access Macros:
32287  *
32288  */
32289 /*
32290  * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_CHHLTDMSK
32291  *
32292  * Mask
32293  */
32294 #define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_MSK 0x0
32295 /*
32296  * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_CHHLTDMSK
32297  *
32298  * No mask
32299  */
32300 #define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_NOMSK 0x1
32301 
32302 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */
32303 #define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_LSB 1
32304 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */
32305 #define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_MSB 1
32306 /* The width in bits of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */
32307 #define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_WIDTH 1
32308 /* The mask used to set the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field value. */
32309 #define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_SET_MSK 0x00000002
32310 /* The mask used to clear the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field value. */
32311 #define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_CLR_MSK 0xfffffffd
32312 /* The reset value of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */
32313 #define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_RESET 0x0
32314 /* Extracts the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK field value from a register. */
32315 #define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
32316 /* Produces a ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field value suitable for setting the register. */
32317 #define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
32318 
32319 /*
32320  * Field : ahberrmsk
32321  *
32322  * AHB Error Mask (AHBErrMsk)
32323  *
32324  * In scatter/gather DMA mode for host,
32325  *
32326  * interrupts will not be generated due to the corresponding bits set in
32327  *
32328  * HCINTn.
32329  *
32330  * Field Enumeration Values:
32331  *
32332  * Enum | Value | Description
32333  * :-----------------------------------------|:------|:------------
32334  * ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_MSK | 0x0 | Mask
32335  * ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_NOMSK | 0x1 | No mask
32336  *
32337  * Field Access Macros:
32338  *
32339  */
32340 /*
32341  * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_AHBERRMSK
32342  *
32343  * Mask
32344  */
32345 #define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_MSK 0x0
32346 /*
32347  * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_AHBERRMSK
32348  *
32349  * No mask
32350  */
32351 #define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_NOMSK 0x1
32352 
32353 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */
32354 #define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_LSB 2
32355 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */
32356 #define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_MSB 2
32357 /* The width in bits of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */
32358 #define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_WIDTH 1
32359 /* The mask used to set the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field value. */
32360 #define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_SET_MSK 0x00000004
32361 /* The mask used to clear the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field value. */
32362 #define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_CLR_MSK 0xfffffffb
32363 /* The reset value of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */
32364 #define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_RESET 0x0
32365 /* Extracts the ALT_USB_HOST_HCINTMSK5_AHBERRMSK field value from a register. */
32366 #define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
32367 /* Produces a ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field value suitable for setting the register. */
32368 #define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
32369 
32370 /*
32371  * Field : stallmsk
32372  *
32373  * STALL Response Received Interrupt Mask (StallMsk)
32374  *
32375  * In scatter/gather DMA mode for host,
32376  *
32377  * interrupts will not be generated due to the corresponding bits set in
32378  *
32379  * HCINTn.
32380  *
32381  * Field Access Macros:
32382  *
32383  */
32384 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_STALLMSK register field. */
32385 #define ALT_USB_HOST_HCINTMSK5_STALLMSK_LSB 3
32386 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_STALLMSK register field. */
32387 #define ALT_USB_HOST_HCINTMSK5_STALLMSK_MSB 3
32388 /* The width in bits of the ALT_USB_HOST_HCINTMSK5_STALLMSK register field. */
32389 #define ALT_USB_HOST_HCINTMSK5_STALLMSK_WIDTH 1
32390 /* The mask used to set the ALT_USB_HOST_HCINTMSK5_STALLMSK register field value. */
32391 #define ALT_USB_HOST_HCINTMSK5_STALLMSK_SET_MSK 0x00000008
32392 /* The mask used to clear the ALT_USB_HOST_HCINTMSK5_STALLMSK register field value. */
32393 #define ALT_USB_HOST_HCINTMSK5_STALLMSK_CLR_MSK 0xfffffff7
32394 /* The reset value of the ALT_USB_HOST_HCINTMSK5_STALLMSK register field. */
32395 #define ALT_USB_HOST_HCINTMSK5_STALLMSK_RESET 0x0
32396 /* Extracts the ALT_USB_HOST_HCINTMSK5_STALLMSK field value from a register. */
32397 #define ALT_USB_HOST_HCINTMSK5_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
32398 /* Produces a ALT_USB_HOST_HCINTMSK5_STALLMSK register field value suitable for setting the register. */
32399 #define ALT_USB_HOST_HCINTMSK5_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
32400 
32401 /*
32402  * Field : nakmsk
32403  *
32404  * NAK Response Received Interrupt Mask (NakMsk)
32405  *
32406  * In scatter/gather DMA mode for host,
32407  *
32408  * interrupts will not be generated due to the corresponding bits set in
32409  *
32410  * HCINTn.
32411  *
32412  * Field Access Macros:
32413  *
32414  */
32415 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_NAKMSK register field. */
32416 #define ALT_USB_HOST_HCINTMSK5_NAKMSK_LSB 4
32417 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_NAKMSK register field. */
32418 #define ALT_USB_HOST_HCINTMSK5_NAKMSK_MSB 4
32419 /* The width in bits of the ALT_USB_HOST_HCINTMSK5_NAKMSK register field. */
32420 #define ALT_USB_HOST_HCINTMSK5_NAKMSK_WIDTH 1
32421 /* The mask used to set the ALT_USB_HOST_HCINTMSK5_NAKMSK register field value. */
32422 #define ALT_USB_HOST_HCINTMSK5_NAKMSK_SET_MSK 0x00000010
32423 /* The mask used to clear the ALT_USB_HOST_HCINTMSK5_NAKMSK register field value. */
32424 #define ALT_USB_HOST_HCINTMSK5_NAKMSK_CLR_MSK 0xffffffef
32425 /* The reset value of the ALT_USB_HOST_HCINTMSK5_NAKMSK register field. */
32426 #define ALT_USB_HOST_HCINTMSK5_NAKMSK_RESET 0x0
32427 /* Extracts the ALT_USB_HOST_HCINTMSK5_NAKMSK field value from a register. */
32428 #define ALT_USB_HOST_HCINTMSK5_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
32429 /* Produces a ALT_USB_HOST_HCINTMSK5_NAKMSK register field value suitable for setting the register. */
32430 #define ALT_USB_HOST_HCINTMSK5_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
32431 
32432 /*
32433  * Field : ackmsk
32434  *
32435  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
32436  *
32437  * In scatter/gather DMA mode for host,
32438  *
32439  * interrupts will not be generated due to the corresponding bits set in
32440  *
32441  * HCINTn.
32442  *
32443  * Field Access Macros:
32444  *
32445  */
32446 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_ACKMSK register field. */
32447 #define ALT_USB_HOST_HCINTMSK5_ACKMSK_LSB 5
32448 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_ACKMSK register field. */
32449 #define ALT_USB_HOST_HCINTMSK5_ACKMSK_MSB 5
32450 /* The width in bits of the ALT_USB_HOST_HCINTMSK5_ACKMSK register field. */
32451 #define ALT_USB_HOST_HCINTMSK5_ACKMSK_WIDTH 1
32452 /* The mask used to set the ALT_USB_HOST_HCINTMSK5_ACKMSK register field value. */
32453 #define ALT_USB_HOST_HCINTMSK5_ACKMSK_SET_MSK 0x00000020
32454 /* The mask used to clear the ALT_USB_HOST_HCINTMSK5_ACKMSK register field value. */
32455 #define ALT_USB_HOST_HCINTMSK5_ACKMSK_CLR_MSK 0xffffffdf
32456 /* The reset value of the ALT_USB_HOST_HCINTMSK5_ACKMSK register field. */
32457 #define ALT_USB_HOST_HCINTMSK5_ACKMSK_RESET 0x0
32458 /* Extracts the ALT_USB_HOST_HCINTMSK5_ACKMSK field value from a register. */
32459 #define ALT_USB_HOST_HCINTMSK5_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
32460 /* Produces a ALT_USB_HOST_HCINTMSK5_ACKMSK register field value suitable for setting the register. */
32461 #define ALT_USB_HOST_HCINTMSK5_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
32462 
32463 /*
32464  * Field : nyetmsk
32465  *
32466  * NYET Response Received Interrupt Mask (NyetMsk)
32467  *
32468  * In scatter/gather DMA mode for host,
32469  *
32470  * interrupts will not be generated due to the corresponding bits set in
32471  *
32472  * HCINTn.
32473  *
32474  * Field Access Macros:
32475  *
32476  */
32477 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_NYETMSK register field. */
32478 #define ALT_USB_HOST_HCINTMSK5_NYETMSK_LSB 6
32479 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_NYETMSK register field. */
32480 #define ALT_USB_HOST_HCINTMSK5_NYETMSK_MSB 6
32481 /* The width in bits of the ALT_USB_HOST_HCINTMSK5_NYETMSK register field. */
32482 #define ALT_USB_HOST_HCINTMSK5_NYETMSK_WIDTH 1
32483 /* The mask used to set the ALT_USB_HOST_HCINTMSK5_NYETMSK register field value. */
32484 #define ALT_USB_HOST_HCINTMSK5_NYETMSK_SET_MSK 0x00000040
32485 /* The mask used to clear the ALT_USB_HOST_HCINTMSK5_NYETMSK register field value. */
32486 #define ALT_USB_HOST_HCINTMSK5_NYETMSK_CLR_MSK 0xffffffbf
32487 /* The reset value of the ALT_USB_HOST_HCINTMSK5_NYETMSK register field. */
32488 #define ALT_USB_HOST_HCINTMSK5_NYETMSK_RESET 0x0
32489 /* Extracts the ALT_USB_HOST_HCINTMSK5_NYETMSK field value from a register. */
32490 #define ALT_USB_HOST_HCINTMSK5_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
32491 /* Produces a ALT_USB_HOST_HCINTMSK5_NYETMSK register field value suitable for setting the register. */
32492 #define ALT_USB_HOST_HCINTMSK5_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
32493 
32494 /*
32495  * Field : xacterrmsk
32496  *
32497  * Transaction Error Mask (XactErrMsk)
32498  *
32499  * In scatter/gather DMA mode for host,
32500  *
32501  * interrupts will not be generated due to the corresponding bits set in
32502  *
32503  * HCINTn.
32504  *
32505  * Field Access Macros:
32506  *
32507  */
32508 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field. */
32509 #define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_LSB 7
32510 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field. */
32511 #define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_MSB 7
32512 /* The width in bits of the ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field. */
32513 #define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_WIDTH 1
32514 /* The mask used to set the ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field value. */
32515 #define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_SET_MSK 0x00000080
32516 /* The mask used to clear the ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field value. */
32517 #define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_CLR_MSK 0xffffff7f
32518 /* The reset value of the ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field. */
32519 #define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_RESET 0x0
32520 /* Extracts the ALT_USB_HOST_HCINTMSK5_XACTERRMSK field value from a register. */
32521 #define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
32522 /* Produces a ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field value suitable for setting the register. */
32523 #define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
32524 
32525 /*
32526  * Field : bblerrmsk
32527  *
32528  * Babble Error Mask (BblErrMsk)
32529  *
32530  * In scatter/gather DMA mode for host,
32531  *
32532  * interrupts will not be generated due to the corresponding bits set in
32533  *
32534  * HCINTn.
32535  *
32536  * Field Access Macros:
32537  *
32538  */
32539 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field. */
32540 #define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_LSB 8
32541 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field. */
32542 #define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_MSB 8
32543 /* The width in bits of the ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field. */
32544 #define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_WIDTH 1
32545 /* The mask used to set the ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field value. */
32546 #define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_SET_MSK 0x00000100
32547 /* The mask used to clear the ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field value. */
32548 #define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_CLR_MSK 0xfffffeff
32549 /* The reset value of the ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field. */
32550 #define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_RESET 0x0
32551 /* Extracts the ALT_USB_HOST_HCINTMSK5_BBLERRMSK field value from a register. */
32552 #define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
32553 /* Produces a ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field value suitable for setting the register. */
32554 #define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
32555 
32556 /*
32557  * Field : frmovrunmsk
32558  *
32559  * Frame Overrun Mask (FrmOvrunMsk)
32560  *
32561  * In scatter/gather DMA mode for host,
32562  *
32563  * interrupts will not be generated due to the corresponding bits set in
32564  *
32565  * HCINTn.
32566  *
32567  * Field Access Macros:
32568  *
32569  */
32570 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field. */
32571 #define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_LSB 9
32572 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field. */
32573 #define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_MSB 9
32574 /* The width in bits of the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field. */
32575 #define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_WIDTH 1
32576 /* The mask used to set the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field value. */
32577 #define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_SET_MSK 0x00000200
32578 /* The mask used to clear the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field value. */
32579 #define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_CLR_MSK 0xfffffdff
32580 /* The reset value of the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field. */
32581 #define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_RESET 0x0
32582 /* Extracts the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK field value from a register. */
32583 #define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
32584 /* Produces a ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field value suitable for setting the register. */
32585 #define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
32586 
32587 /*
32588  * Field : datatglerrmsk
32589  *
32590  * Data Toggle Error Mask (DataTglErrMsk)
32591  *
32592  * In scatter/gather DMA mode for host,
32593  *
32594  * interrupts will not be generated due to the corresponding bits set in
32595  *
32596  * HCINTn.
32597  *
32598  * Field Access Macros:
32599  *
32600  */
32601 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field. */
32602 #define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_LSB 10
32603 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field. */
32604 #define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_MSB 10
32605 /* The width in bits of the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field. */
32606 #define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_WIDTH 1
32607 /* The mask used to set the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field value. */
32608 #define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_SET_MSK 0x00000400
32609 /* The mask used to clear the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field value. */
32610 #define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_CLR_MSK 0xfffffbff
32611 /* The reset value of the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field. */
32612 #define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_RESET 0x0
32613 /* Extracts the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK field value from a register. */
32614 #define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
32615 /* Produces a ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field value suitable for setting the register. */
32616 #define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
32617 
32618 /*
32619  * Field : bnaintrmsk
32620  *
32621  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
32622  *
32623  * This bit is valid only when Scatter/Gather DMA mode is enabled.
32624  *
32625  * Field Enumeration Values:
32626  *
32627  * Enum | Value | Description
32628  * :------------------------------------------|:------|:------------
32629  * ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_MSK | 0x0 | Mask
32630  * ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_NOMSK | 0x1 | No mask
32631  *
32632  * Field Access Macros:
32633  *
32634  */
32635 /*
32636  * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_BNAINTRMSK
32637  *
32638  * Mask
32639  */
32640 #define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_MSK 0x0
32641 /*
32642  * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_BNAINTRMSK
32643  *
32644  * No mask
32645  */
32646 #define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_NOMSK 0x1
32647 
32648 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */
32649 #define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_LSB 11
32650 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */
32651 #define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_MSB 11
32652 /* The width in bits of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */
32653 #define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_WIDTH 1
32654 /* The mask used to set the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field value. */
32655 #define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_SET_MSK 0x00000800
32656 /* The mask used to clear the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field value. */
32657 #define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_CLR_MSK 0xfffff7ff
32658 /* The reset value of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */
32659 #define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_RESET 0x0
32660 /* Extracts the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK field value from a register. */
32661 #define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
32662 /* Produces a ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field value suitable for setting the register. */
32663 #define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
32664 
32665 /*
32666  * Field : frm_lst_rollintrmsk
32667  *
32668  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
32669  *
32670  * This bit is valid only when Scatter/Gather DMA mode is enabled.
32671  *
32672  * Field Enumeration Values:
32673  *
32674  * Enum | Value | Description
32675  * :---------------------------------------------------|:------|:------------
32676  * ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
32677  * ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
32678  *
32679  * Field Access Macros:
32680  *
32681  */
32682 /*
32683  * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK
32684  *
32685  * Mask
32686  */
32687 #define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_MSK 0x0
32688 /*
32689  * Enumerated value for register field ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK
32690  *
32691  * No mask
32692  */
32693 #define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
32694 
32695 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */
32696 #define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_LSB 13
32697 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */
32698 #define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_MSB 13
32699 /* The width in bits of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */
32700 #define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_WIDTH 1
32701 /* The mask used to set the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field value. */
32702 #define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
32703 /* The mask used to clear the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field value. */
32704 #define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
32705 /* The reset value of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */
32706 #define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_RESET 0x0
32707 /* Extracts the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK field value from a register. */
32708 #define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
32709 /* Produces a ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
32710 #define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
32711 
32712 #ifndef __ASSEMBLY__
32713 /*
32714  * WARNING: The C register and register group struct declarations are provided for
32715  * convenience and illustrative purposes. They should, however, be used with
32716  * caution as the C language standard provides no guarantees about the alignment or
32717  * atomicity of device memory accesses. The recommended practice for writing
32718  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32719  * alt_write_word() functions.
32720  *
32721  * The struct declaration for register ALT_USB_HOST_HCINTMSK5.
32722  */
32723 struct ALT_USB_HOST_HCINTMSK5_s
32724 {
32725  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK */
32726  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK5_CHHLTDMSK */
32727  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK5_AHBERRMSK */
32728  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK5_STALLMSK */
32729  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK5_NAKMSK */
32730  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK5_ACKMSK */
32731  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK5_NYETMSK */
32732  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK5_XACTERRMSK */
32733  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK5_BBLERRMSK */
32734  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK */
32735  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK */
32736  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK5_BNAINTRMSK */
32737  uint32_t : 1; /* *UNDEFINED* */
32738  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK */
32739  uint32_t : 18; /* *UNDEFINED* */
32740 };
32741 
32742 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK5. */
32743 typedef volatile struct ALT_USB_HOST_HCINTMSK5_s ALT_USB_HOST_HCINTMSK5_t;
32744 #endif /* __ASSEMBLY__ */
32745 
32746 /* The reset value of the ALT_USB_HOST_HCINTMSK5 register. */
32747 #define ALT_USB_HOST_HCINTMSK5_RESET 0x00000000
32748 /* The byte offset of the ALT_USB_HOST_HCINTMSK5 register from the beginning of the component. */
32749 #define ALT_USB_HOST_HCINTMSK5_OFST 0x1ac
32750 /* The address of the ALT_USB_HOST_HCINTMSK5 register. */
32751 #define ALT_USB_HOST_HCINTMSK5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK5_OFST))
32752 
32753 /*
32754  * Register : hctsiz5
32755  *
32756  * Host Channel 5 Transfer Size Register
32757  *
32758  * Register Layout
32759  *
32760  * Bits | Access | Reset | Description
32761  * :--------|:-------|:------|:------------------------------
32762  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ5_XFERSIZE
32763  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ5_PKTCNT
32764  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ5_PID
32765  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ5_DOPNG
32766  *
32767  */
32768 /*
32769  * Field : xfersize
32770  *
32771  * Transfer Size (XferSize)
32772  *
32773  * For an OUT, this field is the number of data bytes the host sends
32774  *
32775  * during the transfer.
32776  *
32777  * For an IN, this field is the buffer size that the application has
32778  *
32779  * Reserved For the transfer. The application is expected to
32780  *
32781  * program this field as an integer multiple of the maximum packet
32782  *
32783  * size For IN transactions (periodic and non-periodic).
32784  *
32785  * The width of this counter is specified as Width of Transfer Size
32786  *
32787  * Counters
32788  *
32789  * Field Access Macros:
32790  *
32791  */
32792 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */
32793 #define ALT_USB_HOST_HCTSIZ5_XFERSIZE_LSB 0
32794 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */
32795 #define ALT_USB_HOST_HCTSIZ5_XFERSIZE_MSB 18
32796 /* The width in bits of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */
32797 #define ALT_USB_HOST_HCTSIZ5_XFERSIZE_WIDTH 19
32798 /* The mask used to set the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field value. */
32799 #define ALT_USB_HOST_HCTSIZ5_XFERSIZE_SET_MSK 0x0007ffff
32800 /* The mask used to clear the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field value. */
32801 #define ALT_USB_HOST_HCTSIZ5_XFERSIZE_CLR_MSK 0xfff80000
32802 /* The reset value of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */
32803 #define ALT_USB_HOST_HCTSIZ5_XFERSIZE_RESET 0x0
32804 /* Extracts the ALT_USB_HOST_HCTSIZ5_XFERSIZE field value from a register. */
32805 #define ALT_USB_HOST_HCTSIZ5_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
32806 /* Produces a ALT_USB_HOST_HCTSIZ5_XFERSIZE register field value suitable for setting the register. */
32807 #define ALT_USB_HOST_HCTSIZ5_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
32808 
32809 /*
32810  * Field : pktcnt
32811  *
32812  * Packet Count (PktCnt)
32813  *
32814  * This field is programmed by the application with the expected
32815  *
32816  * number of packets to be transmitted (OUT) or received (IN).
32817  *
32818  * The host decrements this count on every successful
32819  *
32820  * transmission or reception of an OUT/IN packet. Once this count
32821  *
32822  * reaches zero, the application is interrupted to indicate normal
32823  *
32824  * completion.
32825  *
32826  * The width of this counter is specified as Width of Packet
32827  *
32828  * Counters
32829  *
32830  * Field Access Macros:
32831  *
32832  */
32833 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */
32834 #define ALT_USB_HOST_HCTSIZ5_PKTCNT_LSB 19
32835 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */
32836 #define ALT_USB_HOST_HCTSIZ5_PKTCNT_MSB 28
32837 /* The width in bits of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */
32838 #define ALT_USB_HOST_HCTSIZ5_PKTCNT_WIDTH 10
32839 /* The mask used to set the ALT_USB_HOST_HCTSIZ5_PKTCNT register field value. */
32840 #define ALT_USB_HOST_HCTSIZ5_PKTCNT_SET_MSK 0x1ff80000
32841 /* The mask used to clear the ALT_USB_HOST_HCTSIZ5_PKTCNT register field value. */
32842 #define ALT_USB_HOST_HCTSIZ5_PKTCNT_CLR_MSK 0xe007ffff
32843 /* The reset value of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */
32844 #define ALT_USB_HOST_HCTSIZ5_PKTCNT_RESET 0x0
32845 /* Extracts the ALT_USB_HOST_HCTSIZ5_PKTCNT field value from a register. */
32846 #define ALT_USB_HOST_HCTSIZ5_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
32847 /* Produces a ALT_USB_HOST_HCTSIZ5_PKTCNT register field value suitable for setting the register. */
32848 #define ALT_USB_HOST_HCTSIZ5_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
32849 
32850 /*
32851  * Field : pid
32852  *
32853  * PID (Pid)
32854  *
32855  * The application programs this field with the type of PID to use For
32856  *
32857  * the initial transaction. The host maintains this field For the rest of
32858  *
32859  * the transfer.
32860  *
32861  * 2'b00: DATA0
32862  *
32863  * 2'b01: DATA2
32864  *
32865  * 2'b10: DATA1
32866  *
32867  * 2'b11: MDATA (non-control)/SETUP (control)
32868  *
32869  * Field Enumeration Values:
32870  *
32871  * Enum | Value | Description
32872  * :---------------------------------|:------|:------------------------------------
32873  * ALT_USB_HOST_HCTSIZ5_PID_E_DATA0 | 0x0 | DATA0
32874  * ALT_USB_HOST_HCTSIZ5_PID_E_DATA2 | 0x1 | DATA2
32875  * ALT_USB_HOST_HCTSIZ5_PID_E_DATA1 | 0x2 | DATA1
32876  * ALT_USB_HOST_HCTSIZ5_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
32877  *
32878  * Field Access Macros:
32879  *
32880  */
32881 /*
32882  * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID
32883  *
32884  * DATA0
32885  */
32886 #define ALT_USB_HOST_HCTSIZ5_PID_E_DATA0 0x0
32887 /*
32888  * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID
32889  *
32890  * DATA2
32891  */
32892 #define ALT_USB_HOST_HCTSIZ5_PID_E_DATA2 0x1
32893 /*
32894  * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID
32895  *
32896  * DATA1
32897  */
32898 #define ALT_USB_HOST_HCTSIZ5_PID_E_DATA1 0x2
32899 /*
32900  * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID
32901  *
32902  * MDATA (non-control)/SETUP (control)
32903  */
32904 #define ALT_USB_HOST_HCTSIZ5_PID_E_MDATA 0x3
32905 
32906 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_PID register field. */
32907 #define ALT_USB_HOST_HCTSIZ5_PID_LSB 29
32908 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_PID register field. */
32909 #define ALT_USB_HOST_HCTSIZ5_PID_MSB 30
32910 /* The width in bits of the ALT_USB_HOST_HCTSIZ5_PID register field. */
32911 #define ALT_USB_HOST_HCTSIZ5_PID_WIDTH 2
32912 /* The mask used to set the ALT_USB_HOST_HCTSIZ5_PID register field value. */
32913 #define ALT_USB_HOST_HCTSIZ5_PID_SET_MSK 0x60000000
32914 /* The mask used to clear the ALT_USB_HOST_HCTSIZ5_PID register field value. */
32915 #define ALT_USB_HOST_HCTSIZ5_PID_CLR_MSK 0x9fffffff
32916 /* The reset value of the ALT_USB_HOST_HCTSIZ5_PID register field. */
32917 #define ALT_USB_HOST_HCTSIZ5_PID_RESET 0x0
32918 /* Extracts the ALT_USB_HOST_HCTSIZ5_PID field value from a register. */
32919 #define ALT_USB_HOST_HCTSIZ5_PID_GET(value) (((value) & 0x60000000) >> 29)
32920 /* Produces a ALT_USB_HOST_HCTSIZ5_PID register field value suitable for setting the register. */
32921 #define ALT_USB_HOST_HCTSIZ5_PID_SET(value) (((value) << 29) & 0x60000000)
32922 
32923 /*
32924  * Field : dopng
32925  *
32926  * Do Ping (DoPng)
32927  *
32928  * This bit is used only For OUT transfers.
32929  *
32930  * Setting this field to 1 directs the host to do PING protocol.
32931  *
32932  * Note: Do not Set this bit For IN transfers. If this bit is Set For
32933  *
32934  * for IN transfers it disables the channel.
32935  *
32936  * Field Enumeration Values:
32937  *
32938  * Enum | Value | Description
32939  * :------------------------------------|:------|:-----------------
32940  * ALT_USB_HOST_HCTSIZ5_DOPNG_E_NOPING | 0x0 | No ping protocol
32941  * ALT_USB_HOST_HCTSIZ5_DOPNG_E_PING | 0x1 | Ping protocol
32942  *
32943  * Field Access Macros:
32944  *
32945  */
32946 /*
32947  * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_DOPNG
32948  *
32949  * No ping protocol
32950  */
32951 #define ALT_USB_HOST_HCTSIZ5_DOPNG_E_NOPING 0x0
32952 /*
32953  * Enumerated value for register field ALT_USB_HOST_HCTSIZ5_DOPNG
32954  *
32955  * Ping protocol
32956  */
32957 #define ALT_USB_HOST_HCTSIZ5_DOPNG_E_PING 0x1
32958 
32959 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */
32960 #define ALT_USB_HOST_HCTSIZ5_DOPNG_LSB 31
32961 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */
32962 #define ALT_USB_HOST_HCTSIZ5_DOPNG_MSB 31
32963 /* The width in bits of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */
32964 #define ALT_USB_HOST_HCTSIZ5_DOPNG_WIDTH 1
32965 /* The mask used to set the ALT_USB_HOST_HCTSIZ5_DOPNG register field value. */
32966 #define ALT_USB_HOST_HCTSIZ5_DOPNG_SET_MSK 0x80000000
32967 /* The mask used to clear the ALT_USB_HOST_HCTSIZ5_DOPNG register field value. */
32968 #define ALT_USB_HOST_HCTSIZ5_DOPNG_CLR_MSK 0x7fffffff
32969 /* The reset value of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */
32970 #define ALT_USB_HOST_HCTSIZ5_DOPNG_RESET 0x0
32971 /* Extracts the ALT_USB_HOST_HCTSIZ5_DOPNG field value from a register. */
32972 #define ALT_USB_HOST_HCTSIZ5_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
32973 /* Produces a ALT_USB_HOST_HCTSIZ5_DOPNG register field value suitable for setting the register. */
32974 #define ALT_USB_HOST_HCTSIZ5_DOPNG_SET(value) (((value) << 31) & 0x80000000)
32975 
32976 #ifndef __ASSEMBLY__
32977 /*
32978  * WARNING: The C register and register group struct declarations are provided for
32979  * convenience and illustrative purposes. They should, however, be used with
32980  * caution as the C language standard provides no guarantees about the alignment or
32981  * atomicity of device memory accesses. The recommended practice for writing
32982  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32983  * alt_write_word() functions.
32984  *
32985  * The struct declaration for register ALT_USB_HOST_HCTSIZ5.
32986  */
32987 struct ALT_USB_HOST_HCTSIZ5_s
32988 {
32989  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ5_XFERSIZE */
32990  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ5_PKTCNT */
32991  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ5_PID */
32992  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ5_DOPNG */
32993 };
32994 
32995 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ5. */
32996 typedef volatile struct ALT_USB_HOST_HCTSIZ5_s ALT_USB_HOST_HCTSIZ5_t;
32997 #endif /* __ASSEMBLY__ */
32998 
32999 /* The reset value of the ALT_USB_HOST_HCTSIZ5 register. */
33000 #define ALT_USB_HOST_HCTSIZ5_RESET 0x00000000
33001 /* The byte offset of the ALT_USB_HOST_HCTSIZ5 register from the beginning of the component. */
33002 #define ALT_USB_HOST_HCTSIZ5_OFST 0x1b0
33003 /* The address of the ALT_USB_HOST_HCTSIZ5 register. */
33004 #define ALT_USB_HOST_HCTSIZ5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ5_OFST))
33005 
33006 /*
33007  * Register : hcdma5
33008  *
33009  * Host Channel 5 DMA Address Register
33010  *
33011  * Register Layout
33012  *
33013  * Bits | Access | Reset | Description
33014  * :-------|:-------|:------|:---------------------------
33015  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA5_HCDMA5
33016  *
33017  */
33018 /*
33019  * Field : hcdma5
33020  *
33021  * Buffer DMA Mode:
33022  *
33023  * [31:0] DMA Address (DMAAddr)
33024  *
33025  * This field holds the start address in the external memory from which the data
33026  * for
33027  *
33028  * the endpoint must be fetched or to which it must be stored. This register is
33029  *
33030  * incremented on every AHB transaction.
33031  *
33032  * Scatter-Gather DMA (DescDMA) Mode:
33033  *
33034  * [31:9] (Non Isoc) Non-Isochronous:
33035  *
33036  * [31:N] (Isoc) Isochronous:
33037  *
33038  * This field holds the start address of the 512 bytes
33039  *
33040  * page. The first descriptor in the list should be located
33041  *
33042  * in this address. The first descriptor may be or may
33043  *
33044  * not be ready. The core starts processing the list from
33045  *
33046  * the CTD value.
33047  *
33048  * This field holds the address of the 2*(nTD+1) bytes of
33049  *
33050  * locations in which the isochronous descriptors are
33051  *
33052  * present where N is based on nTD as per Table below
33053  *
33054  * [31:N] Base Address
33055  *
33056  * [N-1:3] Offset
33057  *
33058  * [2:0] 000
33059  *
33060  * HS ISOC
33061  *
33062  * nTD N
33063  *
33064  * 7 6
33065  *
33066  * 15 7
33067  *
33068  * 31 8
33069  *
33070  * 63 9
33071  *
33072  * 127 10
33073  *
33074  * 255 11
33075  *
33076  * FS ISOC
33077  *
33078  * nTD N
33079  *
33080  * 1 4
33081  *
33082  * 3 5
33083  *
33084  * 7 6
33085  *
33086  * 15 7
33087  *
33088  * 31 8
33089  *
33090  * 63 9
33091  *
33092  * [N-1:3] (Isoc):
33093  *
33094  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
33095  *
33096  * Non Isochronous:
33097  *
33098  * This value is in terms of number of descriptors. The values can be from 0 to 63.
33099  *
33100  * 0 - 1 descriptor.
33101  *
33102  * 63 - 64 descriptors.
33103  *
33104  * This field indicates the current descriptor processed in the list. This field is
33105  * updated
33106  *
33107  * both by application and the core. For example, if the application enables the
33108  *
33109  * channel after programming CTD=5, then the core will start processing the 6th
33110  *
33111  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
33112  *
33113  * to DMAAddr.
33114  *
33115  * Isochronous:
33116  *
33117  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
33118  * set
33119  *
33120  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
33121  *
33122  * [31:9] (Non Isoc) Non-Isochronous:
33123  *
33124  * [31:N] (Isoc) Isochronous:
33125  *
33126  * This field holds the start address of the 512 bytes
33127  *
33128  * page. The first descriptor in the list should be located
33129  *
33130  * in this address. The first descriptor may be or may
33131  *
33132  * not be ready. The core starts processing the list from
33133  *
33134  * the CTD value.
33135  *
33136  * This field holds the address of the 2*(nTD+1) bytes of
33137  *
33138  * locations in which the isochronous descriptors are
33139  *
33140  * present where N is based on nTD as per Table below
33141  *
33142  * [31:N] Base Address
33143  *
33144  * [N-1:3] Offset
33145  *
33146  * [2:0] 000
33147  *
33148  * HS ISOC
33149  *
33150  * nTD N
33151  *
33152  * 7 6
33153  *
33154  * 15 7
33155  *
33156  * 31 8
33157  *
33158  * 63 9
33159  *
33160  * 127 10
33161  *
33162  * 255 11
33163  *
33164  * FS ISOC
33165  *
33166  * nTD N
33167  *
33168  * 1 4
33169  *
33170  * 3 5
33171  *
33172  * 7 6
33173  *
33174  * 15 7
33175  *
33176  * 31 8
33177  *
33178  * 63 9
33179  *
33180  * [N-1:3] (Isoc):
33181  *
33182  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
33183  *
33184  * Non Isochronous:
33185  *
33186  * This value is in terms of number of descriptors. The values can be from 0 to 63.
33187  *
33188  * 0 - 1 descriptor.
33189  *
33190  * 63 - 64 descriptors.
33191  *
33192  * This field indicates the current descriptor processed in the list. This field is
33193  * updated
33194  *
33195  * both by application and the core. For example, if the application enables the
33196  *
33197  * channel after programming CTD=5, then the core will start processing the 6th
33198  *
33199  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
33200  *
33201  * to DMAAddr.
33202  *
33203  * Isochronous:
33204  *
33205  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
33206  * set
33207  *
33208  * to zero by application.
33209  *
33210  * Field Access Macros:
33211  *
33212  */
33213 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */
33214 #define ALT_USB_HOST_HCDMA5_HCDMA5_LSB 0
33215 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */
33216 #define ALT_USB_HOST_HCDMA5_HCDMA5_MSB 31
33217 /* The width in bits of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */
33218 #define ALT_USB_HOST_HCDMA5_HCDMA5_WIDTH 32
33219 /* The mask used to set the ALT_USB_HOST_HCDMA5_HCDMA5 register field value. */
33220 #define ALT_USB_HOST_HCDMA5_HCDMA5_SET_MSK 0xffffffff
33221 /* The mask used to clear the ALT_USB_HOST_HCDMA5_HCDMA5 register field value. */
33222 #define ALT_USB_HOST_HCDMA5_HCDMA5_CLR_MSK 0x00000000
33223 /* The reset value of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */
33224 #define ALT_USB_HOST_HCDMA5_HCDMA5_RESET 0x0
33225 /* Extracts the ALT_USB_HOST_HCDMA5_HCDMA5 field value from a register. */
33226 #define ALT_USB_HOST_HCDMA5_HCDMA5_GET(value) (((value) & 0xffffffff) >> 0)
33227 /* Produces a ALT_USB_HOST_HCDMA5_HCDMA5 register field value suitable for setting the register. */
33228 #define ALT_USB_HOST_HCDMA5_HCDMA5_SET(value) (((value) << 0) & 0xffffffff)
33229 
33230 #ifndef __ASSEMBLY__
33231 /*
33232  * WARNING: The C register and register group struct declarations are provided for
33233  * convenience and illustrative purposes. They should, however, be used with
33234  * caution as the C language standard provides no guarantees about the alignment or
33235  * atomicity of device memory accesses. The recommended practice for writing
33236  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33237  * alt_write_word() functions.
33238  *
33239  * The struct declaration for register ALT_USB_HOST_HCDMA5.
33240  */
33241 struct ALT_USB_HOST_HCDMA5_s
33242 {
33243  uint32_t hcdma5 : 32; /* ALT_USB_HOST_HCDMA5_HCDMA5 */
33244 };
33245 
33246 /* The typedef declaration for register ALT_USB_HOST_HCDMA5. */
33247 typedef volatile struct ALT_USB_HOST_HCDMA5_s ALT_USB_HOST_HCDMA5_t;
33248 #endif /* __ASSEMBLY__ */
33249 
33250 /* The reset value of the ALT_USB_HOST_HCDMA5 register. */
33251 #define ALT_USB_HOST_HCDMA5_RESET 0x00000000
33252 /* The byte offset of the ALT_USB_HOST_HCDMA5 register from the beginning of the component. */
33253 #define ALT_USB_HOST_HCDMA5_OFST 0x1b4
33254 /* The address of the ALT_USB_HOST_HCDMA5 register. */
33255 #define ALT_USB_HOST_HCDMA5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA5_OFST))
33256 
33257 /*
33258  * Register : hcdmab5
33259  *
33260  * Host Channel 5 DMA Buffer Address Register
33261  *
33262  * Register Layout
33263  *
33264  * Bits | Access | Reset | Description
33265  * :-------|:-------|:------|:-----------------------------
33266  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB5_HCDMAB5
33267  *
33268  */
33269 /*
33270  * Field : hcdmab5
33271  *
33272  * Holds the current buffer address.
33273  *
33274  * This register is updated as and when the data transfer for the corresponding end
33275  * point
33276  *
33277  * is in progress. This register is present only in Scatter/Gather DMA mode.
33278  * Otherwise this
33279  *
33280  * field is reserved.
33281  *
33282  * Field Access Macros:
33283  *
33284  */
33285 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */
33286 #define ALT_USB_HOST_HCDMAB5_HCDMAB5_LSB 0
33287 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */
33288 #define ALT_USB_HOST_HCDMAB5_HCDMAB5_MSB 31
33289 /* The width in bits of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */
33290 #define ALT_USB_HOST_HCDMAB5_HCDMAB5_WIDTH 32
33291 /* The mask used to set the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field value. */
33292 #define ALT_USB_HOST_HCDMAB5_HCDMAB5_SET_MSK 0xffffffff
33293 /* The mask used to clear the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field value. */
33294 #define ALT_USB_HOST_HCDMAB5_HCDMAB5_CLR_MSK 0x00000000
33295 /* The reset value of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */
33296 #define ALT_USB_HOST_HCDMAB5_HCDMAB5_RESET 0x0
33297 /* Extracts the ALT_USB_HOST_HCDMAB5_HCDMAB5 field value from a register. */
33298 #define ALT_USB_HOST_HCDMAB5_HCDMAB5_GET(value) (((value) & 0xffffffff) >> 0)
33299 /* Produces a ALT_USB_HOST_HCDMAB5_HCDMAB5 register field value suitable for setting the register. */
33300 #define ALT_USB_HOST_HCDMAB5_HCDMAB5_SET(value) (((value) << 0) & 0xffffffff)
33301 
33302 #ifndef __ASSEMBLY__
33303 /*
33304  * WARNING: The C register and register group struct declarations are provided for
33305  * convenience and illustrative purposes. They should, however, be used with
33306  * caution as the C language standard provides no guarantees about the alignment or
33307  * atomicity of device memory accesses. The recommended practice for writing
33308  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33309  * alt_write_word() functions.
33310  *
33311  * The struct declaration for register ALT_USB_HOST_HCDMAB5.
33312  */
33313 struct ALT_USB_HOST_HCDMAB5_s
33314 {
33315  uint32_t hcdmab5 : 32; /* ALT_USB_HOST_HCDMAB5_HCDMAB5 */
33316 };
33317 
33318 /* The typedef declaration for register ALT_USB_HOST_HCDMAB5. */
33319 typedef volatile struct ALT_USB_HOST_HCDMAB5_s ALT_USB_HOST_HCDMAB5_t;
33320 #endif /* __ASSEMBLY__ */
33321 
33322 /* The reset value of the ALT_USB_HOST_HCDMAB5 register. */
33323 #define ALT_USB_HOST_HCDMAB5_RESET 0x00000000
33324 /* The byte offset of the ALT_USB_HOST_HCDMAB5 register from the beginning of the component. */
33325 #define ALT_USB_HOST_HCDMAB5_OFST 0x1bc
33326 /* The address of the ALT_USB_HOST_HCDMAB5 register. */
33327 #define ALT_USB_HOST_HCDMAB5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB5_OFST))
33328 
33329 /*
33330  * Register : hcchar6
33331  *
33332  * Host Channel 6 Characteristics Register
33333  *
33334  * Register Layout
33335  *
33336  * Bits | Access | Reset | Description
33337  * :--------|:---------|:------|:-----------------------------
33338  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_MPS
33339  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_EPNUM
33340  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_EPDIR
33341  * [16] | ??? | 0x0 | *UNDEFINED*
33342  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_LSPDDEV
33343  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_EPTYPE
33344  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_EC
33345  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_DEVADDR
33346  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_ODDFRM
33347  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR6_CHDIS
33348  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR6_CHENA
33349  *
33350  */
33351 /*
33352  * Field : mps
33353  *
33354  * Maximum Packet Size (MPS)
33355  *
33356  * Indicates the maximum packet size of the associated endpoint.
33357  *
33358  * Field Access Macros:
33359  *
33360  */
33361 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_MPS register field. */
33362 #define ALT_USB_HOST_HCCHAR6_MPS_LSB 0
33363 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_MPS register field. */
33364 #define ALT_USB_HOST_HCCHAR6_MPS_MSB 10
33365 /* The width in bits of the ALT_USB_HOST_HCCHAR6_MPS register field. */
33366 #define ALT_USB_HOST_HCCHAR6_MPS_WIDTH 11
33367 /* The mask used to set the ALT_USB_HOST_HCCHAR6_MPS register field value. */
33368 #define ALT_USB_HOST_HCCHAR6_MPS_SET_MSK 0x000007ff
33369 /* The mask used to clear the ALT_USB_HOST_HCCHAR6_MPS register field value. */
33370 #define ALT_USB_HOST_HCCHAR6_MPS_CLR_MSK 0xfffff800
33371 /* The reset value of the ALT_USB_HOST_HCCHAR6_MPS register field. */
33372 #define ALT_USB_HOST_HCCHAR6_MPS_RESET 0x0
33373 /* Extracts the ALT_USB_HOST_HCCHAR6_MPS field value from a register. */
33374 #define ALT_USB_HOST_HCCHAR6_MPS_GET(value) (((value) & 0x000007ff) >> 0)
33375 /* Produces a ALT_USB_HOST_HCCHAR6_MPS register field value suitable for setting the register. */
33376 #define ALT_USB_HOST_HCCHAR6_MPS_SET(value) (((value) << 0) & 0x000007ff)
33377 
33378 /*
33379  * Field : epnum
33380  *
33381  * Endpoint Number (EPNum)
33382  *
33383  * Indicates the endpoint number on the device serving as the data
33384  *
33385  * source or sink.
33386  *
33387  * Field Enumeration Values:
33388  *
33389  * Enum | Value | Description
33390  * :-------------------------------------|:------|:--------------
33391  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT0 | 0x0 | End point 0
33392  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT1 | 0x1 | End point 1
33393  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT2 | 0x2 | End point 2
33394  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT3 | 0x3 | End point 3
33395  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT4 | 0x4 | End point 4
33396  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT5 | 0x5 | End point 5
33397  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT6 | 0x6 | End point 6
33398  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT7 | 0x7 | End point 7
33399  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT8 | 0x8 | End point 8
33400  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT9 | 0x9 | End point 9
33401  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT10 | 0xa | End point 10
33402  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT11 | 0xb | End point 11
33403  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT12 | 0xc | End point 12
33404  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT13 | 0xd | End point 13
33405  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT14 | 0xe | End point 14
33406  * ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT15 | 0xf | End point 15
33407  *
33408  * Field Access Macros:
33409  *
33410  */
33411 /*
33412  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33413  *
33414  * End point 0
33415  */
33416 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT0 0x0
33417 /*
33418  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33419  *
33420  * End point 1
33421  */
33422 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT1 0x1
33423 /*
33424  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33425  *
33426  * End point 2
33427  */
33428 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT2 0x2
33429 /*
33430  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33431  *
33432  * End point 3
33433  */
33434 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT3 0x3
33435 /*
33436  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33437  *
33438  * End point 4
33439  */
33440 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT4 0x4
33441 /*
33442  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33443  *
33444  * End point 5
33445  */
33446 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT5 0x5
33447 /*
33448  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33449  *
33450  * End point 6
33451  */
33452 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT6 0x6
33453 /*
33454  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33455  *
33456  * End point 7
33457  */
33458 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT7 0x7
33459 /*
33460  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33461  *
33462  * End point 8
33463  */
33464 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT8 0x8
33465 /*
33466  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33467  *
33468  * End point 9
33469  */
33470 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT9 0x9
33471 /*
33472  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33473  *
33474  * End point 10
33475  */
33476 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT10 0xa
33477 /*
33478  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33479  *
33480  * End point 11
33481  */
33482 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT11 0xb
33483 /*
33484  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33485  *
33486  * End point 12
33487  */
33488 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT12 0xc
33489 /*
33490  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33491  *
33492  * End point 13
33493  */
33494 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT13 0xd
33495 /*
33496  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33497  *
33498  * End point 14
33499  */
33500 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT14 0xe
33501 /*
33502  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
33503  *
33504  * End point 15
33505  */
33506 #define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT15 0xf
33507 
33508 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */
33509 #define ALT_USB_HOST_HCCHAR6_EPNUM_LSB 11
33510 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */
33511 #define ALT_USB_HOST_HCCHAR6_EPNUM_MSB 14
33512 /* The width in bits of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */
33513 #define ALT_USB_HOST_HCCHAR6_EPNUM_WIDTH 4
33514 /* The mask used to set the ALT_USB_HOST_HCCHAR6_EPNUM register field value. */
33515 #define ALT_USB_HOST_HCCHAR6_EPNUM_SET_MSK 0x00007800
33516 /* The mask used to clear the ALT_USB_HOST_HCCHAR6_EPNUM register field value. */
33517 #define ALT_USB_HOST_HCCHAR6_EPNUM_CLR_MSK 0xffff87ff
33518 /* The reset value of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */
33519 #define ALT_USB_HOST_HCCHAR6_EPNUM_RESET 0x0
33520 /* Extracts the ALT_USB_HOST_HCCHAR6_EPNUM field value from a register. */
33521 #define ALT_USB_HOST_HCCHAR6_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
33522 /* Produces a ALT_USB_HOST_HCCHAR6_EPNUM register field value suitable for setting the register. */
33523 #define ALT_USB_HOST_HCCHAR6_EPNUM_SET(value) (((value) << 11) & 0x00007800)
33524 
33525 /*
33526  * Field : epdir
33527  *
33528  * Endpoint Direction (EPDir)
33529  *
33530  * Indicates whether the transaction is IN or OUT.
33531  *
33532  * 1'b0: OUT
33533  *
33534  * 1'b1: IN
33535  *
33536  * Field Enumeration Values:
33537  *
33538  * Enum | Value | Description
33539  * :---------------------------------|:------|:--------------
33540  * ALT_USB_HOST_HCCHAR6_EPDIR_E_OUT | 0x0 | OUT Direction
33541  * ALT_USB_HOST_HCCHAR6_EPDIR_E_IN | 0x1 | IN Direction
33542  *
33543  * Field Access Macros:
33544  *
33545  */
33546 /*
33547  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPDIR
33548  *
33549  * OUT Direction
33550  */
33551 #define ALT_USB_HOST_HCCHAR6_EPDIR_E_OUT 0x0
33552 /*
33553  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPDIR
33554  *
33555  * IN Direction
33556  */
33557 #define ALT_USB_HOST_HCCHAR6_EPDIR_E_IN 0x1
33558 
33559 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */
33560 #define ALT_USB_HOST_HCCHAR6_EPDIR_LSB 15
33561 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */
33562 #define ALT_USB_HOST_HCCHAR6_EPDIR_MSB 15
33563 /* The width in bits of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */
33564 #define ALT_USB_HOST_HCCHAR6_EPDIR_WIDTH 1
33565 /* The mask used to set the ALT_USB_HOST_HCCHAR6_EPDIR register field value. */
33566 #define ALT_USB_HOST_HCCHAR6_EPDIR_SET_MSK 0x00008000
33567 /* The mask used to clear the ALT_USB_HOST_HCCHAR6_EPDIR register field value. */
33568 #define ALT_USB_HOST_HCCHAR6_EPDIR_CLR_MSK 0xffff7fff
33569 /* The reset value of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */
33570 #define ALT_USB_HOST_HCCHAR6_EPDIR_RESET 0x0
33571 /* Extracts the ALT_USB_HOST_HCCHAR6_EPDIR field value from a register. */
33572 #define ALT_USB_HOST_HCCHAR6_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
33573 /* Produces a ALT_USB_HOST_HCCHAR6_EPDIR register field value suitable for setting the register. */
33574 #define ALT_USB_HOST_HCCHAR6_EPDIR_SET(value) (((value) << 15) & 0x00008000)
33575 
33576 /*
33577  * Field : lspddev
33578  *
33579  * Low-Speed Device (LSpdDev)
33580  *
33581  * This field is Set by the application to indicate that this channel is
33582  *
33583  * communicating to a low-speed device.
33584  *
33585  * Field Enumeration Values:
33586  *
33587  * Enum | Value | Description
33588  * :------------------------------------|:------|:----------------------------------------
33589  * ALT_USB_HOST_HCCHAR6_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
33590  * ALT_USB_HOST_HCCHAR6_LSPDDEV_E_END | 0x1 | Communicating with low speed device
33591  *
33592  * Field Access Macros:
33593  *
33594  */
33595 /*
33596  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_LSPDDEV
33597  *
33598  * Not Communicating with low speed device
33599  */
33600 #define ALT_USB_HOST_HCCHAR6_LSPDDEV_E_DISD 0x0
33601 /*
33602  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_LSPDDEV
33603  *
33604  * Communicating with low speed device
33605  */
33606 #define ALT_USB_HOST_HCCHAR6_LSPDDEV_E_END 0x1
33607 
33608 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */
33609 #define ALT_USB_HOST_HCCHAR6_LSPDDEV_LSB 17
33610 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */
33611 #define ALT_USB_HOST_HCCHAR6_LSPDDEV_MSB 17
33612 /* The width in bits of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */
33613 #define ALT_USB_HOST_HCCHAR6_LSPDDEV_WIDTH 1
33614 /* The mask used to set the ALT_USB_HOST_HCCHAR6_LSPDDEV register field value. */
33615 #define ALT_USB_HOST_HCCHAR6_LSPDDEV_SET_MSK 0x00020000
33616 /* The mask used to clear the ALT_USB_HOST_HCCHAR6_LSPDDEV register field value. */
33617 #define ALT_USB_HOST_HCCHAR6_LSPDDEV_CLR_MSK 0xfffdffff
33618 /* The reset value of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */
33619 #define ALT_USB_HOST_HCCHAR6_LSPDDEV_RESET 0x0
33620 /* Extracts the ALT_USB_HOST_HCCHAR6_LSPDDEV field value from a register. */
33621 #define ALT_USB_HOST_HCCHAR6_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
33622 /* Produces a ALT_USB_HOST_HCCHAR6_LSPDDEV register field value suitable for setting the register. */
33623 #define ALT_USB_HOST_HCCHAR6_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
33624 
33625 /*
33626  * Field : eptype
33627  *
33628  * Endpoint Type (EPType)
33629  *
33630  * Indicates the transfer type selected.
33631  *
33632  * 2'b00: Control
33633  *
33634  * 2'b01: Isochronous
33635  *
33636  * 2'b10: Bulk
33637  *
33638  * 2'b11: Interrupt
33639  *
33640  * Field Enumeration Values:
33641  *
33642  * Enum | Value | Description
33643  * :-------------------------------------|:------|:------------
33644  * ALT_USB_HOST_HCCHAR6_EPTYPE_E_CTL | 0x0 | Control
33645  * ALT_USB_HOST_HCCHAR6_EPTYPE_E_ISOC | 0x1 | Isochronous
33646  * ALT_USB_HOST_HCCHAR6_EPTYPE_E_BULK | 0x2 | Bulk
33647  * ALT_USB_HOST_HCCHAR6_EPTYPE_E_INTERR | 0x3 | Interrupt
33648  *
33649  * Field Access Macros:
33650  *
33651  */
33652 /*
33653  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE
33654  *
33655  * Control
33656  */
33657 #define ALT_USB_HOST_HCCHAR6_EPTYPE_E_CTL 0x0
33658 /*
33659  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE
33660  *
33661  * Isochronous
33662  */
33663 #define ALT_USB_HOST_HCCHAR6_EPTYPE_E_ISOC 0x1
33664 /*
33665  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE
33666  *
33667  * Bulk
33668  */
33669 #define ALT_USB_HOST_HCCHAR6_EPTYPE_E_BULK 0x2
33670 /*
33671  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE
33672  *
33673  * Interrupt
33674  */
33675 #define ALT_USB_HOST_HCCHAR6_EPTYPE_E_INTERR 0x3
33676 
33677 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */
33678 #define ALT_USB_HOST_HCCHAR6_EPTYPE_LSB 18
33679 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */
33680 #define ALT_USB_HOST_HCCHAR6_EPTYPE_MSB 19
33681 /* The width in bits of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */
33682 #define ALT_USB_HOST_HCCHAR6_EPTYPE_WIDTH 2
33683 /* The mask used to set the ALT_USB_HOST_HCCHAR6_EPTYPE register field value. */
33684 #define ALT_USB_HOST_HCCHAR6_EPTYPE_SET_MSK 0x000c0000
33685 /* The mask used to clear the ALT_USB_HOST_HCCHAR6_EPTYPE register field value. */
33686 #define ALT_USB_HOST_HCCHAR6_EPTYPE_CLR_MSK 0xfff3ffff
33687 /* The reset value of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */
33688 #define ALT_USB_HOST_HCCHAR6_EPTYPE_RESET 0x0
33689 /* Extracts the ALT_USB_HOST_HCCHAR6_EPTYPE field value from a register. */
33690 #define ALT_USB_HOST_HCCHAR6_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
33691 /* Produces a ALT_USB_HOST_HCCHAR6_EPTYPE register field value suitable for setting the register. */
33692 #define ALT_USB_HOST_HCCHAR6_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
33693 
33694 /*
33695  * Field : ec
33696  *
33697  * Multi Count (MC) / Error Count (EC)
33698  *
33699  * When the Split Enable bit of the Host Channel-n Split Control
33700  *
33701  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
33702  *
33703  * the host the number of transactions that must be executed per
33704  *
33705  * microframe For this periodic endpoint. For non periodic transfers,
33706  *
33707  * this field is used only in DMA mode, and specifies the number
33708  *
33709  * packets to be fetched For this channel before the internal DMA
33710  *
33711  * engine changes arbitration.
33712  *
33713  * 2'b00: Reserved This field yields undefined results.
33714  *
33715  * 2'b01: 1 transaction
33716  *
33717  * 2'b10: 2 transactions to be issued For this endpoint per
33718  *
33719  * microframe
33720  *
33721  * 2'b11: 3 transactions to be issued For this endpoint per
33722  *
33723  * microframe
33724  *
33725  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
33726  *
33727  * number of immediate retries to be performed For a periodic split
33728  *
33729  * transactions on transaction errors. This field must be Set to at
33730  *
33731  * least 2'b01.
33732  *
33733  * Field Enumeration Values:
33734  *
33735  * Enum | Value | Description
33736  * :-------------------------------------|:------|:----------------------------------------------
33737  * ALT_USB_HOST_HCCHAR6_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
33738  * ALT_USB_HOST_HCCHAR6_EC_E_TRANSONE | 0x1 | 1 transaction
33739  * ALT_USB_HOST_HCCHAR6_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
33740  * : | | per microframe
33741  * ALT_USB_HOST_HCCHAR6_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
33742  * : | | per microframe
33743  *
33744  * Field Access Macros:
33745  *
33746  */
33747 /*
33748  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC
33749  *
33750  * Reserved This field yields undefined result
33751  */
33752 #define ALT_USB_HOST_HCCHAR6_EC_E_RSVD 0x0
33753 /*
33754  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC
33755  *
33756  * 1 transaction
33757  */
33758 #define ALT_USB_HOST_HCCHAR6_EC_E_TRANSONE 0x1
33759 /*
33760  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC
33761  *
33762  * 2 transactions to be issued for this endpoint per microframe
33763  */
33764 #define ALT_USB_HOST_HCCHAR6_EC_E_TRANSTWO 0x2
33765 /*
33766  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC
33767  *
33768  * 3 transactions to be issued for this endpoint per microframe
33769  */
33770 #define ALT_USB_HOST_HCCHAR6_EC_E_TRANSTHREE 0x3
33771 
33772 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EC register field. */
33773 #define ALT_USB_HOST_HCCHAR6_EC_LSB 20
33774 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EC register field. */
33775 #define ALT_USB_HOST_HCCHAR6_EC_MSB 21
33776 /* The width in bits of the ALT_USB_HOST_HCCHAR6_EC register field. */
33777 #define ALT_USB_HOST_HCCHAR6_EC_WIDTH 2
33778 /* The mask used to set the ALT_USB_HOST_HCCHAR6_EC register field value. */
33779 #define ALT_USB_HOST_HCCHAR6_EC_SET_MSK 0x00300000
33780 /* The mask used to clear the ALT_USB_HOST_HCCHAR6_EC register field value. */
33781 #define ALT_USB_HOST_HCCHAR6_EC_CLR_MSK 0xffcfffff
33782 /* The reset value of the ALT_USB_HOST_HCCHAR6_EC register field. */
33783 #define ALT_USB_HOST_HCCHAR6_EC_RESET 0x0
33784 /* Extracts the ALT_USB_HOST_HCCHAR6_EC field value from a register. */
33785 #define ALT_USB_HOST_HCCHAR6_EC_GET(value) (((value) & 0x00300000) >> 20)
33786 /* Produces a ALT_USB_HOST_HCCHAR6_EC register field value suitable for setting the register. */
33787 #define ALT_USB_HOST_HCCHAR6_EC_SET(value) (((value) << 20) & 0x00300000)
33788 
33789 /*
33790  * Field : devaddr
33791  *
33792  * Device Address (DevAddr)
33793  *
33794  * This field selects the specific device serving as the data source
33795  *
33796  * or sink.
33797  *
33798  * Field Access Macros:
33799  *
33800  */
33801 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */
33802 #define ALT_USB_HOST_HCCHAR6_DEVADDR_LSB 22
33803 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */
33804 #define ALT_USB_HOST_HCCHAR6_DEVADDR_MSB 28
33805 /* The width in bits of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */
33806 #define ALT_USB_HOST_HCCHAR6_DEVADDR_WIDTH 7
33807 /* The mask used to set the ALT_USB_HOST_HCCHAR6_DEVADDR register field value. */
33808 #define ALT_USB_HOST_HCCHAR6_DEVADDR_SET_MSK 0x1fc00000
33809 /* The mask used to clear the ALT_USB_HOST_HCCHAR6_DEVADDR register field value. */
33810 #define ALT_USB_HOST_HCCHAR6_DEVADDR_CLR_MSK 0xe03fffff
33811 /* The reset value of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */
33812 #define ALT_USB_HOST_HCCHAR6_DEVADDR_RESET 0x0
33813 /* Extracts the ALT_USB_HOST_HCCHAR6_DEVADDR field value from a register. */
33814 #define ALT_USB_HOST_HCCHAR6_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
33815 /* Produces a ALT_USB_HOST_HCCHAR6_DEVADDR register field value suitable for setting the register. */
33816 #define ALT_USB_HOST_HCCHAR6_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
33817 
33818 /*
33819  * Field : oddfrm
33820  *
33821  * Odd Frame (OddFrm)
33822  *
33823  * This field is set (reset) by the application to indicate that the OTG host must
33824  * perform
33825  *
33826  * a transfer in an odd (micro)frame. This field is applicable for only periodic
33827  *
33828  * (isochronous and interrupt) transactions.
33829  *
33830  * 1'b0: Even (micro)frame
33831  *
33832  * 1'b1: Odd (micro)frame
33833  *
33834  * Field Access Macros:
33835  *
33836  */
33837 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_ODDFRM register field. */
33838 #define ALT_USB_HOST_HCCHAR6_ODDFRM_LSB 29
33839 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_ODDFRM register field. */
33840 #define ALT_USB_HOST_HCCHAR6_ODDFRM_MSB 29
33841 /* The width in bits of the ALT_USB_HOST_HCCHAR6_ODDFRM register field. */
33842 #define ALT_USB_HOST_HCCHAR6_ODDFRM_WIDTH 1
33843 /* The mask used to set the ALT_USB_HOST_HCCHAR6_ODDFRM register field value. */
33844 #define ALT_USB_HOST_HCCHAR6_ODDFRM_SET_MSK 0x20000000
33845 /* The mask used to clear the ALT_USB_HOST_HCCHAR6_ODDFRM register field value. */
33846 #define ALT_USB_HOST_HCCHAR6_ODDFRM_CLR_MSK 0xdfffffff
33847 /* The reset value of the ALT_USB_HOST_HCCHAR6_ODDFRM register field. */
33848 #define ALT_USB_HOST_HCCHAR6_ODDFRM_RESET 0x0
33849 /* Extracts the ALT_USB_HOST_HCCHAR6_ODDFRM field value from a register. */
33850 #define ALT_USB_HOST_HCCHAR6_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
33851 /* Produces a ALT_USB_HOST_HCCHAR6_ODDFRM register field value suitable for setting the register. */
33852 #define ALT_USB_HOST_HCCHAR6_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
33853 
33854 /*
33855  * Field : chdis
33856  *
33857  * Channel Disable (ChDis)
33858  *
33859  * The application sets this bit to stop transmitting/receiving data
33860  *
33861  * on a channel, even before the transfer For that channel is
33862  *
33863  * complete. The application must wait For the Channel Disabled
33864  *
33865  * interrupt before treating the channel as disabled.
33866  *
33867  * Field Enumeration Values:
33868  *
33869  * Enum | Value | Description
33870  * :-----------------------------------|:------|:----------------------------
33871  * ALT_USB_HOST_HCCHAR6_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
33872  * ALT_USB_HOST_HCCHAR6_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
33873  *
33874  * Field Access Macros:
33875  *
33876  */
33877 /*
33878  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHDIS
33879  *
33880  * Transmit/Recieve normal
33881  */
33882 #define ALT_USB_HOST_HCCHAR6_CHDIS_E_INACT 0x0
33883 /*
33884  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHDIS
33885  *
33886  * Stop transmitting/receiving
33887  */
33888 #define ALT_USB_HOST_HCCHAR6_CHDIS_E_ACT 0x1
33889 
33890 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */
33891 #define ALT_USB_HOST_HCCHAR6_CHDIS_LSB 30
33892 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */
33893 #define ALT_USB_HOST_HCCHAR6_CHDIS_MSB 30
33894 /* The width in bits of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */
33895 #define ALT_USB_HOST_HCCHAR6_CHDIS_WIDTH 1
33896 /* The mask used to set the ALT_USB_HOST_HCCHAR6_CHDIS register field value. */
33897 #define ALT_USB_HOST_HCCHAR6_CHDIS_SET_MSK 0x40000000
33898 /* The mask used to clear the ALT_USB_HOST_HCCHAR6_CHDIS register field value. */
33899 #define ALT_USB_HOST_HCCHAR6_CHDIS_CLR_MSK 0xbfffffff
33900 /* The reset value of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */
33901 #define ALT_USB_HOST_HCCHAR6_CHDIS_RESET 0x0
33902 /* Extracts the ALT_USB_HOST_HCCHAR6_CHDIS field value from a register. */
33903 #define ALT_USB_HOST_HCCHAR6_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
33904 /* Produces a ALT_USB_HOST_HCCHAR6_CHDIS register field value suitable for setting the register. */
33905 #define ALT_USB_HOST_HCCHAR6_CHDIS_SET(value) (((value) << 30) & 0x40000000)
33906 
33907 /*
33908  * Field : chena
33909  *
33910  * Channel Enable (ChEna)
33911  *
33912  * When Scatter/Gather mode is enabled
33913  *
33914  * 1'b0: Indicates that the descriptor structure is not yet ready.
33915  *
33916  * 1'b1: Indicates that the descriptor structure and data buffer with
33917  *
33918  * data is setup and this channel can access the descriptor.
33919  *
33920  * When Scatter/Gather mode is disabled
33921  *
33922  * This field is set by the application and cleared by the OTG host.
33923  *
33924  * 1'b0: Channel disabled
33925  *
33926  * 1'b1: Channel enabled
33927  *
33928  * Field Enumeration Values:
33929  *
33930  * Enum | Value | Description
33931  * :-----------------------------------|:------|:-------------------------------------------------
33932  * ALT_USB_HOST_HCCHAR6_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
33933  * : | | yet ready
33934  * ALT_USB_HOST_HCCHAR6_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
33935  * : | | data buffer with data is setup and this
33936  * : | | channel can access the descriptor
33937  *
33938  * Field Access Macros:
33939  *
33940  */
33941 /*
33942  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHENA
33943  *
33944  * Indicates that the descriptor structure is not yet ready
33945  */
33946 #define ALT_USB_HOST_HCCHAR6_CHENA_E_INACT 0x0
33947 /*
33948  * Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHENA
33949  *
33950  * Indicates that the descriptor structure and data buffer with data is
33951  * setup and this channel can access the descriptor
33952  */
33953 #define ALT_USB_HOST_HCCHAR6_CHENA_E_ACT 0x1
33954 
33955 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_CHENA register field. */
33956 #define ALT_USB_HOST_HCCHAR6_CHENA_LSB 31
33957 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_CHENA register field. */
33958 #define ALT_USB_HOST_HCCHAR6_CHENA_MSB 31
33959 /* The width in bits of the ALT_USB_HOST_HCCHAR6_CHENA register field. */
33960 #define ALT_USB_HOST_HCCHAR6_CHENA_WIDTH 1
33961 /* The mask used to set the ALT_USB_HOST_HCCHAR6_CHENA register field value. */
33962 #define ALT_USB_HOST_HCCHAR6_CHENA_SET_MSK 0x80000000
33963 /* The mask used to clear the ALT_USB_HOST_HCCHAR6_CHENA register field value. */
33964 #define ALT_USB_HOST_HCCHAR6_CHENA_CLR_MSK 0x7fffffff
33965 /* The reset value of the ALT_USB_HOST_HCCHAR6_CHENA register field. */
33966 #define ALT_USB_HOST_HCCHAR6_CHENA_RESET 0x0
33967 /* Extracts the ALT_USB_HOST_HCCHAR6_CHENA field value from a register. */
33968 #define ALT_USB_HOST_HCCHAR6_CHENA_GET(value) (((value) & 0x80000000) >> 31)
33969 /* Produces a ALT_USB_HOST_HCCHAR6_CHENA register field value suitable for setting the register. */
33970 #define ALT_USB_HOST_HCCHAR6_CHENA_SET(value) (((value) << 31) & 0x80000000)
33971 
33972 #ifndef __ASSEMBLY__
33973 /*
33974  * WARNING: The C register and register group struct declarations are provided for
33975  * convenience and illustrative purposes. They should, however, be used with
33976  * caution as the C language standard provides no guarantees about the alignment or
33977  * atomicity of device memory accesses. The recommended practice for writing
33978  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33979  * alt_write_word() functions.
33980  *
33981  * The struct declaration for register ALT_USB_HOST_HCCHAR6.
33982  */
33983 struct ALT_USB_HOST_HCCHAR6_s
33984 {
33985  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR6_MPS */
33986  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR6_EPNUM */
33987  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR6_EPDIR */
33988  uint32_t : 1; /* *UNDEFINED* */
33989  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR6_LSPDDEV */
33990  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR6_EPTYPE */
33991  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR6_EC */
33992  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR6_DEVADDR */
33993  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR6_ODDFRM */
33994  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR6_CHDIS */
33995  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR6_CHENA */
33996 };
33997 
33998 /* The typedef declaration for register ALT_USB_HOST_HCCHAR6. */
33999 typedef volatile struct ALT_USB_HOST_HCCHAR6_s ALT_USB_HOST_HCCHAR6_t;
34000 #endif /* __ASSEMBLY__ */
34001 
34002 /* The reset value of the ALT_USB_HOST_HCCHAR6 register. */
34003 #define ALT_USB_HOST_HCCHAR6_RESET 0x00000000
34004 /* The byte offset of the ALT_USB_HOST_HCCHAR6 register from the beginning of the component. */
34005 #define ALT_USB_HOST_HCCHAR6_OFST 0x1c0
34006 /* The address of the ALT_USB_HOST_HCCHAR6 register. */
34007 #define ALT_USB_HOST_HCCHAR6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR6_OFST))
34008 
34009 /*
34010  * Register : hcsplt6
34011  *
34012  * Host Channel 6 Split Control Register
34013  *
34014  * Register Layout
34015  *
34016  * Bits | Access | Reset | Description
34017  * :--------|:-------|:------|:------------------------------
34018  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT6_PRTADDR
34019  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT6_HUBADDR
34020  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT6_XACTPOS
34021  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT6_COMPSPLT
34022  * [30:17] | ??? | 0x0 | *UNDEFINED*
34023  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT6_SPLTENA
34024  *
34025  */
34026 /*
34027  * Field : prtaddr
34028  *
34029  * Port Address (PrtAddr)
34030  *
34031  * This field is the port number of the recipient transaction
34032  *
34033  * translator.
34034  *
34035  * Field Access Macros:
34036  *
34037  */
34038 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */
34039 #define ALT_USB_HOST_HCSPLT6_PRTADDR_LSB 0
34040 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */
34041 #define ALT_USB_HOST_HCSPLT6_PRTADDR_MSB 6
34042 /* The width in bits of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */
34043 #define ALT_USB_HOST_HCSPLT6_PRTADDR_WIDTH 7
34044 /* The mask used to set the ALT_USB_HOST_HCSPLT6_PRTADDR register field value. */
34045 #define ALT_USB_HOST_HCSPLT6_PRTADDR_SET_MSK 0x0000007f
34046 /* The mask used to clear the ALT_USB_HOST_HCSPLT6_PRTADDR register field value. */
34047 #define ALT_USB_HOST_HCSPLT6_PRTADDR_CLR_MSK 0xffffff80
34048 /* The reset value of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */
34049 #define ALT_USB_HOST_HCSPLT6_PRTADDR_RESET 0x0
34050 /* Extracts the ALT_USB_HOST_HCSPLT6_PRTADDR field value from a register. */
34051 #define ALT_USB_HOST_HCSPLT6_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
34052 /* Produces a ALT_USB_HOST_HCSPLT6_PRTADDR register field value suitable for setting the register. */
34053 #define ALT_USB_HOST_HCSPLT6_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
34054 
34055 /*
34056  * Field : hubaddr
34057  *
34058  * Hub Address (HubAddr)
34059  *
34060  * This field holds the device address of the transaction translator's
34061  *
34062  * hub.
34063  *
34064  * Field Access Macros:
34065  *
34066  */
34067 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */
34068 #define ALT_USB_HOST_HCSPLT6_HUBADDR_LSB 7
34069 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */
34070 #define ALT_USB_HOST_HCSPLT6_HUBADDR_MSB 13
34071 /* The width in bits of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */
34072 #define ALT_USB_HOST_HCSPLT6_HUBADDR_WIDTH 7
34073 /* The mask used to set the ALT_USB_HOST_HCSPLT6_HUBADDR register field value. */
34074 #define ALT_USB_HOST_HCSPLT6_HUBADDR_SET_MSK 0x00003f80
34075 /* The mask used to clear the ALT_USB_HOST_HCSPLT6_HUBADDR register field value. */
34076 #define ALT_USB_HOST_HCSPLT6_HUBADDR_CLR_MSK 0xffffc07f
34077 /* The reset value of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */
34078 #define ALT_USB_HOST_HCSPLT6_HUBADDR_RESET 0x0
34079 /* Extracts the ALT_USB_HOST_HCSPLT6_HUBADDR field value from a register. */
34080 #define ALT_USB_HOST_HCSPLT6_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
34081 /* Produces a ALT_USB_HOST_HCSPLT6_HUBADDR register field value suitable for setting the register. */
34082 #define ALT_USB_HOST_HCSPLT6_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
34083 
34084 /*
34085  * Field : xactpos
34086  *
34087  * Transaction Position (XactPos)
34088  *
34089  * This field is used to determine whether to send all, first, middle,
34090  *
34091  * or last payloads with each OUT transaction.
34092  *
34093  * 2'b11: All. This is the entire data payload is of this transaction
34094  *
34095  * (which is less than or equal to 188 bytes).
34096  *
34097  * 2'b10: Begin. This is the first data payload of this transaction
34098  *
34099  * (which is larger than 188 bytes).
34100  *
34101  * 2'b00: Mid. This is the middle payload of this transaction
34102  *
34103  * (which is larger than 188 bytes).
34104  *
34105  * 2'b01: End. This is the last payload of this transaction (which
34106  *
34107  * is larger than 188 bytes).
34108  *
34109  * Field Enumeration Values:
34110  *
34111  * Enum | Value | Description
34112  * :--------------------------------------|:------|:------------------------------------------------
34113  * ALT_USB_HOST_HCSPLT6_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
34114  * : | | transaction (which is larger than 188 bytes)
34115  * ALT_USB_HOST_HCSPLT6_XACTPOS_E_END | 0x1 | End. This is the last payload of this
34116  * : | | transaction (which is larger than 188 bytes)
34117  * ALT_USB_HOST_HCSPLT6_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
34118  * : | | transaction (which is larger than 188 bytes)
34119  * ALT_USB_HOST_HCSPLT6_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
34120  * : | | transaction (which is less than or equal to 188
34121  * : | | bytes)
34122  *
34123  * Field Access Macros:
34124  *
34125  */
34126 /*
34127  * Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS
34128  *
34129  * Mid. This is the middle payload of this transaction (which is larger than 188
34130  * bytes)
34131  */
34132 #define ALT_USB_HOST_HCSPLT6_XACTPOS_E_MIDDLE 0x0
34133 /*
34134  * Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS
34135  *
34136  * End. This is the last payload of this transaction (which is larger than 188
34137  * bytes)
34138  */
34139 #define ALT_USB_HOST_HCSPLT6_XACTPOS_E_END 0x1
34140 /*
34141  * Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS
34142  *
34143  * Begin. This is the first data payload of this transaction (which is larger than
34144  * 188 bytes)
34145  */
34146 #define ALT_USB_HOST_HCSPLT6_XACTPOS_E_BEGIN 0x2
34147 /*
34148  * Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS
34149  *
34150  * All. This is the entire data payload is of this transaction (which is less than
34151  * or equal to 188 bytes)
34152  */
34153 #define ALT_USB_HOST_HCSPLT6_XACTPOS_E_ALL 0x3
34154 
34155 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */
34156 #define ALT_USB_HOST_HCSPLT6_XACTPOS_LSB 14
34157 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */
34158 #define ALT_USB_HOST_HCSPLT6_XACTPOS_MSB 15
34159 /* The width in bits of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */
34160 #define ALT_USB_HOST_HCSPLT6_XACTPOS_WIDTH 2
34161 /* The mask used to set the ALT_USB_HOST_HCSPLT6_XACTPOS register field value. */
34162 #define ALT_USB_HOST_HCSPLT6_XACTPOS_SET_MSK 0x0000c000
34163 /* The mask used to clear the ALT_USB_HOST_HCSPLT6_XACTPOS register field value. */
34164 #define ALT_USB_HOST_HCSPLT6_XACTPOS_CLR_MSK 0xffff3fff
34165 /* The reset value of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */
34166 #define ALT_USB_HOST_HCSPLT6_XACTPOS_RESET 0x0
34167 /* Extracts the ALT_USB_HOST_HCSPLT6_XACTPOS field value from a register. */
34168 #define ALT_USB_HOST_HCSPLT6_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
34169 /* Produces a ALT_USB_HOST_HCSPLT6_XACTPOS register field value suitable for setting the register. */
34170 #define ALT_USB_HOST_HCSPLT6_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
34171 
34172 /*
34173  * Field : compsplt
34174  *
34175  * Do Complete Split (CompSplt)
34176  *
34177  * The application sets this field to request the OTG host to perform
34178  *
34179  * a complete split transaction.
34180  *
34181  * Field Enumeration Values:
34182  *
34183  * Enum | Value | Description
34184  * :----------------------------------------|:------|:---------------------
34185  * ALT_USB_HOST_HCSPLT6_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
34186  * ALT_USB_HOST_HCSPLT6_COMPSPLT_E_SPLIT | 0x1 | Split transaction
34187  *
34188  * Field Access Macros:
34189  *
34190  */
34191 /*
34192  * Enumerated value for register field ALT_USB_HOST_HCSPLT6_COMPSPLT
34193  *
34194  * No split transaction
34195  */
34196 #define ALT_USB_HOST_HCSPLT6_COMPSPLT_E_NOSPLIT 0x0
34197 /*
34198  * Enumerated value for register field ALT_USB_HOST_HCSPLT6_COMPSPLT
34199  *
34200  * Split transaction
34201  */
34202 #define ALT_USB_HOST_HCSPLT6_COMPSPLT_E_SPLIT 0x1
34203 
34204 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */
34205 #define ALT_USB_HOST_HCSPLT6_COMPSPLT_LSB 16
34206 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */
34207 #define ALT_USB_HOST_HCSPLT6_COMPSPLT_MSB 16
34208 /* The width in bits of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */
34209 #define ALT_USB_HOST_HCSPLT6_COMPSPLT_WIDTH 1
34210 /* The mask used to set the ALT_USB_HOST_HCSPLT6_COMPSPLT register field value. */
34211 #define ALT_USB_HOST_HCSPLT6_COMPSPLT_SET_MSK 0x00010000
34212 /* The mask used to clear the ALT_USB_HOST_HCSPLT6_COMPSPLT register field value. */
34213 #define ALT_USB_HOST_HCSPLT6_COMPSPLT_CLR_MSK 0xfffeffff
34214 /* The reset value of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */
34215 #define ALT_USB_HOST_HCSPLT6_COMPSPLT_RESET 0x0
34216 /* Extracts the ALT_USB_HOST_HCSPLT6_COMPSPLT field value from a register. */
34217 #define ALT_USB_HOST_HCSPLT6_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
34218 /* Produces a ALT_USB_HOST_HCSPLT6_COMPSPLT register field value suitable for setting the register. */
34219 #define ALT_USB_HOST_HCSPLT6_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
34220 
34221 /*
34222  * Field : spltena
34223  *
34224  * Split Enable (SpltEna)
34225  *
34226  * The application sets this field to indicate that this channel is
34227  *
34228  * enabled to perform split transactions.
34229  *
34230  * Field Enumeration Values:
34231  *
34232  * Enum | Value | Description
34233  * :------------------------------------|:------|:------------------
34234  * ALT_USB_HOST_HCSPLT6_SPLTENA_E_DISD | 0x0 | Split not enabled
34235  * ALT_USB_HOST_HCSPLT6_SPLTENA_E_END | 0x1 | Split enabled
34236  *
34237  * Field Access Macros:
34238  *
34239  */
34240 /*
34241  * Enumerated value for register field ALT_USB_HOST_HCSPLT6_SPLTENA
34242  *
34243  * Split not enabled
34244  */
34245 #define ALT_USB_HOST_HCSPLT6_SPLTENA_E_DISD 0x0
34246 /*
34247  * Enumerated value for register field ALT_USB_HOST_HCSPLT6_SPLTENA
34248  *
34249  * Split enabled
34250  */
34251 #define ALT_USB_HOST_HCSPLT6_SPLTENA_E_END 0x1
34252 
34253 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */
34254 #define ALT_USB_HOST_HCSPLT6_SPLTENA_LSB 31
34255 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */
34256 #define ALT_USB_HOST_HCSPLT6_SPLTENA_MSB 31
34257 /* The width in bits of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */
34258 #define ALT_USB_HOST_HCSPLT6_SPLTENA_WIDTH 1
34259 /* The mask used to set the ALT_USB_HOST_HCSPLT6_SPLTENA register field value. */
34260 #define ALT_USB_HOST_HCSPLT6_SPLTENA_SET_MSK 0x80000000
34261 /* The mask used to clear the ALT_USB_HOST_HCSPLT6_SPLTENA register field value. */
34262 #define ALT_USB_HOST_HCSPLT6_SPLTENA_CLR_MSK 0x7fffffff
34263 /* The reset value of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */
34264 #define ALT_USB_HOST_HCSPLT6_SPLTENA_RESET 0x0
34265 /* Extracts the ALT_USB_HOST_HCSPLT6_SPLTENA field value from a register. */
34266 #define ALT_USB_HOST_HCSPLT6_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
34267 /* Produces a ALT_USB_HOST_HCSPLT6_SPLTENA register field value suitable for setting the register. */
34268 #define ALT_USB_HOST_HCSPLT6_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
34269 
34270 #ifndef __ASSEMBLY__
34271 /*
34272  * WARNING: The C register and register group struct declarations are provided for
34273  * convenience and illustrative purposes. They should, however, be used with
34274  * caution as the C language standard provides no guarantees about the alignment or
34275  * atomicity of device memory accesses. The recommended practice for writing
34276  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
34277  * alt_write_word() functions.
34278  *
34279  * The struct declaration for register ALT_USB_HOST_HCSPLT6.
34280  */
34281 struct ALT_USB_HOST_HCSPLT6_s
34282 {
34283  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT6_PRTADDR */
34284  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT6_HUBADDR */
34285  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT6_XACTPOS */
34286  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT6_COMPSPLT */
34287  uint32_t : 14; /* *UNDEFINED* */
34288  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT6_SPLTENA */
34289 };
34290 
34291 /* The typedef declaration for register ALT_USB_HOST_HCSPLT6. */
34292 typedef volatile struct ALT_USB_HOST_HCSPLT6_s ALT_USB_HOST_HCSPLT6_t;
34293 #endif /* __ASSEMBLY__ */
34294 
34295 /* The reset value of the ALT_USB_HOST_HCSPLT6 register. */
34296 #define ALT_USB_HOST_HCSPLT6_RESET 0x00000000
34297 /* The byte offset of the ALT_USB_HOST_HCSPLT6 register from the beginning of the component. */
34298 #define ALT_USB_HOST_HCSPLT6_OFST 0x1c4
34299 /* The address of the ALT_USB_HOST_HCSPLT6 register. */
34300 #define ALT_USB_HOST_HCSPLT6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT6_OFST))
34301 
34302 /*
34303  * Register : hcint6
34304  *
34305  * Host Channel 6 Interrupt Register
34306  *
34307  * Register Layout
34308  *
34309  * Bits | Access | Reset | Description
34310  * :--------|:-------|:------|:--------------------------------------
34311  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT6_XFERCOMPL
34312  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT6_CHHLTD
34313  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT6_AHBERR
34314  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT6_STALL
34315  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT6_NAK
34316  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT6_ACK
34317  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT6_NYET
34318  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT6_XACTERR
34319  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT6_BBLERR
34320  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT6_FRMOVRUN
34321  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT6_DATATGLERR
34322  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT6_BNAINTR
34323  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT6_XCS_XACT_ERR
34324  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR
34325  * [31:14] | ??? | 0x0 | *UNDEFINED*
34326  *
34327  */
34328 /*
34329  * Field : xfercompl
34330  *
34331  * Transfer Completed (XferCompl)
34332  *
34333  * Transfer completed normally without any errors.This bit can be set only by the
34334  * core and the application should write 1 to clear it.
34335  *
34336  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
34337  *
34338  * completed with IOC bit set in its descriptor.
34339  *
34340  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
34341  * without
34342  *
34343  * any errors.
34344  *
34345  * Field Enumeration Values:
34346  *
34347  * Enum | Value | Description
34348  * :--------------------------------------|:------|:-----------------------------------------------
34349  * ALT_USB_HOST_HCINT6_XFERCOMPL_E_INACT | 0x0 | No transfer
34350  * ALT_USB_HOST_HCINT6_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
34351  *
34352  * Field Access Macros:
34353  *
34354  */
34355 /*
34356  * Enumerated value for register field ALT_USB_HOST_HCINT6_XFERCOMPL
34357  *
34358  * No transfer
34359  */
34360 #define ALT_USB_HOST_HCINT6_XFERCOMPL_E_INACT 0x0
34361 /*
34362  * Enumerated value for register field ALT_USB_HOST_HCINT6_XFERCOMPL
34363  *
34364  * Transfer completed normally without any errors
34365  */
34366 #define ALT_USB_HOST_HCINT6_XFERCOMPL_E_ACT 0x1
34367 
34368 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */
34369 #define ALT_USB_HOST_HCINT6_XFERCOMPL_LSB 0
34370 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */
34371 #define ALT_USB_HOST_HCINT6_XFERCOMPL_MSB 0
34372 /* The width in bits of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */
34373 #define ALT_USB_HOST_HCINT6_XFERCOMPL_WIDTH 1
34374 /* The mask used to set the ALT_USB_HOST_HCINT6_XFERCOMPL register field value. */
34375 #define ALT_USB_HOST_HCINT6_XFERCOMPL_SET_MSK 0x00000001
34376 /* The mask used to clear the ALT_USB_HOST_HCINT6_XFERCOMPL register field value. */
34377 #define ALT_USB_HOST_HCINT6_XFERCOMPL_CLR_MSK 0xfffffffe
34378 /* The reset value of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */
34379 #define ALT_USB_HOST_HCINT6_XFERCOMPL_RESET 0x0
34380 /* Extracts the ALT_USB_HOST_HCINT6_XFERCOMPL field value from a register. */
34381 #define ALT_USB_HOST_HCINT6_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
34382 /* Produces a ALT_USB_HOST_HCINT6_XFERCOMPL register field value suitable for setting the register. */
34383 #define ALT_USB_HOST_HCINT6_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
34384 
34385 /*
34386  * Field : chhltd
34387  *
34388  * Channel Halted (ChHltd)
34389  *
34390  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
34391  * either because of any USB transaction error or in response to disable request by
34392  * the application or because of a completed transfer.
34393  *
34394  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
34395  * the following
34396  *
34397  * . EOL being set in descriptor
34398  *
34399  * . AHB error
34400  *
34401  * . Excessive transaction errors
34402  *
34403  * . Babble
34404  *
34405  * . Stall
34406  *
34407  * Field Enumeration Values:
34408  *
34409  * Enum | Value | Description
34410  * :-----------------------------------|:------|:-------------------
34411  * ALT_USB_HOST_HCINT6_CHHLTD_E_INACT | 0x0 | Channel not halted
34412  * ALT_USB_HOST_HCINT6_CHHLTD_E_ACT | 0x1 | Channel Halted
34413  *
34414  * Field Access Macros:
34415  *
34416  */
34417 /*
34418  * Enumerated value for register field ALT_USB_HOST_HCINT6_CHHLTD
34419  *
34420  * Channel not halted
34421  */
34422 #define ALT_USB_HOST_HCINT6_CHHLTD_E_INACT 0x0
34423 /*
34424  * Enumerated value for register field ALT_USB_HOST_HCINT6_CHHLTD
34425  *
34426  * Channel Halted
34427  */
34428 #define ALT_USB_HOST_HCINT6_CHHLTD_E_ACT 0x1
34429 
34430 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_CHHLTD register field. */
34431 #define ALT_USB_HOST_HCINT6_CHHLTD_LSB 1
34432 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_CHHLTD register field. */
34433 #define ALT_USB_HOST_HCINT6_CHHLTD_MSB 1
34434 /* The width in bits of the ALT_USB_HOST_HCINT6_CHHLTD register field. */
34435 #define ALT_USB_HOST_HCINT6_CHHLTD_WIDTH 1
34436 /* The mask used to set the ALT_USB_HOST_HCINT6_CHHLTD register field value. */
34437 #define ALT_USB_HOST_HCINT6_CHHLTD_SET_MSK 0x00000002
34438 /* The mask used to clear the ALT_USB_HOST_HCINT6_CHHLTD register field value. */
34439 #define ALT_USB_HOST_HCINT6_CHHLTD_CLR_MSK 0xfffffffd
34440 /* The reset value of the ALT_USB_HOST_HCINT6_CHHLTD register field. */
34441 #define ALT_USB_HOST_HCINT6_CHHLTD_RESET 0x0
34442 /* Extracts the ALT_USB_HOST_HCINT6_CHHLTD field value from a register. */
34443 #define ALT_USB_HOST_HCINT6_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
34444 /* Produces a ALT_USB_HOST_HCINT6_CHHLTD register field value suitable for setting the register. */
34445 #define ALT_USB_HOST_HCINT6_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
34446 
34447 /*
34448  * Field : ahberr
34449  *
34450  * AHB Error (AHBErr)
34451  *
34452  * This is generated only in Internal DMA mode when there is an
34453  *
34454  * AHB error during AHB read/write. The application can read the
34455  *
34456  * corresponding channel's DMA address register to get the error
34457  *
34458  * address.
34459  *
34460  * Field Enumeration Values:
34461  *
34462  * Enum | Value | Description
34463  * :-----------------------------------|:------|:--------------------------------
34464  * ALT_USB_HOST_HCINT6_AHBERR_E_INACT | 0x0 | No AHB error
34465  * ALT_USB_HOST_HCINT6_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
34466  *
34467  * Field Access Macros:
34468  *
34469  */
34470 /*
34471  * Enumerated value for register field ALT_USB_HOST_HCINT6_AHBERR
34472  *
34473  * No AHB error
34474  */
34475 #define ALT_USB_HOST_HCINT6_AHBERR_E_INACT 0x0
34476 /*
34477  * Enumerated value for register field ALT_USB_HOST_HCINT6_AHBERR
34478  *
34479  * AHB error during AHB read/write
34480  */
34481 #define ALT_USB_HOST_HCINT6_AHBERR_E_ACT 0x1
34482 
34483 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_AHBERR register field. */
34484 #define ALT_USB_HOST_HCINT6_AHBERR_LSB 2
34485 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_AHBERR register field. */
34486 #define ALT_USB_HOST_HCINT6_AHBERR_MSB 2
34487 /* The width in bits of the ALT_USB_HOST_HCINT6_AHBERR register field. */
34488 #define ALT_USB_HOST_HCINT6_AHBERR_WIDTH 1
34489 /* The mask used to set the ALT_USB_HOST_HCINT6_AHBERR register field value. */
34490 #define ALT_USB_HOST_HCINT6_AHBERR_SET_MSK 0x00000004
34491 /* The mask used to clear the ALT_USB_HOST_HCINT6_AHBERR register field value. */
34492 #define ALT_USB_HOST_HCINT6_AHBERR_CLR_MSK 0xfffffffb
34493 /* The reset value of the ALT_USB_HOST_HCINT6_AHBERR register field. */
34494 #define ALT_USB_HOST_HCINT6_AHBERR_RESET 0x0
34495 /* Extracts the ALT_USB_HOST_HCINT6_AHBERR field value from a register. */
34496 #define ALT_USB_HOST_HCINT6_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
34497 /* Produces a ALT_USB_HOST_HCINT6_AHBERR register field value suitable for setting the register. */
34498 #define ALT_USB_HOST_HCINT6_AHBERR_SET(value) (((value) << 2) & 0x00000004)
34499 
34500 /*
34501  * Field : stall
34502  *
34503  * STALL Response Received Interrupt (STALL)
34504  *
34505  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
34506  *
34507  * in the core.This bit can be set only by the core and the application should
34508  * write 1 to clear
34509  *
34510  * it.
34511  *
34512  * Field Enumeration Values:
34513  *
34514  * Enum | Value | Description
34515  * :----------------------------------|:------|:-------------------
34516  * ALT_USB_HOST_HCINT6_STALL_E_INACT | 0x0 | No Stall Interrupt
34517  * ALT_USB_HOST_HCINT6_STALL_E_ACT | 0x1 | Stall Interrupt
34518  *
34519  * Field Access Macros:
34520  *
34521  */
34522 /*
34523  * Enumerated value for register field ALT_USB_HOST_HCINT6_STALL
34524  *
34525  * No Stall Interrupt
34526  */
34527 #define ALT_USB_HOST_HCINT6_STALL_E_INACT 0x0
34528 /*
34529  * Enumerated value for register field ALT_USB_HOST_HCINT6_STALL
34530  *
34531  * Stall Interrupt
34532  */
34533 #define ALT_USB_HOST_HCINT6_STALL_E_ACT 0x1
34534 
34535 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_STALL register field. */
34536 #define ALT_USB_HOST_HCINT6_STALL_LSB 3
34537 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_STALL register field. */
34538 #define ALT_USB_HOST_HCINT6_STALL_MSB 3
34539 /* The width in bits of the ALT_USB_HOST_HCINT6_STALL register field. */
34540 #define ALT_USB_HOST_HCINT6_STALL_WIDTH 1
34541 /* The mask used to set the ALT_USB_HOST_HCINT6_STALL register field value. */
34542 #define ALT_USB_HOST_HCINT6_STALL_SET_MSK 0x00000008
34543 /* The mask used to clear the ALT_USB_HOST_HCINT6_STALL register field value. */
34544 #define ALT_USB_HOST_HCINT6_STALL_CLR_MSK 0xfffffff7
34545 /* The reset value of the ALT_USB_HOST_HCINT6_STALL register field. */
34546 #define ALT_USB_HOST_HCINT6_STALL_RESET 0x0
34547 /* Extracts the ALT_USB_HOST_HCINT6_STALL field value from a register. */
34548 #define ALT_USB_HOST_HCINT6_STALL_GET(value) (((value) & 0x00000008) >> 3)
34549 /* Produces a ALT_USB_HOST_HCINT6_STALL register field value suitable for setting the register. */
34550 #define ALT_USB_HOST_HCINT6_STALL_SET(value) (((value) << 3) & 0x00000008)
34551 
34552 /*
34553  * Field : nak
34554  *
34555  * NAK Response Received Interrupt (NAK)
34556  *
34557  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
34558  *
34559  * in the core.This bit can be set only by the core and the application should
34560  * write 1 to clear
34561  *
34562  * it.
34563  *
34564  * Field Enumeration Values:
34565  *
34566  * Enum | Value | Description
34567  * :--------------------------------|:------|:-----------------------------------
34568  * ALT_USB_HOST_HCINT6_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
34569  * ALT_USB_HOST_HCINT6_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
34570  *
34571  * Field Access Macros:
34572  *
34573  */
34574 /*
34575  * Enumerated value for register field ALT_USB_HOST_HCINT6_NAK
34576  *
34577  * No NAK Response Received Interrupt
34578  */
34579 #define ALT_USB_HOST_HCINT6_NAK_E_INACT 0x0
34580 /*
34581  * Enumerated value for register field ALT_USB_HOST_HCINT6_NAK
34582  *
34583  * NAK Response Received Interrupt
34584  */
34585 #define ALT_USB_HOST_HCINT6_NAK_E_ACT 0x1
34586 
34587 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_NAK register field. */
34588 #define ALT_USB_HOST_HCINT6_NAK_LSB 4
34589 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_NAK register field. */
34590 #define ALT_USB_HOST_HCINT6_NAK_MSB 4
34591 /* The width in bits of the ALT_USB_HOST_HCINT6_NAK register field. */
34592 #define ALT_USB_HOST_HCINT6_NAK_WIDTH 1
34593 /* The mask used to set the ALT_USB_HOST_HCINT6_NAK register field value. */
34594 #define ALT_USB_HOST_HCINT6_NAK_SET_MSK 0x00000010
34595 /* The mask used to clear the ALT_USB_HOST_HCINT6_NAK register field value. */
34596 #define ALT_USB_HOST_HCINT6_NAK_CLR_MSK 0xffffffef
34597 /* The reset value of the ALT_USB_HOST_HCINT6_NAK register field. */
34598 #define ALT_USB_HOST_HCINT6_NAK_RESET 0x0
34599 /* Extracts the ALT_USB_HOST_HCINT6_NAK field value from a register. */
34600 #define ALT_USB_HOST_HCINT6_NAK_GET(value) (((value) & 0x00000010) >> 4)
34601 /* Produces a ALT_USB_HOST_HCINT6_NAK register field value suitable for setting the register. */
34602 #define ALT_USB_HOST_HCINT6_NAK_SET(value) (((value) << 4) & 0x00000010)
34603 
34604 /*
34605  * Field : ack
34606  *
34607  * ACK Response Received/Transmitted Interrupt (ACK)
34608  *
34609  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
34610  *
34611  * in the core.This bit can be set only by the core and the application should
34612  * write 1 to clear
34613  *
34614  * it.
34615  *
34616  * Field Enumeration Values:
34617  *
34618  * Enum | Value | Description
34619  * :--------------------------------|:------|:-----------------------------------------------
34620  * ALT_USB_HOST_HCINT6_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
34621  * ALT_USB_HOST_HCINT6_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
34622  *
34623  * Field Access Macros:
34624  *
34625  */
34626 /*
34627  * Enumerated value for register field ALT_USB_HOST_HCINT6_ACK
34628  *
34629  * No ACK Response Received Transmitted Interrupt
34630  */
34631 #define ALT_USB_HOST_HCINT6_ACK_E_INACT 0x0
34632 /*
34633  * Enumerated value for register field ALT_USB_HOST_HCINT6_ACK
34634  *
34635  * ACK Response Received Transmitted Interrup
34636  */
34637 #define ALT_USB_HOST_HCINT6_ACK_E_ACT 0x1
34638 
34639 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_ACK register field. */
34640 #define ALT_USB_HOST_HCINT6_ACK_LSB 5
34641 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_ACK register field. */
34642 #define ALT_USB_HOST_HCINT6_ACK_MSB 5
34643 /* The width in bits of the ALT_USB_HOST_HCINT6_ACK register field. */
34644 #define ALT_USB_HOST_HCINT6_ACK_WIDTH 1
34645 /* The mask used to set the ALT_USB_HOST_HCINT6_ACK register field value. */
34646 #define ALT_USB_HOST_HCINT6_ACK_SET_MSK 0x00000020
34647 /* The mask used to clear the ALT_USB_HOST_HCINT6_ACK register field value. */
34648 #define ALT_USB_HOST_HCINT6_ACK_CLR_MSK 0xffffffdf
34649 /* The reset value of the ALT_USB_HOST_HCINT6_ACK register field. */
34650 #define ALT_USB_HOST_HCINT6_ACK_RESET 0x0
34651 /* Extracts the ALT_USB_HOST_HCINT6_ACK field value from a register. */
34652 #define ALT_USB_HOST_HCINT6_ACK_GET(value) (((value) & 0x00000020) >> 5)
34653 /* Produces a ALT_USB_HOST_HCINT6_ACK register field value suitable for setting the register. */
34654 #define ALT_USB_HOST_HCINT6_ACK_SET(value) (((value) << 5) & 0x00000020)
34655 
34656 /*
34657  * Field : nyet
34658  *
34659  * NYET Response Received Interrupt (NYET)
34660  *
34661  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
34662  *
34663  * in the core.This bit can be set only by the core and the application should
34664  * write 1 to clear
34665  *
34666  * it.
34667  *
34668  * Field Enumeration Values:
34669  *
34670  * Enum | Value | Description
34671  * :---------------------------------|:------|:------------------------------------
34672  * ALT_USB_HOST_HCINT6_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
34673  * ALT_USB_HOST_HCINT6_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
34674  *
34675  * Field Access Macros:
34676  *
34677  */
34678 /*
34679  * Enumerated value for register field ALT_USB_HOST_HCINT6_NYET
34680  *
34681  * No NYET Response Received Interrupt
34682  */
34683 #define ALT_USB_HOST_HCINT6_NYET_E_INACT 0x0
34684 /*
34685  * Enumerated value for register field ALT_USB_HOST_HCINT6_NYET
34686  *
34687  * NYET Response Received Interrupt
34688  */
34689 #define ALT_USB_HOST_HCINT6_NYET_E_ACT 0x1
34690 
34691 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_NYET register field. */
34692 #define ALT_USB_HOST_HCINT6_NYET_LSB 6
34693 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_NYET register field. */
34694 #define ALT_USB_HOST_HCINT6_NYET_MSB 6
34695 /* The width in bits of the ALT_USB_HOST_HCINT6_NYET register field. */
34696 #define ALT_USB_HOST_HCINT6_NYET_WIDTH 1
34697 /* The mask used to set the ALT_USB_HOST_HCINT6_NYET register field value. */
34698 #define ALT_USB_HOST_HCINT6_NYET_SET_MSK 0x00000040
34699 /* The mask used to clear the ALT_USB_HOST_HCINT6_NYET register field value. */
34700 #define ALT_USB_HOST_HCINT6_NYET_CLR_MSK 0xffffffbf
34701 /* The reset value of the ALT_USB_HOST_HCINT6_NYET register field. */
34702 #define ALT_USB_HOST_HCINT6_NYET_RESET 0x0
34703 /* Extracts the ALT_USB_HOST_HCINT6_NYET field value from a register. */
34704 #define ALT_USB_HOST_HCINT6_NYET_GET(value) (((value) & 0x00000040) >> 6)
34705 /* Produces a ALT_USB_HOST_HCINT6_NYET register field value suitable for setting the register. */
34706 #define ALT_USB_HOST_HCINT6_NYET_SET(value) (((value) << 6) & 0x00000040)
34707 
34708 /*
34709  * Field : xacterr
34710  *
34711  * Transaction Error (XactErr)
34712  *
34713  * Indicates one of the following errors occurred on the USB.
34714  *
34715  * CRC check failure
34716  *
34717  * Timeout
34718  *
34719  * Bit stuff error
34720  *
34721  * False EOP
34722  *
34723  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
34724  *
34725  * in the core.This bit can be set only by the core and the application should
34726  * write 1 to clear
34727  *
34728  * it.
34729  *
34730  * Field Enumeration Values:
34731  *
34732  * Enum | Value | Description
34733  * :------------------------------------|:------|:---------------------
34734  * ALT_USB_HOST_HCINT6_XACTERR_E_INACT | 0x0 | No Transaction Error
34735  * ALT_USB_HOST_HCINT6_XACTERR_E_ACT | 0x1 | Transaction Error
34736  *
34737  * Field Access Macros:
34738  *
34739  */
34740 /*
34741  * Enumerated value for register field ALT_USB_HOST_HCINT6_XACTERR
34742  *
34743  * No Transaction Error
34744  */
34745 #define ALT_USB_HOST_HCINT6_XACTERR_E_INACT 0x0
34746 /*
34747  * Enumerated value for register field ALT_USB_HOST_HCINT6_XACTERR
34748  *
34749  * Transaction Error
34750  */
34751 #define ALT_USB_HOST_HCINT6_XACTERR_E_ACT 0x1
34752 
34753 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_XACTERR register field. */
34754 #define ALT_USB_HOST_HCINT6_XACTERR_LSB 7
34755 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_XACTERR register field. */
34756 #define ALT_USB_HOST_HCINT6_XACTERR_MSB 7
34757 /* The width in bits of the ALT_USB_HOST_HCINT6_XACTERR register field. */
34758 #define ALT_USB_HOST_HCINT6_XACTERR_WIDTH 1
34759 /* The mask used to set the ALT_USB_HOST_HCINT6_XACTERR register field value. */
34760 #define ALT_USB_HOST_HCINT6_XACTERR_SET_MSK 0x00000080
34761 /* The mask used to clear the ALT_USB_HOST_HCINT6_XACTERR register field value. */
34762 #define ALT_USB_HOST_HCINT6_XACTERR_CLR_MSK 0xffffff7f
34763 /* The reset value of the ALT_USB_HOST_HCINT6_XACTERR register field. */
34764 #define ALT_USB_HOST_HCINT6_XACTERR_RESET 0x0
34765 /* Extracts the ALT_USB_HOST_HCINT6_XACTERR field value from a register. */
34766 #define ALT_USB_HOST_HCINT6_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
34767 /* Produces a ALT_USB_HOST_HCINT6_XACTERR register field value suitable for setting the register. */
34768 #define ALT_USB_HOST_HCINT6_XACTERR_SET(value) (((value) << 7) & 0x00000080)
34769 
34770 /*
34771  * Field : bblerr
34772  *
34773  * Babble Error (BblErr)
34774  *
34775  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
34776  *
34777  * in the core..This bit can be set only by the core and the application should
34778  * write 1 to clear
34779  *
34780  * it.
34781  *
34782  * Field Enumeration Values:
34783  *
34784  * Enum | Value | Description
34785  * :-----------------------------------|:------|:----------------
34786  * ALT_USB_HOST_HCINT6_BBLERR_E_INACT | 0x0 | No Babble Error
34787  * ALT_USB_HOST_HCINT6_BBLERR_E_ACT | 0x1 | Babble Error
34788  *
34789  * Field Access Macros:
34790  *
34791  */
34792 /*
34793  * Enumerated value for register field ALT_USB_HOST_HCINT6_BBLERR
34794  *
34795  * No Babble Error
34796  */
34797 #define ALT_USB_HOST_HCINT6_BBLERR_E_INACT 0x0
34798 /*
34799  * Enumerated value for register field ALT_USB_HOST_HCINT6_BBLERR
34800  *
34801  * Babble Error
34802  */
34803 #define ALT_USB_HOST_HCINT6_BBLERR_E_ACT 0x1
34804 
34805 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_BBLERR register field. */
34806 #define ALT_USB_HOST_HCINT6_BBLERR_LSB 8
34807 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_BBLERR register field. */
34808 #define ALT_USB_HOST_HCINT6_BBLERR_MSB 8
34809 /* The width in bits of the ALT_USB_HOST_HCINT6_BBLERR register field. */
34810 #define ALT_USB_HOST_HCINT6_BBLERR_WIDTH 1
34811 /* The mask used to set the ALT_USB_HOST_HCINT6_BBLERR register field value. */
34812 #define ALT_USB_HOST_HCINT6_BBLERR_SET_MSK 0x00000100
34813 /* The mask used to clear the ALT_USB_HOST_HCINT6_BBLERR register field value. */
34814 #define ALT_USB_HOST_HCINT6_BBLERR_CLR_MSK 0xfffffeff
34815 /* The reset value of the ALT_USB_HOST_HCINT6_BBLERR register field. */
34816 #define ALT_USB_HOST_HCINT6_BBLERR_RESET 0x0
34817 /* Extracts the ALT_USB_HOST_HCINT6_BBLERR field value from a register. */
34818 #define ALT_USB_HOST_HCINT6_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
34819 /* Produces a ALT_USB_HOST_HCINT6_BBLERR register field value suitable for setting the register. */
34820 #define ALT_USB_HOST_HCINT6_BBLERR_SET(value) (((value) << 8) & 0x00000100)
34821 
34822 /*
34823  * Field : frmovrun
34824  *
34825  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
34826  * bit is masked
34827  *
34828  * in the core.This bit can be set only by the core and the application should
34829  * write 1 to clear
34830  *
34831  * it.
34832  *
34833  * Field Enumeration Values:
34834  *
34835  * Enum | Value | Description
34836  * :-------------------------------------|:------|:-----------------
34837  * ALT_USB_HOST_HCINT6_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
34838  * ALT_USB_HOST_HCINT6_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
34839  *
34840  * Field Access Macros:
34841  *
34842  */
34843 /*
34844  * Enumerated value for register field ALT_USB_HOST_HCINT6_FRMOVRUN
34845  *
34846  * No Frame Overrun
34847  */
34848 #define ALT_USB_HOST_HCINT6_FRMOVRUN_E_INACT 0x0
34849 /*
34850  * Enumerated value for register field ALT_USB_HOST_HCINT6_FRMOVRUN
34851  *
34852  * Frame Overrun
34853  */
34854 #define ALT_USB_HOST_HCINT6_FRMOVRUN_E_ACT 0x1
34855 
34856 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */
34857 #define ALT_USB_HOST_HCINT6_FRMOVRUN_LSB 9
34858 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */
34859 #define ALT_USB_HOST_HCINT6_FRMOVRUN_MSB 9
34860 /* The width in bits of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */
34861 #define ALT_USB_HOST_HCINT6_FRMOVRUN_WIDTH 1
34862 /* The mask used to set the ALT_USB_HOST_HCINT6_FRMOVRUN register field value. */
34863 #define ALT_USB_HOST_HCINT6_FRMOVRUN_SET_MSK 0x00000200
34864 /* The mask used to clear the ALT_USB_HOST_HCINT6_FRMOVRUN register field value. */
34865 #define ALT_USB_HOST_HCINT6_FRMOVRUN_CLR_MSK 0xfffffdff
34866 /* The reset value of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */
34867 #define ALT_USB_HOST_HCINT6_FRMOVRUN_RESET 0x0
34868 /* Extracts the ALT_USB_HOST_HCINT6_FRMOVRUN field value from a register. */
34869 #define ALT_USB_HOST_HCINT6_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
34870 /* Produces a ALT_USB_HOST_HCINT6_FRMOVRUN register field value suitable for setting the register. */
34871 #define ALT_USB_HOST_HCINT6_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
34872 
34873 /*
34874  * Field : datatglerr
34875  *
34876  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
34877  * application should write 1 to clear
34878  *
34879  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
34880  *
34881  * in the core.
34882  *
34883  * Field Enumeration Values:
34884  *
34885  * Enum | Value | Description
34886  * :---------------------------------------|:------|:---------------------
34887  * ALT_USB_HOST_HCINT6_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
34888  * ALT_USB_HOST_HCINT6_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
34889  *
34890  * Field Access Macros:
34891  *
34892  */
34893 /*
34894  * Enumerated value for register field ALT_USB_HOST_HCINT6_DATATGLERR
34895  *
34896  * No Data Toggle Error
34897  */
34898 #define ALT_USB_HOST_HCINT6_DATATGLERR_E_INACT 0x0
34899 /*
34900  * Enumerated value for register field ALT_USB_HOST_HCINT6_DATATGLERR
34901  *
34902  * Data Toggle Error
34903  */
34904 #define ALT_USB_HOST_HCINT6_DATATGLERR_E_ACT 0x1
34905 
34906 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */
34907 #define ALT_USB_HOST_HCINT6_DATATGLERR_LSB 10
34908 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */
34909 #define ALT_USB_HOST_HCINT6_DATATGLERR_MSB 10
34910 /* The width in bits of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */
34911 #define ALT_USB_HOST_HCINT6_DATATGLERR_WIDTH 1
34912 /* The mask used to set the ALT_USB_HOST_HCINT6_DATATGLERR register field value. */
34913 #define ALT_USB_HOST_HCINT6_DATATGLERR_SET_MSK 0x00000400
34914 /* The mask used to clear the ALT_USB_HOST_HCINT6_DATATGLERR register field value. */
34915 #define ALT_USB_HOST_HCINT6_DATATGLERR_CLR_MSK 0xfffffbff
34916 /* The reset value of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */
34917 #define ALT_USB_HOST_HCINT6_DATATGLERR_RESET 0x0
34918 /* Extracts the ALT_USB_HOST_HCINT6_DATATGLERR field value from a register. */
34919 #define ALT_USB_HOST_HCINT6_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
34920 /* Produces a ALT_USB_HOST_HCINT6_DATATGLERR register field value suitable for setting the register. */
34921 #define ALT_USB_HOST_HCINT6_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
34922 
34923 /*
34924  * Field : bnaintr
34925  *
34926  * BNA (Buffer Not Available) Interrupt (BNAIntr)
34927  *
34928  * This bit is valid only when Scatter/Gather DMA mode is enabled.
34929  *
34930  * The core generates this interrupt when the descriptor accessed
34931  *
34932  * is not ready for the Core to process. BNA will not be generated
34933  *
34934  * for Isochronous channels.
34935  *
34936  * For non Scatter/Gather DMA mode, this bit is reserved.
34937  *
34938  * Field Enumeration Values:
34939  *
34940  * Enum | Value | Description
34941  * :------------------------------------|:------|:-----------------
34942  * ALT_USB_HOST_HCINT6_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
34943  * ALT_USB_HOST_HCINT6_BNAINTR_E_ACT | 0x1 | BNA Interrupt
34944  *
34945  * Field Access Macros:
34946  *
34947  */
34948 /*
34949  * Enumerated value for register field ALT_USB_HOST_HCINT6_BNAINTR
34950  *
34951  * No BNA Interrupt
34952  */
34953 #define ALT_USB_HOST_HCINT6_BNAINTR_E_INACT 0x0
34954 /*
34955  * Enumerated value for register field ALT_USB_HOST_HCINT6_BNAINTR
34956  *
34957  * BNA Interrupt
34958  */
34959 #define ALT_USB_HOST_HCINT6_BNAINTR_E_ACT 0x1
34960 
34961 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_BNAINTR register field. */
34962 #define ALT_USB_HOST_HCINT6_BNAINTR_LSB 11
34963 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_BNAINTR register field. */
34964 #define ALT_USB_HOST_HCINT6_BNAINTR_MSB 11
34965 /* The width in bits of the ALT_USB_HOST_HCINT6_BNAINTR register field. */
34966 #define ALT_USB_HOST_HCINT6_BNAINTR_WIDTH 1
34967 /* The mask used to set the ALT_USB_HOST_HCINT6_BNAINTR register field value. */
34968 #define ALT_USB_HOST_HCINT6_BNAINTR_SET_MSK 0x00000800
34969 /* The mask used to clear the ALT_USB_HOST_HCINT6_BNAINTR register field value. */
34970 #define ALT_USB_HOST_HCINT6_BNAINTR_CLR_MSK 0xfffff7ff
34971 /* The reset value of the ALT_USB_HOST_HCINT6_BNAINTR register field. */
34972 #define ALT_USB_HOST_HCINT6_BNAINTR_RESET 0x0
34973 /* Extracts the ALT_USB_HOST_HCINT6_BNAINTR field value from a register. */
34974 #define ALT_USB_HOST_HCINT6_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
34975 /* Produces a ALT_USB_HOST_HCINT6_BNAINTR register field value suitable for setting the register. */
34976 #define ALT_USB_HOST_HCINT6_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
34977 
34978 /*
34979  * Field : xcs_xact_err
34980  *
34981  * Excessive Transaction Error (XCS_XACT_ERR)
34982  *
34983  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
34984  * this bit
34985  *
34986  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
34987  *
34988  * not be generated for Isochronous channels.
34989  *
34990  * For non Scatter/Gather DMA mode, this bit is reserved.
34991  *
34992  * Field Enumeration Values:
34993  *
34994  * Enum | Value | Description
34995  * :-------------------------------------------|:------|:-------------------------------
34996  * ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
34997  * ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
34998  *
34999  * Field Access Macros:
35000  *
35001  */
35002 /*
35003  * Enumerated value for register field ALT_USB_HOST_HCINT6_XCS_XACT_ERR
35004  *
35005  * No Excessive Transaction Error
35006  */
35007 #define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_INACT 0x0
35008 /*
35009  * Enumerated value for register field ALT_USB_HOST_HCINT6_XCS_XACT_ERR
35010  *
35011  * Excessive Transaction Error
35012  */
35013 #define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_ACVTIVE 0x1
35014 
35015 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */
35016 #define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_LSB 12
35017 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */
35018 #define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_MSB 12
35019 /* The width in bits of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */
35020 #define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_WIDTH 1
35021 /* The mask used to set the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field value. */
35022 #define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_SET_MSK 0x00001000
35023 /* The mask used to clear the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field value. */
35024 #define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_CLR_MSK 0xffffefff
35025 /* The reset value of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */
35026 #define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_RESET 0x0
35027 /* Extracts the ALT_USB_HOST_HCINT6_XCS_XACT_ERR field value from a register. */
35028 #define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
35029 /* Produces a ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field value suitable for setting the register. */
35030 #define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
35031 
35032 /*
35033  * Field : desc_lst_rollintr
35034  *
35035  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
35036  *
35037  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
35038  * this bit
35039  *
35040  * when the corresponding channel's descriptor list rolls over.
35041  *
35042  * For non Scatter/Gather DMA mode, this bit is reserved.
35043  *
35044  * Field Enumeration Values:
35045  *
35046  * Enum | Value | Description
35047  * :----------------------------------------------|:------|:---------------------------------
35048  * ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
35049  * ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
35050  *
35051  * Field Access Macros:
35052  *
35053  */
35054 /*
35055  * Enumerated value for register field ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR
35056  *
35057  * No Descriptor rollover interrupt
35058  */
35059 #define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_INACT 0x0
35060 /*
35061  * Enumerated value for register field ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR
35062  *
35063  * Descriptor rollover interrupt
35064  */
35065 #define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_ACT 0x1
35066 
35067 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */
35068 #define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_LSB 13
35069 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */
35070 #define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_MSB 13
35071 /* The width in bits of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */
35072 #define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_WIDTH 1
35073 /* The mask used to set the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field value. */
35074 #define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_SET_MSK 0x00002000
35075 /* The mask used to clear the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field value. */
35076 #define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
35077 /* The reset value of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */
35078 #define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_RESET 0x0
35079 /* Extracts the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR field value from a register. */
35080 #define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
35081 /* Produces a ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field value suitable for setting the register. */
35082 #define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
35083 
35084 #ifndef __ASSEMBLY__
35085 /*
35086  * WARNING: The C register and register group struct declarations are provided for
35087  * convenience and illustrative purposes. They should, however, be used with
35088  * caution as the C language standard provides no guarantees about the alignment or
35089  * atomicity of device memory accesses. The recommended practice for writing
35090  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35091  * alt_write_word() functions.
35092  *
35093  * The struct declaration for register ALT_USB_HOST_HCINT6.
35094  */
35095 struct ALT_USB_HOST_HCINT6_s
35096 {
35097  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT6_XFERCOMPL */
35098  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT6_CHHLTD */
35099  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT6_AHBERR */
35100  uint32_t stall : 1; /* ALT_USB_HOST_HCINT6_STALL */
35101  uint32_t nak : 1; /* ALT_USB_HOST_HCINT6_NAK */
35102  uint32_t ack : 1; /* ALT_USB_HOST_HCINT6_ACK */
35103  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT6_NYET */
35104  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT6_XACTERR */
35105  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT6_BBLERR */
35106  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT6_FRMOVRUN */
35107  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT6_DATATGLERR */
35108  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT6_BNAINTR */
35109  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT6_XCS_XACT_ERR */
35110  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR */
35111  uint32_t : 18; /* *UNDEFINED* */
35112 };
35113 
35114 /* The typedef declaration for register ALT_USB_HOST_HCINT6. */
35115 typedef volatile struct ALT_USB_HOST_HCINT6_s ALT_USB_HOST_HCINT6_t;
35116 #endif /* __ASSEMBLY__ */
35117 
35118 /* The reset value of the ALT_USB_HOST_HCINT6 register. */
35119 #define ALT_USB_HOST_HCINT6_RESET 0x00000000
35120 /* The byte offset of the ALT_USB_HOST_HCINT6 register from the beginning of the component. */
35121 #define ALT_USB_HOST_HCINT6_OFST 0x1c8
35122 /* The address of the ALT_USB_HOST_HCINT6 register. */
35123 #define ALT_USB_HOST_HCINT6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT6_OFST))
35124 
35125 /*
35126  * Register : hcintmsk6
35127  *
35128  * Host Channel 6 Interrupt Mask Register
35129  *
35130  * Register Layout
35131  *
35132  * Bits | Access | Reset | Description
35133  * :--------|:-------|:------|:-------------------------------------------
35134  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK
35135  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_CHHLTDMSK
35136  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_AHBERRMSK
35137  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_STALLMSK
35138  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_NAKMSK
35139  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_ACKMSK
35140  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_NYETMSK
35141  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_XACTERRMSK
35142  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_BBLERRMSK
35143  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK
35144  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK
35145  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_BNAINTRMSK
35146  * [12] | ??? | 0x0 | *UNDEFINED*
35147  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK
35148  * [31:14] | ??? | 0x0 | *UNDEFINED*
35149  *
35150  */
35151 /*
35152  * Field : xfercomplmsk
35153  *
35154  * Transfer Completed Mask (XferComplMsk)
35155  *
35156  * Field Enumeration Values:
35157  *
35158  * Enum | Value | Description
35159  * :--------------------------------------------|:------|:------------
35160  * ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_MSK | 0x0 | Mask
35161  * ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
35162  *
35163  * Field Access Macros:
35164  *
35165  */
35166 /*
35167  * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK
35168  *
35169  * Mask
35170  */
35171 #define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_MSK 0x0
35172 /*
35173  * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK
35174  *
35175  * No mask
35176  */
35177 #define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_NOMSK 0x1
35178 
35179 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */
35180 #define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_LSB 0
35181 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */
35182 #define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_MSB 0
35183 /* The width in bits of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */
35184 #define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_WIDTH 1
35185 /* The mask used to set the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field value. */
35186 #define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_SET_MSK 0x00000001
35187 /* The mask used to clear the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field value. */
35188 #define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_CLR_MSK 0xfffffffe
35189 /* The reset value of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */
35190 #define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_RESET 0x0
35191 /* Extracts the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK field value from a register. */
35192 #define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
35193 /* Produces a ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field value suitable for setting the register. */
35194 #define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
35195 
35196 /*
35197  * Field : chhltdmsk
35198  *
35199  * Channel Halted Mask (ChHltdMsk)
35200  *
35201  * Field Enumeration Values:
35202  *
35203  * Enum | Value | Description
35204  * :-----------------------------------------|:------|:------------
35205  * ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_MSK | 0x0 | Mask
35206  * ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_NOMSK | 0x1 | No mask
35207  *
35208  * Field Access Macros:
35209  *
35210  */
35211 /*
35212  * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_CHHLTDMSK
35213  *
35214  * Mask
35215  */
35216 #define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_MSK 0x0
35217 /*
35218  * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_CHHLTDMSK
35219  *
35220  * No mask
35221  */
35222 #define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_NOMSK 0x1
35223 
35224 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */
35225 #define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_LSB 1
35226 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */
35227 #define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_MSB 1
35228 /* The width in bits of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */
35229 #define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_WIDTH 1
35230 /* The mask used to set the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field value. */
35231 #define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_SET_MSK 0x00000002
35232 /* The mask used to clear the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field value. */
35233 #define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_CLR_MSK 0xfffffffd
35234 /* The reset value of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */
35235 #define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_RESET 0x0
35236 /* Extracts the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK field value from a register. */
35237 #define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
35238 /* Produces a ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field value suitable for setting the register. */
35239 #define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
35240 
35241 /*
35242  * Field : ahberrmsk
35243  *
35244  * AHB Error Mask (AHBErrMsk)
35245  *
35246  * In scatter/gather DMA mode for host,
35247  *
35248  * interrupts will not be generated due to the corresponding bits set in
35249  *
35250  * HCINTn.
35251  *
35252  * Field Enumeration Values:
35253  *
35254  * Enum | Value | Description
35255  * :-----------------------------------------|:------|:------------
35256  * ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_MSK | 0x0 | Mask
35257  * ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_NOMSK | 0x1 | No mask
35258  *
35259  * Field Access Macros:
35260  *
35261  */
35262 /*
35263  * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_AHBERRMSK
35264  *
35265  * Mask
35266  */
35267 #define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_MSK 0x0
35268 /*
35269  * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_AHBERRMSK
35270  *
35271  * No mask
35272  */
35273 #define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_NOMSK 0x1
35274 
35275 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */
35276 #define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_LSB 2
35277 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */
35278 #define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_MSB 2
35279 /* The width in bits of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */
35280 #define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_WIDTH 1
35281 /* The mask used to set the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field value. */
35282 #define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_SET_MSK 0x00000004
35283 /* The mask used to clear the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field value. */
35284 #define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_CLR_MSK 0xfffffffb
35285 /* The reset value of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */
35286 #define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_RESET 0x0
35287 /* Extracts the ALT_USB_HOST_HCINTMSK6_AHBERRMSK field value from a register. */
35288 #define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
35289 /* Produces a ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field value suitable for setting the register. */
35290 #define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
35291 
35292 /*
35293  * Field : stallmsk
35294  *
35295  * STALL Response Received Interrupt Mask (StallMsk)
35296  *
35297  * In scatter/gather DMA mode for host,
35298  *
35299  * interrupts will not be generated due to the corresponding bits set in
35300  *
35301  * HCINTn.
35302  *
35303  * Field Access Macros:
35304  *
35305  */
35306 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_STALLMSK register field. */
35307 #define ALT_USB_HOST_HCINTMSK6_STALLMSK_LSB 3
35308 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_STALLMSK register field. */
35309 #define ALT_USB_HOST_HCINTMSK6_STALLMSK_MSB 3
35310 /* The width in bits of the ALT_USB_HOST_HCINTMSK6_STALLMSK register field. */
35311 #define ALT_USB_HOST_HCINTMSK6_STALLMSK_WIDTH 1
35312 /* The mask used to set the ALT_USB_HOST_HCINTMSK6_STALLMSK register field value. */
35313 #define ALT_USB_HOST_HCINTMSK6_STALLMSK_SET_MSK 0x00000008
35314 /* The mask used to clear the ALT_USB_HOST_HCINTMSK6_STALLMSK register field value. */
35315 #define ALT_USB_HOST_HCINTMSK6_STALLMSK_CLR_MSK 0xfffffff7
35316 /* The reset value of the ALT_USB_HOST_HCINTMSK6_STALLMSK register field. */
35317 #define ALT_USB_HOST_HCINTMSK6_STALLMSK_RESET 0x0
35318 /* Extracts the ALT_USB_HOST_HCINTMSK6_STALLMSK field value from a register. */
35319 #define ALT_USB_HOST_HCINTMSK6_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
35320 /* Produces a ALT_USB_HOST_HCINTMSK6_STALLMSK register field value suitable for setting the register. */
35321 #define ALT_USB_HOST_HCINTMSK6_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
35322 
35323 /*
35324  * Field : nakmsk
35325  *
35326  * NAK Response Received Interrupt Mask (NakMsk)
35327  *
35328  * In scatter/gather DMA mode for host,
35329  *
35330  * interrupts will not be generated due to the corresponding bits set in
35331  *
35332  * HCINTn.
35333  *
35334  * Field Access Macros:
35335  *
35336  */
35337 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_NAKMSK register field. */
35338 #define ALT_USB_HOST_HCINTMSK6_NAKMSK_LSB 4
35339 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_NAKMSK register field. */
35340 #define ALT_USB_HOST_HCINTMSK6_NAKMSK_MSB 4
35341 /* The width in bits of the ALT_USB_HOST_HCINTMSK6_NAKMSK register field. */
35342 #define ALT_USB_HOST_HCINTMSK6_NAKMSK_WIDTH 1
35343 /* The mask used to set the ALT_USB_HOST_HCINTMSK6_NAKMSK register field value. */
35344 #define ALT_USB_HOST_HCINTMSK6_NAKMSK_SET_MSK 0x00000010
35345 /* The mask used to clear the ALT_USB_HOST_HCINTMSK6_NAKMSK register field value. */
35346 #define ALT_USB_HOST_HCINTMSK6_NAKMSK_CLR_MSK 0xffffffef
35347 /* The reset value of the ALT_USB_HOST_HCINTMSK6_NAKMSK register field. */
35348 #define ALT_USB_HOST_HCINTMSK6_NAKMSK_RESET 0x0
35349 /* Extracts the ALT_USB_HOST_HCINTMSK6_NAKMSK field value from a register. */
35350 #define ALT_USB_HOST_HCINTMSK6_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
35351 /* Produces a ALT_USB_HOST_HCINTMSK6_NAKMSK register field value suitable for setting the register. */
35352 #define ALT_USB_HOST_HCINTMSK6_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
35353 
35354 /*
35355  * Field : ackmsk
35356  *
35357  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
35358  *
35359  * In scatter/gather DMA mode for host,
35360  *
35361  * interrupts will not be generated due to the corresponding bits set in
35362  *
35363  * HCINTn.
35364  *
35365  * Field Access Macros:
35366  *
35367  */
35368 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_ACKMSK register field. */
35369 #define ALT_USB_HOST_HCINTMSK6_ACKMSK_LSB 5
35370 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_ACKMSK register field. */
35371 #define ALT_USB_HOST_HCINTMSK6_ACKMSK_MSB 5
35372 /* The width in bits of the ALT_USB_HOST_HCINTMSK6_ACKMSK register field. */
35373 #define ALT_USB_HOST_HCINTMSK6_ACKMSK_WIDTH 1
35374 /* The mask used to set the ALT_USB_HOST_HCINTMSK6_ACKMSK register field value. */
35375 #define ALT_USB_HOST_HCINTMSK6_ACKMSK_SET_MSK 0x00000020
35376 /* The mask used to clear the ALT_USB_HOST_HCINTMSK6_ACKMSK register field value. */
35377 #define ALT_USB_HOST_HCINTMSK6_ACKMSK_CLR_MSK 0xffffffdf
35378 /* The reset value of the ALT_USB_HOST_HCINTMSK6_ACKMSK register field. */
35379 #define ALT_USB_HOST_HCINTMSK6_ACKMSK_RESET 0x0
35380 /* Extracts the ALT_USB_HOST_HCINTMSK6_ACKMSK field value from a register. */
35381 #define ALT_USB_HOST_HCINTMSK6_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
35382 /* Produces a ALT_USB_HOST_HCINTMSK6_ACKMSK register field value suitable for setting the register. */
35383 #define ALT_USB_HOST_HCINTMSK6_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
35384 
35385 /*
35386  * Field : nyetmsk
35387  *
35388  * NYET Response Received Interrupt Mask (NyetMsk)
35389  *
35390  * In scatter/gather DMA mode for host,
35391  *
35392  * interrupts will not be generated due to the corresponding bits set in
35393  *
35394  * HCINTn.
35395  *
35396  * Field Access Macros:
35397  *
35398  */
35399 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_NYETMSK register field. */
35400 #define ALT_USB_HOST_HCINTMSK6_NYETMSK_LSB 6
35401 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_NYETMSK register field. */
35402 #define ALT_USB_HOST_HCINTMSK6_NYETMSK_MSB 6
35403 /* The width in bits of the ALT_USB_HOST_HCINTMSK6_NYETMSK register field. */
35404 #define ALT_USB_HOST_HCINTMSK6_NYETMSK_WIDTH 1
35405 /* The mask used to set the ALT_USB_HOST_HCINTMSK6_NYETMSK register field value. */
35406 #define ALT_USB_HOST_HCINTMSK6_NYETMSK_SET_MSK 0x00000040
35407 /* The mask used to clear the ALT_USB_HOST_HCINTMSK6_NYETMSK register field value. */
35408 #define ALT_USB_HOST_HCINTMSK6_NYETMSK_CLR_MSK 0xffffffbf
35409 /* The reset value of the ALT_USB_HOST_HCINTMSK6_NYETMSK register field. */
35410 #define ALT_USB_HOST_HCINTMSK6_NYETMSK_RESET 0x0
35411 /* Extracts the ALT_USB_HOST_HCINTMSK6_NYETMSK field value from a register. */
35412 #define ALT_USB_HOST_HCINTMSK6_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
35413 /* Produces a ALT_USB_HOST_HCINTMSK6_NYETMSK register field value suitable for setting the register. */
35414 #define ALT_USB_HOST_HCINTMSK6_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
35415 
35416 /*
35417  * Field : xacterrmsk
35418  *
35419  * Transaction Error Mask (XactErrMsk)
35420  *
35421  * In scatter/gather DMA mode for host,
35422  *
35423  * interrupts will not be generated due to the corresponding bits set in
35424  *
35425  * HCINTn.
35426  *
35427  * Field Access Macros:
35428  *
35429  */
35430 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field. */
35431 #define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_LSB 7
35432 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field. */
35433 #define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_MSB 7
35434 /* The width in bits of the ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field. */
35435 #define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_WIDTH 1
35436 /* The mask used to set the ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field value. */
35437 #define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_SET_MSK 0x00000080
35438 /* The mask used to clear the ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field value. */
35439 #define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_CLR_MSK 0xffffff7f
35440 /* The reset value of the ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field. */
35441 #define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_RESET 0x0
35442 /* Extracts the ALT_USB_HOST_HCINTMSK6_XACTERRMSK field value from a register. */
35443 #define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
35444 /* Produces a ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field value suitable for setting the register. */
35445 #define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
35446 
35447 /*
35448  * Field : bblerrmsk
35449  *
35450  * Babble Error Mask (BblErrMsk)
35451  *
35452  * In scatter/gather DMA mode for host,
35453  *
35454  * interrupts will not be generated due to the corresponding bits set in
35455  *
35456  * HCINTn.
35457  *
35458  * Field Access Macros:
35459  *
35460  */
35461 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field. */
35462 #define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_LSB 8
35463 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field. */
35464 #define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_MSB 8
35465 /* The width in bits of the ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field. */
35466 #define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_WIDTH 1
35467 /* The mask used to set the ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field value. */
35468 #define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_SET_MSK 0x00000100
35469 /* The mask used to clear the ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field value. */
35470 #define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_CLR_MSK 0xfffffeff
35471 /* The reset value of the ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field. */
35472 #define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_RESET 0x0
35473 /* Extracts the ALT_USB_HOST_HCINTMSK6_BBLERRMSK field value from a register. */
35474 #define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
35475 /* Produces a ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field value suitable for setting the register. */
35476 #define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
35477 
35478 /*
35479  * Field : frmovrunmsk
35480  *
35481  * Frame Overrun Mask (FrmOvrunMsk)
35482  *
35483  * In scatter/gather DMA mode for host,
35484  *
35485  * interrupts will not be generated due to the corresponding bits set in
35486  *
35487  * HCINTn.
35488  *
35489  * Field Access Macros:
35490  *
35491  */
35492 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field. */
35493 #define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_LSB 9
35494 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field. */
35495 #define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_MSB 9
35496 /* The width in bits of the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field. */
35497 #define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_WIDTH 1
35498 /* The mask used to set the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field value. */
35499 #define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_SET_MSK 0x00000200
35500 /* The mask used to clear the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field value. */
35501 #define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_CLR_MSK 0xfffffdff
35502 /* The reset value of the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field. */
35503 #define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_RESET 0x0
35504 /* Extracts the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK field value from a register. */
35505 #define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
35506 /* Produces a ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field value suitable for setting the register. */
35507 #define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
35508 
35509 /*
35510  * Field : datatglerrmsk
35511  *
35512  * Data Toggle Error Mask (DataTglErrMsk)
35513  *
35514  * In scatter/gather DMA mode for host,
35515  *
35516  * interrupts will not be generated due to the corresponding bits set in
35517  *
35518  * HCINTn.
35519  *
35520  * Field Access Macros:
35521  *
35522  */
35523 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field. */
35524 #define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_LSB 10
35525 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field. */
35526 #define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_MSB 10
35527 /* The width in bits of the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field. */
35528 #define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_WIDTH 1
35529 /* The mask used to set the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field value. */
35530 #define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_SET_MSK 0x00000400
35531 /* The mask used to clear the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field value. */
35532 #define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_CLR_MSK 0xfffffbff
35533 /* The reset value of the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field. */
35534 #define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_RESET 0x0
35535 /* Extracts the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK field value from a register. */
35536 #define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
35537 /* Produces a ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field value suitable for setting the register. */
35538 #define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
35539 
35540 /*
35541  * Field : bnaintrmsk
35542  *
35543  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
35544  *
35545  * This bit is valid only when Scatter/Gather DMA mode is enabled.
35546  *
35547  * Field Enumeration Values:
35548  *
35549  * Enum | Value | Description
35550  * :------------------------------------------|:------|:------------
35551  * ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_MSK | 0x0 | Mask
35552  * ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_NOMSK | 0x1 | No mask
35553  *
35554  * Field Access Macros:
35555  *
35556  */
35557 /*
35558  * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_BNAINTRMSK
35559  *
35560  * Mask
35561  */
35562 #define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_MSK 0x0
35563 /*
35564  * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_BNAINTRMSK
35565  *
35566  * No mask
35567  */
35568 #define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_NOMSK 0x1
35569 
35570 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */
35571 #define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_LSB 11
35572 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */
35573 #define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_MSB 11
35574 /* The width in bits of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */
35575 #define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_WIDTH 1
35576 /* The mask used to set the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field value. */
35577 #define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_SET_MSK 0x00000800
35578 /* The mask used to clear the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field value. */
35579 #define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_CLR_MSK 0xfffff7ff
35580 /* The reset value of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */
35581 #define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_RESET 0x0
35582 /* Extracts the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK field value from a register. */
35583 #define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
35584 /* Produces a ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field value suitable for setting the register. */
35585 #define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
35586 
35587 /*
35588  * Field : frm_lst_rollintrmsk
35589  *
35590  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
35591  *
35592  * This bit is valid only when Scatter/Gather DMA mode is enabled.
35593  *
35594  * Field Enumeration Values:
35595  *
35596  * Enum | Value | Description
35597  * :---------------------------------------------------|:------|:------------
35598  * ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
35599  * ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
35600  *
35601  * Field Access Macros:
35602  *
35603  */
35604 /*
35605  * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK
35606  *
35607  * Mask
35608  */
35609 #define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_MSK 0x0
35610 /*
35611  * Enumerated value for register field ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK
35612  *
35613  * No mask
35614  */
35615 #define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
35616 
35617 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */
35618 #define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_LSB 13
35619 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */
35620 #define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_MSB 13
35621 /* The width in bits of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */
35622 #define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_WIDTH 1
35623 /* The mask used to set the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field value. */
35624 #define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
35625 /* The mask used to clear the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field value. */
35626 #define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
35627 /* The reset value of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */
35628 #define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_RESET 0x0
35629 /* Extracts the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK field value from a register. */
35630 #define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
35631 /* Produces a ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
35632 #define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
35633 
35634 #ifndef __ASSEMBLY__
35635 /*
35636  * WARNING: The C register and register group struct declarations are provided for
35637  * convenience and illustrative purposes. They should, however, be used with
35638  * caution as the C language standard provides no guarantees about the alignment or
35639  * atomicity of device memory accesses. The recommended practice for writing
35640  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35641  * alt_write_word() functions.
35642  *
35643  * The struct declaration for register ALT_USB_HOST_HCINTMSK6.
35644  */
35645 struct ALT_USB_HOST_HCINTMSK6_s
35646 {
35647  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK */
35648  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK6_CHHLTDMSK */
35649  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK6_AHBERRMSK */
35650  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK6_STALLMSK */
35651  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK6_NAKMSK */
35652  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK6_ACKMSK */
35653  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK6_NYETMSK */
35654  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK6_XACTERRMSK */
35655  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK6_BBLERRMSK */
35656  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK */
35657  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK */
35658  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK6_BNAINTRMSK */
35659  uint32_t : 1; /* *UNDEFINED* */
35660  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK */
35661  uint32_t : 18; /* *UNDEFINED* */
35662 };
35663 
35664 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK6. */
35665 typedef volatile struct ALT_USB_HOST_HCINTMSK6_s ALT_USB_HOST_HCINTMSK6_t;
35666 #endif /* __ASSEMBLY__ */
35667 
35668 /* The reset value of the ALT_USB_HOST_HCINTMSK6 register. */
35669 #define ALT_USB_HOST_HCINTMSK6_RESET 0x00000000
35670 /* The byte offset of the ALT_USB_HOST_HCINTMSK6 register from the beginning of the component. */
35671 #define ALT_USB_HOST_HCINTMSK6_OFST 0x1cc
35672 /* The address of the ALT_USB_HOST_HCINTMSK6 register. */
35673 #define ALT_USB_HOST_HCINTMSK6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK6_OFST))
35674 
35675 /*
35676  * Register : hctsiz6
35677  *
35678  * Host Channel 6 Transfer Size Register
35679  *
35680  * Register Layout
35681  *
35682  * Bits | Access | Reset | Description
35683  * :--------|:-------|:------|:------------------------------
35684  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ6_XFERSIZE
35685  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ6_PKTCNT
35686  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ6_PID
35687  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ6_DOPNG
35688  *
35689  */
35690 /*
35691  * Field : xfersize
35692  *
35693  * Transfer Size (XferSize)
35694  *
35695  * For an OUT, this field is the number of data bytes the host sends
35696  *
35697  * during the transfer.
35698  *
35699  * For an IN, this field is the buffer size that the application has
35700  *
35701  * Reserved For the transfer. The application is expected to
35702  *
35703  * program this field as an integer multiple of the maximum packet
35704  *
35705  * size For IN transactions (periodic and non-periodic).
35706  *
35707  * The width of this counter is specified as Width of Transfer Size
35708  *
35709  * Counters
35710  *
35711  * Field Access Macros:
35712  *
35713  */
35714 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */
35715 #define ALT_USB_HOST_HCTSIZ6_XFERSIZE_LSB 0
35716 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */
35717 #define ALT_USB_HOST_HCTSIZ6_XFERSIZE_MSB 18
35718 /* The width in bits of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */
35719 #define ALT_USB_HOST_HCTSIZ6_XFERSIZE_WIDTH 19
35720 /* The mask used to set the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field value. */
35721 #define ALT_USB_HOST_HCTSIZ6_XFERSIZE_SET_MSK 0x0007ffff
35722 /* The mask used to clear the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field value. */
35723 #define ALT_USB_HOST_HCTSIZ6_XFERSIZE_CLR_MSK 0xfff80000
35724 /* The reset value of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */
35725 #define ALT_USB_HOST_HCTSIZ6_XFERSIZE_RESET 0x0
35726 /* Extracts the ALT_USB_HOST_HCTSIZ6_XFERSIZE field value from a register. */
35727 #define ALT_USB_HOST_HCTSIZ6_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
35728 /* Produces a ALT_USB_HOST_HCTSIZ6_XFERSIZE register field value suitable for setting the register. */
35729 #define ALT_USB_HOST_HCTSIZ6_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
35730 
35731 /*
35732  * Field : pktcnt
35733  *
35734  * Packet Count (PktCnt)
35735  *
35736  * This field is programmed by the application with the expected
35737  *
35738  * number of packets to be transmitted (OUT) or received (IN).
35739  *
35740  * The host decrements this count on every successful
35741  *
35742  * transmission or reception of an OUT/IN packet. Once this count
35743  *
35744  * reaches zero, the application is interrupted to indicate normal
35745  *
35746  * completion.
35747  *
35748  * The width of this counter is specified as Width of Packet
35749  *
35750  * Counters
35751  *
35752  * Field Access Macros:
35753  *
35754  */
35755 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */
35756 #define ALT_USB_HOST_HCTSIZ6_PKTCNT_LSB 19
35757 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */
35758 #define ALT_USB_HOST_HCTSIZ6_PKTCNT_MSB 28
35759 /* The width in bits of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */
35760 #define ALT_USB_HOST_HCTSIZ6_PKTCNT_WIDTH 10
35761 /* The mask used to set the ALT_USB_HOST_HCTSIZ6_PKTCNT register field value. */
35762 #define ALT_USB_HOST_HCTSIZ6_PKTCNT_SET_MSK 0x1ff80000
35763 /* The mask used to clear the ALT_USB_HOST_HCTSIZ6_PKTCNT register field value. */
35764 #define ALT_USB_HOST_HCTSIZ6_PKTCNT_CLR_MSK 0xe007ffff
35765 /* The reset value of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */
35766 #define ALT_USB_HOST_HCTSIZ6_PKTCNT_RESET 0x0
35767 /* Extracts the ALT_USB_HOST_HCTSIZ6_PKTCNT field value from a register. */
35768 #define ALT_USB_HOST_HCTSIZ6_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
35769 /* Produces a ALT_USB_HOST_HCTSIZ6_PKTCNT register field value suitable for setting the register. */
35770 #define ALT_USB_HOST_HCTSIZ6_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
35771 
35772 /*
35773  * Field : pid
35774  *
35775  * PID (Pid)
35776  *
35777  * The application programs this field with the type of PID to use For
35778  *
35779  * the initial transaction. The host maintains this field For the rest of
35780  *
35781  * the transfer.
35782  *
35783  * 2'b00: DATA0
35784  *
35785  * 2'b01: DATA2
35786  *
35787  * 2'b10: DATA1
35788  *
35789  * 2'b11: MDATA (non-control)/SETUP (control)
35790  *
35791  * Field Enumeration Values:
35792  *
35793  * Enum | Value | Description
35794  * :---------------------------------|:------|:------------------------------------
35795  * ALT_USB_HOST_HCTSIZ6_PID_E_DATA0 | 0x0 | DATA0
35796  * ALT_USB_HOST_HCTSIZ6_PID_E_DATA2 | 0x1 | DATA2
35797  * ALT_USB_HOST_HCTSIZ6_PID_E_DATA1 | 0x2 | DATA1
35798  * ALT_USB_HOST_HCTSIZ6_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
35799  *
35800  * Field Access Macros:
35801  *
35802  */
35803 /*
35804  * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID
35805  *
35806  * DATA0
35807  */
35808 #define ALT_USB_HOST_HCTSIZ6_PID_E_DATA0 0x0
35809 /*
35810  * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID
35811  *
35812  * DATA2
35813  */
35814 #define ALT_USB_HOST_HCTSIZ6_PID_E_DATA2 0x1
35815 /*
35816  * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID
35817  *
35818  * DATA1
35819  */
35820 #define ALT_USB_HOST_HCTSIZ6_PID_E_DATA1 0x2
35821 /*
35822  * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID
35823  *
35824  * MDATA (non-control)/SETUP (control)
35825  */
35826 #define ALT_USB_HOST_HCTSIZ6_PID_E_MDATA 0x3
35827 
35828 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_PID register field. */
35829 #define ALT_USB_HOST_HCTSIZ6_PID_LSB 29
35830 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_PID register field. */
35831 #define ALT_USB_HOST_HCTSIZ6_PID_MSB 30
35832 /* The width in bits of the ALT_USB_HOST_HCTSIZ6_PID register field. */
35833 #define ALT_USB_HOST_HCTSIZ6_PID_WIDTH 2
35834 /* The mask used to set the ALT_USB_HOST_HCTSIZ6_PID register field value. */
35835 #define ALT_USB_HOST_HCTSIZ6_PID_SET_MSK 0x60000000
35836 /* The mask used to clear the ALT_USB_HOST_HCTSIZ6_PID register field value. */
35837 #define ALT_USB_HOST_HCTSIZ6_PID_CLR_MSK 0x9fffffff
35838 /* The reset value of the ALT_USB_HOST_HCTSIZ6_PID register field. */
35839 #define ALT_USB_HOST_HCTSIZ6_PID_RESET 0x0
35840 /* Extracts the ALT_USB_HOST_HCTSIZ6_PID field value from a register. */
35841 #define ALT_USB_HOST_HCTSIZ6_PID_GET(value) (((value) & 0x60000000) >> 29)
35842 /* Produces a ALT_USB_HOST_HCTSIZ6_PID register field value suitable for setting the register. */
35843 #define ALT_USB_HOST_HCTSIZ6_PID_SET(value) (((value) << 29) & 0x60000000)
35844 
35845 /*
35846  * Field : dopng
35847  *
35848  * Do Ping (DoPng)
35849  *
35850  * This bit is used only For OUT transfers.
35851  *
35852  * Setting this field to 1 directs the host to do PING protocol.
35853  *
35854  * Note: Do not Set this bit For IN transfers. If this bit is Set For
35855  *
35856  * for IN transfers it disables the channel.
35857  *
35858  * Field Enumeration Values:
35859  *
35860  * Enum | Value | Description
35861  * :------------------------------------|:------|:-----------------
35862  * ALT_USB_HOST_HCTSIZ6_DOPNG_E_NOPING | 0x0 | No ping protocol
35863  * ALT_USB_HOST_HCTSIZ6_DOPNG_E_PING | 0x1 | Ping protocol
35864  *
35865  * Field Access Macros:
35866  *
35867  */
35868 /*
35869  * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_DOPNG
35870  *
35871  * No ping protocol
35872  */
35873 #define ALT_USB_HOST_HCTSIZ6_DOPNG_E_NOPING 0x0
35874 /*
35875  * Enumerated value for register field ALT_USB_HOST_HCTSIZ6_DOPNG
35876  *
35877  * Ping protocol
35878  */
35879 #define ALT_USB_HOST_HCTSIZ6_DOPNG_E_PING 0x1
35880 
35881 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */
35882 #define ALT_USB_HOST_HCTSIZ6_DOPNG_LSB 31
35883 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */
35884 #define ALT_USB_HOST_HCTSIZ6_DOPNG_MSB 31
35885 /* The width in bits of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */
35886 #define ALT_USB_HOST_HCTSIZ6_DOPNG_WIDTH 1
35887 /* The mask used to set the ALT_USB_HOST_HCTSIZ6_DOPNG register field value. */
35888 #define ALT_USB_HOST_HCTSIZ6_DOPNG_SET_MSK 0x80000000
35889 /* The mask used to clear the ALT_USB_HOST_HCTSIZ6_DOPNG register field value. */
35890 #define ALT_USB_HOST_HCTSIZ6_DOPNG_CLR_MSK 0x7fffffff
35891 /* The reset value of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */
35892 #define ALT_USB_HOST_HCTSIZ6_DOPNG_RESET 0x0
35893 /* Extracts the ALT_USB_HOST_HCTSIZ6_DOPNG field value from a register. */
35894 #define ALT_USB_HOST_HCTSIZ6_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
35895 /* Produces a ALT_USB_HOST_HCTSIZ6_DOPNG register field value suitable for setting the register. */
35896 #define ALT_USB_HOST_HCTSIZ6_DOPNG_SET(value) (((value) << 31) & 0x80000000)
35897 
35898 #ifndef __ASSEMBLY__
35899 /*
35900  * WARNING: The C register and register group struct declarations are provided for
35901  * convenience and illustrative purposes. They should, however, be used with
35902  * caution as the C language standard provides no guarantees about the alignment or
35903  * atomicity of device memory accesses. The recommended practice for writing
35904  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35905  * alt_write_word() functions.
35906  *
35907  * The struct declaration for register ALT_USB_HOST_HCTSIZ6.
35908  */
35909 struct ALT_USB_HOST_HCTSIZ6_s
35910 {
35911  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ6_XFERSIZE */
35912  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ6_PKTCNT */
35913  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ6_PID */
35914  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ6_DOPNG */
35915 };
35916 
35917 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ6. */
35918 typedef volatile struct ALT_USB_HOST_HCTSIZ6_s ALT_USB_HOST_HCTSIZ6_t;
35919 #endif /* __ASSEMBLY__ */
35920 
35921 /* The reset value of the ALT_USB_HOST_HCTSIZ6 register. */
35922 #define ALT_USB_HOST_HCTSIZ6_RESET 0x00000000
35923 /* The byte offset of the ALT_USB_HOST_HCTSIZ6 register from the beginning of the component. */
35924 #define ALT_USB_HOST_HCTSIZ6_OFST 0x1d0
35925 /* The address of the ALT_USB_HOST_HCTSIZ6 register. */
35926 #define ALT_USB_HOST_HCTSIZ6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ6_OFST))
35927 
35928 /*
35929  * Register : hcdma6
35930  *
35931  * Host Channel 6 DMA Address Register
35932  *
35933  * Register Layout
35934  *
35935  * Bits | Access | Reset | Description
35936  * :-------|:-------|:------|:---------------------------
35937  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA6_HCDMA6
35938  *
35939  */
35940 /*
35941  * Field : hcdma6
35942  *
35943  * Buffer DMA Mode:
35944  *
35945  * [31:0] DMA Address (DMAAddr)
35946  *
35947  * This field holds the start address in the external memory from which the data
35948  * for
35949  *
35950  * the endpoint must be fetched or to which it must be stored. This register is
35951  *
35952  * incremented on every AHB transaction.
35953  *
35954  * Scatter-Gather DMA (DescDMA) Mode:
35955  *
35956  * [31:9] (Non Isoc) Non-Isochronous:
35957  *
35958  * [31:N] (Isoc) Isochronous:
35959  *
35960  * This field holds the start address of the 512 bytes
35961  *
35962  * page. The first descriptor in the list should be located
35963  *
35964  * in this address. The first descriptor may be or may
35965  *
35966  * not be ready. The core starts processing the list from
35967  *
35968  * the CTD value.
35969  *
35970  * This field holds the address of the 2*(nTD+1) bytes of
35971  *
35972  * locations in which the isochronous descriptors are
35973  *
35974  * present where N is based on nTD as per Table below
35975  *
35976  * [31:N] Base Address
35977  *
35978  * [N-1:3] Offset
35979  *
35980  * [2:0] 000
35981  *
35982  * HS ISOC
35983  *
35984  * nTD N
35985  *
35986  * 7 6
35987  *
35988  * 15 7
35989  *
35990  * 31 8
35991  *
35992  * 63 9
35993  *
35994  * 127 10
35995  *
35996  * 255 11
35997  *
35998  * FS ISOC
35999  *
36000  * nTD N
36001  *
36002  * 1 4
36003  *
36004  * 3 5
36005  *
36006  * 7 6
36007  *
36008  * 15 7
36009  *
36010  * 31 8
36011  *
36012  * 63 9
36013  *
36014  * [N-1:3] (Isoc):
36015  *
36016  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
36017  *
36018  * Non Isochronous:
36019  *
36020  * This value is in terms of number of descriptors. The values can be from 0 to 63.
36021  *
36022  * 0 - 1 descriptor.
36023  *
36024  * 63 - 64 descriptors.
36025  *
36026  * This field indicates the current descriptor processed in the list. This field is
36027  * updated
36028  *
36029  * both by application and the core. For example, if the application enables the
36030  *
36031  * channel after programming CTD=5, then the core will start processing the 6th
36032  *
36033  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
36034  *
36035  * to DMAAddr.
36036  *
36037  * Isochronous:
36038  *
36039  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
36040  * set
36041  *
36042  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
36043  *
36044  * [31:9] (Non Isoc) Non-Isochronous:
36045  *
36046  * [31:N] (Isoc) Isochronous:
36047  *
36048  * This field holds the start address of the 512 bytes
36049  *
36050  * page. The first descriptor in the list should be located
36051  *
36052  * in this address. The first descriptor may be or may
36053  *
36054  * not be ready. The core starts processing the list from
36055  *
36056  * the CTD value.
36057  *
36058  * This field holds the address of the 2*(nTD+1) bytes of
36059  *
36060  * locations in which the isochronous descriptors are
36061  *
36062  * present where N is based on nTD as per Table below
36063  *
36064  * [31:N] Base Address
36065  *
36066  * [N-1:3] Offset
36067  *
36068  * [2:0] 000
36069  *
36070  * HS ISOC
36071  *
36072  * nTD N
36073  *
36074  * 7 6
36075  *
36076  * 15 7
36077  *
36078  * 31 8
36079  *
36080  * 63 9
36081  *
36082  * 127 10
36083  *
36084  * 255 11
36085  *
36086  * FS ISOC
36087  *
36088  * nTD N
36089  *
36090  * 1 4
36091  *
36092  * 3 5
36093  *
36094  * 7 6
36095  *
36096  * 15 7
36097  *
36098  * 31 8
36099  *
36100  * 63 9
36101  *
36102  * [N-1:3] (Isoc):
36103  *
36104  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
36105  *
36106  * Non Isochronous:
36107  *
36108  * This value is in terms of number of descriptors. The values can be from 0 to 63.
36109  *
36110  * 0 - 1 descriptor.
36111  *
36112  * 63 - 64 descriptors.
36113  *
36114  * This field indicates the current descriptor processed in the list. This field is
36115  * updated
36116  *
36117  * both by application and the core. For example, if the application enables the
36118  *
36119  * channel after programming CTD=5, then the core will start processing the 6th
36120  *
36121  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
36122  *
36123  * to DMAAddr.
36124  *
36125  * Isochronous:
36126  *
36127  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
36128  * set
36129  *
36130  * to zero by application.
36131  *
36132  * Field Access Macros:
36133  *
36134  */
36135 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */
36136 #define ALT_USB_HOST_HCDMA6_HCDMA6_LSB 0
36137 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */
36138 #define ALT_USB_HOST_HCDMA6_HCDMA6_MSB 31
36139 /* The width in bits of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */
36140 #define ALT_USB_HOST_HCDMA6_HCDMA6_WIDTH 32
36141 /* The mask used to set the ALT_USB_HOST_HCDMA6_HCDMA6 register field value. */
36142 #define ALT_USB_HOST_HCDMA6_HCDMA6_SET_MSK 0xffffffff
36143 /* The mask used to clear the ALT_USB_HOST_HCDMA6_HCDMA6 register field value. */
36144 #define ALT_USB_HOST_HCDMA6_HCDMA6_CLR_MSK 0x00000000
36145 /* The reset value of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */
36146 #define ALT_USB_HOST_HCDMA6_HCDMA6_RESET 0x0
36147 /* Extracts the ALT_USB_HOST_HCDMA6_HCDMA6 field value from a register. */
36148 #define ALT_USB_HOST_HCDMA6_HCDMA6_GET(value) (((value) & 0xffffffff) >> 0)
36149 /* Produces a ALT_USB_HOST_HCDMA6_HCDMA6 register field value suitable for setting the register. */
36150 #define ALT_USB_HOST_HCDMA6_HCDMA6_SET(value) (((value) << 0) & 0xffffffff)
36151 
36152 #ifndef __ASSEMBLY__
36153 /*
36154  * WARNING: The C register and register group struct declarations are provided for
36155  * convenience and illustrative purposes. They should, however, be used with
36156  * caution as the C language standard provides no guarantees about the alignment or
36157  * atomicity of device memory accesses. The recommended practice for writing
36158  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
36159  * alt_write_word() functions.
36160  *
36161  * The struct declaration for register ALT_USB_HOST_HCDMA6.
36162  */
36163 struct ALT_USB_HOST_HCDMA6_s
36164 {
36165  uint32_t hcdma6 : 32; /* ALT_USB_HOST_HCDMA6_HCDMA6 */
36166 };
36167 
36168 /* The typedef declaration for register ALT_USB_HOST_HCDMA6. */
36169 typedef volatile struct ALT_USB_HOST_HCDMA6_s ALT_USB_HOST_HCDMA6_t;
36170 #endif /* __ASSEMBLY__ */
36171 
36172 /* The reset value of the ALT_USB_HOST_HCDMA6 register. */
36173 #define ALT_USB_HOST_HCDMA6_RESET 0x00000000
36174 /* The byte offset of the ALT_USB_HOST_HCDMA6 register from the beginning of the component. */
36175 #define ALT_USB_HOST_HCDMA6_OFST 0x1d4
36176 /* The address of the ALT_USB_HOST_HCDMA6 register. */
36177 #define ALT_USB_HOST_HCDMA6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA6_OFST))
36178 
36179 /*
36180  * Register : hcdmab6
36181  *
36182  * Host Channel 6 DMA Buffer Address Register
36183  *
36184  * Register Layout
36185  *
36186  * Bits | Access | Reset | Description
36187  * :-------|:-------|:------|:-----------------------------
36188  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB6_HCDMAB6
36189  *
36190  */
36191 /*
36192  * Field : hcdmab6
36193  *
36194  * Holds the current buffer address.
36195  *
36196  * This register is updated as and when the data transfer for the corresponding end
36197  * point
36198  *
36199  * is in progress. This register is present only in Scatter/Gather DMA mode.
36200  * Otherwise this
36201  *
36202  * field is reserved.
36203  *
36204  * Field Access Macros:
36205  *
36206  */
36207 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */
36208 #define ALT_USB_HOST_HCDMAB6_HCDMAB6_LSB 0
36209 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */
36210 #define ALT_USB_HOST_HCDMAB6_HCDMAB6_MSB 31
36211 /* The width in bits of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */
36212 #define ALT_USB_HOST_HCDMAB6_HCDMAB6_WIDTH 32
36213 /* The mask used to set the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field value. */
36214 #define ALT_USB_HOST_HCDMAB6_HCDMAB6_SET_MSK 0xffffffff
36215 /* The mask used to clear the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field value. */
36216 #define ALT_USB_HOST_HCDMAB6_HCDMAB6_CLR_MSK 0x00000000
36217 /* The reset value of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */
36218 #define ALT_USB_HOST_HCDMAB6_HCDMAB6_RESET 0x0
36219 /* Extracts the ALT_USB_HOST_HCDMAB6_HCDMAB6 field value from a register. */
36220 #define ALT_USB_HOST_HCDMAB6_HCDMAB6_GET(value) (((value) & 0xffffffff) >> 0)
36221 /* Produces a ALT_USB_HOST_HCDMAB6_HCDMAB6 register field value suitable for setting the register. */
36222 #define ALT_USB_HOST_HCDMAB6_HCDMAB6_SET(value) (((value) << 0) & 0xffffffff)
36223 
36224 #ifndef __ASSEMBLY__
36225 /*
36226  * WARNING: The C register and register group struct declarations are provided for
36227  * convenience and illustrative purposes. They should, however, be used with
36228  * caution as the C language standard provides no guarantees about the alignment or
36229  * atomicity of device memory accesses. The recommended practice for writing
36230  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
36231  * alt_write_word() functions.
36232  *
36233  * The struct declaration for register ALT_USB_HOST_HCDMAB6.
36234  */
36235 struct ALT_USB_HOST_HCDMAB6_s
36236 {
36237  uint32_t hcdmab6 : 32; /* ALT_USB_HOST_HCDMAB6_HCDMAB6 */
36238 };
36239 
36240 /* The typedef declaration for register ALT_USB_HOST_HCDMAB6. */
36241 typedef volatile struct ALT_USB_HOST_HCDMAB6_s ALT_USB_HOST_HCDMAB6_t;
36242 #endif /* __ASSEMBLY__ */
36243 
36244 /* The reset value of the ALT_USB_HOST_HCDMAB6 register. */
36245 #define ALT_USB_HOST_HCDMAB6_RESET 0x00000000
36246 /* The byte offset of the ALT_USB_HOST_HCDMAB6 register from the beginning of the component. */
36247 #define ALT_USB_HOST_HCDMAB6_OFST 0x1dc
36248 /* The address of the ALT_USB_HOST_HCDMAB6 register. */
36249 #define ALT_USB_HOST_HCDMAB6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB6_OFST))
36250 
36251 /*
36252  * Register : hcchar7
36253  *
36254  * Host Channel 7 Characteristics Register
36255  *
36256  * Register Layout
36257  *
36258  * Bits | Access | Reset | Description
36259  * :--------|:---------|:------|:-----------------------------
36260  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_MPS
36261  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_EPNUM
36262  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_EPDIR
36263  * [16] | ??? | 0x0 | *UNDEFINED*
36264  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_LSPDDEV
36265  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_EPTYPE
36266  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_EC
36267  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_DEVADDR
36268  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_ODDFRM
36269  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR7_CHDIS
36270  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR7_CHENA
36271  *
36272  */
36273 /*
36274  * Field : mps
36275  *
36276  * Maximum Packet Size (MPS)
36277  *
36278  * Indicates the maximum packet size of the associated endpoint.
36279  *
36280  * Field Access Macros:
36281  *
36282  */
36283 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_MPS register field. */
36284 #define ALT_USB_HOST_HCCHAR7_MPS_LSB 0
36285 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_MPS register field. */
36286 #define ALT_USB_HOST_HCCHAR7_MPS_MSB 10
36287 /* The width in bits of the ALT_USB_HOST_HCCHAR7_MPS register field. */
36288 #define ALT_USB_HOST_HCCHAR7_MPS_WIDTH 11
36289 /* The mask used to set the ALT_USB_HOST_HCCHAR7_MPS register field value. */
36290 #define ALT_USB_HOST_HCCHAR7_MPS_SET_MSK 0x000007ff
36291 /* The mask used to clear the ALT_USB_HOST_HCCHAR7_MPS register field value. */
36292 #define ALT_USB_HOST_HCCHAR7_MPS_CLR_MSK 0xfffff800
36293 /* The reset value of the ALT_USB_HOST_HCCHAR7_MPS register field. */
36294 #define ALT_USB_HOST_HCCHAR7_MPS_RESET 0x0
36295 /* Extracts the ALT_USB_HOST_HCCHAR7_MPS field value from a register. */
36296 #define ALT_USB_HOST_HCCHAR7_MPS_GET(value) (((value) & 0x000007ff) >> 0)
36297 /* Produces a ALT_USB_HOST_HCCHAR7_MPS register field value suitable for setting the register. */
36298 #define ALT_USB_HOST_HCCHAR7_MPS_SET(value) (((value) << 0) & 0x000007ff)
36299 
36300 /*
36301  * Field : epnum
36302  *
36303  * Endpoint Number (EPNum)
36304  *
36305  * Indicates the endpoint number on the device serving as the data
36306  *
36307  * source or sink.
36308  *
36309  * Field Enumeration Values:
36310  *
36311  * Enum | Value | Description
36312  * :-------------------------------------|:------|:--------------
36313  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT0 | 0x0 | End point 0
36314  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT1 | 0x1 | End point 1
36315  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT2 | 0x2 | End point 2
36316  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT3 | 0x3 | End point 3
36317  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT4 | 0x4 | End point 4
36318  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT5 | 0x5 | End point 5
36319  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT6 | 0x6 | End point 6
36320  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT7 | 0x7 | End point 7
36321  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT8 | 0x8 | End point 8
36322  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT9 | 0x9 | End point 9
36323  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT10 | 0xa | End point 10
36324  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT11 | 0xb | End point 11
36325  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT12 | 0xc | End point 12
36326  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT13 | 0xd | End point 13
36327  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT14 | 0xe | End point 14
36328  * ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT15 | 0xf | End point 15
36329  *
36330  * Field Access Macros:
36331  *
36332  */
36333 /*
36334  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36335  *
36336  * End point 0
36337  */
36338 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT0 0x0
36339 /*
36340  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36341  *
36342  * End point 1
36343  */
36344 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT1 0x1
36345 /*
36346  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36347  *
36348  * End point 2
36349  */
36350 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT2 0x2
36351 /*
36352  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36353  *
36354  * End point 3
36355  */
36356 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT3 0x3
36357 /*
36358  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36359  *
36360  * End point 4
36361  */
36362 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT4 0x4
36363 /*
36364  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36365  *
36366  * End point 5
36367  */
36368 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT5 0x5
36369 /*
36370  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36371  *
36372  * End point 6
36373  */
36374 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT6 0x6
36375 /*
36376  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36377  *
36378  * End point 7
36379  */
36380 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT7 0x7
36381 /*
36382  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36383  *
36384  * End point 8
36385  */
36386 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT8 0x8
36387 /*
36388  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36389  *
36390  * End point 9
36391  */
36392 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT9 0x9
36393 /*
36394  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36395  *
36396  * End point 10
36397  */
36398 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT10 0xa
36399 /*
36400  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36401  *
36402  * End point 11
36403  */
36404 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT11 0xb
36405 /*
36406  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36407  *
36408  * End point 12
36409  */
36410 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT12 0xc
36411 /*
36412  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36413  *
36414  * End point 13
36415  */
36416 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT13 0xd
36417 /*
36418  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36419  *
36420  * End point 14
36421  */
36422 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT14 0xe
36423 /*
36424  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
36425  *
36426  * End point 15
36427  */
36428 #define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT15 0xf
36429 
36430 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */
36431 #define ALT_USB_HOST_HCCHAR7_EPNUM_LSB 11
36432 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */
36433 #define ALT_USB_HOST_HCCHAR7_EPNUM_MSB 14
36434 /* The width in bits of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */
36435 #define ALT_USB_HOST_HCCHAR7_EPNUM_WIDTH 4
36436 /* The mask used to set the ALT_USB_HOST_HCCHAR7_EPNUM register field value. */
36437 #define ALT_USB_HOST_HCCHAR7_EPNUM_SET_MSK 0x00007800
36438 /* The mask used to clear the ALT_USB_HOST_HCCHAR7_EPNUM register field value. */
36439 #define ALT_USB_HOST_HCCHAR7_EPNUM_CLR_MSK 0xffff87ff
36440 /* The reset value of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */
36441 #define ALT_USB_HOST_HCCHAR7_EPNUM_RESET 0x0
36442 /* Extracts the ALT_USB_HOST_HCCHAR7_EPNUM field value from a register. */
36443 #define ALT_USB_HOST_HCCHAR7_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
36444 /* Produces a ALT_USB_HOST_HCCHAR7_EPNUM register field value suitable for setting the register. */
36445 #define ALT_USB_HOST_HCCHAR7_EPNUM_SET(value) (((value) << 11) & 0x00007800)
36446 
36447 /*
36448  * Field : epdir
36449  *
36450  * Endpoint Direction (EPDir)
36451  *
36452  * Indicates whether the transaction is IN or OUT.
36453  *
36454  * 1'b0: OUT
36455  *
36456  * 1'b1: IN
36457  *
36458  * Field Enumeration Values:
36459  *
36460  * Enum | Value | Description
36461  * :---------------------------------|:------|:--------------
36462  * ALT_USB_HOST_HCCHAR7_EPDIR_E_OUT | 0x0 | OUT Direction
36463  * ALT_USB_HOST_HCCHAR7_EPDIR_E_IN | 0x1 | IN Direction
36464  *
36465  * Field Access Macros:
36466  *
36467  */
36468 /*
36469  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPDIR
36470  *
36471  * OUT Direction
36472  */
36473 #define ALT_USB_HOST_HCCHAR7_EPDIR_E_OUT 0x0
36474 /*
36475  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPDIR
36476  *
36477  * IN Direction
36478  */
36479 #define ALT_USB_HOST_HCCHAR7_EPDIR_E_IN 0x1
36480 
36481 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */
36482 #define ALT_USB_HOST_HCCHAR7_EPDIR_LSB 15
36483 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */
36484 #define ALT_USB_HOST_HCCHAR7_EPDIR_MSB 15
36485 /* The width in bits of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */
36486 #define ALT_USB_HOST_HCCHAR7_EPDIR_WIDTH 1
36487 /* The mask used to set the ALT_USB_HOST_HCCHAR7_EPDIR register field value. */
36488 #define ALT_USB_HOST_HCCHAR7_EPDIR_SET_MSK 0x00008000
36489 /* The mask used to clear the ALT_USB_HOST_HCCHAR7_EPDIR register field value. */
36490 #define ALT_USB_HOST_HCCHAR7_EPDIR_CLR_MSK 0xffff7fff
36491 /* The reset value of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */
36492 #define ALT_USB_HOST_HCCHAR7_EPDIR_RESET 0x0
36493 /* Extracts the ALT_USB_HOST_HCCHAR7_EPDIR field value from a register. */
36494 #define ALT_USB_HOST_HCCHAR7_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
36495 /* Produces a ALT_USB_HOST_HCCHAR7_EPDIR register field value suitable for setting the register. */
36496 #define ALT_USB_HOST_HCCHAR7_EPDIR_SET(value) (((value) << 15) & 0x00008000)
36497 
36498 /*
36499  * Field : lspddev
36500  *
36501  * Low-Speed Device (LSpdDev)
36502  *
36503  * This field is Set by the application to indicate that this channel is
36504  *
36505  * communicating to a low-speed device.
36506  *
36507  * Field Enumeration Values:
36508  *
36509  * Enum | Value | Description
36510  * :------------------------------------|:------|:----------------------------------------
36511  * ALT_USB_HOST_HCCHAR7_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
36512  * ALT_USB_HOST_HCCHAR7_LSPDDEV_E_END | 0x1 | Communicating with low speed device
36513  *
36514  * Field Access Macros:
36515  *
36516  */
36517 /*
36518  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_LSPDDEV
36519  *
36520  * Not Communicating with low speed device
36521  */
36522 #define ALT_USB_HOST_HCCHAR7_LSPDDEV_E_DISD 0x0
36523 /*
36524  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_LSPDDEV
36525  *
36526  * Communicating with low speed device
36527  */
36528 #define ALT_USB_HOST_HCCHAR7_LSPDDEV_E_END 0x1
36529 
36530 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */
36531 #define ALT_USB_HOST_HCCHAR7_LSPDDEV_LSB 17
36532 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */
36533 #define ALT_USB_HOST_HCCHAR7_LSPDDEV_MSB 17
36534 /* The width in bits of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */
36535 #define ALT_USB_HOST_HCCHAR7_LSPDDEV_WIDTH 1
36536 /* The mask used to set the ALT_USB_HOST_HCCHAR7_LSPDDEV register field value. */
36537 #define ALT_USB_HOST_HCCHAR7_LSPDDEV_SET_MSK 0x00020000
36538 /* The mask used to clear the ALT_USB_HOST_HCCHAR7_LSPDDEV register field value. */
36539 #define ALT_USB_HOST_HCCHAR7_LSPDDEV_CLR_MSK 0xfffdffff
36540 /* The reset value of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */
36541 #define ALT_USB_HOST_HCCHAR7_LSPDDEV_RESET 0x0
36542 /* Extracts the ALT_USB_HOST_HCCHAR7_LSPDDEV field value from a register. */
36543 #define ALT_USB_HOST_HCCHAR7_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
36544 /* Produces a ALT_USB_HOST_HCCHAR7_LSPDDEV register field value suitable for setting the register. */
36545 #define ALT_USB_HOST_HCCHAR7_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
36546 
36547 /*
36548  * Field : eptype
36549  *
36550  * Endpoint Type (EPType)
36551  *
36552  * Indicates the transfer type selected.
36553  *
36554  * 2'b00: Control
36555  *
36556  * 2'b01: Isochronous
36557  *
36558  * 2'b10: Bulk
36559  *
36560  * 2'b11: Interrupt
36561  *
36562  * Field Enumeration Values:
36563  *
36564  * Enum | Value | Description
36565  * :-------------------------------------|:------|:------------
36566  * ALT_USB_HOST_HCCHAR7_EPTYPE_E_CTL | 0x0 | Control
36567  * ALT_USB_HOST_HCCHAR7_EPTYPE_E_ISOC | 0x1 | Isochronous
36568  * ALT_USB_HOST_HCCHAR7_EPTYPE_E_BULK | 0x2 | Bulk
36569  * ALT_USB_HOST_HCCHAR7_EPTYPE_E_INTERR | 0x3 | Interrupt
36570  *
36571  * Field Access Macros:
36572  *
36573  */
36574 /*
36575  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE
36576  *
36577  * Control
36578  */
36579 #define ALT_USB_HOST_HCCHAR7_EPTYPE_E_CTL 0x0
36580 /*
36581  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE
36582  *
36583  * Isochronous
36584  */
36585 #define ALT_USB_HOST_HCCHAR7_EPTYPE_E_ISOC 0x1
36586 /*
36587  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE
36588  *
36589  * Bulk
36590  */
36591 #define ALT_USB_HOST_HCCHAR7_EPTYPE_E_BULK 0x2
36592 /*
36593  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE
36594  *
36595  * Interrupt
36596  */
36597 #define ALT_USB_HOST_HCCHAR7_EPTYPE_E_INTERR 0x3
36598 
36599 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */
36600 #define ALT_USB_HOST_HCCHAR7_EPTYPE_LSB 18
36601 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */
36602 #define ALT_USB_HOST_HCCHAR7_EPTYPE_MSB 19
36603 /* The width in bits of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */
36604 #define ALT_USB_HOST_HCCHAR7_EPTYPE_WIDTH 2
36605 /* The mask used to set the ALT_USB_HOST_HCCHAR7_EPTYPE register field value. */
36606 #define ALT_USB_HOST_HCCHAR7_EPTYPE_SET_MSK 0x000c0000
36607 /* The mask used to clear the ALT_USB_HOST_HCCHAR7_EPTYPE register field value. */
36608 #define ALT_USB_HOST_HCCHAR7_EPTYPE_CLR_MSK 0xfff3ffff
36609 /* The reset value of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */
36610 #define ALT_USB_HOST_HCCHAR7_EPTYPE_RESET 0x0
36611 /* Extracts the ALT_USB_HOST_HCCHAR7_EPTYPE field value from a register. */
36612 #define ALT_USB_HOST_HCCHAR7_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
36613 /* Produces a ALT_USB_HOST_HCCHAR7_EPTYPE register field value suitable for setting the register. */
36614 #define ALT_USB_HOST_HCCHAR7_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
36615 
36616 /*
36617  * Field : ec
36618  *
36619  * Multi Count (MC) / Error Count (EC)
36620  *
36621  * When the Split Enable bit of the Host Channel-n Split Control
36622  *
36623  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
36624  *
36625  * the host the number of transactions that must be executed per
36626  *
36627  * microframe For this periodic endpoint. For non periodic transfers,
36628  *
36629  * this field is used only in DMA mode, and specifies the number
36630  *
36631  * packets to be fetched For this channel before the internal DMA
36632  *
36633  * engine changes arbitration.
36634  *
36635  * 2'b00: Reserved This field yields undefined results.
36636  *
36637  * 2'b01: 1 transaction
36638  *
36639  * 2'b10: 2 transactions to be issued For this endpoint per
36640  *
36641  * microframe
36642  *
36643  * 2'b11: 3 transactions to be issued For this endpoint per
36644  *
36645  * microframe
36646  *
36647  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
36648  *
36649  * number of immediate retries to be performed For a periodic split
36650  *
36651  * transactions on transaction errors. This field must be Set to at
36652  *
36653  * least 2'b01.
36654  *
36655  * Field Enumeration Values:
36656  *
36657  * Enum | Value | Description
36658  * :-------------------------------------|:------|:----------------------------------------------
36659  * ALT_USB_HOST_HCCHAR7_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
36660  * ALT_USB_HOST_HCCHAR7_EC_E_TRANSONE | 0x1 | 1 transaction
36661  * ALT_USB_HOST_HCCHAR7_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
36662  * : | | per microframe
36663  * ALT_USB_HOST_HCCHAR7_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
36664  * : | | per microframe
36665  *
36666  * Field Access Macros:
36667  *
36668  */
36669 /*
36670  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC
36671  *
36672  * Reserved This field yields undefined result
36673  */
36674 #define ALT_USB_HOST_HCCHAR7_EC_E_RSVD 0x0
36675 /*
36676  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC
36677  *
36678  * 1 transaction
36679  */
36680 #define ALT_USB_HOST_HCCHAR7_EC_E_TRANSONE 0x1
36681 /*
36682  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC
36683  *
36684  * 2 transactions to be issued for this endpoint per microframe
36685  */
36686 #define ALT_USB_HOST_HCCHAR7_EC_E_TRANSTWO 0x2
36687 /*
36688  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC
36689  *
36690  * 3 transactions to be issued for this endpoint per microframe
36691  */
36692 #define ALT_USB_HOST_HCCHAR7_EC_E_TRANSTHREE 0x3
36693 
36694 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EC register field. */
36695 #define ALT_USB_HOST_HCCHAR7_EC_LSB 20
36696 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EC register field. */
36697 #define ALT_USB_HOST_HCCHAR7_EC_MSB 21
36698 /* The width in bits of the ALT_USB_HOST_HCCHAR7_EC register field. */
36699 #define ALT_USB_HOST_HCCHAR7_EC_WIDTH 2
36700 /* The mask used to set the ALT_USB_HOST_HCCHAR7_EC register field value. */
36701 #define ALT_USB_HOST_HCCHAR7_EC_SET_MSK 0x00300000
36702 /* The mask used to clear the ALT_USB_HOST_HCCHAR7_EC register field value. */
36703 #define ALT_USB_HOST_HCCHAR7_EC_CLR_MSK 0xffcfffff
36704 /* The reset value of the ALT_USB_HOST_HCCHAR7_EC register field. */
36705 #define ALT_USB_HOST_HCCHAR7_EC_RESET 0x0
36706 /* Extracts the ALT_USB_HOST_HCCHAR7_EC field value from a register. */
36707 #define ALT_USB_HOST_HCCHAR7_EC_GET(value) (((value) & 0x00300000) >> 20)
36708 /* Produces a ALT_USB_HOST_HCCHAR7_EC register field value suitable for setting the register. */
36709 #define ALT_USB_HOST_HCCHAR7_EC_SET(value) (((value) << 20) & 0x00300000)
36710 
36711 /*
36712  * Field : devaddr
36713  *
36714  * Device Address (DevAddr)
36715  *
36716  * This field selects the specific device serving as the data source
36717  *
36718  * or sink.
36719  *
36720  * Field Access Macros:
36721  *
36722  */
36723 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */
36724 #define ALT_USB_HOST_HCCHAR7_DEVADDR_LSB 22
36725 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */
36726 #define ALT_USB_HOST_HCCHAR7_DEVADDR_MSB 28
36727 /* The width in bits of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */
36728 #define ALT_USB_HOST_HCCHAR7_DEVADDR_WIDTH 7
36729 /* The mask used to set the ALT_USB_HOST_HCCHAR7_DEVADDR register field value. */
36730 #define ALT_USB_HOST_HCCHAR7_DEVADDR_SET_MSK 0x1fc00000
36731 /* The mask used to clear the ALT_USB_HOST_HCCHAR7_DEVADDR register field value. */
36732 #define ALT_USB_HOST_HCCHAR7_DEVADDR_CLR_MSK 0xe03fffff
36733 /* The reset value of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */
36734 #define ALT_USB_HOST_HCCHAR7_DEVADDR_RESET 0x0
36735 /* Extracts the ALT_USB_HOST_HCCHAR7_DEVADDR field value from a register. */
36736 #define ALT_USB_HOST_HCCHAR7_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
36737 /* Produces a ALT_USB_HOST_HCCHAR7_DEVADDR register field value suitable for setting the register. */
36738 #define ALT_USB_HOST_HCCHAR7_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
36739 
36740 /*
36741  * Field : oddfrm
36742  *
36743  * Odd Frame (OddFrm)
36744  *
36745  * This field is set (reset) by the application to indicate that the OTG host must
36746  * perform
36747  *
36748  * a transfer in an odd (micro)frame. This field is applicable for only periodic
36749  *
36750  * (isochronous and interrupt) transactions.
36751  *
36752  * 1'b0: Even (micro)frame
36753  *
36754  * 1'b1: Odd (micro)frame
36755  *
36756  * Field Access Macros:
36757  *
36758  */
36759 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_ODDFRM register field. */
36760 #define ALT_USB_HOST_HCCHAR7_ODDFRM_LSB 29
36761 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_ODDFRM register field. */
36762 #define ALT_USB_HOST_HCCHAR7_ODDFRM_MSB 29
36763 /* The width in bits of the ALT_USB_HOST_HCCHAR7_ODDFRM register field. */
36764 #define ALT_USB_HOST_HCCHAR7_ODDFRM_WIDTH 1
36765 /* The mask used to set the ALT_USB_HOST_HCCHAR7_ODDFRM register field value. */
36766 #define ALT_USB_HOST_HCCHAR7_ODDFRM_SET_MSK 0x20000000
36767 /* The mask used to clear the ALT_USB_HOST_HCCHAR7_ODDFRM register field value. */
36768 #define ALT_USB_HOST_HCCHAR7_ODDFRM_CLR_MSK 0xdfffffff
36769 /* The reset value of the ALT_USB_HOST_HCCHAR7_ODDFRM register field. */
36770 #define ALT_USB_HOST_HCCHAR7_ODDFRM_RESET 0x0
36771 /* Extracts the ALT_USB_HOST_HCCHAR7_ODDFRM field value from a register. */
36772 #define ALT_USB_HOST_HCCHAR7_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
36773 /* Produces a ALT_USB_HOST_HCCHAR7_ODDFRM register field value suitable for setting the register. */
36774 #define ALT_USB_HOST_HCCHAR7_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
36775 
36776 /*
36777  * Field : chdis
36778  *
36779  * Channel Disable (ChDis)
36780  *
36781  * The application sets this bit to stop transmitting/receiving data
36782  *
36783  * on a channel, even before the transfer For that channel is
36784  *
36785  * complete. The application must wait For the Channel Disabled
36786  *
36787  * interrupt before treating the channel as disabled.
36788  *
36789  * Field Enumeration Values:
36790  *
36791  * Enum | Value | Description
36792  * :-----------------------------------|:------|:----------------------------
36793  * ALT_USB_HOST_HCCHAR7_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
36794  * ALT_USB_HOST_HCCHAR7_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
36795  *
36796  * Field Access Macros:
36797  *
36798  */
36799 /*
36800  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHDIS
36801  *
36802  * Transmit/Recieve normal
36803  */
36804 #define ALT_USB_HOST_HCCHAR7_CHDIS_E_INACT 0x0
36805 /*
36806  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHDIS
36807  *
36808  * Stop transmitting/receiving
36809  */
36810 #define ALT_USB_HOST_HCCHAR7_CHDIS_E_ACT 0x1
36811 
36812 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */
36813 #define ALT_USB_HOST_HCCHAR7_CHDIS_LSB 30
36814 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */
36815 #define ALT_USB_HOST_HCCHAR7_CHDIS_MSB 30
36816 /* The width in bits of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */
36817 #define ALT_USB_HOST_HCCHAR7_CHDIS_WIDTH 1
36818 /* The mask used to set the ALT_USB_HOST_HCCHAR7_CHDIS register field value. */
36819 #define ALT_USB_HOST_HCCHAR7_CHDIS_SET_MSK 0x40000000
36820 /* The mask used to clear the ALT_USB_HOST_HCCHAR7_CHDIS register field value. */
36821 #define ALT_USB_HOST_HCCHAR7_CHDIS_CLR_MSK 0xbfffffff
36822 /* The reset value of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */
36823 #define ALT_USB_HOST_HCCHAR7_CHDIS_RESET 0x0
36824 /* Extracts the ALT_USB_HOST_HCCHAR7_CHDIS field value from a register. */
36825 #define ALT_USB_HOST_HCCHAR7_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
36826 /* Produces a ALT_USB_HOST_HCCHAR7_CHDIS register field value suitable for setting the register. */
36827 #define ALT_USB_HOST_HCCHAR7_CHDIS_SET(value) (((value) << 30) & 0x40000000)
36828 
36829 /*
36830  * Field : chena
36831  *
36832  * Channel Enable (ChEna)
36833  *
36834  * When Scatter/Gather mode is enabled
36835  *
36836  * 1'b0: Indicates that the descriptor structure is not yet ready.
36837  *
36838  * 1'b1: Indicates that the descriptor structure and data buffer with
36839  *
36840  * data is setup and this channel can access the descriptor.
36841  *
36842  * When Scatter/Gather mode is disabled
36843  *
36844  * This field is set by the application and cleared by the OTG host.
36845  *
36846  * 1'b0: Channel disabled
36847  *
36848  * 1'b1: Channel enabled
36849  *
36850  * Field Enumeration Values:
36851  *
36852  * Enum | Value | Description
36853  * :-----------------------------------|:------|:-------------------------------------------------
36854  * ALT_USB_HOST_HCCHAR7_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
36855  * : | | yet ready
36856  * ALT_USB_HOST_HCCHAR7_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
36857  * : | | data buffer with data is setup and this
36858  * : | | channel can access the descriptor
36859  *
36860  * Field Access Macros:
36861  *
36862  */
36863 /*
36864  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHENA
36865  *
36866  * Indicates that the descriptor structure is not yet ready
36867  */
36868 #define ALT_USB_HOST_HCCHAR7_CHENA_E_INACT 0x0
36869 /*
36870  * Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHENA
36871  *
36872  * Indicates that the descriptor structure and data buffer with data is
36873  * setup and this channel can access the descriptor
36874  */
36875 #define ALT_USB_HOST_HCCHAR7_CHENA_E_ACT 0x1
36876 
36877 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_CHENA register field. */
36878 #define ALT_USB_HOST_HCCHAR7_CHENA_LSB 31
36879 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_CHENA register field. */
36880 #define ALT_USB_HOST_HCCHAR7_CHENA_MSB 31
36881 /* The width in bits of the ALT_USB_HOST_HCCHAR7_CHENA register field. */
36882 #define ALT_USB_HOST_HCCHAR7_CHENA_WIDTH 1
36883 /* The mask used to set the ALT_USB_HOST_HCCHAR7_CHENA register field value. */
36884 #define ALT_USB_HOST_HCCHAR7_CHENA_SET_MSK 0x80000000
36885 /* The mask used to clear the ALT_USB_HOST_HCCHAR7_CHENA register field value. */
36886 #define ALT_USB_HOST_HCCHAR7_CHENA_CLR_MSK 0x7fffffff
36887 /* The reset value of the ALT_USB_HOST_HCCHAR7_CHENA register field. */
36888 #define ALT_USB_HOST_HCCHAR7_CHENA_RESET 0x0
36889 /* Extracts the ALT_USB_HOST_HCCHAR7_CHENA field value from a register. */
36890 #define ALT_USB_HOST_HCCHAR7_CHENA_GET(value) (((value) & 0x80000000) >> 31)
36891 /* Produces a ALT_USB_HOST_HCCHAR7_CHENA register field value suitable for setting the register. */
36892 #define ALT_USB_HOST_HCCHAR7_CHENA_SET(value) (((value) << 31) & 0x80000000)
36893 
36894 #ifndef __ASSEMBLY__
36895 /*
36896  * WARNING: The C register and register group struct declarations are provided for
36897  * convenience and illustrative purposes. They should, however, be used with
36898  * caution as the C language standard provides no guarantees about the alignment or
36899  * atomicity of device memory accesses. The recommended practice for writing
36900  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
36901  * alt_write_word() functions.
36902  *
36903  * The struct declaration for register ALT_USB_HOST_HCCHAR7.
36904  */
36905 struct ALT_USB_HOST_HCCHAR7_s
36906 {
36907  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR7_MPS */
36908  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR7_EPNUM */
36909  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR7_EPDIR */
36910  uint32_t : 1; /* *UNDEFINED* */
36911  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR7_LSPDDEV */
36912  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR7_EPTYPE */
36913  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR7_EC */
36914  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR7_DEVADDR */
36915  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR7_ODDFRM */
36916  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR7_CHDIS */
36917  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR7_CHENA */
36918 };
36919 
36920 /* The typedef declaration for register ALT_USB_HOST_HCCHAR7. */
36921 typedef volatile struct ALT_USB_HOST_HCCHAR7_s ALT_USB_HOST_HCCHAR7_t;
36922 #endif /* __ASSEMBLY__ */
36923 
36924 /* The reset value of the ALT_USB_HOST_HCCHAR7 register. */
36925 #define ALT_USB_HOST_HCCHAR7_RESET 0x00000000
36926 /* The byte offset of the ALT_USB_HOST_HCCHAR7 register from the beginning of the component. */
36927 #define ALT_USB_HOST_HCCHAR7_OFST 0x1e0
36928 /* The address of the ALT_USB_HOST_HCCHAR7 register. */
36929 #define ALT_USB_HOST_HCCHAR7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR7_OFST))
36930 
36931 /*
36932  * Register : hcsplt7
36933  *
36934  * Host Channel 7 Split Control Register
36935  *
36936  * Register Layout
36937  *
36938  * Bits | Access | Reset | Description
36939  * :--------|:-------|:------|:------------------------------
36940  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT7_PRTADDR
36941  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT7_HUBADDR
36942  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT7_XACTPOS
36943  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT7_COMPSPLT
36944  * [30:17] | ??? | 0x0 | *UNDEFINED*
36945  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT7_SPLTENA
36946  *
36947  */
36948 /*
36949  * Field : prtaddr
36950  *
36951  * Port Address (PrtAddr)
36952  *
36953  * This field is the port number of the recipient transaction
36954  *
36955  * translator.
36956  *
36957  * Field Access Macros:
36958  *
36959  */
36960 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */
36961 #define ALT_USB_HOST_HCSPLT7_PRTADDR_LSB 0
36962 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */
36963 #define ALT_USB_HOST_HCSPLT7_PRTADDR_MSB 6
36964 /* The width in bits of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */
36965 #define ALT_USB_HOST_HCSPLT7_PRTADDR_WIDTH 7
36966 /* The mask used to set the ALT_USB_HOST_HCSPLT7_PRTADDR register field value. */
36967 #define ALT_USB_HOST_HCSPLT7_PRTADDR_SET_MSK 0x0000007f
36968 /* The mask used to clear the ALT_USB_HOST_HCSPLT7_PRTADDR register field value. */
36969 #define ALT_USB_HOST_HCSPLT7_PRTADDR_CLR_MSK 0xffffff80
36970 /* The reset value of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */
36971 #define ALT_USB_HOST_HCSPLT7_PRTADDR_RESET 0x0
36972 /* Extracts the ALT_USB_HOST_HCSPLT7_PRTADDR field value from a register. */
36973 #define ALT_USB_HOST_HCSPLT7_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
36974 /* Produces a ALT_USB_HOST_HCSPLT7_PRTADDR register field value suitable for setting the register. */
36975 #define ALT_USB_HOST_HCSPLT7_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
36976 
36977 /*
36978  * Field : hubaddr
36979  *
36980  * Hub Address (HubAddr)
36981  *
36982  * This field holds the device address of the transaction translator's
36983  *
36984  * hub.
36985  *
36986  * Field Access Macros:
36987  *
36988  */
36989 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */
36990 #define ALT_USB_HOST_HCSPLT7_HUBADDR_LSB 7
36991 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */
36992 #define ALT_USB_HOST_HCSPLT7_HUBADDR_MSB 13
36993 /* The width in bits of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */
36994 #define ALT_USB_HOST_HCSPLT7_HUBADDR_WIDTH 7
36995 /* The mask used to set the ALT_USB_HOST_HCSPLT7_HUBADDR register field value. */
36996 #define ALT_USB_HOST_HCSPLT7_HUBADDR_SET_MSK 0x00003f80
36997 /* The mask used to clear the ALT_USB_HOST_HCSPLT7_HUBADDR register field value. */
36998 #define ALT_USB_HOST_HCSPLT7_HUBADDR_CLR_MSK 0xffffc07f
36999 /* The reset value of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */
37000 #define ALT_USB_HOST_HCSPLT7_HUBADDR_RESET 0x0
37001 /* Extracts the ALT_USB_HOST_HCSPLT7_HUBADDR field value from a register. */
37002 #define ALT_USB_HOST_HCSPLT7_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
37003 /* Produces a ALT_USB_HOST_HCSPLT7_HUBADDR register field value suitable for setting the register. */
37004 #define ALT_USB_HOST_HCSPLT7_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
37005 
37006 /*
37007  * Field : xactpos
37008  *
37009  * Transaction Position (XactPos)
37010  *
37011  * This field is used to determine whether to send all, first, middle,
37012  *
37013  * or last payloads with each OUT transaction.
37014  *
37015  * 2'b11: All. This is the entire data payload is of this transaction
37016  *
37017  * (which is less than or equal to 188 bytes).
37018  *
37019  * 2'b10: Begin. This is the first data payload of this transaction
37020  *
37021  * (which is larger than 188 bytes).
37022  *
37023  * 2'b00: Mid. This is the middle payload of this transaction
37024  *
37025  * (which is larger than 188 bytes).
37026  *
37027  * 2'b01: End. This is the last payload of this transaction (which
37028  *
37029  * is larger than 188 bytes).
37030  *
37031  * Field Enumeration Values:
37032  *
37033  * Enum | Value | Description
37034  * :--------------------------------------|:------|:------------------------------------------------
37035  * ALT_USB_HOST_HCSPLT7_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
37036  * : | | transaction (which is larger than 188 bytes)
37037  * ALT_USB_HOST_HCSPLT7_XACTPOS_E_END | 0x1 | End. This is the last payload of this
37038  * : | | transaction (which is larger than 188 bytes)
37039  * ALT_USB_HOST_HCSPLT7_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
37040  * : | | transaction (which is larger than 188 bytes)
37041  * ALT_USB_HOST_HCSPLT7_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
37042  * : | | transaction (which is less than or equal to 188
37043  * : | | bytes)
37044  *
37045  * Field Access Macros:
37046  *
37047  */
37048 /*
37049  * Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS
37050  *
37051  * Mid. This is the middle payload of this transaction (which is larger than 188
37052  * bytes)
37053  */
37054 #define ALT_USB_HOST_HCSPLT7_XACTPOS_E_MIDDLE 0x0
37055 /*
37056  * Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS
37057  *
37058  * End. This is the last payload of this transaction (which is larger than 188
37059  * bytes)
37060  */
37061 #define ALT_USB_HOST_HCSPLT7_XACTPOS_E_END 0x1
37062 /*
37063  * Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS
37064  *
37065  * Begin. This is the first data payload of this transaction (which is larger than
37066  * 188 bytes)
37067  */
37068 #define ALT_USB_HOST_HCSPLT7_XACTPOS_E_BEGIN 0x2
37069 /*
37070  * Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS
37071  *
37072  * All. This is the entire data payload is of this transaction (which is less than
37073  * or equal to 188 bytes)
37074  */
37075 #define ALT_USB_HOST_HCSPLT7_XACTPOS_E_ALL 0x3
37076 
37077 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */
37078 #define ALT_USB_HOST_HCSPLT7_XACTPOS_LSB 14
37079 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */
37080 #define ALT_USB_HOST_HCSPLT7_XACTPOS_MSB 15
37081 /* The width in bits of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */
37082 #define ALT_USB_HOST_HCSPLT7_XACTPOS_WIDTH 2
37083 /* The mask used to set the ALT_USB_HOST_HCSPLT7_XACTPOS register field value. */
37084 #define ALT_USB_HOST_HCSPLT7_XACTPOS_SET_MSK 0x0000c000
37085 /* The mask used to clear the ALT_USB_HOST_HCSPLT7_XACTPOS register field value. */
37086 #define ALT_USB_HOST_HCSPLT7_XACTPOS_CLR_MSK 0xffff3fff
37087 /* The reset value of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */
37088 #define ALT_USB_HOST_HCSPLT7_XACTPOS_RESET 0x0
37089 /* Extracts the ALT_USB_HOST_HCSPLT7_XACTPOS field value from a register. */
37090 #define ALT_USB_HOST_HCSPLT7_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
37091 /* Produces a ALT_USB_HOST_HCSPLT7_XACTPOS register field value suitable for setting the register. */
37092 #define ALT_USB_HOST_HCSPLT7_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
37093 
37094 /*
37095  * Field : compsplt
37096  *
37097  * Do Complete Split (CompSplt)
37098  *
37099  * The application sets this field to request the OTG host to perform
37100  *
37101  * a complete split transaction.
37102  *
37103  * Field Enumeration Values:
37104  *
37105  * Enum | Value | Description
37106  * :----------------------------------------|:------|:---------------------
37107  * ALT_USB_HOST_HCSPLT7_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
37108  * ALT_USB_HOST_HCSPLT7_COMPSPLT_E_SPLIT | 0x1 | Split transaction
37109  *
37110  * Field Access Macros:
37111  *
37112  */
37113 /*
37114  * Enumerated value for register field ALT_USB_HOST_HCSPLT7_COMPSPLT
37115  *
37116  * No split transaction
37117  */
37118 #define ALT_USB_HOST_HCSPLT7_COMPSPLT_E_NOSPLIT 0x0
37119 /*
37120  * Enumerated value for register field ALT_USB_HOST_HCSPLT7_COMPSPLT
37121  *
37122  * Split transaction
37123  */
37124 #define ALT_USB_HOST_HCSPLT7_COMPSPLT_E_SPLIT 0x1
37125 
37126 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */
37127 #define ALT_USB_HOST_HCSPLT7_COMPSPLT_LSB 16
37128 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */
37129 #define ALT_USB_HOST_HCSPLT7_COMPSPLT_MSB 16
37130 /* The width in bits of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */
37131 #define ALT_USB_HOST_HCSPLT7_COMPSPLT_WIDTH 1
37132 /* The mask used to set the ALT_USB_HOST_HCSPLT7_COMPSPLT register field value. */
37133 #define ALT_USB_HOST_HCSPLT7_COMPSPLT_SET_MSK 0x00010000
37134 /* The mask used to clear the ALT_USB_HOST_HCSPLT7_COMPSPLT register field value. */
37135 #define ALT_USB_HOST_HCSPLT7_COMPSPLT_CLR_MSK 0xfffeffff
37136 /* The reset value of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */
37137 #define ALT_USB_HOST_HCSPLT7_COMPSPLT_RESET 0x0
37138 /* Extracts the ALT_USB_HOST_HCSPLT7_COMPSPLT field value from a register. */
37139 #define ALT_USB_HOST_HCSPLT7_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
37140 /* Produces a ALT_USB_HOST_HCSPLT7_COMPSPLT register field value suitable for setting the register. */
37141 #define ALT_USB_HOST_HCSPLT7_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
37142 
37143 /*
37144  * Field : spltena
37145  *
37146  * Split Enable (SpltEna)
37147  *
37148  * The application sets this field to indicate that this channel is
37149  *
37150  * enabled to perform split transactions.
37151  *
37152  * Field Enumeration Values:
37153  *
37154  * Enum | Value | Description
37155  * :------------------------------------|:------|:------------------
37156  * ALT_USB_HOST_HCSPLT7_SPLTENA_E_DISD | 0x0 | Split not enabled
37157  * ALT_USB_HOST_HCSPLT7_SPLTENA_E_END | 0x1 | Split enabled
37158  *
37159  * Field Access Macros:
37160  *
37161  */
37162 /*
37163  * Enumerated value for register field ALT_USB_HOST_HCSPLT7_SPLTENA
37164  *
37165  * Split not enabled
37166  */
37167 #define ALT_USB_HOST_HCSPLT7_SPLTENA_E_DISD 0x0
37168 /*
37169  * Enumerated value for register field ALT_USB_HOST_HCSPLT7_SPLTENA
37170  *
37171  * Split enabled
37172  */
37173 #define ALT_USB_HOST_HCSPLT7_SPLTENA_E_END 0x1
37174 
37175 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */
37176 #define ALT_USB_HOST_HCSPLT7_SPLTENA_LSB 31
37177 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */
37178 #define ALT_USB_HOST_HCSPLT7_SPLTENA_MSB 31
37179 /* The width in bits of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */
37180 #define ALT_USB_HOST_HCSPLT7_SPLTENA_WIDTH 1
37181 /* The mask used to set the ALT_USB_HOST_HCSPLT7_SPLTENA register field value. */
37182 #define ALT_USB_HOST_HCSPLT7_SPLTENA_SET_MSK 0x80000000
37183 /* The mask used to clear the ALT_USB_HOST_HCSPLT7_SPLTENA register field value. */
37184 #define ALT_USB_HOST_HCSPLT7_SPLTENA_CLR_MSK 0x7fffffff
37185 /* The reset value of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */
37186 #define ALT_USB_HOST_HCSPLT7_SPLTENA_RESET 0x0
37187 /* Extracts the ALT_USB_HOST_HCSPLT7_SPLTENA field value from a register. */
37188 #define ALT_USB_HOST_HCSPLT7_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
37189 /* Produces a ALT_USB_HOST_HCSPLT7_SPLTENA register field value suitable for setting the register. */
37190 #define ALT_USB_HOST_HCSPLT7_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
37191 
37192 #ifndef __ASSEMBLY__
37193 /*
37194  * WARNING: The C register and register group struct declarations are provided for
37195  * convenience and illustrative purposes. They should, however, be used with
37196  * caution as the C language standard provides no guarantees about the alignment or
37197  * atomicity of device memory accesses. The recommended practice for writing
37198  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
37199  * alt_write_word() functions.
37200  *
37201  * The struct declaration for register ALT_USB_HOST_HCSPLT7.
37202  */
37203 struct ALT_USB_HOST_HCSPLT7_s
37204 {
37205  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT7_PRTADDR */
37206  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT7_HUBADDR */
37207  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT7_XACTPOS */
37208  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT7_COMPSPLT */
37209  uint32_t : 14; /* *UNDEFINED* */
37210  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT7_SPLTENA */
37211 };
37212 
37213 /* The typedef declaration for register ALT_USB_HOST_HCSPLT7. */
37214 typedef volatile struct ALT_USB_HOST_HCSPLT7_s ALT_USB_HOST_HCSPLT7_t;
37215 #endif /* __ASSEMBLY__ */
37216 
37217 /* The reset value of the ALT_USB_HOST_HCSPLT7 register. */
37218 #define ALT_USB_HOST_HCSPLT7_RESET 0x00000000
37219 /* The byte offset of the ALT_USB_HOST_HCSPLT7 register from the beginning of the component. */
37220 #define ALT_USB_HOST_HCSPLT7_OFST 0x1e4
37221 /* The address of the ALT_USB_HOST_HCSPLT7 register. */
37222 #define ALT_USB_HOST_HCSPLT7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT7_OFST))
37223 
37224 /*
37225  * Register : hcint7
37226  *
37227  * Host Channel 7 Interrupt Register
37228  *
37229  * Register Layout
37230  *
37231  * Bits | Access | Reset | Description
37232  * :--------|:-------|:------|:--------------------------------------
37233  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT7_XFERCOMPL
37234  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT7_CHHLTD
37235  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT7_AHBERR
37236  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT7_STALL
37237  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT7_NAK
37238  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT7_ACK
37239  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT7_NYET
37240  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT7_XACTERR
37241  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT7_BBLERR
37242  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT7_FRMOVRUN
37243  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT7_DATATGLERR
37244  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT7_BNAINTR
37245  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT7_XCS_XACT_ERR
37246  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR
37247  * [31:14] | ??? | 0x0 | *UNDEFINED*
37248  *
37249  */
37250 /*
37251  * Field : xfercompl
37252  *
37253  * Transfer Completed (XferCompl)
37254  *
37255  * Transfer completed normally without any errors.This bit can be set only by the
37256  * core and the application should write 1 to clear it.
37257  *
37258  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
37259  *
37260  * completed with IOC bit set in its descriptor.
37261  *
37262  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
37263  * without
37264  *
37265  * any errors.
37266  *
37267  * Field Enumeration Values:
37268  *
37269  * Enum | Value | Description
37270  * :--------------------------------------|:------|:-----------------------------------------------
37271  * ALT_USB_HOST_HCINT7_XFERCOMPL_E_INACT | 0x0 | No transfer
37272  * ALT_USB_HOST_HCINT7_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
37273  *
37274  * Field Access Macros:
37275  *
37276  */
37277 /*
37278  * Enumerated value for register field ALT_USB_HOST_HCINT7_XFERCOMPL
37279  *
37280  * No transfer
37281  */
37282 #define ALT_USB_HOST_HCINT7_XFERCOMPL_E_INACT 0x0
37283 /*
37284  * Enumerated value for register field ALT_USB_HOST_HCINT7_XFERCOMPL
37285  *
37286  * Transfer completed normally without any errors
37287  */
37288 #define ALT_USB_HOST_HCINT7_XFERCOMPL_E_ACT 0x1
37289 
37290 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */
37291 #define ALT_USB_HOST_HCINT7_XFERCOMPL_LSB 0
37292 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */
37293 #define ALT_USB_HOST_HCINT7_XFERCOMPL_MSB 0
37294 /* The width in bits of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */
37295 #define ALT_USB_HOST_HCINT7_XFERCOMPL_WIDTH 1
37296 /* The mask used to set the ALT_USB_HOST_HCINT7_XFERCOMPL register field value. */
37297 #define ALT_USB_HOST_HCINT7_XFERCOMPL_SET_MSK 0x00000001
37298 /* The mask used to clear the ALT_USB_HOST_HCINT7_XFERCOMPL register field value. */
37299 #define ALT_USB_HOST_HCINT7_XFERCOMPL_CLR_MSK 0xfffffffe
37300 /* The reset value of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */
37301 #define ALT_USB_HOST_HCINT7_XFERCOMPL_RESET 0x0
37302 /* Extracts the ALT_USB_HOST_HCINT7_XFERCOMPL field value from a register. */
37303 #define ALT_USB_HOST_HCINT7_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
37304 /* Produces a ALT_USB_HOST_HCINT7_XFERCOMPL register field value suitable for setting the register. */
37305 #define ALT_USB_HOST_HCINT7_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
37306 
37307 /*
37308  * Field : chhltd
37309  *
37310  * Channel Halted (ChHltd)
37311  *
37312  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
37313  * either because of any USB transaction error or in response to disable request by
37314  * the application or because of a completed transfer.
37315  *
37316  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
37317  * the following
37318  *
37319  * . EOL being set in descriptor
37320  *
37321  * . AHB error
37322  *
37323  * . Excessive transaction errors
37324  *
37325  * . Babble
37326  *
37327  * . Stall
37328  *
37329  * Field Enumeration Values:
37330  *
37331  * Enum | Value | Description
37332  * :-----------------------------------|:------|:-------------------
37333  * ALT_USB_HOST_HCINT7_CHHLTD_E_INACT | 0x0 | Channel not halted
37334  * ALT_USB_HOST_HCINT7_CHHLTD_E_ACT | 0x1 | Channel Halted
37335  *
37336  * Field Access Macros:
37337  *
37338  */
37339 /*
37340  * Enumerated value for register field ALT_USB_HOST_HCINT7_CHHLTD
37341  *
37342  * Channel not halted
37343  */
37344 #define ALT_USB_HOST_HCINT7_CHHLTD_E_INACT 0x0
37345 /*
37346  * Enumerated value for register field ALT_USB_HOST_HCINT7_CHHLTD
37347  *
37348  * Channel Halted
37349  */
37350 #define ALT_USB_HOST_HCINT7_CHHLTD_E_ACT 0x1
37351 
37352 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_CHHLTD register field. */
37353 #define ALT_USB_HOST_HCINT7_CHHLTD_LSB 1
37354 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_CHHLTD register field. */
37355 #define ALT_USB_HOST_HCINT7_CHHLTD_MSB 1
37356 /* The width in bits of the ALT_USB_HOST_HCINT7_CHHLTD register field. */
37357 #define ALT_USB_HOST_HCINT7_CHHLTD_WIDTH 1
37358 /* The mask used to set the ALT_USB_HOST_HCINT7_CHHLTD register field value. */
37359 #define ALT_USB_HOST_HCINT7_CHHLTD_SET_MSK 0x00000002
37360 /* The mask used to clear the ALT_USB_HOST_HCINT7_CHHLTD register field value. */
37361 #define ALT_USB_HOST_HCINT7_CHHLTD_CLR_MSK 0xfffffffd
37362 /* The reset value of the ALT_USB_HOST_HCINT7_CHHLTD register field. */
37363 #define ALT_USB_HOST_HCINT7_CHHLTD_RESET 0x0
37364 /* Extracts the ALT_USB_HOST_HCINT7_CHHLTD field value from a register. */
37365 #define ALT_USB_HOST_HCINT7_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
37366 /* Produces a ALT_USB_HOST_HCINT7_CHHLTD register field value suitable for setting the register. */
37367 #define ALT_USB_HOST_HCINT7_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
37368 
37369 /*
37370  * Field : ahberr
37371  *
37372  * AHB Error (AHBErr)
37373  *
37374  * This is generated only in Internal DMA mode when there is an
37375  *
37376  * AHB error during AHB read/write. The application can read the
37377  *
37378  * corresponding channel's DMA address register to get the error
37379  *
37380  * address.
37381  *
37382  * Field Enumeration Values:
37383  *
37384  * Enum | Value | Description
37385  * :-----------------------------------|:------|:--------------------------------
37386  * ALT_USB_HOST_HCINT7_AHBERR_E_INACT | 0x0 | No AHB error
37387  * ALT_USB_HOST_HCINT7_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
37388  *
37389  * Field Access Macros:
37390  *
37391  */
37392 /*
37393  * Enumerated value for register field ALT_USB_HOST_HCINT7_AHBERR
37394  *
37395  * No AHB error
37396  */
37397 #define ALT_USB_HOST_HCINT7_AHBERR_E_INACT 0x0
37398 /*
37399  * Enumerated value for register field ALT_USB_HOST_HCINT7_AHBERR
37400  *
37401  * AHB error during AHB read/write
37402  */
37403 #define ALT_USB_HOST_HCINT7_AHBERR_E_ACT 0x1
37404 
37405 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_AHBERR register field. */
37406 #define ALT_USB_HOST_HCINT7_AHBERR_LSB 2
37407 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_AHBERR register field. */
37408 #define ALT_USB_HOST_HCINT7_AHBERR_MSB 2
37409 /* The width in bits of the ALT_USB_HOST_HCINT7_AHBERR register field. */
37410 #define ALT_USB_HOST_HCINT7_AHBERR_WIDTH 1
37411 /* The mask used to set the ALT_USB_HOST_HCINT7_AHBERR register field value. */
37412 #define ALT_USB_HOST_HCINT7_AHBERR_SET_MSK 0x00000004
37413 /* The mask used to clear the ALT_USB_HOST_HCINT7_AHBERR register field value. */
37414 #define ALT_USB_HOST_HCINT7_AHBERR_CLR_MSK 0xfffffffb
37415 /* The reset value of the ALT_USB_HOST_HCINT7_AHBERR register field. */
37416 #define ALT_USB_HOST_HCINT7_AHBERR_RESET 0x0
37417 /* Extracts the ALT_USB_HOST_HCINT7_AHBERR field value from a register. */
37418 #define ALT_USB_HOST_HCINT7_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
37419 /* Produces a ALT_USB_HOST_HCINT7_AHBERR register field value suitable for setting the register. */
37420 #define ALT_USB_HOST_HCINT7_AHBERR_SET(value) (((value) << 2) & 0x00000004)
37421 
37422 /*
37423  * Field : stall
37424  *
37425  * STALL Response Received Interrupt (STALL)
37426  *
37427  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
37428  *
37429  * in the core.This bit can be set only by the core and the application should
37430  * write 1 to clear
37431  *
37432  * it.
37433  *
37434  * Field Enumeration Values:
37435  *
37436  * Enum | Value | Description
37437  * :----------------------------------|:------|:-------------------
37438  * ALT_USB_HOST_HCINT7_STALL_E_INACT | 0x0 | No Stall Interrupt
37439  * ALT_USB_HOST_HCINT7_STALL_E_ACT | 0x1 | Stall Interrupt
37440  *
37441  * Field Access Macros:
37442  *
37443  */
37444 /*
37445  * Enumerated value for register field ALT_USB_HOST_HCINT7_STALL
37446  *
37447  * No Stall Interrupt
37448  */
37449 #define ALT_USB_HOST_HCINT7_STALL_E_INACT 0x0
37450 /*
37451  * Enumerated value for register field ALT_USB_HOST_HCINT7_STALL
37452  *
37453  * Stall Interrupt
37454  */
37455 #define ALT_USB_HOST_HCINT7_STALL_E_ACT 0x1
37456 
37457 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_STALL register field. */
37458 #define ALT_USB_HOST_HCINT7_STALL_LSB 3
37459 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_STALL register field. */
37460 #define ALT_USB_HOST_HCINT7_STALL_MSB 3
37461 /* The width in bits of the ALT_USB_HOST_HCINT7_STALL register field. */
37462 #define ALT_USB_HOST_HCINT7_STALL_WIDTH 1
37463 /* The mask used to set the ALT_USB_HOST_HCINT7_STALL register field value. */
37464 #define ALT_USB_HOST_HCINT7_STALL_SET_MSK 0x00000008
37465 /* The mask used to clear the ALT_USB_HOST_HCINT7_STALL register field value. */
37466 #define ALT_USB_HOST_HCINT7_STALL_CLR_MSK 0xfffffff7
37467 /* The reset value of the ALT_USB_HOST_HCINT7_STALL register field. */
37468 #define ALT_USB_HOST_HCINT7_STALL_RESET 0x0
37469 /* Extracts the ALT_USB_HOST_HCINT7_STALL field value from a register. */
37470 #define ALT_USB_HOST_HCINT7_STALL_GET(value) (((value) & 0x00000008) >> 3)
37471 /* Produces a ALT_USB_HOST_HCINT7_STALL register field value suitable for setting the register. */
37472 #define ALT_USB_HOST_HCINT7_STALL_SET(value) (((value) << 3) & 0x00000008)
37473 
37474 /*
37475  * Field : nak
37476  *
37477  * NAK Response Received Interrupt (NAK)
37478  *
37479  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
37480  *
37481  * in the core.This bit can be set only by the core and the application should
37482  * write 1 to clear
37483  *
37484  * it.
37485  *
37486  * Field Enumeration Values:
37487  *
37488  * Enum | Value | Description
37489  * :--------------------------------|:------|:-----------------------------------
37490  * ALT_USB_HOST_HCINT7_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
37491  * ALT_USB_HOST_HCINT7_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
37492  *
37493  * Field Access Macros:
37494  *
37495  */
37496 /*
37497  * Enumerated value for register field ALT_USB_HOST_HCINT7_NAK
37498  *
37499  * No NAK Response Received Interrupt
37500  */
37501 #define ALT_USB_HOST_HCINT7_NAK_E_INACT 0x0
37502 /*
37503  * Enumerated value for register field ALT_USB_HOST_HCINT7_NAK
37504  *
37505  * NAK Response Received Interrupt
37506  */
37507 #define ALT_USB_HOST_HCINT7_NAK_E_ACT 0x1
37508 
37509 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_NAK register field. */
37510 #define ALT_USB_HOST_HCINT7_NAK_LSB 4
37511 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_NAK register field. */
37512 #define ALT_USB_HOST_HCINT7_NAK_MSB 4
37513 /* The width in bits of the ALT_USB_HOST_HCINT7_NAK register field. */
37514 #define ALT_USB_HOST_HCINT7_NAK_WIDTH 1
37515 /* The mask used to set the ALT_USB_HOST_HCINT7_NAK register field value. */
37516 #define ALT_USB_HOST_HCINT7_NAK_SET_MSK 0x00000010
37517 /* The mask used to clear the ALT_USB_HOST_HCINT7_NAK register field value. */
37518 #define ALT_USB_HOST_HCINT7_NAK_CLR_MSK 0xffffffef
37519 /* The reset value of the ALT_USB_HOST_HCINT7_NAK register field. */
37520 #define ALT_USB_HOST_HCINT7_NAK_RESET 0x0
37521 /* Extracts the ALT_USB_HOST_HCINT7_NAK field value from a register. */
37522 #define ALT_USB_HOST_HCINT7_NAK_GET(value) (((value) & 0x00000010) >> 4)
37523 /* Produces a ALT_USB_HOST_HCINT7_NAK register field value suitable for setting the register. */
37524 #define ALT_USB_HOST_HCINT7_NAK_SET(value) (((value) << 4) & 0x00000010)
37525 
37526 /*
37527  * Field : ack
37528  *
37529  * ACK Response Received/Transmitted Interrupt (ACK)
37530  *
37531  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
37532  *
37533  * in the core.This bit can be set only by the core and the application should
37534  * write 1 to clear
37535  *
37536  * it.
37537  *
37538  * Field Enumeration Values:
37539  *
37540  * Enum | Value | Description
37541  * :--------------------------------|:------|:-----------------------------------------------
37542  * ALT_USB_HOST_HCINT7_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
37543  * ALT_USB_HOST_HCINT7_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
37544  *
37545  * Field Access Macros:
37546  *
37547  */
37548 /*
37549  * Enumerated value for register field ALT_USB_HOST_HCINT7_ACK
37550  *
37551  * No ACK Response Received Transmitted Interrupt
37552  */
37553 #define ALT_USB_HOST_HCINT7_ACK_E_INACT 0x0
37554 /*
37555  * Enumerated value for register field ALT_USB_HOST_HCINT7_ACK
37556  *
37557  * ACK Response Received Transmitted Interrup
37558  */
37559 #define ALT_USB_HOST_HCINT7_ACK_E_ACT 0x1
37560 
37561 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_ACK register field. */
37562 #define ALT_USB_HOST_HCINT7_ACK_LSB 5
37563 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_ACK register field. */
37564 #define ALT_USB_HOST_HCINT7_ACK_MSB 5
37565 /* The width in bits of the ALT_USB_HOST_HCINT7_ACK register field. */
37566 #define ALT_USB_HOST_HCINT7_ACK_WIDTH 1
37567 /* The mask used to set the ALT_USB_HOST_HCINT7_ACK register field value. */
37568 #define ALT_USB_HOST_HCINT7_ACK_SET_MSK 0x00000020
37569 /* The mask used to clear the ALT_USB_HOST_HCINT7_ACK register field value. */
37570 #define ALT_USB_HOST_HCINT7_ACK_CLR_MSK 0xffffffdf
37571 /* The reset value of the ALT_USB_HOST_HCINT7_ACK register field. */
37572 #define ALT_USB_HOST_HCINT7_ACK_RESET 0x0
37573 /* Extracts the ALT_USB_HOST_HCINT7_ACK field value from a register. */
37574 #define ALT_USB_HOST_HCINT7_ACK_GET(value) (((value) & 0x00000020) >> 5)
37575 /* Produces a ALT_USB_HOST_HCINT7_ACK register field value suitable for setting the register. */
37576 #define ALT_USB_HOST_HCINT7_ACK_SET(value) (((value) << 5) & 0x00000020)
37577 
37578 /*
37579  * Field : nyet
37580  *
37581  * NYET Response Received Interrupt (NYET)
37582  *
37583  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
37584  *
37585  * in the core.This bit can be set only by the core and the application should
37586  * write 1 to clear
37587  *
37588  * it.
37589  *
37590  * Field Enumeration Values:
37591  *
37592  * Enum | Value | Description
37593  * :---------------------------------|:------|:------------------------------------
37594  * ALT_USB_HOST_HCINT7_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
37595  * ALT_USB_HOST_HCINT7_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
37596  *
37597  * Field Access Macros:
37598  *
37599  */
37600 /*
37601  * Enumerated value for register field ALT_USB_HOST_HCINT7_NYET
37602  *
37603  * No NYET Response Received Interrupt
37604  */
37605 #define ALT_USB_HOST_HCINT7_NYET_E_INACT 0x0
37606 /*
37607  * Enumerated value for register field ALT_USB_HOST_HCINT7_NYET
37608  *
37609  * NYET Response Received Interrupt
37610  */
37611 #define ALT_USB_HOST_HCINT7_NYET_E_ACT 0x1
37612 
37613 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_NYET register field. */
37614 #define ALT_USB_HOST_HCINT7_NYET_LSB 6
37615 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_NYET register field. */
37616 #define ALT_USB_HOST_HCINT7_NYET_MSB 6
37617 /* The width in bits of the ALT_USB_HOST_HCINT7_NYET register field. */
37618 #define ALT_USB_HOST_HCINT7_NYET_WIDTH 1
37619 /* The mask used to set the ALT_USB_HOST_HCINT7_NYET register field value. */
37620 #define ALT_USB_HOST_HCINT7_NYET_SET_MSK 0x00000040
37621 /* The mask used to clear the ALT_USB_HOST_HCINT7_NYET register field value. */
37622 #define ALT_USB_HOST_HCINT7_NYET_CLR_MSK 0xffffffbf
37623 /* The reset value of the ALT_USB_HOST_HCINT7_NYET register field. */
37624 #define ALT_USB_HOST_HCINT7_NYET_RESET 0x0
37625 /* Extracts the ALT_USB_HOST_HCINT7_NYET field value from a register. */
37626 #define ALT_USB_HOST_HCINT7_NYET_GET(value) (((value) & 0x00000040) >> 6)
37627 /* Produces a ALT_USB_HOST_HCINT7_NYET register field value suitable for setting the register. */
37628 #define ALT_USB_HOST_HCINT7_NYET_SET(value) (((value) << 6) & 0x00000040)
37629 
37630 /*
37631  * Field : xacterr
37632  *
37633  * Transaction Error (XactErr)
37634  *
37635  * Indicates one of the following errors occurred on the USB.
37636  *
37637  * CRC check failure
37638  *
37639  * Timeout
37640  *
37641  * Bit stuff error
37642  *
37643  * False EOP
37644  *
37645  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
37646  *
37647  * in the core.This bit can be set only by the core and the application should
37648  * write 1 to clear
37649  *
37650  * it.
37651  *
37652  * Field Enumeration Values:
37653  *
37654  * Enum | Value | Description
37655  * :------------------------------------|:------|:---------------------
37656  * ALT_USB_HOST_HCINT7_XACTERR_E_INACT | 0x0 | No Transaction Error
37657  * ALT_USB_HOST_HCINT7_XACTERR_E_ACT | 0x1 | Transaction Error
37658  *
37659  * Field Access Macros:
37660  *
37661  */
37662 /*
37663  * Enumerated value for register field ALT_USB_HOST_HCINT7_XACTERR
37664  *
37665  * No Transaction Error
37666  */
37667 #define ALT_USB_HOST_HCINT7_XACTERR_E_INACT 0x0
37668 /*
37669  * Enumerated value for register field ALT_USB_HOST_HCINT7_XACTERR
37670  *
37671  * Transaction Error
37672  */
37673 #define ALT_USB_HOST_HCINT7_XACTERR_E_ACT 0x1
37674 
37675 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_XACTERR register field. */
37676 #define ALT_USB_HOST_HCINT7_XACTERR_LSB 7
37677 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_XACTERR register field. */
37678 #define ALT_USB_HOST_HCINT7_XACTERR_MSB 7
37679 /* The width in bits of the ALT_USB_HOST_HCINT7_XACTERR register field. */
37680 #define ALT_USB_HOST_HCINT7_XACTERR_WIDTH 1
37681 /* The mask used to set the ALT_USB_HOST_HCINT7_XACTERR register field value. */
37682 #define ALT_USB_HOST_HCINT7_XACTERR_SET_MSK 0x00000080
37683 /* The mask used to clear the ALT_USB_HOST_HCINT7_XACTERR register field value. */
37684 #define ALT_USB_HOST_HCINT7_XACTERR_CLR_MSK 0xffffff7f
37685 /* The reset value of the ALT_USB_HOST_HCINT7_XACTERR register field. */
37686 #define ALT_USB_HOST_HCINT7_XACTERR_RESET 0x0
37687 /* Extracts the ALT_USB_HOST_HCINT7_XACTERR field value from a register. */
37688 #define ALT_USB_HOST_HCINT7_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
37689 /* Produces a ALT_USB_HOST_HCINT7_XACTERR register field value suitable for setting the register. */
37690 #define ALT_USB_HOST_HCINT7_XACTERR_SET(value) (((value) << 7) & 0x00000080)
37691 
37692 /*
37693  * Field : bblerr
37694  *
37695  * Babble Error (BblErr)
37696  *
37697  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
37698  *
37699  * in the core..This bit can be set only by the core and the application should
37700  * write 1 to clear
37701  *
37702  * it.
37703  *
37704  * Field Enumeration Values:
37705  *
37706  * Enum | Value | Description
37707  * :-----------------------------------|:------|:----------------
37708  * ALT_USB_HOST_HCINT7_BBLERR_E_INACT | 0x0 | No Babble Error
37709  * ALT_USB_HOST_HCINT7_BBLERR_E_ACT | 0x1 | Babble Error
37710  *
37711  * Field Access Macros:
37712  *
37713  */
37714 /*
37715  * Enumerated value for register field ALT_USB_HOST_HCINT7_BBLERR
37716  *
37717  * No Babble Error
37718  */
37719 #define ALT_USB_HOST_HCINT7_BBLERR_E_INACT 0x0
37720 /*
37721  * Enumerated value for register field ALT_USB_HOST_HCINT7_BBLERR
37722  *
37723  * Babble Error
37724  */
37725 #define ALT_USB_HOST_HCINT7_BBLERR_E_ACT 0x1
37726 
37727 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_BBLERR register field. */
37728 #define ALT_USB_HOST_HCINT7_BBLERR_LSB 8
37729 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_BBLERR register field. */
37730 #define ALT_USB_HOST_HCINT7_BBLERR_MSB 8
37731 /* The width in bits of the ALT_USB_HOST_HCINT7_BBLERR register field. */
37732 #define ALT_USB_HOST_HCINT7_BBLERR_WIDTH 1
37733 /* The mask used to set the ALT_USB_HOST_HCINT7_BBLERR register field value. */
37734 #define ALT_USB_HOST_HCINT7_BBLERR_SET_MSK 0x00000100
37735 /* The mask used to clear the ALT_USB_HOST_HCINT7_BBLERR register field value. */
37736 #define ALT_USB_HOST_HCINT7_BBLERR_CLR_MSK 0xfffffeff
37737 /* The reset value of the ALT_USB_HOST_HCINT7_BBLERR register field. */
37738 #define ALT_USB_HOST_HCINT7_BBLERR_RESET 0x0
37739 /* Extracts the ALT_USB_HOST_HCINT7_BBLERR field value from a register. */
37740 #define ALT_USB_HOST_HCINT7_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
37741 /* Produces a ALT_USB_HOST_HCINT7_BBLERR register field value suitable for setting the register. */
37742 #define ALT_USB_HOST_HCINT7_BBLERR_SET(value) (((value) << 8) & 0x00000100)
37743 
37744 /*
37745  * Field : frmovrun
37746  *
37747  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
37748  * bit is masked
37749  *
37750  * in the core.This bit can be set only by the core and the application should
37751  * write 1 to clear
37752  *
37753  * it.
37754  *
37755  * Field Enumeration Values:
37756  *
37757  * Enum | Value | Description
37758  * :-------------------------------------|:------|:-----------------
37759  * ALT_USB_HOST_HCINT7_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
37760  * ALT_USB_HOST_HCINT7_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
37761  *
37762  * Field Access Macros:
37763  *
37764  */
37765 /*
37766  * Enumerated value for register field ALT_USB_HOST_HCINT7_FRMOVRUN
37767  *
37768  * No Frame Overrun
37769  */
37770 #define ALT_USB_HOST_HCINT7_FRMOVRUN_E_INACT 0x0
37771 /*
37772  * Enumerated value for register field ALT_USB_HOST_HCINT7_FRMOVRUN
37773  *
37774  * Frame Overrun
37775  */
37776 #define ALT_USB_HOST_HCINT7_FRMOVRUN_E_ACT 0x1
37777 
37778 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */
37779 #define ALT_USB_HOST_HCINT7_FRMOVRUN_LSB 9
37780 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */
37781 #define ALT_USB_HOST_HCINT7_FRMOVRUN_MSB 9
37782 /* The width in bits of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */
37783 #define ALT_USB_HOST_HCINT7_FRMOVRUN_WIDTH 1
37784 /* The mask used to set the ALT_USB_HOST_HCINT7_FRMOVRUN register field value. */
37785 #define ALT_USB_HOST_HCINT7_FRMOVRUN_SET_MSK 0x00000200
37786 /* The mask used to clear the ALT_USB_HOST_HCINT7_FRMOVRUN register field value. */
37787 #define ALT_USB_HOST_HCINT7_FRMOVRUN_CLR_MSK 0xfffffdff
37788 /* The reset value of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */
37789 #define ALT_USB_HOST_HCINT7_FRMOVRUN_RESET 0x0
37790 /* Extracts the ALT_USB_HOST_HCINT7_FRMOVRUN field value from a register. */
37791 #define ALT_USB_HOST_HCINT7_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
37792 /* Produces a ALT_USB_HOST_HCINT7_FRMOVRUN register field value suitable for setting the register. */
37793 #define ALT_USB_HOST_HCINT7_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
37794 
37795 /*
37796  * Field : datatglerr
37797  *
37798  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
37799  * application should write 1 to clear
37800  *
37801  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
37802  *
37803  * in the core.
37804  *
37805  * Field Enumeration Values:
37806  *
37807  * Enum | Value | Description
37808  * :---------------------------------------|:------|:---------------------
37809  * ALT_USB_HOST_HCINT7_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
37810  * ALT_USB_HOST_HCINT7_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
37811  *
37812  * Field Access Macros:
37813  *
37814  */
37815 /*
37816  * Enumerated value for register field ALT_USB_HOST_HCINT7_DATATGLERR
37817  *
37818  * No Data Toggle Error
37819  */
37820 #define ALT_USB_HOST_HCINT7_DATATGLERR_E_INACT 0x0
37821 /*
37822  * Enumerated value for register field ALT_USB_HOST_HCINT7_DATATGLERR
37823  *
37824  * Data Toggle Error
37825  */
37826 #define ALT_USB_HOST_HCINT7_DATATGLERR_E_ACT 0x1
37827 
37828 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */
37829 #define ALT_USB_HOST_HCINT7_DATATGLERR_LSB 10
37830 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */
37831 #define ALT_USB_HOST_HCINT7_DATATGLERR_MSB 10
37832 /* The width in bits of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */
37833 #define ALT_USB_HOST_HCINT7_DATATGLERR_WIDTH 1
37834 /* The mask used to set the ALT_USB_HOST_HCINT7_DATATGLERR register field value. */
37835 #define ALT_USB_HOST_HCINT7_DATATGLERR_SET_MSK 0x00000400
37836 /* The mask used to clear the ALT_USB_HOST_HCINT7_DATATGLERR register field value. */
37837 #define ALT_USB_HOST_HCINT7_DATATGLERR_CLR_MSK 0xfffffbff
37838 /* The reset value of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */
37839 #define ALT_USB_HOST_HCINT7_DATATGLERR_RESET 0x0
37840 /* Extracts the ALT_USB_HOST_HCINT7_DATATGLERR field value from a register. */
37841 #define ALT_USB_HOST_HCINT7_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
37842 /* Produces a ALT_USB_HOST_HCINT7_DATATGLERR register field value suitable for setting the register. */
37843 #define ALT_USB_HOST_HCINT7_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
37844 
37845 /*
37846  * Field : bnaintr
37847  *
37848  * BNA (Buffer Not Available) Interrupt (BNAIntr)
37849  *
37850  * This bit is valid only when Scatter/Gather DMA mode is enabled.
37851  *
37852  * The core generates this interrupt when the descriptor accessed
37853  *
37854  * is not ready for the Core to process. BNA will not be generated
37855  *
37856  * for Isochronous channels.
37857  *
37858  * For non Scatter/Gather DMA mode, this bit is reserved.
37859  *
37860  * Field Enumeration Values:
37861  *
37862  * Enum | Value | Description
37863  * :------------------------------------|:------|:-----------------
37864  * ALT_USB_HOST_HCINT7_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
37865  * ALT_USB_HOST_HCINT7_BNAINTR_E_ACT | 0x1 | BNA Interrupt
37866  *
37867  * Field Access Macros:
37868  *
37869  */
37870 /*
37871  * Enumerated value for register field ALT_USB_HOST_HCINT7_BNAINTR
37872  *
37873  * No BNA Interrupt
37874  */
37875 #define ALT_USB_HOST_HCINT7_BNAINTR_E_INACT 0x0
37876 /*
37877  * Enumerated value for register field ALT_USB_HOST_HCINT7_BNAINTR
37878  *
37879  * BNA Interrupt
37880  */
37881 #define ALT_USB_HOST_HCINT7_BNAINTR_E_ACT 0x1
37882 
37883 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_BNAINTR register field. */
37884 #define ALT_USB_HOST_HCINT7_BNAINTR_LSB 11
37885 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_BNAINTR register field. */
37886 #define ALT_USB_HOST_HCINT7_BNAINTR_MSB 11
37887 /* The width in bits of the ALT_USB_HOST_HCINT7_BNAINTR register field. */
37888 #define ALT_USB_HOST_HCINT7_BNAINTR_WIDTH 1
37889 /* The mask used to set the ALT_USB_HOST_HCINT7_BNAINTR register field value. */
37890 #define ALT_USB_HOST_HCINT7_BNAINTR_SET_MSK 0x00000800
37891 /* The mask used to clear the ALT_USB_HOST_HCINT7_BNAINTR register field value. */
37892 #define ALT_USB_HOST_HCINT7_BNAINTR_CLR_MSK 0xfffff7ff
37893 /* The reset value of the ALT_USB_HOST_HCINT7_BNAINTR register field. */
37894 #define ALT_USB_HOST_HCINT7_BNAINTR_RESET 0x0
37895 /* Extracts the ALT_USB_HOST_HCINT7_BNAINTR field value from a register. */
37896 #define ALT_USB_HOST_HCINT7_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
37897 /* Produces a ALT_USB_HOST_HCINT7_BNAINTR register field value suitable for setting the register. */
37898 #define ALT_USB_HOST_HCINT7_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
37899 
37900 /*
37901  * Field : xcs_xact_err
37902  *
37903  * Excessive Transaction Error (XCS_XACT_ERR)
37904  *
37905  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
37906  * this bit
37907  *
37908  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
37909  *
37910  * not be generated for Isochronous channels.
37911  *
37912  * For non Scatter/Gather DMA mode, this bit is reserved.
37913  *
37914  * Field Enumeration Values:
37915  *
37916  * Enum | Value | Description
37917  * :-------------------------------------------|:------|:-------------------------------
37918  * ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
37919  * ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
37920  *
37921  * Field Access Macros:
37922  *
37923  */
37924 /*
37925  * Enumerated value for register field ALT_USB_HOST_HCINT7_XCS_XACT_ERR
37926  *
37927  * No Excessive Transaction Error
37928  */
37929 #define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_INACT 0x0
37930 /*
37931  * Enumerated value for register field ALT_USB_HOST_HCINT7_XCS_XACT_ERR
37932  *
37933  * Excessive Transaction Error
37934  */
37935 #define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_ACVTIVE 0x1
37936 
37937 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */
37938 #define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_LSB 12
37939 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */
37940 #define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_MSB 12
37941 /* The width in bits of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */
37942 #define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_WIDTH 1
37943 /* The mask used to set the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field value. */
37944 #define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_SET_MSK 0x00001000
37945 /* The mask used to clear the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field value. */
37946 #define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_CLR_MSK 0xffffefff
37947 /* The reset value of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */
37948 #define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_RESET 0x0
37949 /* Extracts the ALT_USB_HOST_HCINT7_XCS_XACT_ERR field value from a register. */
37950 #define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
37951 /* Produces a ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field value suitable for setting the register. */
37952 #define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
37953 
37954 /*
37955  * Field : desc_lst_rollintr
37956  *
37957  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
37958  *
37959  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
37960  * this bit
37961  *
37962  * when the corresponding channel's descriptor list rolls over.
37963  *
37964  * For non Scatter/Gather DMA mode, this bit is reserved.
37965  *
37966  * Field Enumeration Values:
37967  *
37968  * Enum | Value | Description
37969  * :----------------------------------------------|:------|:---------------------------------
37970  * ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
37971  * ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
37972  *
37973  * Field Access Macros:
37974  *
37975  */
37976 /*
37977  * Enumerated value for register field ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR
37978  *
37979  * No Descriptor rollover interrupt
37980  */
37981 #define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_INACT 0x0
37982 /*
37983  * Enumerated value for register field ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR
37984  *
37985  * Descriptor rollover interrupt
37986  */
37987 #define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_ACT 0x1
37988 
37989 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */
37990 #define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_LSB 13
37991 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */
37992 #define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_MSB 13
37993 /* The width in bits of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */
37994 #define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_WIDTH 1
37995 /* The mask used to set the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field value. */
37996 #define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_SET_MSK 0x00002000
37997 /* The mask used to clear the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field value. */
37998 #define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
37999 /* The reset value of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */
38000 #define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_RESET 0x0
38001 /* Extracts the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR field value from a register. */
38002 #define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
38003 /* Produces a ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field value suitable for setting the register. */
38004 #define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
38005 
38006 #ifndef __ASSEMBLY__
38007 /*
38008  * WARNING: The C register and register group struct declarations are provided for
38009  * convenience and illustrative purposes. They should, however, be used with
38010  * caution as the C language standard provides no guarantees about the alignment or
38011  * atomicity of device memory accesses. The recommended practice for writing
38012  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
38013  * alt_write_word() functions.
38014  *
38015  * The struct declaration for register ALT_USB_HOST_HCINT7.
38016  */
38017 struct ALT_USB_HOST_HCINT7_s
38018 {
38019  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT7_XFERCOMPL */
38020  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT7_CHHLTD */
38021  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT7_AHBERR */
38022  uint32_t stall : 1; /* ALT_USB_HOST_HCINT7_STALL */
38023  uint32_t nak : 1; /* ALT_USB_HOST_HCINT7_NAK */
38024  uint32_t ack : 1; /* ALT_USB_HOST_HCINT7_ACK */
38025  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT7_NYET */
38026  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT7_XACTERR */
38027  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT7_BBLERR */
38028  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT7_FRMOVRUN */
38029  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT7_DATATGLERR */
38030  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT7_BNAINTR */
38031  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT7_XCS_XACT_ERR */
38032  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR */
38033  uint32_t : 18; /* *UNDEFINED* */
38034 };
38035 
38036 /* The typedef declaration for register ALT_USB_HOST_HCINT7. */
38037 typedef volatile struct ALT_USB_HOST_HCINT7_s ALT_USB_HOST_HCINT7_t;
38038 #endif /* __ASSEMBLY__ */
38039 
38040 /* The reset value of the ALT_USB_HOST_HCINT7 register. */
38041 #define ALT_USB_HOST_HCINT7_RESET 0x00000000
38042 /* The byte offset of the ALT_USB_HOST_HCINT7 register from the beginning of the component. */
38043 #define ALT_USB_HOST_HCINT7_OFST 0x1e8
38044 /* The address of the ALT_USB_HOST_HCINT7 register. */
38045 #define ALT_USB_HOST_HCINT7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT7_OFST))
38046 
38047 /*
38048  * Register : hcintmsk7
38049  *
38050  * Host Channel 7 Interrupt Mask Register
38051  *
38052  * Register Layout
38053  *
38054  * Bits | Access | Reset | Description
38055  * :--------|:-------|:------|:-------------------------------------------
38056  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK
38057  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_CHHLTDMSK
38058  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_AHBERRMSK
38059  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_STALLMSK
38060  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_NAKMSK
38061  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_ACKMSK
38062  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_NYETMSK
38063  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_XACTERRMSK
38064  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_BBLERRMSK
38065  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK
38066  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK
38067  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_BNAINTRMSK
38068  * [12] | ??? | 0x0 | *UNDEFINED*
38069  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK
38070  * [31:14] | ??? | 0x0 | *UNDEFINED*
38071  *
38072  */
38073 /*
38074  * Field : xfercomplmsk
38075  *
38076  * Transfer Completed Mask (XferComplMsk)
38077  *
38078  * Field Enumeration Values:
38079  *
38080  * Enum | Value | Description
38081  * :--------------------------------------------|:------|:------------
38082  * ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_MSK | 0x0 | Mask
38083  * ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
38084  *
38085  * Field Access Macros:
38086  *
38087  */
38088 /*
38089  * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK
38090  *
38091  * Mask
38092  */
38093 #define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_MSK 0x0
38094 /*
38095  * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK
38096  *
38097  * No mask
38098  */
38099 #define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_NOMSK 0x1
38100 
38101 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */
38102 #define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_LSB 0
38103 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */
38104 #define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_MSB 0
38105 /* The width in bits of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */
38106 #define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_WIDTH 1
38107 /* The mask used to set the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field value. */
38108 #define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_SET_MSK 0x00000001
38109 /* The mask used to clear the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field value. */
38110 #define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_CLR_MSK 0xfffffffe
38111 /* The reset value of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */
38112 #define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_RESET 0x0
38113 /* Extracts the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK field value from a register. */
38114 #define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
38115 /* Produces a ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field value suitable for setting the register. */
38116 #define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
38117 
38118 /*
38119  * Field : chhltdmsk
38120  *
38121  * Channel Halted Mask (ChHltdMsk)
38122  *
38123  * Field Enumeration Values:
38124  *
38125  * Enum | Value | Description
38126  * :-----------------------------------------|:------|:------------
38127  * ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_MSK | 0x0 | Mask
38128  * ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_NOMSK | 0x1 | No mask
38129  *
38130  * Field Access Macros:
38131  *
38132  */
38133 /*
38134  * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_CHHLTDMSK
38135  *
38136  * Mask
38137  */
38138 #define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_MSK 0x0
38139 /*
38140  * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_CHHLTDMSK
38141  *
38142  * No mask
38143  */
38144 #define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_NOMSK 0x1
38145 
38146 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */
38147 #define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_LSB 1
38148 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */
38149 #define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_MSB 1
38150 /* The width in bits of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */
38151 #define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_WIDTH 1
38152 /* The mask used to set the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field value. */
38153 #define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_SET_MSK 0x00000002
38154 /* The mask used to clear the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field value. */
38155 #define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_CLR_MSK 0xfffffffd
38156 /* The reset value of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */
38157 #define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_RESET 0x0
38158 /* Extracts the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK field value from a register. */
38159 #define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
38160 /* Produces a ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field value suitable for setting the register. */
38161 #define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
38162 
38163 /*
38164  * Field : ahberrmsk
38165  *
38166  * AHB Error Mask (AHBErrMsk)
38167  *
38168  * In scatter/gather DMA mode for host,
38169  *
38170  * interrupts will not be generated due to the corresponding bits set in
38171  *
38172  * HCINTn.
38173  *
38174  * Field Enumeration Values:
38175  *
38176  * Enum | Value | Description
38177  * :-----------------------------------------|:------|:------------
38178  * ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_MSK | 0x0 | Mask
38179  * ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_NOMSK | 0x1 | No mask
38180  *
38181  * Field Access Macros:
38182  *
38183  */
38184 /*
38185  * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_AHBERRMSK
38186  *
38187  * Mask
38188  */
38189 #define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_MSK 0x0
38190 /*
38191  * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_AHBERRMSK
38192  *
38193  * No mask
38194  */
38195 #define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_NOMSK 0x1
38196 
38197 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */
38198 #define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_LSB 2
38199 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */
38200 #define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_MSB 2
38201 /* The width in bits of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */
38202 #define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_WIDTH 1
38203 /* The mask used to set the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field value. */
38204 #define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_SET_MSK 0x00000004
38205 /* The mask used to clear the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field value. */
38206 #define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_CLR_MSK 0xfffffffb
38207 /* The reset value of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */
38208 #define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_RESET 0x0
38209 /* Extracts the ALT_USB_HOST_HCINTMSK7_AHBERRMSK field value from a register. */
38210 #define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
38211 /* Produces a ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field value suitable for setting the register. */
38212 #define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
38213 
38214 /*
38215  * Field : stallmsk
38216  *
38217  * STALL Response Received Interrupt Mask (StallMsk)
38218  *
38219  * In scatter/gather DMA mode for host,
38220  *
38221  * interrupts will not be generated due to the corresponding bits set in
38222  *
38223  * HCINTn.
38224  *
38225  * Field Access Macros:
38226  *
38227  */
38228 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_STALLMSK register field. */
38229 #define ALT_USB_HOST_HCINTMSK7_STALLMSK_LSB 3
38230 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_STALLMSK register field. */
38231 #define ALT_USB_HOST_HCINTMSK7_STALLMSK_MSB 3
38232 /* The width in bits of the ALT_USB_HOST_HCINTMSK7_STALLMSK register field. */
38233 #define ALT_USB_HOST_HCINTMSK7_STALLMSK_WIDTH 1
38234 /* The mask used to set the ALT_USB_HOST_HCINTMSK7_STALLMSK register field value. */
38235 #define ALT_USB_HOST_HCINTMSK7_STALLMSK_SET_MSK 0x00000008
38236 /* The mask used to clear the ALT_USB_HOST_HCINTMSK7_STALLMSK register field value. */
38237 #define ALT_USB_HOST_HCINTMSK7_STALLMSK_CLR_MSK 0xfffffff7
38238 /* The reset value of the ALT_USB_HOST_HCINTMSK7_STALLMSK register field. */
38239 #define ALT_USB_HOST_HCINTMSK7_STALLMSK_RESET 0x0
38240 /* Extracts the ALT_USB_HOST_HCINTMSK7_STALLMSK field value from a register. */
38241 #define ALT_USB_HOST_HCINTMSK7_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
38242 /* Produces a ALT_USB_HOST_HCINTMSK7_STALLMSK register field value suitable for setting the register. */
38243 #define ALT_USB_HOST_HCINTMSK7_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
38244 
38245 /*
38246  * Field : nakmsk
38247  *
38248  * NAK Response Received Interrupt Mask (NakMsk)
38249  *
38250  * In scatter/gather DMA mode for host,
38251  *
38252  * interrupts will not be generated due to the corresponding bits set in
38253  *
38254  * HCINTn.
38255  *
38256  * Field Access Macros:
38257  *
38258  */
38259 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_NAKMSK register field. */
38260 #define ALT_USB_HOST_HCINTMSK7_NAKMSK_LSB 4
38261 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_NAKMSK register field. */
38262 #define ALT_USB_HOST_HCINTMSK7_NAKMSK_MSB 4
38263 /* The width in bits of the ALT_USB_HOST_HCINTMSK7_NAKMSK register field. */
38264 #define ALT_USB_HOST_HCINTMSK7_NAKMSK_WIDTH 1
38265 /* The mask used to set the ALT_USB_HOST_HCINTMSK7_NAKMSK register field value. */
38266 #define ALT_USB_HOST_HCINTMSK7_NAKMSK_SET_MSK 0x00000010
38267 /* The mask used to clear the ALT_USB_HOST_HCINTMSK7_NAKMSK register field value. */
38268 #define ALT_USB_HOST_HCINTMSK7_NAKMSK_CLR_MSK 0xffffffef
38269 /* The reset value of the ALT_USB_HOST_HCINTMSK7_NAKMSK register field. */
38270 #define ALT_USB_HOST_HCINTMSK7_NAKMSK_RESET 0x0
38271 /* Extracts the ALT_USB_HOST_HCINTMSK7_NAKMSK field value from a register. */
38272 #define ALT_USB_HOST_HCINTMSK7_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
38273 /* Produces a ALT_USB_HOST_HCINTMSK7_NAKMSK register field value suitable for setting the register. */
38274 #define ALT_USB_HOST_HCINTMSK7_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
38275 
38276 /*
38277  * Field : ackmsk
38278  *
38279  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
38280  *
38281  * In scatter/gather DMA mode for host,
38282  *
38283  * interrupts will not be generated due to the corresponding bits set in
38284  *
38285  * HCINTn.
38286  *
38287  * Field Access Macros:
38288  *
38289  */
38290 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_ACKMSK register field. */
38291 #define ALT_USB_HOST_HCINTMSK7_ACKMSK_LSB 5
38292 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_ACKMSK register field. */
38293 #define ALT_USB_HOST_HCINTMSK7_ACKMSK_MSB 5
38294 /* The width in bits of the ALT_USB_HOST_HCINTMSK7_ACKMSK register field. */
38295 #define ALT_USB_HOST_HCINTMSK7_ACKMSK_WIDTH 1
38296 /* The mask used to set the ALT_USB_HOST_HCINTMSK7_ACKMSK register field value. */
38297 #define ALT_USB_HOST_HCINTMSK7_ACKMSK_SET_MSK 0x00000020
38298 /* The mask used to clear the ALT_USB_HOST_HCINTMSK7_ACKMSK register field value. */
38299 #define ALT_USB_HOST_HCINTMSK7_ACKMSK_CLR_MSK 0xffffffdf
38300 /* The reset value of the ALT_USB_HOST_HCINTMSK7_ACKMSK register field. */
38301 #define ALT_USB_HOST_HCINTMSK7_ACKMSK_RESET 0x0
38302 /* Extracts the ALT_USB_HOST_HCINTMSK7_ACKMSK field value from a register. */
38303 #define ALT_USB_HOST_HCINTMSK7_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
38304 /* Produces a ALT_USB_HOST_HCINTMSK7_ACKMSK register field value suitable for setting the register. */
38305 #define ALT_USB_HOST_HCINTMSK7_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
38306 
38307 /*
38308  * Field : nyetmsk
38309  *
38310  * NYET Response Received Interrupt Mask (NyetMsk)
38311  *
38312  * In scatter/gather DMA mode for host,
38313  *
38314  * interrupts will not be generated due to the corresponding bits set in
38315  *
38316  * HCINTn.
38317  *
38318  * Field Access Macros:
38319  *
38320  */
38321 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_NYETMSK register field. */
38322 #define ALT_USB_HOST_HCINTMSK7_NYETMSK_LSB 6
38323 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_NYETMSK register field. */
38324 #define ALT_USB_HOST_HCINTMSK7_NYETMSK_MSB 6
38325 /* The width in bits of the ALT_USB_HOST_HCINTMSK7_NYETMSK register field. */
38326 #define ALT_USB_HOST_HCINTMSK7_NYETMSK_WIDTH 1
38327 /* The mask used to set the ALT_USB_HOST_HCINTMSK7_NYETMSK register field value. */
38328 #define ALT_USB_HOST_HCINTMSK7_NYETMSK_SET_MSK 0x00000040
38329 /* The mask used to clear the ALT_USB_HOST_HCINTMSK7_NYETMSK register field value. */
38330 #define ALT_USB_HOST_HCINTMSK7_NYETMSK_CLR_MSK 0xffffffbf
38331 /* The reset value of the ALT_USB_HOST_HCINTMSK7_NYETMSK register field. */
38332 #define ALT_USB_HOST_HCINTMSK7_NYETMSK_RESET 0x0
38333 /* Extracts the ALT_USB_HOST_HCINTMSK7_NYETMSK field value from a register. */
38334 #define ALT_USB_HOST_HCINTMSK7_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
38335 /* Produces a ALT_USB_HOST_HCINTMSK7_NYETMSK register field value suitable for setting the register. */
38336 #define ALT_USB_HOST_HCINTMSK7_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
38337 
38338 /*
38339  * Field : xacterrmsk
38340  *
38341  * Transaction Error Mask (XactErrMsk)
38342  *
38343  * In scatter/gather DMA mode for host,
38344  *
38345  * interrupts will not be generated due to the corresponding bits set in
38346  *
38347  * HCINTn.
38348  *
38349  * Field Access Macros:
38350  *
38351  */
38352 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field. */
38353 #define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_LSB 7
38354 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field. */
38355 #define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_MSB 7
38356 /* The width in bits of the ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field. */
38357 #define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_WIDTH 1
38358 /* The mask used to set the ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field value. */
38359 #define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_SET_MSK 0x00000080
38360 /* The mask used to clear the ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field value. */
38361 #define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_CLR_MSK 0xffffff7f
38362 /* The reset value of the ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field. */
38363 #define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_RESET 0x0
38364 /* Extracts the ALT_USB_HOST_HCINTMSK7_XACTERRMSK field value from a register. */
38365 #define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
38366 /* Produces a ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field value suitable for setting the register. */
38367 #define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
38368 
38369 /*
38370  * Field : bblerrmsk
38371  *
38372  * Babble Error Mask (BblErrMsk)
38373  *
38374  * In scatter/gather DMA mode for host,
38375  *
38376  * interrupts will not be generated due to the corresponding bits set in
38377  *
38378  * HCINTn.
38379  *
38380  * Field Access Macros:
38381  *
38382  */
38383 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field. */
38384 #define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_LSB 8
38385 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field. */
38386 #define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_MSB 8
38387 /* The width in bits of the ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field. */
38388 #define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_WIDTH 1
38389 /* The mask used to set the ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field value. */
38390 #define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_SET_MSK 0x00000100
38391 /* The mask used to clear the ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field value. */
38392 #define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_CLR_MSK 0xfffffeff
38393 /* The reset value of the ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field. */
38394 #define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_RESET 0x0
38395 /* Extracts the ALT_USB_HOST_HCINTMSK7_BBLERRMSK field value from a register. */
38396 #define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
38397 /* Produces a ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field value suitable for setting the register. */
38398 #define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
38399 
38400 /*
38401  * Field : frmovrunmsk
38402  *
38403  * Frame Overrun Mask (FrmOvrunMsk)
38404  *
38405  * In scatter/gather DMA mode for host,
38406  *
38407  * interrupts will not be generated due to the corresponding bits set in
38408  *
38409  * HCINTn.
38410  *
38411  * Field Access Macros:
38412  *
38413  */
38414 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field. */
38415 #define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_LSB 9
38416 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field. */
38417 #define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_MSB 9
38418 /* The width in bits of the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field. */
38419 #define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_WIDTH 1
38420 /* The mask used to set the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field value. */
38421 #define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_SET_MSK 0x00000200
38422 /* The mask used to clear the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field value. */
38423 #define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_CLR_MSK 0xfffffdff
38424 /* The reset value of the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field. */
38425 #define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_RESET 0x0
38426 /* Extracts the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK field value from a register. */
38427 #define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
38428 /* Produces a ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field value suitable for setting the register. */
38429 #define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
38430 
38431 /*
38432  * Field : datatglerrmsk
38433  *
38434  * Data Toggle Error Mask (DataTglErrMsk)
38435  *
38436  * In scatter/gather DMA mode for host,
38437  *
38438  * interrupts will not be generated due to the corresponding bits set in
38439  *
38440  * HCINTn.
38441  *
38442  * Field Access Macros:
38443  *
38444  */
38445 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field. */
38446 #define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_LSB 10
38447 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field. */
38448 #define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_MSB 10
38449 /* The width in bits of the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field. */
38450 #define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_WIDTH 1
38451 /* The mask used to set the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field value. */
38452 #define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_SET_MSK 0x00000400
38453 /* The mask used to clear the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field value. */
38454 #define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_CLR_MSK 0xfffffbff
38455 /* The reset value of the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field. */
38456 #define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_RESET 0x0
38457 /* Extracts the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK field value from a register. */
38458 #define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
38459 /* Produces a ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field value suitable for setting the register. */
38460 #define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
38461 
38462 /*
38463  * Field : bnaintrmsk
38464  *
38465  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
38466  *
38467  * This bit is valid only when Scatter/Gather DMA mode is enabled.
38468  *
38469  * Field Enumeration Values:
38470  *
38471  * Enum | Value | Description
38472  * :------------------------------------------|:------|:------------
38473  * ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_MSK | 0x0 | Mask
38474  * ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_NOMSK | 0x1 | No mask
38475  *
38476  * Field Access Macros:
38477  *
38478  */
38479 /*
38480  * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_BNAINTRMSK
38481  *
38482  * Mask
38483  */
38484 #define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_MSK 0x0
38485 /*
38486  * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_BNAINTRMSK
38487  *
38488  * No mask
38489  */
38490 #define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_NOMSK 0x1
38491 
38492 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */
38493 #define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_LSB 11
38494 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */
38495 #define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_MSB 11
38496 /* The width in bits of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */
38497 #define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_WIDTH 1
38498 /* The mask used to set the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field value. */
38499 #define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_SET_MSK 0x00000800
38500 /* The mask used to clear the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field value. */
38501 #define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_CLR_MSK 0xfffff7ff
38502 /* The reset value of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */
38503 #define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_RESET 0x0
38504 /* Extracts the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK field value from a register. */
38505 #define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
38506 /* Produces a ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field value suitable for setting the register. */
38507 #define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
38508 
38509 /*
38510  * Field : frm_lst_rollintrmsk
38511  *
38512  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
38513  *
38514  * This bit is valid only when Scatter/Gather DMA mode is enabled.
38515  *
38516  * Field Enumeration Values:
38517  *
38518  * Enum | Value | Description
38519  * :---------------------------------------------------|:------|:------------
38520  * ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
38521  * ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
38522  *
38523  * Field Access Macros:
38524  *
38525  */
38526 /*
38527  * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK
38528  *
38529  * Mask
38530  */
38531 #define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_MSK 0x0
38532 /*
38533  * Enumerated value for register field ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK
38534  *
38535  * No mask
38536  */
38537 #define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
38538 
38539 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */
38540 #define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_LSB 13
38541 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */
38542 #define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_MSB 13
38543 /* The width in bits of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */
38544 #define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_WIDTH 1
38545 /* The mask used to set the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field value. */
38546 #define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
38547 /* The mask used to clear the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field value. */
38548 #define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
38549 /* The reset value of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */
38550 #define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_RESET 0x0
38551 /* Extracts the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK field value from a register. */
38552 #define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
38553 /* Produces a ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
38554 #define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
38555 
38556 #ifndef __ASSEMBLY__
38557 /*
38558  * WARNING: The C register and register group struct declarations are provided for
38559  * convenience and illustrative purposes. They should, however, be used with
38560  * caution as the C language standard provides no guarantees about the alignment or
38561  * atomicity of device memory accesses. The recommended practice for writing
38562  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
38563  * alt_write_word() functions.
38564  *
38565  * The struct declaration for register ALT_USB_HOST_HCINTMSK7.
38566  */
38567 struct ALT_USB_HOST_HCINTMSK7_s
38568 {
38569  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK */
38570  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK7_CHHLTDMSK */
38571  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK7_AHBERRMSK */
38572  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK7_STALLMSK */
38573  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK7_NAKMSK */
38574  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK7_ACKMSK */
38575  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK7_NYETMSK */
38576  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK7_XACTERRMSK */
38577  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK7_BBLERRMSK */
38578  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK */
38579  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK */
38580  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK7_BNAINTRMSK */
38581  uint32_t : 1; /* *UNDEFINED* */
38582  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK */
38583  uint32_t : 18; /* *UNDEFINED* */
38584 };
38585 
38586 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK7. */
38587 typedef volatile struct ALT_USB_HOST_HCINTMSK7_s ALT_USB_HOST_HCINTMSK7_t;
38588 #endif /* __ASSEMBLY__ */
38589 
38590 /* The reset value of the ALT_USB_HOST_HCINTMSK7 register. */
38591 #define ALT_USB_HOST_HCINTMSK7_RESET 0x00000000
38592 /* The byte offset of the ALT_USB_HOST_HCINTMSK7 register from the beginning of the component. */
38593 #define ALT_USB_HOST_HCINTMSK7_OFST 0x1ec
38594 /* The address of the ALT_USB_HOST_HCINTMSK7 register. */
38595 #define ALT_USB_HOST_HCINTMSK7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK7_OFST))
38596 
38597 /*
38598  * Register : hctsiz7
38599  *
38600  * Host Channel 7 Transfer Size Register
38601  *
38602  * Register Layout
38603  *
38604  * Bits | Access | Reset | Description
38605  * :--------|:-------|:------|:------------------------------
38606  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ7_XFERSIZE
38607  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ7_PKTCNT
38608  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ7_PID
38609  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ7_DOPNG
38610  *
38611  */
38612 /*
38613  * Field : xfersize
38614  *
38615  * Transfer Size (XferSize)
38616  *
38617  * For an OUT, this field is the number of data bytes the host sends
38618  *
38619  * during the transfer.
38620  *
38621  * For an IN, this field is the buffer size that the application has
38622  *
38623  * Reserved For the transfer. The application is expected to
38624  *
38625  * program this field as an integer multiple of the maximum packet
38626  *
38627  * size For IN transactions (periodic and non-periodic).
38628  *
38629  * The width of this counter is specified as Width of Transfer Size
38630  *
38631  * Counters
38632  *
38633  * Field Access Macros:
38634  *
38635  */
38636 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */
38637 #define ALT_USB_HOST_HCTSIZ7_XFERSIZE_LSB 0
38638 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */
38639 #define ALT_USB_HOST_HCTSIZ7_XFERSIZE_MSB 18
38640 /* The width in bits of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */
38641 #define ALT_USB_HOST_HCTSIZ7_XFERSIZE_WIDTH 19
38642 /* The mask used to set the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field value. */
38643 #define ALT_USB_HOST_HCTSIZ7_XFERSIZE_SET_MSK 0x0007ffff
38644 /* The mask used to clear the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field value. */
38645 #define ALT_USB_HOST_HCTSIZ7_XFERSIZE_CLR_MSK 0xfff80000
38646 /* The reset value of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */
38647 #define ALT_USB_HOST_HCTSIZ7_XFERSIZE_RESET 0x0
38648 /* Extracts the ALT_USB_HOST_HCTSIZ7_XFERSIZE field value from a register. */
38649 #define ALT_USB_HOST_HCTSIZ7_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
38650 /* Produces a ALT_USB_HOST_HCTSIZ7_XFERSIZE register field value suitable for setting the register. */
38651 #define ALT_USB_HOST_HCTSIZ7_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
38652 
38653 /*
38654  * Field : pktcnt
38655  *
38656  * Packet Count (PktCnt)
38657  *
38658  * This field is programmed by the application with the expected
38659  *
38660  * number of packets to be transmitted (OUT) or received (IN).
38661  *
38662  * The host decrements this count on every successful
38663  *
38664  * transmission or reception of an OUT/IN packet. Once this count
38665  *
38666  * reaches zero, the application is interrupted to indicate normal
38667  *
38668  * completion.
38669  *
38670  * The width of this counter is specified as Width of Packet
38671  *
38672  * Counters
38673  *
38674  * Field Access Macros:
38675  *
38676  */
38677 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */
38678 #define ALT_USB_HOST_HCTSIZ7_PKTCNT_LSB 19
38679 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */
38680 #define ALT_USB_HOST_HCTSIZ7_PKTCNT_MSB 28
38681 /* The width in bits of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */
38682 #define ALT_USB_HOST_HCTSIZ7_PKTCNT_WIDTH 10
38683 /* The mask used to set the ALT_USB_HOST_HCTSIZ7_PKTCNT register field value. */
38684 #define ALT_USB_HOST_HCTSIZ7_PKTCNT_SET_MSK 0x1ff80000
38685 /* The mask used to clear the ALT_USB_HOST_HCTSIZ7_PKTCNT register field value. */
38686 #define ALT_USB_HOST_HCTSIZ7_PKTCNT_CLR_MSK 0xe007ffff
38687 /* The reset value of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */
38688 #define ALT_USB_HOST_HCTSIZ7_PKTCNT_RESET 0x0
38689 /* Extracts the ALT_USB_HOST_HCTSIZ7_PKTCNT field value from a register. */
38690 #define ALT_USB_HOST_HCTSIZ7_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
38691 /* Produces a ALT_USB_HOST_HCTSIZ7_PKTCNT register field value suitable for setting the register. */
38692 #define ALT_USB_HOST_HCTSIZ7_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
38693 
38694 /*
38695  * Field : pid
38696  *
38697  * PID (Pid)
38698  *
38699  * The application programs this field with the type of PID to use For
38700  *
38701  * the initial transaction. The host maintains this field For the rest of
38702  *
38703  * the transfer.
38704  *
38705  * 2'b00: DATA0
38706  *
38707  * 2'b01: DATA2
38708  *
38709  * 2'b10: DATA1
38710  *
38711  * 2'b11: MDATA (non-control)/SETUP (control)
38712  *
38713  * Field Enumeration Values:
38714  *
38715  * Enum | Value | Description
38716  * :---------------------------------|:------|:------------------------------------
38717  * ALT_USB_HOST_HCTSIZ7_PID_E_DATA0 | 0x0 | DATA0
38718  * ALT_USB_HOST_HCTSIZ7_PID_E_DATA2 | 0x1 | DATA2
38719  * ALT_USB_HOST_HCTSIZ7_PID_E_DATA1 | 0x2 | DATA1
38720  * ALT_USB_HOST_HCTSIZ7_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
38721  *
38722  * Field Access Macros:
38723  *
38724  */
38725 /*
38726  * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID
38727  *
38728  * DATA0
38729  */
38730 #define ALT_USB_HOST_HCTSIZ7_PID_E_DATA0 0x0
38731 /*
38732  * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID
38733  *
38734  * DATA2
38735  */
38736 #define ALT_USB_HOST_HCTSIZ7_PID_E_DATA2 0x1
38737 /*
38738  * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID
38739  *
38740  * DATA1
38741  */
38742 #define ALT_USB_HOST_HCTSIZ7_PID_E_DATA1 0x2
38743 /*
38744  * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID
38745  *
38746  * MDATA (non-control)/SETUP (control)
38747  */
38748 #define ALT_USB_HOST_HCTSIZ7_PID_E_MDATA 0x3
38749 
38750 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_PID register field. */
38751 #define ALT_USB_HOST_HCTSIZ7_PID_LSB 29
38752 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_PID register field. */
38753 #define ALT_USB_HOST_HCTSIZ7_PID_MSB 30
38754 /* The width in bits of the ALT_USB_HOST_HCTSIZ7_PID register field. */
38755 #define ALT_USB_HOST_HCTSIZ7_PID_WIDTH 2
38756 /* The mask used to set the ALT_USB_HOST_HCTSIZ7_PID register field value. */
38757 #define ALT_USB_HOST_HCTSIZ7_PID_SET_MSK 0x60000000
38758 /* The mask used to clear the ALT_USB_HOST_HCTSIZ7_PID register field value. */
38759 #define ALT_USB_HOST_HCTSIZ7_PID_CLR_MSK 0x9fffffff
38760 /* The reset value of the ALT_USB_HOST_HCTSIZ7_PID register field. */
38761 #define ALT_USB_HOST_HCTSIZ7_PID_RESET 0x0
38762 /* Extracts the ALT_USB_HOST_HCTSIZ7_PID field value from a register. */
38763 #define ALT_USB_HOST_HCTSIZ7_PID_GET(value) (((value) & 0x60000000) >> 29)
38764 /* Produces a ALT_USB_HOST_HCTSIZ7_PID register field value suitable for setting the register. */
38765 #define ALT_USB_HOST_HCTSIZ7_PID_SET(value) (((value) << 29) & 0x60000000)
38766 
38767 /*
38768  * Field : dopng
38769  *
38770  * Do Ping (DoPng)
38771  *
38772  * This bit is used only For OUT transfers.
38773  *
38774  * Setting this field to 1 directs the host to do PING protocol.
38775  *
38776  * Note: Do not Set this bit For IN transfers. If this bit is Set For
38777  *
38778  * for IN transfers it disables the channel.
38779  *
38780  * Field Enumeration Values:
38781  *
38782  * Enum | Value | Description
38783  * :------------------------------------|:------|:-----------------
38784  * ALT_USB_HOST_HCTSIZ7_DOPNG_E_NOPING | 0x0 | No ping protocol
38785  * ALT_USB_HOST_HCTSIZ7_DOPNG_E_PING | 0x1 | Ping protocol
38786  *
38787  * Field Access Macros:
38788  *
38789  */
38790 /*
38791  * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_DOPNG
38792  *
38793  * No ping protocol
38794  */
38795 #define ALT_USB_HOST_HCTSIZ7_DOPNG_E_NOPING 0x0
38796 /*
38797  * Enumerated value for register field ALT_USB_HOST_HCTSIZ7_DOPNG
38798  *
38799  * Ping protocol
38800  */
38801 #define ALT_USB_HOST_HCTSIZ7_DOPNG_E_PING 0x1
38802 
38803 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */
38804 #define ALT_USB_HOST_HCTSIZ7_DOPNG_LSB 31
38805 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */
38806 #define ALT_USB_HOST_HCTSIZ7_DOPNG_MSB 31
38807 /* The width in bits of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */
38808 #define ALT_USB_HOST_HCTSIZ7_DOPNG_WIDTH 1
38809 /* The mask used to set the ALT_USB_HOST_HCTSIZ7_DOPNG register field value. */
38810 #define ALT_USB_HOST_HCTSIZ7_DOPNG_SET_MSK 0x80000000
38811 /* The mask used to clear the ALT_USB_HOST_HCTSIZ7_DOPNG register field value. */
38812 #define ALT_USB_HOST_HCTSIZ7_DOPNG_CLR_MSK 0x7fffffff
38813 /* The reset value of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */
38814 #define ALT_USB_HOST_HCTSIZ7_DOPNG_RESET 0x0
38815 /* Extracts the ALT_USB_HOST_HCTSIZ7_DOPNG field value from a register. */
38816 #define ALT_USB_HOST_HCTSIZ7_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
38817 /* Produces a ALT_USB_HOST_HCTSIZ7_DOPNG register field value suitable for setting the register. */
38818 #define ALT_USB_HOST_HCTSIZ7_DOPNG_SET(value) (((value) << 31) & 0x80000000)
38819 
38820 #ifndef __ASSEMBLY__
38821 /*
38822  * WARNING: The C register and register group struct declarations are provided for
38823  * convenience and illustrative purposes. They should, however, be used with
38824  * caution as the C language standard provides no guarantees about the alignment or
38825  * atomicity of device memory accesses. The recommended practice for writing
38826  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
38827  * alt_write_word() functions.
38828  *
38829  * The struct declaration for register ALT_USB_HOST_HCTSIZ7.
38830  */
38831 struct ALT_USB_HOST_HCTSIZ7_s
38832 {
38833  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ7_XFERSIZE */
38834  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ7_PKTCNT */
38835  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ7_PID */
38836  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ7_DOPNG */
38837 };
38838 
38839 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ7. */
38840 typedef volatile struct ALT_USB_HOST_HCTSIZ7_s ALT_USB_HOST_HCTSIZ7_t;
38841 #endif /* __ASSEMBLY__ */
38842 
38843 /* The reset value of the ALT_USB_HOST_HCTSIZ7 register. */
38844 #define ALT_USB_HOST_HCTSIZ7_RESET 0x00000000
38845 /* The byte offset of the ALT_USB_HOST_HCTSIZ7 register from the beginning of the component. */
38846 #define ALT_USB_HOST_HCTSIZ7_OFST 0x1f0
38847 /* The address of the ALT_USB_HOST_HCTSIZ7 register. */
38848 #define ALT_USB_HOST_HCTSIZ7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ7_OFST))
38849 
38850 /*
38851  * Register : hcdma7
38852  *
38853  * Host Channel 7 DMA Address Register
38854  *
38855  * Register Layout
38856  *
38857  * Bits | Access | Reset | Description
38858  * :-------|:-------|:------|:---------------------------
38859  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA7_HCDMA7
38860  *
38861  */
38862 /*
38863  * Field : hcdma7
38864  *
38865  * Buffer DMA Mode:
38866  *
38867  * [31:0] DMA Address (DMAAddr)
38868  *
38869  * This field holds the start address in the external memory from which the data
38870  * for
38871  *
38872  * the endpoint must be fetched or to which it must be stored. This register is
38873  *
38874  * incremented on every AHB transaction.
38875  *
38876  * Scatter-Gather DMA (DescDMA) Mode:
38877  *
38878  * [31:9] (Non Isoc) Non-Isochronous:
38879  *
38880  * [31:N] (Isoc) Isochronous:
38881  *
38882  * This field holds the start address of the 512 bytes
38883  *
38884  * page. The first descriptor in the list should be located
38885  *
38886  * in this address. The first descriptor may be or may
38887  *
38888  * not be ready. The core starts processing the list from
38889  *
38890  * the CTD value.
38891  *
38892  * This field holds the address of the 2*(nTD+1) bytes of
38893  *
38894  * locations in which the isochronous descriptors are
38895  *
38896  * present where N is based on nTD as per Table below
38897  *
38898  * [31:N] Base Address
38899  *
38900  * [N-1:3] Offset
38901  *
38902  * [2:0] 000
38903  *
38904  * HS ISOC
38905  *
38906  * nTD N
38907  *
38908  * 7 6
38909  *
38910  * 15 7
38911  *
38912  * 31 8
38913  *
38914  * 63 9
38915  *
38916  * 127 10
38917  *
38918  * 255 11
38919  *
38920  * FS ISOC
38921  *
38922  * nTD N
38923  *
38924  * 1 4
38925  *
38926  * 3 5
38927  *
38928  * 7 6
38929  *
38930  * 15 7
38931  *
38932  * 31 8
38933  *
38934  * 63 9
38935  *
38936  * [N-1:3] (Isoc):
38937  *
38938  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
38939  *
38940  * Non Isochronous:
38941  *
38942  * This value is in terms of number of descriptors. The values can be from 0 to 63.
38943  *
38944  * 0 - 1 descriptor.
38945  *
38946  * 63 - 64 descriptors.
38947  *
38948  * This field indicates the current descriptor processed in the list. This field is
38949  * updated
38950  *
38951  * both by application and the core. For example, if the application enables the
38952  *
38953  * channel after programming CTD=5, then the core will start processing the 6th
38954  *
38955  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
38956  *
38957  * to DMAAddr.
38958  *
38959  * Isochronous:
38960  *
38961  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
38962  * set
38963  *
38964  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
38965  *
38966  * [31:9] (Non Isoc) Non-Isochronous:
38967  *
38968  * [31:N] (Isoc) Isochronous:
38969  *
38970  * This field holds the start address of the 512 bytes
38971  *
38972  * page. The first descriptor in the list should be located
38973  *
38974  * in this address. The first descriptor may be or may
38975  *
38976  * not be ready. The core starts processing the list from
38977  *
38978  * the CTD value.
38979  *
38980  * This field holds the address of the 2*(nTD+1) bytes of
38981  *
38982  * locations in which the isochronous descriptors are
38983  *
38984  * present where N is based on nTD as per Table below
38985  *
38986  * [31:N] Base Address
38987  *
38988  * [N-1:3] Offset
38989  *
38990  * [2:0] 000
38991  *
38992  * HS ISOC
38993  *
38994  * nTD N
38995  *
38996  * 7 6
38997  *
38998  * 15 7
38999  *
39000  * 31 8
39001  *
39002  * 63 9
39003  *
39004  * 127 10
39005  *
39006  * 255 11
39007  *
39008  * FS ISOC
39009  *
39010  * nTD N
39011  *
39012  * 1 4
39013  *
39014  * 3 5
39015  *
39016  * 7 6
39017  *
39018  * 15 7
39019  *
39020  * 31 8
39021  *
39022  * 63 9
39023  *
39024  * [N-1:3] (Isoc):
39025  *
39026  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
39027  *
39028  * Non Isochronous:
39029  *
39030  * This value is in terms of number of descriptors. The values can be from 0 to 63.
39031  *
39032  * 0 - 1 descriptor.
39033  *
39034  * 63 - 64 descriptors.
39035  *
39036  * This field indicates the current descriptor processed in the list. This field is
39037  * updated
39038  *
39039  * both by application and the core. For example, if the application enables the
39040  *
39041  * channel after programming CTD=5, then the core will start processing the 6th
39042  *
39043  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
39044  *
39045  * to DMAAddr.
39046  *
39047  * Isochronous:
39048  *
39049  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
39050  * set
39051  *
39052  * to zero by application.
39053  *
39054  * Field Access Macros:
39055  *
39056  */
39057 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */
39058 #define ALT_USB_HOST_HCDMA7_HCDMA7_LSB 0
39059 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */
39060 #define ALT_USB_HOST_HCDMA7_HCDMA7_MSB 31
39061 /* The width in bits of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */
39062 #define ALT_USB_HOST_HCDMA7_HCDMA7_WIDTH 32
39063 /* The mask used to set the ALT_USB_HOST_HCDMA7_HCDMA7 register field value. */
39064 #define ALT_USB_HOST_HCDMA7_HCDMA7_SET_MSK 0xffffffff
39065 /* The mask used to clear the ALT_USB_HOST_HCDMA7_HCDMA7 register field value. */
39066 #define ALT_USB_HOST_HCDMA7_HCDMA7_CLR_MSK 0x00000000
39067 /* The reset value of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */
39068 #define ALT_USB_HOST_HCDMA7_HCDMA7_RESET 0x0
39069 /* Extracts the ALT_USB_HOST_HCDMA7_HCDMA7 field value from a register. */
39070 #define ALT_USB_HOST_HCDMA7_HCDMA7_GET(value) (((value) & 0xffffffff) >> 0)
39071 /* Produces a ALT_USB_HOST_HCDMA7_HCDMA7 register field value suitable for setting the register. */
39072 #define ALT_USB_HOST_HCDMA7_HCDMA7_SET(value) (((value) << 0) & 0xffffffff)
39073 
39074 #ifndef __ASSEMBLY__
39075 /*
39076  * WARNING: The C register and register group struct declarations are provided for
39077  * convenience and illustrative purposes. They should, however, be used with
39078  * caution as the C language standard provides no guarantees about the alignment or
39079  * atomicity of device memory accesses. The recommended practice for writing
39080  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
39081  * alt_write_word() functions.
39082  *
39083  * The struct declaration for register ALT_USB_HOST_HCDMA7.
39084  */
39085 struct ALT_USB_HOST_HCDMA7_s
39086 {
39087  uint32_t hcdma7 : 32; /* ALT_USB_HOST_HCDMA7_HCDMA7 */
39088 };
39089 
39090 /* The typedef declaration for register ALT_USB_HOST_HCDMA7. */
39091 typedef volatile struct ALT_USB_HOST_HCDMA7_s ALT_USB_HOST_HCDMA7_t;
39092 #endif /* __ASSEMBLY__ */
39093 
39094 /* The reset value of the ALT_USB_HOST_HCDMA7 register. */
39095 #define ALT_USB_HOST_HCDMA7_RESET 0x00000000
39096 /* The byte offset of the ALT_USB_HOST_HCDMA7 register from the beginning of the component. */
39097 #define ALT_USB_HOST_HCDMA7_OFST 0x1f4
39098 /* The address of the ALT_USB_HOST_HCDMA7 register. */
39099 #define ALT_USB_HOST_HCDMA7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA7_OFST))
39100 
39101 /*
39102  * Register : hcdmab7
39103  *
39104  * Host Channel 7 DMA Buffer Address Register
39105  *
39106  * Register Layout
39107  *
39108  * Bits | Access | Reset | Description
39109  * :-------|:-------|:------|:-----------------------------
39110  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB7_HCDMAB7
39111  *
39112  */
39113 /*
39114  * Field : hcdmab7
39115  *
39116  * Holds the current buffer address.
39117  *
39118  * This register is updated as and when the data transfer for the corresponding end
39119  * point
39120  *
39121  * is in progress. This register is present only in Scatter/Gather DMA mode.
39122  * Otherwise this
39123  *
39124  * field is reserved.
39125  *
39126  * Field Access Macros:
39127  *
39128  */
39129 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */
39130 #define ALT_USB_HOST_HCDMAB7_HCDMAB7_LSB 0
39131 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */
39132 #define ALT_USB_HOST_HCDMAB7_HCDMAB7_MSB 31
39133 /* The width in bits of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */
39134 #define ALT_USB_HOST_HCDMAB7_HCDMAB7_WIDTH 32
39135 /* The mask used to set the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field value. */
39136 #define ALT_USB_HOST_HCDMAB7_HCDMAB7_SET_MSK 0xffffffff
39137 /* The mask used to clear the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field value. */
39138 #define ALT_USB_HOST_HCDMAB7_HCDMAB7_CLR_MSK 0x00000000
39139 /* The reset value of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */
39140 #define ALT_USB_HOST_HCDMAB7_HCDMAB7_RESET 0x0
39141 /* Extracts the ALT_USB_HOST_HCDMAB7_HCDMAB7 field value from a register. */
39142 #define ALT_USB_HOST_HCDMAB7_HCDMAB7_GET(value) (((value) & 0xffffffff) >> 0)
39143 /* Produces a ALT_USB_HOST_HCDMAB7_HCDMAB7 register field value suitable for setting the register. */
39144 #define ALT_USB_HOST_HCDMAB7_HCDMAB7_SET(value) (((value) << 0) & 0xffffffff)
39145 
39146 #ifndef __ASSEMBLY__
39147 /*
39148  * WARNING: The C register and register group struct declarations are provided for
39149  * convenience and illustrative purposes. They should, however, be used with
39150  * caution as the C language standard provides no guarantees about the alignment or
39151  * atomicity of device memory accesses. The recommended practice for writing
39152  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
39153  * alt_write_word() functions.
39154  *
39155  * The struct declaration for register ALT_USB_HOST_HCDMAB7.
39156  */
39157 struct ALT_USB_HOST_HCDMAB7_s
39158 {
39159  uint32_t hcdmab7 : 32; /* ALT_USB_HOST_HCDMAB7_HCDMAB7 */
39160 };
39161 
39162 /* The typedef declaration for register ALT_USB_HOST_HCDMAB7. */
39163 typedef volatile struct ALT_USB_HOST_HCDMAB7_s ALT_USB_HOST_HCDMAB7_t;
39164 #endif /* __ASSEMBLY__ */
39165 
39166 /* The reset value of the ALT_USB_HOST_HCDMAB7 register. */
39167 #define ALT_USB_HOST_HCDMAB7_RESET 0x00000000
39168 /* The byte offset of the ALT_USB_HOST_HCDMAB7 register from the beginning of the component. */
39169 #define ALT_USB_HOST_HCDMAB7_OFST 0x1fc
39170 /* The address of the ALT_USB_HOST_HCDMAB7 register. */
39171 #define ALT_USB_HOST_HCDMAB7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB7_OFST))
39172 
39173 /*
39174  * Register : hcchar8
39175  *
39176  * Host Channel 8 Characteristics Register
39177  *
39178  * Register Layout
39179  *
39180  * Bits | Access | Reset | Description
39181  * :--------|:---------|:------|:-----------------------------
39182  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_MPS
39183  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_EPNUM
39184  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_EPDIR
39185  * [16] | ??? | 0x0 | *UNDEFINED*
39186  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_LSPDDEV
39187  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_EPTYPE
39188  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_EC
39189  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_DEVADDR
39190  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_ODDFRM
39191  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR8_CHDIS
39192  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR8_CHENA
39193  *
39194  */
39195 /*
39196  * Field : mps
39197  *
39198  * Maximum Packet Size (MPS)
39199  *
39200  * Indicates the maximum packet size of the associated endpoint.
39201  *
39202  * Field Access Macros:
39203  *
39204  */
39205 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_MPS register field. */
39206 #define ALT_USB_HOST_HCCHAR8_MPS_LSB 0
39207 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_MPS register field. */
39208 #define ALT_USB_HOST_HCCHAR8_MPS_MSB 10
39209 /* The width in bits of the ALT_USB_HOST_HCCHAR8_MPS register field. */
39210 #define ALT_USB_HOST_HCCHAR8_MPS_WIDTH 11
39211 /* The mask used to set the ALT_USB_HOST_HCCHAR8_MPS register field value. */
39212 #define ALT_USB_HOST_HCCHAR8_MPS_SET_MSK 0x000007ff
39213 /* The mask used to clear the ALT_USB_HOST_HCCHAR8_MPS register field value. */
39214 #define ALT_USB_HOST_HCCHAR8_MPS_CLR_MSK 0xfffff800
39215 /* The reset value of the ALT_USB_HOST_HCCHAR8_MPS register field. */
39216 #define ALT_USB_HOST_HCCHAR8_MPS_RESET 0x0
39217 /* Extracts the ALT_USB_HOST_HCCHAR8_MPS field value from a register. */
39218 #define ALT_USB_HOST_HCCHAR8_MPS_GET(value) (((value) & 0x000007ff) >> 0)
39219 /* Produces a ALT_USB_HOST_HCCHAR8_MPS register field value suitable for setting the register. */
39220 #define ALT_USB_HOST_HCCHAR8_MPS_SET(value) (((value) << 0) & 0x000007ff)
39221 
39222 /*
39223  * Field : epnum
39224  *
39225  * Endpoint Number (EPNum)
39226  *
39227  * Indicates the endpoint number on the device serving as the data
39228  *
39229  * source or sink.
39230  *
39231  * Field Enumeration Values:
39232  *
39233  * Enum | Value | Description
39234  * :-------------------------------------|:------|:--------------
39235  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT0 | 0x0 | End point 0
39236  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT1 | 0x1 | End point 1
39237  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT2 | 0x2 | End point 2
39238  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT3 | 0x3 | End point 3
39239  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT4 | 0x4 | End point 4
39240  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT5 | 0x5 | End point 5
39241  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT6 | 0x6 | End point 6
39242  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT7 | 0x7 | End point 7
39243  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT8 | 0x8 | End point 8
39244  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT9 | 0x9 | End point 9
39245  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT10 | 0xa | End point 10
39246  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT11 | 0xb | End point 11
39247  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT12 | 0xc | End point 12
39248  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT13 | 0xd | End point 13
39249  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT14 | 0xe | End point 14
39250  * ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT15 | 0xf | End point 15
39251  *
39252  * Field Access Macros:
39253  *
39254  */
39255 /*
39256  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39257  *
39258  * End point 0
39259  */
39260 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT0 0x0
39261 /*
39262  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39263  *
39264  * End point 1
39265  */
39266 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT1 0x1
39267 /*
39268  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39269  *
39270  * End point 2
39271  */
39272 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT2 0x2
39273 /*
39274  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39275  *
39276  * End point 3
39277  */
39278 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT3 0x3
39279 /*
39280  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39281  *
39282  * End point 4
39283  */
39284 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT4 0x4
39285 /*
39286  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39287  *
39288  * End point 5
39289  */
39290 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT5 0x5
39291 /*
39292  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39293  *
39294  * End point 6
39295  */
39296 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT6 0x6
39297 /*
39298  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39299  *
39300  * End point 7
39301  */
39302 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT7 0x7
39303 /*
39304  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39305  *
39306  * End point 8
39307  */
39308 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT8 0x8
39309 /*
39310  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39311  *
39312  * End point 9
39313  */
39314 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT9 0x9
39315 /*
39316  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39317  *
39318  * End point 10
39319  */
39320 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT10 0xa
39321 /*
39322  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39323  *
39324  * End point 11
39325  */
39326 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT11 0xb
39327 /*
39328  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39329  *
39330  * End point 12
39331  */
39332 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT12 0xc
39333 /*
39334  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39335  *
39336  * End point 13
39337  */
39338 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT13 0xd
39339 /*
39340  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39341  *
39342  * End point 14
39343  */
39344 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT14 0xe
39345 /*
39346  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
39347  *
39348  * End point 15
39349  */
39350 #define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT15 0xf
39351 
39352 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */
39353 #define ALT_USB_HOST_HCCHAR8_EPNUM_LSB 11
39354 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */
39355 #define ALT_USB_HOST_HCCHAR8_EPNUM_MSB 14
39356 /* The width in bits of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */
39357 #define ALT_USB_HOST_HCCHAR8_EPNUM_WIDTH 4
39358 /* The mask used to set the ALT_USB_HOST_HCCHAR8_EPNUM register field value. */
39359 #define ALT_USB_HOST_HCCHAR8_EPNUM_SET_MSK 0x00007800
39360 /* The mask used to clear the ALT_USB_HOST_HCCHAR8_EPNUM register field value. */
39361 #define ALT_USB_HOST_HCCHAR8_EPNUM_CLR_MSK 0xffff87ff
39362 /* The reset value of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */
39363 #define ALT_USB_HOST_HCCHAR8_EPNUM_RESET 0x0
39364 /* Extracts the ALT_USB_HOST_HCCHAR8_EPNUM field value from a register. */
39365 #define ALT_USB_HOST_HCCHAR8_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
39366 /* Produces a ALT_USB_HOST_HCCHAR8_EPNUM register field value suitable for setting the register. */
39367 #define ALT_USB_HOST_HCCHAR8_EPNUM_SET(value) (((value) << 11) & 0x00007800)
39368 
39369 /*
39370  * Field : epdir
39371  *
39372  * Endpoint Direction (EPDir)
39373  *
39374  * Indicates whether the transaction is IN or OUT.
39375  *
39376  * 1'b0: OUT
39377  *
39378  * 1'b1: IN
39379  *
39380  * Field Enumeration Values:
39381  *
39382  * Enum | Value | Description
39383  * :---------------------------------|:------|:--------------
39384  * ALT_USB_HOST_HCCHAR8_EPDIR_E_OUT | 0x0 | OUT Direction
39385  * ALT_USB_HOST_HCCHAR8_EPDIR_E_IN | 0x1 | IN Direction
39386  *
39387  * Field Access Macros:
39388  *
39389  */
39390 /*
39391  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPDIR
39392  *
39393  * OUT Direction
39394  */
39395 #define ALT_USB_HOST_HCCHAR8_EPDIR_E_OUT 0x0
39396 /*
39397  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPDIR
39398  *
39399  * IN Direction
39400  */
39401 #define ALT_USB_HOST_HCCHAR8_EPDIR_E_IN 0x1
39402 
39403 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */
39404 #define ALT_USB_HOST_HCCHAR8_EPDIR_LSB 15
39405 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */
39406 #define ALT_USB_HOST_HCCHAR8_EPDIR_MSB 15
39407 /* The width in bits of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */
39408 #define ALT_USB_HOST_HCCHAR8_EPDIR_WIDTH 1
39409 /* The mask used to set the ALT_USB_HOST_HCCHAR8_EPDIR register field value. */
39410 #define ALT_USB_HOST_HCCHAR8_EPDIR_SET_MSK 0x00008000
39411 /* The mask used to clear the ALT_USB_HOST_HCCHAR8_EPDIR register field value. */
39412 #define ALT_USB_HOST_HCCHAR8_EPDIR_CLR_MSK 0xffff7fff
39413 /* The reset value of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */
39414 #define ALT_USB_HOST_HCCHAR8_EPDIR_RESET 0x0
39415 /* Extracts the ALT_USB_HOST_HCCHAR8_EPDIR field value from a register. */
39416 #define ALT_USB_HOST_HCCHAR8_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
39417 /* Produces a ALT_USB_HOST_HCCHAR8_EPDIR register field value suitable for setting the register. */
39418 #define ALT_USB_HOST_HCCHAR8_EPDIR_SET(value) (((value) << 15) & 0x00008000)
39419 
39420 /*
39421  * Field : lspddev
39422  *
39423  * Low-Speed Device (LSpdDev)
39424  *
39425  * This field is Set by the application to indicate that this channel is
39426  *
39427  * communicating to a low-speed device.
39428  *
39429  * Field Enumeration Values:
39430  *
39431  * Enum | Value | Description
39432  * :------------------------------------|:------|:----------------------------------------
39433  * ALT_USB_HOST_HCCHAR8_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
39434  * ALT_USB_HOST_HCCHAR8_LSPDDEV_E_END | 0x1 | Communicating with low speed device
39435  *
39436  * Field Access Macros:
39437  *
39438  */
39439 /*
39440  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_LSPDDEV
39441  *
39442  * Not Communicating with low speed device
39443  */
39444 #define ALT_USB_HOST_HCCHAR8_LSPDDEV_E_DISD 0x0
39445 /*
39446  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_LSPDDEV
39447  *
39448  * Communicating with low speed device
39449  */
39450 #define ALT_USB_HOST_HCCHAR8_LSPDDEV_E_END 0x1
39451 
39452 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */
39453 #define ALT_USB_HOST_HCCHAR8_LSPDDEV_LSB 17
39454 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */
39455 #define ALT_USB_HOST_HCCHAR8_LSPDDEV_MSB 17
39456 /* The width in bits of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */
39457 #define ALT_USB_HOST_HCCHAR8_LSPDDEV_WIDTH 1
39458 /* The mask used to set the ALT_USB_HOST_HCCHAR8_LSPDDEV register field value. */
39459 #define ALT_USB_HOST_HCCHAR8_LSPDDEV_SET_MSK 0x00020000
39460 /* The mask used to clear the ALT_USB_HOST_HCCHAR8_LSPDDEV register field value. */
39461 #define ALT_USB_HOST_HCCHAR8_LSPDDEV_CLR_MSK 0xfffdffff
39462 /* The reset value of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */
39463 #define ALT_USB_HOST_HCCHAR8_LSPDDEV_RESET 0x0
39464 /* Extracts the ALT_USB_HOST_HCCHAR8_LSPDDEV field value from a register. */
39465 #define ALT_USB_HOST_HCCHAR8_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
39466 /* Produces a ALT_USB_HOST_HCCHAR8_LSPDDEV register field value suitable for setting the register. */
39467 #define ALT_USB_HOST_HCCHAR8_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
39468 
39469 /*
39470  * Field : eptype
39471  *
39472  * Endpoint Type (EPType)
39473  *
39474  * Indicates the transfer type selected.
39475  *
39476  * 2'b00: Control
39477  *
39478  * 2'b01: Isochronous
39479  *
39480  * 2'b10: Bulk
39481  *
39482  * 2'b11: Interrupt
39483  *
39484  * Field Enumeration Values:
39485  *
39486  * Enum | Value | Description
39487  * :-------------------------------------|:------|:------------
39488  * ALT_USB_HOST_HCCHAR8_EPTYPE_E_CTL | 0x0 | Control
39489  * ALT_USB_HOST_HCCHAR8_EPTYPE_E_ISOC | 0x1 | Isochronous
39490  * ALT_USB_HOST_HCCHAR8_EPTYPE_E_BULK | 0x2 | Bulk
39491  * ALT_USB_HOST_HCCHAR8_EPTYPE_E_INTERR | 0x3 | Interrupt
39492  *
39493  * Field Access Macros:
39494  *
39495  */
39496 /*
39497  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE
39498  *
39499  * Control
39500  */
39501 #define ALT_USB_HOST_HCCHAR8_EPTYPE_E_CTL 0x0
39502 /*
39503  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE
39504  *
39505  * Isochronous
39506  */
39507 #define ALT_USB_HOST_HCCHAR8_EPTYPE_E_ISOC 0x1
39508 /*
39509  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE
39510  *
39511  * Bulk
39512  */
39513 #define ALT_USB_HOST_HCCHAR8_EPTYPE_E_BULK 0x2
39514 /*
39515  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE
39516  *
39517  * Interrupt
39518  */
39519 #define ALT_USB_HOST_HCCHAR8_EPTYPE_E_INTERR 0x3
39520 
39521 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */
39522 #define ALT_USB_HOST_HCCHAR8_EPTYPE_LSB 18
39523 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */
39524 #define ALT_USB_HOST_HCCHAR8_EPTYPE_MSB 19
39525 /* The width in bits of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */
39526 #define ALT_USB_HOST_HCCHAR8_EPTYPE_WIDTH 2
39527 /* The mask used to set the ALT_USB_HOST_HCCHAR8_EPTYPE register field value. */
39528 #define ALT_USB_HOST_HCCHAR8_EPTYPE_SET_MSK 0x000c0000
39529 /* The mask used to clear the ALT_USB_HOST_HCCHAR8_EPTYPE register field value. */
39530 #define ALT_USB_HOST_HCCHAR8_EPTYPE_CLR_MSK 0xfff3ffff
39531 /* The reset value of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */
39532 #define ALT_USB_HOST_HCCHAR8_EPTYPE_RESET 0x0
39533 /* Extracts the ALT_USB_HOST_HCCHAR8_EPTYPE field value from a register. */
39534 #define ALT_USB_HOST_HCCHAR8_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
39535 /* Produces a ALT_USB_HOST_HCCHAR8_EPTYPE register field value suitable for setting the register. */
39536 #define ALT_USB_HOST_HCCHAR8_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
39537 
39538 /*
39539  * Field : ec
39540  *
39541  * Multi Count (MC) / Error Count (EC)
39542  *
39543  * When the Split Enable bit of the Host Channel-n Split Control
39544  *
39545  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
39546  *
39547  * the host the number of transactions that must be executed per
39548  *
39549  * microframe For this periodic endpoint. For non periodic transfers,
39550  *
39551  * this field is used only in DMA mode, and specifies the number
39552  *
39553  * packets to be fetched For this channel before the internal DMA
39554  *
39555  * engine changes arbitration.
39556  *
39557  * 2'b00: Reserved This field yields undefined results.
39558  *
39559  * 2'b01: 1 transaction
39560  *
39561  * 2'b10: 2 transactions to be issued For this endpoint per
39562  *
39563  * microframe
39564  *
39565  * 2'b11: 3 transactions to be issued For this endpoint per
39566  *
39567  * microframe
39568  *
39569  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
39570  *
39571  * number of immediate retries to be performed For a periodic split
39572  *
39573  * transactions on transaction errors. This field must be Set to at
39574  *
39575  * least 2'b01.
39576  *
39577  * Field Enumeration Values:
39578  *
39579  * Enum | Value | Description
39580  * :-------------------------------------|:------|:----------------------------------------------
39581  * ALT_USB_HOST_HCCHAR8_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
39582  * ALT_USB_HOST_HCCHAR8_EC_E_TRANSONE | 0x1 | 1 transaction
39583  * ALT_USB_HOST_HCCHAR8_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
39584  * : | | per microframe
39585  * ALT_USB_HOST_HCCHAR8_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
39586  * : | | per microframe
39587  *
39588  * Field Access Macros:
39589  *
39590  */
39591 /*
39592  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC
39593  *
39594  * Reserved This field yields undefined result
39595  */
39596 #define ALT_USB_HOST_HCCHAR8_EC_E_RSVD 0x0
39597 /*
39598  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC
39599  *
39600  * 1 transaction
39601  */
39602 #define ALT_USB_HOST_HCCHAR8_EC_E_TRANSONE 0x1
39603 /*
39604  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC
39605  *
39606  * 2 transactions to be issued for this endpoint per microframe
39607  */
39608 #define ALT_USB_HOST_HCCHAR8_EC_E_TRANSTWO 0x2
39609 /*
39610  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC
39611  *
39612  * 3 transactions to be issued for this endpoint per microframe
39613  */
39614 #define ALT_USB_HOST_HCCHAR8_EC_E_TRANSTHREE 0x3
39615 
39616 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EC register field. */
39617 #define ALT_USB_HOST_HCCHAR8_EC_LSB 20
39618 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EC register field. */
39619 #define ALT_USB_HOST_HCCHAR8_EC_MSB 21
39620 /* The width in bits of the ALT_USB_HOST_HCCHAR8_EC register field. */
39621 #define ALT_USB_HOST_HCCHAR8_EC_WIDTH 2
39622 /* The mask used to set the ALT_USB_HOST_HCCHAR8_EC register field value. */
39623 #define ALT_USB_HOST_HCCHAR8_EC_SET_MSK 0x00300000
39624 /* The mask used to clear the ALT_USB_HOST_HCCHAR8_EC register field value. */
39625 #define ALT_USB_HOST_HCCHAR8_EC_CLR_MSK 0xffcfffff
39626 /* The reset value of the ALT_USB_HOST_HCCHAR8_EC register field. */
39627 #define ALT_USB_HOST_HCCHAR8_EC_RESET 0x0
39628 /* Extracts the ALT_USB_HOST_HCCHAR8_EC field value from a register. */
39629 #define ALT_USB_HOST_HCCHAR8_EC_GET(value) (((value) & 0x00300000) >> 20)
39630 /* Produces a ALT_USB_HOST_HCCHAR8_EC register field value suitable for setting the register. */
39631 #define ALT_USB_HOST_HCCHAR8_EC_SET(value) (((value) << 20) & 0x00300000)
39632 
39633 /*
39634  * Field : devaddr
39635  *
39636  * Device Address (DevAddr)
39637  *
39638  * This field selects the specific device serving as the data source
39639  *
39640  * or sink.
39641  *
39642  * Field Access Macros:
39643  *
39644  */
39645 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */
39646 #define ALT_USB_HOST_HCCHAR8_DEVADDR_LSB 22
39647 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */
39648 #define ALT_USB_HOST_HCCHAR8_DEVADDR_MSB 28
39649 /* The width in bits of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */
39650 #define ALT_USB_HOST_HCCHAR8_DEVADDR_WIDTH 7
39651 /* The mask used to set the ALT_USB_HOST_HCCHAR8_DEVADDR register field value. */
39652 #define ALT_USB_HOST_HCCHAR8_DEVADDR_SET_MSK 0x1fc00000
39653 /* The mask used to clear the ALT_USB_HOST_HCCHAR8_DEVADDR register field value. */
39654 #define ALT_USB_HOST_HCCHAR8_DEVADDR_CLR_MSK 0xe03fffff
39655 /* The reset value of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */
39656 #define ALT_USB_HOST_HCCHAR8_DEVADDR_RESET 0x0
39657 /* Extracts the ALT_USB_HOST_HCCHAR8_DEVADDR field value from a register. */
39658 #define ALT_USB_HOST_HCCHAR8_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
39659 /* Produces a ALT_USB_HOST_HCCHAR8_DEVADDR register field value suitable for setting the register. */
39660 #define ALT_USB_HOST_HCCHAR8_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
39661 
39662 /*
39663  * Field : oddfrm
39664  *
39665  * Odd Frame (OddFrm)
39666  *
39667  * This field is set (reset) by the application to indicate that the OTG host must
39668  * perform
39669  *
39670  * a transfer in an odd (micro)frame. This field is applicable for only periodic
39671  *
39672  * (isochronous and interrupt) transactions.
39673  *
39674  * 1'b0: Even (micro)frame
39675  *
39676  * 1'b1: Odd (micro)frame
39677  *
39678  * Field Access Macros:
39679  *
39680  */
39681 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_ODDFRM register field. */
39682 #define ALT_USB_HOST_HCCHAR8_ODDFRM_LSB 29
39683 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_ODDFRM register field. */
39684 #define ALT_USB_HOST_HCCHAR8_ODDFRM_MSB 29
39685 /* The width in bits of the ALT_USB_HOST_HCCHAR8_ODDFRM register field. */
39686 #define ALT_USB_HOST_HCCHAR8_ODDFRM_WIDTH 1
39687 /* The mask used to set the ALT_USB_HOST_HCCHAR8_ODDFRM register field value. */
39688 #define ALT_USB_HOST_HCCHAR8_ODDFRM_SET_MSK 0x20000000
39689 /* The mask used to clear the ALT_USB_HOST_HCCHAR8_ODDFRM register field value. */
39690 #define ALT_USB_HOST_HCCHAR8_ODDFRM_CLR_MSK 0xdfffffff
39691 /* The reset value of the ALT_USB_HOST_HCCHAR8_ODDFRM register field. */
39692 #define ALT_USB_HOST_HCCHAR8_ODDFRM_RESET 0x0
39693 /* Extracts the ALT_USB_HOST_HCCHAR8_ODDFRM field value from a register. */
39694 #define ALT_USB_HOST_HCCHAR8_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
39695 /* Produces a ALT_USB_HOST_HCCHAR8_ODDFRM register field value suitable for setting the register. */
39696 #define ALT_USB_HOST_HCCHAR8_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
39697 
39698 /*
39699  * Field : chdis
39700  *
39701  * Channel Disable (ChDis)
39702  *
39703  * The application sets this bit to stop transmitting/receiving data
39704  *
39705  * on a channel, even before the transfer For that channel is
39706  *
39707  * complete. The application must wait For the Channel Disabled
39708  *
39709  * interrupt before treating the channel as disabled.
39710  *
39711  * Field Enumeration Values:
39712  *
39713  * Enum | Value | Description
39714  * :-----------------------------------|:------|:----------------------------
39715  * ALT_USB_HOST_HCCHAR8_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
39716  * ALT_USB_HOST_HCCHAR8_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
39717  *
39718  * Field Access Macros:
39719  *
39720  */
39721 /*
39722  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHDIS
39723  *
39724  * Transmit/Recieve normal
39725  */
39726 #define ALT_USB_HOST_HCCHAR8_CHDIS_E_INACT 0x0
39727 /*
39728  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHDIS
39729  *
39730  * Stop transmitting/receiving
39731  */
39732 #define ALT_USB_HOST_HCCHAR8_CHDIS_E_ACT 0x1
39733 
39734 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */
39735 #define ALT_USB_HOST_HCCHAR8_CHDIS_LSB 30
39736 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */
39737 #define ALT_USB_HOST_HCCHAR8_CHDIS_MSB 30
39738 /* The width in bits of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */
39739 #define ALT_USB_HOST_HCCHAR8_CHDIS_WIDTH 1
39740 /* The mask used to set the ALT_USB_HOST_HCCHAR8_CHDIS register field value. */
39741 #define ALT_USB_HOST_HCCHAR8_CHDIS_SET_MSK 0x40000000
39742 /* The mask used to clear the ALT_USB_HOST_HCCHAR8_CHDIS register field value. */
39743 #define ALT_USB_HOST_HCCHAR8_CHDIS_CLR_MSK 0xbfffffff
39744 /* The reset value of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */
39745 #define ALT_USB_HOST_HCCHAR8_CHDIS_RESET 0x0
39746 /* Extracts the ALT_USB_HOST_HCCHAR8_CHDIS field value from a register. */
39747 #define ALT_USB_HOST_HCCHAR8_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
39748 /* Produces a ALT_USB_HOST_HCCHAR8_CHDIS register field value suitable for setting the register. */
39749 #define ALT_USB_HOST_HCCHAR8_CHDIS_SET(value) (((value) << 30) & 0x40000000)
39750 
39751 /*
39752  * Field : chena
39753  *
39754  * Channel Enable (ChEna)
39755  *
39756  * When Scatter/Gather mode is enabled
39757  *
39758  * 1'b0: Indicates that the descriptor structure is not yet ready.
39759  *
39760  * 1'b1: Indicates that the descriptor structure and data buffer with
39761  *
39762  * data is setup and this channel can access the descriptor.
39763  *
39764  * When Scatter/Gather mode is disabled
39765  *
39766  * This field is set by the application and cleared by the OTG host.
39767  *
39768  * 1'b0: Channel disabled
39769  *
39770  * 1'b1: Channel enabled
39771  *
39772  * Field Enumeration Values:
39773  *
39774  * Enum | Value | Description
39775  * :-----------------------------------|:------|:-------------------------------------------------
39776  * ALT_USB_HOST_HCCHAR8_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
39777  * : | | yet ready
39778  * ALT_USB_HOST_HCCHAR8_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
39779  * : | | data buffer with data is setup and this
39780  * : | | channel can access the descriptor
39781  *
39782  * Field Access Macros:
39783  *
39784  */
39785 /*
39786  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHENA
39787  *
39788  * Indicates that the descriptor structure is not yet ready
39789  */
39790 #define ALT_USB_HOST_HCCHAR8_CHENA_E_INACT 0x0
39791 /*
39792  * Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHENA
39793  *
39794  * Indicates that the descriptor structure and data buffer with data is
39795  * setup and this channel can access the descriptor
39796  */
39797 #define ALT_USB_HOST_HCCHAR8_CHENA_E_ACT 0x1
39798 
39799 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_CHENA register field. */
39800 #define ALT_USB_HOST_HCCHAR8_CHENA_LSB 31
39801 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_CHENA register field. */
39802 #define ALT_USB_HOST_HCCHAR8_CHENA_MSB 31
39803 /* The width in bits of the ALT_USB_HOST_HCCHAR8_CHENA register field. */
39804 #define ALT_USB_HOST_HCCHAR8_CHENA_WIDTH 1
39805 /* The mask used to set the ALT_USB_HOST_HCCHAR8_CHENA register field value. */
39806 #define ALT_USB_HOST_HCCHAR8_CHENA_SET_MSK 0x80000000
39807 /* The mask used to clear the ALT_USB_HOST_HCCHAR8_CHENA register field value. */
39808 #define ALT_USB_HOST_HCCHAR8_CHENA_CLR_MSK 0x7fffffff
39809 /* The reset value of the ALT_USB_HOST_HCCHAR8_CHENA register field. */
39810 #define ALT_USB_HOST_HCCHAR8_CHENA_RESET 0x0
39811 /* Extracts the ALT_USB_HOST_HCCHAR8_CHENA field value from a register. */
39812 #define ALT_USB_HOST_HCCHAR8_CHENA_GET(value) (((value) & 0x80000000) >> 31)
39813 /* Produces a ALT_USB_HOST_HCCHAR8_CHENA register field value suitable for setting the register. */
39814 #define ALT_USB_HOST_HCCHAR8_CHENA_SET(value) (((value) << 31) & 0x80000000)
39815 
39816 #ifndef __ASSEMBLY__
39817 /*
39818  * WARNING: The C register and register group struct declarations are provided for
39819  * convenience and illustrative purposes. They should, however, be used with
39820  * caution as the C language standard provides no guarantees about the alignment or
39821  * atomicity of device memory accesses. The recommended practice for writing
39822  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
39823  * alt_write_word() functions.
39824  *
39825  * The struct declaration for register ALT_USB_HOST_HCCHAR8.
39826  */
39827 struct ALT_USB_HOST_HCCHAR8_s
39828 {
39829  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR8_MPS */
39830  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR8_EPNUM */
39831  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR8_EPDIR */
39832  uint32_t : 1; /* *UNDEFINED* */
39833  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR8_LSPDDEV */
39834  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR8_EPTYPE */
39835  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR8_EC */
39836  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR8_DEVADDR */
39837  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR8_ODDFRM */
39838  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR8_CHDIS */
39839  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR8_CHENA */
39840 };
39841 
39842 /* The typedef declaration for register ALT_USB_HOST_HCCHAR8. */
39843 typedef volatile struct ALT_USB_HOST_HCCHAR8_s ALT_USB_HOST_HCCHAR8_t;
39844 #endif /* __ASSEMBLY__ */
39845 
39846 /* The reset value of the ALT_USB_HOST_HCCHAR8 register. */
39847 #define ALT_USB_HOST_HCCHAR8_RESET 0x00000000
39848 /* The byte offset of the ALT_USB_HOST_HCCHAR8 register from the beginning of the component. */
39849 #define ALT_USB_HOST_HCCHAR8_OFST 0x200
39850 /* The address of the ALT_USB_HOST_HCCHAR8 register. */
39851 #define ALT_USB_HOST_HCCHAR8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR8_OFST))
39852 
39853 /*
39854  * Register : hcsplt8
39855  *
39856  * Host Channel 8 Split Control Register
39857  *
39858  * Register Layout
39859  *
39860  * Bits | Access | Reset | Description
39861  * :--------|:-------|:------|:------------------------------
39862  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT8_PRTADDR
39863  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT8_HUBADDR
39864  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT8_XACTPOS
39865  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT8_COMPSPLT
39866  * [30:17] | ??? | 0x0 | *UNDEFINED*
39867  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT8_SPLTENA
39868  *
39869  */
39870 /*
39871  * Field : prtaddr
39872  *
39873  * Port Address (PrtAddr)
39874  *
39875  * This field is the port number of the recipient transaction
39876  *
39877  * translator.
39878  *
39879  * Field Access Macros:
39880  *
39881  */
39882 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */
39883 #define ALT_USB_HOST_HCSPLT8_PRTADDR_LSB 0
39884 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */
39885 #define ALT_USB_HOST_HCSPLT8_PRTADDR_MSB 6
39886 /* The width in bits of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */
39887 #define ALT_USB_HOST_HCSPLT8_PRTADDR_WIDTH 7
39888 /* The mask used to set the ALT_USB_HOST_HCSPLT8_PRTADDR register field value. */
39889 #define ALT_USB_HOST_HCSPLT8_PRTADDR_SET_MSK 0x0000007f
39890 /* The mask used to clear the ALT_USB_HOST_HCSPLT8_PRTADDR register field value. */
39891 #define ALT_USB_HOST_HCSPLT8_PRTADDR_CLR_MSK 0xffffff80
39892 /* The reset value of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */
39893 #define ALT_USB_HOST_HCSPLT8_PRTADDR_RESET 0x0
39894 /* Extracts the ALT_USB_HOST_HCSPLT8_PRTADDR field value from a register. */
39895 #define ALT_USB_HOST_HCSPLT8_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
39896 /* Produces a ALT_USB_HOST_HCSPLT8_PRTADDR register field value suitable for setting the register. */
39897 #define ALT_USB_HOST_HCSPLT8_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
39898 
39899 /*
39900  * Field : hubaddr
39901  *
39902  * Hub Address (HubAddr)
39903  *
39904  * This field holds the device address of the transaction translator's
39905  *
39906  * hub.
39907  *
39908  * Field Access Macros:
39909  *
39910  */
39911 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */
39912 #define ALT_USB_HOST_HCSPLT8_HUBADDR_LSB 7
39913 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */
39914 #define ALT_USB_HOST_HCSPLT8_HUBADDR_MSB 13
39915 /* The width in bits of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */
39916 #define ALT_USB_HOST_HCSPLT8_HUBADDR_WIDTH 7
39917 /* The mask used to set the ALT_USB_HOST_HCSPLT8_HUBADDR register field value. */
39918 #define ALT_USB_HOST_HCSPLT8_HUBADDR_SET_MSK 0x00003f80
39919 /* The mask used to clear the ALT_USB_HOST_HCSPLT8_HUBADDR register field value. */
39920 #define ALT_USB_HOST_HCSPLT8_HUBADDR_CLR_MSK 0xffffc07f
39921 /* The reset value of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */
39922 #define ALT_USB_HOST_HCSPLT8_HUBADDR_RESET 0x0
39923 /* Extracts the ALT_USB_HOST_HCSPLT8_HUBADDR field value from a register. */
39924 #define ALT_USB_HOST_HCSPLT8_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
39925 /* Produces a ALT_USB_HOST_HCSPLT8_HUBADDR register field value suitable for setting the register. */
39926 #define ALT_USB_HOST_HCSPLT8_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
39927 
39928 /*
39929  * Field : xactpos
39930  *
39931  * Transaction Position (XactPos)
39932  *
39933  * This field is used to determine whether to send all, first, middle,
39934  *
39935  * or last payloads with each OUT transaction.
39936  *
39937  * 2'b11: All. This is the entire data payload is of this transaction
39938  *
39939  * (which is less than or equal to 188 bytes).
39940  *
39941  * 2'b10: Begin. This is the first data payload of this transaction
39942  *
39943  * (which is larger than 188 bytes).
39944  *
39945  * 2'b00: Mid. This is the middle payload of this transaction
39946  *
39947  * (which is larger than 188 bytes).
39948  *
39949  * 2'b01: End. This is the last payload of this transaction (which
39950  *
39951  * is larger than 188 bytes).
39952  *
39953  * Field Enumeration Values:
39954  *
39955  * Enum | Value | Description
39956  * :--------------------------------------|:------|:------------------------------------------------
39957  * ALT_USB_HOST_HCSPLT8_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
39958  * : | | transaction (which is larger than 188 bytes)
39959  * ALT_USB_HOST_HCSPLT8_XACTPOS_E_END | 0x1 | End. This is the last payload of this
39960  * : | | transaction (which is larger than 188 bytes)
39961  * ALT_USB_HOST_HCSPLT8_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
39962  * : | | transaction (which is larger than 188 bytes)
39963  * ALT_USB_HOST_HCSPLT8_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
39964  * : | | transaction (which is less than or equal to 188
39965  * : | | bytes)
39966  *
39967  * Field Access Macros:
39968  *
39969  */
39970 /*
39971  * Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS
39972  *
39973  * Mid. This is the middle payload of this transaction (which is larger than 188
39974  * bytes)
39975  */
39976 #define ALT_USB_HOST_HCSPLT8_XACTPOS_E_MIDDLE 0x0
39977 /*
39978  * Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS
39979  *
39980  * End. This is the last payload of this transaction (which is larger than 188
39981  * bytes)
39982  */
39983 #define ALT_USB_HOST_HCSPLT8_XACTPOS_E_END 0x1
39984 /*
39985  * Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS
39986  *
39987  * Begin. This is the first data payload of this transaction (which is larger than
39988  * 188 bytes)
39989  */
39990 #define ALT_USB_HOST_HCSPLT8_XACTPOS_E_BEGIN 0x2
39991 /*
39992  * Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS
39993  *
39994  * All. This is the entire data payload is of this transaction (which is less than
39995  * or equal to 188 bytes)
39996  */
39997 #define ALT_USB_HOST_HCSPLT8_XACTPOS_E_ALL 0x3
39998 
39999 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */
40000 #define ALT_USB_HOST_HCSPLT8_XACTPOS_LSB 14
40001 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */
40002 #define ALT_USB_HOST_HCSPLT8_XACTPOS_MSB 15
40003 /* The width in bits of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */
40004 #define ALT_USB_HOST_HCSPLT8_XACTPOS_WIDTH 2
40005 /* The mask used to set the ALT_USB_HOST_HCSPLT8_XACTPOS register field value. */
40006 #define ALT_USB_HOST_HCSPLT8_XACTPOS_SET_MSK 0x0000c000
40007 /* The mask used to clear the ALT_USB_HOST_HCSPLT8_XACTPOS register field value. */
40008 #define ALT_USB_HOST_HCSPLT8_XACTPOS_CLR_MSK 0xffff3fff
40009 /* The reset value of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */
40010 #define ALT_USB_HOST_HCSPLT8_XACTPOS_RESET 0x0
40011 /* Extracts the ALT_USB_HOST_HCSPLT8_XACTPOS field value from a register. */
40012 #define ALT_USB_HOST_HCSPLT8_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
40013 /* Produces a ALT_USB_HOST_HCSPLT8_XACTPOS register field value suitable for setting the register. */
40014 #define ALT_USB_HOST_HCSPLT8_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
40015 
40016 /*
40017  * Field : compsplt
40018  *
40019  * Do Complete Split (CompSplt)
40020  *
40021  * The application sets this field to request the OTG host to perform
40022  *
40023  * a complete split transaction.
40024  *
40025  * Field Enumeration Values:
40026  *
40027  * Enum | Value | Description
40028  * :----------------------------------------|:------|:---------------------
40029  * ALT_USB_HOST_HCSPLT8_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
40030  * ALT_USB_HOST_HCSPLT8_COMPSPLT_E_SPLIT | 0x1 | Split transaction
40031  *
40032  * Field Access Macros:
40033  *
40034  */
40035 /*
40036  * Enumerated value for register field ALT_USB_HOST_HCSPLT8_COMPSPLT
40037  *
40038  * No split transaction
40039  */
40040 #define ALT_USB_HOST_HCSPLT8_COMPSPLT_E_NOSPLIT 0x0
40041 /*
40042  * Enumerated value for register field ALT_USB_HOST_HCSPLT8_COMPSPLT
40043  *
40044  * Split transaction
40045  */
40046 #define ALT_USB_HOST_HCSPLT8_COMPSPLT_E_SPLIT 0x1
40047 
40048 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */
40049 #define ALT_USB_HOST_HCSPLT8_COMPSPLT_LSB 16
40050 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */
40051 #define ALT_USB_HOST_HCSPLT8_COMPSPLT_MSB 16
40052 /* The width in bits of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */
40053 #define ALT_USB_HOST_HCSPLT8_COMPSPLT_WIDTH 1
40054 /* The mask used to set the ALT_USB_HOST_HCSPLT8_COMPSPLT register field value. */
40055 #define ALT_USB_HOST_HCSPLT8_COMPSPLT_SET_MSK 0x00010000
40056 /* The mask used to clear the ALT_USB_HOST_HCSPLT8_COMPSPLT register field value. */
40057 #define ALT_USB_HOST_HCSPLT8_COMPSPLT_CLR_MSK 0xfffeffff
40058 /* The reset value of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */
40059 #define ALT_USB_HOST_HCSPLT8_COMPSPLT_RESET 0x0
40060 /* Extracts the ALT_USB_HOST_HCSPLT8_COMPSPLT field value from a register. */
40061 #define ALT_USB_HOST_HCSPLT8_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
40062 /* Produces a ALT_USB_HOST_HCSPLT8_COMPSPLT register field value suitable for setting the register. */
40063 #define ALT_USB_HOST_HCSPLT8_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
40064 
40065 /*
40066  * Field : spltena
40067  *
40068  * Split Enable (SpltEna)
40069  *
40070  * The application sets this field to indicate that this channel is
40071  *
40072  * enabled to perform split transactions.
40073  *
40074  * Field Enumeration Values:
40075  *
40076  * Enum | Value | Description
40077  * :------------------------------------|:------|:------------------
40078  * ALT_USB_HOST_HCSPLT8_SPLTENA_E_DISD | 0x0 | Split not enabled
40079  * ALT_USB_HOST_HCSPLT8_SPLTENA_E_END | 0x1 | Split enabled
40080  *
40081  * Field Access Macros:
40082  *
40083  */
40084 /*
40085  * Enumerated value for register field ALT_USB_HOST_HCSPLT8_SPLTENA
40086  *
40087  * Split not enabled
40088  */
40089 #define ALT_USB_HOST_HCSPLT8_SPLTENA_E_DISD 0x0
40090 /*
40091  * Enumerated value for register field ALT_USB_HOST_HCSPLT8_SPLTENA
40092  *
40093  * Split enabled
40094  */
40095 #define ALT_USB_HOST_HCSPLT8_SPLTENA_E_END 0x1
40096 
40097 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */
40098 #define ALT_USB_HOST_HCSPLT8_SPLTENA_LSB 31
40099 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */
40100 #define ALT_USB_HOST_HCSPLT8_SPLTENA_MSB 31
40101 /* The width in bits of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */
40102 #define ALT_USB_HOST_HCSPLT8_SPLTENA_WIDTH 1
40103 /* The mask used to set the ALT_USB_HOST_HCSPLT8_SPLTENA register field value. */
40104 #define ALT_USB_HOST_HCSPLT8_SPLTENA_SET_MSK 0x80000000
40105 /* The mask used to clear the ALT_USB_HOST_HCSPLT8_SPLTENA register field value. */
40106 #define ALT_USB_HOST_HCSPLT8_SPLTENA_CLR_MSK 0x7fffffff
40107 /* The reset value of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */
40108 #define ALT_USB_HOST_HCSPLT8_SPLTENA_RESET 0x0
40109 /* Extracts the ALT_USB_HOST_HCSPLT8_SPLTENA field value from a register. */
40110 #define ALT_USB_HOST_HCSPLT8_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
40111 /* Produces a ALT_USB_HOST_HCSPLT8_SPLTENA register field value suitable for setting the register. */
40112 #define ALT_USB_HOST_HCSPLT8_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
40113 
40114 #ifndef __ASSEMBLY__
40115 /*
40116  * WARNING: The C register and register group struct declarations are provided for
40117  * convenience and illustrative purposes. They should, however, be used with
40118  * caution as the C language standard provides no guarantees about the alignment or
40119  * atomicity of device memory accesses. The recommended practice for writing
40120  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
40121  * alt_write_word() functions.
40122  *
40123  * The struct declaration for register ALT_USB_HOST_HCSPLT8.
40124  */
40125 struct ALT_USB_HOST_HCSPLT8_s
40126 {
40127  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT8_PRTADDR */
40128  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT8_HUBADDR */
40129  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT8_XACTPOS */
40130  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT8_COMPSPLT */
40131  uint32_t : 14; /* *UNDEFINED* */
40132  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT8_SPLTENA */
40133 };
40134 
40135 /* The typedef declaration for register ALT_USB_HOST_HCSPLT8. */
40136 typedef volatile struct ALT_USB_HOST_HCSPLT8_s ALT_USB_HOST_HCSPLT8_t;
40137 #endif /* __ASSEMBLY__ */
40138 
40139 /* The reset value of the ALT_USB_HOST_HCSPLT8 register. */
40140 #define ALT_USB_HOST_HCSPLT8_RESET 0x00000000
40141 /* The byte offset of the ALT_USB_HOST_HCSPLT8 register from the beginning of the component. */
40142 #define ALT_USB_HOST_HCSPLT8_OFST 0x204
40143 /* The address of the ALT_USB_HOST_HCSPLT8 register. */
40144 #define ALT_USB_HOST_HCSPLT8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT8_OFST))
40145 
40146 /*
40147  * Register : hcint8
40148  *
40149  * Host Channel 8 Interrupt Register
40150  *
40151  * Register Layout
40152  *
40153  * Bits | Access | Reset | Description
40154  * :--------|:-------|:------|:--------------------------------------
40155  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT8_XFERCOMPL
40156  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT8_CHHLTD
40157  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT8_AHBERR
40158  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT8_STALL
40159  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT8_NAK
40160  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT8_ACK
40161  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT8_NYET
40162  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT8_XACTERR
40163  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT8_BBLERR
40164  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT8_FRMOVRUN
40165  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT8_DATATGLERR
40166  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT8_BNAINTR
40167  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT8_XCS_XACT_ERR
40168  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR
40169  * [31:14] | ??? | 0x0 | *UNDEFINED*
40170  *
40171  */
40172 /*
40173  * Field : xfercompl
40174  *
40175  * Transfer Completed (XferCompl)
40176  *
40177  * Transfer completed normally without any errors.This bit can be set only by the
40178  * core and the application should write 1 to clear it.
40179  *
40180  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
40181  *
40182  * completed with IOC bit set in its descriptor.
40183  *
40184  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
40185  * without
40186  *
40187  * any errors.
40188  *
40189  * Field Enumeration Values:
40190  *
40191  * Enum | Value | Description
40192  * :--------------------------------------|:------|:-----------------------------------------------
40193  * ALT_USB_HOST_HCINT8_XFERCOMPL_E_INACT | 0x0 | No transfer
40194  * ALT_USB_HOST_HCINT8_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
40195  *
40196  * Field Access Macros:
40197  *
40198  */
40199 /*
40200  * Enumerated value for register field ALT_USB_HOST_HCINT8_XFERCOMPL
40201  *
40202  * No transfer
40203  */
40204 #define ALT_USB_HOST_HCINT8_XFERCOMPL_E_INACT 0x0
40205 /*
40206  * Enumerated value for register field ALT_USB_HOST_HCINT8_XFERCOMPL
40207  *
40208  * Transfer completed normally without any errors
40209  */
40210 #define ALT_USB_HOST_HCINT8_XFERCOMPL_E_ACT 0x1
40211 
40212 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */
40213 #define ALT_USB_HOST_HCINT8_XFERCOMPL_LSB 0
40214 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */
40215 #define ALT_USB_HOST_HCINT8_XFERCOMPL_MSB 0
40216 /* The width in bits of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */
40217 #define ALT_USB_HOST_HCINT8_XFERCOMPL_WIDTH 1
40218 /* The mask used to set the ALT_USB_HOST_HCINT8_XFERCOMPL register field value. */
40219 #define ALT_USB_HOST_HCINT8_XFERCOMPL_SET_MSK 0x00000001
40220 /* The mask used to clear the ALT_USB_HOST_HCINT8_XFERCOMPL register field value. */
40221 #define ALT_USB_HOST_HCINT8_XFERCOMPL_CLR_MSK 0xfffffffe
40222 /* The reset value of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */
40223 #define ALT_USB_HOST_HCINT8_XFERCOMPL_RESET 0x0
40224 /* Extracts the ALT_USB_HOST_HCINT8_XFERCOMPL field value from a register. */
40225 #define ALT_USB_HOST_HCINT8_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
40226 /* Produces a ALT_USB_HOST_HCINT8_XFERCOMPL register field value suitable for setting the register. */
40227 #define ALT_USB_HOST_HCINT8_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
40228 
40229 /*
40230  * Field : chhltd
40231  *
40232  * Channel Halted (ChHltd)
40233  *
40234  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
40235  * either because of any USB transaction error or in response to disable request by
40236  * the application or because of a completed transfer.
40237  *
40238  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
40239  * the following
40240  *
40241  * . EOL being set in descriptor
40242  *
40243  * . AHB error
40244  *
40245  * . Excessive transaction errors
40246  *
40247  * . Babble
40248  *
40249  * . Stall
40250  *
40251  * Field Enumeration Values:
40252  *
40253  * Enum | Value | Description
40254  * :-----------------------------------|:------|:-------------------
40255  * ALT_USB_HOST_HCINT8_CHHLTD_E_INACT | 0x0 | Channel not halted
40256  * ALT_USB_HOST_HCINT8_CHHLTD_E_ACT | 0x1 | Channel Halted
40257  *
40258  * Field Access Macros:
40259  *
40260  */
40261 /*
40262  * Enumerated value for register field ALT_USB_HOST_HCINT8_CHHLTD
40263  *
40264  * Channel not halted
40265  */
40266 #define ALT_USB_HOST_HCINT8_CHHLTD_E_INACT 0x0
40267 /*
40268  * Enumerated value for register field ALT_USB_HOST_HCINT8_CHHLTD
40269  *
40270  * Channel Halted
40271  */
40272 #define ALT_USB_HOST_HCINT8_CHHLTD_E_ACT 0x1
40273 
40274 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_CHHLTD register field. */
40275 #define ALT_USB_HOST_HCINT8_CHHLTD_LSB 1
40276 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_CHHLTD register field. */
40277 #define ALT_USB_HOST_HCINT8_CHHLTD_MSB 1
40278 /* The width in bits of the ALT_USB_HOST_HCINT8_CHHLTD register field. */
40279 #define ALT_USB_HOST_HCINT8_CHHLTD_WIDTH 1
40280 /* The mask used to set the ALT_USB_HOST_HCINT8_CHHLTD register field value. */
40281 #define ALT_USB_HOST_HCINT8_CHHLTD_SET_MSK 0x00000002
40282 /* The mask used to clear the ALT_USB_HOST_HCINT8_CHHLTD register field value. */
40283 #define ALT_USB_HOST_HCINT8_CHHLTD_CLR_MSK 0xfffffffd
40284 /* The reset value of the ALT_USB_HOST_HCINT8_CHHLTD register field. */
40285 #define ALT_USB_HOST_HCINT8_CHHLTD_RESET 0x0
40286 /* Extracts the ALT_USB_HOST_HCINT8_CHHLTD field value from a register. */
40287 #define ALT_USB_HOST_HCINT8_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
40288 /* Produces a ALT_USB_HOST_HCINT8_CHHLTD register field value suitable for setting the register. */
40289 #define ALT_USB_HOST_HCINT8_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
40290 
40291 /*
40292  * Field : ahberr
40293  *
40294  * AHB Error (AHBErr)
40295  *
40296  * This is generated only in Internal DMA mode when there is an
40297  *
40298  * AHB error during AHB read/write. The application can read the
40299  *
40300  * corresponding channel's DMA address register to get the error
40301  *
40302  * address.
40303  *
40304  * Field Enumeration Values:
40305  *
40306  * Enum | Value | Description
40307  * :-----------------------------------|:------|:--------------------------------
40308  * ALT_USB_HOST_HCINT8_AHBERR_E_INACT | 0x0 | No AHB error
40309  * ALT_USB_HOST_HCINT8_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
40310  *
40311  * Field Access Macros:
40312  *
40313  */
40314 /*
40315  * Enumerated value for register field ALT_USB_HOST_HCINT8_AHBERR
40316  *
40317  * No AHB error
40318  */
40319 #define ALT_USB_HOST_HCINT8_AHBERR_E_INACT 0x0
40320 /*
40321  * Enumerated value for register field ALT_USB_HOST_HCINT8_AHBERR
40322  *
40323  * AHB error during AHB read/write
40324  */
40325 #define ALT_USB_HOST_HCINT8_AHBERR_E_ACT 0x1
40326 
40327 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_AHBERR register field. */
40328 #define ALT_USB_HOST_HCINT8_AHBERR_LSB 2
40329 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_AHBERR register field. */
40330 #define ALT_USB_HOST_HCINT8_AHBERR_MSB 2
40331 /* The width in bits of the ALT_USB_HOST_HCINT8_AHBERR register field. */
40332 #define ALT_USB_HOST_HCINT8_AHBERR_WIDTH 1
40333 /* The mask used to set the ALT_USB_HOST_HCINT8_AHBERR register field value. */
40334 #define ALT_USB_HOST_HCINT8_AHBERR_SET_MSK 0x00000004
40335 /* The mask used to clear the ALT_USB_HOST_HCINT8_AHBERR register field value. */
40336 #define ALT_USB_HOST_HCINT8_AHBERR_CLR_MSK 0xfffffffb
40337 /* The reset value of the ALT_USB_HOST_HCINT8_AHBERR register field. */
40338 #define ALT_USB_HOST_HCINT8_AHBERR_RESET 0x0
40339 /* Extracts the ALT_USB_HOST_HCINT8_AHBERR field value from a register. */
40340 #define ALT_USB_HOST_HCINT8_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
40341 /* Produces a ALT_USB_HOST_HCINT8_AHBERR register field value suitable for setting the register. */
40342 #define ALT_USB_HOST_HCINT8_AHBERR_SET(value) (((value) << 2) & 0x00000004)
40343 
40344 /*
40345  * Field : stall
40346  *
40347  * STALL Response Received Interrupt (STALL)
40348  *
40349  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
40350  *
40351  * in the core.This bit can be set only by the core and the application should
40352  * write 1 to clear
40353  *
40354  * it.
40355  *
40356  * Field Enumeration Values:
40357  *
40358  * Enum | Value | Description
40359  * :----------------------------------|:------|:-------------------
40360  * ALT_USB_HOST_HCINT8_STALL_E_INACT | 0x0 | No Stall Interrupt
40361  * ALT_USB_HOST_HCINT8_STALL_E_ACT | 0x1 | Stall Interrupt
40362  *
40363  * Field Access Macros:
40364  *
40365  */
40366 /*
40367  * Enumerated value for register field ALT_USB_HOST_HCINT8_STALL
40368  *
40369  * No Stall Interrupt
40370  */
40371 #define ALT_USB_HOST_HCINT8_STALL_E_INACT 0x0
40372 /*
40373  * Enumerated value for register field ALT_USB_HOST_HCINT8_STALL
40374  *
40375  * Stall Interrupt
40376  */
40377 #define ALT_USB_HOST_HCINT8_STALL_E_ACT 0x1
40378 
40379 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_STALL register field. */
40380 #define ALT_USB_HOST_HCINT8_STALL_LSB 3
40381 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_STALL register field. */
40382 #define ALT_USB_HOST_HCINT8_STALL_MSB 3
40383 /* The width in bits of the ALT_USB_HOST_HCINT8_STALL register field. */
40384 #define ALT_USB_HOST_HCINT8_STALL_WIDTH 1
40385 /* The mask used to set the ALT_USB_HOST_HCINT8_STALL register field value. */
40386 #define ALT_USB_HOST_HCINT8_STALL_SET_MSK 0x00000008
40387 /* The mask used to clear the ALT_USB_HOST_HCINT8_STALL register field value. */
40388 #define ALT_USB_HOST_HCINT8_STALL_CLR_MSK 0xfffffff7
40389 /* The reset value of the ALT_USB_HOST_HCINT8_STALL register field. */
40390 #define ALT_USB_HOST_HCINT8_STALL_RESET 0x0
40391 /* Extracts the ALT_USB_HOST_HCINT8_STALL field value from a register. */
40392 #define ALT_USB_HOST_HCINT8_STALL_GET(value) (((value) & 0x00000008) >> 3)
40393 /* Produces a ALT_USB_HOST_HCINT8_STALL register field value suitable for setting the register. */
40394 #define ALT_USB_HOST_HCINT8_STALL_SET(value) (((value) << 3) & 0x00000008)
40395 
40396 /*
40397  * Field : nak
40398  *
40399  * NAK Response Received Interrupt (NAK)
40400  *
40401  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
40402  *
40403  * in the core.This bit can be set only by the core and the application should
40404  * write 1 to clear
40405  *
40406  * it.
40407  *
40408  * Field Enumeration Values:
40409  *
40410  * Enum | Value | Description
40411  * :--------------------------------|:------|:-----------------------------------
40412  * ALT_USB_HOST_HCINT8_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
40413  * ALT_USB_HOST_HCINT8_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
40414  *
40415  * Field Access Macros:
40416  *
40417  */
40418 /*
40419  * Enumerated value for register field ALT_USB_HOST_HCINT8_NAK
40420  *
40421  * No NAK Response Received Interrupt
40422  */
40423 #define ALT_USB_HOST_HCINT8_NAK_E_INACT 0x0
40424 /*
40425  * Enumerated value for register field ALT_USB_HOST_HCINT8_NAK
40426  *
40427  * NAK Response Received Interrupt
40428  */
40429 #define ALT_USB_HOST_HCINT8_NAK_E_ACT 0x1
40430 
40431 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_NAK register field. */
40432 #define ALT_USB_HOST_HCINT8_NAK_LSB 4
40433 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_NAK register field. */
40434 #define ALT_USB_HOST_HCINT8_NAK_MSB 4
40435 /* The width in bits of the ALT_USB_HOST_HCINT8_NAK register field. */
40436 #define ALT_USB_HOST_HCINT8_NAK_WIDTH 1
40437 /* The mask used to set the ALT_USB_HOST_HCINT8_NAK register field value. */
40438 #define ALT_USB_HOST_HCINT8_NAK_SET_MSK 0x00000010
40439 /* The mask used to clear the ALT_USB_HOST_HCINT8_NAK register field value. */
40440 #define ALT_USB_HOST_HCINT8_NAK_CLR_MSK 0xffffffef
40441 /* The reset value of the ALT_USB_HOST_HCINT8_NAK register field. */
40442 #define ALT_USB_HOST_HCINT8_NAK_RESET 0x0
40443 /* Extracts the ALT_USB_HOST_HCINT8_NAK field value from a register. */
40444 #define ALT_USB_HOST_HCINT8_NAK_GET(value) (((value) & 0x00000010) >> 4)
40445 /* Produces a ALT_USB_HOST_HCINT8_NAK register field value suitable for setting the register. */
40446 #define ALT_USB_HOST_HCINT8_NAK_SET(value) (((value) << 4) & 0x00000010)
40447 
40448 /*
40449  * Field : ack
40450  *
40451  * ACK Response Received/Transmitted Interrupt (ACK)
40452  *
40453  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
40454  *
40455  * in the core.This bit can be set only by the core and the application should
40456  * write 1 to clear
40457  *
40458  * it.
40459  *
40460  * Field Enumeration Values:
40461  *
40462  * Enum | Value | Description
40463  * :--------------------------------|:------|:-----------------------------------------------
40464  * ALT_USB_HOST_HCINT8_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
40465  * ALT_USB_HOST_HCINT8_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
40466  *
40467  * Field Access Macros:
40468  *
40469  */
40470 /*
40471  * Enumerated value for register field ALT_USB_HOST_HCINT8_ACK
40472  *
40473  * No ACK Response Received Transmitted Interrupt
40474  */
40475 #define ALT_USB_HOST_HCINT8_ACK_E_INACT 0x0
40476 /*
40477  * Enumerated value for register field ALT_USB_HOST_HCINT8_ACK
40478  *
40479  * ACK Response Received Transmitted Interrup
40480  */
40481 #define ALT_USB_HOST_HCINT8_ACK_E_ACT 0x1
40482 
40483 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_ACK register field. */
40484 #define ALT_USB_HOST_HCINT8_ACK_LSB 5
40485 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_ACK register field. */
40486 #define ALT_USB_HOST_HCINT8_ACK_MSB 5
40487 /* The width in bits of the ALT_USB_HOST_HCINT8_ACK register field. */
40488 #define ALT_USB_HOST_HCINT8_ACK_WIDTH 1
40489 /* The mask used to set the ALT_USB_HOST_HCINT8_ACK register field value. */
40490 #define ALT_USB_HOST_HCINT8_ACK_SET_MSK 0x00000020
40491 /* The mask used to clear the ALT_USB_HOST_HCINT8_ACK register field value. */
40492 #define ALT_USB_HOST_HCINT8_ACK_CLR_MSK 0xffffffdf
40493 /* The reset value of the ALT_USB_HOST_HCINT8_ACK register field. */
40494 #define ALT_USB_HOST_HCINT8_ACK_RESET 0x0
40495 /* Extracts the ALT_USB_HOST_HCINT8_ACK field value from a register. */
40496 #define ALT_USB_HOST_HCINT8_ACK_GET(value) (((value) & 0x00000020) >> 5)
40497 /* Produces a ALT_USB_HOST_HCINT8_ACK register field value suitable for setting the register. */
40498 #define ALT_USB_HOST_HCINT8_ACK_SET(value) (((value) << 5) & 0x00000020)
40499 
40500 /*
40501  * Field : nyet
40502  *
40503  * NYET Response Received Interrupt (NYET)
40504  *
40505  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
40506  *
40507  * in the core.This bit can be set only by the core and the application should
40508  * write 1 to clear
40509  *
40510  * it.
40511  *
40512  * Field Enumeration Values:
40513  *
40514  * Enum | Value | Description
40515  * :---------------------------------|:------|:------------------------------------
40516  * ALT_USB_HOST_HCINT8_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
40517  * ALT_USB_HOST_HCINT8_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
40518  *
40519  * Field Access Macros:
40520  *
40521  */
40522 /*
40523  * Enumerated value for register field ALT_USB_HOST_HCINT8_NYET
40524  *
40525  * No NYET Response Received Interrupt
40526  */
40527 #define ALT_USB_HOST_HCINT8_NYET_E_INACT 0x0
40528 /*
40529  * Enumerated value for register field ALT_USB_HOST_HCINT8_NYET
40530  *
40531  * NYET Response Received Interrupt
40532  */
40533 #define ALT_USB_HOST_HCINT8_NYET_E_ACT 0x1
40534 
40535 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_NYET register field. */
40536 #define ALT_USB_HOST_HCINT8_NYET_LSB 6
40537 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_NYET register field. */
40538 #define ALT_USB_HOST_HCINT8_NYET_MSB 6
40539 /* The width in bits of the ALT_USB_HOST_HCINT8_NYET register field. */
40540 #define ALT_USB_HOST_HCINT8_NYET_WIDTH 1
40541 /* The mask used to set the ALT_USB_HOST_HCINT8_NYET register field value. */
40542 #define ALT_USB_HOST_HCINT8_NYET_SET_MSK 0x00000040
40543 /* The mask used to clear the ALT_USB_HOST_HCINT8_NYET register field value. */
40544 #define ALT_USB_HOST_HCINT8_NYET_CLR_MSK 0xffffffbf
40545 /* The reset value of the ALT_USB_HOST_HCINT8_NYET register field. */
40546 #define ALT_USB_HOST_HCINT8_NYET_RESET 0x0
40547 /* Extracts the ALT_USB_HOST_HCINT8_NYET field value from a register. */
40548 #define ALT_USB_HOST_HCINT8_NYET_GET(value) (((value) & 0x00000040) >> 6)
40549 /* Produces a ALT_USB_HOST_HCINT8_NYET register field value suitable for setting the register. */
40550 #define ALT_USB_HOST_HCINT8_NYET_SET(value) (((value) << 6) & 0x00000040)
40551 
40552 /*
40553  * Field : xacterr
40554  *
40555  * Transaction Error (XactErr)
40556  *
40557  * Indicates one of the following errors occurred on the USB.
40558  *
40559  * CRC check failure
40560  *
40561  * Timeout
40562  *
40563  * Bit stuff error
40564  *
40565  * False EOP
40566  *
40567  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
40568  *
40569  * in the core.This bit can be set only by the core and the application should
40570  * write 1 to clear
40571  *
40572  * it.
40573  *
40574  * Field Enumeration Values:
40575  *
40576  * Enum | Value | Description
40577  * :------------------------------------|:------|:---------------------
40578  * ALT_USB_HOST_HCINT8_XACTERR_E_INACT | 0x0 | No Transaction Error
40579  * ALT_USB_HOST_HCINT8_XACTERR_E_ACT | 0x1 | Transaction Error
40580  *
40581  * Field Access Macros:
40582  *
40583  */
40584 /*
40585  * Enumerated value for register field ALT_USB_HOST_HCINT8_XACTERR
40586  *
40587  * No Transaction Error
40588  */
40589 #define ALT_USB_HOST_HCINT8_XACTERR_E_INACT 0x0
40590 /*
40591  * Enumerated value for register field ALT_USB_HOST_HCINT8_XACTERR
40592  *
40593  * Transaction Error
40594  */
40595 #define ALT_USB_HOST_HCINT8_XACTERR_E_ACT 0x1
40596 
40597 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_XACTERR register field. */
40598 #define ALT_USB_HOST_HCINT8_XACTERR_LSB 7
40599 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_XACTERR register field. */
40600 #define ALT_USB_HOST_HCINT8_XACTERR_MSB 7
40601 /* The width in bits of the ALT_USB_HOST_HCINT8_XACTERR register field. */
40602 #define ALT_USB_HOST_HCINT8_XACTERR_WIDTH 1
40603 /* The mask used to set the ALT_USB_HOST_HCINT8_XACTERR register field value. */
40604 #define ALT_USB_HOST_HCINT8_XACTERR_SET_MSK 0x00000080
40605 /* The mask used to clear the ALT_USB_HOST_HCINT8_XACTERR register field value. */
40606 #define ALT_USB_HOST_HCINT8_XACTERR_CLR_MSK 0xffffff7f
40607 /* The reset value of the ALT_USB_HOST_HCINT8_XACTERR register field. */
40608 #define ALT_USB_HOST_HCINT8_XACTERR_RESET 0x0
40609 /* Extracts the ALT_USB_HOST_HCINT8_XACTERR field value from a register. */
40610 #define ALT_USB_HOST_HCINT8_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
40611 /* Produces a ALT_USB_HOST_HCINT8_XACTERR register field value suitable for setting the register. */
40612 #define ALT_USB_HOST_HCINT8_XACTERR_SET(value) (((value) << 7) & 0x00000080)
40613 
40614 /*
40615  * Field : bblerr
40616  *
40617  * Babble Error (BblErr)
40618  *
40619  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
40620  *
40621  * in the core..This bit can be set only by the core and the application should
40622  * write 1 to clear
40623  *
40624  * it.
40625  *
40626  * Field Enumeration Values:
40627  *
40628  * Enum | Value | Description
40629  * :-----------------------------------|:------|:----------------
40630  * ALT_USB_HOST_HCINT8_BBLERR_E_INACT | 0x0 | No Babble Error
40631  * ALT_USB_HOST_HCINT8_BBLERR_E_ACT | 0x1 | Babble Error
40632  *
40633  * Field Access Macros:
40634  *
40635  */
40636 /*
40637  * Enumerated value for register field ALT_USB_HOST_HCINT8_BBLERR
40638  *
40639  * No Babble Error
40640  */
40641 #define ALT_USB_HOST_HCINT8_BBLERR_E_INACT 0x0
40642 /*
40643  * Enumerated value for register field ALT_USB_HOST_HCINT8_BBLERR
40644  *
40645  * Babble Error
40646  */
40647 #define ALT_USB_HOST_HCINT8_BBLERR_E_ACT 0x1
40648 
40649 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_BBLERR register field. */
40650 #define ALT_USB_HOST_HCINT8_BBLERR_LSB 8
40651 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_BBLERR register field. */
40652 #define ALT_USB_HOST_HCINT8_BBLERR_MSB 8
40653 /* The width in bits of the ALT_USB_HOST_HCINT8_BBLERR register field. */
40654 #define ALT_USB_HOST_HCINT8_BBLERR_WIDTH 1
40655 /* The mask used to set the ALT_USB_HOST_HCINT8_BBLERR register field value. */
40656 #define ALT_USB_HOST_HCINT8_BBLERR_SET_MSK 0x00000100
40657 /* The mask used to clear the ALT_USB_HOST_HCINT8_BBLERR register field value. */
40658 #define ALT_USB_HOST_HCINT8_BBLERR_CLR_MSK 0xfffffeff
40659 /* The reset value of the ALT_USB_HOST_HCINT8_BBLERR register field. */
40660 #define ALT_USB_HOST_HCINT8_BBLERR_RESET 0x0
40661 /* Extracts the ALT_USB_HOST_HCINT8_BBLERR field value from a register. */
40662 #define ALT_USB_HOST_HCINT8_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
40663 /* Produces a ALT_USB_HOST_HCINT8_BBLERR register field value suitable for setting the register. */
40664 #define ALT_USB_HOST_HCINT8_BBLERR_SET(value) (((value) << 8) & 0x00000100)
40665 
40666 /*
40667  * Field : frmovrun
40668  *
40669  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
40670  * bit is masked
40671  *
40672  * in the core.This bit can be set only by the core and the application should
40673  * write 1 to clear
40674  *
40675  * it.
40676  *
40677  * Field Enumeration Values:
40678  *
40679  * Enum | Value | Description
40680  * :-------------------------------------|:------|:-----------------
40681  * ALT_USB_HOST_HCINT8_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
40682  * ALT_USB_HOST_HCINT8_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
40683  *
40684  * Field Access Macros:
40685  *
40686  */
40687 /*
40688  * Enumerated value for register field ALT_USB_HOST_HCINT8_FRMOVRUN
40689  *
40690  * No Frame Overrun
40691  */
40692 #define ALT_USB_HOST_HCINT8_FRMOVRUN_E_INACT 0x0
40693 /*
40694  * Enumerated value for register field ALT_USB_HOST_HCINT8_FRMOVRUN
40695  *
40696  * Frame Overrun
40697  */
40698 #define ALT_USB_HOST_HCINT8_FRMOVRUN_E_ACT 0x1
40699 
40700 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */
40701 #define ALT_USB_HOST_HCINT8_FRMOVRUN_LSB 9
40702 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */
40703 #define ALT_USB_HOST_HCINT8_FRMOVRUN_MSB 9
40704 /* The width in bits of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */
40705 #define ALT_USB_HOST_HCINT8_FRMOVRUN_WIDTH 1
40706 /* The mask used to set the ALT_USB_HOST_HCINT8_FRMOVRUN register field value. */
40707 #define ALT_USB_HOST_HCINT8_FRMOVRUN_SET_MSK 0x00000200
40708 /* The mask used to clear the ALT_USB_HOST_HCINT8_FRMOVRUN register field value. */
40709 #define ALT_USB_HOST_HCINT8_FRMOVRUN_CLR_MSK 0xfffffdff
40710 /* The reset value of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */
40711 #define ALT_USB_HOST_HCINT8_FRMOVRUN_RESET 0x0
40712 /* Extracts the ALT_USB_HOST_HCINT8_FRMOVRUN field value from a register. */
40713 #define ALT_USB_HOST_HCINT8_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
40714 /* Produces a ALT_USB_HOST_HCINT8_FRMOVRUN register field value suitable for setting the register. */
40715 #define ALT_USB_HOST_HCINT8_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
40716 
40717 /*
40718  * Field : datatglerr
40719  *
40720  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
40721  * application should write 1 to clear
40722  *
40723  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
40724  *
40725  * in the core.
40726  *
40727  * Field Enumeration Values:
40728  *
40729  * Enum | Value | Description
40730  * :---------------------------------------|:------|:---------------------
40731  * ALT_USB_HOST_HCINT8_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
40732  * ALT_USB_HOST_HCINT8_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
40733  *
40734  * Field Access Macros:
40735  *
40736  */
40737 /*
40738  * Enumerated value for register field ALT_USB_HOST_HCINT8_DATATGLERR
40739  *
40740  * No Data Toggle Error
40741  */
40742 #define ALT_USB_HOST_HCINT8_DATATGLERR_E_INACT 0x0
40743 /*
40744  * Enumerated value for register field ALT_USB_HOST_HCINT8_DATATGLERR
40745  *
40746  * Data Toggle Error
40747  */
40748 #define ALT_USB_HOST_HCINT8_DATATGLERR_E_ACT 0x1
40749 
40750 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */
40751 #define ALT_USB_HOST_HCINT8_DATATGLERR_LSB 10
40752 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */
40753 #define ALT_USB_HOST_HCINT8_DATATGLERR_MSB 10
40754 /* The width in bits of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */
40755 #define ALT_USB_HOST_HCINT8_DATATGLERR_WIDTH 1
40756 /* The mask used to set the ALT_USB_HOST_HCINT8_DATATGLERR register field value. */
40757 #define ALT_USB_HOST_HCINT8_DATATGLERR_SET_MSK 0x00000400
40758 /* The mask used to clear the ALT_USB_HOST_HCINT8_DATATGLERR register field value. */
40759 #define ALT_USB_HOST_HCINT8_DATATGLERR_CLR_MSK 0xfffffbff
40760 /* The reset value of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */
40761 #define ALT_USB_HOST_HCINT8_DATATGLERR_RESET 0x0
40762 /* Extracts the ALT_USB_HOST_HCINT8_DATATGLERR field value from a register. */
40763 #define ALT_USB_HOST_HCINT8_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
40764 /* Produces a ALT_USB_HOST_HCINT8_DATATGLERR register field value suitable for setting the register. */
40765 #define ALT_USB_HOST_HCINT8_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
40766 
40767 /*
40768  * Field : bnaintr
40769  *
40770  * BNA (Buffer Not Available) Interrupt (BNAIntr)
40771  *
40772  * This bit is valid only when Scatter/Gather DMA mode is enabled.
40773  *
40774  * The core generates this interrupt when the descriptor accessed
40775  *
40776  * is not ready for the Core to process. BNA will not be generated
40777  *
40778  * for Isochronous channels.
40779  *
40780  * For non Scatter/Gather DMA mode, this bit is reserved.
40781  *
40782  * Field Enumeration Values:
40783  *
40784  * Enum | Value | Description
40785  * :------------------------------------|:------|:-----------------
40786  * ALT_USB_HOST_HCINT8_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
40787  * ALT_USB_HOST_HCINT8_BNAINTR_E_ACT | 0x1 | BNA Interrupt
40788  *
40789  * Field Access Macros:
40790  *
40791  */
40792 /*
40793  * Enumerated value for register field ALT_USB_HOST_HCINT8_BNAINTR
40794  *
40795  * No BNA Interrupt
40796  */
40797 #define ALT_USB_HOST_HCINT8_BNAINTR_E_INACT 0x0
40798 /*
40799  * Enumerated value for register field ALT_USB_HOST_HCINT8_BNAINTR
40800  *
40801  * BNA Interrupt
40802  */
40803 #define ALT_USB_HOST_HCINT8_BNAINTR_E_ACT 0x1
40804 
40805 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_BNAINTR register field. */
40806 #define ALT_USB_HOST_HCINT8_BNAINTR_LSB 11
40807 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_BNAINTR register field. */
40808 #define ALT_USB_HOST_HCINT8_BNAINTR_MSB 11
40809 /* The width in bits of the ALT_USB_HOST_HCINT8_BNAINTR register field. */
40810 #define ALT_USB_HOST_HCINT8_BNAINTR_WIDTH 1
40811 /* The mask used to set the ALT_USB_HOST_HCINT8_BNAINTR register field value. */
40812 #define ALT_USB_HOST_HCINT8_BNAINTR_SET_MSK 0x00000800
40813 /* The mask used to clear the ALT_USB_HOST_HCINT8_BNAINTR register field value. */
40814 #define ALT_USB_HOST_HCINT8_BNAINTR_CLR_MSK 0xfffff7ff
40815 /* The reset value of the ALT_USB_HOST_HCINT8_BNAINTR register field. */
40816 #define ALT_USB_HOST_HCINT8_BNAINTR_RESET 0x0
40817 /* Extracts the ALT_USB_HOST_HCINT8_BNAINTR field value from a register. */
40818 #define ALT_USB_HOST_HCINT8_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
40819 /* Produces a ALT_USB_HOST_HCINT8_BNAINTR register field value suitable for setting the register. */
40820 #define ALT_USB_HOST_HCINT8_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
40821 
40822 /*
40823  * Field : xcs_xact_err
40824  *
40825  * Excessive Transaction Error (XCS_XACT_ERR)
40826  *
40827  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
40828  * this bit
40829  *
40830  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
40831  *
40832  * not be generated for Isochronous channels.
40833  *
40834  * For non Scatter/Gather DMA mode, this bit is reserved.
40835  *
40836  * Field Enumeration Values:
40837  *
40838  * Enum | Value | Description
40839  * :-------------------------------------------|:------|:-------------------------------
40840  * ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
40841  * ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
40842  *
40843  * Field Access Macros:
40844  *
40845  */
40846 /*
40847  * Enumerated value for register field ALT_USB_HOST_HCINT8_XCS_XACT_ERR
40848  *
40849  * No Excessive Transaction Error
40850  */
40851 #define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_INACT 0x0
40852 /*
40853  * Enumerated value for register field ALT_USB_HOST_HCINT8_XCS_XACT_ERR
40854  *
40855  * Excessive Transaction Error
40856  */
40857 #define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_ACVTIVE 0x1
40858 
40859 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */
40860 #define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_LSB 12
40861 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */
40862 #define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_MSB 12
40863 /* The width in bits of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */
40864 #define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_WIDTH 1
40865 /* The mask used to set the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field value. */
40866 #define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_SET_MSK 0x00001000
40867 /* The mask used to clear the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field value. */
40868 #define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_CLR_MSK 0xffffefff
40869 /* The reset value of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */
40870 #define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_RESET 0x0
40871 /* Extracts the ALT_USB_HOST_HCINT8_XCS_XACT_ERR field value from a register. */
40872 #define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
40873 /* Produces a ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field value suitable for setting the register. */
40874 #define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
40875 
40876 /*
40877  * Field : desc_lst_rollintr
40878  *
40879  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
40880  *
40881  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
40882  * this bit
40883  *
40884  * when the corresponding channel's descriptor list rolls over.
40885  *
40886  * For non Scatter/Gather DMA mode, this bit is reserved.
40887  *
40888  * Field Enumeration Values:
40889  *
40890  * Enum | Value | Description
40891  * :----------------------------------------------|:------|:---------------------------------
40892  * ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
40893  * ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
40894  *
40895  * Field Access Macros:
40896  *
40897  */
40898 /*
40899  * Enumerated value for register field ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR
40900  *
40901  * No Descriptor rollover interrupt
40902  */
40903 #define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_INACT 0x0
40904 /*
40905  * Enumerated value for register field ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR
40906  *
40907  * Descriptor rollover interrupt
40908  */
40909 #define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_ACT 0x1
40910 
40911 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */
40912 #define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_LSB 13
40913 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */
40914 #define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_MSB 13
40915 /* The width in bits of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */
40916 #define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_WIDTH 1
40917 /* The mask used to set the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field value. */
40918 #define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_SET_MSK 0x00002000
40919 /* The mask used to clear the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field value. */
40920 #define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
40921 /* The reset value of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */
40922 #define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_RESET 0x0
40923 /* Extracts the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR field value from a register. */
40924 #define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
40925 /* Produces a ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field value suitable for setting the register. */
40926 #define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
40927 
40928 #ifndef __ASSEMBLY__
40929 /*
40930  * WARNING: The C register and register group struct declarations are provided for
40931  * convenience and illustrative purposes. They should, however, be used with
40932  * caution as the C language standard provides no guarantees about the alignment or
40933  * atomicity of device memory accesses. The recommended practice for writing
40934  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
40935  * alt_write_word() functions.
40936  *
40937  * The struct declaration for register ALT_USB_HOST_HCINT8.
40938  */
40939 struct ALT_USB_HOST_HCINT8_s
40940 {
40941  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT8_XFERCOMPL */
40942  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT8_CHHLTD */
40943  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT8_AHBERR */
40944  uint32_t stall : 1; /* ALT_USB_HOST_HCINT8_STALL */
40945  uint32_t nak : 1; /* ALT_USB_HOST_HCINT8_NAK */
40946  uint32_t ack : 1; /* ALT_USB_HOST_HCINT8_ACK */
40947  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT8_NYET */
40948  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT8_XACTERR */
40949  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT8_BBLERR */
40950  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT8_FRMOVRUN */
40951  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT8_DATATGLERR */
40952  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT8_BNAINTR */
40953  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT8_XCS_XACT_ERR */
40954  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR */
40955  uint32_t : 18; /* *UNDEFINED* */
40956 };
40957 
40958 /* The typedef declaration for register ALT_USB_HOST_HCINT8. */
40959 typedef volatile struct ALT_USB_HOST_HCINT8_s ALT_USB_HOST_HCINT8_t;
40960 #endif /* __ASSEMBLY__ */
40961 
40962 /* The reset value of the ALT_USB_HOST_HCINT8 register. */
40963 #define ALT_USB_HOST_HCINT8_RESET 0x00000000
40964 /* The byte offset of the ALT_USB_HOST_HCINT8 register from the beginning of the component. */
40965 #define ALT_USB_HOST_HCINT8_OFST 0x208
40966 /* The address of the ALT_USB_HOST_HCINT8 register. */
40967 #define ALT_USB_HOST_HCINT8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT8_OFST))
40968 
40969 /*
40970  * Register : hcintmsk8
40971  *
40972  * Host Channel 8 Interrupt Mask Register
40973  *
40974  * Register Layout
40975  *
40976  * Bits | Access | Reset | Description
40977  * :--------|:-------|:------|:-------------------------------------------
40978  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK
40979  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_CHHLTDMSK
40980  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_AHBERRMSK
40981  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_STALLMSK
40982  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_NAKMSK
40983  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_ACKMSK
40984  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_NYETMSK
40985  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_XACTERRMSK
40986  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_BBLERRMSK
40987  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK
40988  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK
40989  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_BNAINTRMSK
40990  * [12] | ??? | 0x0 | *UNDEFINED*
40991  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK
40992  * [31:14] | ??? | 0x0 | *UNDEFINED*
40993  *
40994  */
40995 /*
40996  * Field : xfercomplmsk
40997  *
40998  * Transfer Completed Mask (XferComplMsk)
40999  *
41000  * Field Enumeration Values:
41001  *
41002  * Enum | Value | Description
41003  * :--------------------------------------------|:------|:------------
41004  * ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_MSK | 0x0 | Mask
41005  * ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
41006  *
41007  * Field Access Macros:
41008  *
41009  */
41010 /*
41011  * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK
41012  *
41013  * Mask
41014  */
41015 #define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_MSK 0x0
41016 /*
41017  * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK
41018  *
41019  * No mask
41020  */
41021 #define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_NOMSK 0x1
41022 
41023 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */
41024 #define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_LSB 0
41025 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */
41026 #define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_MSB 0
41027 /* The width in bits of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */
41028 #define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_WIDTH 1
41029 /* The mask used to set the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field value. */
41030 #define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_SET_MSK 0x00000001
41031 /* The mask used to clear the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field value. */
41032 #define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_CLR_MSK 0xfffffffe
41033 /* The reset value of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */
41034 #define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_RESET 0x0
41035 /* Extracts the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK field value from a register. */
41036 #define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
41037 /* Produces a ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field value suitable for setting the register. */
41038 #define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
41039 
41040 /*
41041  * Field : chhltdmsk
41042  *
41043  * Channel Halted Mask (ChHltdMsk)
41044  *
41045  * Field Enumeration Values:
41046  *
41047  * Enum | Value | Description
41048  * :-----------------------------------------|:------|:------------
41049  * ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_MSK | 0x0 | Mask
41050  * ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_NOMSK | 0x1 | No mask
41051  *
41052  * Field Access Macros:
41053  *
41054  */
41055 /*
41056  * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_CHHLTDMSK
41057  *
41058  * Mask
41059  */
41060 #define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_MSK 0x0
41061 /*
41062  * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_CHHLTDMSK
41063  *
41064  * No mask
41065  */
41066 #define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_NOMSK 0x1
41067 
41068 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */
41069 #define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_LSB 1
41070 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */
41071 #define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_MSB 1
41072 /* The width in bits of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */
41073 #define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_WIDTH 1
41074 /* The mask used to set the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field value. */
41075 #define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_SET_MSK 0x00000002
41076 /* The mask used to clear the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field value. */
41077 #define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_CLR_MSK 0xfffffffd
41078 /* The reset value of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */
41079 #define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_RESET 0x0
41080 /* Extracts the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK field value from a register. */
41081 #define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
41082 /* Produces a ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field value suitable for setting the register. */
41083 #define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
41084 
41085 /*
41086  * Field : ahberrmsk
41087  *
41088  * AHB Error Mask (AHBErrMsk)
41089  *
41090  * In scatter/gather DMA mode for host,
41091  *
41092  * interrupts will not be generated due to the corresponding bits set in
41093  *
41094  * HCINTn.
41095  *
41096  * Field Enumeration Values:
41097  *
41098  * Enum | Value | Description
41099  * :-----------------------------------------|:------|:------------
41100  * ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_MSK | 0x0 | Mask
41101  * ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_NOMSK | 0x1 | No mask
41102  *
41103  * Field Access Macros:
41104  *
41105  */
41106 /*
41107  * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_AHBERRMSK
41108  *
41109  * Mask
41110  */
41111 #define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_MSK 0x0
41112 /*
41113  * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_AHBERRMSK
41114  *
41115  * No mask
41116  */
41117 #define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_NOMSK 0x1
41118 
41119 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */
41120 #define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_LSB 2
41121 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */
41122 #define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_MSB 2
41123 /* The width in bits of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */
41124 #define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_WIDTH 1
41125 /* The mask used to set the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field value. */
41126 #define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_SET_MSK 0x00000004
41127 /* The mask used to clear the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field value. */
41128 #define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_CLR_MSK 0xfffffffb
41129 /* The reset value of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */
41130 #define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_RESET 0x0
41131 /* Extracts the ALT_USB_HOST_HCINTMSK8_AHBERRMSK field value from a register. */
41132 #define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
41133 /* Produces a ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field value suitable for setting the register. */
41134 #define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
41135 
41136 /*
41137  * Field : stallmsk
41138  *
41139  * STALL Response Received Interrupt Mask (StallMsk)
41140  *
41141  * In scatter/gather DMA mode for host,
41142  *
41143  * interrupts will not be generated due to the corresponding bits set in
41144  *
41145  * HCINTn.
41146  *
41147  * Field Access Macros:
41148  *
41149  */
41150 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_STALLMSK register field. */
41151 #define ALT_USB_HOST_HCINTMSK8_STALLMSK_LSB 3
41152 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_STALLMSK register field. */
41153 #define ALT_USB_HOST_HCINTMSK8_STALLMSK_MSB 3
41154 /* The width in bits of the ALT_USB_HOST_HCINTMSK8_STALLMSK register field. */
41155 #define ALT_USB_HOST_HCINTMSK8_STALLMSK_WIDTH 1
41156 /* The mask used to set the ALT_USB_HOST_HCINTMSK8_STALLMSK register field value. */
41157 #define ALT_USB_HOST_HCINTMSK8_STALLMSK_SET_MSK 0x00000008
41158 /* The mask used to clear the ALT_USB_HOST_HCINTMSK8_STALLMSK register field value. */
41159 #define ALT_USB_HOST_HCINTMSK8_STALLMSK_CLR_MSK 0xfffffff7
41160 /* The reset value of the ALT_USB_HOST_HCINTMSK8_STALLMSK register field. */
41161 #define ALT_USB_HOST_HCINTMSK8_STALLMSK_RESET 0x0
41162 /* Extracts the ALT_USB_HOST_HCINTMSK8_STALLMSK field value from a register. */
41163 #define ALT_USB_HOST_HCINTMSK8_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
41164 /* Produces a ALT_USB_HOST_HCINTMSK8_STALLMSK register field value suitable for setting the register. */
41165 #define ALT_USB_HOST_HCINTMSK8_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
41166 
41167 /*
41168  * Field : nakmsk
41169  *
41170  * NAK Response Received Interrupt Mask (NakMsk)
41171  *
41172  * In scatter/gather DMA mode for host,
41173  *
41174  * interrupts will not be generated due to the corresponding bits set in
41175  *
41176  * HCINTn.
41177  *
41178  * Field Access Macros:
41179  *
41180  */
41181 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_NAKMSK register field. */
41182 #define ALT_USB_HOST_HCINTMSK8_NAKMSK_LSB 4
41183 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_NAKMSK register field. */
41184 #define ALT_USB_HOST_HCINTMSK8_NAKMSK_MSB 4
41185 /* The width in bits of the ALT_USB_HOST_HCINTMSK8_NAKMSK register field. */
41186 #define ALT_USB_HOST_HCINTMSK8_NAKMSK_WIDTH 1
41187 /* The mask used to set the ALT_USB_HOST_HCINTMSK8_NAKMSK register field value. */
41188 #define ALT_USB_HOST_HCINTMSK8_NAKMSK_SET_MSK 0x00000010
41189 /* The mask used to clear the ALT_USB_HOST_HCINTMSK8_NAKMSK register field value. */
41190 #define ALT_USB_HOST_HCINTMSK8_NAKMSK_CLR_MSK 0xffffffef
41191 /* The reset value of the ALT_USB_HOST_HCINTMSK8_NAKMSK register field. */
41192 #define ALT_USB_HOST_HCINTMSK8_NAKMSK_RESET 0x0
41193 /* Extracts the ALT_USB_HOST_HCINTMSK8_NAKMSK field value from a register. */
41194 #define ALT_USB_HOST_HCINTMSK8_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
41195 /* Produces a ALT_USB_HOST_HCINTMSK8_NAKMSK register field value suitable for setting the register. */
41196 #define ALT_USB_HOST_HCINTMSK8_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
41197 
41198 /*
41199  * Field : ackmsk
41200  *
41201  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
41202  *
41203  * In scatter/gather DMA mode for host,
41204  *
41205  * interrupts will not be generated due to the corresponding bits set in
41206  *
41207  * HCINTn.
41208  *
41209  * Field Access Macros:
41210  *
41211  */
41212 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_ACKMSK register field. */
41213 #define ALT_USB_HOST_HCINTMSK8_ACKMSK_LSB 5
41214 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_ACKMSK register field. */
41215 #define ALT_USB_HOST_HCINTMSK8_ACKMSK_MSB 5
41216 /* The width in bits of the ALT_USB_HOST_HCINTMSK8_ACKMSK register field. */
41217 #define ALT_USB_HOST_HCINTMSK8_ACKMSK_WIDTH 1
41218 /* The mask used to set the ALT_USB_HOST_HCINTMSK8_ACKMSK register field value. */
41219 #define ALT_USB_HOST_HCINTMSK8_ACKMSK_SET_MSK 0x00000020
41220 /* The mask used to clear the ALT_USB_HOST_HCINTMSK8_ACKMSK register field value. */
41221 #define ALT_USB_HOST_HCINTMSK8_ACKMSK_CLR_MSK 0xffffffdf
41222 /* The reset value of the ALT_USB_HOST_HCINTMSK8_ACKMSK register field. */
41223 #define ALT_USB_HOST_HCINTMSK8_ACKMSK_RESET 0x0
41224 /* Extracts the ALT_USB_HOST_HCINTMSK8_ACKMSK field value from a register. */
41225 #define ALT_USB_HOST_HCINTMSK8_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
41226 /* Produces a ALT_USB_HOST_HCINTMSK8_ACKMSK register field value suitable for setting the register. */
41227 #define ALT_USB_HOST_HCINTMSK8_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
41228 
41229 /*
41230  * Field : nyetmsk
41231  *
41232  * NYET Response Received Interrupt Mask (NyetMsk)
41233  *
41234  * In scatter/gather DMA mode for host,
41235  *
41236  * interrupts will not be generated due to the corresponding bits set in
41237  *
41238  * HCINTn.
41239  *
41240  * Field Access Macros:
41241  *
41242  */
41243 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_NYETMSK register field. */
41244 #define ALT_USB_HOST_HCINTMSK8_NYETMSK_LSB 6
41245 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_NYETMSK register field. */
41246 #define ALT_USB_HOST_HCINTMSK8_NYETMSK_MSB 6
41247 /* The width in bits of the ALT_USB_HOST_HCINTMSK8_NYETMSK register field. */
41248 #define ALT_USB_HOST_HCINTMSK8_NYETMSK_WIDTH 1
41249 /* The mask used to set the ALT_USB_HOST_HCINTMSK8_NYETMSK register field value. */
41250 #define ALT_USB_HOST_HCINTMSK8_NYETMSK_SET_MSK 0x00000040
41251 /* The mask used to clear the ALT_USB_HOST_HCINTMSK8_NYETMSK register field value. */
41252 #define ALT_USB_HOST_HCINTMSK8_NYETMSK_CLR_MSK 0xffffffbf
41253 /* The reset value of the ALT_USB_HOST_HCINTMSK8_NYETMSK register field. */
41254 #define ALT_USB_HOST_HCINTMSK8_NYETMSK_RESET 0x0
41255 /* Extracts the ALT_USB_HOST_HCINTMSK8_NYETMSK field value from a register. */
41256 #define ALT_USB_HOST_HCINTMSK8_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
41257 /* Produces a ALT_USB_HOST_HCINTMSK8_NYETMSK register field value suitable for setting the register. */
41258 #define ALT_USB_HOST_HCINTMSK8_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
41259 
41260 /*
41261  * Field : xacterrmsk
41262  *
41263  * Transaction Error Mask (XactErrMsk)
41264  *
41265  * In scatter/gather DMA mode for host,
41266  *
41267  * interrupts will not be generated due to the corresponding bits set in
41268  *
41269  * HCINTn.
41270  *
41271  * Field Access Macros:
41272  *
41273  */
41274 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field. */
41275 #define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_LSB 7
41276 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field. */
41277 #define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_MSB 7
41278 /* The width in bits of the ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field. */
41279 #define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_WIDTH 1
41280 /* The mask used to set the ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field value. */
41281 #define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_SET_MSK 0x00000080
41282 /* The mask used to clear the ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field value. */
41283 #define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_CLR_MSK 0xffffff7f
41284 /* The reset value of the ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field. */
41285 #define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_RESET 0x0
41286 /* Extracts the ALT_USB_HOST_HCINTMSK8_XACTERRMSK field value from a register. */
41287 #define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
41288 /* Produces a ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field value suitable for setting the register. */
41289 #define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
41290 
41291 /*
41292  * Field : bblerrmsk
41293  *
41294  * Babble Error Mask (BblErrMsk)
41295  *
41296  * In scatter/gather DMA mode for host,
41297  *
41298  * interrupts will not be generated due to the corresponding bits set in
41299  *
41300  * HCINTn.
41301  *
41302  * Field Access Macros:
41303  *
41304  */
41305 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field. */
41306 #define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_LSB 8
41307 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field. */
41308 #define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_MSB 8
41309 /* The width in bits of the ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field. */
41310 #define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_WIDTH 1
41311 /* The mask used to set the ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field value. */
41312 #define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_SET_MSK 0x00000100
41313 /* The mask used to clear the ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field value. */
41314 #define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_CLR_MSK 0xfffffeff
41315 /* The reset value of the ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field. */
41316 #define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_RESET 0x0
41317 /* Extracts the ALT_USB_HOST_HCINTMSK8_BBLERRMSK field value from a register. */
41318 #define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
41319 /* Produces a ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field value suitable for setting the register. */
41320 #define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
41321 
41322 /*
41323  * Field : frmovrunmsk
41324  *
41325  * Frame Overrun Mask (FrmOvrunMsk)
41326  *
41327  * In scatter/gather DMA mode for host,
41328  *
41329  * interrupts will not be generated due to the corresponding bits set in
41330  *
41331  * HCINTn.
41332  *
41333  * Field Access Macros:
41334  *
41335  */
41336 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field. */
41337 #define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_LSB 9
41338 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field. */
41339 #define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_MSB 9
41340 /* The width in bits of the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field. */
41341 #define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_WIDTH 1
41342 /* The mask used to set the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field value. */
41343 #define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_SET_MSK 0x00000200
41344 /* The mask used to clear the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field value. */
41345 #define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_CLR_MSK 0xfffffdff
41346 /* The reset value of the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field. */
41347 #define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_RESET 0x0
41348 /* Extracts the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK field value from a register. */
41349 #define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
41350 /* Produces a ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field value suitable for setting the register. */
41351 #define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
41352 
41353 /*
41354  * Field : datatglerrmsk
41355  *
41356  * Data Toggle Error Mask (DataTglErrMsk)
41357  *
41358  * In scatter/gather DMA mode for host,
41359  *
41360  * interrupts will not be generated due to the corresponding bits set in
41361  *
41362  * HCINTn.
41363  *
41364  * Field Access Macros:
41365  *
41366  */
41367 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field. */
41368 #define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_LSB 10
41369 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field. */
41370 #define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_MSB 10
41371 /* The width in bits of the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field. */
41372 #define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_WIDTH 1
41373 /* The mask used to set the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field value. */
41374 #define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_SET_MSK 0x00000400
41375 /* The mask used to clear the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field value. */
41376 #define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_CLR_MSK 0xfffffbff
41377 /* The reset value of the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field. */
41378 #define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_RESET 0x0
41379 /* Extracts the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK field value from a register. */
41380 #define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
41381 /* Produces a ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field value suitable for setting the register. */
41382 #define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
41383 
41384 /*
41385  * Field : bnaintrmsk
41386  *
41387  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
41388  *
41389  * This bit is valid only when Scatter/Gather DMA mode is enabled.
41390  *
41391  * Field Enumeration Values:
41392  *
41393  * Enum | Value | Description
41394  * :------------------------------------------|:------|:------------
41395  * ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_MSK | 0x0 | Mask
41396  * ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_NOMSK | 0x1 | No mask
41397  *
41398  * Field Access Macros:
41399  *
41400  */
41401 /*
41402  * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_BNAINTRMSK
41403  *
41404  * Mask
41405  */
41406 #define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_MSK 0x0
41407 /*
41408  * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_BNAINTRMSK
41409  *
41410  * No mask
41411  */
41412 #define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_NOMSK 0x1
41413 
41414 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */
41415 #define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_LSB 11
41416 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */
41417 #define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_MSB 11
41418 /* The width in bits of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */
41419 #define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_WIDTH 1
41420 /* The mask used to set the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field value. */
41421 #define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_SET_MSK 0x00000800
41422 /* The mask used to clear the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field value. */
41423 #define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_CLR_MSK 0xfffff7ff
41424 /* The reset value of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */
41425 #define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_RESET 0x0
41426 /* Extracts the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK field value from a register. */
41427 #define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
41428 /* Produces a ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field value suitable for setting the register. */
41429 #define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
41430 
41431 /*
41432  * Field : frm_lst_rollintrmsk
41433  *
41434  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
41435  *
41436  * This bit is valid only when Scatter/Gather DMA mode is enabled.
41437  *
41438  * Field Enumeration Values:
41439  *
41440  * Enum | Value | Description
41441  * :---------------------------------------------------|:------|:------------
41442  * ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
41443  * ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
41444  *
41445  * Field Access Macros:
41446  *
41447  */
41448 /*
41449  * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK
41450  *
41451  * Mask
41452  */
41453 #define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_MSK 0x0
41454 /*
41455  * Enumerated value for register field ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK
41456  *
41457  * No mask
41458  */
41459 #define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
41460 
41461 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */
41462 #define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_LSB 13
41463 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */
41464 #define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_MSB 13
41465 /* The width in bits of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */
41466 #define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_WIDTH 1
41467 /* The mask used to set the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field value. */
41468 #define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
41469 /* The mask used to clear the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field value. */
41470 #define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
41471 /* The reset value of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */
41472 #define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_RESET 0x0
41473 /* Extracts the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK field value from a register. */
41474 #define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
41475 /* Produces a ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
41476 #define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
41477 
41478 #ifndef __ASSEMBLY__
41479 /*
41480  * WARNING: The C register and register group struct declarations are provided for
41481  * convenience and illustrative purposes. They should, however, be used with
41482  * caution as the C language standard provides no guarantees about the alignment or
41483  * atomicity of device memory accesses. The recommended practice for writing
41484  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
41485  * alt_write_word() functions.
41486  *
41487  * The struct declaration for register ALT_USB_HOST_HCINTMSK8.
41488  */
41489 struct ALT_USB_HOST_HCINTMSK8_s
41490 {
41491  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK */
41492  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK8_CHHLTDMSK */
41493  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK8_AHBERRMSK */
41494  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK8_STALLMSK */
41495  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK8_NAKMSK */
41496  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK8_ACKMSK */
41497  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK8_NYETMSK */
41498  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK8_XACTERRMSK */
41499  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK8_BBLERRMSK */
41500  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK */
41501  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK */
41502  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK8_BNAINTRMSK */
41503  uint32_t : 1; /* *UNDEFINED* */
41504  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK */
41505  uint32_t : 18; /* *UNDEFINED* */
41506 };
41507 
41508 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK8. */
41509 typedef volatile struct ALT_USB_HOST_HCINTMSK8_s ALT_USB_HOST_HCINTMSK8_t;
41510 #endif /* __ASSEMBLY__ */
41511 
41512 /* The reset value of the ALT_USB_HOST_HCINTMSK8 register. */
41513 #define ALT_USB_HOST_HCINTMSK8_RESET 0x00000000
41514 /* The byte offset of the ALT_USB_HOST_HCINTMSK8 register from the beginning of the component. */
41515 #define ALT_USB_HOST_HCINTMSK8_OFST 0x20c
41516 /* The address of the ALT_USB_HOST_HCINTMSK8 register. */
41517 #define ALT_USB_HOST_HCINTMSK8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK8_OFST))
41518 
41519 /*
41520  * Register : hctsiz8
41521  *
41522  * Host Channel 8 Transfer Size Register
41523  *
41524  * Register Layout
41525  *
41526  * Bits | Access | Reset | Description
41527  * :--------|:-------|:------|:------------------------------
41528  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ8_XFERSIZE
41529  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ8_PKTCNT
41530  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ8_PID
41531  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ8_DOPNG
41532  *
41533  */
41534 /*
41535  * Field : xfersize
41536  *
41537  * Transfer Size (XferSize)
41538  *
41539  * For an OUT, this field is the number of data bytes the host sends
41540  *
41541  * during the transfer.
41542  *
41543  * For an IN, this field is the buffer size that the application has
41544  *
41545  * Reserved For the transfer. The application is expected to
41546  *
41547  * program this field as an integer multiple of the maximum packet
41548  *
41549  * size For IN transactions (periodic and non-periodic).
41550  *
41551  * The width of this counter is specified as Width of Transfer Size
41552  *
41553  * Counters
41554  *
41555  * Field Access Macros:
41556  *
41557  */
41558 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */
41559 #define ALT_USB_HOST_HCTSIZ8_XFERSIZE_LSB 0
41560 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */
41561 #define ALT_USB_HOST_HCTSIZ8_XFERSIZE_MSB 18
41562 /* The width in bits of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */
41563 #define ALT_USB_HOST_HCTSIZ8_XFERSIZE_WIDTH 19
41564 /* The mask used to set the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field value. */
41565 #define ALT_USB_HOST_HCTSIZ8_XFERSIZE_SET_MSK 0x0007ffff
41566 /* The mask used to clear the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field value. */
41567 #define ALT_USB_HOST_HCTSIZ8_XFERSIZE_CLR_MSK 0xfff80000
41568 /* The reset value of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */
41569 #define ALT_USB_HOST_HCTSIZ8_XFERSIZE_RESET 0x0
41570 /* Extracts the ALT_USB_HOST_HCTSIZ8_XFERSIZE field value from a register. */
41571 #define ALT_USB_HOST_HCTSIZ8_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
41572 /* Produces a ALT_USB_HOST_HCTSIZ8_XFERSIZE register field value suitable for setting the register. */
41573 #define ALT_USB_HOST_HCTSIZ8_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
41574 
41575 /*
41576  * Field : pktcnt
41577  *
41578  * Packet Count (PktCnt)
41579  *
41580  * This field is programmed by the application with the expected
41581  *
41582  * number of packets to be transmitted (OUT) or received (IN).
41583  *
41584  * The host decrements this count on every successful
41585  *
41586  * transmission or reception of an OUT/IN packet. Once this count
41587  *
41588  * reaches zero, the application is interrupted to indicate normal
41589  *
41590  * completion.
41591  *
41592  * The width of this counter is specified as Width of Packet
41593  *
41594  * Counters
41595  *
41596  * Field Access Macros:
41597  *
41598  */
41599 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */
41600 #define ALT_USB_HOST_HCTSIZ8_PKTCNT_LSB 19
41601 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */
41602 #define ALT_USB_HOST_HCTSIZ8_PKTCNT_MSB 28
41603 /* The width in bits of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */
41604 #define ALT_USB_HOST_HCTSIZ8_PKTCNT_WIDTH 10
41605 /* The mask used to set the ALT_USB_HOST_HCTSIZ8_PKTCNT register field value. */
41606 #define ALT_USB_HOST_HCTSIZ8_PKTCNT_SET_MSK 0x1ff80000
41607 /* The mask used to clear the ALT_USB_HOST_HCTSIZ8_PKTCNT register field value. */
41608 #define ALT_USB_HOST_HCTSIZ8_PKTCNT_CLR_MSK 0xe007ffff
41609 /* The reset value of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */
41610 #define ALT_USB_HOST_HCTSIZ8_PKTCNT_RESET 0x0
41611 /* Extracts the ALT_USB_HOST_HCTSIZ8_PKTCNT field value from a register. */
41612 #define ALT_USB_HOST_HCTSIZ8_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
41613 /* Produces a ALT_USB_HOST_HCTSIZ8_PKTCNT register field value suitable for setting the register. */
41614 #define ALT_USB_HOST_HCTSIZ8_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
41615 
41616 /*
41617  * Field : pid
41618  *
41619  * PID (Pid)
41620  *
41621  * The application programs this field with the type of PID to use For
41622  *
41623  * the initial transaction. The host maintains this field For the rest of
41624  *
41625  * the transfer.
41626  *
41627  * 2'b00: DATA0
41628  *
41629  * 2'b01: DATA2
41630  *
41631  * 2'b10: DATA1
41632  *
41633  * 2'b11: MDATA (non-control)/SETUP (control)
41634  *
41635  * Field Enumeration Values:
41636  *
41637  * Enum | Value | Description
41638  * :---------------------------------|:------|:------------------------------------
41639  * ALT_USB_HOST_HCTSIZ8_PID_E_DATA0 | 0x0 | DATA0
41640  * ALT_USB_HOST_HCTSIZ8_PID_E_DATA2 | 0x1 | DATA2
41641  * ALT_USB_HOST_HCTSIZ8_PID_E_DATA1 | 0x2 | DATA1
41642  * ALT_USB_HOST_HCTSIZ8_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
41643  *
41644  * Field Access Macros:
41645  *
41646  */
41647 /*
41648  * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID
41649  *
41650  * DATA0
41651  */
41652 #define ALT_USB_HOST_HCTSIZ8_PID_E_DATA0 0x0
41653 /*
41654  * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID
41655  *
41656  * DATA2
41657  */
41658 #define ALT_USB_HOST_HCTSIZ8_PID_E_DATA2 0x1
41659 /*
41660  * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID
41661  *
41662  * DATA1
41663  */
41664 #define ALT_USB_HOST_HCTSIZ8_PID_E_DATA1 0x2
41665 /*
41666  * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID
41667  *
41668  * MDATA (non-control)/SETUP (control)
41669  */
41670 #define ALT_USB_HOST_HCTSIZ8_PID_E_MDATA 0x3
41671 
41672 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_PID register field. */
41673 #define ALT_USB_HOST_HCTSIZ8_PID_LSB 29
41674 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_PID register field. */
41675 #define ALT_USB_HOST_HCTSIZ8_PID_MSB 30
41676 /* The width in bits of the ALT_USB_HOST_HCTSIZ8_PID register field. */
41677 #define ALT_USB_HOST_HCTSIZ8_PID_WIDTH 2
41678 /* The mask used to set the ALT_USB_HOST_HCTSIZ8_PID register field value. */
41679 #define ALT_USB_HOST_HCTSIZ8_PID_SET_MSK 0x60000000
41680 /* The mask used to clear the ALT_USB_HOST_HCTSIZ8_PID register field value. */
41681 #define ALT_USB_HOST_HCTSIZ8_PID_CLR_MSK 0x9fffffff
41682 /* The reset value of the ALT_USB_HOST_HCTSIZ8_PID register field. */
41683 #define ALT_USB_HOST_HCTSIZ8_PID_RESET 0x0
41684 /* Extracts the ALT_USB_HOST_HCTSIZ8_PID field value from a register. */
41685 #define ALT_USB_HOST_HCTSIZ8_PID_GET(value) (((value) & 0x60000000) >> 29)
41686 /* Produces a ALT_USB_HOST_HCTSIZ8_PID register field value suitable for setting the register. */
41687 #define ALT_USB_HOST_HCTSIZ8_PID_SET(value) (((value) << 29) & 0x60000000)
41688 
41689 /*
41690  * Field : dopng
41691  *
41692  * Do Ping (DoPng)
41693  *
41694  * This bit is used only For OUT transfers.
41695  *
41696  * Setting this field to 1 directs the host to do PING protocol.
41697  *
41698  * Note: Do not Set this bit For IN transfers. If this bit is Set For
41699  *
41700  * for IN transfers it disables the channel.
41701  *
41702  * Field Enumeration Values:
41703  *
41704  * Enum | Value | Description
41705  * :------------------------------------|:------|:-----------------
41706  * ALT_USB_HOST_HCTSIZ8_DOPNG_E_NOPING | 0x0 | No ping protocol
41707  * ALT_USB_HOST_HCTSIZ8_DOPNG_E_PING | 0x1 | Ping protocol
41708  *
41709  * Field Access Macros:
41710  *
41711  */
41712 /*
41713  * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_DOPNG
41714  *
41715  * No ping protocol
41716  */
41717 #define ALT_USB_HOST_HCTSIZ8_DOPNG_E_NOPING 0x0
41718 /*
41719  * Enumerated value for register field ALT_USB_HOST_HCTSIZ8_DOPNG
41720  *
41721  * Ping protocol
41722  */
41723 #define ALT_USB_HOST_HCTSIZ8_DOPNG_E_PING 0x1
41724 
41725 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */
41726 #define ALT_USB_HOST_HCTSIZ8_DOPNG_LSB 31
41727 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */
41728 #define ALT_USB_HOST_HCTSIZ8_DOPNG_MSB 31
41729 /* The width in bits of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */
41730 #define ALT_USB_HOST_HCTSIZ8_DOPNG_WIDTH 1
41731 /* The mask used to set the ALT_USB_HOST_HCTSIZ8_DOPNG register field value. */
41732 #define ALT_USB_HOST_HCTSIZ8_DOPNG_SET_MSK 0x80000000
41733 /* The mask used to clear the ALT_USB_HOST_HCTSIZ8_DOPNG register field value. */
41734 #define ALT_USB_HOST_HCTSIZ8_DOPNG_CLR_MSK 0x7fffffff
41735 /* The reset value of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */
41736 #define ALT_USB_HOST_HCTSIZ8_DOPNG_RESET 0x0
41737 /* Extracts the ALT_USB_HOST_HCTSIZ8_DOPNG field value from a register. */
41738 #define ALT_USB_HOST_HCTSIZ8_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
41739 /* Produces a ALT_USB_HOST_HCTSIZ8_DOPNG register field value suitable for setting the register. */
41740 #define ALT_USB_HOST_HCTSIZ8_DOPNG_SET(value) (((value) << 31) & 0x80000000)
41741 
41742 #ifndef __ASSEMBLY__
41743 /*
41744  * WARNING: The C register and register group struct declarations are provided for
41745  * convenience and illustrative purposes. They should, however, be used with
41746  * caution as the C language standard provides no guarantees about the alignment or
41747  * atomicity of device memory accesses. The recommended practice for writing
41748  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
41749  * alt_write_word() functions.
41750  *
41751  * The struct declaration for register ALT_USB_HOST_HCTSIZ8.
41752  */
41753 struct ALT_USB_HOST_HCTSIZ8_s
41754 {
41755  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ8_XFERSIZE */
41756  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ8_PKTCNT */
41757  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ8_PID */
41758  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ8_DOPNG */
41759 };
41760 
41761 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ8. */
41762 typedef volatile struct ALT_USB_HOST_HCTSIZ8_s ALT_USB_HOST_HCTSIZ8_t;
41763 #endif /* __ASSEMBLY__ */
41764 
41765 /* The reset value of the ALT_USB_HOST_HCTSIZ8 register. */
41766 #define ALT_USB_HOST_HCTSIZ8_RESET 0x00000000
41767 /* The byte offset of the ALT_USB_HOST_HCTSIZ8 register from the beginning of the component. */
41768 #define ALT_USB_HOST_HCTSIZ8_OFST 0x210
41769 /* The address of the ALT_USB_HOST_HCTSIZ8 register. */
41770 #define ALT_USB_HOST_HCTSIZ8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ8_OFST))
41771 
41772 /*
41773  * Register : hcdma8
41774  *
41775  * Host Channel 8 DMA Address Register
41776  *
41777  * Register Layout
41778  *
41779  * Bits | Access | Reset | Description
41780  * :-------|:-------|:------|:---------------------------
41781  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA8_HCDMA8
41782  *
41783  */
41784 /*
41785  * Field : hcdma8
41786  *
41787  * Buffer DMA Mode:
41788  *
41789  * [31:0] DMA Address (DMAAddr)
41790  *
41791  * This field holds the start address in the external memory from which the data
41792  * for
41793  *
41794  * the endpoint must be fetched or to which it must be stored. This register is
41795  *
41796  * incremented on every AHB transaction.
41797  *
41798  * Scatter-Gather DMA (DescDMA) Mode:
41799  *
41800  * [31:9] (Non Isoc) Non-Isochronous:
41801  *
41802  * [31:N] (Isoc) Isochronous:
41803  *
41804  * This field holds the start address of the 512 bytes
41805  *
41806  * page. The first descriptor in the list should be located
41807  *
41808  * in this address. The first descriptor may be or may
41809  *
41810  * not be ready. The core starts processing the list from
41811  *
41812  * the CTD value.
41813  *
41814  * This field holds the address of the 2*(nTD+1) bytes of
41815  *
41816  * locations in which the isochronous descriptors are
41817  *
41818  * present where N is based on nTD as per Table below
41819  *
41820  * [31:N] Base Address
41821  *
41822  * [N-1:3] Offset
41823  *
41824  * [2:0] 000
41825  *
41826  * HS ISOC
41827  *
41828  * nTD N
41829  *
41830  * 7 6
41831  *
41832  * 15 7
41833  *
41834  * 31 8
41835  *
41836  * 63 9
41837  *
41838  * 127 10
41839  *
41840  * 255 11
41841  *
41842  * FS ISOC
41843  *
41844  * nTD N
41845  *
41846  * 1 4
41847  *
41848  * 3 5
41849  *
41850  * 7 6
41851  *
41852  * 15 7
41853  *
41854  * 31 8
41855  *
41856  * 63 9
41857  *
41858  * [N-1:3] (Isoc):
41859  *
41860  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
41861  *
41862  * Non Isochronous:
41863  *
41864  * This value is in terms of number of descriptors. The values can be from 0 to 63.
41865  *
41866  * 0 - 1 descriptor.
41867  *
41868  * 63 - 64 descriptors.
41869  *
41870  * This field indicates the current descriptor processed in the list. This field is
41871  * updated
41872  *
41873  * both by application and the core. For example, if the application enables the
41874  *
41875  * channel after programming CTD=5, then the core will start processing the 6th
41876  *
41877  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
41878  *
41879  * to DMAAddr.
41880  *
41881  * Isochronous:
41882  *
41883  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
41884  * set
41885  *
41886  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
41887  *
41888  * [31:9] (Non Isoc) Non-Isochronous:
41889  *
41890  * [31:N] (Isoc) Isochronous:
41891  *
41892  * This field holds the start address of the 512 bytes
41893  *
41894  * page. The first descriptor in the list should be located
41895  *
41896  * in this address. The first descriptor may be or may
41897  *
41898  * not be ready. The core starts processing the list from
41899  *
41900  * the CTD value.
41901  *
41902  * This field holds the address of the 2*(nTD+1) bytes of
41903  *
41904  * locations in which the isochronous descriptors are
41905  *
41906  * present where N is based on nTD as per Table below
41907  *
41908  * [31:N] Base Address
41909  *
41910  * [N-1:3] Offset
41911  *
41912  * [2:0] 000
41913  *
41914  * HS ISOC
41915  *
41916  * nTD N
41917  *
41918  * 7 6
41919  *
41920  * 15 7
41921  *
41922  * 31 8
41923  *
41924  * 63 9
41925  *
41926  * 127 10
41927  *
41928  * 255 11
41929  *
41930  * FS ISOC
41931  *
41932  * nTD N
41933  *
41934  * 1 4
41935  *
41936  * 3 5
41937  *
41938  * 7 6
41939  *
41940  * 15 7
41941  *
41942  * 31 8
41943  *
41944  * 63 9
41945  *
41946  * [N-1:3] (Isoc):
41947  *
41948  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
41949  *
41950  * Non Isochronous:
41951  *
41952  * This value is in terms of number of descriptors. The values can be from 0 to 63.
41953  *
41954  * 0 - 1 descriptor.
41955  *
41956  * 63 - 64 descriptors.
41957  *
41958  * This field indicates the current descriptor processed in the list. This field is
41959  * updated
41960  *
41961  * both by application and the core. For example, if the application enables the
41962  *
41963  * channel after programming CTD=5, then the core will start processing the 6th
41964  *
41965  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
41966  *
41967  * to DMAAddr.
41968  *
41969  * Isochronous:
41970  *
41971  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
41972  * set
41973  *
41974  * to zero by application.
41975  *
41976  * Field Access Macros:
41977  *
41978  */
41979 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */
41980 #define ALT_USB_HOST_HCDMA8_HCDMA8_LSB 0
41981 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */
41982 #define ALT_USB_HOST_HCDMA8_HCDMA8_MSB 31
41983 /* The width in bits of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */
41984 #define ALT_USB_HOST_HCDMA8_HCDMA8_WIDTH 32
41985 /* The mask used to set the ALT_USB_HOST_HCDMA8_HCDMA8 register field value. */
41986 #define ALT_USB_HOST_HCDMA8_HCDMA8_SET_MSK 0xffffffff
41987 /* The mask used to clear the ALT_USB_HOST_HCDMA8_HCDMA8 register field value. */
41988 #define ALT_USB_HOST_HCDMA8_HCDMA8_CLR_MSK 0x00000000
41989 /* The reset value of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */
41990 #define ALT_USB_HOST_HCDMA8_HCDMA8_RESET 0x0
41991 /* Extracts the ALT_USB_HOST_HCDMA8_HCDMA8 field value from a register. */
41992 #define ALT_USB_HOST_HCDMA8_HCDMA8_GET(value) (((value) & 0xffffffff) >> 0)
41993 /* Produces a ALT_USB_HOST_HCDMA8_HCDMA8 register field value suitable for setting the register. */
41994 #define ALT_USB_HOST_HCDMA8_HCDMA8_SET(value) (((value) << 0) & 0xffffffff)
41995 
41996 #ifndef __ASSEMBLY__
41997 /*
41998  * WARNING: The C register and register group struct declarations are provided for
41999  * convenience and illustrative purposes. They should, however, be used with
42000  * caution as the C language standard provides no guarantees about the alignment or
42001  * atomicity of device memory accesses. The recommended practice for writing
42002  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
42003  * alt_write_word() functions.
42004  *
42005  * The struct declaration for register ALT_USB_HOST_HCDMA8.
42006  */
42007 struct ALT_USB_HOST_HCDMA8_s
42008 {
42009  uint32_t hcdma8 : 32; /* ALT_USB_HOST_HCDMA8_HCDMA8 */
42010 };
42011 
42012 /* The typedef declaration for register ALT_USB_HOST_HCDMA8. */
42013 typedef volatile struct ALT_USB_HOST_HCDMA8_s ALT_USB_HOST_HCDMA8_t;
42014 #endif /* __ASSEMBLY__ */
42015 
42016 /* The reset value of the ALT_USB_HOST_HCDMA8 register. */
42017 #define ALT_USB_HOST_HCDMA8_RESET 0x00000000
42018 /* The byte offset of the ALT_USB_HOST_HCDMA8 register from the beginning of the component. */
42019 #define ALT_USB_HOST_HCDMA8_OFST 0x214
42020 /* The address of the ALT_USB_HOST_HCDMA8 register. */
42021 #define ALT_USB_HOST_HCDMA8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA8_OFST))
42022 
42023 /*
42024  * Register : hcdmab8
42025  *
42026  * Host Channel 8 DMA Buffer Address Register
42027  *
42028  * Register Layout
42029  *
42030  * Bits | Access | Reset | Description
42031  * :-------|:-------|:------|:-----------------------------
42032  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB8_HCDMAB8
42033  *
42034  */
42035 /*
42036  * Field : hcdmab8
42037  *
42038  * Holds the current buffer address.
42039  *
42040  * This register is updated as and when the data transfer for the corresponding end
42041  * point
42042  *
42043  * is in progress. This register is present only in Scatter/Gather DMA mode.
42044  * Otherwise this
42045  *
42046  * field is reserved.
42047  *
42048  * Field Access Macros:
42049  *
42050  */
42051 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */
42052 #define ALT_USB_HOST_HCDMAB8_HCDMAB8_LSB 0
42053 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */
42054 #define ALT_USB_HOST_HCDMAB8_HCDMAB8_MSB 31
42055 /* The width in bits of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */
42056 #define ALT_USB_HOST_HCDMAB8_HCDMAB8_WIDTH 32
42057 /* The mask used to set the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field value. */
42058 #define ALT_USB_HOST_HCDMAB8_HCDMAB8_SET_MSK 0xffffffff
42059 /* The mask used to clear the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field value. */
42060 #define ALT_USB_HOST_HCDMAB8_HCDMAB8_CLR_MSK 0x00000000
42061 /* The reset value of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */
42062 #define ALT_USB_HOST_HCDMAB8_HCDMAB8_RESET 0x0
42063 /* Extracts the ALT_USB_HOST_HCDMAB8_HCDMAB8 field value from a register. */
42064 #define ALT_USB_HOST_HCDMAB8_HCDMAB8_GET(value) (((value) & 0xffffffff) >> 0)
42065 /* Produces a ALT_USB_HOST_HCDMAB8_HCDMAB8 register field value suitable for setting the register. */
42066 #define ALT_USB_HOST_HCDMAB8_HCDMAB8_SET(value) (((value) << 0) & 0xffffffff)
42067 
42068 #ifndef __ASSEMBLY__
42069 /*
42070  * WARNING: The C register and register group struct declarations are provided for
42071  * convenience and illustrative purposes. They should, however, be used with
42072  * caution as the C language standard provides no guarantees about the alignment or
42073  * atomicity of device memory accesses. The recommended practice for writing
42074  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
42075  * alt_write_word() functions.
42076  *
42077  * The struct declaration for register ALT_USB_HOST_HCDMAB8.
42078  */
42079 struct ALT_USB_HOST_HCDMAB8_s
42080 {
42081  uint32_t hcdmab8 : 32; /* ALT_USB_HOST_HCDMAB8_HCDMAB8 */
42082 };
42083 
42084 /* The typedef declaration for register ALT_USB_HOST_HCDMAB8. */
42085 typedef volatile struct ALT_USB_HOST_HCDMAB8_s ALT_USB_HOST_HCDMAB8_t;
42086 #endif /* __ASSEMBLY__ */
42087 
42088 /* The reset value of the ALT_USB_HOST_HCDMAB8 register. */
42089 #define ALT_USB_HOST_HCDMAB8_RESET 0x00000000
42090 /* The byte offset of the ALT_USB_HOST_HCDMAB8 register from the beginning of the component. */
42091 #define ALT_USB_HOST_HCDMAB8_OFST 0x21c
42092 /* The address of the ALT_USB_HOST_HCDMAB8 register. */
42093 #define ALT_USB_HOST_HCDMAB8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB8_OFST))
42094 
42095 /*
42096  * Register : hcchar9
42097  *
42098  * Host Channel 9 Characteristics Register
42099  *
42100  * Register Layout
42101  *
42102  * Bits | Access | Reset | Description
42103  * :--------|:---------|:------|:-----------------------------
42104  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_MPS
42105  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_EPNUM
42106  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_EPDIR
42107  * [16] | ??? | 0x0 | *UNDEFINED*
42108  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_LSPDDEV
42109  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_EPTYPE
42110  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_EC
42111  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_DEVADDR
42112  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_ODDFRM
42113  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR9_CHDIS
42114  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR9_CHENA
42115  *
42116  */
42117 /*
42118  * Field : mps
42119  *
42120  * Maximum Packet Size (MPS)
42121  *
42122  * Indicates the maximum packet size of the associated endpoint.
42123  *
42124  * Field Access Macros:
42125  *
42126  */
42127 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_MPS register field. */
42128 #define ALT_USB_HOST_HCCHAR9_MPS_LSB 0
42129 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_MPS register field. */
42130 #define ALT_USB_HOST_HCCHAR9_MPS_MSB 10
42131 /* The width in bits of the ALT_USB_HOST_HCCHAR9_MPS register field. */
42132 #define ALT_USB_HOST_HCCHAR9_MPS_WIDTH 11
42133 /* The mask used to set the ALT_USB_HOST_HCCHAR9_MPS register field value. */
42134 #define ALT_USB_HOST_HCCHAR9_MPS_SET_MSK 0x000007ff
42135 /* The mask used to clear the ALT_USB_HOST_HCCHAR9_MPS register field value. */
42136 #define ALT_USB_HOST_HCCHAR9_MPS_CLR_MSK 0xfffff800
42137 /* The reset value of the ALT_USB_HOST_HCCHAR9_MPS register field. */
42138 #define ALT_USB_HOST_HCCHAR9_MPS_RESET 0x0
42139 /* Extracts the ALT_USB_HOST_HCCHAR9_MPS field value from a register. */
42140 #define ALT_USB_HOST_HCCHAR9_MPS_GET(value) (((value) & 0x000007ff) >> 0)
42141 /* Produces a ALT_USB_HOST_HCCHAR9_MPS register field value suitable for setting the register. */
42142 #define ALT_USB_HOST_HCCHAR9_MPS_SET(value) (((value) << 0) & 0x000007ff)
42143 
42144 /*
42145  * Field : epnum
42146  *
42147  * Endpoint Number (EPNum)
42148  *
42149  * Indicates the endpoint number on the device serving as the data
42150  *
42151  * source or sink.
42152  *
42153  * Field Enumeration Values:
42154  *
42155  * Enum | Value | Description
42156  * :-------------------------------------|:------|:--------------
42157  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT0 | 0x0 | End point 0
42158  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT1 | 0x1 | End point 1
42159  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT2 | 0x2 | End point 2
42160  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT3 | 0x3 | End point 3
42161  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT4 | 0x4 | End point 4
42162  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT5 | 0x5 | End point 5
42163  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT6 | 0x6 | End point 6
42164  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT7 | 0x7 | End point 7
42165  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT8 | 0x8 | End point 8
42166  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT9 | 0x9 | End point 9
42167  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT10 | 0xa | End point 10
42168  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT11 | 0xb | End point 11
42169  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT12 | 0xc | End point 12
42170  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT13 | 0xd | End point 13
42171  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT14 | 0xe | End point 14
42172  * ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT15 | 0xf | End point 15
42173  *
42174  * Field Access Macros:
42175  *
42176  */
42177 /*
42178  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42179  *
42180  * End point 0
42181  */
42182 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT0 0x0
42183 /*
42184  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42185  *
42186  * End point 1
42187  */
42188 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT1 0x1
42189 /*
42190  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42191  *
42192  * End point 2
42193  */
42194 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT2 0x2
42195 /*
42196  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42197  *
42198  * End point 3
42199  */
42200 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT3 0x3
42201 /*
42202  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42203  *
42204  * End point 4
42205  */
42206 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT4 0x4
42207 /*
42208  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42209  *
42210  * End point 5
42211  */
42212 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT5 0x5
42213 /*
42214  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42215  *
42216  * End point 6
42217  */
42218 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT6 0x6
42219 /*
42220  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42221  *
42222  * End point 7
42223  */
42224 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT7 0x7
42225 /*
42226  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42227  *
42228  * End point 8
42229  */
42230 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT8 0x8
42231 /*
42232  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42233  *
42234  * End point 9
42235  */
42236 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT9 0x9
42237 /*
42238  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42239  *
42240  * End point 10
42241  */
42242 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT10 0xa
42243 /*
42244  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42245  *
42246  * End point 11
42247  */
42248 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT11 0xb
42249 /*
42250  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42251  *
42252  * End point 12
42253  */
42254 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT12 0xc
42255 /*
42256  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42257  *
42258  * End point 13
42259  */
42260 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT13 0xd
42261 /*
42262  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42263  *
42264  * End point 14
42265  */
42266 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT14 0xe
42267 /*
42268  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
42269  *
42270  * End point 15
42271  */
42272 #define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT15 0xf
42273 
42274 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */
42275 #define ALT_USB_HOST_HCCHAR9_EPNUM_LSB 11
42276 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */
42277 #define ALT_USB_HOST_HCCHAR9_EPNUM_MSB 14
42278 /* The width in bits of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */
42279 #define ALT_USB_HOST_HCCHAR9_EPNUM_WIDTH 4
42280 /* The mask used to set the ALT_USB_HOST_HCCHAR9_EPNUM register field value. */
42281 #define ALT_USB_HOST_HCCHAR9_EPNUM_SET_MSK 0x00007800
42282 /* The mask used to clear the ALT_USB_HOST_HCCHAR9_EPNUM register field value. */
42283 #define ALT_USB_HOST_HCCHAR9_EPNUM_CLR_MSK 0xffff87ff
42284 /* The reset value of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */
42285 #define ALT_USB_HOST_HCCHAR9_EPNUM_RESET 0x0
42286 /* Extracts the ALT_USB_HOST_HCCHAR9_EPNUM field value from a register. */
42287 #define ALT_USB_HOST_HCCHAR9_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
42288 /* Produces a ALT_USB_HOST_HCCHAR9_EPNUM register field value suitable for setting the register. */
42289 #define ALT_USB_HOST_HCCHAR9_EPNUM_SET(value) (((value) << 11) & 0x00007800)
42290 
42291 /*
42292  * Field : epdir
42293  *
42294  * Endpoint Direction (EPDir)
42295  *
42296  * Indicates whether the transaction is IN or OUT.
42297  *
42298  * 1'b0: OUT
42299  *
42300  * 1'b1: IN
42301  *
42302  * Field Enumeration Values:
42303  *
42304  * Enum | Value | Description
42305  * :---------------------------------|:------|:--------------
42306  * ALT_USB_HOST_HCCHAR9_EPDIR_E_OUT | 0x0 | OUT Direction
42307  * ALT_USB_HOST_HCCHAR9_EPDIR_E_IN | 0x1 | IN Direction
42308  *
42309  * Field Access Macros:
42310  *
42311  */
42312 /*
42313  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPDIR
42314  *
42315  * OUT Direction
42316  */
42317 #define ALT_USB_HOST_HCCHAR9_EPDIR_E_OUT 0x0
42318 /*
42319  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPDIR
42320  *
42321  * IN Direction
42322  */
42323 #define ALT_USB_HOST_HCCHAR9_EPDIR_E_IN 0x1
42324 
42325 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */
42326 #define ALT_USB_HOST_HCCHAR9_EPDIR_LSB 15
42327 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */
42328 #define ALT_USB_HOST_HCCHAR9_EPDIR_MSB 15
42329 /* The width in bits of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */
42330 #define ALT_USB_HOST_HCCHAR9_EPDIR_WIDTH 1
42331 /* The mask used to set the ALT_USB_HOST_HCCHAR9_EPDIR register field value. */
42332 #define ALT_USB_HOST_HCCHAR9_EPDIR_SET_MSK 0x00008000
42333 /* The mask used to clear the ALT_USB_HOST_HCCHAR9_EPDIR register field value. */
42334 #define ALT_USB_HOST_HCCHAR9_EPDIR_CLR_MSK 0xffff7fff
42335 /* The reset value of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */
42336 #define ALT_USB_HOST_HCCHAR9_EPDIR_RESET 0x0
42337 /* Extracts the ALT_USB_HOST_HCCHAR9_EPDIR field value from a register. */
42338 #define ALT_USB_HOST_HCCHAR9_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
42339 /* Produces a ALT_USB_HOST_HCCHAR9_EPDIR register field value suitable for setting the register. */
42340 #define ALT_USB_HOST_HCCHAR9_EPDIR_SET(value) (((value) << 15) & 0x00008000)
42341 
42342 /*
42343  * Field : lspddev
42344  *
42345  * Low-Speed Device (LSpdDev)
42346  *
42347  * This field is Set by the application to indicate that this channel is
42348  *
42349  * communicating to a low-speed device.
42350  *
42351  * Field Enumeration Values:
42352  *
42353  * Enum | Value | Description
42354  * :------------------------------------|:------|:----------------------------------------
42355  * ALT_USB_HOST_HCCHAR9_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
42356  * ALT_USB_HOST_HCCHAR9_LSPDDEV_E_END | 0x1 | Communicating with low speed device
42357  *
42358  * Field Access Macros:
42359  *
42360  */
42361 /*
42362  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_LSPDDEV
42363  *
42364  * Not Communicating with low speed device
42365  */
42366 #define ALT_USB_HOST_HCCHAR9_LSPDDEV_E_DISD 0x0
42367 /*
42368  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_LSPDDEV
42369  *
42370  * Communicating with low speed device
42371  */
42372 #define ALT_USB_HOST_HCCHAR9_LSPDDEV_E_END 0x1
42373 
42374 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */
42375 #define ALT_USB_HOST_HCCHAR9_LSPDDEV_LSB 17
42376 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */
42377 #define ALT_USB_HOST_HCCHAR9_LSPDDEV_MSB 17
42378 /* The width in bits of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */
42379 #define ALT_USB_HOST_HCCHAR9_LSPDDEV_WIDTH 1
42380 /* The mask used to set the ALT_USB_HOST_HCCHAR9_LSPDDEV register field value. */
42381 #define ALT_USB_HOST_HCCHAR9_LSPDDEV_SET_MSK 0x00020000
42382 /* The mask used to clear the ALT_USB_HOST_HCCHAR9_LSPDDEV register field value. */
42383 #define ALT_USB_HOST_HCCHAR9_LSPDDEV_CLR_MSK 0xfffdffff
42384 /* The reset value of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */
42385 #define ALT_USB_HOST_HCCHAR9_LSPDDEV_RESET 0x0
42386 /* Extracts the ALT_USB_HOST_HCCHAR9_LSPDDEV field value from a register. */
42387 #define ALT_USB_HOST_HCCHAR9_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
42388 /* Produces a ALT_USB_HOST_HCCHAR9_LSPDDEV register field value suitable for setting the register. */
42389 #define ALT_USB_HOST_HCCHAR9_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
42390 
42391 /*
42392  * Field : eptype
42393  *
42394  * Endpoint Type (EPType)
42395  *
42396  * Indicates the transfer type selected.
42397  *
42398  * 2'b00: Control
42399  *
42400  * 2'b01: Isochronous
42401  *
42402  * 2'b10: Bulk
42403  *
42404  * 2'b11: Interrupt
42405  *
42406  * Field Enumeration Values:
42407  *
42408  * Enum | Value | Description
42409  * :-------------------------------------|:------|:------------
42410  * ALT_USB_HOST_HCCHAR9_EPTYPE_E_CTL | 0x0 | Control
42411  * ALT_USB_HOST_HCCHAR9_EPTYPE_E_ISOC | 0x1 | Isochronous
42412  * ALT_USB_HOST_HCCHAR9_EPTYPE_E_BULK | 0x2 | Bulk
42413  * ALT_USB_HOST_HCCHAR9_EPTYPE_E_INTERR | 0x3 | Interrupt
42414  *
42415  * Field Access Macros:
42416  *
42417  */
42418 /*
42419  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE
42420  *
42421  * Control
42422  */
42423 #define ALT_USB_HOST_HCCHAR9_EPTYPE_E_CTL 0x0
42424 /*
42425  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE
42426  *
42427  * Isochronous
42428  */
42429 #define ALT_USB_HOST_HCCHAR9_EPTYPE_E_ISOC 0x1
42430 /*
42431  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE
42432  *
42433  * Bulk
42434  */
42435 #define ALT_USB_HOST_HCCHAR9_EPTYPE_E_BULK 0x2
42436 /*
42437  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE
42438  *
42439  * Interrupt
42440  */
42441 #define ALT_USB_HOST_HCCHAR9_EPTYPE_E_INTERR 0x3
42442 
42443 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */
42444 #define ALT_USB_HOST_HCCHAR9_EPTYPE_LSB 18
42445 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */
42446 #define ALT_USB_HOST_HCCHAR9_EPTYPE_MSB 19
42447 /* The width in bits of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */
42448 #define ALT_USB_HOST_HCCHAR9_EPTYPE_WIDTH 2
42449 /* The mask used to set the ALT_USB_HOST_HCCHAR9_EPTYPE register field value. */
42450 #define ALT_USB_HOST_HCCHAR9_EPTYPE_SET_MSK 0x000c0000
42451 /* The mask used to clear the ALT_USB_HOST_HCCHAR9_EPTYPE register field value. */
42452 #define ALT_USB_HOST_HCCHAR9_EPTYPE_CLR_MSK 0xfff3ffff
42453 /* The reset value of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */
42454 #define ALT_USB_HOST_HCCHAR9_EPTYPE_RESET 0x0
42455 /* Extracts the ALT_USB_HOST_HCCHAR9_EPTYPE field value from a register. */
42456 #define ALT_USB_HOST_HCCHAR9_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
42457 /* Produces a ALT_USB_HOST_HCCHAR9_EPTYPE register field value suitable for setting the register. */
42458 #define ALT_USB_HOST_HCCHAR9_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
42459 
42460 /*
42461  * Field : ec
42462  *
42463  * Multi Count (MC) / Error Count (EC)
42464  *
42465  * When the Split Enable bit of the Host Channel-n Split Control
42466  *
42467  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
42468  *
42469  * the host the number of transactions that must be executed per
42470  *
42471  * microframe For this periodic endpoint. For non periodic transfers,
42472  *
42473  * this field is used only in DMA mode, and specifies the number
42474  *
42475  * packets to be fetched For this channel before the internal DMA
42476  *
42477  * engine changes arbitration.
42478  *
42479  * 2'b00: Reserved This field yields undefined results.
42480  *
42481  * 2'b01: 1 transaction
42482  *
42483  * 2'b10: 2 transactions to be issued For this endpoint per
42484  *
42485  * microframe
42486  *
42487  * 2'b11: 3 transactions to be issued For this endpoint per
42488  *
42489  * microframe
42490  *
42491  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
42492  *
42493  * number of immediate retries to be performed For a periodic split
42494  *
42495  * transactions on transaction errors. This field must be Set to at
42496  *
42497  * least 2'b01.
42498  *
42499  * Field Enumeration Values:
42500  *
42501  * Enum | Value | Description
42502  * :-------------------------------------|:------|:----------------------------------------------
42503  * ALT_USB_HOST_HCCHAR9_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
42504  * ALT_USB_HOST_HCCHAR9_EC_E_TRANSONE | 0x1 | 1 transaction
42505  * ALT_USB_HOST_HCCHAR9_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
42506  * : | | per microframe
42507  * ALT_USB_HOST_HCCHAR9_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
42508  * : | | per microframe
42509  *
42510  * Field Access Macros:
42511  *
42512  */
42513 /*
42514  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC
42515  *
42516  * Reserved This field yields undefined result
42517  */
42518 #define ALT_USB_HOST_HCCHAR9_EC_E_RSVD 0x0
42519 /*
42520  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC
42521  *
42522  * 1 transaction
42523  */
42524 #define ALT_USB_HOST_HCCHAR9_EC_E_TRANSONE 0x1
42525 /*
42526  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC
42527  *
42528  * 2 transactions to be issued for this endpoint per microframe
42529  */
42530 #define ALT_USB_HOST_HCCHAR9_EC_E_TRANSTWO 0x2
42531 /*
42532  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC
42533  *
42534  * 3 transactions to be issued for this endpoint per microframe
42535  */
42536 #define ALT_USB_HOST_HCCHAR9_EC_E_TRANSTHREE 0x3
42537 
42538 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EC register field. */
42539 #define ALT_USB_HOST_HCCHAR9_EC_LSB 20
42540 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EC register field. */
42541 #define ALT_USB_HOST_HCCHAR9_EC_MSB 21
42542 /* The width in bits of the ALT_USB_HOST_HCCHAR9_EC register field. */
42543 #define ALT_USB_HOST_HCCHAR9_EC_WIDTH 2
42544 /* The mask used to set the ALT_USB_HOST_HCCHAR9_EC register field value. */
42545 #define ALT_USB_HOST_HCCHAR9_EC_SET_MSK 0x00300000
42546 /* The mask used to clear the ALT_USB_HOST_HCCHAR9_EC register field value. */
42547 #define ALT_USB_HOST_HCCHAR9_EC_CLR_MSK 0xffcfffff
42548 /* The reset value of the ALT_USB_HOST_HCCHAR9_EC register field. */
42549 #define ALT_USB_HOST_HCCHAR9_EC_RESET 0x0
42550 /* Extracts the ALT_USB_HOST_HCCHAR9_EC field value from a register. */
42551 #define ALT_USB_HOST_HCCHAR9_EC_GET(value) (((value) & 0x00300000) >> 20)
42552 /* Produces a ALT_USB_HOST_HCCHAR9_EC register field value suitable for setting the register. */
42553 #define ALT_USB_HOST_HCCHAR9_EC_SET(value) (((value) << 20) & 0x00300000)
42554 
42555 /*
42556  * Field : devaddr
42557  *
42558  * Device Address (DevAddr)
42559  *
42560  * This field selects the specific device serving as the data source
42561  *
42562  * or sink.
42563  *
42564  * Field Access Macros:
42565  *
42566  */
42567 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */
42568 #define ALT_USB_HOST_HCCHAR9_DEVADDR_LSB 22
42569 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */
42570 #define ALT_USB_HOST_HCCHAR9_DEVADDR_MSB 28
42571 /* The width in bits of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */
42572 #define ALT_USB_HOST_HCCHAR9_DEVADDR_WIDTH 7
42573 /* The mask used to set the ALT_USB_HOST_HCCHAR9_DEVADDR register field value. */
42574 #define ALT_USB_HOST_HCCHAR9_DEVADDR_SET_MSK 0x1fc00000
42575 /* The mask used to clear the ALT_USB_HOST_HCCHAR9_DEVADDR register field value. */
42576 #define ALT_USB_HOST_HCCHAR9_DEVADDR_CLR_MSK 0xe03fffff
42577 /* The reset value of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */
42578 #define ALT_USB_HOST_HCCHAR9_DEVADDR_RESET 0x0
42579 /* Extracts the ALT_USB_HOST_HCCHAR9_DEVADDR field value from a register. */
42580 #define ALT_USB_HOST_HCCHAR9_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
42581 /* Produces a ALT_USB_HOST_HCCHAR9_DEVADDR register field value suitable for setting the register. */
42582 #define ALT_USB_HOST_HCCHAR9_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
42583 
42584 /*
42585  * Field : oddfrm
42586  *
42587  * Odd Frame (OddFrm)
42588  *
42589  * This field is set (reset) by the application to indicate that the OTG host must
42590  * perform
42591  *
42592  * a transfer in an odd (micro)frame. This field is applicable for only periodic
42593  *
42594  * (isochronous and interrupt) transactions.
42595  *
42596  * 1'b0: Even (micro)frame
42597  *
42598  * 1'b1: Odd (micro)frame
42599  *
42600  * Field Access Macros:
42601  *
42602  */
42603 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_ODDFRM register field. */
42604 #define ALT_USB_HOST_HCCHAR9_ODDFRM_LSB 29
42605 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_ODDFRM register field. */
42606 #define ALT_USB_HOST_HCCHAR9_ODDFRM_MSB 29
42607 /* The width in bits of the ALT_USB_HOST_HCCHAR9_ODDFRM register field. */
42608 #define ALT_USB_HOST_HCCHAR9_ODDFRM_WIDTH 1
42609 /* The mask used to set the ALT_USB_HOST_HCCHAR9_ODDFRM register field value. */
42610 #define ALT_USB_HOST_HCCHAR9_ODDFRM_SET_MSK 0x20000000
42611 /* The mask used to clear the ALT_USB_HOST_HCCHAR9_ODDFRM register field value. */
42612 #define ALT_USB_HOST_HCCHAR9_ODDFRM_CLR_MSK 0xdfffffff
42613 /* The reset value of the ALT_USB_HOST_HCCHAR9_ODDFRM register field. */
42614 #define ALT_USB_HOST_HCCHAR9_ODDFRM_RESET 0x0
42615 /* Extracts the ALT_USB_HOST_HCCHAR9_ODDFRM field value from a register. */
42616 #define ALT_USB_HOST_HCCHAR9_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
42617 /* Produces a ALT_USB_HOST_HCCHAR9_ODDFRM register field value suitable for setting the register. */
42618 #define ALT_USB_HOST_HCCHAR9_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
42619 
42620 /*
42621  * Field : chdis
42622  *
42623  * Channel Disable (ChDis)
42624  *
42625  * The application sets this bit to stop transmitting/receiving data
42626  *
42627  * on a channel, even before the transfer For that channel is
42628  *
42629  * complete. The application must wait For the Channel Disabled
42630  *
42631  * interrupt before treating the channel as disabled.
42632  *
42633  * Field Enumeration Values:
42634  *
42635  * Enum | Value | Description
42636  * :-----------------------------------|:------|:----------------------------
42637  * ALT_USB_HOST_HCCHAR9_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
42638  * ALT_USB_HOST_HCCHAR9_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
42639  *
42640  * Field Access Macros:
42641  *
42642  */
42643 /*
42644  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHDIS
42645  *
42646  * Transmit/Recieve normal
42647  */
42648 #define ALT_USB_HOST_HCCHAR9_CHDIS_E_INACT 0x0
42649 /*
42650  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHDIS
42651  *
42652  * Stop transmitting/receiving
42653  */
42654 #define ALT_USB_HOST_HCCHAR9_CHDIS_E_ACT 0x1
42655 
42656 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */
42657 #define ALT_USB_HOST_HCCHAR9_CHDIS_LSB 30
42658 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */
42659 #define ALT_USB_HOST_HCCHAR9_CHDIS_MSB 30
42660 /* The width in bits of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */
42661 #define ALT_USB_HOST_HCCHAR9_CHDIS_WIDTH 1
42662 /* The mask used to set the ALT_USB_HOST_HCCHAR9_CHDIS register field value. */
42663 #define ALT_USB_HOST_HCCHAR9_CHDIS_SET_MSK 0x40000000
42664 /* The mask used to clear the ALT_USB_HOST_HCCHAR9_CHDIS register field value. */
42665 #define ALT_USB_HOST_HCCHAR9_CHDIS_CLR_MSK 0xbfffffff
42666 /* The reset value of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */
42667 #define ALT_USB_HOST_HCCHAR9_CHDIS_RESET 0x0
42668 /* Extracts the ALT_USB_HOST_HCCHAR9_CHDIS field value from a register. */
42669 #define ALT_USB_HOST_HCCHAR9_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
42670 /* Produces a ALT_USB_HOST_HCCHAR9_CHDIS register field value suitable for setting the register. */
42671 #define ALT_USB_HOST_HCCHAR9_CHDIS_SET(value) (((value) << 30) & 0x40000000)
42672 
42673 /*
42674  * Field : chena
42675  *
42676  * Channel Enable (ChEna)
42677  *
42678  * When Scatter/Gather mode is enabled
42679  *
42680  * 1'b0: Indicates that the descriptor structure is not yet ready.
42681  *
42682  * 1'b1: Indicates that the descriptor structure and data buffer with
42683  *
42684  * data is setup and this channel can access the descriptor.
42685  *
42686  * When Scatter/Gather mode is disabled
42687  *
42688  * This field is set by the application and cleared by the OTG host.
42689  *
42690  * 1'b0: Channel disabled
42691  *
42692  * 1'b1: Channel enabled
42693  *
42694  * Field Enumeration Values:
42695  *
42696  * Enum | Value | Description
42697  * :-----------------------------------|:------|:-------------------------------------------------
42698  * ALT_USB_HOST_HCCHAR9_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
42699  * : | | yet ready
42700  * ALT_USB_HOST_HCCHAR9_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
42701  * : | | data buffer with data is setup and this
42702  * : | | channel can access the descriptor
42703  *
42704  * Field Access Macros:
42705  *
42706  */
42707 /*
42708  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHENA
42709  *
42710  * Indicates that the descriptor structure is not yet ready
42711  */
42712 #define ALT_USB_HOST_HCCHAR9_CHENA_E_INACT 0x0
42713 /*
42714  * Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHENA
42715  *
42716  * Indicates that the descriptor structure and data buffer with data is
42717  * setup and this channel can access the descriptor
42718  */
42719 #define ALT_USB_HOST_HCCHAR9_CHENA_E_ACT 0x1
42720 
42721 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_CHENA register field. */
42722 #define ALT_USB_HOST_HCCHAR9_CHENA_LSB 31
42723 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_CHENA register field. */
42724 #define ALT_USB_HOST_HCCHAR9_CHENA_MSB 31
42725 /* The width in bits of the ALT_USB_HOST_HCCHAR9_CHENA register field. */
42726 #define ALT_USB_HOST_HCCHAR9_CHENA_WIDTH 1
42727 /* The mask used to set the ALT_USB_HOST_HCCHAR9_CHENA register field value. */
42728 #define ALT_USB_HOST_HCCHAR9_CHENA_SET_MSK 0x80000000
42729 /* The mask used to clear the ALT_USB_HOST_HCCHAR9_CHENA register field value. */
42730 #define ALT_USB_HOST_HCCHAR9_CHENA_CLR_MSK 0x7fffffff
42731 /* The reset value of the ALT_USB_HOST_HCCHAR9_CHENA register field. */
42732 #define ALT_USB_HOST_HCCHAR9_CHENA_RESET 0x0
42733 /* Extracts the ALT_USB_HOST_HCCHAR9_CHENA field value from a register. */
42734 #define ALT_USB_HOST_HCCHAR9_CHENA_GET(value) (((value) & 0x80000000) >> 31)
42735 /* Produces a ALT_USB_HOST_HCCHAR9_CHENA register field value suitable for setting the register. */
42736 #define ALT_USB_HOST_HCCHAR9_CHENA_SET(value) (((value) << 31) & 0x80000000)
42737 
42738 #ifndef __ASSEMBLY__
42739 /*
42740  * WARNING: The C register and register group struct declarations are provided for
42741  * convenience and illustrative purposes. They should, however, be used with
42742  * caution as the C language standard provides no guarantees about the alignment or
42743  * atomicity of device memory accesses. The recommended practice for writing
42744  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
42745  * alt_write_word() functions.
42746  *
42747  * The struct declaration for register ALT_USB_HOST_HCCHAR9.
42748  */
42749 struct ALT_USB_HOST_HCCHAR9_s
42750 {
42751  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR9_MPS */
42752  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR9_EPNUM */
42753  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR9_EPDIR */
42754  uint32_t : 1; /* *UNDEFINED* */
42755  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR9_LSPDDEV */
42756  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR9_EPTYPE */
42757  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR9_EC */
42758  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR9_DEVADDR */
42759  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR9_ODDFRM */
42760  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR9_CHDIS */
42761  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR9_CHENA */
42762 };
42763 
42764 /* The typedef declaration for register ALT_USB_HOST_HCCHAR9. */
42765 typedef volatile struct ALT_USB_HOST_HCCHAR9_s ALT_USB_HOST_HCCHAR9_t;
42766 #endif /* __ASSEMBLY__ */
42767 
42768 /* The reset value of the ALT_USB_HOST_HCCHAR9 register. */
42769 #define ALT_USB_HOST_HCCHAR9_RESET 0x00000000
42770 /* The byte offset of the ALT_USB_HOST_HCCHAR9 register from the beginning of the component. */
42771 #define ALT_USB_HOST_HCCHAR9_OFST 0x220
42772 /* The address of the ALT_USB_HOST_HCCHAR9 register. */
42773 #define ALT_USB_HOST_HCCHAR9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR9_OFST))
42774 
42775 /*
42776  * Register : hcsplt9
42777  *
42778  * Host Channel 9 Split Control Register
42779  *
42780  * Register Layout
42781  *
42782  * Bits | Access | Reset | Description
42783  * :--------|:-------|:------|:------------------------------
42784  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT9_PRTADDR
42785  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT9_HUBADDR
42786  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT9_XACTPOS
42787  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT9_COMPSPLT
42788  * [30:17] | ??? | 0x0 | *UNDEFINED*
42789  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT9_SPLTENA
42790  *
42791  */
42792 /*
42793  * Field : prtaddr
42794  *
42795  * Port Address (PrtAddr)
42796  *
42797  * This field is the port number of the recipient transaction
42798  *
42799  * translator.
42800  *
42801  * Field Access Macros:
42802  *
42803  */
42804 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */
42805 #define ALT_USB_HOST_HCSPLT9_PRTADDR_LSB 0
42806 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */
42807 #define ALT_USB_HOST_HCSPLT9_PRTADDR_MSB 6
42808 /* The width in bits of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */
42809 #define ALT_USB_HOST_HCSPLT9_PRTADDR_WIDTH 7
42810 /* The mask used to set the ALT_USB_HOST_HCSPLT9_PRTADDR register field value. */
42811 #define ALT_USB_HOST_HCSPLT9_PRTADDR_SET_MSK 0x0000007f
42812 /* The mask used to clear the ALT_USB_HOST_HCSPLT9_PRTADDR register field value. */
42813 #define ALT_USB_HOST_HCSPLT9_PRTADDR_CLR_MSK 0xffffff80
42814 /* The reset value of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */
42815 #define ALT_USB_HOST_HCSPLT9_PRTADDR_RESET 0x0
42816 /* Extracts the ALT_USB_HOST_HCSPLT9_PRTADDR field value from a register. */
42817 #define ALT_USB_HOST_HCSPLT9_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
42818 /* Produces a ALT_USB_HOST_HCSPLT9_PRTADDR register field value suitable for setting the register. */
42819 #define ALT_USB_HOST_HCSPLT9_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
42820 
42821 /*
42822  * Field : hubaddr
42823  *
42824  * Hub Address (HubAddr)
42825  *
42826  * This field holds the device address of the transaction translator's
42827  *
42828  * hub.
42829  *
42830  * Field Access Macros:
42831  *
42832  */
42833 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */
42834 #define ALT_USB_HOST_HCSPLT9_HUBADDR_LSB 7
42835 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */
42836 #define ALT_USB_HOST_HCSPLT9_HUBADDR_MSB 13
42837 /* The width in bits of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */
42838 #define ALT_USB_HOST_HCSPLT9_HUBADDR_WIDTH 7
42839 /* The mask used to set the ALT_USB_HOST_HCSPLT9_HUBADDR register field value. */
42840 #define ALT_USB_HOST_HCSPLT9_HUBADDR_SET_MSK 0x00003f80
42841 /* The mask used to clear the ALT_USB_HOST_HCSPLT9_HUBADDR register field value. */
42842 #define ALT_USB_HOST_HCSPLT9_HUBADDR_CLR_MSK 0xffffc07f
42843 /* The reset value of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */
42844 #define ALT_USB_HOST_HCSPLT9_HUBADDR_RESET 0x0
42845 /* Extracts the ALT_USB_HOST_HCSPLT9_HUBADDR field value from a register. */
42846 #define ALT_USB_HOST_HCSPLT9_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
42847 /* Produces a ALT_USB_HOST_HCSPLT9_HUBADDR register field value suitable for setting the register. */
42848 #define ALT_USB_HOST_HCSPLT9_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
42849 
42850 /*
42851  * Field : xactpos
42852  *
42853  * Transaction Position (XactPos)
42854  *
42855  * This field is used to determine whether to send all, first, middle,
42856  *
42857  * or last payloads with each OUT transaction.
42858  *
42859  * 2'b11: All. This is the entire data payload is of this transaction
42860  *
42861  * (which is less than or equal to 188 bytes).
42862  *
42863  * 2'b10: Begin. This is the first data payload of this transaction
42864  *
42865  * (which is larger than 188 bytes).
42866  *
42867  * 2'b00: Mid. This is the middle payload of this transaction
42868  *
42869  * (which is larger than 188 bytes).
42870  *
42871  * 2'b01: End. This is the last payload of this transaction (which
42872  *
42873  * is larger than 188 bytes).
42874  *
42875  * Field Enumeration Values:
42876  *
42877  * Enum | Value | Description
42878  * :--------------------------------------|:------|:------------------------------------------------
42879  * ALT_USB_HOST_HCSPLT9_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
42880  * : | | transaction (which is larger than 188 bytes)
42881  * ALT_USB_HOST_HCSPLT9_XACTPOS_E_END | 0x1 | End. This is the last payload of this
42882  * : | | transaction (which is larger than 188 bytes)
42883  * ALT_USB_HOST_HCSPLT9_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
42884  * : | | transaction (which is larger than 188 bytes)
42885  * ALT_USB_HOST_HCSPLT9_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
42886  * : | | transaction (which is less than or equal to 188
42887  * : | | bytes)
42888  *
42889  * Field Access Macros:
42890  *
42891  */
42892 /*
42893  * Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS
42894  *
42895  * Mid. This is the middle payload of this transaction (which is larger than 188
42896  * bytes)
42897  */
42898 #define ALT_USB_HOST_HCSPLT9_XACTPOS_E_MIDDLE 0x0
42899 /*
42900  * Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS
42901  *
42902  * End. This is the last payload of this transaction (which is larger than 188
42903  * bytes)
42904  */
42905 #define ALT_USB_HOST_HCSPLT9_XACTPOS_E_END 0x1
42906 /*
42907  * Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS
42908  *
42909  * Begin. This is the first data payload of this transaction (which is larger than
42910  * 188 bytes)
42911  */
42912 #define ALT_USB_HOST_HCSPLT9_XACTPOS_E_BEGIN 0x2
42913 /*
42914  * Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS
42915  *
42916  * All. This is the entire data payload is of this transaction (which is less than
42917  * or equal to 188 bytes)
42918  */
42919 #define ALT_USB_HOST_HCSPLT9_XACTPOS_E_ALL 0x3
42920 
42921 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */
42922 #define ALT_USB_HOST_HCSPLT9_XACTPOS_LSB 14
42923 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */
42924 #define ALT_USB_HOST_HCSPLT9_XACTPOS_MSB 15
42925 /* The width in bits of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */
42926 #define ALT_USB_HOST_HCSPLT9_XACTPOS_WIDTH 2
42927 /* The mask used to set the ALT_USB_HOST_HCSPLT9_XACTPOS register field value. */
42928 #define ALT_USB_HOST_HCSPLT9_XACTPOS_SET_MSK 0x0000c000
42929 /* The mask used to clear the ALT_USB_HOST_HCSPLT9_XACTPOS register field value. */
42930 #define ALT_USB_HOST_HCSPLT9_XACTPOS_CLR_MSK 0xffff3fff
42931 /* The reset value of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */
42932 #define ALT_USB_HOST_HCSPLT9_XACTPOS_RESET 0x0
42933 /* Extracts the ALT_USB_HOST_HCSPLT9_XACTPOS field value from a register. */
42934 #define ALT_USB_HOST_HCSPLT9_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
42935 /* Produces a ALT_USB_HOST_HCSPLT9_XACTPOS register field value suitable for setting the register. */
42936 #define ALT_USB_HOST_HCSPLT9_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
42937 
42938 /*
42939  * Field : compsplt
42940  *
42941  * Do Complete Split (CompSplt)
42942  *
42943  * The application sets this field to request the OTG host to perform
42944  *
42945  * a complete split transaction.
42946  *
42947  * Field Enumeration Values:
42948  *
42949  * Enum | Value | Description
42950  * :----------------------------------------|:------|:---------------------
42951  * ALT_USB_HOST_HCSPLT9_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
42952  * ALT_USB_HOST_HCSPLT9_COMPSPLT_E_SPLIT | 0x1 | Split transaction
42953  *
42954  * Field Access Macros:
42955  *
42956  */
42957 /*
42958  * Enumerated value for register field ALT_USB_HOST_HCSPLT9_COMPSPLT
42959  *
42960  * No split transaction
42961  */
42962 #define ALT_USB_HOST_HCSPLT9_COMPSPLT_E_NOSPLIT 0x0
42963 /*
42964  * Enumerated value for register field ALT_USB_HOST_HCSPLT9_COMPSPLT
42965  *
42966  * Split transaction
42967  */
42968 #define ALT_USB_HOST_HCSPLT9_COMPSPLT_E_SPLIT 0x1
42969 
42970 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */
42971 #define ALT_USB_HOST_HCSPLT9_COMPSPLT_LSB 16
42972 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */
42973 #define ALT_USB_HOST_HCSPLT9_COMPSPLT_MSB 16
42974 /* The width in bits of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */
42975 #define ALT_USB_HOST_HCSPLT9_COMPSPLT_WIDTH 1
42976 /* The mask used to set the ALT_USB_HOST_HCSPLT9_COMPSPLT register field value. */
42977 #define ALT_USB_HOST_HCSPLT9_COMPSPLT_SET_MSK 0x00010000
42978 /* The mask used to clear the ALT_USB_HOST_HCSPLT9_COMPSPLT register field value. */
42979 #define ALT_USB_HOST_HCSPLT9_COMPSPLT_CLR_MSK 0xfffeffff
42980 /* The reset value of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */
42981 #define ALT_USB_HOST_HCSPLT9_COMPSPLT_RESET 0x0
42982 /* Extracts the ALT_USB_HOST_HCSPLT9_COMPSPLT field value from a register. */
42983 #define ALT_USB_HOST_HCSPLT9_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
42984 /* Produces a ALT_USB_HOST_HCSPLT9_COMPSPLT register field value suitable for setting the register. */
42985 #define ALT_USB_HOST_HCSPLT9_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
42986 
42987 /*
42988  * Field : spltena
42989  *
42990  * Split Enable (SpltEna)
42991  *
42992  * The application sets this field to indicate that this channel is
42993  *
42994  * enabled to perform split transactions.
42995  *
42996  * Field Enumeration Values:
42997  *
42998  * Enum | Value | Description
42999  * :------------------------------------|:------|:------------------
43000  * ALT_USB_HOST_HCSPLT9_SPLTENA_E_DISD | 0x0 | Split not enabled
43001  * ALT_USB_HOST_HCSPLT9_SPLTENA_E_END | 0x1 | Split enabled
43002  *
43003  * Field Access Macros:
43004  *
43005  */
43006 /*
43007  * Enumerated value for register field ALT_USB_HOST_HCSPLT9_SPLTENA
43008  *
43009  * Split not enabled
43010  */
43011 #define ALT_USB_HOST_HCSPLT9_SPLTENA_E_DISD 0x0
43012 /*
43013  * Enumerated value for register field ALT_USB_HOST_HCSPLT9_SPLTENA
43014  *
43015  * Split enabled
43016  */
43017 #define ALT_USB_HOST_HCSPLT9_SPLTENA_E_END 0x1
43018 
43019 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */
43020 #define ALT_USB_HOST_HCSPLT9_SPLTENA_LSB 31
43021 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */
43022 #define ALT_USB_HOST_HCSPLT9_SPLTENA_MSB 31
43023 /* The width in bits of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */
43024 #define ALT_USB_HOST_HCSPLT9_SPLTENA_WIDTH 1
43025 /* The mask used to set the ALT_USB_HOST_HCSPLT9_SPLTENA register field value. */
43026 #define ALT_USB_HOST_HCSPLT9_SPLTENA_SET_MSK 0x80000000
43027 /* The mask used to clear the ALT_USB_HOST_HCSPLT9_SPLTENA register field value. */
43028 #define ALT_USB_HOST_HCSPLT9_SPLTENA_CLR_MSK 0x7fffffff
43029 /* The reset value of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */
43030 #define ALT_USB_HOST_HCSPLT9_SPLTENA_RESET 0x0
43031 /* Extracts the ALT_USB_HOST_HCSPLT9_SPLTENA field value from a register. */
43032 #define ALT_USB_HOST_HCSPLT9_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
43033 /* Produces a ALT_USB_HOST_HCSPLT9_SPLTENA register field value suitable for setting the register. */
43034 #define ALT_USB_HOST_HCSPLT9_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
43035 
43036 #ifndef __ASSEMBLY__
43037 /*
43038  * WARNING: The C register and register group struct declarations are provided for
43039  * convenience and illustrative purposes. They should, however, be used with
43040  * caution as the C language standard provides no guarantees about the alignment or
43041  * atomicity of device memory accesses. The recommended practice for writing
43042  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
43043  * alt_write_word() functions.
43044  *
43045  * The struct declaration for register ALT_USB_HOST_HCSPLT9.
43046  */
43047 struct ALT_USB_HOST_HCSPLT9_s
43048 {
43049  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT9_PRTADDR */
43050  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT9_HUBADDR */
43051  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT9_XACTPOS */
43052  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT9_COMPSPLT */
43053  uint32_t : 14; /* *UNDEFINED* */
43054  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT9_SPLTENA */
43055 };
43056 
43057 /* The typedef declaration for register ALT_USB_HOST_HCSPLT9. */
43058 typedef volatile struct ALT_USB_HOST_HCSPLT9_s ALT_USB_HOST_HCSPLT9_t;
43059 #endif /* __ASSEMBLY__ */
43060 
43061 /* The reset value of the ALT_USB_HOST_HCSPLT9 register. */
43062 #define ALT_USB_HOST_HCSPLT9_RESET 0x00000000
43063 /* The byte offset of the ALT_USB_HOST_HCSPLT9 register from the beginning of the component. */
43064 #define ALT_USB_HOST_HCSPLT9_OFST 0x224
43065 /* The address of the ALT_USB_HOST_HCSPLT9 register. */
43066 #define ALT_USB_HOST_HCSPLT9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT9_OFST))
43067 
43068 /*
43069  * Register : hcint9
43070  *
43071  * Host Channel 9 Interrupt Register
43072  *
43073  * Register Layout
43074  *
43075  * Bits | Access | Reset | Description
43076  * :--------|:-------|:------|:--------------------------------------
43077  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT9_XFERCOMPL
43078  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT9_CHHLTD
43079  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT9_AHBERR
43080  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT9_STALL
43081  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT9_NAK
43082  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT9_ACK
43083  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT9_NYET
43084  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT9_XACTERR
43085  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT9_BBLERR
43086  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT9_FRMOVRUN
43087  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT9_DATATGLERR
43088  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT9_BNAINTR
43089  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT9_XCS_XACT_ERR
43090  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR
43091  * [31:14] | ??? | 0x0 | *UNDEFINED*
43092  *
43093  */
43094 /*
43095  * Field : xfercompl
43096  *
43097  * Transfer Completed (XferCompl)
43098  *
43099  * Transfer completed normally without any errors.This bit can be set only by the
43100  * core and the application should write 1 to clear it.
43101  *
43102  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
43103  *
43104  * completed with IOC bit set in its descriptor.
43105  *
43106  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
43107  * without
43108  *
43109  * any errors.
43110  *
43111  * Field Enumeration Values:
43112  *
43113  * Enum | Value | Description
43114  * :--------------------------------------|:------|:-----------------------------------------------
43115  * ALT_USB_HOST_HCINT9_XFERCOMPL_E_INACT | 0x0 | No transfer
43116  * ALT_USB_HOST_HCINT9_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
43117  *
43118  * Field Access Macros:
43119  *
43120  */
43121 /*
43122  * Enumerated value for register field ALT_USB_HOST_HCINT9_XFERCOMPL
43123  *
43124  * No transfer
43125  */
43126 #define ALT_USB_HOST_HCINT9_XFERCOMPL_E_INACT 0x0
43127 /*
43128  * Enumerated value for register field ALT_USB_HOST_HCINT9_XFERCOMPL
43129  *
43130  * Transfer completed normally without any errors
43131  */
43132 #define ALT_USB_HOST_HCINT9_XFERCOMPL_E_ACT 0x1
43133 
43134 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */
43135 #define ALT_USB_HOST_HCINT9_XFERCOMPL_LSB 0
43136 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */
43137 #define ALT_USB_HOST_HCINT9_XFERCOMPL_MSB 0
43138 /* The width in bits of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */
43139 #define ALT_USB_HOST_HCINT9_XFERCOMPL_WIDTH 1
43140 /* The mask used to set the ALT_USB_HOST_HCINT9_XFERCOMPL register field value. */
43141 #define ALT_USB_HOST_HCINT9_XFERCOMPL_SET_MSK 0x00000001
43142 /* The mask used to clear the ALT_USB_HOST_HCINT9_XFERCOMPL register field value. */
43143 #define ALT_USB_HOST_HCINT9_XFERCOMPL_CLR_MSK 0xfffffffe
43144 /* The reset value of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */
43145 #define ALT_USB_HOST_HCINT9_XFERCOMPL_RESET 0x0
43146 /* Extracts the ALT_USB_HOST_HCINT9_XFERCOMPL field value from a register. */
43147 #define ALT_USB_HOST_HCINT9_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
43148 /* Produces a ALT_USB_HOST_HCINT9_XFERCOMPL register field value suitable for setting the register. */
43149 #define ALT_USB_HOST_HCINT9_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
43150 
43151 /*
43152  * Field : chhltd
43153  *
43154  * Channel Halted (ChHltd)
43155  *
43156  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
43157  * either because of any USB transaction error or in response to disable request by
43158  * the application or because of a completed transfer.
43159  *
43160  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
43161  * the following
43162  *
43163  * . EOL being set in descriptor
43164  *
43165  * . AHB error
43166  *
43167  * . Excessive transaction errors
43168  *
43169  * . Babble
43170  *
43171  * . Stall
43172  *
43173  * Field Enumeration Values:
43174  *
43175  * Enum | Value | Description
43176  * :-----------------------------------|:------|:-------------------
43177  * ALT_USB_HOST_HCINT9_CHHLTD_E_INACT | 0x0 | Channel not halted
43178  * ALT_USB_HOST_HCINT9_CHHLTD_E_ACT | 0x1 | Channel Halted
43179  *
43180  * Field Access Macros:
43181  *
43182  */
43183 /*
43184  * Enumerated value for register field ALT_USB_HOST_HCINT9_CHHLTD
43185  *
43186  * Channel not halted
43187  */
43188 #define ALT_USB_HOST_HCINT9_CHHLTD_E_INACT 0x0
43189 /*
43190  * Enumerated value for register field ALT_USB_HOST_HCINT9_CHHLTD
43191  *
43192  * Channel Halted
43193  */
43194 #define ALT_USB_HOST_HCINT9_CHHLTD_E_ACT 0x1
43195 
43196 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_CHHLTD register field. */
43197 #define ALT_USB_HOST_HCINT9_CHHLTD_LSB 1
43198 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_CHHLTD register field. */
43199 #define ALT_USB_HOST_HCINT9_CHHLTD_MSB 1
43200 /* The width in bits of the ALT_USB_HOST_HCINT9_CHHLTD register field. */
43201 #define ALT_USB_HOST_HCINT9_CHHLTD_WIDTH 1
43202 /* The mask used to set the ALT_USB_HOST_HCINT9_CHHLTD register field value. */
43203 #define ALT_USB_HOST_HCINT9_CHHLTD_SET_MSK 0x00000002
43204 /* The mask used to clear the ALT_USB_HOST_HCINT9_CHHLTD register field value. */
43205 #define ALT_USB_HOST_HCINT9_CHHLTD_CLR_MSK 0xfffffffd
43206 /* The reset value of the ALT_USB_HOST_HCINT9_CHHLTD register field. */
43207 #define ALT_USB_HOST_HCINT9_CHHLTD_RESET 0x0
43208 /* Extracts the ALT_USB_HOST_HCINT9_CHHLTD field value from a register. */
43209 #define ALT_USB_HOST_HCINT9_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
43210 /* Produces a ALT_USB_HOST_HCINT9_CHHLTD register field value suitable for setting the register. */
43211 #define ALT_USB_HOST_HCINT9_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
43212 
43213 /*
43214  * Field : ahberr
43215  *
43216  * AHB Error (AHBErr)
43217  *
43218  * This is generated only in Internal DMA mode when there is an
43219  *
43220  * AHB error during AHB read/write. The application can read the
43221  *
43222  * corresponding channel's DMA address register to get the error
43223  *
43224  * address.
43225  *
43226  * Field Enumeration Values:
43227  *
43228  * Enum | Value | Description
43229  * :-----------------------------------|:------|:--------------------------------
43230  * ALT_USB_HOST_HCINT9_AHBERR_E_INACT | 0x0 | No AHB error
43231  * ALT_USB_HOST_HCINT9_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
43232  *
43233  * Field Access Macros:
43234  *
43235  */
43236 /*
43237  * Enumerated value for register field ALT_USB_HOST_HCINT9_AHBERR
43238  *
43239  * No AHB error
43240  */
43241 #define ALT_USB_HOST_HCINT9_AHBERR_E_INACT 0x0
43242 /*
43243  * Enumerated value for register field ALT_USB_HOST_HCINT9_AHBERR
43244  *
43245  * AHB error during AHB read/write
43246  */
43247 #define ALT_USB_HOST_HCINT9_AHBERR_E_ACT 0x1
43248 
43249 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_AHBERR register field. */
43250 #define ALT_USB_HOST_HCINT9_AHBERR_LSB 2
43251 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_AHBERR register field. */
43252 #define ALT_USB_HOST_HCINT9_AHBERR_MSB 2
43253 /* The width in bits of the ALT_USB_HOST_HCINT9_AHBERR register field. */
43254 #define ALT_USB_HOST_HCINT9_AHBERR_WIDTH 1
43255 /* The mask used to set the ALT_USB_HOST_HCINT9_AHBERR register field value. */
43256 #define ALT_USB_HOST_HCINT9_AHBERR_SET_MSK 0x00000004
43257 /* The mask used to clear the ALT_USB_HOST_HCINT9_AHBERR register field value. */
43258 #define ALT_USB_HOST_HCINT9_AHBERR_CLR_MSK 0xfffffffb
43259 /* The reset value of the ALT_USB_HOST_HCINT9_AHBERR register field. */
43260 #define ALT_USB_HOST_HCINT9_AHBERR_RESET 0x0
43261 /* Extracts the ALT_USB_HOST_HCINT9_AHBERR field value from a register. */
43262 #define ALT_USB_HOST_HCINT9_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
43263 /* Produces a ALT_USB_HOST_HCINT9_AHBERR register field value suitable for setting the register. */
43264 #define ALT_USB_HOST_HCINT9_AHBERR_SET(value) (((value) << 2) & 0x00000004)
43265 
43266 /*
43267  * Field : stall
43268  *
43269  * STALL Response Received Interrupt (STALL)
43270  *
43271  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
43272  *
43273  * in the core.This bit can be set only by the core and the application should
43274  * write 1 to clear
43275  *
43276  * it.
43277  *
43278  * Field Enumeration Values:
43279  *
43280  * Enum | Value | Description
43281  * :----------------------------------|:------|:-------------------
43282  * ALT_USB_HOST_HCINT9_STALL_E_INACT | 0x0 | No Stall Interrupt
43283  * ALT_USB_HOST_HCINT9_STALL_E_ACT | 0x1 | Stall Interrupt
43284  *
43285  * Field Access Macros:
43286  *
43287  */
43288 /*
43289  * Enumerated value for register field ALT_USB_HOST_HCINT9_STALL
43290  *
43291  * No Stall Interrupt
43292  */
43293 #define ALT_USB_HOST_HCINT9_STALL_E_INACT 0x0
43294 /*
43295  * Enumerated value for register field ALT_USB_HOST_HCINT9_STALL
43296  *
43297  * Stall Interrupt
43298  */
43299 #define ALT_USB_HOST_HCINT9_STALL_E_ACT 0x1
43300 
43301 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_STALL register field. */
43302 #define ALT_USB_HOST_HCINT9_STALL_LSB 3
43303 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_STALL register field. */
43304 #define ALT_USB_HOST_HCINT9_STALL_MSB 3
43305 /* The width in bits of the ALT_USB_HOST_HCINT9_STALL register field. */
43306 #define ALT_USB_HOST_HCINT9_STALL_WIDTH 1
43307 /* The mask used to set the ALT_USB_HOST_HCINT9_STALL register field value. */
43308 #define ALT_USB_HOST_HCINT9_STALL_SET_MSK 0x00000008
43309 /* The mask used to clear the ALT_USB_HOST_HCINT9_STALL register field value. */
43310 #define ALT_USB_HOST_HCINT9_STALL_CLR_MSK 0xfffffff7
43311 /* The reset value of the ALT_USB_HOST_HCINT9_STALL register field. */
43312 #define ALT_USB_HOST_HCINT9_STALL_RESET 0x0
43313 /* Extracts the ALT_USB_HOST_HCINT9_STALL field value from a register. */
43314 #define ALT_USB_HOST_HCINT9_STALL_GET(value) (((value) & 0x00000008) >> 3)
43315 /* Produces a ALT_USB_HOST_HCINT9_STALL register field value suitable for setting the register. */
43316 #define ALT_USB_HOST_HCINT9_STALL_SET(value) (((value) << 3) & 0x00000008)
43317 
43318 /*
43319  * Field : nak
43320  *
43321  * NAK Response Received Interrupt (NAK)
43322  *
43323  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
43324  *
43325  * in the core.This bit can be set only by the core and the application should
43326  * write 1 to clear
43327  *
43328  * it.
43329  *
43330  * Field Enumeration Values:
43331  *
43332  * Enum | Value | Description
43333  * :--------------------------------|:------|:-----------------------------------
43334  * ALT_USB_HOST_HCINT9_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
43335  * ALT_USB_HOST_HCINT9_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
43336  *
43337  * Field Access Macros:
43338  *
43339  */
43340 /*
43341  * Enumerated value for register field ALT_USB_HOST_HCINT9_NAK
43342  *
43343  * No NAK Response Received Interrupt
43344  */
43345 #define ALT_USB_HOST_HCINT9_NAK_E_INACT 0x0
43346 /*
43347  * Enumerated value for register field ALT_USB_HOST_HCINT9_NAK
43348  *
43349  * NAK Response Received Interrupt
43350  */
43351 #define ALT_USB_HOST_HCINT9_NAK_E_ACT 0x1
43352 
43353 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_NAK register field. */
43354 #define ALT_USB_HOST_HCINT9_NAK_LSB 4
43355 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_NAK register field. */
43356 #define ALT_USB_HOST_HCINT9_NAK_MSB 4
43357 /* The width in bits of the ALT_USB_HOST_HCINT9_NAK register field. */
43358 #define ALT_USB_HOST_HCINT9_NAK_WIDTH 1
43359 /* The mask used to set the ALT_USB_HOST_HCINT9_NAK register field value. */
43360 #define ALT_USB_HOST_HCINT9_NAK_SET_MSK 0x00000010
43361 /* The mask used to clear the ALT_USB_HOST_HCINT9_NAK register field value. */
43362 #define ALT_USB_HOST_HCINT9_NAK_CLR_MSK 0xffffffef
43363 /* The reset value of the ALT_USB_HOST_HCINT9_NAK register field. */
43364 #define ALT_USB_HOST_HCINT9_NAK_RESET 0x0
43365 /* Extracts the ALT_USB_HOST_HCINT9_NAK field value from a register. */
43366 #define ALT_USB_HOST_HCINT9_NAK_GET(value) (((value) & 0x00000010) >> 4)
43367 /* Produces a ALT_USB_HOST_HCINT9_NAK register field value suitable for setting the register. */
43368 #define ALT_USB_HOST_HCINT9_NAK_SET(value) (((value) << 4) & 0x00000010)
43369 
43370 /*
43371  * Field : ack
43372  *
43373  * ACK Response Received/Transmitted Interrupt (ACK)
43374  *
43375  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
43376  *
43377  * in the core.This bit can be set only by the core and the application should
43378  * write 1 to clear
43379  *
43380  * it.
43381  *
43382  * Field Enumeration Values:
43383  *
43384  * Enum | Value | Description
43385  * :--------------------------------|:------|:-----------------------------------------------
43386  * ALT_USB_HOST_HCINT9_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
43387  * ALT_USB_HOST_HCINT9_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
43388  *
43389  * Field Access Macros:
43390  *
43391  */
43392 /*
43393  * Enumerated value for register field ALT_USB_HOST_HCINT9_ACK
43394  *
43395  * No ACK Response Received Transmitted Interrupt
43396  */
43397 #define ALT_USB_HOST_HCINT9_ACK_E_INACT 0x0
43398 /*
43399  * Enumerated value for register field ALT_USB_HOST_HCINT9_ACK
43400  *
43401  * ACK Response Received Transmitted Interrup
43402  */
43403 #define ALT_USB_HOST_HCINT9_ACK_E_ACT 0x1
43404 
43405 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_ACK register field. */
43406 #define ALT_USB_HOST_HCINT9_ACK_LSB 5
43407 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_ACK register field. */
43408 #define ALT_USB_HOST_HCINT9_ACK_MSB 5
43409 /* The width in bits of the ALT_USB_HOST_HCINT9_ACK register field. */
43410 #define ALT_USB_HOST_HCINT9_ACK_WIDTH 1
43411 /* The mask used to set the ALT_USB_HOST_HCINT9_ACK register field value. */
43412 #define ALT_USB_HOST_HCINT9_ACK_SET_MSK 0x00000020
43413 /* The mask used to clear the ALT_USB_HOST_HCINT9_ACK register field value. */
43414 #define ALT_USB_HOST_HCINT9_ACK_CLR_MSK 0xffffffdf
43415 /* The reset value of the ALT_USB_HOST_HCINT9_ACK register field. */
43416 #define ALT_USB_HOST_HCINT9_ACK_RESET 0x0
43417 /* Extracts the ALT_USB_HOST_HCINT9_ACK field value from a register. */
43418 #define ALT_USB_HOST_HCINT9_ACK_GET(value) (((value) & 0x00000020) >> 5)
43419 /* Produces a ALT_USB_HOST_HCINT9_ACK register field value suitable for setting the register. */
43420 #define ALT_USB_HOST_HCINT9_ACK_SET(value) (((value) << 5) & 0x00000020)
43421 
43422 /*
43423  * Field : nyet
43424  *
43425  * NYET Response Received Interrupt (NYET)
43426  *
43427  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
43428  *
43429  * in the core.This bit can be set only by the core and the application should
43430  * write 1 to clear
43431  *
43432  * it.
43433  *
43434  * Field Enumeration Values:
43435  *
43436  * Enum | Value | Description
43437  * :---------------------------------|:------|:------------------------------------
43438  * ALT_USB_HOST_HCINT9_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
43439  * ALT_USB_HOST_HCINT9_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
43440  *
43441  * Field Access Macros:
43442  *
43443  */
43444 /*
43445  * Enumerated value for register field ALT_USB_HOST_HCINT9_NYET
43446  *
43447  * No NYET Response Received Interrupt
43448  */
43449 #define ALT_USB_HOST_HCINT9_NYET_E_INACT 0x0
43450 /*
43451  * Enumerated value for register field ALT_USB_HOST_HCINT9_NYET
43452  *
43453  * NYET Response Received Interrupt
43454  */
43455 #define ALT_USB_HOST_HCINT9_NYET_E_ACT 0x1
43456 
43457 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_NYET register field. */
43458 #define ALT_USB_HOST_HCINT9_NYET_LSB 6
43459 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_NYET register field. */
43460 #define ALT_USB_HOST_HCINT9_NYET_MSB 6
43461 /* The width in bits of the ALT_USB_HOST_HCINT9_NYET register field. */
43462 #define ALT_USB_HOST_HCINT9_NYET_WIDTH 1
43463 /* The mask used to set the ALT_USB_HOST_HCINT9_NYET register field value. */
43464 #define ALT_USB_HOST_HCINT9_NYET_SET_MSK 0x00000040
43465 /* The mask used to clear the ALT_USB_HOST_HCINT9_NYET register field value. */
43466 #define ALT_USB_HOST_HCINT9_NYET_CLR_MSK 0xffffffbf
43467 /* The reset value of the ALT_USB_HOST_HCINT9_NYET register field. */
43468 #define ALT_USB_HOST_HCINT9_NYET_RESET 0x0
43469 /* Extracts the ALT_USB_HOST_HCINT9_NYET field value from a register. */
43470 #define ALT_USB_HOST_HCINT9_NYET_GET(value) (((value) & 0x00000040) >> 6)
43471 /* Produces a ALT_USB_HOST_HCINT9_NYET register field value suitable for setting the register. */
43472 #define ALT_USB_HOST_HCINT9_NYET_SET(value) (((value) << 6) & 0x00000040)
43473 
43474 /*
43475  * Field : xacterr
43476  *
43477  * Transaction Error (XactErr)
43478  *
43479  * Indicates one of the following errors occurred on the USB.
43480  *
43481  * CRC check failure
43482  *
43483  * Timeout
43484  *
43485  * Bit stuff error
43486  *
43487  * False EOP
43488  *
43489  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
43490  *
43491  * in the core.This bit can be set only by the core and the application should
43492  * write 1 to clear
43493  *
43494  * it.
43495  *
43496  * Field Enumeration Values:
43497  *
43498  * Enum | Value | Description
43499  * :------------------------------------|:------|:---------------------
43500  * ALT_USB_HOST_HCINT9_XACTERR_E_INACT | 0x0 | No Transaction Error
43501  * ALT_USB_HOST_HCINT9_XACTERR_E_ACT | 0x1 | Transaction Error
43502  *
43503  * Field Access Macros:
43504  *
43505  */
43506 /*
43507  * Enumerated value for register field ALT_USB_HOST_HCINT9_XACTERR
43508  *
43509  * No Transaction Error
43510  */
43511 #define ALT_USB_HOST_HCINT9_XACTERR_E_INACT 0x0
43512 /*
43513  * Enumerated value for register field ALT_USB_HOST_HCINT9_XACTERR
43514  *
43515  * Transaction Error
43516  */
43517 #define ALT_USB_HOST_HCINT9_XACTERR_E_ACT 0x1
43518 
43519 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_XACTERR register field. */
43520 #define ALT_USB_HOST_HCINT9_XACTERR_LSB 7
43521 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_XACTERR register field. */
43522 #define ALT_USB_HOST_HCINT9_XACTERR_MSB 7
43523 /* The width in bits of the ALT_USB_HOST_HCINT9_XACTERR register field. */
43524 #define ALT_USB_HOST_HCINT9_XACTERR_WIDTH 1
43525 /* The mask used to set the ALT_USB_HOST_HCINT9_XACTERR register field value. */
43526 #define ALT_USB_HOST_HCINT9_XACTERR_SET_MSK 0x00000080
43527 /* The mask used to clear the ALT_USB_HOST_HCINT9_XACTERR register field value. */
43528 #define ALT_USB_HOST_HCINT9_XACTERR_CLR_MSK 0xffffff7f
43529 /* The reset value of the ALT_USB_HOST_HCINT9_XACTERR register field. */
43530 #define ALT_USB_HOST_HCINT9_XACTERR_RESET 0x0
43531 /* Extracts the ALT_USB_HOST_HCINT9_XACTERR field value from a register. */
43532 #define ALT_USB_HOST_HCINT9_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
43533 /* Produces a ALT_USB_HOST_HCINT9_XACTERR register field value suitable for setting the register. */
43534 #define ALT_USB_HOST_HCINT9_XACTERR_SET(value) (((value) << 7) & 0x00000080)
43535 
43536 /*
43537  * Field : bblerr
43538  *
43539  * Babble Error (BblErr)
43540  *
43541  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
43542  *
43543  * in the core..This bit can be set only by the core and the application should
43544  * write 1 to clear
43545  *
43546  * it.
43547  *
43548  * Field Enumeration Values:
43549  *
43550  * Enum | Value | Description
43551  * :-----------------------------------|:------|:----------------
43552  * ALT_USB_HOST_HCINT9_BBLERR_E_INACT | 0x0 | No Babble Error
43553  * ALT_USB_HOST_HCINT9_BBLERR_E_ACT | 0x1 | Babble Error
43554  *
43555  * Field Access Macros:
43556  *
43557  */
43558 /*
43559  * Enumerated value for register field ALT_USB_HOST_HCINT9_BBLERR
43560  *
43561  * No Babble Error
43562  */
43563 #define ALT_USB_HOST_HCINT9_BBLERR_E_INACT 0x0
43564 /*
43565  * Enumerated value for register field ALT_USB_HOST_HCINT9_BBLERR
43566  *
43567  * Babble Error
43568  */
43569 #define ALT_USB_HOST_HCINT9_BBLERR_E_ACT 0x1
43570 
43571 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_BBLERR register field. */
43572 #define ALT_USB_HOST_HCINT9_BBLERR_LSB 8
43573 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_BBLERR register field. */
43574 #define ALT_USB_HOST_HCINT9_BBLERR_MSB 8
43575 /* The width in bits of the ALT_USB_HOST_HCINT9_BBLERR register field. */
43576 #define ALT_USB_HOST_HCINT9_BBLERR_WIDTH 1
43577 /* The mask used to set the ALT_USB_HOST_HCINT9_BBLERR register field value. */
43578 #define ALT_USB_HOST_HCINT9_BBLERR_SET_MSK 0x00000100
43579 /* The mask used to clear the ALT_USB_HOST_HCINT9_BBLERR register field value. */
43580 #define ALT_USB_HOST_HCINT9_BBLERR_CLR_MSK 0xfffffeff
43581 /* The reset value of the ALT_USB_HOST_HCINT9_BBLERR register field. */
43582 #define ALT_USB_HOST_HCINT9_BBLERR_RESET 0x0
43583 /* Extracts the ALT_USB_HOST_HCINT9_BBLERR field value from a register. */
43584 #define ALT_USB_HOST_HCINT9_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
43585 /* Produces a ALT_USB_HOST_HCINT9_BBLERR register field value suitable for setting the register. */
43586 #define ALT_USB_HOST_HCINT9_BBLERR_SET(value) (((value) << 8) & 0x00000100)
43587 
43588 /*
43589  * Field : frmovrun
43590  *
43591  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
43592  * bit is masked
43593  *
43594  * in the core.This bit can be set only by the core and the application should
43595  * write 1 to clear
43596  *
43597  * it.
43598  *
43599  * Field Enumeration Values:
43600  *
43601  * Enum | Value | Description
43602  * :-------------------------------------|:------|:-----------------
43603  * ALT_USB_HOST_HCINT9_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
43604  * ALT_USB_HOST_HCINT9_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
43605  *
43606  * Field Access Macros:
43607  *
43608  */
43609 /*
43610  * Enumerated value for register field ALT_USB_HOST_HCINT9_FRMOVRUN
43611  *
43612  * No Frame Overrun
43613  */
43614 #define ALT_USB_HOST_HCINT9_FRMOVRUN_E_INACT 0x0
43615 /*
43616  * Enumerated value for register field ALT_USB_HOST_HCINT9_FRMOVRUN
43617  *
43618  * Frame Overrun
43619  */
43620 #define ALT_USB_HOST_HCINT9_FRMOVRUN_E_ACT 0x1
43621 
43622 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */
43623 #define ALT_USB_HOST_HCINT9_FRMOVRUN_LSB 9
43624 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */
43625 #define ALT_USB_HOST_HCINT9_FRMOVRUN_MSB 9
43626 /* The width in bits of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */
43627 #define ALT_USB_HOST_HCINT9_FRMOVRUN_WIDTH 1
43628 /* The mask used to set the ALT_USB_HOST_HCINT9_FRMOVRUN register field value. */
43629 #define ALT_USB_HOST_HCINT9_FRMOVRUN_SET_MSK 0x00000200
43630 /* The mask used to clear the ALT_USB_HOST_HCINT9_FRMOVRUN register field value. */
43631 #define ALT_USB_HOST_HCINT9_FRMOVRUN_CLR_MSK 0xfffffdff
43632 /* The reset value of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */
43633 #define ALT_USB_HOST_HCINT9_FRMOVRUN_RESET 0x0
43634 /* Extracts the ALT_USB_HOST_HCINT9_FRMOVRUN field value from a register. */
43635 #define ALT_USB_HOST_HCINT9_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
43636 /* Produces a ALT_USB_HOST_HCINT9_FRMOVRUN register field value suitable for setting the register. */
43637 #define ALT_USB_HOST_HCINT9_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
43638 
43639 /*
43640  * Field : datatglerr
43641  *
43642  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
43643  * application should write 1 to clear
43644  *
43645  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
43646  *
43647  * in the core.
43648  *
43649  * Field Enumeration Values:
43650  *
43651  * Enum | Value | Description
43652  * :---------------------------------------|:------|:---------------------
43653  * ALT_USB_HOST_HCINT9_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
43654  * ALT_USB_HOST_HCINT9_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
43655  *
43656  * Field Access Macros:
43657  *
43658  */
43659 /*
43660  * Enumerated value for register field ALT_USB_HOST_HCINT9_DATATGLERR
43661  *
43662  * No Data Toggle Error
43663  */
43664 #define ALT_USB_HOST_HCINT9_DATATGLERR_E_INACT 0x0
43665 /*
43666  * Enumerated value for register field ALT_USB_HOST_HCINT9_DATATGLERR
43667  *
43668  * Data Toggle Error
43669  */
43670 #define ALT_USB_HOST_HCINT9_DATATGLERR_E_ACT 0x1
43671 
43672 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */
43673 #define ALT_USB_HOST_HCINT9_DATATGLERR_LSB 10
43674 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */
43675 #define ALT_USB_HOST_HCINT9_DATATGLERR_MSB 10
43676 /* The width in bits of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */
43677 #define ALT_USB_HOST_HCINT9_DATATGLERR_WIDTH 1
43678 /* The mask used to set the ALT_USB_HOST_HCINT9_DATATGLERR register field value. */
43679 #define ALT_USB_HOST_HCINT9_DATATGLERR_SET_MSK 0x00000400
43680 /* The mask used to clear the ALT_USB_HOST_HCINT9_DATATGLERR register field value. */
43681 #define ALT_USB_HOST_HCINT9_DATATGLERR_CLR_MSK 0xfffffbff
43682 /* The reset value of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */
43683 #define ALT_USB_HOST_HCINT9_DATATGLERR_RESET 0x0
43684 /* Extracts the ALT_USB_HOST_HCINT9_DATATGLERR field value from a register. */
43685 #define ALT_USB_HOST_HCINT9_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
43686 /* Produces a ALT_USB_HOST_HCINT9_DATATGLERR register field value suitable for setting the register. */
43687 #define ALT_USB_HOST_HCINT9_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
43688 
43689 /*
43690  * Field : bnaintr
43691  *
43692  * BNA (Buffer Not Available) Interrupt (BNAIntr)
43693  *
43694  * This bit is valid only when Scatter/Gather DMA mode is enabled.
43695  *
43696  * The core generates this interrupt when the descriptor accessed
43697  *
43698  * is not ready for the Core to process. BNA will not be generated
43699  *
43700  * for Isochronous channels.
43701  *
43702  * For non Scatter/Gather DMA mode, this bit is reserved.
43703  *
43704  * Field Enumeration Values:
43705  *
43706  * Enum | Value | Description
43707  * :------------------------------------|:------|:-----------------
43708  * ALT_USB_HOST_HCINT9_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
43709  * ALT_USB_HOST_HCINT9_BNAINTR_E_ACT | 0x1 | BNA Interrupt
43710  *
43711  * Field Access Macros:
43712  *
43713  */
43714 /*
43715  * Enumerated value for register field ALT_USB_HOST_HCINT9_BNAINTR
43716  *
43717  * No BNA Interrupt
43718  */
43719 #define ALT_USB_HOST_HCINT9_BNAINTR_E_INACT 0x0
43720 /*
43721  * Enumerated value for register field ALT_USB_HOST_HCINT9_BNAINTR
43722  *
43723  * BNA Interrupt
43724  */
43725 #define ALT_USB_HOST_HCINT9_BNAINTR_E_ACT 0x1
43726 
43727 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_BNAINTR register field. */
43728 #define ALT_USB_HOST_HCINT9_BNAINTR_LSB 11
43729 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_BNAINTR register field. */
43730 #define ALT_USB_HOST_HCINT9_BNAINTR_MSB 11
43731 /* The width in bits of the ALT_USB_HOST_HCINT9_BNAINTR register field. */
43732 #define ALT_USB_HOST_HCINT9_BNAINTR_WIDTH 1
43733 /* The mask used to set the ALT_USB_HOST_HCINT9_BNAINTR register field value. */
43734 #define ALT_USB_HOST_HCINT9_BNAINTR_SET_MSK 0x00000800
43735 /* The mask used to clear the ALT_USB_HOST_HCINT9_BNAINTR register field value. */
43736 #define ALT_USB_HOST_HCINT9_BNAINTR_CLR_MSK 0xfffff7ff
43737 /* The reset value of the ALT_USB_HOST_HCINT9_BNAINTR register field. */
43738 #define ALT_USB_HOST_HCINT9_BNAINTR_RESET 0x0
43739 /* Extracts the ALT_USB_HOST_HCINT9_BNAINTR field value from a register. */
43740 #define ALT_USB_HOST_HCINT9_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
43741 /* Produces a ALT_USB_HOST_HCINT9_BNAINTR register field value suitable for setting the register. */
43742 #define ALT_USB_HOST_HCINT9_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
43743 
43744 /*
43745  * Field : xcs_xact_err
43746  *
43747  * Excessive Transaction Error (XCS_XACT_ERR)
43748  *
43749  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
43750  * this bit
43751  *
43752  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
43753  *
43754  * not be generated for Isochronous channels.
43755  *
43756  * For non Scatter/Gather DMA mode, this bit is reserved.
43757  *
43758  * Field Enumeration Values:
43759  *
43760  * Enum | Value | Description
43761  * :-------------------------------------------|:------|:-------------------------------
43762  * ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
43763  * ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
43764  *
43765  * Field Access Macros:
43766  *
43767  */
43768 /*
43769  * Enumerated value for register field ALT_USB_HOST_HCINT9_XCS_XACT_ERR
43770  *
43771  * No Excessive Transaction Error
43772  */
43773 #define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_INACT 0x0
43774 /*
43775  * Enumerated value for register field ALT_USB_HOST_HCINT9_XCS_XACT_ERR
43776  *
43777  * Excessive Transaction Error
43778  */
43779 #define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_ACVTIVE 0x1
43780 
43781 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */
43782 #define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_LSB 12
43783 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */
43784 #define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_MSB 12
43785 /* The width in bits of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */
43786 #define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_WIDTH 1
43787 /* The mask used to set the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field value. */
43788 #define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_SET_MSK 0x00001000
43789 /* The mask used to clear the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field value. */
43790 #define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_CLR_MSK 0xffffefff
43791 /* The reset value of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */
43792 #define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_RESET 0x0
43793 /* Extracts the ALT_USB_HOST_HCINT9_XCS_XACT_ERR field value from a register. */
43794 #define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
43795 /* Produces a ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field value suitable for setting the register. */
43796 #define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
43797 
43798 /*
43799  * Field : desc_lst_rollintr
43800  *
43801  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
43802  *
43803  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
43804  * this bit
43805  *
43806  * when the corresponding channel's descriptor list rolls over.
43807  *
43808  * For non Scatter/Gather DMA mode, this bit is reserved.
43809  *
43810  * Field Enumeration Values:
43811  *
43812  * Enum | Value | Description
43813  * :----------------------------------------------|:------|:---------------------------------
43814  * ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
43815  * ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
43816  *
43817  * Field Access Macros:
43818  *
43819  */
43820 /*
43821  * Enumerated value for register field ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR
43822  *
43823  * No Descriptor rollover interrupt
43824  */
43825 #define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_INACT 0x0
43826 /*
43827  * Enumerated value for register field ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR
43828  *
43829  * Descriptor rollover interrupt
43830  */
43831 #define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_ACT 0x1
43832 
43833 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */
43834 #define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_LSB 13
43835 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */
43836 #define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_MSB 13
43837 /* The width in bits of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */
43838 #define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_WIDTH 1
43839 /* The mask used to set the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field value. */
43840 #define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_SET_MSK 0x00002000
43841 /* The mask used to clear the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field value. */
43842 #define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
43843 /* The reset value of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */
43844 #define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_RESET 0x0
43845 /* Extracts the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR field value from a register. */
43846 #define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
43847 /* Produces a ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field value suitable for setting the register. */
43848 #define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
43849 
43850 #ifndef __ASSEMBLY__
43851 /*
43852  * WARNING: The C register and register group struct declarations are provided for
43853  * convenience and illustrative purposes. They should, however, be used with
43854  * caution as the C language standard provides no guarantees about the alignment or
43855  * atomicity of device memory accesses. The recommended practice for writing
43856  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
43857  * alt_write_word() functions.
43858  *
43859  * The struct declaration for register ALT_USB_HOST_HCINT9.
43860  */
43861 struct ALT_USB_HOST_HCINT9_s
43862 {
43863  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT9_XFERCOMPL */
43864  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT9_CHHLTD */
43865  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT9_AHBERR */
43866  uint32_t stall : 1; /* ALT_USB_HOST_HCINT9_STALL */
43867  uint32_t nak : 1; /* ALT_USB_HOST_HCINT9_NAK */
43868  uint32_t ack : 1; /* ALT_USB_HOST_HCINT9_ACK */
43869  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT9_NYET */
43870  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT9_XACTERR */
43871  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT9_BBLERR */
43872  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT9_FRMOVRUN */
43873  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT9_DATATGLERR */
43874  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT9_BNAINTR */
43875  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT9_XCS_XACT_ERR */
43876  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR */
43877  uint32_t : 18; /* *UNDEFINED* */
43878 };
43879 
43880 /* The typedef declaration for register ALT_USB_HOST_HCINT9. */
43881 typedef volatile struct ALT_USB_HOST_HCINT9_s ALT_USB_HOST_HCINT9_t;
43882 #endif /* __ASSEMBLY__ */
43883 
43884 /* The reset value of the ALT_USB_HOST_HCINT9 register. */
43885 #define ALT_USB_HOST_HCINT9_RESET 0x00000000
43886 /* The byte offset of the ALT_USB_HOST_HCINT9 register from the beginning of the component. */
43887 #define ALT_USB_HOST_HCINT9_OFST 0x228
43888 /* The address of the ALT_USB_HOST_HCINT9 register. */
43889 #define ALT_USB_HOST_HCINT9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT9_OFST))
43890 
43891 /*
43892  * Register : hcintmsk9
43893  *
43894  * Host Channel 9 Interrupt Mask Register
43895  *
43896  * Register Layout
43897  *
43898  * Bits | Access | Reset | Description
43899  * :--------|:-------|:------|:-------------------------------------------
43900  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK
43901  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_CHHLTDMSK
43902  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_AHBERRMSK
43903  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_STALLMSK
43904  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_NAKMSK
43905  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_ACKMSK
43906  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_NYETMSK
43907  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_XACTERRMSK
43908  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_BBLERRMSK
43909  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK
43910  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK
43911  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_BNAINTRMSK
43912  * [12] | ??? | 0x0 | *UNDEFINED*
43913  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK
43914  * [31:14] | ??? | 0x0 | *UNDEFINED*
43915  *
43916  */
43917 /*
43918  * Field : xfercomplmsk
43919  *
43920  * Transfer Completed Mask (XferComplMsk)
43921  *
43922  * Field Enumeration Values:
43923  *
43924  * Enum | Value | Description
43925  * :--------------------------------------------|:------|:------------
43926  * ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_MSK | 0x0 | Mask
43927  * ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
43928  *
43929  * Field Access Macros:
43930  *
43931  */
43932 /*
43933  * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK
43934  *
43935  * Mask
43936  */
43937 #define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_MSK 0x0
43938 /*
43939  * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK
43940  *
43941  * No mask
43942  */
43943 #define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_NOMSK 0x1
43944 
43945 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */
43946 #define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_LSB 0
43947 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */
43948 #define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_MSB 0
43949 /* The width in bits of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */
43950 #define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_WIDTH 1
43951 /* The mask used to set the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field value. */
43952 #define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_SET_MSK 0x00000001
43953 /* The mask used to clear the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field value. */
43954 #define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_CLR_MSK 0xfffffffe
43955 /* The reset value of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */
43956 #define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_RESET 0x0
43957 /* Extracts the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK field value from a register. */
43958 #define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
43959 /* Produces a ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field value suitable for setting the register. */
43960 #define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
43961 
43962 /*
43963  * Field : chhltdmsk
43964  *
43965  * Channel Halted Mask (ChHltdMsk)
43966  *
43967  * Field Enumeration Values:
43968  *
43969  * Enum | Value | Description
43970  * :-----------------------------------------|:------|:------------
43971  * ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_MSK | 0x0 | Mask
43972  * ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_NOMSK | 0x1 | No mask
43973  *
43974  * Field Access Macros:
43975  *
43976  */
43977 /*
43978  * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_CHHLTDMSK
43979  *
43980  * Mask
43981  */
43982 #define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_MSK 0x0
43983 /*
43984  * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_CHHLTDMSK
43985  *
43986  * No mask
43987  */
43988 #define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_NOMSK 0x1
43989 
43990 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */
43991 #define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_LSB 1
43992 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */
43993 #define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_MSB 1
43994 /* The width in bits of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */
43995 #define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_WIDTH 1
43996 /* The mask used to set the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field value. */
43997 #define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_SET_MSK 0x00000002
43998 /* The mask used to clear the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field value. */
43999 #define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_CLR_MSK 0xfffffffd
44000 /* The reset value of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */
44001 #define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_RESET 0x0
44002 /* Extracts the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK field value from a register. */
44003 #define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
44004 /* Produces a ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field value suitable for setting the register. */
44005 #define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
44006 
44007 /*
44008  * Field : ahberrmsk
44009  *
44010  * AHB Error Mask (AHBErrMsk)
44011  *
44012  * In scatter/gather DMA mode for host,
44013  *
44014  * interrupts will not be generated due to the corresponding bits set in
44015  *
44016  * HCINTn.
44017  *
44018  * Field Enumeration Values:
44019  *
44020  * Enum | Value | Description
44021  * :-----------------------------------------|:------|:------------
44022  * ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_MSK | 0x0 | Mask
44023  * ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_NOMSK | 0x1 | No mask
44024  *
44025  * Field Access Macros:
44026  *
44027  */
44028 /*
44029  * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_AHBERRMSK
44030  *
44031  * Mask
44032  */
44033 #define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_MSK 0x0
44034 /*
44035  * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_AHBERRMSK
44036  *
44037  * No mask
44038  */
44039 #define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_NOMSK 0x1
44040 
44041 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */
44042 #define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_LSB 2
44043 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */
44044 #define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_MSB 2
44045 /* The width in bits of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */
44046 #define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_WIDTH 1
44047 /* The mask used to set the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field value. */
44048 #define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_SET_MSK 0x00000004
44049 /* The mask used to clear the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field value. */
44050 #define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_CLR_MSK 0xfffffffb
44051 /* The reset value of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */
44052 #define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_RESET 0x0
44053 /* Extracts the ALT_USB_HOST_HCINTMSK9_AHBERRMSK field value from a register. */
44054 #define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
44055 /* Produces a ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field value suitable for setting the register. */
44056 #define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
44057 
44058 /*
44059  * Field : stallmsk
44060  *
44061  * STALL Response Received Interrupt Mask (StallMsk)
44062  *
44063  * In scatter/gather DMA mode for host,
44064  *
44065  * interrupts will not be generated due to the corresponding bits set in
44066  *
44067  * HCINTn.
44068  *
44069  * Field Access Macros:
44070  *
44071  */
44072 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_STALLMSK register field. */
44073 #define ALT_USB_HOST_HCINTMSK9_STALLMSK_LSB 3
44074 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_STALLMSK register field. */
44075 #define ALT_USB_HOST_HCINTMSK9_STALLMSK_MSB 3
44076 /* The width in bits of the ALT_USB_HOST_HCINTMSK9_STALLMSK register field. */
44077 #define ALT_USB_HOST_HCINTMSK9_STALLMSK_WIDTH 1
44078 /* The mask used to set the ALT_USB_HOST_HCINTMSK9_STALLMSK register field value. */
44079 #define ALT_USB_HOST_HCINTMSK9_STALLMSK_SET_MSK 0x00000008
44080 /* The mask used to clear the ALT_USB_HOST_HCINTMSK9_STALLMSK register field value. */
44081 #define ALT_USB_HOST_HCINTMSK9_STALLMSK_CLR_MSK 0xfffffff7
44082 /* The reset value of the ALT_USB_HOST_HCINTMSK9_STALLMSK register field. */
44083 #define ALT_USB_HOST_HCINTMSK9_STALLMSK_RESET 0x0
44084 /* Extracts the ALT_USB_HOST_HCINTMSK9_STALLMSK field value from a register. */
44085 #define ALT_USB_HOST_HCINTMSK9_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
44086 /* Produces a ALT_USB_HOST_HCINTMSK9_STALLMSK register field value suitable for setting the register. */
44087 #define ALT_USB_HOST_HCINTMSK9_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
44088 
44089 /*
44090  * Field : nakmsk
44091  *
44092  * NAK Response Received Interrupt Mask (NakMsk)
44093  *
44094  * In scatter/gather DMA mode for host,
44095  *
44096  * interrupts will not be generated due to the corresponding bits set in
44097  *
44098  * HCINTn.
44099  *
44100  * Field Access Macros:
44101  *
44102  */
44103 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_NAKMSK register field. */
44104 #define ALT_USB_HOST_HCINTMSK9_NAKMSK_LSB 4
44105 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_NAKMSK register field. */
44106 #define ALT_USB_HOST_HCINTMSK9_NAKMSK_MSB 4
44107 /* The width in bits of the ALT_USB_HOST_HCINTMSK9_NAKMSK register field. */
44108 #define ALT_USB_HOST_HCINTMSK9_NAKMSK_WIDTH 1
44109 /* The mask used to set the ALT_USB_HOST_HCINTMSK9_NAKMSK register field value. */
44110 #define ALT_USB_HOST_HCINTMSK9_NAKMSK_SET_MSK 0x00000010
44111 /* The mask used to clear the ALT_USB_HOST_HCINTMSK9_NAKMSK register field value. */
44112 #define ALT_USB_HOST_HCINTMSK9_NAKMSK_CLR_MSK 0xffffffef
44113 /* The reset value of the ALT_USB_HOST_HCINTMSK9_NAKMSK register field. */
44114 #define ALT_USB_HOST_HCINTMSK9_NAKMSK_RESET 0x0
44115 /* Extracts the ALT_USB_HOST_HCINTMSK9_NAKMSK field value from a register. */
44116 #define ALT_USB_HOST_HCINTMSK9_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
44117 /* Produces a ALT_USB_HOST_HCINTMSK9_NAKMSK register field value suitable for setting the register. */
44118 #define ALT_USB_HOST_HCINTMSK9_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
44119 
44120 /*
44121  * Field : ackmsk
44122  *
44123  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
44124  *
44125  * In scatter/gather DMA mode for host,
44126  *
44127  * interrupts will not be generated due to the corresponding bits set in
44128  *
44129  * HCINTn.
44130  *
44131  * Field Access Macros:
44132  *
44133  */
44134 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_ACKMSK register field. */
44135 #define ALT_USB_HOST_HCINTMSK9_ACKMSK_LSB 5
44136 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_ACKMSK register field. */
44137 #define ALT_USB_HOST_HCINTMSK9_ACKMSK_MSB 5
44138 /* The width in bits of the ALT_USB_HOST_HCINTMSK9_ACKMSK register field. */
44139 #define ALT_USB_HOST_HCINTMSK9_ACKMSK_WIDTH 1
44140 /* The mask used to set the ALT_USB_HOST_HCINTMSK9_ACKMSK register field value. */
44141 #define ALT_USB_HOST_HCINTMSK9_ACKMSK_SET_MSK 0x00000020
44142 /* The mask used to clear the ALT_USB_HOST_HCINTMSK9_ACKMSK register field value. */
44143 #define ALT_USB_HOST_HCINTMSK9_ACKMSK_CLR_MSK 0xffffffdf
44144 /* The reset value of the ALT_USB_HOST_HCINTMSK9_ACKMSK register field. */
44145 #define ALT_USB_HOST_HCINTMSK9_ACKMSK_RESET 0x0
44146 /* Extracts the ALT_USB_HOST_HCINTMSK9_ACKMSK field value from a register. */
44147 #define ALT_USB_HOST_HCINTMSK9_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
44148 /* Produces a ALT_USB_HOST_HCINTMSK9_ACKMSK register field value suitable for setting the register. */
44149 #define ALT_USB_HOST_HCINTMSK9_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
44150 
44151 /*
44152  * Field : nyetmsk
44153  *
44154  * NYET Response Received Interrupt Mask (NyetMsk)
44155  *
44156  * In scatter/gather DMA mode for host,
44157  *
44158  * interrupts will not be generated due to the corresponding bits set in
44159  *
44160  * HCINTn.
44161  *
44162  * Field Access Macros:
44163  *
44164  */
44165 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_NYETMSK register field. */
44166 #define ALT_USB_HOST_HCINTMSK9_NYETMSK_LSB 6
44167 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_NYETMSK register field. */
44168 #define ALT_USB_HOST_HCINTMSK9_NYETMSK_MSB 6
44169 /* The width in bits of the ALT_USB_HOST_HCINTMSK9_NYETMSK register field. */
44170 #define ALT_USB_HOST_HCINTMSK9_NYETMSK_WIDTH 1
44171 /* The mask used to set the ALT_USB_HOST_HCINTMSK9_NYETMSK register field value. */
44172 #define ALT_USB_HOST_HCINTMSK9_NYETMSK_SET_MSK 0x00000040
44173 /* The mask used to clear the ALT_USB_HOST_HCINTMSK9_NYETMSK register field value. */
44174 #define ALT_USB_HOST_HCINTMSK9_NYETMSK_CLR_MSK 0xffffffbf
44175 /* The reset value of the ALT_USB_HOST_HCINTMSK9_NYETMSK register field. */
44176 #define ALT_USB_HOST_HCINTMSK9_NYETMSK_RESET 0x0
44177 /* Extracts the ALT_USB_HOST_HCINTMSK9_NYETMSK field value from a register. */
44178 #define ALT_USB_HOST_HCINTMSK9_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
44179 /* Produces a ALT_USB_HOST_HCINTMSK9_NYETMSK register field value suitable for setting the register. */
44180 #define ALT_USB_HOST_HCINTMSK9_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
44181 
44182 /*
44183  * Field : xacterrmsk
44184  *
44185  * Transaction Error Mask (XactErrMsk)
44186  *
44187  * In scatter/gather DMA mode for host,
44188  *
44189  * interrupts will not be generated due to the corresponding bits set in
44190  *
44191  * HCINTn.
44192  *
44193  * Field Access Macros:
44194  *
44195  */
44196 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field. */
44197 #define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_LSB 7
44198 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field. */
44199 #define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_MSB 7
44200 /* The width in bits of the ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field. */
44201 #define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_WIDTH 1
44202 /* The mask used to set the ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field value. */
44203 #define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_SET_MSK 0x00000080
44204 /* The mask used to clear the ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field value. */
44205 #define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_CLR_MSK 0xffffff7f
44206 /* The reset value of the ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field. */
44207 #define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_RESET 0x0
44208 /* Extracts the ALT_USB_HOST_HCINTMSK9_XACTERRMSK field value from a register. */
44209 #define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
44210 /* Produces a ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field value suitable for setting the register. */
44211 #define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
44212 
44213 /*
44214  * Field : bblerrmsk
44215  *
44216  * Babble Error Mask (BblErrMsk)
44217  *
44218  * In scatter/gather DMA mode for host,
44219  *
44220  * interrupts will not be generated due to the corresponding bits set in
44221  *
44222  * HCINTn.
44223  *
44224  * Field Access Macros:
44225  *
44226  */
44227 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field. */
44228 #define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_LSB 8
44229 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field. */
44230 #define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_MSB 8
44231 /* The width in bits of the ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field. */
44232 #define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_WIDTH 1
44233 /* The mask used to set the ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field value. */
44234 #define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_SET_MSK 0x00000100
44235 /* The mask used to clear the ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field value. */
44236 #define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_CLR_MSK 0xfffffeff
44237 /* The reset value of the ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field. */
44238 #define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_RESET 0x0
44239 /* Extracts the ALT_USB_HOST_HCINTMSK9_BBLERRMSK field value from a register. */
44240 #define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
44241 /* Produces a ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field value suitable for setting the register. */
44242 #define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
44243 
44244 /*
44245  * Field : frmovrunmsk
44246  *
44247  * Frame Overrun Mask (FrmOvrunMsk)
44248  *
44249  * In scatter/gather DMA mode for host,
44250  *
44251  * interrupts will not be generated due to the corresponding bits set in
44252  *
44253  * HCINTn.
44254  *
44255  * Field Access Macros:
44256  *
44257  */
44258 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field. */
44259 #define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_LSB 9
44260 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field. */
44261 #define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_MSB 9
44262 /* The width in bits of the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field. */
44263 #define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_WIDTH 1
44264 /* The mask used to set the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field value. */
44265 #define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_SET_MSK 0x00000200
44266 /* The mask used to clear the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field value. */
44267 #define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_CLR_MSK 0xfffffdff
44268 /* The reset value of the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field. */
44269 #define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_RESET 0x0
44270 /* Extracts the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK field value from a register. */
44271 #define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
44272 /* Produces a ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field value suitable for setting the register. */
44273 #define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
44274 
44275 /*
44276  * Field : datatglerrmsk
44277  *
44278  * Data Toggle Error Mask (DataTglErrMsk)
44279  *
44280  * In scatter/gather DMA mode for host,
44281  *
44282  * interrupts will not be generated due to the corresponding bits set in
44283  *
44284  * HCINTn.
44285  *
44286  * Field Access Macros:
44287  *
44288  */
44289 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field. */
44290 #define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_LSB 10
44291 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field. */
44292 #define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_MSB 10
44293 /* The width in bits of the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field. */
44294 #define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_WIDTH 1
44295 /* The mask used to set the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field value. */
44296 #define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_SET_MSK 0x00000400
44297 /* The mask used to clear the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field value. */
44298 #define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_CLR_MSK 0xfffffbff
44299 /* The reset value of the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field. */
44300 #define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_RESET 0x0
44301 /* Extracts the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK field value from a register. */
44302 #define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
44303 /* Produces a ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field value suitable for setting the register. */
44304 #define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
44305 
44306 /*
44307  * Field : bnaintrmsk
44308  *
44309  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
44310  *
44311  * This bit is valid only when Scatter/Gather DMA mode is enabled.
44312  *
44313  * Field Enumeration Values:
44314  *
44315  * Enum | Value | Description
44316  * :------------------------------------------|:------|:------------
44317  * ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_MSK | 0x0 | Mask
44318  * ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_NOMSK | 0x1 | No mask
44319  *
44320  * Field Access Macros:
44321  *
44322  */
44323 /*
44324  * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_BNAINTRMSK
44325  *
44326  * Mask
44327  */
44328 #define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_MSK 0x0
44329 /*
44330  * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_BNAINTRMSK
44331  *
44332  * No mask
44333  */
44334 #define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_NOMSK 0x1
44335 
44336 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */
44337 #define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_LSB 11
44338 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */
44339 #define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_MSB 11
44340 /* The width in bits of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */
44341 #define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_WIDTH 1
44342 /* The mask used to set the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field value. */
44343 #define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_SET_MSK 0x00000800
44344 /* The mask used to clear the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field value. */
44345 #define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_CLR_MSK 0xfffff7ff
44346 /* The reset value of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */
44347 #define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_RESET 0x0
44348 /* Extracts the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK field value from a register. */
44349 #define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
44350 /* Produces a ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field value suitable for setting the register. */
44351 #define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
44352 
44353 /*
44354  * Field : frm_lst_rollintrmsk
44355  *
44356  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
44357  *
44358  * This bit is valid only when Scatter/Gather DMA mode is enabled.
44359  *
44360  * Field Enumeration Values:
44361  *
44362  * Enum | Value | Description
44363  * :---------------------------------------------------|:------|:------------
44364  * ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
44365  * ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
44366  *
44367  * Field Access Macros:
44368  *
44369  */
44370 /*
44371  * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK
44372  *
44373  * Mask
44374  */
44375 #define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_MSK 0x0
44376 /*
44377  * Enumerated value for register field ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK
44378  *
44379  * No mask
44380  */
44381 #define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
44382 
44383 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */
44384 #define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_LSB 13
44385 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */
44386 #define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_MSB 13
44387 /* The width in bits of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */
44388 #define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_WIDTH 1
44389 /* The mask used to set the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field value. */
44390 #define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
44391 /* The mask used to clear the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field value. */
44392 #define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
44393 /* The reset value of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */
44394 #define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_RESET 0x0
44395 /* Extracts the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK field value from a register. */
44396 #define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
44397 /* Produces a ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
44398 #define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
44399 
44400 #ifndef __ASSEMBLY__
44401 /*
44402  * WARNING: The C register and register group struct declarations are provided for
44403  * convenience and illustrative purposes. They should, however, be used with
44404  * caution as the C language standard provides no guarantees about the alignment or
44405  * atomicity of device memory accesses. The recommended practice for writing
44406  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
44407  * alt_write_word() functions.
44408  *
44409  * The struct declaration for register ALT_USB_HOST_HCINTMSK9.
44410  */
44411 struct ALT_USB_HOST_HCINTMSK9_s
44412 {
44413  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK */
44414  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK9_CHHLTDMSK */
44415  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK9_AHBERRMSK */
44416  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK9_STALLMSK */
44417  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK9_NAKMSK */
44418  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK9_ACKMSK */
44419  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK9_NYETMSK */
44420  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK9_XACTERRMSK */
44421  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK9_BBLERRMSK */
44422  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK */
44423  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK */
44424  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK9_BNAINTRMSK */
44425  uint32_t : 1; /* *UNDEFINED* */
44426  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK */
44427  uint32_t : 18; /* *UNDEFINED* */
44428 };
44429 
44430 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK9. */
44431 typedef volatile struct ALT_USB_HOST_HCINTMSK9_s ALT_USB_HOST_HCINTMSK9_t;
44432 #endif /* __ASSEMBLY__ */
44433 
44434 /* The reset value of the ALT_USB_HOST_HCINTMSK9 register. */
44435 #define ALT_USB_HOST_HCINTMSK9_RESET 0x00000000
44436 /* The byte offset of the ALT_USB_HOST_HCINTMSK9 register from the beginning of the component. */
44437 #define ALT_USB_HOST_HCINTMSK9_OFST 0x22c
44438 /* The address of the ALT_USB_HOST_HCINTMSK9 register. */
44439 #define ALT_USB_HOST_HCINTMSK9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK9_OFST))
44440 
44441 /*
44442  * Register : hctsiz9
44443  *
44444  * Host Channel 9 Transfer Size Register
44445  *
44446  * Register Layout
44447  *
44448  * Bits | Access | Reset | Description
44449  * :--------|:-------|:------|:------------------------------
44450  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ9_XFERSIZE
44451  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ9_PKTCNT
44452  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ9_PID
44453  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ9_DOPNG
44454  *
44455  */
44456 /*
44457  * Field : xfersize
44458  *
44459  * Transfer Size (XferSize)
44460  *
44461  * For an OUT, this field is the number of data bytes the host sends
44462  *
44463  * during the transfer.
44464  *
44465  * For an IN, this field is the buffer size that the application has
44466  *
44467  * Reserved For the transfer. The application is expected to
44468  *
44469  * program this field as an integer multiple of the maximum packet
44470  *
44471  * size For IN transactions (periodic and non-periodic).
44472  *
44473  * The width of this counter is specified as Width of Transfer Size
44474  *
44475  * Counters
44476  *
44477  * Field Access Macros:
44478  *
44479  */
44480 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */
44481 #define ALT_USB_HOST_HCTSIZ9_XFERSIZE_LSB 0
44482 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */
44483 #define ALT_USB_HOST_HCTSIZ9_XFERSIZE_MSB 18
44484 /* The width in bits of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */
44485 #define ALT_USB_HOST_HCTSIZ9_XFERSIZE_WIDTH 19
44486 /* The mask used to set the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field value. */
44487 #define ALT_USB_HOST_HCTSIZ9_XFERSIZE_SET_MSK 0x0007ffff
44488 /* The mask used to clear the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field value. */
44489 #define ALT_USB_HOST_HCTSIZ9_XFERSIZE_CLR_MSK 0xfff80000
44490 /* The reset value of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */
44491 #define ALT_USB_HOST_HCTSIZ9_XFERSIZE_RESET 0x0
44492 /* Extracts the ALT_USB_HOST_HCTSIZ9_XFERSIZE field value from a register. */
44493 #define ALT_USB_HOST_HCTSIZ9_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
44494 /* Produces a ALT_USB_HOST_HCTSIZ9_XFERSIZE register field value suitable for setting the register. */
44495 #define ALT_USB_HOST_HCTSIZ9_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
44496 
44497 /*
44498  * Field : pktcnt
44499  *
44500  * Packet Count (PktCnt)
44501  *
44502  * This field is programmed by the application with the expected
44503  *
44504  * number of packets to be transmitted (OUT) or received (IN).
44505  *
44506  * The host decrements this count on every successful
44507  *
44508  * transmission or reception of an OUT/IN packet. Once this count
44509  *
44510  * reaches zero, the application is interrupted to indicate normal
44511  *
44512  * completion.
44513  *
44514  * The width of this counter is specified as Width of Packet
44515  *
44516  * Counters
44517  *
44518  * Field Access Macros:
44519  *
44520  */
44521 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */
44522 #define ALT_USB_HOST_HCTSIZ9_PKTCNT_LSB 19
44523 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */
44524 #define ALT_USB_HOST_HCTSIZ9_PKTCNT_MSB 28
44525 /* The width in bits of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */
44526 #define ALT_USB_HOST_HCTSIZ9_PKTCNT_WIDTH 10
44527 /* The mask used to set the ALT_USB_HOST_HCTSIZ9_PKTCNT register field value. */
44528 #define ALT_USB_HOST_HCTSIZ9_PKTCNT_SET_MSK 0x1ff80000
44529 /* The mask used to clear the ALT_USB_HOST_HCTSIZ9_PKTCNT register field value. */
44530 #define ALT_USB_HOST_HCTSIZ9_PKTCNT_CLR_MSK 0xe007ffff
44531 /* The reset value of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */
44532 #define ALT_USB_HOST_HCTSIZ9_PKTCNT_RESET 0x0
44533 /* Extracts the ALT_USB_HOST_HCTSIZ9_PKTCNT field value from a register. */
44534 #define ALT_USB_HOST_HCTSIZ9_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
44535 /* Produces a ALT_USB_HOST_HCTSIZ9_PKTCNT register field value suitable for setting the register. */
44536 #define ALT_USB_HOST_HCTSIZ9_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
44537 
44538 /*
44539  * Field : pid
44540  *
44541  * PID (Pid)
44542  *
44543  * The application programs this field with the type of PID to use For
44544  *
44545  * the initial transaction. The host maintains this field For the rest of
44546  *
44547  * the transfer.
44548  *
44549  * 2'b00: DATA0
44550  *
44551  * 2'b01: DATA2
44552  *
44553  * 2'b10: DATA1
44554  *
44555  * 2'b11: MDATA (non-control)/SETUP (control)
44556  *
44557  * Field Enumeration Values:
44558  *
44559  * Enum | Value | Description
44560  * :---------------------------------|:------|:------------------------------------
44561  * ALT_USB_HOST_HCTSIZ9_PID_E_DATA0 | 0x0 | DATA0
44562  * ALT_USB_HOST_HCTSIZ9_PID_E_DATA2 | 0x1 | DATA2
44563  * ALT_USB_HOST_HCTSIZ9_PID_E_DATA1 | 0x2 | DATA1
44564  * ALT_USB_HOST_HCTSIZ9_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
44565  *
44566  * Field Access Macros:
44567  *
44568  */
44569 /*
44570  * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID
44571  *
44572  * DATA0
44573  */
44574 #define ALT_USB_HOST_HCTSIZ9_PID_E_DATA0 0x0
44575 /*
44576  * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID
44577  *
44578  * DATA2
44579  */
44580 #define ALT_USB_HOST_HCTSIZ9_PID_E_DATA2 0x1
44581 /*
44582  * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID
44583  *
44584  * DATA1
44585  */
44586 #define ALT_USB_HOST_HCTSIZ9_PID_E_DATA1 0x2
44587 /*
44588  * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID
44589  *
44590  * MDATA (non-control)/SETUP (control)
44591  */
44592 #define ALT_USB_HOST_HCTSIZ9_PID_E_MDATA 0x3
44593 
44594 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_PID register field. */
44595 #define ALT_USB_HOST_HCTSIZ9_PID_LSB 29
44596 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_PID register field. */
44597 #define ALT_USB_HOST_HCTSIZ9_PID_MSB 30
44598 /* The width in bits of the ALT_USB_HOST_HCTSIZ9_PID register field. */
44599 #define ALT_USB_HOST_HCTSIZ9_PID_WIDTH 2
44600 /* The mask used to set the ALT_USB_HOST_HCTSIZ9_PID register field value. */
44601 #define ALT_USB_HOST_HCTSIZ9_PID_SET_MSK 0x60000000
44602 /* The mask used to clear the ALT_USB_HOST_HCTSIZ9_PID register field value. */
44603 #define ALT_USB_HOST_HCTSIZ9_PID_CLR_MSK 0x9fffffff
44604 /* The reset value of the ALT_USB_HOST_HCTSIZ9_PID register field. */
44605 #define ALT_USB_HOST_HCTSIZ9_PID_RESET 0x0
44606 /* Extracts the ALT_USB_HOST_HCTSIZ9_PID field value from a register. */
44607 #define ALT_USB_HOST_HCTSIZ9_PID_GET(value) (((value) & 0x60000000) >> 29)
44608 /* Produces a ALT_USB_HOST_HCTSIZ9_PID register field value suitable for setting the register. */
44609 #define ALT_USB_HOST_HCTSIZ9_PID_SET(value) (((value) << 29) & 0x60000000)
44610 
44611 /*
44612  * Field : dopng
44613  *
44614  * Do Ping (DoPng)
44615  *
44616  * This bit is used only For OUT transfers.
44617  *
44618  * Setting this field to 1 directs the host to do PING protocol.
44619  *
44620  * Note: Do not Set this bit For IN transfers. If this bit is Set For
44621  *
44622  * for IN transfers it disables the channel.
44623  *
44624  * Field Enumeration Values:
44625  *
44626  * Enum | Value | Description
44627  * :------------------------------------|:------|:-----------------
44628  * ALT_USB_HOST_HCTSIZ9_DOPNG_E_NOPING | 0x0 | No ping protocol
44629  * ALT_USB_HOST_HCTSIZ9_DOPNG_E_PING | 0x1 | Ping protocol
44630  *
44631  * Field Access Macros:
44632  *
44633  */
44634 /*
44635  * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_DOPNG
44636  *
44637  * No ping protocol
44638  */
44639 #define ALT_USB_HOST_HCTSIZ9_DOPNG_E_NOPING 0x0
44640 /*
44641  * Enumerated value for register field ALT_USB_HOST_HCTSIZ9_DOPNG
44642  *
44643  * Ping protocol
44644  */
44645 #define ALT_USB_HOST_HCTSIZ9_DOPNG_E_PING 0x1
44646 
44647 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */
44648 #define ALT_USB_HOST_HCTSIZ9_DOPNG_LSB 31
44649 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */
44650 #define ALT_USB_HOST_HCTSIZ9_DOPNG_MSB 31
44651 /* The width in bits of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */
44652 #define ALT_USB_HOST_HCTSIZ9_DOPNG_WIDTH 1
44653 /* The mask used to set the ALT_USB_HOST_HCTSIZ9_DOPNG register field value. */
44654 #define ALT_USB_HOST_HCTSIZ9_DOPNG_SET_MSK 0x80000000
44655 /* The mask used to clear the ALT_USB_HOST_HCTSIZ9_DOPNG register field value. */
44656 #define ALT_USB_HOST_HCTSIZ9_DOPNG_CLR_MSK 0x7fffffff
44657 /* The reset value of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */
44658 #define ALT_USB_HOST_HCTSIZ9_DOPNG_RESET 0x0
44659 /* Extracts the ALT_USB_HOST_HCTSIZ9_DOPNG field value from a register. */
44660 #define ALT_USB_HOST_HCTSIZ9_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
44661 /* Produces a ALT_USB_HOST_HCTSIZ9_DOPNG register field value suitable for setting the register. */
44662 #define ALT_USB_HOST_HCTSIZ9_DOPNG_SET(value) (((value) << 31) & 0x80000000)
44663 
44664 #ifndef __ASSEMBLY__
44665 /*
44666  * WARNING: The C register and register group struct declarations are provided for
44667  * convenience and illustrative purposes. They should, however, be used with
44668  * caution as the C language standard provides no guarantees about the alignment or
44669  * atomicity of device memory accesses. The recommended practice for writing
44670  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
44671  * alt_write_word() functions.
44672  *
44673  * The struct declaration for register ALT_USB_HOST_HCTSIZ9.
44674  */
44675 struct ALT_USB_HOST_HCTSIZ9_s
44676 {
44677  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ9_XFERSIZE */
44678  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ9_PKTCNT */
44679  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ9_PID */
44680  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ9_DOPNG */
44681 };
44682 
44683 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ9. */
44684 typedef volatile struct ALT_USB_HOST_HCTSIZ9_s ALT_USB_HOST_HCTSIZ9_t;
44685 #endif /* __ASSEMBLY__ */
44686 
44687 /* The reset value of the ALT_USB_HOST_HCTSIZ9 register. */
44688 #define ALT_USB_HOST_HCTSIZ9_RESET 0x00000000
44689 /* The byte offset of the ALT_USB_HOST_HCTSIZ9 register from the beginning of the component. */
44690 #define ALT_USB_HOST_HCTSIZ9_OFST 0x230
44691 /* The address of the ALT_USB_HOST_HCTSIZ9 register. */
44692 #define ALT_USB_HOST_HCTSIZ9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ9_OFST))
44693 
44694 /*
44695  * Register : hcdma9
44696  *
44697  * Host Channel 9 DMA Address Register
44698  *
44699  * Register Layout
44700  *
44701  * Bits | Access | Reset | Description
44702  * :-------|:-------|:------|:---------------------------
44703  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA9_HCDMA9
44704  *
44705  */
44706 /*
44707  * Field : hcdma9
44708  *
44709  * Buffer DMA Mode:
44710  *
44711  * [31:0] DMA Address (DMAAddr)
44712  *
44713  * This field holds the start address in the external memory from which the data
44714  * for
44715  *
44716  * the endpoint must be fetched or to which it must be stored. This register is
44717  *
44718  * incremented on every AHB transaction.
44719  *
44720  * Scatter-Gather DMA (DescDMA) Mode:
44721  *
44722  * [31:9] (Non Isoc) Non-Isochronous:
44723  *
44724  * [31:N] (Isoc) Isochronous:
44725  *
44726  * This field holds the start address of the 512 bytes
44727  *
44728  * page. The first descriptor in the list should be located
44729  *
44730  * in this address. The first descriptor may be or may
44731  *
44732  * not be ready. The core starts processing the list from
44733  *
44734  * the CTD value.
44735  *
44736  * This field holds the address of the 2*(nTD+1) bytes of
44737  *
44738  * locations in which the isochronous descriptors are
44739  *
44740  * present where N is based on nTD as per Table below
44741  *
44742  * [31:N] Base Address
44743  *
44744  * [N-1:3] Offset
44745  *
44746  * [2:0] 000
44747  *
44748  * HS ISOC
44749  *
44750  * nTD N
44751  *
44752  * 7 6
44753  *
44754  * 15 7
44755  *
44756  * 31 8
44757  *
44758  * 63 9
44759  *
44760  * 127 10
44761  *
44762  * 255 11
44763  *
44764  * FS ISOC
44765  *
44766  * nTD N
44767  *
44768  * 1 4
44769  *
44770  * 3 5
44771  *
44772  * 7 6
44773  *
44774  * 15 7
44775  *
44776  * 31 8
44777  *
44778  * 63 9
44779  *
44780  * [N-1:3] (Isoc):
44781  *
44782  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
44783  *
44784  * Non Isochronous:
44785  *
44786  * This value is in terms of number of descriptors. The values can be from 0 to 63.
44787  *
44788  * 0 - 1 descriptor.
44789  *
44790  * 63 - 64 descriptors.
44791  *
44792  * This field indicates the current descriptor processed in the list. This field is
44793  * updated
44794  *
44795  * both by application and the core. For example, if the application enables the
44796  *
44797  * channel after programming CTD=5, then the core will start processing the 6th
44798  *
44799  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
44800  *
44801  * to DMAAddr.
44802  *
44803  * Isochronous:
44804  *
44805  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
44806  * set
44807  *
44808  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
44809  *
44810  * [31:9] (Non Isoc) Non-Isochronous:
44811  *
44812  * [31:N] (Isoc) Isochronous:
44813  *
44814  * This field holds the start address of the 512 bytes
44815  *
44816  * page. The first descriptor in the list should be located
44817  *
44818  * in this address. The first descriptor may be or may
44819  *
44820  * not be ready. The core starts processing the list from
44821  *
44822  * the CTD value.
44823  *
44824  * This field holds the address of the 2*(nTD+1) bytes of
44825  *
44826  * locations in which the isochronous descriptors are
44827  *
44828  * present where N is based on nTD as per Table below
44829  *
44830  * [31:N] Base Address
44831  *
44832  * [N-1:3] Offset
44833  *
44834  * [2:0] 000
44835  *
44836  * HS ISOC
44837  *
44838  * nTD N
44839  *
44840  * 7 6
44841  *
44842  * 15 7
44843  *
44844  * 31 8
44845  *
44846  * 63 9
44847  *
44848  * 127 10
44849  *
44850  * 255 11
44851  *
44852  * FS ISOC
44853  *
44854  * nTD N
44855  *
44856  * 1 4
44857  *
44858  * 3 5
44859  *
44860  * 7 6
44861  *
44862  * 15 7
44863  *
44864  * 31 8
44865  *
44866  * 63 9
44867  *
44868  * [N-1:3] (Isoc):
44869  *
44870  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
44871  *
44872  * Non Isochronous:
44873  *
44874  * This value is in terms of number of descriptors. The values can be from 0 to 63.
44875  *
44876  * 0 - 1 descriptor.
44877  *
44878  * 63 - 64 descriptors.
44879  *
44880  * This field indicates the current descriptor processed in the list. This field is
44881  * updated
44882  *
44883  * both by application and the core. For example, if the application enables the
44884  *
44885  * channel after programming CTD=5, then the core will start processing the 6th
44886  *
44887  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
44888  *
44889  * to DMAAddr.
44890  *
44891  * Isochronous:
44892  *
44893  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
44894  * set
44895  *
44896  * to zero by application.
44897  *
44898  * Field Access Macros:
44899  *
44900  */
44901 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */
44902 #define ALT_USB_HOST_HCDMA9_HCDMA9_LSB 0
44903 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */
44904 #define ALT_USB_HOST_HCDMA9_HCDMA9_MSB 31
44905 /* The width in bits of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */
44906 #define ALT_USB_HOST_HCDMA9_HCDMA9_WIDTH 32
44907 /* The mask used to set the ALT_USB_HOST_HCDMA9_HCDMA9 register field value. */
44908 #define ALT_USB_HOST_HCDMA9_HCDMA9_SET_MSK 0xffffffff
44909 /* The mask used to clear the ALT_USB_HOST_HCDMA9_HCDMA9 register field value. */
44910 #define ALT_USB_HOST_HCDMA9_HCDMA9_CLR_MSK 0x00000000
44911 /* The reset value of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */
44912 #define ALT_USB_HOST_HCDMA9_HCDMA9_RESET 0x0
44913 /* Extracts the ALT_USB_HOST_HCDMA9_HCDMA9 field value from a register. */
44914 #define ALT_USB_HOST_HCDMA9_HCDMA9_GET(value) (((value) & 0xffffffff) >> 0)
44915 /* Produces a ALT_USB_HOST_HCDMA9_HCDMA9 register field value suitable for setting the register. */
44916 #define ALT_USB_HOST_HCDMA9_HCDMA9_SET(value) (((value) << 0) & 0xffffffff)
44917 
44918 #ifndef __ASSEMBLY__
44919 /*
44920  * WARNING: The C register and register group struct declarations are provided for
44921  * convenience and illustrative purposes. They should, however, be used with
44922  * caution as the C language standard provides no guarantees about the alignment or
44923  * atomicity of device memory accesses. The recommended practice for writing
44924  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
44925  * alt_write_word() functions.
44926  *
44927  * The struct declaration for register ALT_USB_HOST_HCDMA9.
44928  */
44929 struct ALT_USB_HOST_HCDMA9_s
44930 {
44931  uint32_t hcdma9 : 32; /* ALT_USB_HOST_HCDMA9_HCDMA9 */
44932 };
44933 
44934 /* The typedef declaration for register ALT_USB_HOST_HCDMA9. */
44935 typedef volatile struct ALT_USB_HOST_HCDMA9_s ALT_USB_HOST_HCDMA9_t;
44936 #endif /* __ASSEMBLY__ */
44937 
44938 /* The reset value of the ALT_USB_HOST_HCDMA9 register. */
44939 #define ALT_USB_HOST_HCDMA9_RESET 0x00000000
44940 /* The byte offset of the ALT_USB_HOST_HCDMA9 register from the beginning of the component. */
44941 #define ALT_USB_HOST_HCDMA9_OFST 0x234
44942 /* The address of the ALT_USB_HOST_HCDMA9 register. */
44943 #define ALT_USB_HOST_HCDMA9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA9_OFST))
44944 
44945 /*
44946  * Register : hcdmab9
44947  *
44948  * Host Channel 9 DMA Buffer Address Register
44949  *
44950  * Register Layout
44951  *
44952  * Bits | Access | Reset | Description
44953  * :-------|:-------|:------|:-----------------------------
44954  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB9_HCDMAB9
44955  *
44956  */
44957 /*
44958  * Field : hcdmab9
44959  *
44960  * Holds the current buffer address.
44961  *
44962  * This register is updated as and when the data transfer for the corresponding end
44963  * point
44964  *
44965  * is in progress. This register is present only in Scatter/Gather DMA mode.
44966  * Otherwise this
44967  *
44968  * field is reserved.
44969  *
44970  * Field Access Macros:
44971  *
44972  */
44973 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */
44974 #define ALT_USB_HOST_HCDMAB9_HCDMAB9_LSB 0
44975 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */
44976 #define ALT_USB_HOST_HCDMAB9_HCDMAB9_MSB 31
44977 /* The width in bits of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */
44978 #define ALT_USB_HOST_HCDMAB9_HCDMAB9_WIDTH 32
44979 /* The mask used to set the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field value. */
44980 #define ALT_USB_HOST_HCDMAB9_HCDMAB9_SET_MSK 0xffffffff
44981 /* The mask used to clear the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field value. */
44982 #define ALT_USB_HOST_HCDMAB9_HCDMAB9_CLR_MSK 0x00000000
44983 /* The reset value of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */
44984 #define ALT_USB_HOST_HCDMAB9_HCDMAB9_RESET 0x0
44985 /* Extracts the ALT_USB_HOST_HCDMAB9_HCDMAB9 field value from a register. */
44986 #define ALT_USB_HOST_HCDMAB9_HCDMAB9_GET(value) (((value) & 0xffffffff) >> 0)
44987 /* Produces a ALT_USB_HOST_HCDMAB9_HCDMAB9 register field value suitable for setting the register. */
44988 #define ALT_USB_HOST_HCDMAB9_HCDMAB9_SET(value) (((value) << 0) & 0xffffffff)
44989 
44990 #ifndef __ASSEMBLY__
44991 /*
44992  * WARNING: The C register and register group struct declarations are provided for
44993  * convenience and illustrative purposes. They should, however, be used with
44994  * caution as the C language standard provides no guarantees about the alignment or
44995  * atomicity of device memory accesses. The recommended practice for writing
44996  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
44997  * alt_write_word() functions.
44998  *
44999  * The struct declaration for register ALT_USB_HOST_HCDMAB9.
45000  */
45001 struct ALT_USB_HOST_HCDMAB9_s
45002 {
45003  uint32_t hcdmab9 : 32; /* ALT_USB_HOST_HCDMAB9_HCDMAB9 */
45004 };
45005 
45006 /* The typedef declaration for register ALT_USB_HOST_HCDMAB9. */
45007 typedef volatile struct ALT_USB_HOST_HCDMAB9_s ALT_USB_HOST_HCDMAB9_t;
45008 #endif /* __ASSEMBLY__ */
45009 
45010 /* The reset value of the ALT_USB_HOST_HCDMAB9 register. */
45011 #define ALT_USB_HOST_HCDMAB9_RESET 0x00000000
45012 /* The byte offset of the ALT_USB_HOST_HCDMAB9 register from the beginning of the component. */
45013 #define ALT_USB_HOST_HCDMAB9_OFST 0x23c
45014 /* The address of the ALT_USB_HOST_HCDMAB9 register. */
45015 #define ALT_USB_HOST_HCDMAB9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB9_OFST))
45016 
45017 /*
45018  * Register : hcchar10
45019  *
45020  * Host Channel 10 Characteristics Register
45021  *
45022  * Register Layout
45023  *
45024  * Bits | Access | Reset | Description
45025  * :--------|:---------|:------|:------------------------------
45026  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_MPS
45027  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_EPNUM
45028  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_EPDIR
45029  * [16] | ??? | 0x0 | *UNDEFINED*
45030  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_LSPDDEV
45031  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_EPTYPE
45032  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_EC
45033  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_DEVADDR
45034  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_ODDFRM
45035  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR10_CHDIS
45036  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR10_CHENA
45037  *
45038  */
45039 /*
45040  * Field : mps
45041  *
45042  * Maximum Packet Size (MPS)
45043  *
45044  * Indicates the maximum packet size of the associated endpoint.
45045  *
45046  * Field Access Macros:
45047  *
45048  */
45049 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_MPS register field. */
45050 #define ALT_USB_HOST_HCCHAR10_MPS_LSB 0
45051 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_MPS register field. */
45052 #define ALT_USB_HOST_HCCHAR10_MPS_MSB 10
45053 /* The width in bits of the ALT_USB_HOST_HCCHAR10_MPS register field. */
45054 #define ALT_USB_HOST_HCCHAR10_MPS_WIDTH 11
45055 /* The mask used to set the ALT_USB_HOST_HCCHAR10_MPS register field value. */
45056 #define ALT_USB_HOST_HCCHAR10_MPS_SET_MSK 0x000007ff
45057 /* The mask used to clear the ALT_USB_HOST_HCCHAR10_MPS register field value. */
45058 #define ALT_USB_HOST_HCCHAR10_MPS_CLR_MSK 0xfffff800
45059 /* The reset value of the ALT_USB_HOST_HCCHAR10_MPS register field. */
45060 #define ALT_USB_HOST_HCCHAR10_MPS_RESET 0x0
45061 /* Extracts the ALT_USB_HOST_HCCHAR10_MPS field value from a register. */
45062 #define ALT_USB_HOST_HCCHAR10_MPS_GET(value) (((value) & 0x000007ff) >> 0)
45063 /* Produces a ALT_USB_HOST_HCCHAR10_MPS register field value suitable for setting the register. */
45064 #define ALT_USB_HOST_HCCHAR10_MPS_SET(value) (((value) << 0) & 0x000007ff)
45065 
45066 /*
45067  * Field : epnum
45068  *
45069  * Endpoint Number (EPNum)
45070  *
45071  * Indicates the endpoint number on the device serving as the data
45072  *
45073  * source or sink.
45074  *
45075  * Field Enumeration Values:
45076  *
45077  * Enum | Value | Description
45078  * :--------------------------------------|:------|:--------------
45079  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT0 | 0x0 | End point 0
45080  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT1 | 0x1 | End point 1
45081  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT2 | 0x2 | End point 2
45082  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT3 | 0x3 | End point 3
45083  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT4 | 0x4 | End point 4
45084  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT5 | 0x5 | End point 5
45085  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT6 | 0x6 | End point 6
45086  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT7 | 0x7 | End point 7
45087  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT8 | 0x8 | End point 8
45088  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT9 | 0x9 | End point 9
45089  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT10 | 0xa | End point 10
45090  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT11 | 0xb | End point 11
45091  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT12 | 0xc | End point 12
45092  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT13 | 0xd | End point 13
45093  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT14 | 0xe | End point 14
45094  * ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT15 | 0xf | End point 15
45095  *
45096  * Field Access Macros:
45097  *
45098  */
45099 /*
45100  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45101  *
45102  * End point 0
45103  */
45104 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT0 0x0
45105 /*
45106  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45107  *
45108  * End point 1
45109  */
45110 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT1 0x1
45111 /*
45112  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45113  *
45114  * End point 2
45115  */
45116 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT2 0x2
45117 /*
45118  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45119  *
45120  * End point 3
45121  */
45122 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT3 0x3
45123 /*
45124  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45125  *
45126  * End point 4
45127  */
45128 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT4 0x4
45129 /*
45130  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45131  *
45132  * End point 5
45133  */
45134 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT5 0x5
45135 /*
45136  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45137  *
45138  * End point 6
45139  */
45140 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT6 0x6
45141 /*
45142  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45143  *
45144  * End point 7
45145  */
45146 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT7 0x7
45147 /*
45148  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45149  *
45150  * End point 8
45151  */
45152 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT8 0x8
45153 /*
45154  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45155  *
45156  * End point 9
45157  */
45158 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT9 0x9
45159 /*
45160  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45161  *
45162  * End point 10
45163  */
45164 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT10 0xa
45165 /*
45166  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45167  *
45168  * End point 11
45169  */
45170 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT11 0xb
45171 /*
45172  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45173  *
45174  * End point 12
45175  */
45176 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT12 0xc
45177 /*
45178  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45179  *
45180  * End point 13
45181  */
45182 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT13 0xd
45183 /*
45184  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45185  *
45186  * End point 14
45187  */
45188 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT14 0xe
45189 /*
45190  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
45191  *
45192  * End point 15
45193  */
45194 #define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT15 0xf
45195 
45196 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */
45197 #define ALT_USB_HOST_HCCHAR10_EPNUM_LSB 11
45198 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */
45199 #define ALT_USB_HOST_HCCHAR10_EPNUM_MSB 14
45200 /* The width in bits of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */
45201 #define ALT_USB_HOST_HCCHAR10_EPNUM_WIDTH 4
45202 /* The mask used to set the ALT_USB_HOST_HCCHAR10_EPNUM register field value. */
45203 #define ALT_USB_HOST_HCCHAR10_EPNUM_SET_MSK 0x00007800
45204 /* The mask used to clear the ALT_USB_HOST_HCCHAR10_EPNUM register field value. */
45205 #define ALT_USB_HOST_HCCHAR10_EPNUM_CLR_MSK 0xffff87ff
45206 /* The reset value of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */
45207 #define ALT_USB_HOST_HCCHAR10_EPNUM_RESET 0x0
45208 /* Extracts the ALT_USB_HOST_HCCHAR10_EPNUM field value from a register. */
45209 #define ALT_USB_HOST_HCCHAR10_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
45210 /* Produces a ALT_USB_HOST_HCCHAR10_EPNUM register field value suitable for setting the register. */
45211 #define ALT_USB_HOST_HCCHAR10_EPNUM_SET(value) (((value) << 11) & 0x00007800)
45212 
45213 /*
45214  * Field : epdir
45215  *
45216  * Endpoint Direction (EPDir)
45217  *
45218  * Indicates whether the transaction is IN or OUT.
45219  *
45220  * 1'b0: OUT
45221  *
45222  * 1'b1: IN
45223  *
45224  * Field Enumeration Values:
45225  *
45226  * Enum | Value | Description
45227  * :----------------------------------|:------|:--------------
45228  * ALT_USB_HOST_HCCHAR10_EPDIR_E_OUT | 0x0 | OUT Direction
45229  * ALT_USB_HOST_HCCHAR10_EPDIR_E_IN | 0x1 | IN Direction
45230  *
45231  * Field Access Macros:
45232  *
45233  */
45234 /*
45235  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPDIR
45236  *
45237  * OUT Direction
45238  */
45239 #define ALT_USB_HOST_HCCHAR10_EPDIR_E_OUT 0x0
45240 /*
45241  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPDIR
45242  *
45243  * IN Direction
45244  */
45245 #define ALT_USB_HOST_HCCHAR10_EPDIR_E_IN 0x1
45246 
45247 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */
45248 #define ALT_USB_HOST_HCCHAR10_EPDIR_LSB 15
45249 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */
45250 #define ALT_USB_HOST_HCCHAR10_EPDIR_MSB 15
45251 /* The width in bits of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */
45252 #define ALT_USB_HOST_HCCHAR10_EPDIR_WIDTH 1
45253 /* The mask used to set the ALT_USB_HOST_HCCHAR10_EPDIR register field value. */
45254 #define ALT_USB_HOST_HCCHAR10_EPDIR_SET_MSK 0x00008000
45255 /* The mask used to clear the ALT_USB_HOST_HCCHAR10_EPDIR register field value. */
45256 #define ALT_USB_HOST_HCCHAR10_EPDIR_CLR_MSK 0xffff7fff
45257 /* The reset value of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */
45258 #define ALT_USB_HOST_HCCHAR10_EPDIR_RESET 0x0
45259 /* Extracts the ALT_USB_HOST_HCCHAR10_EPDIR field value from a register. */
45260 #define ALT_USB_HOST_HCCHAR10_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
45261 /* Produces a ALT_USB_HOST_HCCHAR10_EPDIR register field value suitable for setting the register. */
45262 #define ALT_USB_HOST_HCCHAR10_EPDIR_SET(value) (((value) << 15) & 0x00008000)
45263 
45264 /*
45265  * Field : lspddev
45266  *
45267  * Low-Speed Device (LSpdDev)
45268  *
45269  * This field is Set by the application to indicate that this channel is
45270  *
45271  * communicating to a low-speed device.
45272  *
45273  * Field Enumeration Values:
45274  *
45275  * Enum | Value | Description
45276  * :-------------------------------------|:------|:----------------------------------------
45277  * ALT_USB_HOST_HCCHAR10_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
45278  * ALT_USB_HOST_HCCHAR10_LSPDDEV_E_END | 0x1 | Communicating with low speed device
45279  *
45280  * Field Access Macros:
45281  *
45282  */
45283 /*
45284  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_LSPDDEV
45285  *
45286  * Not Communicating with low speed device
45287  */
45288 #define ALT_USB_HOST_HCCHAR10_LSPDDEV_E_DISD 0x0
45289 /*
45290  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_LSPDDEV
45291  *
45292  * Communicating with low speed device
45293  */
45294 #define ALT_USB_HOST_HCCHAR10_LSPDDEV_E_END 0x1
45295 
45296 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */
45297 #define ALT_USB_HOST_HCCHAR10_LSPDDEV_LSB 17
45298 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */
45299 #define ALT_USB_HOST_HCCHAR10_LSPDDEV_MSB 17
45300 /* The width in bits of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */
45301 #define ALT_USB_HOST_HCCHAR10_LSPDDEV_WIDTH 1
45302 /* The mask used to set the ALT_USB_HOST_HCCHAR10_LSPDDEV register field value. */
45303 #define ALT_USB_HOST_HCCHAR10_LSPDDEV_SET_MSK 0x00020000
45304 /* The mask used to clear the ALT_USB_HOST_HCCHAR10_LSPDDEV register field value. */
45305 #define ALT_USB_HOST_HCCHAR10_LSPDDEV_CLR_MSK 0xfffdffff
45306 /* The reset value of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */
45307 #define ALT_USB_HOST_HCCHAR10_LSPDDEV_RESET 0x0
45308 /* Extracts the ALT_USB_HOST_HCCHAR10_LSPDDEV field value from a register. */
45309 #define ALT_USB_HOST_HCCHAR10_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
45310 /* Produces a ALT_USB_HOST_HCCHAR10_LSPDDEV register field value suitable for setting the register. */
45311 #define ALT_USB_HOST_HCCHAR10_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
45312 
45313 /*
45314  * Field : eptype
45315  *
45316  * Endpoint Type (EPType)
45317  *
45318  * Indicates the transfer type selected.
45319  *
45320  * 2'b00: Control
45321  *
45322  * 2'b01: Isochronous
45323  *
45324  * 2'b10: Bulk
45325  *
45326  * 2'b11: Interrupt
45327  *
45328  * Field Enumeration Values:
45329  *
45330  * Enum | Value | Description
45331  * :--------------------------------------|:------|:------------
45332  * ALT_USB_HOST_HCCHAR10_EPTYPE_E_CTL | 0x0 | Control
45333  * ALT_USB_HOST_HCCHAR10_EPTYPE_E_ISOC | 0x1 | Isochronous
45334  * ALT_USB_HOST_HCCHAR10_EPTYPE_E_BULK | 0x2 | Bulk
45335  * ALT_USB_HOST_HCCHAR10_EPTYPE_E_INTERR | 0x3 | Interrupt
45336  *
45337  * Field Access Macros:
45338  *
45339  */
45340 /*
45341  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE
45342  *
45343  * Control
45344  */
45345 #define ALT_USB_HOST_HCCHAR10_EPTYPE_E_CTL 0x0
45346 /*
45347  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE
45348  *
45349  * Isochronous
45350  */
45351 #define ALT_USB_HOST_HCCHAR10_EPTYPE_E_ISOC 0x1
45352 /*
45353  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE
45354  *
45355  * Bulk
45356  */
45357 #define ALT_USB_HOST_HCCHAR10_EPTYPE_E_BULK 0x2
45358 /*
45359  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE
45360  *
45361  * Interrupt
45362  */
45363 #define ALT_USB_HOST_HCCHAR10_EPTYPE_E_INTERR 0x3
45364 
45365 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */
45366 #define ALT_USB_HOST_HCCHAR10_EPTYPE_LSB 18
45367 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */
45368 #define ALT_USB_HOST_HCCHAR10_EPTYPE_MSB 19
45369 /* The width in bits of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */
45370 #define ALT_USB_HOST_HCCHAR10_EPTYPE_WIDTH 2
45371 /* The mask used to set the ALT_USB_HOST_HCCHAR10_EPTYPE register field value. */
45372 #define ALT_USB_HOST_HCCHAR10_EPTYPE_SET_MSK 0x000c0000
45373 /* The mask used to clear the ALT_USB_HOST_HCCHAR10_EPTYPE register field value. */
45374 #define ALT_USB_HOST_HCCHAR10_EPTYPE_CLR_MSK 0xfff3ffff
45375 /* The reset value of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */
45376 #define ALT_USB_HOST_HCCHAR10_EPTYPE_RESET 0x0
45377 /* Extracts the ALT_USB_HOST_HCCHAR10_EPTYPE field value from a register. */
45378 #define ALT_USB_HOST_HCCHAR10_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
45379 /* Produces a ALT_USB_HOST_HCCHAR10_EPTYPE register field value suitable for setting the register. */
45380 #define ALT_USB_HOST_HCCHAR10_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
45381 
45382 /*
45383  * Field : ec
45384  *
45385  * Multi Count (MC) / Error Count (EC)
45386  *
45387  * When the Split Enable bit of the Host Channel-n Split Control
45388  *
45389  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
45390  *
45391  * the host the number of transactions that must be executed per
45392  *
45393  * microframe For this periodic endpoint. For non periodic transfers,
45394  *
45395  * this field is used only in DMA mode, and specifies the number
45396  *
45397  * packets to be fetched For this channel before the internal DMA
45398  *
45399  * engine changes arbitration.
45400  *
45401  * 2'b00: Reserved This field yields undefined results.
45402  *
45403  * 2'b01: 1 transaction
45404  *
45405  * 2'b10: 2 transactions to be issued For this endpoint per
45406  *
45407  * microframe
45408  *
45409  * 2'b11: 3 transactions to be issued For this endpoint per
45410  *
45411  * microframe
45412  *
45413  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
45414  *
45415  * number of immediate retries to be performed For a periodic split
45416  *
45417  * transactions on transaction errors. This field must be Set to at
45418  *
45419  * least 2'b01.
45420  *
45421  * Field Enumeration Values:
45422  *
45423  * Enum | Value | Description
45424  * :--------------------------------------|:------|:----------------------------------------------
45425  * ALT_USB_HOST_HCCHAR10_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
45426  * ALT_USB_HOST_HCCHAR10_EC_E_TRANSONE | 0x1 | 1 transaction
45427  * ALT_USB_HOST_HCCHAR10_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
45428  * : | | per microframe
45429  * ALT_USB_HOST_HCCHAR10_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
45430  * : | | per microframe
45431  *
45432  * Field Access Macros:
45433  *
45434  */
45435 /*
45436  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC
45437  *
45438  * Reserved This field yields undefined result
45439  */
45440 #define ALT_USB_HOST_HCCHAR10_EC_E_RSVD 0x0
45441 /*
45442  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC
45443  *
45444  * 1 transaction
45445  */
45446 #define ALT_USB_HOST_HCCHAR10_EC_E_TRANSONE 0x1
45447 /*
45448  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC
45449  *
45450  * 2 transactions to be issued for this endpoint per microframe
45451  */
45452 #define ALT_USB_HOST_HCCHAR10_EC_E_TRANSTWO 0x2
45453 /*
45454  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC
45455  *
45456  * 3 transactions to be issued for this endpoint per microframe
45457  */
45458 #define ALT_USB_HOST_HCCHAR10_EC_E_TRANSTHREE 0x3
45459 
45460 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EC register field. */
45461 #define ALT_USB_HOST_HCCHAR10_EC_LSB 20
45462 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EC register field. */
45463 #define ALT_USB_HOST_HCCHAR10_EC_MSB 21
45464 /* The width in bits of the ALT_USB_HOST_HCCHAR10_EC register field. */
45465 #define ALT_USB_HOST_HCCHAR10_EC_WIDTH 2
45466 /* The mask used to set the ALT_USB_HOST_HCCHAR10_EC register field value. */
45467 #define ALT_USB_HOST_HCCHAR10_EC_SET_MSK 0x00300000
45468 /* The mask used to clear the ALT_USB_HOST_HCCHAR10_EC register field value. */
45469 #define ALT_USB_HOST_HCCHAR10_EC_CLR_MSK 0xffcfffff
45470 /* The reset value of the ALT_USB_HOST_HCCHAR10_EC register field. */
45471 #define ALT_USB_HOST_HCCHAR10_EC_RESET 0x0
45472 /* Extracts the ALT_USB_HOST_HCCHAR10_EC field value from a register. */
45473 #define ALT_USB_HOST_HCCHAR10_EC_GET(value) (((value) & 0x00300000) >> 20)
45474 /* Produces a ALT_USB_HOST_HCCHAR10_EC register field value suitable for setting the register. */
45475 #define ALT_USB_HOST_HCCHAR10_EC_SET(value) (((value) << 20) & 0x00300000)
45476 
45477 /*
45478  * Field : devaddr
45479  *
45480  * Device Address (DevAddr)
45481  *
45482  * This field selects the specific device serving as the data source
45483  *
45484  * or sink.
45485  *
45486  * Field Access Macros:
45487  *
45488  */
45489 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */
45490 #define ALT_USB_HOST_HCCHAR10_DEVADDR_LSB 22
45491 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */
45492 #define ALT_USB_HOST_HCCHAR10_DEVADDR_MSB 28
45493 /* The width in bits of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */
45494 #define ALT_USB_HOST_HCCHAR10_DEVADDR_WIDTH 7
45495 /* The mask used to set the ALT_USB_HOST_HCCHAR10_DEVADDR register field value. */
45496 #define ALT_USB_HOST_HCCHAR10_DEVADDR_SET_MSK 0x1fc00000
45497 /* The mask used to clear the ALT_USB_HOST_HCCHAR10_DEVADDR register field value. */
45498 #define ALT_USB_HOST_HCCHAR10_DEVADDR_CLR_MSK 0xe03fffff
45499 /* The reset value of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */
45500 #define ALT_USB_HOST_HCCHAR10_DEVADDR_RESET 0x0
45501 /* Extracts the ALT_USB_HOST_HCCHAR10_DEVADDR field value from a register. */
45502 #define ALT_USB_HOST_HCCHAR10_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
45503 /* Produces a ALT_USB_HOST_HCCHAR10_DEVADDR register field value suitable for setting the register. */
45504 #define ALT_USB_HOST_HCCHAR10_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
45505 
45506 /*
45507  * Field : oddfrm
45508  *
45509  * Odd Frame (OddFrm)
45510  *
45511  * This field is set (reset) by the application to indicate that the OTG host must
45512  * perform
45513  *
45514  * a transfer in an odd (micro)frame. This field is applicable for only periodic
45515  *
45516  * (isochronous and interrupt) transactions.
45517  *
45518  * 1'b0: Even (micro)frame
45519  *
45520  * 1'b1: Odd (micro)frame
45521  *
45522  * Field Access Macros:
45523  *
45524  */
45525 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_ODDFRM register field. */
45526 #define ALT_USB_HOST_HCCHAR10_ODDFRM_LSB 29
45527 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_ODDFRM register field. */
45528 #define ALT_USB_HOST_HCCHAR10_ODDFRM_MSB 29
45529 /* The width in bits of the ALT_USB_HOST_HCCHAR10_ODDFRM register field. */
45530 #define ALT_USB_HOST_HCCHAR10_ODDFRM_WIDTH 1
45531 /* The mask used to set the ALT_USB_HOST_HCCHAR10_ODDFRM register field value. */
45532 #define ALT_USB_HOST_HCCHAR10_ODDFRM_SET_MSK 0x20000000
45533 /* The mask used to clear the ALT_USB_HOST_HCCHAR10_ODDFRM register field value. */
45534 #define ALT_USB_HOST_HCCHAR10_ODDFRM_CLR_MSK 0xdfffffff
45535 /* The reset value of the ALT_USB_HOST_HCCHAR10_ODDFRM register field. */
45536 #define ALT_USB_HOST_HCCHAR10_ODDFRM_RESET 0x0
45537 /* Extracts the ALT_USB_HOST_HCCHAR10_ODDFRM field value from a register. */
45538 #define ALT_USB_HOST_HCCHAR10_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
45539 /* Produces a ALT_USB_HOST_HCCHAR10_ODDFRM register field value suitable for setting the register. */
45540 #define ALT_USB_HOST_HCCHAR10_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
45541 
45542 /*
45543  * Field : chdis
45544  *
45545  * Channel Disable (ChDis)
45546  *
45547  * The application sets this bit to stop transmitting/receiving data
45548  *
45549  * on a channel, even before the transfer For that channel is
45550  *
45551  * complete. The application must wait For the Channel Disabled
45552  *
45553  * interrupt before treating the channel as disabled.
45554  *
45555  * Field Enumeration Values:
45556  *
45557  * Enum | Value | Description
45558  * :------------------------------------|:------|:----------------------------
45559  * ALT_USB_HOST_HCCHAR10_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
45560  * ALT_USB_HOST_HCCHAR10_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
45561  *
45562  * Field Access Macros:
45563  *
45564  */
45565 /*
45566  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHDIS
45567  *
45568  * Transmit/Recieve normal
45569  */
45570 #define ALT_USB_HOST_HCCHAR10_CHDIS_E_INACT 0x0
45571 /*
45572  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHDIS
45573  *
45574  * Stop transmitting/receiving
45575  */
45576 #define ALT_USB_HOST_HCCHAR10_CHDIS_E_ACT 0x1
45577 
45578 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */
45579 #define ALT_USB_HOST_HCCHAR10_CHDIS_LSB 30
45580 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */
45581 #define ALT_USB_HOST_HCCHAR10_CHDIS_MSB 30
45582 /* The width in bits of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */
45583 #define ALT_USB_HOST_HCCHAR10_CHDIS_WIDTH 1
45584 /* The mask used to set the ALT_USB_HOST_HCCHAR10_CHDIS register field value. */
45585 #define ALT_USB_HOST_HCCHAR10_CHDIS_SET_MSK 0x40000000
45586 /* The mask used to clear the ALT_USB_HOST_HCCHAR10_CHDIS register field value. */
45587 #define ALT_USB_HOST_HCCHAR10_CHDIS_CLR_MSK 0xbfffffff
45588 /* The reset value of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */
45589 #define ALT_USB_HOST_HCCHAR10_CHDIS_RESET 0x0
45590 /* Extracts the ALT_USB_HOST_HCCHAR10_CHDIS field value from a register. */
45591 #define ALT_USB_HOST_HCCHAR10_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
45592 /* Produces a ALT_USB_HOST_HCCHAR10_CHDIS register field value suitable for setting the register. */
45593 #define ALT_USB_HOST_HCCHAR10_CHDIS_SET(value) (((value) << 30) & 0x40000000)
45594 
45595 /*
45596  * Field : chena
45597  *
45598  * Channel Enable (ChEna)
45599  *
45600  * When Scatter/Gather mode is enabled
45601  *
45602  * 1'b0: Indicates that the descriptor structure is not yet ready.
45603  *
45604  * 1'b1: Indicates that the descriptor structure and data buffer with
45605  *
45606  * data is setup and this channel can access the descriptor.
45607  *
45608  * When Scatter/Gather mode is disabled
45609  *
45610  * This field is set by the application and cleared by the OTG host.
45611  *
45612  * 1'b0: Channel disabled
45613  *
45614  * 1'b1: Channel enabled
45615  *
45616  * Field Enumeration Values:
45617  *
45618  * Enum | Value | Description
45619  * :------------------------------------|:------|:-------------------------------------------------
45620  * ALT_USB_HOST_HCCHAR10_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
45621  * : | | yet ready
45622  * ALT_USB_HOST_HCCHAR10_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
45623  * : | | data buffer with data is setup and this
45624  * : | | channel can access the descriptor
45625  *
45626  * Field Access Macros:
45627  *
45628  */
45629 /*
45630  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHENA
45631  *
45632  * Indicates that the descriptor structure is not yet ready
45633  */
45634 #define ALT_USB_HOST_HCCHAR10_CHENA_E_INACT 0x0
45635 /*
45636  * Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHENA
45637  *
45638  * Indicates that the descriptor structure and data buffer with data is
45639  * setup and this channel can access the descriptor
45640  */
45641 #define ALT_USB_HOST_HCCHAR10_CHENA_E_ACT 0x1
45642 
45643 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_CHENA register field. */
45644 #define ALT_USB_HOST_HCCHAR10_CHENA_LSB 31
45645 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_CHENA register field. */
45646 #define ALT_USB_HOST_HCCHAR10_CHENA_MSB 31
45647 /* The width in bits of the ALT_USB_HOST_HCCHAR10_CHENA register field. */
45648 #define ALT_USB_HOST_HCCHAR10_CHENA_WIDTH 1
45649 /* The mask used to set the ALT_USB_HOST_HCCHAR10_CHENA register field value. */
45650 #define ALT_USB_HOST_HCCHAR10_CHENA_SET_MSK 0x80000000
45651 /* The mask used to clear the ALT_USB_HOST_HCCHAR10_CHENA register field value. */
45652 #define ALT_USB_HOST_HCCHAR10_CHENA_CLR_MSK 0x7fffffff
45653 /* The reset value of the ALT_USB_HOST_HCCHAR10_CHENA register field. */
45654 #define ALT_USB_HOST_HCCHAR10_CHENA_RESET 0x0
45655 /* Extracts the ALT_USB_HOST_HCCHAR10_CHENA field value from a register. */
45656 #define ALT_USB_HOST_HCCHAR10_CHENA_GET(value) (((value) & 0x80000000) >> 31)
45657 /* Produces a ALT_USB_HOST_HCCHAR10_CHENA register field value suitable for setting the register. */
45658 #define ALT_USB_HOST_HCCHAR10_CHENA_SET(value) (((value) << 31) & 0x80000000)
45659 
45660 #ifndef __ASSEMBLY__
45661 /*
45662  * WARNING: The C register and register group struct declarations are provided for
45663  * convenience and illustrative purposes. They should, however, be used with
45664  * caution as the C language standard provides no guarantees about the alignment or
45665  * atomicity of device memory accesses. The recommended practice for writing
45666  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
45667  * alt_write_word() functions.
45668  *
45669  * The struct declaration for register ALT_USB_HOST_HCCHAR10.
45670  */
45671 struct ALT_USB_HOST_HCCHAR10_s
45672 {
45673  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR10_MPS */
45674  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR10_EPNUM */
45675  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR10_EPDIR */
45676  uint32_t : 1; /* *UNDEFINED* */
45677  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR10_LSPDDEV */
45678  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR10_EPTYPE */
45679  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR10_EC */
45680  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR10_DEVADDR */
45681  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR10_ODDFRM */
45682  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR10_CHDIS */
45683  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR10_CHENA */
45684 };
45685 
45686 /* The typedef declaration for register ALT_USB_HOST_HCCHAR10. */
45687 typedef volatile struct ALT_USB_HOST_HCCHAR10_s ALT_USB_HOST_HCCHAR10_t;
45688 #endif /* __ASSEMBLY__ */
45689 
45690 /* The reset value of the ALT_USB_HOST_HCCHAR10 register. */
45691 #define ALT_USB_HOST_HCCHAR10_RESET 0x00000000
45692 /* The byte offset of the ALT_USB_HOST_HCCHAR10 register from the beginning of the component. */
45693 #define ALT_USB_HOST_HCCHAR10_OFST 0x240
45694 /* The address of the ALT_USB_HOST_HCCHAR10 register. */
45695 #define ALT_USB_HOST_HCCHAR10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR10_OFST))
45696 
45697 /*
45698  * Register : hcsplt10
45699  *
45700  * Host Channel 10 Split Control Register
45701  *
45702  * Register Layout
45703  *
45704  * Bits | Access | Reset | Description
45705  * :--------|:-------|:------|:-------------------------------
45706  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT10_PRTADDR
45707  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT10_HUBADDR
45708  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT10_XACTPOS
45709  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT10_COMPSPLT
45710  * [30:17] | ??? | 0x0 | *UNDEFINED*
45711  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT10_SPLTENA
45712  *
45713  */
45714 /*
45715  * Field : prtaddr
45716  *
45717  * Port Address (PrtAddr)
45718  *
45719  * This field is the port number of the recipient transaction
45720  *
45721  * translator.
45722  *
45723  * Field Access Macros:
45724  *
45725  */
45726 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */
45727 #define ALT_USB_HOST_HCSPLT10_PRTADDR_LSB 0
45728 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */
45729 #define ALT_USB_HOST_HCSPLT10_PRTADDR_MSB 6
45730 /* The width in bits of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */
45731 #define ALT_USB_HOST_HCSPLT10_PRTADDR_WIDTH 7
45732 /* The mask used to set the ALT_USB_HOST_HCSPLT10_PRTADDR register field value. */
45733 #define ALT_USB_HOST_HCSPLT10_PRTADDR_SET_MSK 0x0000007f
45734 /* The mask used to clear the ALT_USB_HOST_HCSPLT10_PRTADDR register field value. */
45735 #define ALT_USB_HOST_HCSPLT10_PRTADDR_CLR_MSK 0xffffff80
45736 /* The reset value of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */
45737 #define ALT_USB_HOST_HCSPLT10_PRTADDR_RESET 0x0
45738 /* Extracts the ALT_USB_HOST_HCSPLT10_PRTADDR field value from a register. */
45739 #define ALT_USB_HOST_HCSPLT10_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
45740 /* Produces a ALT_USB_HOST_HCSPLT10_PRTADDR register field value suitable for setting the register. */
45741 #define ALT_USB_HOST_HCSPLT10_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
45742 
45743 /*
45744  * Field : hubaddr
45745  *
45746  * Hub Address (HubAddr)
45747  *
45748  * This field holds the device address of the transaction translator's
45749  *
45750  * hub.
45751  *
45752  * Field Access Macros:
45753  *
45754  */
45755 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */
45756 #define ALT_USB_HOST_HCSPLT10_HUBADDR_LSB 7
45757 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */
45758 #define ALT_USB_HOST_HCSPLT10_HUBADDR_MSB 13
45759 /* The width in bits of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */
45760 #define ALT_USB_HOST_HCSPLT10_HUBADDR_WIDTH 7
45761 /* The mask used to set the ALT_USB_HOST_HCSPLT10_HUBADDR register field value. */
45762 #define ALT_USB_HOST_HCSPLT10_HUBADDR_SET_MSK 0x00003f80
45763 /* The mask used to clear the ALT_USB_HOST_HCSPLT10_HUBADDR register field value. */
45764 #define ALT_USB_HOST_HCSPLT10_HUBADDR_CLR_MSK 0xffffc07f
45765 /* The reset value of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */
45766 #define ALT_USB_HOST_HCSPLT10_HUBADDR_RESET 0x0
45767 /* Extracts the ALT_USB_HOST_HCSPLT10_HUBADDR field value from a register. */
45768 #define ALT_USB_HOST_HCSPLT10_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
45769 /* Produces a ALT_USB_HOST_HCSPLT10_HUBADDR register field value suitable for setting the register. */
45770 #define ALT_USB_HOST_HCSPLT10_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
45771 
45772 /*
45773  * Field : xactpos
45774  *
45775  * Transaction Position (XactPos)
45776  *
45777  * This field is used to determine whether to send all, first, middle,
45778  *
45779  * or last payloads with each OUT transaction.
45780  *
45781  * 2'b11: All. This is the entire data payload is of this transaction
45782  *
45783  * (which is less than or equal to 188 bytes).
45784  *
45785  * 2'b10: Begin. This is the first data payload of this transaction
45786  *
45787  * (which is larger than 188 bytes).
45788  *
45789  * 2'b00: Mid. This is the middle payload of this transaction
45790  *
45791  * (which is larger than 188 bytes).
45792  *
45793  * 2'b01: End. This is the last payload of this transaction (which
45794  *
45795  * is larger than 188 bytes).
45796  *
45797  * Field Enumeration Values:
45798  *
45799  * Enum | Value | Description
45800  * :---------------------------------------|:------|:------------------------------------------------
45801  * ALT_USB_HOST_HCSPLT10_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
45802  * : | | transaction (which is larger than 188 bytes)
45803  * ALT_USB_HOST_HCSPLT10_XACTPOS_E_END | 0x1 | End. This is the last payload of this
45804  * : | | transaction (which is larger than 188 bytes)
45805  * ALT_USB_HOST_HCSPLT10_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
45806  * : | | transaction (which is larger than 188 bytes)
45807  * ALT_USB_HOST_HCSPLT10_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
45808  * : | | transaction (which is less than or equal to 188
45809  * : | | bytes)
45810  *
45811  * Field Access Macros:
45812  *
45813  */
45814 /*
45815  * Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS
45816  *
45817  * Mid. This is the middle payload of this transaction (which is larger than 188
45818  * bytes)
45819  */
45820 #define ALT_USB_HOST_HCSPLT10_XACTPOS_E_MIDDLE 0x0
45821 /*
45822  * Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS
45823  *
45824  * End. This is the last payload of this transaction (which is larger than 188
45825  * bytes)
45826  */
45827 #define ALT_USB_HOST_HCSPLT10_XACTPOS_E_END 0x1
45828 /*
45829  * Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS
45830  *
45831  * Begin. This is the first data payload of this transaction (which is larger than
45832  * 188 bytes)
45833  */
45834 #define ALT_USB_HOST_HCSPLT10_XACTPOS_E_BEGIN 0x2
45835 /*
45836  * Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS
45837  *
45838  * All. This is the entire data payload is of this transaction (which is less than
45839  * or equal to 188 bytes)
45840  */
45841 #define ALT_USB_HOST_HCSPLT10_XACTPOS_E_ALL 0x3
45842 
45843 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */
45844 #define ALT_USB_HOST_HCSPLT10_XACTPOS_LSB 14
45845 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */
45846 #define ALT_USB_HOST_HCSPLT10_XACTPOS_MSB 15
45847 /* The width in bits of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */
45848 #define ALT_USB_HOST_HCSPLT10_XACTPOS_WIDTH 2
45849 /* The mask used to set the ALT_USB_HOST_HCSPLT10_XACTPOS register field value. */
45850 #define ALT_USB_HOST_HCSPLT10_XACTPOS_SET_MSK 0x0000c000
45851 /* The mask used to clear the ALT_USB_HOST_HCSPLT10_XACTPOS register field value. */
45852 #define ALT_USB_HOST_HCSPLT10_XACTPOS_CLR_MSK 0xffff3fff
45853 /* The reset value of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */
45854 #define ALT_USB_HOST_HCSPLT10_XACTPOS_RESET 0x0
45855 /* Extracts the ALT_USB_HOST_HCSPLT10_XACTPOS field value from a register. */
45856 #define ALT_USB_HOST_HCSPLT10_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
45857 /* Produces a ALT_USB_HOST_HCSPLT10_XACTPOS register field value suitable for setting the register. */
45858 #define ALT_USB_HOST_HCSPLT10_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
45859 
45860 /*
45861  * Field : compsplt
45862  *
45863  * Do Complete Split (CompSplt)
45864  *
45865  * The application sets this field to request the OTG host to perform
45866  *
45867  * a complete split transaction.
45868  *
45869  * Field Enumeration Values:
45870  *
45871  * Enum | Value | Description
45872  * :-----------------------------------------|:------|:---------------------
45873  * ALT_USB_HOST_HCSPLT10_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
45874  * ALT_USB_HOST_HCSPLT10_COMPSPLT_E_SPLIT | 0x1 | Split transaction
45875  *
45876  * Field Access Macros:
45877  *
45878  */
45879 /*
45880  * Enumerated value for register field ALT_USB_HOST_HCSPLT10_COMPSPLT
45881  *
45882  * No split transaction
45883  */
45884 #define ALT_USB_HOST_HCSPLT10_COMPSPLT_E_NOSPLIT 0x0
45885 /*
45886  * Enumerated value for register field ALT_USB_HOST_HCSPLT10_COMPSPLT
45887  *
45888  * Split transaction
45889  */
45890 #define ALT_USB_HOST_HCSPLT10_COMPSPLT_E_SPLIT 0x1
45891 
45892 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */
45893 #define ALT_USB_HOST_HCSPLT10_COMPSPLT_LSB 16
45894 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */
45895 #define ALT_USB_HOST_HCSPLT10_COMPSPLT_MSB 16
45896 /* The width in bits of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */
45897 #define ALT_USB_HOST_HCSPLT10_COMPSPLT_WIDTH 1
45898 /* The mask used to set the ALT_USB_HOST_HCSPLT10_COMPSPLT register field value. */
45899 #define ALT_USB_HOST_HCSPLT10_COMPSPLT_SET_MSK 0x00010000
45900 /* The mask used to clear the ALT_USB_HOST_HCSPLT10_COMPSPLT register field value. */
45901 #define ALT_USB_HOST_HCSPLT10_COMPSPLT_CLR_MSK 0xfffeffff
45902 /* The reset value of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */
45903 #define ALT_USB_HOST_HCSPLT10_COMPSPLT_RESET 0x0
45904 /* Extracts the ALT_USB_HOST_HCSPLT10_COMPSPLT field value from a register. */
45905 #define ALT_USB_HOST_HCSPLT10_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
45906 /* Produces a ALT_USB_HOST_HCSPLT10_COMPSPLT register field value suitable for setting the register. */
45907 #define ALT_USB_HOST_HCSPLT10_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
45908 
45909 /*
45910  * Field : spltena
45911  *
45912  * Split Enable (SpltEna)
45913  *
45914  * The application sets this field to indicate that this channel is
45915  *
45916  * enabled to perform split transactions.
45917  *
45918  * Field Enumeration Values:
45919  *
45920  * Enum | Value | Description
45921  * :-------------------------------------|:------|:------------------
45922  * ALT_USB_HOST_HCSPLT10_SPLTENA_E_DISD | 0x0 | Split not enabled
45923  * ALT_USB_HOST_HCSPLT10_SPLTENA_E_END | 0x1 | Split enabled
45924  *
45925  * Field Access Macros:
45926  *
45927  */
45928 /*
45929  * Enumerated value for register field ALT_USB_HOST_HCSPLT10_SPLTENA
45930  *
45931  * Split not enabled
45932  */
45933 #define ALT_USB_HOST_HCSPLT10_SPLTENA_E_DISD 0x0
45934 /*
45935  * Enumerated value for register field ALT_USB_HOST_HCSPLT10_SPLTENA
45936  *
45937  * Split enabled
45938  */
45939 #define ALT_USB_HOST_HCSPLT10_SPLTENA_E_END 0x1
45940 
45941 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */
45942 #define ALT_USB_HOST_HCSPLT10_SPLTENA_LSB 31
45943 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */
45944 #define ALT_USB_HOST_HCSPLT10_SPLTENA_MSB 31
45945 /* The width in bits of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */
45946 #define ALT_USB_HOST_HCSPLT10_SPLTENA_WIDTH 1
45947 /* The mask used to set the ALT_USB_HOST_HCSPLT10_SPLTENA register field value. */
45948 #define ALT_USB_HOST_HCSPLT10_SPLTENA_SET_MSK 0x80000000
45949 /* The mask used to clear the ALT_USB_HOST_HCSPLT10_SPLTENA register field value. */
45950 #define ALT_USB_HOST_HCSPLT10_SPLTENA_CLR_MSK 0x7fffffff
45951 /* The reset value of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */
45952 #define ALT_USB_HOST_HCSPLT10_SPLTENA_RESET 0x0
45953 /* Extracts the ALT_USB_HOST_HCSPLT10_SPLTENA field value from a register. */
45954 #define ALT_USB_HOST_HCSPLT10_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
45955 /* Produces a ALT_USB_HOST_HCSPLT10_SPLTENA register field value suitable for setting the register. */
45956 #define ALT_USB_HOST_HCSPLT10_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
45957 
45958 #ifndef __ASSEMBLY__
45959 /*
45960  * WARNING: The C register and register group struct declarations are provided for
45961  * convenience and illustrative purposes. They should, however, be used with
45962  * caution as the C language standard provides no guarantees about the alignment or
45963  * atomicity of device memory accesses. The recommended practice for writing
45964  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
45965  * alt_write_word() functions.
45966  *
45967  * The struct declaration for register ALT_USB_HOST_HCSPLT10.
45968  */
45969 struct ALT_USB_HOST_HCSPLT10_s
45970 {
45971  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT10_PRTADDR */
45972  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT10_HUBADDR */
45973  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT10_XACTPOS */
45974  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT10_COMPSPLT */
45975  uint32_t : 14; /* *UNDEFINED* */
45976  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT10_SPLTENA */
45977 };
45978 
45979 /* The typedef declaration for register ALT_USB_HOST_HCSPLT10. */
45980 typedef volatile struct ALT_USB_HOST_HCSPLT10_s ALT_USB_HOST_HCSPLT10_t;
45981 #endif /* __ASSEMBLY__ */
45982 
45983 /* The reset value of the ALT_USB_HOST_HCSPLT10 register. */
45984 #define ALT_USB_HOST_HCSPLT10_RESET 0x00000000
45985 /* The byte offset of the ALT_USB_HOST_HCSPLT10 register from the beginning of the component. */
45986 #define ALT_USB_HOST_HCSPLT10_OFST 0x244
45987 /* The address of the ALT_USB_HOST_HCSPLT10 register. */
45988 #define ALT_USB_HOST_HCSPLT10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT10_OFST))
45989 
45990 /*
45991  * Register : hcint10
45992  *
45993  * Host Channel 10 Interrupt Register
45994  *
45995  * Register Layout
45996  *
45997  * Bits | Access | Reset | Description
45998  * :--------|:-------|:------|:---------------------------------------
45999  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT10_XFERCOMPL
46000  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT10_CHHLTD
46001  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT10_AHBERR
46002  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT10_STALL
46003  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT10_NAK
46004  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT10_ACK
46005  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT10_NYET
46006  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT10_XACTERR
46007  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT10_BBLERR
46008  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT10_FRMOVRUN
46009  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT10_DATATGLERR
46010  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT10_BNAINTR
46011  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT10_XCS_XACT_ERR
46012  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR
46013  * [31:14] | ??? | 0x0 | *UNDEFINED*
46014  *
46015  */
46016 /*
46017  * Field : xfercompl
46018  *
46019  * Transfer Completed (XferCompl)
46020  *
46021  * Transfer completed normally without any errors.This bit can be set only by the
46022  * core and the application should write 1 to clear it.
46023  *
46024  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
46025  *
46026  * completed with IOC bit set in its descriptor.
46027  *
46028  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
46029  * without
46030  *
46031  * any errors.
46032  *
46033  * Field Enumeration Values:
46034  *
46035  * Enum | Value | Description
46036  * :---------------------------------------|:------|:-----------------------------------------------
46037  * ALT_USB_HOST_HCINT10_XFERCOMPL_E_INACT | 0x0 | No transfer
46038  * ALT_USB_HOST_HCINT10_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
46039  *
46040  * Field Access Macros:
46041  *
46042  */
46043 /*
46044  * Enumerated value for register field ALT_USB_HOST_HCINT10_XFERCOMPL
46045  *
46046  * No transfer
46047  */
46048 #define ALT_USB_HOST_HCINT10_XFERCOMPL_E_INACT 0x0
46049 /*
46050  * Enumerated value for register field ALT_USB_HOST_HCINT10_XFERCOMPL
46051  *
46052  * Transfer completed normally without any errors
46053  */
46054 #define ALT_USB_HOST_HCINT10_XFERCOMPL_E_ACT 0x1
46055 
46056 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */
46057 #define ALT_USB_HOST_HCINT10_XFERCOMPL_LSB 0
46058 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */
46059 #define ALT_USB_HOST_HCINT10_XFERCOMPL_MSB 0
46060 /* The width in bits of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */
46061 #define ALT_USB_HOST_HCINT10_XFERCOMPL_WIDTH 1
46062 /* The mask used to set the ALT_USB_HOST_HCINT10_XFERCOMPL register field value. */
46063 #define ALT_USB_HOST_HCINT10_XFERCOMPL_SET_MSK 0x00000001
46064 /* The mask used to clear the ALT_USB_HOST_HCINT10_XFERCOMPL register field value. */
46065 #define ALT_USB_HOST_HCINT10_XFERCOMPL_CLR_MSK 0xfffffffe
46066 /* The reset value of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */
46067 #define ALT_USB_HOST_HCINT10_XFERCOMPL_RESET 0x0
46068 /* Extracts the ALT_USB_HOST_HCINT10_XFERCOMPL field value from a register. */
46069 #define ALT_USB_HOST_HCINT10_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
46070 /* Produces a ALT_USB_HOST_HCINT10_XFERCOMPL register field value suitable for setting the register. */
46071 #define ALT_USB_HOST_HCINT10_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
46072 
46073 /*
46074  * Field : chhltd
46075  *
46076  * Channel Halted (ChHltd)
46077  *
46078  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
46079  * either because of any USB transaction error or in response to disable request by
46080  * the application or because of a completed transfer.
46081  *
46082  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
46083  * the following
46084  *
46085  * . EOL being set in descriptor
46086  *
46087  * . AHB error
46088  *
46089  * . Excessive transaction errors
46090  *
46091  * . Babble
46092  *
46093  * . Stall
46094  *
46095  * Field Enumeration Values:
46096  *
46097  * Enum | Value | Description
46098  * :------------------------------------|:------|:-------------------
46099  * ALT_USB_HOST_HCINT10_CHHLTD_E_INACT | 0x0 | Channel not halted
46100  * ALT_USB_HOST_HCINT10_CHHLTD_E_ACT | 0x1 | Channel Halted
46101  *
46102  * Field Access Macros:
46103  *
46104  */
46105 /*
46106  * Enumerated value for register field ALT_USB_HOST_HCINT10_CHHLTD
46107  *
46108  * Channel not halted
46109  */
46110 #define ALT_USB_HOST_HCINT10_CHHLTD_E_INACT 0x0
46111 /*
46112  * Enumerated value for register field ALT_USB_HOST_HCINT10_CHHLTD
46113  *
46114  * Channel Halted
46115  */
46116 #define ALT_USB_HOST_HCINT10_CHHLTD_E_ACT 0x1
46117 
46118 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_CHHLTD register field. */
46119 #define ALT_USB_HOST_HCINT10_CHHLTD_LSB 1
46120 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_CHHLTD register field. */
46121 #define ALT_USB_HOST_HCINT10_CHHLTD_MSB 1
46122 /* The width in bits of the ALT_USB_HOST_HCINT10_CHHLTD register field. */
46123 #define ALT_USB_HOST_HCINT10_CHHLTD_WIDTH 1
46124 /* The mask used to set the ALT_USB_HOST_HCINT10_CHHLTD register field value. */
46125 #define ALT_USB_HOST_HCINT10_CHHLTD_SET_MSK 0x00000002
46126 /* The mask used to clear the ALT_USB_HOST_HCINT10_CHHLTD register field value. */
46127 #define ALT_USB_HOST_HCINT10_CHHLTD_CLR_MSK 0xfffffffd
46128 /* The reset value of the ALT_USB_HOST_HCINT10_CHHLTD register field. */
46129 #define ALT_USB_HOST_HCINT10_CHHLTD_RESET 0x0
46130 /* Extracts the ALT_USB_HOST_HCINT10_CHHLTD field value from a register. */
46131 #define ALT_USB_HOST_HCINT10_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
46132 /* Produces a ALT_USB_HOST_HCINT10_CHHLTD register field value suitable for setting the register. */
46133 #define ALT_USB_HOST_HCINT10_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
46134 
46135 /*
46136  * Field : ahberr
46137  *
46138  * AHB Error (AHBErr)
46139  *
46140  * This is generated only in Internal DMA mode when there is an
46141  *
46142  * AHB error during AHB read/write. The application can read the
46143  *
46144  * corresponding channel's DMA address register to get the error
46145  *
46146  * address.
46147  *
46148  * Field Enumeration Values:
46149  *
46150  * Enum | Value | Description
46151  * :------------------------------------|:------|:--------------------------------
46152  * ALT_USB_HOST_HCINT10_AHBERR_E_INACT | 0x0 | No AHB error
46153  * ALT_USB_HOST_HCINT10_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
46154  *
46155  * Field Access Macros:
46156  *
46157  */
46158 /*
46159  * Enumerated value for register field ALT_USB_HOST_HCINT10_AHBERR
46160  *
46161  * No AHB error
46162  */
46163 #define ALT_USB_HOST_HCINT10_AHBERR_E_INACT 0x0
46164 /*
46165  * Enumerated value for register field ALT_USB_HOST_HCINT10_AHBERR
46166  *
46167  * AHB error during AHB read/write
46168  */
46169 #define ALT_USB_HOST_HCINT10_AHBERR_E_ACT 0x1
46170 
46171 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_AHBERR register field. */
46172 #define ALT_USB_HOST_HCINT10_AHBERR_LSB 2
46173 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_AHBERR register field. */
46174 #define ALT_USB_HOST_HCINT10_AHBERR_MSB 2
46175 /* The width in bits of the ALT_USB_HOST_HCINT10_AHBERR register field. */
46176 #define ALT_USB_HOST_HCINT10_AHBERR_WIDTH 1
46177 /* The mask used to set the ALT_USB_HOST_HCINT10_AHBERR register field value. */
46178 #define ALT_USB_HOST_HCINT10_AHBERR_SET_MSK 0x00000004
46179 /* The mask used to clear the ALT_USB_HOST_HCINT10_AHBERR register field value. */
46180 #define ALT_USB_HOST_HCINT10_AHBERR_CLR_MSK 0xfffffffb
46181 /* The reset value of the ALT_USB_HOST_HCINT10_AHBERR register field. */
46182 #define ALT_USB_HOST_HCINT10_AHBERR_RESET 0x0
46183 /* Extracts the ALT_USB_HOST_HCINT10_AHBERR field value from a register. */
46184 #define ALT_USB_HOST_HCINT10_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
46185 /* Produces a ALT_USB_HOST_HCINT10_AHBERR register field value suitable for setting the register. */
46186 #define ALT_USB_HOST_HCINT10_AHBERR_SET(value) (((value) << 2) & 0x00000004)
46187 
46188 /*
46189  * Field : stall
46190  *
46191  * STALL Response Received Interrupt (STALL)
46192  *
46193  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
46194  *
46195  * in the core.This bit can be set only by the core and the application should
46196  * write 1 to clear
46197  *
46198  * it.
46199  *
46200  * Field Enumeration Values:
46201  *
46202  * Enum | Value | Description
46203  * :-----------------------------------|:------|:-------------------
46204  * ALT_USB_HOST_HCINT10_STALL_E_INACT | 0x0 | No Stall Interrupt
46205  * ALT_USB_HOST_HCINT10_STALL_E_ACT | 0x1 | Stall Interrupt
46206  *
46207  * Field Access Macros:
46208  *
46209  */
46210 /*
46211  * Enumerated value for register field ALT_USB_HOST_HCINT10_STALL
46212  *
46213  * No Stall Interrupt
46214  */
46215 #define ALT_USB_HOST_HCINT10_STALL_E_INACT 0x0
46216 /*
46217  * Enumerated value for register field ALT_USB_HOST_HCINT10_STALL
46218  *
46219  * Stall Interrupt
46220  */
46221 #define ALT_USB_HOST_HCINT10_STALL_E_ACT 0x1
46222 
46223 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_STALL register field. */
46224 #define ALT_USB_HOST_HCINT10_STALL_LSB 3
46225 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_STALL register field. */
46226 #define ALT_USB_HOST_HCINT10_STALL_MSB 3
46227 /* The width in bits of the ALT_USB_HOST_HCINT10_STALL register field. */
46228 #define ALT_USB_HOST_HCINT10_STALL_WIDTH 1
46229 /* The mask used to set the ALT_USB_HOST_HCINT10_STALL register field value. */
46230 #define ALT_USB_HOST_HCINT10_STALL_SET_MSK 0x00000008
46231 /* The mask used to clear the ALT_USB_HOST_HCINT10_STALL register field value. */
46232 #define ALT_USB_HOST_HCINT10_STALL_CLR_MSK 0xfffffff7
46233 /* The reset value of the ALT_USB_HOST_HCINT10_STALL register field. */
46234 #define ALT_USB_HOST_HCINT10_STALL_RESET 0x0
46235 /* Extracts the ALT_USB_HOST_HCINT10_STALL field value from a register. */
46236 #define ALT_USB_HOST_HCINT10_STALL_GET(value) (((value) & 0x00000008) >> 3)
46237 /* Produces a ALT_USB_HOST_HCINT10_STALL register field value suitable for setting the register. */
46238 #define ALT_USB_HOST_HCINT10_STALL_SET(value) (((value) << 3) & 0x00000008)
46239 
46240 /*
46241  * Field : nak
46242  *
46243  * NAK Response Received Interrupt (NAK)
46244  *
46245  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
46246  *
46247  * in the core.This bit can be set only by the core and the application should
46248  * write 1 to clear
46249  *
46250  * it.
46251  *
46252  * Field Enumeration Values:
46253  *
46254  * Enum | Value | Description
46255  * :---------------------------------|:------|:-----------------------------------
46256  * ALT_USB_HOST_HCINT10_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
46257  * ALT_USB_HOST_HCINT10_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
46258  *
46259  * Field Access Macros:
46260  *
46261  */
46262 /*
46263  * Enumerated value for register field ALT_USB_HOST_HCINT10_NAK
46264  *
46265  * No NAK Response Received Interrupt
46266  */
46267 #define ALT_USB_HOST_HCINT10_NAK_E_INACT 0x0
46268 /*
46269  * Enumerated value for register field ALT_USB_HOST_HCINT10_NAK
46270  *
46271  * NAK Response Received Interrupt
46272  */
46273 #define ALT_USB_HOST_HCINT10_NAK_E_ACT 0x1
46274 
46275 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_NAK register field. */
46276 #define ALT_USB_HOST_HCINT10_NAK_LSB 4
46277 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_NAK register field. */
46278 #define ALT_USB_HOST_HCINT10_NAK_MSB 4
46279 /* The width in bits of the ALT_USB_HOST_HCINT10_NAK register field. */
46280 #define ALT_USB_HOST_HCINT10_NAK_WIDTH 1
46281 /* The mask used to set the ALT_USB_HOST_HCINT10_NAK register field value. */
46282 #define ALT_USB_HOST_HCINT10_NAK_SET_MSK 0x00000010
46283 /* The mask used to clear the ALT_USB_HOST_HCINT10_NAK register field value. */
46284 #define ALT_USB_HOST_HCINT10_NAK_CLR_MSK 0xffffffef
46285 /* The reset value of the ALT_USB_HOST_HCINT10_NAK register field. */
46286 #define ALT_USB_HOST_HCINT10_NAK_RESET 0x0
46287 /* Extracts the ALT_USB_HOST_HCINT10_NAK field value from a register. */
46288 #define ALT_USB_HOST_HCINT10_NAK_GET(value) (((value) & 0x00000010) >> 4)
46289 /* Produces a ALT_USB_HOST_HCINT10_NAK register field value suitable for setting the register. */
46290 #define ALT_USB_HOST_HCINT10_NAK_SET(value) (((value) << 4) & 0x00000010)
46291 
46292 /*
46293  * Field : ack
46294  *
46295  * ACK Response Received/Transmitted Interrupt (ACK)
46296  *
46297  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
46298  *
46299  * in the core.This bit can be set only by the core and the application should
46300  * write 1 to clear
46301  *
46302  * it.
46303  *
46304  * Field Enumeration Values:
46305  *
46306  * Enum | Value | Description
46307  * :---------------------------------|:------|:-----------------------------------------------
46308  * ALT_USB_HOST_HCINT10_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
46309  * ALT_USB_HOST_HCINT10_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
46310  *
46311  * Field Access Macros:
46312  *
46313  */
46314 /*
46315  * Enumerated value for register field ALT_USB_HOST_HCINT10_ACK
46316  *
46317  * No ACK Response Received Transmitted Interrupt
46318  */
46319 #define ALT_USB_HOST_HCINT10_ACK_E_INACT 0x0
46320 /*
46321  * Enumerated value for register field ALT_USB_HOST_HCINT10_ACK
46322  *
46323  * ACK Response Received Transmitted Interrup
46324  */
46325 #define ALT_USB_HOST_HCINT10_ACK_E_ACT 0x1
46326 
46327 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_ACK register field. */
46328 #define ALT_USB_HOST_HCINT10_ACK_LSB 5
46329 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_ACK register field. */
46330 #define ALT_USB_HOST_HCINT10_ACK_MSB 5
46331 /* The width in bits of the ALT_USB_HOST_HCINT10_ACK register field. */
46332 #define ALT_USB_HOST_HCINT10_ACK_WIDTH 1
46333 /* The mask used to set the ALT_USB_HOST_HCINT10_ACK register field value. */
46334 #define ALT_USB_HOST_HCINT10_ACK_SET_MSK 0x00000020
46335 /* The mask used to clear the ALT_USB_HOST_HCINT10_ACK register field value. */
46336 #define ALT_USB_HOST_HCINT10_ACK_CLR_MSK 0xffffffdf
46337 /* The reset value of the ALT_USB_HOST_HCINT10_ACK register field. */
46338 #define ALT_USB_HOST_HCINT10_ACK_RESET 0x0
46339 /* Extracts the ALT_USB_HOST_HCINT10_ACK field value from a register. */
46340 #define ALT_USB_HOST_HCINT10_ACK_GET(value) (((value) & 0x00000020) >> 5)
46341 /* Produces a ALT_USB_HOST_HCINT10_ACK register field value suitable for setting the register. */
46342 #define ALT_USB_HOST_HCINT10_ACK_SET(value) (((value) << 5) & 0x00000020)
46343 
46344 /*
46345  * Field : nyet
46346  *
46347  * NYET Response Received Interrupt (NYET)
46348  *
46349  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
46350  *
46351  * in the core.This bit can be set only by the core and the application should
46352  * write 1 to clear
46353  *
46354  * it.
46355  *
46356  * Field Enumeration Values:
46357  *
46358  * Enum | Value | Description
46359  * :----------------------------------|:------|:------------------------------------
46360  * ALT_USB_HOST_HCINT10_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
46361  * ALT_USB_HOST_HCINT10_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
46362  *
46363  * Field Access Macros:
46364  *
46365  */
46366 /*
46367  * Enumerated value for register field ALT_USB_HOST_HCINT10_NYET
46368  *
46369  * No NYET Response Received Interrupt
46370  */
46371 #define ALT_USB_HOST_HCINT10_NYET_E_INACT 0x0
46372 /*
46373  * Enumerated value for register field ALT_USB_HOST_HCINT10_NYET
46374  *
46375  * NYET Response Received Interrupt
46376  */
46377 #define ALT_USB_HOST_HCINT10_NYET_E_ACT 0x1
46378 
46379 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_NYET register field. */
46380 #define ALT_USB_HOST_HCINT10_NYET_LSB 6
46381 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_NYET register field. */
46382 #define ALT_USB_HOST_HCINT10_NYET_MSB 6
46383 /* The width in bits of the ALT_USB_HOST_HCINT10_NYET register field. */
46384 #define ALT_USB_HOST_HCINT10_NYET_WIDTH 1
46385 /* The mask used to set the ALT_USB_HOST_HCINT10_NYET register field value. */
46386 #define ALT_USB_HOST_HCINT10_NYET_SET_MSK 0x00000040
46387 /* The mask used to clear the ALT_USB_HOST_HCINT10_NYET register field value. */
46388 #define ALT_USB_HOST_HCINT10_NYET_CLR_MSK 0xffffffbf
46389 /* The reset value of the ALT_USB_HOST_HCINT10_NYET register field. */
46390 #define ALT_USB_HOST_HCINT10_NYET_RESET 0x0
46391 /* Extracts the ALT_USB_HOST_HCINT10_NYET field value from a register. */
46392 #define ALT_USB_HOST_HCINT10_NYET_GET(value) (((value) & 0x00000040) >> 6)
46393 /* Produces a ALT_USB_HOST_HCINT10_NYET register field value suitable for setting the register. */
46394 #define ALT_USB_HOST_HCINT10_NYET_SET(value) (((value) << 6) & 0x00000040)
46395 
46396 /*
46397  * Field : xacterr
46398  *
46399  * Transaction Error (XactErr)
46400  *
46401  * Indicates one of the following errors occurred on the USB.
46402  *
46403  * CRC check failure
46404  *
46405  * Timeout
46406  *
46407  * Bit stuff error
46408  *
46409  * False EOP
46410  *
46411  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
46412  *
46413  * in the core.This bit can be set only by the core and the application should
46414  * write 1 to clear
46415  *
46416  * it.
46417  *
46418  * Field Enumeration Values:
46419  *
46420  * Enum | Value | Description
46421  * :-------------------------------------|:------|:---------------------
46422  * ALT_USB_HOST_HCINT10_XACTERR_E_INACT | 0x0 | No Transaction Error
46423  * ALT_USB_HOST_HCINT10_XACTERR_E_ACT | 0x1 | Transaction Error
46424  *
46425  * Field Access Macros:
46426  *
46427  */
46428 /*
46429  * Enumerated value for register field ALT_USB_HOST_HCINT10_XACTERR
46430  *
46431  * No Transaction Error
46432  */
46433 #define ALT_USB_HOST_HCINT10_XACTERR_E_INACT 0x0
46434 /*
46435  * Enumerated value for register field ALT_USB_HOST_HCINT10_XACTERR
46436  *
46437  * Transaction Error
46438  */
46439 #define ALT_USB_HOST_HCINT10_XACTERR_E_ACT 0x1
46440 
46441 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_XACTERR register field. */
46442 #define ALT_USB_HOST_HCINT10_XACTERR_LSB 7
46443 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_XACTERR register field. */
46444 #define ALT_USB_HOST_HCINT10_XACTERR_MSB 7
46445 /* The width in bits of the ALT_USB_HOST_HCINT10_XACTERR register field. */
46446 #define ALT_USB_HOST_HCINT10_XACTERR_WIDTH 1
46447 /* The mask used to set the ALT_USB_HOST_HCINT10_XACTERR register field value. */
46448 #define ALT_USB_HOST_HCINT10_XACTERR_SET_MSK 0x00000080
46449 /* The mask used to clear the ALT_USB_HOST_HCINT10_XACTERR register field value. */
46450 #define ALT_USB_HOST_HCINT10_XACTERR_CLR_MSK 0xffffff7f
46451 /* The reset value of the ALT_USB_HOST_HCINT10_XACTERR register field. */
46452 #define ALT_USB_HOST_HCINT10_XACTERR_RESET 0x0
46453 /* Extracts the ALT_USB_HOST_HCINT10_XACTERR field value from a register. */
46454 #define ALT_USB_HOST_HCINT10_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
46455 /* Produces a ALT_USB_HOST_HCINT10_XACTERR register field value suitable for setting the register. */
46456 #define ALT_USB_HOST_HCINT10_XACTERR_SET(value) (((value) << 7) & 0x00000080)
46457 
46458 /*
46459  * Field : bblerr
46460  *
46461  * Babble Error (BblErr)
46462  *
46463  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
46464  *
46465  * in the core..This bit can be set only by the core and the application should
46466  * write 1 to clear
46467  *
46468  * it.
46469  *
46470  * Field Enumeration Values:
46471  *
46472  * Enum | Value | Description
46473  * :------------------------------------|:------|:----------------
46474  * ALT_USB_HOST_HCINT10_BBLERR_E_INACT | 0x0 | No Babble Error
46475  * ALT_USB_HOST_HCINT10_BBLERR_E_ACT | 0x1 | Babble Error
46476  *
46477  * Field Access Macros:
46478  *
46479  */
46480 /*
46481  * Enumerated value for register field ALT_USB_HOST_HCINT10_BBLERR
46482  *
46483  * No Babble Error
46484  */
46485 #define ALT_USB_HOST_HCINT10_BBLERR_E_INACT 0x0
46486 /*
46487  * Enumerated value for register field ALT_USB_HOST_HCINT10_BBLERR
46488  *
46489  * Babble Error
46490  */
46491 #define ALT_USB_HOST_HCINT10_BBLERR_E_ACT 0x1
46492 
46493 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_BBLERR register field. */
46494 #define ALT_USB_HOST_HCINT10_BBLERR_LSB 8
46495 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_BBLERR register field. */
46496 #define ALT_USB_HOST_HCINT10_BBLERR_MSB 8
46497 /* The width in bits of the ALT_USB_HOST_HCINT10_BBLERR register field. */
46498 #define ALT_USB_HOST_HCINT10_BBLERR_WIDTH 1
46499 /* The mask used to set the ALT_USB_HOST_HCINT10_BBLERR register field value. */
46500 #define ALT_USB_HOST_HCINT10_BBLERR_SET_MSK 0x00000100
46501 /* The mask used to clear the ALT_USB_HOST_HCINT10_BBLERR register field value. */
46502 #define ALT_USB_HOST_HCINT10_BBLERR_CLR_MSK 0xfffffeff
46503 /* The reset value of the ALT_USB_HOST_HCINT10_BBLERR register field. */
46504 #define ALT_USB_HOST_HCINT10_BBLERR_RESET 0x0
46505 /* Extracts the ALT_USB_HOST_HCINT10_BBLERR field value from a register. */
46506 #define ALT_USB_HOST_HCINT10_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
46507 /* Produces a ALT_USB_HOST_HCINT10_BBLERR register field value suitable for setting the register. */
46508 #define ALT_USB_HOST_HCINT10_BBLERR_SET(value) (((value) << 8) & 0x00000100)
46509 
46510 /*
46511  * Field : frmovrun
46512  *
46513  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
46514  * bit is masked
46515  *
46516  * in the core.This bit can be set only by the core and the application should
46517  * write 1 to clear
46518  *
46519  * it.
46520  *
46521  * Field Enumeration Values:
46522  *
46523  * Enum | Value | Description
46524  * :--------------------------------------|:------|:-----------------
46525  * ALT_USB_HOST_HCINT10_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
46526  * ALT_USB_HOST_HCINT10_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
46527  *
46528  * Field Access Macros:
46529  *
46530  */
46531 /*
46532  * Enumerated value for register field ALT_USB_HOST_HCINT10_FRMOVRUN
46533  *
46534  * No Frame Overrun
46535  */
46536 #define ALT_USB_HOST_HCINT10_FRMOVRUN_E_INACT 0x0
46537 /*
46538  * Enumerated value for register field ALT_USB_HOST_HCINT10_FRMOVRUN
46539  *
46540  * Frame Overrun
46541  */
46542 #define ALT_USB_HOST_HCINT10_FRMOVRUN_E_ACT 0x1
46543 
46544 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */
46545 #define ALT_USB_HOST_HCINT10_FRMOVRUN_LSB 9
46546 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */
46547 #define ALT_USB_HOST_HCINT10_FRMOVRUN_MSB 9
46548 /* The width in bits of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */
46549 #define ALT_USB_HOST_HCINT10_FRMOVRUN_WIDTH 1
46550 /* The mask used to set the ALT_USB_HOST_HCINT10_FRMOVRUN register field value. */
46551 #define ALT_USB_HOST_HCINT10_FRMOVRUN_SET_MSK 0x00000200
46552 /* The mask used to clear the ALT_USB_HOST_HCINT10_FRMOVRUN register field value. */
46553 #define ALT_USB_HOST_HCINT10_FRMOVRUN_CLR_MSK 0xfffffdff
46554 /* The reset value of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */
46555 #define ALT_USB_HOST_HCINT10_FRMOVRUN_RESET 0x0
46556 /* Extracts the ALT_USB_HOST_HCINT10_FRMOVRUN field value from a register. */
46557 #define ALT_USB_HOST_HCINT10_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
46558 /* Produces a ALT_USB_HOST_HCINT10_FRMOVRUN register field value suitable for setting the register. */
46559 #define ALT_USB_HOST_HCINT10_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
46560 
46561 /*
46562  * Field : datatglerr
46563  *
46564  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
46565  * application should write 1 to clear
46566  *
46567  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
46568  *
46569  * in the core.
46570  *
46571  * Field Enumeration Values:
46572  *
46573  * Enum | Value | Description
46574  * :----------------------------------------|:------|:---------------------
46575  * ALT_USB_HOST_HCINT10_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
46576  * ALT_USB_HOST_HCINT10_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
46577  *
46578  * Field Access Macros:
46579  *
46580  */
46581 /*
46582  * Enumerated value for register field ALT_USB_HOST_HCINT10_DATATGLERR
46583  *
46584  * No Data Toggle Error
46585  */
46586 #define ALT_USB_HOST_HCINT10_DATATGLERR_E_INACT 0x0
46587 /*
46588  * Enumerated value for register field ALT_USB_HOST_HCINT10_DATATGLERR
46589  *
46590  * Data Toggle Error
46591  */
46592 #define ALT_USB_HOST_HCINT10_DATATGLERR_E_ACT 0x1
46593 
46594 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */
46595 #define ALT_USB_HOST_HCINT10_DATATGLERR_LSB 10
46596 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */
46597 #define ALT_USB_HOST_HCINT10_DATATGLERR_MSB 10
46598 /* The width in bits of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */
46599 #define ALT_USB_HOST_HCINT10_DATATGLERR_WIDTH 1
46600 /* The mask used to set the ALT_USB_HOST_HCINT10_DATATGLERR register field value. */
46601 #define ALT_USB_HOST_HCINT10_DATATGLERR_SET_MSK 0x00000400
46602 /* The mask used to clear the ALT_USB_HOST_HCINT10_DATATGLERR register field value. */
46603 #define ALT_USB_HOST_HCINT10_DATATGLERR_CLR_MSK 0xfffffbff
46604 /* The reset value of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */
46605 #define ALT_USB_HOST_HCINT10_DATATGLERR_RESET 0x0
46606 /* Extracts the ALT_USB_HOST_HCINT10_DATATGLERR field value from a register. */
46607 #define ALT_USB_HOST_HCINT10_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
46608 /* Produces a ALT_USB_HOST_HCINT10_DATATGLERR register field value suitable for setting the register. */
46609 #define ALT_USB_HOST_HCINT10_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
46610 
46611 /*
46612  * Field : bnaintr
46613  *
46614  * BNA (Buffer Not Available) Interrupt (BNAIntr)
46615  *
46616  * This bit is valid only when Scatter/Gather DMA mode is enabled.
46617  *
46618  * The core generates this interrupt when the descriptor accessed
46619  *
46620  * is not ready for the Core to process. BNA will not be generated
46621  *
46622  * for Isochronous channels.
46623  *
46624  * For non Scatter/Gather DMA mode, this bit is reserved.
46625  *
46626  * Field Enumeration Values:
46627  *
46628  * Enum | Value | Description
46629  * :-------------------------------------|:------|:-----------------
46630  * ALT_USB_HOST_HCINT10_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
46631  * ALT_USB_HOST_HCINT10_BNAINTR_E_ACT | 0x1 | BNA Interrupt
46632  *
46633  * Field Access Macros:
46634  *
46635  */
46636 /*
46637  * Enumerated value for register field ALT_USB_HOST_HCINT10_BNAINTR
46638  *
46639  * No BNA Interrupt
46640  */
46641 #define ALT_USB_HOST_HCINT10_BNAINTR_E_INACT 0x0
46642 /*
46643  * Enumerated value for register field ALT_USB_HOST_HCINT10_BNAINTR
46644  *
46645  * BNA Interrupt
46646  */
46647 #define ALT_USB_HOST_HCINT10_BNAINTR_E_ACT 0x1
46648 
46649 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_BNAINTR register field. */
46650 #define ALT_USB_HOST_HCINT10_BNAINTR_LSB 11
46651 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_BNAINTR register field. */
46652 #define ALT_USB_HOST_HCINT10_BNAINTR_MSB 11
46653 /* The width in bits of the ALT_USB_HOST_HCINT10_BNAINTR register field. */
46654 #define ALT_USB_HOST_HCINT10_BNAINTR_WIDTH 1
46655 /* The mask used to set the ALT_USB_HOST_HCINT10_BNAINTR register field value. */
46656 #define ALT_USB_HOST_HCINT10_BNAINTR_SET_MSK 0x00000800
46657 /* The mask used to clear the ALT_USB_HOST_HCINT10_BNAINTR register field value. */
46658 #define ALT_USB_HOST_HCINT10_BNAINTR_CLR_MSK 0xfffff7ff
46659 /* The reset value of the ALT_USB_HOST_HCINT10_BNAINTR register field. */
46660 #define ALT_USB_HOST_HCINT10_BNAINTR_RESET 0x0
46661 /* Extracts the ALT_USB_HOST_HCINT10_BNAINTR field value from a register. */
46662 #define ALT_USB_HOST_HCINT10_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
46663 /* Produces a ALT_USB_HOST_HCINT10_BNAINTR register field value suitable for setting the register. */
46664 #define ALT_USB_HOST_HCINT10_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
46665 
46666 /*
46667  * Field : xcs_xact_err
46668  *
46669  * Excessive Transaction Error (XCS_XACT_ERR)
46670  *
46671  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
46672  * this bit
46673  *
46674  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
46675  *
46676  * not be generated for Isochronous channels.
46677  *
46678  * For non Scatter/Gather DMA mode, this bit is reserved.
46679  *
46680  * Field Enumeration Values:
46681  *
46682  * Enum | Value | Description
46683  * :--------------------------------------------|:------|:-------------------------------
46684  * ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
46685  * ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
46686  *
46687  * Field Access Macros:
46688  *
46689  */
46690 /*
46691  * Enumerated value for register field ALT_USB_HOST_HCINT10_XCS_XACT_ERR
46692  *
46693  * No Excessive Transaction Error
46694  */
46695 #define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_INACT 0x0
46696 /*
46697  * Enumerated value for register field ALT_USB_HOST_HCINT10_XCS_XACT_ERR
46698  *
46699  * Excessive Transaction Error
46700  */
46701 #define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_ACVTIVE 0x1
46702 
46703 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */
46704 #define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_LSB 12
46705 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */
46706 #define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_MSB 12
46707 /* The width in bits of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */
46708 #define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_WIDTH 1
46709 /* The mask used to set the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field value. */
46710 #define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_SET_MSK 0x00001000
46711 /* The mask used to clear the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field value. */
46712 #define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_CLR_MSK 0xffffefff
46713 /* The reset value of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */
46714 #define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_RESET 0x0
46715 /* Extracts the ALT_USB_HOST_HCINT10_XCS_XACT_ERR field value from a register. */
46716 #define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
46717 /* Produces a ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field value suitable for setting the register. */
46718 #define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
46719 
46720 /*
46721  * Field : desc_lst_rollintr
46722  *
46723  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
46724  *
46725  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
46726  * this bit
46727  *
46728  * when the corresponding channel's descriptor list rolls over.
46729  *
46730  * For non Scatter/Gather DMA mode, this bit is reserved.
46731  *
46732  * Field Enumeration Values:
46733  *
46734  * Enum | Value | Description
46735  * :-----------------------------------------------|:------|:---------------------------------
46736  * ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
46737  * ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
46738  *
46739  * Field Access Macros:
46740  *
46741  */
46742 /*
46743  * Enumerated value for register field ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR
46744  *
46745  * No Descriptor rollover interrupt
46746  */
46747 #define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_INACT 0x0
46748 /*
46749  * Enumerated value for register field ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR
46750  *
46751  * Descriptor rollover interrupt
46752  */
46753 #define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_ACT 0x1
46754 
46755 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */
46756 #define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_LSB 13
46757 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */
46758 #define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_MSB 13
46759 /* The width in bits of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */
46760 #define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_WIDTH 1
46761 /* The mask used to set the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field value. */
46762 #define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_SET_MSK 0x00002000
46763 /* The mask used to clear the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field value. */
46764 #define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
46765 /* The reset value of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */
46766 #define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_RESET 0x0
46767 /* Extracts the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR field value from a register. */
46768 #define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
46769 /* Produces a ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field value suitable for setting the register. */
46770 #define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
46771 
46772 #ifndef __ASSEMBLY__
46773 /*
46774  * WARNING: The C register and register group struct declarations are provided for
46775  * convenience and illustrative purposes. They should, however, be used with
46776  * caution as the C language standard provides no guarantees about the alignment or
46777  * atomicity of device memory accesses. The recommended practice for writing
46778  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46779  * alt_write_word() functions.
46780  *
46781  * The struct declaration for register ALT_USB_HOST_HCINT10.
46782  */
46783 struct ALT_USB_HOST_HCINT10_s
46784 {
46785  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT10_XFERCOMPL */
46786  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT10_CHHLTD */
46787  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT10_AHBERR */
46788  uint32_t stall : 1; /* ALT_USB_HOST_HCINT10_STALL */
46789  uint32_t nak : 1; /* ALT_USB_HOST_HCINT10_NAK */
46790  uint32_t ack : 1; /* ALT_USB_HOST_HCINT10_ACK */
46791  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT10_NYET */
46792  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT10_XACTERR */
46793  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT10_BBLERR */
46794  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT10_FRMOVRUN */
46795  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT10_DATATGLERR */
46796  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT10_BNAINTR */
46797  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT10_XCS_XACT_ERR */
46798  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR */
46799  uint32_t : 18; /* *UNDEFINED* */
46800 };
46801 
46802 /* The typedef declaration for register ALT_USB_HOST_HCINT10. */
46803 typedef volatile struct ALT_USB_HOST_HCINT10_s ALT_USB_HOST_HCINT10_t;
46804 #endif /* __ASSEMBLY__ */
46805 
46806 /* The reset value of the ALT_USB_HOST_HCINT10 register. */
46807 #define ALT_USB_HOST_HCINT10_RESET 0x00000000
46808 /* The byte offset of the ALT_USB_HOST_HCINT10 register from the beginning of the component. */
46809 #define ALT_USB_HOST_HCINT10_OFST 0x248
46810 /* The address of the ALT_USB_HOST_HCINT10 register. */
46811 #define ALT_USB_HOST_HCINT10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT10_OFST))
46812 
46813 /*
46814  * Register : hcintmsk10
46815  *
46816  * Host Channel 10 Interrupt Mask Register
46817  *
46818  * Register Layout
46819  *
46820  * Bits | Access | Reset | Description
46821  * :--------|:-------|:------|:--------------------------------------------
46822  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK
46823  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_CHHLTDMSK
46824  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_AHBERRMSK
46825  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_STALLMSK
46826  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_NAKMSK
46827  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_ACKMSK
46828  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_NYETMSK
46829  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_XACTERRMSK
46830  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_BBLERRMSK
46831  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK
46832  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK
46833  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_BNAINTRMSK
46834  * [12] | ??? | 0x0 | *UNDEFINED*
46835  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK
46836  * [31:14] | ??? | 0x0 | *UNDEFINED*
46837  *
46838  */
46839 /*
46840  * Field : xfercomplmsk
46841  *
46842  * Transfer Completed Mask (XferComplMsk)
46843  *
46844  * Field Enumeration Values:
46845  *
46846  * Enum | Value | Description
46847  * :---------------------------------------------|:------|:------------
46848  * ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_MSK | 0x0 | Mask
46849  * ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
46850  *
46851  * Field Access Macros:
46852  *
46853  */
46854 /*
46855  * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK
46856  *
46857  * Mask
46858  */
46859 #define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_MSK 0x0
46860 /*
46861  * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK
46862  *
46863  * No mask
46864  */
46865 #define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_NOMSK 0x1
46866 
46867 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */
46868 #define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_LSB 0
46869 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */
46870 #define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_MSB 0
46871 /* The width in bits of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */
46872 #define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_WIDTH 1
46873 /* The mask used to set the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field value. */
46874 #define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_SET_MSK 0x00000001
46875 /* The mask used to clear the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field value. */
46876 #define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_CLR_MSK 0xfffffffe
46877 /* The reset value of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */
46878 #define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_RESET 0x0
46879 /* Extracts the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK field value from a register. */
46880 #define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
46881 /* Produces a ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field value suitable for setting the register. */
46882 #define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
46883 
46884 /*
46885  * Field : chhltdmsk
46886  *
46887  * Channel Halted Mask (ChHltdMsk)
46888  *
46889  * Field Enumeration Values:
46890  *
46891  * Enum | Value | Description
46892  * :------------------------------------------|:------|:------------
46893  * ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_MSK | 0x0 | Mask
46894  * ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_NOMSK | 0x1 | No mask
46895  *
46896  * Field Access Macros:
46897  *
46898  */
46899 /*
46900  * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_CHHLTDMSK
46901  *
46902  * Mask
46903  */
46904 #define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_MSK 0x0
46905 /*
46906  * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_CHHLTDMSK
46907  *
46908  * No mask
46909  */
46910 #define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_NOMSK 0x1
46911 
46912 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */
46913 #define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_LSB 1
46914 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */
46915 #define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_MSB 1
46916 /* The width in bits of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */
46917 #define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_WIDTH 1
46918 /* The mask used to set the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field value. */
46919 #define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_SET_MSK 0x00000002
46920 /* The mask used to clear the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field value. */
46921 #define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_CLR_MSK 0xfffffffd
46922 /* The reset value of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */
46923 #define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_RESET 0x0
46924 /* Extracts the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK field value from a register. */
46925 #define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
46926 /* Produces a ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field value suitable for setting the register. */
46927 #define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
46928 
46929 /*
46930  * Field : ahberrmsk
46931  *
46932  * AHB Error Mask (AHBErrMsk)
46933  *
46934  * In scatter/gather DMA mode for host,
46935  *
46936  * interrupts will not be generated due to the corresponding bits set in
46937  *
46938  * HCINTn.
46939  *
46940  * Field Enumeration Values:
46941  *
46942  * Enum | Value | Description
46943  * :------------------------------------------|:------|:------------
46944  * ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_MSK | 0x0 | Mask
46945  * ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_NOMSK | 0x1 | No mask
46946  *
46947  * Field Access Macros:
46948  *
46949  */
46950 /*
46951  * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_AHBERRMSK
46952  *
46953  * Mask
46954  */
46955 #define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_MSK 0x0
46956 /*
46957  * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_AHBERRMSK
46958  *
46959  * No mask
46960  */
46961 #define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_NOMSK 0x1
46962 
46963 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */
46964 #define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_LSB 2
46965 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */
46966 #define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_MSB 2
46967 /* The width in bits of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */
46968 #define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_WIDTH 1
46969 /* The mask used to set the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field value. */
46970 #define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_SET_MSK 0x00000004
46971 /* The mask used to clear the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field value. */
46972 #define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_CLR_MSK 0xfffffffb
46973 /* The reset value of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */
46974 #define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_RESET 0x0
46975 /* Extracts the ALT_USB_HOST_HCINTMSK10_AHBERRMSK field value from a register. */
46976 #define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
46977 /* Produces a ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field value suitable for setting the register. */
46978 #define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
46979 
46980 /*
46981  * Field : stallmsk
46982  *
46983  * STALL Response Received Interrupt Mask (StallMsk)
46984  *
46985  * In scatter/gather DMA mode for host,
46986  *
46987  * interrupts will not be generated due to the corresponding bits set in
46988  *
46989  * HCINTn.
46990  *
46991  * Field Access Macros:
46992  *
46993  */
46994 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_STALLMSK register field. */
46995 #define ALT_USB_HOST_HCINTMSK10_STALLMSK_LSB 3
46996 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_STALLMSK register field. */
46997 #define ALT_USB_HOST_HCINTMSK10_STALLMSK_MSB 3
46998 /* The width in bits of the ALT_USB_HOST_HCINTMSK10_STALLMSK register field. */
46999 #define ALT_USB_HOST_HCINTMSK10_STALLMSK_WIDTH 1
47000 /* The mask used to set the ALT_USB_HOST_HCINTMSK10_STALLMSK register field value. */
47001 #define ALT_USB_HOST_HCINTMSK10_STALLMSK_SET_MSK 0x00000008
47002 /* The mask used to clear the ALT_USB_HOST_HCINTMSK10_STALLMSK register field value. */
47003 #define ALT_USB_HOST_HCINTMSK10_STALLMSK_CLR_MSK 0xfffffff7
47004 /* The reset value of the ALT_USB_HOST_HCINTMSK10_STALLMSK register field. */
47005 #define ALT_USB_HOST_HCINTMSK10_STALLMSK_RESET 0x0
47006 /* Extracts the ALT_USB_HOST_HCINTMSK10_STALLMSK field value from a register. */
47007 #define ALT_USB_HOST_HCINTMSK10_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
47008 /* Produces a ALT_USB_HOST_HCINTMSK10_STALLMSK register field value suitable for setting the register. */
47009 #define ALT_USB_HOST_HCINTMSK10_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
47010 
47011 /*
47012  * Field : nakmsk
47013  *
47014  * NAK Response Received Interrupt Mask (NakMsk)
47015  *
47016  * In scatter/gather DMA mode for host,
47017  *
47018  * interrupts will not be generated due to the corresponding bits set in
47019  *
47020  * HCINTn.
47021  *
47022  * Field Access Macros:
47023  *
47024  */
47025 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_NAKMSK register field. */
47026 #define ALT_USB_HOST_HCINTMSK10_NAKMSK_LSB 4
47027 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_NAKMSK register field. */
47028 #define ALT_USB_HOST_HCINTMSK10_NAKMSK_MSB 4
47029 /* The width in bits of the ALT_USB_HOST_HCINTMSK10_NAKMSK register field. */
47030 #define ALT_USB_HOST_HCINTMSK10_NAKMSK_WIDTH 1
47031 /* The mask used to set the ALT_USB_HOST_HCINTMSK10_NAKMSK register field value. */
47032 #define ALT_USB_HOST_HCINTMSK10_NAKMSK_SET_MSK 0x00000010
47033 /* The mask used to clear the ALT_USB_HOST_HCINTMSK10_NAKMSK register field value. */
47034 #define ALT_USB_HOST_HCINTMSK10_NAKMSK_CLR_MSK 0xffffffef
47035 /* The reset value of the ALT_USB_HOST_HCINTMSK10_NAKMSK register field. */
47036 #define ALT_USB_HOST_HCINTMSK10_NAKMSK_RESET 0x0
47037 /* Extracts the ALT_USB_HOST_HCINTMSK10_NAKMSK field value from a register. */
47038 #define ALT_USB_HOST_HCINTMSK10_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
47039 /* Produces a ALT_USB_HOST_HCINTMSK10_NAKMSK register field value suitable for setting the register. */
47040 #define ALT_USB_HOST_HCINTMSK10_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
47041 
47042 /*
47043  * Field : ackmsk
47044  *
47045  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
47046  *
47047  * In scatter/gather DMA mode for host,
47048  *
47049  * interrupts will not be generated due to the corresponding bits set in
47050  *
47051  * HCINTn.
47052  *
47053  * Field Access Macros:
47054  *
47055  */
47056 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_ACKMSK register field. */
47057 #define ALT_USB_HOST_HCINTMSK10_ACKMSK_LSB 5
47058 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_ACKMSK register field. */
47059 #define ALT_USB_HOST_HCINTMSK10_ACKMSK_MSB 5
47060 /* The width in bits of the ALT_USB_HOST_HCINTMSK10_ACKMSK register field. */
47061 #define ALT_USB_HOST_HCINTMSK10_ACKMSK_WIDTH 1
47062 /* The mask used to set the ALT_USB_HOST_HCINTMSK10_ACKMSK register field value. */
47063 #define ALT_USB_HOST_HCINTMSK10_ACKMSK_SET_MSK 0x00000020
47064 /* The mask used to clear the ALT_USB_HOST_HCINTMSK10_ACKMSK register field value. */
47065 #define ALT_USB_HOST_HCINTMSK10_ACKMSK_CLR_MSK 0xffffffdf
47066 /* The reset value of the ALT_USB_HOST_HCINTMSK10_ACKMSK register field. */
47067 #define ALT_USB_HOST_HCINTMSK10_ACKMSK_RESET 0x0
47068 /* Extracts the ALT_USB_HOST_HCINTMSK10_ACKMSK field value from a register. */
47069 #define ALT_USB_HOST_HCINTMSK10_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
47070 /* Produces a ALT_USB_HOST_HCINTMSK10_ACKMSK register field value suitable for setting the register. */
47071 #define ALT_USB_HOST_HCINTMSK10_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
47072 
47073 /*
47074  * Field : nyetmsk
47075  *
47076  * NYET Response Received Interrupt Mask (NyetMsk)
47077  *
47078  * In scatter/gather DMA mode for host,
47079  *
47080  * interrupts will not be generated due to the corresponding bits set in
47081  *
47082  * HCINTn.
47083  *
47084  * Field Access Macros:
47085  *
47086  */
47087 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_NYETMSK register field. */
47088 #define ALT_USB_HOST_HCINTMSK10_NYETMSK_LSB 6
47089 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_NYETMSK register field. */
47090 #define ALT_USB_HOST_HCINTMSK10_NYETMSK_MSB 6
47091 /* The width in bits of the ALT_USB_HOST_HCINTMSK10_NYETMSK register field. */
47092 #define ALT_USB_HOST_HCINTMSK10_NYETMSK_WIDTH 1
47093 /* The mask used to set the ALT_USB_HOST_HCINTMSK10_NYETMSK register field value. */
47094 #define ALT_USB_HOST_HCINTMSK10_NYETMSK_SET_MSK 0x00000040
47095 /* The mask used to clear the ALT_USB_HOST_HCINTMSK10_NYETMSK register field value. */
47096 #define ALT_USB_HOST_HCINTMSK10_NYETMSK_CLR_MSK 0xffffffbf
47097 /* The reset value of the ALT_USB_HOST_HCINTMSK10_NYETMSK register field. */
47098 #define ALT_USB_HOST_HCINTMSK10_NYETMSK_RESET 0x0
47099 /* Extracts the ALT_USB_HOST_HCINTMSK10_NYETMSK field value from a register. */
47100 #define ALT_USB_HOST_HCINTMSK10_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
47101 /* Produces a ALT_USB_HOST_HCINTMSK10_NYETMSK register field value suitable for setting the register. */
47102 #define ALT_USB_HOST_HCINTMSK10_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
47103 
47104 /*
47105  * Field : xacterrmsk
47106  *
47107  * Transaction Error Mask (XactErrMsk)
47108  *
47109  * In scatter/gather DMA mode for host,
47110  *
47111  * interrupts will not be generated due to the corresponding bits set in
47112  *
47113  * HCINTn.
47114  *
47115  * Field Access Macros:
47116  *
47117  */
47118 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field. */
47119 #define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_LSB 7
47120 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field. */
47121 #define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_MSB 7
47122 /* The width in bits of the ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field. */
47123 #define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_WIDTH 1
47124 /* The mask used to set the ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field value. */
47125 #define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_SET_MSK 0x00000080
47126 /* The mask used to clear the ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field value. */
47127 #define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_CLR_MSK 0xffffff7f
47128 /* The reset value of the ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field. */
47129 #define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_RESET 0x0
47130 /* Extracts the ALT_USB_HOST_HCINTMSK10_XACTERRMSK field value from a register. */
47131 #define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
47132 /* Produces a ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field value suitable for setting the register. */
47133 #define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
47134 
47135 /*
47136  * Field : bblerrmsk
47137  *
47138  * Babble Error Mask (BblErrMsk)
47139  *
47140  * In scatter/gather DMA mode for host,
47141  *
47142  * interrupts will not be generated due to the corresponding bits set in
47143  *
47144  * HCINTn.
47145  *
47146  * Field Access Macros:
47147  *
47148  */
47149 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field. */
47150 #define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_LSB 8
47151 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field. */
47152 #define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_MSB 8
47153 /* The width in bits of the ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field. */
47154 #define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_WIDTH 1
47155 /* The mask used to set the ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field value. */
47156 #define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_SET_MSK 0x00000100
47157 /* The mask used to clear the ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field value. */
47158 #define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_CLR_MSK 0xfffffeff
47159 /* The reset value of the ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field. */
47160 #define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_RESET 0x0
47161 /* Extracts the ALT_USB_HOST_HCINTMSK10_BBLERRMSK field value from a register. */
47162 #define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
47163 /* Produces a ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field value suitable for setting the register. */
47164 #define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
47165 
47166 /*
47167  * Field : frmovrunmsk
47168  *
47169  * Frame Overrun Mask (FrmOvrunMsk)
47170  *
47171  * In scatter/gather DMA mode for host,
47172  *
47173  * interrupts will not be generated due to the corresponding bits set in
47174  *
47175  * HCINTn.
47176  *
47177  * Field Access Macros:
47178  *
47179  */
47180 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field. */
47181 #define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_LSB 9
47182 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field. */
47183 #define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_MSB 9
47184 /* The width in bits of the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field. */
47185 #define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_WIDTH 1
47186 /* The mask used to set the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field value. */
47187 #define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_SET_MSK 0x00000200
47188 /* The mask used to clear the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field value. */
47189 #define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_CLR_MSK 0xfffffdff
47190 /* The reset value of the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field. */
47191 #define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_RESET 0x0
47192 /* Extracts the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK field value from a register. */
47193 #define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
47194 /* Produces a ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field value suitable for setting the register. */
47195 #define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
47196 
47197 /*
47198  * Field : datatglerrmsk
47199  *
47200  * Data Toggle Error Mask (DataTglErrMsk)
47201  *
47202  * In scatter/gather DMA mode for host,
47203  *
47204  * interrupts will not be generated due to the corresponding bits set in
47205  *
47206  * HCINTn.
47207  *
47208  * Field Access Macros:
47209  *
47210  */
47211 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field. */
47212 #define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_LSB 10
47213 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field. */
47214 #define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_MSB 10
47215 /* The width in bits of the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field. */
47216 #define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_WIDTH 1
47217 /* The mask used to set the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field value. */
47218 #define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_SET_MSK 0x00000400
47219 /* The mask used to clear the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field value. */
47220 #define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_CLR_MSK 0xfffffbff
47221 /* The reset value of the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field. */
47222 #define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_RESET 0x0
47223 /* Extracts the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK field value from a register. */
47224 #define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
47225 /* Produces a ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field value suitable for setting the register. */
47226 #define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
47227 
47228 /*
47229  * Field : bnaintrmsk
47230  *
47231  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
47232  *
47233  * This bit is valid only when Scatter/Gather DMA mode is enabled.
47234  *
47235  * Field Enumeration Values:
47236  *
47237  * Enum | Value | Description
47238  * :-------------------------------------------|:------|:------------
47239  * ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_MSK | 0x0 | Mask
47240  * ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_NOMSK | 0x1 | No mask
47241  *
47242  * Field Access Macros:
47243  *
47244  */
47245 /*
47246  * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_BNAINTRMSK
47247  *
47248  * Mask
47249  */
47250 #define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_MSK 0x0
47251 /*
47252  * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_BNAINTRMSK
47253  *
47254  * No mask
47255  */
47256 #define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_NOMSK 0x1
47257 
47258 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */
47259 #define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_LSB 11
47260 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */
47261 #define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_MSB 11
47262 /* The width in bits of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */
47263 #define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_WIDTH 1
47264 /* The mask used to set the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field value. */
47265 #define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_SET_MSK 0x00000800
47266 /* The mask used to clear the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field value. */
47267 #define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_CLR_MSK 0xfffff7ff
47268 /* The reset value of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */
47269 #define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_RESET 0x0
47270 /* Extracts the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK field value from a register. */
47271 #define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
47272 /* Produces a ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field value suitable for setting the register. */
47273 #define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
47274 
47275 /*
47276  * Field : frm_lst_rollintrmsk
47277  *
47278  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
47279  *
47280  * This bit is valid only when Scatter/Gather DMA mode is enabled.
47281  *
47282  * Field Enumeration Values:
47283  *
47284  * Enum | Value | Description
47285  * :----------------------------------------------------|:------|:------------
47286  * ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
47287  * ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
47288  *
47289  * Field Access Macros:
47290  *
47291  */
47292 /*
47293  * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK
47294  *
47295  * Mask
47296  */
47297 #define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_MSK 0x0
47298 /*
47299  * Enumerated value for register field ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK
47300  *
47301  * No mask
47302  */
47303 #define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
47304 
47305 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */
47306 #define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_LSB 13
47307 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */
47308 #define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_MSB 13
47309 /* The width in bits of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */
47310 #define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_WIDTH 1
47311 /* The mask used to set the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field value. */
47312 #define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
47313 /* The mask used to clear the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field value. */
47314 #define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
47315 /* The reset value of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */
47316 #define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_RESET 0x0
47317 /* Extracts the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK field value from a register. */
47318 #define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
47319 /* Produces a ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
47320 #define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
47321 
47322 #ifndef __ASSEMBLY__
47323 /*
47324  * WARNING: The C register and register group struct declarations are provided for
47325  * convenience and illustrative purposes. They should, however, be used with
47326  * caution as the C language standard provides no guarantees about the alignment or
47327  * atomicity of device memory accesses. The recommended practice for writing
47328  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47329  * alt_write_word() functions.
47330  *
47331  * The struct declaration for register ALT_USB_HOST_HCINTMSK10.
47332  */
47333 struct ALT_USB_HOST_HCINTMSK10_s
47334 {
47335  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK */
47336  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK10_CHHLTDMSK */
47337  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK10_AHBERRMSK */
47338  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK10_STALLMSK */
47339  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK10_NAKMSK */
47340  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK10_ACKMSK */
47341  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK10_NYETMSK */
47342  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK10_XACTERRMSK */
47343  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK10_BBLERRMSK */
47344  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK */
47345  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK */
47346  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK10_BNAINTRMSK */
47347  uint32_t : 1; /* *UNDEFINED* */
47348  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK */
47349  uint32_t : 18; /* *UNDEFINED* */
47350 };
47351 
47352 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK10. */
47353 typedef volatile struct ALT_USB_HOST_HCINTMSK10_s ALT_USB_HOST_HCINTMSK10_t;
47354 #endif /* __ASSEMBLY__ */
47355 
47356 /* The reset value of the ALT_USB_HOST_HCINTMSK10 register. */
47357 #define ALT_USB_HOST_HCINTMSK10_RESET 0x00000000
47358 /* The byte offset of the ALT_USB_HOST_HCINTMSK10 register from the beginning of the component. */
47359 #define ALT_USB_HOST_HCINTMSK10_OFST 0x24c
47360 /* The address of the ALT_USB_HOST_HCINTMSK10 register. */
47361 #define ALT_USB_HOST_HCINTMSK10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK10_OFST))
47362 
47363 /*
47364  * Register : hctsiz10
47365  *
47366  * Host Channel 10 Transfer Size Register
47367  *
47368  * Register Layout
47369  *
47370  * Bits | Access | Reset | Description
47371  * :--------|:-------|:------|:-------------------------------
47372  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ10_XFERSIZE
47373  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ10_PKTCNT
47374  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ10_PID
47375  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ10_DOPNG
47376  *
47377  */
47378 /*
47379  * Field : xfersize
47380  *
47381  * Transfer Size (XferSize)
47382  *
47383  * For an OUT, this field is the number of data bytes the host sends
47384  *
47385  * during the transfer.
47386  *
47387  * For an IN, this field is the buffer size that the application has
47388  *
47389  * Reserved For the transfer. The application is expected to
47390  *
47391  * program this field as an integer multiple of the maximum packet
47392  *
47393  * size For IN transactions (periodic and non-periodic).
47394  *
47395  * The width of this counter is specified as Width of Transfer Size
47396  *
47397  * Counters
47398  *
47399  * Field Access Macros:
47400  *
47401  */
47402 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */
47403 #define ALT_USB_HOST_HCTSIZ10_XFERSIZE_LSB 0
47404 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */
47405 #define ALT_USB_HOST_HCTSIZ10_XFERSIZE_MSB 18
47406 /* The width in bits of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */
47407 #define ALT_USB_HOST_HCTSIZ10_XFERSIZE_WIDTH 19
47408 /* The mask used to set the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field value. */
47409 #define ALT_USB_HOST_HCTSIZ10_XFERSIZE_SET_MSK 0x0007ffff
47410 /* The mask used to clear the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field value. */
47411 #define ALT_USB_HOST_HCTSIZ10_XFERSIZE_CLR_MSK 0xfff80000
47412 /* The reset value of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */
47413 #define ALT_USB_HOST_HCTSIZ10_XFERSIZE_RESET 0x0
47414 /* Extracts the ALT_USB_HOST_HCTSIZ10_XFERSIZE field value from a register. */
47415 #define ALT_USB_HOST_HCTSIZ10_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
47416 /* Produces a ALT_USB_HOST_HCTSIZ10_XFERSIZE register field value suitable for setting the register. */
47417 #define ALT_USB_HOST_HCTSIZ10_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
47418 
47419 /*
47420  * Field : pktcnt
47421  *
47422  * Packet Count (PktCnt)
47423  *
47424  * This field is programmed by the application with the expected
47425  *
47426  * number of packets to be transmitted (OUT) or received (IN).
47427  *
47428  * The host decrements this count on every successful
47429  *
47430  * transmission or reception of an OUT/IN packet. Once this count
47431  *
47432  * reaches zero, the application is interrupted to indicate normal
47433  *
47434  * completion.
47435  *
47436  * The width of this counter is specified as Width of Packet
47437  *
47438  * Counters
47439  *
47440  * Field Access Macros:
47441  *
47442  */
47443 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */
47444 #define ALT_USB_HOST_HCTSIZ10_PKTCNT_LSB 19
47445 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */
47446 #define ALT_USB_HOST_HCTSIZ10_PKTCNT_MSB 28
47447 /* The width in bits of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */
47448 #define ALT_USB_HOST_HCTSIZ10_PKTCNT_WIDTH 10
47449 /* The mask used to set the ALT_USB_HOST_HCTSIZ10_PKTCNT register field value. */
47450 #define ALT_USB_HOST_HCTSIZ10_PKTCNT_SET_MSK 0x1ff80000
47451 /* The mask used to clear the ALT_USB_HOST_HCTSIZ10_PKTCNT register field value. */
47452 #define ALT_USB_HOST_HCTSIZ10_PKTCNT_CLR_MSK 0xe007ffff
47453 /* The reset value of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */
47454 #define ALT_USB_HOST_HCTSIZ10_PKTCNT_RESET 0x0
47455 /* Extracts the ALT_USB_HOST_HCTSIZ10_PKTCNT field value from a register. */
47456 #define ALT_USB_HOST_HCTSIZ10_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
47457 /* Produces a ALT_USB_HOST_HCTSIZ10_PKTCNT register field value suitable for setting the register. */
47458 #define ALT_USB_HOST_HCTSIZ10_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
47459 
47460 /*
47461  * Field : pid
47462  *
47463  * PID (Pid)
47464  *
47465  * The application programs this field with the type of PID to use For
47466  *
47467  * the initial transaction. The host maintains this field For the rest of
47468  *
47469  * the transfer.
47470  *
47471  * 2'b00: DATA0
47472  *
47473  * 2'b01: DATA2
47474  *
47475  * 2'b10: DATA1
47476  *
47477  * 2'b11: MDATA (non-control)/SETUP (control)
47478  *
47479  * Field Enumeration Values:
47480  *
47481  * Enum | Value | Description
47482  * :----------------------------------|:------|:------------------------------------
47483  * ALT_USB_HOST_HCTSIZ10_PID_E_DATA0 | 0x0 | DATA0
47484  * ALT_USB_HOST_HCTSIZ10_PID_E_DATA2 | 0x1 | DATA2
47485  * ALT_USB_HOST_HCTSIZ10_PID_E_DATA1 | 0x2 | DATA1
47486  * ALT_USB_HOST_HCTSIZ10_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
47487  *
47488  * Field Access Macros:
47489  *
47490  */
47491 /*
47492  * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID
47493  *
47494  * DATA0
47495  */
47496 #define ALT_USB_HOST_HCTSIZ10_PID_E_DATA0 0x0
47497 /*
47498  * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID
47499  *
47500  * DATA2
47501  */
47502 #define ALT_USB_HOST_HCTSIZ10_PID_E_DATA2 0x1
47503 /*
47504  * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID
47505  *
47506  * DATA1
47507  */
47508 #define ALT_USB_HOST_HCTSIZ10_PID_E_DATA1 0x2
47509 /*
47510  * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID
47511  *
47512  * MDATA (non-control)/SETUP (control)
47513  */
47514 #define ALT_USB_HOST_HCTSIZ10_PID_E_MDATA 0x3
47515 
47516 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_PID register field. */
47517 #define ALT_USB_HOST_HCTSIZ10_PID_LSB 29
47518 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_PID register field. */
47519 #define ALT_USB_HOST_HCTSIZ10_PID_MSB 30
47520 /* The width in bits of the ALT_USB_HOST_HCTSIZ10_PID register field. */
47521 #define ALT_USB_HOST_HCTSIZ10_PID_WIDTH 2
47522 /* The mask used to set the ALT_USB_HOST_HCTSIZ10_PID register field value. */
47523 #define ALT_USB_HOST_HCTSIZ10_PID_SET_MSK 0x60000000
47524 /* The mask used to clear the ALT_USB_HOST_HCTSIZ10_PID register field value. */
47525 #define ALT_USB_HOST_HCTSIZ10_PID_CLR_MSK 0x9fffffff
47526 /* The reset value of the ALT_USB_HOST_HCTSIZ10_PID register field. */
47527 #define ALT_USB_HOST_HCTSIZ10_PID_RESET 0x0
47528 /* Extracts the ALT_USB_HOST_HCTSIZ10_PID field value from a register. */
47529 #define ALT_USB_HOST_HCTSIZ10_PID_GET(value) (((value) & 0x60000000) >> 29)
47530 /* Produces a ALT_USB_HOST_HCTSIZ10_PID register field value suitable for setting the register. */
47531 #define ALT_USB_HOST_HCTSIZ10_PID_SET(value) (((value) << 29) & 0x60000000)
47532 
47533 /*
47534  * Field : dopng
47535  *
47536  * Do Ping (DoPng)
47537  *
47538  * This bit is used only For OUT transfers.
47539  *
47540  * Setting this field to 1 directs the host to do PING protocol.
47541  *
47542  * Note: Do not Set this bit For IN transfers. If this bit is Set For
47543  *
47544  * for IN transfers it disables the channel.
47545  *
47546  * Field Enumeration Values:
47547  *
47548  * Enum | Value | Description
47549  * :-------------------------------------|:------|:-----------------
47550  * ALT_USB_HOST_HCTSIZ10_DOPNG_E_NOPING | 0x0 | No ping protocol
47551  * ALT_USB_HOST_HCTSIZ10_DOPNG_E_PING | 0x1 | Ping protocol
47552  *
47553  * Field Access Macros:
47554  *
47555  */
47556 /*
47557  * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_DOPNG
47558  *
47559  * No ping protocol
47560  */
47561 #define ALT_USB_HOST_HCTSIZ10_DOPNG_E_NOPING 0x0
47562 /*
47563  * Enumerated value for register field ALT_USB_HOST_HCTSIZ10_DOPNG
47564  *
47565  * Ping protocol
47566  */
47567 #define ALT_USB_HOST_HCTSIZ10_DOPNG_E_PING 0x1
47568 
47569 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */
47570 #define ALT_USB_HOST_HCTSIZ10_DOPNG_LSB 31
47571 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */
47572 #define ALT_USB_HOST_HCTSIZ10_DOPNG_MSB 31
47573 /* The width in bits of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */
47574 #define ALT_USB_HOST_HCTSIZ10_DOPNG_WIDTH 1
47575 /* The mask used to set the ALT_USB_HOST_HCTSIZ10_DOPNG register field value. */
47576 #define ALT_USB_HOST_HCTSIZ10_DOPNG_SET_MSK 0x80000000
47577 /* The mask used to clear the ALT_USB_HOST_HCTSIZ10_DOPNG register field value. */
47578 #define ALT_USB_HOST_HCTSIZ10_DOPNG_CLR_MSK 0x7fffffff
47579 /* The reset value of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */
47580 #define ALT_USB_HOST_HCTSIZ10_DOPNG_RESET 0x0
47581 /* Extracts the ALT_USB_HOST_HCTSIZ10_DOPNG field value from a register. */
47582 #define ALT_USB_HOST_HCTSIZ10_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
47583 /* Produces a ALT_USB_HOST_HCTSIZ10_DOPNG register field value suitable for setting the register. */
47584 #define ALT_USB_HOST_HCTSIZ10_DOPNG_SET(value) (((value) << 31) & 0x80000000)
47585 
47586 #ifndef __ASSEMBLY__
47587 /*
47588  * WARNING: The C register and register group struct declarations are provided for
47589  * convenience and illustrative purposes. They should, however, be used with
47590  * caution as the C language standard provides no guarantees about the alignment or
47591  * atomicity of device memory accesses. The recommended practice for writing
47592  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47593  * alt_write_word() functions.
47594  *
47595  * The struct declaration for register ALT_USB_HOST_HCTSIZ10.
47596  */
47597 struct ALT_USB_HOST_HCTSIZ10_s
47598 {
47599  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ10_XFERSIZE */
47600  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ10_PKTCNT */
47601  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ10_PID */
47602  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ10_DOPNG */
47603 };
47604 
47605 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ10. */
47606 typedef volatile struct ALT_USB_HOST_HCTSIZ10_s ALT_USB_HOST_HCTSIZ10_t;
47607 #endif /* __ASSEMBLY__ */
47608 
47609 /* The reset value of the ALT_USB_HOST_HCTSIZ10 register. */
47610 #define ALT_USB_HOST_HCTSIZ10_RESET 0x00000000
47611 /* The byte offset of the ALT_USB_HOST_HCTSIZ10 register from the beginning of the component. */
47612 #define ALT_USB_HOST_HCTSIZ10_OFST 0x250
47613 /* The address of the ALT_USB_HOST_HCTSIZ10 register. */
47614 #define ALT_USB_HOST_HCTSIZ10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ10_OFST))
47615 
47616 /*
47617  * Register : hcdma10
47618  *
47619  * Host Channel 10 DMA Address Register
47620  *
47621  * Register Layout
47622  *
47623  * Bits | Access | Reset | Description
47624  * :-------|:-------|:------|:-----------------------------
47625  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA10_HCDMA10
47626  *
47627  */
47628 /*
47629  * Field : hcdma10
47630  *
47631  * Buffer DMA Mode:
47632  *
47633  * [31:0] DMA Address (DMAAddr)
47634  *
47635  * This field holds the start address in the external memory from which the data
47636  * for
47637  *
47638  * the endpoint must be fetched or to which it must be stored. This register is
47639  *
47640  * incremented on every AHB transaction.
47641  *
47642  * Scatter-Gather DMA (DescDMA) Mode:
47643  *
47644  * [31:9] (Non Isoc) Non-Isochronous:
47645  *
47646  * [31:N] (Isoc) Isochronous:
47647  *
47648  * This field holds the start address of the 512 bytes
47649  *
47650  * page. The first descriptor in the list should be located
47651  *
47652  * in this address. The first descriptor may be or may
47653  *
47654  * not be ready. The core starts processing the list from
47655  *
47656  * the CTD value.
47657  *
47658  * This field holds the address of the 2*(nTD+1) bytes of
47659  *
47660  * locations in which the isochronous descriptors are
47661  *
47662  * present where N is based on nTD as per Table below
47663  *
47664  * [31:N] Base Address
47665  *
47666  * [N-1:3] Offset
47667  *
47668  * [2:0] 000
47669  *
47670  * HS ISOC
47671  *
47672  * nTD N
47673  *
47674  * 7 6
47675  *
47676  * 15 7
47677  *
47678  * 31 8
47679  *
47680  * 63 9
47681  *
47682  * 127 10
47683  *
47684  * 255 11
47685  *
47686  * FS ISOC
47687  *
47688  * nTD N
47689  *
47690  * 1 4
47691  *
47692  * 3 5
47693  *
47694  * 7 6
47695  *
47696  * 15 7
47697  *
47698  * 31 8
47699  *
47700  * 63 9
47701  *
47702  * [N-1:3] (Isoc):
47703  *
47704  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
47705  *
47706  * Non Isochronous:
47707  *
47708  * This value is in terms of number of descriptors. The values can be from 0 to 63.
47709  *
47710  * 0 - 1 descriptor.
47711  *
47712  * 63 - 64 descriptors.
47713  *
47714  * This field indicates the current descriptor processed in the list. This field is
47715  * updated
47716  *
47717  * both by application and the core. For example, if the application enables the
47718  *
47719  * channel after programming CTD=5, then the core will start processing the 6th
47720  *
47721  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
47722  *
47723  * to DMAAddr.
47724  *
47725  * Isochronous:
47726  *
47727  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
47728  * set
47729  *
47730  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
47731  *
47732  * [31:9] (Non Isoc) Non-Isochronous:
47733  *
47734  * [31:N] (Isoc) Isochronous:
47735  *
47736  * This field holds the start address of the 512 bytes
47737  *
47738  * page. The first descriptor in the list should be located
47739  *
47740  * in this address. The first descriptor may be or may
47741  *
47742  * not be ready. The core starts processing the list from
47743  *
47744  * the CTD value.
47745  *
47746  * This field holds the address of the 2*(nTD+1) bytes of
47747  *
47748  * locations in which the isochronous descriptors are
47749  *
47750  * present where N is based on nTD as per Table below
47751  *
47752  * [31:N] Base Address
47753  *
47754  * [N-1:3] Offset
47755  *
47756  * [2:0] 000
47757  *
47758  * HS ISOC
47759  *
47760  * nTD N
47761  *
47762  * 7 6
47763  *
47764  * 15 7
47765  *
47766  * 31 8
47767  *
47768  * 63 9
47769  *
47770  * 127 10
47771  *
47772  * 255 11
47773  *
47774  * FS ISOC
47775  *
47776  * nTD N
47777  *
47778  * 1 4
47779  *
47780  * 3 5
47781  *
47782  * 7 6
47783  *
47784  * 15 7
47785  *
47786  * 31 8
47787  *
47788  * 63 9
47789  *
47790  * [N-1:3] (Isoc):
47791  *
47792  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
47793  *
47794  * Non Isochronous:
47795  *
47796  * This value is in terms of number of descriptors. The values can be from 0 to 63.
47797  *
47798  * 0 - 1 descriptor.
47799  *
47800  * 63 - 64 descriptors.
47801  *
47802  * This field indicates the current descriptor processed in the list. This field is
47803  * updated
47804  *
47805  * both by application and the core. For example, if the application enables the
47806  *
47807  * channel after programming CTD=5, then the core will start processing the 6th
47808  *
47809  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
47810  *
47811  * to DMAAddr.
47812  *
47813  * Isochronous:
47814  *
47815  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
47816  * set
47817  *
47818  * to zero by application.
47819  *
47820  * Field Access Macros:
47821  *
47822  */
47823 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */
47824 #define ALT_USB_HOST_HCDMA10_HCDMA10_LSB 0
47825 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */
47826 #define ALT_USB_HOST_HCDMA10_HCDMA10_MSB 31
47827 /* The width in bits of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */
47828 #define ALT_USB_HOST_HCDMA10_HCDMA10_WIDTH 32
47829 /* The mask used to set the ALT_USB_HOST_HCDMA10_HCDMA10 register field value. */
47830 #define ALT_USB_HOST_HCDMA10_HCDMA10_SET_MSK 0xffffffff
47831 /* The mask used to clear the ALT_USB_HOST_HCDMA10_HCDMA10 register field value. */
47832 #define ALT_USB_HOST_HCDMA10_HCDMA10_CLR_MSK 0x00000000
47833 /* The reset value of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */
47834 #define ALT_USB_HOST_HCDMA10_HCDMA10_RESET 0x0
47835 /* Extracts the ALT_USB_HOST_HCDMA10_HCDMA10 field value from a register. */
47836 #define ALT_USB_HOST_HCDMA10_HCDMA10_GET(value) (((value) & 0xffffffff) >> 0)
47837 /* Produces a ALT_USB_HOST_HCDMA10_HCDMA10 register field value suitable for setting the register. */
47838 #define ALT_USB_HOST_HCDMA10_HCDMA10_SET(value) (((value) << 0) & 0xffffffff)
47839 
47840 #ifndef __ASSEMBLY__
47841 /*
47842  * WARNING: The C register and register group struct declarations are provided for
47843  * convenience and illustrative purposes. They should, however, be used with
47844  * caution as the C language standard provides no guarantees about the alignment or
47845  * atomicity of device memory accesses. The recommended practice for writing
47846  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47847  * alt_write_word() functions.
47848  *
47849  * The struct declaration for register ALT_USB_HOST_HCDMA10.
47850  */
47851 struct ALT_USB_HOST_HCDMA10_s
47852 {
47853  uint32_t hcdma10 : 32; /* ALT_USB_HOST_HCDMA10_HCDMA10 */
47854 };
47855 
47856 /* The typedef declaration for register ALT_USB_HOST_HCDMA10. */
47857 typedef volatile struct ALT_USB_HOST_HCDMA10_s ALT_USB_HOST_HCDMA10_t;
47858 #endif /* __ASSEMBLY__ */
47859 
47860 /* The reset value of the ALT_USB_HOST_HCDMA10 register. */
47861 #define ALT_USB_HOST_HCDMA10_RESET 0x00000000
47862 /* The byte offset of the ALT_USB_HOST_HCDMA10 register from the beginning of the component. */
47863 #define ALT_USB_HOST_HCDMA10_OFST 0x254
47864 /* The address of the ALT_USB_HOST_HCDMA10 register. */
47865 #define ALT_USB_HOST_HCDMA10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA10_OFST))
47866 
47867 /*
47868  * Register : hcdmab10
47869  *
47870  * Host Channel 10 DMA Buffer Address Register
47871  *
47872  * Register Layout
47873  *
47874  * Bits | Access | Reset | Description
47875  * :-------|:-------|:------|:-------------------------------
47876  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB10_HCDMAB10
47877  *
47878  */
47879 /*
47880  * Field : hcdmab10
47881  *
47882  * Holds the current buffer address.
47883  *
47884  * This register is updated as and when the data transfer for the corresponding end
47885  * point
47886  *
47887  * is in progress. This register is present only in Scatter/Gather DMA mode.
47888  * Otherwise this
47889  *
47890  * field is reserved.
47891  *
47892  * Field Access Macros:
47893  *
47894  */
47895 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */
47896 #define ALT_USB_HOST_HCDMAB10_HCDMAB10_LSB 0
47897 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */
47898 #define ALT_USB_HOST_HCDMAB10_HCDMAB10_MSB 31
47899 /* The width in bits of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */
47900 #define ALT_USB_HOST_HCDMAB10_HCDMAB10_WIDTH 32
47901 /* The mask used to set the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field value. */
47902 #define ALT_USB_HOST_HCDMAB10_HCDMAB10_SET_MSK 0xffffffff
47903 /* The mask used to clear the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field value. */
47904 #define ALT_USB_HOST_HCDMAB10_HCDMAB10_CLR_MSK 0x00000000
47905 /* The reset value of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */
47906 #define ALT_USB_HOST_HCDMAB10_HCDMAB10_RESET 0x0
47907 /* Extracts the ALT_USB_HOST_HCDMAB10_HCDMAB10 field value from a register. */
47908 #define ALT_USB_HOST_HCDMAB10_HCDMAB10_GET(value) (((value) & 0xffffffff) >> 0)
47909 /* Produces a ALT_USB_HOST_HCDMAB10_HCDMAB10 register field value suitable for setting the register. */
47910 #define ALT_USB_HOST_HCDMAB10_HCDMAB10_SET(value) (((value) << 0) & 0xffffffff)
47911 
47912 #ifndef __ASSEMBLY__
47913 /*
47914  * WARNING: The C register and register group struct declarations are provided for
47915  * convenience and illustrative purposes. They should, however, be used with
47916  * caution as the C language standard provides no guarantees about the alignment or
47917  * atomicity of device memory accesses. The recommended practice for writing
47918  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47919  * alt_write_word() functions.
47920  *
47921  * The struct declaration for register ALT_USB_HOST_HCDMAB10.
47922  */
47923 struct ALT_USB_HOST_HCDMAB10_s
47924 {
47925  uint32_t hcdmab10 : 32; /* ALT_USB_HOST_HCDMAB10_HCDMAB10 */
47926 };
47927 
47928 /* The typedef declaration for register ALT_USB_HOST_HCDMAB10. */
47929 typedef volatile struct ALT_USB_HOST_HCDMAB10_s ALT_USB_HOST_HCDMAB10_t;
47930 #endif /* __ASSEMBLY__ */
47931 
47932 /* The reset value of the ALT_USB_HOST_HCDMAB10 register. */
47933 #define ALT_USB_HOST_HCDMAB10_RESET 0x00000000
47934 /* The byte offset of the ALT_USB_HOST_HCDMAB10 register from the beginning of the component. */
47935 #define ALT_USB_HOST_HCDMAB10_OFST 0x25c
47936 /* The address of the ALT_USB_HOST_HCDMAB10 register. */
47937 #define ALT_USB_HOST_HCDMAB10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB10_OFST))
47938 
47939 /*
47940  * Register : hcchar11
47941  *
47942  * Host Channel 11 Characteristics Register
47943  *
47944  * Register Layout
47945  *
47946  * Bits | Access | Reset | Description
47947  * :--------|:---------|:------|:------------------------------
47948  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_MPS
47949  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_EPNUM
47950  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_EPDIR
47951  * [16] | ??? | 0x0 | *UNDEFINED*
47952  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_LSPDDEV
47953  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_EPTYPE
47954  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_EC
47955  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_DEVADDR
47956  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_ODDFRM
47957  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR11_CHDIS
47958  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR11_CHENA
47959  *
47960  */
47961 /*
47962  * Field : mps
47963  *
47964  * Maximum Packet Size (MPS)
47965  *
47966  * Indicates the maximum packet size of the associated endpoint.
47967  *
47968  * Field Access Macros:
47969  *
47970  */
47971 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_MPS register field. */
47972 #define ALT_USB_HOST_HCCHAR11_MPS_LSB 0
47973 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_MPS register field. */
47974 #define ALT_USB_HOST_HCCHAR11_MPS_MSB 10
47975 /* The width in bits of the ALT_USB_HOST_HCCHAR11_MPS register field. */
47976 #define ALT_USB_HOST_HCCHAR11_MPS_WIDTH 11
47977 /* The mask used to set the ALT_USB_HOST_HCCHAR11_MPS register field value. */
47978 #define ALT_USB_HOST_HCCHAR11_MPS_SET_MSK 0x000007ff
47979 /* The mask used to clear the ALT_USB_HOST_HCCHAR11_MPS register field value. */
47980 #define ALT_USB_HOST_HCCHAR11_MPS_CLR_MSK 0xfffff800
47981 /* The reset value of the ALT_USB_HOST_HCCHAR11_MPS register field. */
47982 #define ALT_USB_HOST_HCCHAR11_MPS_RESET 0x0
47983 /* Extracts the ALT_USB_HOST_HCCHAR11_MPS field value from a register. */
47984 #define ALT_USB_HOST_HCCHAR11_MPS_GET(value) (((value) & 0x000007ff) >> 0)
47985 /* Produces a ALT_USB_HOST_HCCHAR11_MPS register field value suitable for setting the register. */
47986 #define ALT_USB_HOST_HCCHAR11_MPS_SET(value) (((value) << 0) & 0x000007ff)
47987 
47988 /*
47989  * Field : epnum
47990  *
47991  * Endpoint Number (EPNum)
47992  *
47993  * Indicates the endpoint number on the device serving as the data
47994  *
47995  * source or sink.
47996  *
47997  * Field Enumeration Values:
47998  *
47999  * Enum | Value | Description
48000  * :--------------------------------------|:------|:--------------
48001  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT0 | 0x0 | End point 0
48002  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT1 | 0x1 | End point 1
48003  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT2 | 0x2 | End point 2
48004  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT3 | 0x3 | End point 3
48005  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT4 | 0x4 | End point 4
48006  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT5 | 0x5 | End point 5
48007  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT6 | 0x6 | End point 6
48008  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT7 | 0x7 | End point 7
48009  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT8 | 0x8 | End point 8
48010  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT9 | 0x9 | End point 9
48011  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT10 | 0xa | End point 10
48012  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT11 | 0xb | End point 11
48013  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT12 | 0xc | End point 12
48014  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT13 | 0xd | End point 13
48015  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT14 | 0xe | End point 14
48016  * ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT15 | 0xf | End point 15
48017  *
48018  * Field Access Macros:
48019  *
48020  */
48021 /*
48022  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48023  *
48024  * End point 0
48025  */
48026 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT0 0x0
48027 /*
48028  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48029  *
48030  * End point 1
48031  */
48032 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT1 0x1
48033 /*
48034  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48035  *
48036  * End point 2
48037  */
48038 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT2 0x2
48039 /*
48040  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48041  *
48042  * End point 3
48043  */
48044 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT3 0x3
48045 /*
48046  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48047  *
48048  * End point 4
48049  */
48050 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT4 0x4
48051 /*
48052  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48053  *
48054  * End point 5
48055  */
48056 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT5 0x5
48057 /*
48058  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48059  *
48060  * End point 6
48061  */
48062 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT6 0x6
48063 /*
48064  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48065  *
48066  * End point 7
48067  */
48068 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT7 0x7
48069 /*
48070  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48071  *
48072  * End point 8
48073  */
48074 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT8 0x8
48075 /*
48076  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48077  *
48078  * End point 9
48079  */
48080 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT9 0x9
48081 /*
48082  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48083  *
48084  * End point 10
48085  */
48086 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT10 0xa
48087 /*
48088  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48089  *
48090  * End point 11
48091  */
48092 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT11 0xb
48093 /*
48094  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48095  *
48096  * End point 12
48097  */
48098 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT12 0xc
48099 /*
48100  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48101  *
48102  * End point 13
48103  */
48104 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT13 0xd
48105 /*
48106  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48107  *
48108  * End point 14
48109  */
48110 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT14 0xe
48111 /*
48112  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
48113  *
48114  * End point 15
48115  */
48116 #define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT15 0xf
48117 
48118 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */
48119 #define ALT_USB_HOST_HCCHAR11_EPNUM_LSB 11
48120 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */
48121 #define ALT_USB_HOST_HCCHAR11_EPNUM_MSB 14
48122 /* The width in bits of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */
48123 #define ALT_USB_HOST_HCCHAR11_EPNUM_WIDTH 4
48124 /* The mask used to set the ALT_USB_HOST_HCCHAR11_EPNUM register field value. */
48125 #define ALT_USB_HOST_HCCHAR11_EPNUM_SET_MSK 0x00007800
48126 /* The mask used to clear the ALT_USB_HOST_HCCHAR11_EPNUM register field value. */
48127 #define ALT_USB_HOST_HCCHAR11_EPNUM_CLR_MSK 0xffff87ff
48128 /* The reset value of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */
48129 #define ALT_USB_HOST_HCCHAR11_EPNUM_RESET 0x0
48130 /* Extracts the ALT_USB_HOST_HCCHAR11_EPNUM field value from a register. */
48131 #define ALT_USB_HOST_HCCHAR11_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
48132 /* Produces a ALT_USB_HOST_HCCHAR11_EPNUM register field value suitable for setting the register. */
48133 #define ALT_USB_HOST_HCCHAR11_EPNUM_SET(value) (((value) << 11) & 0x00007800)
48134 
48135 /*
48136  * Field : epdir
48137  *
48138  * Endpoint Direction (EPDir)
48139  *
48140  * Indicates whether the transaction is IN or OUT.
48141  *
48142  * 1'b0: OUT
48143  *
48144  * 1'b1: IN
48145  *
48146  * Field Enumeration Values:
48147  *
48148  * Enum | Value | Description
48149  * :----------------------------------|:------|:--------------
48150  * ALT_USB_HOST_HCCHAR11_EPDIR_E_OUT | 0x0 | OUT Direction
48151  * ALT_USB_HOST_HCCHAR11_EPDIR_E_IN | 0x1 | IN Direction
48152  *
48153  * Field Access Macros:
48154  *
48155  */
48156 /*
48157  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPDIR
48158  *
48159  * OUT Direction
48160  */
48161 #define ALT_USB_HOST_HCCHAR11_EPDIR_E_OUT 0x0
48162 /*
48163  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPDIR
48164  *
48165  * IN Direction
48166  */
48167 #define ALT_USB_HOST_HCCHAR11_EPDIR_E_IN 0x1
48168 
48169 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */
48170 #define ALT_USB_HOST_HCCHAR11_EPDIR_LSB 15
48171 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */
48172 #define ALT_USB_HOST_HCCHAR11_EPDIR_MSB 15
48173 /* The width in bits of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */
48174 #define ALT_USB_HOST_HCCHAR11_EPDIR_WIDTH 1
48175 /* The mask used to set the ALT_USB_HOST_HCCHAR11_EPDIR register field value. */
48176 #define ALT_USB_HOST_HCCHAR11_EPDIR_SET_MSK 0x00008000
48177 /* The mask used to clear the ALT_USB_HOST_HCCHAR11_EPDIR register field value. */
48178 #define ALT_USB_HOST_HCCHAR11_EPDIR_CLR_MSK 0xffff7fff
48179 /* The reset value of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */
48180 #define ALT_USB_HOST_HCCHAR11_EPDIR_RESET 0x0
48181 /* Extracts the ALT_USB_HOST_HCCHAR11_EPDIR field value from a register. */
48182 #define ALT_USB_HOST_HCCHAR11_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
48183 /* Produces a ALT_USB_HOST_HCCHAR11_EPDIR register field value suitable for setting the register. */
48184 #define ALT_USB_HOST_HCCHAR11_EPDIR_SET(value) (((value) << 15) & 0x00008000)
48185 
48186 /*
48187  * Field : lspddev
48188  *
48189  * Low-Speed Device (LSpdDev)
48190  *
48191  * This field is Set by the application to indicate that this channel is
48192  *
48193  * communicating to a low-speed device.
48194  *
48195  * Field Enumeration Values:
48196  *
48197  * Enum | Value | Description
48198  * :-------------------------------------|:------|:----------------------------------------
48199  * ALT_USB_HOST_HCCHAR11_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
48200  * ALT_USB_HOST_HCCHAR11_LSPDDEV_E_END | 0x1 | Communicating with low speed device
48201  *
48202  * Field Access Macros:
48203  *
48204  */
48205 /*
48206  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_LSPDDEV
48207  *
48208  * Not Communicating with low speed device
48209  */
48210 #define ALT_USB_HOST_HCCHAR11_LSPDDEV_E_DISD 0x0
48211 /*
48212  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_LSPDDEV
48213  *
48214  * Communicating with low speed device
48215  */
48216 #define ALT_USB_HOST_HCCHAR11_LSPDDEV_E_END 0x1
48217 
48218 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */
48219 #define ALT_USB_HOST_HCCHAR11_LSPDDEV_LSB 17
48220 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */
48221 #define ALT_USB_HOST_HCCHAR11_LSPDDEV_MSB 17
48222 /* The width in bits of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */
48223 #define ALT_USB_HOST_HCCHAR11_LSPDDEV_WIDTH 1
48224 /* The mask used to set the ALT_USB_HOST_HCCHAR11_LSPDDEV register field value. */
48225 #define ALT_USB_HOST_HCCHAR11_LSPDDEV_SET_MSK 0x00020000
48226 /* The mask used to clear the ALT_USB_HOST_HCCHAR11_LSPDDEV register field value. */
48227 #define ALT_USB_HOST_HCCHAR11_LSPDDEV_CLR_MSK 0xfffdffff
48228 /* The reset value of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */
48229 #define ALT_USB_HOST_HCCHAR11_LSPDDEV_RESET 0x0
48230 /* Extracts the ALT_USB_HOST_HCCHAR11_LSPDDEV field value from a register. */
48231 #define ALT_USB_HOST_HCCHAR11_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
48232 /* Produces a ALT_USB_HOST_HCCHAR11_LSPDDEV register field value suitable for setting the register. */
48233 #define ALT_USB_HOST_HCCHAR11_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
48234 
48235 /*
48236  * Field : eptype
48237  *
48238  * Endpoint Type (EPType)
48239  *
48240  * Indicates the transfer type selected.
48241  *
48242  * 2'b00: Control
48243  *
48244  * 2'b01: Isochronous
48245  *
48246  * 2'b10: Bulk
48247  *
48248  * 2'b11: Interrupt
48249  *
48250  * Field Enumeration Values:
48251  *
48252  * Enum | Value | Description
48253  * :--------------------------------------|:------|:------------
48254  * ALT_USB_HOST_HCCHAR11_EPTYPE_E_CTL | 0x0 | Control
48255  * ALT_USB_HOST_HCCHAR11_EPTYPE_E_ISOC | 0x1 | Isochronous
48256  * ALT_USB_HOST_HCCHAR11_EPTYPE_E_BULK | 0x2 | Bulk
48257  * ALT_USB_HOST_HCCHAR11_EPTYPE_E_INTERR | 0x3 | Interrupt
48258  *
48259  * Field Access Macros:
48260  *
48261  */
48262 /*
48263  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE
48264  *
48265  * Control
48266  */
48267 #define ALT_USB_HOST_HCCHAR11_EPTYPE_E_CTL 0x0
48268 /*
48269  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE
48270  *
48271  * Isochronous
48272  */
48273 #define ALT_USB_HOST_HCCHAR11_EPTYPE_E_ISOC 0x1
48274 /*
48275  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE
48276  *
48277  * Bulk
48278  */
48279 #define ALT_USB_HOST_HCCHAR11_EPTYPE_E_BULK 0x2
48280 /*
48281  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE
48282  *
48283  * Interrupt
48284  */
48285 #define ALT_USB_HOST_HCCHAR11_EPTYPE_E_INTERR 0x3
48286 
48287 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */
48288 #define ALT_USB_HOST_HCCHAR11_EPTYPE_LSB 18
48289 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */
48290 #define ALT_USB_HOST_HCCHAR11_EPTYPE_MSB 19
48291 /* The width in bits of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */
48292 #define ALT_USB_HOST_HCCHAR11_EPTYPE_WIDTH 2
48293 /* The mask used to set the ALT_USB_HOST_HCCHAR11_EPTYPE register field value. */
48294 #define ALT_USB_HOST_HCCHAR11_EPTYPE_SET_MSK 0x000c0000
48295 /* The mask used to clear the ALT_USB_HOST_HCCHAR11_EPTYPE register field value. */
48296 #define ALT_USB_HOST_HCCHAR11_EPTYPE_CLR_MSK 0xfff3ffff
48297 /* The reset value of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */
48298 #define ALT_USB_HOST_HCCHAR11_EPTYPE_RESET 0x0
48299 /* Extracts the ALT_USB_HOST_HCCHAR11_EPTYPE field value from a register. */
48300 #define ALT_USB_HOST_HCCHAR11_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
48301 /* Produces a ALT_USB_HOST_HCCHAR11_EPTYPE register field value suitable for setting the register. */
48302 #define ALT_USB_HOST_HCCHAR11_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
48303 
48304 /*
48305  * Field : ec
48306  *
48307  * Multi Count (MC) / Error Count (EC)
48308  *
48309  * When the Split Enable bit of the Host Channel-n Split Control
48310  *
48311  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
48312  *
48313  * the host the number of transactions that must be executed per
48314  *
48315  * microframe For this periodic endpoint. For non periodic transfers,
48316  *
48317  * this field is used only in DMA mode, and specifies the number
48318  *
48319  * packets to be fetched For this channel before the internal DMA
48320  *
48321  * engine changes arbitration.
48322  *
48323  * 2'b00: Reserved This field yields undefined results.
48324  *
48325  * 2'b01: 1 transaction
48326  *
48327  * 2'b10: 2 transactions to be issued For this endpoint per
48328  *
48329  * microframe
48330  *
48331  * 2'b11: 3 transactions to be issued For this endpoint per
48332  *
48333  * microframe
48334  *
48335  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
48336  *
48337  * number of immediate retries to be performed For a periodic split
48338  *
48339  * transactions on transaction errors. This field must be Set to at
48340  *
48341  * least 2'b01.
48342  *
48343  * Field Enumeration Values:
48344  *
48345  * Enum | Value | Description
48346  * :--------------------------------------|:------|:----------------------------------------------
48347  * ALT_USB_HOST_HCCHAR11_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
48348  * ALT_USB_HOST_HCCHAR11_EC_E_TRANSONE | 0x1 | 1 transaction
48349  * ALT_USB_HOST_HCCHAR11_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
48350  * : | | per microframe
48351  * ALT_USB_HOST_HCCHAR11_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
48352  * : | | per microframe
48353  *
48354  * Field Access Macros:
48355  *
48356  */
48357 /*
48358  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC
48359  *
48360  * Reserved This field yields undefined result
48361  */
48362 #define ALT_USB_HOST_HCCHAR11_EC_E_RSVD 0x0
48363 /*
48364  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC
48365  *
48366  * 1 transaction
48367  */
48368 #define ALT_USB_HOST_HCCHAR11_EC_E_TRANSONE 0x1
48369 /*
48370  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC
48371  *
48372  * 2 transactions to be issued for this endpoint per microframe
48373  */
48374 #define ALT_USB_HOST_HCCHAR11_EC_E_TRANSTWO 0x2
48375 /*
48376  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC
48377  *
48378  * 3 transactions to be issued for this endpoint per microframe
48379  */
48380 #define ALT_USB_HOST_HCCHAR11_EC_E_TRANSTHREE 0x3
48381 
48382 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EC register field. */
48383 #define ALT_USB_HOST_HCCHAR11_EC_LSB 20
48384 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EC register field. */
48385 #define ALT_USB_HOST_HCCHAR11_EC_MSB 21
48386 /* The width in bits of the ALT_USB_HOST_HCCHAR11_EC register field. */
48387 #define ALT_USB_HOST_HCCHAR11_EC_WIDTH 2
48388 /* The mask used to set the ALT_USB_HOST_HCCHAR11_EC register field value. */
48389 #define ALT_USB_HOST_HCCHAR11_EC_SET_MSK 0x00300000
48390 /* The mask used to clear the ALT_USB_HOST_HCCHAR11_EC register field value. */
48391 #define ALT_USB_HOST_HCCHAR11_EC_CLR_MSK 0xffcfffff
48392 /* The reset value of the ALT_USB_HOST_HCCHAR11_EC register field. */
48393 #define ALT_USB_HOST_HCCHAR11_EC_RESET 0x0
48394 /* Extracts the ALT_USB_HOST_HCCHAR11_EC field value from a register. */
48395 #define ALT_USB_HOST_HCCHAR11_EC_GET(value) (((value) & 0x00300000) >> 20)
48396 /* Produces a ALT_USB_HOST_HCCHAR11_EC register field value suitable for setting the register. */
48397 #define ALT_USB_HOST_HCCHAR11_EC_SET(value) (((value) << 20) & 0x00300000)
48398 
48399 /*
48400  * Field : devaddr
48401  *
48402  * Device Address (DevAddr)
48403  *
48404  * This field selects the specific device serving as the data source
48405  *
48406  * or sink.
48407  *
48408  * Field Access Macros:
48409  *
48410  */
48411 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */
48412 #define ALT_USB_HOST_HCCHAR11_DEVADDR_LSB 22
48413 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */
48414 #define ALT_USB_HOST_HCCHAR11_DEVADDR_MSB 28
48415 /* The width in bits of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */
48416 #define ALT_USB_HOST_HCCHAR11_DEVADDR_WIDTH 7
48417 /* The mask used to set the ALT_USB_HOST_HCCHAR11_DEVADDR register field value. */
48418 #define ALT_USB_HOST_HCCHAR11_DEVADDR_SET_MSK 0x1fc00000
48419 /* The mask used to clear the ALT_USB_HOST_HCCHAR11_DEVADDR register field value. */
48420 #define ALT_USB_HOST_HCCHAR11_DEVADDR_CLR_MSK 0xe03fffff
48421 /* The reset value of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */
48422 #define ALT_USB_HOST_HCCHAR11_DEVADDR_RESET 0x0
48423 /* Extracts the ALT_USB_HOST_HCCHAR11_DEVADDR field value from a register. */
48424 #define ALT_USB_HOST_HCCHAR11_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
48425 /* Produces a ALT_USB_HOST_HCCHAR11_DEVADDR register field value suitable for setting the register. */
48426 #define ALT_USB_HOST_HCCHAR11_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
48427 
48428 /*
48429  * Field : oddfrm
48430  *
48431  * Odd Frame (OddFrm)
48432  *
48433  * This field is set (reset) by the application to indicate that the OTG host must
48434  * perform
48435  *
48436  * a transfer in an odd (micro)frame. This field is applicable for only periodic
48437  *
48438  * (isochronous and interrupt) transactions.
48439  *
48440  * 1'b0: Even (micro)frame
48441  *
48442  * 1'b1: Odd (micro)frame
48443  *
48444  * Field Access Macros:
48445  *
48446  */
48447 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_ODDFRM register field. */
48448 #define ALT_USB_HOST_HCCHAR11_ODDFRM_LSB 29
48449 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_ODDFRM register field. */
48450 #define ALT_USB_HOST_HCCHAR11_ODDFRM_MSB 29
48451 /* The width in bits of the ALT_USB_HOST_HCCHAR11_ODDFRM register field. */
48452 #define ALT_USB_HOST_HCCHAR11_ODDFRM_WIDTH 1
48453 /* The mask used to set the ALT_USB_HOST_HCCHAR11_ODDFRM register field value. */
48454 #define ALT_USB_HOST_HCCHAR11_ODDFRM_SET_MSK 0x20000000
48455 /* The mask used to clear the ALT_USB_HOST_HCCHAR11_ODDFRM register field value. */
48456 #define ALT_USB_HOST_HCCHAR11_ODDFRM_CLR_MSK 0xdfffffff
48457 /* The reset value of the ALT_USB_HOST_HCCHAR11_ODDFRM register field. */
48458 #define ALT_USB_HOST_HCCHAR11_ODDFRM_RESET 0x0
48459 /* Extracts the ALT_USB_HOST_HCCHAR11_ODDFRM field value from a register. */
48460 #define ALT_USB_HOST_HCCHAR11_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
48461 /* Produces a ALT_USB_HOST_HCCHAR11_ODDFRM register field value suitable for setting the register. */
48462 #define ALT_USB_HOST_HCCHAR11_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
48463 
48464 /*
48465  * Field : chdis
48466  *
48467  * Channel Disable (ChDis)
48468  *
48469  * The application sets this bit to stop transmitting/receiving data
48470  *
48471  * on a channel, even before the transfer For that channel is
48472  *
48473  * complete. The application must wait For the Channel Disabled
48474  *
48475  * interrupt before treating the channel as disabled.
48476  *
48477  * Field Enumeration Values:
48478  *
48479  * Enum | Value | Description
48480  * :------------------------------------|:------|:----------------------------
48481  * ALT_USB_HOST_HCCHAR11_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
48482  * ALT_USB_HOST_HCCHAR11_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
48483  *
48484  * Field Access Macros:
48485  *
48486  */
48487 /*
48488  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHDIS
48489  *
48490  * Transmit/Recieve normal
48491  */
48492 #define ALT_USB_HOST_HCCHAR11_CHDIS_E_INACT 0x0
48493 /*
48494  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHDIS
48495  *
48496  * Stop transmitting/receiving
48497  */
48498 #define ALT_USB_HOST_HCCHAR11_CHDIS_E_ACT 0x1
48499 
48500 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */
48501 #define ALT_USB_HOST_HCCHAR11_CHDIS_LSB 30
48502 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */
48503 #define ALT_USB_HOST_HCCHAR11_CHDIS_MSB 30
48504 /* The width in bits of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */
48505 #define ALT_USB_HOST_HCCHAR11_CHDIS_WIDTH 1
48506 /* The mask used to set the ALT_USB_HOST_HCCHAR11_CHDIS register field value. */
48507 #define ALT_USB_HOST_HCCHAR11_CHDIS_SET_MSK 0x40000000
48508 /* The mask used to clear the ALT_USB_HOST_HCCHAR11_CHDIS register field value. */
48509 #define ALT_USB_HOST_HCCHAR11_CHDIS_CLR_MSK 0xbfffffff
48510 /* The reset value of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */
48511 #define ALT_USB_HOST_HCCHAR11_CHDIS_RESET 0x0
48512 /* Extracts the ALT_USB_HOST_HCCHAR11_CHDIS field value from a register. */
48513 #define ALT_USB_HOST_HCCHAR11_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
48514 /* Produces a ALT_USB_HOST_HCCHAR11_CHDIS register field value suitable for setting the register. */
48515 #define ALT_USB_HOST_HCCHAR11_CHDIS_SET(value) (((value) << 30) & 0x40000000)
48516 
48517 /*
48518  * Field : chena
48519  *
48520  * Channel Enable (ChEna)
48521  *
48522  * When Scatter/Gather mode is enabled
48523  *
48524  * 1'b0: Indicates that the descriptor structure is not yet ready.
48525  *
48526  * 1'b1: Indicates that the descriptor structure and data buffer with
48527  *
48528  * data is setup and this channel can access the descriptor.
48529  *
48530  * When Scatter/Gather mode is disabled
48531  *
48532  * This field is set by the application and cleared by the OTG host.
48533  *
48534  * 1'b0: Channel disabled
48535  *
48536  * 1'b1: Channel enabled
48537  *
48538  * Field Enumeration Values:
48539  *
48540  * Enum | Value | Description
48541  * :------------------------------------|:------|:-------------------------------------------------
48542  * ALT_USB_HOST_HCCHAR11_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
48543  * : | | yet ready
48544  * ALT_USB_HOST_HCCHAR11_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
48545  * : | | data buffer with data is setup and this
48546  * : | | channel can access the descriptor
48547  *
48548  * Field Access Macros:
48549  *
48550  */
48551 /*
48552  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHENA
48553  *
48554  * Indicates that the descriptor structure is not yet ready
48555  */
48556 #define ALT_USB_HOST_HCCHAR11_CHENA_E_INACT 0x0
48557 /*
48558  * Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHENA
48559  *
48560  * Indicates that the descriptor structure and data buffer with data is
48561  * setup and this channel can access the descriptor
48562  */
48563 #define ALT_USB_HOST_HCCHAR11_CHENA_E_ACT 0x1
48564 
48565 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_CHENA register field. */
48566 #define ALT_USB_HOST_HCCHAR11_CHENA_LSB 31
48567 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_CHENA register field. */
48568 #define ALT_USB_HOST_HCCHAR11_CHENA_MSB 31
48569 /* The width in bits of the ALT_USB_HOST_HCCHAR11_CHENA register field. */
48570 #define ALT_USB_HOST_HCCHAR11_CHENA_WIDTH 1
48571 /* The mask used to set the ALT_USB_HOST_HCCHAR11_CHENA register field value. */
48572 #define ALT_USB_HOST_HCCHAR11_CHENA_SET_MSK 0x80000000
48573 /* The mask used to clear the ALT_USB_HOST_HCCHAR11_CHENA register field value. */
48574 #define ALT_USB_HOST_HCCHAR11_CHENA_CLR_MSK 0x7fffffff
48575 /* The reset value of the ALT_USB_HOST_HCCHAR11_CHENA register field. */
48576 #define ALT_USB_HOST_HCCHAR11_CHENA_RESET 0x0
48577 /* Extracts the ALT_USB_HOST_HCCHAR11_CHENA field value from a register. */
48578 #define ALT_USB_HOST_HCCHAR11_CHENA_GET(value) (((value) & 0x80000000) >> 31)
48579 /* Produces a ALT_USB_HOST_HCCHAR11_CHENA register field value suitable for setting the register. */
48580 #define ALT_USB_HOST_HCCHAR11_CHENA_SET(value) (((value) << 31) & 0x80000000)
48581 
48582 #ifndef __ASSEMBLY__
48583 /*
48584  * WARNING: The C register and register group struct declarations are provided for
48585  * convenience and illustrative purposes. They should, however, be used with
48586  * caution as the C language standard provides no guarantees about the alignment or
48587  * atomicity of device memory accesses. The recommended practice for writing
48588  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
48589  * alt_write_word() functions.
48590  *
48591  * The struct declaration for register ALT_USB_HOST_HCCHAR11.
48592  */
48593 struct ALT_USB_HOST_HCCHAR11_s
48594 {
48595  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR11_MPS */
48596  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR11_EPNUM */
48597  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR11_EPDIR */
48598  uint32_t : 1; /* *UNDEFINED* */
48599  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR11_LSPDDEV */
48600  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR11_EPTYPE */
48601  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR11_EC */
48602  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR11_DEVADDR */
48603  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR11_ODDFRM */
48604  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR11_CHDIS */
48605  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR11_CHENA */
48606 };
48607 
48608 /* The typedef declaration for register ALT_USB_HOST_HCCHAR11. */
48609 typedef volatile struct ALT_USB_HOST_HCCHAR11_s ALT_USB_HOST_HCCHAR11_t;
48610 #endif /* __ASSEMBLY__ */
48611 
48612 /* The reset value of the ALT_USB_HOST_HCCHAR11 register. */
48613 #define ALT_USB_HOST_HCCHAR11_RESET 0x00000000
48614 /* The byte offset of the ALT_USB_HOST_HCCHAR11 register from the beginning of the component. */
48615 #define ALT_USB_HOST_HCCHAR11_OFST 0x260
48616 /* The address of the ALT_USB_HOST_HCCHAR11 register. */
48617 #define ALT_USB_HOST_HCCHAR11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR11_OFST))
48618 
48619 /*
48620  * Register : hcsplt11
48621  *
48622  * Host Channel 11 Split Control Register
48623  *
48624  * Register Layout
48625  *
48626  * Bits | Access | Reset | Description
48627  * :--------|:-------|:------|:-------------------------------
48628  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT11_PRTADDR
48629  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT11_HUBADDR
48630  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT11_XACTPOS
48631  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT11_COMPSPLT
48632  * [30:17] | ??? | 0x0 | *UNDEFINED*
48633  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT11_SPLTENA
48634  *
48635  */
48636 /*
48637  * Field : prtaddr
48638  *
48639  * Port Address (PrtAddr)
48640  *
48641  * This field is the port number of the recipient transaction
48642  *
48643  * translator.
48644  *
48645  * Field Access Macros:
48646  *
48647  */
48648 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */
48649 #define ALT_USB_HOST_HCSPLT11_PRTADDR_LSB 0
48650 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */
48651 #define ALT_USB_HOST_HCSPLT11_PRTADDR_MSB 6
48652 /* The width in bits of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */
48653 #define ALT_USB_HOST_HCSPLT11_PRTADDR_WIDTH 7
48654 /* The mask used to set the ALT_USB_HOST_HCSPLT11_PRTADDR register field value. */
48655 #define ALT_USB_HOST_HCSPLT11_PRTADDR_SET_MSK 0x0000007f
48656 /* The mask used to clear the ALT_USB_HOST_HCSPLT11_PRTADDR register field value. */
48657 #define ALT_USB_HOST_HCSPLT11_PRTADDR_CLR_MSK 0xffffff80
48658 /* The reset value of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */
48659 #define ALT_USB_HOST_HCSPLT11_PRTADDR_RESET 0x0
48660 /* Extracts the ALT_USB_HOST_HCSPLT11_PRTADDR field value from a register. */
48661 #define ALT_USB_HOST_HCSPLT11_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
48662 /* Produces a ALT_USB_HOST_HCSPLT11_PRTADDR register field value suitable for setting the register. */
48663 #define ALT_USB_HOST_HCSPLT11_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
48664 
48665 /*
48666  * Field : hubaddr
48667  *
48668  * Hub Address (HubAddr)
48669  *
48670  * This field holds the device address of the transaction translator's
48671  *
48672  * hub.
48673  *
48674  * Field Access Macros:
48675  *
48676  */
48677 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */
48678 #define ALT_USB_HOST_HCSPLT11_HUBADDR_LSB 7
48679 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */
48680 #define ALT_USB_HOST_HCSPLT11_HUBADDR_MSB 13
48681 /* The width in bits of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */
48682 #define ALT_USB_HOST_HCSPLT11_HUBADDR_WIDTH 7
48683 /* The mask used to set the ALT_USB_HOST_HCSPLT11_HUBADDR register field value. */
48684 #define ALT_USB_HOST_HCSPLT11_HUBADDR_SET_MSK 0x00003f80
48685 /* The mask used to clear the ALT_USB_HOST_HCSPLT11_HUBADDR register field value. */
48686 #define ALT_USB_HOST_HCSPLT11_HUBADDR_CLR_MSK 0xffffc07f
48687 /* The reset value of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */
48688 #define ALT_USB_HOST_HCSPLT11_HUBADDR_RESET 0x0
48689 /* Extracts the ALT_USB_HOST_HCSPLT11_HUBADDR field value from a register. */
48690 #define ALT_USB_HOST_HCSPLT11_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
48691 /* Produces a ALT_USB_HOST_HCSPLT11_HUBADDR register field value suitable for setting the register. */
48692 #define ALT_USB_HOST_HCSPLT11_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
48693 
48694 /*
48695  * Field : xactpos
48696  *
48697  * Transaction Position (XactPos)
48698  *
48699  * This field is used to determine whether to send all, first, middle,
48700  *
48701  * or last payloads with each OUT transaction.
48702  *
48703  * 2'b11: All. This is the entire data payload is of this transaction
48704  *
48705  * (which is less than or equal to 188 bytes).
48706  *
48707  * 2'b10: Begin. This is the first data payload of this transaction
48708  *
48709  * (which is larger than 188 bytes).
48710  *
48711  * 2'b00: Mid. This is the middle payload of this transaction
48712  *
48713  * (which is larger than 188 bytes).
48714  *
48715  * 2'b01: End. This is the last payload of this transaction (which
48716  *
48717  * is larger than 188 bytes).
48718  *
48719  * Field Enumeration Values:
48720  *
48721  * Enum | Value | Description
48722  * :---------------------------------------|:------|:------------------------------------------------
48723  * ALT_USB_HOST_HCSPLT11_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
48724  * : | | transaction (which is larger than 188 bytes)
48725  * ALT_USB_HOST_HCSPLT11_XACTPOS_E_END | 0x1 | End. This is the last payload of this
48726  * : | | transaction (which is larger than 188 bytes)
48727  * ALT_USB_HOST_HCSPLT11_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
48728  * : | | transaction (which is larger than 188 bytes)
48729  * ALT_USB_HOST_HCSPLT11_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
48730  * : | | transaction (which is less than or equal to 188
48731  * : | | bytes)
48732  *
48733  * Field Access Macros:
48734  *
48735  */
48736 /*
48737  * Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS
48738  *
48739  * Mid. This is the middle payload of this transaction (which is larger than 188
48740  * bytes)
48741  */
48742 #define ALT_USB_HOST_HCSPLT11_XACTPOS_E_MIDDLE 0x0
48743 /*
48744  * Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS
48745  *
48746  * End. This is the last payload of this transaction (which is larger than 188
48747  * bytes)
48748  */
48749 #define ALT_USB_HOST_HCSPLT11_XACTPOS_E_END 0x1
48750 /*
48751  * Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS
48752  *
48753  * Begin. This is the first data payload of this transaction (which is larger than
48754  * 188 bytes)
48755  */
48756 #define ALT_USB_HOST_HCSPLT11_XACTPOS_E_BEGIN 0x2
48757 /*
48758  * Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS
48759  *
48760  * All. This is the entire data payload is of this transaction (which is less than
48761  * or equal to 188 bytes)
48762  */
48763 #define ALT_USB_HOST_HCSPLT11_XACTPOS_E_ALL 0x3
48764 
48765 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */
48766 #define ALT_USB_HOST_HCSPLT11_XACTPOS_LSB 14
48767 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */
48768 #define ALT_USB_HOST_HCSPLT11_XACTPOS_MSB 15
48769 /* The width in bits of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */
48770 #define ALT_USB_HOST_HCSPLT11_XACTPOS_WIDTH 2
48771 /* The mask used to set the ALT_USB_HOST_HCSPLT11_XACTPOS register field value. */
48772 #define ALT_USB_HOST_HCSPLT11_XACTPOS_SET_MSK 0x0000c000
48773 /* The mask used to clear the ALT_USB_HOST_HCSPLT11_XACTPOS register field value. */
48774 #define ALT_USB_HOST_HCSPLT11_XACTPOS_CLR_MSK 0xffff3fff
48775 /* The reset value of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */
48776 #define ALT_USB_HOST_HCSPLT11_XACTPOS_RESET 0x0
48777 /* Extracts the ALT_USB_HOST_HCSPLT11_XACTPOS field value from a register. */
48778 #define ALT_USB_HOST_HCSPLT11_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
48779 /* Produces a ALT_USB_HOST_HCSPLT11_XACTPOS register field value suitable for setting the register. */
48780 #define ALT_USB_HOST_HCSPLT11_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
48781 
48782 /*
48783  * Field : compsplt
48784  *
48785  * Do Complete Split (CompSplt)
48786  *
48787  * The application sets this field to request the OTG host to perform
48788  *
48789  * a complete split transaction.
48790  *
48791  * Field Enumeration Values:
48792  *
48793  * Enum | Value | Description
48794  * :-----------------------------------------|:------|:---------------------
48795  * ALT_USB_HOST_HCSPLT11_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
48796  * ALT_USB_HOST_HCSPLT11_COMPSPLT_E_SPLIT | 0x1 | Split transaction
48797  *
48798  * Field Access Macros:
48799  *
48800  */
48801 /*
48802  * Enumerated value for register field ALT_USB_HOST_HCSPLT11_COMPSPLT
48803  *
48804  * No split transaction
48805  */
48806 #define ALT_USB_HOST_HCSPLT11_COMPSPLT_E_NOSPLIT 0x0
48807 /*
48808  * Enumerated value for register field ALT_USB_HOST_HCSPLT11_COMPSPLT
48809  *
48810  * Split transaction
48811  */
48812 #define ALT_USB_HOST_HCSPLT11_COMPSPLT_E_SPLIT 0x1
48813 
48814 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */
48815 #define ALT_USB_HOST_HCSPLT11_COMPSPLT_LSB 16
48816 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */
48817 #define ALT_USB_HOST_HCSPLT11_COMPSPLT_MSB 16
48818 /* The width in bits of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */
48819 #define ALT_USB_HOST_HCSPLT11_COMPSPLT_WIDTH 1
48820 /* The mask used to set the ALT_USB_HOST_HCSPLT11_COMPSPLT register field value. */
48821 #define ALT_USB_HOST_HCSPLT11_COMPSPLT_SET_MSK 0x00010000
48822 /* The mask used to clear the ALT_USB_HOST_HCSPLT11_COMPSPLT register field value. */
48823 #define ALT_USB_HOST_HCSPLT11_COMPSPLT_CLR_MSK 0xfffeffff
48824 /* The reset value of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */
48825 #define ALT_USB_HOST_HCSPLT11_COMPSPLT_RESET 0x0
48826 /* Extracts the ALT_USB_HOST_HCSPLT11_COMPSPLT field value from a register. */
48827 #define ALT_USB_HOST_HCSPLT11_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
48828 /* Produces a ALT_USB_HOST_HCSPLT11_COMPSPLT register field value suitable for setting the register. */
48829 #define ALT_USB_HOST_HCSPLT11_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
48830 
48831 /*
48832  * Field : spltena
48833  *
48834  * Split Enable (SpltEna)
48835  *
48836  * The application sets this field to indicate that this channel is
48837  *
48838  * enabled to perform split transactions.
48839  *
48840  * Field Enumeration Values:
48841  *
48842  * Enum | Value | Description
48843  * :-------------------------------------|:------|:------------------
48844  * ALT_USB_HOST_HCSPLT11_SPLTENA_E_DISD | 0x0 | Split not enabled
48845  * ALT_USB_HOST_HCSPLT11_SPLTENA_E_END | 0x1 | Split enabled
48846  *
48847  * Field Access Macros:
48848  *
48849  */
48850 /*
48851  * Enumerated value for register field ALT_USB_HOST_HCSPLT11_SPLTENA
48852  *
48853  * Split not enabled
48854  */
48855 #define ALT_USB_HOST_HCSPLT11_SPLTENA_E_DISD 0x0
48856 /*
48857  * Enumerated value for register field ALT_USB_HOST_HCSPLT11_SPLTENA
48858  *
48859  * Split enabled
48860  */
48861 #define ALT_USB_HOST_HCSPLT11_SPLTENA_E_END 0x1
48862 
48863 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */
48864 #define ALT_USB_HOST_HCSPLT11_SPLTENA_LSB 31
48865 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */
48866 #define ALT_USB_HOST_HCSPLT11_SPLTENA_MSB 31
48867 /* The width in bits of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */
48868 #define ALT_USB_HOST_HCSPLT11_SPLTENA_WIDTH 1
48869 /* The mask used to set the ALT_USB_HOST_HCSPLT11_SPLTENA register field value. */
48870 #define ALT_USB_HOST_HCSPLT11_SPLTENA_SET_MSK 0x80000000
48871 /* The mask used to clear the ALT_USB_HOST_HCSPLT11_SPLTENA register field value. */
48872 #define ALT_USB_HOST_HCSPLT11_SPLTENA_CLR_MSK 0x7fffffff
48873 /* The reset value of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */
48874 #define ALT_USB_HOST_HCSPLT11_SPLTENA_RESET 0x0
48875 /* Extracts the ALT_USB_HOST_HCSPLT11_SPLTENA field value from a register. */
48876 #define ALT_USB_HOST_HCSPLT11_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
48877 /* Produces a ALT_USB_HOST_HCSPLT11_SPLTENA register field value suitable for setting the register. */
48878 #define ALT_USB_HOST_HCSPLT11_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
48879 
48880 #ifndef __ASSEMBLY__
48881 /*
48882  * WARNING: The C register and register group struct declarations are provided for
48883  * convenience and illustrative purposes. They should, however, be used with
48884  * caution as the C language standard provides no guarantees about the alignment or
48885  * atomicity of device memory accesses. The recommended practice for writing
48886  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
48887  * alt_write_word() functions.
48888  *
48889  * The struct declaration for register ALT_USB_HOST_HCSPLT11.
48890  */
48891 struct ALT_USB_HOST_HCSPLT11_s
48892 {
48893  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT11_PRTADDR */
48894  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT11_HUBADDR */
48895  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT11_XACTPOS */
48896  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT11_COMPSPLT */
48897  uint32_t : 14; /* *UNDEFINED* */
48898  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT11_SPLTENA */
48899 };
48900 
48901 /* The typedef declaration for register ALT_USB_HOST_HCSPLT11. */
48902 typedef volatile struct ALT_USB_HOST_HCSPLT11_s ALT_USB_HOST_HCSPLT11_t;
48903 #endif /* __ASSEMBLY__ */
48904 
48905 /* The reset value of the ALT_USB_HOST_HCSPLT11 register. */
48906 #define ALT_USB_HOST_HCSPLT11_RESET 0x00000000
48907 /* The byte offset of the ALT_USB_HOST_HCSPLT11 register from the beginning of the component. */
48908 #define ALT_USB_HOST_HCSPLT11_OFST 0x264
48909 /* The address of the ALT_USB_HOST_HCSPLT11 register. */
48910 #define ALT_USB_HOST_HCSPLT11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT11_OFST))
48911 
48912 /*
48913  * Register : hcint11
48914  *
48915  * Host Channel 11 Interrupt Register
48916  *
48917  * Register Layout
48918  *
48919  * Bits | Access | Reset | Description
48920  * :--------|:-------|:------|:---------------------------------------
48921  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT11_XFERCOMPL
48922  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT11_CHHLTD
48923  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT11_AHBERR
48924  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT11_STALL
48925  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT11_NAK
48926  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT11_ACK
48927  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT11_NYET
48928  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT11_XACTERR
48929  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT11_BBLERR
48930  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT11_FRMOVRUN
48931  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT11_DATATGLERR
48932  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT11_BNAINTR
48933  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT11_XCS_XACT_ERR
48934  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR
48935  * [31:14] | ??? | 0x0 | *UNDEFINED*
48936  *
48937  */
48938 /*
48939  * Field : xfercompl
48940  *
48941  * Transfer Completed (XferCompl)
48942  *
48943  * Transfer completed normally without any errors.This bit can be set only by the
48944  * core and the application should write 1 to clear it.
48945  *
48946  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
48947  *
48948  * completed with IOC bit set in its descriptor.
48949  *
48950  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
48951  * without
48952  *
48953  * any errors.
48954  *
48955  * Field Enumeration Values:
48956  *
48957  * Enum | Value | Description
48958  * :---------------------------------------|:------|:-----------------------------------------------
48959  * ALT_USB_HOST_HCINT11_XFERCOMPL_E_INACT | 0x0 | No transfer
48960  * ALT_USB_HOST_HCINT11_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
48961  *
48962  * Field Access Macros:
48963  *
48964  */
48965 /*
48966  * Enumerated value for register field ALT_USB_HOST_HCINT11_XFERCOMPL
48967  *
48968  * No transfer
48969  */
48970 #define ALT_USB_HOST_HCINT11_XFERCOMPL_E_INACT 0x0
48971 /*
48972  * Enumerated value for register field ALT_USB_HOST_HCINT11_XFERCOMPL
48973  *
48974  * Transfer completed normally without any errors
48975  */
48976 #define ALT_USB_HOST_HCINT11_XFERCOMPL_E_ACT 0x1
48977 
48978 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */
48979 #define ALT_USB_HOST_HCINT11_XFERCOMPL_LSB 0
48980 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */
48981 #define ALT_USB_HOST_HCINT11_XFERCOMPL_MSB 0
48982 /* The width in bits of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */
48983 #define ALT_USB_HOST_HCINT11_XFERCOMPL_WIDTH 1
48984 /* The mask used to set the ALT_USB_HOST_HCINT11_XFERCOMPL register field value. */
48985 #define ALT_USB_HOST_HCINT11_XFERCOMPL_SET_MSK 0x00000001
48986 /* The mask used to clear the ALT_USB_HOST_HCINT11_XFERCOMPL register field value. */
48987 #define ALT_USB_HOST_HCINT11_XFERCOMPL_CLR_MSK 0xfffffffe
48988 /* The reset value of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */
48989 #define ALT_USB_HOST_HCINT11_XFERCOMPL_RESET 0x0
48990 /* Extracts the ALT_USB_HOST_HCINT11_XFERCOMPL field value from a register. */
48991 #define ALT_USB_HOST_HCINT11_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
48992 /* Produces a ALT_USB_HOST_HCINT11_XFERCOMPL register field value suitable for setting the register. */
48993 #define ALT_USB_HOST_HCINT11_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
48994 
48995 /*
48996  * Field : chhltd
48997  *
48998  * Channel Halted (ChHltd)
48999  *
49000  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
49001  * either because of any USB transaction error or in response to disable request by
49002  * the application or because of a completed transfer.
49003  *
49004  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
49005  * the following
49006  *
49007  * . EOL being set in descriptor
49008  *
49009  * . AHB error
49010  *
49011  * . Excessive transaction errors
49012  *
49013  * . Babble
49014  *
49015  * . Stall
49016  *
49017  * Field Enumeration Values:
49018  *
49019  * Enum | Value | Description
49020  * :------------------------------------|:------|:-------------------
49021  * ALT_USB_HOST_HCINT11_CHHLTD_E_INACT | 0x0 | Channel not halted
49022  * ALT_USB_HOST_HCINT11_CHHLTD_E_ACT | 0x1 | Channel Halted
49023  *
49024  * Field Access Macros:
49025  *
49026  */
49027 /*
49028  * Enumerated value for register field ALT_USB_HOST_HCINT11_CHHLTD
49029  *
49030  * Channel not halted
49031  */
49032 #define ALT_USB_HOST_HCINT11_CHHLTD_E_INACT 0x0
49033 /*
49034  * Enumerated value for register field ALT_USB_HOST_HCINT11_CHHLTD
49035  *
49036  * Channel Halted
49037  */
49038 #define ALT_USB_HOST_HCINT11_CHHLTD_E_ACT 0x1
49039 
49040 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_CHHLTD register field. */
49041 #define ALT_USB_HOST_HCINT11_CHHLTD_LSB 1
49042 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_CHHLTD register field. */
49043 #define ALT_USB_HOST_HCINT11_CHHLTD_MSB 1
49044 /* The width in bits of the ALT_USB_HOST_HCINT11_CHHLTD register field. */
49045 #define ALT_USB_HOST_HCINT11_CHHLTD_WIDTH 1
49046 /* The mask used to set the ALT_USB_HOST_HCINT11_CHHLTD register field value. */
49047 #define ALT_USB_HOST_HCINT11_CHHLTD_SET_MSK 0x00000002
49048 /* The mask used to clear the ALT_USB_HOST_HCINT11_CHHLTD register field value. */
49049 #define ALT_USB_HOST_HCINT11_CHHLTD_CLR_MSK 0xfffffffd
49050 /* The reset value of the ALT_USB_HOST_HCINT11_CHHLTD register field. */
49051 #define ALT_USB_HOST_HCINT11_CHHLTD_RESET 0x0
49052 /* Extracts the ALT_USB_HOST_HCINT11_CHHLTD field value from a register. */
49053 #define ALT_USB_HOST_HCINT11_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
49054 /* Produces a ALT_USB_HOST_HCINT11_CHHLTD register field value suitable for setting the register. */
49055 #define ALT_USB_HOST_HCINT11_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
49056 
49057 /*
49058  * Field : ahberr
49059  *
49060  * AHB Error (AHBErr)
49061  *
49062  * This is generated only in Internal DMA mode when there is an
49063  *
49064  * AHB error during AHB read/write. The application can read the
49065  *
49066  * corresponding channel's DMA address register to get the error
49067  *
49068  * address.
49069  *
49070  * Field Enumeration Values:
49071  *
49072  * Enum | Value | Description
49073  * :------------------------------------|:------|:--------------------------------
49074  * ALT_USB_HOST_HCINT11_AHBERR_E_INACT | 0x0 | No AHB error
49075  * ALT_USB_HOST_HCINT11_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
49076  *
49077  * Field Access Macros:
49078  *
49079  */
49080 /*
49081  * Enumerated value for register field ALT_USB_HOST_HCINT11_AHBERR
49082  *
49083  * No AHB error
49084  */
49085 #define ALT_USB_HOST_HCINT11_AHBERR_E_INACT 0x0
49086 /*
49087  * Enumerated value for register field ALT_USB_HOST_HCINT11_AHBERR
49088  *
49089  * AHB error during AHB read/write
49090  */
49091 #define ALT_USB_HOST_HCINT11_AHBERR_E_ACT 0x1
49092 
49093 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_AHBERR register field. */
49094 #define ALT_USB_HOST_HCINT11_AHBERR_LSB 2
49095 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_AHBERR register field. */
49096 #define ALT_USB_HOST_HCINT11_AHBERR_MSB 2
49097 /* The width in bits of the ALT_USB_HOST_HCINT11_AHBERR register field. */
49098 #define ALT_USB_HOST_HCINT11_AHBERR_WIDTH 1
49099 /* The mask used to set the ALT_USB_HOST_HCINT11_AHBERR register field value. */
49100 #define ALT_USB_HOST_HCINT11_AHBERR_SET_MSK 0x00000004
49101 /* The mask used to clear the ALT_USB_HOST_HCINT11_AHBERR register field value. */
49102 #define ALT_USB_HOST_HCINT11_AHBERR_CLR_MSK 0xfffffffb
49103 /* The reset value of the ALT_USB_HOST_HCINT11_AHBERR register field. */
49104 #define ALT_USB_HOST_HCINT11_AHBERR_RESET 0x0
49105 /* Extracts the ALT_USB_HOST_HCINT11_AHBERR field value from a register. */
49106 #define ALT_USB_HOST_HCINT11_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
49107 /* Produces a ALT_USB_HOST_HCINT11_AHBERR register field value suitable for setting the register. */
49108 #define ALT_USB_HOST_HCINT11_AHBERR_SET(value) (((value) << 2) & 0x00000004)
49109 
49110 /*
49111  * Field : stall
49112  *
49113  * STALL Response Received Interrupt (STALL)
49114  *
49115  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
49116  *
49117  * in the core.This bit can be set only by the core and the application should
49118  * write 1 to clear
49119  *
49120  * it.
49121  *
49122  * Field Enumeration Values:
49123  *
49124  * Enum | Value | Description
49125  * :-----------------------------------|:------|:-------------------
49126  * ALT_USB_HOST_HCINT11_STALL_E_INACT | 0x0 | No Stall Interrupt
49127  * ALT_USB_HOST_HCINT11_STALL_E_ACT | 0x1 | Stall Interrupt
49128  *
49129  * Field Access Macros:
49130  *
49131  */
49132 /*
49133  * Enumerated value for register field ALT_USB_HOST_HCINT11_STALL
49134  *
49135  * No Stall Interrupt
49136  */
49137 #define ALT_USB_HOST_HCINT11_STALL_E_INACT 0x0
49138 /*
49139  * Enumerated value for register field ALT_USB_HOST_HCINT11_STALL
49140  *
49141  * Stall Interrupt
49142  */
49143 #define ALT_USB_HOST_HCINT11_STALL_E_ACT 0x1
49144 
49145 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_STALL register field. */
49146 #define ALT_USB_HOST_HCINT11_STALL_LSB 3
49147 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_STALL register field. */
49148 #define ALT_USB_HOST_HCINT11_STALL_MSB 3
49149 /* The width in bits of the ALT_USB_HOST_HCINT11_STALL register field. */
49150 #define ALT_USB_HOST_HCINT11_STALL_WIDTH 1
49151 /* The mask used to set the ALT_USB_HOST_HCINT11_STALL register field value. */
49152 #define ALT_USB_HOST_HCINT11_STALL_SET_MSK 0x00000008
49153 /* The mask used to clear the ALT_USB_HOST_HCINT11_STALL register field value. */
49154 #define ALT_USB_HOST_HCINT11_STALL_CLR_MSK 0xfffffff7
49155 /* The reset value of the ALT_USB_HOST_HCINT11_STALL register field. */
49156 #define ALT_USB_HOST_HCINT11_STALL_RESET 0x0
49157 /* Extracts the ALT_USB_HOST_HCINT11_STALL field value from a register. */
49158 #define ALT_USB_HOST_HCINT11_STALL_GET(value) (((value) & 0x00000008) >> 3)
49159 /* Produces a ALT_USB_HOST_HCINT11_STALL register field value suitable for setting the register. */
49160 #define ALT_USB_HOST_HCINT11_STALL_SET(value) (((value) << 3) & 0x00000008)
49161 
49162 /*
49163  * Field : nak
49164  *
49165  * NAK Response Received Interrupt (NAK)
49166  *
49167  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
49168  *
49169  * in the core.This bit can be set only by the core and the application should
49170  * write 1 to clear
49171  *
49172  * it.
49173  *
49174  * Field Enumeration Values:
49175  *
49176  * Enum | Value | Description
49177  * :---------------------------------|:------|:-----------------------------------
49178  * ALT_USB_HOST_HCINT11_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
49179  * ALT_USB_HOST_HCINT11_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
49180  *
49181  * Field Access Macros:
49182  *
49183  */
49184 /*
49185  * Enumerated value for register field ALT_USB_HOST_HCINT11_NAK
49186  *
49187  * No NAK Response Received Interrupt
49188  */
49189 #define ALT_USB_HOST_HCINT11_NAK_E_INACT 0x0
49190 /*
49191  * Enumerated value for register field ALT_USB_HOST_HCINT11_NAK
49192  *
49193  * NAK Response Received Interrupt
49194  */
49195 #define ALT_USB_HOST_HCINT11_NAK_E_ACT 0x1
49196 
49197 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_NAK register field. */
49198 #define ALT_USB_HOST_HCINT11_NAK_LSB 4
49199 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_NAK register field. */
49200 #define ALT_USB_HOST_HCINT11_NAK_MSB 4
49201 /* The width in bits of the ALT_USB_HOST_HCINT11_NAK register field. */
49202 #define ALT_USB_HOST_HCINT11_NAK_WIDTH 1
49203 /* The mask used to set the ALT_USB_HOST_HCINT11_NAK register field value. */
49204 #define ALT_USB_HOST_HCINT11_NAK_SET_MSK 0x00000010
49205 /* The mask used to clear the ALT_USB_HOST_HCINT11_NAK register field value. */
49206 #define ALT_USB_HOST_HCINT11_NAK_CLR_MSK 0xffffffef
49207 /* The reset value of the ALT_USB_HOST_HCINT11_NAK register field. */
49208 #define ALT_USB_HOST_HCINT11_NAK_RESET 0x0
49209 /* Extracts the ALT_USB_HOST_HCINT11_NAK field value from a register. */
49210 #define ALT_USB_HOST_HCINT11_NAK_GET(value) (((value) & 0x00000010) >> 4)
49211 /* Produces a ALT_USB_HOST_HCINT11_NAK register field value suitable for setting the register. */
49212 #define ALT_USB_HOST_HCINT11_NAK_SET(value) (((value) << 4) & 0x00000010)
49213 
49214 /*
49215  * Field : ack
49216  *
49217  * ACK Response Received/Transmitted Interrupt (ACK)
49218  *
49219  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
49220  *
49221  * in the core.This bit can be set only by the core and the application should
49222  * write 1 to clear
49223  *
49224  * it.
49225  *
49226  * Field Enumeration Values:
49227  *
49228  * Enum | Value | Description
49229  * :---------------------------------|:------|:-----------------------------------------------
49230  * ALT_USB_HOST_HCINT11_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
49231  * ALT_USB_HOST_HCINT11_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
49232  *
49233  * Field Access Macros:
49234  *
49235  */
49236 /*
49237  * Enumerated value for register field ALT_USB_HOST_HCINT11_ACK
49238  *
49239  * No ACK Response Received Transmitted Interrupt
49240  */
49241 #define ALT_USB_HOST_HCINT11_ACK_E_INACT 0x0
49242 /*
49243  * Enumerated value for register field ALT_USB_HOST_HCINT11_ACK
49244  *
49245  * ACK Response Received Transmitted Interrup
49246  */
49247 #define ALT_USB_HOST_HCINT11_ACK_E_ACT 0x1
49248 
49249 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_ACK register field. */
49250 #define ALT_USB_HOST_HCINT11_ACK_LSB 5
49251 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_ACK register field. */
49252 #define ALT_USB_HOST_HCINT11_ACK_MSB 5
49253 /* The width in bits of the ALT_USB_HOST_HCINT11_ACK register field. */
49254 #define ALT_USB_HOST_HCINT11_ACK_WIDTH 1
49255 /* The mask used to set the ALT_USB_HOST_HCINT11_ACK register field value. */
49256 #define ALT_USB_HOST_HCINT11_ACK_SET_MSK 0x00000020
49257 /* The mask used to clear the ALT_USB_HOST_HCINT11_ACK register field value. */
49258 #define ALT_USB_HOST_HCINT11_ACK_CLR_MSK 0xffffffdf
49259 /* The reset value of the ALT_USB_HOST_HCINT11_ACK register field. */
49260 #define ALT_USB_HOST_HCINT11_ACK_RESET 0x0
49261 /* Extracts the ALT_USB_HOST_HCINT11_ACK field value from a register. */
49262 #define ALT_USB_HOST_HCINT11_ACK_GET(value) (((value) & 0x00000020) >> 5)
49263 /* Produces a ALT_USB_HOST_HCINT11_ACK register field value suitable for setting the register. */
49264 #define ALT_USB_HOST_HCINT11_ACK_SET(value) (((value) << 5) & 0x00000020)
49265 
49266 /*
49267  * Field : nyet
49268  *
49269  * NYET Response Received Interrupt (NYET)
49270  *
49271  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
49272  *
49273  * in the core.This bit can be set only by the core and the application should
49274  * write 1 to clear
49275  *
49276  * it.
49277  *
49278  * Field Enumeration Values:
49279  *
49280  * Enum | Value | Description
49281  * :----------------------------------|:------|:------------------------------------
49282  * ALT_USB_HOST_HCINT11_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
49283  * ALT_USB_HOST_HCINT11_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
49284  *
49285  * Field Access Macros:
49286  *
49287  */
49288 /*
49289  * Enumerated value for register field ALT_USB_HOST_HCINT11_NYET
49290  *
49291  * No NYET Response Received Interrupt
49292  */
49293 #define ALT_USB_HOST_HCINT11_NYET_E_INACT 0x0
49294 /*
49295  * Enumerated value for register field ALT_USB_HOST_HCINT11_NYET
49296  *
49297  * NYET Response Received Interrupt
49298  */
49299 #define ALT_USB_HOST_HCINT11_NYET_E_ACT 0x1
49300 
49301 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_NYET register field. */
49302 #define ALT_USB_HOST_HCINT11_NYET_LSB 6
49303 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_NYET register field. */
49304 #define ALT_USB_HOST_HCINT11_NYET_MSB 6
49305 /* The width in bits of the ALT_USB_HOST_HCINT11_NYET register field. */
49306 #define ALT_USB_HOST_HCINT11_NYET_WIDTH 1
49307 /* The mask used to set the ALT_USB_HOST_HCINT11_NYET register field value. */
49308 #define ALT_USB_HOST_HCINT11_NYET_SET_MSK 0x00000040
49309 /* The mask used to clear the ALT_USB_HOST_HCINT11_NYET register field value. */
49310 #define ALT_USB_HOST_HCINT11_NYET_CLR_MSK 0xffffffbf
49311 /* The reset value of the ALT_USB_HOST_HCINT11_NYET register field. */
49312 #define ALT_USB_HOST_HCINT11_NYET_RESET 0x0
49313 /* Extracts the ALT_USB_HOST_HCINT11_NYET field value from a register. */
49314 #define ALT_USB_HOST_HCINT11_NYET_GET(value) (((value) & 0x00000040) >> 6)
49315 /* Produces a ALT_USB_HOST_HCINT11_NYET register field value suitable for setting the register. */
49316 #define ALT_USB_HOST_HCINT11_NYET_SET(value) (((value) << 6) & 0x00000040)
49317 
49318 /*
49319  * Field : xacterr
49320  *
49321  * Transaction Error (XactErr)
49322  *
49323  * Indicates one of the following errors occurred on the USB.
49324  *
49325  * CRC check failure
49326  *
49327  * Timeout
49328  *
49329  * Bit stuff error
49330  *
49331  * False EOP
49332  *
49333  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
49334  *
49335  * in the core.This bit can be set only by the core and the application should
49336  * write 1 to clear
49337  *
49338  * it.
49339  *
49340  * Field Enumeration Values:
49341  *
49342  * Enum | Value | Description
49343  * :-------------------------------------|:------|:---------------------
49344  * ALT_USB_HOST_HCINT11_XACTERR_E_INACT | 0x0 | No Transaction Error
49345  * ALT_USB_HOST_HCINT11_XACTERR_E_ACT | 0x1 | Transaction Error
49346  *
49347  * Field Access Macros:
49348  *
49349  */
49350 /*
49351  * Enumerated value for register field ALT_USB_HOST_HCINT11_XACTERR
49352  *
49353  * No Transaction Error
49354  */
49355 #define ALT_USB_HOST_HCINT11_XACTERR_E_INACT 0x0
49356 /*
49357  * Enumerated value for register field ALT_USB_HOST_HCINT11_XACTERR
49358  *
49359  * Transaction Error
49360  */
49361 #define ALT_USB_HOST_HCINT11_XACTERR_E_ACT 0x1
49362 
49363 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_XACTERR register field. */
49364 #define ALT_USB_HOST_HCINT11_XACTERR_LSB 7
49365 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_XACTERR register field. */
49366 #define ALT_USB_HOST_HCINT11_XACTERR_MSB 7
49367 /* The width in bits of the ALT_USB_HOST_HCINT11_XACTERR register field. */
49368 #define ALT_USB_HOST_HCINT11_XACTERR_WIDTH 1
49369 /* The mask used to set the ALT_USB_HOST_HCINT11_XACTERR register field value. */
49370 #define ALT_USB_HOST_HCINT11_XACTERR_SET_MSK 0x00000080
49371 /* The mask used to clear the ALT_USB_HOST_HCINT11_XACTERR register field value. */
49372 #define ALT_USB_HOST_HCINT11_XACTERR_CLR_MSK 0xffffff7f
49373 /* The reset value of the ALT_USB_HOST_HCINT11_XACTERR register field. */
49374 #define ALT_USB_HOST_HCINT11_XACTERR_RESET 0x0
49375 /* Extracts the ALT_USB_HOST_HCINT11_XACTERR field value from a register. */
49376 #define ALT_USB_HOST_HCINT11_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
49377 /* Produces a ALT_USB_HOST_HCINT11_XACTERR register field value suitable for setting the register. */
49378 #define ALT_USB_HOST_HCINT11_XACTERR_SET(value) (((value) << 7) & 0x00000080)
49379 
49380 /*
49381  * Field : bblerr
49382  *
49383  * Babble Error (BblErr)
49384  *
49385  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
49386  *
49387  * in the core..This bit can be set only by the core and the application should
49388  * write 1 to clear
49389  *
49390  * it.
49391  *
49392  * Field Enumeration Values:
49393  *
49394  * Enum | Value | Description
49395  * :------------------------------------|:------|:----------------
49396  * ALT_USB_HOST_HCINT11_BBLERR_E_INACT | 0x0 | No Babble Error
49397  * ALT_USB_HOST_HCINT11_BBLERR_E_ACT | 0x1 | Babble Error
49398  *
49399  * Field Access Macros:
49400  *
49401  */
49402 /*
49403  * Enumerated value for register field ALT_USB_HOST_HCINT11_BBLERR
49404  *
49405  * No Babble Error
49406  */
49407 #define ALT_USB_HOST_HCINT11_BBLERR_E_INACT 0x0
49408 /*
49409  * Enumerated value for register field ALT_USB_HOST_HCINT11_BBLERR
49410  *
49411  * Babble Error
49412  */
49413 #define ALT_USB_HOST_HCINT11_BBLERR_E_ACT 0x1
49414 
49415 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_BBLERR register field. */
49416 #define ALT_USB_HOST_HCINT11_BBLERR_LSB 8
49417 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_BBLERR register field. */
49418 #define ALT_USB_HOST_HCINT11_BBLERR_MSB 8
49419 /* The width in bits of the ALT_USB_HOST_HCINT11_BBLERR register field. */
49420 #define ALT_USB_HOST_HCINT11_BBLERR_WIDTH 1
49421 /* The mask used to set the ALT_USB_HOST_HCINT11_BBLERR register field value. */
49422 #define ALT_USB_HOST_HCINT11_BBLERR_SET_MSK 0x00000100
49423 /* The mask used to clear the ALT_USB_HOST_HCINT11_BBLERR register field value. */
49424 #define ALT_USB_HOST_HCINT11_BBLERR_CLR_MSK 0xfffffeff
49425 /* The reset value of the ALT_USB_HOST_HCINT11_BBLERR register field. */
49426 #define ALT_USB_HOST_HCINT11_BBLERR_RESET 0x0
49427 /* Extracts the ALT_USB_HOST_HCINT11_BBLERR field value from a register. */
49428 #define ALT_USB_HOST_HCINT11_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
49429 /* Produces a ALT_USB_HOST_HCINT11_BBLERR register field value suitable for setting the register. */
49430 #define ALT_USB_HOST_HCINT11_BBLERR_SET(value) (((value) << 8) & 0x00000100)
49431 
49432 /*
49433  * Field : frmovrun
49434  *
49435  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
49436  * bit is masked
49437  *
49438  * in the core.This bit can be set only by the core and the application should
49439  * write 1 to clear
49440  *
49441  * it.
49442  *
49443  * Field Enumeration Values:
49444  *
49445  * Enum | Value | Description
49446  * :--------------------------------------|:------|:-----------------
49447  * ALT_USB_HOST_HCINT11_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
49448  * ALT_USB_HOST_HCINT11_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
49449  *
49450  * Field Access Macros:
49451  *
49452  */
49453 /*
49454  * Enumerated value for register field ALT_USB_HOST_HCINT11_FRMOVRUN
49455  *
49456  * No Frame Overrun
49457  */
49458 #define ALT_USB_HOST_HCINT11_FRMOVRUN_E_INACT 0x0
49459 /*
49460  * Enumerated value for register field ALT_USB_HOST_HCINT11_FRMOVRUN
49461  *
49462  * Frame Overrun
49463  */
49464 #define ALT_USB_HOST_HCINT11_FRMOVRUN_E_ACT 0x1
49465 
49466 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */
49467 #define ALT_USB_HOST_HCINT11_FRMOVRUN_LSB 9
49468 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */
49469 #define ALT_USB_HOST_HCINT11_FRMOVRUN_MSB 9
49470 /* The width in bits of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */
49471 #define ALT_USB_HOST_HCINT11_FRMOVRUN_WIDTH 1
49472 /* The mask used to set the ALT_USB_HOST_HCINT11_FRMOVRUN register field value. */
49473 #define ALT_USB_HOST_HCINT11_FRMOVRUN_SET_MSK 0x00000200
49474 /* The mask used to clear the ALT_USB_HOST_HCINT11_FRMOVRUN register field value. */
49475 #define ALT_USB_HOST_HCINT11_FRMOVRUN_CLR_MSK 0xfffffdff
49476 /* The reset value of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */
49477 #define ALT_USB_HOST_HCINT11_FRMOVRUN_RESET 0x0
49478 /* Extracts the ALT_USB_HOST_HCINT11_FRMOVRUN field value from a register. */
49479 #define ALT_USB_HOST_HCINT11_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
49480 /* Produces a ALT_USB_HOST_HCINT11_FRMOVRUN register field value suitable for setting the register. */
49481 #define ALT_USB_HOST_HCINT11_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
49482 
49483 /*
49484  * Field : datatglerr
49485  *
49486  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
49487  * application should write 1 to clear
49488  *
49489  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
49490  *
49491  * in the core.
49492  *
49493  * Field Enumeration Values:
49494  *
49495  * Enum | Value | Description
49496  * :----------------------------------------|:------|:---------------------
49497  * ALT_USB_HOST_HCINT11_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
49498  * ALT_USB_HOST_HCINT11_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
49499  *
49500  * Field Access Macros:
49501  *
49502  */
49503 /*
49504  * Enumerated value for register field ALT_USB_HOST_HCINT11_DATATGLERR
49505  *
49506  * No Data Toggle Error
49507  */
49508 #define ALT_USB_HOST_HCINT11_DATATGLERR_E_INACT 0x0
49509 /*
49510  * Enumerated value for register field ALT_USB_HOST_HCINT11_DATATGLERR
49511  *
49512  * Data Toggle Error
49513  */
49514 #define ALT_USB_HOST_HCINT11_DATATGLERR_E_ACT 0x1
49515 
49516 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */
49517 #define ALT_USB_HOST_HCINT11_DATATGLERR_LSB 10
49518 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */
49519 #define ALT_USB_HOST_HCINT11_DATATGLERR_MSB 10
49520 /* The width in bits of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */
49521 #define ALT_USB_HOST_HCINT11_DATATGLERR_WIDTH 1
49522 /* The mask used to set the ALT_USB_HOST_HCINT11_DATATGLERR register field value. */
49523 #define ALT_USB_HOST_HCINT11_DATATGLERR_SET_MSK 0x00000400
49524 /* The mask used to clear the ALT_USB_HOST_HCINT11_DATATGLERR register field value. */
49525 #define ALT_USB_HOST_HCINT11_DATATGLERR_CLR_MSK 0xfffffbff
49526 /* The reset value of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */
49527 #define ALT_USB_HOST_HCINT11_DATATGLERR_RESET 0x0
49528 /* Extracts the ALT_USB_HOST_HCINT11_DATATGLERR field value from a register. */
49529 #define ALT_USB_HOST_HCINT11_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
49530 /* Produces a ALT_USB_HOST_HCINT11_DATATGLERR register field value suitable for setting the register. */
49531 #define ALT_USB_HOST_HCINT11_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
49532 
49533 /*
49534  * Field : bnaintr
49535  *
49536  * BNA (Buffer Not Available) Interrupt (BNAIntr)
49537  *
49538  * This bit is valid only when Scatter/Gather DMA mode is enabled.
49539  *
49540  * The core generates this interrupt when the descriptor accessed
49541  *
49542  * is not ready for the Core to process. BNA will not be generated
49543  *
49544  * for Isochronous channels.
49545  *
49546  * For non Scatter/Gather DMA mode, this bit is reserved.
49547  *
49548  * Field Enumeration Values:
49549  *
49550  * Enum | Value | Description
49551  * :-------------------------------------|:------|:-----------------
49552  * ALT_USB_HOST_HCINT11_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
49553  * ALT_USB_HOST_HCINT11_BNAINTR_E_ACT | 0x1 | BNA Interrupt
49554  *
49555  * Field Access Macros:
49556  *
49557  */
49558 /*
49559  * Enumerated value for register field ALT_USB_HOST_HCINT11_BNAINTR
49560  *
49561  * No BNA Interrupt
49562  */
49563 #define ALT_USB_HOST_HCINT11_BNAINTR_E_INACT 0x0
49564 /*
49565  * Enumerated value for register field ALT_USB_HOST_HCINT11_BNAINTR
49566  *
49567  * BNA Interrupt
49568  */
49569 #define ALT_USB_HOST_HCINT11_BNAINTR_E_ACT 0x1
49570 
49571 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_BNAINTR register field. */
49572 #define ALT_USB_HOST_HCINT11_BNAINTR_LSB 11
49573 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_BNAINTR register field. */
49574 #define ALT_USB_HOST_HCINT11_BNAINTR_MSB 11
49575 /* The width in bits of the ALT_USB_HOST_HCINT11_BNAINTR register field. */
49576 #define ALT_USB_HOST_HCINT11_BNAINTR_WIDTH 1
49577 /* The mask used to set the ALT_USB_HOST_HCINT11_BNAINTR register field value. */
49578 #define ALT_USB_HOST_HCINT11_BNAINTR_SET_MSK 0x00000800
49579 /* The mask used to clear the ALT_USB_HOST_HCINT11_BNAINTR register field value. */
49580 #define ALT_USB_HOST_HCINT11_BNAINTR_CLR_MSK 0xfffff7ff
49581 /* The reset value of the ALT_USB_HOST_HCINT11_BNAINTR register field. */
49582 #define ALT_USB_HOST_HCINT11_BNAINTR_RESET 0x0
49583 /* Extracts the ALT_USB_HOST_HCINT11_BNAINTR field value from a register. */
49584 #define ALT_USB_HOST_HCINT11_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
49585 /* Produces a ALT_USB_HOST_HCINT11_BNAINTR register field value suitable for setting the register. */
49586 #define ALT_USB_HOST_HCINT11_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
49587 
49588 /*
49589  * Field : xcs_xact_err
49590  *
49591  * Excessive Transaction Error (XCS_XACT_ERR)
49592  *
49593  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
49594  * this bit
49595  *
49596  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
49597  *
49598  * not be generated for Isochronous channels.
49599  *
49600  * For non Scatter/Gather DMA mode, this bit is reserved.
49601  *
49602  * Field Enumeration Values:
49603  *
49604  * Enum | Value | Description
49605  * :--------------------------------------------|:------|:-------------------------------
49606  * ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
49607  * ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
49608  *
49609  * Field Access Macros:
49610  *
49611  */
49612 /*
49613  * Enumerated value for register field ALT_USB_HOST_HCINT11_XCS_XACT_ERR
49614  *
49615  * No Excessive Transaction Error
49616  */
49617 #define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_INACT 0x0
49618 /*
49619  * Enumerated value for register field ALT_USB_HOST_HCINT11_XCS_XACT_ERR
49620  *
49621  * Excessive Transaction Error
49622  */
49623 #define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_ACVTIVE 0x1
49624 
49625 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */
49626 #define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_LSB 12
49627 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */
49628 #define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_MSB 12
49629 /* The width in bits of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */
49630 #define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_WIDTH 1
49631 /* The mask used to set the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field value. */
49632 #define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_SET_MSK 0x00001000
49633 /* The mask used to clear the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field value. */
49634 #define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_CLR_MSK 0xffffefff
49635 /* The reset value of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */
49636 #define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_RESET 0x0
49637 /* Extracts the ALT_USB_HOST_HCINT11_XCS_XACT_ERR field value from a register. */
49638 #define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
49639 /* Produces a ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field value suitable for setting the register. */
49640 #define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
49641 
49642 /*
49643  * Field : desc_lst_rollintr
49644  *
49645  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
49646  *
49647  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
49648  * this bit
49649  *
49650  * when the corresponding channel's descriptor list rolls over.
49651  *
49652  * For non Scatter/Gather DMA mode, this bit is reserved.
49653  *
49654  * Field Enumeration Values:
49655  *
49656  * Enum | Value | Description
49657  * :-----------------------------------------------|:------|:---------------------------------
49658  * ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
49659  * ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
49660  *
49661  * Field Access Macros:
49662  *
49663  */
49664 /*
49665  * Enumerated value for register field ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR
49666  *
49667  * No Descriptor rollover interrupt
49668  */
49669 #define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_INACT 0x0
49670 /*
49671  * Enumerated value for register field ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR
49672  *
49673  * Descriptor rollover interrupt
49674  */
49675 #define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_ACT 0x1
49676 
49677 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */
49678 #define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_LSB 13
49679 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */
49680 #define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_MSB 13
49681 /* The width in bits of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */
49682 #define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_WIDTH 1
49683 /* The mask used to set the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field value. */
49684 #define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_SET_MSK 0x00002000
49685 /* The mask used to clear the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field value. */
49686 #define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
49687 /* The reset value of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */
49688 #define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_RESET 0x0
49689 /* Extracts the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR field value from a register. */
49690 #define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
49691 /* Produces a ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field value suitable for setting the register. */
49692 #define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
49693 
49694 #ifndef __ASSEMBLY__
49695 /*
49696  * WARNING: The C register and register group struct declarations are provided for
49697  * convenience and illustrative purposes. They should, however, be used with
49698  * caution as the C language standard provides no guarantees about the alignment or
49699  * atomicity of device memory accesses. The recommended practice for writing
49700  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49701  * alt_write_word() functions.
49702  *
49703  * The struct declaration for register ALT_USB_HOST_HCINT11.
49704  */
49705 struct ALT_USB_HOST_HCINT11_s
49706 {
49707  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT11_XFERCOMPL */
49708  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT11_CHHLTD */
49709  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT11_AHBERR */
49710  uint32_t stall : 1; /* ALT_USB_HOST_HCINT11_STALL */
49711  uint32_t nak : 1; /* ALT_USB_HOST_HCINT11_NAK */
49712  uint32_t ack : 1; /* ALT_USB_HOST_HCINT11_ACK */
49713  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT11_NYET */
49714  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT11_XACTERR */
49715  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT11_BBLERR */
49716  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT11_FRMOVRUN */
49717  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT11_DATATGLERR */
49718  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT11_BNAINTR */
49719  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT11_XCS_XACT_ERR */
49720  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR */
49721  uint32_t : 18; /* *UNDEFINED* */
49722 };
49723 
49724 /* The typedef declaration for register ALT_USB_HOST_HCINT11. */
49725 typedef volatile struct ALT_USB_HOST_HCINT11_s ALT_USB_HOST_HCINT11_t;
49726 #endif /* __ASSEMBLY__ */
49727 
49728 /* The reset value of the ALT_USB_HOST_HCINT11 register. */
49729 #define ALT_USB_HOST_HCINT11_RESET 0x00000000
49730 /* The byte offset of the ALT_USB_HOST_HCINT11 register from the beginning of the component. */
49731 #define ALT_USB_HOST_HCINT11_OFST 0x268
49732 /* The address of the ALT_USB_HOST_HCINT11 register. */
49733 #define ALT_USB_HOST_HCINT11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT11_OFST))
49734 
49735 /*
49736  * Register : hcintmsk11
49737  *
49738  * Host Channel 11 Interrupt Mask Register
49739  *
49740  * Register Layout
49741  *
49742  * Bits | Access | Reset | Description
49743  * :--------|:-------|:------|:--------------------------------------------
49744  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK
49745  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_CHHLTDMSK
49746  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_AHBERRMSK
49747  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_STALLMSK
49748  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_NAKMSK
49749  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_ACKMSK
49750  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_NYETMSK
49751  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_XACTERRMSK
49752  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_BBLERRMSK
49753  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK
49754  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK
49755  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_BNAINTRMSK
49756  * [12] | ??? | 0x0 | *UNDEFINED*
49757  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK
49758  * [31:14] | ??? | 0x0 | *UNDEFINED*
49759  *
49760  */
49761 /*
49762  * Field : xfercomplmsk
49763  *
49764  * Transfer Completed Mask (XferComplMsk)
49765  *
49766  * Field Enumeration Values:
49767  *
49768  * Enum | Value | Description
49769  * :---------------------------------------------|:------|:------------
49770  * ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_MSK | 0x0 | Mask
49771  * ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
49772  *
49773  * Field Access Macros:
49774  *
49775  */
49776 /*
49777  * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK
49778  *
49779  * Mask
49780  */
49781 #define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_MSK 0x0
49782 /*
49783  * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK
49784  *
49785  * No mask
49786  */
49787 #define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_NOMSK 0x1
49788 
49789 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */
49790 #define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_LSB 0
49791 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */
49792 #define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_MSB 0
49793 /* The width in bits of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */
49794 #define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_WIDTH 1
49795 /* The mask used to set the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field value. */
49796 #define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_SET_MSK 0x00000001
49797 /* The mask used to clear the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field value. */
49798 #define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_CLR_MSK 0xfffffffe
49799 /* The reset value of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */
49800 #define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_RESET 0x0
49801 /* Extracts the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK field value from a register. */
49802 #define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
49803 /* Produces a ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field value suitable for setting the register. */
49804 #define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
49805 
49806 /*
49807  * Field : chhltdmsk
49808  *
49809  * Channel Halted Mask (ChHltdMsk)
49810  *
49811  * Field Enumeration Values:
49812  *
49813  * Enum | Value | Description
49814  * :------------------------------------------|:------|:------------
49815  * ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_MSK | 0x0 | Mask
49816  * ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_NOMSK | 0x1 | No mask
49817  *
49818  * Field Access Macros:
49819  *
49820  */
49821 /*
49822  * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_CHHLTDMSK
49823  *
49824  * Mask
49825  */
49826 #define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_MSK 0x0
49827 /*
49828  * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_CHHLTDMSK
49829  *
49830  * No mask
49831  */
49832 #define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_NOMSK 0x1
49833 
49834 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */
49835 #define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_LSB 1
49836 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */
49837 #define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_MSB 1
49838 /* The width in bits of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */
49839 #define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_WIDTH 1
49840 /* The mask used to set the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field value. */
49841 #define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_SET_MSK 0x00000002
49842 /* The mask used to clear the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field value. */
49843 #define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_CLR_MSK 0xfffffffd
49844 /* The reset value of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */
49845 #define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_RESET 0x0
49846 /* Extracts the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK field value from a register. */
49847 #define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
49848 /* Produces a ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field value suitable for setting the register. */
49849 #define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
49850 
49851 /*
49852  * Field : ahberrmsk
49853  *
49854  * AHB Error Mask (AHBErrMsk)
49855  *
49856  * In scatter/gather DMA mode for host,
49857  *
49858  * interrupts will not be generated due to the corresponding bits set in
49859  *
49860  * HCINTn.
49861  *
49862  * Field Enumeration Values:
49863  *
49864  * Enum | Value | Description
49865  * :------------------------------------------|:------|:------------
49866  * ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_MSK | 0x0 | Mask
49867  * ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_NOMSK | 0x1 | No mask
49868  *
49869  * Field Access Macros:
49870  *
49871  */
49872 /*
49873  * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_AHBERRMSK
49874  *
49875  * Mask
49876  */
49877 #define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_MSK 0x0
49878 /*
49879  * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_AHBERRMSK
49880  *
49881  * No mask
49882  */
49883 #define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_NOMSK 0x1
49884 
49885 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */
49886 #define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_LSB 2
49887 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */
49888 #define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_MSB 2
49889 /* The width in bits of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */
49890 #define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_WIDTH 1
49891 /* The mask used to set the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field value. */
49892 #define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_SET_MSK 0x00000004
49893 /* The mask used to clear the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field value. */
49894 #define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_CLR_MSK 0xfffffffb
49895 /* The reset value of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */
49896 #define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_RESET 0x0
49897 /* Extracts the ALT_USB_HOST_HCINTMSK11_AHBERRMSK field value from a register. */
49898 #define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
49899 /* Produces a ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field value suitable for setting the register. */
49900 #define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
49901 
49902 /*
49903  * Field : stallmsk
49904  *
49905  * STALL Response Received Interrupt Mask (StallMsk)
49906  *
49907  * In scatter/gather DMA mode for host,
49908  *
49909  * interrupts will not be generated due to the corresponding bits set in
49910  *
49911  * HCINTn.
49912  *
49913  * Field Access Macros:
49914  *
49915  */
49916 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_STALLMSK register field. */
49917 #define ALT_USB_HOST_HCINTMSK11_STALLMSK_LSB 3
49918 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_STALLMSK register field. */
49919 #define ALT_USB_HOST_HCINTMSK11_STALLMSK_MSB 3
49920 /* The width in bits of the ALT_USB_HOST_HCINTMSK11_STALLMSK register field. */
49921 #define ALT_USB_HOST_HCINTMSK11_STALLMSK_WIDTH 1
49922 /* The mask used to set the ALT_USB_HOST_HCINTMSK11_STALLMSK register field value. */
49923 #define ALT_USB_HOST_HCINTMSK11_STALLMSK_SET_MSK 0x00000008
49924 /* The mask used to clear the ALT_USB_HOST_HCINTMSK11_STALLMSK register field value. */
49925 #define ALT_USB_HOST_HCINTMSK11_STALLMSK_CLR_MSK 0xfffffff7
49926 /* The reset value of the ALT_USB_HOST_HCINTMSK11_STALLMSK register field. */
49927 #define ALT_USB_HOST_HCINTMSK11_STALLMSK_RESET 0x0
49928 /* Extracts the ALT_USB_HOST_HCINTMSK11_STALLMSK field value from a register. */
49929 #define ALT_USB_HOST_HCINTMSK11_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
49930 /* Produces a ALT_USB_HOST_HCINTMSK11_STALLMSK register field value suitable for setting the register. */
49931 #define ALT_USB_HOST_HCINTMSK11_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
49932 
49933 /*
49934  * Field : nakmsk
49935  *
49936  * NAK Response Received Interrupt Mask (NakMsk)
49937  *
49938  * In scatter/gather DMA mode for host,
49939  *
49940  * interrupts will not be generated due to the corresponding bits set in
49941  *
49942  * HCINTn.
49943  *
49944  * Field Access Macros:
49945  *
49946  */
49947 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_NAKMSK register field. */
49948 #define ALT_USB_HOST_HCINTMSK11_NAKMSK_LSB 4
49949 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_NAKMSK register field. */
49950 #define ALT_USB_HOST_HCINTMSK11_NAKMSK_MSB 4
49951 /* The width in bits of the ALT_USB_HOST_HCINTMSK11_NAKMSK register field. */
49952 #define ALT_USB_HOST_HCINTMSK11_NAKMSK_WIDTH 1
49953 /* The mask used to set the ALT_USB_HOST_HCINTMSK11_NAKMSK register field value. */
49954 #define ALT_USB_HOST_HCINTMSK11_NAKMSK_SET_MSK 0x00000010
49955 /* The mask used to clear the ALT_USB_HOST_HCINTMSK11_NAKMSK register field value. */
49956 #define ALT_USB_HOST_HCINTMSK11_NAKMSK_CLR_MSK 0xffffffef
49957 /* The reset value of the ALT_USB_HOST_HCINTMSK11_NAKMSK register field. */
49958 #define ALT_USB_HOST_HCINTMSK11_NAKMSK_RESET 0x0
49959 /* Extracts the ALT_USB_HOST_HCINTMSK11_NAKMSK field value from a register. */
49960 #define ALT_USB_HOST_HCINTMSK11_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
49961 /* Produces a ALT_USB_HOST_HCINTMSK11_NAKMSK register field value suitable for setting the register. */
49962 #define ALT_USB_HOST_HCINTMSK11_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
49963 
49964 /*
49965  * Field : ackmsk
49966  *
49967  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
49968  *
49969  * In scatter/gather DMA mode for host,
49970  *
49971  * interrupts will not be generated due to the corresponding bits set in
49972  *
49973  * HCINTn.
49974  *
49975  * Field Access Macros:
49976  *
49977  */
49978 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_ACKMSK register field. */
49979 #define ALT_USB_HOST_HCINTMSK11_ACKMSK_LSB 5
49980 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_ACKMSK register field. */
49981 #define ALT_USB_HOST_HCINTMSK11_ACKMSK_MSB 5
49982 /* The width in bits of the ALT_USB_HOST_HCINTMSK11_ACKMSK register field. */
49983 #define ALT_USB_HOST_HCINTMSK11_ACKMSK_WIDTH 1
49984 /* The mask used to set the ALT_USB_HOST_HCINTMSK11_ACKMSK register field value. */
49985 #define ALT_USB_HOST_HCINTMSK11_ACKMSK_SET_MSK 0x00000020
49986 /* The mask used to clear the ALT_USB_HOST_HCINTMSK11_ACKMSK register field value. */
49987 #define ALT_USB_HOST_HCINTMSK11_ACKMSK_CLR_MSK 0xffffffdf
49988 /* The reset value of the ALT_USB_HOST_HCINTMSK11_ACKMSK register field. */
49989 #define ALT_USB_HOST_HCINTMSK11_ACKMSK_RESET 0x0
49990 /* Extracts the ALT_USB_HOST_HCINTMSK11_ACKMSK field value from a register. */
49991 #define ALT_USB_HOST_HCINTMSK11_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
49992 /* Produces a ALT_USB_HOST_HCINTMSK11_ACKMSK register field value suitable for setting the register. */
49993 #define ALT_USB_HOST_HCINTMSK11_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
49994 
49995 /*
49996  * Field : nyetmsk
49997  *
49998  * NYET Response Received Interrupt Mask (NyetMsk)
49999  *
50000  * In scatter/gather DMA mode for host,
50001  *
50002  * interrupts will not be generated due to the corresponding bits set in
50003  *
50004  * HCINTn.
50005  *
50006  * Field Access Macros:
50007  *
50008  */
50009 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_NYETMSK register field. */
50010 #define ALT_USB_HOST_HCINTMSK11_NYETMSK_LSB 6
50011 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_NYETMSK register field. */
50012 #define ALT_USB_HOST_HCINTMSK11_NYETMSK_MSB 6
50013 /* The width in bits of the ALT_USB_HOST_HCINTMSK11_NYETMSK register field. */
50014 #define ALT_USB_HOST_HCINTMSK11_NYETMSK_WIDTH 1
50015 /* The mask used to set the ALT_USB_HOST_HCINTMSK11_NYETMSK register field value. */
50016 #define ALT_USB_HOST_HCINTMSK11_NYETMSK_SET_MSK 0x00000040
50017 /* The mask used to clear the ALT_USB_HOST_HCINTMSK11_NYETMSK register field value. */
50018 #define ALT_USB_HOST_HCINTMSK11_NYETMSK_CLR_MSK 0xffffffbf
50019 /* The reset value of the ALT_USB_HOST_HCINTMSK11_NYETMSK register field. */
50020 #define ALT_USB_HOST_HCINTMSK11_NYETMSK_RESET 0x0
50021 /* Extracts the ALT_USB_HOST_HCINTMSK11_NYETMSK field value from a register. */
50022 #define ALT_USB_HOST_HCINTMSK11_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
50023 /* Produces a ALT_USB_HOST_HCINTMSK11_NYETMSK register field value suitable for setting the register. */
50024 #define ALT_USB_HOST_HCINTMSK11_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
50025 
50026 /*
50027  * Field : xacterrmsk
50028  *
50029  * Transaction Error Mask (XactErrMsk)
50030  *
50031  * In scatter/gather DMA mode for host,
50032  *
50033  * interrupts will not be generated due to the corresponding bits set in
50034  *
50035  * HCINTn.
50036  *
50037  * Field Access Macros:
50038  *
50039  */
50040 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field. */
50041 #define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_LSB 7
50042 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field. */
50043 #define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_MSB 7
50044 /* The width in bits of the ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field. */
50045 #define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_WIDTH 1
50046 /* The mask used to set the ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field value. */
50047 #define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_SET_MSK 0x00000080
50048 /* The mask used to clear the ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field value. */
50049 #define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_CLR_MSK 0xffffff7f
50050 /* The reset value of the ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field. */
50051 #define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_RESET 0x0
50052 /* Extracts the ALT_USB_HOST_HCINTMSK11_XACTERRMSK field value from a register. */
50053 #define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
50054 /* Produces a ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field value suitable for setting the register. */
50055 #define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
50056 
50057 /*
50058  * Field : bblerrmsk
50059  *
50060  * Babble Error Mask (BblErrMsk)
50061  *
50062  * In scatter/gather DMA mode for host,
50063  *
50064  * interrupts will not be generated due to the corresponding bits set in
50065  *
50066  * HCINTn.
50067  *
50068  * Field Access Macros:
50069  *
50070  */
50071 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field. */
50072 #define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_LSB 8
50073 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field. */
50074 #define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_MSB 8
50075 /* The width in bits of the ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field. */
50076 #define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_WIDTH 1
50077 /* The mask used to set the ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field value. */
50078 #define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_SET_MSK 0x00000100
50079 /* The mask used to clear the ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field value. */
50080 #define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_CLR_MSK 0xfffffeff
50081 /* The reset value of the ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field. */
50082 #define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_RESET 0x0
50083 /* Extracts the ALT_USB_HOST_HCINTMSK11_BBLERRMSK field value from a register. */
50084 #define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
50085 /* Produces a ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field value suitable for setting the register. */
50086 #define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
50087 
50088 /*
50089  * Field : frmovrunmsk
50090  *
50091  * Frame Overrun Mask (FrmOvrunMsk)
50092  *
50093  * In scatter/gather DMA mode for host,
50094  *
50095  * interrupts will not be generated due to the corresponding bits set in
50096  *
50097  * HCINTn.
50098  *
50099  * Field Access Macros:
50100  *
50101  */
50102 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field. */
50103 #define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_LSB 9
50104 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field. */
50105 #define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_MSB 9
50106 /* The width in bits of the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field. */
50107 #define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_WIDTH 1
50108 /* The mask used to set the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field value. */
50109 #define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_SET_MSK 0x00000200
50110 /* The mask used to clear the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field value. */
50111 #define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_CLR_MSK 0xfffffdff
50112 /* The reset value of the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field. */
50113 #define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_RESET 0x0
50114 /* Extracts the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK field value from a register. */
50115 #define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
50116 /* Produces a ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field value suitable for setting the register. */
50117 #define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
50118 
50119 /*
50120  * Field : datatglerrmsk
50121  *
50122  * Data Toggle Error Mask (DataTglErrMsk)
50123  *
50124  * In scatter/gather DMA mode for host,
50125  *
50126  * interrupts will not be generated due to the corresponding bits set in
50127  *
50128  * HCINTn.
50129  *
50130  * Field Access Macros:
50131  *
50132  */
50133 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field. */
50134 #define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_LSB 10
50135 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field. */
50136 #define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_MSB 10
50137 /* The width in bits of the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field. */
50138 #define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_WIDTH 1
50139 /* The mask used to set the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field value. */
50140 #define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_SET_MSK 0x00000400
50141 /* The mask used to clear the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field value. */
50142 #define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_CLR_MSK 0xfffffbff
50143 /* The reset value of the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field. */
50144 #define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_RESET 0x0
50145 /* Extracts the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK field value from a register. */
50146 #define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
50147 /* Produces a ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field value suitable for setting the register. */
50148 #define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
50149 
50150 /*
50151  * Field : bnaintrmsk
50152  *
50153  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
50154  *
50155  * This bit is valid only when Scatter/Gather DMA mode is enabled.
50156  *
50157  * Field Enumeration Values:
50158  *
50159  * Enum | Value | Description
50160  * :-------------------------------------------|:------|:------------
50161  * ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_MSK | 0x0 | Mask
50162  * ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_NOMSK | 0x1 | No mask
50163  *
50164  * Field Access Macros:
50165  *
50166  */
50167 /*
50168  * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_BNAINTRMSK
50169  *
50170  * Mask
50171  */
50172 #define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_MSK 0x0
50173 /*
50174  * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_BNAINTRMSK
50175  *
50176  * No mask
50177  */
50178 #define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_NOMSK 0x1
50179 
50180 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */
50181 #define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_LSB 11
50182 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */
50183 #define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_MSB 11
50184 /* The width in bits of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */
50185 #define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_WIDTH 1
50186 /* The mask used to set the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field value. */
50187 #define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_SET_MSK 0x00000800
50188 /* The mask used to clear the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field value. */
50189 #define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_CLR_MSK 0xfffff7ff
50190 /* The reset value of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */
50191 #define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_RESET 0x0
50192 /* Extracts the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK field value from a register. */
50193 #define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
50194 /* Produces a ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field value suitable for setting the register. */
50195 #define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
50196 
50197 /*
50198  * Field : frm_lst_rollintrmsk
50199  *
50200  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
50201  *
50202  * This bit is valid only when Scatter/Gather DMA mode is enabled.
50203  *
50204  * Field Enumeration Values:
50205  *
50206  * Enum | Value | Description
50207  * :----------------------------------------------------|:------|:------------
50208  * ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
50209  * ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
50210  *
50211  * Field Access Macros:
50212  *
50213  */
50214 /*
50215  * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK
50216  *
50217  * Mask
50218  */
50219 #define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_MSK 0x0
50220 /*
50221  * Enumerated value for register field ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK
50222  *
50223  * No mask
50224  */
50225 #define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
50226 
50227 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */
50228 #define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_LSB 13
50229 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */
50230 #define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_MSB 13
50231 /* The width in bits of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */
50232 #define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_WIDTH 1
50233 /* The mask used to set the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field value. */
50234 #define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
50235 /* The mask used to clear the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field value. */
50236 #define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
50237 /* The reset value of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */
50238 #define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_RESET 0x0
50239 /* Extracts the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK field value from a register. */
50240 #define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
50241 /* Produces a ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
50242 #define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
50243 
50244 #ifndef __ASSEMBLY__
50245 /*
50246  * WARNING: The C register and register group struct declarations are provided for
50247  * convenience and illustrative purposes. They should, however, be used with
50248  * caution as the C language standard provides no guarantees about the alignment or
50249  * atomicity of device memory accesses. The recommended practice for writing
50250  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50251  * alt_write_word() functions.
50252  *
50253  * The struct declaration for register ALT_USB_HOST_HCINTMSK11.
50254  */
50255 struct ALT_USB_HOST_HCINTMSK11_s
50256 {
50257  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK */
50258  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK11_CHHLTDMSK */
50259  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK11_AHBERRMSK */
50260  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK11_STALLMSK */
50261  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK11_NAKMSK */
50262  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK11_ACKMSK */
50263  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK11_NYETMSK */
50264  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK11_XACTERRMSK */
50265  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK11_BBLERRMSK */
50266  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK */
50267  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK */
50268  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK11_BNAINTRMSK */
50269  uint32_t : 1; /* *UNDEFINED* */
50270  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK */
50271  uint32_t : 18; /* *UNDEFINED* */
50272 };
50273 
50274 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK11. */
50275 typedef volatile struct ALT_USB_HOST_HCINTMSK11_s ALT_USB_HOST_HCINTMSK11_t;
50276 #endif /* __ASSEMBLY__ */
50277 
50278 /* The reset value of the ALT_USB_HOST_HCINTMSK11 register. */
50279 #define ALT_USB_HOST_HCINTMSK11_RESET 0x00000000
50280 /* The byte offset of the ALT_USB_HOST_HCINTMSK11 register from the beginning of the component. */
50281 #define ALT_USB_HOST_HCINTMSK11_OFST 0x26c
50282 /* The address of the ALT_USB_HOST_HCINTMSK11 register. */
50283 #define ALT_USB_HOST_HCINTMSK11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK11_OFST))
50284 
50285 /*
50286  * Register : hctsiz11
50287  *
50288  * Host Channel 11 Transfer Size Register
50289  *
50290  * Register Layout
50291  *
50292  * Bits | Access | Reset | Description
50293  * :--------|:-------|:------|:-------------------------------
50294  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ11_XFERSIZE
50295  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ11_PKTCNT
50296  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ11_PID
50297  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ11_DOPNG
50298  *
50299  */
50300 /*
50301  * Field : xfersize
50302  *
50303  * Transfer Size (XferSize)
50304  *
50305  * For an OUT, this field is the number of data bytes the host sends
50306  *
50307  * during the transfer.
50308  *
50309  * For an IN, this field is the buffer size that the application has
50310  *
50311  * Reserved For the transfer. The application is expected to
50312  *
50313  * program this field as an integer multiple of the maximum packet
50314  *
50315  * size For IN transactions (periodic and non-periodic).
50316  *
50317  * The width of this counter is specified as Width of Transfer Size
50318  *
50319  * Counters
50320  *
50321  * Field Access Macros:
50322  *
50323  */
50324 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */
50325 #define ALT_USB_HOST_HCTSIZ11_XFERSIZE_LSB 0
50326 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */
50327 #define ALT_USB_HOST_HCTSIZ11_XFERSIZE_MSB 18
50328 /* The width in bits of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */
50329 #define ALT_USB_HOST_HCTSIZ11_XFERSIZE_WIDTH 19
50330 /* The mask used to set the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field value. */
50331 #define ALT_USB_HOST_HCTSIZ11_XFERSIZE_SET_MSK 0x0007ffff
50332 /* The mask used to clear the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field value. */
50333 #define ALT_USB_HOST_HCTSIZ11_XFERSIZE_CLR_MSK 0xfff80000
50334 /* The reset value of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */
50335 #define ALT_USB_HOST_HCTSIZ11_XFERSIZE_RESET 0x0
50336 /* Extracts the ALT_USB_HOST_HCTSIZ11_XFERSIZE field value from a register. */
50337 #define ALT_USB_HOST_HCTSIZ11_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
50338 /* Produces a ALT_USB_HOST_HCTSIZ11_XFERSIZE register field value suitable for setting the register. */
50339 #define ALT_USB_HOST_HCTSIZ11_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
50340 
50341 /*
50342  * Field : pktcnt
50343  *
50344  * Packet Count (PktCnt)
50345  *
50346  * This field is programmed by the application with the expected
50347  *
50348  * number of packets to be transmitted (OUT) or received (IN).
50349  *
50350  * The host decrements this count on every successful
50351  *
50352  * transmission or reception of an OUT/IN packet. Once this count
50353  *
50354  * reaches zero, the application is interrupted to indicate normal
50355  *
50356  * completion.
50357  *
50358  * The width of this counter is specified as Width of Packet
50359  *
50360  * Counters
50361  *
50362  * Field Access Macros:
50363  *
50364  */
50365 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */
50366 #define ALT_USB_HOST_HCTSIZ11_PKTCNT_LSB 19
50367 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */
50368 #define ALT_USB_HOST_HCTSIZ11_PKTCNT_MSB 28
50369 /* The width in bits of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */
50370 #define ALT_USB_HOST_HCTSIZ11_PKTCNT_WIDTH 10
50371 /* The mask used to set the ALT_USB_HOST_HCTSIZ11_PKTCNT register field value. */
50372 #define ALT_USB_HOST_HCTSIZ11_PKTCNT_SET_MSK 0x1ff80000
50373 /* The mask used to clear the ALT_USB_HOST_HCTSIZ11_PKTCNT register field value. */
50374 #define ALT_USB_HOST_HCTSIZ11_PKTCNT_CLR_MSK 0xe007ffff
50375 /* The reset value of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */
50376 #define ALT_USB_HOST_HCTSIZ11_PKTCNT_RESET 0x0
50377 /* Extracts the ALT_USB_HOST_HCTSIZ11_PKTCNT field value from a register. */
50378 #define ALT_USB_HOST_HCTSIZ11_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
50379 /* Produces a ALT_USB_HOST_HCTSIZ11_PKTCNT register field value suitable for setting the register. */
50380 #define ALT_USB_HOST_HCTSIZ11_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
50381 
50382 /*
50383  * Field : pid
50384  *
50385  * PID (Pid)
50386  *
50387  * The application programs this field with the type of PID to use For
50388  *
50389  * the initial transaction. The host maintains this field For the rest of
50390  *
50391  * the transfer.
50392  *
50393  * 2'b00: DATA0
50394  *
50395  * 2'b01: DATA2
50396  *
50397  * 2'b10: DATA1
50398  *
50399  * 2'b11: MDATA (non-control)/SETUP (control)
50400  *
50401  * Field Enumeration Values:
50402  *
50403  * Enum | Value | Description
50404  * :----------------------------------|:------|:------------------------------------
50405  * ALT_USB_HOST_HCTSIZ11_PID_E_DATA0 | 0x0 | DATA0
50406  * ALT_USB_HOST_HCTSIZ11_PID_E_DATA2 | 0x1 | DATA2
50407  * ALT_USB_HOST_HCTSIZ11_PID_E_DATA1 | 0x2 | DATA1
50408  * ALT_USB_HOST_HCTSIZ11_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
50409  *
50410  * Field Access Macros:
50411  *
50412  */
50413 /*
50414  * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID
50415  *
50416  * DATA0
50417  */
50418 #define ALT_USB_HOST_HCTSIZ11_PID_E_DATA0 0x0
50419 /*
50420  * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID
50421  *
50422  * DATA2
50423  */
50424 #define ALT_USB_HOST_HCTSIZ11_PID_E_DATA2 0x1
50425 /*
50426  * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID
50427  *
50428  * DATA1
50429  */
50430 #define ALT_USB_HOST_HCTSIZ11_PID_E_DATA1 0x2
50431 /*
50432  * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID
50433  *
50434  * MDATA (non-control)/SETUP (control)
50435  */
50436 #define ALT_USB_HOST_HCTSIZ11_PID_E_MDATA 0x3
50437 
50438 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_PID register field. */
50439 #define ALT_USB_HOST_HCTSIZ11_PID_LSB 29
50440 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_PID register field. */
50441 #define ALT_USB_HOST_HCTSIZ11_PID_MSB 30
50442 /* The width in bits of the ALT_USB_HOST_HCTSIZ11_PID register field. */
50443 #define ALT_USB_HOST_HCTSIZ11_PID_WIDTH 2
50444 /* The mask used to set the ALT_USB_HOST_HCTSIZ11_PID register field value. */
50445 #define ALT_USB_HOST_HCTSIZ11_PID_SET_MSK 0x60000000
50446 /* The mask used to clear the ALT_USB_HOST_HCTSIZ11_PID register field value. */
50447 #define ALT_USB_HOST_HCTSIZ11_PID_CLR_MSK 0x9fffffff
50448 /* The reset value of the ALT_USB_HOST_HCTSIZ11_PID register field. */
50449 #define ALT_USB_HOST_HCTSIZ11_PID_RESET 0x0
50450 /* Extracts the ALT_USB_HOST_HCTSIZ11_PID field value from a register. */
50451 #define ALT_USB_HOST_HCTSIZ11_PID_GET(value) (((value) & 0x60000000) >> 29)
50452 /* Produces a ALT_USB_HOST_HCTSIZ11_PID register field value suitable for setting the register. */
50453 #define ALT_USB_HOST_HCTSIZ11_PID_SET(value) (((value) << 29) & 0x60000000)
50454 
50455 /*
50456  * Field : dopng
50457  *
50458  * Do Ping (DoPng)
50459  *
50460  * This bit is used only For OUT transfers.
50461  *
50462  * Setting this field to 1 directs the host to do PING protocol.
50463  *
50464  * Note: Do not Set this bit For IN transfers. If this bit is Set For
50465  *
50466  * for IN transfers it disables the channel.
50467  *
50468  * Field Enumeration Values:
50469  *
50470  * Enum | Value | Description
50471  * :-------------------------------------|:------|:-----------------
50472  * ALT_USB_HOST_HCTSIZ11_DOPNG_E_NOPING | 0x0 | No ping protocol
50473  * ALT_USB_HOST_HCTSIZ11_DOPNG_E_PING | 0x1 | Ping protocol
50474  *
50475  * Field Access Macros:
50476  *
50477  */
50478 /*
50479  * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_DOPNG
50480  *
50481  * No ping protocol
50482  */
50483 #define ALT_USB_HOST_HCTSIZ11_DOPNG_E_NOPING 0x0
50484 /*
50485  * Enumerated value for register field ALT_USB_HOST_HCTSIZ11_DOPNG
50486  *
50487  * Ping protocol
50488  */
50489 #define ALT_USB_HOST_HCTSIZ11_DOPNG_E_PING 0x1
50490 
50491 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */
50492 #define ALT_USB_HOST_HCTSIZ11_DOPNG_LSB 31
50493 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */
50494 #define ALT_USB_HOST_HCTSIZ11_DOPNG_MSB 31
50495 /* The width in bits of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */
50496 #define ALT_USB_HOST_HCTSIZ11_DOPNG_WIDTH 1
50497 /* The mask used to set the ALT_USB_HOST_HCTSIZ11_DOPNG register field value. */
50498 #define ALT_USB_HOST_HCTSIZ11_DOPNG_SET_MSK 0x80000000
50499 /* The mask used to clear the ALT_USB_HOST_HCTSIZ11_DOPNG register field value. */
50500 #define ALT_USB_HOST_HCTSIZ11_DOPNG_CLR_MSK 0x7fffffff
50501 /* The reset value of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */
50502 #define ALT_USB_HOST_HCTSIZ11_DOPNG_RESET 0x0
50503 /* Extracts the ALT_USB_HOST_HCTSIZ11_DOPNG field value from a register. */
50504 #define ALT_USB_HOST_HCTSIZ11_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
50505 /* Produces a ALT_USB_HOST_HCTSIZ11_DOPNG register field value suitable for setting the register. */
50506 #define ALT_USB_HOST_HCTSIZ11_DOPNG_SET(value) (((value) << 31) & 0x80000000)
50507 
50508 #ifndef __ASSEMBLY__
50509 /*
50510  * WARNING: The C register and register group struct declarations are provided for
50511  * convenience and illustrative purposes. They should, however, be used with
50512  * caution as the C language standard provides no guarantees about the alignment or
50513  * atomicity of device memory accesses. The recommended practice for writing
50514  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50515  * alt_write_word() functions.
50516  *
50517  * The struct declaration for register ALT_USB_HOST_HCTSIZ11.
50518  */
50519 struct ALT_USB_HOST_HCTSIZ11_s
50520 {
50521  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ11_XFERSIZE */
50522  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ11_PKTCNT */
50523  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ11_PID */
50524  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ11_DOPNG */
50525 };
50526 
50527 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ11. */
50528 typedef volatile struct ALT_USB_HOST_HCTSIZ11_s ALT_USB_HOST_HCTSIZ11_t;
50529 #endif /* __ASSEMBLY__ */
50530 
50531 /* The reset value of the ALT_USB_HOST_HCTSIZ11 register. */
50532 #define ALT_USB_HOST_HCTSIZ11_RESET 0x00000000
50533 /* The byte offset of the ALT_USB_HOST_HCTSIZ11 register from the beginning of the component. */
50534 #define ALT_USB_HOST_HCTSIZ11_OFST 0x270
50535 /* The address of the ALT_USB_HOST_HCTSIZ11 register. */
50536 #define ALT_USB_HOST_HCTSIZ11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ11_OFST))
50537 
50538 /*
50539  * Register : hcdma11
50540  *
50541  * Host Channel 11 DMA Address Register
50542  *
50543  * Register Layout
50544  *
50545  * Bits | Access | Reset | Description
50546  * :-------|:-------|:------|:-----------------------------
50547  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA11_HCDMA11
50548  *
50549  */
50550 /*
50551  * Field : hcdma11
50552  *
50553  * Buffer DMA Mode:
50554  *
50555  * [31:0] DMA Address (DMAAddr)
50556  *
50557  * This field holds the start address in the external memory from which the data
50558  * for
50559  *
50560  * the endpoint must be fetched or to which it must be stored. This register is
50561  *
50562  * incremented on every AHB transaction.
50563  *
50564  * Scatter-Gather DMA (DescDMA) Mode:
50565  *
50566  * [31:9] (Non Isoc) Non-Isochronous:
50567  *
50568  * [31:N] (Isoc) Isochronous:
50569  *
50570  * This field holds the start address of the 512 bytes
50571  *
50572  * page. The first descriptor in the list should be located
50573  *
50574  * in this address. The first descriptor may be or may
50575  *
50576  * not be ready. The core starts processing the list from
50577  *
50578  * the CTD value.
50579  *
50580  * This field holds the address of the 2*(nTD+1) bytes of
50581  *
50582  * locations in which the isochronous descriptors are
50583  *
50584  * present where N is based on nTD as per Table below
50585  *
50586  * [31:N] Base Address
50587  *
50588  * [N-1:3] Offset
50589  *
50590  * [2:0] 000
50591  *
50592  * HS ISOC
50593  *
50594  * nTD N
50595  *
50596  * 7 6
50597  *
50598  * 15 7
50599  *
50600  * 31 8
50601  *
50602  * 63 9
50603  *
50604  * 127 10
50605  *
50606  * 255 11
50607  *
50608  * FS ISOC
50609  *
50610  * nTD N
50611  *
50612  * 1 4
50613  *
50614  * 3 5
50615  *
50616  * 7 6
50617  *
50618  * 15 7
50619  *
50620  * 31 8
50621  *
50622  * 63 9
50623  *
50624  * [N-1:3] (Isoc):
50625  *
50626  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
50627  *
50628  * Non Isochronous:
50629  *
50630  * This value is in terms of number of descriptors. The values can be from 0 to 63.
50631  *
50632  * 0 - 1 descriptor.
50633  *
50634  * 63 - 64 descriptors.
50635  *
50636  * This field indicates the current descriptor processed in the list. This field is
50637  * updated
50638  *
50639  * both by application and the core. For example, if the application enables the
50640  *
50641  * channel after programming CTD=5, then the core will start processing the 6th
50642  *
50643  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
50644  *
50645  * to DMAAddr.
50646  *
50647  * Isochronous:
50648  *
50649  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
50650  * set
50651  *
50652  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
50653  *
50654  * [31:9] (Non Isoc) Non-Isochronous:
50655  *
50656  * [31:N] (Isoc) Isochronous:
50657  *
50658  * This field holds the start address of the 512 bytes
50659  *
50660  * page. The first descriptor in the list should be located
50661  *
50662  * in this address. The first descriptor may be or may
50663  *
50664  * not be ready. The core starts processing the list from
50665  *
50666  * the CTD value.
50667  *
50668  * This field holds the address of the 2*(nTD+1) bytes of
50669  *
50670  * locations in which the isochronous descriptors are
50671  *
50672  * present where N is based on nTD as per Table below
50673  *
50674  * [31:N] Base Address
50675  *
50676  * [N-1:3] Offset
50677  *
50678  * [2:0] 000
50679  *
50680  * HS ISOC
50681  *
50682  * nTD N
50683  *
50684  * 7 6
50685  *
50686  * 15 7
50687  *
50688  * 31 8
50689  *
50690  * 63 9
50691  *
50692  * 127 10
50693  *
50694  * 255 11
50695  *
50696  * FS ISOC
50697  *
50698  * nTD N
50699  *
50700  * 1 4
50701  *
50702  * 3 5
50703  *
50704  * 7 6
50705  *
50706  * 15 7
50707  *
50708  * 31 8
50709  *
50710  * 63 9
50711  *
50712  * [N-1:3] (Isoc):
50713  *
50714  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
50715  *
50716  * Non Isochronous:
50717  *
50718  * This value is in terms of number of descriptors. The values can be from 0 to 63.
50719  *
50720  * 0 - 1 descriptor.
50721  *
50722  * 63 - 64 descriptors.
50723  *
50724  * This field indicates the current descriptor processed in the list. This field is
50725  * updated
50726  *
50727  * both by application and the core. For example, if the application enables the
50728  *
50729  * channel after programming CTD=5, then the core will start processing the 6th
50730  *
50731  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
50732  *
50733  * to DMAAddr.
50734  *
50735  * Isochronous:
50736  *
50737  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
50738  * set
50739  *
50740  * to zero by application.
50741  *
50742  * Field Access Macros:
50743  *
50744  */
50745 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */
50746 #define ALT_USB_HOST_HCDMA11_HCDMA11_LSB 0
50747 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */
50748 #define ALT_USB_HOST_HCDMA11_HCDMA11_MSB 31
50749 /* The width in bits of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */
50750 #define ALT_USB_HOST_HCDMA11_HCDMA11_WIDTH 32
50751 /* The mask used to set the ALT_USB_HOST_HCDMA11_HCDMA11 register field value. */
50752 #define ALT_USB_HOST_HCDMA11_HCDMA11_SET_MSK 0xffffffff
50753 /* The mask used to clear the ALT_USB_HOST_HCDMA11_HCDMA11 register field value. */
50754 #define ALT_USB_HOST_HCDMA11_HCDMA11_CLR_MSK 0x00000000
50755 /* The reset value of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */
50756 #define ALT_USB_HOST_HCDMA11_HCDMA11_RESET 0x0
50757 /* Extracts the ALT_USB_HOST_HCDMA11_HCDMA11 field value from a register. */
50758 #define ALT_USB_HOST_HCDMA11_HCDMA11_GET(value) (((value) & 0xffffffff) >> 0)
50759 /* Produces a ALT_USB_HOST_HCDMA11_HCDMA11 register field value suitable for setting the register. */
50760 #define ALT_USB_HOST_HCDMA11_HCDMA11_SET(value) (((value) << 0) & 0xffffffff)
50761 
50762 #ifndef __ASSEMBLY__
50763 /*
50764  * WARNING: The C register and register group struct declarations are provided for
50765  * convenience and illustrative purposes. They should, however, be used with
50766  * caution as the C language standard provides no guarantees about the alignment or
50767  * atomicity of device memory accesses. The recommended practice for writing
50768  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50769  * alt_write_word() functions.
50770  *
50771  * The struct declaration for register ALT_USB_HOST_HCDMA11.
50772  */
50773 struct ALT_USB_HOST_HCDMA11_s
50774 {
50775  uint32_t hcdma11 : 32; /* ALT_USB_HOST_HCDMA11_HCDMA11 */
50776 };
50777 
50778 /* The typedef declaration for register ALT_USB_HOST_HCDMA11. */
50779 typedef volatile struct ALT_USB_HOST_HCDMA11_s ALT_USB_HOST_HCDMA11_t;
50780 #endif /* __ASSEMBLY__ */
50781 
50782 /* The reset value of the ALT_USB_HOST_HCDMA11 register. */
50783 #define ALT_USB_HOST_HCDMA11_RESET 0x00000000
50784 /* The byte offset of the ALT_USB_HOST_HCDMA11 register from the beginning of the component. */
50785 #define ALT_USB_HOST_HCDMA11_OFST 0x274
50786 /* The address of the ALT_USB_HOST_HCDMA11 register. */
50787 #define ALT_USB_HOST_HCDMA11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA11_OFST))
50788 
50789 /*
50790  * Register : hcdmab11
50791  *
50792  * Host Channel 11 DMA Buffer Address Register
50793  *
50794  * Register Layout
50795  *
50796  * Bits | Access | Reset | Description
50797  * :-------|:-------|:------|:-------------------------------
50798  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB11_HCDMAB11
50799  *
50800  */
50801 /*
50802  * Field : hcdmab11
50803  *
50804  * Holds the current buffer address.
50805  *
50806  * This register is updated as and when the data transfer for the corresponding end
50807  * point
50808  *
50809  * is in progress. This register is present only in Scatter/Gather DMA mode.
50810  * Otherwise this
50811  *
50812  * field is reserved.
50813  *
50814  * Field Access Macros:
50815  *
50816  */
50817 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */
50818 #define ALT_USB_HOST_HCDMAB11_HCDMAB11_LSB 0
50819 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */
50820 #define ALT_USB_HOST_HCDMAB11_HCDMAB11_MSB 31
50821 /* The width in bits of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */
50822 #define ALT_USB_HOST_HCDMAB11_HCDMAB11_WIDTH 32
50823 /* The mask used to set the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field value. */
50824 #define ALT_USB_HOST_HCDMAB11_HCDMAB11_SET_MSK 0xffffffff
50825 /* The mask used to clear the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field value. */
50826 #define ALT_USB_HOST_HCDMAB11_HCDMAB11_CLR_MSK 0x00000000
50827 /* The reset value of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */
50828 #define ALT_USB_HOST_HCDMAB11_HCDMAB11_RESET 0x0
50829 /* Extracts the ALT_USB_HOST_HCDMAB11_HCDMAB11 field value from a register. */
50830 #define ALT_USB_HOST_HCDMAB11_HCDMAB11_GET(value) (((value) & 0xffffffff) >> 0)
50831 /* Produces a ALT_USB_HOST_HCDMAB11_HCDMAB11 register field value suitable for setting the register. */
50832 #define ALT_USB_HOST_HCDMAB11_HCDMAB11_SET(value) (((value) << 0) & 0xffffffff)
50833 
50834 #ifndef __ASSEMBLY__
50835 /*
50836  * WARNING: The C register and register group struct declarations are provided for
50837  * convenience and illustrative purposes. They should, however, be used with
50838  * caution as the C language standard provides no guarantees about the alignment or
50839  * atomicity of device memory accesses. The recommended practice for writing
50840  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50841  * alt_write_word() functions.
50842  *
50843  * The struct declaration for register ALT_USB_HOST_HCDMAB11.
50844  */
50845 struct ALT_USB_HOST_HCDMAB11_s
50846 {
50847  uint32_t hcdmab11 : 32; /* ALT_USB_HOST_HCDMAB11_HCDMAB11 */
50848 };
50849 
50850 /* The typedef declaration for register ALT_USB_HOST_HCDMAB11. */
50851 typedef volatile struct ALT_USB_HOST_HCDMAB11_s ALT_USB_HOST_HCDMAB11_t;
50852 #endif /* __ASSEMBLY__ */
50853 
50854 /* The reset value of the ALT_USB_HOST_HCDMAB11 register. */
50855 #define ALT_USB_HOST_HCDMAB11_RESET 0x00000000
50856 /* The byte offset of the ALT_USB_HOST_HCDMAB11 register from the beginning of the component. */
50857 #define ALT_USB_HOST_HCDMAB11_OFST 0x27c
50858 /* The address of the ALT_USB_HOST_HCDMAB11 register. */
50859 #define ALT_USB_HOST_HCDMAB11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB11_OFST))
50860 
50861 /*
50862  * Register : hcchar12
50863  *
50864  * Host Channel 12 Characteristics Register
50865  *
50866  * Register Layout
50867  *
50868  * Bits | Access | Reset | Description
50869  * :--------|:---------|:------|:------------------------------
50870  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_MPS
50871  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_EPNUM
50872  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_EPDIR
50873  * [16] | ??? | 0x0 | *UNDEFINED*
50874  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_LSPDDEV
50875  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_EPTYPE
50876  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_EC
50877  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_DEVADDR
50878  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_ODDFRM
50879  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR12_CHDIS
50880  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR12_CHENA
50881  *
50882  */
50883 /*
50884  * Field : mps
50885  *
50886  * Maximum Packet Size (MPS)
50887  *
50888  * Indicates the maximum packet size of the associated endpoint.
50889  *
50890  * Field Access Macros:
50891  *
50892  */
50893 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_MPS register field. */
50894 #define ALT_USB_HOST_HCCHAR12_MPS_LSB 0
50895 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_MPS register field. */
50896 #define ALT_USB_HOST_HCCHAR12_MPS_MSB 10
50897 /* The width in bits of the ALT_USB_HOST_HCCHAR12_MPS register field. */
50898 #define ALT_USB_HOST_HCCHAR12_MPS_WIDTH 11
50899 /* The mask used to set the ALT_USB_HOST_HCCHAR12_MPS register field value. */
50900 #define ALT_USB_HOST_HCCHAR12_MPS_SET_MSK 0x000007ff
50901 /* The mask used to clear the ALT_USB_HOST_HCCHAR12_MPS register field value. */
50902 #define ALT_USB_HOST_HCCHAR12_MPS_CLR_MSK 0xfffff800
50903 /* The reset value of the ALT_USB_HOST_HCCHAR12_MPS register field. */
50904 #define ALT_USB_HOST_HCCHAR12_MPS_RESET 0x0
50905 /* Extracts the ALT_USB_HOST_HCCHAR12_MPS field value from a register. */
50906 #define ALT_USB_HOST_HCCHAR12_MPS_GET(value) (((value) & 0x000007ff) >> 0)
50907 /* Produces a ALT_USB_HOST_HCCHAR12_MPS register field value suitable for setting the register. */
50908 #define ALT_USB_HOST_HCCHAR12_MPS_SET(value) (((value) << 0) & 0x000007ff)
50909 
50910 /*
50911  * Field : epnum
50912  *
50913  * Endpoint Number (EPNum)
50914  *
50915  * Indicates the endpoint number on the device serving as the data
50916  *
50917  * source or sink.
50918  *
50919  * Field Enumeration Values:
50920  *
50921  * Enum | Value | Description
50922  * :--------------------------------------|:------|:--------------
50923  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT0 | 0x0 | End point 0
50924  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT1 | 0x1 | End point 1
50925  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT2 | 0x2 | End point 2
50926  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT3 | 0x3 | End point 3
50927  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT4 | 0x4 | End point 4
50928  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT5 | 0x5 | End point 5
50929  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT6 | 0x6 | End point 6
50930  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT7 | 0x7 | End point 7
50931  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT8 | 0x8 | End point 8
50932  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT9 | 0x9 | End point 9
50933  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT10 | 0xa | End point 10
50934  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT11 | 0xb | End point 11
50935  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT12 | 0xc | End point 12
50936  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT13 | 0xd | End point 13
50937  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT14 | 0xe | End point 14
50938  * ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT15 | 0xf | End point 15
50939  *
50940  * Field Access Macros:
50941  *
50942  */
50943 /*
50944  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
50945  *
50946  * End point 0
50947  */
50948 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT0 0x0
50949 /*
50950  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
50951  *
50952  * End point 1
50953  */
50954 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT1 0x1
50955 /*
50956  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
50957  *
50958  * End point 2
50959  */
50960 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT2 0x2
50961 /*
50962  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
50963  *
50964  * End point 3
50965  */
50966 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT3 0x3
50967 /*
50968  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
50969  *
50970  * End point 4
50971  */
50972 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT4 0x4
50973 /*
50974  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
50975  *
50976  * End point 5
50977  */
50978 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT5 0x5
50979 /*
50980  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
50981  *
50982  * End point 6
50983  */
50984 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT6 0x6
50985 /*
50986  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
50987  *
50988  * End point 7
50989  */
50990 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT7 0x7
50991 /*
50992  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
50993  *
50994  * End point 8
50995  */
50996 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT8 0x8
50997 /*
50998  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
50999  *
51000  * End point 9
51001  */
51002 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT9 0x9
51003 /*
51004  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
51005  *
51006  * End point 10
51007  */
51008 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT10 0xa
51009 /*
51010  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
51011  *
51012  * End point 11
51013  */
51014 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT11 0xb
51015 /*
51016  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
51017  *
51018  * End point 12
51019  */
51020 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT12 0xc
51021 /*
51022  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
51023  *
51024  * End point 13
51025  */
51026 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT13 0xd
51027 /*
51028  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
51029  *
51030  * End point 14
51031  */
51032 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT14 0xe
51033 /*
51034  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
51035  *
51036  * End point 15
51037  */
51038 #define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT15 0xf
51039 
51040 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */
51041 #define ALT_USB_HOST_HCCHAR12_EPNUM_LSB 11
51042 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */
51043 #define ALT_USB_HOST_HCCHAR12_EPNUM_MSB 14
51044 /* The width in bits of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */
51045 #define ALT_USB_HOST_HCCHAR12_EPNUM_WIDTH 4
51046 /* The mask used to set the ALT_USB_HOST_HCCHAR12_EPNUM register field value. */
51047 #define ALT_USB_HOST_HCCHAR12_EPNUM_SET_MSK 0x00007800
51048 /* The mask used to clear the ALT_USB_HOST_HCCHAR12_EPNUM register field value. */
51049 #define ALT_USB_HOST_HCCHAR12_EPNUM_CLR_MSK 0xffff87ff
51050 /* The reset value of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */
51051 #define ALT_USB_HOST_HCCHAR12_EPNUM_RESET 0x0
51052 /* Extracts the ALT_USB_HOST_HCCHAR12_EPNUM field value from a register. */
51053 #define ALT_USB_HOST_HCCHAR12_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
51054 /* Produces a ALT_USB_HOST_HCCHAR12_EPNUM register field value suitable for setting the register. */
51055 #define ALT_USB_HOST_HCCHAR12_EPNUM_SET(value) (((value) << 11) & 0x00007800)
51056 
51057 /*
51058  * Field : epdir
51059  *
51060  * Endpoint Direction (EPDir)
51061  *
51062  * Indicates whether the transaction is IN or OUT.
51063  *
51064  * 1'b0: OUT
51065  *
51066  * 1'b1: IN
51067  *
51068  * Field Enumeration Values:
51069  *
51070  * Enum | Value | Description
51071  * :----------------------------------|:------|:--------------
51072  * ALT_USB_HOST_HCCHAR12_EPDIR_E_OUT | 0x0 | OUT Direction
51073  * ALT_USB_HOST_HCCHAR12_EPDIR_E_IN | 0x1 | IN Direction
51074  *
51075  * Field Access Macros:
51076  *
51077  */
51078 /*
51079  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPDIR
51080  *
51081  * OUT Direction
51082  */
51083 #define ALT_USB_HOST_HCCHAR12_EPDIR_E_OUT 0x0
51084 /*
51085  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPDIR
51086  *
51087  * IN Direction
51088  */
51089 #define ALT_USB_HOST_HCCHAR12_EPDIR_E_IN 0x1
51090 
51091 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */
51092 #define ALT_USB_HOST_HCCHAR12_EPDIR_LSB 15
51093 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */
51094 #define ALT_USB_HOST_HCCHAR12_EPDIR_MSB 15
51095 /* The width in bits of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */
51096 #define ALT_USB_HOST_HCCHAR12_EPDIR_WIDTH 1
51097 /* The mask used to set the ALT_USB_HOST_HCCHAR12_EPDIR register field value. */
51098 #define ALT_USB_HOST_HCCHAR12_EPDIR_SET_MSK 0x00008000
51099 /* The mask used to clear the ALT_USB_HOST_HCCHAR12_EPDIR register field value. */
51100 #define ALT_USB_HOST_HCCHAR12_EPDIR_CLR_MSK 0xffff7fff
51101 /* The reset value of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */
51102 #define ALT_USB_HOST_HCCHAR12_EPDIR_RESET 0x0
51103 /* Extracts the ALT_USB_HOST_HCCHAR12_EPDIR field value from a register. */
51104 #define ALT_USB_HOST_HCCHAR12_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
51105 /* Produces a ALT_USB_HOST_HCCHAR12_EPDIR register field value suitable for setting the register. */
51106 #define ALT_USB_HOST_HCCHAR12_EPDIR_SET(value) (((value) << 15) & 0x00008000)
51107 
51108 /*
51109  * Field : lspddev
51110  *
51111  * Low-Speed Device (LSpdDev)
51112  *
51113  * This field is Set by the application to indicate that this channel is
51114  *
51115  * communicating to a low-speed device.
51116  *
51117  * Field Enumeration Values:
51118  *
51119  * Enum | Value | Description
51120  * :-------------------------------------|:------|:----------------------------------------
51121  * ALT_USB_HOST_HCCHAR12_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
51122  * ALT_USB_HOST_HCCHAR12_LSPDDEV_E_END | 0x1 | Communicating with low speed device
51123  *
51124  * Field Access Macros:
51125  *
51126  */
51127 /*
51128  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_LSPDDEV
51129  *
51130  * Not Communicating with low speed device
51131  */
51132 #define ALT_USB_HOST_HCCHAR12_LSPDDEV_E_DISD 0x0
51133 /*
51134  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_LSPDDEV
51135  *
51136  * Communicating with low speed device
51137  */
51138 #define ALT_USB_HOST_HCCHAR12_LSPDDEV_E_END 0x1
51139 
51140 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */
51141 #define ALT_USB_HOST_HCCHAR12_LSPDDEV_LSB 17
51142 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */
51143 #define ALT_USB_HOST_HCCHAR12_LSPDDEV_MSB 17
51144 /* The width in bits of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */
51145 #define ALT_USB_HOST_HCCHAR12_LSPDDEV_WIDTH 1
51146 /* The mask used to set the ALT_USB_HOST_HCCHAR12_LSPDDEV register field value. */
51147 #define ALT_USB_HOST_HCCHAR12_LSPDDEV_SET_MSK 0x00020000
51148 /* The mask used to clear the ALT_USB_HOST_HCCHAR12_LSPDDEV register field value. */
51149 #define ALT_USB_HOST_HCCHAR12_LSPDDEV_CLR_MSK 0xfffdffff
51150 /* The reset value of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */
51151 #define ALT_USB_HOST_HCCHAR12_LSPDDEV_RESET 0x0
51152 /* Extracts the ALT_USB_HOST_HCCHAR12_LSPDDEV field value from a register. */
51153 #define ALT_USB_HOST_HCCHAR12_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
51154 /* Produces a ALT_USB_HOST_HCCHAR12_LSPDDEV register field value suitable for setting the register. */
51155 #define ALT_USB_HOST_HCCHAR12_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
51156 
51157 /*
51158  * Field : eptype
51159  *
51160  * Endpoint Type (EPType)
51161  *
51162  * Indicates the transfer type selected.
51163  *
51164  * 2'b00: Control
51165  *
51166  * 2'b01: Isochronous
51167  *
51168  * 2'b10: Bulk
51169  *
51170  * 2'b11: Interrupt
51171  *
51172  * Field Enumeration Values:
51173  *
51174  * Enum | Value | Description
51175  * :--------------------------------------|:------|:------------
51176  * ALT_USB_HOST_HCCHAR12_EPTYPE_E_CTL | 0x0 | Control
51177  * ALT_USB_HOST_HCCHAR12_EPTYPE_E_ISOC | 0x1 | Isochronous
51178  * ALT_USB_HOST_HCCHAR12_EPTYPE_E_BULK | 0x2 | Bulk
51179  * ALT_USB_HOST_HCCHAR12_EPTYPE_E_INTERR | 0x3 | Interrupt
51180  *
51181  * Field Access Macros:
51182  *
51183  */
51184 /*
51185  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE
51186  *
51187  * Control
51188  */
51189 #define ALT_USB_HOST_HCCHAR12_EPTYPE_E_CTL 0x0
51190 /*
51191  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE
51192  *
51193  * Isochronous
51194  */
51195 #define ALT_USB_HOST_HCCHAR12_EPTYPE_E_ISOC 0x1
51196 /*
51197  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE
51198  *
51199  * Bulk
51200  */
51201 #define ALT_USB_HOST_HCCHAR12_EPTYPE_E_BULK 0x2
51202 /*
51203  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE
51204  *
51205  * Interrupt
51206  */
51207 #define ALT_USB_HOST_HCCHAR12_EPTYPE_E_INTERR 0x3
51208 
51209 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */
51210 #define ALT_USB_HOST_HCCHAR12_EPTYPE_LSB 18
51211 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */
51212 #define ALT_USB_HOST_HCCHAR12_EPTYPE_MSB 19
51213 /* The width in bits of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */
51214 #define ALT_USB_HOST_HCCHAR12_EPTYPE_WIDTH 2
51215 /* The mask used to set the ALT_USB_HOST_HCCHAR12_EPTYPE register field value. */
51216 #define ALT_USB_HOST_HCCHAR12_EPTYPE_SET_MSK 0x000c0000
51217 /* The mask used to clear the ALT_USB_HOST_HCCHAR12_EPTYPE register field value. */
51218 #define ALT_USB_HOST_HCCHAR12_EPTYPE_CLR_MSK 0xfff3ffff
51219 /* The reset value of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */
51220 #define ALT_USB_HOST_HCCHAR12_EPTYPE_RESET 0x0
51221 /* Extracts the ALT_USB_HOST_HCCHAR12_EPTYPE field value from a register. */
51222 #define ALT_USB_HOST_HCCHAR12_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
51223 /* Produces a ALT_USB_HOST_HCCHAR12_EPTYPE register field value suitable for setting the register. */
51224 #define ALT_USB_HOST_HCCHAR12_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
51225 
51226 /*
51227  * Field : ec
51228  *
51229  * Multi Count (MC) / Error Count (EC)
51230  *
51231  * When the Split Enable bit of the Host Channel-n Split Control
51232  *
51233  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
51234  *
51235  * the host the number of transactions that must be executed per
51236  *
51237  * microframe For this periodic endpoint. For non periodic transfers,
51238  *
51239  * this field is used only in DMA mode, and specifies the number
51240  *
51241  * packets to be fetched For this channel before the internal DMA
51242  *
51243  * engine changes arbitration.
51244  *
51245  * 2'b00: Reserved This field yields undefined results.
51246  *
51247  * 2'b01: 1 transaction
51248  *
51249  * 2'b10: 2 transactions to be issued For this endpoint per
51250  *
51251  * microframe
51252  *
51253  * 2'b11: 3 transactions to be issued For this endpoint per
51254  *
51255  * microframe
51256  *
51257  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
51258  *
51259  * number of immediate retries to be performed For a periodic split
51260  *
51261  * transactions on transaction errors. This field must be Set to at
51262  *
51263  * least 2'b01.
51264  *
51265  * Field Enumeration Values:
51266  *
51267  * Enum | Value | Description
51268  * :--------------------------------------|:------|:----------------------------------------------
51269  * ALT_USB_HOST_HCCHAR12_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
51270  * ALT_USB_HOST_HCCHAR12_EC_E_TRANSONE | 0x1 | 1 transaction
51271  * ALT_USB_HOST_HCCHAR12_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
51272  * : | | per microframe
51273  * ALT_USB_HOST_HCCHAR12_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
51274  * : | | per microframe
51275  *
51276  * Field Access Macros:
51277  *
51278  */
51279 /*
51280  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC
51281  *
51282  * Reserved This field yields undefined result
51283  */
51284 #define ALT_USB_HOST_HCCHAR12_EC_E_RSVD 0x0
51285 /*
51286  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC
51287  *
51288  * 1 transaction
51289  */
51290 #define ALT_USB_HOST_HCCHAR12_EC_E_TRANSONE 0x1
51291 /*
51292  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC
51293  *
51294  * 2 transactions to be issued for this endpoint per microframe
51295  */
51296 #define ALT_USB_HOST_HCCHAR12_EC_E_TRANSTWO 0x2
51297 /*
51298  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC
51299  *
51300  * 3 transactions to be issued for this endpoint per microframe
51301  */
51302 #define ALT_USB_HOST_HCCHAR12_EC_E_TRANSTHREE 0x3
51303 
51304 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EC register field. */
51305 #define ALT_USB_HOST_HCCHAR12_EC_LSB 20
51306 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EC register field. */
51307 #define ALT_USB_HOST_HCCHAR12_EC_MSB 21
51308 /* The width in bits of the ALT_USB_HOST_HCCHAR12_EC register field. */
51309 #define ALT_USB_HOST_HCCHAR12_EC_WIDTH 2
51310 /* The mask used to set the ALT_USB_HOST_HCCHAR12_EC register field value. */
51311 #define ALT_USB_HOST_HCCHAR12_EC_SET_MSK 0x00300000
51312 /* The mask used to clear the ALT_USB_HOST_HCCHAR12_EC register field value. */
51313 #define ALT_USB_HOST_HCCHAR12_EC_CLR_MSK 0xffcfffff
51314 /* The reset value of the ALT_USB_HOST_HCCHAR12_EC register field. */
51315 #define ALT_USB_HOST_HCCHAR12_EC_RESET 0x0
51316 /* Extracts the ALT_USB_HOST_HCCHAR12_EC field value from a register. */
51317 #define ALT_USB_HOST_HCCHAR12_EC_GET(value) (((value) & 0x00300000) >> 20)
51318 /* Produces a ALT_USB_HOST_HCCHAR12_EC register field value suitable for setting the register. */
51319 #define ALT_USB_HOST_HCCHAR12_EC_SET(value) (((value) << 20) & 0x00300000)
51320 
51321 /*
51322  * Field : devaddr
51323  *
51324  * Device Address (DevAddr)
51325  *
51326  * This field selects the specific device serving as the data source
51327  *
51328  * or sink.
51329  *
51330  * Field Access Macros:
51331  *
51332  */
51333 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */
51334 #define ALT_USB_HOST_HCCHAR12_DEVADDR_LSB 22
51335 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */
51336 #define ALT_USB_HOST_HCCHAR12_DEVADDR_MSB 28
51337 /* The width in bits of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */
51338 #define ALT_USB_HOST_HCCHAR12_DEVADDR_WIDTH 7
51339 /* The mask used to set the ALT_USB_HOST_HCCHAR12_DEVADDR register field value. */
51340 #define ALT_USB_HOST_HCCHAR12_DEVADDR_SET_MSK 0x1fc00000
51341 /* The mask used to clear the ALT_USB_HOST_HCCHAR12_DEVADDR register field value. */
51342 #define ALT_USB_HOST_HCCHAR12_DEVADDR_CLR_MSK 0xe03fffff
51343 /* The reset value of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */
51344 #define ALT_USB_HOST_HCCHAR12_DEVADDR_RESET 0x0
51345 /* Extracts the ALT_USB_HOST_HCCHAR12_DEVADDR field value from a register. */
51346 #define ALT_USB_HOST_HCCHAR12_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
51347 /* Produces a ALT_USB_HOST_HCCHAR12_DEVADDR register field value suitable for setting the register. */
51348 #define ALT_USB_HOST_HCCHAR12_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
51349 
51350 /*
51351  * Field : oddfrm
51352  *
51353  * Odd Frame (OddFrm)
51354  *
51355  * This field is set (reset) by the application to indicate that the OTG host must
51356  * perform
51357  *
51358  * a transfer in an odd (micro)frame. This field is applicable for only periodic
51359  *
51360  * (isochronous and interrupt) transactions.
51361  *
51362  * 1'b0: Even (micro)frame
51363  *
51364  * 1'b1: Odd (micro)frame
51365  *
51366  * Field Access Macros:
51367  *
51368  */
51369 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_ODDFRM register field. */
51370 #define ALT_USB_HOST_HCCHAR12_ODDFRM_LSB 29
51371 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_ODDFRM register field. */
51372 #define ALT_USB_HOST_HCCHAR12_ODDFRM_MSB 29
51373 /* The width in bits of the ALT_USB_HOST_HCCHAR12_ODDFRM register field. */
51374 #define ALT_USB_HOST_HCCHAR12_ODDFRM_WIDTH 1
51375 /* The mask used to set the ALT_USB_HOST_HCCHAR12_ODDFRM register field value. */
51376 #define ALT_USB_HOST_HCCHAR12_ODDFRM_SET_MSK 0x20000000
51377 /* The mask used to clear the ALT_USB_HOST_HCCHAR12_ODDFRM register field value. */
51378 #define ALT_USB_HOST_HCCHAR12_ODDFRM_CLR_MSK 0xdfffffff
51379 /* The reset value of the ALT_USB_HOST_HCCHAR12_ODDFRM register field. */
51380 #define ALT_USB_HOST_HCCHAR12_ODDFRM_RESET 0x0
51381 /* Extracts the ALT_USB_HOST_HCCHAR12_ODDFRM field value from a register. */
51382 #define ALT_USB_HOST_HCCHAR12_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
51383 /* Produces a ALT_USB_HOST_HCCHAR12_ODDFRM register field value suitable for setting the register. */
51384 #define ALT_USB_HOST_HCCHAR12_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
51385 
51386 /*
51387  * Field : chdis
51388  *
51389  * Channel Disable (ChDis)
51390  *
51391  * The application sets this bit to stop transmitting/receiving data
51392  *
51393  * on a channel, even before the transfer For that channel is
51394  *
51395  * complete. The application must wait For the Channel Disabled
51396  *
51397  * interrupt before treating the channel as disabled.
51398  *
51399  * Field Enumeration Values:
51400  *
51401  * Enum | Value | Description
51402  * :------------------------------------|:------|:----------------------------
51403  * ALT_USB_HOST_HCCHAR12_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
51404  * ALT_USB_HOST_HCCHAR12_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
51405  *
51406  * Field Access Macros:
51407  *
51408  */
51409 /*
51410  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHDIS
51411  *
51412  * Transmit/Recieve normal
51413  */
51414 #define ALT_USB_HOST_HCCHAR12_CHDIS_E_INACT 0x0
51415 /*
51416  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHDIS
51417  *
51418  * Stop transmitting/receiving
51419  */
51420 #define ALT_USB_HOST_HCCHAR12_CHDIS_E_ACT 0x1
51421 
51422 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */
51423 #define ALT_USB_HOST_HCCHAR12_CHDIS_LSB 30
51424 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */
51425 #define ALT_USB_HOST_HCCHAR12_CHDIS_MSB 30
51426 /* The width in bits of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */
51427 #define ALT_USB_HOST_HCCHAR12_CHDIS_WIDTH 1
51428 /* The mask used to set the ALT_USB_HOST_HCCHAR12_CHDIS register field value. */
51429 #define ALT_USB_HOST_HCCHAR12_CHDIS_SET_MSK 0x40000000
51430 /* The mask used to clear the ALT_USB_HOST_HCCHAR12_CHDIS register field value. */
51431 #define ALT_USB_HOST_HCCHAR12_CHDIS_CLR_MSK 0xbfffffff
51432 /* The reset value of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */
51433 #define ALT_USB_HOST_HCCHAR12_CHDIS_RESET 0x0
51434 /* Extracts the ALT_USB_HOST_HCCHAR12_CHDIS field value from a register. */
51435 #define ALT_USB_HOST_HCCHAR12_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
51436 /* Produces a ALT_USB_HOST_HCCHAR12_CHDIS register field value suitable for setting the register. */
51437 #define ALT_USB_HOST_HCCHAR12_CHDIS_SET(value) (((value) << 30) & 0x40000000)
51438 
51439 /*
51440  * Field : chena
51441  *
51442  * Channel Enable (ChEna)
51443  *
51444  * When Scatter/Gather mode is enabled
51445  *
51446  * 1'b0: Indicates that the descriptor structure is not yet ready.
51447  *
51448  * 1'b1: Indicates that the descriptor structure and data buffer with
51449  *
51450  * data is setup and this channel can access the descriptor.
51451  *
51452  * When Scatter/Gather mode is disabled
51453  *
51454  * This field is set by the application and cleared by the OTG host.
51455  *
51456  * 1'b0: Channel disabled
51457  *
51458  * 1'b1: Channel enabled
51459  *
51460  * Field Enumeration Values:
51461  *
51462  * Enum | Value | Description
51463  * :------------------------------------|:------|:-------------------------------------------------
51464  * ALT_USB_HOST_HCCHAR12_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
51465  * : | | yet ready
51466  * ALT_USB_HOST_HCCHAR12_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
51467  * : | | data buffer with data is setup and this
51468  * : | | channel can access the descriptor
51469  *
51470  * Field Access Macros:
51471  *
51472  */
51473 /*
51474  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHENA
51475  *
51476  * Indicates that the descriptor structure is not yet ready
51477  */
51478 #define ALT_USB_HOST_HCCHAR12_CHENA_E_INACT 0x0
51479 /*
51480  * Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHENA
51481  *
51482  * Indicates that the descriptor structure and data buffer with data is
51483  * setup and this channel can access the descriptor
51484  */
51485 #define ALT_USB_HOST_HCCHAR12_CHENA_E_ACT 0x1
51486 
51487 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_CHENA register field. */
51488 #define ALT_USB_HOST_HCCHAR12_CHENA_LSB 31
51489 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_CHENA register field. */
51490 #define ALT_USB_HOST_HCCHAR12_CHENA_MSB 31
51491 /* The width in bits of the ALT_USB_HOST_HCCHAR12_CHENA register field. */
51492 #define ALT_USB_HOST_HCCHAR12_CHENA_WIDTH 1
51493 /* The mask used to set the ALT_USB_HOST_HCCHAR12_CHENA register field value. */
51494 #define ALT_USB_HOST_HCCHAR12_CHENA_SET_MSK 0x80000000
51495 /* The mask used to clear the ALT_USB_HOST_HCCHAR12_CHENA register field value. */
51496 #define ALT_USB_HOST_HCCHAR12_CHENA_CLR_MSK 0x7fffffff
51497 /* The reset value of the ALT_USB_HOST_HCCHAR12_CHENA register field. */
51498 #define ALT_USB_HOST_HCCHAR12_CHENA_RESET 0x0
51499 /* Extracts the ALT_USB_HOST_HCCHAR12_CHENA field value from a register. */
51500 #define ALT_USB_HOST_HCCHAR12_CHENA_GET(value) (((value) & 0x80000000) >> 31)
51501 /* Produces a ALT_USB_HOST_HCCHAR12_CHENA register field value suitable for setting the register. */
51502 #define ALT_USB_HOST_HCCHAR12_CHENA_SET(value) (((value) << 31) & 0x80000000)
51503 
51504 #ifndef __ASSEMBLY__
51505 /*
51506  * WARNING: The C register and register group struct declarations are provided for
51507  * convenience and illustrative purposes. They should, however, be used with
51508  * caution as the C language standard provides no guarantees about the alignment or
51509  * atomicity of device memory accesses. The recommended practice for writing
51510  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51511  * alt_write_word() functions.
51512  *
51513  * The struct declaration for register ALT_USB_HOST_HCCHAR12.
51514  */
51515 struct ALT_USB_HOST_HCCHAR12_s
51516 {
51517  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR12_MPS */
51518  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR12_EPNUM */
51519  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR12_EPDIR */
51520  uint32_t : 1; /* *UNDEFINED* */
51521  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR12_LSPDDEV */
51522  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR12_EPTYPE */
51523  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR12_EC */
51524  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR12_DEVADDR */
51525  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR12_ODDFRM */
51526  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR12_CHDIS */
51527  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR12_CHENA */
51528 };
51529 
51530 /* The typedef declaration for register ALT_USB_HOST_HCCHAR12. */
51531 typedef volatile struct ALT_USB_HOST_HCCHAR12_s ALT_USB_HOST_HCCHAR12_t;
51532 #endif /* __ASSEMBLY__ */
51533 
51534 /* The reset value of the ALT_USB_HOST_HCCHAR12 register. */
51535 #define ALT_USB_HOST_HCCHAR12_RESET 0x00000000
51536 /* The byte offset of the ALT_USB_HOST_HCCHAR12 register from the beginning of the component. */
51537 #define ALT_USB_HOST_HCCHAR12_OFST 0x280
51538 /* The address of the ALT_USB_HOST_HCCHAR12 register. */
51539 #define ALT_USB_HOST_HCCHAR12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR12_OFST))
51540 
51541 /*
51542  * Register : hcsplt12
51543  *
51544  * Host Channel 12 Split Control Register
51545  *
51546  * Register Layout
51547  *
51548  * Bits | Access | Reset | Description
51549  * :--------|:-------|:------|:-------------------------------
51550  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT12_PRTADDR
51551  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT12_HUBADDR
51552  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT12_XACTPOS
51553  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT12_COMPSPLT
51554  * [30:17] | ??? | 0x0 | *UNDEFINED*
51555  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT12_SPLTENA
51556  *
51557  */
51558 /*
51559  * Field : prtaddr
51560  *
51561  * Port Address (PrtAddr)
51562  *
51563  * This field is the port number of the recipient transaction
51564  *
51565  * translator.
51566  *
51567  * Field Access Macros:
51568  *
51569  */
51570 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */
51571 #define ALT_USB_HOST_HCSPLT12_PRTADDR_LSB 0
51572 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */
51573 #define ALT_USB_HOST_HCSPLT12_PRTADDR_MSB 6
51574 /* The width in bits of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */
51575 #define ALT_USB_HOST_HCSPLT12_PRTADDR_WIDTH 7
51576 /* The mask used to set the ALT_USB_HOST_HCSPLT12_PRTADDR register field value. */
51577 #define ALT_USB_HOST_HCSPLT12_PRTADDR_SET_MSK 0x0000007f
51578 /* The mask used to clear the ALT_USB_HOST_HCSPLT12_PRTADDR register field value. */
51579 #define ALT_USB_HOST_HCSPLT12_PRTADDR_CLR_MSK 0xffffff80
51580 /* The reset value of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */
51581 #define ALT_USB_HOST_HCSPLT12_PRTADDR_RESET 0x0
51582 /* Extracts the ALT_USB_HOST_HCSPLT12_PRTADDR field value from a register. */
51583 #define ALT_USB_HOST_HCSPLT12_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
51584 /* Produces a ALT_USB_HOST_HCSPLT12_PRTADDR register field value suitable for setting the register. */
51585 #define ALT_USB_HOST_HCSPLT12_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
51586 
51587 /*
51588  * Field : hubaddr
51589  *
51590  * Hub Address (HubAddr)
51591  *
51592  * This field holds the device address of the transaction translator's
51593  *
51594  * hub.
51595  *
51596  * Field Access Macros:
51597  *
51598  */
51599 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */
51600 #define ALT_USB_HOST_HCSPLT12_HUBADDR_LSB 7
51601 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */
51602 #define ALT_USB_HOST_HCSPLT12_HUBADDR_MSB 13
51603 /* The width in bits of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */
51604 #define ALT_USB_HOST_HCSPLT12_HUBADDR_WIDTH 7
51605 /* The mask used to set the ALT_USB_HOST_HCSPLT12_HUBADDR register field value. */
51606 #define ALT_USB_HOST_HCSPLT12_HUBADDR_SET_MSK 0x00003f80
51607 /* The mask used to clear the ALT_USB_HOST_HCSPLT12_HUBADDR register field value. */
51608 #define ALT_USB_HOST_HCSPLT12_HUBADDR_CLR_MSK 0xffffc07f
51609 /* The reset value of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */
51610 #define ALT_USB_HOST_HCSPLT12_HUBADDR_RESET 0x0
51611 /* Extracts the ALT_USB_HOST_HCSPLT12_HUBADDR field value from a register. */
51612 #define ALT_USB_HOST_HCSPLT12_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
51613 /* Produces a ALT_USB_HOST_HCSPLT12_HUBADDR register field value suitable for setting the register. */
51614 #define ALT_USB_HOST_HCSPLT12_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
51615 
51616 /*
51617  * Field : xactpos
51618  *
51619  * Transaction Position (XactPos)
51620  *
51621  * This field is used to determine whether to send all, first, middle,
51622  *
51623  * or last payloads with each OUT transaction.
51624  *
51625  * 2'b11: All. This is the entire data payload is of this transaction
51626  *
51627  * (which is less than or equal to 188 bytes).
51628  *
51629  * 2'b10: Begin. This is the first data payload of this transaction
51630  *
51631  * (which is larger than 188 bytes).
51632  *
51633  * 2'b00: Mid. This is the middle payload of this transaction
51634  *
51635  * (which is larger than 188 bytes).
51636  *
51637  * 2'b01: End. This is the last payload of this transaction (which
51638  *
51639  * is larger than 188 bytes).
51640  *
51641  * Field Enumeration Values:
51642  *
51643  * Enum | Value | Description
51644  * :---------------------------------------|:------|:------------------------------------------------
51645  * ALT_USB_HOST_HCSPLT12_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
51646  * : | | transaction (which is larger than 188 bytes)
51647  * ALT_USB_HOST_HCSPLT12_XACTPOS_E_END | 0x1 | End. This is the last payload of this
51648  * : | | transaction (which is larger than 188 bytes)
51649  * ALT_USB_HOST_HCSPLT12_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
51650  * : | | transaction (which is larger than 188 bytes)
51651  * ALT_USB_HOST_HCSPLT12_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
51652  * : | | transaction (which is less than or equal to 188
51653  * : | | bytes)
51654  *
51655  * Field Access Macros:
51656  *
51657  */
51658 /*
51659  * Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS
51660  *
51661  * Mid. This is the middle payload of this transaction (which is larger than 188
51662  * bytes)
51663  */
51664 #define ALT_USB_HOST_HCSPLT12_XACTPOS_E_MIDDLE 0x0
51665 /*
51666  * Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS
51667  *
51668  * End. This is the last payload of this transaction (which is larger than 188
51669  * bytes)
51670  */
51671 #define ALT_USB_HOST_HCSPLT12_XACTPOS_E_END 0x1
51672 /*
51673  * Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS
51674  *
51675  * Begin. This is the first data payload of this transaction (which is larger than
51676  * 188 bytes)
51677  */
51678 #define ALT_USB_HOST_HCSPLT12_XACTPOS_E_BEGIN 0x2
51679 /*
51680  * Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS
51681  *
51682  * All. This is the entire data payload is of this transaction (which is less than
51683  * or equal to 188 bytes)
51684  */
51685 #define ALT_USB_HOST_HCSPLT12_XACTPOS_E_ALL 0x3
51686 
51687 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */
51688 #define ALT_USB_HOST_HCSPLT12_XACTPOS_LSB 14
51689 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */
51690 #define ALT_USB_HOST_HCSPLT12_XACTPOS_MSB 15
51691 /* The width in bits of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */
51692 #define ALT_USB_HOST_HCSPLT12_XACTPOS_WIDTH 2
51693 /* The mask used to set the ALT_USB_HOST_HCSPLT12_XACTPOS register field value. */
51694 #define ALT_USB_HOST_HCSPLT12_XACTPOS_SET_MSK 0x0000c000
51695 /* The mask used to clear the ALT_USB_HOST_HCSPLT12_XACTPOS register field value. */
51696 #define ALT_USB_HOST_HCSPLT12_XACTPOS_CLR_MSK 0xffff3fff
51697 /* The reset value of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */
51698 #define ALT_USB_HOST_HCSPLT12_XACTPOS_RESET 0x0
51699 /* Extracts the ALT_USB_HOST_HCSPLT12_XACTPOS field value from a register. */
51700 #define ALT_USB_HOST_HCSPLT12_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
51701 /* Produces a ALT_USB_HOST_HCSPLT12_XACTPOS register field value suitable for setting the register. */
51702 #define ALT_USB_HOST_HCSPLT12_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
51703 
51704 /*
51705  * Field : compsplt
51706  *
51707  * Do Complete Split (CompSplt)
51708  *
51709  * The application sets this field to request the OTG host to perform
51710  *
51711  * a complete split transaction.
51712  *
51713  * Field Enumeration Values:
51714  *
51715  * Enum | Value | Description
51716  * :-----------------------------------------|:------|:---------------------
51717  * ALT_USB_HOST_HCSPLT12_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
51718  * ALT_USB_HOST_HCSPLT12_COMPSPLT_E_SPLIT | 0x1 | Split transaction
51719  *
51720  * Field Access Macros:
51721  *
51722  */
51723 /*
51724  * Enumerated value for register field ALT_USB_HOST_HCSPLT12_COMPSPLT
51725  *
51726  * No split transaction
51727  */
51728 #define ALT_USB_HOST_HCSPLT12_COMPSPLT_E_NOSPLIT 0x0
51729 /*
51730  * Enumerated value for register field ALT_USB_HOST_HCSPLT12_COMPSPLT
51731  *
51732  * Split transaction
51733  */
51734 #define ALT_USB_HOST_HCSPLT12_COMPSPLT_E_SPLIT 0x1
51735 
51736 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */
51737 #define ALT_USB_HOST_HCSPLT12_COMPSPLT_LSB 16
51738 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */
51739 #define ALT_USB_HOST_HCSPLT12_COMPSPLT_MSB 16
51740 /* The width in bits of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */
51741 #define ALT_USB_HOST_HCSPLT12_COMPSPLT_WIDTH 1
51742 /* The mask used to set the ALT_USB_HOST_HCSPLT12_COMPSPLT register field value. */
51743 #define ALT_USB_HOST_HCSPLT12_COMPSPLT_SET_MSK 0x00010000
51744 /* The mask used to clear the ALT_USB_HOST_HCSPLT12_COMPSPLT register field value. */
51745 #define ALT_USB_HOST_HCSPLT12_COMPSPLT_CLR_MSK 0xfffeffff
51746 /* The reset value of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */
51747 #define ALT_USB_HOST_HCSPLT12_COMPSPLT_RESET 0x0
51748 /* Extracts the ALT_USB_HOST_HCSPLT12_COMPSPLT field value from a register. */
51749 #define ALT_USB_HOST_HCSPLT12_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
51750 /* Produces a ALT_USB_HOST_HCSPLT12_COMPSPLT register field value suitable for setting the register. */
51751 #define ALT_USB_HOST_HCSPLT12_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
51752 
51753 /*
51754  * Field : spltena
51755  *
51756  * Split Enable (SpltEna)
51757  *
51758  * The application sets this field to indicate that this channel is
51759  *
51760  * enabled to perform split transactions.
51761  *
51762  * Field Enumeration Values:
51763  *
51764  * Enum | Value | Description
51765  * :-------------------------------------|:------|:------------------
51766  * ALT_USB_HOST_HCSPLT12_SPLTENA_E_DISD | 0x0 | Split not enabled
51767  * ALT_USB_HOST_HCSPLT12_SPLTENA_E_END | 0x1 | Split enabled
51768  *
51769  * Field Access Macros:
51770  *
51771  */
51772 /*
51773  * Enumerated value for register field ALT_USB_HOST_HCSPLT12_SPLTENA
51774  *
51775  * Split not enabled
51776  */
51777 #define ALT_USB_HOST_HCSPLT12_SPLTENA_E_DISD 0x0
51778 /*
51779  * Enumerated value for register field ALT_USB_HOST_HCSPLT12_SPLTENA
51780  *
51781  * Split enabled
51782  */
51783 #define ALT_USB_HOST_HCSPLT12_SPLTENA_E_END 0x1
51784 
51785 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */
51786 #define ALT_USB_HOST_HCSPLT12_SPLTENA_LSB 31
51787 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */
51788 #define ALT_USB_HOST_HCSPLT12_SPLTENA_MSB 31
51789 /* The width in bits of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */
51790 #define ALT_USB_HOST_HCSPLT12_SPLTENA_WIDTH 1
51791 /* The mask used to set the ALT_USB_HOST_HCSPLT12_SPLTENA register field value. */
51792 #define ALT_USB_HOST_HCSPLT12_SPLTENA_SET_MSK 0x80000000
51793 /* The mask used to clear the ALT_USB_HOST_HCSPLT12_SPLTENA register field value. */
51794 #define ALT_USB_HOST_HCSPLT12_SPLTENA_CLR_MSK 0x7fffffff
51795 /* The reset value of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */
51796 #define ALT_USB_HOST_HCSPLT12_SPLTENA_RESET 0x0
51797 /* Extracts the ALT_USB_HOST_HCSPLT12_SPLTENA field value from a register. */
51798 #define ALT_USB_HOST_HCSPLT12_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
51799 /* Produces a ALT_USB_HOST_HCSPLT12_SPLTENA register field value suitable for setting the register. */
51800 #define ALT_USB_HOST_HCSPLT12_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
51801 
51802 #ifndef __ASSEMBLY__
51803 /*
51804  * WARNING: The C register and register group struct declarations are provided for
51805  * convenience and illustrative purposes. They should, however, be used with
51806  * caution as the C language standard provides no guarantees about the alignment or
51807  * atomicity of device memory accesses. The recommended practice for writing
51808  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51809  * alt_write_word() functions.
51810  *
51811  * The struct declaration for register ALT_USB_HOST_HCSPLT12.
51812  */
51813 struct ALT_USB_HOST_HCSPLT12_s
51814 {
51815  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT12_PRTADDR */
51816  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT12_HUBADDR */
51817  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT12_XACTPOS */
51818  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT12_COMPSPLT */
51819  uint32_t : 14; /* *UNDEFINED* */
51820  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT12_SPLTENA */
51821 };
51822 
51823 /* The typedef declaration for register ALT_USB_HOST_HCSPLT12. */
51824 typedef volatile struct ALT_USB_HOST_HCSPLT12_s ALT_USB_HOST_HCSPLT12_t;
51825 #endif /* __ASSEMBLY__ */
51826 
51827 /* The reset value of the ALT_USB_HOST_HCSPLT12 register. */
51828 #define ALT_USB_HOST_HCSPLT12_RESET 0x00000000
51829 /* The byte offset of the ALT_USB_HOST_HCSPLT12 register from the beginning of the component. */
51830 #define ALT_USB_HOST_HCSPLT12_OFST 0x284
51831 /* The address of the ALT_USB_HOST_HCSPLT12 register. */
51832 #define ALT_USB_HOST_HCSPLT12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT12_OFST))
51833 
51834 /*
51835  * Register : hcint12
51836  *
51837  * Host Channel 12 Interrupt Register
51838  *
51839  * Register Layout
51840  *
51841  * Bits | Access | Reset | Description
51842  * :--------|:-------|:------|:---------------------------------------
51843  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT12_XFERCOMPL
51844  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT12_CHHLTD
51845  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT12_AHBERR
51846  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT12_STALL
51847  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT12_NAK
51848  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT12_ACK
51849  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT12_NYET
51850  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT12_XACTERR
51851  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT12_BBLERR
51852  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT12_FRMOVRUN
51853  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT12_DATATGLERR
51854  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT12_BNAINTR
51855  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT12_XCS_XACT_ERR
51856  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR
51857  * [31:14] | ??? | 0x0 | *UNDEFINED*
51858  *
51859  */
51860 /*
51861  * Field : xfercompl
51862  *
51863  * Transfer Completed (XferCompl)
51864  *
51865  * Transfer completed normally without any errors.This bit can be set only by the
51866  * core and the application should write 1 to clear it.
51867  *
51868  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
51869  *
51870  * completed with IOC bit set in its descriptor.
51871  *
51872  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
51873  * without
51874  *
51875  * any errors.
51876  *
51877  * Field Enumeration Values:
51878  *
51879  * Enum | Value | Description
51880  * :---------------------------------------|:------|:-----------------------------------------------
51881  * ALT_USB_HOST_HCINT12_XFERCOMPL_E_INACT | 0x0 | No transfer
51882  * ALT_USB_HOST_HCINT12_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
51883  *
51884  * Field Access Macros:
51885  *
51886  */
51887 /*
51888  * Enumerated value for register field ALT_USB_HOST_HCINT12_XFERCOMPL
51889  *
51890  * No transfer
51891  */
51892 #define ALT_USB_HOST_HCINT12_XFERCOMPL_E_INACT 0x0
51893 /*
51894  * Enumerated value for register field ALT_USB_HOST_HCINT12_XFERCOMPL
51895  *
51896  * Transfer completed normally without any errors
51897  */
51898 #define ALT_USB_HOST_HCINT12_XFERCOMPL_E_ACT 0x1
51899 
51900 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */
51901 #define ALT_USB_HOST_HCINT12_XFERCOMPL_LSB 0
51902 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */
51903 #define ALT_USB_HOST_HCINT12_XFERCOMPL_MSB 0
51904 /* The width in bits of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */
51905 #define ALT_USB_HOST_HCINT12_XFERCOMPL_WIDTH 1
51906 /* The mask used to set the ALT_USB_HOST_HCINT12_XFERCOMPL register field value. */
51907 #define ALT_USB_HOST_HCINT12_XFERCOMPL_SET_MSK 0x00000001
51908 /* The mask used to clear the ALT_USB_HOST_HCINT12_XFERCOMPL register field value. */
51909 #define ALT_USB_HOST_HCINT12_XFERCOMPL_CLR_MSK 0xfffffffe
51910 /* The reset value of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */
51911 #define ALT_USB_HOST_HCINT12_XFERCOMPL_RESET 0x0
51912 /* Extracts the ALT_USB_HOST_HCINT12_XFERCOMPL field value from a register. */
51913 #define ALT_USB_HOST_HCINT12_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
51914 /* Produces a ALT_USB_HOST_HCINT12_XFERCOMPL register field value suitable for setting the register. */
51915 #define ALT_USB_HOST_HCINT12_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
51916 
51917 /*
51918  * Field : chhltd
51919  *
51920  * Channel Halted (ChHltd)
51921  *
51922  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
51923  * either because of any USB transaction error or in response to disable request by
51924  * the application or because of a completed transfer.
51925  *
51926  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
51927  * the following
51928  *
51929  * . EOL being set in descriptor
51930  *
51931  * . AHB error
51932  *
51933  * . Excessive transaction errors
51934  *
51935  * . Babble
51936  *
51937  * . Stall
51938  *
51939  * Field Enumeration Values:
51940  *
51941  * Enum | Value | Description
51942  * :------------------------------------|:------|:-------------------
51943  * ALT_USB_HOST_HCINT12_CHHLTD_E_INACT | 0x0 | Channel not halted
51944  * ALT_USB_HOST_HCINT12_CHHLTD_E_ACT | 0x1 | Channel Halted
51945  *
51946  * Field Access Macros:
51947  *
51948  */
51949 /*
51950  * Enumerated value for register field ALT_USB_HOST_HCINT12_CHHLTD
51951  *
51952  * Channel not halted
51953  */
51954 #define ALT_USB_HOST_HCINT12_CHHLTD_E_INACT 0x0
51955 /*
51956  * Enumerated value for register field ALT_USB_HOST_HCINT12_CHHLTD
51957  *
51958  * Channel Halted
51959  */
51960 #define ALT_USB_HOST_HCINT12_CHHLTD_E_ACT 0x1
51961 
51962 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_CHHLTD register field. */
51963 #define ALT_USB_HOST_HCINT12_CHHLTD_LSB 1
51964 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_CHHLTD register field. */
51965 #define ALT_USB_HOST_HCINT12_CHHLTD_MSB 1
51966 /* The width in bits of the ALT_USB_HOST_HCINT12_CHHLTD register field. */
51967 #define ALT_USB_HOST_HCINT12_CHHLTD_WIDTH 1
51968 /* The mask used to set the ALT_USB_HOST_HCINT12_CHHLTD register field value. */
51969 #define ALT_USB_HOST_HCINT12_CHHLTD_SET_MSK 0x00000002
51970 /* The mask used to clear the ALT_USB_HOST_HCINT12_CHHLTD register field value. */
51971 #define ALT_USB_HOST_HCINT12_CHHLTD_CLR_MSK 0xfffffffd
51972 /* The reset value of the ALT_USB_HOST_HCINT12_CHHLTD register field. */
51973 #define ALT_USB_HOST_HCINT12_CHHLTD_RESET 0x0
51974 /* Extracts the ALT_USB_HOST_HCINT12_CHHLTD field value from a register. */
51975 #define ALT_USB_HOST_HCINT12_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
51976 /* Produces a ALT_USB_HOST_HCINT12_CHHLTD register field value suitable for setting the register. */
51977 #define ALT_USB_HOST_HCINT12_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
51978 
51979 /*
51980  * Field : ahberr
51981  *
51982  * AHB Error (AHBErr)
51983  *
51984  * This is generated only in Internal DMA mode when there is an
51985  *
51986  * AHB error during AHB read/write. The application can read the
51987  *
51988  * corresponding channel's DMA address register to get the error
51989  *
51990  * address.
51991  *
51992  * Field Enumeration Values:
51993  *
51994  * Enum | Value | Description
51995  * :------------------------------------|:------|:--------------------------------
51996  * ALT_USB_HOST_HCINT12_AHBERR_E_INACT | 0x0 | No AHB error
51997  * ALT_USB_HOST_HCINT12_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
51998  *
51999  * Field Access Macros:
52000  *
52001  */
52002 /*
52003  * Enumerated value for register field ALT_USB_HOST_HCINT12_AHBERR
52004  *
52005  * No AHB error
52006  */
52007 #define ALT_USB_HOST_HCINT12_AHBERR_E_INACT 0x0
52008 /*
52009  * Enumerated value for register field ALT_USB_HOST_HCINT12_AHBERR
52010  *
52011  * AHB error during AHB read/write
52012  */
52013 #define ALT_USB_HOST_HCINT12_AHBERR_E_ACT 0x1
52014 
52015 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_AHBERR register field. */
52016 #define ALT_USB_HOST_HCINT12_AHBERR_LSB 2
52017 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_AHBERR register field. */
52018 #define ALT_USB_HOST_HCINT12_AHBERR_MSB 2
52019 /* The width in bits of the ALT_USB_HOST_HCINT12_AHBERR register field. */
52020 #define ALT_USB_HOST_HCINT12_AHBERR_WIDTH 1
52021 /* The mask used to set the ALT_USB_HOST_HCINT12_AHBERR register field value. */
52022 #define ALT_USB_HOST_HCINT12_AHBERR_SET_MSK 0x00000004
52023 /* The mask used to clear the ALT_USB_HOST_HCINT12_AHBERR register field value. */
52024 #define ALT_USB_HOST_HCINT12_AHBERR_CLR_MSK 0xfffffffb
52025 /* The reset value of the ALT_USB_HOST_HCINT12_AHBERR register field. */
52026 #define ALT_USB_HOST_HCINT12_AHBERR_RESET 0x0
52027 /* Extracts the ALT_USB_HOST_HCINT12_AHBERR field value from a register. */
52028 #define ALT_USB_HOST_HCINT12_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
52029 /* Produces a ALT_USB_HOST_HCINT12_AHBERR register field value suitable for setting the register. */
52030 #define ALT_USB_HOST_HCINT12_AHBERR_SET(value) (((value) << 2) & 0x00000004)
52031 
52032 /*
52033  * Field : stall
52034  *
52035  * STALL Response Received Interrupt (STALL)
52036  *
52037  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
52038  *
52039  * in the core.This bit can be set only by the core and the application should
52040  * write 1 to clear
52041  *
52042  * it.
52043  *
52044  * Field Enumeration Values:
52045  *
52046  * Enum | Value | Description
52047  * :-----------------------------------|:------|:-------------------
52048  * ALT_USB_HOST_HCINT12_STALL_E_INACT | 0x0 | No Stall Interrupt
52049  * ALT_USB_HOST_HCINT12_STALL_E_ACT | 0x1 | Stall Interrupt
52050  *
52051  * Field Access Macros:
52052  *
52053  */
52054 /*
52055  * Enumerated value for register field ALT_USB_HOST_HCINT12_STALL
52056  *
52057  * No Stall Interrupt
52058  */
52059 #define ALT_USB_HOST_HCINT12_STALL_E_INACT 0x0
52060 /*
52061  * Enumerated value for register field ALT_USB_HOST_HCINT12_STALL
52062  *
52063  * Stall Interrupt
52064  */
52065 #define ALT_USB_HOST_HCINT12_STALL_E_ACT 0x1
52066 
52067 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_STALL register field. */
52068 #define ALT_USB_HOST_HCINT12_STALL_LSB 3
52069 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_STALL register field. */
52070 #define ALT_USB_HOST_HCINT12_STALL_MSB 3
52071 /* The width in bits of the ALT_USB_HOST_HCINT12_STALL register field. */
52072 #define ALT_USB_HOST_HCINT12_STALL_WIDTH 1
52073 /* The mask used to set the ALT_USB_HOST_HCINT12_STALL register field value. */
52074 #define ALT_USB_HOST_HCINT12_STALL_SET_MSK 0x00000008
52075 /* The mask used to clear the ALT_USB_HOST_HCINT12_STALL register field value. */
52076 #define ALT_USB_HOST_HCINT12_STALL_CLR_MSK 0xfffffff7
52077 /* The reset value of the ALT_USB_HOST_HCINT12_STALL register field. */
52078 #define ALT_USB_HOST_HCINT12_STALL_RESET 0x0
52079 /* Extracts the ALT_USB_HOST_HCINT12_STALL field value from a register. */
52080 #define ALT_USB_HOST_HCINT12_STALL_GET(value) (((value) & 0x00000008) >> 3)
52081 /* Produces a ALT_USB_HOST_HCINT12_STALL register field value suitable for setting the register. */
52082 #define ALT_USB_HOST_HCINT12_STALL_SET(value) (((value) << 3) & 0x00000008)
52083 
52084 /*
52085  * Field : nak
52086  *
52087  * NAK Response Received Interrupt (NAK)
52088  *
52089  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
52090  *
52091  * in the core.This bit can be set only by the core and the application should
52092  * write 1 to clear
52093  *
52094  * it.
52095  *
52096  * Field Enumeration Values:
52097  *
52098  * Enum | Value | Description
52099  * :---------------------------------|:------|:-----------------------------------
52100  * ALT_USB_HOST_HCINT12_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
52101  * ALT_USB_HOST_HCINT12_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
52102  *
52103  * Field Access Macros:
52104  *
52105  */
52106 /*
52107  * Enumerated value for register field ALT_USB_HOST_HCINT12_NAK
52108  *
52109  * No NAK Response Received Interrupt
52110  */
52111 #define ALT_USB_HOST_HCINT12_NAK_E_INACT 0x0
52112 /*
52113  * Enumerated value for register field ALT_USB_HOST_HCINT12_NAK
52114  *
52115  * NAK Response Received Interrupt
52116  */
52117 #define ALT_USB_HOST_HCINT12_NAK_E_ACT 0x1
52118 
52119 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_NAK register field. */
52120 #define ALT_USB_HOST_HCINT12_NAK_LSB 4
52121 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_NAK register field. */
52122 #define ALT_USB_HOST_HCINT12_NAK_MSB 4
52123 /* The width in bits of the ALT_USB_HOST_HCINT12_NAK register field. */
52124 #define ALT_USB_HOST_HCINT12_NAK_WIDTH 1
52125 /* The mask used to set the ALT_USB_HOST_HCINT12_NAK register field value. */
52126 #define ALT_USB_HOST_HCINT12_NAK_SET_MSK 0x00000010
52127 /* The mask used to clear the ALT_USB_HOST_HCINT12_NAK register field value. */
52128 #define ALT_USB_HOST_HCINT12_NAK_CLR_MSK 0xffffffef
52129 /* The reset value of the ALT_USB_HOST_HCINT12_NAK register field. */
52130 #define ALT_USB_HOST_HCINT12_NAK_RESET 0x0
52131 /* Extracts the ALT_USB_HOST_HCINT12_NAK field value from a register. */
52132 #define ALT_USB_HOST_HCINT12_NAK_GET(value) (((value) & 0x00000010) >> 4)
52133 /* Produces a ALT_USB_HOST_HCINT12_NAK register field value suitable for setting the register. */
52134 #define ALT_USB_HOST_HCINT12_NAK_SET(value) (((value) << 4) & 0x00000010)
52135 
52136 /*
52137  * Field : ack
52138  *
52139  * ACK Response Received/Transmitted Interrupt (ACK)
52140  *
52141  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
52142  *
52143  * in the core.This bit can be set only by the core and the application should
52144  * write 1 to clear
52145  *
52146  * it.
52147  *
52148  * Field Enumeration Values:
52149  *
52150  * Enum | Value | Description
52151  * :---------------------------------|:------|:-----------------------------------------------
52152  * ALT_USB_HOST_HCINT12_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
52153  * ALT_USB_HOST_HCINT12_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
52154  *
52155  * Field Access Macros:
52156  *
52157  */
52158 /*
52159  * Enumerated value for register field ALT_USB_HOST_HCINT12_ACK
52160  *
52161  * No ACK Response Received Transmitted Interrupt
52162  */
52163 #define ALT_USB_HOST_HCINT12_ACK_E_INACT 0x0
52164 /*
52165  * Enumerated value for register field ALT_USB_HOST_HCINT12_ACK
52166  *
52167  * ACK Response Received Transmitted Interrup
52168  */
52169 #define ALT_USB_HOST_HCINT12_ACK_E_ACT 0x1
52170 
52171 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_ACK register field. */
52172 #define ALT_USB_HOST_HCINT12_ACK_LSB 5
52173 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_ACK register field. */
52174 #define ALT_USB_HOST_HCINT12_ACK_MSB 5
52175 /* The width in bits of the ALT_USB_HOST_HCINT12_ACK register field. */
52176 #define ALT_USB_HOST_HCINT12_ACK_WIDTH 1
52177 /* The mask used to set the ALT_USB_HOST_HCINT12_ACK register field value. */
52178 #define ALT_USB_HOST_HCINT12_ACK_SET_MSK 0x00000020
52179 /* The mask used to clear the ALT_USB_HOST_HCINT12_ACK register field value. */
52180 #define ALT_USB_HOST_HCINT12_ACK_CLR_MSK 0xffffffdf
52181 /* The reset value of the ALT_USB_HOST_HCINT12_ACK register field. */
52182 #define ALT_USB_HOST_HCINT12_ACK_RESET 0x0
52183 /* Extracts the ALT_USB_HOST_HCINT12_ACK field value from a register. */
52184 #define ALT_USB_HOST_HCINT12_ACK_GET(value) (((value) & 0x00000020) >> 5)
52185 /* Produces a ALT_USB_HOST_HCINT12_ACK register field value suitable for setting the register. */
52186 #define ALT_USB_HOST_HCINT12_ACK_SET(value) (((value) << 5) & 0x00000020)
52187 
52188 /*
52189  * Field : nyet
52190  *
52191  * NYET Response Received Interrupt (NYET)
52192  *
52193  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
52194  *
52195  * in the core.This bit can be set only by the core and the application should
52196  * write 1 to clear
52197  *
52198  * it.
52199  *
52200  * Field Enumeration Values:
52201  *
52202  * Enum | Value | Description
52203  * :----------------------------------|:------|:------------------------------------
52204  * ALT_USB_HOST_HCINT12_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
52205  * ALT_USB_HOST_HCINT12_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
52206  *
52207  * Field Access Macros:
52208  *
52209  */
52210 /*
52211  * Enumerated value for register field ALT_USB_HOST_HCINT12_NYET
52212  *
52213  * No NYET Response Received Interrupt
52214  */
52215 #define ALT_USB_HOST_HCINT12_NYET_E_INACT 0x0
52216 /*
52217  * Enumerated value for register field ALT_USB_HOST_HCINT12_NYET
52218  *
52219  * NYET Response Received Interrupt
52220  */
52221 #define ALT_USB_HOST_HCINT12_NYET_E_ACT 0x1
52222 
52223 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_NYET register field. */
52224 #define ALT_USB_HOST_HCINT12_NYET_LSB 6
52225 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_NYET register field. */
52226 #define ALT_USB_HOST_HCINT12_NYET_MSB 6
52227 /* The width in bits of the ALT_USB_HOST_HCINT12_NYET register field. */
52228 #define ALT_USB_HOST_HCINT12_NYET_WIDTH 1
52229 /* The mask used to set the ALT_USB_HOST_HCINT12_NYET register field value. */
52230 #define ALT_USB_HOST_HCINT12_NYET_SET_MSK 0x00000040
52231 /* The mask used to clear the ALT_USB_HOST_HCINT12_NYET register field value. */
52232 #define ALT_USB_HOST_HCINT12_NYET_CLR_MSK 0xffffffbf
52233 /* The reset value of the ALT_USB_HOST_HCINT12_NYET register field. */
52234 #define ALT_USB_HOST_HCINT12_NYET_RESET 0x0
52235 /* Extracts the ALT_USB_HOST_HCINT12_NYET field value from a register. */
52236 #define ALT_USB_HOST_HCINT12_NYET_GET(value) (((value) & 0x00000040) >> 6)
52237 /* Produces a ALT_USB_HOST_HCINT12_NYET register field value suitable for setting the register. */
52238 #define ALT_USB_HOST_HCINT12_NYET_SET(value) (((value) << 6) & 0x00000040)
52239 
52240 /*
52241  * Field : xacterr
52242  *
52243  * Transaction Error (XactErr)
52244  *
52245  * Indicates one of the following errors occurred on the USB.
52246  *
52247  * CRC check failure
52248  *
52249  * Timeout
52250  *
52251  * Bit stuff error
52252  *
52253  * False EOP
52254  *
52255  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
52256  *
52257  * in the core.This bit can be set only by the core and the application should
52258  * write 1 to clear
52259  *
52260  * it.
52261  *
52262  * Field Enumeration Values:
52263  *
52264  * Enum | Value | Description
52265  * :-------------------------------------|:------|:---------------------
52266  * ALT_USB_HOST_HCINT12_XACTERR_E_INACT | 0x0 | No Transaction Error
52267  * ALT_USB_HOST_HCINT12_XACTERR_E_ACT | 0x1 | Transaction Error
52268  *
52269  * Field Access Macros:
52270  *
52271  */
52272 /*
52273  * Enumerated value for register field ALT_USB_HOST_HCINT12_XACTERR
52274  *
52275  * No Transaction Error
52276  */
52277 #define ALT_USB_HOST_HCINT12_XACTERR_E_INACT 0x0
52278 /*
52279  * Enumerated value for register field ALT_USB_HOST_HCINT12_XACTERR
52280  *
52281  * Transaction Error
52282  */
52283 #define ALT_USB_HOST_HCINT12_XACTERR_E_ACT 0x1
52284 
52285 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_XACTERR register field. */
52286 #define ALT_USB_HOST_HCINT12_XACTERR_LSB 7
52287 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_XACTERR register field. */
52288 #define ALT_USB_HOST_HCINT12_XACTERR_MSB 7
52289 /* The width in bits of the ALT_USB_HOST_HCINT12_XACTERR register field. */
52290 #define ALT_USB_HOST_HCINT12_XACTERR_WIDTH 1
52291 /* The mask used to set the ALT_USB_HOST_HCINT12_XACTERR register field value. */
52292 #define ALT_USB_HOST_HCINT12_XACTERR_SET_MSK 0x00000080
52293 /* The mask used to clear the ALT_USB_HOST_HCINT12_XACTERR register field value. */
52294 #define ALT_USB_HOST_HCINT12_XACTERR_CLR_MSK 0xffffff7f
52295 /* The reset value of the ALT_USB_HOST_HCINT12_XACTERR register field. */
52296 #define ALT_USB_HOST_HCINT12_XACTERR_RESET 0x0
52297 /* Extracts the ALT_USB_HOST_HCINT12_XACTERR field value from a register. */
52298 #define ALT_USB_HOST_HCINT12_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
52299 /* Produces a ALT_USB_HOST_HCINT12_XACTERR register field value suitable for setting the register. */
52300 #define ALT_USB_HOST_HCINT12_XACTERR_SET(value) (((value) << 7) & 0x00000080)
52301 
52302 /*
52303  * Field : bblerr
52304  *
52305  * Babble Error (BblErr)
52306  *
52307  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
52308  *
52309  * in the core..This bit can be set only by the core and the application should
52310  * write 1 to clear
52311  *
52312  * it.
52313  *
52314  * Field Enumeration Values:
52315  *
52316  * Enum | Value | Description
52317  * :------------------------------------|:------|:----------------
52318  * ALT_USB_HOST_HCINT12_BBLERR_E_INACT | 0x0 | No Babble Error
52319  * ALT_USB_HOST_HCINT12_BBLERR_E_ACT | 0x1 | Babble Error
52320  *
52321  * Field Access Macros:
52322  *
52323  */
52324 /*
52325  * Enumerated value for register field ALT_USB_HOST_HCINT12_BBLERR
52326  *
52327  * No Babble Error
52328  */
52329 #define ALT_USB_HOST_HCINT12_BBLERR_E_INACT 0x0
52330 /*
52331  * Enumerated value for register field ALT_USB_HOST_HCINT12_BBLERR
52332  *
52333  * Babble Error
52334  */
52335 #define ALT_USB_HOST_HCINT12_BBLERR_E_ACT 0x1
52336 
52337 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_BBLERR register field. */
52338 #define ALT_USB_HOST_HCINT12_BBLERR_LSB 8
52339 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_BBLERR register field. */
52340 #define ALT_USB_HOST_HCINT12_BBLERR_MSB 8
52341 /* The width in bits of the ALT_USB_HOST_HCINT12_BBLERR register field. */
52342 #define ALT_USB_HOST_HCINT12_BBLERR_WIDTH 1
52343 /* The mask used to set the ALT_USB_HOST_HCINT12_BBLERR register field value. */
52344 #define ALT_USB_HOST_HCINT12_BBLERR_SET_MSK 0x00000100
52345 /* The mask used to clear the ALT_USB_HOST_HCINT12_BBLERR register field value. */
52346 #define ALT_USB_HOST_HCINT12_BBLERR_CLR_MSK 0xfffffeff
52347 /* The reset value of the ALT_USB_HOST_HCINT12_BBLERR register field. */
52348 #define ALT_USB_HOST_HCINT12_BBLERR_RESET 0x0
52349 /* Extracts the ALT_USB_HOST_HCINT12_BBLERR field value from a register. */
52350 #define ALT_USB_HOST_HCINT12_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
52351 /* Produces a ALT_USB_HOST_HCINT12_BBLERR register field value suitable for setting the register. */
52352 #define ALT_USB_HOST_HCINT12_BBLERR_SET(value) (((value) << 8) & 0x00000100)
52353 
52354 /*
52355  * Field : frmovrun
52356  *
52357  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
52358  * bit is masked
52359  *
52360  * in the core.This bit can be set only by the core and the application should
52361  * write 1 to clear
52362  *
52363  * it.
52364  *
52365  * Field Enumeration Values:
52366  *
52367  * Enum | Value | Description
52368  * :--------------------------------------|:------|:-----------------
52369  * ALT_USB_HOST_HCINT12_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
52370  * ALT_USB_HOST_HCINT12_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
52371  *
52372  * Field Access Macros:
52373  *
52374  */
52375 /*
52376  * Enumerated value for register field ALT_USB_HOST_HCINT12_FRMOVRUN
52377  *
52378  * No Frame Overrun
52379  */
52380 #define ALT_USB_HOST_HCINT12_FRMOVRUN_E_INACT 0x0
52381 /*
52382  * Enumerated value for register field ALT_USB_HOST_HCINT12_FRMOVRUN
52383  *
52384  * Frame Overrun
52385  */
52386 #define ALT_USB_HOST_HCINT12_FRMOVRUN_E_ACT 0x1
52387 
52388 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */
52389 #define ALT_USB_HOST_HCINT12_FRMOVRUN_LSB 9
52390 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */
52391 #define ALT_USB_HOST_HCINT12_FRMOVRUN_MSB 9
52392 /* The width in bits of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */
52393 #define ALT_USB_HOST_HCINT12_FRMOVRUN_WIDTH 1
52394 /* The mask used to set the ALT_USB_HOST_HCINT12_FRMOVRUN register field value. */
52395 #define ALT_USB_HOST_HCINT12_FRMOVRUN_SET_MSK 0x00000200
52396 /* The mask used to clear the ALT_USB_HOST_HCINT12_FRMOVRUN register field value. */
52397 #define ALT_USB_HOST_HCINT12_FRMOVRUN_CLR_MSK 0xfffffdff
52398 /* The reset value of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */
52399 #define ALT_USB_HOST_HCINT12_FRMOVRUN_RESET 0x0
52400 /* Extracts the ALT_USB_HOST_HCINT12_FRMOVRUN field value from a register. */
52401 #define ALT_USB_HOST_HCINT12_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
52402 /* Produces a ALT_USB_HOST_HCINT12_FRMOVRUN register field value suitable for setting the register. */
52403 #define ALT_USB_HOST_HCINT12_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
52404 
52405 /*
52406  * Field : datatglerr
52407  *
52408  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
52409  * application should write 1 to clear
52410  *
52411  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
52412  *
52413  * in the core.
52414  *
52415  * Field Enumeration Values:
52416  *
52417  * Enum | Value | Description
52418  * :----------------------------------------|:------|:---------------------
52419  * ALT_USB_HOST_HCINT12_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
52420  * ALT_USB_HOST_HCINT12_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
52421  *
52422  * Field Access Macros:
52423  *
52424  */
52425 /*
52426  * Enumerated value for register field ALT_USB_HOST_HCINT12_DATATGLERR
52427  *
52428  * No Data Toggle Error
52429  */
52430 #define ALT_USB_HOST_HCINT12_DATATGLERR_E_INACT 0x0
52431 /*
52432  * Enumerated value for register field ALT_USB_HOST_HCINT12_DATATGLERR
52433  *
52434  * Data Toggle Error
52435  */
52436 #define ALT_USB_HOST_HCINT12_DATATGLERR_E_ACT 0x1
52437 
52438 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */
52439 #define ALT_USB_HOST_HCINT12_DATATGLERR_LSB 10
52440 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */
52441 #define ALT_USB_HOST_HCINT12_DATATGLERR_MSB 10
52442 /* The width in bits of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */
52443 #define ALT_USB_HOST_HCINT12_DATATGLERR_WIDTH 1
52444 /* The mask used to set the ALT_USB_HOST_HCINT12_DATATGLERR register field value. */
52445 #define ALT_USB_HOST_HCINT12_DATATGLERR_SET_MSK 0x00000400
52446 /* The mask used to clear the ALT_USB_HOST_HCINT12_DATATGLERR register field value. */
52447 #define ALT_USB_HOST_HCINT12_DATATGLERR_CLR_MSK 0xfffffbff
52448 /* The reset value of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */
52449 #define ALT_USB_HOST_HCINT12_DATATGLERR_RESET 0x0
52450 /* Extracts the ALT_USB_HOST_HCINT12_DATATGLERR field value from a register. */
52451 #define ALT_USB_HOST_HCINT12_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
52452 /* Produces a ALT_USB_HOST_HCINT12_DATATGLERR register field value suitable for setting the register. */
52453 #define ALT_USB_HOST_HCINT12_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
52454 
52455 /*
52456  * Field : bnaintr
52457  *
52458  * BNA (Buffer Not Available) Interrupt (BNAIntr)
52459  *
52460  * This bit is valid only when Scatter/Gather DMA mode is enabled.
52461  *
52462  * The core generates this interrupt when the descriptor accessed
52463  *
52464  * is not ready for the Core to process. BNA will not be generated
52465  *
52466  * for Isochronous channels.
52467  *
52468  * For non Scatter/Gather DMA mode, this bit is reserved.
52469  *
52470  * Field Enumeration Values:
52471  *
52472  * Enum | Value | Description
52473  * :-------------------------------------|:------|:-----------------
52474  * ALT_USB_HOST_HCINT12_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
52475  * ALT_USB_HOST_HCINT12_BNAINTR_E_ACT | 0x1 | BNA Interrupt
52476  *
52477  * Field Access Macros:
52478  *
52479  */
52480 /*
52481  * Enumerated value for register field ALT_USB_HOST_HCINT12_BNAINTR
52482  *
52483  * No BNA Interrupt
52484  */
52485 #define ALT_USB_HOST_HCINT12_BNAINTR_E_INACT 0x0
52486 /*
52487  * Enumerated value for register field ALT_USB_HOST_HCINT12_BNAINTR
52488  *
52489  * BNA Interrupt
52490  */
52491 #define ALT_USB_HOST_HCINT12_BNAINTR_E_ACT 0x1
52492 
52493 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_BNAINTR register field. */
52494 #define ALT_USB_HOST_HCINT12_BNAINTR_LSB 11
52495 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_BNAINTR register field. */
52496 #define ALT_USB_HOST_HCINT12_BNAINTR_MSB 11
52497 /* The width in bits of the ALT_USB_HOST_HCINT12_BNAINTR register field. */
52498 #define ALT_USB_HOST_HCINT12_BNAINTR_WIDTH 1
52499 /* The mask used to set the ALT_USB_HOST_HCINT12_BNAINTR register field value. */
52500 #define ALT_USB_HOST_HCINT12_BNAINTR_SET_MSK 0x00000800
52501 /* The mask used to clear the ALT_USB_HOST_HCINT12_BNAINTR register field value. */
52502 #define ALT_USB_HOST_HCINT12_BNAINTR_CLR_MSK 0xfffff7ff
52503 /* The reset value of the ALT_USB_HOST_HCINT12_BNAINTR register field. */
52504 #define ALT_USB_HOST_HCINT12_BNAINTR_RESET 0x0
52505 /* Extracts the ALT_USB_HOST_HCINT12_BNAINTR field value from a register. */
52506 #define ALT_USB_HOST_HCINT12_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
52507 /* Produces a ALT_USB_HOST_HCINT12_BNAINTR register field value suitable for setting the register. */
52508 #define ALT_USB_HOST_HCINT12_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
52509 
52510 /*
52511  * Field : xcs_xact_err
52512  *
52513  * Excessive Transaction Error (XCS_XACT_ERR)
52514  *
52515  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
52516  * this bit
52517  *
52518  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
52519  *
52520  * not be generated for Isochronous channels.
52521  *
52522  * For non Scatter/Gather DMA mode, this bit is reserved.
52523  *
52524  * Field Enumeration Values:
52525  *
52526  * Enum | Value | Description
52527  * :--------------------------------------------|:------|:-------------------------------
52528  * ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
52529  * ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
52530  *
52531  * Field Access Macros:
52532  *
52533  */
52534 /*
52535  * Enumerated value for register field ALT_USB_HOST_HCINT12_XCS_XACT_ERR
52536  *
52537  * No Excessive Transaction Error
52538  */
52539 #define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_INACT 0x0
52540 /*
52541  * Enumerated value for register field ALT_USB_HOST_HCINT12_XCS_XACT_ERR
52542  *
52543  * Excessive Transaction Error
52544  */
52545 #define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_ACVTIVE 0x1
52546 
52547 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */
52548 #define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_LSB 12
52549 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */
52550 #define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_MSB 12
52551 /* The width in bits of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */
52552 #define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_WIDTH 1
52553 /* The mask used to set the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field value. */
52554 #define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_SET_MSK 0x00001000
52555 /* The mask used to clear the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field value. */
52556 #define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_CLR_MSK 0xffffefff
52557 /* The reset value of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */
52558 #define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_RESET 0x0
52559 /* Extracts the ALT_USB_HOST_HCINT12_XCS_XACT_ERR field value from a register. */
52560 #define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
52561 /* Produces a ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field value suitable for setting the register. */
52562 #define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
52563 
52564 /*
52565  * Field : desc_lst_rollintr
52566  *
52567  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
52568  *
52569  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
52570  * this bit
52571  *
52572  * when the corresponding channel's descriptor list rolls over.
52573  *
52574  * For non Scatter/Gather DMA mode, this bit is reserved.
52575  *
52576  * Field Enumeration Values:
52577  *
52578  * Enum | Value | Description
52579  * :-----------------------------------------------|:------|:---------------------------------
52580  * ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
52581  * ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
52582  *
52583  * Field Access Macros:
52584  *
52585  */
52586 /*
52587  * Enumerated value for register field ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR
52588  *
52589  * No Descriptor rollover interrupt
52590  */
52591 #define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_INACT 0x0
52592 /*
52593  * Enumerated value for register field ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR
52594  *
52595  * Descriptor rollover interrupt
52596  */
52597 #define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_ACT 0x1
52598 
52599 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */
52600 #define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_LSB 13
52601 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */
52602 #define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_MSB 13
52603 /* The width in bits of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */
52604 #define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_WIDTH 1
52605 /* The mask used to set the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field value. */
52606 #define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_SET_MSK 0x00002000
52607 /* The mask used to clear the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field value. */
52608 #define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
52609 /* The reset value of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */
52610 #define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_RESET 0x0
52611 /* Extracts the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR field value from a register. */
52612 #define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
52613 /* Produces a ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field value suitable for setting the register. */
52614 #define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
52615 
52616 #ifndef __ASSEMBLY__
52617 /*
52618  * WARNING: The C register and register group struct declarations are provided for
52619  * convenience and illustrative purposes. They should, however, be used with
52620  * caution as the C language standard provides no guarantees about the alignment or
52621  * atomicity of device memory accesses. The recommended practice for writing
52622  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
52623  * alt_write_word() functions.
52624  *
52625  * The struct declaration for register ALT_USB_HOST_HCINT12.
52626  */
52627 struct ALT_USB_HOST_HCINT12_s
52628 {
52629  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT12_XFERCOMPL */
52630  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT12_CHHLTD */
52631  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT12_AHBERR */
52632  uint32_t stall : 1; /* ALT_USB_HOST_HCINT12_STALL */
52633  uint32_t nak : 1; /* ALT_USB_HOST_HCINT12_NAK */
52634  uint32_t ack : 1; /* ALT_USB_HOST_HCINT12_ACK */
52635  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT12_NYET */
52636  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT12_XACTERR */
52637  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT12_BBLERR */
52638  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT12_FRMOVRUN */
52639  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT12_DATATGLERR */
52640  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT12_BNAINTR */
52641  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT12_XCS_XACT_ERR */
52642  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR */
52643  uint32_t : 18; /* *UNDEFINED* */
52644 };
52645 
52646 /* The typedef declaration for register ALT_USB_HOST_HCINT12. */
52647 typedef volatile struct ALT_USB_HOST_HCINT12_s ALT_USB_HOST_HCINT12_t;
52648 #endif /* __ASSEMBLY__ */
52649 
52650 /* The reset value of the ALT_USB_HOST_HCINT12 register. */
52651 #define ALT_USB_HOST_HCINT12_RESET 0x00000000
52652 /* The byte offset of the ALT_USB_HOST_HCINT12 register from the beginning of the component. */
52653 #define ALT_USB_HOST_HCINT12_OFST 0x288
52654 /* The address of the ALT_USB_HOST_HCINT12 register. */
52655 #define ALT_USB_HOST_HCINT12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT12_OFST))
52656 
52657 /*
52658  * Register : hcintmsk12
52659  *
52660  * Host Channel 12 Interrupt Mask Register
52661  *
52662  * Register Layout
52663  *
52664  * Bits | Access | Reset | Description
52665  * :--------|:-------|:------|:--------------------------------------------
52666  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK
52667  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_CHHLTDMSK
52668  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_AHBERRMSK
52669  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_STALLMSK
52670  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_NAKMSK
52671  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_ACKMSK
52672  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_NYETMSK
52673  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_XACTERRMSK
52674  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_BBLERRMSK
52675  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK
52676  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK
52677  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_BNAINTRMSK
52678  * [12] | ??? | 0x0 | *UNDEFINED*
52679  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK
52680  * [31:14] | ??? | 0x0 | *UNDEFINED*
52681  *
52682  */
52683 /*
52684  * Field : xfercomplmsk
52685  *
52686  * Transfer Completed Mask (XferComplMsk)
52687  *
52688  * Field Enumeration Values:
52689  *
52690  * Enum | Value | Description
52691  * :---------------------------------------------|:------|:------------
52692  * ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_MSK | 0x0 | Mask
52693  * ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
52694  *
52695  * Field Access Macros:
52696  *
52697  */
52698 /*
52699  * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK
52700  *
52701  * Mask
52702  */
52703 #define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_MSK 0x0
52704 /*
52705  * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK
52706  *
52707  * No mask
52708  */
52709 #define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_NOMSK 0x1
52710 
52711 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */
52712 #define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_LSB 0
52713 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */
52714 #define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_MSB 0
52715 /* The width in bits of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */
52716 #define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_WIDTH 1
52717 /* The mask used to set the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field value. */
52718 #define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_SET_MSK 0x00000001
52719 /* The mask used to clear the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field value. */
52720 #define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_CLR_MSK 0xfffffffe
52721 /* The reset value of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */
52722 #define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_RESET 0x0
52723 /* Extracts the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK field value from a register. */
52724 #define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
52725 /* Produces a ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field value suitable for setting the register. */
52726 #define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
52727 
52728 /*
52729  * Field : chhltdmsk
52730  *
52731  * Channel Halted Mask (ChHltdMsk)
52732  *
52733  * Field Enumeration Values:
52734  *
52735  * Enum | Value | Description
52736  * :------------------------------------------|:------|:------------
52737  * ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_MSK | 0x0 | Mask
52738  * ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_NOMSK | 0x1 | No mask
52739  *
52740  * Field Access Macros:
52741  *
52742  */
52743 /*
52744  * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_CHHLTDMSK
52745  *
52746  * Mask
52747  */
52748 #define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_MSK 0x0
52749 /*
52750  * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_CHHLTDMSK
52751  *
52752  * No mask
52753  */
52754 #define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_NOMSK 0x1
52755 
52756 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */
52757 #define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_LSB 1
52758 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */
52759 #define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_MSB 1
52760 /* The width in bits of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */
52761 #define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_WIDTH 1
52762 /* The mask used to set the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field value. */
52763 #define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_SET_MSK 0x00000002
52764 /* The mask used to clear the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field value. */
52765 #define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_CLR_MSK 0xfffffffd
52766 /* The reset value of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */
52767 #define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_RESET 0x0
52768 /* Extracts the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK field value from a register. */
52769 #define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
52770 /* Produces a ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field value suitable for setting the register. */
52771 #define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
52772 
52773 /*
52774  * Field : ahberrmsk
52775  *
52776  * AHB Error Mask (AHBErrMsk)
52777  *
52778  * In scatter/gather DMA mode for host,
52779  *
52780  * interrupts will not be generated due to the corresponding bits set in
52781  *
52782  * HCINTn.
52783  *
52784  * Field Enumeration Values:
52785  *
52786  * Enum | Value | Description
52787  * :------------------------------------------|:------|:------------
52788  * ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_MSK | 0x0 | Mask
52789  * ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_NOMSK | 0x1 | No mask
52790  *
52791  * Field Access Macros:
52792  *
52793  */
52794 /*
52795  * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_AHBERRMSK
52796  *
52797  * Mask
52798  */
52799 #define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_MSK 0x0
52800 /*
52801  * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_AHBERRMSK
52802  *
52803  * No mask
52804  */
52805 #define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_NOMSK 0x1
52806 
52807 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */
52808 #define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_LSB 2
52809 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */
52810 #define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_MSB 2
52811 /* The width in bits of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */
52812 #define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_WIDTH 1
52813 /* The mask used to set the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field value. */
52814 #define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_SET_MSK 0x00000004
52815 /* The mask used to clear the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field value. */
52816 #define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_CLR_MSK 0xfffffffb
52817 /* The reset value of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */
52818 #define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_RESET 0x0
52819 /* Extracts the ALT_USB_HOST_HCINTMSK12_AHBERRMSK field value from a register. */
52820 #define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
52821 /* Produces a ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field value suitable for setting the register. */
52822 #define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
52823 
52824 /*
52825  * Field : stallmsk
52826  *
52827  * STALL Response Received Interrupt Mask (StallMsk)
52828  *
52829  * In scatter/gather DMA mode for host,
52830  *
52831  * interrupts will not be generated due to the corresponding bits set in
52832  *
52833  * HCINTn.
52834  *
52835  * Field Access Macros:
52836  *
52837  */
52838 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_STALLMSK register field. */
52839 #define ALT_USB_HOST_HCINTMSK12_STALLMSK_LSB 3
52840 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_STALLMSK register field. */
52841 #define ALT_USB_HOST_HCINTMSK12_STALLMSK_MSB 3
52842 /* The width in bits of the ALT_USB_HOST_HCINTMSK12_STALLMSK register field. */
52843 #define ALT_USB_HOST_HCINTMSK12_STALLMSK_WIDTH 1
52844 /* The mask used to set the ALT_USB_HOST_HCINTMSK12_STALLMSK register field value. */
52845 #define ALT_USB_HOST_HCINTMSK12_STALLMSK_SET_MSK 0x00000008
52846 /* The mask used to clear the ALT_USB_HOST_HCINTMSK12_STALLMSK register field value. */
52847 #define ALT_USB_HOST_HCINTMSK12_STALLMSK_CLR_MSK 0xfffffff7
52848 /* The reset value of the ALT_USB_HOST_HCINTMSK12_STALLMSK register field. */
52849 #define ALT_USB_HOST_HCINTMSK12_STALLMSK_RESET 0x0
52850 /* Extracts the ALT_USB_HOST_HCINTMSK12_STALLMSK field value from a register. */
52851 #define ALT_USB_HOST_HCINTMSK12_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
52852 /* Produces a ALT_USB_HOST_HCINTMSK12_STALLMSK register field value suitable for setting the register. */
52853 #define ALT_USB_HOST_HCINTMSK12_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
52854 
52855 /*
52856  * Field : nakmsk
52857  *
52858  * NAK Response Received Interrupt Mask (NakMsk)
52859  *
52860  * In scatter/gather DMA mode for host,
52861  *
52862  * interrupts will not be generated due to the corresponding bits set in
52863  *
52864  * HCINTn.
52865  *
52866  * Field Access Macros:
52867  *
52868  */
52869 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_NAKMSK register field. */
52870 #define ALT_USB_HOST_HCINTMSK12_NAKMSK_LSB 4
52871 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_NAKMSK register field. */
52872 #define ALT_USB_HOST_HCINTMSK12_NAKMSK_MSB 4
52873 /* The width in bits of the ALT_USB_HOST_HCINTMSK12_NAKMSK register field. */
52874 #define ALT_USB_HOST_HCINTMSK12_NAKMSK_WIDTH 1
52875 /* The mask used to set the ALT_USB_HOST_HCINTMSK12_NAKMSK register field value. */
52876 #define ALT_USB_HOST_HCINTMSK12_NAKMSK_SET_MSK 0x00000010
52877 /* The mask used to clear the ALT_USB_HOST_HCINTMSK12_NAKMSK register field value. */
52878 #define ALT_USB_HOST_HCINTMSK12_NAKMSK_CLR_MSK 0xffffffef
52879 /* The reset value of the ALT_USB_HOST_HCINTMSK12_NAKMSK register field. */
52880 #define ALT_USB_HOST_HCINTMSK12_NAKMSK_RESET 0x0
52881 /* Extracts the ALT_USB_HOST_HCINTMSK12_NAKMSK field value from a register. */
52882 #define ALT_USB_HOST_HCINTMSK12_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
52883 /* Produces a ALT_USB_HOST_HCINTMSK12_NAKMSK register field value suitable for setting the register. */
52884 #define ALT_USB_HOST_HCINTMSK12_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
52885 
52886 /*
52887  * Field : ackmsk
52888  *
52889  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
52890  *
52891  * In scatter/gather DMA mode for host,
52892  *
52893  * interrupts will not be generated due to the corresponding bits set in
52894  *
52895  * HCINTn.
52896  *
52897  * Field Access Macros:
52898  *
52899  */
52900 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_ACKMSK register field. */
52901 #define ALT_USB_HOST_HCINTMSK12_ACKMSK_LSB 5
52902 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_ACKMSK register field. */
52903 #define ALT_USB_HOST_HCINTMSK12_ACKMSK_MSB 5
52904 /* The width in bits of the ALT_USB_HOST_HCINTMSK12_ACKMSK register field. */
52905 #define ALT_USB_HOST_HCINTMSK12_ACKMSK_WIDTH 1
52906 /* The mask used to set the ALT_USB_HOST_HCINTMSK12_ACKMSK register field value. */
52907 #define ALT_USB_HOST_HCINTMSK12_ACKMSK_SET_MSK 0x00000020
52908 /* The mask used to clear the ALT_USB_HOST_HCINTMSK12_ACKMSK register field value. */
52909 #define ALT_USB_HOST_HCINTMSK12_ACKMSK_CLR_MSK 0xffffffdf
52910 /* The reset value of the ALT_USB_HOST_HCINTMSK12_ACKMSK register field. */
52911 #define ALT_USB_HOST_HCINTMSK12_ACKMSK_RESET 0x0
52912 /* Extracts the ALT_USB_HOST_HCINTMSK12_ACKMSK field value from a register. */
52913 #define ALT_USB_HOST_HCINTMSK12_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
52914 /* Produces a ALT_USB_HOST_HCINTMSK12_ACKMSK register field value suitable for setting the register. */
52915 #define ALT_USB_HOST_HCINTMSK12_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
52916 
52917 /*
52918  * Field : nyetmsk
52919  *
52920  * NYET Response Received Interrupt Mask (NyetMsk)
52921  *
52922  * In scatter/gather DMA mode for host,
52923  *
52924  * interrupts will not be generated due to the corresponding bits set in
52925  *
52926  * HCINTn.
52927  *
52928  * Field Access Macros:
52929  *
52930  */
52931 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_NYETMSK register field. */
52932 #define ALT_USB_HOST_HCINTMSK12_NYETMSK_LSB 6
52933 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_NYETMSK register field. */
52934 #define ALT_USB_HOST_HCINTMSK12_NYETMSK_MSB 6
52935 /* The width in bits of the ALT_USB_HOST_HCINTMSK12_NYETMSK register field. */
52936 #define ALT_USB_HOST_HCINTMSK12_NYETMSK_WIDTH 1
52937 /* The mask used to set the ALT_USB_HOST_HCINTMSK12_NYETMSK register field value. */
52938 #define ALT_USB_HOST_HCINTMSK12_NYETMSK_SET_MSK 0x00000040
52939 /* The mask used to clear the ALT_USB_HOST_HCINTMSK12_NYETMSK register field value. */
52940 #define ALT_USB_HOST_HCINTMSK12_NYETMSK_CLR_MSK 0xffffffbf
52941 /* The reset value of the ALT_USB_HOST_HCINTMSK12_NYETMSK register field. */
52942 #define ALT_USB_HOST_HCINTMSK12_NYETMSK_RESET 0x0
52943 /* Extracts the ALT_USB_HOST_HCINTMSK12_NYETMSK field value from a register. */
52944 #define ALT_USB_HOST_HCINTMSK12_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
52945 /* Produces a ALT_USB_HOST_HCINTMSK12_NYETMSK register field value suitable for setting the register. */
52946 #define ALT_USB_HOST_HCINTMSK12_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
52947 
52948 /*
52949  * Field : xacterrmsk
52950  *
52951  * Transaction Error Mask (XactErrMsk)
52952  *
52953  * In scatter/gather DMA mode for host,
52954  *
52955  * interrupts will not be generated due to the corresponding bits set in
52956  *
52957  * HCINTn.
52958  *
52959  * Field Access Macros:
52960  *
52961  */
52962 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field. */
52963 #define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_LSB 7
52964 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field. */
52965 #define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_MSB 7
52966 /* The width in bits of the ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field. */
52967 #define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_WIDTH 1
52968 /* The mask used to set the ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field value. */
52969 #define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_SET_MSK 0x00000080
52970 /* The mask used to clear the ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field value. */
52971 #define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_CLR_MSK 0xffffff7f
52972 /* The reset value of the ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field. */
52973 #define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_RESET 0x0
52974 /* Extracts the ALT_USB_HOST_HCINTMSK12_XACTERRMSK field value from a register. */
52975 #define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
52976 /* Produces a ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field value suitable for setting the register. */
52977 #define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
52978 
52979 /*
52980  * Field : bblerrmsk
52981  *
52982  * Babble Error Mask (BblErrMsk)
52983  *
52984  * In scatter/gather DMA mode for host,
52985  *
52986  * interrupts will not be generated due to the corresponding bits set in
52987  *
52988  * HCINTn.
52989  *
52990  * Field Access Macros:
52991  *
52992  */
52993 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field. */
52994 #define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_LSB 8
52995 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field. */
52996 #define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_MSB 8
52997 /* The width in bits of the ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field. */
52998 #define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_WIDTH 1
52999 /* The mask used to set the ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field value. */
53000 #define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_SET_MSK 0x00000100
53001 /* The mask used to clear the ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field value. */
53002 #define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_CLR_MSK 0xfffffeff
53003 /* The reset value of the ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field. */
53004 #define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_RESET 0x0
53005 /* Extracts the ALT_USB_HOST_HCINTMSK12_BBLERRMSK field value from a register. */
53006 #define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
53007 /* Produces a ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field value suitable for setting the register. */
53008 #define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
53009 
53010 /*
53011  * Field : frmovrunmsk
53012  *
53013  * Frame Overrun Mask (FrmOvrunMsk)
53014  *
53015  * In scatter/gather DMA mode for host,
53016  *
53017  * interrupts will not be generated due to the corresponding bits set in
53018  *
53019  * HCINTn.
53020  *
53021  * Field Access Macros:
53022  *
53023  */
53024 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field. */
53025 #define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_LSB 9
53026 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field. */
53027 #define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_MSB 9
53028 /* The width in bits of the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field. */
53029 #define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_WIDTH 1
53030 /* The mask used to set the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field value. */
53031 #define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_SET_MSK 0x00000200
53032 /* The mask used to clear the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field value. */
53033 #define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_CLR_MSK 0xfffffdff
53034 /* The reset value of the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field. */
53035 #define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_RESET 0x0
53036 /* Extracts the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK field value from a register. */
53037 #define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
53038 /* Produces a ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field value suitable for setting the register. */
53039 #define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
53040 
53041 /*
53042  * Field : datatglerrmsk
53043  *
53044  * Data Toggle Error Mask (DataTglErrMsk)
53045  *
53046  * In scatter/gather DMA mode for host,
53047  *
53048  * interrupts will not be generated due to the corresponding bits set in
53049  *
53050  * HCINTn.
53051  *
53052  * Field Access Macros:
53053  *
53054  */
53055 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field. */
53056 #define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_LSB 10
53057 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field. */
53058 #define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_MSB 10
53059 /* The width in bits of the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field. */
53060 #define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_WIDTH 1
53061 /* The mask used to set the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field value. */
53062 #define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_SET_MSK 0x00000400
53063 /* The mask used to clear the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field value. */
53064 #define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_CLR_MSK 0xfffffbff
53065 /* The reset value of the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field. */
53066 #define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_RESET 0x0
53067 /* Extracts the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK field value from a register. */
53068 #define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
53069 /* Produces a ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field value suitable for setting the register. */
53070 #define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
53071 
53072 /*
53073  * Field : bnaintrmsk
53074  *
53075  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
53076  *
53077  * This bit is valid only when Scatter/Gather DMA mode is enabled.
53078  *
53079  * Field Enumeration Values:
53080  *
53081  * Enum | Value | Description
53082  * :-------------------------------------------|:------|:------------
53083  * ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_MSK | 0x0 | Mask
53084  * ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_NOMSK | 0x1 | No mask
53085  *
53086  * Field Access Macros:
53087  *
53088  */
53089 /*
53090  * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_BNAINTRMSK
53091  *
53092  * Mask
53093  */
53094 #define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_MSK 0x0
53095 /*
53096  * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_BNAINTRMSK
53097  *
53098  * No mask
53099  */
53100 #define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_NOMSK 0x1
53101 
53102 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */
53103 #define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_LSB 11
53104 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */
53105 #define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_MSB 11
53106 /* The width in bits of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */
53107 #define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_WIDTH 1
53108 /* The mask used to set the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field value. */
53109 #define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_SET_MSK 0x00000800
53110 /* The mask used to clear the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field value. */
53111 #define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_CLR_MSK 0xfffff7ff
53112 /* The reset value of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */
53113 #define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_RESET 0x0
53114 /* Extracts the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK field value from a register. */
53115 #define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
53116 /* Produces a ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field value suitable for setting the register. */
53117 #define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
53118 
53119 /*
53120  * Field : frm_lst_rollintrmsk
53121  *
53122  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
53123  *
53124  * This bit is valid only when Scatter/Gather DMA mode is enabled.
53125  *
53126  * Field Enumeration Values:
53127  *
53128  * Enum | Value | Description
53129  * :----------------------------------------------------|:------|:------------
53130  * ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
53131  * ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
53132  *
53133  * Field Access Macros:
53134  *
53135  */
53136 /*
53137  * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK
53138  *
53139  * Mask
53140  */
53141 #define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_MSK 0x0
53142 /*
53143  * Enumerated value for register field ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK
53144  *
53145  * No mask
53146  */
53147 #define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
53148 
53149 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */
53150 #define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_LSB 13
53151 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */
53152 #define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_MSB 13
53153 /* The width in bits of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */
53154 #define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_WIDTH 1
53155 /* The mask used to set the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field value. */
53156 #define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
53157 /* The mask used to clear the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field value. */
53158 #define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
53159 /* The reset value of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */
53160 #define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_RESET 0x0
53161 /* Extracts the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK field value from a register. */
53162 #define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
53163 /* Produces a ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
53164 #define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
53165 
53166 #ifndef __ASSEMBLY__
53167 /*
53168  * WARNING: The C register and register group struct declarations are provided for
53169  * convenience and illustrative purposes. They should, however, be used with
53170  * caution as the C language standard provides no guarantees about the alignment or
53171  * atomicity of device memory accesses. The recommended practice for writing
53172  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53173  * alt_write_word() functions.
53174  *
53175  * The struct declaration for register ALT_USB_HOST_HCINTMSK12.
53176  */
53177 struct ALT_USB_HOST_HCINTMSK12_s
53178 {
53179  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK */
53180  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK12_CHHLTDMSK */
53181  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK12_AHBERRMSK */
53182  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK12_STALLMSK */
53183  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK12_NAKMSK */
53184  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK12_ACKMSK */
53185  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK12_NYETMSK */
53186  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK12_XACTERRMSK */
53187  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK12_BBLERRMSK */
53188  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK */
53189  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK */
53190  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK12_BNAINTRMSK */
53191  uint32_t : 1; /* *UNDEFINED* */
53192  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK */
53193  uint32_t : 18; /* *UNDEFINED* */
53194 };
53195 
53196 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK12. */
53197 typedef volatile struct ALT_USB_HOST_HCINTMSK12_s ALT_USB_HOST_HCINTMSK12_t;
53198 #endif /* __ASSEMBLY__ */
53199 
53200 /* The reset value of the ALT_USB_HOST_HCINTMSK12 register. */
53201 #define ALT_USB_HOST_HCINTMSK12_RESET 0x00000000
53202 /* The byte offset of the ALT_USB_HOST_HCINTMSK12 register from the beginning of the component. */
53203 #define ALT_USB_HOST_HCINTMSK12_OFST 0x28c
53204 /* The address of the ALT_USB_HOST_HCINTMSK12 register. */
53205 #define ALT_USB_HOST_HCINTMSK12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK12_OFST))
53206 
53207 /*
53208  * Register : hctsiz12
53209  *
53210  * Host Channel 12 Transfer Size Register
53211  *
53212  * Register Layout
53213  *
53214  * Bits | Access | Reset | Description
53215  * :--------|:-------|:------|:-------------------------------
53216  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ12_XFERSIZE
53217  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ12_PKTCNT
53218  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ12_PID
53219  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ12_DOPNG
53220  *
53221  */
53222 /*
53223  * Field : xfersize
53224  *
53225  * Transfer Size (XferSize)
53226  *
53227  * For an OUT, this field is the number of data bytes the host sends
53228  *
53229  * during the transfer.
53230  *
53231  * For an IN, this field is the buffer size that the application has
53232  *
53233  * Reserved For the transfer. The application is expected to
53234  *
53235  * program this field as an integer multiple of the maximum packet
53236  *
53237  * size For IN transactions (periodic and non-periodic).
53238  *
53239  * The width of this counter is specified as Width of Transfer Size
53240  *
53241  * Counters
53242  *
53243  * Field Access Macros:
53244  *
53245  */
53246 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */
53247 #define ALT_USB_HOST_HCTSIZ12_XFERSIZE_LSB 0
53248 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */
53249 #define ALT_USB_HOST_HCTSIZ12_XFERSIZE_MSB 18
53250 /* The width in bits of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */
53251 #define ALT_USB_HOST_HCTSIZ12_XFERSIZE_WIDTH 19
53252 /* The mask used to set the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field value. */
53253 #define ALT_USB_HOST_HCTSIZ12_XFERSIZE_SET_MSK 0x0007ffff
53254 /* The mask used to clear the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field value. */
53255 #define ALT_USB_HOST_HCTSIZ12_XFERSIZE_CLR_MSK 0xfff80000
53256 /* The reset value of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */
53257 #define ALT_USB_HOST_HCTSIZ12_XFERSIZE_RESET 0x0
53258 /* Extracts the ALT_USB_HOST_HCTSIZ12_XFERSIZE field value from a register. */
53259 #define ALT_USB_HOST_HCTSIZ12_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
53260 /* Produces a ALT_USB_HOST_HCTSIZ12_XFERSIZE register field value suitable for setting the register. */
53261 #define ALT_USB_HOST_HCTSIZ12_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
53262 
53263 /*
53264  * Field : pktcnt
53265  *
53266  * Packet Count (PktCnt)
53267  *
53268  * This field is programmed by the application with the expected
53269  *
53270  * number of packets to be transmitted (OUT) or received (IN).
53271  *
53272  * The host decrements this count on every successful
53273  *
53274  * transmission or reception of an OUT/IN packet. Once this count
53275  *
53276  * reaches zero, the application is interrupted to indicate normal
53277  *
53278  * completion.
53279  *
53280  * The width of this counter is specified as Width of Packet
53281  *
53282  * Counters
53283  *
53284  * Field Access Macros:
53285  *
53286  */
53287 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */
53288 #define ALT_USB_HOST_HCTSIZ12_PKTCNT_LSB 19
53289 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */
53290 #define ALT_USB_HOST_HCTSIZ12_PKTCNT_MSB 28
53291 /* The width in bits of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */
53292 #define ALT_USB_HOST_HCTSIZ12_PKTCNT_WIDTH 10
53293 /* The mask used to set the ALT_USB_HOST_HCTSIZ12_PKTCNT register field value. */
53294 #define ALT_USB_HOST_HCTSIZ12_PKTCNT_SET_MSK 0x1ff80000
53295 /* The mask used to clear the ALT_USB_HOST_HCTSIZ12_PKTCNT register field value. */
53296 #define ALT_USB_HOST_HCTSIZ12_PKTCNT_CLR_MSK 0xe007ffff
53297 /* The reset value of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */
53298 #define ALT_USB_HOST_HCTSIZ12_PKTCNT_RESET 0x0
53299 /* Extracts the ALT_USB_HOST_HCTSIZ12_PKTCNT field value from a register. */
53300 #define ALT_USB_HOST_HCTSIZ12_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
53301 /* Produces a ALT_USB_HOST_HCTSIZ12_PKTCNT register field value suitable for setting the register. */
53302 #define ALT_USB_HOST_HCTSIZ12_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
53303 
53304 /*
53305  * Field : pid
53306  *
53307  * PID (Pid)
53308  *
53309  * The application programs this field with the type of PID to use For
53310  *
53311  * the initial transaction. The host maintains this field For the rest of
53312  *
53313  * the transfer.
53314  *
53315  * 2'b00: DATA0
53316  *
53317  * 2'b01: DATA2
53318  *
53319  * 2'b10: DATA1
53320  *
53321  * 2'b11: MDATA (non-control)/SETUP (control)
53322  *
53323  * Field Enumeration Values:
53324  *
53325  * Enum | Value | Description
53326  * :----------------------------------|:------|:------------------------------------
53327  * ALT_USB_HOST_HCTSIZ12_PID_E_DATA0 | 0x0 | DATA0
53328  * ALT_USB_HOST_HCTSIZ12_PID_E_DATA2 | 0x1 | DATA2
53329  * ALT_USB_HOST_HCTSIZ12_PID_E_DATA1 | 0x2 | DATA1
53330  * ALT_USB_HOST_HCTSIZ12_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
53331  *
53332  * Field Access Macros:
53333  *
53334  */
53335 /*
53336  * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID
53337  *
53338  * DATA0
53339  */
53340 #define ALT_USB_HOST_HCTSIZ12_PID_E_DATA0 0x0
53341 /*
53342  * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID
53343  *
53344  * DATA2
53345  */
53346 #define ALT_USB_HOST_HCTSIZ12_PID_E_DATA2 0x1
53347 /*
53348  * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID
53349  *
53350  * DATA1
53351  */
53352 #define ALT_USB_HOST_HCTSIZ12_PID_E_DATA1 0x2
53353 /*
53354  * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID
53355  *
53356  * MDATA (non-control)/SETUP (control)
53357  */
53358 #define ALT_USB_HOST_HCTSIZ12_PID_E_MDATA 0x3
53359 
53360 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_PID register field. */
53361 #define ALT_USB_HOST_HCTSIZ12_PID_LSB 29
53362 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_PID register field. */
53363 #define ALT_USB_HOST_HCTSIZ12_PID_MSB 30
53364 /* The width in bits of the ALT_USB_HOST_HCTSIZ12_PID register field. */
53365 #define ALT_USB_HOST_HCTSIZ12_PID_WIDTH 2
53366 /* The mask used to set the ALT_USB_HOST_HCTSIZ12_PID register field value. */
53367 #define ALT_USB_HOST_HCTSIZ12_PID_SET_MSK 0x60000000
53368 /* The mask used to clear the ALT_USB_HOST_HCTSIZ12_PID register field value. */
53369 #define ALT_USB_HOST_HCTSIZ12_PID_CLR_MSK 0x9fffffff
53370 /* The reset value of the ALT_USB_HOST_HCTSIZ12_PID register field. */
53371 #define ALT_USB_HOST_HCTSIZ12_PID_RESET 0x0
53372 /* Extracts the ALT_USB_HOST_HCTSIZ12_PID field value from a register. */
53373 #define ALT_USB_HOST_HCTSIZ12_PID_GET(value) (((value) & 0x60000000) >> 29)
53374 /* Produces a ALT_USB_HOST_HCTSIZ12_PID register field value suitable for setting the register. */
53375 #define ALT_USB_HOST_HCTSIZ12_PID_SET(value) (((value) << 29) & 0x60000000)
53376 
53377 /*
53378  * Field : dopng
53379  *
53380  * Do Ping (DoPng)
53381  *
53382  * This bit is used only For OUT transfers.
53383  *
53384  * Setting this field to 1 directs the host to do PING protocol.
53385  *
53386  * Note: Do not Set this bit For IN transfers. If this bit is Set For
53387  *
53388  * for IN transfers it disables the channel.
53389  *
53390  * Field Enumeration Values:
53391  *
53392  * Enum | Value | Description
53393  * :-------------------------------------|:------|:-----------------
53394  * ALT_USB_HOST_HCTSIZ12_DOPNG_E_NOPING | 0x0 | No ping protocol
53395  * ALT_USB_HOST_HCTSIZ12_DOPNG_E_PING | 0x1 | Ping protocol
53396  *
53397  * Field Access Macros:
53398  *
53399  */
53400 /*
53401  * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_DOPNG
53402  *
53403  * No ping protocol
53404  */
53405 #define ALT_USB_HOST_HCTSIZ12_DOPNG_E_NOPING 0x0
53406 /*
53407  * Enumerated value for register field ALT_USB_HOST_HCTSIZ12_DOPNG
53408  *
53409  * Ping protocol
53410  */
53411 #define ALT_USB_HOST_HCTSIZ12_DOPNG_E_PING 0x1
53412 
53413 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */
53414 #define ALT_USB_HOST_HCTSIZ12_DOPNG_LSB 31
53415 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */
53416 #define ALT_USB_HOST_HCTSIZ12_DOPNG_MSB 31
53417 /* The width in bits of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */
53418 #define ALT_USB_HOST_HCTSIZ12_DOPNG_WIDTH 1
53419 /* The mask used to set the ALT_USB_HOST_HCTSIZ12_DOPNG register field value. */
53420 #define ALT_USB_HOST_HCTSIZ12_DOPNG_SET_MSK 0x80000000
53421 /* The mask used to clear the ALT_USB_HOST_HCTSIZ12_DOPNG register field value. */
53422 #define ALT_USB_HOST_HCTSIZ12_DOPNG_CLR_MSK 0x7fffffff
53423 /* The reset value of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */
53424 #define ALT_USB_HOST_HCTSIZ12_DOPNG_RESET 0x0
53425 /* Extracts the ALT_USB_HOST_HCTSIZ12_DOPNG field value from a register. */
53426 #define ALT_USB_HOST_HCTSIZ12_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
53427 /* Produces a ALT_USB_HOST_HCTSIZ12_DOPNG register field value suitable for setting the register. */
53428 #define ALT_USB_HOST_HCTSIZ12_DOPNG_SET(value) (((value) << 31) & 0x80000000)
53429 
53430 #ifndef __ASSEMBLY__
53431 /*
53432  * WARNING: The C register and register group struct declarations are provided for
53433  * convenience and illustrative purposes. They should, however, be used with
53434  * caution as the C language standard provides no guarantees about the alignment or
53435  * atomicity of device memory accesses. The recommended practice for writing
53436  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53437  * alt_write_word() functions.
53438  *
53439  * The struct declaration for register ALT_USB_HOST_HCTSIZ12.
53440  */
53441 struct ALT_USB_HOST_HCTSIZ12_s
53442 {
53443  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ12_XFERSIZE */
53444  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ12_PKTCNT */
53445  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ12_PID */
53446  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ12_DOPNG */
53447 };
53448 
53449 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ12. */
53450 typedef volatile struct ALT_USB_HOST_HCTSIZ12_s ALT_USB_HOST_HCTSIZ12_t;
53451 #endif /* __ASSEMBLY__ */
53452 
53453 /* The reset value of the ALT_USB_HOST_HCTSIZ12 register. */
53454 #define ALT_USB_HOST_HCTSIZ12_RESET 0x00000000
53455 /* The byte offset of the ALT_USB_HOST_HCTSIZ12 register from the beginning of the component. */
53456 #define ALT_USB_HOST_HCTSIZ12_OFST 0x290
53457 /* The address of the ALT_USB_HOST_HCTSIZ12 register. */
53458 #define ALT_USB_HOST_HCTSIZ12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ12_OFST))
53459 
53460 /*
53461  * Register : hcdma12
53462  *
53463  * Host Channel 12 DMA Address Register
53464  *
53465  * Register Layout
53466  *
53467  * Bits | Access | Reset | Description
53468  * :-------|:-------|:------|:-----------------------------
53469  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA12_HCDMA12
53470  *
53471  */
53472 /*
53473  * Field : hcdma12
53474  *
53475  * Buffer DMA Mode:
53476  *
53477  * [31:0] DMA Address (DMAAddr)
53478  *
53479  * This field holds the start address in the external memory from which the data
53480  * for
53481  *
53482  * the endpoint must be fetched or to which it must be stored. This register is
53483  *
53484  * incremented on every AHB transaction.
53485  *
53486  * Scatter-Gather DMA (DescDMA) Mode:
53487  *
53488  * [31:9] (Non Isoc) Non-Isochronous:
53489  *
53490  * [31:N] (Isoc) Isochronous:
53491  *
53492  * This field holds the start address of the 512 bytes
53493  *
53494  * page. The first descriptor in the list should be located
53495  *
53496  * in this address. The first descriptor may be or may
53497  *
53498  * not be ready. The core starts processing the list from
53499  *
53500  * the CTD value.
53501  *
53502  * This field holds the address of the 2*(nTD+1) bytes of
53503  *
53504  * locations in which the isochronous descriptors are
53505  *
53506  * present where N is based on nTD as per Table below
53507  *
53508  * [31:N] Base Address
53509  *
53510  * [N-1:3] Offset
53511  *
53512  * [2:0] 000
53513  *
53514  * HS ISOC
53515  *
53516  * nTD N
53517  *
53518  * 7 6
53519  *
53520  * 15 7
53521  *
53522  * 31 8
53523  *
53524  * 63 9
53525  *
53526  * 127 10
53527  *
53528  * 255 11
53529  *
53530  * FS ISOC
53531  *
53532  * nTD N
53533  *
53534  * 1 4
53535  *
53536  * 3 5
53537  *
53538  * 7 6
53539  *
53540  * 15 7
53541  *
53542  * 31 8
53543  *
53544  * 63 9
53545  *
53546  * [N-1:3] (Isoc):
53547  *
53548  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
53549  *
53550  * Non Isochronous:
53551  *
53552  * This value is in terms of number of descriptors. The values can be from 0 to 63.
53553  *
53554  * 0 - 1 descriptor.
53555  *
53556  * 63 - 64 descriptors.
53557  *
53558  * This field indicates the current descriptor processed in the list. This field is
53559  * updated
53560  *
53561  * both by application and the core. For example, if the application enables the
53562  *
53563  * channel after programming CTD=5, then the core will start processing the 6th
53564  *
53565  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
53566  *
53567  * to DMAAddr.
53568  *
53569  * Isochronous:
53570  *
53571  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
53572  * set
53573  *
53574  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
53575  *
53576  * [31:9] (Non Isoc) Non-Isochronous:
53577  *
53578  * [31:N] (Isoc) Isochronous:
53579  *
53580  * This field holds the start address of the 512 bytes
53581  *
53582  * page. The first descriptor in the list should be located
53583  *
53584  * in this address. The first descriptor may be or may
53585  *
53586  * not be ready. The core starts processing the list from
53587  *
53588  * the CTD value.
53589  *
53590  * This field holds the address of the 2*(nTD+1) bytes of
53591  *
53592  * locations in which the isochronous descriptors are
53593  *
53594  * present where N is based on nTD as per Table below
53595  *
53596  * [31:N] Base Address
53597  *
53598  * [N-1:3] Offset
53599  *
53600  * [2:0] 000
53601  *
53602  * HS ISOC
53603  *
53604  * nTD N
53605  *
53606  * 7 6
53607  *
53608  * 15 7
53609  *
53610  * 31 8
53611  *
53612  * 63 9
53613  *
53614  * 127 10
53615  *
53616  * 255 11
53617  *
53618  * FS ISOC
53619  *
53620  * nTD N
53621  *
53622  * 1 4
53623  *
53624  * 3 5
53625  *
53626  * 7 6
53627  *
53628  * 15 7
53629  *
53630  * 31 8
53631  *
53632  * 63 9
53633  *
53634  * [N-1:3] (Isoc):
53635  *
53636  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
53637  *
53638  * Non Isochronous:
53639  *
53640  * This value is in terms of number of descriptors. The values can be from 0 to 63.
53641  *
53642  * 0 - 1 descriptor.
53643  *
53644  * 63 - 64 descriptors.
53645  *
53646  * This field indicates the current descriptor processed in the list. This field is
53647  * updated
53648  *
53649  * both by application and the core. For example, if the application enables the
53650  *
53651  * channel after programming CTD=5, then the core will start processing the 6th
53652  *
53653  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
53654  *
53655  * to DMAAddr.
53656  *
53657  * Isochronous:
53658  *
53659  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
53660  * set
53661  *
53662  * to zero by application.
53663  *
53664  * Field Access Macros:
53665  *
53666  */
53667 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */
53668 #define ALT_USB_HOST_HCDMA12_HCDMA12_LSB 0
53669 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */
53670 #define ALT_USB_HOST_HCDMA12_HCDMA12_MSB 31
53671 /* The width in bits of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */
53672 #define ALT_USB_HOST_HCDMA12_HCDMA12_WIDTH 32
53673 /* The mask used to set the ALT_USB_HOST_HCDMA12_HCDMA12 register field value. */
53674 #define ALT_USB_HOST_HCDMA12_HCDMA12_SET_MSK 0xffffffff
53675 /* The mask used to clear the ALT_USB_HOST_HCDMA12_HCDMA12 register field value. */
53676 #define ALT_USB_HOST_HCDMA12_HCDMA12_CLR_MSK 0x00000000
53677 /* The reset value of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */
53678 #define ALT_USB_HOST_HCDMA12_HCDMA12_RESET 0x0
53679 /* Extracts the ALT_USB_HOST_HCDMA12_HCDMA12 field value from a register. */
53680 #define ALT_USB_HOST_HCDMA12_HCDMA12_GET(value) (((value) & 0xffffffff) >> 0)
53681 /* Produces a ALT_USB_HOST_HCDMA12_HCDMA12 register field value suitable for setting the register. */
53682 #define ALT_USB_HOST_HCDMA12_HCDMA12_SET(value) (((value) << 0) & 0xffffffff)
53683 
53684 #ifndef __ASSEMBLY__
53685 /*
53686  * WARNING: The C register and register group struct declarations are provided for
53687  * convenience and illustrative purposes. They should, however, be used with
53688  * caution as the C language standard provides no guarantees about the alignment or
53689  * atomicity of device memory accesses. The recommended practice for writing
53690  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53691  * alt_write_word() functions.
53692  *
53693  * The struct declaration for register ALT_USB_HOST_HCDMA12.
53694  */
53695 struct ALT_USB_HOST_HCDMA12_s
53696 {
53697  uint32_t hcdma12 : 32; /* ALT_USB_HOST_HCDMA12_HCDMA12 */
53698 };
53699 
53700 /* The typedef declaration for register ALT_USB_HOST_HCDMA12. */
53701 typedef volatile struct ALT_USB_HOST_HCDMA12_s ALT_USB_HOST_HCDMA12_t;
53702 #endif /* __ASSEMBLY__ */
53703 
53704 /* The reset value of the ALT_USB_HOST_HCDMA12 register. */
53705 #define ALT_USB_HOST_HCDMA12_RESET 0x00000000
53706 /* The byte offset of the ALT_USB_HOST_HCDMA12 register from the beginning of the component. */
53707 #define ALT_USB_HOST_HCDMA12_OFST 0x294
53708 /* The address of the ALT_USB_HOST_HCDMA12 register. */
53709 #define ALT_USB_HOST_HCDMA12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA12_OFST))
53710 
53711 /*
53712  * Register : hcdmab12
53713  *
53714  * Host Channel 12 DMA Buffer Address Register
53715  *
53716  * Register Layout
53717  *
53718  * Bits | Access | Reset | Description
53719  * :-------|:-------|:------|:-------------------------------
53720  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB12_HCDMAB12
53721  *
53722  */
53723 /*
53724  * Field : hcdmab12
53725  *
53726  * Holds the current buffer address.
53727  *
53728  * This register is updated as and when the data transfer for the corresponding end
53729  * point
53730  *
53731  * is in progress. This register is present only in Scatter/Gather DMA mode.
53732  * Otherwise this
53733  *
53734  * field is reserved.
53735  *
53736  * Field Access Macros:
53737  *
53738  */
53739 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */
53740 #define ALT_USB_HOST_HCDMAB12_HCDMAB12_LSB 0
53741 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */
53742 #define ALT_USB_HOST_HCDMAB12_HCDMAB12_MSB 31
53743 /* The width in bits of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */
53744 #define ALT_USB_HOST_HCDMAB12_HCDMAB12_WIDTH 32
53745 /* The mask used to set the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field value. */
53746 #define ALT_USB_HOST_HCDMAB12_HCDMAB12_SET_MSK 0xffffffff
53747 /* The mask used to clear the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field value. */
53748 #define ALT_USB_HOST_HCDMAB12_HCDMAB12_CLR_MSK 0x00000000
53749 /* The reset value of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */
53750 #define ALT_USB_HOST_HCDMAB12_HCDMAB12_RESET 0x0
53751 /* Extracts the ALT_USB_HOST_HCDMAB12_HCDMAB12 field value from a register. */
53752 #define ALT_USB_HOST_HCDMAB12_HCDMAB12_GET(value) (((value) & 0xffffffff) >> 0)
53753 /* Produces a ALT_USB_HOST_HCDMAB12_HCDMAB12 register field value suitable for setting the register. */
53754 #define ALT_USB_HOST_HCDMAB12_HCDMAB12_SET(value) (((value) << 0) & 0xffffffff)
53755 
53756 #ifndef __ASSEMBLY__
53757 /*
53758  * WARNING: The C register and register group struct declarations are provided for
53759  * convenience and illustrative purposes. They should, however, be used with
53760  * caution as the C language standard provides no guarantees about the alignment or
53761  * atomicity of device memory accesses. The recommended practice for writing
53762  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53763  * alt_write_word() functions.
53764  *
53765  * The struct declaration for register ALT_USB_HOST_HCDMAB12.
53766  */
53767 struct ALT_USB_HOST_HCDMAB12_s
53768 {
53769  uint32_t hcdmab12 : 32; /* ALT_USB_HOST_HCDMAB12_HCDMAB12 */
53770 };
53771 
53772 /* The typedef declaration for register ALT_USB_HOST_HCDMAB12. */
53773 typedef volatile struct ALT_USB_HOST_HCDMAB12_s ALT_USB_HOST_HCDMAB12_t;
53774 #endif /* __ASSEMBLY__ */
53775 
53776 /* The reset value of the ALT_USB_HOST_HCDMAB12 register. */
53777 #define ALT_USB_HOST_HCDMAB12_RESET 0x00000000
53778 /* The byte offset of the ALT_USB_HOST_HCDMAB12 register from the beginning of the component. */
53779 #define ALT_USB_HOST_HCDMAB12_OFST 0x29c
53780 /* The address of the ALT_USB_HOST_HCDMAB12 register. */
53781 #define ALT_USB_HOST_HCDMAB12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB12_OFST))
53782 
53783 /*
53784  * Register : hcchar13
53785  *
53786  * Host Channel 13 Characteristics Register
53787  *
53788  * Register Layout
53789  *
53790  * Bits | Access | Reset | Description
53791  * :--------|:---------|:------|:------------------------------
53792  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_MPS
53793  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_EPNUM
53794  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_EPDIR
53795  * [16] | ??? | 0x0 | *UNDEFINED*
53796  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_LSPDDEV
53797  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_EPTYPE
53798  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_EC
53799  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_DEVADDR
53800  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_ODDFRM
53801  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR13_CHDIS
53802  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR13_CHENA
53803  *
53804  */
53805 /*
53806  * Field : mps
53807  *
53808  * Maximum Packet Size (MPS)
53809  *
53810  * Indicates the maximum packet size of the associated endpoint.
53811  *
53812  * Field Access Macros:
53813  *
53814  */
53815 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_MPS register field. */
53816 #define ALT_USB_HOST_HCCHAR13_MPS_LSB 0
53817 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_MPS register field. */
53818 #define ALT_USB_HOST_HCCHAR13_MPS_MSB 10
53819 /* The width in bits of the ALT_USB_HOST_HCCHAR13_MPS register field. */
53820 #define ALT_USB_HOST_HCCHAR13_MPS_WIDTH 11
53821 /* The mask used to set the ALT_USB_HOST_HCCHAR13_MPS register field value. */
53822 #define ALT_USB_HOST_HCCHAR13_MPS_SET_MSK 0x000007ff
53823 /* The mask used to clear the ALT_USB_HOST_HCCHAR13_MPS register field value. */
53824 #define ALT_USB_HOST_HCCHAR13_MPS_CLR_MSK 0xfffff800
53825 /* The reset value of the ALT_USB_HOST_HCCHAR13_MPS register field. */
53826 #define ALT_USB_HOST_HCCHAR13_MPS_RESET 0x0
53827 /* Extracts the ALT_USB_HOST_HCCHAR13_MPS field value from a register. */
53828 #define ALT_USB_HOST_HCCHAR13_MPS_GET(value) (((value) & 0x000007ff) >> 0)
53829 /* Produces a ALT_USB_HOST_HCCHAR13_MPS register field value suitable for setting the register. */
53830 #define ALT_USB_HOST_HCCHAR13_MPS_SET(value) (((value) << 0) & 0x000007ff)
53831 
53832 /*
53833  * Field : epnum
53834  *
53835  * Endpoint Number (EPNum)
53836  *
53837  * Indicates the endpoint number on the device serving as the data
53838  *
53839  * source or sink.
53840  *
53841  * Field Enumeration Values:
53842  *
53843  * Enum | Value | Description
53844  * :--------------------------------------|:------|:--------------
53845  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT0 | 0x0 | End point 0
53846  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT1 | 0x1 | End point 1
53847  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT2 | 0x2 | End point 2
53848  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT3 | 0x3 | End point 3
53849  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT4 | 0x4 | End point 4
53850  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT5 | 0x5 | End point 5
53851  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT6 | 0x6 | End point 6
53852  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT7 | 0x7 | End point 7
53853  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT8 | 0x8 | End point 8
53854  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT9 | 0x9 | End point 9
53855  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT10 | 0xa | End point 10
53856  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT11 | 0xb | End point 11
53857  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT12 | 0xc | End point 12
53858  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT13 | 0xd | End point 13
53859  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT14 | 0xe | End point 14
53860  * ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT15 | 0xf | End point 15
53861  *
53862  * Field Access Macros:
53863  *
53864  */
53865 /*
53866  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53867  *
53868  * End point 0
53869  */
53870 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT0 0x0
53871 /*
53872  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53873  *
53874  * End point 1
53875  */
53876 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT1 0x1
53877 /*
53878  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53879  *
53880  * End point 2
53881  */
53882 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT2 0x2
53883 /*
53884  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53885  *
53886  * End point 3
53887  */
53888 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT3 0x3
53889 /*
53890  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53891  *
53892  * End point 4
53893  */
53894 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT4 0x4
53895 /*
53896  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53897  *
53898  * End point 5
53899  */
53900 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT5 0x5
53901 /*
53902  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53903  *
53904  * End point 6
53905  */
53906 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT6 0x6
53907 /*
53908  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53909  *
53910  * End point 7
53911  */
53912 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT7 0x7
53913 /*
53914  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53915  *
53916  * End point 8
53917  */
53918 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT8 0x8
53919 /*
53920  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53921  *
53922  * End point 9
53923  */
53924 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT9 0x9
53925 /*
53926  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53927  *
53928  * End point 10
53929  */
53930 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT10 0xa
53931 /*
53932  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53933  *
53934  * End point 11
53935  */
53936 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT11 0xb
53937 /*
53938  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53939  *
53940  * End point 12
53941  */
53942 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT12 0xc
53943 /*
53944  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53945  *
53946  * End point 13
53947  */
53948 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT13 0xd
53949 /*
53950  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53951  *
53952  * End point 14
53953  */
53954 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT14 0xe
53955 /*
53956  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
53957  *
53958  * End point 15
53959  */
53960 #define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT15 0xf
53961 
53962 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */
53963 #define ALT_USB_HOST_HCCHAR13_EPNUM_LSB 11
53964 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */
53965 #define ALT_USB_HOST_HCCHAR13_EPNUM_MSB 14
53966 /* The width in bits of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */
53967 #define ALT_USB_HOST_HCCHAR13_EPNUM_WIDTH 4
53968 /* The mask used to set the ALT_USB_HOST_HCCHAR13_EPNUM register field value. */
53969 #define ALT_USB_HOST_HCCHAR13_EPNUM_SET_MSK 0x00007800
53970 /* The mask used to clear the ALT_USB_HOST_HCCHAR13_EPNUM register field value. */
53971 #define ALT_USB_HOST_HCCHAR13_EPNUM_CLR_MSK 0xffff87ff
53972 /* The reset value of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */
53973 #define ALT_USB_HOST_HCCHAR13_EPNUM_RESET 0x0
53974 /* Extracts the ALT_USB_HOST_HCCHAR13_EPNUM field value from a register. */
53975 #define ALT_USB_HOST_HCCHAR13_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
53976 /* Produces a ALT_USB_HOST_HCCHAR13_EPNUM register field value suitable for setting the register. */
53977 #define ALT_USB_HOST_HCCHAR13_EPNUM_SET(value) (((value) << 11) & 0x00007800)
53978 
53979 /*
53980  * Field : epdir
53981  *
53982  * Endpoint Direction (EPDir)
53983  *
53984  * Indicates whether the transaction is IN or OUT.
53985  *
53986  * 1'b0: OUT
53987  *
53988  * 1'b1: IN
53989  *
53990  * Field Enumeration Values:
53991  *
53992  * Enum | Value | Description
53993  * :----------------------------------|:------|:--------------
53994  * ALT_USB_HOST_HCCHAR13_EPDIR_E_OUT | 0x0 | OUT Direction
53995  * ALT_USB_HOST_HCCHAR13_EPDIR_E_IN | 0x1 | IN Direction
53996  *
53997  * Field Access Macros:
53998  *
53999  */
54000 /*
54001  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPDIR
54002  *
54003  * OUT Direction
54004  */
54005 #define ALT_USB_HOST_HCCHAR13_EPDIR_E_OUT 0x0
54006 /*
54007  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPDIR
54008  *
54009  * IN Direction
54010  */
54011 #define ALT_USB_HOST_HCCHAR13_EPDIR_E_IN 0x1
54012 
54013 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */
54014 #define ALT_USB_HOST_HCCHAR13_EPDIR_LSB 15
54015 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */
54016 #define ALT_USB_HOST_HCCHAR13_EPDIR_MSB 15
54017 /* The width in bits of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */
54018 #define ALT_USB_HOST_HCCHAR13_EPDIR_WIDTH 1
54019 /* The mask used to set the ALT_USB_HOST_HCCHAR13_EPDIR register field value. */
54020 #define ALT_USB_HOST_HCCHAR13_EPDIR_SET_MSK 0x00008000
54021 /* The mask used to clear the ALT_USB_HOST_HCCHAR13_EPDIR register field value. */
54022 #define ALT_USB_HOST_HCCHAR13_EPDIR_CLR_MSK 0xffff7fff
54023 /* The reset value of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */
54024 #define ALT_USB_HOST_HCCHAR13_EPDIR_RESET 0x0
54025 /* Extracts the ALT_USB_HOST_HCCHAR13_EPDIR field value from a register. */
54026 #define ALT_USB_HOST_HCCHAR13_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
54027 /* Produces a ALT_USB_HOST_HCCHAR13_EPDIR register field value suitable for setting the register. */
54028 #define ALT_USB_HOST_HCCHAR13_EPDIR_SET(value) (((value) << 15) & 0x00008000)
54029 
54030 /*
54031  * Field : lspddev
54032  *
54033  * Low-Speed Device (LSpdDev)
54034  *
54035  * This field is Set by the application to indicate that this channel is
54036  *
54037  * communicating to a low-speed device.
54038  *
54039  * Field Enumeration Values:
54040  *
54041  * Enum | Value | Description
54042  * :-------------------------------------|:------|:----------------------------------------
54043  * ALT_USB_HOST_HCCHAR13_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
54044  * ALT_USB_HOST_HCCHAR13_LSPDDEV_E_END | 0x1 | Communicating with low speed device
54045  *
54046  * Field Access Macros:
54047  *
54048  */
54049 /*
54050  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_LSPDDEV
54051  *
54052  * Not Communicating with low speed device
54053  */
54054 #define ALT_USB_HOST_HCCHAR13_LSPDDEV_E_DISD 0x0
54055 /*
54056  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_LSPDDEV
54057  *
54058  * Communicating with low speed device
54059  */
54060 #define ALT_USB_HOST_HCCHAR13_LSPDDEV_E_END 0x1
54061 
54062 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */
54063 #define ALT_USB_HOST_HCCHAR13_LSPDDEV_LSB 17
54064 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */
54065 #define ALT_USB_HOST_HCCHAR13_LSPDDEV_MSB 17
54066 /* The width in bits of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */
54067 #define ALT_USB_HOST_HCCHAR13_LSPDDEV_WIDTH 1
54068 /* The mask used to set the ALT_USB_HOST_HCCHAR13_LSPDDEV register field value. */
54069 #define ALT_USB_HOST_HCCHAR13_LSPDDEV_SET_MSK 0x00020000
54070 /* The mask used to clear the ALT_USB_HOST_HCCHAR13_LSPDDEV register field value. */
54071 #define ALT_USB_HOST_HCCHAR13_LSPDDEV_CLR_MSK 0xfffdffff
54072 /* The reset value of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */
54073 #define ALT_USB_HOST_HCCHAR13_LSPDDEV_RESET 0x0
54074 /* Extracts the ALT_USB_HOST_HCCHAR13_LSPDDEV field value from a register. */
54075 #define ALT_USB_HOST_HCCHAR13_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
54076 /* Produces a ALT_USB_HOST_HCCHAR13_LSPDDEV register field value suitable for setting the register. */
54077 #define ALT_USB_HOST_HCCHAR13_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
54078 
54079 /*
54080  * Field : eptype
54081  *
54082  * Endpoint Type (EPType)
54083  *
54084  * Indicates the transfer type selected.
54085  *
54086  * 2'b00: Control
54087  *
54088  * 2'b01: Isochronous
54089  *
54090  * 2'b10: Bulk
54091  *
54092  * 2'b11: Interrupt
54093  *
54094  * Field Enumeration Values:
54095  *
54096  * Enum | Value | Description
54097  * :--------------------------------------|:------|:------------
54098  * ALT_USB_HOST_HCCHAR13_EPTYPE_E_CTL | 0x0 | Control
54099  * ALT_USB_HOST_HCCHAR13_EPTYPE_E_ISOC | 0x1 | Isochronous
54100  * ALT_USB_HOST_HCCHAR13_EPTYPE_E_BULK | 0x2 | Bulk
54101  * ALT_USB_HOST_HCCHAR13_EPTYPE_E_INTERR | 0x3 | Interrupt
54102  *
54103  * Field Access Macros:
54104  *
54105  */
54106 /*
54107  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE
54108  *
54109  * Control
54110  */
54111 #define ALT_USB_HOST_HCCHAR13_EPTYPE_E_CTL 0x0
54112 /*
54113  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE
54114  *
54115  * Isochronous
54116  */
54117 #define ALT_USB_HOST_HCCHAR13_EPTYPE_E_ISOC 0x1
54118 /*
54119  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE
54120  *
54121  * Bulk
54122  */
54123 #define ALT_USB_HOST_HCCHAR13_EPTYPE_E_BULK 0x2
54124 /*
54125  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE
54126  *
54127  * Interrupt
54128  */
54129 #define ALT_USB_HOST_HCCHAR13_EPTYPE_E_INTERR 0x3
54130 
54131 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */
54132 #define ALT_USB_HOST_HCCHAR13_EPTYPE_LSB 18
54133 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */
54134 #define ALT_USB_HOST_HCCHAR13_EPTYPE_MSB 19
54135 /* The width in bits of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */
54136 #define ALT_USB_HOST_HCCHAR13_EPTYPE_WIDTH 2
54137 /* The mask used to set the ALT_USB_HOST_HCCHAR13_EPTYPE register field value. */
54138 #define ALT_USB_HOST_HCCHAR13_EPTYPE_SET_MSK 0x000c0000
54139 /* The mask used to clear the ALT_USB_HOST_HCCHAR13_EPTYPE register field value. */
54140 #define ALT_USB_HOST_HCCHAR13_EPTYPE_CLR_MSK 0xfff3ffff
54141 /* The reset value of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */
54142 #define ALT_USB_HOST_HCCHAR13_EPTYPE_RESET 0x0
54143 /* Extracts the ALT_USB_HOST_HCCHAR13_EPTYPE field value from a register. */
54144 #define ALT_USB_HOST_HCCHAR13_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
54145 /* Produces a ALT_USB_HOST_HCCHAR13_EPTYPE register field value suitable for setting the register. */
54146 #define ALT_USB_HOST_HCCHAR13_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
54147 
54148 /*
54149  * Field : ec
54150  *
54151  * Multi Count (MC) / Error Count (EC)
54152  *
54153  * When the Split Enable bit of the Host Channel-n Split Control
54154  *
54155  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
54156  *
54157  * the host the number of transactions that must be executed per
54158  *
54159  * microframe For this periodic endpoint. For non periodic transfers,
54160  *
54161  * this field is used only in DMA mode, and specifies the number
54162  *
54163  * packets to be fetched For this channel before the internal DMA
54164  *
54165  * engine changes arbitration.
54166  *
54167  * 2'b00: Reserved This field yields undefined results.
54168  *
54169  * 2'b01: 1 transaction
54170  *
54171  * 2'b10: 2 transactions to be issued For this endpoint per
54172  *
54173  * microframe
54174  *
54175  * 2'b11: 3 transactions to be issued For this endpoint per
54176  *
54177  * microframe
54178  *
54179  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
54180  *
54181  * number of immediate retries to be performed For a periodic split
54182  *
54183  * transactions on transaction errors. This field must be Set to at
54184  *
54185  * least 2'b01.
54186  *
54187  * Field Enumeration Values:
54188  *
54189  * Enum | Value | Description
54190  * :--------------------------------------|:------|:----------------------------------------------
54191  * ALT_USB_HOST_HCCHAR13_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
54192  * ALT_USB_HOST_HCCHAR13_EC_E_TRANSONE | 0x1 | 1 transaction
54193  * ALT_USB_HOST_HCCHAR13_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
54194  * : | | per microframe
54195  * ALT_USB_HOST_HCCHAR13_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
54196  * : | | per microframe
54197  *
54198  * Field Access Macros:
54199  *
54200  */
54201 /*
54202  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC
54203  *
54204  * Reserved This field yields undefined result
54205  */
54206 #define ALT_USB_HOST_HCCHAR13_EC_E_RSVD 0x0
54207 /*
54208  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC
54209  *
54210  * 1 transaction
54211  */
54212 #define ALT_USB_HOST_HCCHAR13_EC_E_TRANSONE 0x1
54213 /*
54214  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC
54215  *
54216  * 2 transactions to be issued for this endpoint per microframe
54217  */
54218 #define ALT_USB_HOST_HCCHAR13_EC_E_TRANSTWO 0x2
54219 /*
54220  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC
54221  *
54222  * 3 transactions to be issued for this endpoint per microframe
54223  */
54224 #define ALT_USB_HOST_HCCHAR13_EC_E_TRANSTHREE 0x3
54225 
54226 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EC register field. */
54227 #define ALT_USB_HOST_HCCHAR13_EC_LSB 20
54228 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EC register field. */
54229 #define ALT_USB_HOST_HCCHAR13_EC_MSB 21
54230 /* The width in bits of the ALT_USB_HOST_HCCHAR13_EC register field. */
54231 #define ALT_USB_HOST_HCCHAR13_EC_WIDTH 2
54232 /* The mask used to set the ALT_USB_HOST_HCCHAR13_EC register field value. */
54233 #define ALT_USB_HOST_HCCHAR13_EC_SET_MSK 0x00300000
54234 /* The mask used to clear the ALT_USB_HOST_HCCHAR13_EC register field value. */
54235 #define ALT_USB_HOST_HCCHAR13_EC_CLR_MSK 0xffcfffff
54236 /* The reset value of the ALT_USB_HOST_HCCHAR13_EC register field. */
54237 #define ALT_USB_HOST_HCCHAR13_EC_RESET 0x0
54238 /* Extracts the ALT_USB_HOST_HCCHAR13_EC field value from a register. */
54239 #define ALT_USB_HOST_HCCHAR13_EC_GET(value) (((value) & 0x00300000) >> 20)
54240 /* Produces a ALT_USB_HOST_HCCHAR13_EC register field value suitable for setting the register. */
54241 #define ALT_USB_HOST_HCCHAR13_EC_SET(value) (((value) << 20) & 0x00300000)
54242 
54243 /*
54244  * Field : devaddr
54245  *
54246  * Device Address (DevAddr)
54247  *
54248  * This field selects the specific device serving as the data source
54249  *
54250  * or sink.
54251  *
54252  * Field Access Macros:
54253  *
54254  */
54255 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */
54256 #define ALT_USB_HOST_HCCHAR13_DEVADDR_LSB 22
54257 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */
54258 #define ALT_USB_HOST_HCCHAR13_DEVADDR_MSB 28
54259 /* The width in bits of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */
54260 #define ALT_USB_HOST_HCCHAR13_DEVADDR_WIDTH 7
54261 /* The mask used to set the ALT_USB_HOST_HCCHAR13_DEVADDR register field value. */
54262 #define ALT_USB_HOST_HCCHAR13_DEVADDR_SET_MSK 0x1fc00000
54263 /* The mask used to clear the ALT_USB_HOST_HCCHAR13_DEVADDR register field value. */
54264 #define ALT_USB_HOST_HCCHAR13_DEVADDR_CLR_MSK 0xe03fffff
54265 /* The reset value of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */
54266 #define ALT_USB_HOST_HCCHAR13_DEVADDR_RESET 0x0
54267 /* Extracts the ALT_USB_HOST_HCCHAR13_DEVADDR field value from a register. */
54268 #define ALT_USB_HOST_HCCHAR13_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
54269 /* Produces a ALT_USB_HOST_HCCHAR13_DEVADDR register field value suitable for setting the register. */
54270 #define ALT_USB_HOST_HCCHAR13_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
54271 
54272 /*
54273  * Field : oddfrm
54274  *
54275  * Odd Frame (OddFrm)
54276  *
54277  * This field is set (reset) by the application to indicate that the OTG host must
54278  * perform
54279  *
54280  * a transfer in an odd (micro)frame. This field is applicable for only periodic
54281  *
54282  * (isochronous and interrupt) transactions.
54283  *
54284  * 1'b0: Even (micro)frame
54285  *
54286  * 1'b1: Odd (micro)frame
54287  *
54288  * Field Access Macros:
54289  *
54290  */
54291 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_ODDFRM register field. */
54292 #define ALT_USB_HOST_HCCHAR13_ODDFRM_LSB 29
54293 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_ODDFRM register field. */
54294 #define ALT_USB_HOST_HCCHAR13_ODDFRM_MSB 29
54295 /* The width in bits of the ALT_USB_HOST_HCCHAR13_ODDFRM register field. */
54296 #define ALT_USB_HOST_HCCHAR13_ODDFRM_WIDTH 1
54297 /* The mask used to set the ALT_USB_HOST_HCCHAR13_ODDFRM register field value. */
54298 #define ALT_USB_HOST_HCCHAR13_ODDFRM_SET_MSK 0x20000000
54299 /* The mask used to clear the ALT_USB_HOST_HCCHAR13_ODDFRM register field value. */
54300 #define ALT_USB_HOST_HCCHAR13_ODDFRM_CLR_MSK 0xdfffffff
54301 /* The reset value of the ALT_USB_HOST_HCCHAR13_ODDFRM register field. */
54302 #define ALT_USB_HOST_HCCHAR13_ODDFRM_RESET 0x0
54303 /* Extracts the ALT_USB_HOST_HCCHAR13_ODDFRM field value from a register. */
54304 #define ALT_USB_HOST_HCCHAR13_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
54305 /* Produces a ALT_USB_HOST_HCCHAR13_ODDFRM register field value suitable for setting the register. */
54306 #define ALT_USB_HOST_HCCHAR13_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
54307 
54308 /*
54309  * Field : chdis
54310  *
54311  * Channel Disable (ChDis)
54312  *
54313  * The application sets this bit to stop transmitting/receiving data
54314  *
54315  * on a channel, even before the transfer For that channel is
54316  *
54317  * complete. The application must wait For the Channel Disabled
54318  *
54319  * interrupt before treating the channel as disabled.
54320  *
54321  * Field Enumeration Values:
54322  *
54323  * Enum | Value | Description
54324  * :------------------------------------|:------|:----------------------------
54325  * ALT_USB_HOST_HCCHAR13_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
54326  * ALT_USB_HOST_HCCHAR13_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
54327  *
54328  * Field Access Macros:
54329  *
54330  */
54331 /*
54332  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHDIS
54333  *
54334  * Transmit/Recieve normal
54335  */
54336 #define ALT_USB_HOST_HCCHAR13_CHDIS_E_INACT 0x0
54337 /*
54338  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHDIS
54339  *
54340  * Stop transmitting/receiving
54341  */
54342 #define ALT_USB_HOST_HCCHAR13_CHDIS_E_ACT 0x1
54343 
54344 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */
54345 #define ALT_USB_HOST_HCCHAR13_CHDIS_LSB 30
54346 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */
54347 #define ALT_USB_HOST_HCCHAR13_CHDIS_MSB 30
54348 /* The width in bits of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */
54349 #define ALT_USB_HOST_HCCHAR13_CHDIS_WIDTH 1
54350 /* The mask used to set the ALT_USB_HOST_HCCHAR13_CHDIS register field value. */
54351 #define ALT_USB_HOST_HCCHAR13_CHDIS_SET_MSK 0x40000000
54352 /* The mask used to clear the ALT_USB_HOST_HCCHAR13_CHDIS register field value. */
54353 #define ALT_USB_HOST_HCCHAR13_CHDIS_CLR_MSK 0xbfffffff
54354 /* The reset value of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */
54355 #define ALT_USB_HOST_HCCHAR13_CHDIS_RESET 0x0
54356 /* Extracts the ALT_USB_HOST_HCCHAR13_CHDIS field value from a register. */
54357 #define ALT_USB_HOST_HCCHAR13_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
54358 /* Produces a ALT_USB_HOST_HCCHAR13_CHDIS register field value suitable for setting the register. */
54359 #define ALT_USB_HOST_HCCHAR13_CHDIS_SET(value) (((value) << 30) & 0x40000000)
54360 
54361 /*
54362  * Field : chena
54363  *
54364  * Channel Enable (ChEna)
54365  *
54366  * When Scatter/Gather mode is enabled
54367  *
54368  * 1'b0: Indicates that the descriptor structure is not yet ready.
54369  *
54370  * 1'b1: Indicates that the descriptor structure and data buffer with
54371  *
54372  * data is setup and this channel can access the descriptor.
54373  *
54374  * When Scatter/Gather mode is disabled
54375  *
54376  * This field is set by the application and cleared by the OTG host.
54377  *
54378  * 1'b0: Channel disabled
54379  *
54380  * 1'b1: Channel enabled
54381  *
54382  * Field Enumeration Values:
54383  *
54384  * Enum | Value | Description
54385  * :------------------------------------|:------|:-------------------------------------------------
54386  * ALT_USB_HOST_HCCHAR13_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
54387  * : | | yet ready
54388  * ALT_USB_HOST_HCCHAR13_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
54389  * : | | data buffer with data is setup and this
54390  * : | | channel can access the descriptor
54391  *
54392  * Field Access Macros:
54393  *
54394  */
54395 /*
54396  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHENA
54397  *
54398  * Indicates that the descriptor structure is not yet ready
54399  */
54400 #define ALT_USB_HOST_HCCHAR13_CHENA_E_INACT 0x0
54401 /*
54402  * Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHENA
54403  *
54404  * Indicates that the descriptor structure and data buffer with data is
54405  * setup and this channel can access the descriptor
54406  */
54407 #define ALT_USB_HOST_HCCHAR13_CHENA_E_ACT 0x1
54408 
54409 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_CHENA register field. */
54410 #define ALT_USB_HOST_HCCHAR13_CHENA_LSB 31
54411 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_CHENA register field. */
54412 #define ALT_USB_HOST_HCCHAR13_CHENA_MSB 31
54413 /* The width in bits of the ALT_USB_HOST_HCCHAR13_CHENA register field. */
54414 #define ALT_USB_HOST_HCCHAR13_CHENA_WIDTH 1
54415 /* The mask used to set the ALT_USB_HOST_HCCHAR13_CHENA register field value. */
54416 #define ALT_USB_HOST_HCCHAR13_CHENA_SET_MSK 0x80000000
54417 /* The mask used to clear the ALT_USB_HOST_HCCHAR13_CHENA register field value. */
54418 #define ALT_USB_HOST_HCCHAR13_CHENA_CLR_MSK 0x7fffffff
54419 /* The reset value of the ALT_USB_HOST_HCCHAR13_CHENA register field. */
54420 #define ALT_USB_HOST_HCCHAR13_CHENA_RESET 0x0
54421 /* Extracts the ALT_USB_HOST_HCCHAR13_CHENA field value from a register. */
54422 #define ALT_USB_HOST_HCCHAR13_CHENA_GET(value) (((value) & 0x80000000) >> 31)
54423 /* Produces a ALT_USB_HOST_HCCHAR13_CHENA register field value suitable for setting the register. */
54424 #define ALT_USB_HOST_HCCHAR13_CHENA_SET(value) (((value) << 31) & 0x80000000)
54425 
54426 #ifndef __ASSEMBLY__
54427 /*
54428  * WARNING: The C register and register group struct declarations are provided for
54429  * convenience and illustrative purposes. They should, however, be used with
54430  * caution as the C language standard provides no guarantees about the alignment or
54431  * atomicity of device memory accesses. The recommended practice for writing
54432  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54433  * alt_write_word() functions.
54434  *
54435  * The struct declaration for register ALT_USB_HOST_HCCHAR13.
54436  */
54437 struct ALT_USB_HOST_HCCHAR13_s
54438 {
54439  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR13_MPS */
54440  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR13_EPNUM */
54441  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR13_EPDIR */
54442  uint32_t : 1; /* *UNDEFINED* */
54443  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR13_LSPDDEV */
54444  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR13_EPTYPE */
54445  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR13_EC */
54446  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR13_DEVADDR */
54447  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR13_ODDFRM */
54448  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR13_CHDIS */
54449  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR13_CHENA */
54450 };
54451 
54452 /* The typedef declaration for register ALT_USB_HOST_HCCHAR13. */
54453 typedef volatile struct ALT_USB_HOST_HCCHAR13_s ALT_USB_HOST_HCCHAR13_t;
54454 #endif /* __ASSEMBLY__ */
54455 
54456 /* The reset value of the ALT_USB_HOST_HCCHAR13 register. */
54457 #define ALT_USB_HOST_HCCHAR13_RESET 0x00000000
54458 /* The byte offset of the ALT_USB_HOST_HCCHAR13 register from the beginning of the component. */
54459 #define ALT_USB_HOST_HCCHAR13_OFST 0x2a0
54460 /* The address of the ALT_USB_HOST_HCCHAR13 register. */
54461 #define ALT_USB_HOST_HCCHAR13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR13_OFST))
54462 
54463 /*
54464  * Register : hcsplt13
54465  *
54466  * Host Channel 13 Split Control Register
54467  *
54468  * Register Layout
54469  *
54470  * Bits | Access | Reset | Description
54471  * :--------|:-------|:------|:-------------------------------
54472  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT13_PRTADDR
54473  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT13_HUBADDR
54474  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT13_XACTPOS
54475  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT13_COMPSPLT
54476  * [30:17] | ??? | 0x0 | *UNDEFINED*
54477  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT13_SPLTENA
54478  *
54479  */
54480 /*
54481  * Field : prtaddr
54482  *
54483  * Port Address (PrtAddr)
54484  *
54485  * This field is the port number of the recipient transaction
54486  *
54487  * translator.
54488  *
54489  * Field Access Macros:
54490  *
54491  */
54492 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */
54493 #define ALT_USB_HOST_HCSPLT13_PRTADDR_LSB 0
54494 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */
54495 #define ALT_USB_HOST_HCSPLT13_PRTADDR_MSB 6
54496 /* The width in bits of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */
54497 #define ALT_USB_HOST_HCSPLT13_PRTADDR_WIDTH 7
54498 /* The mask used to set the ALT_USB_HOST_HCSPLT13_PRTADDR register field value. */
54499 #define ALT_USB_HOST_HCSPLT13_PRTADDR_SET_MSK 0x0000007f
54500 /* The mask used to clear the ALT_USB_HOST_HCSPLT13_PRTADDR register field value. */
54501 #define ALT_USB_HOST_HCSPLT13_PRTADDR_CLR_MSK 0xffffff80
54502 /* The reset value of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */
54503 #define ALT_USB_HOST_HCSPLT13_PRTADDR_RESET 0x0
54504 /* Extracts the ALT_USB_HOST_HCSPLT13_PRTADDR field value from a register. */
54505 #define ALT_USB_HOST_HCSPLT13_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
54506 /* Produces a ALT_USB_HOST_HCSPLT13_PRTADDR register field value suitable for setting the register. */
54507 #define ALT_USB_HOST_HCSPLT13_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
54508 
54509 /*
54510  * Field : hubaddr
54511  *
54512  * Hub Address (HubAddr)
54513  *
54514  * This field holds the device address of the transaction translator's
54515  *
54516  * hub.
54517  *
54518  * Field Access Macros:
54519  *
54520  */
54521 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */
54522 #define ALT_USB_HOST_HCSPLT13_HUBADDR_LSB 7
54523 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */
54524 #define ALT_USB_HOST_HCSPLT13_HUBADDR_MSB 13
54525 /* The width in bits of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */
54526 #define ALT_USB_HOST_HCSPLT13_HUBADDR_WIDTH 7
54527 /* The mask used to set the ALT_USB_HOST_HCSPLT13_HUBADDR register field value. */
54528 #define ALT_USB_HOST_HCSPLT13_HUBADDR_SET_MSK 0x00003f80
54529 /* The mask used to clear the ALT_USB_HOST_HCSPLT13_HUBADDR register field value. */
54530 #define ALT_USB_HOST_HCSPLT13_HUBADDR_CLR_MSK 0xffffc07f
54531 /* The reset value of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */
54532 #define ALT_USB_HOST_HCSPLT13_HUBADDR_RESET 0x0
54533 /* Extracts the ALT_USB_HOST_HCSPLT13_HUBADDR field value from a register. */
54534 #define ALT_USB_HOST_HCSPLT13_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
54535 /* Produces a ALT_USB_HOST_HCSPLT13_HUBADDR register field value suitable for setting the register. */
54536 #define ALT_USB_HOST_HCSPLT13_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
54537 
54538 /*
54539  * Field : xactpos
54540  *
54541  * Transaction Position (XactPos)
54542  *
54543  * This field is used to determine whether to send all, first, middle,
54544  *
54545  * or last payloads with each OUT transaction.
54546  *
54547  * 2'b11: All. This is the entire data payload is of this transaction
54548  *
54549  * (which is less than or equal to 188 bytes).
54550  *
54551  * 2'b10: Begin. This is the first data payload of this transaction
54552  *
54553  * (which is larger than 188 bytes).
54554  *
54555  * 2'b00: Mid. This is the middle payload of this transaction
54556  *
54557  * (which is larger than 188 bytes).
54558  *
54559  * 2'b01: End. This is the last payload of this transaction (which
54560  *
54561  * is larger than 188 bytes).
54562  *
54563  * Field Enumeration Values:
54564  *
54565  * Enum | Value | Description
54566  * :---------------------------------------|:------|:------------------------------------------------
54567  * ALT_USB_HOST_HCSPLT13_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
54568  * : | | transaction (which is larger than 188 bytes)
54569  * ALT_USB_HOST_HCSPLT13_XACTPOS_E_END | 0x1 | End. This is the last payload of this
54570  * : | | transaction (which is larger than 188 bytes)
54571  * ALT_USB_HOST_HCSPLT13_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
54572  * : | | transaction (which is larger than 188 bytes)
54573  * ALT_USB_HOST_HCSPLT13_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
54574  * : | | transaction (which is less than or equal to 188
54575  * : | | bytes)
54576  *
54577  * Field Access Macros:
54578  *
54579  */
54580 /*
54581  * Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS
54582  *
54583  * Mid. This is the middle payload of this transaction (which is larger than 188
54584  * bytes)
54585  */
54586 #define ALT_USB_HOST_HCSPLT13_XACTPOS_E_MIDDLE 0x0
54587 /*
54588  * Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS
54589  *
54590  * End. This is the last payload of this transaction (which is larger than 188
54591  * bytes)
54592  */
54593 #define ALT_USB_HOST_HCSPLT13_XACTPOS_E_END 0x1
54594 /*
54595  * Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS
54596  *
54597  * Begin. This is the first data payload of this transaction (which is larger than
54598  * 188 bytes)
54599  */
54600 #define ALT_USB_HOST_HCSPLT13_XACTPOS_E_BEGIN 0x2
54601 /*
54602  * Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS
54603  *
54604  * All. This is the entire data payload is of this transaction (which is less than
54605  * or equal to 188 bytes)
54606  */
54607 #define ALT_USB_HOST_HCSPLT13_XACTPOS_E_ALL 0x3
54608 
54609 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */
54610 #define ALT_USB_HOST_HCSPLT13_XACTPOS_LSB 14
54611 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */
54612 #define ALT_USB_HOST_HCSPLT13_XACTPOS_MSB 15
54613 /* The width in bits of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */
54614 #define ALT_USB_HOST_HCSPLT13_XACTPOS_WIDTH 2
54615 /* The mask used to set the ALT_USB_HOST_HCSPLT13_XACTPOS register field value. */
54616 #define ALT_USB_HOST_HCSPLT13_XACTPOS_SET_MSK 0x0000c000
54617 /* The mask used to clear the ALT_USB_HOST_HCSPLT13_XACTPOS register field value. */
54618 #define ALT_USB_HOST_HCSPLT13_XACTPOS_CLR_MSK 0xffff3fff
54619 /* The reset value of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */
54620 #define ALT_USB_HOST_HCSPLT13_XACTPOS_RESET 0x0
54621 /* Extracts the ALT_USB_HOST_HCSPLT13_XACTPOS field value from a register. */
54622 #define ALT_USB_HOST_HCSPLT13_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
54623 /* Produces a ALT_USB_HOST_HCSPLT13_XACTPOS register field value suitable for setting the register. */
54624 #define ALT_USB_HOST_HCSPLT13_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
54625 
54626 /*
54627  * Field : compsplt
54628  *
54629  * Do Complete Split (CompSplt)
54630  *
54631  * The application sets this field to request the OTG host to perform
54632  *
54633  * a complete split transaction.
54634  *
54635  * Field Enumeration Values:
54636  *
54637  * Enum | Value | Description
54638  * :-----------------------------------------|:------|:---------------------
54639  * ALT_USB_HOST_HCSPLT13_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
54640  * ALT_USB_HOST_HCSPLT13_COMPSPLT_E_SPLIT | 0x1 | Split transaction
54641  *
54642  * Field Access Macros:
54643  *
54644  */
54645 /*
54646  * Enumerated value for register field ALT_USB_HOST_HCSPLT13_COMPSPLT
54647  *
54648  * No split transaction
54649  */
54650 #define ALT_USB_HOST_HCSPLT13_COMPSPLT_E_NOSPLIT 0x0
54651 /*
54652  * Enumerated value for register field ALT_USB_HOST_HCSPLT13_COMPSPLT
54653  *
54654  * Split transaction
54655  */
54656 #define ALT_USB_HOST_HCSPLT13_COMPSPLT_E_SPLIT 0x1
54657 
54658 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */
54659 #define ALT_USB_HOST_HCSPLT13_COMPSPLT_LSB 16
54660 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */
54661 #define ALT_USB_HOST_HCSPLT13_COMPSPLT_MSB 16
54662 /* The width in bits of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */
54663 #define ALT_USB_HOST_HCSPLT13_COMPSPLT_WIDTH 1
54664 /* The mask used to set the ALT_USB_HOST_HCSPLT13_COMPSPLT register field value. */
54665 #define ALT_USB_HOST_HCSPLT13_COMPSPLT_SET_MSK 0x00010000
54666 /* The mask used to clear the ALT_USB_HOST_HCSPLT13_COMPSPLT register field value. */
54667 #define ALT_USB_HOST_HCSPLT13_COMPSPLT_CLR_MSK 0xfffeffff
54668 /* The reset value of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */
54669 #define ALT_USB_HOST_HCSPLT13_COMPSPLT_RESET 0x0
54670 /* Extracts the ALT_USB_HOST_HCSPLT13_COMPSPLT field value from a register. */
54671 #define ALT_USB_HOST_HCSPLT13_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
54672 /* Produces a ALT_USB_HOST_HCSPLT13_COMPSPLT register field value suitable for setting the register. */
54673 #define ALT_USB_HOST_HCSPLT13_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
54674 
54675 /*
54676  * Field : spltena
54677  *
54678  * Split Enable (SpltEna)
54679  *
54680  * The application sets this field to indicate that this channel is
54681  *
54682  * enabled to perform split transactions.
54683  *
54684  * Field Enumeration Values:
54685  *
54686  * Enum | Value | Description
54687  * :-------------------------------------|:------|:------------------
54688  * ALT_USB_HOST_HCSPLT13_SPLTENA_E_DISD | 0x0 | Split not enabled
54689  * ALT_USB_HOST_HCSPLT13_SPLTENA_E_END | 0x1 | Split enabled
54690  *
54691  * Field Access Macros:
54692  *
54693  */
54694 /*
54695  * Enumerated value for register field ALT_USB_HOST_HCSPLT13_SPLTENA
54696  *
54697  * Split not enabled
54698  */
54699 #define ALT_USB_HOST_HCSPLT13_SPLTENA_E_DISD 0x0
54700 /*
54701  * Enumerated value for register field ALT_USB_HOST_HCSPLT13_SPLTENA
54702  *
54703  * Split enabled
54704  */
54705 #define ALT_USB_HOST_HCSPLT13_SPLTENA_E_END 0x1
54706 
54707 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */
54708 #define ALT_USB_HOST_HCSPLT13_SPLTENA_LSB 31
54709 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */
54710 #define ALT_USB_HOST_HCSPLT13_SPLTENA_MSB 31
54711 /* The width in bits of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */
54712 #define ALT_USB_HOST_HCSPLT13_SPLTENA_WIDTH 1
54713 /* The mask used to set the ALT_USB_HOST_HCSPLT13_SPLTENA register field value. */
54714 #define ALT_USB_HOST_HCSPLT13_SPLTENA_SET_MSK 0x80000000
54715 /* The mask used to clear the ALT_USB_HOST_HCSPLT13_SPLTENA register field value. */
54716 #define ALT_USB_HOST_HCSPLT13_SPLTENA_CLR_MSK 0x7fffffff
54717 /* The reset value of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */
54718 #define ALT_USB_HOST_HCSPLT13_SPLTENA_RESET 0x0
54719 /* Extracts the ALT_USB_HOST_HCSPLT13_SPLTENA field value from a register. */
54720 #define ALT_USB_HOST_HCSPLT13_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
54721 /* Produces a ALT_USB_HOST_HCSPLT13_SPLTENA register field value suitable for setting the register. */
54722 #define ALT_USB_HOST_HCSPLT13_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
54723 
54724 #ifndef __ASSEMBLY__
54725 /*
54726  * WARNING: The C register and register group struct declarations are provided for
54727  * convenience and illustrative purposes. They should, however, be used with
54728  * caution as the C language standard provides no guarantees about the alignment or
54729  * atomicity of device memory accesses. The recommended practice for writing
54730  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54731  * alt_write_word() functions.
54732  *
54733  * The struct declaration for register ALT_USB_HOST_HCSPLT13.
54734  */
54735 struct ALT_USB_HOST_HCSPLT13_s
54736 {
54737  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT13_PRTADDR */
54738  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT13_HUBADDR */
54739  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT13_XACTPOS */
54740  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT13_COMPSPLT */
54741  uint32_t : 14; /* *UNDEFINED* */
54742  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT13_SPLTENA */
54743 };
54744 
54745 /* The typedef declaration for register ALT_USB_HOST_HCSPLT13. */
54746 typedef volatile struct ALT_USB_HOST_HCSPLT13_s ALT_USB_HOST_HCSPLT13_t;
54747 #endif /* __ASSEMBLY__ */
54748 
54749 /* The reset value of the ALT_USB_HOST_HCSPLT13 register. */
54750 #define ALT_USB_HOST_HCSPLT13_RESET 0x00000000
54751 /* The byte offset of the ALT_USB_HOST_HCSPLT13 register from the beginning of the component. */
54752 #define ALT_USB_HOST_HCSPLT13_OFST 0x2a4
54753 /* The address of the ALT_USB_HOST_HCSPLT13 register. */
54754 #define ALT_USB_HOST_HCSPLT13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT13_OFST))
54755 
54756 /*
54757  * Register : hcint13
54758  *
54759  * Host Channel 13 Interrupt Register
54760  *
54761  * Register Layout
54762  *
54763  * Bits | Access | Reset | Description
54764  * :--------|:-------|:------|:---------------------------------------
54765  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT13_XFERCOMPL
54766  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT13_CHHLTD
54767  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT13_AHBERR
54768  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT13_STALL
54769  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT13_NAK
54770  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT13_ACK
54771  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT13_NYET
54772  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT13_XACTERR
54773  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT13_BBLERR
54774  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT13_FRMOVRUN
54775  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT13_DATATGLERR
54776  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT13_BNAINTR
54777  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT13_XCS_XACT_ERR
54778  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR
54779  * [31:14] | ??? | 0x0 | *UNDEFINED*
54780  *
54781  */
54782 /*
54783  * Field : xfercompl
54784  *
54785  * Transfer Completed (XferCompl)
54786  *
54787  * Transfer completed normally without any errors.This bit can be set only by the
54788  * core and the application should write 1 to clear it.
54789  *
54790  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
54791  *
54792  * completed with IOC bit set in its descriptor.
54793  *
54794  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
54795  * without
54796  *
54797  * any errors.
54798  *
54799  * Field Enumeration Values:
54800  *
54801  * Enum | Value | Description
54802  * :---------------------------------------|:------|:-----------------------------------------------
54803  * ALT_USB_HOST_HCINT13_XFERCOMPL_E_INACT | 0x0 | No transfer
54804  * ALT_USB_HOST_HCINT13_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
54805  *
54806  * Field Access Macros:
54807  *
54808  */
54809 /*
54810  * Enumerated value for register field ALT_USB_HOST_HCINT13_XFERCOMPL
54811  *
54812  * No transfer
54813  */
54814 #define ALT_USB_HOST_HCINT13_XFERCOMPL_E_INACT 0x0
54815 /*
54816  * Enumerated value for register field ALT_USB_HOST_HCINT13_XFERCOMPL
54817  *
54818  * Transfer completed normally without any errors
54819  */
54820 #define ALT_USB_HOST_HCINT13_XFERCOMPL_E_ACT 0x1
54821 
54822 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */
54823 #define ALT_USB_HOST_HCINT13_XFERCOMPL_LSB 0
54824 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */
54825 #define ALT_USB_HOST_HCINT13_XFERCOMPL_MSB 0
54826 /* The width in bits of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */
54827 #define ALT_USB_HOST_HCINT13_XFERCOMPL_WIDTH 1
54828 /* The mask used to set the ALT_USB_HOST_HCINT13_XFERCOMPL register field value. */
54829 #define ALT_USB_HOST_HCINT13_XFERCOMPL_SET_MSK 0x00000001
54830 /* The mask used to clear the ALT_USB_HOST_HCINT13_XFERCOMPL register field value. */
54831 #define ALT_USB_HOST_HCINT13_XFERCOMPL_CLR_MSK 0xfffffffe
54832 /* The reset value of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */
54833 #define ALT_USB_HOST_HCINT13_XFERCOMPL_RESET 0x0
54834 /* Extracts the ALT_USB_HOST_HCINT13_XFERCOMPL field value from a register. */
54835 #define ALT_USB_HOST_HCINT13_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
54836 /* Produces a ALT_USB_HOST_HCINT13_XFERCOMPL register field value suitable for setting the register. */
54837 #define ALT_USB_HOST_HCINT13_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
54838 
54839 /*
54840  * Field : chhltd
54841  *
54842  * Channel Halted (ChHltd)
54843  *
54844  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
54845  * either because of any USB transaction error or in response to disable request by
54846  * the application or because of a completed transfer.
54847  *
54848  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
54849  * the following
54850  *
54851  * . EOL being set in descriptor
54852  *
54853  * . AHB error
54854  *
54855  * . Excessive transaction errors
54856  *
54857  * . Babble
54858  *
54859  * . Stall
54860  *
54861  * Field Enumeration Values:
54862  *
54863  * Enum | Value | Description
54864  * :------------------------------------|:------|:-------------------
54865  * ALT_USB_HOST_HCINT13_CHHLTD_E_INACT | 0x0 | Channel not halted
54866  * ALT_USB_HOST_HCINT13_CHHLTD_E_ACT | 0x1 | Channel Halted
54867  *
54868  * Field Access Macros:
54869  *
54870  */
54871 /*
54872  * Enumerated value for register field ALT_USB_HOST_HCINT13_CHHLTD
54873  *
54874  * Channel not halted
54875  */
54876 #define ALT_USB_HOST_HCINT13_CHHLTD_E_INACT 0x0
54877 /*
54878  * Enumerated value for register field ALT_USB_HOST_HCINT13_CHHLTD
54879  *
54880  * Channel Halted
54881  */
54882 #define ALT_USB_HOST_HCINT13_CHHLTD_E_ACT 0x1
54883 
54884 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_CHHLTD register field. */
54885 #define ALT_USB_HOST_HCINT13_CHHLTD_LSB 1
54886 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_CHHLTD register field. */
54887 #define ALT_USB_HOST_HCINT13_CHHLTD_MSB 1
54888 /* The width in bits of the ALT_USB_HOST_HCINT13_CHHLTD register field. */
54889 #define ALT_USB_HOST_HCINT13_CHHLTD_WIDTH 1
54890 /* The mask used to set the ALT_USB_HOST_HCINT13_CHHLTD register field value. */
54891 #define ALT_USB_HOST_HCINT13_CHHLTD_SET_MSK 0x00000002
54892 /* The mask used to clear the ALT_USB_HOST_HCINT13_CHHLTD register field value. */
54893 #define ALT_USB_HOST_HCINT13_CHHLTD_CLR_MSK 0xfffffffd
54894 /* The reset value of the ALT_USB_HOST_HCINT13_CHHLTD register field. */
54895 #define ALT_USB_HOST_HCINT13_CHHLTD_RESET 0x0
54896 /* Extracts the ALT_USB_HOST_HCINT13_CHHLTD field value from a register. */
54897 #define ALT_USB_HOST_HCINT13_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
54898 /* Produces a ALT_USB_HOST_HCINT13_CHHLTD register field value suitable for setting the register. */
54899 #define ALT_USB_HOST_HCINT13_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
54900 
54901 /*
54902  * Field : ahberr
54903  *
54904  * AHB Error (AHBErr)
54905  *
54906  * This is generated only in Internal DMA mode when there is an
54907  *
54908  * AHB error during AHB read/write. The application can read the
54909  *
54910  * corresponding channel's DMA address register to get the error
54911  *
54912  * address.
54913  *
54914  * Field Enumeration Values:
54915  *
54916  * Enum | Value | Description
54917  * :------------------------------------|:------|:--------------------------------
54918  * ALT_USB_HOST_HCINT13_AHBERR_E_INACT | 0x0 | No AHB error
54919  * ALT_USB_HOST_HCINT13_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
54920  *
54921  * Field Access Macros:
54922  *
54923  */
54924 /*
54925  * Enumerated value for register field ALT_USB_HOST_HCINT13_AHBERR
54926  *
54927  * No AHB error
54928  */
54929 #define ALT_USB_HOST_HCINT13_AHBERR_E_INACT 0x0
54930 /*
54931  * Enumerated value for register field ALT_USB_HOST_HCINT13_AHBERR
54932  *
54933  * AHB error during AHB read/write
54934  */
54935 #define ALT_USB_HOST_HCINT13_AHBERR_E_ACT 0x1
54936 
54937 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_AHBERR register field. */
54938 #define ALT_USB_HOST_HCINT13_AHBERR_LSB 2
54939 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_AHBERR register field. */
54940 #define ALT_USB_HOST_HCINT13_AHBERR_MSB 2
54941 /* The width in bits of the ALT_USB_HOST_HCINT13_AHBERR register field. */
54942 #define ALT_USB_HOST_HCINT13_AHBERR_WIDTH 1
54943 /* The mask used to set the ALT_USB_HOST_HCINT13_AHBERR register field value. */
54944 #define ALT_USB_HOST_HCINT13_AHBERR_SET_MSK 0x00000004
54945 /* The mask used to clear the ALT_USB_HOST_HCINT13_AHBERR register field value. */
54946 #define ALT_USB_HOST_HCINT13_AHBERR_CLR_MSK 0xfffffffb
54947 /* The reset value of the ALT_USB_HOST_HCINT13_AHBERR register field. */
54948 #define ALT_USB_HOST_HCINT13_AHBERR_RESET 0x0
54949 /* Extracts the ALT_USB_HOST_HCINT13_AHBERR field value from a register. */
54950 #define ALT_USB_HOST_HCINT13_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
54951 /* Produces a ALT_USB_HOST_HCINT13_AHBERR register field value suitable for setting the register. */
54952 #define ALT_USB_HOST_HCINT13_AHBERR_SET(value) (((value) << 2) & 0x00000004)
54953 
54954 /*
54955  * Field : stall
54956  *
54957  * STALL Response Received Interrupt (STALL)
54958  *
54959  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
54960  *
54961  * in the core.This bit can be set only by the core and the application should
54962  * write 1 to clear
54963  *
54964  * it.
54965  *
54966  * Field Enumeration Values:
54967  *
54968  * Enum | Value | Description
54969  * :-----------------------------------|:------|:-------------------
54970  * ALT_USB_HOST_HCINT13_STALL_E_INACT | 0x0 | No Stall Interrupt
54971  * ALT_USB_HOST_HCINT13_STALL_E_ACT | 0x1 | Stall Interrupt
54972  *
54973  * Field Access Macros:
54974  *
54975  */
54976 /*
54977  * Enumerated value for register field ALT_USB_HOST_HCINT13_STALL
54978  *
54979  * No Stall Interrupt
54980  */
54981 #define ALT_USB_HOST_HCINT13_STALL_E_INACT 0x0
54982 /*
54983  * Enumerated value for register field ALT_USB_HOST_HCINT13_STALL
54984  *
54985  * Stall Interrupt
54986  */
54987 #define ALT_USB_HOST_HCINT13_STALL_E_ACT 0x1
54988 
54989 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_STALL register field. */
54990 #define ALT_USB_HOST_HCINT13_STALL_LSB 3
54991 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_STALL register field. */
54992 #define ALT_USB_HOST_HCINT13_STALL_MSB 3
54993 /* The width in bits of the ALT_USB_HOST_HCINT13_STALL register field. */
54994 #define ALT_USB_HOST_HCINT13_STALL_WIDTH 1
54995 /* The mask used to set the ALT_USB_HOST_HCINT13_STALL register field value. */
54996 #define ALT_USB_HOST_HCINT13_STALL_SET_MSK 0x00000008
54997 /* The mask used to clear the ALT_USB_HOST_HCINT13_STALL register field value. */
54998 #define ALT_USB_HOST_HCINT13_STALL_CLR_MSK 0xfffffff7
54999 /* The reset value of the ALT_USB_HOST_HCINT13_STALL register field. */
55000 #define ALT_USB_HOST_HCINT13_STALL_RESET 0x0
55001 /* Extracts the ALT_USB_HOST_HCINT13_STALL field value from a register. */
55002 #define ALT_USB_HOST_HCINT13_STALL_GET(value) (((value) & 0x00000008) >> 3)
55003 /* Produces a ALT_USB_HOST_HCINT13_STALL register field value suitable for setting the register. */
55004 #define ALT_USB_HOST_HCINT13_STALL_SET(value) (((value) << 3) & 0x00000008)
55005 
55006 /*
55007  * Field : nak
55008  *
55009  * NAK Response Received Interrupt (NAK)
55010  *
55011  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
55012  *
55013  * in the core.This bit can be set only by the core and the application should
55014  * write 1 to clear
55015  *
55016  * it.
55017  *
55018  * Field Enumeration Values:
55019  *
55020  * Enum | Value | Description
55021  * :---------------------------------|:------|:-----------------------------------
55022  * ALT_USB_HOST_HCINT13_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
55023  * ALT_USB_HOST_HCINT13_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
55024  *
55025  * Field Access Macros:
55026  *
55027  */
55028 /*
55029  * Enumerated value for register field ALT_USB_HOST_HCINT13_NAK
55030  *
55031  * No NAK Response Received Interrupt
55032  */
55033 #define ALT_USB_HOST_HCINT13_NAK_E_INACT 0x0
55034 /*
55035  * Enumerated value for register field ALT_USB_HOST_HCINT13_NAK
55036  *
55037  * NAK Response Received Interrupt
55038  */
55039 #define ALT_USB_HOST_HCINT13_NAK_E_ACT 0x1
55040 
55041 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_NAK register field. */
55042 #define ALT_USB_HOST_HCINT13_NAK_LSB 4
55043 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_NAK register field. */
55044 #define ALT_USB_HOST_HCINT13_NAK_MSB 4
55045 /* The width in bits of the ALT_USB_HOST_HCINT13_NAK register field. */
55046 #define ALT_USB_HOST_HCINT13_NAK_WIDTH 1
55047 /* The mask used to set the ALT_USB_HOST_HCINT13_NAK register field value. */
55048 #define ALT_USB_HOST_HCINT13_NAK_SET_MSK 0x00000010
55049 /* The mask used to clear the ALT_USB_HOST_HCINT13_NAK register field value. */
55050 #define ALT_USB_HOST_HCINT13_NAK_CLR_MSK 0xffffffef
55051 /* The reset value of the ALT_USB_HOST_HCINT13_NAK register field. */
55052 #define ALT_USB_HOST_HCINT13_NAK_RESET 0x0
55053 /* Extracts the ALT_USB_HOST_HCINT13_NAK field value from a register. */
55054 #define ALT_USB_HOST_HCINT13_NAK_GET(value) (((value) & 0x00000010) >> 4)
55055 /* Produces a ALT_USB_HOST_HCINT13_NAK register field value suitable for setting the register. */
55056 #define ALT_USB_HOST_HCINT13_NAK_SET(value) (((value) << 4) & 0x00000010)
55057 
55058 /*
55059  * Field : ack
55060  *
55061  * ACK Response Received/Transmitted Interrupt (ACK)
55062  *
55063  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
55064  *
55065  * in the core.This bit can be set only by the core and the application should
55066  * write 1 to clear
55067  *
55068  * it.
55069  *
55070  * Field Enumeration Values:
55071  *
55072  * Enum | Value | Description
55073  * :---------------------------------|:------|:-----------------------------------------------
55074  * ALT_USB_HOST_HCINT13_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
55075  * ALT_USB_HOST_HCINT13_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
55076  *
55077  * Field Access Macros:
55078  *
55079  */
55080 /*
55081  * Enumerated value for register field ALT_USB_HOST_HCINT13_ACK
55082  *
55083  * No ACK Response Received Transmitted Interrupt
55084  */
55085 #define ALT_USB_HOST_HCINT13_ACK_E_INACT 0x0
55086 /*
55087  * Enumerated value for register field ALT_USB_HOST_HCINT13_ACK
55088  *
55089  * ACK Response Received Transmitted Interrup
55090  */
55091 #define ALT_USB_HOST_HCINT13_ACK_E_ACT 0x1
55092 
55093 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_ACK register field. */
55094 #define ALT_USB_HOST_HCINT13_ACK_LSB 5
55095 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_ACK register field. */
55096 #define ALT_USB_HOST_HCINT13_ACK_MSB 5
55097 /* The width in bits of the ALT_USB_HOST_HCINT13_ACK register field. */
55098 #define ALT_USB_HOST_HCINT13_ACK_WIDTH 1
55099 /* The mask used to set the ALT_USB_HOST_HCINT13_ACK register field value. */
55100 #define ALT_USB_HOST_HCINT13_ACK_SET_MSK 0x00000020
55101 /* The mask used to clear the ALT_USB_HOST_HCINT13_ACK register field value. */
55102 #define ALT_USB_HOST_HCINT13_ACK_CLR_MSK 0xffffffdf
55103 /* The reset value of the ALT_USB_HOST_HCINT13_ACK register field. */
55104 #define ALT_USB_HOST_HCINT13_ACK_RESET 0x0
55105 /* Extracts the ALT_USB_HOST_HCINT13_ACK field value from a register. */
55106 #define ALT_USB_HOST_HCINT13_ACK_GET(value) (((value) & 0x00000020) >> 5)
55107 /* Produces a ALT_USB_HOST_HCINT13_ACK register field value suitable for setting the register. */
55108 #define ALT_USB_HOST_HCINT13_ACK_SET(value) (((value) << 5) & 0x00000020)
55109 
55110 /*
55111  * Field : nyet
55112  *
55113  * NYET Response Received Interrupt (NYET)
55114  *
55115  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
55116  *
55117  * in the core.This bit can be set only by the core and the application should
55118  * write 1 to clear
55119  *
55120  * it.
55121  *
55122  * Field Enumeration Values:
55123  *
55124  * Enum | Value | Description
55125  * :----------------------------------|:------|:------------------------------------
55126  * ALT_USB_HOST_HCINT13_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
55127  * ALT_USB_HOST_HCINT13_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
55128  *
55129  * Field Access Macros:
55130  *
55131  */
55132 /*
55133  * Enumerated value for register field ALT_USB_HOST_HCINT13_NYET
55134  *
55135  * No NYET Response Received Interrupt
55136  */
55137 #define ALT_USB_HOST_HCINT13_NYET_E_INACT 0x0
55138 /*
55139  * Enumerated value for register field ALT_USB_HOST_HCINT13_NYET
55140  *
55141  * NYET Response Received Interrupt
55142  */
55143 #define ALT_USB_HOST_HCINT13_NYET_E_ACT 0x1
55144 
55145 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_NYET register field. */
55146 #define ALT_USB_HOST_HCINT13_NYET_LSB 6
55147 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_NYET register field. */
55148 #define ALT_USB_HOST_HCINT13_NYET_MSB 6
55149 /* The width in bits of the ALT_USB_HOST_HCINT13_NYET register field. */
55150 #define ALT_USB_HOST_HCINT13_NYET_WIDTH 1
55151 /* The mask used to set the ALT_USB_HOST_HCINT13_NYET register field value. */
55152 #define ALT_USB_HOST_HCINT13_NYET_SET_MSK 0x00000040
55153 /* The mask used to clear the ALT_USB_HOST_HCINT13_NYET register field value. */
55154 #define ALT_USB_HOST_HCINT13_NYET_CLR_MSK 0xffffffbf
55155 /* The reset value of the ALT_USB_HOST_HCINT13_NYET register field. */
55156 #define ALT_USB_HOST_HCINT13_NYET_RESET 0x0
55157 /* Extracts the ALT_USB_HOST_HCINT13_NYET field value from a register. */
55158 #define ALT_USB_HOST_HCINT13_NYET_GET(value) (((value) & 0x00000040) >> 6)
55159 /* Produces a ALT_USB_HOST_HCINT13_NYET register field value suitable for setting the register. */
55160 #define ALT_USB_HOST_HCINT13_NYET_SET(value) (((value) << 6) & 0x00000040)
55161 
55162 /*
55163  * Field : xacterr
55164  *
55165  * Transaction Error (XactErr)
55166  *
55167  * Indicates one of the following errors occurred on the USB.
55168  *
55169  * CRC check failure
55170  *
55171  * Timeout
55172  *
55173  * Bit stuff error
55174  *
55175  * False EOP
55176  *
55177  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
55178  *
55179  * in the core.This bit can be set only by the core and the application should
55180  * write 1 to clear
55181  *
55182  * it.
55183  *
55184  * Field Enumeration Values:
55185  *
55186  * Enum | Value | Description
55187  * :-------------------------------------|:------|:---------------------
55188  * ALT_USB_HOST_HCINT13_XACTERR_E_INACT | 0x0 | No Transaction Error
55189  * ALT_USB_HOST_HCINT13_XACTERR_E_ACT | 0x1 | Transaction Error
55190  *
55191  * Field Access Macros:
55192  *
55193  */
55194 /*
55195  * Enumerated value for register field ALT_USB_HOST_HCINT13_XACTERR
55196  *
55197  * No Transaction Error
55198  */
55199 #define ALT_USB_HOST_HCINT13_XACTERR_E_INACT 0x0
55200 /*
55201  * Enumerated value for register field ALT_USB_HOST_HCINT13_XACTERR
55202  *
55203  * Transaction Error
55204  */
55205 #define ALT_USB_HOST_HCINT13_XACTERR_E_ACT 0x1
55206 
55207 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_XACTERR register field. */
55208 #define ALT_USB_HOST_HCINT13_XACTERR_LSB 7
55209 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_XACTERR register field. */
55210 #define ALT_USB_HOST_HCINT13_XACTERR_MSB 7
55211 /* The width in bits of the ALT_USB_HOST_HCINT13_XACTERR register field. */
55212 #define ALT_USB_HOST_HCINT13_XACTERR_WIDTH 1
55213 /* The mask used to set the ALT_USB_HOST_HCINT13_XACTERR register field value. */
55214 #define ALT_USB_HOST_HCINT13_XACTERR_SET_MSK 0x00000080
55215 /* The mask used to clear the ALT_USB_HOST_HCINT13_XACTERR register field value. */
55216 #define ALT_USB_HOST_HCINT13_XACTERR_CLR_MSK 0xffffff7f
55217 /* The reset value of the ALT_USB_HOST_HCINT13_XACTERR register field. */
55218 #define ALT_USB_HOST_HCINT13_XACTERR_RESET 0x0
55219 /* Extracts the ALT_USB_HOST_HCINT13_XACTERR field value from a register. */
55220 #define ALT_USB_HOST_HCINT13_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
55221 /* Produces a ALT_USB_HOST_HCINT13_XACTERR register field value suitable for setting the register. */
55222 #define ALT_USB_HOST_HCINT13_XACTERR_SET(value) (((value) << 7) & 0x00000080)
55223 
55224 /*
55225  * Field : bblerr
55226  *
55227  * Babble Error (BblErr)
55228  *
55229  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
55230  *
55231  * in the core..This bit can be set only by the core and the application should
55232  * write 1 to clear
55233  *
55234  * it.
55235  *
55236  * Field Enumeration Values:
55237  *
55238  * Enum | Value | Description
55239  * :------------------------------------|:------|:----------------
55240  * ALT_USB_HOST_HCINT13_BBLERR_E_INACT | 0x0 | No Babble Error
55241  * ALT_USB_HOST_HCINT13_BBLERR_E_ACT | 0x1 | Babble Error
55242  *
55243  * Field Access Macros:
55244  *
55245  */
55246 /*
55247  * Enumerated value for register field ALT_USB_HOST_HCINT13_BBLERR
55248  *
55249  * No Babble Error
55250  */
55251 #define ALT_USB_HOST_HCINT13_BBLERR_E_INACT 0x0
55252 /*
55253  * Enumerated value for register field ALT_USB_HOST_HCINT13_BBLERR
55254  *
55255  * Babble Error
55256  */
55257 #define ALT_USB_HOST_HCINT13_BBLERR_E_ACT 0x1
55258 
55259 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_BBLERR register field. */
55260 #define ALT_USB_HOST_HCINT13_BBLERR_LSB 8
55261 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_BBLERR register field. */
55262 #define ALT_USB_HOST_HCINT13_BBLERR_MSB 8
55263 /* The width in bits of the ALT_USB_HOST_HCINT13_BBLERR register field. */
55264 #define ALT_USB_HOST_HCINT13_BBLERR_WIDTH 1
55265 /* The mask used to set the ALT_USB_HOST_HCINT13_BBLERR register field value. */
55266 #define ALT_USB_HOST_HCINT13_BBLERR_SET_MSK 0x00000100
55267 /* The mask used to clear the ALT_USB_HOST_HCINT13_BBLERR register field value. */
55268 #define ALT_USB_HOST_HCINT13_BBLERR_CLR_MSK 0xfffffeff
55269 /* The reset value of the ALT_USB_HOST_HCINT13_BBLERR register field. */
55270 #define ALT_USB_HOST_HCINT13_BBLERR_RESET 0x0
55271 /* Extracts the ALT_USB_HOST_HCINT13_BBLERR field value from a register. */
55272 #define ALT_USB_HOST_HCINT13_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
55273 /* Produces a ALT_USB_HOST_HCINT13_BBLERR register field value suitable for setting the register. */
55274 #define ALT_USB_HOST_HCINT13_BBLERR_SET(value) (((value) << 8) & 0x00000100)
55275 
55276 /*
55277  * Field : frmovrun
55278  *
55279  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
55280  * bit is masked
55281  *
55282  * in the core.This bit can be set only by the core and the application should
55283  * write 1 to clear
55284  *
55285  * it.
55286  *
55287  * Field Enumeration Values:
55288  *
55289  * Enum | Value | Description
55290  * :--------------------------------------|:------|:-----------------
55291  * ALT_USB_HOST_HCINT13_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
55292  * ALT_USB_HOST_HCINT13_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
55293  *
55294  * Field Access Macros:
55295  *
55296  */
55297 /*
55298  * Enumerated value for register field ALT_USB_HOST_HCINT13_FRMOVRUN
55299  *
55300  * No Frame Overrun
55301  */
55302 #define ALT_USB_HOST_HCINT13_FRMOVRUN_E_INACT 0x0
55303 /*
55304  * Enumerated value for register field ALT_USB_HOST_HCINT13_FRMOVRUN
55305  *
55306  * Frame Overrun
55307  */
55308 #define ALT_USB_HOST_HCINT13_FRMOVRUN_E_ACT 0x1
55309 
55310 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */
55311 #define ALT_USB_HOST_HCINT13_FRMOVRUN_LSB 9
55312 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */
55313 #define ALT_USB_HOST_HCINT13_FRMOVRUN_MSB 9
55314 /* The width in bits of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */
55315 #define ALT_USB_HOST_HCINT13_FRMOVRUN_WIDTH 1
55316 /* The mask used to set the ALT_USB_HOST_HCINT13_FRMOVRUN register field value. */
55317 #define ALT_USB_HOST_HCINT13_FRMOVRUN_SET_MSK 0x00000200
55318 /* The mask used to clear the ALT_USB_HOST_HCINT13_FRMOVRUN register field value. */
55319 #define ALT_USB_HOST_HCINT13_FRMOVRUN_CLR_MSK 0xfffffdff
55320 /* The reset value of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */
55321 #define ALT_USB_HOST_HCINT13_FRMOVRUN_RESET 0x0
55322 /* Extracts the ALT_USB_HOST_HCINT13_FRMOVRUN field value from a register. */
55323 #define ALT_USB_HOST_HCINT13_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
55324 /* Produces a ALT_USB_HOST_HCINT13_FRMOVRUN register field value suitable for setting the register. */
55325 #define ALT_USB_HOST_HCINT13_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
55326 
55327 /*
55328  * Field : datatglerr
55329  *
55330  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
55331  * application should write 1 to clear
55332  *
55333  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
55334  *
55335  * in the core.
55336  *
55337  * Field Enumeration Values:
55338  *
55339  * Enum | Value | Description
55340  * :----------------------------------------|:------|:---------------------
55341  * ALT_USB_HOST_HCINT13_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
55342  * ALT_USB_HOST_HCINT13_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
55343  *
55344  * Field Access Macros:
55345  *
55346  */
55347 /*
55348  * Enumerated value for register field ALT_USB_HOST_HCINT13_DATATGLERR
55349  *
55350  * No Data Toggle Error
55351  */
55352 #define ALT_USB_HOST_HCINT13_DATATGLERR_E_INACT 0x0
55353 /*
55354  * Enumerated value for register field ALT_USB_HOST_HCINT13_DATATGLERR
55355  *
55356  * Data Toggle Error
55357  */
55358 #define ALT_USB_HOST_HCINT13_DATATGLERR_E_ACT 0x1
55359 
55360 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */
55361 #define ALT_USB_HOST_HCINT13_DATATGLERR_LSB 10
55362 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */
55363 #define ALT_USB_HOST_HCINT13_DATATGLERR_MSB 10
55364 /* The width in bits of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */
55365 #define ALT_USB_HOST_HCINT13_DATATGLERR_WIDTH 1
55366 /* The mask used to set the ALT_USB_HOST_HCINT13_DATATGLERR register field value. */
55367 #define ALT_USB_HOST_HCINT13_DATATGLERR_SET_MSK 0x00000400
55368 /* The mask used to clear the ALT_USB_HOST_HCINT13_DATATGLERR register field value. */
55369 #define ALT_USB_HOST_HCINT13_DATATGLERR_CLR_MSK 0xfffffbff
55370 /* The reset value of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */
55371 #define ALT_USB_HOST_HCINT13_DATATGLERR_RESET 0x0
55372 /* Extracts the ALT_USB_HOST_HCINT13_DATATGLERR field value from a register. */
55373 #define ALT_USB_HOST_HCINT13_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
55374 /* Produces a ALT_USB_HOST_HCINT13_DATATGLERR register field value suitable for setting the register. */
55375 #define ALT_USB_HOST_HCINT13_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
55376 
55377 /*
55378  * Field : bnaintr
55379  *
55380  * BNA (Buffer Not Available) Interrupt (BNAIntr)
55381  *
55382  * This bit is valid only when Scatter/Gather DMA mode is enabled.
55383  *
55384  * The core generates this interrupt when the descriptor accessed
55385  *
55386  * is not ready for the Core to process. BNA will not be generated
55387  *
55388  * for Isochronous channels.
55389  *
55390  * For non Scatter/Gather DMA mode, this bit is reserved.
55391  *
55392  * Field Enumeration Values:
55393  *
55394  * Enum | Value | Description
55395  * :-------------------------------------|:------|:-----------------
55396  * ALT_USB_HOST_HCINT13_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
55397  * ALT_USB_HOST_HCINT13_BNAINTR_E_ACT | 0x1 | BNA Interrupt
55398  *
55399  * Field Access Macros:
55400  *
55401  */
55402 /*
55403  * Enumerated value for register field ALT_USB_HOST_HCINT13_BNAINTR
55404  *
55405  * No BNA Interrupt
55406  */
55407 #define ALT_USB_HOST_HCINT13_BNAINTR_E_INACT 0x0
55408 /*
55409  * Enumerated value for register field ALT_USB_HOST_HCINT13_BNAINTR
55410  *
55411  * BNA Interrupt
55412  */
55413 #define ALT_USB_HOST_HCINT13_BNAINTR_E_ACT 0x1
55414 
55415 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_BNAINTR register field. */
55416 #define ALT_USB_HOST_HCINT13_BNAINTR_LSB 11
55417 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_BNAINTR register field. */
55418 #define ALT_USB_HOST_HCINT13_BNAINTR_MSB 11
55419 /* The width in bits of the ALT_USB_HOST_HCINT13_BNAINTR register field. */
55420 #define ALT_USB_HOST_HCINT13_BNAINTR_WIDTH 1
55421 /* The mask used to set the ALT_USB_HOST_HCINT13_BNAINTR register field value. */
55422 #define ALT_USB_HOST_HCINT13_BNAINTR_SET_MSK 0x00000800
55423 /* The mask used to clear the ALT_USB_HOST_HCINT13_BNAINTR register field value. */
55424 #define ALT_USB_HOST_HCINT13_BNAINTR_CLR_MSK 0xfffff7ff
55425 /* The reset value of the ALT_USB_HOST_HCINT13_BNAINTR register field. */
55426 #define ALT_USB_HOST_HCINT13_BNAINTR_RESET 0x0
55427 /* Extracts the ALT_USB_HOST_HCINT13_BNAINTR field value from a register. */
55428 #define ALT_USB_HOST_HCINT13_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
55429 /* Produces a ALT_USB_HOST_HCINT13_BNAINTR register field value suitable for setting the register. */
55430 #define ALT_USB_HOST_HCINT13_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
55431 
55432 /*
55433  * Field : xcs_xact_err
55434  *
55435  * Excessive Transaction Error (XCS_XACT_ERR)
55436  *
55437  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
55438  * this bit
55439  *
55440  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
55441  *
55442  * not be generated for Isochronous channels.
55443  *
55444  * For non Scatter/Gather DMA mode, this bit is reserved.
55445  *
55446  * Field Enumeration Values:
55447  *
55448  * Enum | Value | Description
55449  * :--------------------------------------------|:------|:-------------------------------
55450  * ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
55451  * ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
55452  *
55453  * Field Access Macros:
55454  *
55455  */
55456 /*
55457  * Enumerated value for register field ALT_USB_HOST_HCINT13_XCS_XACT_ERR
55458  *
55459  * No Excessive Transaction Error
55460  */
55461 #define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_INACT 0x0
55462 /*
55463  * Enumerated value for register field ALT_USB_HOST_HCINT13_XCS_XACT_ERR
55464  *
55465  * Excessive Transaction Error
55466  */
55467 #define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_ACVTIVE 0x1
55468 
55469 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */
55470 #define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_LSB 12
55471 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */
55472 #define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_MSB 12
55473 /* The width in bits of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */
55474 #define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_WIDTH 1
55475 /* The mask used to set the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field value. */
55476 #define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_SET_MSK 0x00001000
55477 /* The mask used to clear the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field value. */
55478 #define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_CLR_MSK 0xffffefff
55479 /* The reset value of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */
55480 #define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_RESET 0x0
55481 /* Extracts the ALT_USB_HOST_HCINT13_XCS_XACT_ERR field value from a register. */
55482 #define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
55483 /* Produces a ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field value suitable for setting the register. */
55484 #define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
55485 
55486 /*
55487  * Field : desc_lst_rollintr
55488  *
55489  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
55490  *
55491  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
55492  * this bit
55493  *
55494  * when the corresponding channel's descriptor list rolls over.
55495  *
55496  * For non Scatter/Gather DMA mode, this bit is reserved.
55497  *
55498  * Field Enumeration Values:
55499  *
55500  * Enum | Value | Description
55501  * :-----------------------------------------------|:------|:---------------------------------
55502  * ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
55503  * ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
55504  *
55505  * Field Access Macros:
55506  *
55507  */
55508 /*
55509  * Enumerated value for register field ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR
55510  *
55511  * No Descriptor rollover interrupt
55512  */
55513 #define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_INACT 0x0
55514 /*
55515  * Enumerated value for register field ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR
55516  *
55517  * Descriptor rollover interrupt
55518  */
55519 #define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_ACT 0x1
55520 
55521 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */
55522 #define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_LSB 13
55523 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */
55524 #define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_MSB 13
55525 /* The width in bits of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */
55526 #define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_WIDTH 1
55527 /* The mask used to set the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field value. */
55528 #define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_SET_MSK 0x00002000
55529 /* The mask used to clear the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field value. */
55530 #define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
55531 /* The reset value of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */
55532 #define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_RESET 0x0
55533 /* Extracts the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR field value from a register. */
55534 #define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
55535 /* Produces a ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field value suitable for setting the register. */
55536 #define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
55537 
55538 #ifndef __ASSEMBLY__
55539 /*
55540  * WARNING: The C register and register group struct declarations are provided for
55541  * convenience and illustrative purposes. They should, however, be used with
55542  * caution as the C language standard provides no guarantees about the alignment or
55543  * atomicity of device memory accesses. The recommended practice for writing
55544  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
55545  * alt_write_word() functions.
55546  *
55547  * The struct declaration for register ALT_USB_HOST_HCINT13.
55548  */
55549 struct ALT_USB_HOST_HCINT13_s
55550 {
55551  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT13_XFERCOMPL */
55552  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT13_CHHLTD */
55553  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT13_AHBERR */
55554  uint32_t stall : 1; /* ALT_USB_HOST_HCINT13_STALL */
55555  uint32_t nak : 1; /* ALT_USB_HOST_HCINT13_NAK */
55556  uint32_t ack : 1; /* ALT_USB_HOST_HCINT13_ACK */
55557  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT13_NYET */
55558  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT13_XACTERR */
55559  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT13_BBLERR */
55560  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT13_FRMOVRUN */
55561  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT13_DATATGLERR */
55562  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT13_BNAINTR */
55563  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT13_XCS_XACT_ERR */
55564  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR */
55565  uint32_t : 18; /* *UNDEFINED* */
55566 };
55567 
55568 /* The typedef declaration for register ALT_USB_HOST_HCINT13. */
55569 typedef volatile struct ALT_USB_HOST_HCINT13_s ALT_USB_HOST_HCINT13_t;
55570 #endif /* __ASSEMBLY__ */
55571 
55572 /* The reset value of the ALT_USB_HOST_HCINT13 register. */
55573 #define ALT_USB_HOST_HCINT13_RESET 0x00000000
55574 /* The byte offset of the ALT_USB_HOST_HCINT13 register from the beginning of the component. */
55575 #define ALT_USB_HOST_HCINT13_OFST 0x2a8
55576 /* The address of the ALT_USB_HOST_HCINT13 register. */
55577 #define ALT_USB_HOST_HCINT13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT13_OFST))
55578 
55579 /*
55580  * Register : hcintmsk13
55581  *
55582  * Host Channel 13 Interrupt Mask Register
55583  *
55584  * Register Layout
55585  *
55586  * Bits | Access | Reset | Description
55587  * :--------|:-------|:------|:--------------------------------------------
55588  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK
55589  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_CHHLTDMSK
55590  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_AHBERRMSK
55591  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_STALLMSK
55592  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_NAKMSK
55593  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_ACKMSK
55594  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_NYETMSK
55595  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_XACTERRMSK
55596  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_BBLERRMSK
55597  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK
55598  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK
55599  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_BNAINTRMSK
55600  * [12] | ??? | 0x0 | *UNDEFINED*
55601  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK
55602  * [31:14] | ??? | 0x0 | *UNDEFINED*
55603  *
55604  */
55605 /*
55606  * Field : xfercomplmsk
55607  *
55608  * Transfer Completed Mask (XferComplMsk)
55609  *
55610  * Field Enumeration Values:
55611  *
55612  * Enum | Value | Description
55613  * :---------------------------------------------|:------|:------------
55614  * ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_MSK | 0x0 | Mask
55615  * ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
55616  *
55617  * Field Access Macros:
55618  *
55619  */
55620 /*
55621  * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK
55622  *
55623  * Mask
55624  */
55625 #define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_MSK 0x0
55626 /*
55627  * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK
55628  *
55629  * No mask
55630  */
55631 #define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_NOMSK 0x1
55632 
55633 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */
55634 #define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_LSB 0
55635 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */
55636 #define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_MSB 0
55637 /* The width in bits of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */
55638 #define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_WIDTH 1
55639 /* The mask used to set the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field value. */
55640 #define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_SET_MSK 0x00000001
55641 /* The mask used to clear the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field value. */
55642 #define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_CLR_MSK 0xfffffffe
55643 /* The reset value of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */
55644 #define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_RESET 0x0
55645 /* Extracts the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK field value from a register. */
55646 #define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
55647 /* Produces a ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field value suitable for setting the register. */
55648 #define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
55649 
55650 /*
55651  * Field : chhltdmsk
55652  *
55653  * Channel Halted Mask (ChHltdMsk)
55654  *
55655  * Field Enumeration Values:
55656  *
55657  * Enum | Value | Description
55658  * :------------------------------------------|:------|:------------
55659  * ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_MSK | 0x0 | Mask
55660  * ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_NOMSK | 0x1 | No mask
55661  *
55662  * Field Access Macros:
55663  *
55664  */
55665 /*
55666  * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_CHHLTDMSK
55667  *
55668  * Mask
55669  */
55670 #define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_MSK 0x0
55671 /*
55672  * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_CHHLTDMSK
55673  *
55674  * No mask
55675  */
55676 #define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_NOMSK 0x1
55677 
55678 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */
55679 #define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_LSB 1
55680 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */
55681 #define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_MSB 1
55682 /* The width in bits of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */
55683 #define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_WIDTH 1
55684 /* The mask used to set the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field value. */
55685 #define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_SET_MSK 0x00000002
55686 /* The mask used to clear the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field value. */
55687 #define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_CLR_MSK 0xfffffffd
55688 /* The reset value of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */
55689 #define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_RESET 0x0
55690 /* Extracts the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK field value from a register. */
55691 #define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
55692 /* Produces a ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field value suitable for setting the register. */
55693 #define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
55694 
55695 /*
55696  * Field : ahberrmsk
55697  *
55698  * AHB Error Mask (AHBErrMsk)
55699  *
55700  * In scatter/gather DMA mode for host,
55701  *
55702  * interrupts will not be generated due to the corresponding bits set in
55703  *
55704  * HCINTn.
55705  *
55706  * Field Enumeration Values:
55707  *
55708  * Enum | Value | Description
55709  * :------------------------------------------|:------|:------------
55710  * ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_MSK | 0x0 | Mask
55711  * ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_NOMSK | 0x1 | No mask
55712  *
55713  * Field Access Macros:
55714  *
55715  */
55716 /*
55717  * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_AHBERRMSK
55718  *
55719  * Mask
55720  */
55721 #define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_MSK 0x0
55722 /*
55723  * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_AHBERRMSK
55724  *
55725  * No mask
55726  */
55727 #define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_NOMSK 0x1
55728 
55729 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */
55730 #define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_LSB 2
55731 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */
55732 #define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_MSB 2
55733 /* The width in bits of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */
55734 #define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_WIDTH 1
55735 /* The mask used to set the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field value. */
55736 #define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_SET_MSK 0x00000004
55737 /* The mask used to clear the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field value. */
55738 #define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_CLR_MSK 0xfffffffb
55739 /* The reset value of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */
55740 #define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_RESET 0x0
55741 /* Extracts the ALT_USB_HOST_HCINTMSK13_AHBERRMSK field value from a register. */
55742 #define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
55743 /* Produces a ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field value suitable for setting the register. */
55744 #define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
55745 
55746 /*
55747  * Field : stallmsk
55748  *
55749  * STALL Response Received Interrupt Mask (StallMsk)
55750  *
55751  * In scatter/gather DMA mode for host,
55752  *
55753  * interrupts will not be generated due to the corresponding bits set in
55754  *
55755  * HCINTn.
55756  *
55757  * Field Access Macros:
55758  *
55759  */
55760 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_STALLMSK register field. */
55761 #define ALT_USB_HOST_HCINTMSK13_STALLMSK_LSB 3
55762 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_STALLMSK register field. */
55763 #define ALT_USB_HOST_HCINTMSK13_STALLMSK_MSB 3
55764 /* The width in bits of the ALT_USB_HOST_HCINTMSK13_STALLMSK register field. */
55765 #define ALT_USB_HOST_HCINTMSK13_STALLMSK_WIDTH 1
55766 /* The mask used to set the ALT_USB_HOST_HCINTMSK13_STALLMSK register field value. */
55767 #define ALT_USB_HOST_HCINTMSK13_STALLMSK_SET_MSK 0x00000008
55768 /* The mask used to clear the ALT_USB_HOST_HCINTMSK13_STALLMSK register field value. */
55769 #define ALT_USB_HOST_HCINTMSK13_STALLMSK_CLR_MSK 0xfffffff7
55770 /* The reset value of the ALT_USB_HOST_HCINTMSK13_STALLMSK register field. */
55771 #define ALT_USB_HOST_HCINTMSK13_STALLMSK_RESET 0x0
55772 /* Extracts the ALT_USB_HOST_HCINTMSK13_STALLMSK field value from a register. */
55773 #define ALT_USB_HOST_HCINTMSK13_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
55774 /* Produces a ALT_USB_HOST_HCINTMSK13_STALLMSK register field value suitable for setting the register. */
55775 #define ALT_USB_HOST_HCINTMSK13_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
55776 
55777 /*
55778  * Field : nakmsk
55779  *
55780  * NAK Response Received Interrupt Mask (NakMsk)
55781  *
55782  * In scatter/gather DMA mode for host,
55783  *
55784  * interrupts will not be generated due to the corresponding bits set in
55785  *
55786  * HCINTn.
55787  *
55788  * Field Access Macros:
55789  *
55790  */
55791 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_NAKMSK register field. */
55792 #define ALT_USB_HOST_HCINTMSK13_NAKMSK_LSB 4
55793 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_NAKMSK register field. */
55794 #define ALT_USB_HOST_HCINTMSK13_NAKMSK_MSB 4
55795 /* The width in bits of the ALT_USB_HOST_HCINTMSK13_NAKMSK register field. */
55796 #define ALT_USB_HOST_HCINTMSK13_NAKMSK_WIDTH 1
55797 /* The mask used to set the ALT_USB_HOST_HCINTMSK13_NAKMSK register field value. */
55798 #define ALT_USB_HOST_HCINTMSK13_NAKMSK_SET_MSK 0x00000010
55799 /* The mask used to clear the ALT_USB_HOST_HCINTMSK13_NAKMSK register field value. */
55800 #define ALT_USB_HOST_HCINTMSK13_NAKMSK_CLR_MSK 0xffffffef
55801 /* The reset value of the ALT_USB_HOST_HCINTMSK13_NAKMSK register field. */
55802 #define ALT_USB_HOST_HCINTMSK13_NAKMSK_RESET 0x0
55803 /* Extracts the ALT_USB_HOST_HCINTMSK13_NAKMSK field value from a register. */
55804 #define ALT_USB_HOST_HCINTMSK13_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
55805 /* Produces a ALT_USB_HOST_HCINTMSK13_NAKMSK register field value suitable for setting the register. */
55806 #define ALT_USB_HOST_HCINTMSK13_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
55807 
55808 /*
55809  * Field : ackmsk
55810  *
55811  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
55812  *
55813  * In scatter/gather DMA mode for host,
55814  *
55815  * interrupts will not be generated due to the corresponding bits set in
55816  *
55817  * HCINTn.
55818  *
55819  * Field Access Macros:
55820  *
55821  */
55822 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_ACKMSK register field. */
55823 #define ALT_USB_HOST_HCINTMSK13_ACKMSK_LSB 5
55824 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_ACKMSK register field. */
55825 #define ALT_USB_HOST_HCINTMSK13_ACKMSK_MSB 5
55826 /* The width in bits of the ALT_USB_HOST_HCINTMSK13_ACKMSK register field. */
55827 #define ALT_USB_HOST_HCINTMSK13_ACKMSK_WIDTH 1
55828 /* The mask used to set the ALT_USB_HOST_HCINTMSK13_ACKMSK register field value. */
55829 #define ALT_USB_HOST_HCINTMSK13_ACKMSK_SET_MSK 0x00000020
55830 /* The mask used to clear the ALT_USB_HOST_HCINTMSK13_ACKMSK register field value. */
55831 #define ALT_USB_HOST_HCINTMSK13_ACKMSK_CLR_MSK 0xffffffdf
55832 /* The reset value of the ALT_USB_HOST_HCINTMSK13_ACKMSK register field. */
55833 #define ALT_USB_HOST_HCINTMSK13_ACKMSK_RESET 0x0
55834 /* Extracts the ALT_USB_HOST_HCINTMSK13_ACKMSK field value from a register. */
55835 #define ALT_USB_HOST_HCINTMSK13_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
55836 /* Produces a ALT_USB_HOST_HCINTMSK13_ACKMSK register field value suitable for setting the register. */
55837 #define ALT_USB_HOST_HCINTMSK13_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
55838 
55839 /*
55840  * Field : nyetmsk
55841  *
55842  * NYET Response Received Interrupt Mask (NyetMsk)
55843  *
55844  * In scatter/gather DMA mode for host,
55845  *
55846  * interrupts will not be generated due to the corresponding bits set in
55847  *
55848  * HCINTn.
55849  *
55850  * Field Access Macros:
55851  *
55852  */
55853 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_NYETMSK register field. */
55854 #define ALT_USB_HOST_HCINTMSK13_NYETMSK_LSB 6
55855 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_NYETMSK register field. */
55856 #define ALT_USB_HOST_HCINTMSK13_NYETMSK_MSB 6
55857 /* The width in bits of the ALT_USB_HOST_HCINTMSK13_NYETMSK register field. */
55858 #define ALT_USB_HOST_HCINTMSK13_NYETMSK_WIDTH 1
55859 /* The mask used to set the ALT_USB_HOST_HCINTMSK13_NYETMSK register field value. */
55860 #define ALT_USB_HOST_HCINTMSK13_NYETMSK_SET_MSK 0x00000040
55861 /* The mask used to clear the ALT_USB_HOST_HCINTMSK13_NYETMSK register field value. */
55862 #define ALT_USB_HOST_HCINTMSK13_NYETMSK_CLR_MSK 0xffffffbf
55863 /* The reset value of the ALT_USB_HOST_HCINTMSK13_NYETMSK register field. */
55864 #define ALT_USB_HOST_HCINTMSK13_NYETMSK_RESET 0x0
55865 /* Extracts the ALT_USB_HOST_HCINTMSK13_NYETMSK field value from a register. */
55866 #define ALT_USB_HOST_HCINTMSK13_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
55867 /* Produces a ALT_USB_HOST_HCINTMSK13_NYETMSK register field value suitable for setting the register. */
55868 #define ALT_USB_HOST_HCINTMSK13_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
55869 
55870 /*
55871  * Field : xacterrmsk
55872  *
55873  * Transaction Error Mask (XactErrMsk)
55874  *
55875  * In scatter/gather DMA mode for host,
55876  *
55877  * interrupts will not be generated due to the corresponding bits set in
55878  *
55879  * HCINTn.
55880  *
55881  * Field Access Macros:
55882  *
55883  */
55884 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field. */
55885 #define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_LSB 7
55886 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field. */
55887 #define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_MSB 7
55888 /* The width in bits of the ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field. */
55889 #define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_WIDTH 1
55890 /* The mask used to set the ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field value. */
55891 #define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_SET_MSK 0x00000080
55892 /* The mask used to clear the ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field value. */
55893 #define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_CLR_MSK 0xffffff7f
55894 /* The reset value of the ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field. */
55895 #define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_RESET 0x0
55896 /* Extracts the ALT_USB_HOST_HCINTMSK13_XACTERRMSK field value from a register. */
55897 #define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
55898 /* Produces a ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field value suitable for setting the register. */
55899 #define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
55900 
55901 /*
55902  * Field : bblerrmsk
55903  *
55904  * Babble Error Mask (BblErrMsk)
55905  *
55906  * In scatter/gather DMA mode for host,
55907  *
55908  * interrupts will not be generated due to the corresponding bits set in
55909  *
55910  * HCINTn.
55911  *
55912  * Field Access Macros:
55913  *
55914  */
55915 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field. */
55916 #define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_LSB 8
55917 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field. */
55918 #define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_MSB 8
55919 /* The width in bits of the ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field. */
55920 #define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_WIDTH 1
55921 /* The mask used to set the ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field value. */
55922 #define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_SET_MSK 0x00000100
55923 /* The mask used to clear the ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field value. */
55924 #define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_CLR_MSK 0xfffffeff
55925 /* The reset value of the ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field. */
55926 #define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_RESET 0x0
55927 /* Extracts the ALT_USB_HOST_HCINTMSK13_BBLERRMSK field value from a register. */
55928 #define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
55929 /* Produces a ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field value suitable for setting the register. */
55930 #define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
55931 
55932 /*
55933  * Field : frmovrunmsk
55934  *
55935  * Frame Overrun Mask (FrmOvrunMsk)
55936  *
55937  * In scatter/gather DMA mode for host,
55938  *
55939  * interrupts will not be generated due to the corresponding bits set in
55940  *
55941  * HCINTn.
55942  *
55943  * Field Access Macros:
55944  *
55945  */
55946 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field. */
55947 #define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_LSB 9
55948 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field. */
55949 #define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_MSB 9
55950 /* The width in bits of the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field. */
55951 #define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_WIDTH 1
55952 /* The mask used to set the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field value. */
55953 #define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_SET_MSK 0x00000200
55954 /* The mask used to clear the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field value. */
55955 #define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_CLR_MSK 0xfffffdff
55956 /* The reset value of the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field. */
55957 #define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_RESET 0x0
55958 /* Extracts the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK field value from a register. */
55959 #define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
55960 /* Produces a ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field value suitable for setting the register. */
55961 #define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
55962 
55963 /*
55964  * Field : datatglerrmsk
55965  *
55966  * Data Toggle Error Mask (DataTglErrMsk)
55967  *
55968  * In scatter/gather DMA mode for host,
55969  *
55970  * interrupts will not be generated due to the corresponding bits set in
55971  *
55972  * HCINTn.
55973  *
55974  * Field Access Macros:
55975  *
55976  */
55977 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field. */
55978 #define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_LSB 10
55979 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field. */
55980 #define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_MSB 10
55981 /* The width in bits of the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field. */
55982 #define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_WIDTH 1
55983 /* The mask used to set the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field value. */
55984 #define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_SET_MSK 0x00000400
55985 /* The mask used to clear the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field value. */
55986 #define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_CLR_MSK 0xfffffbff
55987 /* The reset value of the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field. */
55988 #define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_RESET 0x0
55989 /* Extracts the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK field value from a register. */
55990 #define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
55991 /* Produces a ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field value suitable for setting the register. */
55992 #define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
55993 
55994 /*
55995  * Field : bnaintrmsk
55996  *
55997  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
55998  *
55999  * This bit is valid only when Scatter/Gather DMA mode is enabled.
56000  *
56001  * Field Enumeration Values:
56002  *
56003  * Enum | Value | Description
56004  * :-------------------------------------------|:------|:------------
56005  * ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_MSK | 0x0 | Mask
56006  * ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_NOMSK | 0x1 | No mask
56007  *
56008  * Field Access Macros:
56009  *
56010  */
56011 /*
56012  * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_BNAINTRMSK
56013  *
56014  * Mask
56015  */
56016 #define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_MSK 0x0
56017 /*
56018  * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_BNAINTRMSK
56019  *
56020  * No mask
56021  */
56022 #define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_NOMSK 0x1
56023 
56024 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */
56025 #define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_LSB 11
56026 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */
56027 #define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_MSB 11
56028 /* The width in bits of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */
56029 #define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_WIDTH 1
56030 /* The mask used to set the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field value. */
56031 #define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_SET_MSK 0x00000800
56032 /* The mask used to clear the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field value. */
56033 #define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_CLR_MSK 0xfffff7ff
56034 /* The reset value of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */
56035 #define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_RESET 0x0
56036 /* Extracts the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK field value from a register. */
56037 #define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
56038 /* Produces a ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field value suitable for setting the register. */
56039 #define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
56040 
56041 /*
56042  * Field : frm_lst_rollintrmsk
56043  *
56044  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
56045  *
56046  * This bit is valid only when Scatter/Gather DMA mode is enabled.
56047  *
56048  * Field Enumeration Values:
56049  *
56050  * Enum | Value | Description
56051  * :----------------------------------------------------|:------|:------------
56052  * ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
56053  * ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
56054  *
56055  * Field Access Macros:
56056  *
56057  */
56058 /*
56059  * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK
56060  *
56061  * Mask
56062  */
56063 #define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_MSK 0x0
56064 /*
56065  * Enumerated value for register field ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK
56066  *
56067  * No mask
56068  */
56069 #define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
56070 
56071 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */
56072 #define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_LSB 13
56073 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */
56074 #define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_MSB 13
56075 /* The width in bits of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */
56076 #define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_WIDTH 1
56077 /* The mask used to set the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field value. */
56078 #define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
56079 /* The mask used to clear the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field value. */
56080 #define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
56081 /* The reset value of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */
56082 #define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_RESET 0x0
56083 /* Extracts the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK field value from a register. */
56084 #define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
56085 /* Produces a ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
56086 #define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
56087 
56088 #ifndef __ASSEMBLY__
56089 /*
56090  * WARNING: The C register and register group struct declarations are provided for
56091  * convenience and illustrative purposes. They should, however, be used with
56092  * caution as the C language standard provides no guarantees about the alignment or
56093  * atomicity of device memory accesses. The recommended practice for writing
56094  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56095  * alt_write_word() functions.
56096  *
56097  * The struct declaration for register ALT_USB_HOST_HCINTMSK13.
56098  */
56099 struct ALT_USB_HOST_HCINTMSK13_s
56100 {
56101  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK */
56102  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK13_CHHLTDMSK */
56103  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK13_AHBERRMSK */
56104  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK13_STALLMSK */
56105  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK13_NAKMSK */
56106  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK13_ACKMSK */
56107  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK13_NYETMSK */
56108  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK13_XACTERRMSK */
56109  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK13_BBLERRMSK */
56110  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK */
56111  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK */
56112  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK13_BNAINTRMSK */
56113  uint32_t : 1; /* *UNDEFINED* */
56114  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK */
56115  uint32_t : 18; /* *UNDEFINED* */
56116 };
56117 
56118 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK13. */
56119 typedef volatile struct ALT_USB_HOST_HCINTMSK13_s ALT_USB_HOST_HCINTMSK13_t;
56120 #endif /* __ASSEMBLY__ */
56121 
56122 /* The reset value of the ALT_USB_HOST_HCINTMSK13 register. */
56123 #define ALT_USB_HOST_HCINTMSK13_RESET 0x00000000
56124 /* The byte offset of the ALT_USB_HOST_HCINTMSK13 register from the beginning of the component. */
56125 #define ALT_USB_HOST_HCINTMSK13_OFST 0x2ac
56126 /* The address of the ALT_USB_HOST_HCINTMSK13 register. */
56127 #define ALT_USB_HOST_HCINTMSK13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK13_OFST))
56128 
56129 /*
56130  * Register : hctsiz13
56131  *
56132  * Host Channel 13 Transfer Size Register
56133  *
56134  * Register Layout
56135  *
56136  * Bits | Access | Reset | Description
56137  * :--------|:-------|:------|:-------------------------------
56138  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ13_XFERSIZE
56139  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ13_PKTCNT
56140  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ13_PID
56141  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ13_DOPNG
56142  *
56143  */
56144 /*
56145  * Field : xfersize
56146  *
56147  * Transfer Size (XferSize)
56148  *
56149  * For an OUT, this field is the number of data bytes the host sends
56150  *
56151  * during the transfer.
56152  *
56153  * For an IN, this field is the buffer size that the application has
56154  *
56155  * Reserved For the transfer. The application is expected to
56156  *
56157  * program this field as an integer multiple of the maximum packet
56158  *
56159  * size For IN transactions (periodic and non-periodic).
56160  *
56161  * The width of this counter is specified as Width of Transfer Size
56162  *
56163  * Counters
56164  *
56165  * Field Access Macros:
56166  *
56167  */
56168 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */
56169 #define ALT_USB_HOST_HCTSIZ13_XFERSIZE_LSB 0
56170 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */
56171 #define ALT_USB_HOST_HCTSIZ13_XFERSIZE_MSB 18
56172 /* The width in bits of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */
56173 #define ALT_USB_HOST_HCTSIZ13_XFERSIZE_WIDTH 19
56174 /* The mask used to set the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field value. */
56175 #define ALT_USB_HOST_HCTSIZ13_XFERSIZE_SET_MSK 0x0007ffff
56176 /* The mask used to clear the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field value. */
56177 #define ALT_USB_HOST_HCTSIZ13_XFERSIZE_CLR_MSK 0xfff80000
56178 /* The reset value of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */
56179 #define ALT_USB_HOST_HCTSIZ13_XFERSIZE_RESET 0x0
56180 /* Extracts the ALT_USB_HOST_HCTSIZ13_XFERSIZE field value from a register. */
56181 #define ALT_USB_HOST_HCTSIZ13_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
56182 /* Produces a ALT_USB_HOST_HCTSIZ13_XFERSIZE register field value suitable for setting the register. */
56183 #define ALT_USB_HOST_HCTSIZ13_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
56184 
56185 /*
56186  * Field : pktcnt
56187  *
56188  * Packet Count (PktCnt)
56189  *
56190  * This field is programmed by the application with the expected
56191  *
56192  * number of packets to be transmitted (OUT) or received (IN).
56193  *
56194  * The host decrements this count on every successful
56195  *
56196  * transmission or reception of an OUT/IN packet. Once this count
56197  *
56198  * reaches zero, the application is interrupted to indicate normal
56199  *
56200  * completion.
56201  *
56202  * The width of this counter is specified as Width of Packet
56203  *
56204  * Counters
56205  *
56206  * Field Access Macros:
56207  *
56208  */
56209 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */
56210 #define ALT_USB_HOST_HCTSIZ13_PKTCNT_LSB 19
56211 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */
56212 #define ALT_USB_HOST_HCTSIZ13_PKTCNT_MSB 28
56213 /* The width in bits of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */
56214 #define ALT_USB_HOST_HCTSIZ13_PKTCNT_WIDTH 10
56215 /* The mask used to set the ALT_USB_HOST_HCTSIZ13_PKTCNT register field value. */
56216 #define ALT_USB_HOST_HCTSIZ13_PKTCNT_SET_MSK 0x1ff80000
56217 /* The mask used to clear the ALT_USB_HOST_HCTSIZ13_PKTCNT register field value. */
56218 #define ALT_USB_HOST_HCTSIZ13_PKTCNT_CLR_MSK 0xe007ffff
56219 /* The reset value of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */
56220 #define ALT_USB_HOST_HCTSIZ13_PKTCNT_RESET 0x0
56221 /* Extracts the ALT_USB_HOST_HCTSIZ13_PKTCNT field value from a register. */
56222 #define ALT_USB_HOST_HCTSIZ13_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
56223 /* Produces a ALT_USB_HOST_HCTSIZ13_PKTCNT register field value suitable for setting the register. */
56224 #define ALT_USB_HOST_HCTSIZ13_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
56225 
56226 /*
56227  * Field : pid
56228  *
56229  * PID (Pid)
56230  *
56231  * The application programs this field with the type of PID to use For
56232  *
56233  * the initial transaction. The host maintains this field For the rest of
56234  *
56235  * the transfer.
56236  *
56237  * 2'b00: DATA0
56238  *
56239  * 2'b01: DATA2
56240  *
56241  * 2'b10: DATA1
56242  *
56243  * 2'b11: MDATA (non-control)/SETUP (control)
56244  *
56245  * Field Enumeration Values:
56246  *
56247  * Enum | Value | Description
56248  * :----------------------------------|:------|:------------------------------------
56249  * ALT_USB_HOST_HCTSIZ13_PID_E_DATA0 | 0x0 | DATA0
56250  * ALT_USB_HOST_HCTSIZ13_PID_E_DATA2 | 0x1 | DATA2
56251  * ALT_USB_HOST_HCTSIZ13_PID_E_DATA1 | 0x2 | DATA1
56252  * ALT_USB_HOST_HCTSIZ13_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
56253  *
56254  * Field Access Macros:
56255  *
56256  */
56257 /*
56258  * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID
56259  *
56260  * DATA0
56261  */
56262 #define ALT_USB_HOST_HCTSIZ13_PID_E_DATA0 0x0
56263 /*
56264  * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID
56265  *
56266  * DATA2
56267  */
56268 #define ALT_USB_HOST_HCTSIZ13_PID_E_DATA2 0x1
56269 /*
56270  * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID
56271  *
56272  * DATA1
56273  */
56274 #define ALT_USB_HOST_HCTSIZ13_PID_E_DATA1 0x2
56275 /*
56276  * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID
56277  *
56278  * MDATA (non-control)/SETUP (control)
56279  */
56280 #define ALT_USB_HOST_HCTSIZ13_PID_E_MDATA 0x3
56281 
56282 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_PID register field. */
56283 #define ALT_USB_HOST_HCTSIZ13_PID_LSB 29
56284 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_PID register field. */
56285 #define ALT_USB_HOST_HCTSIZ13_PID_MSB 30
56286 /* The width in bits of the ALT_USB_HOST_HCTSIZ13_PID register field. */
56287 #define ALT_USB_HOST_HCTSIZ13_PID_WIDTH 2
56288 /* The mask used to set the ALT_USB_HOST_HCTSIZ13_PID register field value. */
56289 #define ALT_USB_HOST_HCTSIZ13_PID_SET_MSK 0x60000000
56290 /* The mask used to clear the ALT_USB_HOST_HCTSIZ13_PID register field value. */
56291 #define ALT_USB_HOST_HCTSIZ13_PID_CLR_MSK 0x9fffffff
56292 /* The reset value of the ALT_USB_HOST_HCTSIZ13_PID register field. */
56293 #define ALT_USB_HOST_HCTSIZ13_PID_RESET 0x0
56294 /* Extracts the ALT_USB_HOST_HCTSIZ13_PID field value from a register. */
56295 #define ALT_USB_HOST_HCTSIZ13_PID_GET(value) (((value) & 0x60000000) >> 29)
56296 /* Produces a ALT_USB_HOST_HCTSIZ13_PID register field value suitable for setting the register. */
56297 #define ALT_USB_HOST_HCTSIZ13_PID_SET(value) (((value) << 29) & 0x60000000)
56298 
56299 /*
56300  * Field : dopng
56301  *
56302  * Do Ping (DoPng)
56303  *
56304  * This bit is used only For OUT transfers.
56305  *
56306  * Setting this field to 1 directs the host to do PING protocol.
56307  *
56308  * Note: Do not Set this bit For IN transfers. If this bit is Set For
56309  *
56310  * for IN transfers it disables the channel.
56311  *
56312  * Field Enumeration Values:
56313  *
56314  * Enum | Value | Description
56315  * :-------------------------------------|:------|:-----------------
56316  * ALT_USB_HOST_HCTSIZ13_DOPNG_E_NOPING | 0x0 | No ping protocol
56317  * ALT_USB_HOST_HCTSIZ13_DOPNG_E_PING | 0x1 | Ping protocol
56318  *
56319  * Field Access Macros:
56320  *
56321  */
56322 /*
56323  * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_DOPNG
56324  *
56325  * No ping protocol
56326  */
56327 #define ALT_USB_HOST_HCTSIZ13_DOPNG_E_NOPING 0x0
56328 /*
56329  * Enumerated value for register field ALT_USB_HOST_HCTSIZ13_DOPNG
56330  *
56331  * Ping protocol
56332  */
56333 #define ALT_USB_HOST_HCTSIZ13_DOPNG_E_PING 0x1
56334 
56335 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */
56336 #define ALT_USB_HOST_HCTSIZ13_DOPNG_LSB 31
56337 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */
56338 #define ALT_USB_HOST_HCTSIZ13_DOPNG_MSB 31
56339 /* The width in bits of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */
56340 #define ALT_USB_HOST_HCTSIZ13_DOPNG_WIDTH 1
56341 /* The mask used to set the ALT_USB_HOST_HCTSIZ13_DOPNG register field value. */
56342 #define ALT_USB_HOST_HCTSIZ13_DOPNG_SET_MSK 0x80000000
56343 /* The mask used to clear the ALT_USB_HOST_HCTSIZ13_DOPNG register field value. */
56344 #define ALT_USB_HOST_HCTSIZ13_DOPNG_CLR_MSK 0x7fffffff
56345 /* The reset value of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */
56346 #define ALT_USB_HOST_HCTSIZ13_DOPNG_RESET 0x0
56347 /* Extracts the ALT_USB_HOST_HCTSIZ13_DOPNG field value from a register. */
56348 #define ALT_USB_HOST_HCTSIZ13_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
56349 /* Produces a ALT_USB_HOST_HCTSIZ13_DOPNG register field value suitable for setting the register. */
56350 #define ALT_USB_HOST_HCTSIZ13_DOPNG_SET(value) (((value) << 31) & 0x80000000)
56351 
56352 #ifndef __ASSEMBLY__
56353 /*
56354  * WARNING: The C register and register group struct declarations are provided for
56355  * convenience and illustrative purposes. They should, however, be used with
56356  * caution as the C language standard provides no guarantees about the alignment or
56357  * atomicity of device memory accesses. The recommended practice for writing
56358  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56359  * alt_write_word() functions.
56360  *
56361  * The struct declaration for register ALT_USB_HOST_HCTSIZ13.
56362  */
56363 struct ALT_USB_HOST_HCTSIZ13_s
56364 {
56365  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ13_XFERSIZE */
56366  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ13_PKTCNT */
56367  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ13_PID */
56368  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ13_DOPNG */
56369 };
56370 
56371 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ13. */
56372 typedef volatile struct ALT_USB_HOST_HCTSIZ13_s ALT_USB_HOST_HCTSIZ13_t;
56373 #endif /* __ASSEMBLY__ */
56374 
56375 /* The reset value of the ALT_USB_HOST_HCTSIZ13 register. */
56376 #define ALT_USB_HOST_HCTSIZ13_RESET 0x00000000
56377 /* The byte offset of the ALT_USB_HOST_HCTSIZ13 register from the beginning of the component. */
56378 #define ALT_USB_HOST_HCTSIZ13_OFST 0x2b0
56379 /* The address of the ALT_USB_HOST_HCTSIZ13 register. */
56380 #define ALT_USB_HOST_HCTSIZ13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ13_OFST))
56381 
56382 /*
56383  * Register : hcdma13
56384  *
56385  * Host Channel 13 DMA Address Register
56386  *
56387  * Register Layout
56388  *
56389  * Bits | Access | Reset | Description
56390  * :-------|:-------|:------|:-----------------------------
56391  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA13_HCDMA13
56392  *
56393  */
56394 /*
56395  * Field : hcdma13
56396  *
56397  * Buffer DMA Mode:
56398  *
56399  * [31:0] DMA Address (DMAAddr)
56400  *
56401  * This field holds the start address in the external memory from which the data
56402  * for
56403  *
56404  * the endpoint must be fetched or to which it must be stored. This register is
56405  *
56406  * incremented on every AHB transaction.
56407  *
56408  * Scatter-Gather DMA (DescDMA) Mode:
56409  *
56410  * [31:9] (Non Isoc) Non-Isochronous:
56411  *
56412  * [31:N] (Isoc) Isochronous:
56413  *
56414  * This field holds the start address of the 512 bytes
56415  *
56416  * page. The first descriptor in the list should be located
56417  *
56418  * in this address. The first descriptor may be or may
56419  *
56420  * not be ready. The core starts processing the list from
56421  *
56422  * the CTD value.
56423  *
56424  * This field holds the address of the 2*(nTD+1) bytes of
56425  *
56426  * locations in which the isochronous descriptors are
56427  *
56428  * present where N is based on nTD as per Table below
56429  *
56430  * [31:N] Base Address
56431  *
56432  * [N-1:3] Offset
56433  *
56434  * [2:0] 000
56435  *
56436  * HS ISOC
56437  *
56438  * nTD N
56439  *
56440  * 7 6
56441  *
56442  * 15 7
56443  *
56444  * 31 8
56445  *
56446  * 63 9
56447  *
56448  * 127 10
56449  *
56450  * 255 11
56451  *
56452  * FS ISOC
56453  *
56454  * nTD N
56455  *
56456  * 1 4
56457  *
56458  * 3 5
56459  *
56460  * 7 6
56461  *
56462  * 15 7
56463  *
56464  * 31 8
56465  *
56466  * 63 9
56467  *
56468  * [N-1:3] (Isoc):
56469  *
56470  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
56471  *
56472  * Non Isochronous:
56473  *
56474  * This value is in terms of number of descriptors. The values can be from 0 to 63.
56475  *
56476  * 0 - 1 descriptor.
56477  *
56478  * 63 - 64 descriptors.
56479  *
56480  * This field indicates the current descriptor processed in the list. This field is
56481  * updated
56482  *
56483  * both by application and the core. For example, if the application enables the
56484  *
56485  * channel after programming CTD=5, then the core will start processing the 6th
56486  *
56487  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
56488  *
56489  * to DMAAddr.
56490  *
56491  * Isochronous:
56492  *
56493  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
56494  * set
56495  *
56496  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
56497  *
56498  * [31:9] (Non Isoc) Non-Isochronous:
56499  *
56500  * [31:N] (Isoc) Isochronous:
56501  *
56502  * This field holds the start address of the 512 bytes
56503  *
56504  * page. The first descriptor in the list should be located
56505  *
56506  * in this address. The first descriptor may be or may
56507  *
56508  * not be ready. The core starts processing the list from
56509  *
56510  * the CTD value.
56511  *
56512  * This field holds the address of the 2*(nTD+1) bytes of
56513  *
56514  * locations in which the isochronous descriptors are
56515  *
56516  * present where N is based on nTD as per Table below
56517  *
56518  * [31:N] Base Address
56519  *
56520  * [N-1:3] Offset
56521  *
56522  * [2:0] 000
56523  *
56524  * HS ISOC
56525  *
56526  * nTD N
56527  *
56528  * 7 6
56529  *
56530  * 15 7
56531  *
56532  * 31 8
56533  *
56534  * 63 9
56535  *
56536  * 127 10
56537  *
56538  * 255 11
56539  *
56540  * FS ISOC
56541  *
56542  * nTD N
56543  *
56544  * 1 4
56545  *
56546  * 3 5
56547  *
56548  * 7 6
56549  *
56550  * 15 7
56551  *
56552  * 31 8
56553  *
56554  * 63 9
56555  *
56556  * [N-1:3] (Isoc):
56557  *
56558  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
56559  *
56560  * Non Isochronous:
56561  *
56562  * This value is in terms of number of descriptors. The values can be from 0 to 63.
56563  *
56564  * 0 - 1 descriptor.
56565  *
56566  * 63 - 64 descriptors.
56567  *
56568  * This field indicates the current descriptor processed in the list. This field is
56569  * updated
56570  *
56571  * both by application and the core. For example, if the application enables the
56572  *
56573  * channel after programming CTD=5, then the core will start processing the 6th
56574  *
56575  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
56576  *
56577  * to DMAAddr.
56578  *
56579  * Isochronous:
56580  *
56581  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
56582  * set
56583  *
56584  * to zero by application.
56585  *
56586  * Field Access Macros:
56587  *
56588  */
56589 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */
56590 #define ALT_USB_HOST_HCDMA13_HCDMA13_LSB 0
56591 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */
56592 #define ALT_USB_HOST_HCDMA13_HCDMA13_MSB 31
56593 /* The width in bits of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */
56594 #define ALT_USB_HOST_HCDMA13_HCDMA13_WIDTH 32
56595 /* The mask used to set the ALT_USB_HOST_HCDMA13_HCDMA13 register field value. */
56596 #define ALT_USB_HOST_HCDMA13_HCDMA13_SET_MSK 0xffffffff
56597 /* The mask used to clear the ALT_USB_HOST_HCDMA13_HCDMA13 register field value. */
56598 #define ALT_USB_HOST_HCDMA13_HCDMA13_CLR_MSK 0x00000000
56599 /* The reset value of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */
56600 #define ALT_USB_HOST_HCDMA13_HCDMA13_RESET 0x0
56601 /* Extracts the ALT_USB_HOST_HCDMA13_HCDMA13 field value from a register. */
56602 #define ALT_USB_HOST_HCDMA13_HCDMA13_GET(value) (((value) & 0xffffffff) >> 0)
56603 /* Produces a ALT_USB_HOST_HCDMA13_HCDMA13 register field value suitable for setting the register. */
56604 #define ALT_USB_HOST_HCDMA13_HCDMA13_SET(value) (((value) << 0) & 0xffffffff)
56605 
56606 #ifndef __ASSEMBLY__
56607 /*
56608  * WARNING: The C register and register group struct declarations are provided for
56609  * convenience and illustrative purposes. They should, however, be used with
56610  * caution as the C language standard provides no guarantees about the alignment or
56611  * atomicity of device memory accesses. The recommended practice for writing
56612  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56613  * alt_write_word() functions.
56614  *
56615  * The struct declaration for register ALT_USB_HOST_HCDMA13.
56616  */
56617 struct ALT_USB_HOST_HCDMA13_s
56618 {
56619  uint32_t hcdma13 : 32; /* ALT_USB_HOST_HCDMA13_HCDMA13 */
56620 };
56621 
56622 /* The typedef declaration for register ALT_USB_HOST_HCDMA13. */
56623 typedef volatile struct ALT_USB_HOST_HCDMA13_s ALT_USB_HOST_HCDMA13_t;
56624 #endif /* __ASSEMBLY__ */
56625 
56626 /* The reset value of the ALT_USB_HOST_HCDMA13 register. */
56627 #define ALT_USB_HOST_HCDMA13_RESET 0x00000000
56628 /* The byte offset of the ALT_USB_HOST_HCDMA13 register from the beginning of the component. */
56629 #define ALT_USB_HOST_HCDMA13_OFST 0x2b4
56630 /* The address of the ALT_USB_HOST_HCDMA13 register. */
56631 #define ALT_USB_HOST_HCDMA13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA13_OFST))
56632 
56633 /*
56634  * Register : hcdmab13
56635  *
56636  * Host Channel 13 DMA Buffer Address Register
56637  *
56638  * Register Layout
56639  *
56640  * Bits | Access | Reset | Description
56641  * :-------|:-------|:------|:-------------------------------
56642  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB13_HCDMAB13
56643  *
56644  */
56645 /*
56646  * Field : hcdmab13
56647  *
56648  * Holds the current buffer address.
56649  *
56650  * This register is updated as and when the data transfer for the corresponding end
56651  * point
56652  *
56653  * is in progress. This register is present only in Scatter/Gather DMA mode.
56654  * Otherwise this
56655  *
56656  * field is reserved.
56657  *
56658  * Field Access Macros:
56659  *
56660  */
56661 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */
56662 #define ALT_USB_HOST_HCDMAB13_HCDMAB13_LSB 0
56663 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */
56664 #define ALT_USB_HOST_HCDMAB13_HCDMAB13_MSB 31
56665 /* The width in bits of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */
56666 #define ALT_USB_HOST_HCDMAB13_HCDMAB13_WIDTH 32
56667 /* The mask used to set the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field value. */
56668 #define ALT_USB_HOST_HCDMAB13_HCDMAB13_SET_MSK 0xffffffff
56669 /* The mask used to clear the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field value. */
56670 #define ALT_USB_HOST_HCDMAB13_HCDMAB13_CLR_MSK 0x00000000
56671 /* The reset value of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */
56672 #define ALT_USB_HOST_HCDMAB13_HCDMAB13_RESET 0x0
56673 /* Extracts the ALT_USB_HOST_HCDMAB13_HCDMAB13 field value from a register. */
56674 #define ALT_USB_HOST_HCDMAB13_HCDMAB13_GET(value) (((value) & 0xffffffff) >> 0)
56675 /* Produces a ALT_USB_HOST_HCDMAB13_HCDMAB13 register field value suitable for setting the register. */
56676 #define ALT_USB_HOST_HCDMAB13_HCDMAB13_SET(value) (((value) << 0) & 0xffffffff)
56677 
56678 #ifndef __ASSEMBLY__
56679 /*
56680  * WARNING: The C register and register group struct declarations are provided for
56681  * convenience and illustrative purposes. They should, however, be used with
56682  * caution as the C language standard provides no guarantees about the alignment or
56683  * atomicity of device memory accesses. The recommended practice for writing
56684  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56685  * alt_write_word() functions.
56686  *
56687  * The struct declaration for register ALT_USB_HOST_HCDMAB13.
56688  */
56689 struct ALT_USB_HOST_HCDMAB13_s
56690 {
56691  uint32_t hcdmab13 : 32; /* ALT_USB_HOST_HCDMAB13_HCDMAB13 */
56692 };
56693 
56694 /* The typedef declaration for register ALT_USB_HOST_HCDMAB13. */
56695 typedef volatile struct ALT_USB_HOST_HCDMAB13_s ALT_USB_HOST_HCDMAB13_t;
56696 #endif /* __ASSEMBLY__ */
56697 
56698 /* The reset value of the ALT_USB_HOST_HCDMAB13 register. */
56699 #define ALT_USB_HOST_HCDMAB13_RESET 0x00000000
56700 /* The byte offset of the ALT_USB_HOST_HCDMAB13 register from the beginning of the component. */
56701 #define ALT_USB_HOST_HCDMAB13_OFST 0x2bc
56702 /* The address of the ALT_USB_HOST_HCDMAB13 register. */
56703 #define ALT_USB_HOST_HCDMAB13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB13_OFST))
56704 
56705 /*
56706  * Register : hcchar14
56707  *
56708  * Host Channel 14 Characteristics Register
56709  *
56710  * Register Layout
56711  *
56712  * Bits | Access | Reset | Description
56713  * :--------|:---------|:------|:------------------------------
56714  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_MPS
56715  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_EPNUM
56716  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_EPDIR
56717  * [16] | ??? | 0x0 | *UNDEFINED*
56718  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_LSPDDEV
56719  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_EPTYPE
56720  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_EC
56721  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_DEVADDR
56722  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_ODDFRM
56723  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR14_CHDIS
56724  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR14_CHENA
56725  *
56726  */
56727 /*
56728  * Field : mps
56729  *
56730  * Maximum Packet Size (MPS)
56731  *
56732  * Indicates the maximum packet size of the associated endpoint.
56733  *
56734  * Field Access Macros:
56735  *
56736  */
56737 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_MPS register field. */
56738 #define ALT_USB_HOST_HCCHAR14_MPS_LSB 0
56739 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_MPS register field. */
56740 #define ALT_USB_HOST_HCCHAR14_MPS_MSB 10
56741 /* The width in bits of the ALT_USB_HOST_HCCHAR14_MPS register field. */
56742 #define ALT_USB_HOST_HCCHAR14_MPS_WIDTH 11
56743 /* The mask used to set the ALT_USB_HOST_HCCHAR14_MPS register field value. */
56744 #define ALT_USB_HOST_HCCHAR14_MPS_SET_MSK 0x000007ff
56745 /* The mask used to clear the ALT_USB_HOST_HCCHAR14_MPS register field value. */
56746 #define ALT_USB_HOST_HCCHAR14_MPS_CLR_MSK 0xfffff800
56747 /* The reset value of the ALT_USB_HOST_HCCHAR14_MPS register field. */
56748 #define ALT_USB_HOST_HCCHAR14_MPS_RESET 0x0
56749 /* Extracts the ALT_USB_HOST_HCCHAR14_MPS field value from a register. */
56750 #define ALT_USB_HOST_HCCHAR14_MPS_GET(value) (((value) & 0x000007ff) >> 0)
56751 /* Produces a ALT_USB_HOST_HCCHAR14_MPS register field value suitable for setting the register. */
56752 #define ALT_USB_HOST_HCCHAR14_MPS_SET(value) (((value) << 0) & 0x000007ff)
56753 
56754 /*
56755  * Field : epnum
56756  *
56757  * Endpoint Number (EPNum)
56758  *
56759  * Indicates the endpoint number on the device serving as the data
56760  *
56761  * source or sink.
56762  *
56763  * Field Enumeration Values:
56764  *
56765  * Enum | Value | Description
56766  * :--------------------------------------|:------|:--------------
56767  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT0 | 0x0 | End point 0
56768  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT1 | 0x1 | End point 1
56769  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT2 | 0x2 | End point 2
56770  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT3 | 0x3 | End point 3
56771  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT4 | 0x4 | End point 4
56772  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT5 | 0x5 | End point 5
56773  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT6 | 0x6 | End point 6
56774  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT7 | 0x7 | End point 7
56775  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT8 | 0x8 | End point 8
56776  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT9 | 0x9 | End point 9
56777  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT10 | 0xa | End point 10
56778  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT11 | 0xb | End point 11
56779  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT12 | 0xc | End point 12
56780  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT13 | 0xd | End point 13
56781  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT14 | 0xe | End point 14
56782  * ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT15 | 0xf | End point 15
56783  *
56784  * Field Access Macros:
56785  *
56786  */
56787 /*
56788  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56789  *
56790  * End point 0
56791  */
56792 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT0 0x0
56793 /*
56794  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56795  *
56796  * End point 1
56797  */
56798 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT1 0x1
56799 /*
56800  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56801  *
56802  * End point 2
56803  */
56804 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT2 0x2
56805 /*
56806  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56807  *
56808  * End point 3
56809  */
56810 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT3 0x3
56811 /*
56812  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56813  *
56814  * End point 4
56815  */
56816 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT4 0x4
56817 /*
56818  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56819  *
56820  * End point 5
56821  */
56822 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT5 0x5
56823 /*
56824  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56825  *
56826  * End point 6
56827  */
56828 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT6 0x6
56829 /*
56830  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56831  *
56832  * End point 7
56833  */
56834 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT7 0x7
56835 /*
56836  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56837  *
56838  * End point 8
56839  */
56840 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT8 0x8
56841 /*
56842  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56843  *
56844  * End point 9
56845  */
56846 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT9 0x9
56847 /*
56848  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56849  *
56850  * End point 10
56851  */
56852 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT10 0xa
56853 /*
56854  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56855  *
56856  * End point 11
56857  */
56858 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT11 0xb
56859 /*
56860  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56861  *
56862  * End point 12
56863  */
56864 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT12 0xc
56865 /*
56866  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56867  *
56868  * End point 13
56869  */
56870 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT13 0xd
56871 /*
56872  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56873  *
56874  * End point 14
56875  */
56876 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT14 0xe
56877 /*
56878  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
56879  *
56880  * End point 15
56881  */
56882 #define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT15 0xf
56883 
56884 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */
56885 #define ALT_USB_HOST_HCCHAR14_EPNUM_LSB 11
56886 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */
56887 #define ALT_USB_HOST_HCCHAR14_EPNUM_MSB 14
56888 /* The width in bits of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */
56889 #define ALT_USB_HOST_HCCHAR14_EPNUM_WIDTH 4
56890 /* The mask used to set the ALT_USB_HOST_HCCHAR14_EPNUM register field value. */
56891 #define ALT_USB_HOST_HCCHAR14_EPNUM_SET_MSK 0x00007800
56892 /* The mask used to clear the ALT_USB_HOST_HCCHAR14_EPNUM register field value. */
56893 #define ALT_USB_HOST_HCCHAR14_EPNUM_CLR_MSK 0xffff87ff
56894 /* The reset value of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */
56895 #define ALT_USB_HOST_HCCHAR14_EPNUM_RESET 0x0
56896 /* Extracts the ALT_USB_HOST_HCCHAR14_EPNUM field value from a register. */
56897 #define ALT_USB_HOST_HCCHAR14_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
56898 /* Produces a ALT_USB_HOST_HCCHAR14_EPNUM register field value suitable for setting the register. */
56899 #define ALT_USB_HOST_HCCHAR14_EPNUM_SET(value) (((value) << 11) & 0x00007800)
56900 
56901 /*
56902  * Field : epdir
56903  *
56904  * Endpoint Direction (EPDir)
56905  *
56906  * Indicates whether the transaction is IN or OUT.
56907  *
56908  * 1'b0: OUT
56909  *
56910  * 1'b1: IN
56911  *
56912  * Field Enumeration Values:
56913  *
56914  * Enum | Value | Description
56915  * :----------------------------------|:------|:--------------
56916  * ALT_USB_HOST_HCCHAR14_EPDIR_E_OUT | 0x0 | OUT Direction
56917  * ALT_USB_HOST_HCCHAR14_EPDIR_E_IN | 0x1 | IN Direction
56918  *
56919  * Field Access Macros:
56920  *
56921  */
56922 /*
56923  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPDIR
56924  *
56925  * OUT Direction
56926  */
56927 #define ALT_USB_HOST_HCCHAR14_EPDIR_E_OUT 0x0
56928 /*
56929  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPDIR
56930  *
56931  * IN Direction
56932  */
56933 #define ALT_USB_HOST_HCCHAR14_EPDIR_E_IN 0x1
56934 
56935 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */
56936 #define ALT_USB_HOST_HCCHAR14_EPDIR_LSB 15
56937 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */
56938 #define ALT_USB_HOST_HCCHAR14_EPDIR_MSB 15
56939 /* The width in bits of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */
56940 #define ALT_USB_HOST_HCCHAR14_EPDIR_WIDTH 1
56941 /* The mask used to set the ALT_USB_HOST_HCCHAR14_EPDIR register field value. */
56942 #define ALT_USB_HOST_HCCHAR14_EPDIR_SET_MSK 0x00008000
56943 /* The mask used to clear the ALT_USB_HOST_HCCHAR14_EPDIR register field value. */
56944 #define ALT_USB_HOST_HCCHAR14_EPDIR_CLR_MSK 0xffff7fff
56945 /* The reset value of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */
56946 #define ALT_USB_HOST_HCCHAR14_EPDIR_RESET 0x0
56947 /* Extracts the ALT_USB_HOST_HCCHAR14_EPDIR field value from a register. */
56948 #define ALT_USB_HOST_HCCHAR14_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
56949 /* Produces a ALT_USB_HOST_HCCHAR14_EPDIR register field value suitable for setting the register. */
56950 #define ALT_USB_HOST_HCCHAR14_EPDIR_SET(value) (((value) << 15) & 0x00008000)
56951 
56952 /*
56953  * Field : lspddev
56954  *
56955  * Low-Speed Device (LSpdDev)
56956  *
56957  * This field is Set by the application to indicate that this channel is
56958  *
56959  * communicating to a low-speed device.
56960  *
56961  * Field Enumeration Values:
56962  *
56963  * Enum | Value | Description
56964  * :-------------------------------------|:------|:----------------------------------------
56965  * ALT_USB_HOST_HCCHAR14_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
56966  * ALT_USB_HOST_HCCHAR14_LSPDDEV_E_END | 0x1 | Communicating with low speed device
56967  *
56968  * Field Access Macros:
56969  *
56970  */
56971 /*
56972  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_LSPDDEV
56973  *
56974  * Not Communicating with low speed device
56975  */
56976 #define ALT_USB_HOST_HCCHAR14_LSPDDEV_E_DISD 0x0
56977 /*
56978  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_LSPDDEV
56979  *
56980  * Communicating with low speed device
56981  */
56982 #define ALT_USB_HOST_HCCHAR14_LSPDDEV_E_END 0x1
56983 
56984 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */
56985 #define ALT_USB_HOST_HCCHAR14_LSPDDEV_LSB 17
56986 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */
56987 #define ALT_USB_HOST_HCCHAR14_LSPDDEV_MSB 17
56988 /* The width in bits of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */
56989 #define ALT_USB_HOST_HCCHAR14_LSPDDEV_WIDTH 1
56990 /* The mask used to set the ALT_USB_HOST_HCCHAR14_LSPDDEV register field value. */
56991 #define ALT_USB_HOST_HCCHAR14_LSPDDEV_SET_MSK 0x00020000
56992 /* The mask used to clear the ALT_USB_HOST_HCCHAR14_LSPDDEV register field value. */
56993 #define ALT_USB_HOST_HCCHAR14_LSPDDEV_CLR_MSK 0xfffdffff
56994 /* The reset value of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */
56995 #define ALT_USB_HOST_HCCHAR14_LSPDDEV_RESET 0x0
56996 /* Extracts the ALT_USB_HOST_HCCHAR14_LSPDDEV field value from a register. */
56997 #define ALT_USB_HOST_HCCHAR14_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
56998 /* Produces a ALT_USB_HOST_HCCHAR14_LSPDDEV register field value suitable for setting the register. */
56999 #define ALT_USB_HOST_HCCHAR14_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
57000 
57001 /*
57002  * Field : eptype
57003  *
57004  * Endpoint Type (EPType)
57005  *
57006  * Indicates the transfer type selected.
57007  *
57008  * 2'b00: Control
57009  *
57010  * 2'b01: Isochronous
57011  *
57012  * 2'b10: Bulk
57013  *
57014  * 2'b11: Interrupt
57015  *
57016  * Field Enumeration Values:
57017  *
57018  * Enum | Value | Description
57019  * :--------------------------------------|:------|:------------
57020  * ALT_USB_HOST_HCCHAR14_EPTYPE_E_CTL | 0x0 | Control
57021  * ALT_USB_HOST_HCCHAR14_EPTYPE_E_ISOC | 0x1 | Isochronous
57022  * ALT_USB_HOST_HCCHAR14_EPTYPE_E_BULK | 0x2 | Bulk
57023  * ALT_USB_HOST_HCCHAR14_EPTYPE_E_INTERR | 0x3 | Interrupt
57024  *
57025  * Field Access Macros:
57026  *
57027  */
57028 /*
57029  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE
57030  *
57031  * Control
57032  */
57033 #define ALT_USB_HOST_HCCHAR14_EPTYPE_E_CTL 0x0
57034 /*
57035  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE
57036  *
57037  * Isochronous
57038  */
57039 #define ALT_USB_HOST_HCCHAR14_EPTYPE_E_ISOC 0x1
57040 /*
57041  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE
57042  *
57043  * Bulk
57044  */
57045 #define ALT_USB_HOST_HCCHAR14_EPTYPE_E_BULK 0x2
57046 /*
57047  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE
57048  *
57049  * Interrupt
57050  */
57051 #define ALT_USB_HOST_HCCHAR14_EPTYPE_E_INTERR 0x3
57052 
57053 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */
57054 #define ALT_USB_HOST_HCCHAR14_EPTYPE_LSB 18
57055 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */
57056 #define ALT_USB_HOST_HCCHAR14_EPTYPE_MSB 19
57057 /* The width in bits of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */
57058 #define ALT_USB_HOST_HCCHAR14_EPTYPE_WIDTH 2
57059 /* The mask used to set the ALT_USB_HOST_HCCHAR14_EPTYPE register field value. */
57060 #define ALT_USB_HOST_HCCHAR14_EPTYPE_SET_MSK 0x000c0000
57061 /* The mask used to clear the ALT_USB_HOST_HCCHAR14_EPTYPE register field value. */
57062 #define ALT_USB_HOST_HCCHAR14_EPTYPE_CLR_MSK 0xfff3ffff
57063 /* The reset value of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */
57064 #define ALT_USB_HOST_HCCHAR14_EPTYPE_RESET 0x0
57065 /* Extracts the ALT_USB_HOST_HCCHAR14_EPTYPE field value from a register. */
57066 #define ALT_USB_HOST_HCCHAR14_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
57067 /* Produces a ALT_USB_HOST_HCCHAR14_EPTYPE register field value suitable for setting the register. */
57068 #define ALT_USB_HOST_HCCHAR14_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
57069 
57070 /*
57071  * Field : ec
57072  *
57073  * Multi Count (MC) / Error Count (EC)
57074  *
57075  * When the Split Enable bit of the Host Channel-n Split Control
57076  *
57077  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
57078  *
57079  * the host the number of transactions that must be executed per
57080  *
57081  * microframe For this periodic endpoint. For non periodic transfers,
57082  *
57083  * this field is used only in DMA mode, and specifies the number
57084  *
57085  * packets to be fetched For this channel before the internal DMA
57086  *
57087  * engine changes arbitration.
57088  *
57089  * 2'b00: Reserved This field yields undefined results.
57090  *
57091  * 2'b01: 1 transaction
57092  *
57093  * 2'b10: 2 transactions to be issued For this endpoint per
57094  *
57095  * microframe
57096  *
57097  * 2'b11: 3 transactions to be issued For this endpoint per
57098  *
57099  * microframe
57100  *
57101  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
57102  *
57103  * number of immediate retries to be performed For a periodic split
57104  *
57105  * transactions on transaction errors. This field must be Set to at
57106  *
57107  * least 2'b01.
57108  *
57109  * Field Enumeration Values:
57110  *
57111  * Enum | Value | Description
57112  * :--------------------------------------|:------|:----------------------------------------------
57113  * ALT_USB_HOST_HCCHAR14_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
57114  * ALT_USB_HOST_HCCHAR14_EC_E_TRANSONE | 0x1 | 1 transaction
57115  * ALT_USB_HOST_HCCHAR14_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
57116  * : | | per microframe
57117  * ALT_USB_HOST_HCCHAR14_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
57118  * : | | per microframe
57119  *
57120  * Field Access Macros:
57121  *
57122  */
57123 /*
57124  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC
57125  *
57126  * Reserved This field yields undefined result
57127  */
57128 #define ALT_USB_HOST_HCCHAR14_EC_E_RSVD 0x0
57129 /*
57130  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC
57131  *
57132  * 1 transaction
57133  */
57134 #define ALT_USB_HOST_HCCHAR14_EC_E_TRANSONE 0x1
57135 /*
57136  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC
57137  *
57138  * 2 transactions to be issued for this endpoint per microframe
57139  */
57140 #define ALT_USB_HOST_HCCHAR14_EC_E_TRANSTWO 0x2
57141 /*
57142  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC
57143  *
57144  * 3 transactions to be issued for this endpoint per microframe
57145  */
57146 #define ALT_USB_HOST_HCCHAR14_EC_E_TRANSTHREE 0x3
57147 
57148 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EC register field. */
57149 #define ALT_USB_HOST_HCCHAR14_EC_LSB 20
57150 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EC register field. */
57151 #define ALT_USB_HOST_HCCHAR14_EC_MSB 21
57152 /* The width in bits of the ALT_USB_HOST_HCCHAR14_EC register field. */
57153 #define ALT_USB_HOST_HCCHAR14_EC_WIDTH 2
57154 /* The mask used to set the ALT_USB_HOST_HCCHAR14_EC register field value. */
57155 #define ALT_USB_HOST_HCCHAR14_EC_SET_MSK 0x00300000
57156 /* The mask used to clear the ALT_USB_HOST_HCCHAR14_EC register field value. */
57157 #define ALT_USB_HOST_HCCHAR14_EC_CLR_MSK 0xffcfffff
57158 /* The reset value of the ALT_USB_HOST_HCCHAR14_EC register field. */
57159 #define ALT_USB_HOST_HCCHAR14_EC_RESET 0x0
57160 /* Extracts the ALT_USB_HOST_HCCHAR14_EC field value from a register. */
57161 #define ALT_USB_HOST_HCCHAR14_EC_GET(value) (((value) & 0x00300000) >> 20)
57162 /* Produces a ALT_USB_HOST_HCCHAR14_EC register field value suitable for setting the register. */
57163 #define ALT_USB_HOST_HCCHAR14_EC_SET(value) (((value) << 20) & 0x00300000)
57164 
57165 /*
57166  * Field : devaddr
57167  *
57168  * Device Address (DevAddr)
57169  *
57170  * This field selects the specific device serving as the data source
57171  *
57172  * or sink.
57173  *
57174  * Field Access Macros:
57175  *
57176  */
57177 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */
57178 #define ALT_USB_HOST_HCCHAR14_DEVADDR_LSB 22
57179 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */
57180 #define ALT_USB_HOST_HCCHAR14_DEVADDR_MSB 28
57181 /* The width in bits of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */
57182 #define ALT_USB_HOST_HCCHAR14_DEVADDR_WIDTH 7
57183 /* The mask used to set the ALT_USB_HOST_HCCHAR14_DEVADDR register field value. */
57184 #define ALT_USB_HOST_HCCHAR14_DEVADDR_SET_MSK 0x1fc00000
57185 /* The mask used to clear the ALT_USB_HOST_HCCHAR14_DEVADDR register field value. */
57186 #define ALT_USB_HOST_HCCHAR14_DEVADDR_CLR_MSK 0xe03fffff
57187 /* The reset value of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */
57188 #define ALT_USB_HOST_HCCHAR14_DEVADDR_RESET 0x0
57189 /* Extracts the ALT_USB_HOST_HCCHAR14_DEVADDR field value from a register. */
57190 #define ALT_USB_HOST_HCCHAR14_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
57191 /* Produces a ALT_USB_HOST_HCCHAR14_DEVADDR register field value suitable for setting the register. */
57192 #define ALT_USB_HOST_HCCHAR14_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
57193 
57194 /*
57195  * Field : oddfrm
57196  *
57197  * Odd Frame (OddFrm)
57198  *
57199  * This field is set (reset) by the application to indicate that the OTG host must
57200  * perform
57201  *
57202  * a transfer in an odd (micro)frame. This field is applicable for only periodic
57203  *
57204  * (isochronous and interrupt) transactions.
57205  *
57206  * 1'b0: Even (micro)frame
57207  *
57208  * 1'b1: Odd (micro)frame
57209  *
57210  * Field Access Macros:
57211  *
57212  */
57213 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_ODDFRM register field. */
57214 #define ALT_USB_HOST_HCCHAR14_ODDFRM_LSB 29
57215 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_ODDFRM register field. */
57216 #define ALT_USB_HOST_HCCHAR14_ODDFRM_MSB 29
57217 /* The width in bits of the ALT_USB_HOST_HCCHAR14_ODDFRM register field. */
57218 #define ALT_USB_HOST_HCCHAR14_ODDFRM_WIDTH 1
57219 /* The mask used to set the ALT_USB_HOST_HCCHAR14_ODDFRM register field value. */
57220 #define ALT_USB_HOST_HCCHAR14_ODDFRM_SET_MSK 0x20000000
57221 /* The mask used to clear the ALT_USB_HOST_HCCHAR14_ODDFRM register field value. */
57222 #define ALT_USB_HOST_HCCHAR14_ODDFRM_CLR_MSK 0xdfffffff
57223 /* The reset value of the ALT_USB_HOST_HCCHAR14_ODDFRM register field. */
57224 #define ALT_USB_HOST_HCCHAR14_ODDFRM_RESET 0x0
57225 /* Extracts the ALT_USB_HOST_HCCHAR14_ODDFRM field value from a register. */
57226 #define ALT_USB_HOST_HCCHAR14_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
57227 /* Produces a ALT_USB_HOST_HCCHAR14_ODDFRM register field value suitable for setting the register. */
57228 #define ALT_USB_HOST_HCCHAR14_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
57229 
57230 /*
57231  * Field : chdis
57232  *
57233  * Channel Disable (ChDis)
57234  *
57235  * The application sets this bit to stop transmitting/receiving data
57236  *
57237  * on a channel, even before the transfer For that channel is
57238  *
57239  * complete. The application must wait For the Channel Disabled
57240  *
57241  * interrupt before treating the channel as disabled.
57242  *
57243  * Field Enumeration Values:
57244  *
57245  * Enum | Value | Description
57246  * :------------------------------------|:------|:----------------------------
57247  * ALT_USB_HOST_HCCHAR14_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
57248  * ALT_USB_HOST_HCCHAR14_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
57249  *
57250  * Field Access Macros:
57251  *
57252  */
57253 /*
57254  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHDIS
57255  *
57256  * Transmit/Recieve normal
57257  */
57258 #define ALT_USB_HOST_HCCHAR14_CHDIS_E_INACT 0x0
57259 /*
57260  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHDIS
57261  *
57262  * Stop transmitting/receiving
57263  */
57264 #define ALT_USB_HOST_HCCHAR14_CHDIS_E_ACT 0x1
57265 
57266 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */
57267 #define ALT_USB_HOST_HCCHAR14_CHDIS_LSB 30
57268 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */
57269 #define ALT_USB_HOST_HCCHAR14_CHDIS_MSB 30
57270 /* The width in bits of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */
57271 #define ALT_USB_HOST_HCCHAR14_CHDIS_WIDTH 1
57272 /* The mask used to set the ALT_USB_HOST_HCCHAR14_CHDIS register field value. */
57273 #define ALT_USB_HOST_HCCHAR14_CHDIS_SET_MSK 0x40000000
57274 /* The mask used to clear the ALT_USB_HOST_HCCHAR14_CHDIS register field value. */
57275 #define ALT_USB_HOST_HCCHAR14_CHDIS_CLR_MSK 0xbfffffff
57276 /* The reset value of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */
57277 #define ALT_USB_HOST_HCCHAR14_CHDIS_RESET 0x0
57278 /* Extracts the ALT_USB_HOST_HCCHAR14_CHDIS field value from a register. */
57279 #define ALT_USB_HOST_HCCHAR14_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
57280 /* Produces a ALT_USB_HOST_HCCHAR14_CHDIS register field value suitable for setting the register. */
57281 #define ALT_USB_HOST_HCCHAR14_CHDIS_SET(value) (((value) << 30) & 0x40000000)
57282 
57283 /*
57284  * Field : chena
57285  *
57286  * Channel Enable (ChEna)
57287  *
57288  * When Scatter/Gather mode is enabled
57289  *
57290  * 1'b0: Indicates that the descriptor structure is not yet ready.
57291  *
57292  * 1'b1: Indicates that the descriptor structure and data buffer with
57293  *
57294  * data is setup and this channel can access the descriptor.
57295  *
57296  * When Scatter/Gather mode is disabled
57297  *
57298  * This field is set by the application and cleared by the OTG host.
57299  *
57300  * 1'b0: Channel disabled
57301  *
57302  * 1'b1: Channel enabled
57303  *
57304  * Field Enumeration Values:
57305  *
57306  * Enum | Value | Description
57307  * :------------------------------------|:------|:-------------------------------------------------
57308  * ALT_USB_HOST_HCCHAR14_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
57309  * : | | yet ready
57310  * ALT_USB_HOST_HCCHAR14_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
57311  * : | | data buffer with data is setup and this
57312  * : | | channel can access the descriptor
57313  *
57314  * Field Access Macros:
57315  *
57316  */
57317 /*
57318  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHENA
57319  *
57320  * Indicates that the descriptor structure is not yet ready
57321  */
57322 #define ALT_USB_HOST_HCCHAR14_CHENA_E_INACT 0x0
57323 /*
57324  * Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHENA
57325  *
57326  * Indicates that the descriptor structure and data buffer with data is
57327  * setup and this channel can access the descriptor
57328  */
57329 #define ALT_USB_HOST_HCCHAR14_CHENA_E_ACT 0x1
57330 
57331 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_CHENA register field. */
57332 #define ALT_USB_HOST_HCCHAR14_CHENA_LSB 31
57333 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_CHENA register field. */
57334 #define ALT_USB_HOST_HCCHAR14_CHENA_MSB 31
57335 /* The width in bits of the ALT_USB_HOST_HCCHAR14_CHENA register field. */
57336 #define ALT_USB_HOST_HCCHAR14_CHENA_WIDTH 1
57337 /* The mask used to set the ALT_USB_HOST_HCCHAR14_CHENA register field value. */
57338 #define ALT_USB_HOST_HCCHAR14_CHENA_SET_MSK 0x80000000
57339 /* The mask used to clear the ALT_USB_HOST_HCCHAR14_CHENA register field value. */
57340 #define ALT_USB_HOST_HCCHAR14_CHENA_CLR_MSK 0x7fffffff
57341 /* The reset value of the ALT_USB_HOST_HCCHAR14_CHENA register field. */
57342 #define ALT_USB_HOST_HCCHAR14_CHENA_RESET 0x0
57343 /* Extracts the ALT_USB_HOST_HCCHAR14_CHENA field value from a register. */
57344 #define ALT_USB_HOST_HCCHAR14_CHENA_GET(value) (((value) & 0x80000000) >> 31)
57345 /* Produces a ALT_USB_HOST_HCCHAR14_CHENA register field value suitable for setting the register. */
57346 #define ALT_USB_HOST_HCCHAR14_CHENA_SET(value) (((value) << 31) & 0x80000000)
57347 
57348 #ifndef __ASSEMBLY__
57349 /*
57350  * WARNING: The C register and register group struct declarations are provided for
57351  * convenience and illustrative purposes. They should, however, be used with
57352  * caution as the C language standard provides no guarantees about the alignment or
57353  * atomicity of device memory accesses. The recommended practice for writing
57354  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
57355  * alt_write_word() functions.
57356  *
57357  * The struct declaration for register ALT_USB_HOST_HCCHAR14.
57358  */
57359 struct ALT_USB_HOST_HCCHAR14_s
57360 {
57361  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR14_MPS */
57362  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR14_EPNUM */
57363  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR14_EPDIR */
57364  uint32_t : 1; /* *UNDEFINED* */
57365  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR14_LSPDDEV */
57366  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR14_EPTYPE */
57367  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR14_EC */
57368  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR14_DEVADDR */
57369  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR14_ODDFRM */
57370  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR14_CHDIS */
57371  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR14_CHENA */
57372 };
57373 
57374 /* The typedef declaration for register ALT_USB_HOST_HCCHAR14. */
57375 typedef volatile struct ALT_USB_HOST_HCCHAR14_s ALT_USB_HOST_HCCHAR14_t;
57376 #endif /* __ASSEMBLY__ */
57377 
57378 /* The reset value of the ALT_USB_HOST_HCCHAR14 register. */
57379 #define ALT_USB_HOST_HCCHAR14_RESET 0x00000000
57380 /* The byte offset of the ALT_USB_HOST_HCCHAR14 register from the beginning of the component. */
57381 #define ALT_USB_HOST_HCCHAR14_OFST 0x2c0
57382 /* The address of the ALT_USB_HOST_HCCHAR14 register. */
57383 #define ALT_USB_HOST_HCCHAR14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR14_OFST))
57384 
57385 /*
57386  * Register : hcsplt14
57387  *
57388  * Host Channel 14 Split Control Register
57389  *
57390  * Register Layout
57391  *
57392  * Bits | Access | Reset | Description
57393  * :--------|:-------|:------|:-------------------------------
57394  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT14_PRTADDR
57395  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT14_HUBADDR
57396  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT14_XACTPOS
57397  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT14_COMPSPLT
57398  * [30:17] | ??? | 0x0 | *UNDEFINED*
57399  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT14_SPLTENA
57400  *
57401  */
57402 /*
57403  * Field : prtaddr
57404  *
57405  * Port Address (PrtAddr)
57406  *
57407  * This field is the port number of the recipient transaction
57408  *
57409  * translator.
57410  *
57411  * Field Access Macros:
57412  *
57413  */
57414 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */
57415 #define ALT_USB_HOST_HCSPLT14_PRTADDR_LSB 0
57416 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */
57417 #define ALT_USB_HOST_HCSPLT14_PRTADDR_MSB 6
57418 /* The width in bits of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */
57419 #define ALT_USB_HOST_HCSPLT14_PRTADDR_WIDTH 7
57420 /* The mask used to set the ALT_USB_HOST_HCSPLT14_PRTADDR register field value. */
57421 #define ALT_USB_HOST_HCSPLT14_PRTADDR_SET_MSK 0x0000007f
57422 /* The mask used to clear the ALT_USB_HOST_HCSPLT14_PRTADDR register field value. */
57423 #define ALT_USB_HOST_HCSPLT14_PRTADDR_CLR_MSK 0xffffff80
57424 /* The reset value of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */
57425 #define ALT_USB_HOST_HCSPLT14_PRTADDR_RESET 0x0
57426 /* Extracts the ALT_USB_HOST_HCSPLT14_PRTADDR field value from a register. */
57427 #define ALT_USB_HOST_HCSPLT14_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
57428 /* Produces a ALT_USB_HOST_HCSPLT14_PRTADDR register field value suitable for setting the register. */
57429 #define ALT_USB_HOST_HCSPLT14_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
57430 
57431 /*
57432  * Field : hubaddr
57433  *
57434  * Hub Address (HubAddr)
57435  *
57436  * This field holds the device address of the transaction translator's
57437  *
57438  * hub.
57439  *
57440  * Field Access Macros:
57441  *
57442  */
57443 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */
57444 #define ALT_USB_HOST_HCSPLT14_HUBADDR_LSB 7
57445 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */
57446 #define ALT_USB_HOST_HCSPLT14_HUBADDR_MSB 13
57447 /* The width in bits of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */
57448 #define ALT_USB_HOST_HCSPLT14_HUBADDR_WIDTH 7
57449 /* The mask used to set the ALT_USB_HOST_HCSPLT14_HUBADDR register field value. */
57450 #define ALT_USB_HOST_HCSPLT14_HUBADDR_SET_MSK 0x00003f80
57451 /* The mask used to clear the ALT_USB_HOST_HCSPLT14_HUBADDR register field value. */
57452 #define ALT_USB_HOST_HCSPLT14_HUBADDR_CLR_MSK 0xffffc07f
57453 /* The reset value of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */
57454 #define ALT_USB_HOST_HCSPLT14_HUBADDR_RESET 0x0
57455 /* Extracts the ALT_USB_HOST_HCSPLT14_HUBADDR field value from a register. */
57456 #define ALT_USB_HOST_HCSPLT14_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
57457 /* Produces a ALT_USB_HOST_HCSPLT14_HUBADDR register field value suitable for setting the register. */
57458 #define ALT_USB_HOST_HCSPLT14_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
57459 
57460 /*
57461  * Field : xactpos
57462  *
57463  * Transaction Position (XactPos)
57464  *
57465  * This field is used to determine whether to send all, first, middle,
57466  *
57467  * or last payloads with each OUT transaction.
57468  *
57469  * 2'b11: All. This is the entire data payload is of this transaction
57470  *
57471  * (which is less than or equal to 188 bytes).
57472  *
57473  * 2'b10: Begin. This is the first data payload of this transaction
57474  *
57475  * (which is larger than 188 bytes).
57476  *
57477  * 2'b00: Mid. This is the middle payload of this transaction
57478  *
57479  * (which is larger than 188 bytes).
57480  *
57481  * 2'b01: End. This is the last payload of this transaction (which
57482  *
57483  * is larger than 188 bytes).
57484  *
57485  * Field Enumeration Values:
57486  *
57487  * Enum | Value | Description
57488  * :---------------------------------------|:------|:------------------------------------------------
57489  * ALT_USB_HOST_HCSPLT14_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
57490  * : | | transaction (which is larger than 188 bytes)
57491  * ALT_USB_HOST_HCSPLT14_XACTPOS_E_END | 0x1 | End. This is the last payload of this
57492  * : | | transaction (which is larger than 188 bytes)
57493  * ALT_USB_HOST_HCSPLT14_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
57494  * : | | transaction (which is larger than 188 bytes)
57495  * ALT_USB_HOST_HCSPLT14_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
57496  * : | | transaction (which is less than or equal to 188
57497  * : | | bytes)
57498  *
57499  * Field Access Macros:
57500  *
57501  */
57502 /*
57503  * Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS
57504  *
57505  * Mid. This is the middle payload of this transaction (which is larger than 188
57506  * bytes)
57507  */
57508 #define ALT_USB_HOST_HCSPLT14_XACTPOS_E_MIDDLE 0x0
57509 /*
57510  * Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS
57511  *
57512  * End. This is the last payload of this transaction (which is larger than 188
57513  * bytes)
57514  */
57515 #define ALT_USB_HOST_HCSPLT14_XACTPOS_E_END 0x1
57516 /*
57517  * Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS
57518  *
57519  * Begin. This is the first data payload of this transaction (which is larger than
57520  * 188 bytes)
57521  */
57522 #define ALT_USB_HOST_HCSPLT14_XACTPOS_E_BEGIN 0x2
57523 /*
57524  * Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS
57525  *
57526  * All. This is the entire data payload is of this transaction (which is less than
57527  * or equal to 188 bytes)
57528  */
57529 #define ALT_USB_HOST_HCSPLT14_XACTPOS_E_ALL 0x3
57530 
57531 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */
57532 #define ALT_USB_HOST_HCSPLT14_XACTPOS_LSB 14
57533 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */
57534 #define ALT_USB_HOST_HCSPLT14_XACTPOS_MSB 15
57535 /* The width in bits of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */
57536 #define ALT_USB_HOST_HCSPLT14_XACTPOS_WIDTH 2
57537 /* The mask used to set the ALT_USB_HOST_HCSPLT14_XACTPOS register field value. */
57538 #define ALT_USB_HOST_HCSPLT14_XACTPOS_SET_MSK 0x0000c000
57539 /* The mask used to clear the ALT_USB_HOST_HCSPLT14_XACTPOS register field value. */
57540 #define ALT_USB_HOST_HCSPLT14_XACTPOS_CLR_MSK 0xffff3fff
57541 /* The reset value of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */
57542 #define ALT_USB_HOST_HCSPLT14_XACTPOS_RESET 0x0
57543 /* Extracts the ALT_USB_HOST_HCSPLT14_XACTPOS field value from a register. */
57544 #define ALT_USB_HOST_HCSPLT14_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
57545 /* Produces a ALT_USB_HOST_HCSPLT14_XACTPOS register field value suitable for setting the register. */
57546 #define ALT_USB_HOST_HCSPLT14_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
57547 
57548 /*
57549  * Field : compsplt
57550  *
57551  * Do Complete Split (CompSplt)
57552  *
57553  * The application sets this field to request the OTG host to perform
57554  *
57555  * a complete split transaction.
57556  *
57557  * Field Enumeration Values:
57558  *
57559  * Enum | Value | Description
57560  * :-----------------------------------------|:------|:---------------------
57561  * ALT_USB_HOST_HCSPLT14_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
57562  * ALT_USB_HOST_HCSPLT14_COMPSPLT_E_SPLIT | 0x1 | Split transaction
57563  *
57564  * Field Access Macros:
57565  *
57566  */
57567 /*
57568  * Enumerated value for register field ALT_USB_HOST_HCSPLT14_COMPSPLT
57569  *
57570  * No split transaction
57571  */
57572 #define ALT_USB_HOST_HCSPLT14_COMPSPLT_E_NOSPLIT 0x0
57573 /*
57574  * Enumerated value for register field ALT_USB_HOST_HCSPLT14_COMPSPLT
57575  *
57576  * Split transaction
57577  */
57578 #define ALT_USB_HOST_HCSPLT14_COMPSPLT_E_SPLIT 0x1
57579 
57580 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */
57581 #define ALT_USB_HOST_HCSPLT14_COMPSPLT_LSB 16
57582 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */
57583 #define ALT_USB_HOST_HCSPLT14_COMPSPLT_MSB 16
57584 /* The width in bits of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */
57585 #define ALT_USB_HOST_HCSPLT14_COMPSPLT_WIDTH 1
57586 /* The mask used to set the ALT_USB_HOST_HCSPLT14_COMPSPLT register field value. */
57587 #define ALT_USB_HOST_HCSPLT14_COMPSPLT_SET_MSK 0x00010000
57588 /* The mask used to clear the ALT_USB_HOST_HCSPLT14_COMPSPLT register field value. */
57589 #define ALT_USB_HOST_HCSPLT14_COMPSPLT_CLR_MSK 0xfffeffff
57590 /* The reset value of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */
57591 #define ALT_USB_HOST_HCSPLT14_COMPSPLT_RESET 0x0
57592 /* Extracts the ALT_USB_HOST_HCSPLT14_COMPSPLT field value from a register. */
57593 #define ALT_USB_HOST_HCSPLT14_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
57594 /* Produces a ALT_USB_HOST_HCSPLT14_COMPSPLT register field value suitable for setting the register. */
57595 #define ALT_USB_HOST_HCSPLT14_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
57596 
57597 /*
57598  * Field : spltena
57599  *
57600  * Split Enable (SpltEna)
57601  *
57602  * The application sets this field to indicate that this channel is
57603  *
57604  * enabled to perform split transactions.
57605  *
57606  * Field Enumeration Values:
57607  *
57608  * Enum | Value | Description
57609  * :-------------------------------------|:------|:------------------
57610  * ALT_USB_HOST_HCSPLT14_SPLTENA_E_DISD | 0x0 | Split not enabled
57611  * ALT_USB_HOST_HCSPLT14_SPLTENA_E_END | 0x1 | Split enabled
57612  *
57613  * Field Access Macros:
57614  *
57615  */
57616 /*
57617  * Enumerated value for register field ALT_USB_HOST_HCSPLT14_SPLTENA
57618  *
57619  * Split not enabled
57620  */
57621 #define ALT_USB_HOST_HCSPLT14_SPLTENA_E_DISD 0x0
57622 /*
57623  * Enumerated value for register field ALT_USB_HOST_HCSPLT14_SPLTENA
57624  *
57625  * Split enabled
57626  */
57627 #define ALT_USB_HOST_HCSPLT14_SPLTENA_E_END 0x1
57628 
57629 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */
57630 #define ALT_USB_HOST_HCSPLT14_SPLTENA_LSB 31
57631 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */
57632 #define ALT_USB_HOST_HCSPLT14_SPLTENA_MSB 31
57633 /* The width in bits of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */
57634 #define ALT_USB_HOST_HCSPLT14_SPLTENA_WIDTH 1
57635 /* The mask used to set the ALT_USB_HOST_HCSPLT14_SPLTENA register field value. */
57636 #define ALT_USB_HOST_HCSPLT14_SPLTENA_SET_MSK 0x80000000
57637 /* The mask used to clear the ALT_USB_HOST_HCSPLT14_SPLTENA register field value. */
57638 #define ALT_USB_HOST_HCSPLT14_SPLTENA_CLR_MSK 0x7fffffff
57639 /* The reset value of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */
57640 #define ALT_USB_HOST_HCSPLT14_SPLTENA_RESET 0x0
57641 /* Extracts the ALT_USB_HOST_HCSPLT14_SPLTENA field value from a register. */
57642 #define ALT_USB_HOST_HCSPLT14_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
57643 /* Produces a ALT_USB_HOST_HCSPLT14_SPLTENA register field value suitable for setting the register. */
57644 #define ALT_USB_HOST_HCSPLT14_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
57645 
57646 #ifndef __ASSEMBLY__
57647 /*
57648  * WARNING: The C register and register group struct declarations are provided for
57649  * convenience and illustrative purposes. They should, however, be used with
57650  * caution as the C language standard provides no guarantees about the alignment or
57651  * atomicity of device memory accesses. The recommended practice for writing
57652  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
57653  * alt_write_word() functions.
57654  *
57655  * The struct declaration for register ALT_USB_HOST_HCSPLT14.
57656  */
57657 struct ALT_USB_HOST_HCSPLT14_s
57658 {
57659  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT14_PRTADDR */
57660  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT14_HUBADDR */
57661  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT14_XACTPOS */
57662  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT14_COMPSPLT */
57663  uint32_t : 14; /* *UNDEFINED* */
57664  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT14_SPLTENA */
57665 };
57666 
57667 /* The typedef declaration for register ALT_USB_HOST_HCSPLT14. */
57668 typedef volatile struct ALT_USB_HOST_HCSPLT14_s ALT_USB_HOST_HCSPLT14_t;
57669 #endif /* __ASSEMBLY__ */
57670 
57671 /* The reset value of the ALT_USB_HOST_HCSPLT14 register. */
57672 #define ALT_USB_HOST_HCSPLT14_RESET 0x00000000
57673 /* The byte offset of the ALT_USB_HOST_HCSPLT14 register from the beginning of the component. */
57674 #define ALT_USB_HOST_HCSPLT14_OFST 0x2c4
57675 /* The address of the ALT_USB_HOST_HCSPLT14 register. */
57676 #define ALT_USB_HOST_HCSPLT14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT14_OFST))
57677 
57678 /*
57679  * Register : hcint14
57680  *
57681  * Host Channel 14 Interrupt Register
57682  *
57683  * Register Layout
57684  *
57685  * Bits | Access | Reset | Description
57686  * :--------|:-------|:------|:---------------------------------------
57687  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT14_XFERCOMPL
57688  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT14_CHHLTD
57689  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT14_AHBERR
57690  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT14_STALL
57691  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT14_NAK
57692  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT14_ACK
57693  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT14_NYET
57694  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT14_XACTERR
57695  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT14_BBLERR
57696  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT14_FRMOVRUN
57697  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT14_DATATGLERR
57698  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT14_BNAINTR
57699  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT14_XCS_XACT_ERR
57700  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR
57701  * [31:14] | ??? | 0x0 | *UNDEFINED*
57702  *
57703  */
57704 /*
57705  * Field : xfercompl
57706  *
57707  * Transfer Completed (XferCompl)
57708  *
57709  * Transfer completed normally without any errors.This bit can be set only by the
57710  * core and the application should write 1 to clear it.
57711  *
57712  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
57713  *
57714  * completed with IOC bit set in its descriptor.
57715  *
57716  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
57717  * without
57718  *
57719  * any errors.
57720  *
57721  * Field Enumeration Values:
57722  *
57723  * Enum | Value | Description
57724  * :---------------------------------------|:------|:-----------------------------------------------
57725  * ALT_USB_HOST_HCINT14_XFERCOMPL_E_INACT | 0x0 | No transfer
57726  * ALT_USB_HOST_HCINT14_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
57727  *
57728  * Field Access Macros:
57729  *
57730  */
57731 /*
57732  * Enumerated value for register field ALT_USB_HOST_HCINT14_XFERCOMPL
57733  *
57734  * No transfer
57735  */
57736 #define ALT_USB_HOST_HCINT14_XFERCOMPL_E_INACT 0x0
57737 /*
57738  * Enumerated value for register field ALT_USB_HOST_HCINT14_XFERCOMPL
57739  *
57740  * Transfer completed normally without any errors
57741  */
57742 #define ALT_USB_HOST_HCINT14_XFERCOMPL_E_ACT 0x1
57743 
57744 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */
57745 #define ALT_USB_HOST_HCINT14_XFERCOMPL_LSB 0
57746 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */
57747 #define ALT_USB_HOST_HCINT14_XFERCOMPL_MSB 0
57748 /* The width in bits of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */
57749 #define ALT_USB_HOST_HCINT14_XFERCOMPL_WIDTH 1
57750 /* The mask used to set the ALT_USB_HOST_HCINT14_XFERCOMPL register field value. */
57751 #define ALT_USB_HOST_HCINT14_XFERCOMPL_SET_MSK 0x00000001
57752 /* The mask used to clear the ALT_USB_HOST_HCINT14_XFERCOMPL register field value. */
57753 #define ALT_USB_HOST_HCINT14_XFERCOMPL_CLR_MSK 0xfffffffe
57754 /* The reset value of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */
57755 #define ALT_USB_HOST_HCINT14_XFERCOMPL_RESET 0x0
57756 /* Extracts the ALT_USB_HOST_HCINT14_XFERCOMPL field value from a register. */
57757 #define ALT_USB_HOST_HCINT14_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
57758 /* Produces a ALT_USB_HOST_HCINT14_XFERCOMPL register field value suitable for setting the register. */
57759 #define ALT_USB_HOST_HCINT14_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
57760 
57761 /*
57762  * Field : chhltd
57763  *
57764  * Channel Halted (ChHltd)
57765  *
57766  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
57767  * either because of any USB transaction error or in response to disable request by
57768  * the application or because of a completed transfer.
57769  *
57770  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
57771  * the following
57772  *
57773  * . EOL being set in descriptor
57774  *
57775  * . AHB error
57776  *
57777  * . Excessive transaction errors
57778  *
57779  * . Babble
57780  *
57781  * . Stall
57782  *
57783  * Field Enumeration Values:
57784  *
57785  * Enum | Value | Description
57786  * :------------------------------------|:------|:-------------------
57787  * ALT_USB_HOST_HCINT14_CHHLTD_E_INACT | 0x0 | Channel not halted
57788  * ALT_USB_HOST_HCINT14_CHHLTD_E_ACT | 0x1 | Channel Halted
57789  *
57790  * Field Access Macros:
57791  *
57792  */
57793 /*
57794  * Enumerated value for register field ALT_USB_HOST_HCINT14_CHHLTD
57795  *
57796  * Channel not halted
57797  */
57798 #define ALT_USB_HOST_HCINT14_CHHLTD_E_INACT 0x0
57799 /*
57800  * Enumerated value for register field ALT_USB_HOST_HCINT14_CHHLTD
57801  *
57802  * Channel Halted
57803  */
57804 #define ALT_USB_HOST_HCINT14_CHHLTD_E_ACT 0x1
57805 
57806 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_CHHLTD register field. */
57807 #define ALT_USB_HOST_HCINT14_CHHLTD_LSB 1
57808 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_CHHLTD register field. */
57809 #define ALT_USB_HOST_HCINT14_CHHLTD_MSB 1
57810 /* The width in bits of the ALT_USB_HOST_HCINT14_CHHLTD register field. */
57811 #define ALT_USB_HOST_HCINT14_CHHLTD_WIDTH 1
57812 /* The mask used to set the ALT_USB_HOST_HCINT14_CHHLTD register field value. */
57813 #define ALT_USB_HOST_HCINT14_CHHLTD_SET_MSK 0x00000002
57814 /* The mask used to clear the ALT_USB_HOST_HCINT14_CHHLTD register field value. */
57815 #define ALT_USB_HOST_HCINT14_CHHLTD_CLR_MSK 0xfffffffd
57816 /* The reset value of the ALT_USB_HOST_HCINT14_CHHLTD register field. */
57817 #define ALT_USB_HOST_HCINT14_CHHLTD_RESET 0x0
57818 /* Extracts the ALT_USB_HOST_HCINT14_CHHLTD field value from a register. */
57819 #define ALT_USB_HOST_HCINT14_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
57820 /* Produces a ALT_USB_HOST_HCINT14_CHHLTD register field value suitable for setting the register. */
57821 #define ALT_USB_HOST_HCINT14_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
57822 
57823 /*
57824  * Field : ahberr
57825  *
57826  * AHB Error (AHBErr)
57827  *
57828  * This is generated only in Internal DMA mode when there is an
57829  *
57830  * AHB error during AHB read/write. The application can read the
57831  *
57832  * corresponding channel's DMA address register to get the error
57833  *
57834  * address.
57835  *
57836  * Field Enumeration Values:
57837  *
57838  * Enum | Value | Description
57839  * :------------------------------------|:------|:--------------------------------
57840  * ALT_USB_HOST_HCINT14_AHBERR_E_INACT | 0x0 | No AHB error
57841  * ALT_USB_HOST_HCINT14_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
57842  *
57843  * Field Access Macros:
57844  *
57845  */
57846 /*
57847  * Enumerated value for register field ALT_USB_HOST_HCINT14_AHBERR
57848  *
57849  * No AHB error
57850  */
57851 #define ALT_USB_HOST_HCINT14_AHBERR_E_INACT 0x0
57852 /*
57853  * Enumerated value for register field ALT_USB_HOST_HCINT14_AHBERR
57854  *
57855  * AHB error during AHB read/write
57856  */
57857 #define ALT_USB_HOST_HCINT14_AHBERR_E_ACT 0x1
57858 
57859 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_AHBERR register field. */
57860 #define ALT_USB_HOST_HCINT14_AHBERR_LSB 2
57861 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_AHBERR register field. */
57862 #define ALT_USB_HOST_HCINT14_AHBERR_MSB 2
57863 /* The width in bits of the ALT_USB_HOST_HCINT14_AHBERR register field. */
57864 #define ALT_USB_HOST_HCINT14_AHBERR_WIDTH 1
57865 /* The mask used to set the ALT_USB_HOST_HCINT14_AHBERR register field value. */
57866 #define ALT_USB_HOST_HCINT14_AHBERR_SET_MSK 0x00000004
57867 /* The mask used to clear the ALT_USB_HOST_HCINT14_AHBERR register field value. */
57868 #define ALT_USB_HOST_HCINT14_AHBERR_CLR_MSK 0xfffffffb
57869 /* The reset value of the ALT_USB_HOST_HCINT14_AHBERR register field. */
57870 #define ALT_USB_HOST_HCINT14_AHBERR_RESET 0x0
57871 /* Extracts the ALT_USB_HOST_HCINT14_AHBERR field value from a register. */
57872 #define ALT_USB_HOST_HCINT14_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
57873 /* Produces a ALT_USB_HOST_HCINT14_AHBERR register field value suitable for setting the register. */
57874 #define ALT_USB_HOST_HCINT14_AHBERR_SET(value) (((value) << 2) & 0x00000004)
57875 
57876 /*
57877  * Field : stall
57878  *
57879  * STALL Response Received Interrupt (STALL)
57880  *
57881  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
57882  *
57883  * in the core.This bit can be set only by the core and the application should
57884  * write 1 to clear
57885  *
57886  * it.
57887  *
57888  * Field Enumeration Values:
57889  *
57890  * Enum | Value | Description
57891  * :-----------------------------------|:------|:-------------------
57892  * ALT_USB_HOST_HCINT14_STALL_E_INACT | 0x0 | No Stall Interrupt
57893  * ALT_USB_HOST_HCINT14_STALL_E_ACT | 0x1 | Stall Interrupt
57894  *
57895  * Field Access Macros:
57896  *
57897  */
57898 /*
57899  * Enumerated value for register field ALT_USB_HOST_HCINT14_STALL
57900  *
57901  * No Stall Interrupt
57902  */
57903 #define ALT_USB_HOST_HCINT14_STALL_E_INACT 0x0
57904 /*
57905  * Enumerated value for register field ALT_USB_HOST_HCINT14_STALL
57906  *
57907  * Stall Interrupt
57908  */
57909 #define ALT_USB_HOST_HCINT14_STALL_E_ACT 0x1
57910 
57911 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_STALL register field. */
57912 #define ALT_USB_HOST_HCINT14_STALL_LSB 3
57913 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_STALL register field. */
57914 #define ALT_USB_HOST_HCINT14_STALL_MSB 3
57915 /* The width in bits of the ALT_USB_HOST_HCINT14_STALL register field. */
57916 #define ALT_USB_HOST_HCINT14_STALL_WIDTH 1
57917 /* The mask used to set the ALT_USB_HOST_HCINT14_STALL register field value. */
57918 #define ALT_USB_HOST_HCINT14_STALL_SET_MSK 0x00000008
57919 /* The mask used to clear the ALT_USB_HOST_HCINT14_STALL register field value. */
57920 #define ALT_USB_HOST_HCINT14_STALL_CLR_MSK 0xfffffff7
57921 /* The reset value of the ALT_USB_HOST_HCINT14_STALL register field. */
57922 #define ALT_USB_HOST_HCINT14_STALL_RESET 0x0
57923 /* Extracts the ALT_USB_HOST_HCINT14_STALL field value from a register. */
57924 #define ALT_USB_HOST_HCINT14_STALL_GET(value) (((value) & 0x00000008) >> 3)
57925 /* Produces a ALT_USB_HOST_HCINT14_STALL register field value suitable for setting the register. */
57926 #define ALT_USB_HOST_HCINT14_STALL_SET(value) (((value) << 3) & 0x00000008)
57927 
57928 /*
57929  * Field : nak
57930  *
57931  * NAK Response Received Interrupt (NAK)
57932  *
57933  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
57934  *
57935  * in the core.This bit can be set only by the core and the application should
57936  * write 1 to clear
57937  *
57938  * it.
57939  *
57940  * Field Enumeration Values:
57941  *
57942  * Enum | Value | Description
57943  * :---------------------------------|:------|:-----------------------------------
57944  * ALT_USB_HOST_HCINT14_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
57945  * ALT_USB_HOST_HCINT14_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
57946  *
57947  * Field Access Macros:
57948  *
57949  */
57950 /*
57951  * Enumerated value for register field ALT_USB_HOST_HCINT14_NAK
57952  *
57953  * No NAK Response Received Interrupt
57954  */
57955 #define ALT_USB_HOST_HCINT14_NAK_E_INACT 0x0
57956 /*
57957  * Enumerated value for register field ALT_USB_HOST_HCINT14_NAK
57958  *
57959  * NAK Response Received Interrupt
57960  */
57961 #define ALT_USB_HOST_HCINT14_NAK_E_ACT 0x1
57962 
57963 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_NAK register field. */
57964 #define ALT_USB_HOST_HCINT14_NAK_LSB 4
57965 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_NAK register field. */
57966 #define ALT_USB_HOST_HCINT14_NAK_MSB 4
57967 /* The width in bits of the ALT_USB_HOST_HCINT14_NAK register field. */
57968 #define ALT_USB_HOST_HCINT14_NAK_WIDTH 1
57969 /* The mask used to set the ALT_USB_HOST_HCINT14_NAK register field value. */
57970 #define ALT_USB_HOST_HCINT14_NAK_SET_MSK 0x00000010
57971 /* The mask used to clear the ALT_USB_HOST_HCINT14_NAK register field value. */
57972 #define ALT_USB_HOST_HCINT14_NAK_CLR_MSK 0xffffffef
57973 /* The reset value of the ALT_USB_HOST_HCINT14_NAK register field. */
57974 #define ALT_USB_HOST_HCINT14_NAK_RESET 0x0
57975 /* Extracts the ALT_USB_HOST_HCINT14_NAK field value from a register. */
57976 #define ALT_USB_HOST_HCINT14_NAK_GET(value) (((value) & 0x00000010) >> 4)
57977 /* Produces a ALT_USB_HOST_HCINT14_NAK register field value suitable for setting the register. */
57978 #define ALT_USB_HOST_HCINT14_NAK_SET(value) (((value) << 4) & 0x00000010)
57979 
57980 /*
57981  * Field : ack
57982  *
57983  * ACK Response Received/Transmitted Interrupt (ACK)
57984  *
57985  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
57986  *
57987  * in the core.This bit can be set only by the core and the application should
57988  * write 1 to clear
57989  *
57990  * it.
57991  *
57992  * Field Enumeration Values:
57993  *
57994  * Enum | Value | Description
57995  * :---------------------------------|:------|:-----------------------------------------------
57996  * ALT_USB_HOST_HCINT14_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
57997  * ALT_USB_HOST_HCINT14_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
57998  *
57999  * Field Access Macros:
58000  *
58001  */
58002 /*
58003  * Enumerated value for register field ALT_USB_HOST_HCINT14_ACK
58004  *
58005  * No ACK Response Received Transmitted Interrupt
58006  */
58007 #define ALT_USB_HOST_HCINT14_ACK_E_INACT 0x0
58008 /*
58009  * Enumerated value for register field ALT_USB_HOST_HCINT14_ACK
58010  *
58011  * ACK Response Received Transmitted Interrup
58012  */
58013 #define ALT_USB_HOST_HCINT14_ACK_E_ACT 0x1
58014 
58015 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_ACK register field. */
58016 #define ALT_USB_HOST_HCINT14_ACK_LSB 5
58017 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_ACK register field. */
58018 #define ALT_USB_HOST_HCINT14_ACK_MSB 5
58019 /* The width in bits of the ALT_USB_HOST_HCINT14_ACK register field. */
58020 #define ALT_USB_HOST_HCINT14_ACK_WIDTH 1
58021 /* The mask used to set the ALT_USB_HOST_HCINT14_ACK register field value. */
58022 #define ALT_USB_HOST_HCINT14_ACK_SET_MSK 0x00000020
58023 /* The mask used to clear the ALT_USB_HOST_HCINT14_ACK register field value. */
58024 #define ALT_USB_HOST_HCINT14_ACK_CLR_MSK 0xffffffdf
58025 /* The reset value of the ALT_USB_HOST_HCINT14_ACK register field. */
58026 #define ALT_USB_HOST_HCINT14_ACK_RESET 0x0
58027 /* Extracts the ALT_USB_HOST_HCINT14_ACK field value from a register. */
58028 #define ALT_USB_HOST_HCINT14_ACK_GET(value) (((value) & 0x00000020) >> 5)
58029 /* Produces a ALT_USB_HOST_HCINT14_ACK register field value suitable for setting the register. */
58030 #define ALT_USB_HOST_HCINT14_ACK_SET(value) (((value) << 5) & 0x00000020)
58031 
58032 /*
58033  * Field : nyet
58034  *
58035  * NYET Response Received Interrupt (NYET)
58036  *
58037  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
58038  *
58039  * in the core.This bit can be set only by the core and the application should
58040  * write 1 to clear
58041  *
58042  * it.
58043  *
58044  * Field Enumeration Values:
58045  *
58046  * Enum | Value | Description
58047  * :----------------------------------|:------|:------------------------------------
58048  * ALT_USB_HOST_HCINT14_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
58049  * ALT_USB_HOST_HCINT14_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
58050  *
58051  * Field Access Macros:
58052  *
58053  */
58054 /*
58055  * Enumerated value for register field ALT_USB_HOST_HCINT14_NYET
58056  *
58057  * No NYET Response Received Interrupt
58058  */
58059 #define ALT_USB_HOST_HCINT14_NYET_E_INACT 0x0
58060 /*
58061  * Enumerated value for register field ALT_USB_HOST_HCINT14_NYET
58062  *
58063  * NYET Response Received Interrupt
58064  */
58065 #define ALT_USB_HOST_HCINT14_NYET_E_ACT 0x1
58066 
58067 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_NYET register field. */
58068 #define ALT_USB_HOST_HCINT14_NYET_LSB 6
58069 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_NYET register field. */
58070 #define ALT_USB_HOST_HCINT14_NYET_MSB 6
58071 /* The width in bits of the ALT_USB_HOST_HCINT14_NYET register field. */
58072 #define ALT_USB_HOST_HCINT14_NYET_WIDTH 1
58073 /* The mask used to set the ALT_USB_HOST_HCINT14_NYET register field value. */
58074 #define ALT_USB_HOST_HCINT14_NYET_SET_MSK 0x00000040
58075 /* The mask used to clear the ALT_USB_HOST_HCINT14_NYET register field value. */
58076 #define ALT_USB_HOST_HCINT14_NYET_CLR_MSK 0xffffffbf
58077 /* The reset value of the ALT_USB_HOST_HCINT14_NYET register field. */
58078 #define ALT_USB_HOST_HCINT14_NYET_RESET 0x0
58079 /* Extracts the ALT_USB_HOST_HCINT14_NYET field value from a register. */
58080 #define ALT_USB_HOST_HCINT14_NYET_GET(value) (((value) & 0x00000040) >> 6)
58081 /* Produces a ALT_USB_HOST_HCINT14_NYET register field value suitable for setting the register. */
58082 #define ALT_USB_HOST_HCINT14_NYET_SET(value) (((value) << 6) & 0x00000040)
58083 
58084 /*
58085  * Field : xacterr
58086  *
58087  * Transaction Error (XactErr)
58088  *
58089  * Indicates one of the following errors occurred on the USB.
58090  *
58091  * CRC check failure
58092  *
58093  * Timeout
58094  *
58095  * Bit stuff error
58096  *
58097  * False EOP
58098  *
58099  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
58100  *
58101  * in the core.This bit can be set only by the core and the application should
58102  * write 1 to clear
58103  *
58104  * it.
58105  *
58106  * Field Enumeration Values:
58107  *
58108  * Enum | Value | Description
58109  * :-------------------------------------|:------|:---------------------
58110  * ALT_USB_HOST_HCINT14_XACTERR_E_INACT | 0x0 | No Transaction Error
58111  * ALT_USB_HOST_HCINT14_XACTERR_E_ACT | 0x1 | Transaction Error
58112  *
58113  * Field Access Macros:
58114  *
58115  */
58116 /*
58117  * Enumerated value for register field ALT_USB_HOST_HCINT14_XACTERR
58118  *
58119  * No Transaction Error
58120  */
58121 #define ALT_USB_HOST_HCINT14_XACTERR_E_INACT 0x0
58122 /*
58123  * Enumerated value for register field ALT_USB_HOST_HCINT14_XACTERR
58124  *
58125  * Transaction Error
58126  */
58127 #define ALT_USB_HOST_HCINT14_XACTERR_E_ACT 0x1
58128 
58129 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_XACTERR register field. */
58130 #define ALT_USB_HOST_HCINT14_XACTERR_LSB 7
58131 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_XACTERR register field. */
58132 #define ALT_USB_HOST_HCINT14_XACTERR_MSB 7
58133 /* The width in bits of the ALT_USB_HOST_HCINT14_XACTERR register field. */
58134 #define ALT_USB_HOST_HCINT14_XACTERR_WIDTH 1
58135 /* The mask used to set the ALT_USB_HOST_HCINT14_XACTERR register field value. */
58136 #define ALT_USB_HOST_HCINT14_XACTERR_SET_MSK 0x00000080
58137 /* The mask used to clear the ALT_USB_HOST_HCINT14_XACTERR register field value. */
58138 #define ALT_USB_HOST_HCINT14_XACTERR_CLR_MSK 0xffffff7f
58139 /* The reset value of the ALT_USB_HOST_HCINT14_XACTERR register field. */
58140 #define ALT_USB_HOST_HCINT14_XACTERR_RESET 0x0
58141 /* Extracts the ALT_USB_HOST_HCINT14_XACTERR field value from a register. */
58142 #define ALT_USB_HOST_HCINT14_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
58143 /* Produces a ALT_USB_HOST_HCINT14_XACTERR register field value suitable for setting the register. */
58144 #define ALT_USB_HOST_HCINT14_XACTERR_SET(value) (((value) << 7) & 0x00000080)
58145 
58146 /*
58147  * Field : bblerr
58148  *
58149  * Babble Error (BblErr)
58150  *
58151  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
58152  *
58153  * in the core..This bit can be set only by the core and the application should
58154  * write 1 to clear
58155  *
58156  * it.
58157  *
58158  * Field Enumeration Values:
58159  *
58160  * Enum | Value | Description
58161  * :------------------------------------|:------|:----------------
58162  * ALT_USB_HOST_HCINT14_BBLERR_E_INACT | 0x0 | No Babble Error
58163  * ALT_USB_HOST_HCINT14_BBLERR_E_ACT | 0x1 | Babble Error
58164  *
58165  * Field Access Macros:
58166  *
58167  */
58168 /*
58169  * Enumerated value for register field ALT_USB_HOST_HCINT14_BBLERR
58170  *
58171  * No Babble Error
58172  */
58173 #define ALT_USB_HOST_HCINT14_BBLERR_E_INACT 0x0
58174 /*
58175  * Enumerated value for register field ALT_USB_HOST_HCINT14_BBLERR
58176  *
58177  * Babble Error
58178  */
58179 #define ALT_USB_HOST_HCINT14_BBLERR_E_ACT 0x1
58180 
58181 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_BBLERR register field. */
58182 #define ALT_USB_HOST_HCINT14_BBLERR_LSB 8
58183 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_BBLERR register field. */
58184 #define ALT_USB_HOST_HCINT14_BBLERR_MSB 8
58185 /* The width in bits of the ALT_USB_HOST_HCINT14_BBLERR register field. */
58186 #define ALT_USB_HOST_HCINT14_BBLERR_WIDTH 1
58187 /* The mask used to set the ALT_USB_HOST_HCINT14_BBLERR register field value. */
58188 #define ALT_USB_HOST_HCINT14_BBLERR_SET_MSK 0x00000100
58189 /* The mask used to clear the ALT_USB_HOST_HCINT14_BBLERR register field value. */
58190 #define ALT_USB_HOST_HCINT14_BBLERR_CLR_MSK 0xfffffeff
58191 /* The reset value of the ALT_USB_HOST_HCINT14_BBLERR register field. */
58192 #define ALT_USB_HOST_HCINT14_BBLERR_RESET 0x0
58193 /* Extracts the ALT_USB_HOST_HCINT14_BBLERR field value from a register. */
58194 #define ALT_USB_HOST_HCINT14_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
58195 /* Produces a ALT_USB_HOST_HCINT14_BBLERR register field value suitable for setting the register. */
58196 #define ALT_USB_HOST_HCINT14_BBLERR_SET(value) (((value) << 8) & 0x00000100)
58197 
58198 /*
58199  * Field : frmovrun
58200  *
58201  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
58202  * bit is masked
58203  *
58204  * in the core.This bit can be set only by the core and the application should
58205  * write 1 to clear
58206  *
58207  * it.
58208  *
58209  * Field Enumeration Values:
58210  *
58211  * Enum | Value | Description
58212  * :--------------------------------------|:------|:-----------------
58213  * ALT_USB_HOST_HCINT14_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
58214  * ALT_USB_HOST_HCINT14_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
58215  *
58216  * Field Access Macros:
58217  *
58218  */
58219 /*
58220  * Enumerated value for register field ALT_USB_HOST_HCINT14_FRMOVRUN
58221  *
58222  * No Frame Overrun
58223  */
58224 #define ALT_USB_HOST_HCINT14_FRMOVRUN_E_INACT 0x0
58225 /*
58226  * Enumerated value for register field ALT_USB_HOST_HCINT14_FRMOVRUN
58227  *
58228  * Frame Overrun
58229  */
58230 #define ALT_USB_HOST_HCINT14_FRMOVRUN_E_ACT 0x1
58231 
58232 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */
58233 #define ALT_USB_HOST_HCINT14_FRMOVRUN_LSB 9
58234 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */
58235 #define ALT_USB_HOST_HCINT14_FRMOVRUN_MSB 9
58236 /* The width in bits of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */
58237 #define ALT_USB_HOST_HCINT14_FRMOVRUN_WIDTH 1
58238 /* The mask used to set the ALT_USB_HOST_HCINT14_FRMOVRUN register field value. */
58239 #define ALT_USB_HOST_HCINT14_FRMOVRUN_SET_MSK 0x00000200
58240 /* The mask used to clear the ALT_USB_HOST_HCINT14_FRMOVRUN register field value. */
58241 #define ALT_USB_HOST_HCINT14_FRMOVRUN_CLR_MSK 0xfffffdff
58242 /* The reset value of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */
58243 #define ALT_USB_HOST_HCINT14_FRMOVRUN_RESET 0x0
58244 /* Extracts the ALT_USB_HOST_HCINT14_FRMOVRUN field value from a register. */
58245 #define ALT_USB_HOST_HCINT14_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
58246 /* Produces a ALT_USB_HOST_HCINT14_FRMOVRUN register field value suitable for setting the register. */
58247 #define ALT_USB_HOST_HCINT14_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
58248 
58249 /*
58250  * Field : datatglerr
58251  *
58252  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
58253  * application should write 1 to clear
58254  *
58255  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
58256  *
58257  * in the core.
58258  *
58259  * Field Enumeration Values:
58260  *
58261  * Enum | Value | Description
58262  * :----------------------------------------|:------|:---------------------
58263  * ALT_USB_HOST_HCINT14_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
58264  * ALT_USB_HOST_HCINT14_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
58265  *
58266  * Field Access Macros:
58267  *
58268  */
58269 /*
58270  * Enumerated value for register field ALT_USB_HOST_HCINT14_DATATGLERR
58271  *
58272  * No Data Toggle Error
58273  */
58274 #define ALT_USB_HOST_HCINT14_DATATGLERR_E_INACT 0x0
58275 /*
58276  * Enumerated value for register field ALT_USB_HOST_HCINT14_DATATGLERR
58277  *
58278  * Data Toggle Error
58279  */
58280 #define ALT_USB_HOST_HCINT14_DATATGLERR_E_ACT 0x1
58281 
58282 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */
58283 #define ALT_USB_HOST_HCINT14_DATATGLERR_LSB 10
58284 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */
58285 #define ALT_USB_HOST_HCINT14_DATATGLERR_MSB 10
58286 /* The width in bits of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */
58287 #define ALT_USB_HOST_HCINT14_DATATGLERR_WIDTH 1
58288 /* The mask used to set the ALT_USB_HOST_HCINT14_DATATGLERR register field value. */
58289 #define ALT_USB_HOST_HCINT14_DATATGLERR_SET_MSK 0x00000400
58290 /* The mask used to clear the ALT_USB_HOST_HCINT14_DATATGLERR register field value. */
58291 #define ALT_USB_HOST_HCINT14_DATATGLERR_CLR_MSK 0xfffffbff
58292 /* The reset value of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */
58293 #define ALT_USB_HOST_HCINT14_DATATGLERR_RESET 0x0
58294 /* Extracts the ALT_USB_HOST_HCINT14_DATATGLERR field value from a register. */
58295 #define ALT_USB_HOST_HCINT14_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
58296 /* Produces a ALT_USB_HOST_HCINT14_DATATGLERR register field value suitable for setting the register. */
58297 #define ALT_USB_HOST_HCINT14_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
58298 
58299 /*
58300  * Field : bnaintr
58301  *
58302  * BNA (Buffer Not Available) Interrupt (BNAIntr)
58303  *
58304  * This bit is valid only when Scatter/Gather DMA mode is enabled.
58305  *
58306  * The core generates this interrupt when the descriptor accessed
58307  *
58308  * is not ready for the Core to process. BNA will not be generated
58309  *
58310  * for Isochronous channels.
58311  *
58312  * For non Scatter/Gather DMA mode, this bit is reserved.
58313  *
58314  * Field Enumeration Values:
58315  *
58316  * Enum | Value | Description
58317  * :-------------------------------------|:------|:-----------------
58318  * ALT_USB_HOST_HCINT14_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
58319  * ALT_USB_HOST_HCINT14_BNAINTR_E_ACT | 0x1 | BNA Interrupt
58320  *
58321  * Field Access Macros:
58322  *
58323  */
58324 /*
58325  * Enumerated value for register field ALT_USB_HOST_HCINT14_BNAINTR
58326  *
58327  * No BNA Interrupt
58328  */
58329 #define ALT_USB_HOST_HCINT14_BNAINTR_E_INACT 0x0
58330 /*
58331  * Enumerated value for register field ALT_USB_HOST_HCINT14_BNAINTR
58332  *
58333  * BNA Interrupt
58334  */
58335 #define ALT_USB_HOST_HCINT14_BNAINTR_E_ACT 0x1
58336 
58337 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_BNAINTR register field. */
58338 #define ALT_USB_HOST_HCINT14_BNAINTR_LSB 11
58339 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_BNAINTR register field. */
58340 #define ALT_USB_HOST_HCINT14_BNAINTR_MSB 11
58341 /* The width in bits of the ALT_USB_HOST_HCINT14_BNAINTR register field. */
58342 #define ALT_USB_HOST_HCINT14_BNAINTR_WIDTH 1
58343 /* The mask used to set the ALT_USB_HOST_HCINT14_BNAINTR register field value. */
58344 #define ALT_USB_HOST_HCINT14_BNAINTR_SET_MSK 0x00000800
58345 /* The mask used to clear the ALT_USB_HOST_HCINT14_BNAINTR register field value. */
58346 #define ALT_USB_HOST_HCINT14_BNAINTR_CLR_MSK 0xfffff7ff
58347 /* The reset value of the ALT_USB_HOST_HCINT14_BNAINTR register field. */
58348 #define ALT_USB_HOST_HCINT14_BNAINTR_RESET 0x0
58349 /* Extracts the ALT_USB_HOST_HCINT14_BNAINTR field value from a register. */
58350 #define ALT_USB_HOST_HCINT14_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
58351 /* Produces a ALT_USB_HOST_HCINT14_BNAINTR register field value suitable for setting the register. */
58352 #define ALT_USB_HOST_HCINT14_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
58353 
58354 /*
58355  * Field : xcs_xact_err
58356  *
58357  * Excessive Transaction Error (XCS_XACT_ERR)
58358  *
58359  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
58360  * this bit
58361  *
58362  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
58363  *
58364  * not be generated for Isochronous channels.
58365  *
58366  * For non Scatter/Gather DMA mode, this bit is reserved.
58367  *
58368  * Field Enumeration Values:
58369  *
58370  * Enum | Value | Description
58371  * :--------------------------------------------|:------|:-------------------------------
58372  * ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
58373  * ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
58374  *
58375  * Field Access Macros:
58376  *
58377  */
58378 /*
58379  * Enumerated value for register field ALT_USB_HOST_HCINT14_XCS_XACT_ERR
58380  *
58381  * No Excessive Transaction Error
58382  */
58383 #define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_INACT 0x0
58384 /*
58385  * Enumerated value for register field ALT_USB_HOST_HCINT14_XCS_XACT_ERR
58386  *
58387  * Excessive Transaction Error
58388  */
58389 #define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_ACVTIVE 0x1
58390 
58391 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */
58392 #define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_LSB 12
58393 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */
58394 #define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_MSB 12
58395 /* The width in bits of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */
58396 #define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_WIDTH 1
58397 /* The mask used to set the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field value. */
58398 #define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_SET_MSK 0x00001000
58399 /* The mask used to clear the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field value. */
58400 #define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_CLR_MSK 0xffffefff
58401 /* The reset value of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */
58402 #define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_RESET 0x0
58403 /* Extracts the ALT_USB_HOST_HCINT14_XCS_XACT_ERR field value from a register. */
58404 #define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
58405 /* Produces a ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field value suitable for setting the register. */
58406 #define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
58407 
58408 /*
58409  * Field : desc_lst_rollintr
58410  *
58411  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
58412  *
58413  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
58414  * this bit
58415  *
58416  * when the corresponding channel's descriptor list rolls over.
58417  *
58418  * For non Scatter/Gather DMA mode, this bit is reserved.
58419  *
58420  * Field Enumeration Values:
58421  *
58422  * Enum | Value | Description
58423  * :-----------------------------------------------|:------|:---------------------------------
58424  * ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
58425  * ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
58426  *
58427  * Field Access Macros:
58428  *
58429  */
58430 /*
58431  * Enumerated value for register field ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR
58432  *
58433  * No Descriptor rollover interrupt
58434  */
58435 #define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_INACT 0x0
58436 /*
58437  * Enumerated value for register field ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR
58438  *
58439  * Descriptor rollover interrupt
58440  */
58441 #define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_ACT 0x1
58442 
58443 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */
58444 #define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_LSB 13
58445 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */
58446 #define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_MSB 13
58447 /* The width in bits of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */
58448 #define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_WIDTH 1
58449 /* The mask used to set the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field value. */
58450 #define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_SET_MSK 0x00002000
58451 /* The mask used to clear the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field value. */
58452 #define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
58453 /* The reset value of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */
58454 #define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_RESET 0x0
58455 /* Extracts the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR field value from a register. */
58456 #define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
58457 /* Produces a ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field value suitable for setting the register. */
58458 #define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
58459 
58460 #ifndef __ASSEMBLY__
58461 /*
58462  * WARNING: The C register and register group struct declarations are provided for
58463  * convenience and illustrative purposes. They should, however, be used with
58464  * caution as the C language standard provides no guarantees about the alignment or
58465  * atomicity of device memory accesses. The recommended practice for writing
58466  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58467  * alt_write_word() functions.
58468  *
58469  * The struct declaration for register ALT_USB_HOST_HCINT14.
58470  */
58471 struct ALT_USB_HOST_HCINT14_s
58472 {
58473  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT14_XFERCOMPL */
58474  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT14_CHHLTD */
58475  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT14_AHBERR */
58476  uint32_t stall : 1; /* ALT_USB_HOST_HCINT14_STALL */
58477  uint32_t nak : 1; /* ALT_USB_HOST_HCINT14_NAK */
58478  uint32_t ack : 1; /* ALT_USB_HOST_HCINT14_ACK */
58479  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT14_NYET */
58480  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT14_XACTERR */
58481  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT14_BBLERR */
58482  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT14_FRMOVRUN */
58483  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT14_DATATGLERR */
58484  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT14_BNAINTR */
58485  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT14_XCS_XACT_ERR */
58486  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR */
58487  uint32_t : 18; /* *UNDEFINED* */
58488 };
58489 
58490 /* The typedef declaration for register ALT_USB_HOST_HCINT14. */
58491 typedef volatile struct ALT_USB_HOST_HCINT14_s ALT_USB_HOST_HCINT14_t;
58492 #endif /* __ASSEMBLY__ */
58493 
58494 /* The reset value of the ALT_USB_HOST_HCINT14 register. */
58495 #define ALT_USB_HOST_HCINT14_RESET 0x00000000
58496 /* The byte offset of the ALT_USB_HOST_HCINT14 register from the beginning of the component. */
58497 #define ALT_USB_HOST_HCINT14_OFST 0x2c8
58498 /* The address of the ALT_USB_HOST_HCINT14 register. */
58499 #define ALT_USB_HOST_HCINT14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT14_OFST))
58500 
58501 /*
58502  * Register : hcintmsk14
58503  *
58504  * Host Channel 14 Interrupt Mask Register
58505  *
58506  * Register Layout
58507  *
58508  * Bits | Access | Reset | Description
58509  * :--------|:-------|:------|:--------------------------------------------
58510  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK
58511  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_CHHLTDMSK
58512  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_AHBERRMSK
58513  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_STALLMSK
58514  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_NAKMSK
58515  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_ACKMSK
58516  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_NYETMSK
58517  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_XACTERRMSK
58518  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_BBLERRMSK
58519  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK
58520  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK
58521  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_BNAINTRMSK
58522  * [12] | ??? | 0x0 | *UNDEFINED*
58523  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK
58524  * [31:14] | ??? | 0x0 | *UNDEFINED*
58525  *
58526  */
58527 /*
58528  * Field : xfercomplmsk
58529  *
58530  * Transfer Completed Mask (XferComplMsk)
58531  *
58532  * Field Enumeration Values:
58533  *
58534  * Enum | Value | Description
58535  * :---------------------------------------------|:------|:------------
58536  * ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_MSK | 0x0 | Mask
58537  * ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
58538  *
58539  * Field Access Macros:
58540  *
58541  */
58542 /*
58543  * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK
58544  *
58545  * Mask
58546  */
58547 #define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_MSK 0x0
58548 /*
58549  * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK
58550  *
58551  * No mask
58552  */
58553 #define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_NOMSK 0x1
58554 
58555 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */
58556 #define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_LSB 0
58557 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */
58558 #define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_MSB 0
58559 /* The width in bits of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */
58560 #define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_WIDTH 1
58561 /* The mask used to set the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field value. */
58562 #define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_SET_MSK 0x00000001
58563 /* The mask used to clear the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field value. */
58564 #define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_CLR_MSK 0xfffffffe
58565 /* The reset value of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */
58566 #define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_RESET 0x0
58567 /* Extracts the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK field value from a register. */
58568 #define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
58569 /* Produces a ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field value suitable for setting the register. */
58570 #define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
58571 
58572 /*
58573  * Field : chhltdmsk
58574  *
58575  * Channel Halted Mask (ChHltdMsk)
58576  *
58577  * Field Enumeration Values:
58578  *
58579  * Enum | Value | Description
58580  * :------------------------------------------|:------|:------------
58581  * ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_MSK | 0x0 | Mask
58582  * ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_NOMSK | 0x1 | No mask
58583  *
58584  * Field Access Macros:
58585  *
58586  */
58587 /*
58588  * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_CHHLTDMSK
58589  *
58590  * Mask
58591  */
58592 #define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_MSK 0x0
58593 /*
58594  * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_CHHLTDMSK
58595  *
58596  * No mask
58597  */
58598 #define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_NOMSK 0x1
58599 
58600 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */
58601 #define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_LSB 1
58602 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */
58603 #define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_MSB 1
58604 /* The width in bits of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */
58605 #define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_WIDTH 1
58606 /* The mask used to set the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field value. */
58607 #define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_SET_MSK 0x00000002
58608 /* The mask used to clear the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field value. */
58609 #define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_CLR_MSK 0xfffffffd
58610 /* The reset value of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */
58611 #define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_RESET 0x0
58612 /* Extracts the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK field value from a register. */
58613 #define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
58614 /* Produces a ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field value suitable for setting the register. */
58615 #define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
58616 
58617 /*
58618  * Field : ahberrmsk
58619  *
58620  * AHB Error Mask (AHBErrMsk)
58621  *
58622  * In scatter/gather DMA mode for host,
58623  *
58624  * interrupts will not be generated due to the corresponding bits set in
58625  *
58626  * HCINTn.
58627  *
58628  * Field Enumeration Values:
58629  *
58630  * Enum | Value | Description
58631  * :------------------------------------------|:------|:------------
58632  * ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_MSK | 0x0 | Mask
58633  * ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_NOMSK | 0x1 | No mask
58634  *
58635  * Field Access Macros:
58636  *
58637  */
58638 /*
58639  * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_AHBERRMSK
58640  *
58641  * Mask
58642  */
58643 #define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_MSK 0x0
58644 /*
58645  * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_AHBERRMSK
58646  *
58647  * No mask
58648  */
58649 #define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_NOMSK 0x1
58650 
58651 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */
58652 #define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_LSB 2
58653 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */
58654 #define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_MSB 2
58655 /* The width in bits of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */
58656 #define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_WIDTH 1
58657 /* The mask used to set the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field value. */
58658 #define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_SET_MSK 0x00000004
58659 /* The mask used to clear the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field value. */
58660 #define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_CLR_MSK 0xfffffffb
58661 /* The reset value of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */
58662 #define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_RESET 0x0
58663 /* Extracts the ALT_USB_HOST_HCINTMSK14_AHBERRMSK field value from a register. */
58664 #define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
58665 /* Produces a ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field value suitable for setting the register. */
58666 #define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
58667 
58668 /*
58669  * Field : stallmsk
58670  *
58671  * STALL Response Received Interrupt Mask (StallMsk)
58672  *
58673  * In scatter/gather DMA mode for host,
58674  *
58675  * interrupts will not be generated due to the corresponding bits set in
58676  *
58677  * HCINTn.
58678  *
58679  * Field Access Macros:
58680  *
58681  */
58682 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_STALLMSK register field. */
58683 #define ALT_USB_HOST_HCINTMSK14_STALLMSK_LSB 3
58684 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_STALLMSK register field. */
58685 #define ALT_USB_HOST_HCINTMSK14_STALLMSK_MSB 3
58686 /* The width in bits of the ALT_USB_HOST_HCINTMSK14_STALLMSK register field. */
58687 #define ALT_USB_HOST_HCINTMSK14_STALLMSK_WIDTH 1
58688 /* The mask used to set the ALT_USB_HOST_HCINTMSK14_STALLMSK register field value. */
58689 #define ALT_USB_HOST_HCINTMSK14_STALLMSK_SET_MSK 0x00000008
58690 /* The mask used to clear the ALT_USB_HOST_HCINTMSK14_STALLMSK register field value. */
58691 #define ALT_USB_HOST_HCINTMSK14_STALLMSK_CLR_MSK 0xfffffff7
58692 /* The reset value of the ALT_USB_HOST_HCINTMSK14_STALLMSK register field. */
58693 #define ALT_USB_HOST_HCINTMSK14_STALLMSK_RESET 0x0
58694 /* Extracts the ALT_USB_HOST_HCINTMSK14_STALLMSK field value from a register. */
58695 #define ALT_USB_HOST_HCINTMSK14_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
58696 /* Produces a ALT_USB_HOST_HCINTMSK14_STALLMSK register field value suitable for setting the register. */
58697 #define ALT_USB_HOST_HCINTMSK14_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
58698 
58699 /*
58700  * Field : nakmsk
58701  *
58702  * NAK Response Received Interrupt Mask (NakMsk)
58703  *
58704  * In scatter/gather DMA mode for host,
58705  *
58706  * interrupts will not be generated due to the corresponding bits set in
58707  *
58708  * HCINTn.
58709  *
58710  * Field Access Macros:
58711  *
58712  */
58713 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_NAKMSK register field. */
58714 #define ALT_USB_HOST_HCINTMSK14_NAKMSK_LSB 4
58715 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_NAKMSK register field. */
58716 #define ALT_USB_HOST_HCINTMSK14_NAKMSK_MSB 4
58717 /* The width in bits of the ALT_USB_HOST_HCINTMSK14_NAKMSK register field. */
58718 #define ALT_USB_HOST_HCINTMSK14_NAKMSK_WIDTH 1
58719 /* The mask used to set the ALT_USB_HOST_HCINTMSK14_NAKMSK register field value. */
58720 #define ALT_USB_HOST_HCINTMSK14_NAKMSK_SET_MSK 0x00000010
58721 /* The mask used to clear the ALT_USB_HOST_HCINTMSK14_NAKMSK register field value. */
58722 #define ALT_USB_HOST_HCINTMSK14_NAKMSK_CLR_MSK 0xffffffef
58723 /* The reset value of the ALT_USB_HOST_HCINTMSK14_NAKMSK register field. */
58724 #define ALT_USB_HOST_HCINTMSK14_NAKMSK_RESET 0x0
58725 /* Extracts the ALT_USB_HOST_HCINTMSK14_NAKMSK field value from a register. */
58726 #define ALT_USB_HOST_HCINTMSK14_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
58727 /* Produces a ALT_USB_HOST_HCINTMSK14_NAKMSK register field value suitable for setting the register. */
58728 #define ALT_USB_HOST_HCINTMSK14_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
58729 
58730 /*
58731  * Field : ackmsk
58732  *
58733  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
58734  *
58735  * In scatter/gather DMA mode for host,
58736  *
58737  * interrupts will not be generated due to the corresponding bits set in
58738  *
58739  * HCINTn.
58740  *
58741  * Field Access Macros:
58742  *
58743  */
58744 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_ACKMSK register field. */
58745 #define ALT_USB_HOST_HCINTMSK14_ACKMSK_LSB 5
58746 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_ACKMSK register field. */
58747 #define ALT_USB_HOST_HCINTMSK14_ACKMSK_MSB 5
58748 /* The width in bits of the ALT_USB_HOST_HCINTMSK14_ACKMSK register field. */
58749 #define ALT_USB_HOST_HCINTMSK14_ACKMSK_WIDTH 1
58750 /* The mask used to set the ALT_USB_HOST_HCINTMSK14_ACKMSK register field value. */
58751 #define ALT_USB_HOST_HCINTMSK14_ACKMSK_SET_MSK 0x00000020
58752 /* The mask used to clear the ALT_USB_HOST_HCINTMSK14_ACKMSK register field value. */
58753 #define ALT_USB_HOST_HCINTMSK14_ACKMSK_CLR_MSK 0xffffffdf
58754 /* The reset value of the ALT_USB_HOST_HCINTMSK14_ACKMSK register field. */
58755 #define ALT_USB_HOST_HCINTMSK14_ACKMSK_RESET 0x0
58756 /* Extracts the ALT_USB_HOST_HCINTMSK14_ACKMSK field value from a register. */
58757 #define ALT_USB_HOST_HCINTMSK14_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
58758 /* Produces a ALT_USB_HOST_HCINTMSK14_ACKMSK register field value suitable for setting the register. */
58759 #define ALT_USB_HOST_HCINTMSK14_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
58760 
58761 /*
58762  * Field : nyetmsk
58763  *
58764  * NYET Response Received Interrupt Mask (NyetMsk)
58765  *
58766  * In scatter/gather DMA mode for host,
58767  *
58768  * interrupts will not be generated due to the corresponding bits set in
58769  *
58770  * HCINTn.
58771  *
58772  * Field Access Macros:
58773  *
58774  */
58775 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_NYETMSK register field. */
58776 #define ALT_USB_HOST_HCINTMSK14_NYETMSK_LSB 6
58777 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_NYETMSK register field. */
58778 #define ALT_USB_HOST_HCINTMSK14_NYETMSK_MSB 6
58779 /* The width in bits of the ALT_USB_HOST_HCINTMSK14_NYETMSK register field. */
58780 #define ALT_USB_HOST_HCINTMSK14_NYETMSK_WIDTH 1
58781 /* The mask used to set the ALT_USB_HOST_HCINTMSK14_NYETMSK register field value. */
58782 #define ALT_USB_HOST_HCINTMSK14_NYETMSK_SET_MSK 0x00000040
58783 /* The mask used to clear the ALT_USB_HOST_HCINTMSK14_NYETMSK register field value. */
58784 #define ALT_USB_HOST_HCINTMSK14_NYETMSK_CLR_MSK 0xffffffbf
58785 /* The reset value of the ALT_USB_HOST_HCINTMSK14_NYETMSK register field. */
58786 #define ALT_USB_HOST_HCINTMSK14_NYETMSK_RESET 0x0
58787 /* Extracts the ALT_USB_HOST_HCINTMSK14_NYETMSK field value from a register. */
58788 #define ALT_USB_HOST_HCINTMSK14_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
58789 /* Produces a ALT_USB_HOST_HCINTMSK14_NYETMSK register field value suitable for setting the register. */
58790 #define ALT_USB_HOST_HCINTMSK14_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
58791 
58792 /*
58793  * Field : xacterrmsk
58794  *
58795  * Transaction Error Mask (XactErrMsk)
58796  *
58797  * In scatter/gather DMA mode for host,
58798  *
58799  * interrupts will not be generated due to the corresponding bits set in
58800  *
58801  * HCINTn.
58802  *
58803  * Field Access Macros:
58804  *
58805  */
58806 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field. */
58807 #define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_LSB 7
58808 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field. */
58809 #define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_MSB 7
58810 /* The width in bits of the ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field. */
58811 #define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_WIDTH 1
58812 /* The mask used to set the ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field value. */
58813 #define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_SET_MSK 0x00000080
58814 /* The mask used to clear the ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field value. */
58815 #define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_CLR_MSK 0xffffff7f
58816 /* The reset value of the ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field. */
58817 #define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_RESET 0x0
58818 /* Extracts the ALT_USB_HOST_HCINTMSK14_XACTERRMSK field value from a register. */
58819 #define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
58820 /* Produces a ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field value suitable for setting the register. */
58821 #define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
58822 
58823 /*
58824  * Field : bblerrmsk
58825  *
58826  * Babble Error Mask (BblErrMsk)
58827  *
58828  * In scatter/gather DMA mode for host,
58829  *
58830  * interrupts will not be generated due to the corresponding bits set in
58831  *
58832  * HCINTn.
58833  *
58834  * Field Access Macros:
58835  *
58836  */
58837 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field. */
58838 #define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_LSB 8
58839 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field. */
58840 #define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_MSB 8
58841 /* The width in bits of the ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field. */
58842 #define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_WIDTH 1
58843 /* The mask used to set the ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field value. */
58844 #define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_SET_MSK 0x00000100
58845 /* The mask used to clear the ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field value. */
58846 #define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_CLR_MSK 0xfffffeff
58847 /* The reset value of the ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field. */
58848 #define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_RESET 0x0
58849 /* Extracts the ALT_USB_HOST_HCINTMSK14_BBLERRMSK field value from a register. */
58850 #define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
58851 /* Produces a ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field value suitable for setting the register. */
58852 #define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
58853 
58854 /*
58855  * Field : frmovrunmsk
58856  *
58857  * Frame Overrun Mask (FrmOvrunMsk)
58858  *
58859  * In scatter/gather DMA mode for host,
58860  *
58861  * interrupts will not be generated due to the corresponding bits set in
58862  *
58863  * HCINTn.
58864  *
58865  * Field Access Macros:
58866  *
58867  */
58868 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field. */
58869 #define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_LSB 9
58870 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field. */
58871 #define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_MSB 9
58872 /* The width in bits of the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field. */
58873 #define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_WIDTH 1
58874 /* The mask used to set the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field value. */
58875 #define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_SET_MSK 0x00000200
58876 /* The mask used to clear the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field value. */
58877 #define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_CLR_MSK 0xfffffdff
58878 /* The reset value of the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field. */
58879 #define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_RESET 0x0
58880 /* Extracts the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK field value from a register. */
58881 #define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
58882 /* Produces a ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field value suitable for setting the register. */
58883 #define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
58884 
58885 /*
58886  * Field : datatglerrmsk
58887  *
58888  * Data Toggle Error Mask (DataTglErrMsk)
58889  *
58890  * In scatter/gather DMA mode for host,
58891  *
58892  * interrupts will not be generated due to the corresponding bits set in
58893  *
58894  * HCINTn.
58895  *
58896  * Field Access Macros:
58897  *
58898  */
58899 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field. */
58900 #define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_LSB 10
58901 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field. */
58902 #define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_MSB 10
58903 /* The width in bits of the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field. */
58904 #define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_WIDTH 1
58905 /* The mask used to set the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field value. */
58906 #define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_SET_MSK 0x00000400
58907 /* The mask used to clear the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field value. */
58908 #define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_CLR_MSK 0xfffffbff
58909 /* The reset value of the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field. */
58910 #define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_RESET 0x0
58911 /* Extracts the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK field value from a register. */
58912 #define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
58913 /* Produces a ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field value suitable for setting the register. */
58914 #define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
58915 
58916 /*
58917  * Field : bnaintrmsk
58918  *
58919  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
58920  *
58921  * This bit is valid only when Scatter/Gather DMA mode is enabled.
58922  *
58923  * Field Enumeration Values:
58924  *
58925  * Enum | Value | Description
58926  * :-------------------------------------------|:------|:------------
58927  * ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_MSK | 0x0 | Mask
58928  * ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_NOMSK | 0x1 | No mask
58929  *
58930  * Field Access Macros:
58931  *
58932  */
58933 /*
58934  * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_BNAINTRMSK
58935  *
58936  * Mask
58937  */
58938 #define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_MSK 0x0
58939 /*
58940  * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_BNAINTRMSK
58941  *
58942  * No mask
58943  */
58944 #define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_NOMSK 0x1
58945 
58946 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */
58947 #define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_LSB 11
58948 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */
58949 #define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_MSB 11
58950 /* The width in bits of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */
58951 #define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_WIDTH 1
58952 /* The mask used to set the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field value. */
58953 #define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_SET_MSK 0x00000800
58954 /* The mask used to clear the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field value. */
58955 #define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_CLR_MSK 0xfffff7ff
58956 /* The reset value of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */
58957 #define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_RESET 0x0
58958 /* Extracts the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK field value from a register. */
58959 #define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
58960 /* Produces a ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field value suitable for setting the register. */
58961 #define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
58962 
58963 /*
58964  * Field : frm_lst_rollintrmsk
58965  *
58966  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
58967  *
58968  * This bit is valid only when Scatter/Gather DMA mode is enabled.
58969  *
58970  * Field Enumeration Values:
58971  *
58972  * Enum | Value | Description
58973  * :----------------------------------------------------|:------|:------------
58974  * ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
58975  * ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
58976  *
58977  * Field Access Macros:
58978  *
58979  */
58980 /*
58981  * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK
58982  *
58983  * Mask
58984  */
58985 #define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_MSK 0x0
58986 /*
58987  * Enumerated value for register field ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK
58988  *
58989  * No mask
58990  */
58991 #define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
58992 
58993 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */
58994 #define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_LSB 13
58995 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */
58996 #define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_MSB 13
58997 /* The width in bits of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */
58998 #define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_WIDTH 1
58999 /* The mask used to set the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field value. */
59000 #define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
59001 /* The mask used to clear the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field value. */
59002 #define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
59003 /* The reset value of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */
59004 #define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_RESET 0x0
59005 /* Extracts the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK field value from a register. */
59006 #define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
59007 /* Produces a ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
59008 #define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
59009 
59010 #ifndef __ASSEMBLY__
59011 /*
59012  * WARNING: The C register and register group struct declarations are provided for
59013  * convenience and illustrative purposes. They should, however, be used with
59014  * caution as the C language standard provides no guarantees about the alignment or
59015  * atomicity of device memory accesses. The recommended practice for writing
59016  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59017  * alt_write_word() functions.
59018  *
59019  * The struct declaration for register ALT_USB_HOST_HCINTMSK14.
59020  */
59021 struct ALT_USB_HOST_HCINTMSK14_s
59022 {
59023  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK */
59024  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK14_CHHLTDMSK */
59025  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK14_AHBERRMSK */
59026  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK14_STALLMSK */
59027  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK14_NAKMSK */
59028  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK14_ACKMSK */
59029  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK14_NYETMSK */
59030  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK14_XACTERRMSK */
59031  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK14_BBLERRMSK */
59032  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK */
59033  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK */
59034  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK14_BNAINTRMSK */
59035  uint32_t : 1; /* *UNDEFINED* */
59036  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK */
59037  uint32_t : 18; /* *UNDEFINED* */
59038 };
59039 
59040 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK14. */
59041 typedef volatile struct ALT_USB_HOST_HCINTMSK14_s ALT_USB_HOST_HCINTMSK14_t;
59042 #endif /* __ASSEMBLY__ */
59043 
59044 /* The reset value of the ALT_USB_HOST_HCINTMSK14 register. */
59045 #define ALT_USB_HOST_HCINTMSK14_RESET 0x00000000
59046 /* The byte offset of the ALT_USB_HOST_HCINTMSK14 register from the beginning of the component. */
59047 #define ALT_USB_HOST_HCINTMSK14_OFST 0x2cc
59048 /* The address of the ALT_USB_HOST_HCINTMSK14 register. */
59049 #define ALT_USB_HOST_HCINTMSK14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK14_OFST))
59050 
59051 /*
59052  * Register : hctsiz14
59053  *
59054  * Host Channel 14 Transfer Size Register
59055  *
59056  * Register Layout
59057  *
59058  * Bits | Access | Reset | Description
59059  * :--------|:-------|:------|:-------------------------------
59060  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ14_XFERSIZE
59061  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ14_PKTCNT
59062  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ14_PID
59063  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ14_DOPNG
59064  *
59065  */
59066 /*
59067  * Field : xfersize
59068  *
59069  * Transfer Size (XferSize)
59070  *
59071  * For an OUT, this field is the number of data bytes the host sends
59072  *
59073  * during the transfer.
59074  *
59075  * For an IN, this field is the buffer size that the application has
59076  *
59077  * Reserved For the transfer. The application is expected to
59078  *
59079  * program this field as an integer multiple of the maximum packet
59080  *
59081  * size For IN transactions (periodic and non-periodic).
59082  *
59083  * The width of this counter is specified as Width of Transfer Size
59084  *
59085  * Counters
59086  *
59087  * Field Access Macros:
59088  *
59089  */
59090 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */
59091 #define ALT_USB_HOST_HCTSIZ14_XFERSIZE_LSB 0
59092 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */
59093 #define ALT_USB_HOST_HCTSIZ14_XFERSIZE_MSB 18
59094 /* The width in bits of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */
59095 #define ALT_USB_HOST_HCTSIZ14_XFERSIZE_WIDTH 19
59096 /* The mask used to set the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field value. */
59097 #define ALT_USB_HOST_HCTSIZ14_XFERSIZE_SET_MSK 0x0007ffff
59098 /* The mask used to clear the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field value. */
59099 #define ALT_USB_HOST_HCTSIZ14_XFERSIZE_CLR_MSK 0xfff80000
59100 /* The reset value of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */
59101 #define ALT_USB_HOST_HCTSIZ14_XFERSIZE_RESET 0x0
59102 /* Extracts the ALT_USB_HOST_HCTSIZ14_XFERSIZE field value from a register. */
59103 #define ALT_USB_HOST_HCTSIZ14_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
59104 /* Produces a ALT_USB_HOST_HCTSIZ14_XFERSIZE register field value suitable for setting the register. */
59105 #define ALT_USB_HOST_HCTSIZ14_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
59106 
59107 /*
59108  * Field : pktcnt
59109  *
59110  * Packet Count (PktCnt)
59111  *
59112  * This field is programmed by the application with the expected
59113  *
59114  * number of packets to be transmitted (OUT) or received (IN).
59115  *
59116  * The host decrements this count on every successful
59117  *
59118  * transmission or reception of an OUT/IN packet. Once this count
59119  *
59120  * reaches zero, the application is interrupted to indicate normal
59121  *
59122  * completion.
59123  *
59124  * The width of this counter is specified as Width of Packet
59125  *
59126  * Counters
59127  *
59128  * Field Access Macros:
59129  *
59130  */
59131 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */
59132 #define ALT_USB_HOST_HCTSIZ14_PKTCNT_LSB 19
59133 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */
59134 #define ALT_USB_HOST_HCTSIZ14_PKTCNT_MSB 28
59135 /* The width in bits of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */
59136 #define ALT_USB_HOST_HCTSIZ14_PKTCNT_WIDTH 10
59137 /* The mask used to set the ALT_USB_HOST_HCTSIZ14_PKTCNT register field value. */
59138 #define ALT_USB_HOST_HCTSIZ14_PKTCNT_SET_MSK 0x1ff80000
59139 /* The mask used to clear the ALT_USB_HOST_HCTSIZ14_PKTCNT register field value. */
59140 #define ALT_USB_HOST_HCTSIZ14_PKTCNT_CLR_MSK 0xe007ffff
59141 /* The reset value of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */
59142 #define ALT_USB_HOST_HCTSIZ14_PKTCNT_RESET 0x0
59143 /* Extracts the ALT_USB_HOST_HCTSIZ14_PKTCNT field value from a register. */
59144 #define ALT_USB_HOST_HCTSIZ14_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
59145 /* Produces a ALT_USB_HOST_HCTSIZ14_PKTCNT register field value suitable for setting the register. */
59146 #define ALT_USB_HOST_HCTSIZ14_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
59147 
59148 /*
59149  * Field : pid
59150  *
59151  * PID (Pid)
59152  *
59153  * The application programs this field with the type of PID to use For
59154  *
59155  * the initial transaction. The host maintains this field For the rest of
59156  *
59157  * the transfer.
59158  *
59159  * 2'b00: DATA0
59160  *
59161  * 2'b01: DATA2
59162  *
59163  * 2'b10: DATA1
59164  *
59165  * 2'b11: MDATA (non-control)/SETUP (control)
59166  *
59167  * Field Enumeration Values:
59168  *
59169  * Enum | Value | Description
59170  * :----------------------------------|:------|:------------------------------------
59171  * ALT_USB_HOST_HCTSIZ14_PID_E_DATA0 | 0x0 | DATA0
59172  * ALT_USB_HOST_HCTSIZ14_PID_E_DATA2 | 0x1 | DATA2
59173  * ALT_USB_HOST_HCTSIZ14_PID_E_DATA1 | 0x2 | DATA1
59174  * ALT_USB_HOST_HCTSIZ14_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
59175  *
59176  * Field Access Macros:
59177  *
59178  */
59179 /*
59180  * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID
59181  *
59182  * DATA0
59183  */
59184 #define ALT_USB_HOST_HCTSIZ14_PID_E_DATA0 0x0
59185 /*
59186  * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID
59187  *
59188  * DATA2
59189  */
59190 #define ALT_USB_HOST_HCTSIZ14_PID_E_DATA2 0x1
59191 /*
59192  * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID
59193  *
59194  * DATA1
59195  */
59196 #define ALT_USB_HOST_HCTSIZ14_PID_E_DATA1 0x2
59197 /*
59198  * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID
59199  *
59200  * MDATA (non-control)/SETUP (control)
59201  */
59202 #define ALT_USB_HOST_HCTSIZ14_PID_E_MDATA 0x3
59203 
59204 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_PID register field. */
59205 #define ALT_USB_HOST_HCTSIZ14_PID_LSB 29
59206 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_PID register field. */
59207 #define ALT_USB_HOST_HCTSIZ14_PID_MSB 30
59208 /* The width in bits of the ALT_USB_HOST_HCTSIZ14_PID register field. */
59209 #define ALT_USB_HOST_HCTSIZ14_PID_WIDTH 2
59210 /* The mask used to set the ALT_USB_HOST_HCTSIZ14_PID register field value. */
59211 #define ALT_USB_HOST_HCTSIZ14_PID_SET_MSK 0x60000000
59212 /* The mask used to clear the ALT_USB_HOST_HCTSIZ14_PID register field value. */
59213 #define ALT_USB_HOST_HCTSIZ14_PID_CLR_MSK 0x9fffffff
59214 /* The reset value of the ALT_USB_HOST_HCTSIZ14_PID register field. */
59215 #define ALT_USB_HOST_HCTSIZ14_PID_RESET 0x0
59216 /* Extracts the ALT_USB_HOST_HCTSIZ14_PID field value from a register. */
59217 #define ALT_USB_HOST_HCTSIZ14_PID_GET(value) (((value) & 0x60000000) >> 29)
59218 /* Produces a ALT_USB_HOST_HCTSIZ14_PID register field value suitable for setting the register. */
59219 #define ALT_USB_HOST_HCTSIZ14_PID_SET(value) (((value) << 29) & 0x60000000)
59220 
59221 /*
59222  * Field : dopng
59223  *
59224  * Do Ping (DoPng)
59225  *
59226  * This bit is used only For OUT transfers.
59227  *
59228  * Setting this field to 1 directs the host to do PING protocol.
59229  *
59230  * Note: Do not Set this bit For IN transfers. If this bit is Set For
59231  *
59232  * for IN transfers it disables the channel.
59233  *
59234  * Field Enumeration Values:
59235  *
59236  * Enum | Value | Description
59237  * :-------------------------------------|:------|:-----------------
59238  * ALT_USB_HOST_HCTSIZ14_DOPNG_E_NOPING | 0x0 | No ping protocol
59239  * ALT_USB_HOST_HCTSIZ14_DOPNG_E_PING | 0x1 | Ping protocol
59240  *
59241  * Field Access Macros:
59242  *
59243  */
59244 /*
59245  * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_DOPNG
59246  *
59247  * No ping protocol
59248  */
59249 #define ALT_USB_HOST_HCTSIZ14_DOPNG_E_NOPING 0x0
59250 /*
59251  * Enumerated value for register field ALT_USB_HOST_HCTSIZ14_DOPNG
59252  *
59253  * Ping protocol
59254  */
59255 #define ALT_USB_HOST_HCTSIZ14_DOPNG_E_PING 0x1
59256 
59257 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */
59258 #define ALT_USB_HOST_HCTSIZ14_DOPNG_LSB 31
59259 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */
59260 #define ALT_USB_HOST_HCTSIZ14_DOPNG_MSB 31
59261 /* The width in bits of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */
59262 #define ALT_USB_HOST_HCTSIZ14_DOPNG_WIDTH 1
59263 /* The mask used to set the ALT_USB_HOST_HCTSIZ14_DOPNG register field value. */
59264 #define ALT_USB_HOST_HCTSIZ14_DOPNG_SET_MSK 0x80000000
59265 /* The mask used to clear the ALT_USB_HOST_HCTSIZ14_DOPNG register field value. */
59266 #define ALT_USB_HOST_HCTSIZ14_DOPNG_CLR_MSK 0x7fffffff
59267 /* The reset value of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */
59268 #define ALT_USB_HOST_HCTSIZ14_DOPNG_RESET 0x0
59269 /* Extracts the ALT_USB_HOST_HCTSIZ14_DOPNG field value from a register. */
59270 #define ALT_USB_HOST_HCTSIZ14_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
59271 /* Produces a ALT_USB_HOST_HCTSIZ14_DOPNG register field value suitable for setting the register. */
59272 #define ALT_USB_HOST_HCTSIZ14_DOPNG_SET(value) (((value) << 31) & 0x80000000)
59273 
59274 #ifndef __ASSEMBLY__
59275 /*
59276  * WARNING: The C register and register group struct declarations are provided for
59277  * convenience and illustrative purposes. They should, however, be used with
59278  * caution as the C language standard provides no guarantees about the alignment or
59279  * atomicity of device memory accesses. The recommended practice for writing
59280  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59281  * alt_write_word() functions.
59282  *
59283  * The struct declaration for register ALT_USB_HOST_HCTSIZ14.
59284  */
59285 struct ALT_USB_HOST_HCTSIZ14_s
59286 {
59287  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ14_XFERSIZE */
59288  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ14_PKTCNT */
59289  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ14_PID */
59290  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ14_DOPNG */
59291 };
59292 
59293 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ14. */
59294 typedef volatile struct ALT_USB_HOST_HCTSIZ14_s ALT_USB_HOST_HCTSIZ14_t;
59295 #endif /* __ASSEMBLY__ */
59296 
59297 /* The reset value of the ALT_USB_HOST_HCTSIZ14 register. */
59298 #define ALT_USB_HOST_HCTSIZ14_RESET 0x00000000
59299 /* The byte offset of the ALT_USB_HOST_HCTSIZ14 register from the beginning of the component. */
59300 #define ALT_USB_HOST_HCTSIZ14_OFST 0x2d0
59301 /* The address of the ALT_USB_HOST_HCTSIZ14 register. */
59302 #define ALT_USB_HOST_HCTSIZ14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ14_OFST))
59303 
59304 /*
59305  * Register : hcdma14
59306  *
59307  * Host Channel 14 DMA Address Register
59308  *
59309  * Register Layout
59310  *
59311  * Bits | Access | Reset | Description
59312  * :-------|:-------|:------|:-----------------------------
59313  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA14_HCDMA14
59314  *
59315  */
59316 /*
59317  * Field : hcdma14
59318  *
59319  * Buffer DMA Mode:
59320  *
59321  * [31:0] DMA Address (DMAAddr)
59322  *
59323  * This field holds the start address in the external memory from which the data
59324  * for
59325  *
59326  * the endpoint must be fetched or to which it must be stored. This register is
59327  *
59328  * incremented on every AHB transaction.
59329  *
59330  * Scatter-Gather DMA (DescDMA) Mode:
59331  *
59332  * [31:9] (Non Isoc) Non-Isochronous:
59333  *
59334  * [31:N] (Isoc) Isochronous:
59335  *
59336  * This field holds the start address of the 512 bytes
59337  *
59338  * page. The first descriptor in the list should be located
59339  *
59340  * in this address. The first descriptor may be or may
59341  *
59342  * not be ready. The core starts processing the list from
59343  *
59344  * the CTD value.
59345  *
59346  * This field holds the address of the 2*(nTD+1) bytes of
59347  *
59348  * locations in which the isochronous descriptors are
59349  *
59350  * present where N is based on nTD as per Table below
59351  *
59352  * [31:N] Base Address
59353  *
59354  * [N-1:3] Offset
59355  *
59356  * [2:0] 000
59357  *
59358  * HS ISOC
59359  *
59360  * nTD N
59361  *
59362  * 7 6
59363  *
59364  * 15 7
59365  *
59366  * 31 8
59367  *
59368  * 63 9
59369  *
59370  * 127 10
59371  *
59372  * 255 11
59373  *
59374  * FS ISOC
59375  *
59376  * nTD N
59377  *
59378  * 1 4
59379  *
59380  * 3 5
59381  *
59382  * 7 6
59383  *
59384  * 15 7
59385  *
59386  * 31 8
59387  *
59388  * 63 9
59389  *
59390  * [N-1:3] (Isoc):
59391  *
59392  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
59393  *
59394  * Non Isochronous:
59395  *
59396  * This value is in terms of number of descriptors. The values can be from 0 to 63.
59397  *
59398  * 0 - 1 descriptor.
59399  *
59400  * 63 - 64 descriptors.
59401  *
59402  * This field indicates the current descriptor processed in the list. This field is
59403  * updated
59404  *
59405  * both by application and the core. For example, if the application enables the
59406  *
59407  * channel after programming CTD=5, then the core will start processing the 6th
59408  *
59409  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
59410  *
59411  * to DMAAddr.
59412  *
59413  * Isochronous:
59414  *
59415  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
59416  * set
59417  *
59418  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
59419  *
59420  * [31:9] (Non Isoc) Non-Isochronous:
59421  *
59422  * [31:N] (Isoc) Isochronous:
59423  *
59424  * This field holds the start address of the 512 bytes
59425  *
59426  * page. The first descriptor in the list should be located
59427  *
59428  * in this address. The first descriptor may be or may
59429  *
59430  * not be ready. The core starts processing the list from
59431  *
59432  * the CTD value.
59433  *
59434  * This field holds the address of the 2*(nTD+1) bytes of
59435  *
59436  * locations in which the isochronous descriptors are
59437  *
59438  * present where N is based on nTD as per Table below
59439  *
59440  * [31:N] Base Address
59441  *
59442  * [N-1:3] Offset
59443  *
59444  * [2:0] 000
59445  *
59446  * HS ISOC
59447  *
59448  * nTD N
59449  *
59450  * 7 6
59451  *
59452  * 15 7
59453  *
59454  * 31 8
59455  *
59456  * 63 9
59457  *
59458  * 127 10
59459  *
59460  * 255 11
59461  *
59462  * FS ISOC
59463  *
59464  * nTD N
59465  *
59466  * 1 4
59467  *
59468  * 3 5
59469  *
59470  * 7 6
59471  *
59472  * 15 7
59473  *
59474  * 31 8
59475  *
59476  * 63 9
59477  *
59478  * [N-1:3] (Isoc):
59479  *
59480  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
59481  *
59482  * Non Isochronous:
59483  *
59484  * This value is in terms of number of descriptors. The values can be from 0 to 63.
59485  *
59486  * 0 - 1 descriptor.
59487  *
59488  * 63 - 64 descriptors.
59489  *
59490  * This field indicates the current descriptor processed in the list. This field is
59491  * updated
59492  *
59493  * both by application and the core. For example, if the application enables the
59494  *
59495  * channel after programming CTD=5, then the core will start processing the 6th
59496  *
59497  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
59498  *
59499  * to DMAAddr.
59500  *
59501  * Isochronous:
59502  *
59503  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
59504  * set
59505  *
59506  * to zero by application.
59507  *
59508  * Field Access Macros:
59509  *
59510  */
59511 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */
59512 #define ALT_USB_HOST_HCDMA14_HCDMA14_LSB 0
59513 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */
59514 #define ALT_USB_HOST_HCDMA14_HCDMA14_MSB 31
59515 /* The width in bits of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */
59516 #define ALT_USB_HOST_HCDMA14_HCDMA14_WIDTH 32
59517 /* The mask used to set the ALT_USB_HOST_HCDMA14_HCDMA14 register field value. */
59518 #define ALT_USB_HOST_HCDMA14_HCDMA14_SET_MSK 0xffffffff
59519 /* The mask used to clear the ALT_USB_HOST_HCDMA14_HCDMA14 register field value. */
59520 #define ALT_USB_HOST_HCDMA14_HCDMA14_CLR_MSK 0x00000000
59521 /* The reset value of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */
59522 #define ALT_USB_HOST_HCDMA14_HCDMA14_RESET 0x0
59523 /* Extracts the ALT_USB_HOST_HCDMA14_HCDMA14 field value from a register. */
59524 #define ALT_USB_HOST_HCDMA14_HCDMA14_GET(value) (((value) & 0xffffffff) >> 0)
59525 /* Produces a ALT_USB_HOST_HCDMA14_HCDMA14 register field value suitable for setting the register. */
59526 #define ALT_USB_HOST_HCDMA14_HCDMA14_SET(value) (((value) << 0) & 0xffffffff)
59527 
59528 #ifndef __ASSEMBLY__
59529 /*
59530  * WARNING: The C register and register group struct declarations are provided for
59531  * convenience and illustrative purposes. They should, however, be used with
59532  * caution as the C language standard provides no guarantees about the alignment or
59533  * atomicity of device memory accesses. The recommended practice for writing
59534  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59535  * alt_write_word() functions.
59536  *
59537  * The struct declaration for register ALT_USB_HOST_HCDMA14.
59538  */
59539 struct ALT_USB_HOST_HCDMA14_s
59540 {
59541  uint32_t hcdma14 : 32; /* ALT_USB_HOST_HCDMA14_HCDMA14 */
59542 };
59543 
59544 /* The typedef declaration for register ALT_USB_HOST_HCDMA14. */
59545 typedef volatile struct ALT_USB_HOST_HCDMA14_s ALT_USB_HOST_HCDMA14_t;
59546 #endif /* __ASSEMBLY__ */
59547 
59548 /* The reset value of the ALT_USB_HOST_HCDMA14 register. */
59549 #define ALT_USB_HOST_HCDMA14_RESET 0x00000000
59550 /* The byte offset of the ALT_USB_HOST_HCDMA14 register from the beginning of the component. */
59551 #define ALT_USB_HOST_HCDMA14_OFST 0x2d4
59552 /* The address of the ALT_USB_HOST_HCDMA14 register. */
59553 #define ALT_USB_HOST_HCDMA14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA14_OFST))
59554 
59555 /*
59556  * Register : hcdmab14
59557  *
59558  * Host Channel 14 DMA Buffer Address Register
59559  *
59560  * Register Layout
59561  *
59562  * Bits | Access | Reset | Description
59563  * :-------|:-------|:------|:-------------------------------
59564  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB14_HCDMAB14
59565  *
59566  */
59567 /*
59568  * Field : hcdmab14
59569  *
59570  * Holds the current buffer address.
59571  *
59572  * This register is updated as and when the data transfer for the corresponding end
59573  * point
59574  *
59575  * is in progress. This register is present only in Scatter/Gather DMA mode.
59576  * Otherwise this
59577  *
59578  * field is reserved.
59579  *
59580  * Field Access Macros:
59581  *
59582  */
59583 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */
59584 #define ALT_USB_HOST_HCDMAB14_HCDMAB14_LSB 0
59585 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */
59586 #define ALT_USB_HOST_HCDMAB14_HCDMAB14_MSB 31
59587 /* The width in bits of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */
59588 #define ALT_USB_HOST_HCDMAB14_HCDMAB14_WIDTH 32
59589 /* The mask used to set the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field value. */
59590 #define ALT_USB_HOST_HCDMAB14_HCDMAB14_SET_MSK 0xffffffff
59591 /* The mask used to clear the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field value. */
59592 #define ALT_USB_HOST_HCDMAB14_HCDMAB14_CLR_MSK 0x00000000
59593 /* The reset value of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */
59594 #define ALT_USB_HOST_HCDMAB14_HCDMAB14_RESET 0x0
59595 /* Extracts the ALT_USB_HOST_HCDMAB14_HCDMAB14 field value from a register. */
59596 #define ALT_USB_HOST_HCDMAB14_HCDMAB14_GET(value) (((value) & 0xffffffff) >> 0)
59597 /* Produces a ALT_USB_HOST_HCDMAB14_HCDMAB14 register field value suitable for setting the register. */
59598 #define ALT_USB_HOST_HCDMAB14_HCDMAB14_SET(value) (((value) << 0) & 0xffffffff)
59599 
59600 #ifndef __ASSEMBLY__
59601 /*
59602  * WARNING: The C register and register group struct declarations are provided for
59603  * convenience and illustrative purposes. They should, however, be used with
59604  * caution as the C language standard provides no guarantees about the alignment or
59605  * atomicity of device memory accesses. The recommended practice for writing
59606  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59607  * alt_write_word() functions.
59608  *
59609  * The struct declaration for register ALT_USB_HOST_HCDMAB14.
59610  */
59611 struct ALT_USB_HOST_HCDMAB14_s
59612 {
59613  uint32_t hcdmab14 : 32; /* ALT_USB_HOST_HCDMAB14_HCDMAB14 */
59614 };
59615 
59616 /* The typedef declaration for register ALT_USB_HOST_HCDMAB14. */
59617 typedef volatile struct ALT_USB_HOST_HCDMAB14_s ALT_USB_HOST_HCDMAB14_t;
59618 #endif /* __ASSEMBLY__ */
59619 
59620 /* The reset value of the ALT_USB_HOST_HCDMAB14 register. */
59621 #define ALT_USB_HOST_HCDMAB14_RESET 0x00000000
59622 /* The byte offset of the ALT_USB_HOST_HCDMAB14 register from the beginning of the component. */
59623 #define ALT_USB_HOST_HCDMAB14_OFST 0x2dc
59624 /* The address of the ALT_USB_HOST_HCDMAB14 register. */
59625 #define ALT_USB_HOST_HCDMAB14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB14_OFST))
59626 
59627 /*
59628  * Register : hcchar15
59629  *
59630  * Host Channel 15 Characteristics Register
59631  *
59632  * Register Layout
59633  *
59634  * Bits | Access | Reset | Description
59635  * :--------|:---------|:------|:------------------------------
59636  * [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_MPS
59637  * [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_EPNUM
59638  * [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_EPDIR
59639  * [16] | ??? | 0x0 | *UNDEFINED*
59640  * [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_LSPDDEV
59641  * [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_EPTYPE
59642  * [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_EC
59643  * [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_DEVADDR
59644  * [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_ODDFRM
59645  * [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR15_CHDIS
59646  * [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR15_CHENA
59647  *
59648  */
59649 /*
59650  * Field : mps
59651  *
59652  * Maximum Packet Size (MPS)
59653  *
59654  * Indicates the maximum packet size of the associated endpoint.
59655  *
59656  * Field Access Macros:
59657  *
59658  */
59659 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_MPS register field. */
59660 #define ALT_USB_HOST_HCCHAR15_MPS_LSB 0
59661 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_MPS register field. */
59662 #define ALT_USB_HOST_HCCHAR15_MPS_MSB 10
59663 /* The width in bits of the ALT_USB_HOST_HCCHAR15_MPS register field. */
59664 #define ALT_USB_HOST_HCCHAR15_MPS_WIDTH 11
59665 /* The mask used to set the ALT_USB_HOST_HCCHAR15_MPS register field value. */
59666 #define ALT_USB_HOST_HCCHAR15_MPS_SET_MSK 0x000007ff
59667 /* The mask used to clear the ALT_USB_HOST_HCCHAR15_MPS register field value. */
59668 #define ALT_USB_HOST_HCCHAR15_MPS_CLR_MSK 0xfffff800
59669 /* The reset value of the ALT_USB_HOST_HCCHAR15_MPS register field. */
59670 #define ALT_USB_HOST_HCCHAR15_MPS_RESET 0x0
59671 /* Extracts the ALT_USB_HOST_HCCHAR15_MPS field value from a register. */
59672 #define ALT_USB_HOST_HCCHAR15_MPS_GET(value) (((value) & 0x000007ff) >> 0)
59673 /* Produces a ALT_USB_HOST_HCCHAR15_MPS register field value suitable for setting the register. */
59674 #define ALT_USB_HOST_HCCHAR15_MPS_SET(value) (((value) << 0) & 0x000007ff)
59675 
59676 /*
59677  * Field : epnum
59678  *
59679  * Endpoint Number (EPNum)
59680  *
59681  * Indicates the endpoint number on the device serving as the data
59682  *
59683  * source or sink.
59684  *
59685  * Field Enumeration Values:
59686  *
59687  * Enum | Value | Description
59688  * :--------------------------------------|:------|:--------------
59689  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT0 | 0x0 | End point 0
59690  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT1 | 0x1 | End point 1
59691  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT2 | 0x2 | End point 2
59692  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT3 | 0x3 | End point 3
59693  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT4 | 0x4 | End point 4
59694  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT5 | 0x5 | End point 5
59695  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT6 | 0x6 | End point 6
59696  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT7 | 0x7 | End point 7
59697  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT8 | 0x8 | End point 8
59698  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT9 | 0x9 | End point 9
59699  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT10 | 0xa | End point 10
59700  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT11 | 0xb | End point 11
59701  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT12 | 0xc | End point 12
59702  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT13 | 0xd | End point 13
59703  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT14 | 0xe | End point 14
59704  * ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT15 | 0xf | End point 15
59705  *
59706  * Field Access Macros:
59707  *
59708  */
59709 /*
59710  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59711  *
59712  * End point 0
59713  */
59714 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT0 0x0
59715 /*
59716  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59717  *
59718  * End point 1
59719  */
59720 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT1 0x1
59721 /*
59722  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59723  *
59724  * End point 2
59725  */
59726 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT2 0x2
59727 /*
59728  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59729  *
59730  * End point 3
59731  */
59732 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT3 0x3
59733 /*
59734  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59735  *
59736  * End point 4
59737  */
59738 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT4 0x4
59739 /*
59740  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59741  *
59742  * End point 5
59743  */
59744 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT5 0x5
59745 /*
59746  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59747  *
59748  * End point 6
59749  */
59750 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT6 0x6
59751 /*
59752  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59753  *
59754  * End point 7
59755  */
59756 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT7 0x7
59757 /*
59758  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59759  *
59760  * End point 8
59761  */
59762 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT8 0x8
59763 /*
59764  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59765  *
59766  * End point 9
59767  */
59768 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT9 0x9
59769 /*
59770  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59771  *
59772  * End point 10
59773  */
59774 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT10 0xa
59775 /*
59776  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59777  *
59778  * End point 11
59779  */
59780 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT11 0xb
59781 /*
59782  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59783  *
59784  * End point 12
59785  */
59786 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT12 0xc
59787 /*
59788  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59789  *
59790  * End point 13
59791  */
59792 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT13 0xd
59793 /*
59794  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59795  *
59796  * End point 14
59797  */
59798 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT14 0xe
59799 /*
59800  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
59801  *
59802  * End point 15
59803  */
59804 #define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT15 0xf
59805 
59806 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */
59807 #define ALT_USB_HOST_HCCHAR15_EPNUM_LSB 11
59808 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */
59809 #define ALT_USB_HOST_HCCHAR15_EPNUM_MSB 14
59810 /* The width in bits of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */
59811 #define ALT_USB_HOST_HCCHAR15_EPNUM_WIDTH 4
59812 /* The mask used to set the ALT_USB_HOST_HCCHAR15_EPNUM register field value. */
59813 #define ALT_USB_HOST_HCCHAR15_EPNUM_SET_MSK 0x00007800
59814 /* The mask used to clear the ALT_USB_HOST_HCCHAR15_EPNUM register field value. */
59815 #define ALT_USB_HOST_HCCHAR15_EPNUM_CLR_MSK 0xffff87ff
59816 /* The reset value of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */
59817 #define ALT_USB_HOST_HCCHAR15_EPNUM_RESET 0x0
59818 /* Extracts the ALT_USB_HOST_HCCHAR15_EPNUM field value from a register. */
59819 #define ALT_USB_HOST_HCCHAR15_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
59820 /* Produces a ALT_USB_HOST_HCCHAR15_EPNUM register field value suitable for setting the register. */
59821 #define ALT_USB_HOST_HCCHAR15_EPNUM_SET(value) (((value) << 11) & 0x00007800)
59822 
59823 /*
59824  * Field : epdir
59825  *
59826  * Endpoint Direction (EPDir)
59827  *
59828  * Indicates whether the transaction is IN or OUT.
59829  *
59830  * 1'b0: OUT
59831  *
59832  * 1'b1: IN
59833  *
59834  * Field Enumeration Values:
59835  *
59836  * Enum | Value | Description
59837  * :----------------------------------|:------|:--------------
59838  * ALT_USB_HOST_HCCHAR15_EPDIR_E_OUT | 0x0 | OUT Direction
59839  * ALT_USB_HOST_HCCHAR15_EPDIR_E_IN | 0x1 | IN Direction
59840  *
59841  * Field Access Macros:
59842  *
59843  */
59844 /*
59845  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPDIR
59846  *
59847  * OUT Direction
59848  */
59849 #define ALT_USB_HOST_HCCHAR15_EPDIR_E_OUT 0x0
59850 /*
59851  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPDIR
59852  *
59853  * IN Direction
59854  */
59855 #define ALT_USB_HOST_HCCHAR15_EPDIR_E_IN 0x1
59856 
59857 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */
59858 #define ALT_USB_HOST_HCCHAR15_EPDIR_LSB 15
59859 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */
59860 #define ALT_USB_HOST_HCCHAR15_EPDIR_MSB 15
59861 /* The width in bits of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */
59862 #define ALT_USB_HOST_HCCHAR15_EPDIR_WIDTH 1
59863 /* The mask used to set the ALT_USB_HOST_HCCHAR15_EPDIR register field value. */
59864 #define ALT_USB_HOST_HCCHAR15_EPDIR_SET_MSK 0x00008000
59865 /* The mask used to clear the ALT_USB_HOST_HCCHAR15_EPDIR register field value. */
59866 #define ALT_USB_HOST_HCCHAR15_EPDIR_CLR_MSK 0xffff7fff
59867 /* The reset value of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */
59868 #define ALT_USB_HOST_HCCHAR15_EPDIR_RESET 0x0
59869 /* Extracts the ALT_USB_HOST_HCCHAR15_EPDIR field value from a register. */
59870 #define ALT_USB_HOST_HCCHAR15_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
59871 /* Produces a ALT_USB_HOST_HCCHAR15_EPDIR register field value suitable for setting the register. */
59872 #define ALT_USB_HOST_HCCHAR15_EPDIR_SET(value) (((value) << 15) & 0x00008000)
59873 
59874 /*
59875  * Field : lspddev
59876  *
59877  * Low-Speed Device (LSpdDev)
59878  *
59879  * This field is Set by the application to indicate that this channel is
59880  *
59881  * communicating to a low-speed device.
59882  *
59883  * Field Enumeration Values:
59884  *
59885  * Enum | Value | Description
59886  * :-------------------------------------|:------|:----------------------------------------
59887  * ALT_USB_HOST_HCCHAR15_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
59888  * ALT_USB_HOST_HCCHAR15_LSPDDEV_E_END | 0x1 | Communicating with low speed device
59889  *
59890  * Field Access Macros:
59891  *
59892  */
59893 /*
59894  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_LSPDDEV
59895  *
59896  * Not Communicating with low speed device
59897  */
59898 #define ALT_USB_HOST_HCCHAR15_LSPDDEV_E_DISD 0x0
59899 /*
59900  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_LSPDDEV
59901  *
59902  * Communicating with low speed device
59903  */
59904 #define ALT_USB_HOST_HCCHAR15_LSPDDEV_E_END 0x1
59905 
59906 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */
59907 #define ALT_USB_HOST_HCCHAR15_LSPDDEV_LSB 17
59908 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */
59909 #define ALT_USB_HOST_HCCHAR15_LSPDDEV_MSB 17
59910 /* The width in bits of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */
59911 #define ALT_USB_HOST_HCCHAR15_LSPDDEV_WIDTH 1
59912 /* The mask used to set the ALT_USB_HOST_HCCHAR15_LSPDDEV register field value. */
59913 #define ALT_USB_HOST_HCCHAR15_LSPDDEV_SET_MSK 0x00020000
59914 /* The mask used to clear the ALT_USB_HOST_HCCHAR15_LSPDDEV register field value. */
59915 #define ALT_USB_HOST_HCCHAR15_LSPDDEV_CLR_MSK 0xfffdffff
59916 /* The reset value of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */
59917 #define ALT_USB_HOST_HCCHAR15_LSPDDEV_RESET 0x0
59918 /* Extracts the ALT_USB_HOST_HCCHAR15_LSPDDEV field value from a register. */
59919 #define ALT_USB_HOST_HCCHAR15_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
59920 /* Produces a ALT_USB_HOST_HCCHAR15_LSPDDEV register field value suitable for setting the register. */
59921 #define ALT_USB_HOST_HCCHAR15_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
59922 
59923 /*
59924  * Field : eptype
59925  *
59926  * Endpoint Type (EPType)
59927  *
59928  * Indicates the transfer type selected.
59929  *
59930  * 2'b00: Control
59931  *
59932  * 2'b01: Isochronous
59933  *
59934  * 2'b10: Bulk
59935  *
59936  * 2'b11: Interrupt
59937  *
59938  * Field Enumeration Values:
59939  *
59940  * Enum | Value | Description
59941  * :--------------------------------------|:------|:------------
59942  * ALT_USB_HOST_HCCHAR15_EPTYPE_E_CTL | 0x0 | Control
59943  * ALT_USB_HOST_HCCHAR15_EPTYPE_E_ISOC | 0x1 | Isochronous
59944  * ALT_USB_HOST_HCCHAR15_EPTYPE_E_BULK | 0x2 | Bulk
59945  * ALT_USB_HOST_HCCHAR15_EPTYPE_E_INTERR | 0x3 | Interrupt
59946  *
59947  * Field Access Macros:
59948  *
59949  */
59950 /*
59951  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE
59952  *
59953  * Control
59954  */
59955 #define ALT_USB_HOST_HCCHAR15_EPTYPE_E_CTL 0x0
59956 /*
59957  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE
59958  *
59959  * Isochronous
59960  */
59961 #define ALT_USB_HOST_HCCHAR15_EPTYPE_E_ISOC 0x1
59962 /*
59963  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE
59964  *
59965  * Bulk
59966  */
59967 #define ALT_USB_HOST_HCCHAR15_EPTYPE_E_BULK 0x2
59968 /*
59969  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE
59970  *
59971  * Interrupt
59972  */
59973 #define ALT_USB_HOST_HCCHAR15_EPTYPE_E_INTERR 0x3
59974 
59975 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */
59976 #define ALT_USB_HOST_HCCHAR15_EPTYPE_LSB 18
59977 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */
59978 #define ALT_USB_HOST_HCCHAR15_EPTYPE_MSB 19
59979 /* The width in bits of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */
59980 #define ALT_USB_HOST_HCCHAR15_EPTYPE_WIDTH 2
59981 /* The mask used to set the ALT_USB_HOST_HCCHAR15_EPTYPE register field value. */
59982 #define ALT_USB_HOST_HCCHAR15_EPTYPE_SET_MSK 0x000c0000
59983 /* The mask used to clear the ALT_USB_HOST_HCCHAR15_EPTYPE register field value. */
59984 #define ALT_USB_HOST_HCCHAR15_EPTYPE_CLR_MSK 0xfff3ffff
59985 /* The reset value of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */
59986 #define ALT_USB_HOST_HCCHAR15_EPTYPE_RESET 0x0
59987 /* Extracts the ALT_USB_HOST_HCCHAR15_EPTYPE field value from a register. */
59988 #define ALT_USB_HOST_HCCHAR15_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
59989 /* Produces a ALT_USB_HOST_HCCHAR15_EPTYPE register field value suitable for setting the register. */
59990 #define ALT_USB_HOST_HCCHAR15_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
59991 
59992 /*
59993  * Field : ec
59994  *
59995  * Multi Count (MC) / Error Count (EC)
59996  *
59997  * When the Split Enable bit of the Host Channel-n Split Control
59998  *
59999  * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
60000  *
60001  * the host the number of transactions that must be executed per
60002  *
60003  * microframe For this periodic endpoint. For non periodic transfers,
60004  *
60005  * this field is used only in DMA mode, and specifies the number
60006  *
60007  * packets to be fetched For this channel before the internal DMA
60008  *
60009  * engine changes arbitration.
60010  *
60011  * 2'b00: Reserved This field yields undefined results.
60012  *
60013  * 2'b01: 1 transaction
60014  *
60015  * 2'b10: 2 transactions to be issued For this endpoint per
60016  *
60017  * microframe
60018  *
60019  * 2'b11: 3 transactions to be issued For this endpoint per
60020  *
60021  * microframe
60022  *
60023  * When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
60024  *
60025  * number of immediate retries to be performed For a periodic split
60026  *
60027  * transactions on transaction errors. This field must be Set to at
60028  *
60029  * least 2'b01.
60030  *
60031  * Field Enumeration Values:
60032  *
60033  * Enum | Value | Description
60034  * :--------------------------------------|:------|:----------------------------------------------
60035  * ALT_USB_HOST_HCCHAR15_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
60036  * ALT_USB_HOST_HCCHAR15_EC_E_TRANSONE | 0x1 | 1 transaction
60037  * ALT_USB_HOST_HCCHAR15_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
60038  * : | | per microframe
60039  * ALT_USB_HOST_HCCHAR15_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
60040  * : | | per microframe
60041  *
60042  * Field Access Macros:
60043  *
60044  */
60045 /*
60046  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC
60047  *
60048  * Reserved This field yields undefined result
60049  */
60050 #define ALT_USB_HOST_HCCHAR15_EC_E_RSVD 0x0
60051 /*
60052  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC
60053  *
60054  * 1 transaction
60055  */
60056 #define ALT_USB_HOST_HCCHAR15_EC_E_TRANSONE 0x1
60057 /*
60058  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC
60059  *
60060  * 2 transactions to be issued for this endpoint per microframe
60061  */
60062 #define ALT_USB_HOST_HCCHAR15_EC_E_TRANSTWO 0x2
60063 /*
60064  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC
60065  *
60066  * 3 transactions to be issued for this endpoint per microframe
60067  */
60068 #define ALT_USB_HOST_HCCHAR15_EC_E_TRANSTHREE 0x3
60069 
60070 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EC register field. */
60071 #define ALT_USB_HOST_HCCHAR15_EC_LSB 20
60072 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EC register field. */
60073 #define ALT_USB_HOST_HCCHAR15_EC_MSB 21
60074 /* The width in bits of the ALT_USB_HOST_HCCHAR15_EC register field. */
60075 #define ALT_USB_HOST_HCCHAR15_EC_WIDTH 2
60076 /* The mask used to set the ALT_USB_HOST_HCCHAR15_EC register field value. */
60077 #define ALT_USB_HOST_HCCHAR15_EC_SET_MSK 0x00300000
60078 /* The mask used to clear the ALT_USB_HOST_HCCHAR15_EC register field value. */
60079 #define ALT_USB_HOST_HCCHAR15_EC_CLR_MSK 0xffcfffff
60080 /* The reset value of the ALT_USB_HOST_HCCHAR15_EC register field. */
60081 #define ALT_USB_HOST_HCCHAR15_EC_RESET 0x0
60082 /* Extracts the ALT_USB_HOST_HCCHAR15_EC field value from a register. */
60083 #define ALT_USB_HOST_HCCHAR15_EC_GET(value) (((value) & 0x00300000) >> 20)
60084 /* Produces a ALT_USB_HOST_HCCHAR15_EC register field value suitable for setting the register. */
60085 #define ALT_USB_HOST_HCCHAR15_EC_SET(value) (((value) << 20) & 0x00300000)
60086 
60087 /*
60088  * Field : devaddr
60089  *
60090  * Device Address (DevAddr)
60091  *
60092  * This field selects the specific device serving as the data source
60093  *
60094  * or sink.
60095  *
60096  * Field Access Macros:
60097  *
60098  */
60099 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */
60100 #define ALT_USB_HOST_HCCHAR15_DEVADDR_LSB 22
60101 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */
60102 #define ALT_USB_HOST_HCCHAR15_DEVADDR_MSB 28
60103 /* The width in bits of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */
60104 #define ALT_USB_HOST_HCCHAR15_DEVADDR_WIDTH 7
60105 /* The mask used to set the ALT_USB_HOST_HCCHAR15_DEVADDR register field value. */
60106 #define ALT_USB_HOST_HCCHAR15_DEVADDR_SET_MSK 0x1fc00000
60107 /* The mask used to clear the ALT_USB_HOST_HCCHAR15_DEVADDR register field value. */
60108 #define ALT_USB_HOST_HCCHAR15_DEVADDR_CLR_MSK 0xe03fffff
60109 /* The reset value of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */
60110 #define ALT_USB_HOST_HCCHAR15_DEVADDR_RESET 0x0
60111 /* Extracts the ALT_USB_HOST_HCCHAR15_DEVADDR field value from a register. */
60112 #define ALT_USB_HOST_HCCHAR15_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
60113 /* Produces a ALT_USB_HOST_HCCHAR15_DEVADDR register field value suitable for setting the register. */
60114 #define ALT_USB_HOST_HCCHAR15_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
60115 
60116 /*
60117  * Field : oddfrm
60118  *
60119  * Odd Frame (OddFrm)
60120  *
60121  * This field is set (reset) by the application to indicate that the OTG host must
60122  * perform
60123  *
60124  * a transfer in an odd (micro)frame. This field is applicable for only periodic
60125  *
60126  * (isochronous and interrupt) transactions.
60127  *
60128  * 1'b0: Even (micro)frame
60129  *
60130  * 1'b1: Odd (micro)frame
60131  *
60132  * Field Access Macros:
60133  *
60134  */
60135 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_ODDFRM register field. */
60136 #define ALT_USB_HOST_HCCHAR15_ODDFRM_LSB 29
60137 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_ODDFRM register field. */
60138 #define ALT_USB_HOST_HCCHAR15_ODDFRM_MSB 29
60139 /* The width in bits of the ALT_USB_HOST_HCCHAR15_ODDFRM register field. */
60140 #define ALT_USB_HOST_HCCHAR15_ODDFRM_WIDTH 1
60141 /* The mask used to set the ALT_USB_HOST_HCCHAR15_ODDFRM register field value. */
60142 #define ALT_USB_HOST_HCCHAR15_ODDFRM_SET_MSK 0x20000000
60143 /* The mask used to clear the ALT_USB_HOST_HCCHAR15_ODDFRM register field value. */
60144 #define ALT_USB_HOST_HCCHAR15_ODDFRM_CLR_MSK 0xdfffffff
60145 /* The reset value of the ALT_USB_HOST_HCCHAR15_ODDFRM register field. */
60146 #define ALT_USB_HOST_HCCHAR15_ODDFRM_RESET 0x0
60147 /* Extracts the ALT_USB_HOST_HCCHAR15_ODDFRM field value from a register. */
60148 #define ALT_USB_HOST_HCCHAR15_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
60149 /* Produces a ALT_USB_HOST_HCCHAR15_ODDFRM register field value suitable for setting the register. */
60150 #define ALT_USB_HOST_HCCHAR15_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
60151 
60152 /*
60153  * Field : chdis
60154  *
60155  * Channel Disable (ChDis)
60156  *
60157  * The application sets this bit to stop transmitting/receiving data
60158  *
60159  * on a channel, even before the transfer For that channel is
60160  *
60161  * complete. The application must wait For the Channel Disabled
60162  *
60163  * interrupt before treating the channel as disabled.
60164  *
60165  * Field Enumeration Values:
60166  *
60167  * Enum | Value | Description
60168  * :------------------------------------|:------|:----------------------------
60169  * ALT_USB_HOST_HCCHAR15_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
60170  * ALT_USB_HOST_HCCHAR15_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
60171  *
60172  * Field Access Macros:
60173  *
60174  */
60175 /*
60176  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHDIS
60177  *
60178  * Transmit/Recieve normal
60179  */
60180 #define ALT_USB_HOST_HCCHAR15_CHDIS_E_INACT 0x0
60181 /*
60182  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHDIS
60183  *
60184  * Stop transmitting/receiving
60185  */
60186 #define ALT_USB_HOST_HCCHAR15_CHDIS_E_ACT 0x1
60187 
60188 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */
60189 #define ALT_USB_HOST_HCCHAR15_CHDIS_LSB 30
60190 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */
60191 #define ALT_USB_HOST_HCCHAR15_CHDIS_MSB 30
60192 /* The width in bits of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */
60193 #define ALT_USB_HOST_HCCHAR15_CHDIS_WIDTH 1
60194 /* The mask used to set the ALT_USB_HOST_HCCHAR15_CHDIS register field value. */
60195 #define ALT_USB_HOST_HCCHAR15_CHDIS_SET_MSK 0x40000000
60196 /* The mask used to clear the ALT_USB_HOST_HCCHAR15_CHDIS register field value. */
60197 #define ALT_USB_HOST_HCCHAR15_CHDIS_CLR_MSK 0xbfffffff
60198 /* The reset value of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */
60199 #define ALT_USB_HOST_HCCHAR15_CHDIS_RESET 0x0
60200 /* Extracts the ALT_USB_HOST_HCCHAR15_CHDIS field value from a register. */
60201 #define ALT_USB_HOST_HCCHAR15_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
60202 /* Produces a ALT_USB_HOST_HCCHAR15_CHDIS register field value suitable for setting the register. */
60203 #define ALT_USB_HOST_HCCHAR15_CHDIS_SET(value) (((value) << 30) & 0x40000000)
60204 
60205 /*
60206  * Field : chena
60207  *
60208  * Channel Enable (ChEna)
60209  *
60210  * When Scatter/Gather mode is enabled
60211  *
60212  * 1'b0: Indicates that the descriptor structure is not yet ready.
60213  *
60214  * 1'b1: Indicates that the descriptor structure and data buffer with
60215  *
60216  * data is setup and this channel can access the descriptor.
60217  *
60218  * When Scatter/Gather mode is disabled
60219  *
60220  * This field is set by the application and cleared by the OTG host.
60221  *
60222  * 1'b0: Channel disabled
60223  *
60224  * 1'b1: Channel enabled
60225  *
60226  * Field Enumeration Values:
60227  *
60228  * Enum | Value | Description
60229  * :------------------------------------|:------|:-------------------------------------------------
60230  * ALT_USB_HOST_HCCHAR15_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
60231  * : | | yet ready
60232  * ALT_USB_HOST_HCCHAR15_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
60233  * : | | data buffer with data is setup and this
60234  * : | | channel can access the descriptor
60235  *
60236  * Field Access Macros:
60237  *
60238  */
60239 /*
60240  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHENA
60241  *
60242  * Indicates that the descriptor structure is not yet ready
60243  */
60244 #define ALT_USB_HOST_HCCHAR15_CHENA_E_INACT 0x0
60245 /*
60246  * Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHENA
60247  *
60248  * Indicates that the descriptor structure and data buffer with data is
60249  * setup and this channel can access the descriptor
60250  */
60251 #define ALT_USB_HOST_HCCHAR15_CHENA_E_ACT 0x1
60252 
60253 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_CHENA register field. */
60254 #define ALT_USB_HOST_HCCHAR15_CHENA_LSB 31
60255 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_CHENA register field. */
60256 #define ALT_USB_HOST_HCCHAR15_CHENA_MSB 31
60257 /* The width in bits of the ALT_USB_HOST_HCCHAR15_CHENA register field. */
60258 #define ALT_USB_HOST_HCCHAR15_CHENA_WIDTH 1
60259 /* The mask used to set the ALT_USB_HOST_HCCHAR15_CHENA register field value. */
60260 #define ALT_USB_HOST_HCCHAR15_CHENA_SET_MSK 0x80000000
60261 /* The mask used to clear the ALT_USB_HOST_HCCHAR15_CHENA register field value. */
60262 #define ALT_USB_HOST_HCCHAR15_CHENA_CLR_MSK 0x7fffffff
60263 /* The reset value of the ALT_USB_HOST_HCCHAR15_CHENA register field. */
60264 #define ALT_USB_HOST_HCCHAR15_CHENA_RESET 0x0
60265 /* Extracts the ALT_USB_HOST_HCCHAR15_CHENA field value from a register. */
60266 #define ALT_USB_HOST_HCCHAR15_CHENA_GET(value) (((value) & 0x80000000) >> 31)
60267 /* Produces a ALT_USB_HOST_HCCHAR15_CHENA register field value suitable for setting the register. */
60268 #define ALT_USB_HOST_HCCHAR15_CHENA_SET(value) (((value) << 31) & 0x80000000)
60269 
60270 #ifndef __ASSEMBLY__
60271 /*
60272  * WARNING: The C register and register group struct declarations are provided for
60273  * convenience and illustrative purposes. They should, however, be used with
60274  * caution as the C language standard provides no guarantees about the alignment or
60275  * atomicity of device memory accesses. The recommended practice for writing
60276  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60277  * alt_write_word() functions.
60278  *
60279  * The struct declaration for register ALT_USB_HOST_HCCHAR15.
60280  */
60281 struct ALT_USB_HOST_HCCHAR15_s
60282 {
60283  uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR15_MPS */
60284  uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR15_EPNUM */
60285  uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR15_EPDIR */
60286  uint32_t : 1; /* *UNDEFINED* */
60287  uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR15_LSPDDEV */
60288  uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR15_EPTYPE */
60289  uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR15_EC */
60290  uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR15_DEVADDR */
60291  uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR15_ODDFRM */
60292  uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR15_CHDIS */
60293  uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR15_CHENA */
60294 };
60295 
60296 /* The typedef declaration for register ALT_USB_HOST_HCCHAR15. */
60297 typedef volatile struct ALT_USB_HOST_HCCHAR15_s ALT_USB_HOST_HCCHAR15_t;
60298 #endif /* __ASSEMBLY__ */
60299 
60300 /* The reset value of the ALT_USB_HOST_HCCHAR15 register. */
60301 #define ALT_USB_HOST_HCCHAR15_RESET 0x00000000
60302 /* The byte offset of the ALT_USB_HOST_HCCHAR15 register from the beginning of the component. */
60303 #define ALT_USB_HOST_HCCHAR15_OFST 0x2e0
60304 /* The address of the ALT_USB_HOST_HCCHAR15 register. */
60305 #define ALT_USB_HOST_HCCHAR15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR15_OFST))
60306 
60307 /*
60308  * Register : hcsplt15
60309  *
60310  * Host Channel 15 Split Control Register
60311  *
60312  * Register Layout
60313  *
60314  * Bits | Access | Reset | Description
60315  * :--------|:-------|:------|:-------------------------------
60316  * [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT15_PRTADDR
60317  * [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT15_HUBADDR
60318  * [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT15_XACTPOS
60319  * [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT15_COMPSPLT
60320  * [30:17] | ??? | 0x0 | *UNDEFINED*
60321  * [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT15_SPLTENA
60322  *
60323  */
60324 /*
60325  * Field : prtaddr
60326  *
60327  * Port Address (PrtAddr)
60328  *
60329  * This field is the port number of the recipient transaction
60330  *
60331  * translator.
60332  *
60333  * Field Access Macros:
60334  *
60335  */
60336 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */
60337 #define ALT_USB_HOST_HCSPLT15_PRTADDR_LSB 0
60338 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */
60339 #define ALT_USB_HOST_HCSPLT15_PRTADDR_MSB 6
60340 /* The width in bits of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */
60341 #define ALT_USB_HOST_HCSPLT15_PRTADDR_WIDTH 7
60342 /* The mask used to set the ALT_USB_HOST_HCSPLT15_PRTADDR register field value. */
60343 #define ALT_USB_HOST_HCSPLT15_PRTADDR_SET_MSK 0x0000007f
60344 /* The mask used to clear the ALT_USB_HOST_HCSPLT15_PRTADDR register field value. */
60345 #define ALT_USB_HOST_HCSPLT15_PRTADDR_CLR_MSK 0xffffff80
60346 /* The reset value of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */
60347 #define ALT_USB_HOST_HCSPLT15_PRTADDR_RESET 0x0
60348 /* Extracts the ALT_USB_HOST_HCSPLT15_PRTADDR field value from a register. */
60349 #define ALT_USB_HOST_HCSPLT15_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
60350 /* Produces a ALT_USB_HOST_HCSPLT15_PRTADDR register field value suitable for setting the register. */
60351 #define ALT_USB_HOST_HCSPLT15_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
60352 
60353 /*
60354  * Field : hubaddr
60355  *
60356  * Hub Address (HubAddr)
60357  *
60358  * This field holds the device address of the transaction translator's
60359  *
60360  * hub.
60361  *
60362  * Field Access Macros:
60363  *
60364  */
60365 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */
60366 #define ALT_USB_HOST_HCSPLT15_HUBADDR_LSB 7
60367 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */
60368 #define ALT_USB_HOST_HCSPLT15_HUBADDR_MSB 13
60369 /* The width in bits of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */
60370 #define ALT_USB_HOST_HCSPLT15_HUBADDR_WIDTH 7
60371 /* The mask used to set the ALT_USB_HOST_HCSPLT15_HUBADDR register field value. */
60372 #define ALT_USB_HOST_HCSPLT15_HUBADDR_SET_MSK 0x00003f80
60373 /* The mask used to clear the ALT_USB_HOST_HCSPLT15_HUBADDR register field value. */
60374 #define ALT_USB_HOST_HCSPLT15_HUBADDR_CLR_MSK 0xffffc07f
60375 /* The reset value of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */
60376 #define ALT_USB_HOST_HCSPLT15_HUBADDR_RESET 0x0
60377 /* Extracts the ALT_USB_HOST_HCSPLT15_HUBADDR field value from a register. */
60378 #define ALT_USB_HOST_HCSPLT15_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
60379 /* Produces a ALT_USB_HOST_HCSPLT15_HUBADDR register field value suitable for setting the register. */
60380 #define ALT_USB_HOST_HCSPLT15_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
60381 
60382 /*
60383  * Field : xactpos
60384  *
60385  * Transaction Position (XactPos)
60386  *
60387  * This field is used to determine whether to send all, first, middle,
60388  *
60389  * or last payloads with each OUT transaction.
60390  *
60391  * 2'b11: All. This is the entire data payload is of this transaction
60392  *
60393  * (which is less than or equal to 188 bytes).
60394  *
60395  * 2'b10: Begin. This is the first data payload of this transaction
60396  *
60397  * (which is larger than 188 bytes).
60398  *
60399  * 2'b00: Mid. This is the middle payload of this transaction
60400  *
60401  * (which is larger than 188 bytes).
60402  *
60403  * 2'b01: End. This is the last payload of this transaction (which
60404  *
60405  * is larger than 188 bytes).
60406  *
60407  * Field Enumeration Values:
60408  *
60409  * Enum | Value | Description
60410  * :---------------------------------------|:------|:------------------------------------------------
60411  * ALT_USB_HOST_HCSPLT15_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
60412  * : | | transaction (which is larger than 188 bytes)
60413  * ALT_USB_HOST_HCSPLT15_XACTPOS_E_END | 0x1 | End. This is the last payload of this
60414  * : | | transaction (which is larger than 188 bytes)
60415  * ALT_USB_HOST_HCSPLT15_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
60416  * : | | transaction (which is larger than 188 bytes)
60417  * ALT_USB_HOST_HCSPLT15_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
60418  * : | | transaction (which is less than or equal to 188
60419  * : | | bytes)
60420  *
60421  * Field Access Macros:
60422  *
60423  */
60424 /*
60425  * Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS
60426  *
60427  * Mid. This is the middle payload of this transaction (which is larger than 188
60428  * bytes)
60429  */
60430 #define ALT_USB_HOST_HCSPLT15_XACTPOS_E_MIDDLE 0x0
60431 /*
60432  * Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS
60433  *
60434  * End. This is the last payload of this transaction (which is larger than 188
60435  * bytes)
60436  */
60437 #define ALT_USB_HOST_HCSPLT15_XACTPOS_E_END 0x1
60438 /*
60439  * Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS
60440  *
60441  * Begin. This is the first data payload of this transaction (which is larger than
60442  * 188 bytes)
60443  */
60444 #define ALT_USB_HOST_HCSPLT15_XACTPOS_E_BEGIN 0x2
60445 /*
60446  * Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS
60447  *
60448  * All. This is the entire data payload is of this transaction (which is less than
60449  * or equal to 188 bytes)
60450  */
60451 #define ALT_USB_HOST_HCSPLT15_XACTPOS_E_ALL 0x3
60452 
60453 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */
60454 #define ALT_USB_HOST_HCSPLT15_XACTPOS_LSB 14
60455 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */
60456 #define ALT_USB_HOST_HCSPLT15_XACTPOS_MSB 15
60457 /* The width in bits of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */
60458 #define ALT_USB_HOST_HCSPLT15_XACTPOS_WIDTH 2
60459 /* The mask used to set the ALT_USB_HOST_HCSPLT15_XACTPOS register field value. */
60460 #define ALT_USB_HOST_HCSPLT15_XACTPOS_SET_MSK 0x0000c000
60461 /* The mask used to clear the ALT_USB_HOST_HCSPLT15_XACTPOS register field value. */
60462 #define ALT_USB_HOST_HCSPLT15_XACTPOS_CLR_MSK 0xffff3fff
60463 /* The reset value of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */
60464 #define ALT_USB_HOST_HCSPLT15_XACTPOS_RESET 0x0
60465 /* Extracts the ALT_USB_HOST_HCSPLT15_XACTPOS field value from a register. */
60466 #define ALT_USB_HOST_HCSPLT15_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
60467 /* Produces a ALT_USB_HOST_HCSPLT15_XACTPOS register field value suitable for setting the register. */
60468 #define ALT_USB_HOST_HCSPLT15_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
60469 
60470 /*
60471  * Field : compsplt
60472  *
60473  * Do Complete Split (CompSplt)
60474  *
60475  * The application sets this field to request the OTG host to perform
60476  *
60477  * a complete split transaction.
60478  *
60479  * Field Enumeration Values:
60480  *
60481  * Enum | Value | Description
60482  * :-----------------------------------------|:------|:---------------------
60483  * ALT_USB_HOST_HCSPLT15_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
60484  * ALT_USB_HOST_HCSPLT15_COMPSPLT_E_SPLIT | 0x1 | Split transaction
60485  *
60486  * Field Access Macros:
60487  *
60488  */
60489 /*
60490  * Enumerated value for register field ALT_USB_HOST_HCSPLT15_COMPSPLT
60491  *
60492  * No split transaction
60493  */
60494 #define ALT_USB_HOST_HCSPLT15_COMPSPLT_E_NOSPLIT 0x0
60495 /*
60496  * Enumerated value for register field ALT_USB_HOST_HCSPLT15_COMPSPLT
60497  *
60498  * Split transaction
60499  */
60500 #define ALT_USB_HOST_HCSPLT15_COMPSPLT_E_SPLIT 0x1
60501 
60502 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */
60503 #define ALT_USB_HOST_HCSPLT15_COMPSPLT_LSB 16
60504 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */
60505 #define ALT_USB_HOST_HCSPLT15_COMPSPLT_MSB 16
60506 /* The width in bits of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */
60507 #define ALT_USB_HOST_HCSPLT15_COMPSPLT_WIDTH 1
60508 /* The mask used to set the ALT_USB_HOST_HCSPLT15_COMPSPLT register field value. */
60509 #define ALT_USB_HOST_HCSPLT15_COMPSPLT_SET_MSK 0x00010000
60510 /* The mask used to clear the ALT_USB_HOST_HCSPLT15_COMPSPLT register field value. */
60511 #define ALT_USB_HOST_HCSPLT15_COMPSPLT_CLR_MSK 0xfffeffff
60512 /* The reset value of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */
60513 #define ALT_USB_HOST_HCSPLT15_COMPSPLT_RESET 0x0
60514 /* Extracts the ALT_USB_HOST_HCSPLT15_COMPSPLT field value from a register. */
60515 #define ALT_USB_HOST_HCSPLT15_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
60516 /* Produces a ALT_USB_HOST_HCSPLT15_COMPSPLT register field value suitable for setting the register. */
60517 #define ALT_USB_HOST_HCSPLT15_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
60518 
60519 /*
60520  * Field : spltena
60521  *
60522  * Split Enable (SpltEna)
60523  *
60524  * The application sets this field to indicate that this channel is
60525  *
60526  * enabled to perform split transactions.
60527  *
60528  * Field Enumeration Values:
60529  *
60530  * Enum | Value | Description
60531  * :-------------------------------------|:------|:------------------
60532  * ALT_USB_HOST_HCSPLT15_SPLTENA_E_DISD | 0x0 | Split not enabled
60533  * ALT_USB_HOST_HCSPLT15_SPLTENA_E_END | 0x1 | Split enabled
60534  *
60535  * Field Access Macros:
60536  *
60537  */
60538 /*
60539  * Enumerated value for register field ALT_USB_HOST_HCSPLT15_SPLTENA
60540  *
60541  * Split not enabled
60542  */
60543 #define ALT_USB_HOST_HCSPLT15_SPLTENA_E_DISD 0x0
60544 /*
60545  * Enumerated value for register field ALT_USB_HOST_HCSPLT15_SPLTENA
60546  *
60547  * Split enabled
60548  */
60549 #define ALT_USB_HOST_HCSPLT15_SPLTENA_E_END 0x1
60550 
60551 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */
60552 #define ALT_USB_HOST_HCSPLT15_SPLTENA_LSB 31
60553 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */
60554 #define ALT_USB_HOST_HCSPLT15_SPLTENA_MSB 31
60555 /* The width in bits of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */
60556 #define ALT_USB_HOST_HCSPLT15_SPLTENA_WIDTH 1
60557 /* The mask used to set the ALT_USB_HOST_HCSPLT15_SPLTENA register field value. */
60558 #define ALT_USB_HOST_HCSPLT15_SPLTENA_SET_MSK 0x80000000
60559 /* The mask used to clear the ALT_USB_HOST_HCSPLT15_SPLTENA register field value. */
60560 #define ALT_USB_HOST_HCSPLT15_SPLTENA_CLR_MSK 0x7fffffff
60561 /* The reset value of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */
60562 #define ALT_USB_HOST_HCSPLT15_SPLTENA_RESET 0x0
60563 /* Extracts the ALT_USB_HOST_HCSPLT15_SPLTENA field value from a register. */
60564 #define ALT_USB_HOST_HCSPLT15_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
60565 /* Produces a ALT_USB_HOST_HCSPLT15_SPLTENA register field value suitable for setting the register. */
60566 #define ALT_USB_HOST_HCSPLT15_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
60567 
60568 #ifndef __ASSEMBLY__
60569 /*
60570  * WARNING: The C register and register group struct declarations are provided for
60571  * convenience and illustrative purposes. They should, however, be used with
60572  * caution as the C language standard provides no guarantees about the alignment or
60573  * atomicity of device memory accesses. The recommended practice for writing
60574  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60575  * alt_write_word() functions.
60576  *
60577  * The struct declaration for register ALT_USB_HOST_HCSPLT15.
60578  */
60579 struct ALT_USB_HOST_HCSPLT15_s
60580 {
60581  uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT15_PRTADDR */
60582  uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT15_HUBADDR */
60583  uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT15_XACTPOS */
60584  uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT15_COMPSPLT */
60585  uint32_t : 14; /* *UNDEFINED* */
60586  uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT15_SPLTENA */
60587 };
60588 
60589 /* The typedef declaration for register ALT_USB_HOST_HCSPLT15. */
60590 typedef volatile struct ALT_USB_HOST_HCSPLT15_s ALT_USB_HOST_HCSPLT15_t;
60591 #endif /* __ASSEMBLY__ */
60592 
60593 /* The reset value of the ALT_USB_HOST_HCSPLT15 register. */
60594 #define ALT_USB_HOST_HCSPLT15_RESET 0x00000000
60595 /* The byte offset of the ALT_USB_HOST_HCSPLT15 register from the beginning of the component. */
60596 #define ALT_USB_HOST_HCSPLT15_OFST 0x2e4
60597 /* The address of the ALT_USB_HOST_HCSPLT15 register. */
60598 #define ALT_USB_HOST_HCSPLT15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT15_OFST))
60599 
60600 /*
60601  * Register : hcint15
60602  *
60603  * Host Channel 15 Interrupt Register
60604  *
60605  * Register Layout
60606  *
60607  * Bits | Access | Reset | Description
60608  * :--------|:-------|:------|:---------------------------------------
60609  * [0] | RW | 0x0 | ALT_USB_HOST_HCINT15_XFERCOMPL
60610  * [1] | RW | 0x0 | ALT_USB_HOST_HCINT15_CHHLTD
60611  * [2] | RW | 0x0 | ALT_USB_HOST_HCINT15_AHBERR
60612  * [3] | RW | 0x0 | ALT_USB_HOST_HCINT15_STALL
60613  * [4] | RW | 0x0 | ALT_USB_HOST_HCINT15_NAK
60614  * [5] | RW | 0x0 | ALT_USB_HOST_HCINT15_ACK
60615  * [6] | RW | 0x0 | ALT_USB_HOST_HCINT15_NYET
60616  * [7] | RW | 0x0 | ALT_USB_HOST_HCINT15_XACTERR
60617  * [8] | RW | 0x0 | ALT_USB_HOST_HCINT15_BBLERR
60618  * [9] | RW | 0x0 | ALT_USB_HOST_HCINT15_FRMOVRUN
60619  * [10] | RW | 0x0 | ALT_USB_HOST_HCINT15_DATATGLERR
60620  * [11] | RW | 0x0 | ALT_USB_HOST_HCINT15_BNAINTR
60621  * [12] | RW | 0x0 | ALT_USB_HOST_HCINT15_XCS_XACT_ERR
60622  * [13] | RW | 0x0 | ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR
60623  * [31:14] | ??? | 0x0 | *UNDEFINED*
60624  *
60625  */
60626 /*
60627  * Field : xfercompl
60628  *
60629  * Transfer Completed (XferCompl)
60630  *
60631  * Transfer completed normally without any errors.This bit can be set only by the
60632  * core and the application should write 1 to clear it.
60633  *
60634  * For Scatter/Gather DMA mode, it indicates that current descriptor processing got
60635  *
60636  * completed with IOC bit set in its descriptor.
60637  *
60638  * In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
60639  * without
60640  *
60641  * any errors.
60642  *
60643  * Field Enumeration Values:
60644  *
60645  * Enum | Value | Description
60646  * :---------------------------------------|:------|:-----------------------------------------------
60647  * ALT_USB_HOST_HCINT15_XFERCOMPL_E_INACT | 0x0 | No transfer
60648  * ALT_USB_HOST_HCINT15_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
60649  *
60650  * Field Access Macros:
60651  *
60652  */
60653 /*
60654  * Enumerated value for register field ALT_USB_HOST_HCINT15_XFERCOMPL
60655  *
60656  * No transfer
60657  */
60658 #define ALT_USB_HOST_HCINT15_XFERCOMPL_E_INACT 0x0
60659 /*
60660  * Enumerated value for register field ALT_USB_HOST_HCINT15_XFERCOMPL
60661  *
60662  * Transfer completed normally without any errors
60663  */
60664 #define ALT_USB_HOST_HCINT15_XFERCOMPL_E_ACT 0x1
60665 
60666 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */
60667 #define ALT_USB_HOST_HCINT15_XFERCOMPL_LSB 0
60668 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */
60669 #define ALT_USB_HOST_HCINT15_XFERCOMPL_MSB 0
60670 /* The width in bits of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */
60671 #define ALT_USB_HOST_HCINT15_XFERCOMPL_WIDTH 1
60672 /* The mask used to set the ALT_USB_HOST_HCINT15_XFERCOMPL register field value. */
60673 #define ALT_USB_HOST_HCINT15_XFERCOMPL_SET_MSK 0x00000001
60674 /* The mask used to clear the ALT_USB_HOST_HCINT15_XFERCOMPL register field value. */
60675 #define ALT_USB_HOST_HCINT15_XFERCOMPL_CLR_MSK 0xfffffffe
60676 /* The reset value of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */
60677 #define ALT_USB_HOST_HCINT15_XFERCOMPL_RESET 0x0
60678 /* Extracts the ALT_USB_HOST_HCINT15_XFERCOMPL field value from a register. */
60679 #define ALT_USB_HOST_HCINT15_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
60680 /* Produces a ALT_USB_HOST_HCINT15_XFERCOMPL register field value suitable for setting the register. */
60681 #define ALT_USB_HOST_HCINT15_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
60682 
60683 /*
60684  * Field : chhltd
60685  *
60686  * Channel Halted (ChHltd)
60687  *
60688  * In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
60689  * either because of any USB transaction error or in response to disable request by
60690  * the application or because of a completed transfer.
60691  *
60692  * in Scatter/gather DMA mode, this indicates that transfer completed due to any of
60693  * the following
60694  *
60695  * . EOL being set in descriptor
60696  *
60697  * . AHB error
60698  *
60699  * . Excessive transaction errors
60700  *
60701  * . Babble
60702  *
60703  * . Stall
60704  *
60705  * Field Enumeration Values:
60706  *
60707  * Enum | Value | Description
60708  * :------------------------------------|:------|:-------------------
60709  * ALT_USB_HOST_HCINT15_CHHLTD_E_INACT | 0x0 | Channel not halted
60710  * ALT_USB_HOST_HCINT15_CHHLTD_E_ACT | 0x1 | Channel Halted
60711  *
60712  * Field Access Macros:
60713  *
60714  */
60715 /*
60716  * Enumerated value for register field ALT_USB_HOST_HCINT15_CHHLTD
60717  *
60718  * Channel not halted
60719  */
60720 #define ALT_USB_HOST_HCINT15_CHHLTD_E_INACT 0x0
60721 /*
60722  * Enumerated value for register field ALT_USB_HOST_HCINT15_CHHLTD
60723  *
60724  * Channel Halted
60725  */
60726 #define ALT_USB_HOST_HCINT15_CHHLTD_E_ACT 0x1
60727 
60728 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_CHHLTD register field. */
60729 #define ALT_USB_HOST_HCINT15_CHHLTD_LSB 1
60730 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_CHHLTD register field. */
60731 #define ALT_USB_HOST_HCINT15_CHHLTD_MSB 1
60732 /* The width in bits of the ALT_USB_HOST_HCINT15_CHHLTD register field. */
60733 #define ALT_USB_HOST_HCINT15_CHHLTD_WIDTH 1
60734 /* The mask used to set the ALT_USB_HOST_HCINT15_CHHLTD register field value. */
60735 #define ALT_USB_HOST_HCINT15_CHHLTD_SET_MSK 0x00000002
60736 /* The mask used to clear the ALT_USB_HOST_HCINT15_CHHLTD register field value. */
60737 #define ALT_USB_HOST_HCINT15_CHHLTD_CLR_MSK 0xfffffffd
60738 /* The reset value of the ALT_USB_HOST_HCINT15_CHHLTD register field. */
60739 #define ALT_USB_HOST_HCINT15_CHHLTD_RESET 0x0
60740 /* Extracts the ALT_USB_HOST_HCINT15_CHHLTD field value from a register. */
60741 #define ALT_USB_HOST_HCINT15_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
60742 /* Produces a ALT_USB_HOST_HCINT15_CHHLTD register field value suitable for setting the register. */
60743 #define ALT_USB_HOST_HCINT15_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
60744 
60745 /*
60746  * Field : ahberr
60747  *
60748  * AHB Error (AHBErr)
60749  *
60750  * This is generated only in Internal DMA mode when there is an
60751  *
60752  * AHB error during AHB read/write. The application can read the
60753  *
60754  * corresponding channel's DMA address register to get the error
60755  *
60756  * address.
60757  *
60758  * Field Enumeration Values:
60759  *
60760  * Enum | Value | Description
60761  * :------------------------------------|:------|:--------------------------------
60762  * ALT_USB_HOST_HCINT15_AHBERR_E_INACT | 0x0 | No AHB error
60763  * ALT_USB_HOST_HCINT15_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
60764  *
60765  * Field Access Macros:
60766  *
60767  */
60768 /*
60769  * Enumerated value for register field ALT_USB_HOST_HCINT15_AHBERR
60770  *
60771  * No AHB error
60772  */
60773 #define ALT_USB_HOST_HCINT15_AHBERR_E_INACT 0x0
60774 /*
60775  * Enumerated value for register field ALT_USB_HOST_HCINT15_AHBERR
60776  *
60777  * AHB error during AHB read/write
60778  */
60779 #define ALT_USB_HOST_HCINT15_AHBERR_E_ACT 0x1
60780 
60781 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_AHBERR register field. */
60782 #define ALT_USB_HOST_HCINT15_AHBERR_LSB 2
60783 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_AHBERR register field. */
60784 #define ALT_USB_HOST_HCINT15_AHBERR_MSB 2
60785 /* The width in bits of the ALT_USB_HOST_HCINT15_AHBERR register field. */
60786 #define ALT_USB_HOST_HCINT15_AHBERR_WIDTH 1
60787 /* The mask used to set the ALT_USB_HOST_HCINT15_AHBERR register field value. */
60788 #define ALT_USB_HOST_HCINT15_AHBERR_SET_MSK 0x00000004
60789 /* The mask used to clear the ALT_USB_HOST_HCINT15_AHBERR register field value. */
60790 #define ALT_USB_HOST_HCINT15_AHBERR_CLR_MSK 0xfffffffb
60791 /* The reset value of the ALT_USB_HOST_HCINT15_AHBERR register field. */
60792 #define ALT_USB_HOST_HCINT15_AHBERR_RESET 0x0
60793 /* Extracts the ALT_USB_HOST_HCINT15_AHBERR field value from a register. */
60794 #define ALT_USB_HOST_HCINT15_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
60795 /* Produces a ALT_USB_HOST_HCINT15_AHBERR register field value suitable for setting the register. */
60796 #define ALT_USB_HOST_HCINT15_AHBERR_SET(value) (((value) << 2) & 0x00000004)
60797 
60798 /*
60799  * Field : stall
60800  *
60801  * STALL Response Received Interrupt (STALL)
60802  *
60803  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
60804  *
60805  * in the core.This bit can be set only by the core and the application should
60806  * write 1 to clear
60807  *
60808  * it.
60809  *
60810  * Field Enumeration Values:
60811  *
60812  * Enum | Value | Description
60813  * :-----------------------------------|:------|:-------------------
60814  * ALT_USB_HOST_HCINT15_STALL_E_INACT | 0x0 | No Stall Interrupt
60815  * ALT_USB_HOST_HCINT15_STALL_E_ACT | 0x1 | Stall Interrupt
60816  *
60817  * Field Access Macros:
60818  *
60819  */
60820 /*
60821  * Enumerated value for register field ALT_USB_HOST_HCINT15_STALL
60822  *
60823  * No Stall Interrupt
60824  */
60825 #define ALT_USB_HOST_HCINT15_STALL_E_INACT 0x0
60826 /*
60827  * Enumerated value for register field ALT_USB_HOST_HCINT15_STALL
60828  *
60829  * Stall Interrupt
60830  */
60831 #define ALT_USB_HOST_HCINT15_STALL_E_ACT 0x1
60832 
60833 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_STALL register field. */
60834 #define ALT_USB_HOST_HCINT15_STALL_LSB 3
60835 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_STALL register field. */
60836 #define ALT_USB_HOST_HCINT15_STALL_MSB 3
60837 /* The width in bits of the ALT_USB_HOST_HCINT15_STALL register field. */
60838 #define ALT_USB_HOST_HCINT15_STALL_WIDTH 1
60839 /* The mask used to set the ALT_USB_HOST_HCINT15_STALL register field value. */
60840 #define ALT_USB_HOST_HCINT15_STALL_SET_MSK 0x00000008
60841 /* The mask used to clear the ALT_USB_HOST_HCINT15_STALL register field value. */
60842 #define ALT_USB_HOST_HCINT15_STALL_CLR_MSK 0xfffffff7
60843 /* The reset value of the ALT_USB_HOST_HCINT15_STALL register field. */
60844 #define ALT_USB_HOST_HCINT15_STALL_RESET 0x0
60845 /* Extracts the ALT_USB_HOST_HCINT15_STALL field value from a register. */
60846 #define ALT_USB_HOST_HCINT15_STALL_GET(value) (((value) & 0x00000008) >> 3)
60847 /* Produces a ALT_USB_HOST_HCINT15_STALL register field value suitable for setting the register. */
60848 #define ALT_USB_HOST_HCINT15_STALL_SET(value) (((value) << 3) & 0x00000008)
60849 
60850 /*
60851  * Field : nak
60852  *
60853  * NAK Response Received Interrupt (NAK)
60854  *
60855  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
60856  *
60857  * in the core.This bit can be set only by the core and the application should
60858  * write 1 to clear
60859  *
60860  * it.
60861  *
60862  * Field Enumeration Values:
60863  *
60864  * Enum | Value | Description
60865  * :---------------------------------|:------|:-----------------------------------
60866  * ALT_USB_HOST_HCINT15_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
60867  * ALT_USB_HOST_HCINT15_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
60868  *
60869  * Field Access Macros:
60870  *
60871  */
60872 /*
60873  * Enumerated value for register field ALT_USB_HOST_HCINT15_NAK
60874  *
60875  * No NAK Response Received Interrupt
60876  */
60877 #define ALT_USB_HOST_HCINT15_NAK_E_INACT 0x0
60878 /*
60879  * Enumerated value for register field ALT_USB_HOST_HCINT15_NAK
60880  *
60881  * NAK Response Received Interrupt
60882  */
60883 #define ALT_USB_HOST_HCINT15_NAK_E_ACT 0x1
60884 
60885 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_NAK register field. */
60886 #define ALT_USB_HOST_HCINT15_NAK_LSB 4
60887 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_NAK register field. */
60888 #define ALT_USB_HOST_HCINT15_NAK_MSB 4
60889 /* The width in bits of the ALT_USB_HOST_HCINT15_NAK register field. */
60890 #define ALT_USB_HOST_HCINT15_NAK_WIDTH 1
60891 /* The mask used to set the ALT_USB_HOST_HCINT15_NAK register field value. */
60892 #define ALT_USB_HOST_HCINT15_NAK_SET_MSK 0x00000010
60893 /* The mask used to clear the ALT_USB_HOST_HCINT15_NAK register field value. */
60894 #define ALT_USB_HOST_HCINT15_NAK_CLR_MSK 0xffffffef
60895 /* The reset value of the ALT_USB_HOST_HCINT15_NAK register field. */
60896 #define ALT_USB_HOST_HCINT15_NAK_RESET 0x0
60897 /* Extracts the ALT_USB_HOST_HCINT15_NAK field value from a register. */
60898 #define ALT_USB_HOST_HCINT15_NAK_GET(value) (((value) & 0x00000010) >> 4)
60899 /* Produces a ALT_USB_HOST_HCINT15_NAK register field value suitable for setting the register. */
60900 #define ALT_USB_HOST_HCINT15_NAK_SET(value) (((value) << 4) & 0x00000010)
60901 
60902 /*
60903  * Field : ack
60904  *
60905  * ACK Response Received/Transmitted Interrupt (ACK)
60906  *
60907  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
60908  *
60909  * in the core.This bit can be set only by the core and the application should
60910  * write 1 to clear
60911  *
60912  * it.
60913  *
60914  * Field Enumeration Values:
60915  *
60916  * Enum | Value | Description
60917  * :---------------------------------|:------|:-----------------------------------------------
60918  * ALT_USB_HOST_HCINT15_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
60919  * ALT_USB_HOST_HCINT15_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
60920  *
60921  * Field Access Macros:
60922  *
60923  */
60924 /*
60925  * Enumerated value for register field ALT_USB_HOST_HCINT15_ACK
60926  *
60927  * No ACK Response Received Transmitted Interrupt
60928  */
60929 #define ALT_USB_HOST_HCINT15_ACK_E_INACT 0x0
60930 /*
60931  * Enumerated value for register field ALT_USB_HOST_HCINT15_ACK
60932  *
60933  * ACK Response Received Transmitted Interrup
60934  */
60935 #define ALT_USB_HOST_HCINT15_ACK_E_ACT 0x1
60936 
60937 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_ACK register field. */
60938 #define ALT_USB_HOST_HCINT15_ACK_LSB 5
60939 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_ACK register field. */
60940 #define ALT_USB_HOST_HCINT15_ACK_MSB 5
60941 /* The width in bits of the ALT_USB_HOST_HCINT15_ACK register field. */
60942 #define ALT_USB_HOST_HCINT15_ACK_WIDTH 1
60943 /* The mask used to set the ALT_USB_HOST_HCINT15_ACK register field value. */
60944 #define ALT_USB_HOST_HCINT15_ACK_SET_MSK 0x00000020
60945 /* The mask used to clear the ALT_USB_HOST_HCINT15_ACK register field value. */
60946 #define ALT_USB_HOST_HCINT15_ACK_CLR_MSK 0xffffffdf
60947 /* The reset value of the ALT_USB_HOST_HCINT15_ACK register field. */
60948 #define ALT_USB_HOST_HCINT15_ACK_RESET 0x0
60949 /* Extracts the ALT_USB_HOST_HCINT15_ACK field value from a register. */
60950 #define ALT_USB_HOST_HCINT15_ACK_GET(value) (((value) & 0x00000020) >> 5)
60951 /* Produces a ALT_USB_HOST_HCINT15_ACK register field value suitable for setting the register. */
60952 #define ALT_USB_HOST_HCINT15_ACK_SET(value) (((value) << 5) & 0x00000020)
60953 
60954 /*
60955  * Field : nyet
60956  *
60957  * NYET Response Received Interrupt (NYET)
60958  *
60959  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
60960  *
60961  * in the core.This bit can be set only by the core and the application should
60962  * write 1 to clear
60963  *
60964  * it.
60965  *
60966  * Field Enumeration Values:
60967  *
60968  * Enum | Value | Description
60969  * :----------------------------------|:------|:------------------------------------
60970  * ALT_USB_HOST_HCINT15_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
60971  * ALT_USB_HOST_HCINT15_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
60972  *
60973  * Field Access Macros:
60974  *
60975  */
60976 /*
60977  * Enumerated value for register field ALT_USB_HOST_HCINT15_NYET
60978  *
60979  * No NYET Response Received Interrupt
60980  */
60981 #define ALT_USB_HOST_HCINT15_NYET_E_INACT 0x0
60982 /*
60983  * Enumerated value for register field ALT_USB_HOST_HCINT15_NYET
60984  *
60985  * NYET Response Received Interrupt
60986  */
60987 #define ALT_USB_HOST_HCINT15_NYET_E_ACT 0x1
60988 
60989 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_NYET register field. */
60990 #define ALT_USB_HOST_HCINT15_NYET_LSB 6
60991 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_NYET register field. */
60992 #define ALT_USB_HOST_HCINT15_NYET_MSB 6
60993 /* The width in bits of the ALT_USB_HOST_HCINT15_NYET register field. */
60994 #define ALT_USB_HOST_HCINT15_NYET_WIDTH 1
60995 /* The mask used to set the ALT_USB_HOST_HCINT15_NYET register field value. */
60996 #define ALT_USB_HOST_HCINT15_NYET_SET_MSK 0x00000040
60997 /* The mask used to clear the ALT_USB_HOST_HCINT15_NYET register field value. */
60998 #define ALT_USB_HOST_HCINT15_NYET_CLR_MSK 0xffffffbf
60999 /* The reset value of the ALT_USB_HOST_HCINT15_NYET register field. */
61000 #define ALT_USB_HOST_HCINT15_NYET_RESET 0x0
61001 /* Extracts the ALT_USB_HOST_HCINT15_NYET field value from a register. */
61002 #define ALT_USB_HOST_HCINT15_NYET_GET(value) (((value) & 0x00000040) >> 6)
61003 /* Produces a ALT_USB_HOST_HCINT15_NYET register field value suitable for setting the register. */
61004 #define ALT_USB_HOST_HCINT15_NYET_SET(value) (((value) << 6) & 0x00000040)
61005 
61006 /*
61007  * Field : xacterr
61008  *
61009  * Transaction Error (XactErr)
61010  *
61011  * Indicates one of the following errors occurred on the USB.
61012  *
61013  * CRC check failure
61014  *
61015  * Timeout
61016  *
61017  * Bit stuff error
61018  *
61019  * False EOP
61020  *
61021  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
61022  *
61023  * in the core.This bit can be set only by the core and the application should
61024  * write 1 to clear
61025  *
61026  * it.
61027  *
61028  * Field Enumeration Values:
61029  *
61030  * Enum | Value | Description
61031  * :-------------------------------------|:------|:---------------------
61032  * ALT_USB_HOST_HCINT15_XACTERR_E_INACT | 0x0 | No Transaction Error
61033  * ALT_USB_HOST_HCINT15_XACTERR_E_ACT | 0x1 | Transaction Error
61034  *
61035  * Field Access Macros:
61036  *
61037  */
61038 /*
61039  * Enumerated value for register field ALT_USB_HOST_HCINT15_XACTERR
61040  *
61041  * No Transaction Error
61042  */
61043 #define ALT_USB_HOST_HCINT15_XACTERR_E_INACT 0x0
61044 /*
61045  * Enumerated value for register field ALT_USB_HOST_HCINT15_XACTERR
61046  *
61047  * Transaction Error
61048  */
61049 #define ALT_USB_HOST_HCINT15_XACTERR_E_ACT 0x1
61050 
61051 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_XACTERR register field. */
61052 #define ALT_USB_HOST_HCINT15_XACTERR_LSB 7
61053 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_XACTERR register field. */
61054 #define ALT_USB_HOST_HCINT15_XACTERR_MSB 7
61055 /* The width in bits of the ALT_USB_HOST_HCINT15_XACTERR register field. */
61056 #define ALT_USB_HOST_HCINT15_XACTERR_WIDTH 1
61057 /* The mask used to set the ALT_USB_HOST_HCINT15_XACTERR register field value. */
61058 #define ALT_USB_HOST_HCINT15_XACTERR_SET_MSK 0x00000080
61059 /* The mask used to clear the ALT_USB_HOST_HCINT15_XACTERR register field value. */
61060 #define ALT_USB_HOST_HCINT15_XACTERR_CLR_MSK 0xffffff7f
61061 /* The reset value of the ALT_USB_HOST_HCINT15_XACTERR register field. */
61062 #define ALT_USB_HOST_HCINT15_XACTERR_RESET 0x0
61063 /* Extracts the ALT_USB_HOST_HCINT15_XACTERR field value from a register. */
61064 #define ALT_USB_HOST_HCINT15_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
61065 /* Produces a ALT_USB_HOST_HCINT15_XACTERR register field value suitable for setting the register. */
61066 #define ALT_USB_HOST_HCINT15_XACTERR_SET(value) (((value) << 7) & 0x00000080)
61067 
61068 /*
61069  * Field : bblerr
61070  *
61071  * Babble Error (BblErr)
61072  *
61073  * In Scatter/Gather DMA mode, the interrupt due to this bit is masked
61074  *
61075  * in the core..This bit can be set only by the core and the application should
61076  * write 1 to clear
61077  *
61078  * it.
61079  *
61080  * Field Enumeration Values:
61081  *
61082  * Enum | Value | Description
61083  * :------------------------------------|:------|:----------------
61084  * ALT_USB_HOST_HCINT15_BBLERR_E_INACT | 0x0 | No Babble Error
61085  * ALT_USB_HOST_HCINT15_BBLERR_E_ACT | 0x1 | Babble Error
61086  *
61087  * Field Access Macros:
61088  *
61089  */
61090 /*
61091  * Enumerated value for register field ALT_USB_HOST_HCINT15_BBLERR
61092  *
61093  * No Babble Error
61094  */
61095 #define ALT_USB_HOST_HCINT15_BBLERR_E_INACT 0x0
61096 /*
61097  * Enumerated value for register field ALT_USB_HOST_HCINT15_BBLERR
61098  *
61099  * Babble Error
61100  */
61101 #define ALT_USB_HOST_HCINT15_BBLERR_E_ACT 0x1
61102 
61103 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_BBLERR register field. */
61104 #define ALT_USB_HOST_HCINT15_BBLERR_LSB 8
61105 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_BBLERR register field. */
61106 #define ALT_USB_HOST_HCINT15_BBLERR_MSB 8
61107 /* The width in bits of the ALT_USB_HOST_HCINT15_BBLERR register field. */
61108 #define ALT_USB_HOST_HCINT15_BBLERR_WIDTH 1
61109 /* The mask used to set the ALT_USB_HOST_HCINT15_BBLERR register field value. */
61110 #define ALT_USB_HOST_HCINT15_BBLERR_SET_MSK 0x00000100
61111 /* The mask used to clear the ALT_USB_HOST_HCINT15_BBLERR register field value. */
61112 #define ALT_USB_HOST_HCINT15_BBLERR_CLR_MSK 0xfffffeff
61113 /* The reset value of the ALT_USB_HOST_HCINT15_BBLERR register field. */
61114 #define ALT_USB_HOST_HCINT15_BBLERR_RESET 0x0
61115 /* Extracts the ALT_USB_HOST_HCINT15_BBLERR field value from a register. */
61116 #define ALT_USB_HOST_HCINT15_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
61117 /* Produces a ALT_USB_HOST_HCINT15_BBLERR register field value suitable for setting the register. */
61118 #define ALT_USB_HOST_HCINT15_BBLERR_SET(value) (((value) << 8) & 0x00000100)
61119 
61120 /*
61121  * Field : frmovrun
61122  *
61123  * Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
61124  * bit is masked
61125  *
61126  * in the core.This bit can be set only by the core and the application should
61127  * write 1 to clear
61128  *
61129  * it.
61130  *
61131  * Field Enumeration Values:
61132  *
61133  * Enum | Value | Description
61134  * :--------------------------------------|:------|:-----------------
61135  * ALT_USB_HOST_HCINT15_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
61136  * ALT_USB_HOST_HCINT15_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
61137  *
61138  * Field Access Macros:
61139  *
61140  */
61141 /*
61142  * Enumerated value for register field ALT_USB_HOST_HCINT15_FRMOVRUN
61143  *
61144  * No Frame Overrun
61145  */
61146 #define ALT_USB_HOST_HCINT15_FRMOVRUN_E_INACT 0x0
61147 /*
61148  * Enumerated value for register field ALT_USB_HOST_HCINT15_FRMOVRUN
61149  *
61150  * Frame Overrun
61151  */
61152 #define ALT_USB_HOST_HCINT15_FRMOVRUN_E_ACT 0x1
61153 
61154 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */
61155 #define ALT_USB_HOST_HCINT15_FRMOVRUN_LSB 9
61156 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */
61157 #define ALT_USB_HOST_HCINT15_FRMOVRUN_MSB 9
61158 /* The width in bits of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */
61159 #define ALT_USB_HOST_HCINT15_FRMOVRUN_WIDTH 1
61160 /* The mask used to set the ALT_USB_HOST_HCINT15_FRMOVRUN register field value. */
61161 #define ALT_USB_HOST_HCINT15_FRMOVRUN_SET_MSK 0x00000200
61162 /* The mask used to clear the ALT_USB_HOST_HCINT15_FRMOVRUN register field value. */
61163 #define ALT_USB_HOST_HCINT15_FRMOVRUN_CLR_MSK 0xfffffdff
61164 /* The reset value of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */
61165 #define ALT_USB_HOST_HCINT15_FRMOVRUN_RESET 0x0
61166 /* Extracts the ALT_USB_HOST_HCINT15_FRMOVRUN field value from a register. */
61167 #define ALT_USB_HOST_HCINT15_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
61168 /* Produces a ALT_USB_HOST_HCINT15_FRMOVRUN register field value suitable for setting the register. */
61169 #define ALT_USB_HOST_HCINT15_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
61170 
61171 /*
61172  * Field : datatglerr
61173  *
61174  * Data Toggle Error (DataTglErr).This bit can be set only by the core and the
61175  * application should write 1 to clear
61176  *
61177  * it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
61178  *
61179  * in the core.
61180  *
61181  * Field Enumeration Values:
61182  *
61183  * Enum | Value | Description
61184  * :----------------------------------------|:------|:---------------------
61185  * ALT_USB_HOST_HCINT15_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
61186  * ALT_USB_HOST_HCINT15_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
61187  *
61188  * Field Access Macros:
61189  *
61190  */
61191 /*
61192  * Enumerated value for register field ALT_USB_HOST_HCINT15_DATATGLERR
61193  *
61194  * No Data Toggle Error
61195  */
61196 #define ALT_USB_HOST_HCINT15_DATATGLERR_E_INACT 0x0
61197 /*
61198  * Enumerated value for register field ALT_USB_HOST_HCINT15_DATATGLERR
61199  *
61200  * Data Toggle Error
61201  */
61202 #define ALT_USB_HOST_HCINT15_DATATGLERR_E_ACT 0x1
61203 
61204 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */
61205 #define ALT_USB_HOST_HCINT15_DATATGLERR_LSB 10
61206 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */
61207 #define ALT_USB_HOST_HCINT15_DATATGLERR_MSB 10
61208 /* The width in bits of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */
61209 #define ALT_USB_HOST_HCINT15_DATATGLERR_WIDTH 1
61210 /* The mask used to set the ALT_USB_HOST_HCINT15_DATATGLERR register field value. */
61211 #define ALT_USB_HOST_HCINT15_DATATGLERR_SET_MSK 0x00000400
61212 /* The mask used to clear the ALT_USB_HOST_HCINT15_DATATGLERR register field value. */
61213 #define ALT_USB_HOST_HCINT15_DATATGLERR_CLR_MSK 0xfffffbff
61214 /* The reset value of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */
61215 #define ALT_USB_HOST_HCINT15_DATATGLERR_RESET 0x0
61216 /* Extracts the ALT_USB_HOST_HCINT15_DATATGLERR field value from a register. */
61217 #define ALT_USB_HOST_HCINT15_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
61218 /* Produces a ALT_USB_HOST_HCINT15_DATATGLERR register field value suitable for setting the register. */
61219 #define ALT_USB_HOST_HCINT15_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
61220 
61221 /*
61222  * Field : bnaintr
61223  *
61224  * BNA (Buffer Not Available) Interrupt (BNAIntr)
61225  *
61226  * This bit is valid only when Scatter/Gather DMA mode is enabled.
61227  *
61228  * The core generates this interrupt when the descriptor accessed
61229  *
61230  * is not ready for the Core to process. BNA will not be generated
61231  *
61232  * for Isochronous channels.
61233  *
61234  * For non Scatter/Gather DMA mode, this bit is reserved.
61235  *
61236  * Field Enumeration Values:
61237  *
61238  * Enum | Value | Description
61239  * :-------------------------------------|:------|:-----------------
61240  * ALT_USB_HOST_HCINT15_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
61241  * ALT_USB_HOST_HCINT15_BNAINTR_E_ACT | 0x1 | BNA Interrupt
61242  *
61243  * Field Access Macros:
61244  *
61245  */
61246 /*
61247  * Enumerated value for register field ALT_USB_HOST_HCINT15_BNAINTR
61248  *
61249  * No BNA Interrupt
61250  */
61251 #define ALT_USB_HOST_HCINT15_BNAINTR_E_INACT 0x0
61252 /*
61253  * Enumerated value for register field ALT_USB_HOST_HCINT15_BNAINTR
61254  *
61255  * BNA Interrupt
61256  */
61257 #define ALT_USB_HOST_HCINT15_BNAINTR_E_ACT 0x1
61258 
61259 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_BNAINTR register field. */
61260 #define ALT_USB_HOST_HCINT15_BNAINTR_LSB 11
61261 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_BNAINTR register field. */
61262 #define ALT_USB_HOST_HCINT15_BNAINTR_MSB 11
61263 /* The width in bits of the ALT_USB_HOST_HCINT15_BNAINTR register field. */
61264 #define ALT_USB_HOST_HCINT15_BNAINTR_WIDTH 1
61265 /* The mask used to set the ALT_USB_HOST_HCINT15_BNAINTR register field value. */
61266 #define ALT_USB_HOST_HCINT15_BNAINTR_SET_MSK 0x00000800
61267 /* The mask used to clear the ALT_USB_HOST_HCINT15_BNAINTR register field value. */
61268 #define ALT_USB_HOST_HCINT15_BNAINTR_CLR_MSK 0xfffff7ff
61269 /* The reset value of the ALT_USB_HOST_HCINT15_BNAINTR register field. */
61270 #define ALT_USB_HOST_HCINT15_BNAINTR_RESET 0x0
61271 /* Extracts the ALT_USB_HOST_HCINT15_BNAINTR field value from a register. */
61272 #define ALT_USB_HOST_HCINT15_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
61273 /* Produces a ALT_USB_HOST_HCINT15_BNAINTR register field value suitable for setting the register. */
61274 #define ALT_USB_HOST_HCINT15_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
61275 
61276 /*
61277  * Field : xcs_xact_err
61278  *
61279  * Excessive Transaction Error (XCS_XACT_ERR)
61280  *
61281  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
61282  * this bit
61283  *
61284  * when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
61285  *
61286  * not be generated for Isochronous channels.
61287  *
61288  * For non Scatter/Gather DMA mode, this bit is reserved.
61289  *
61290  * Field Enumeration Values:
61291  *
61292  * Enum | Value | Description
61293  * :--------------------------------------------|:------|:-------------------------------
61294  * ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
61295  * ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
61296  *
61297  * Field Access Macros:
61298  *
61299  */
61300 /*
61301  * Enumerated value for register field ALT_USB_HOST_HCINT15_XCS_XACT_ERR
61302  *
61303  * No Excessive Transaction Error
61304  */
61305 #define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_INACT 0x0
61306 /*
61307  * Enumerated value for register field ALT_USB_HOST_HCINT15_XCS_XACT_ERR
61308  *
61309  * Excessive Transaction Error
61310  */
61311 #define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_ACVTIVE 0x1
61312 
61313 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */
61314 #define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_LSB 12
61315 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */
61316 #define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_MSB 12
61317 /* The width in bits of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */
61318 #define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_WIDTH 1
61319 /* The mask used to set the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field value. */
61320 #define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_SET_MSK 0x00001000
61321 /* The mask used to clear the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field value. */
61322 #define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_CLR_MSK 0xffffefff
61323 /* The reset value of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */
61324 #define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_RESET 0x0
61325 /* Extracts the ALT_USB_HOST_HCINT15_XCS_XACT_ERR field value from a register. */
61326 #define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
61327 /* Produces a ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field value suitable for setting the register. */
61328 #define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
61329 
61330 /*
61331  * Field : desc_lst_rollintr
61332  *
61333  * Descriptor rollover interrupt (DESC_LST_ROLLIntr)
61334  *
61335  * This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
61336  * this bit
61337  *
61338  * when the corresponding channel's descriptor list rolls over.
61339  *
61340  * For non Scatter/Gather DMA mode, this bit is reserved.
61341  *
61342  * Field Enumeration Values:
61343  *
61344  * Enum | Value | Description
61345  * :-----------------------------------------------|:------|:---------------------------------
61346  * ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
61347  * ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
61348  *
61349  * Field Access Macros:
61350  *
61351  */
61352 /*
61353  * Enumerated value for register field ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR
61354  *
61355  * No Descriptor rollover interrupt
61356  */
61357 #define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_INACT 0x0
61358 /*
61359  * Enumerated value for register field ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR
61360  *
61361  * Descriptor rollover interrupt
61362  */
61363 #define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_ACT 0x1
61364 
61365 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */
61366 #define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_LSB 13
61367 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */
61368 #define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_MSB 13
61369 /* The width in bits of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */
61370 #define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_WIDTH 1
61371 /* The mask used to set the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field value. */
61372 #define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_SET_MSK 0x00002000
61373 /* The mask used to clear the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field value. */
61374 #define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
61375 /* The reset value of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */
61376 #define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_RESET 0x0
61377 /* Extracts the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR field value from a register. */
61378 #define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
61379 /* Produces a ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field value suitable for setting the register. */
61380 #define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
61381 
61382 #ifndef __ASSEMBLY__
61383 /*
61384  * WARNING: The C register and register group struct declarations are provided for
61385  * convenience and illustrative purposes. They should, however, be used with
61386  * caution as the C language standard provides no guarantees about the alignment or
61387  * atomicity of device memory accesses. The recommended practice for writing
61388  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61389  * alt_write_word() functions.
61390  *
61391  * The struct declaration for register ALT_USB_HOST_HCINT15.
61392  */
61393 struct ALT_USB_HOST_HCINT15_s
61394 {
61395  uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT15_XFERCOMPL */
61396  uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT15_CHHLTD */
61397  uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT15_AHBERR */
61398  uint32_t stall : 1; /* ALT_USB_HOST_HCINT15_STALL */
61399  uint32_t nak : 1; /* ALT_USB_HOST_HCINT15_NAK */
61400  uint32_t ack : 1; /* ALT_USB_HOST_HCINT15_ACK */
61401  uint32_t nyet : 1; /* ALT_USB_HOST_HCINT15_NYET */
61402  uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT15_XACTERR */
61403  uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT15_BBLERR */
61404  uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT15_FRMOVRUN */
61405  uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT15_DATATGLERR */
61406  uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT15_BNAINTR */
61407  uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT15_XCS_XACT_ERR */
61408  uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR */
61409  uint32_t : 18; /* *UNDEFINED* */
61410 };
61411 
61412 /* The typedef declaration for register ALT_USB_HOST_HCINT15. */
61413 typedef volatile struct ALT_USB_HOST_HCINT15_s ALT_USB_HOST_HCINT15_t;
61414 #endif /* __ASSEMBLY__ */
61415 
61416 /* The reset value of the ALT_USB_HOST_HCINT15 register. */
61417 #define ALT_USB_HOST_HCINT15_RESET 0x00000000
61418 /* The byte offset of the ALT_USB_HOST_HCINT15 register from the beginning of the component. */
61419 #define ALT_USB_HOST_HCINT15_OFST 0x2e8
61420 /* The address of the ALT_USB_HOST_HCINT15 register. */
61421 #define ALT_USB_HOST_HCINT15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT15_OFST))
61422 
61423 /*
61424  * Register : hcintmsk15
61425  *
61426  * Host Channel 15 Interrupt Mask Register
61427  *
61428  * Register Layout
61429  *
61430  * Bits | Access | Reset | Description
61431  * :--------|:-------|:------|:--------------------------------------------
61432  * [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK
61433  * [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_CHHLTDMSK
61434  * [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_AHBERRMSK
61435  * [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_STALLMSK
61436  * [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_NAKMSK
61437  * [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_ACKMSK
61438  * [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_NYETMSK
61439  * [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_XACTERRMSK
61440  * [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_BBLERRMSK
61441  * [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK
61442  * [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK
61443  * [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_BNAINTRMSK
61444  * [12] | ??? | 0x0 | *UNDEFINED*
61445  * [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK
61446  * [31:14] | ??? | 0x0 | *UNDEFINED*
61447  *
61448  */
61449 /*
61450  * Field : xfercomplmsk
61451  *
61452  * Transfer Completed Mask (XferComplMsk)
61453  *
61454  * Field Enumeration Values:
61455  *
61456  * Enum | Value | Description
61457  * :---------------------------------------------|:------|:------------
61458  * ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_MSK | 0x0 | Mask
61459  * ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
61460  *
61461  * Field Access Macros:
61462  *
61463  */
61464 /*
61465  * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK
61466  *
61467  * Mask
61468  */
61469 #define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_MSK 0x0
61470 /*
61471  * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK
61472  *
61473  * No mask
61474  */
61475 #define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_NOMSK 0x1
61476 
61477 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */
61478 #define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_LSB 0
61479 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */
61480 #define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_MSB 0
61481 /* The width in bits of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */
61482 #define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_WIDTH 1
61483 /* The mask used to set the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field value. */
61484 #define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_SET_MSK 0x00000001
61485 /* The mask used to clear the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field value. */
61486 #define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_CLR_MSK 0xfffffffe
61487 /* The reset value of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */
61488 #define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_RESET 0x0
61489 /* Extracts the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK field value from a register. */
61490 #define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
61491 /* Produces a ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field value suitable for setting the register. */
61492 #define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
61493 
61494 /*
61495  * Field : chhltdmsk
61496  *
61497  * Channel Halted Mask (ChHltdMsk)
61498  *
61499  * Field Enumeration Values:
61500  *
61501  * Enum | Value | Description
61502  * :------------------------------------------|:------|:------------
61503  * ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_MSK | 0x0 | Mask
61504  * ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_NOMSK | 0x1 | No mask
61505  *
61506  * Field Access Macros:
61507  *
61508  */
61509 /*
61510  * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_CHHLTDMSK
61511  *
61512  * Mask
61513  */
61514 #define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_MSK 0x0
61515 /*
61516  * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_CHHLTDMSK
61517  *
61518  * No mask
61519  */
61520 #define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_NOMSK 0x1
61521 
61522 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */
61523 #define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_LSB 1
61524 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */
61525 #define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_MSB 1
61526 /* The width in bits of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */
61527 #define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_WIDTH 1
61528 /* The mask used to set the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field value. */
61529 #define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_SET_MSK 0x00000002
61530 /* The mask used to clear the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field value. */
61531 #define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_CLR_MSK 0xfffffffd
61532 /* The reset value of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */
61533 #define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_RESET 0x0
61534 /* Extracts the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK field value from a register. */
61535 #define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
61536 /* Produces a ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field value suitable for setting the register. */
61537 #define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
61538 
61539 /*
61540  * Field : ahberrmsk
61541  *
61542  * AHB Error Mask (AHBErrMsk)
61543  *
61544  * In scatter/gather DMA mode for host,
61545  *
61546  * interrupts will not be generated due to the corresponding bits set in
61547  *
61548  * HCINTn.
61549  *
61550  * Field Enumeration Values:
61551  *
61552  * Enum | Value | Description
61553  * :------------------------------------------|:------|:------------
61554  * ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_MSK | 0x0 | Mask
61555  * ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_NOMSK | 0x1 | No mask
61556  *
61557  * Field Access Macros:
61558  *
61559  */
61560 /*
61561  * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_AHBERRMSK
61562  *
61563  * Mask
61564  */
61565 #define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_MSK 0x0
61566 /*
61567  * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_AHBERRMSK
61568  *
61569  * No mask
61570  */
61571 #define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_NOMSK 0x1
61572 
61573 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */
61574 #define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_LSB 2
61575 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */
61576 #define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_MSB 2
61577 /* The width in bits of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */
61578 #define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_WIDTH 1
61579 /* The mask used to set the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field value. */
61580 #define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_SET_MSK 0x00000004
61581 /* The mask used to clear the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field value. */
61582 #define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_CLR_MSK 0xfffffffb
61583 /* The reset value of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */
61584 #define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_RESET 0x0
61585 /* Extracts the ALT_USB_HOST_HCINTMSK15_AHBERRMSK field value from a register. */
61586 #define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
61587 /* Produces a ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field value suitable for setting the register. */
61588 #define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
61589 
61590 /*
61591  * Field : stallmsk
61592  *
61593  * STALL Response Received Interrupt Mask (StallMsk)
61594  *
61595  * In scatter/gather DMA mode for host,
61596  *
61597  * interrupts will not be generated due to the corresponding bits set in
61598  *
61599  * HCINTn.
61600  *
61601  * Field Access Macros:
61602  *
61603  */
61604 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_STALLMSK register field. */
61605 #define ALT_USB_HOST_HCINTMSK15_STALLMSK_LSB 3
61606 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_STALLMSK register field. */
61607 #define ALT_USB_HOST_HCINTMSK15_STALLMSK_MSB 3
61608 /* The width in bits of the ALT_USB_HOST_HCINTMSK15_STALLMSK register field. */
61609 #define ALT_USB_HOST_HCINTMSK15_STALLMSK_WIDTH 1
61610 /* The mask used to set the ALT_USB_HOST_HCINTMSK15_STALLMSK register field value. */
61611 #define ALT_USB_HOST_HCINTMSK15_STALLMSK_SET_MSK 0x00000008
61612 /* The mask used to clear the ALT_USB_HOST_HCINTMSK15_STALLMSK register field value. */
61613 #define ALT_USB_HOST_HCINTMSK15_STALLMSK_CLR_MSK 0xfffffff7
61614 /* The reset value of the ALT_USB_HOST_HCINTMSK15_STALLMSK register field. */
61615 #define ALT_USB_HOST_HCINTMSK15_STALLMSK_RESET 0x0
61616 /* Extracts the ALT_USB_HOST_HCINTMSK15_STALLMSK field value from a register. */
61617 #define ALT_USB_HOST_HCINTMSK15_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
61618 /* Produces a ALT_USB_HOST_HCINTMSK15_STALLMSK register field value suitable for setting the register. */
61619 #define ALT_USB_HOST_HCINTMSK15_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
61620 
61621 /*
61622  * Field : nakmsk
61623  *
61624  * NAK Response Received Interrupt Mask (NakMsk)
61625  *
61626  * In scatter/gather DMA mode for host,
61627  *
61628  * interrupts will not be generated due to the corresponding bits set in
61629  *
61630  * HCINTn.
61631  *
61632  * Field Access Macros:
61633  *
61634  */
61635 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_NAKMSK register field. */
61636 #define ALT_USB_HOST_HCINTMSK15_NAKMSK_LSB 4
61637 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_NAKMSK register field. */
61638 #define ALT_USB_HOST_HCINTMSK15_NAKMSK_MSB 4
61639 /* The width in bits of the ALT_USB_HOST_HCINTMSK15_NAKMSK register field. */
61640 #define ALT_USB_HOST_HCINTMSK15_NAKMSK_WIDTH 1
61641 /* The mask used to set the ALT_USB_HOST_HCINTMSK15_NAKMSK register field value. */
61642 #define ALT_USB_HOST_HCINTMSK15_NAKMSK_SET_MSK 0x00000010
61643 /* The mask used to clear the ALT_USB_HOST_HCINTMSK15_NAKMSK register field value. */
61644 #define ALT_USB_HOST_HCINTMSK15_NAKMSK_CLR_MSK 0xffffffef
61645 /* The reset value of the ALT_USB_HOST_HCINTMSK15_NAKMSK register field. */
61646 #define ALT_USB_HOST_HCINTMSK15_NAKMSK_RESET 0x0
61647 /* Extracts the ALT_USB_HOST_HCINTMSK15_NAKMSK field value from a register. */
61648 #define ALT_USB_HOST_HCINTMSK15_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
61649 /* Produces a ALT_USB_HOST_HCINTMSK15_NAKMSK register field value suitable for setting the register. */
61650 #define ALT_USB_HOST_HCINTMSK15_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
61651 
61652 /*
61653  * Field : ackmsk
61654  *
61655  * ACK Response Received/Transmitted Interrupt Mask (AckMsk)
61656  *
61657  * In scatter/gather DMA mode for host,
61658  *
61659  * interrupts will not be generated due to the corresponding bits set in
61660  *
61661  * HCINTn.
61662  *
61663  * Field Access Macros:
61664  *
61665  */
61666 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_ACKMSK register field. */
61667 #define ALT_USB_HOST_HCINTMSK15_ACKMSK_LSB 5
61668 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_ACKMSK register field. */
61669 #define ALT_USB_HOST_HCINTMSK15_ACKMSK_MSB 5
61670 /* The width in bits of the ALT_USB_HOST_HCINTMSK15_ACKMSK register field. */
61671 #define ALT_USB_HOST_HCINTMSK15_ACKMSK_WIDTH 1
61672 /* The mask used to set the ALT_USB_HOST_HCINTMSK15_ACKMSK register field value. */
61673 #define ALT_USB_HOST_HCINTMSK15_ACKMSK_SET_MSK 0x00000020
61674 /* The mask used to clear the ALT_USB_HOST_HCINTMSK15_ACKMSK register field value. */
61675 #define ALT_USB_HOST_HCINTMSK15_ACKMSK_CLR_MSK 0xffffffdf
61676 /* The reset value of the ALT_USB_HOST_HCINTMSK15_ACKMSK register field. */
61677 #define ALT_USB_HOST_HCINTMSK15_ACKMSK_RESET 0x0
61678 /* Extracts the ALT_USB_HOST_HCINTMSK15_ACKMSK field value from a register. */
61679 #define ALT_USB_HOST_HCINTMSK15_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
61680 /* Produces a ALT_USB_HOST_HCINTMSK15_ACKMSK register field value suitable for setting the register. */
61681 #define ALT_USB_HOST_HCINTMSK15_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
61682 
61683 /*
61684  * Field : nyetmsk
61685  *
61686  * NYET Response Received Interrupt Mask (NyetMsk)
61687  *
61688  * In scatter/gather DMA mode for host,
61689  *
61690  * interrupts will not be generated due to the corresponding bits set in
61691  *
61692  * HCINTn.
61693  *
61694  * Field Access Macros:
61695  *
61696  */
61697 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_NYETMSK register field. */
61698 #define ALT_USB_HOST_HCINTMSK15_NYETMSK_LSB 6
61699 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_NYETMSK register field. */
61700 #define ALT_USB_HOST_HCINTMSK15_NYETMSK_MSB 6
61701 /* The width in bits of the ALT_USB_HOST_HCINTMSK15_NYETMSK register field. */
61702 #define ALT_USB_HOST_HCINTMSK15_NYETMSK_WIDTH 1
61703 /* The mask used to set the ALT_USB_HOST_HCINTMSK15_NYETMSK register field value. */
61704 #define ALT_USB_HOST_HCINTMSK15_NYETMSK_SET_MSK 0x00000040
61705 /* The mask used to clear the ALT_USB_HOST_HCINTMSK15_NYETMSK register field value. */
61706 #define ALT_USB_HOST_HCINTMSK15_NYETMSK_CLR_MSK 0xffffffbf
61707 /* The reset value of the ALT_USB_HOST_HCINTMSK15_NYETMSK register field. */
61708 #define ALT_USB_HOST_HCINTMSK15_NYETMSK_RESET 0x0
61709 /* Extracts the ALT_USB_HOST_HCINTMSK15_NYETMSK field value from a register. */
61710 #define ALT_USB_HOST_HCINTMSK15_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
61711 /* Produces a ALT_USB_HOST_HCINTMSK15_NYETMSK register field value suitable for setting the register. */
61712 #define ALT_USB_HOST_HCINTMSK15_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
61713 
61714 /*
61715  * Field : xacterrmsk
61716  *
61717  * Transaction Error Mask (XactErrMsk)
61718  *
61719  * In scatter/gather DMA mode for host,
61720  *
61721  * interrupts will not be generated due to the corresponding bits set in
61722  *
61723  * HCINTn.
61724  *
61725  * Field Access Macros:
61726  *
61727  */
61728 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field. */
61729 #define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_LSB 7
61730 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field. */
61731 #define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_MSB 7
61732 /* The width in bits of the ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field. */
61733 #define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_WIDTH 1
61734 /* The mask used to set the ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field value. */
61735 #define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_SET_MSK 0x00000080
61736 /* The mask used to clear the ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field value. */
61737 #define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_CLR_MSK 0xffffff7f
61738 /* The reset value of the ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field. */
61739 #define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_RESET 0x0
61740 /* Extracts the ALT_USB_HOST_HCINTMSK15_XACTERRMSK field value from a register. */
61741 #define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
61742 /* Produces a ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field value suitable for setting the register. */
61743 #define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
61744 
61745 /*
61746  * Field : bblerrmsk
61747  *
61748  * Babble Error Mask (BblErrMsk)
61749  *
61750  * In scatter/gather DMA mode for host,
61751  *
61752  * interrupts will not be generated due to the corresponding bits set in
61753  *
61754  * HCINTn.
61755  *
61756  * Field Access Macros:
61757  *
61758  */
61759 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field. */
61760 #define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_LSB 8
61761 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field. */
61762 #define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_MSB 8
61763 /* The width in bits of the ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field. */
61764 #define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_WIDTH 1
61765 /* The mask used to set the ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field value. */
61766 #define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_SET_MSK 0x00000100
61767 /* The mask used to clear the ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field value. */
61768 #define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_CLR_MSK 0xfffffeff
61769 /* The reset value of the ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field. */
61770 #define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_RESET 0x0
61771 /* Extracts the ALT_USB_HOST_HCINTMSK15_BBLERRMSK field value from a register. */
61772 #define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
61773 /* Produces a ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field value suitable for setting the register. */
61774 #define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
61775 
61776 /*
61777  * Field : frmovrunmsk
61778  *
61779  * Frame Overrun Mask (FrmOvrunMsk)
61780  *
61781  * In scatter/gather DMA mode for host,
61782  *
61783  * interrupts will not be generated due to the corresponding bits set in
61784  *
61785  * HCINTn.
61786  *
61787  * Field Access Macros:
61788  *
61789  */
61790 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field. */
61791 #define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_LSB 9
61792 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field. */
61793 #define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_MSB 9
61794 /* The width in bits of the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field. */
61795 #define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_WIDTH 1
61796 /* The mask used to set the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field value. */
61797 #define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_SET_MSK 0x00000200
61798 /* The mask used to clear the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field value. */
61799 #define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_CLR_MSK 0xfffffdff
61800 /* The reset value of the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field. */
61801 #define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_RESET 0x0
61802 /* Extracts the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK field value from a register. */
61803 #define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
61804 /* Produces a ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field value suitable for setting the register. */
61805 #define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
61806 
61807 /*
61808  * Field : datatglerrmsk
61809  *
61810  * Data Toggle Error Mask (DataTglErrMsk)
61811  *
61812  * In scatter/gather DMA mode for host,
61813  *
61814  * interrupts will not be generated due to the corresponding bits set in
61815  *
61816  * HCINTn.
61817  *
61818  * Field Access Macros:
61819  *
61820  */
61821 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field. */
61822 #define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_LSB 10
61823 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field. */
61824 #define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_MSB 10
61825 /* The width in bits of the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field. */
61826 #define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_WIDTH 1
61827 /* The mask used to set the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field value. */
61828 #define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_SET_MSK 0x00000400
61829 /* The mask used to clear the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field value. */
61830 #define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_CLR_MSK 0xfffffbff
61831 /* The reset value of the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field. */
61832 #define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_RESET 0x0
61833 /* Extracts the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK field value from a register. */
61834 #define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
61835 /* Produces a ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field value suitable for setting the register. */
61836 #define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
61837 
61838 /*
61839  * Field : bnaintrmsk
61840  *
61841  * BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
61842  *
61843  * This bit is valid only when Scatter/Gather DMA mode is enabled.
61844  *
61845  * Field Enumeration Values:
61846  *
61847  * Enum | Value | Description
61848  * :-------------------------------------------|:------|:------------
61849  * ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_MSK | 0x0 | Mask
61850  * ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_NOMSK | 0x1 | No mask
61851  *
61852  * Field Access Macros:
61853  *
61854  */
61855 /*
61856  * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_BNAINTRMSK
61857  *
61858  * Mask
61859  */
61860 #define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_MSK 0x0
61861 /*
61862  * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_BNAINTRMSK
61863  *
61864  * No mask
61865  */
61866 #define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_NOMSK 0x1
61867 
61868 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */
61869 #define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_LSB 11
61870 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */
61871 #define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_MSB 11
61872 /* The width in bits of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */
61873 #define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_WIDTH 1
61874 /* The mask used to set the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field value. */
61875 #define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_SET_MSK 0x00000800
61876 /* The mask used to clear the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field value. */
61877 #define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_CLR_MSK 0xfffff7ff
61878 /* The reset value of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */
61879 #define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_RESET 0x0
61880 /* Extracts the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK field value from a register. */
61881 #define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
61882 /* Produces a ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field value suitable for setting the register. */
61883 #define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
61884 
61885 /*
61886  * Field : frm_lst_rollintrmsk
61887  *
61888  * Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
61889  *
61890  * This bit is valid only when Scatter/Gather DMA mode is enabled.
61891  *
61892  * Field Enumeration Values:
61893  *
61894  * Enum | Value | Description
61895  * :----------------------------------------------------|:------|:------------
61896  * ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
61897  * ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
61898  *
61899  * Field Access Macros:
61900  *
61901  */
61902 /*
61903  * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK
61904  *
61905  * Mask
61906  */
61907 #define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_MSK 0x0
61908 /*
61909  * Enumerated value for register field ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK
61910  *
61911  * No mask
61912  */
61913 #define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
61914 
61915 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */
61916 #define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_LSB 13
61917 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */
61918 #define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_MSB 13
61919 /* The width in bits of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */
61920 #define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_WIDTH 1
61921 /* The mask used to set the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field value. */
61922 #define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
61923 /* The mask used to clear the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field value. */
61924 #define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
61925 /* The reset value of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */
61926 #define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_RESET 0x0
61927 /* Extracts the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK field value from a register. */
61928 #define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
61929 /* Produces a ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
61930 #define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
61931 
61932 #ifndef __ASSEMBLY__
61933 /*
61934  * WARNING: The C register and register group struct declarations are provided for
61935  * convenience and illustrative purposes. They should, however, be used with
61936  * caution as the C language standard provides no guarantees about the alignment or
61937  * atomicity of device memory accesses. The recommended practice for writing
61938  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61939  * alt_write_word() functions.
61940  *
61941  * The struct declaration for register ALT_USB_HOST_HCINTMSK15.
61942  */
61943 struct ALT_USB_HOST_HCINTMSK15_s
61944 {
61945  uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK */
61946  uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK15_CHHLTDMSK */
61947  uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK15_AHBERRMSK */
61948  uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK15_STALLMSK */
61949  uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK15_NAKMSK */
61950  uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK15_ACKMSK */
61951  uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK15_NYETMSK */
61952  uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK15_XACTERRMSK */
61953  uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK15_BBLERRMSK */
61954  uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK */
61955  uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK */
61956  uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK15_BNAINTRMSK */
61957  uint32_t : 1; /* *UNDEFINED* */
61958  uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK */
61959  uint32_t : 18; /* *UNDEFINED* */
61960 };
61961 
61962 /* The typedef declaration for register ALT_USB_HOST_HCINTMSK15. */
61963 typedef volatile struct ALT_USB_HOST_HCINTMSK15_s ALT_USB_HOST_HCINTMSK15_t;
61964 #endif /* __ASSEMBLY__ */
61965 
61966 /* The reset value of the ALT_USB_HOST_HCINTMSK15 register. */
61967 #define ALT_USB_HOST_HCINTMSK15_RESET 0x00000000
61968 /* The byte offset of the ALT_USB_HOST_HCINTMSK15 register from the beginning of the component. */
61969 #define ALT_USB_HOST_HCINTMSK15_OFST 0x2ec
61970 /* The address of the ALT_USB_HOST_HCINTMSK15 register. */
61971 #define ALT_USB_HOST_HCINTMSK15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK15_OFST))
61972 
61973 /*
61974  * Register : hctsiz15
61975  *
61976  * Host Channel 15 Transfer Size Register
61977  *
61978  * Register Layout
61979  *
61980  * Bits | Access | Reset | Description
61981  * :--------|:-------|:------|:-------------------------------
61982  * [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ15_XFERSIZE
61983  * [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ15_PKTCNT
61984  * [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ15_PID
61985  * [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ15_DOPNG
61986  *
61987  */
61988 /*
61989  * Field : xfersize
61990  *
61991  * Transfer Size (XferSize)
61992  *
61993  * For an OUT, this field is the number of data bytes the host sends
61994  *
61995  * during the transfer.
61996  *
61997  * For an IN, this field is the buffer size that the application has
61998  *
61999  * Reserved For the transfer. The application is expected to
62000  *
62001  * program this field as an integer multiple of the maximum packet
62002  *
62003  * size For IN transactions (periodic and non-periodic).
62004  *
62005  * The width of this counter is specified as Width of Transfer Size
62006  *
62007  * Counters
62008  *
62009  * Field Access Macros:
62010  *
62011  */
62012 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */
62013 #define ALT_USB_HOST_HCTSIZ15_XFERSIZE_LSB 0
62014 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */
62015 #define ALT_USB_HOST_HCTSIZ15_XFERSIZE_MSB 18
62016 /* The width in bits of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */
62017 #define ALT_USB_HOST_HCTSIZ15_XFERSIZE_WIDTH 19
62018 /* The mask used to set the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field value. */
62019 #define ALT_USB_HOST_HCTSIZ15_XFERSIZE_SET_MSK 0x0007ffff
62020 /* The mask used to clear the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field value. */
62021 #define ALT_USB_HOST_HCTSIZ15_XFERSIZE_CLR_MSK 0xfff80000
62022 /* The reset value of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */
62023 #define ALT_USB_HOST_HCTSIZ15_XFERSIZE_RESET 0x0
62024 /* Extracts the ALT_USB_HOST_HCTSIZ15_XFERSIZE field value from a register. */
62025 #define ALT_USB_HOST_HCTSIZ15_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
62026 /* Produces a ALT_USB_HOST_HCTSIZ15_XFERSIZE register field value suitable for setting the register. */
62027 #define ALT_USB_HOST_HCTSIZ15_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
62028 
62029 /*
62030  * Field : pktcnt
62031  *
62032  * Packet Count (PktCnt)
62033  *
62034  * This field is programmed by the application with the expected
62035  *
62036  * number of packets to be transmitted (OUT) or received (IN).
62037  *
62038  * The host decrements this count on every successful
62039  *
62040  * transmission or reception of an OUT/IN packet. Once this count
62041  *
62042  * reaches zero, the application is interrupted to indicate normal
62043  *
62044  * completion.
62045  *
62046  * The width of this counter is specified as Width of Packet
62047  *
62048  * Counters
62049  *
62050  * Field Access Macros:
62051  *
62052  */
62053 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */
62054 #define ALT_USB_HOST_HCTSIZ15_PKTCNT_LSB 19
62055 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */
62056 #define ALT_USB_HOST_HCTSIZ15_PKTCNT_MSB 28
62057 /* The width in bits of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */
62058 #define ALT_USB_HOST_HCTSIZ15_PKTCNT_WIDTH 10
62059 /* The mask used to set the ALT_USB_HOST_HCTSIZ15_PKTCNT register field value. */
62060 #define ALT_USB_HOST_HCTSIZ15_PKTCNT_SET_MSK 0x1ff80000
62061 /* The mask used to clear the ALT_USB_HOST_HCTSIZ15_PKTCNT register field value. */
62062 #define ALT_USB_HOST_HCTSIZ15_PKTCNT_CLR_MSK 0xe007ffff
62063 /* The reset value of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */
62064 #define ALT_USB_HOST_HCTSIZ15_PKTCNT_RESET 0x0
62065 /* Extracts the ALT_USB_HOST_HCTSIZ15_PKTCNT field value from a register. */
62066 #define ALT_USB_HOST_HCTSIZ15_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
62067 /* Produces a ALT_USB_HOST_HCTSIZ15_PKTCNT register field value suitable for setting the register. */
62068 #define ALT_USB_HOST_HCTSIZ15_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
62069 
62070 /*
62071  * Field : pid
62072  *
62073  * PID (Pid)
62074  *
62075  * The application programs this field with the type of PID to use For
62076  *
62077  * the initial transaction. The host maintains this field For the rest of
62078  *
62079  * the transfer.
62080  *
62081  * 2'b00: DATA0
62082  *
62083  * 2'b01: DATA2
62084  *
62085  * 2'b10: DATA1
62086  *
62087  * 2'b11: MDATA (non-control)/SETUP (control)
62088  *
62089  * Field Enumeration Values:
62090  *
62091  * Enum | Value | Description
62092  * :----------------------------------|:------|:------------------------------------
62093  * ALT_USB_HOST_HCTSIZ15_PID_E_DATA0 | 0x0 | DATA0
62094  * ALT_USB_HOST_HCTSIZ15_PID_E_DATA2 | 0x1 | DATA2
62095  * ALT_USB_HOST_HCTSIZ15_PID_E_DATA1 | 0x2 | DATA1
62096  * ALT_USB_HOST_HCTSIZ15_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
62097  *
62098  * Field Access Macros:
62099  *
62100  */
62101 /*
62102  * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID
62103  *
62104  * DATA0
62105  */
62106 #define ALT_USB_HOST_HCTSIZ15_PID_E_DATA0 0x0
62107 /*
62108  * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID
62109  *
62110  * DATA2
62111  */
62112 #define ALT_USB_HOST_HCTSIZ15_PID_E_DATA2 0x1
62113 /*
62114  * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID
62115  *
62116  * DATA1
62117  */
62118 #define ALT_USB_HOST_HCTSIZ15_PID_E_DATA1 0x2
62119 /*
62120  * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID
62121  *
62122  * MDATA (non-control)/SETUP (control)
62123  */
62124 #define ALT_USB_HOST_HCTSIZ15_PID_E_MDATA 0x3
62125 
62126 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_PID register field. */
62127 #define ALT_USB_HOST_HCTSIZ15_PID_LSB 29
62128 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_PID register field. */
62129 #define ALT_USB_HOST_HCTSIZ15_PID_MSB 30
62130 /* The width in bits of the ALT_USB_HOST_HCTSIZ15_PID register field. */
62131 #define ALT_USB_HOST_HCTSIZ15_PID_WIDTH 2
62132 /* The mask used to set the ALT_USB_HOST_HCTSIZ15_PID register field value. */
62133 #define ALT_USB_HOST_HCTSIZ15_PID_SET_MSK 0x60000000
62134 /* The mask used to clear the ALT_USB_HOST_HCTSIZ15_PID register field value. */
62135 #define ALT_USB_HOST_HCTSIZ15_PID_CLR_MSK 0x9fffffff
62136 /* The reset value of the ALT_USB_HOST_HCTSIZ15_PID register field. */
62137 #define ALT_USB_HOST_HCTSIZ15_PID_RESET 0x0
62138 /* Extracts the ALT_USB_HOST_HCTSIZ15_PID field value from a register. */
62139 #define ALT_USB_HOST_HCTSIZ15_PID_GET(value) (((value) & 0x60000000) >> 29)
62140 /* Produces a ALT_USB_HOST_HCTSIZ15_PID register field value suitable for setting the register. */
62141 #define ALT_USB_HOST_HCTSIZ15_PID_SET(value) (((value) << 29) & 0x60000000)
62142 
62143 /*
62144  * Field : dopng
62145  *
62146  * Do Ping (DoPng)
62147  *
62148  * This bit is used only For OUT transfers.
62149  *
62150  * Setting this field to 1 directs the host to do PING protocol.
62151  *
62152  * Note: Do not Set this bit For IN transfers. If this bit is Set For
62153  *
62154  * for IN transfers it disables the channel.
62155  *
62156  * Field Enumeration Values:
62157  *
62158  * Enum | Value | Description
62159  * :-------------------------------------|:------|:-----------------
62160  * ALT_USB_HOST_HCTSIZ15_DOPNG_E_NOPING | 0x0 | No ping protocol
62161  * ALT_USB_HOST_HCTSIZ15_DOPNG_E_PING | 0x1 | Ping protocol
62162  *
62163  * Field Access Macros:
62164  *
62165  */
62166 /*
62167  * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_DOPNG
62168  *
62169  * No ping protocol
62170  */
62171 #define ALT_USB_HOST_HCTSIZ15_DOPNG_E_NOPING 0x0
62172 /*
62173  * Enumerated value for register field ALT_USB_HOST_HCTSIZ15_DOPNG
62174  *
62175  * Ping protocol
62176  */
62177 #define ALT_USB_HOST_HCTSIZ15_DOPNG_E_PING 0x1
62178 
62179 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */
62180 #define ALT_USB_HOST_HCTSIZ15_DOPNG_LSB 31
62181 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */
62182 #define ALT_USB_HOST_HCTSIZ15_DOPNG_MSB 31
62183 /* The width in bits of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */
62184 #define ALT_USB_HOST_HCTSIZ15_DOPNG_WIDTH 1
62185 /* The mask used to set the ALT_USB_HOST_HCTSIZ15_DOPNG register field value. */
62186 #define ALT_USB_HOST_HCTSIZ15_DOPNG_SET_MSK 0x80000000
62187 /* The mask used to clear the ALT_USB_HOST_HCTSIZ15_DOPNG register field value. */
62188 #define ALT_USB_HOST_HCTSIZ15_DOPNG_CLR_MSK 0x7fffffff
62189 /* The reset value of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */
62190 #define ALT_USB_HOST_HCTSIZ15_DOPNG_RESET 0x0
62191 /* Extracts the ALT_USB_HOST_HCTSIZ15_DOPNG field value from a register. */
62192 #define ALT_USB_HOST_HCTSIZ15_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
62193 /* Produces a ALT_USB_HOST_HCTSIZ15_DOPNG register field value suitable for setting the register. */
62194 #define ALT_USB_HOST_HCTSIZ15_DOPNG_SET(value) (((value) << 31) & 0x80000000)
62195 
62196 #ifndef __ASSEMBLY__
62197 /*
62198  * WARNING: The C register and register group struct declarations are provided for
62199  * convenience and illustrative purposes. They should, however, be used with
62200  * caution as the C language standard provides no guarantees about the alignment or
62201  * atomicity of device memory accesses. The recommended practice for writing
62202  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62203  * alt_write_word() functions.
62204  *
62205  * The struct declaration for register ALT_USB_HOST_HCTSIZ15.
62206  */
62207 struct ALT_USB_HOST_HCTSIZ15_s
62208 {
62209  uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ15_XFERSIZE */
62210  uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ15_PKTCNT */
62211  uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ15_PID */
62212  uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ15_DOPNG */
62213 };
62214 
62215 /* The typedef declaration for register ALT_USB_HOST_HCTSIZ15. */
62216 typedef volatile struct ALT_USB_HOST_HCTSIZ15_s ALT_USB_HOST_HCTSIZ15_t;
62217 #endif /* __ASSEMBLY__ */
62218 
62219 /* The reset value of the ALT_USB_HOST_HCTSIZ15 register. */
62220 #define ALT_USB_HOST_HCTSIZ15_RESET 0x00000000
62221 /* The byte offset of the ALT_USB_HOST_HCTSIZ15 register from the beginning of the component. */
62222 #define ALT_USB_HOST_HCTSIZ15_OFST 0x2f0
62223 /* The address of the ALT_USB_HOST_HCTSIZ15 register. */
62224 #define ALT_USB_HOST_HCTSIZ15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ15_OFST))
62225 
62226 /*
62227  * Register : hcdma15
62228  *
62229  * Host Channel 15 DMA Address Register
62230  *
62231  * Register Layout
62232  *
62233  * Bits | Access | Reset | Description
62234  * :-------|:-------|:------|:-----------------------------
62235  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA15_HCDMA15
62236  *
62237  */
62238 /*
62239  * Field : hcdma15
62240  *
62241  * Buffer DMA Mode:
62242  *
62243  * [31:0] DMA Address (DMAAddr)
62244  *
62245  * This field holds the start address in the external memory from which the data
62246  * for
62247  *
62248  * the endpoint must be fetched or to which it must be stored. This register is
62249  *
62250  * incremented on every AHB transaction.
62251  *
62252  * Scatter-Gather DMA (DescDMA) Mode:
62253  *
62254  * [31:9] (Non Isoc) Non-Isochronous:
62255  *
62256  * [31:N] (Isoc) Isochronous:
62257  *
62258  * This field holds the start address of the 512 bytes
62259  *
62260  * page. The first descriptor in the list should be located
62261  *
62262  * in this address. The first descriptor may be or may
62263  *
62264  * not be ready. The core starts processing the list from
62265  *
62266  * the CTD value.
62267  *
62268  * This field holds the address of the 2*(nTD+1) bytes of
62269  *
62270  * locations in which the isochronous descriptors are
62271  *
62272  * present where N is based on nTD as per Table below
62273  *
62274  * [31:N] Base Address
62275  *
62276  * [N-1:3] Offset
62277  *
62278  * [2:0] 000
62279  *
62280  * HS ISOC
62281  *
62282  * nTD N
62283  *
62284  * 7 6
62285  *
62286  * 15 7
62287  *
62288  * 31 8
62289  *
62290  * 63 9
62291  *
62292  * 127 10
62293  *
62294  * 255 11
62295  *
62296  * FS ISOC
62297  *
62298  * nTD N
62299  *
62300  * 1 4
62301  *
62302  * 3 5
62303  *
62304  * 7 6
62305  *
62306  * 15 7
62307  *
62308  * 31 8
62309  *
62310  * 63 9
62311  *
62312  * [N-1:3] (Isoc):
62313  *
62314  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
62315  *
62316  * Non Isochronous:
62317  *
62318  * This value is in terms of number of descriptors. The values can be from 0 to 63.
62319  *
62320  * 0 - 1 descriptor.
62321  *
62322  * 63 - 64 descriptors.
62323  *
62324  * This field indicates the current descriptor processed in the list. This field is
62325  * updated
62326  *
62327  * both by application and the core. For example, if the application enables the
62328  *
62329  * channel after programming CTD=5, then the core will start processing the 6th
62330  *
62331  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
62332  *
62333  * to DMAAddr.
62334  *
62335  * Isochronous:
62336  *
62337  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
62338  * set
62339  *
62340  * to zero by application.Scatter-Gather DMA (DescDMA) Mode:
62341  *
62342  * [31:9] (Non Isoc) Non-Isochronous:
62343  *
62344  * [31:N] (Isoc) Isochronous:
62345  *
62346  * This field holds the start address of the 512 bytes
62347  *
62348  * page. The first descriptor in the list should be located
62349  *
62350  * in this address. The first descriptor may be or may
62351  *
62352  * not be ready. The core starts processing the list from
62353  *
62354  * the CTD value.
62355  *
62356  * This field holds the address of the 2*(nTD+1) bytes of
62357  *
62358  * locations in which the isochronous descriptors are
62359  *
62360  * present where N is based on nTD as per Table below
62361  *
62362  * [31:N] Base Address
62363  *
62364  * [N-1:3] Offset
62365  *
62366  * [2:0] 000
62367  *
62368  * HS ISOC
62369  *
62370  * nTD N
62371  *
62372  * 7 6
62373  *
62374  * 15 7
62375  *
62376  * 31 8
62377  *
62378  * 63 9
62379  *
62380  * 127 10
62381  *
62382  * 255 11
62383  *
62384  * FS ISOC
62385  *
62386  * nTD N
62387  *
62388  * 1 4
62389  *
62390  * 3 5
62391  *
62392  * 7 6
62393  *
62394  * 15 7
62395  *
62396  * 31 8
62397  *
62398  * 63 9
62399  *
62400  * [N-1:3] (Isoc):
62401  *
62402  * [8:3] (Non Isoc): Current Transfer Desc(CTD):
62403  *
62404  * Non Isochronous:
62405  *
62406  * This value is in terms of number of descriptors. The values can be from 0 to 63.
62407  *
62408  * 0 - 1 descriptor.
62409  *
62410  * 63 - 64 descriptors.
62411  *
62412  * This field indicates the current descriptor processed in the list. This field is
62413  * updated
62414  *
62415  * both by application and the core. For example, if the application enables the
62416  *
62417  * channel after programming CTD=5, then the core will start processing the 6th
62418  *
62419  * descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
62420  *
62421  * to DMAAddr.
62422  *
62423  * Isochronous:
62424  *
62425  * CTD for isochronous is based on the current frame/(micro)frame value. Need to be
62426  * set
62427  *
62428  * to zero by application.
62429  *
62430  * Field Access Macros:
62431  *
62432  */
62433 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */
62434 #define ALT_USB_HOST_HCDMA15_HCDMA15_LSB 0
62435 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */
62436 #define ALT_USB_HOST_HCDMA15_HCDMA15_MSB 31
62437 /* The width in bits of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */
62438 #define ALT_USB_HOST_HCDMA15_HCDMA15_WIDTH 32
62439 /* The mask used to set the ALT_USB_HOST_HCDMA15_HCDMA15 register field value. */
62440 #define ALT_USB_HOST_HCDMA15_HCDMA15_SET_MSK 0xffffffff
62441 /* The mask used to clear the ALT_USB_HOST_HCDMA15_HCDMA15 register field value. */
62442 #define ALT_USB_HOST_HCDMA15_HCDMA15_CLR_MSK 0x00000000
62443 /* The reset value of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */
62444 #define ALT_USB_HOST_HCDMA15_HCDMA15_RESET 0x0
62445 /* Extracts the ALT_USB_HOST_HCDMA15_HCDMA15 field value from a register. */
62446 #define ALT_USB_HOST_HCDMA15_HCDMA15_GET(value) (((value) & 0xffffffff) >> 0)
62447 /* Produces a ALT_USB_HOST_HCDMA15_HCDMA15 register field value suitable for setting the register. */
62448 #define ALT_USB_HOST_HCDMA15_HCDMA15_SET(value) (((value) << 0) & 0xffffffff)
62449 
62450 #ifndef __ASSEMBLY__
62451 /*
62452  * WARNING: The C register and register group struct declarations are provided for
62453  * convenience and illustrative purposes. They should, however, be used with
62454  * caution as the C language standard provides no guarantees about the alignment or
62455  * atomicity of device memory accesses. The recommended practice for writing
62456  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62457  * alt_write_word() functions.
62458  *
62459  * The struct declaration for register ALT_USB_HOST_HCDMA15.
62460  */
62461 struct ALT_USB_HOST_HCDMA15_s
62462 {
62463  uint32_t hcdma15 : 32; /* ALT_USB_HOST_HCDMA15_HCDMA15 */
62464 };
62465 
62466 /* The typedef declaration for register ALT_USB_HOST_HCDMA15. */
62467 typedef volatile struct ALT_USB_HOST_HCDMA15_s ALT_USB_HOST_HCDMA15_t;
62468 #endif /* __ASSEMBLY__ */
62469 
62470 /* The reset value of the ALT_USB_HOST_HCDMA15 register. */
62471 #define ALT_USB_HOST_HCDMA15_RESET 0x00000000
62472 /* The byte offset of the ALT_USB_HOST_HCDMA15 register from the beginning of the component. */
62473 #define ALT_USB_HOST_HCDMA15_OFST 0x2f4
62474 /* The address of the ALT_USB_HOST_HCDMA15 register. */
62475 #define ALT_USB_HOST_HCDMA15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA15_OFST))
62476 
62477 /*
62478  * Register : hcdmab15
62479  *
62480  * Host Channel 15 DMA Buffer Address Register
62481  *
62482  * Register Layout
62483  *
62484  * Bits | Access | Reset | Description
62485  * :-------|:-------|:------|:-------------------------------
62486  * [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB15_HCDMAB15
62487  *
62488  */
62489 /*
62490  * Field : hcdmab15
62491  *
62492  * Holds the current buffer address.
62493  *
62494  * This register is updated as and when the data transfer for the corresponding end
62495  * point
62496  *
62497  * is in progress. This register is present only in Scatter/Gather DMA mode.
62498  * Otherwise this
62499  *
62500  * field is reserved.
62501  *
62502  * Field Access Macros:
62503  *
62504  */
62505 /* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */
62506 #define ALT_USB_HOST_HCDMAB15_HCDMAB15_LSB 0
62507 /* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */
62508 #define ALT_USB_HOST_HCDMAB15_HCDMAB15_MSB 31
62509 /* The width in bits of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */
62510 #define ALT_USB_HOST_HCDMAB15_HCDMAB15_WIDTH 32
62511 /* The mask used to set the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field value. */
62512 #define ALT_USB_HOST_HCDMAB15_HCDMAB15_SET_MSK 0xffffffff
62513 /* The mask used to clear the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field value. */
62514 #define ALT_USB_HOST_HCDMAB15_HCDMAB15_CLR_MSK 0x00000000
62515 /* The reset value of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */
62516 #define ALT_USB_HOST_HCDMAB15_HCDMAB15_RESET 0x0
62517 /* Extracts the ALT_USB_HOST_HCDMAB15_HCDMAB15 field value from a register. */
62518 #define ALT_USB_HOST_HCDMAB15_HCDMAB15_GET(value) (((value) & 0xffffffff) >> 0)
62519 /* Produces a ALT_USB_HOST_HCDMAB15_HCDMAB15 register field value suitable for setting the register. */
62520 #define ALT_USB_HOST_HCDMAB15_HCDMAB15_SET(value) (((value) << 0) & 0xffffffff)
62521 
62522 #ifndef __ASSEMBLY__
62523 /*
62524  * WARNING: The C register and register group struct declarations are provided for
62525  * convenience and illustrative purposes. They should, however, be used with
62526  * caution as the C language standard provides no guarantees about the alignment or
62527  * atomicity of device memory accesses. The recommended practice for writing
62528  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62529  * alt_write_word() functions.
62530  *
62531  * The struct declaration for register ALT_USB_HOST_HCDMAB15.
62532  */
62533 struct ALT_USB_HOST_HCDMAB15_s
62534 {
62535  uint32_t hcdmab15 : 32; /* ALT_USB_HOST_HCDMAB15_HCDMAB15 */
62536 };
62537 
62538 /* The typedef declaration for register ALT_USB_HOST_HCDMAB15. */
62539 typedef volatile struct ALT_USB_HOST_HCDMAB15_s ALT_USB_HOST_HCDMAB15_t;
62540 #endif /* __ASSEMBLY__ */
62541 
62542 /* The reset value of the ALT_USB_HOST_HCDMAB15 register. */
62543 #define ALT_USB_HOST_HCDMAB15_RESET 0x00000000
62544 /* The byte offset of the ALT_USB_HOST_HCDMAB15 register from the beginning of the component. */
62545 #define ALT_USB_HOST_HCDMAB15_OFST 0x2fc
62546 /* The address of the ALT_USB_HOST_HCDMAB15 register. */
62547 #define ALT_USB_HOST_HCDMAB15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB15_OFST))
62548 
62549 #ifndef __ASSEMBLY__
62550 /*
62551  * WARNING: The C register and register group struct declarations are provided for
62552  * convenience and illustrative purposes. They should, however, be used with
62553  * caution as the C language standard provides no guarantees about the alignment or
62554  * atomicity of device memory accesses. The recommended practice for writing
62555  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62556  * alt_write_word() functions.
62557  *
62558  * The struct declaration for register group ALT_USB_HOST.
62559  */
62560 struct ALT_USB_HOST_s
62561 {
62562  ALT_USB_HOST_HCFG_t hcfg; /* ALT_USB_HOST_HCFG */
62563  ALT_USB_HOST_HFIR_t hfir; /* ALT_USB_HOST_HFIR */
62564  ALT_USB_HOST_HFNUM_t hfnum; /* ALT_USB_HOST_HFNUM */
62565  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
62566  ALT_USB_HOST_HPTXSTS_t hptxsts; /* ALT_USB_HOST_HPTXSTS */
62567  ALT_USB_HOST_HAINT_t haint; /* ALT_USB_HOST_HAINT */
62568  ALT_USB_HOST_HAINTMSK_t haintmsk; /* ALT_USB_HOST_HAINTMSK */
62569  ALT_USB_HOST_HFLBADDR_t hflbaddr; /* ALT_USB_HOST_HFLBADDR */
62570  volatile uint32_t _pad_0x20_0x3f[8]; /* *UNDEFINED* */
62571  ALT_USB_HOST_HPRT_t hprt; /* ALT_USB_HOST_HPRT */
62572  volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */
62573  ALT_USB_HOST_HCCHAR0_t hcchar0; /* ALT_USB_HOST_HCCHAR0 */
62574  ALT_USB_HOST_HCSPLT0_t hcsplt0; /* ALT_USB_HOST_HCSPLT0 */
62575  ALT_USB_HOST_HCINT0_t hcint0; /* ALT_USB_HOST_HCINT0 */
62576  ALT_USB_HOST_HCINTMSK0_t hcintmsk0; /* ALT_USB_HOST_HCINTMSK0 */
62577  ALT_USB_HOST_HCTSIZ0_t hctsiz0; /* ALT_USB_HOST_HCTSIZ0 */
62578  ALT_USB_HOST_HCDMA0_t hcdma0; /* ALT_USB_HOST_HCDMA0 */
62579  volatile uint32_t _pad_0x118_0x11b; /* *UNDEFINED* */
62580  ALT_USB_HOST_HCDMAB0_t hcdmab0; /* ALT_USB_HOST_HCDMAB0 */
62581  ALT_USB_HOST_HCCHAR1_t hcchar1; /* ALT_USB_HOST_HCCHAR1 */
62582  ALT_USB_HOST_HCSPLT1_t hcsplt1; /* ALT_USB_HOST_HCSPLT1 */
62583  ALT_USB_HOST_HCINT1_t hcint1; /* ALT_USB_HOST_HCINT1 */
62584  ALT_USB_HOST_HCINTMSK1_t hcintmsk1; /* ALT_USB_HOST_HCINTMSK1 */
62585  ALT_USB_HOST_HCTSIZ1_t hctsiz1; /* ALT_USB_HOST_HCTSIZ1 */
62586  ALT_USB_HOST_HCDMA1_t hcdma1; /* ALT_USB_HOST_HCDMA1 */
62587  volatile uint32_t _pad_0x138_0x13b; /* *UNDEFINED* */
62588  ALT_USB_HOST_HCDMAB1_t hcdmab1; /* ALT_USB_HOST_HCDMAB1 */
62589  ALT_USB_HOST_HCCHAR2_t hcchar2; /* ALT_USB_HOST_HCCHAR2 */
62590  ALT_USB_HOST_HCSPLT2_t hcsplt2; /* ALT_USB_HOST_HCSPLT2 */
62591  ALT_USB_HOST_HCINT2_t hcint2; /* ALT_USB_HOST_HCINT2 */
62592  ALT_USB_HOST_HCINTMSK2_t hcintmsk2; /* ALT_USB_HOST_HCINTMSK2 */
62593  ALT_USB_HOST_HCTSIZ2_t hctsiz2; /* ALT_USB_HOST_HCTSIZ2 */
62594  ALT_USB_HOST_HCDMA2_t hcdma2; /* ALT_USB_HOST_HCDMA2 */
62595  volatile uint32_t _pad_0x158_0x15b; /* *UNDEFINED* */
62596  ALT_USB_HOST_HCDMAB2_t hcdmab2; /* ALT_USB_HOST_HCDMAB2 */
62597  ALT_USB_HOST_HCCHAR3_t hcchar3; /* ALT_USB_HOST_HCCHAR3 */
62598  ALT_USB_HOST_HCSPLT3_t hcsplt3; /* ALT_USB_HOST_HCSPLT3 */
62599  ALT_USB_HOST_HCINT3_t hcint3; /* ALT_USB_HOST_HCINT3 */
62600  ALT_USB_HOST_HCINTMSK3_t hcintmsk3; /* ALT_USB_HOST_HCINTMSK3 */
62601  ALT_USB_HOST_HCTSIZ3_t hctsiz3; /* ALT_USB_HOST_HCTSIZ3 */
62602  ALT_USB_HOST_HCDMA3_t hcdma3; /* ALT_USB_HOST_HCDMA3 */
62603  volatile uint32_t _pad_0x178_0x17b; /* *UNDEFINED* */
62604  ALT_USB_HOST_HCDMAB3_t hcdmab3; /* ALT_USB_HOST_HCDMAB3 */
62605  ALT_USB_HOST_HCCHAR4_t hcchar4; /* ALT_USB_HOST_HCCHAR4 */
62606  ALT_USB_HOST_HCSPLT4_t hcsplt4; /* ALT_USB_HOST_HCSPLT4 */
62607  ALT_USB_HOST_HCINT4_t hcint4; /* ALT_USB_HOST_HCINT4 */
62608  ALT_USB_HOST_HCINTMSK4_t hcintmsk4; /* ALT_USB_HOST_HCINTMSK4 */
62609  ALT_USB_HOST_HCTSIZ4_t hctsiz4; /* ALT_USB_HOST_HCTSIZ4 */
62610  ALT_USB_HOST_HCDMA4_t hcdma4; /* ALT_USB_HOST_HCDMA4 */
62611  volatile uint32_t _pad_0x198_0x19b; /* *UNDEFINED* */
62612  ALT_USB_HOST_HCDMAB4_t hcdmab4; /* ALT_USB_HOST_HCDMAB4 */
62613  ALT_USB_HOST_HCCHAR5_t hcchar5; /* ALT_USB_HOST_HCCHAR5 */
62614  ALT_USB_HOST_HCSPLT5_t hcsplt5; /* ALT_USB_HOST_HCSPLT5 */
62615  ALT_USB_HOST_HCINT5_t hcint5; /* ALT_USB_HOST_HCINT5 */
62616  ALT_USB_HOST_HCINTMSK5_t hcintmsk5; /* ALT_USB_HOST_HCINTMSK5 */
62617  ALT_USB_HOST_HCTSIZ5_t hctsiz5; /* ALT_USB_HOST_HCTSIZ5 */
62618  ALT_USB_HOST_HCDMA5_t hcdma5; /* ALT_USB_HOST_HCDMA5 */
62619  volatile uint32_t _pad_0x1b8_0x1bb; /* *UNDEFINED* */
62620  ALT_USB_HOST_HCDMAB5_t hcdmab5; /* ALT_USB_HOST_HCDMAB5 */
62621  ALT_USB_HOST_HCCHAR6_t hcchar6; /* ALT_USB_HOST_HCCHAR6 */
62622  ALT_USB_HOST_HCSPLT6_t hcsplt6; /* ALT_USB_HOST_HCSPLT6 */
62623  ALT_USB_HOST_HCINT6_t hcint6; /* ALT_USB_HOST_HCINT6 */
62624  ALT_USB_HOST_HCINTMSK6_t hcintmsk6; /* ALT_USB_HOST_HCINTMSK6 */
62625  ALT_USB_HOST_HCTSIZ6_t hctsiz6; /* ALT_USB_HOST_HCTSIZ6 */
62626  ALT_USB_HOST_HCDMA6_t hcdma6; /* ALT_USB_HOST_HCDMA6 */
62627  volatile uint32_t _pad_0x1d8_0x1db; /* *UNDEFINED* */
62628  ALT_USB_HOST_HCDMAB6_t hcdmab6; /* ALT_USB_HOST_HCDMAB6 */
62629  ALT_USB_HOST_HCCHAR7_t hcchar7; /* ALT_USB_HOST_HCCHAR7 */
62630  ALT_USB_HOST_HCSPLT7_t hcsplt7; /* ALT_USB_HOST_HCSPLT7 */
62631  ALT_USB_HOST_HCINT7_t hcint7; /* ALT_USB_HOST_HCINT7 */
62632  ALT_USB_HOST_HCINTMSK7_t hcintmsk7; /* ALT_USB_HOST_HCINTMSK7 */
62633  ALT_USB_HOST_HCTSIZ7_t hctsiz7; /* ALT_USB_HOST_HCTSIZ7 */
62634  ALT_USB_HOST_HCDMA7_t hcdma7; /* ALT_USB_HOST_HCDMA7 */
62635  volatile uint32_t _pad_0x1f8_0x1fb; /* *UNDEFINED* */
62636  ALT_USB_HOST_HCDMAB7_t hcdmab7; /* ALT_USB_HOST_HCDMAB7 */
62637  ALT_USB_HOST_HCCHAR8_t hcchar8; /* ALT_USB_HOST_HCCHAR8 */
62638  ALT_USB_HOST_HCSPLT8_t hcsplt8; /* ALT_USB_HOST_HCSPLT8 */
62639  ALT_USB_HOST_HCINT8_t hcint8; /* ALT_USB_HOST_HCINT8 */
62640  ALT_USB_HOST_HCINTMSK8_t hcintmsk8; /* ALT_USB_HOST_HCINTMSK8 */
62641  ALT_USB_HOST_HCTSIZ8_t hctsiz8; /* ALT_USB_HOST_HCTSIZ8 */
62642  ALT_USB_HOST_HCDMA8_t hcdma8; /* ALT_USB_HOST_HCDMA8 */
62643  volatile uint32_t _pad_0x218_0x21b; /* *UNDEFINED* */
62644  ALT_USB_HOST_HCDMAB8_t hcdmab8; /* ALT_USB_HOST_HCDMAB8 */
62645  ALT_USB_HOST_HCCHAR9_t hcchar9; /* ALT_USB_HOST_HCCHAR9 */
62646  ALT_USB_HOST_HCSPLT9_t hcsplt9; /* ALT_USB_HOST_HCSPLT9 */
62647  ALT_USB_HOST_HCINT9_t hcint9; /* ALT_USB_HOST_HCINT9 */
62648  ALT_USB_HOST_HCINTMSK9_t hcintmsk9; /* ALT_USB_HOST_HCINTMSK9 */
62649  ALT_USB_HOST_HCTSIZ9_t hctsiz9; /* ALT_USB_HOST_HCTSIZ9 */
62650  ALT_USB_HOST_HCDMA9_t hcdma9; /* ALT_USB_HOST_HCDMA9 */
62651  volatile uint32_t _pad_0x238_0x23b; /* *UNDEFINED* */
62652  ALT_USB_HOST_HCDMAB9_t hcdmab9; /* ALT_USB_HOST_HCDMAB9 */
62653  ALT_USB_HOST_HCCHAR10_t hcchar10; /* ALT_USB_HOST_HCCHAR10 */
62654  ALT_USB_HOST_HCSPLT10_t hcsplt10; /* ALT_USB_HOST_HCSPLT10 */
62655  ALT_USB_HOST_HCINT10_t hcint10; /* ALT_USB_HOST_HCINT10 */
62656  ALT_USB_HOST_HCINTMSK10_t hcintmsk10; /* ALT_USB_HOST_HCINTMSK10 */
62657  ALT_USB_HOST_HCTSIZ10_t hctsiz10; /* ALT_USB_HOST_HCTSIZ10 */
62658  ALT_USB_HOST_HCDMA10_t hcdma10; /* ALT_USB_HOST_HCDMA10 */
62659  volatile uint32_t _pad_0x258_0x25b; /* *UNDEFINED* */
62660  ALT_USB_HOST_HCDMAB10_t hcdmab10; /* ALT_USB_HOST_HCDMAB10 */
62661  ALT_USB_HOST_HCCHAR11_t hcchar11; /* ALT_USB_HOST_HCCHAR11 */
62662  ALT_USB_HOST_HCSPLT11_t hcsplt11; /* ALT_USB_HOST_HCSPLT11 */
62663  ALT_USB_HOST_HCINT11_t hcint11; /* ALT_USB_HOST_HCINT11 */
62664  ALT_USB_HOST_HCINTMSK11_t hcintmsk11; /* ALT_USB_HOST_HCINTMSK11 */
62665  ALT_USB_HOST_HCTSIZ11_t hctsiz11; /* ALT_USB_HOST_HCTSIZ11 */
62666  ALT_USB_HOST_HCDMA11_t hcdma11; /* ALT_USB_HOST_HCDMA11 */
62667  volatile uint32_t _pad_0x278_0x27b; /* *UNDEFINED* */
62668  ALT_USB_HOST_HCDMAB11_t hcdmab11; /* ALT_USB_HOST_HCDMAB11 */
62669  ALT_USB_HOST_HCCHAR12_t hcchar12; /* ALT_USB_HOST_HCCHAR12 */
62670  ALT_USB_HOST_HCSPLT12_t hcsplt12; /* ALT_USB_HOST_HCSPLT12 */
62671  ALT_USB_HOST_HCINT12_t hcint12; /* ALT_USB_HOST_HCINT12 */
62672  ALT_USB_HOST_HCINTMSK12_t hcintmsk12; /* ALT_USB_HOST_HCINTMSK12 */
62673  ALT_USB_HOST_HCTSIZ12_t hctsiz12; /* ALT_USB_HOST_HCTSIZ12 */
62674  ALT_USB_HOST_HCDMA12_t hcdma12; /* ALT_USB_HOST_HCDMA12 */
62675  volatile uint32_t _pad_0x298_0x29b; /* *UNDEFINED* */
62676  ALT_USB_HOST_HCDMAB12_t hcdmab12; /* ALT_USB_HOST_HCDMAB12 */
62677  ALT_USB_HOST_HCCHAR13_t hcchar13; /* ALT_USB_HOST_HCCHAR13 */
62678  ALT_USB_HOST_HCSPLT13_t hcsplt13; /* ALT_USB_HOST_HCSPLT13 */
62679  ALT_USB_HOST_HCINT13_t hcint13; /* ALT_USB_HOST_HCINT13 */
62680  ALT_USB_HOST_HCINTMSK13_t hcintmsk13; /* ALT_USB_HOST_HCINTMSK13 */
62681  ALT_USB_HOST_HCTSIZ13_t hctsiz13; /* ALT_USB_HOST_HCTSIZ13 */
62682  ALT_USB_HOST_HCDMA13_t hcdma13; /* ALT_USB_HOST_HCDMA13 */
62683  volatile uint32_t _pad_0x2b8_0x2bb; /* *UNDEFINED* */
62684  ALT_USB_HOST_HCDMAB13_t hcdmab13; /* ALT_USB_HOST_HCDMAB13 */
62685  ALT_USB_HOST_HCCHAR14_t hcchar14; /* ALT_USB_HOST_HCCHAR14 */
62686  ALT_USB_HOST_HCSPLT14_t hcsplt14; /* ALT_USB_HOST_HCSPLT14 */
62687  ALT_USB_HOST_HCINT14_t hcint14; /* ALT_USB_HOST_HCINT14 */
62688  ALT_USB_HOST_HCINTMSK14_t hcintmsk14; /* ALT_USB_HOST_HCINTMSK14 */
62689  ALT_USB_HOST_HCTSIZ14_t hctsiz14; /* ALT_USB_HOST_HCTSIZ14 */
62690  ALT_USB_HOST_HCDMA14_t hcdma14; /* ALT_USB_HOST_HCDMA14 */
62691  volatile uint32_t _pad_0x2d8_0x2db; /* *UNDEFINED* */
62692  ALT_USB_HOST_HCDMAB14_t hcdmab14; /* ALT_USB_HOST_HCDMAB14 */
62693  ALT_USB_HOST_HCCHAR15_t hcchar15; /* ALT_USB_HOST_HCCHAR15 */
62694  ALT_USB_HOST_HCSPLT15_t hcsplt15; /* ALT_USB_HOST_HCSPLT15 */
62695  ALT_USB_HOST_HCINT15_t hcint15; /* ALT_USB_HOST_HCINT15 */
62696  ALT_USB_HOST_HCINTMSK15_t hcintmsk15; /* ALT_USB_HOST_HCINTMSK15 */
62697  ALT_USB_HOST_HCTSIZ15_t hctsiz15; /* ALT_USB_HOST_HCTSIZ15 */
62698  ALT_USB_HOST_HCDMA15_t hcdma15; /* ALT_USB_HOST_HCDMA15 */
62699  volatile uint32_t _pad_0x2f8_0x2fb; /* *UNDEFINED* */
62700  ALT_USB_HOST_HCDMAB15_t hcdmab15; /* ALT_USB_HOST_HCDMAB15 */
62701 };
62702 
62703 /* The typedef declaration for register group ALT_USB_HOST. */
62704 typedef volatile struct ALT_USB_HOST_s ALT_USB_HOST_t;
62705 /* The struct declaration for the raw register contents of register group ALT_USB_HOST. */
62706 struct ALT_USB_HOST_raw_s
62707 {
62708  volatile uint32_t hcfg; /* ALT_USB_HOST_HCFG */
62709  volatile uint32_t hfir; /* ALT_USB_HOST_HFIR */
62710  volatile uint32_t hfnum; /* ALT_USB_HOST_HFNUM */
62711  uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
62712  volatile uint32_t hptxsts; /* ALT_USB_HOST_HPTXSTS */
62713  volatile uint32_t haint; /* ALT_USB_HOST_HAINT */
62714  volatile uint32_t haintmsk; /* ALT_USB_HOST_HAINTMSK */
62715  volatile uint32_t hflbaddr; /* ALT_USB_HOST_HFLBADDR */
62716  uint32_t _pad_0x20_0x3f[8]; /* *UNDEFINED* */
62717  volatile uint32_t hprt; /* ALT_USB_HOST_HPRT */
62718  uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */
62719  volatile uint32_t hcchar0; /* ALT_USB_HOST_HCCHAR0 */
62720  volatile uint32_t hcsplt0; /* ALT_USB_HOST_HCSPLT0 */
62721  volatile uint32_t hcint0; /* ALT_USB_HOST_HCINT0 */
62722  volatile uint32_t hcintmsk0; /* ALT_USB_HOST_HCINTMSK0 */
62723  volatile uint32_t hctsiz0; /* ALT_USB_HOST_HCTSIZ0 */
62724  volatile uint32_t hcdma0; /* ALT_USB_HOST_HCDMA0 */
62725  uint32_t _pad_0x118_0x11b; /* *UNDEFINED* */
62726  volatile uint32_t hcdmab0; /* ALT_USB_HOST_HCDMAB0 */
62727  volatile uint32_t hcchar1; /* ALT_USB_HOST_HCCHAR1 */
62728  volatile uint32_t hcsplt1; /* ALT_USB_HOST_HCSPLT1 */
62729  volatile uint32_t hcint1; /* ALT_USB_HOST_HCINT1 */
62730  volatile uint32_t hcintmsk1; /* ALT_USB_HOST_HCINTMSK1 */
62731  volatile uint32_t hctsiz1; /* ALT_USB_HOST_HCTSIZ1 */
62732  volatile uint32_t hcdma1; /* ALT_USB_HOST_HCDMA1 */
62733  uint32_t _pad_0x138_0x13b; /* *UNDEFINED* */
62734  volatile uint32_t hcdmab1; /* ALT_USB_HOST_HCDMAB1 */
62735  volatile uint32_t hcchar2; /* ALT_USB_HOST_HCCHAR2 */
62736  volatile uint32_t hcsplt2; /* ALT_USB_HOST_HCSPLT2 */
62737  volatile uint32_t hcint2; /* ALT_USB_HOST_HCINT2 */
62738  volatile uint32_t hcintmsk2; /* ALT_USB_HOST_HCINTMSK2 */
62739  volatile uint32_t hctsiz2; /* ALT_USB_HOST_HCTSIZ2 */
62740  volatile uint32_t hcdma2; /* ALT_USB_HOST_HCDMA2 */
62741  uint32_t _pad_0x158_0x15b; /* *UNDEFINED* */
62742  volatile uint32_t hcdmab2; /* ALT_USB_HOST_HCDMAB2 */
62743  volatile uint32_t hcchar3; /* ALT_USB_HOST_HCCHAR3 */
62744  volatile uint32_t hcsplt3; /* ALT_USB_HOST_HCSPLT3 */
62745  volatile uint32_t hcint3; /* ALT_USB_HOST_HCINT3 */
62746  volatile uint32_t hcintmsk3; /* ALT_USB_HOST_HCINTMSK3 */
62747  volatile uint32_t hctsiz3; /* ALT_USB_HOST_HCTSIZ3 */
62748  volatile uint32_t hcdma3; /* ALT_USB_HOST_HCDMA3 */
62749  uint32_t _pad_0x178_0x17b; /* *UNDEFINED* */
62750  volatile uint32_t hcdmab3; /* ALT_USB_HOST_HCDMAB3 */
62751  volatile uint32_t hcchar4; /* ALT_USB_HOST_HCCHAR4 */
62752  volatile uint32_t hcsplt4; /* ALT_USB_HOST_HCSPLT4 */
62753  volatile uint32_t hcint4; /* ALT_USB_HOST_HCINT4 */
62754  volatile uint32_t hcintmsk4; /* ALT_USB_HOST_HCINTMSK4 */
62755  volatile uint32_t hctsiz4; /* ALT_USB_HOST_HCTSIZ4 */
62756  volatile uint32_t hcdma4; /* ALT_USB_HOST_HCDMA4 */
62757  uint32_t _pad_0x198_0x19b; /* *UNDEFINED* */
62758  volatile uint32_t hcdmab4; /* ALT_USB_HOST_HCDMAB4 */
62759  volatile uint32_t hcchar5; /* ALT_USB_HOST_HCCHAR5 */
62760  volatile uint32_t hcsplt5; /* ALT_USB_HOST_HCSPLT5 */
62761  volatile uint32_t hcint5; /* ALT_USB_HOST_HCINT5 */
62762  volatile uint32_t hcintmsk5; /* ALT_USB_HOST_HCINTMSK5 */
62763  volatile uint32_t hctsiz5; /* ALT_USB_HOST_HCTSIZ5 */
62764  volatile uint32_t hcdma5; /* ALT_USB_HOST_HCDMA5 */
62765  uint32_t _pad_0x1b8_0x1bb; /* *UNDEFINED* */
62766  volatile uint32_t hcdmab5; /* ALT_USB_HOST_HCDMAB5 */
62767  volatile uint32_t hcchar6; /* ALT_USB_HOST_HCCHAR6 */
62768  volatile uint32_t hcsplt6; /* ALT_USB_HOST_HCSPLT6 */
62769  volatile uint32_t hcint6; /* ALT_USB_HOST_HCINT6 */
62770  volatile uint32_t hcintmsk6; /* ALT_USB_HOST_HCINTMSK6 */
62771  volatile uint32_t hctsiz6; /* ALT_USB_HOST_HCTSIZ6 */
62772  volatile uint32_t hcdma6; /* ALT_USB_HOST_HCDMA6 */
62773  uint32_t _pad_0x1d8_0x1db; /* *UNDEFINED* */
62774  volatile uint32_t hcdmab6; /* ALT_USB_HOST_HCDMAB6 */
62775  volatile uint32_t hcchar7; /* ALT_USB_HOST_HCCHAR7 */
62776  volatile uint32_t hcsplt7; /* ALT_USB_HOST_HCSPLT7 */
62777  volatile uint32_t hcint7; /* ALT_USB_HOST_HCINT7 */
62778  volatile uint32_t hcintmsk7; /* ALT_USB_HOST_HCINTMSK7 */
62779  volatile uint32_t hctsiz7; /* ALT_USB_HOST_HCTSIZ7 */
62780  volatile uint32_t hcdma7; /* ALT_USB_HOST_HCDMA7 */
62781  uint32_t _pad_0x1f8_0x1fb; /* *UNDEFINED* */
62782  volatile uint32_t hcdmab7; /* ALT_USB_HOST_HCDMAB7 */
62783  volatile uint32_t hcchar8; /* ALT_USB_HOST_HCCHAR8 */
62784  volatile uint32_t hcsplt8; /* ALT_USB_HOST_HCSPLT8 */
62785  volatile uint32_t hcint8; /* ALT_USB_HOST_HCINT8 */
62786  volatile uint32_t hcintmsk8; /* ALT_USB_HOST_HCINTMSK8 */
62787  volatile uint32_t hctsiz8; /* ALT_USB_HOST_HCTSIZ8 */
62788  volatile uint32_t hcdma8; /* ALT_USB_HOST_HCDMA8 */
62789  uint32_t _pad_0x218_0x21b; /* *UNDEFINED* */
62790  volatile uint32_t hcdmab8; /* ALT_USB_HOST_HCDMAB8 */
62791  volatile uint32_t hcchar9; /* ALT_USB_HOST_HCCHAR9 */
62792  volatile uint32_t hcsplt9; /* ALT_USB_HOST_HCSPLT9 */
62793  volatile uint32_t hcint9; /* ALT_USB_HOST_HCINT9 */
62794  volatile uint32_t hcintmsk9; /* ALT_USB_HOST_HCINTMSK9 */
62795  volatile uint32_t hctsiz9; /* ALT_USB_HOST_HCTSIZ9 */
62796  volatile uint32_t hcdma9; /* ALT_USB_HOST_HCDMA9 */
62797  uint32_t _pad_0x238_0x23b; /* *UNDEFINED* */
62798  volatile uint32_t hcdmab9; /* ALT_USB_HOST_HCDMAB9 */
62799  volatile uint32_t hcchar10; /* ALT_USB_HOST_HCCHAR10 */
62800  volatile uint32_t hcsplt10; /* ALT_USB_HOST_HCSPLT10 */
62801  volatile uint32_t hcint10; /* ALT_USB_HOST_HCINT10 */
62802  volatile uint32_t hcintmsk10; /* ALT_USB_HOST_HCINTMSK10 */
62803  volatile uint32_t hctsiz10; /* ALT_USB_HOST_HCTSIZ10 */
62804  volatile uint32_t hcdma10; /* ALT_USB_HOST_HCDMA10 */
62805  uint32_t _pad_0x258_0x25b; /* *UNDEFINED* */
62806  volatile uint32_t hcdmab10; /* ALT_USB_HOST_HCDMAB10 */
62807  volatile uint32_t hcchar11; /* ALT_USB_HOST_HCCHAR11 */
62808  volatile uint32_t hcsplt11; /* ALT_USB_HOST_HCSPLT11 */
62809  volatile uint32_t hcint11; /* ALT_USB_HOST_HCINT11 */
62810  volatile uint32_t hcintmsk11; /* ALT_USB_HOST_HCINTMSK11 */
62811  volatile uint32_t hctsiz11; /* ALT_USB_HOST_HCTSIZ11 */
62812  volatile uint32_t hcdma11; /* ALT_USB_HOST_HCDMA11 */
62813  uint32_t _pad_0x278_0x27b; /* *UNDEFINED* */
62814  volatile uint32_t hcdmab11; /* ALT_USB_HOST_HCDMAB11 */
62815  volatile uint32_t hcchar12; /* ALT_USB_HOST_HCCHAR12 */
62816  volatile uint32_t hcsplt12; /* ALT_USB_HOST_HCSPLT12 */
62817  volatile uint32_t hcint12; /* ALT_USB_HOST_HCINT12 */
62818  volatile uint32_t hcintmsk12; /* ALT_USB_HOST_HCINTMSK12 */
62819  volatile uint32_t hctsiz12; /* ALT_USB_HOST_HCTSIZ12 */
62820  volatile uint32_t hcdma12; /* ALT_USB_HOST_HCDMA12 */
62821  uint32_t _pad_0x298_0x29b; /* *UNDEFINED* */
62822  volatile uint32_t hcdmab12; /* ALT_USB_HOST_HCDMAB12 */
62823  volatile uint32_t hcchar13; /* ALT_USB_HOST_HCCHAR13 */
62824  volatile uint32_t hcsplt13; /* ALT_USB_HOST_HCSPLT13 */
62825  volatile uint32_t hcint13; /* ALT_USB_HOST_HCINT13 */
62826  volatile uint32_t hcintmsk13; /* ALT_USB_HOST_HCINTMSK13 */
62827  volatile uint32_t hctsiz13; /* ALT_USB_HOST_HCTSIZ13 */
62828  volatile uint32_t hcdma13; /* ALT_USB_HOST_HCDMA13 */
62829  uint32_t _pad_0x2b8_0x2bb; /* *UNDEFINED* */
62830  volatile uint32_t hcdmab13; /* ALT_USB_HOST_HCDMAB13 */
62831  volatile uint32_t hcchar14; /* ALT_USB_HOST_HCCHAR14 */
62832  volatile uint32_t hcsplt14; /* ALT_USB_HOST_HCSPLT14 */
62833  volatile uint32_t hcint14; /* ALT_USB_HOST_HCINT14 */
62834  volatile uint32_t hcintmsk14; /* ALT_USB_HOST_HCINTMSK14 */
62835  volatile uint32_t hctsiz14; /* ALT_USB_HOST_HCTSIZ14 */
62836  volatile uint32_t hcdma14; /* ALT_USB_HOST_HCDMA14 */
62837  uint32_t _pad_0x2d8_0x2db; /* *UNDEFINED* */
62838  volatile uint32_t hcdmab14; /* ALT_USB_HOST_HCDMAB14 */
62839  volatile uint32_t hcchar15; /* ALT_USB_HOST_HCCHAR15 */
62840  volatile uint32_t hcsplt15; /* ALT_USB_HOST_HCSPLT15 */
62841  volatile uint32_t hcint15; /* ALT_USB_HOST_HCINT15 */
62842  volatile uint32_t hcintmsk15; /* ALT_USB_HOST_HCINTMSK15 */
62843  volatile uint32_t hctsiz15; /* ALT_USB_HOST_HCTSIZ15 */
62844  volatile uint32_t hcdma15; /* ALT_USB_HOST_HCDMA15 */
62845  uint32_t _pad_0x2f8_0x2fb; /* *UNDEFINED* */
62846  volatile uint32_t hcdmab15; /* ALT_USB_HOST_HCDMAB15 */
62847 };
62848 
62849 /* The typedef declaration for the raw register contents of register group ALT_USB_HOST. */
62850 typedef volatile struct ALT_USB_HOST_raw_s ALT_USB_HOST_raw_t;
62851 #endif /* __ASSEMBLY__ */
62852 
62853 
62854 /*
62855  * Component : ALT_USB_DEV
62856  *
62857  */
62858 /*
62859  * Register : dcfg
62860  *
62861  * Device Configuration Register
62862  *
62863  * Register Layout
62864  *
62865  * Bits | Access | Reset | Description
62866  * :--------|:-------|:------|:-------------------------------
62867  * [1:0] | RW | 0x0 | ALT_USB_DEV_DCFG_DEVSPD
62868  * [2] | RW | 0x0 | ALT_USB_DEV_DCFG_NZSTSOUTHSHK
62869  * [3] | RW | 0x0 | ALT_USB_DEV_DCFG_ENA32KHZSUSP
62870  * [10:4] | RW | 0x0 | ALT_USB_DEV_DCFG_DEVADDR
62871  * [12:11] | RW | 0x0 | ALT_USB_DEV_DCFG_PERFRINT
62872  * [13] | RW | 0x0 | ALT_USB_DEV_DCFG_ENDEVOUTNAK
62873  * [14] | RW | 0x0 | ALT_USB_DEV_DCFG_XCVRDLY
62874  * [15] | RW | 0x0 | ALT_USB_DEV_DCFG_ERRATICINTMSK
62875  * [22:16] | ??? | 0x20 | *UNDEFINED*
62876  * [23] | RW | 0x0 | ALT_USB_DEV_DCFG_DESCDMA
62877  * [25:24] | RW | 0x0 | ALT_USB_DEV_DCFG_PERSCHINTVL
62878  * [31:26] | RW | 0x2 | ALT_USB_DEV_DCFG_RESVALID
62879  *
62880  */
62881 /*
62882  * Field : devspd
62883  *
62884  * Device Speed (DevSpd)
62885  *
62886  * Indicates the speed at which the application requires the core to
62887  *
62888  * enumerate, or the maximum speed the application can support.
62889  *
62890  * However, the actual bus speed is determined only after the chirp
62891  *
62892  * sequence is completed, and is based on the speed of the USB
62893  *
62894  * host to which the core is connected. See "Device Initialization"
62895  *
62896  * .
62897  *
62898  * 2'b00: High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
62899  *
62900  * 2'b01: Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
62901  *
62902  * 2'b10: Low speed (USB 1.1 transceiver clock is 6 MHz). If
62903  *
62904  * you select 6 MHz LS mode, you must do a soft reset.
62905  *
62906  * 2'b11: Full speed (USB 1.1 transceiver clock is 48 MHz)
62907  *
62908  * Field Enumeration Values:
62909  *
62910  * Enum | Value | Description
62911  * :------------------------------------|:------|:-------------------------------------------------
62912  * ALT_USB_DEV_DCFG_DEVSPD_E_USBHS20 | 0x0 | High speed USB 2.0 PHY clock is 30 MHz or 60 MHz
62913  * ALT_USB_DEV_DCFG_DEVSPD_E_USBFS20 | 0x1 | Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz
62914  * ALT_USB_DEV_DCFG_DEVSPD_E_USBLS116 | 0x2 | Low speed USB 1.1 transceiver clock is 6 MHz
62915  * ALT_USB_DEV_DCFG_DEVSPD_E_USBLS1148 | 0x3 | Full speed USB 1.1 transceiver clock is 48 MHz
62916  *
62917  * Field Access Macros:
62918  *
62919  */
62920 /*
62921  * Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD
62922  *
62923  * High speed USB 2.0 PHY clock is 30 MHz or 60 MHz
62924  */
62925 #define ALT_USB_DEV_DCFG_DEVSPD_E_USBHS20 0x0
62926 /*
62927  * Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD
62928  *
62929  * Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz
62930  */
62931 #define ALT_USB_DEV_DCFG_DEVSPD_E_USBFS20 0x1
62932 /*
62933  * Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD
62934  *
62935  * Low speed USB 1.1 transceiver clock is 6 MHz
62936  */
62937 #define ALT_USB_DEV_DCFG_DEVSPD_E_USBLS116 0x2
62938 /*
62939  * Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD
62940  *
62941  * Full speed USB 1.1 transceiver clock is 48 MHz
62942  */
62943 #define ALT_USB_DEV_DCFG_DEVSPD_E_USBLS1148 0x3
62944 
62945 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DEVSPD register field. */
62946 #define ALT_USB_DEV_DCFG_DEVSPD_LSB 0
62947 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DEVSPD register field. */
62948 #define ALT_USB_DEV_DCFG_DEVSPD_MSB 1
62949 /* The width in bits of the ALT_USB_DEV_DCFG_DEVSPD register field. */
62950 #define ALT_USB_DEV_DCFG_DEVSPD_WIDTH 2
62951 /* The mask used to set the ALT_USB_DEV_DCFG_DEVSPD register field value. */
62952 #define ALT_USB_DEV_DCFG_DEVSPD_SET_MSK 0x00000003
62953 /* The mask used to clear the ALT_USB_DEV_DCFG_DEVSPD register field value. */
62954 #define ALT_USB_DEV_DCFG_DEVSPD_CLR_MSK 0xfffffffc
62955 /* The reset value of the ALT_USB_DEV_DCFG_DEVSPD register field. */
62956 #define ALT_USB_DEV_DCFG_DEVSPD_RESET 0x0
62957 /* Extracts the ALT_USB_DEV_DCFG_DEVSPD field value from a register. */
62958 #define ALT_USB_DEV_DCFG_DEVSPD_GET(value) (((value) & 0x00000003) >> 0)
62959 /* Produces a ALT_USB_DEV_DCFG_DEVSPD register field value suitable for setting the register. */
62960 #define ALT_USB_DEV_DCFG_DEVSPD_SET(value) (((value) << 0) & 0x00000003)
62961 
62962 /*
62963  * Field : nzstsouthshk
62964  *
62965  * Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)
62966  *
62967  * The application can use this field to select the handshake the
62968  *
62969  * core sends on receiving a nonzero-length data packet during the
62970  *
62971  * OUT transaction of a control transfer's Status stage.
62972  *
62973  * 1'b1: Send a STALL handshake on a nonzero-length status
62974  *
62975  * OUT transaction and do not send the received OUT packet to
62976  *
62977  * the application.
62978  *
62979  * 1'b0: Send the received OUT packet to the application (zerolength
62980  *
62981  * or nonzero-length) and send a handshake based on
62982  *
62983  * the NAK and STALL bits For the endpoint in the Device
62984  *
62985  * Endpoint Control register.
62986  *
62987  * Field Enumeration Values:
62988  *
62989  * Enum | Value | Description
62990  * :------------------------------------------|:------|:------------------------------------------------
62991  * ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDOUT | 0x0 | Send the received OUT packet to the application
62992  * : | | zerolength
62993  * ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDSTALL | 0x1 | Send a STALL handshake on a nonzero-length
62994  * : | | status OUT transaction and do not send the
62995  * : | | received OUT packet to the application
62996  *
62997  * Field Access Macros:
62998  *
62999  */
63000 /*
63001  * Enumerated value for register field ALT_USB_DEV_DCFG_NZSTSOUTHSHK
63002  *
63003  * Send the received OUT packet to the application zerolength
63004  */
63005 #define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDOUT 0x0
63006 /*
63007  * Enumerated value for register field ALT_USB_DEV_DCFG_NZSTSOUTHSHK
63008  *
63009  * Send a STALL handshake on a nonzero-length status OUT transaction and do not
63010  * send the received OUT packet to the application
63011  */
63012 #define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDSTALL 0x1
63013 
63014 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */
63015 #define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_LSB 2
63016 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */
63017 #define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_MSB 2
63018 /* The width in bits of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */
63019 #define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_WIDTH 1
63020 /* The mask used to set the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value. */
63021 #define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_SET_MSK 0x00000004
63022 /* The mask used to clear the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value. */
63023 #define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_CLR_MSK 0xfffffffb
63024 /* The reset value of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */
63025 #define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_RESET 0x0
63026 /* Extracts the ALT_USB_DEV_DCFG_NZSTSOUTHSHK field value from a register. */
63027 #define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_GET(value) (((value) & 0x00000004) >> 2)
63028 /* Produces a ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value suitable for setting the register. */
63029 #define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_SET(value) (((value) << 2) & 0x00000004)
63030 
63031 /*
63032  * Field : ena32khzsusp
63033  *
63034  * Enable 32 KHz Suspend mode (Ena32KHzSusp)
63035  *
63036  * This bit can be set only if FS PHY interface is selected. Else,
63037  *
63038  * this bit needs to be set to zero. When FS PHY interface is chosen
63039  *
63040  * and this bit is set, the core expects that the PHY clock during
63041  *
63042  * Suspend is switched from 48 MHz to 32 KHz.
63043  *
63044  * Field Enumeration Values:
63045  *
63046  * Enum | Value | Description
63047  * :-------------------------------------|:------|:------------------------------------------------
63048  * ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_DISD | 0x0 | USB 1.1 Full-Speed Serial Transceiver not
63049  * : | | selected
63050  * ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_END | 0x1 | USB 1.1 Full-Speed Serial Transceiver Interface
63051  * : | | selected
63052  *
63053  * Field Access Macros:
63054  *
63055  */
63056 /*
63057  * Enumerated value for register field ALT_USB_DEV_DCFG_ENA32KHZSUSP
63058  *
63059  * USB 1.1 Full-Speed Serial Transceiver not selected
63060  */
63061 #define ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_DISD 0x0
63062 /*
63063  * Enumerated value for register field ALT_USB_DEV_DCFG_ENA32KHZSUSP
63064  *
63065  * USB 1.1 Full-Speed Serial Transceiver Interface selected
63066  */
63067 #define ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_END 0x1
63068 
63069 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */
63070 #define ALT_USB_DEV_DCFG_ENA32KHZSUSP_LSB 3
63071 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */
63072 #define ALT_USB_DEV_DCFG_ENA32KHZSUSP_MSB 3
63073 /* The width in bits of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */
63074 #define ALT_USB_DEV_DCFG_ENA32KHZSUSP_WIDTH 1
63075 /* The mask used to set the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value. */
63076 #define ALT_USB_DEV_DCFG_ENA32KHZSUSP_SET_MSK 0x00000008
63077 /* The mask used to clear the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value. */
63078 #define ALT_USB_DEV_DCFG_ENA32KHZSUSP_CLR_MSK 0xfffffff7
63079 /* The reset value of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */
63080 #define ALT_USB_DEV_DCFG_ENA32KHZSUSP_RESET 0x0
63081 /* Extracts the ALT_USB_DEV_DCFG_ENA32KHZSUSP field value from a register. */
63082 #define ALT_USB_DEV_DCFG_ENA32KHZSUSP_GET(value) (((value) & 0x00000008) >> 3)
63083 /* Produces a ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value suitable for setting the register. */
63084 #define ALT_USB_DEV_DCFG_ENA32KHZSUSP_SET(value) (((value) << 3) & 0x00000008)
63085 
63086 /*
63087  * Field : devaddr
63088  *
63089  * Device Address (DevAddr)
63090  *
63091  * The application must program this field after every SetAddress
63092  *
63093  * control command.
63094  *
63095  * Field Access Macros:
63096  *
63097  */
63098 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DEVADDR register field. */
63099 #define ALT_USB_DEV_DCFG_DEVADDR_LSB 4
63100 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DEVADDR register field. */
63101 #define ALT_USB_DEV_DCFG_DEVADDR_MSB 10
63102 /* The width in bits of the ALT_USB_DEV_DCFG_DEVADDR register field. */
63103 #define ALT_USB_DEV_DCFG_DEVADDR_WIDTH 7
63104 /* The mask used to set the ALT_USB_DEV_DCFG_DEVADDR register field value. */
63105 #define ALT_USB_DEV_DCFG_DEVADDR_SET_MSK 0x000007f0
63106 /* The mask used to clear the ALT_USB_DEV_DCFG_DEVADDR register field value. */
63107 #define ALT_USB_DEV_DCFG_DEVADDR_CLR_MSK 0xfffff80f
63108 /* The reset value of the ALT_USB_DEV_DCFG_DEVADDR register field. */
63109 #define ALT_USB_DEV_DCFG_DEVADDR_RESET 0x0
63110 /* Extracts the ALT_USB_DEV_DCFG_DEVADDR field value from a register. */
63111 #define ALT_USB_DEV_DCFG_DEVADDR_GET(value) (((value) & 0x000007f0) >> 4)
63112 /* Produces a ALT_USB_DEV_DCFG_DEVADDR register field value suitable for setting the register. */
63113 #define ALT_USB_DEV_DCFG_DEVADDR_SET(value) (((value) << 4) & 0x000007f0)
63114 
63115 /*
63116  * Field : perfrint
63117  *
63118  * Periodic Frame Interval (PerFrInt)
63119  *
63120  * Indicates the time within a (micro)frame at which the application
63121  *
63122  * must be notified using the End Of Periodic Frame Interrupt. This
63123  *
63124  * can be used to determine If all the isochronous traffic For that
63125  *
63126  * (micro)frame is complete.
63127  *
63128  * 2'b00: 80% of the (micro)frame interval
63129  *
63130  * 2'b01: 85%
63131  *
63132  * 2'b10: 90%
63133  *
63134  * 2'b11: 95%
63135  *
63136  * Field Enumeration Values:
63137  *
63138  * Enum | Value | Description
63139  * :-----------------------------------|:------|:---------------------------------
63140  * ALT_USB_DEV_DCFG_PERFRINT_E_EOPF80 | 0x0 | 80% of the (micro)frame interval
63141  * ALT_USB_DEV_DCFG_PERFRINT_E_EOPF85 | 0x1 | 85% of the (micro)frame interval
63142  * ALT_USB_DEV_DCFG_PERFRINT_E_EOPF90 | 0x2 | 90% of the (micro)frame interval
63143  * ALT_USB_DEV_DCFG_PERFRINT_E_EOPF95 | 0x3 | 95% of the (micro)frame interval
63144  *
63145  * Field Access Macros:
63146  *
63147  */
63148 /*
63149  * Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT
63150  *
63151  * 80% of the (micro)frame interval
63152  */
63153 #define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF80 0x0
63154 /*
63155  * Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT
63156  *
63157  * 85% of the (micro)frame interval
63158  */
63159 #define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF85 0x1
63160 /*
63161  * Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT
63162  *
63163  * 90% of the (micro)frame interval
63164  */
63165 #define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF90 0x2
63166 /*
63167  * Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT
63168  *
63169  * 95% of the (micro)frame interval
63170  */
63171 #define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF95 0x3
63172 
63173 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_PERFRINT register field. */
63174 #define ALT_USB_DEV_DCFG_PERFRINT_LSB 11
63175 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_PERFRINT register field. */
63176 #define ALT_USB_DEV_DCFG_PERFRINT_MSB 12
63177 /* The width in bits of the ALT_USB_DEV_DCFG_PERFRINT register field. */
63178 #define ALT_USB_DEV_DCFG_PERFRINT_WIDTH 2
63179 /* The mask used to set the ALT_USB_DEV_DCFG_PERFRINT register field value. */
63180 #define ALT_USB_DEV_DCFG_PERFRINT_SET_MSK 0x00001800
63181 /* The mask used to clear the ALT_USB_DEV_DCFG_PERFRINT register field value. */
63182 #define ALT_USB_DEV_DCFG_PERFRINT_CLR_MSK 0xffffe7ff
63183 /* The reset value of the ALT_USB_DEV_DCFG_PERFRINT register field. */
63184 #define ALT_USB_DEV_DCFG_PERFRINT_RESET 0x0
63185 /* Extracts the ALT_USB_DEV_DCFG_PERFRINT field value from a register. */
63186 #define ALT_USB_DEV_DCFG_PERFRINT_GET(value) (((value) & 0x00001800) >> 11)
63187 /* Produces a ALT_USB_DEV_DCFG_PERFRINT register field value suitable for setting the register. */
63188 #define ALT_USB_DEV_DCFG_PERFRINT_SET(value) (((value) << 11) & 0x00001800)
63189 
63190 /*
63191  * Field : endevoutnak
63192  *
63193  * Enable Device OUT NAK (EnDevOutNak)
63194  *
63195  * This bit enables setting NAK for Bulk OUT endpoints after the transfer is
63196  * completed
63197  *
63198  * for Device mode Descriptor DMA
63199  *
63200  * 1'b0 : The core does not set NAK after Bulk OUT transfer complete
63201  *
63202  * 1'b1 : The core sets NAK after Bulk OUT transfer complete
63203  *
63204  * It is one time
63205  *
63206  * programmable after reset like any other DCFG register bits.
63207  *
63208  * Field Enumeration Values:
63209  *
63210  * Enum | Value | Description
63211  * :------------------------------------|:------|:------------------------------------------
63212  * ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_DISD | 0x0 | The core does not set NAK after Bulk OUT
63213  * : | | transfer complete
63214  * ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_END | 0x1 | The core sets NAK after Bulk OUT transfer
63215  * : | | complete
63216  *
63217  * Field Access Macros:
63218  *
63219  */
63220 /*
63221  * Enumerated value for register field ALT_USB_DEV_DCFG_ENDEVOUTNAK
63222  *
63223  * The core does not set NAK after Bulk OUT transfer complete
63224  */
63225 #define ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_DISD 0x0
63226 /*
63227  * Enumerated value for register field ALT_USB_DEV_DCFG_ENDEVOUTNAK
63228  *
63229  * The core sets NAK after Bulk OUT transfer complete
63230  */
63231 #define ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_END 0x1
63232 
63233 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */
63234 #define ALT_USB_DEV_DCFG_ENDEVOUTNAK_LSB 13
63235 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */
63236 #define ALT_USB_DEV_DCFG_ENDEVOUTNAK_MSB 13
63237 /* The width in bits of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */
63238 #define ALT_USB_DEV_DCFG_ENDEVOUTNAK_WIDTH 1
63239 /* The mask used to set the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value. */
63240 #define ALT_USB_DEV_DCFG_ENDEVOUTNAK_SET_MSK 0x00002000
63241 /* The mask used to clear the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value. */
63242 #define ALT_USB_DEV_DCFG_ENDEVOUTNAK_CLR_MSK 0xffffdfff
63243 /* The reset value of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */
63244 #define ALT_USB_DEV_DCFG_ENDEVOUTNAK_RESET 0x0
63245 /* Extracts the ALT_USB_DEV_DCFG_ENDEVOUTNAK field value from a register. */
63246 #define ALT_USB_DEV_DCFG_ENDEVOUTNAK_GET(value) (((value) & 0x00002000) >> 13)
63247 /* Produces a ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value suitable for setting the register. */
63248 #define ALT_USB_DEV_DCFG_ENDEVOUTNAK_SET(value) (((value) << 13) & 0x00002000)
63249 
63250 /*
63251  * Field : xcvrdly
63252  *
63253  * 1'b1: Enable delay between xcvr_sel and txvalid during Device chirp
63254  *
63255  * 1'b0: No delay between xcvr_sel and txvalid during Device chirp
63256  *
63257  * Field Access Macros:
63258  *
63259  */
63260 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_XCVRDLY register field. */
63261 #define ALT_USB_DEV_DCFG_XCVRDLY_LSB 14
63262 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_XCVRDLY register field. */
63263 #define ALT_USB_DEV_DCFG_XCVRDLY_MSB 14
63264 /* The width in bits of the ALT_USB_DEV_DCFG_XCVRDLY register field. */
63265 #define ALT_USB_DEV_DCFG_XCVRDLY_WIDTH 1
63266 /* The mask used to set the ALT_USB_DEV_DCFG_XCVRDLY register field value. */
63267 #define ALT_USB_DEV_DCFG_XCVRDLY_SET_MSK 0x00004000
63268 /* The mask used to clear the ALT_USB_DEV_DCFG_XCVRDLY register field value. */
63269 #define ALT_USB_DEV_DCFG_XCVRDLY_CLR_MSK 0xffffbfff
63270 /* The reset value of the ALT_USB_DEV_DCFG_XCVRDLY register field. */
63271 #define ALT_USB_DEV_DCFG_XCVRDLY_RESET 0x0
63272 /* Extracts the ALT_USB_DEV_DCFG_XCVRDLY field value from a register. */
63273 #define ALT_USB_DEV_DCFG_XCVRDLY_GET(value) (((value) & 0x00004000) >> 14)
63274 /* Produces a ALT_USB_DEV_DCFG_XCVRDLY register field value suitable for setting the register. */
63275 #define ALT_USB_DEV_DCFG_XCVRDLY_SET(value) (((value) << 14) & 0x00004000)
63276 
63277 /*
63278  * Field : erraticintmsk
63279  *
63280  * Erratic Error Interrupt Mask
63281  *
63282  * 1'b1: Mask early suspend interrupt on erratic error
63283  *
63284  * 1'b0: Early suspend interrupt is generated on erratic error
63285  *
63286  * Field Access Macros:
63287  *
63288  */
63289 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_ERRATICINTMSK register field. */
63290 #define ALT_USB_DEV_DCFG_ERRATICINTMSK_LSB 15
63291 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_ERRATICINTMSK register field. */
63292 #define ALT_USB_DEV_DCFG_ERRATICINTMSK_MSB 15
63293 /* The width in bits of the ALT_USB_DEV_DCFG_ERRATICINTMSK register field. */
63294 #define ALT_USB_DEV_DCFG_ERRATICINTMSK_WIDTH 1
63295 /* The mask used to set the ALT_USB_DEV_DCFG_ERRATICINTMSK register field value. */
63296 #define ALT_USB_DEV_DCFG_ERRATICINTMSK_SET_MSK 0x00008000
63297 /* The mask used to clear the ALT_USB_DEV_DCFG_ERRATICINTMSK register field value. */
63298 #define ALT_USB_DEV_DCFG_ERRATICINTMSK_CLR_MSK 0xffff7fff
63299 /* The reset value of the ALT_USB_DEV_DCFG_ERRATICINTMSK register field. */
63300 #define ALT_USB_DEV_DCFG_ERRATICINTMSK_RESET 0x0
63301 /* Extracts the ALT_USB_DEV_DCFG_ERRATICINTMSK field value from a register. */
63302 #define ALT_USB_DEV_DCFG_ERRATICINTMSK_GET(value) (((value) & 0x00008000) >> 15)
63303 /* Produces a ALT_USB_DEV_DCFG_ERRATICINTMSK register field value suitable for setting the register. */
63304 #define ALT_USB_DEV_DCFG_ERRATICINTMSK_SET(value) (((value) << 15) & 0x00008000)
63305 
63306 /*
63307  * Field : descdma
63308  *
63309  * Enable Scatter/gather DMA in device mode (DescDMA).
63310  *
63311  * When the Scatter/Gather DMA option selected during
63312  *
63313  * configuration of the RTL, the application can Set this bit during
63314  *
63315  * initialization to enable the Scatter/Gather DMA operation.
63316  *
63317  * NOTE: This bit must be modified only once after a reset.
63318  *
63319  * The following combinations are available For programming:
63320  *
63321  * GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Slave mode
63322  *
63323  * GAHBCFG.DMAEn=0,DCFG.DescDMA=1 => Invalid
63324  *
63325  * GAHBCFG.DMAEn=1,DCFG.DescDMA=0 => Buffered DMA
63326  *
63327  * mode
63328  *
63329  * GAHBCFG.DMAEn=1,DCFG.DescDMA=1 =>
63330  *
63331  * Scatter/Gather DMA mode
63332  *
63333  * Field Enumeration Values:
63334  *
63335  * Enum | Value | Description
63336  * :--------------------------------|:------|:---------------------------
63337  * ALT_USB_DEV_DCFG_DESCDMA_E_DISD | 0x0 | Disable Scatter gather DMA
63338  * ALT_USB_DEV_DCFG_DESCDMA_E_END | 0x1 | Enable Scatter gather DMA
63339  *
63340  * Field Access Macros:
63341  *
63342  */
63343 /*
63344  * Enumerated value for register field ALT_USB_DEV_DCFG_DESCDMA
63345  *
63346  * Disable Scatter gather DMA
63347  */
63348 #define ALT_USB_DEV_DCFG_DESCDMA_E_DISD 0x0
63349 /*
63350  * Enumerated value for register field ALT_USB_DEV_DCFG_DESCDMA
63351  *
63352  * Enable Scatter gather DMA
63353  */
63354 #define ALT_USB_DEV_DCFG_DESCDMA_E_END 0x1
63355 
63356 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DESCDMA register field. */
63357 #define ALT_USB_DEV_DCFG_DESCDMA_LSB 23
63358 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DESCDMA register field. */
63359 #define ALT_USB_DEV_DCFG_DESCDMA_MSB 23
63360 /* The width in bits of the ALT_USB_DEV_DCFG_DESCDMA register field. */
63361 #define ALT_USB_DEV_DCFG_DESCDMA_WIDTH 1
63362 /* The mask used to set the ALT_USB_DEV_DCFG_DESCDMA register field value. */
63363 #define ALT_USB_DEV_DCFG_DESCDMA_SET_MSK 0x00800000
63364 /* The mask used to clear the ALT_USB_DEV_DCFG_DESCDMA register field value. */
63365 #define ALT_USB_DEV_DCFG_DESCDMA_CLR_MSK 0xff7fffff
63366 /* The reset value of the ALT_USB_DEV_DCFG_DESCDMA register field. */
63367 #define ALT_USB_DEV_DCFG_DESCDMA_RESET 0x0
63368 /* Extracts the ALT_USB_DEV_DCFG_DESCDMA field value from a register. */
63369 #define ALT_USB_DEV_DCFG_DESCDMA_GET(value) (((value) & 0x00800000) >> 23)
63370 /* Produces a ALT_USB_DEV_DCFG_DESCDMA register field value suitable for setting the register. */
63371 #define ALT_USB_DEV_DCFG_DESCDMA_SET(value) (((value) << 23) & 0x00800000)
63372 
63373 /*
63374  * Field : perschintvl
63375  *
63376  * Periodic Scheduling Interval (PerSchIntvl)
63377  *
63378  * PerSchIntvl must be programmed only For Scatter/Gather DMA
63379  *
63380  * mode.
63381  *
63382  * Description: This field specifies the amount of time the Internal
63383  *
63384  * DMA engine must allocate For fetching periodic IN endpoint data.
63385  *
63386  * Based on the number of periodic endpoints, this value must be
63387  *
63388  * specified as 25,50 or 75% of (micro)frame.
63389  *
63390  * When any periodic endpoints are active, the internal DMA
63391  *
63392  * engine allocates the specified amount of time in fetching
63393  *
63394  * periodic IN endpoint data .
63395  *
63396  * When no periodic endpoints are active, Then the internal
63397  *
63398  * DMA engine services non-periodic endpoints, ignoring this
63399  *
63400  * field.
63401  *
63402  * After the specified time within a (micro)frame, the DMA switches
63403  *
63404  * to fetching For non-periodic endpoints.
63405  *
63406  * 2'b00: 25% of (micro)frame.
63407  *
63408  * 2'b01: 50% of (micro)frame.
63409  *
63410  * 2'b10: 75% of (micro)frame.
63411  *
63412  * 2'b11: Reserved.
63413  *
63414  * Reset: 2'b00
63415  *
63416  * Field Enumeration Values:
63417  *
63418  * Enum | Value | Description
63419  * :------------------------------------|:------|:--------------------
63420  * ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF25 | 0x0 | 25% of (micro)frame
63421  * ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF50 | 0x1 | 50% of (micro)frame
63422  * ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF75 | 0x2 | 75% of (micro)frame
63423  * ALT_USB_DEV_DCFG_PERSCHINTVL_E_RSVD | 0x3 | Reserved
63424  *
63425  * Field Access Macros:
63426  *
63427  */
63428 /*
63429  * Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL
63430  *
63431  * 25% of (micro)frame
63432  */
63433 #define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF25 0x0
63434 /*
63435  * Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL
63436  *
63437  * 50% of (micro)frame
63438  */
63439 #define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF50 0x1
63440 /*
63441  * Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL
63442  *
63443  * 75% of (micro)frame
63444  */
63445 #define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF75 0x2
63446 /*
63447  * Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL
63448  *
63449  * Reserved
63450  */
63451 #define ALT_USB_DEV_DCFG_PERSCHINTVL_E_RSVD 0x3
63452 
63453 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */
63454 #define ALT_USB_DEV_DCFG_PERSCHINTVL_LSB 24
63455 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */
63456 #define ALT_USB_DEV_DCFG_PERSCHINTVL_MSB 25
63457 /* The width in bits of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */
63458 #define ALT_USB_DEV_DCFG_PERSCHINTVL_WIDTH 2
63459 /* The mask used to set the ALT_USB_DEV_DCFG_PERSCHINTVL register field value. */
63460 #define ALT_USB_DEV_DCFG_PERSCHINTVL_SET_MSK 0x03000000
63461 /* The mask used to clear the ALT_USB_DEV_DCFG_PERSCHINTVL register field value. */
63462 #define ALT_USB_DEV_DCFG_PERSCHINTVL_CLR_MSK 0xfcffffff
63463 /* The reset value of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */
63464 #define ALT_USB_DEV_DCFG_PERSCHINTVL_RESET 0x0
63465 /* Extracts the ALT_USB_DEV_DCFG_PERSCHINTVL field value from a register. */
63466 #define ALT_USB_DEV_DCFG_PERSCHINTVL_GET(value) (((value) & 0x03000000) >> 24)
63467 /* Produces a ALT_USB_DEV_DCFG_PERSCHINTVL register field value suitable for setting the register. */
63468 #define ALT_USB_DEV_DCFG_PERSCHINTVL_SET(value) (((value) << 24) & 0x03000000)
63469 
63470 /*
63471  * Field : resvalid
63472  *
63473  * Resume Validation Period (ResValid)
63474  *
63475  * This field is effective only when DCFG.Ena32KHzSusp is set.
63476  *
63477  * It will control the resume period when the core resumes from
63478  *
63479  * suspend. The core counts for "ResValid" number of clock cycles
63480  *
63481  * to detect a valid resume when this is set
63482  *
63483  * Field Access Macros:
63484  *
63485  */
63486 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_RESVALID register field. */
63487 #define ALT_USB_DEV_DCFG_RESVALID_LSB 26
63488 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_RESVALID register field. */
63489 #define ALT_USB_DEV_DCFG_RESVALID_MSB 31
63490 /* The width in bits of the ALT_USB_DEV_DCFG_RESVALID register field. */
63491 #define ALT_USB_DEV_DCFG_RESVALID_WIDTH 6
63492 /* The mask used to set the ALT_USB_DEV_DCFG_RESVALID register field value. */
63493 #define ALT_USB_DEV_DCFG_RESVALID_SET_MSK 0xfc000000
63494 /* The mask used to clear the ALT_USB_DEV_DCFG_RESVALID register field value. */
63495 #define ALT_USB_DEV_DCFG_RESVALID_CLR_MSK 0x03ffffff
63496 /* The reset value of the ALT_USB_DEV_DCFG_RESVALID register field. */
63497 #define ALT_USB_DEV_DCFG_RESVALID_RESET 0x2
63498 /* Extracts the ALT_USB_DEV_DCFG_RESVALID field value from a register. */
63499 #define ALT_USB_DEV_DCFG_RESVALID_GET(value) (((value) & 0xfc000000) >> 26)
63500 /* Produces a ALT_USB_DEV_DCFG_RESVALID register field value suitable for setting the register. */
63501 #define ALT_USB_DEV_DCFG_RESVALID_SET(value) (((value) << 26) & 0xfc000000)
63502 
63503 #ifndef __ASSEMBLY__
63504 /*
63505  * WARNING: The C register and register group struct declarations are provided for
63506  * convenience and illustrative purposes. They should, however, be used with
63507  * caution as the C language standard provides no guarantees about the alignment or
63508  * atomicity of device memory accesses. The recommended practice for writing
63509  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63510  * alt_write_word() functions.
63511  *
63512  * The struct declaration for register ALT_USB_DEV_DCFG.
63513  */
63514 struct ALT_USB_DEV_DCFG_s
63515 {
63516  uint32_t devspd : 2; /* ALT_USB_DEV_DCFG_DEVSPD */
63517  uint32_t nzstsouthshk : 1; /* ALT_USB_DEV_DCFG_NZSTSOUTHSHK */
63518  uint32_t ena32khzsusp : 1; /* ALT_USB_DEV_DCFG_ENA32KHZSUSP */
63519  uint32_t devaddr : 7; /* ALT_USB_DEV_DCFG_DEVADDR */
63520  uint32_t perfrint : 2; /* ALT_USB_DEV_DCFG_PERFRINT */
63521  uint32_t endevoutnak : 1; /* ALT_USB_DEV_DCFG_ENDEVOUTNAK */
63522  uint32_t xcvrdly : 1; /* ALT_USB_DEV_DCFG_XCVRDLY */
63523  uint32_t erraticintmsk : 1; /* ALT_USB_DEV_DCFG_ERRATICINTMSK */
63524  uint32_t : 7; /* *UNDEFINED* */
63525  uint32_t descdma : 1; /* ALT_USB_DEV_DCFG_DESCDMA */
63526  uint32_t perschintvl : 2; /* ALT_USB_DEV_DCFG_PERSCHINTVL */
63527  uint32_t resvalid : 6; /* ALT_USB_DEV_DCFG_RESVALID */
63528 };
63529 
63530 /* The typedef declaration for register ALT_USB_DEV_DCFG. */
63531 typedef volatile struct ALT_USB_DEV_DCFG_s ALT_USB_DEV_DCFG_t;
63532 #endif /* __ASSEMBLY__ */
63533 
63534 /* The reset value of the ALT_USB_DEV_DCFG register. */
63535 #define ALT_USB_DEV_DCFG_RESET 0x08200000
63536 /* The byte offset of the ALT_USB_DEV_DCFG register from the beginning of the component. */
63537 #define ALT_USB_DEV_DCFG_OFST 0x0
63538 /* The address of the ALT_USB_DEV_DCFG register. */
63539 #define ALT_USB_DEV_DCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DCFG_OFST))
63540 
63541 /*
63542  * Register : dctl
63543  *
63544  * Device Control Register
63545  *
63546  * Register Layout
63547  *
63548  * Bits | Access | Reset | Description
63549  * :--------|:-------|:------|:------------------------------
63550  * [0] | RW | 0x0 | ALT_USB_DEV_DCTL_RMTWKUPSIG
63551  * [1] | RW | 0x1 | ALT_USB_DEV_DCTL_SFTDISCON
63552  * [2] | R | 0x0 | ALT_USB_DEV_DCTL_GNPINNAKSTS
63553  * [3] | R | 0x0 | ALT_USB_DEV_DCTL_GOUTNAKSTS
63554  * [6:4] | RW | 0x0 | ALT_USB_DEV_DCTL_TSTCTL
63555  * [7] | W | 0x0 | ALT_USB_DEV_DCTL_SGNPINNAK
63556  * [8] | W | 0x0 | ALT_USB_DEV_DCTL_CGNPINNAK
63557  * [9] | W | 0x0 | ALT_USB_DEV_DCTL_SGOUTNAK
63558  * [10] | W | 0x0 | ALT_USB_DEV_DCTL_CGOUTNAK
63559  * [11] | RW | 0x0 | ALT_USB_DEV_DCTL_PWRONPRGDONE
63560  * [12] | ??? | 0x0 | *UNDEFINED*
63561  * [14:13] | RW | 0x0 | ALT_USB_DEV_DCTL_GMC
63562  * [15] | RW | 0x0 | ALT_USB_DEV_DCTL_IGNRFRMNUM
63563  * [16] | RW | 0x0 | ALT_USB_DEV_DCTL_NAKONBBLE
63564  * [17] | RW | 0x0 | ALT_USB_DEV_DCTL_ENCONTONBNA
63565  * [31:18] | ??? | 0x0 | *UNDEFINED*
63566  *
63567  */
63568 /*
63569  * Field : rmtwkupsig
63570  *
63571  * Remote Wakeup Signaling (RmtWkUpSig)
63572  *
63573  * When the application sets this bit, the core initiates remote
63574  *
63575  * signaling to wake up the USB host. The application must Set this
63576  *
63577  * bit to instruct the core to exit the Suspend state. As specified in
63578  *
63579  * the USB 2.0 specification, the application must clear this bit
63580  *
63581  * 1-15 ms after setting it.
63582  *
63583  * Remote Wakeup Signaling (RmtWkUpSig) When LPM is enabled,
63584  *
63585  * In L1 state the behavior of this bit is as follows:
63586  *
63587  * When the application sets this bit, the core initiates L1 remote signaling to
63588  *
63589  * wake up the USB host. The application must set this bit to instruct the core
63590  *
63591  * to exit the Sleep state. As specified in the LPM specification,
63592  *
63593  * the hardware will automatically clear this bit after a time of 50 micro sec
63594  * (TL1DevDrvResume)
63595  *
63596  * after set by application. Application should not set this bit when GLPMCFG
63597  * bRemoteWake
63598  *
63599  * from the previous LPM transaction was zero.
63600  *
63601  * Field Enumeration Values:
63602  *
63603  * Enum | Value | Description
63604  * :-------------------------------------|:------|:----------------------
63605  * ALT_USB_DEV_DCTL_RMTWKUPSIG_E_NOEXIT | 0x0 | No exit suspend state
63606  * ALT_USB_DEV_DCTL_RMTWKUPSIG_E_EXIT | 0x1 | Exit Suspend State
63607  *
63608  * Field Access Macros:
63609  *
63610  */
63611 /*
63612  * Enumerated value for register field ALT_USB_DEV_DCTL_RMTWKUPSIG
63613  *
63614  * No exit suspend state
63615  */
63616 #define ALT_USB_DEV_DCTL_RMTWKUPSIG_E_NOEXIT 0x0
63617 /*
63618  * Enumerated value for register field ALT_USB_DEV_DCTL_RMTWKUPSIG
63619  *
63620  * Exit Suspend State
63621  */
63622 #define ALT_USB_DEV_DCTL_RMTWKUPSIG_E_EXIT 0x1
63623 
63624 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */
63625 #define ALT_USB_DEV_DCTL_RMTWKUPSIG_LSB 0
63626 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */
63627 #define ALT_USB_DEV_DCTL_RMTWKUPSIG_MSB 0
63628 /* The width in bits of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */
63629 #define ALT_USB_DEV_DCTL_RMTWKUPSIG_WIDTH 1
63630 /* The mask used to set the ALT_USB_DEV_DCTL_RMTWKUPSIG register field value. */
63631 #define ALT_USB_DEV_DCTL_RMTWKUPSIG_SET_MSK 0x00000001
63632 /* The mask used to clear the ALT_USB_DEV_DCTL_RMTWKUPSIG register field value. */
63633 #define ALT_USB_DEV_DCTL_RMTWKUPSIG_CLR_MSK 0xfffffffe
63634 /* The reset value of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */
63635 #define ALT_USB_DEV_DCTL_RMTWKUPSIG_RESET 0x0
63636 /* Extracts the ALT_USB_DEV_DCTL_RMTWKUPSIG field value from a register. */
63637 #define ALT_USB_DEV_DCTL_RMTWKUPSIG_GET(value) (((value) & 0x00000001) >> 0)
63638 /* Produces a ALT_USB_DEV_DCTL_RMTWKUPSIG register field value suitable for setting the register. */
63639 #define ALT_USB_DEV_DCTL_RMTWKUPSIG_SET(value) (((value) << 0) & 0x00000001)
63640 
63641 /*
63642  * Field : sftdiscon
63643  *
63644  * Soft Disconnect (SftDiscon)
63645  *
63646  * The application uses this bit to signal the DWC_otg core to do a
63647  *
63648  * soft disconnect. As long as this bit is Set, the host does not see
63649  *
63650  * that the device is connected, and the device does not receive
63651  *
63652  * signals on the USB. The core stays in the disconnected state
63653  *
63654  * until the application clears this bit.
63655  *
63656  * The minimum duration For which the core must keep this bit Set
63657  *
63658  * is specified in Table 5-46.
63659  *
63660  * 1'b0: Normal operation. When this bit is cleared after a soft
63661  *
63662  * disconnect, the core drives the phy_opmode_o signal on the
63663  *
63664  * UTMI+ to 2'b00, which generates a device connect event to
63665  *
63666  * the USB host. When the device is reconnected, the USB host
63667  *
63668  * restarts device enumeration.
63669  *
63670  * 1'b1: The core drives the phy_opmode_o signal on the
63671  *
63672  * UTMI+ to 2'b01, which generates a device disconnect event
63673  *
63674  * to the USB host.
63675  *
63676  * Note: This bit can be also used for ULPI/FS Serial interfaces.
63677  *
63678  * Note: This bit is not impacted by a soft reset.
63679  *
63680  * Field Enumeration Values:
63681  *
63682  * Enum | Value | Description
63683  * :------------------------------------------|:------|:-----------------------------------------------
63684  * ALT_USB_DEV_DCTL_SFTDISCON_E_NODISCONNECT | 0x0 | Normal operation
63685  * ALT_USB_DEV_DCTL_SFTDISCON_E_DISCONNECT | 0x1 | The core drives the phy_opmode_o signal on the
63686  * : | | ULPI
63687  *
63688  * Field Access Macros:
63689  *
63690  */
63691 /*
63692  * Enumerated value for register field ALT_USB_DEV_DCTL_SFTDISCON
63693  *
63694  * Normal operation
63695  */
63696 #define ALT_USB_DEV_DCTL_SFTDISCON_E_NODISCONNECT 0x0
63697 /*
63698  * Enumerated value for register field ALT_USB_DEV_DCTL_SFTDISCON
63699  *
63700  * The core drives the phy_opmode_o signal on the ULPI
63701  */
63702 #define ALT_USB_DEV_DCTL_SFTDISCON_E_DISCONNECT 0x1
63703 
63704 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_SFTDISCON register field. */
63705 #define ALT_USB_DEV_DCTL_SFTDISCON_LSB 1
63706 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_SFTDISCON register field. */
63707 #define ALT_USB_DEV_DCTL_SFTDISCON_MSB 1
63708 /* The width in bits of the ALT_USB_DEV_DCTL_SFTDISCON register field. */
63709 #define ALT_USB_DEV_DCTL_SFTDISCON_WIDTH 1
63710 /* The mask used to set the ALT_USB_DEV_DCTL_SFTDISCON register field value. */
63711 #define ALT_USB_DEV_DCTL_SFTDISCON_SET_MSK 0x00000002
63712 /* The mask used to clear the ALT_USB_DEV_DCTL_SFTDISCON register field value. */
63713 #define ALT_USB_DEV_DCTL_SFTDISCON_CLR_MSK 0xfffffffd
63714 /* The reset value of the ALT_USB_DEV_DCTL_SFTDISCON register field. */
63715 #define ALT_USB_DEV_DCTL_SFTDISCON_RESET 0x1
63716 /* Extracts the ALT_USB_DEV_DCTL_SFTDISCON field value from a register. */
63717 #define ALT_USB_DEV_DCTL_SFTDISCON_GET(value) (((value) & 0x00000002) >> 1)
63718 /* Produces a ALT_USB_DEV_DCTL_SFTDISCON register field value suitable for setting the register. */
63719 #define ALT_USB_DEV_DCTL_SFTDISCON_SET(value) (((value) << 1) & 0x00000002)
63720 
63721 /*
63722  * Field : gnpinnaksts
63723  *
63724  * Global Non-periodic IN NAK Status (GNPINNakSts)
63725  *
63726  * 1'b0: A handshake is sent out based on the data availability
63727  *
63728  * in the transmit FIFO.
63729  *
63730  * 1'b1: A NAK handshake is sent out on all non-periodic IN
63731  *
63732  * endpoints, irrespective of the data availability in the transmit
63733  *
63734  * FIFO.
63735  *
63736  * Field Enumeration Values:
63737  *
63738  * Enum | Value | Description
63739  * :-------------------------------------|:------|:------------------------------------------------
63740  * ALT_USB_DEV_DCTL_GNPINNAKSTS_E_INACT | 0x0 | A handshake is sent out based on the data
63741  * : | | availability in the transmit FIFO
63742  * ALT_USB_DEV_DCTL_GNPINNAKSTS_E_ACT | 0x1 | A NAK handshake is sent out on all non-periodic
63743  * : | | IN endpoints, irrespective of the data
63744  * : | | availability in the transmit FIFO.
63745  *
63746  * Field Access Macros:
63747  *
63748  */
63749 /*
63750  * Enumerated value for register field ALT_USB_DEV_DCTL_GNPINNAKSTS
63751  *
63752  * A handshake is sent out based on the data availability in the transmit FIFO
63753  */
63754 #define ALT_USB_DEV_DCTL_GNPINNAKSTS_E_INACT 0x0
63755 /*
63756  * Enumerated value for register field ALT_USB_DEV_DCTL_GNPINNAKSTS
63757  *
63758  * A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of
63759  * the data availability in the transmit FIFO.
63760  */
63761 #define ALT_USB_DEV_DCTL_GNPINNAKSTS_E_ACT 0x1
63762 
63763 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */
63764 #define ALT_USB_DEV_DCTL_GNPINNAKSTS_LSB 2
63765 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */
63766 #define ALT_USB_DEV_DCTL_GNPINNAKSTS_MSB 2
63767 /* The width in bits of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */
63768 #define ALT_USB_DEV_DCTL_GNPINNAKSTS_WIDTH 1
63769 /* The mask used to set the ALT_USB_DEV_DCTL_GNPINNAKSTS register field value. */
63770 #define ALT_USB_DEV_DCTL_GNPINNAKSTS_SET_MSK 0x00000004
63771 /* The mask used to clear the ALT_USB_DEV_DCTL_GNPINNAKSTS register field value. */
63772 #define ALT_USB_DEV_DCTL_GNPINNAKSTS_CLR_MSK 0xfffffffb
63773 /* The reset value of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */
63774 #define ALT_USB_DEV_DCTL_GNPINNAKSTS_RESET 0x0
63775 /* Extracts the ALT_USB_DEV_DCTL_GNPINNAKSTS field value from a register. */
63776 #define ALT_USB_DEV_DCTL_GNPINNAKSTS_GET(value) (((value) & 0x00000004) >> 2)
63777 /* Produces a ALT_USB_DEV_DCTL_GNPINNAKSTS register field value suitable for setting the register. */
63778 #define ALT_USB_DEV_DCTL_GNPINNAKSTS_SET(value) (((value) << 2) & 0x00000004)
63779 
63780 /*
63781  * Field : goutnaksts
63782  *
63783  * Global OUT NAK Status (GOUTNakSts)
63784  *
63785  * 1'b0: A handshake is sent based on the FIFO Status and the
63786  *
63787  * NAK and STALL bit settings.
63788  *
63789  * 1'b1: No data is written to the RxFIFO, irrespective of space
63790  *
63791  * availability. Sends a NAK handshake on all packets, except
63792  *
63793  * on SETUP transactions. All isochronous OUT packets are
63794  *
63795  * dropped.
63796  *
63797  * Field Enumeration Values:
63798  *
63799  * Enum | Value | Description
63800  * :------------------------------------|:------|:-------------------------------------------------
63801  * ALT_USB_DEV_DCTL_GOUTNAKSTS_E_INACT | 0x0 | A handshake is sent based on the FIFO Status and
63802  * : | | the NAK and STALL bit settings.
63803  * ALT_USB_DEV_DCTL_GOUTNAKSTS_E_ACT | 0x1 | No data is written to the RxFIFO, irrespective
63804  * : | | of space availability. Sends a NAK handshake on
63805  * : | | all packets, except on SETUP transactions. All
63806  * : | | isochronous OUT packets are dropped.
63807  *
63808  * Field Access Macros:
63809  *
63810  */
63811 /*
63812  * Enumerated value for register field ALT_USB_DEV_DCTL_GOUTNAKSTS
63813  *
63814  * A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.
63815  */
63816 #define ALT_USB_DEV_DCTL_GOUTNAKSTS_E_INACT 0x0
63817 /*
63818  * Enumerated value for register field ALT_USB_DEV_DCTL_GOUTNAKSTS
63819  *
63820  * No data is written to the RxFIFO, irrespective of space availability. Sends a
63821  * NAK handshake on all packets, except on SETUP transactions. All isochronous OUT
63822  * packets are dropped.
63823  */
63824 #define ALT_USB_DEV_DCTL_GOUTNAKSTS_E_ACT 0x1
63825 
63826 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */
63827 #define ALT_USB_DEV_DCTL_GOUTNAKSTS_LSB 3
63828 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */
63829 #define ALT_USB_DEV_DCTL_GOUTNAKSTS_MSB 3
63830 /* The width in bits of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */
63831 #define ALT_USB_DEV_DCTL_GOUTNAKSTS_WIDTH 1
63832 /* The mask used to set the ALT_USB_DEV_DCTL_GOUTNAKSTS register field value. */
63833 #define ALT_USB_DEV_DCTL_GOUTNAKSTS_SET_MSK 0x00000008
63834 /* The mask used to clear the ALT_USB_DEV_DCTL_GOUTNAKSTS register field value. */
63835 #define ALT_USB_DEV_DCTL_GOUTNAKSTS_CLR_MSK 0xfffffff7
63836 /* The reset value of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */
63837 #define ALT_USB_DEV_DCTL_GOUTNAKSTS_RESET 0x0
63838 /* Extracts the ALT_USB_DEV_DCTL_GOUTNAKSTS field value from a register. */
63839 #define ALT_USB_DEV_DCTL_GOUTNAKSTS_GET(value) (((value) & 0x00000008) >> 3)
63840 /* Produces a ALT_USB_DEV_DCTL_GOUTNAKSTS register field value suitable for setting the register. */
63841 #define ALT_USB_DEV_DCTL_GOUTNAKSTS_SET(value) (((value) << 3) & 0x00000008)
63842 
63843 /*
63844  * Field : tstctl
63845  *
63846  * Test Control (TstCtl)
63847  *
63848  * 3'b000: Test mode disabled
63849  *
63850  * 3'b001: Test_J mode
63851  *
63852  * 3'b010: Test_K mode
63853  *
63854  * 3'b011: Test_SE0_NAK mode
63855  *
63856  * 3'b100: Test_Packet mode
63857  *
63858  * 3'b101: Test_Force_Enable
63859  *
63860  * Others: Reserved
63861  *
63862  * Field Enumeration Values:
63863  *
63864  * Enum | Value | Description
63865  * :---------------------------------|:------|:-------------------
63866  * ALT_USB_DEV_DCTL_TSTCTL_E_DISD | 0x0 | Test mode disabled
63867  * ALT_USB_DEV_DCTL_TSTCTL_E_TESTJ | 0x1 | Test_J mode
63868  * ALT_USB_DEV_DCTL_TSTCTL_E_TESTK | 0x2 | Test_K mode
63869  * ALT_USB_DEV_DCTL_TSTCTL_E_TESTSN | 0x3 | Test_SE0_NAK mode
63870  * ALT_USB_DEV_DCTL_TSTCTL_E_TESTPM | 0x4 | Test_Packet mode
63871  * ALT_USB_DEV_DCTL_TSTCTL_E_TESTFE | 0x5 | Test_force_Enable
63872  *
63873  * Field Access Macros:
63874  *
63875  */
63876 /*
63877  * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
63878  *
63879  * Test mode disabled
63880  */
63881 #define ALT_USB_DEV_DCTL_TSTCTL_E_DISD 0x0
63882 /*
63883  * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
63884  *
63885  * Test_J mode
63886  */
63887 #define ALT_USB_DEV_DCTL_TSTCTL_E_TESTJ 0x1
63888 /*
63889  * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
63890  *
63891  * Test_K mode
63892  */
63893 #define ALT_USB_DEV_DCTL_TSTCTL_E_TESTK 0x2
63894 /*
63895  * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
63896  *
63897  * Test_SE0_NAK mode
63898  */
63899 #define ALT_USB_DEV_DCTL_TSTCTL_E_TESTSN 0x3
63900 /*
63901  * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
63902  *
63903  * Test_Packet mode
63904  */
63905 #define ALT_USB_DEV_DCTL_TSTCTL_E_TESTPM 0x4
63906 /*
63907  * Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
63908  *
63909  * Test_force_Enable
63910  */
63911 #define ALT_USB_DEV_DCTL_TSTCTL_E_TESTFE 0x5
63912 
63913 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_TSTCTL register field. */
63914 #define ALT_USB_DEV_DCTL_TSTCTL_LSB 4
63915 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_TSTCTL register field. */
63916 #define ALT_USB_DEV_DCTL_TSTCTL_MSB 6
63917 /* The width in bits of the ALT_USB_DEV_DCTL_TSTCTL register field. */
63918 #define ALT_USB_DEV_DCTL_TSTCTL_WIDTH 3
63919 /* The mask used to set the ALT_USB_DEV_DCTL_TSTCTL register field value. */
63920 #define ALT_USB_DEV_DCTL_TSTCTL_SET_MSK 0x00000070
63921 /* The mask used to clear the ALT_USB_DEV_DCTL_TSTCTL register field value. */
63922 #define ALT_USB_DEV_DCTL_TSTCTL_CLR_MSK 0xffffff8f
63923 /* The reset value of the ALT_USB_DEV_DCTL_TSTCTL register field. */
63924 #define ALT_USB_DEV_DCTL_TSTCTL_RESET 0x0
63925 /* Extracts the ALT_USB_DEV_DCTL_TSTCTL field value from a register. */
63926 #define ALT_USB_DEV_DCTL_TSTCTL_GET(value) (((value) & 0x00000070) >> 4)
63927 /* Produces a ALT_USB_DEV_DCTL_TSTCTL register field value suitable for setting the register. */
63928 #define ALT_USB_DEV_DCTL_TSTCTL_SET(value) (((value) << 4) & 0x00000070)
63929 
63930 /*
63931  * Field : sgnpinnak
63932  *
63933  * Set Global Non-periodic IN NAK (SGNPInNak)
63934  *
63935  * A write to this field sets the Global Non-periodic IN NAK.The
63936  *
63937  * application uses this bit to send a NAK handshake on all nonperiodic
63938  *
63939  * IN endpoints. The core can also Set this bit when a
63940  *
63941  * timeout condition is detected on a non-periodic endpoint in
63942  *
63943  * shared FIFO operation.
63944  *
63945  * The application must Set this bit only after making sure that the
63946  *
63947  * Global IN NAK Effective bit in the Core Interrupt Register
63948  *
63949  * (GINTSTS.GINNakEff) is cleared
63950  *
63951  * Field Enumeration Values:
63952  *
63953  * Enum | Value | Description
63954  * :----------------------------------|:------|:-----------------------------------
63955  * ALT_USB_DEV_DCTL_SGNPINNAK_E_DISD | 0x0 | Disable Global Non-periodic IN NAK
63956  * ALT_USB_DEV_DCTL_SGNPINNAK_E_END | 0x1 | Global Non-periodic IN NAK
63957  *
63958  * Field Access Macros:
63959  *
63960  */
63961 /*
63962  * Enumerated value for register field ALT_USB_DEV_DCTL_SGNPINNAK
63963  *
63964  * Disable Global Non-periodic IN NAK
63965  */
63966 #define ALT_USB_DEV_DCTL_SGNPINNAK_E_DISD 0x0
63967 /*
63968  * Enumerated value for register field ALT_USB_DEV_DCTL_SGNPINNAK
63969  *
63970  * Global Non-periodic IN NAK
63971  */
63972 #define ALT_USB_DEV_DCTL_SGNPINNAK_E_END 0x1
63973 
63974 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */
63975 #define ALT_USB_DEV_DCTL_SGNPINNAK_LSB 7
63976 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */
63977 #define ALT_USB_DEV_DCTL_SGNPINNAK_MSB 7
63978 /* The width in bits of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */
63979 #define ALT_USB_DEV_DCTL_SGNPINNAK_WIDTH 1
63980 /* The mask used to set the ALT_USB_DEV_DCTL_SGNPINNAK register field value. */
63981 #define ALT_USB_DEV_DCTL_SGNPINNAK_SET_MSK 0x00000080
63982 /* The mask used to clear the ALT_USB_DEV_DCTL_SGNPINNAK register field value. */
63983 #define ALT_USB_DEV_DCTL_SGNPINNAK_CLR_MSK 0xffffff7f
63984 /* The reset value of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */
63985 #define ALT_USB_DEV_DCTL_SGNPINNAK_RESET 0x0
63986 /* Extracts the ALT_USB_DEV_DCTL_SGNPINNAK field value from a register. */
63987 #define ALT_USB_DEV_DCTL_SGNPINNAK_GET(value) (((value) & 0x00000080) >> 7)
63988 /* Produces a ALT_USB_DEV_DCTL_SGNPINNAK register field value suitable for setting the register. */
63989 #define ALT_USB_DEV_DCTL_SGNPINNAK_SET(value) (((value) << 7) & 0x00000080)
63990 
63991 /*
63992  * Field : cgnpinnak
63993  *
63994  * Clear Global Non-periodic IN NAK (CGNPInNak)
63995  *
63996  * A write to this field clears the Global Non-periodic IN NAK.
63997  *
63998  * Field Enumeration Values:
63999  *
64000  * Enum | Value | Description
64001  * :---------------------------------|:------|:-----------------------------------
64002  * ALT_USB_DEV_DCTL_CGNPINNAK_E_DIS | 0x0 | Disable Global Non-periodic IN NAK
64003  * ALT_USB_DEV_DCTL_CGNPINNAK_E_EN | 0x1 | Clear Global Non-periodic IN NAK
64004  *
64005  * Field Access Macros:
64006  *
64007  */
64008 /*
64009  * Enumerated value for register field ALT_USB_DEV_DCTL_CGNPINNAK
64010  *
64011  * Disable Global Non-periodic IN NAK
64012  */
64013 #define ALT_USB_DEV_DCTL_CGNPINNAK_E_DIS 0x0
64014 /*
64015  * Enumerated value for register field ALT_USB_DEV_DCTL_CGNPINNAK
64016  *
64017  * Clear Global Non-periodic IN NAK
64018  */
64019 #define ALT_USB_DEV_DCTL_CGNPINNAK_E_EN 0x1
64020 
64021 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */
64022 #define ALT_USB_DEV_DCTL_CGNPINNAK_LSB 8
64023 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */
64024 #define ALT_USB_DEV_DCTL_CGNPINNAK_MSB 8
64025 /* The width in bits of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */
64026 #define ALT_USB_DEV_DCTL_CGNPINNAK_WIDTH 1
64027 /* The mask used to set the ALT_USB_DEV_DCTL_CGNPINNAK register field value. */
64028 #define ALT_USB_DEV_DCTL_CGNPINNAK_SET_MSK 0x00000100
64029 /* The mask used to clear the ALT_USB_DEV_DCTL_CGNPINNAK register field value. */
64030 #define ALT_USB_DEV_DCTL_CGNPINNAK_CLR_MSK 0xfffffeff
64031 /* The reset value of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */
64032 #define ALT_USB_DEV_DCTL_CGNPINNAK_RESET 0x0
64033 /* Extracts the ALT_USB_DEV_DCTL_CGNPINNAK field value from a register. */
64034 #define ALT_USB_DEV_DCTL_CGNPINNAK_GET(value) (((value) & 0x00000100) >> 8)
64035 /* Produces a ALT_USB_DEV_DCTL_CGNPINNAK register field value suitable for setting the register. */
64036 #define ALT_USB_DEV_DCTL_CGNPINNAK_SET(value) (((value) << 8) & 0x00000100)
64037 
64038 /*
64039  * Field : sgoutnak
64040  *
64041  * Set Global OUT NAK (SGOUTNak)
64042  *
64043  * A write to this field sets the Global OUT NAK.
64044  *
64045  * The application uses this bit to send a NAK handshake on all
64046  *
64047  * OUT endpoints.
64048  *
64049  * The application must Set the this bit only after making sure that
64050  *
64051  * the Global OUT NAK Effective bit in the Core Interrupt Register
64052  *
64053  * (GINTSTS.GOUTNakEff) is cleared.
64054  *
64055  * Field Enumeration Values:
64056  *
64057  * Enum | Value | Description
64058  * :---------------------------------|:------|:-----------------------
64059  * ALT_USB_DEV_DCTL_SGOUTNAK_E_DISD | 0x0 | Disable Global OUT NAK
64060  * ALT_USB_DEV_DCTL_SGOUTNAK_E_END | 0x1 | Global OUT NAK
64061  *
64062  * Field Access Macros:
64063  *
64064  */
64065 /*
64066  * Enumerated value for register field ALT_USB_DEV_DCTL_SGOUTNAK
64067  *
64068  * Disable Global OUT NAK
64069  */
64070 #define ALT_USB_DEV_DCTL_SGOUTNAK_E_DISD 0x0
64071 /*
64072  * Enumerated value for register field ALT_USB_DEV_DCTL_SGOUTNAK
64073  *
64074  * Global OUT NAK
64075  */
64076 #define ALT_USB_DEV_DCTL_SGOUTNAK_E_END 0x1
64077 
64078 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */
64079 #define ALT_USB_DEV_DCTL_SGOUTNAK_LSB 9
64080 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */
64081 #define ALT_USB_DEV_DCTL_SGOUTNAK_MSB 9
64082 /* The width in bits of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */
64083 #define ALT_USB_DEV_DCTL_SGOUTNAK_WIDTH 1
64084 /* The mask used to set the ALT_USB_DEV_DCTL_SGOUTNAK register field value. */
64085 #define ALT_USB_DEV_DCTL_SGOUTNAK_SET_MSK 0x00000200
64086 /* The mask used to clear the ALT_USB_DEV_DCTL_SGOUTNAK register field value. */
64087 #define ALT_USB_DEV_DCTL_SGOUTNAK_CLR_MSK 0xfffffdff
64088 /* The reset value of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */
64089 #define ALT_USB_DEV_DCTL_SGOUTNAK_RESET 0x0
64090 /* Extracts the ALT_USB_DEV_DCTL_SGOUTNAK field value from a register. */
64091 #define ALT_USB_DEV_DCTL_SGOUTNAK_GET(value) (((value) & 0x00000200) >> 9)
64092 /* Produces a ALT_USB_DEV_DCTL_SGOUTNAK register field value suitable for setting the register. */
64093 #define ALT_USB_DEV_DCTL_SGOUTNAK_SET(value) (((value) << 9) & 0x00000200)
64094 
64095 /*
64096  * Field : cgoutnak
64097  *
64098  * Clear Global OUT NAK (CGOUTNak)
64099  *
64100  * A write to this field clears the Global OUT NAK.
64101  *
64102  * Field Enumeration Values:
64103  *
64104  * Enum | Value | Description
64105  * :---------------------------------|:------|:-----------------------------
64106  * ALT_USB_DEV_DCTL_CGOUTNAK_E_DISD | 0x0 | Disable Clear Global OUT NAK
64107  * ALT_USB_DEV_DCTL_CGOUTNAK_E_END | 0x1 | Clear Global OUT NAK
64108  *
64109  * Field Access Macros:
64110  *
64111  */
64112 /*
64113  * Enumerated value for register field ALT_USB_DEV_DCTL_CGOUTNAK
64114  *
64115  * Disable Clear Global OUT NAK
64116  */
64117 #define ALT_USB_DEV_DCTL_CGOUTNAK_E_DISD 0x0
64118 /*
64119  * Enumerated value for register field ALT_USB_DEV_DCTL_CGOUTNAK
64120  *
64121  * Clear Global OUT NAK
64122  */
64123 #define ALT_USB_DEV_DCTL_CGOUTNAK_E_END 0x1
64124 
64125 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */
64126 #define ALT_USB_DEV_DCTL_CGOUTNAK_LSB 10
64127 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */
64128 #define ALT_USB_DEV_DCTL_CGOUTNAK_MSB 10
64129 /* The width in bits of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */
64130 #define ALT_USB_DEV_DCTL_CGOUTNAK_WIDTH 1
64131 /* The mask used to set the ALT_USB_DEV_DCTL_CGOUTNAK register field value. */
64132 #define ALT_USB_DEV_DCTL_CGOUTNAK_SET_MSK 0x00000400
64133 /* The mask used to clear the ALT_USB_DEV_DCTL_CGOUTNAK register field value. */
64134 #define ALT_USB_DEV_DCTL_CGOUTNAK_CLR_MSK 0xfffffbff
64135 /* The reset value of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */
64136 #define ALT_USB_DEV_DCTL_CGOUTNAK_RESET 0x0
64137 /* Extracts the ALT_USB_DEV_DCTL_CGOUTNAK field value from a register. */
64138 #define ALT_USB_DEV_DCTL_CGOUTNAK_GET(value) (((value) & 0x00000400) >> 10)
64139 /* Produces a ALT_USB_DEV_DCTL_CGOUTNAK register field value suitable for setting the register. */
64140 #define ALT_USB_DEV_DCTL_CGOUTNAK_SET(value) (((value) << 10) & 0x00000400)
64141 
64142 /*
64143  * Field : pwronprgdone
64144  *
64145  * Power-On Programming Done (PWROnPrgDone)
64146  *
64147  * The application uses this bit to indicate that register
64148  *
64149  * programming is completed after a wake-up from Power Down
64150  *
64151  * mode.
64152  *
64153  * Field Enumeration Values:
64154  *
64155  * Enum | Value | Description
64156  * :----------------------------------------|:------|:------------------------------
64157  * ALT_USB_DEV_DCTL_PWRONPRGDONE_E_NOTDONE | 0x0 | Power-On Programming not done
64158  * ALT_USB_DEV_DCTL_PWRONPRGDONE_E_DONE | 0x1 | Power-On Programming Done
64159  *
64160  * Field Access Macros:
64161  *
64162  */
64163 /*
64164  * Enumerated value for register field ALT_USB_DEV_DCTL_PWRONPRGDONE
64165  *
64166  * Power-On Programming not done
64167  */
64168 #define ALT_USB_DEV_DCTL_PWRONPRGDONE_E_NOTDONE 0x0
64169 /*
64170  * Enumerated value for register field ALT_USB_DEV_DCTL_PWRONPRGDONE
64171  *
64172  * Power-On Programming Done
64173  */
64174 #define ALT_USB_DEV_DCTL_PWRONPRGDONE_E_DONE 0x1
64175 
64176 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */
64177 #define ALT_USB_DEV_DCTL_PWRONPRGDONE_LSB 11
64178 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */
64179 #define ALT_USB_DEV_DCTL_PWRONPRGDONE_MSB 11
64180 /* The width in bits of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */
64181 #define ALT_USB_DEV_DCTL_PWRONPRGDONE_WIDTH 1
64182 /* The mask used to set the ALT_USB_DEV_DCTL_PWRONPRGDONE register field value. */
64183 #define ALT_USB_DEV_DCTL_PWRONPRGDONE_SET_MSK 0x00000800
64184 /* The mask used to clear the ALT_USB_DEV_DCTL_PWRONPRGDONE register field value. */
64185 #define ALT_USB_DEV_DCTL_PWRONPRGDONE_CLR_MSK 0xfffff7ff
64186 /* The reset value of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */
64187 #define ALT_USB_DEV_DCTL_PWRONPRGDONE_RESET 0x0
64188 /* Extracts the ALT_USB_DEV_DCTL_PWRONPRGDONE field value from a register. */
64189 #define ALT_USB_DEV_DCTL_PWRONPRGDONE_GET(value) (((value) & 0x00000800) >> 11)
64190 /* Produces a ALT_USB_DEV_DCTL_PWRONPRGDONE register field value suitable for setting the register. */
64191 #define ALT_USB_DEV_DCTL_PWRONPRGDONE_SET(value) (((value) << 11) & 0x00000800)
64192 
64193 /*
64194  * Field : gmc
64195  *
64196  * Global Multi Count (GMC)
64197  *
64198  * GMC must be programmed only once after initialization.
64199  *
64200  * Applicable only For Scatter/Gather DMA mode. This indicates the
64201  *
64202  * number of packets to be serviced For that end point before
64203  *
64204  * moving to the next end point. It is only For non-periodic end
64205  *
64206  * points.
64207  *
64208  * 2'b00: Invalid.
64209  *
64210  * 2'b01: 1 packet.
64211  *
64212  * 2'b10: 2 packets.
64213  *
64214  * 2'b11: 3 packets.
64215  *
64216  * When Scatter/Gather DMA mode is disabled, this field is
64217  *
64218  * reserved. and reads 2'b00.
64219  *
64220  * Field Enumeration Values:
64221  *
64222  * Enum | Value | Description
64223  * :--------------------------------|:------|:------------
64224  * ALT_USB_DEV_DCTL_GMC_E_NOTVALID | 0x0 | Invalid
64225  * ALT_USB_DEV_DCTL_GMC_E_ONEPKT | 0x1 | 1 packet
64226  * ALT_USB_DEV_DCTL_GMC_E_TWOPKT | 0x2 | 2 packets
64227  * ALT_USB_DEV_DCTL_GMC_E_THREEPKT | 0x3 | 3 packets
64228  *
64229  * Field Access Macros:
64230  *
64231  */
64232 /*
64233  * Enumerated value for register field ALT_USB_DEV_DCTL_GMC
64234  *
64235  * Invalid
64236  */
64237 #define ALT_USB_DEV_DCTL_GMC_E_NOTVALID 0x0
64238 /*
64239  * Enumerated value for register field ALT_USB_DEV_DCTL_GMC
64240  *
64241  * 1 packet
64242  */
64243 #define ALT_USB_DEV_DCTL_GMC_E_ONEPKT 0x1
64244 /*
64245  * Enumerated value for register field ALT_USB_DEV_DCTL_GMC
64246  *
64247  * 2 packets
64248  */
64249 #define ALT_USB_DEV_DCTL_GMC_E_TWOPKT 0x2
64250 /*
64251  * Enumerated value for register field ALT_USB_DEV_DCTL_GMC
64252  *
64253  * 3 packets
64254  */
64255 #define ALT_USB_DEV_DCTL_GMC_E_THREEPKT 0x3
64256 
64257 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_GMC register field. */
64258 #define ALT_USB_DEV_DCTL_GMC_LSB 13
64259 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_GMC register field. */
64260 #define ALT_USB_DEV_DCTL_GMC_MSB 14
64261 /* The width in bits of the ALT_USB_DEV_DCTL_GMC register field. */
64262 #define ALT_USB_DEV_DCTL_GMC_WIDTH 2
64263 /* The mask used to set the ALT_USB_DEV_DCTL_GMC register field value. */
64264 #define ALT_USB_DEV_DCTL_GMC_SET_MSK 0x00006000
64265 /* The mask used to clear the ALT_USB_DEV_DCTL_GMC register field value. */
64266 #define ALT_USB_DEV_DCTL_GMC_CLR_MSK 0xffff9fff
64267 /* The reset value of the ALT_USB_DEV_DCTL_GMC register field. */
64268 #define ALT_USB_DEV_DCTL_GMC_RESET 0x0
64269 /* Extracts the ALT_USB_DEV_DCTL_GMC field value from a register. */
64270 #define ALT_USB_DEV_DCTL_GMC_GET(value) (((value) & 0x00006000) >> 13)
64271 /* Produces a ALT_USB_DEV_DCTL_GMC register field value suitable for setting the register. */
64272 #define ALT_USB_DEV_DCTL_GMC_SET(value) (((value) << 13) & 0x00006000)
64273 
64274 /*
64275  * Field : ignrfrmnum
64276  *
64277  * Ignore Frame number For Isochronous End points (IgnrFrmNum)
64278  *
64279  * Do NOT program IgnrFrmNum bit to 1'b1 when the core is
64280  *
64281  * operating in threshold mode.
64282  *
64283  * Note: When Scatter/Gather DMA mode is enabled this feature is not applicable to
64284  * High Speed, High bandwidth transfers. When this bit is enabled, there must be
64285  * only one packet per descriptor.
64286  *
64287  * 0: The core transmits the packets only in the frame number in which they are
64288  * intended to be transmitted.
64289  *
64290  * 1: The core ignores the frame number, sending packets immediately as the packets
64291  * are ready.
64292  *
64293  * In Scatter/Gather DMA mode, if this bit is enabled, the packets are not flushed
64294  * when a ISOC IN token is received for an elapsed frame.
64295  *
64296  * When Scatter/Gather DMA mode is disabled, this field is used by the application
64297  * to enable periodic transfer interrupt. The application can program periodic
64298  * endpoint transfers for multiple (micro)frames.
64299  *
64300  * 0: periodic transfer interrupt feature is disabled, application needs to program
64301  * transfers for periodic endpoints every (micro)frame
64302  *
64303  * 1: periodic transfer interrupt feature is enabled, application can program
64304  * transfers for multiple (micro)frames for periodic endpoints.
64305  *
64306  * In non Scatter/Gather DMA mode the application will receive transfer complete
64307  * interrupt after transfers for multiple (micro)frames are completed.
64308  *
64309  * Field Enumeration Values:
64310  *
64311  * Enum | Value | Description
64312  * :-----------------------------------|:------|:-------------------------------------------------
64313  * ALT_USB_DEV_DCTL_IGNRFRMNUM_E_DISD | 0x0 | The core transmits the packets only in the frame
64314  * : | | number in which they are intended to be
64315  * : | | transmitted
64316  * ALT_USB_DEV_DCTL_IGNRFRMNUM_E_END | 0x1 | The core ignores the frame number, sending
64317  * : | | packets immediately as the packets are ready
64318  *
64319  * Field Access Macros:
64320  *
64321  */
64322 /*
64323  * Enumerated value for register field ALT_USB_DEV_DCTL_IGNRFRMNUM
64324  *
64325  * The core transmits the packets only in the frame number in which they are
64326  * intended to be transmitted
64327  */
64328 #define ALT_USB_DEV_DCTL_IGNRFRMNUM_E_DISD 0x0
64329 /*
64330  * Enumerated value for register field ALT_USB_DEV_DCTL_IGNRFRMNUM
64331  *
64332  * The core ignores the frame number, sending packets immediately as the packets
64333  * are ready
64334  */
64335 #define ALT_USB_DEV_DCTL_IGNRFRMNUM_E_END 0x1
64336 
64337 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */
64338 #define ALT_USB_DEV_DCTL_IGNRFRMNUM_LSB 15
64339 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */
64340 #define ALT_USB_DEV_DCTL_IGNRFRMNUM_MSB 15
64341 /* The width in bits of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */
64342 #define ALT_USB_DEV_DCTL_IGNRFRMNUM_WIDTH 1
64343 /* The mask used to set the ALT_USB_DEV_DCTL_IGNRFRMNUM register field value. */
64344 #define ALT_USB_DEV_DCTL_IGNRFRMNUM_SET_MSK 0x00008000
64345 /* The mask used to clear the ALT_USB_DEV_DCTL_IGNRFRMNUM register field value. */
64346 #define ALT_USB_DEV_DCTL_IGNRFRMNUM_CLR_MSK 0xffff7fff
64347 /* The reset value of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */
64348 #define ALT_USB_DEV_DCTL_IGNRFRMNUM_RESET 0x0
64349 /* Extracts the ALT_USB_DEV_DCTL_IGNRFRMNUM field value from a register. */
64350 #define ALT_USB_DEV_DCTL_IGNRFRMNUM_GET(value) (((value) & 0x00008000) >> 15)
64351 /* Produces a ALT_USB_DEV_DCTL_IGNRFRMNUM register field value suitable for setting the register. */
64352 #define ALT_USB_DEV_DCTL_IGNRFRMNUM_SET(value) (((value) << 15) & 0x00008000)
64353 
64354 /*
64355  * Field : nakonbble
64356  *
64357  * NAK on Babble Error (NakOnBble)
64358  *
64359  * Set NAK automatically on babble (NakOnBble). The core sets NAK automatically for
64360  * the
64361  *
64362  * endpoint on which babble is received.
64363  *
64364  * Field Enumeration Values:
64365  *
64366  * Enum | Value | Description
64367  * :----------------------------------|:------|:----------------------------
64368  * ALT_USB_DEV_DCTL_NAKONBBLE_E_DISD | 0x0 | Disable NAK on Babble Error
64369  * ALT_USB_DEV_DCTL_NAKONBBLE_E_END | 0x1 | NAK on Babble Error
64370  *
64371  * Field Access Macros:
64372  *
64373  */
64374 /*
64375  * Enumerated value for register field ALT_USB_DEV_DCTL_NAKONBBLE
64376  *
64377  * Disable NAK on Babble Error
64378  */
64379 #define ALT_USB_DEV_DCTL_NAKONBBLE_E_DISD 0x0
64380 /*
64381  * Enumerated value for register field ALT_USB_DEV_DCTL_NAKONBBLE
64382  *
64383  * NAK on Babble Error
64384  */
64385 #define ALT_USB_DEV_DCTL_NAKONBBLE_E_END 0x1
64386 
64387 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */
64388 #define ALT_USB_DEV_DCTL_NAKONBBLE_LSB 16
64389 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */
64390 #define ALT_USB_DEV_DCTL_NAKONBBLE_MSB 16
64391 /* The width in bits of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */
64392 #define ALT_USB_DEV_DCTL_NAKONBBLE_WIDTH 1
64393 /* The mask used to set the ALT_USB_DEV_DCTL_NAKONBBLE register field value. */
64394 #define ALT_USB_DEV_DCTL_NAKONBBLE_SET_MSK 0x00010000
64395 /* The mask used to clear the ALT_USB_DEV_DCTL_NAKONBBLE register field value. */
64396 #define ALT_USB_DEV_DCTL_NAKONBBLE_CLR_MSK 0xfffeffff
64397 /* The reset value of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */
64398 #define ALT_USB_DEV_DCTL_NAKONBBLE_RESET 0x0
64399 /* Extracts the ALT_USB_DEV_DCTL_NAKONBBLE field value from a register. */
64400 #define ALT_USB_DEV_DCTL_NAKONBBLE_GET(value) (((value) & 0x00010000) >> 16)
64401 /* Produces a ALT_USB_DEV_DCTL_NAKONBBLE register field value suitable for setting the register. */
64402 #define ALT_USB_DEV_DCTL_NAKONBBLE_SET(value) (((value) << 16) & 0x00010000)
64403 
64404 /*
64405  * Field : encontonbna
64406  *
64407  * Enable Continue on BNA (EnContOnBNA)
64408  *
64409  * This bit enables the DWC_otg core to continue on BNA for Bulk OUT endpoints.
64410  *
64411  * With this feature enabled, when a Bulk OUT endpoint receives a BNA interrupt
64412  *
64413  * the core starts processing the descriptor that caused the BNA interrupt after
64414  *
64415  * the endpoint re-enables the endpoint.
64416  *
64417  * 1'b0: After receiving BNA interrupt,the core disables the endpoint. When the
64418  *
64419  * endpoint is re-enabled by the application,the core starts processing from
64420  *
64421  * the DOEPDMA descriptor.
64422  *
64423  * 1'b1: After receiving BNA interrupt, the core disables the endpoint. When the
64424  *
64425  * endpoint is re-enabled by the application, the core starts processing from
64426  *
64427  * the descriptor that received the BNA interrupt. This bit is valid only when
64428  *
64429  * OTG_EN_DESC_DMA == 1'b1. It is a one-time programmable after reset bit like
64430  *
64431  * any other DCTL register bits.
64432  *
64433  * Field Access Macros:
64434  *
64435  */
64436 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_ENCONTONBNA register field. */
64437 #define ALT_USB_DEV_DCTL_ENCONTONBNA_LSB 17
64438 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_ENCONTONBNA register field. */
64439 #define ALT_USB_DEV_DCTL_ENCONTONBNA_MSB 17
64440 /* The width in bits of the ALT_USB_DEV_DCTL_ENCONTONBNA register field. */
64441 #define ALT_USB_DEV_DCTL_ENCONTONBNA_WIDTH 1
64442 /* The mask used to set the ALT_USB_DEV_DCTL_ENCONTONBNA register field value. */
64443 #define ALT_USB_DEV_DCTL_ENCONTONBNA_SET_MSK 0x00020000
64444 /* The mask used to clear the ALT_USB_DEV_DCTL_ENCONTONBNA register field value. */
64445 #define ALT_USB_DEV_DCTL_ENCONTONBNA_CLR_MSK 0xfffdffff
64446 /* The reset value of the ALT_USB_DEV_DCTL_ENCONTONBNA register field. */
64447 #define ALT_USB_DEV_DCTL_ENCONTONBNA_RESET 0x0
64448 /* Extracts the ALT_USB_DEV_DCTL_ENCONTONBNA field value from a register. */
64449 #define ALT_USB_DEV_DCTL_ENCONTONBNA_GET(value) (((value) & 0x00020000) >> 17)
64450 /* Produces a ALT_USB_DEV_DCTL_ENCONTONBNA register field value suitable for setting the register. */
64451 #define ALT_USB_DEV_DCTL_ENCONTONBNA_SET(value) (((value) << 17) & 0x00020000)
64452 
64453 #ifndef __ASSEMBLY__
64454 /*
64455  * WARNING: The C register and register group struct declarations are provided for
64456  * convenience and illustrative purposes. They should, however, be used with
64457  * caution as the C language standard provides no guarantees about the alignment or
64458  * atomicity of device memory accesses. The recommended practice for writing
64459  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64460  * alt_write_word() functions.
64461  *
64462  * The struct declaration for register ALT_USB_DEV_DCTL.
64463  */
64464 struct ALT_USB_DEV_DCTL_s
64465 {
64466  uint32_t rmtwkupsig : 1; /* ALT_USB_DEV_DCTL_RMTWKUPSIG */
64467  uint32_t sftdiscon : 1; /* ALT_USB_DEV_DCTL_SFTDISCON */
64468  const uint32_t gnpinnaksts : 1; /* ALT_USB_DEV_DCTL_GNPINNAKSTS */
64469  const uint32_t goutnaksts : 1; /* ALT_USB_DEV_DCTL_GOUTNAKSTS */
64470  uint32_t tstctl : 3; /* ALT_USB_DEV_DCTL_TSTCTL */
64471  uint32_t sgnpinnak : 1; /* ALT_USB_DEV_DCTL_SGNPINNAK */
64472  uint32_t cgnpinnak : 1; /* ALT_USB_DEV_DCTL_CGNPINNAK */
64473  uint32_t sgoutnak : 1; /* ALT_USB_DEV_DCTL_SGOUTNAK */
64474  uint32_t cgoutnak : 1; /* ALT_USB_DEV_DCTL_CGOUTNAK */
64475  uint32_t pwronprgdone : 1; /* ALT_USB_DEV_DCTL_PWRONPRGDONE */
64476  uint32_t : 1; /* *UNDEFINED* */
64477  uint32_t gmc : 2; /* ALT_USB_DEV_DCTL_GMC */
64478  uint32_t ignrfrmnum : 1; /* ALT_USB_DEV_DCTL_IGNRFRMNUM */
64479  uint32_t nakonbble : 1; /* ALT_USB_DEV_DCTL_NAKONBBLE */
64480  uint32_t encontonbna : 1; /* ALT_USB_DEV_DCTL_ENCONTONBNA */
64481  uint32_t : 14; /* *UNDEFINED* */
64482 };
64483 
64484 /* The typedef declaration for register ALT_USB_DEV_DCTL. */
64485 typedef volatile struct ALT_USB_DEV_DCTL_s ALT_USB_DEV_DCTL_t;
64486 #endif /* __ASSEMBLY__ */
64487 
64488 /* The reset value of the ALT_USB_DEV_DCTL register. */
64489 #define ALT_USB_DEV_DCTL_RESET 0x00000002
64490 /* The byte offset of the ALT_USB_DEV_DCTL register from the beginning of the component. */
64491 #define ALT_USB_DEV_DCTL_OFST 0x4
64492 /* The address of the ALT_USB_DEV_DCTL register. */
64493 #define ALT_USB_DEV_DCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DCTL_OFST))
64494 
64495 /*
64496  * Register : dsts
64497  *
64498  * Device Status Register
64499  *
64500  * Register Layout
64501  *
64502  * Bits | Access | Reset | Description
64503  * :--------|:-------|:------|:---------------------------
64504  * [0] | R | 0x0 | ALT_USB_DEV_DSTS_SUSPSTS
64505  * [2:1] | R | 0x1 | ALT_USB_DEV_DSTS_ENUMSPD
64506  * [3] | R | 0x0 | ALT_USB_DEV_DSTS_ERRTICERR
64507  * [7:4] | ??? | 0x0 | *UNDEFINED*
64508  * [21:8] | R | 0x0 | ALT_USB_DEV_DSTS_SOFFN
64509  * [23:22] | R | 0x0 | ALT_USB_DEV_DSTS_DEVLNSTS
64510  * [31:24] | ??? | 0x0 | *UNDEFINED*
64511  *
64512  */
64513 /*
64514  * Field : suspsts
64515  *
64516  * Suspend Status (SuspSts)
64517  *
64518  * In Device mode, this bit is Set as long as a Suspend condition is
64519  *
64520  * detected on the USB. The core enters the Suspended state
64521  *
64522  * when there is no activity on the phy_line_state_i signal For an
64523  *
64524  * extended period of time. The core comes out of the suspend:
64525  *
64526  * When there is any activity on the phy_line_state_i signal
64527  *
64528  * When the application writes to the Remote Wakeup Signaling
64529  *
64530  * bit in the Device Control register (DCTL.RmtWkUpSig).
64531  *
64532  * Field Enumeration Values:
64533  *
64534  * Enum | Value | Description
64535  * :---------------------------------|:------|:-----------------
64536  * ALT_USB_DEV_DSTS_SUSPSTS_E_INACT | 0x0 | No suspend state
64537  * ALT_USB_DEV_DSTS_SUSPSTS_E_ACT | 0x1 | Suspend state
64538  *
64539  * Field Access Macros:
64540  *
64541  */
64542 /*
64543  * Enumerated value for register field ALT_USB_DEV_DSTS_SUSPSTS
64544  *
64545  * No suspend state
64546  */
64547 #define ALT_USB_DEV_DSTS_SUSPSTS_E_INACT 0x0
64548 /*
64549  * Enumerated value for register field ALT_USB_DEV_DSTS_SUSPSTS
64550  *
64551  * Suspend state
64552  */
64553 #define ALT_USB_DEV_DSTS_SUSPSTS_E_ACT 0x1
64554 
64555 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_SUSPSTS register field. */
64556 #define ALT_USB_DEV_DSTS_SUSPSTS_LSB 0
64557 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_SUSPSTS register field. */
64558 #define ALT_USB_DEV_DSTS_SUSPSTS_MSB 0
64559 /* The width in bits of the ALT_USB_DEV_DSTS_SUSPSTS register field. */
64560 #define ALT_USB_DEV_DSTS_SUSPSTS_WIDTH 1
64561 /* The mask used to set the ALT_USB_DEV_DSTS_SUSPSTS register field value. */
64562 #define ALT_USB_DEV_DSTS_SUSPSTS_SET_MSK 0x00000001
64563 /* The mask used to clear the ALT_USB_DEV_DSTS_SUSPSTS register field value. */
64564 #define ALT_USB_DEV_DSTS_SUSPSTS_CLR_MSK 0xfffffffe
64565 /* The reset value of the ALT_USB_DEV_DSTS_SUSPSTS register field. */
64566 #define ALT_USB_DEV_DSTS_SUSPSTS_RESET 0x0
64567 /* Extracts the ALT_USB_DEV_DSTS_SUSPSTS field value from a register. */
64568 #define ALT_USB_DEV_DSTS_SUSPSTS_GET(value) (((value) & 0x00000001) >> 0)
64569 /* Produces a ALT_USB_DEV_DSTS_SUSPSTS register field value suitable for setting the register. */
64570 #define ALT_USB_DEV_DSTS_SUSPSTS_SET(value) (((value) << 0) & 0x00000001)
64571 
64572 /*
64573  * Field : enumspd
64574  *
64575  * Enumerated Speed (EnumSpd)
64576  *
64577  * Indicates the speed at which the DWC_otg core has come up
64578  *
64579  * after speed detection through a chirp sequence.
64580  *
64581  * 2'b00: High speed (PHY clock is running at 30 or 60 MHz)
64582  *
64583  * 2'b01: Full speed (PHY clock is running at 30 or 60 MHz)
64584  *
64585  * 2'b10: Low speed (PHY clock is running at 6 MHz)
64586  *
64587  * 2'b11: Full speed (PHY clock is running at 48 MHz)
64588  *
64589  * Low speed is not supported For devices using a UTMI+ PHY.
64590  *
64591  * Field Enumeration Values:
64592  *
64593  * Enum | Value | Description
64594  * :----------------------------------|:------|:---------------------------------------------
64595  * ALT_USB_DEV_DSTS_ENUMSPD_E_HS3060 | 0x0 | High speed (PHY clock is running at 30 or 60
64596  * : | | MHz)
64597  * ALT_USB_DEV_DSTS_ENUMSPD_E_FS3060 | 0x1 | Full speed (PHY clock is running at 30 or 60
64598  * : | | MHz)
64599  * ALT_USB_DEV_DSTS_ENUMSPD_E_LS6 | 0x2 | Low speed (PHY clock is running at 6 MHz)
64600  * ALT_USB_DEV_DSTS_ENUMSPD_E_FS48 | 0x3 | Full speed (PHY clock is running at 48 MHz)
64601  *
64602  * Field Access Macros:
64603  *
64604  */
64605 /*
64606  * Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD
64607  *
64608  * High speed (PHY clock is running at 30 or 60 MHz)
64609  */
64610 #define ALT_USB_DEV_DSTS_ENUMSPD_E_HS3060 0x0
64611 /*
64612  * Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD
64613  *
64614  * Full speed (PHY clock is running at 30 or 60 MHz)
64615  */
64616 #define ALT_USB_DEV_DSTS_ENUMSPD_E_FS3060 0x1
64617 /*
64618  * Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD
64619  *
64620  * Low speed (PHY clock is running at 6 MHz)
64621  */
64622 #define ALT_USB_DEV_DSTS_ENUMSPD_E_LS6 0x2
64623 /*
64624  * Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD
64625  *
64626  * Full speed (PHY clock is running at 48 MHz)
64627  */
64628 #define ALT_USB_DEV_DSTS_ENUMSPD_E_FS48 0x3
64629 
64630 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_ENUMSPD register field. */
64631 #define ALT_USB_DEV_DSTS_ENUMSPD_LSB 1
64632 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_ENUMSPD register field. */
64633 #define ALT_USB_DEV_DSTS_ENUMSPD_MSB 2
64634 /* The width in bits of the ALT_USB_DEV_DSTS_ENUMSPD register field. */
64635 #define ALT_USB_DEV_DSTS_ENUMSPD_WIDTH 2
64636 /* The mask used to set the ALT_USB_DEV_DSTS_ENUMSPD register field value. */
64637 #define ALT_USB_DEV_DSTS_ENUMSPD_SET_MSK 0x00000006
64638 /* The mask used to clear the ALT_USB_DEV_DSTS_ENUMSPD register field value. */
64639 #define ALT_USB_DEV_DSTS_ENUMSPD_CLR_MSK 0xfffffff9
64640 /* The reset value of the ALT_USB_DEV_DSTS_ENUMSPD register field. */
64641 #define ALT_USB_DEV_DSTS_ENUMSPD_RESET 0x1
64642 /* Extracts the ALT_USB_DEV_DSTS_ENUMSPD field value from a register. */
64643 #define ALT_USB_DEV_DSTS_ENUMSPD_GET(value) (((value) & 0x00000006) >> 1)
64644 /* Produces a ALT_USB_DEV_DSTS_ENUMSPD register field value suitable for setting the register. */
64645 #define ALT_USB_DEV_DSTS_ENUMSPD_SET(value) (((value) << 1) & 0x00000006)
64646 
64647 /*
64648  * Field : errticerr
64649  *
64650  * Erratic Error (ErrticErr)
64651  *
64652  * The core sets this bit to report any erratic errors
64653  *
64654  * (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted For at
64655  *
64656  * least 2 ms, due to PHY error) seen on the UTMI+ .
64657  *
64658  * Due to erratic errors, the DWC_otg core goes into Suspended
64659  *
64660  * state and an interrupt is generated to the application with Early
64661  *
64662  * Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp).
64663  *
64664  * If the early suspend is asserted due to an erratic error, the
64665  *
64666  * application can only perform a soft disconnect recover.
64667  *
64668  * Field Enumeration Values:
64669  *
64670  * Enum | Value | Description
64671  * :-----------------------------------|:------|:-----------------
64672  * ALT_USB_DEV_DSTS_ERRTICERR_E_INACT | 0x0 | No Erratic Error
64673  * ALT_USB_DEV_DSTS_ERRTICERR_E_ACT | 0x1 | Erratic Error
64674  *
64675  * Field Access Macros:
64676  *
64677  */
64678 /*
64679  * Enumerated value for register field ALT_USB_DEV_DSTS_ERRTICERR
64680  *
64681  * No Erratic Error
64682  */
64683 #define ALT_USB_DEV_DSTS_ERRTICERR_E_INACT 0x0
64684 /*
64685  * Enumerated value for register field ALT_USB_DEV_DSTS_ERRTICERR
64686  *
64687  * Erratic Error
64688  */
64689 #define ALT_USB_DEV_DSTS_ERRTICERR_E_ACT 0x1
64690 
64691 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_ERRTICERR register field. */
64692 #define ALT_USB_DEV_DSTS_ERRTICERR_LSB 3
64693 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_ERRTICERR register field. */
64694 #define ALT_USB_DEV_DSTS_ERRTICERR_MSB 3
64695 /* The width in bits of the ALT_USB_DEV_DSTS_ERRTICERR register field. */
64696 #define ALT_USB_DEV_DSTS_ERRTICERR_WIDTH 1
64697 /* The mask used to set the ALT_USB_DEV_DSTS_ERRTICERR register field value. */
64698 #define ALT_USB_DEV_DSTS_ERRTICERR_SET_MSK 0x00000008
64699 /* The mask used to clear the ALT_USB_DEV_DSTS_ERRTICERR register field value. */
64700 #define ALT_USB_DEV_DSTS_ERRTICERR_CLR_MSK 0xfffffff7
64701 /* The reset value of the ALT_USB_DEV_DSTS_ERRTICERR register field. */
64702 #define ALT_USB_DEV_DSTS_ERRTICERR_RESET 0x0
64703 /* Extracts the ALT_USB_DEV_DSTS_ERRTICERR field value from a register. */
64704 #define ALT_USB_DEV_DSTS_ERRTICERR_GET(value) (((value) & 0x00000008) >> 3)
64705 /* Produces a ALT_USB_DEV_DSTS_ERRTICERR register field value suitable for setting the register. */
64706 #define ALT_USB_DEV_DSTS_ERRTICERR_SET(value) (((value) << 3) & 0x00000008)
64707 
64708 /*
64709  * Field : soffn
64710  *
64711  * Frame or Microframe Number of the Received SOF (SOFFN)
64712  *
64713  * When the core is operating at high speed, this field contains a
64714  *
64715  * microframe number. When the core is operating at full or low
64716  *
64717  * speed, this field contains a Frame number.
64718  *
64719  * Note: This register may return a non zero value if read immediately after power
64720  * on reset.
64721  *
64722  * In case the register bit reads non zero immediately after power on reset it does
64723  * not
64724  *
64725  * indicate that SOF has been received from the host. The read value of this
64726  * interrupt is
64727  *
64728  * valid only after a valid connection between host and device is established.
64729  *
64730  * Field Access Macros:
64731  *
64732  */
64733 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_SOFFN register field. */
64734 #define ALT_USB_DEV_DSTS_SOFFN_LSB 8
64735 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_SOFFN register field. */
64736 #define ALT_USB_DEV_DSTS_SOFFN_MSB 21
64737 /* The width in bits of the ALT_USB_DEV_DSTS_SOFFN register field. */
64738 #define ALT_USB_DEV_DSTS_SOFFN_WIDTH 14
64739 /* The mask used to set the ALT_USB_DEV_DSTS_SOFFN register field value. */
64740 #define ALT_USB_DEV_DSTS_SOFFN_SET_MSK 0x003fff00
64741 /* The mask used to clear the ALT_USB_DEV_DSTS_SOFFN register field value. */
64742 #define ALT_USB_DEV_DSTS_SOFFN_CLR_MSK 0xffc000ff
64743 /* The reset value of the ALT_USB_DEV_DSTS_SOFFN register field. */
64744 #define ALT_USB_DEV_DSTS_SOFFN_RESET 0x0
64745 /* Extracts the ALT_USB_DEV_DSTS_SOFFN field value from a register. */
64746 #define ALT_USB_DEV_DSTS_SOFFN_GET(value) (((value) & 0x003fff00) >> 8)
64747 /* Produces a ALT_USB_DEV_DSTS_SOFFN register field value suitable for setting the register. */
64748 #define ALT_USB_DEV_DSTS_SOFFN_SET(value) (((value) << 8) & 0x003fff00)
64749 
64750 /*
64751  * Field : devlnsts
64752  *
64753  * Device Line Status (DevLnSts)
64754  *
64755  * Indicates the current logic level USB data lines
64756  *
64757  * DevLnSts[1]: Logic level of D+
64758  *
64759  * DevLnSts[0]: Logic level of D-
64760  *
64761  * Field Access Macros:
64762  *
64763  */
64764 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_DEVLNSTS register field. */
64765 #define ALT_USB_DEV_DSTS_DEVLNSTS_LSB 22
64766 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_DEVLNSTS register field. */
64767 #define ALT_USB_DEV_DSTS_DEVLNSTS_MSB 23
64768 /* The width in bits of the ALT_USB_DEV_DSTS_DEVLNSTS register field. */
64769 #define ALT_USB_DEV_DSTS_DEVLNSTS_WIDTH 2
64770 /* The mask used to set the ALT_USB_DEV_DSTS_DEVLNSTS register field value. */
64771 #define ALT_USB_DEV_DSTS_DEVLNSTS_SET_MSK 0x00c00000
64772 /* The mask used to clear the ALT_USB_DEV_DSTS_DEVLNSTS register field value. */
64773 #define ALT_USB_DEV_DSTS_DEVLNSTS_CLR_MSK 0xff3fffff
64774 /* The reset value of the ALT_USB_DEV_DSTS_DEVLNSTS register field. */
64775 #define ALT_USB_DEV_DSTS_DEVLNSTS_RESET 0x0
64776 /* Extracts the ALT_USB_DEV_DSTS_DEVLNSTS field value from a register. */
64777 #define ALT_USB_DEV_DSTS_DEVLNSTS_GET(value) (((value) & 0x00c00000) >> 22)
64778 /* Produces a ALT_USB_DEV_DSTS_DEVLNSTS register field value suitable for setting the register. */
64779 #define ALT_USB_DEV_DSTS_DEVLNSTS_SET(value) (((value) << 22) & 0x00c00000)
64780 
64781 #ifndef __ASSEMBLY__
64782 /*
64783  * WARNING: The C register and register group struct declarations are provided for
64784  * convenience and illustrative purposes. They should, however, be used with
64785  * caution as the C language standard provides no guarantees about the alignment or
64786  * atomicity of device memory accesses. The recommended practice for writing
64787  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64788  * alt_write_word() functions.
64789  *
64790  * The struct declaration for register ALT_USB_DEV_DSTS.
64791  */
64792 struct ALT_USB_DEV_DSTS_s
64793 {
64794  const uint32_t suspsts : 1; /* ALT_USB_DEV_DSTS_SUSPSTS */
64795  const uint32_t enumspd : 2; /* ALT_USB_DEV_DSTS_ENUMSPD */
64796  const uint32_t errticerr : 1; /* ALT_USB_DEV_DSTS_ERRTICERR */
64797  uint32_t : 4; /* *UNDEFINED* */
64798  const uint32_t soffn : 14; /* ALT_USB_DEV_DSTS_SOFFN */
64799  const uint32_t devlnsts : 2; /* ALT_USB_DEV_DSTS_DEVLNSTS */
64800  uint32_t : 8; /* *UNDEFINED* */
64801 };
64802 
64803 /* The typedef declaration for register ALT_USB_DEV_DSTS. */
64804 typedef volatile struct ALT_USB_DEV_DSTS_s ALT_USB_DEV_DSTS_t;
64805 #endif /* __ASSEMBLY__ */
64806 
64807 /* The reset value of the ALT_USB_DEV_DSTS register. */
64808 #define ALT_USB_DEV_DSTS_RESET 0x00000002
64809 /* The byte offset of the ALT_USB_DEV_DSTS register from the beginning of the component. */
64810 #define ALT_USB_DEV_DSTS_OFST 0x8
64811 /* The address of the ALT_USB_DEV_DSTS register. */
64812 #define ALT_USB_DEV_DSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DSTS_OFST))
64813 
64814 /*
64815  * Register : diepmsk
64816  *
64817  * Device IN Endpoint Common Interrupt Mask Register
64818  *
64819  * Register Layout
64820  *
64821  * Bits | Access | Reset | Description
64822  * :--------|:-------|:------|:-----------------------------------
64823  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK
64824  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_EPDISBLDMSK
64825  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_AHBERRMSK
64826  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_TMOMSK
64827  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK
64828  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK
64829  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK
64830  * [7] | ??? | 0x0 | *UNDEFINED*
64831  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK
64832  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_BNAININTRMSK
64833  * [12:10] | ??? | 0x0 | *UNDEFINED*
64834  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_NAKMSK
64835  * [31:14] | ??? | 0x0 | *UNDEFINED*
64836  *
64837  */
64838 /*
64839  * Field : xfercomplmsk
64840  *
64841  * Transfer Completed Interrupt Mask (XferComplMsk)
64842  *
64843  * Field Enumeration Values:
64844  *
64845  * Enum | Value | Description
64846  * :-----------------------------------------|:------|:-------------------------------------
64847  * ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_MSK | 0x0 | Mask Transfer Completed Interrupt
64848  * ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_NOMSK | 0x1 | No Mask Transfer Completed Interrupt
64849  *
64850  * Field Access Macros:
64851  *
64852  */
64853 /*
64854  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK
64855  *
64856  * Mask Transfer Completed Interrupt
64857  */
64858 #define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_MSK 0x0
64859 /*
64860  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK
64861  *
64862  * No Mask Transfer Completed Interrupt
64863  */
64864 #define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_NOMSK 0x1
64865 
64866 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */
64867 #define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_LSB 0
64868 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */
64869 #define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_MSB 0
64870 /* The width in bits of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */
64871 #define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_WIDTH 1
64872 /* The mask used to set the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field value. */
64873 #define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_SET_MSK 0x00000001
64874 /* The mask used to clear the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field value. */
64875 #define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_CLR_MSK 0xfffffffe
64876 /* The reset value of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */
64877 #define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_RESET 0x0
64878 /* Extracts the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK field value from a register. */
64879 #define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
64880 /* Produces a ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field value suitable for setting the register. */
64881 #define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
64882 
64883 /*
64884  * Field : epdisbldmsk
64885  *
64886  * Endpoint Disabled Interrupt Mask (EPDisbldMsk)
64887  *
64888  * Field Enumeration Values:
64889  *
64890  * Enum | Value | Description
64891  * :----------------------------------------|:------|:------------------------------------
64892  * ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_MSK | 0x0 | Mask Endpoint Disabled Interrupt
64893  * ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_NOMSK | 0x1 | No Mask Endpoint Disabled Interrupt
64894  *
64895  * Field Access Macros:
64896  *
64897  */
64898 /*
64899  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_EPDISBLDMSK
64900  *
64901  * Mask Endpoint Disabled Interrupt
64902  */
64903 #define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_MSK 0x0
64904 /*
64905  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_EPDISBLDMSK
64906  *
64907  * No Mask Endpoint Disabled Interrupt
64908  */
64909 #define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_NOMSK 0x1
64910 
64911 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */
64912 #define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_LSB 1
64913 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */
64914 #define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_MSB 1
64915 /* The width in bits of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */
64916 #define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_WIDTH 1
64917 /* The mask used to set the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field value. */
64918 #define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_SET_MSK 0x00000002
64919 /* The mask used to clear the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field value. */
64920 #define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_CLR_MSK 0xfffffffd
64921 /* The reset value of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */
64922 #define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_RESET 0x0
64923 /* Extracts the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK field value from a register. */
64924 #define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_GET(value) (((value) & 0x00000002) >> 1)
64925 /* Produces a ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field value suitable for setting the register. */
64926 #define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_SET(value) (((value) << 1) & 0x00000002)
64927 
64928 /*
64929  * Field : ahberrmsk
64930  *
64931  * AHB Error Mask (AHBErrMsk)
64932  *
64933  * Field Enumeration Values:
64934  *
64935  * Enum | Value | Description
64936  * :--------------------------------------|:------|:-----------------------------
64937  * ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_MSK | 0x0 | Mask AHB Error Interrupt
64938  * ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_NOMSK | 0x1 | No Mask AHB Error Interrupt
64939  *
64940  * Field Access Macros:
64941  *
64942  */
64943 /*
64944  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_AHBERRMSK
64945  *
64946  * Mask AHB Error Interrupt
64947  */
64948 #define ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_MSK 0x0
64949 /*
64950  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_AHBERRMSK
64951  *
64952  * No Mask AHB Error Interrupt
64953  */
64954 #define ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_NOMSK 0x1
64955 
64956 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */
64957 #define ALT_USB_DEV_DIEPMSK_AHBERRMSK_LSB 2
64958 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */
64959 #define ALT_USB_DEV_DIEPMSK_AHBERRMSK_MSB 2
64960 /* The width in bits of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */
64961 #define ALT_USB_DEV_DIEPMSK_AHBERRMSK_WIDTH 1
64962 /* The mask used to set the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field value. */
64963 #define ALT_USB_DEV_DIEPMSK_AHBERRMSK_SET_MSK 0x00000004
64964 /* The mask used to clear the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field value. */
64965 #define ALT_USB_DEV_DIEPMSK_AHBERRMSK_CLR_MSK 0xfffffffb
64966 /* The reset value of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */
64967 #define ALT_USB_DEV_DIEPMSK_AHBERRMSK_RESET 0x0
64968 /* Extracts the ALT_USB_DEV_DIEPMSK_AHBERRMSK field value from a register. */
64969 #define ALT_USB_DEV_DIEPMSK_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
64970 /* Produces a ALT_USB_DEV_DIEPMSK_AHBERRMSK register field value suitable for setting the register. */
64971 #define ALT_USB_DEV_DIEPMSK_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
64972 
64973 /*
64974  * Field : timeoutmsk
64975  *
64976  * Timeout Condition Mask (TimeOUTMsk)
64977  *
64978  * (Non-isochronous endpoints)
64979  *
64980  * Field Enumeration Values:
64981  *
64982  * Enum | Value | Description
64983  * :-----------------------------------|:------|:------------------------------------
64984  * ALT_USB_DEV_DIEPMSK_TMOMSK_E_MSK | 0x0 | Mask Timeout Condition Interrupt
64985  * ALT_USB_DEV_DIEPMSK_TMOMSK_E_NOMSK | 0x1 | No Mask Timeout Condition Interrupt
64986  *
64987  * Field Access Macros:
64988  *
64989  */
64990 /*
64991  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_TMOMSK
64992  *
64993  * Mask Timeout Condition Interrupt
64994  */
64995 #define ALT_USB_DEV_DIEPMSK_TMOMSK_E_MSK 0x0
64996 /*
64997  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_TMOMSK
64998  *
64999  * No Mask Timeout Condition Interrupt
65000  */
65001 #define ALT_USB_DEV_DIEPMSK_TMOMSK_E_NOMSK 0x1
65002 
65003 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */
65004 #define ALT_USB_DEV_DIEPMSK_TMOMSK_LSB 3
65005 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */
65006 #define ALT_USB_DEV_DIEPMSK_TMOMSK_MSB 3
65007 /* The width in bits of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */
65008 #define ALT_USB_DEV_DIEPMSK_TMOMSK_WIDTH 1
65009 /* The mask used to set the ALT_USB_DEV_DIEPMSK_TMOMSK register field value. */
65010 #define ALT_USB_DEV_DIEPMSK_TMOMSK_SET_MSK 0x00000008
65011 /* The mask used to clear the ALT_USB_DEV_DIEPMSK_TMOMSK register field value. */
65012 #define ALT_USB_DEV_DIEPMSK_TMOMSK_CLR_MSK 0xfffffff7
65013 /* The reset value of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */
65014 #define ALT_USB_DEV_DIEPMSK_TMOMSK_RESET 0x0
65015 /* Extracts the ALT_USB_DEV_DIEPMSK_TMOMSK field value from a register. */
65016 #define ALT_USB_DEV_DIEPMSK_TMOMSK_GET(value) (((value) & 0x00000008) >> 3)
65017 /* Produces a ALT_USB_DEV_DIEPMSK_TMOMSK register field value suitable for setting the register. */
65018 #define ALT_USB_DEV_DIEPMSK_TMOMSK_SET(value) (((value) << 3) & 0x00000008)
65019 
65020 /*
65021  * Field : intkntxfempmsk
65022  *
65023  * IN Token Received When TxFIFO Empty Mask
65024  *
65025  * (INTknTXFEmpMsk)
65026  *
65027  * Field Enumeration Values:
65028  *
65029  * Enum | Value | Description
65030  * :-------------------------------------------|:------|:--------------------------------------------
65031  * ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_MSK | 0x0 | Mask IN Token Received When TxFIFO Empty
65032  * : | | Interrupt
65033  * ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_NOMSK | 0x1 | No Mask IN Token Received When TxFIFO Empty
65034  * : | | Interrupt
65035  *
65036  * Field Access Macros:
65037  *
65038  */
65039 /*
65040  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK
65041  *
65042  * Mask IN Token Received When TxFIFO Empty Interrupt
65043  */
65044 #define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_MSK 0x0
65045 /*
65046  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK
65047  *
65048  * No Mask IN Token Received When TxFIFO Empty Interrupt
65049  */
65050 #define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_NOMSK 0x1
65051 
65052 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */
65053 #define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_LSB 4
65054 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */
65055 #define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_MSB 4
65056 /* The width in bits of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */
65057 #define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_WIDTH 1
65058 /* The mask used to set the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field value. */
65059 #define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_SET_MSK 0x00000010
65060 /* The mask used to clear the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field value. */
65061 #define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_CLR_MSK 0xffffffef
65062 /* The reset value of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */
65063 #define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_RESET 0x0
65064 /* Extracts the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK field value from a register. */
65065 #define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_GET(value) (((value) & 0x00000010) >> 4)
65066 /* Produces a ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field value suitable for setting the register. */
65067 #define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_SET(value) (((value) << 4) & 0x00000010)
65068 
65069 /*
65070  * Field : intknepmismsk
65071  *
65072  * IN Token received with EP Mismatch Mask (INTknEPMisMsk)
65073  *
65074  * Field Enumeration Values:
65075  *
65076  * Enum | Value | Description
65077  * :------------------------------------------|:------|:-------------------------------------------
65078  * ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_MSK | 0x0 | Mask IN Token received with EP Mismatch
65079  * : | | Interrupt
65080  * ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_NOMSK | 0x1 | No Mask IN Token received with EP Mismatch
65081  * : | | Interrupt
65082  *
65083  * Field Access Macros:
65084  *
65085  */
65086 /*
65087  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK
65088  *
65089  * Mask IN Token received with EP Mismatch Interrupt
65090  */
65091 #define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_MSK 0x0
65092 /*
65093  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK
65094  *
65095  * No Mask IN Token received with EP Mismatch Interrupt
65096  */
65097 #define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_NOMSK 0x1
65098 
65099 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */
65100 #define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_LSB 5
65101 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */
65102 #define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_MSB 5
65103 /* The width in bits of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */
65104 #define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_WIDTH 1
65105 /* The mask used to set the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field value. */
65106 #define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_SET_MSK 0x00000020
65107 /* The mask used to clear the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field value. */
65108 #define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_CLR_MSK 0xffffffdf
65109 /* The reset value of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */
65110 #define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_RESET 0x0
65111 /* Extracts the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK field value from a register. */
65112 #define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_GET(value) (((value) & 0x00000020) >> 5)
65113 /* Produces a ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field value suitable for setting the register. */
65114 #define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_SET(value) (((value) << 5) & 0x00000020)
65115 
65116 /*
65117  * Field : inepnakeffmsk
65118  *
65119  * IN Endpoint NAK Effective Mask (INEPNakEffMsk)
65120  *
65121  * Field Enumeration Values:
65122  *
65123  * Enum | Value | Description
65124  * :------------------------------------------|:------|:--------------------------------------------
65125  * ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_MSK | 0x0 | Mask IN Endpoint NAK Effective Interrupt
65126  * ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_NOMSK | 0x1 | No Mask IN Endpoint NAK Effective Interrupt
65127  *
65128  * Field Access Macros:
65129  *
65130  */
65131 /*
65132  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK
65133  *
65134  * Mask IN Endpoint NAK Effective Interrupt
65135  */
65136 #define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_MSK 0x0
65137 /*
65138  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK
65139  *
65140  * No Mask IN Endpoint NAK Effective Interrupt
65141  */
65142 #define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_NOMSK 0x1
65143 
65144 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */
65145 #define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_LSB 6
65146 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */
65147 #define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_MSB 6
65148 /* The width in bits of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */
65149 #define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_WIDTH 1
65150 /* The mask used to set the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field value. */
65151 #define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_SET_MSK 0x00000040
65152 /* The mask used to clear the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field value. */
65153 #define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_CLR_MSK 0xffffffbf
65154 /* The reset value of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */
65155 #define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_RESET 0x0
65156 /* Extracts the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK field value from a register. */
65157 #define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_GET(value) (((value) & 0x00000040) >> 6)
65158 /* Produces a ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field value suitable for setting the register. */
65159 #define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_SET(value) (((value) << 6) & 0x00000040)
65160 
65161 /*
65162  * Field : txfifoundrnmsk
65163  *
65164  * Fifo Underrun Mask (TxfifoUndrnMsk)
65165  *
65166  * Field Enumeration Values:
65167  *
65168  * Enum | Value | Description
65169  * :-------------------------------------------|:------|:--------------------------------
65170  * ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_MSK | 0x0 | Mask Fifo Underrun Interrupt
65171  * ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_NOMSK | 0x1 | No Mask Fifo Underrun Interrupt
65172  *
65173  * Field Access Macros:
65174  *
65175  */
65176 /*
65177  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK
65178  *
65179  * Mask Fifo Underrun Interrupt
65180  */
65181 #define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_MSK 0x0
65182 /*
65183  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK
65184  *
65185  * No Mask Fifo Underrun Interrupt
65186  */
65187 #define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_NOMSK 0x1
65188 
65189 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */
65190 #define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_LSB 8
65191 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */
65192 #define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_MSB 8
65193 /* The width in bits of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */
65194 #define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_WIDTH 1
65195 /* The mask used to set the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field value. */
65196 #define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_SET_MSK 0x00000100
65197 /* The mask used to clear the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field value. */
65198 #define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_CLR_MSK 0xfffffeff
65199 /* The reset value of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */
65200 #define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_RESET 0x0
65201 /* Extracts the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK field value from a register. */
65202 #define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_GET(value) (((value) & 0x00000100) >> 8)
65203 /* Produces a ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field value suitable for setting the register. */
65204 #define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_SET(value) (((value) << 8) & 0x00000100)
65205 
65206 /*
65207  * Field : bnainintrmsk
65208  *
65209  * BNA interrupt Mask (BNAInIntrMsk)
65210  *
65211  * Field Enumeration Values:
65212  *
65213  * Enum | Value | Description
65214  * :-----------------------------------------|:------|:----------------------
65215  * ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_MSK | 0x0 | Mask BNA Interrupt
65216  * ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_NOMSK | 0x1 | No Mask BNA Interrupt
65217  *
65218  * Field Access Macros:
65219  *
65220  */
65221 /*
65222  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_BNAININTRMSK
65223  *
65224  * Mask BNA Interrupt
65225  */
65226 #define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_MSK 0x0
65227 /*
65228  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_BNAININTRMSK
65229  *
65230  * No Mask BNA Interrupt
65231  */
65232 #define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_NOMSK 0x1
65233 
65234 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */
65235 #define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_LSB 9
65236 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */
65237 #define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_MSB 9
65238 /* The width in bits of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */
65239 #define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_WIDTH 1
65240 /* The mask used to set the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field value. */
65241 #define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_SET_MSK 0x00000200
65242 /* The mask used to clear the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field value. */
65243 #define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_CLR_MSK 0xfffffdff
65244 /* The reset value of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */
65245 #define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_RESET 0x0
65246 /* Extracts the ALT_USB_DEV_DIEPMSK_BNAININTRMSK field value from a register. */
65247 #define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_GET(value) (((value) & 0x00000200) >> 9)
65248 /* Produces a ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field value suitable for setting the register. */
65249 #define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_SET(value) (((value) << 9) & 0x00000200)
65250 
65251 /*
65252  * Field : nakmsk
65253  *
65254  * NAK interrupt Mask (NAKMsk)
65255  *
65256  * Field Enumeration Values:
65257  *
65258  * Enum | Value | Description
65259  * :-----------------------------------|:------|:----------------------
65260  * ALT_USB_DEV_DIEPMSK_NAKMSK_E_MSK | 0x0 | Mask NAK Interrupt
65261  * ALT_USB_DEV_DIEPMSK_NAKMSK_E_NOMSK | 0x1 | No Mask NAK Interrupt
65262  *
65263  * Field Access Macros:
65264  *
65265  */
65266 /*
65267  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_NAKMSK
65268  *
65269  * Mask NAK Interrupt
65270  */
65271 #define ALT_USB_DEV_DIEPMSK_NAKMSK_E_MSK 0x0
65272 /*
65273  * Enumerated value for register field ALT_USB_DEV_DIEPMSK_NAKMSK
65274  *
65275  * No Mask NAK Interrupt
65276  */
65277 #define ALT_USB_DEV_DIEPMSK_NAKMSK_E_NOMSK 0x1
65278 
65279 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */
65280 #define ALT_USB_DEV_DIEPMSK_NAKMSK_LSB 13
65281 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */
65282 #define ALT_USB_DEV_DIEPMSK_NAKMSK_MSB 13
65283 /* The width in bits of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */
65284 #define ALT_USB_DEV_DIEPMSK_NAKMSK_WIDTH 1
65285 /* The mask used to set the ALT_USB_DEV_DIEPMSK_NAKMSK register field value. */
65286 #define ALT_USB_DEV_DIEPMSK_NAKMSK_SET_MSK 0x00002000
65287 /* The mask used to clear the ALT_USB_DEV_DIEPMSK_NAKMSK register field value. */
65288 #define ALT_USB_DEV_DIEPMSK_NAKMSK_CLR_MSK 0xffffdfff
65289 /* The reset value of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */
65290 #define ALT_USB_DEV_DIEPMSK_NAKMSK_RESET 0x0
65291 /* Extracts the ALT_USB_DEV_DIEPMSK_NAKMSK field value from a register. */
65292 #define ALT_USB_DEV_DIEPMSK_NAKMSK_GET(value) (((value) & 0x00002000) >> 13)
65293 /* Produces a ALT_USB_DEV_DIEPMSK_NAKMSK register field value suitable for setting the register. */
65294 #define ALT_USB_DEV_DIEPMSK_NAKMSK_SET(value) (((value) << 13) & 0x00002000)
65295 
65296 #ifndef __ASSEMBLY__
65297 /*
65298  * WARNING: The C register and register group struct declarations are provided for
65299  * convenience and illustrative purposes. They should, however, be used with
65300  * caution as the C language standard provides no guarantees about the alignment or
65301  * atomicity of device memory accesses. The recommended practice for writing
65302  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65303  * alt_write_word() functions.
65304  *
65305  * The struct declaration for register ALT_USB_DEV_DIEPMSK.
65306  */
65307 struct ALT_USB_DEV_DIEPMSK_s
65308 {
65309  uint32_t xfercomplmsk : 1; /* ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK */
65310  uint32_t epdisbldmsk : 1; /* ALT_USB_DEV_DIEPMSK_EPDISBLDMSK */
65311  uint32_t ahberrmsk : 1; /* ALT_USB_DEV_DIEPMSK_AHBERRMSK */
65312  uint32_t timeoutmsk : 1; /* ALT_USB_DEV_DIEPMSK_TMOMSK */
65313  uint32_t intkntxfempmsk : 1; /* ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK */
65314  uint32_t intknepmismsk : 1; /* ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK */
65315  uint32_t inepnakeffmsk : 1; /* ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK */
65316  uint32_t : 1; /* *UNDEFINED* */
65317  uint32_t txfifoundrnmsk : 1; /* ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK */
65318  uint32_t bnainintrmsk : 1; /* ALT_USB_DEV_DIEPMSK_BNAININTRMSK */
65319  uint32_t : 3; /* *UNDEFINED* */
65320  uint32_t nakmsk : 1; /* ALT_USB_DEV_DIEPMSK_NAKMSK */
65321  uint32_t : 18; /* *UNDEFINED* */
65322 };
65323 
65324 /* The typedef declaration for register ALT_USB_DEV_DIEPMSK. */
65325 typedef volatile struct ALT_USB_DEV_DIEPMSK_s ALT_USB_DEV_DIEPMSK_t;
65326 #endif /* __ASSEMBLY__ */
65327 
65328 /* The reset value of the ALT_USB_DEV_DIEPMSK register. */
65329 #define ALT_USB_DEV_DIEPMSK_RESET 0x00000000
65330 /* The byte offset of the ALT_USB_DEV_DIEPMSK register from the beginning of the component. */
65331 #define ALT_USB_DEV_DIEPMSK_OFST 0x10
65332 /* The address of the ALT_USB_DEV_DIEPMSK register. */
65333 #define ALT_USB_DEV_DIEPMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPMSK_OFST))
65334 
65335 /*
65336  * Register : doepmsk
65337  *
65338  * Device OUT Endpoint Common Interrupt Mask Register
65339  *
65340  * Register Layout
65341  *
65342  * Bits | Access | Reset | Description
65343  * :--------|:-------|:------|:-----------------------------------
65344  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK
65345  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_EPDISBLDMSK
65346  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_AHBERRMSK
65347  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_SETUPMSK
65348  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK
65349  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK
65350  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP
65351  * [7] | ??? | 0x0 | *UNDEFINED*
65352  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK
65353  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK
65354  * [11:10] | ??? | 0x0 | *UNDEFINED*
65355  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_BBLEERRMSK
65356  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_NAKMSK
65357  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_NYETMSK
65358  * [31:15] | ??? | 0x0 | *UNDEFINED*
65359  *
65360  */
65361 /*
65362  * Field : xfercomplmsk
65363  *
65364  * Transfer Completed Interrupt Mask (XferComplMsk)
65365  *
65366  * Field Enumeration Values:
65367  *
65368  * Enum | Value | Description
65369  * :-----------------------------------------|:------|:-------------------------------------
65370  * ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_MSK | 0x0 | Mask Transfer Completed Interrupt
65371  * ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_NOMSK | 0x1 | No Mask Transfer Completed Interrupt
65372  *
65373  * Field Access Macros:
65374  *
65375  */
65376 /*
65377  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK
65378  *
65379  * Mask Transfer Completed Interrupt
65380  */
65381 #define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_MSK 0x0
65382 /*
65383  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK
65384  *
65385  * No Mask Transfer Completed Interrupt
65386  */
65387 #define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_NOMSK 0x1
65388 
65389 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */
65390 #define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_LSB 0
65391 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */
65392 #define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_MSB 0
65393 /* The width in bits of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */
65394 #define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_WIDTH 1
65395 /* The mask used to set the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field value. */
65396 #define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_SET_MSK 0x00000001
65397 /* The mask used to clear the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field value. */
65398 #define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_CLR_MSK 0xfffffffe
65399 /* The reset value of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */
65400 #define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_RESET 0x0
65401 /* Extracts the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK field value from a register. */
65402 #define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
65403 /* Produces a ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field value suitable for setting the register. */
65404 #define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
65405 
65406 /*
65407  * Field : epdisbldmsk
65408  *
65409  * Endpoint Disabled Interrupt Mask (EPDisbldMsk)
65410  *
65411  * Field Enumeration Values:
65412  *
65413  * Enum | Value | Description
65414  * :----------------------------------------|:------|:------------------------------------
65415  * ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_MSK | 0x0 | Mask Endpoint Disabled Interrupt
65416  * ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_NOMSK | 0x1 | No Mask Endpoint Disabled Interrupt
65417  *
65418  * Field Access Macros:
65419  *
65420  */
65421 /*
65422  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_EPDISBLDMSK
65423  *
65424  * Mask Endpoint Disabled Interrupt
65425  */
65426 #define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_MSK 0x0
65427 /*
65428  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_EPDISBLDMSK
65429  *
65430  * No Mask Endpoint Disabled Interrupt
65431  */
65432 #define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_NOMSK 0x1
65433 
65434 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */
65435 #define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_LSB 1
65436 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */
65437 #define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_MSB 1
65438 /* The width in bits of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */
65439 #define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_WIDTH 1
65440 /* The mask used to set the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field value. */
65441 #define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_SET_MSK 0x00000002
65442 /* The mask used to clear the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field value. */
65443 #define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_CLR_MSK 0xfffffffd
65444 /* The reset value of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */
65445 #define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_RESET 0x0
65446 /* Extracts the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK field value from a register. */
65447 #define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_GET(value) (((value) & 0x00000002) >> 1)
65448 /* Produces a ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field value suitable for setting the register. */
65449 #define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_SET(value) (((value) << 1) & 0x00000002)
65450 
65451 /*
65452  * Field : ahberrmsk
65453  *
65454  * AHB Error (AHBErrMsk)
65455  *
65456  * Field Enumeration Values:
65457  *
65458  * Enum | Value | Description
65459  * :--------------------------------------|:------|:-----------------------------
65460  * ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_MSK | 0x0 | Mask AHB Error Interrupt
65461  * ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_NOMSK | 0x1 | No Mask AHB Error Interrupt
65462  *
65463  * Field Access Macros:
65464  *
65465  */
65466 /*
65467  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_AHBERRMSK
65468  *
65469  * Mask AHB Error Interrupt
65470  */
65471 #define ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_MSK 0x0
65472 /*
65473  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_AHBERRMSK
65474  *
65475  * No Mask AHB Error Interrupt
65476  */
65477 #define ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_NOMSK 0x1
65478 
65479 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */
65480 #define ALT_USB_DEV_DOEPMSK_AHBERRMSK_LSB 2
65481 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */
65482 #define ALT_USB_DEV_DOEPMSK_AHBERRMSK_MSB 2
65483 /* The width in bits of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */
65484 #define ALT_USB_DEV_DOEPMSK_AHBERRMSK_WIDTH 1
65485 /* The mask used to set the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field value. */
65486 #define ALT_USB_DEV_DOEPMSK_AHBERRMSK_SET_MSK 0x00000004
65487 /* The mask used to clear the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field value. */
65488 #define ALT_USB_DEV_DOEPMSK_AHBERRMSK_CLR_MSK 0xfffffffb
65489 /* The reset value of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */
65490 #define ALT_USB_DEV_DOEPMSK_AHBERRMSK_RESET 0x0
65491 /* Extracts the ALT_USB_DEV_DOEPMSK_AHBERRMSK field value from a register. */
65492 #define ALT_USB_DEV_DOEPMSK_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
65493 /* Produces a ALT_USB_DEV_DOEPMSK_AHBERRMSK register field value suitable for setting the register. */
65494 #define ALT_USB_DEV_DOEPMSK_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
65495 
65496 /*
65497  * Field : setupmsk
65498  *
65499  * SETUP Phase Done Mask (SetUPMsk)
65500  *
65501  * Applies to control endpoints only.
65502  *
65503  * Field Enumeration Values:
65504  *
65505  * Enum | Value | Description
65506  * :-------------------------------------|:------|:-----------------------------------
65507  * ALT_USB_DEV_DOEPMSK_SETUPMSK_E_MSK | 0x0 | Mask SETUP Phase Done Interrupt
65508  * ALT_USB_DEV_DOEPMSK_SETUPMSK_E_NOMSK | 0x1 | No Mask SETUP Phase Done Interrupt
65509  *
65510  * Field Access Macros:
65511  *
65512  */
65513 /*
65514  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_SETUPMSK
65515  *
65516  * Mask SETUP Phase Done Interrupt
65517  */
65518 #define ALT_USB_DEV_DOEPMSK_SETUPMSK_E_MSK 0x0
65519 /*
65520  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_SETUPMSK
65521  *
65522  * No Mask SETUP Phase Done Interrupt
65523  */
65524 #define ALT_USB_DEV_DOEPMSK_SETUPMSK_E_NOMSK 0x1
65525 
65526 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */
65527 #define ALT_USB_DEV_DOEPMSK_SETUPMSK_LSB 3
65528 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */
65529 #define ALT_USB_DEV_DOEPMSK_SETUPMSK_MSB 3
65530 /* The width in bits of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */
65531 #define ALT_USB_DEV_DOEPMSK_SETUPMSK_WIDTH 1
65532 /* The mask used to set the ALT_USB_DEV_DOEPMSK_SETUPMSK register field value. */
65533 #define ALT_USB_DEV_DOEPMSK_SETUPMSK_SET_MSK 0x00000008
65534 /* The mask used to clear the ALT_USB_DEV_DOEPMSK_SETUPMSK register field value. */
65535 #define ALT_USB_DEV_DOEPMSK_SETUPMSK_CLR_MSK 0xfffffff7
65536 /* The reset value of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */
65537 #define ALT_USB_DEV_DOEPMSK_SETUPMSK_RESET 0x0
65538 /* Extracts the ALT_USB_DEV_DOEPMSK_SETUPMSK field value from a register. */
65539 #define ALT_USB_DEV_DOEPMSK_SETUPMSK_GET(value) (((value) & 0x00000008) >> 3)
65540 /* Produces a ALT_USB_DEV_DOEPMSK_SETUPMSK register field value suitable for setting the register. */
65541 #define ALT_USB_DEV_DOEPMSK_SETUPMSK_SET(value) (((value) << 3) & 0x00000008)
65542 
65543 /*
65544  * Field : outtknepdismsk
65545  *
65546  * OUT Token Received when Endpoint Disabled Mask
65547  *
65548  * (OUTTknEPdisMsk)
65549  *
65550  * Applies to control OUT endpoints only.
65551  *
65552  * Field Enumeration Values:
65553  *
65554  * Enum | Value | Description
65555  * :-------------------------------------------|:------|:-----------------------------------------------
65556  * ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_MSK | 0x0 | Mask OUT Token Received when Endpoint Disabled
65557  * : | | Interrupt
65558  * ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_NOMSK | 0x1 | No Mask OUT Token Received when Endpoint
65559  * : | | Disabled Interrupt
65560  *
65561  * Field Access Macros:
65562  *
65563  */
65564 /*
65565  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK
65566  *
65567  * Mask OUT Token Received when Endpoint Disabled Interrupt
65568  */
65569 #define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_MSK 0x0
65570 /*
65571  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK
65572  *
65573  * No Mask OUT Token Received when Endpoint Disabled Interrupt
65574  */
65575 #define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_NOMSK 0x1
65576 
65577 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */
65578 #define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_LSB 4
65579 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */
65580 #define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_MSB 4
65581 /* The width in bits of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */
65582 #define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_WIDTH 1
65583 /* The mask used to set the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field value. */
65584 #define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_SET_MSK 0x00000010
65585 /* The mask used to clear the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field value. */
65586 #define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_CLR_MSK 0xffffffef
65587 /* The reset value of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */
65588 #define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_RESET 0x0
65589 /* Extracts the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK field value from a register. */
65590 #define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_GET(value) (((value) & 0x00000010) >> 4)
65591 /* Produces a ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field value suitable for setting the register. */
65592 #define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_SET(value) (((value) << 4) & 0x00000010)
65593 
65594 /*
65595  * Field : stsphsercvdmsk
65596  *
65597  * Status Phase Received Mask
65598  *
65599  * (StsPhseRcvdMsk)
65600  *
65601  * Applies to control OUT endpoints only.
65602  *
65603  * Field Access Macros:
65604  *
65605  */
65606 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field. */
65607 #define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_LSB 5
65608 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field. */
65609 #define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_MSB 5
65610 /* The width in bits of the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field. */
65611 #define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_WIDTH 1
65612 /* The mask used to set the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field value. */
65613 #define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_SET_MSK 0x00000020
65614 /* The mask used to clear the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field value. */
65615 #define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_CLR_MSK 0xffffffdf
65616 /* The reset value of the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field. */
65617 #define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_RESET 0x0
65618 /* Extracts the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK field value from a register. */
65619 #define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_GET(value) (((value) & 0x00000020) >> 5)
65620 /* Produces a ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field value suitable for setting the register. */
65621 #define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_SET(value) (((value) << 5) & 0x00000020)
65622 
65623 /*
65624  * Field : back2backsetup
65625  *
65626  * Back-to-Back SETUP Packets Received Mask
65627  *
65628  * (Back2BackSETup)
65629  *
65630  * Applies to control OUT endpoints only.
65631  *
65632  * Field Enumeration Values:
65633  *
65634  * Enum | Value | Description
65635  * :-------------------------------------------|:------|:--------------------------------------------
65636  * ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_MSK | 0x0 | Mask Back-to-Back SETUP Packets Received
65637  * : | | Interrupt
65638  * ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_NOMSK | 0x1 | No Mask Back-to-Back SETUP Packets Received
65639  * : | | Interrupt
65640  *
65641  * Field Access Macros:
65642  *
65643  */
65644 /*
65645  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP
65646  *
65647  * Mask Back-to-Back SETUP Packets Received Interrupt
65648  */
65649 #define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_MSK 0x0
65650 /*
65651  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP
65652  *
65653  * No Mask Back-to-Back SETUP Packets Received Interrupt
65654  */
65655 #define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_NOMSK 0x1
65656 
65657 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */
65658 #define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_LSB 6
65659 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */
65660 #define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_MSB 6
65661 /* The width in bits of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */
65662 #define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_WIDTH 1
65663 /* The mask used to set the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field value. */
65664 #define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_SET_MSK 0x00000040
65665 /* The mask used to clear the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field value. */
65666 #define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_CLR_MSK 0xffffffbf
65667 /* The reset value of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */
65668 #define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_RESET 0x0
65669 /* Extracts the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP field value from a register. */
65670 #define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
65671 /* Produces a ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field value suitable for setting the register. */
65672 #define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
65673 
65674 /*
65675  * Field : outpkterrmsk
65676  *
65677  * OUT Packet Error Mask (OutPktErrMsk)
65678  *
65679  * Field Enumeration Values:
65680  *
65681  * Enum | Value | Description
65682  * :-----------------------------------------|:------|:-----------------------------------
65683  * ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_MSK | 0x0 | Mask OUT Packet Error Interrupt
65684  * ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_NOMSK | 0x1 | No Mask OUT Packet Error Interrupt
65685  *
65686  * Field Access Macros:
65687  *
65688  */
65689 /*
65690  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK
65691  *
65692  * Mask OUT Packet Error Interrupt
65693  */
65694 #define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_MSK 0x0
65695 /*
65696  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK
65697  *
65698  * No Mask OUT Packet Error Interrupt
65699  */
65700 #define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_NOMSK 0x1
65701 
65702 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */
65703 #define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_LSB 8
65704 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */
65705 #define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_MSB 8
65706 /* The width in bits of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */
65707 #define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_WIDTH 1
65708 /* The mask used to set the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field value. */
65709 #define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_SET_MSK 0x00000100
65710 /* The mask used to clear the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field value. */
65711 #define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_CLR_MSK 0xfffffeff
65712 /* The reset value of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */
65713 #define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_RESET 0x0
65714 /* Extracts the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK field value from a register. */
65715 #define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_GET(value) (((value) & 0x00000100) >> 8)
65716 /* Produces a ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field value suitable for setting the register. */
65717 #define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_SET(value) (((value) << 8) & 0x00000100)
65718 
65719 /*
65720  * Field : bnaoutintrmsk
65721  *
65722  * BNA interrupt Mask (BnaOutIntrMsk)
65723  *
65724  * Field Enumeration Values:
65725  *
65726  * Enum | Value | Description
65727  * :------------------------------------------|:------|:----------------------
65728  * ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_MSK | 0x0 | Mask BNA Interrupt
65729  * ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_NOMSK | 0x1 | No Mask BNA Interrupt
65730  *
65731  * Field Access Macros:
65732  *
65733  */
65734 /*
65735  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK
65736  *
65737  * Mask BNA Interrupt
65738  */
65739 #define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_MSK 0x0
65740 /*
65741  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK
65742  *
65743  * No Mask BNA Interrupt
65744  */
65745 #define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_NOMSK 0x1
65746 
65747 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */
65748 #define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_LSB 9
65749 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */
65750 #define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_MSB 9
65751 /* The width in bits of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */
65752 #define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_WIDTH 1
65753 /* The mask used to set the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field value. */
65754 #define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_SET_MSK 0x00000200
65755 /* The mask used to clear the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field value. */
65756 #define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_CLR_MSK 0xfffffdff
65757 /* The reset value of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */
65758 #define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_RESET 0x0
65759 /* Extracts the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK field value from a register. */
65760 #define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_GET(value) (((value) & 0x00000200) >> 9)
65761 /* Produces a ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field value suitable for setting the register. */
65762 #define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_SET(value) (((value) << 9) & 0x00000200)
65763 
65764 /*
65765  * Field : bbleerrmsk
65766  *
65767  * Babble Error interrupt Mask (BbleErrMsk)
65768  *
65769  * Field Enumeration Values:
65770  *
65771  * Enum | Value | Description
65772  * :---------------------------------------|:------|:-------------------------------
65773  * ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_MSK | 0x0 | Mask Babble Error Interrupt
65774  * ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_NOMSK | 0x1 | No Mask Babble Error Interrupt
65775  *
65776  * Field Access Macros:
65777  *
65778  */
65779 /*
65780  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BBLEERRMSK
65781  *
65782  * Mask Babble Error Interrupt
65783  */
65784 #define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_MSK 0x0
65785 /*
65786  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_BBLEERRMSK
65787  *
65788  * No Mask Babble Error Interrupt
65789  */
65790 #define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_NOMSK 0x1
65791 
65792 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */
65793 #define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_LSB 12
65794 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */
65795 #define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_MSB 12
65796 /* The width in bits of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */
65797 #define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_WIDTH 1
65798 /* The mask used to set the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field value. */
65799 #define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_SET_MSK 0x00001000
65800 /* The mask used to clear the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field value. */
65801 #define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_CLR_MSK 0xffffefff
65802 /* The reset value of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */
65803 #define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_RESET 0x0
65804 /* Extracts the ALT_USB_DEV_DOEPMSK_BBLEERRMSK field value from a register. */
65805 #define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_GET(value) (((value) & 0x00001000) >> 12)
65806 /* Produces a ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field value suitable for setting the register. */
65807 #define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_SET(value) (((value) << 12) & 0x00001000)
65808 
65809 /*
65810  * Field : nakmsk
65811  *
65812  * NAK interrupt Mask (NAKMsk)
65813  *
65814  * Field Enumeration Values:
65815  *
65816  * Enum | Value | Description
65817  * :-----------------------------------|:------|:----------------------
65818  * ALT_USB_DEV_DOEPMSK_NAKMSK_E_MSK | 0x0 | Mask NAK Interrupt
65819  * ALT_USB_DEV_DOEPMSK_NAKMSK_E_NOMSK | 0x1 | No Mask NAK Interrupt
65820  *
65821  * Field Access Macros:
65822  *
65823  */
65824 /*
65825  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_NAKMSK
65826  *
65827  * Mask NAK Interrupt
65828  */
65829 #define ALT_USB_DEV_DOEPMSK_NAKMSK_E_MSK 0x0
65830 /*
65831  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_NAKMSK
65832  *
65833  * No Mask NAK Interrupt
65834  */
65835 #define ALT_USB_DEV_DOEPMSK_NAKMSK_E_NOMSK 0x1
65836 
65837 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */
65838 #define ALT_USB_DEV_DOEPMSK_NAKMSK_LSB 13
65839 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */
65840 #define ALT_USB_DEV_DOEPMSK_NAKMSK_MSB 13
65841 /* The width in bits of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */
65842 #define ALT_USB_DEV_DOEPMSK_NAKMSK_WIDTH 1
65843 /* The mask used to set the ALT_USB_DEV_DOEPMSK_NAKMSK register field value. */
65844 #define ALT_USB_DEV_DOEPMSK_NAKMSK_SET_MSK 0x00002000
65845 /* The mask used to clear the ALT_USB_DEV_DOEPMSK_NAKMSK register field value. */
65846 #define ALT_USB_DEV_DOEPMSK_NAKMSK_CLR_MSK 0xffffdfff
65847 /* The reset value of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */
65848 #define ALT_USB_DEV_DOEPMSK_NAKMSK_RESET 0x0
65849 /* Extracts the ALT_USB_DEV_DOEPMSK_NAKMSK field value from a register. */
65850 #define ALT_USB_DEV_DOEPMSK_NAKMSK_GET(value) (((value) & 0x00002000) >> 13)
65851 /* Produces a ALT_USB_DEV_DOEPMSK_NAKMSK register field value suitable for setting the register. */
65852 #define ALT_USB_DEV_DOEPMSK_NAKMSK_SET(value) (((value) << 13) & 0x00002000)
65853 
65854 /*
65855  * Field : nyetmsk
65856  *
65857  * NYET interrupt Mask (NYETMsk)
65858  *
65859  * Field Enumeration Values:
65860  *
65861  * Enum | Value | Description
65862  * :------------------------------------|:------|:-----------------------
65863  * ALT_USB_DEV_DOEPMSK_NYETMSK_E_MSK | 0x0 | Mask NYET Interrupt
65864  * ALT_USB_DEV_DOEPMSK_NYETMSK_E_NOMSK | 0x1 | No Mask NYET Interrupt
65865  *
65866  * Field Access Macros:
65867  *
65868  */
65869 /*
65870  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_NYETMSK
65871  *
65872  * Mask NYET Interrupt
65873  */
65874 #define ALT_USB_DEV_DOEPMSK_NYETMSK_E_MSK 0x0
65875 /*
65876  * Enumerated value for register field ALT_USB_DEV_DOEPMSK_NYETMSK
65877  *
65878  * No Mask NYET Interrupt
65879  */
65880 #define ALT_USB_DEV_DOEPMSK_NYETMSK_E_NOMSK 0x1
65881 
65882 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */
65883 #define ALT_USB_DEV_DOEPMSK_NYETMSK_LSB 14
65884 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */
65885 #define ALT_USB_DEV_DOEPMSK_NYETMSK_MSB 14
65886 /* The width in bits of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */
65887 #define ALT_USB_DEV_DOEPMSK_NYETMSK_WIDTH 1
65888 /* The mask used to set the ALT_USB_DEV_DOEPMSK_NYETMSK register field value. */
65889 #define ALT_USB_DEV_DOEPMSK_NYETMSK_SET_MSK 0x00004000
65890 /* The mask used to clear the ALT_USB_DEV_DOEPMSK_NYETMSK register field value. */
65891 #define ALT_USB_DEV_DOEPMSK_NYETMSK_CLR_MSK 0xffffbfff
65892 /* The reset value of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */
65893 #define ALT_USB_DEV_DOEPMSK_NYETMSK_RESET 0x0
65894 /* Extracts the ALT_USB_DEV_DOEPMSK_NYETMSK field value from a register. */
65895 #define ALT_USB_DEV_DOEPMSK_NYETMSK_GET(value) (((value) & 0x00004000) >> 14)
65896 /* Produces a ALT_USB_DEV_DOEPMSK_NYETMSK register field value suitable for setting the register. */
65897 #define ALT_USB_DEV_DOEPMSK_NYETMSK_SET(value) (((value) << 14) & 0x00004000)
65898 
65899 #ifndef __ASSEMBLY__
65900 /*
65901  * WARNING: The C register and register group struct declarations are provided for
65902  * convenience and illustrative purposes. They should, however, be used with
65903  * caution as the C language standard provides no guarantees about the alignment or
65904  * atomicity of device memory accesses. The recommended practice for writing
65905  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65906  * alt_write_word() functions.
65907  *
65908  * The struct declaration for register ALT_USB_DEV_DOEPMSK.
65909  */
65910 struct ALT_USB_DEV_DOEPMSK_s
65911 {
65912  uint32_t xfercomplmsk : 1; /* ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK */
65913  uint32_t epdisbldmsk : 1; /* ALT_USB_DEV_DOEPMSK_EPDISBLDMSK */
65914  uint32_t ahberrmsk : 1; /* ALT_USB_DEV_DOEPMSK_AHBERRMSK */
65915  uint32_t setupmsk : 1; /* ALT_USB_DEV_DOEPMSK_SETUPMSK */
65916  uint32_t outtknepdismsk : 1; /* ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK */
65917  uint32_t stsphsercvdmsk : 1; /* ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK */
65918  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP */
65919  uint32_t : 1; /* *UNDEFINED* */
65920  uint32_t outpkterrmsk : 1; /* ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK */
65921  uint32_t bnaoutintrmsk : 1; /* ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK */
65922  uint32_t : 2; /* *UNDEFINED* */
65923  uint32_t bbleerrmsk : 1; /* ALT_USB_DEV_DOEPMSK_BBLEERRMSK */
65924  uint32_t nakmsk : 1; /* ALT_USB_DEV_DOEPMSK_NAKMSK */
65925  uint32_t nyetmsk : 1; /* ALT_USB_DEV_DOEPMSK_NYETMSK */
65926  uint32_t : 17; /* *UNDEFINED* */
65927 };
65928 
65929 /* The typedef declaration for register ALT_USB_DEV_DOEPMSK. */
65930 typedef volatile struct ALT_USB_DEV_DOEPMSK_s ALT_USB_DEV_DOEPMSK_t;
65931 #endif /* __ASSEMBLY__ */
65932 
65933 /* The reset value of the ALT_USB_DEV_DOEPMSK register. */
65934 #define ALT_USB_DEV_DOEPMSK_RESET 0x00000000
65935 /* The byte offset of the ALT_USB_DEV_DOEPMSK register from the beginning of the component. */
65936 #define ALT_USB_DEV_DOEPMSK_OFST 0x14
65937 /* The address of the ALT_USB_DEV_DOEPMSK register. */
65938 #define ALT_USB_DEV_DOEPMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPMSK_OFST))
65939 
65940 /*
65941  * Register : daint
65942  *
65943  * Device All Endpoints Interrupt Register
65944  *
65945  * Register Layout
65946  *
65947  * Bits | Access | Reset | Description
65948  * :-----|:-------|:------|:-----------------------------
65949  * [0] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT0
65950  * [1] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT1
65951  * [2] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT2
65952  * [3] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT3
65953  * [4] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT4
65954  * [5] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT5
65955  * [6] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT6
65956  * [7] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT7
65957  * [8] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT8
65958  * [9] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT9
65959  * [10] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT10
65960  * [11] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT11
65961  * [12] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT12
65962  * [13] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT13
65963  * [14] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT14
65964  * [15] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT15
65965  * [16] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT0
65966  * [17] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT1
65967  * [18] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT2
65968  * [19] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT3
65969  * [20] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT4
65970  * [21] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT5
65971  * [22] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT6
65972  * [23] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT7
65973  * [24] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT8
65974  * [25] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT9
65975  * [26] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT10
65976  * [27] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT11
65977  * [28] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT12
65978  * [29] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT13
65979  * [30] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT14
65980  * [31] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT15
65981  *
65982  */
65983 /*
65984  * Field : inepint0
65985  *
65986  * IN Endpoint 0 Interrupt Bit
65987  *
65988  * Field Enumeration Values:
65989  *
65990  * Enum | Value | Description
65991  * :-----------------------------------|:------|:------------------------
65992  * ALT_USB_DEV_DAINT_INEPINT0_E_INACT | 0x0 | No Interrupt
65993  * ALT_USB_DEV_DAINT_INEPINT0_E_ACT | 0x1 | IN Endpoint 0 Interrupt
65994  *
65995  * Field Access Macros:
65996  *
65997  */
65998 /*
65999  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT0
66000  *
66001  * No Interrupt
66002  */
66003 #define ALT_USB_DEV_DAINT_INEPINT0_E_INACT 0x0
66004 /*
66005  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT0
66006  *
66007  * IN Endpoint 0 Interrupt
66008  */
66009 #define ALT_USB_DEV_DAINT_INEPINT0_E_ACT 0x1
66010 
66011 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT0 register field. */
66012 #define ALT_USB_DEV_DAINT_INEPINT0_LSB 0
66013 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT0 register field. */
66014 #define ALT_USB_DEV_DAINT_INEPINT0_MSB 0
66015 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT0 register field. */
66016 #define ALT_USB_DEV_DAINT_INEPINT0_WIDTH 1
66017 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT0 register field value. */
66018 #define ALT_USB_DEV_DAINT_INEPINT0_SET_MSK 0x00000001
66019 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT0 register field value. */
66020 #define ALT_USB_DEV_DAINT_INEPINT0_CLR_MSK 0xfffffffe
66021 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT0 register field. */
66022 #define ALT_USB_DEV_DAINT_INEPINT0_RESET 0x0
66023 /* Extracts the ALT_USB_DEV_DAINT_INEPINT0 field value from a register. */
66024 #define ALT_USB_DEV_DAINT_INEPINT0_GET(value) (((value) & 0x00000001) >> 0)
66025 /* Produces a ALT_USB_DEV_DAINT_INEPINT0 register field value suitable for setting the register. */
66026 #define ALT_USB_DEV_DAINT_INEPINT0_SET(value) (((value) << 0) & 0x00000001)
66027 
66028 /*
66029  * Field : inepint1
66030  *
66031  * IN Endpoint 1 Interrupt Bit
66032  *
66033  * Field Enumeration Values:
66034  *
66035  * Enum | Value | Description
66036  * :-----------------------------------|:------|:------------------------
66037  * ALT_USB_DEV_DAINT_INEPINT1_E_INACT | 0x0 | No Interrupt
66038  * ALT_USB_DEV_DAINT_INEPINT1_E_ACT | 0x1 | IN Endpoint 1 Interrupt
66039  *
66040  * Field Access Macros:
66041  *
66042  */
66043 /*
66044  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT1
66045  *
66046  * No Interrupt
66047  */
66048 #define ALT_USB_DEV_DAINT_INEPINT1_E_INACT 0x0
66049 /*
66050  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT1
66051  *
66052  * IN Endpoint 1 Interrupt
66053  */
66054 #define ALT_USB_DEV_DAINT_INEPINT1_E_ACT 0x1
66055 
66056 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT1 register field. */
66057 #define ALT_USB_DEV_DAINT_INEPINT1_LSB 1
66058 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT1 register field. */
66059 #define ALT_USB_DEV_DAINT_INEPINT1_MSB 1
66060 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT1 register field. */
66061 #define ALT_USB_DEV_DAINT_INEPINT1_WIDTH 1
66062 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT1 register field value. */
66063 #define ALT_USB_DEV_DAINT_INEPINT1_SET_MSK 0x00000002
66064 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT1 register field value. */
66065 #define ALT_USB_DEV_DAINT_INEPINT1_CLR_MSK 0xfffffffd
66066 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT1 register field. */
66067 #define ALT_USB_DEV_DAINT_INEPINT1_RESET 0x0
66068 /* Extracts the ALT_USB_DEV_DAINT_INEPINT1 field value from a register. */
66069 #define ALT_USB_DEV_DAINT_INEPINT1_GET(value) (((value) & 0x00000002) >> 1)
66070 /* Produces a ALT_USB_DEV_DAINT_INEPINT1 register field value suitable for setting the register. */
66071 #define ALT_USB_DEV_DAINT_INEPINT1_SET(value) (((value) << 1) & 0x00000002)
66072 
66073 /*
66074  * Field : inepint2
66075  *
66076  * IN Endpoint 2 Interrupt Bit
66077  *
66078  * Field Enumeration Values:
66079  *
66080  * Enum | Value | Description
66081  * :-----------------------------------|:------|:------------------------
66082  * ALT_USB_DEV_DAINT_INEPINT2_E_INACT | 0x0 | No Interrupt
66083  * ALT_USB_DEV_DAINT_INEPINT2_E_ACT | 0x1 | IN Endpoint 2 Interrupt
66084  *
66085  * Field Access Macros:
66086  *
66087  */
66088 /*
66089  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT2
66090  *
66091  * No Interrupt
66092  */
66093 #define ALT_USB_DEV_DAINT_INEPINT2_E_INACT 0x0
66094 /*
66095  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT2
66096  *
66097  * IN Endpoint 2 Interrupt
66098  */
66099 #define ALT_USB_DEV_DAINT_INEPINT2_E_ACT 0x1
66100 
66101 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT2 register field. */
66102 #define ALT_USB_DEV_DAINT_INEPINT2_LSB 2
66103 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT2 register field. */
66104 #define ALT_USB_DEV_DAINT_INEPINT2_MSB 2
66105 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT2 register field. */
66106 #define ALT_USB_DEV_DAINT_INEPINT2_WIDTH 1
66107 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT2 register field value. */
66108 #define ALT_USB_DEV_DAINT_INEPINT2_SET_MSK 0x00000004
66109 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT2 register field value. */
66110 #define ALT_USB_DEV_DAINT_INEPINT2_CLR_MSK 0xfffffffb
66111 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT2 register field. */
66112 #define ALT_USB_DEV_DAINT_INEPINT2_RESET 0x0
66113 /* Extracts the ALT_USB_DEV_DAINT_INEPINT2 field value from a register. */
66114 #define ALT_USB_DEV_DAINT_INEPINT2_GET(value) (((value) & 0x00000004) >> 2)
66115 /* Produces a ALT_USB_DEV_DAINT_INEPINT2 register field value suitable for setting the register. */
66116 #define ALT_USB_DEV_DAINT_INEPINT2_SET(value) (((value) << 2) & 0x00000004)
66117 
66118 /*
66119  * Field : inepint3
66120  *
66121  * IN Endpoint 3 Interrupt Bit
66122  *
66123  * Field Enumeration Values:
66124  *
66125  * Enum | Value | Description
66126  * :-----------------------------------|:------|:------------------------
66127  * ALT_USB_DEV_DAINT_INEPINT3_E_INACT | 0x0 | No Interrupt
66128  * ALT_USB_DEV_DAINT_INEPINT3_E_ACT | 0x1 | IN Endpoint 3 Interrupt
66129  *
66130  * Field Access Macros:
66131  *
66132  */
66133 /*
66134  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT3
66135  *
66136  * No Interrupt
66137  */
66138 #define ALT_USB_DEV_DAINT_INEPINT3_E_INACT 0x0
66139 /*
66140  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT3
66141  *
66142  * IN Endpoint 3 Interrupt
66143  */
66144 #define ALT_USB_DEV_DAINT_INEPINT3_E_ACT 0x1
66145 
66146 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT3 register field. */
66147 #define ALT_USB_DEV_DAINT_INEPINT3_LSB 3
66148 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT3 register field. */
66149 #define ALT_USB_DEV_DAINT_INEPINT3_MSB 3
66150 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT3 register field. */
66151 #define ALT_USB_DEV_DAINT_INEPINT3_WIDTH 1
66152 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT3 register field value. */
66153 #define ALT_USB_DEV_DAINT_INEPINT3_SET_MSK 0x00000008
66154 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT3 register field value. */
66155 #define ALT_USB_DEV_DAINT_INEPINT3_CLR_MSK 0xfffffff7
66156 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT3 register field. */
66157 #define ALT_USB_DEV_DAINT_INEPINT3_RESET 0x0
66158 /* Extracts the ALT_USB_DEV_DAINT_INEPINT3 field value from a register. */
66159 #define ALT_USB_DEV_DAINT_INEPINT3_GET(value) (((value) & 0x00000008) >> 3)
66160 /* Produces a ALT_USB_DEV_DAINT_INEPINT3 register field value suitable for setting the register. */
66161 #define ALT_USB_DEV_DAINT_INEPINT3_SET(value) (((value) << 3) & 0x00000008)
66162 
66163 /*
66164  * Field : inepint4
66165  *
66166  * IN Endpoint 4 Interrupt Bit
66167  *
66168  * Field Enumeration Values:
66169  *
66170  * Enum | Value | Description
66171  * :-----------------------------------|:------|:------------------------
66172  * ALT_USB_DEV_DAINT_INEPINT4_E_INACT | 0x0 | No Interrupt
66173  * ALT_USB_DEV_DAINT_INEPINT4_E_ACT | 0x1 | IN Endpoint 4 Interrupt
66174  *
66175  * Field Access Macros:
66176  *
66177  */
66178 /*
66179  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT4
66180  *
66181  * No Interrupt
66182  */
66183 #define ALT_USB_DEV_DAINT_INEPINT4_E_INACT 0x0
66184 /*
66185  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT4
66186  *
66187  * IN Endpoint 4 Interrupt
66188  */
66189 #define ALT_USB_DEV_DAINT_INEPINT4_E_ACT 0x1
66190 
66191 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT4 register field. */
66192 #define ALT_USB_DEV_DAINT_INEPINT4_LSB 4
66193 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT4 register field. */
66194 #define ALT_USB_DEV_DAINT_INEPINT4_MSB 4
66195 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT4 register field. */
66196 #define ALT_USB_DEV_DAINT_INEPINT4_WIDTH 1
66197 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT4 register field value. */
66198 #define ALT_USB_DEV_DAINT_INEPINT4_SET_MSK 0x00000010
66199 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT4 register field value. */
66200 #define ALT_USB_DEV_DAINT_INEPINT4_CLR_MSK 0xffffffef
66201 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT4 register field. */
66202 #define ALT_USB_DEV_DAINT_INEPINT4_RESET 0x0
66203 /* Extracts the ALT_USB_DEV_DAINT_INEPINT4 field value from a register. */
66204 #define ALT_USB_DEV_DAINT_INEPINT4_GET(value) (((value) & 0x00000010) >> 4)
66205 /* Produces a ALT_USB_DEV_DAINT_INEPINT4 register field value suitable for setting the register. */
66206 #define ALT_USB_DEV_DAINT_INEPINT4_SET(value) (((value) << 4) & 0x00000010)
66207 
66208 /*
66209  * Field : inepint5
66210  *
66211  * IN Endpoint 5 Interrupt Bit
66212  *
66213  * Field Enumeration Values:
66214  *
66215  * Enum | Value | Description
66216  * :-----------------------------------|:------|:------------------------
66217  * ALT_USB_DEV_DAINT_INEPINT5_E_INACT | 0x0 | No Interrupt
66218  * ALT_USB_DEV_DAINT_INEPINT5_E_ACT | 0x1 | IN Endpoint 5 Interrupt
66219  *
66220  * Field Access Macros:
66221  *
66222  */
66223 /*
66224  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT5
66225  *
66226  * No Interrupt
66227  */
66228 #define ALT_USB_DEV_DAINT_INEPINT5_E_INACT 0x0
66229 /*
66230  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT5
66231  *
66232  * IN Endpoint 5 Interrupt
66233  */
66234 #define ALT_USB_DEV_DAINT_INEPINT5_E_ACT 0x1
66235 
66236 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT5 register field. */
66237 #define ALT_USB_DEV_DAINT_INEPINT5_LSB 5
66238 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT5 register field. */
66239 #define ALT_USB_DEV_DAINT_INEPINT5_MSB 5
66240 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT5 register field. */
66241 #define ALT_USB_DEV_DAINT_INEPINT5_WIDTH 1
66242 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT5 register field value. */
66243 #define ALT_USB_DEV_DAINT_INEPINT5_SET_MSK 0x00000020
66244 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT5 register field value. */
66245 #define ALT_USB_DEV_DAINT_INEPINT5_CLR_MSK 0xffffffdf
66246 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT5 register field. */
66247 #define ALT_USB_DEV_DAINT_INEPINT5_RESET 0x0
66248 /* Extracts the ALT_USB_DEV_DAINT_INEPINT5 field value from a register. */
66249 #define ALT_USB_DEV_DAINT_INEPINT5_GET(value) (((value) & 0x00000020) >> 5)
66250 /* Produces a ALT_USB_DEV_DAINT_INEPINT5 register field value suitable for setting the register. */
66251 #define ALT_USB_DEV_DAINT_INEPINT5_SET(value) (((value) << 5) & 0x00000020)
66252 
66253 /*
66254  * Field : inepint6
66255  *
66256  * IN Endpoint 6 Interrupt Bit
66257  *
66258  * Field Enumeration Values:
66259  *
66260  * Enum | Value | Description
66261  * :-----------------------------------|:------|:------------------------
66262  * ALT_USB_DEV_DAINT_INEPINT6_E_INACT | 0x0 | No Interrupt
66263  * ALT_USB_DEV_DAINT_INEPINT6_E_ACT | 0x1 | IN Endpoint 6 Interrupt
66264  *
66265  * Field Access Macros:
66266  *
66267  */
66268 /*
66269  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT6
66270  *
66271  * No Interrupt
66272  */
66273 #define ALT_USB_DEV_DAINT_INEPINT6_E_INACT 0x0
66274 /*
66275  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT6
66276  *
66277  * IN Endpoint 6 Interrupt
66278  */
66279 #define ALT_USB_DEV_DAINT_INEPINT6_E_ACT 0x1
66280 
66281 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT6 register field. */
66282 #define ALT_USB_DEV_DAINT_INEPINT6_LSB 6
66283 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT6 register field. */
66284 #define ALT_USB_DEV_DAINT_INEPINT6_MSB 6
66285 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT6 register field. */
66286 #define ALT_USB_DEV_DAINT_INEPINT6_WIDTH 1
66287 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT6 register field value. */
66288 #define ALT_USB_DEV_DAINT_INEPINT6_SET_MSK 0x00000040
66289 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT6 register field value. */
66290 #define ALT_USB_DEV_DAINT_INEPINT6_CLR_MSK 0xffffffbf
66291 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT6 register field. */
66292 #define ALT_USB_DEV_DAINT_INEPINT6_RESET 0x0
66293 /* Extracts the ALT_USB_DEV_DAINT_INEPINT6 field value from a register. */
66294 #define ALT_USB_DEV_DAINT_INEPINT6_GET(value) (((value) & 0x00000040) >> 6)
66295 /* Produces a ALT_USB_DEV_DAINT_INEPINT6 register field value suitable for setting the register. */
66296 #define ALT_USB_DEV_DAINT_INEPINT6_SET(value) (((value) << 6) & 0x00000040)
66297 
66298 /*
66299  * Field : inepint7
66300  *
66301  * IN Endpoint 7 Interrupt Bit
66302  *
66303  * Field Enumeration Values:
66304  *
66305  * Enum | Value | Description
66306  * :-----------------------------------|:------|:------------------------
66307  * ALT_USB_DEV_DAINT_INEPINT7_E_INACT | 0x0 | No Interrupt
66308  * ALT_USB_DEV_DAINT_INEPINT7_E_ACT | 0x1 | IN Endpoint 7 Interrupt
66309  *
66310  * Field Access Macros:
66311  *
66312  */
66313 /*
66314  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT7
66315  *
66316  * No Interrupt
66317  */
66318 #define ALT_USB_DEV_DAINT_INEPINT7_E_INACT 0x0
66319 /*
66320  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT7
66321  *
66322  * IN Endpoint 7 Interrupt
66323  */
66324 #define ALT_USB_DEV_DAINT_INEPINT7_E_ACT 0x1
66325 
66326 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT7 register field. */
66327 #define ALT_USB_DEV_DAINT_INEPINT7_LSB 7
66328 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT7 register field. */
66329 #define ALT_USB_DEV_DAINT_INEPINT7_MSB 7
66330 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT7 register field. */
66331 #define ALT_USB_DEV_DAINT_INEPINT7_WIDTH 1
66332 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT7 register field value. */
66333 #define ALT_USB_DEV_DAINT_INEPINT7_SET_MSK 0x00000080
66334 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT7 register field value. */
66335 #define ALT_USB_DEV_DAINT_INEPINT7_CLR_MSK 0xffffff7f
66336 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT7 register field. */
66337 #define ALT_USB_DEV_DAINT_INEPINT7_RESET 0x0
66338 /* Extracts the ALT_USB_DEV_DAINT_INEPINT7 field value from a register. */
66339 #define ALT_USB_DEV_DAINT_INEPINT7_GET(value) (((value) & 0x00000080) >> 7)
66340 /* Produces a ALT_USB_DEV_DAINT_INEPINT7 register field value suitable for setting the register. */
66341 #define ALT_USB_DEV_DAINT_INEPINT7_SET(value) (((value) << 7) & 0x00000080)
66342 
66343 /*
66344  * Field : inepint8
66345  *
66346  * IN Endpoint 8 Interrupt Bit
66347  *
66348  * Field Enumeration Values:
66349  *
66350  * Enum | Value | Description
66351  * :-----------------------------------|:------|:------------------------
66352  * ALT_USB_DEV_DAINT_INEPINT8_E_INACT | 0x0 | No Interrupt
66353  * ALT_USB_DEV_DAINT_INEPINT8_E_ACT | 0x1 | IN Endpoint 8 Interrupt
66354  *
66355  * Field Access Macros:
66356  *
66357  */
66358 /*
66359  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT8
66360  *
66361  * No Interrupt
66362  */
66363 #define ALT_USB_DEV_DAINT_INEPINT8_E_INACT 0x0
66364 /*
66365  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT8
66366  *
66367  * IN Endpoint 8 Interrupt
66368  */
66369 #define ALT_USB_DEV_DAINT_INEPINT8_E_ACT 0x1
66370 
66371 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT8 register field. */
66372 #define ALT_USB_DEV_DAINT_INEPINT8_LSB 8
66373 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT8 register field. */
66374 #define ALT_USB_DEV_DAINT_INEPINT8_MSB 8
66375 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT8 register field. */
66376 #define ALT_USB_DEV_DAINT_INEPINT8_WIDTH 1
66377 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT8 register field value. */
66378 #define ALT_USB_DEV_DAINT_INEPINT8_SET_MSK 0x00000100
66379 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT8 register field value. */
66380 #define ALT_USB_DEV_DAINT_INEPINT8_CLR_MSK 0xfffffeff
66381 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT8 register field. */
66382 #define ALT_USB_DEV_DAINT_INEPINT8_RESET 0x0
66383 /* Extracts the ALT_USB_DEV_DAINT_INEPINT8 field value from a register. */
66384 #define ALT_USB_DEV_DAINT_INEPINT8_GET(value) (((value) & 0x00000100) >> 8)
66385 /* Produces a ALT_USB_DEV_DAINT_INEPINT8 register field value suitable for setting the register. */
66386 #define ALT_USB_DEV_DAINT_INEPINT8_SET(value) (((value) << 8) & 0x00000100)
66387 
66388 /*
66389  * Field : inepint9
66390  *
66391  * IN Endpoint 9 Interrupt Bit
66392  *
66393  * Field Enumeration Values:
66394  *
66395  * Enum | Value | Description
66396  * :-----------------------------------|:------|:------------------------
66397  * ALT_USB_DEV_DAINT_INEPINT9_E_INACT | 0x0 | No Interrupt
66398  * ALT_USB_DEV_DAINT_INEPINT9_E_ACT | 0x1 | IN Endpoint 9 Interrupt
66399  *
66400  * Field Access Macros:
66401  *
66402  */
66403 /*
66404  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT9
66405  *
66406  * No Interrupt
66407  */
66408 #define ALT_USB_DEV_DAINT_INEPINT9_E_INACT 0x0
66409 /*
66410  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT9
66411  *
66412  * IN Endpoint 9 Interrupt
66413  */
66414 #define ALT_USB_DEV_DAINT_INEPINT9_E_ACT 0x1
66415 
66416 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT9 register field. */
66417 #define ALT_USB_DEV_DAINT_INEPINT9_LSB 9
66418 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT9 register field. */
66419 #define ALT_USB_DEV_DAINT_INEPINT9_MSB 9
66420 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT9 register field. */
66421 #define ALT_USB_DEV_DAINT_INEPINT9_WIDTH 1
66422 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT9 register field value. */
66423 #define ALT_USB_DEV_DAINT_INEPINT9_SET_MSK 0x00000200
66424 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT9 register field value. */
66425 #define ALT_USB_DEV_DAINT_INEPINT9_CLR_MSK 0xfffffdff
66426 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT9 register field. */
66427 #define ALT_USB_DEV_DAINT_INEPINT9_RESET 0x0
66428 /* Extracts the ALT_USB_DEV_DAINT_INEPINT9 field value from a register. */
66429 #define ALT_USB_DEV_DAINT_INEPINT9_GET(value) (((value) & 0x00000200) >> 9)
66430 /* Produces a ALT_USB_DEV_DAINT_INEPINT9 register field value suitable for setting the register. */
66431 #define ALT_USB_DEV_DAINT_INEPINT9_SET(value) (((value) << 9) & 0x00000200)
66432 
66433 /*
66434  * Field : inepint10
66435  *
66436  * IN Endpoint 10 Interrupt Bit
66437  *
66438  * Field Enumeration Values:
66439  *
66440  * Enum | Value | Description
66441  * :------------------------------------|:------|:-------------------------
66442  * ALT_USB_DEV_DAINT_INEPINT10_E_INACT | 0x0 | No Interrupt
66443  * ALT_USB_DEV_DAINT_INEPINT10_E_ACT | 0x1 | IN Endpoint 10 Interrupt
66444  *
66445  * Field Access Macros:
66446  *
66447  */
66448 /*
66449  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT10
66450  *
66451  * No Interrupt
66452  */
66453 #define ALT_USB_DEV_DAINT_INEPINT10_E_INACT 0x0
66454 /*
66455  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT10
66456  *
66457  * IN Endpoint 10 Interrupt
66458  */
66459 #define ALT_USB_DEV_DAINT_INEPINT10_E_ACT 0x1
66460 
66461 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT10 register field. */
66462 #define ALT_USB_DEV_DAINT_INEPINT10_LSB 10
66463 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT10 register field. */
66464 #define ALT_USB_DEV_DAINT_INEPINT10_MSB 10
66465 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT10 register field. */
66466 #define ALT_USB_DEV_DAINT_INEPINT10_WIDTH 1
66467 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT10 register field value. */
66468 #define ALT_USB_DEV_DAINT_INEPINT10_SET_MSK 0x00000400
66469 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT10 register field value. */
66470 #define ALT_USB_DEV_DAINT_INEPINT10_CLR_MSK 0xfffffbff
66471 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT10 register field. */
66472 #define ALT_USB_DEV_DAINT_INEPINT10_RESET 0x0
66473 /* Extracts the ALT_USB_DEV_DAINT_INEPINT10 field value from a register. */
66474 #define ALT_USB_DEV_DAINT_INEPINT10_GET(value) (((value) & 0x00000400) >> 10)
66475 /* Produces a ALT_USB_DEV_DAINT_INEPINT10 register field value suitable for setting the register. */
66476 #define ALT_USB_DEV_DAINT_INEPINT10_SET(value) (((value) << 10) & 0x00000400)
66477 
66478 /*
66479  * Field : inepint11
66480  *
66481  * IN Endpoint 11 Interrupt Bit
66482  *
66483  * Field Enumeration Values:
66484  *
66485  * Enum | Value | Description
66486  * :------------------------------------|:------|:-------------------------
66487  * ALT_USB_DEV_DAINT_INEPINT11_E_INACT | 0x0 | No Interrupt
66488  * ALT_USB_DEV_DAINT_INEPINT11_E_ACT | 0x1 | IN Endpoint 11 Interrupt
66489  *
66490  * Field Access Macros:
66491  *
66492  */
66493 /*
66494  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT11
66495  *
66496  * No Interrupt
66497  */
66498 #define ALT_USB_DEV_DAINT_INEPINT11_E_INACT 0x0
66499 /*
66500  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT11
66501  *
66502  * IN Endpoint 11 Interrupt
66503  */
66504 #define ALT_USB_DEV_DAINT_INEPINT11_E_ACT 0x1
66505 
66506 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT11 register field. */
66507 #define ALT_USB_DEV_DAINT_INEPINT11_LSB 11
66508 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT11 register field. */
66509 #define ALT_USB_DEV_DAINT_INEPINT11_MSB 11
66510 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT11 register field. */
66511 #define ALT_USB_DEV_DAINT_INEPINT11_WIDTH 1
66512 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT11 register field value. */
66513 #define ALT_USB_DEV_DAINT_INEPINT11_SET_MSK 0x00000800
66514 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT11 register field value. */
66515 #define ALT_USB_DEV_DAINT_INEPINT11_CLR_MSK 0xfffff7ff
66516 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT11 register field. */
66517 #define ALT_USB_DEV_DAINT_INEPINT11_RESET 0x0
66518 /* Extracts the ALT_USB_DEV_DAINT_INEPINT11 field value from a register. */
66519 #define ALT_USB_DEV_DAINT_INEPINT11_GET(value) (((value) & 0x00000800) >> 11)
66520 /* Produces a ALT_USB_DEV_DAINT_INEPINT11 register field value suitable for setting the register. */
66521 #define ALT_USB_DEV_DAINT_INEPINT11_SET(value) (((value) << 11) & 0x00000800)
66522 
66523 /*
66524  * Field : inepint12
66525  *
66526  * IN Endpoint 12 Interrupt Bit
66527  *
66528  * Field Enumeration Values:
66529  *
66530  * Enum | Value | Description
66531  * :------------------------------------|:------|:-------------------------
66532  * ALT_USB_DEV_DAINT_INEPINT12_E_INACT | 0x0 | No Interrupt
66533  * ALT_USB_DEV_DAINT_INEPINT12_E_ACT | 0x1 | IN Endpoint 12 Interrupt
66534  *
66535  * Field Access Macros:
66536  *
66537  */
66538 /*
66539  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT12
66540  *
66541  * No Interrupt
66542  */
66543 #define ALT_USB_DEV_DAINT_INEPINT12_E_INACT 0x0
66544 /*
66545  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT12
66546  *
66547  * IN Endpoint 12 Interrupt
66548  */
66549 #define ALT_USB_DEV_DAINT_INEPINT12_E_ACT 0x1
66550 
66551 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT12 register field. */
66552 #define ALT_USB_DEV_DAINT_INEPINT12_LSB 12
66553 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT12 register field. */
66554 #define ALT_USB_DEV_DAINT_INEPINT12_MSB 12
66555 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT12 register field. */
66556 #define ALT_USB_DEV_DAINT_INEPINT12_WIDTH 1
66557 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT12 register field value. */
66558 #define ALT_USB_DEV_DAINT_INEPINT12_SET_MSK 0x00001000
66559 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT12 register field value. */
66560 #define ALT_USB_DEV_DAINT_INEPINT12_CLR_MSK 0xffffefff
66561 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT12 register field. */
66562 #define ALT_USB_DEV_DAINT_INEPINT12_RESET 0x0
66563 /* Extracts the ALT_USB_DEV_DAINT_INEPINT12 field value from a register. */
66564 #define ALT_USB_DEV_DAINT_INEPINT12_GET(value) (((value) & 0x00001000) >> 12)
66565 /* Produces a ALT_USB_DEV_DAINT_INEPINT12 register field value suitable for setting the register. */
66566 #define ALT_USB_DEV_DAINT_INEPINT12_SET(value) (((value) << 12) & 0x00001000)
66567 
66568 /*
66569  * Field : inepint13
66570  *
66571  * IN Endpoint 13 Interrupt Bit
66572  *
66573  * Field Enumeration Values:
66574  *
66575  * Enum | Value | Description
66576  * :------------------------------------|:------|:-------------------------
66577  * ALT_USB_DEV_DAINT_INEPINT13_E_INACT | 0x0 | No Interrupt
66578  * ALT_USB_DEV_DAINT_INEPINT13_E_ACT | 0x1 | IN Endpoint 13 Interrupt
66579  *
66580  * Field Access Macros:
66581  *
66582  */
66583 /*
66584  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT13
66585  *
66586  * No Interrupt
66587  */
66588 #define ALT_USB_DEV_DAINT_INEPINT13_E_INACT 0x0
66589 /*
66590  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT13
66591  *
66592  * IN Endpoint 13 Interrupt
66593  */
66594 #define ALT_USB_DEV_DAINT_INEPINT13_E_ACT 0x1
66595 
66596 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT13 register field. */
66597 #define ALT_USB_DEV_DAINT_INEPINT13_LSB 13
66598 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT13 register field. */
66599 #define ALT_USB_DEV_DAINT_INEPINT13_MSB 13
66600 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT13 register field. */
66601 #define ALT_USB_DEV_DAINT_INEPINT13_WIDTH 1
66602 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT13 register field value. */
66603 #define ALT_USB_DEV_DAINT_INEPINT13_SET_MSK 0x00002000
66604 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT13 register field value. */
66605 #define ALT_USB_DEV_DAINT_INEPINT13_CLR_MSK 0xffffdfff
66606 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT13 register field. */
66607 #define ALT_USB_DEV_DAINT_INEPINT13_RESET 0x0
66608 /* Extracts the ALT_USB_DEV_DAINT_INEPINT13 field value from a register. */
66609 #define ALT_USB_DEV_DAINT_INEPINT13_GET(value) (((value) & 0x00002000) >> 13)
66610 /* Produces a ALT_USB_DEV_DAINT_INEPINT13 register field value suitable for setting the register. */
66611 #define ALT_USB_DEV_DAINT_INEPINT13_SET(value) (((value) << 13) & 0x00002000)
66612 
66613 /*
66614  * Field : inepint14
66615  *
66616  * IN Endpoint 14 Interrupt Bit
66617  *
66618  * Field Enumeration Values:
66619  *
66620  * Enum | Value | Description
66621  * :------------------------------------|:------|:-------------------------
66622  * ALT_USB_DEV_DAINT_INEPINT14_E_INACT | 0x0 | No Interrupt
66623  * ALT_USB_DEV_DAINT_INEPINT14_E_ACT | 0x1 | IN Endpoint 14 Interrupt
66624  *
66625  * Field Access Macros:
66626  *
66627  */
66628 /*
66629  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT14
66630  *
66631  * No Interrupt
66632  */
66633 #define ALT_USB_DEV_DAINT_INEPINT14_E_INACT 0x0
66634 /*
66635  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT14
66636  *
66637  * IN Endpoint 14 Interrupt
66638  */
66639 #define ALT_USB_DEV_DAINT_INEPINT14_E_ACT 0x1
66640 
66641 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT14 register field. */
66642 #define ALT_USB_DEV_DAINT_INEPINT14_LSB 14
66643 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT14 register field. */
66644 #define ALT_USB_DEV_DAINT_INEPINT14_MSB 14
66645 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT14 register field. */
66646 #define ALT_USB_DEV_DAINT_INEPINT14_WIDTH 1
66647 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT14 register field value. */
66648 #define ALT_USB_DEV_DAINT_INEPINT14_SET_MSK 0x00004000
66649 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT14 register field value. */
66650 #define ALT_USB_DEV_DAINT_INEPINT14_CLR_MSK 0xffffbfff
66651 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT14 register field. */
66652 #define ALT_USB_DEV_DAINT_INEPINT14_RESET 0x0
66653 /* Extracts the ALT_USB_DEV_DAINT_INEPINT14 field value from a register. */
66654 #define ALT_USB_DEV_DAINT_INEPINT14_GET(value) (((value) & 0x00004000) >> 14)
66655 /* Produces a ALT_USB_DEV_DAINT_INEPINT14 register field value suitable for setting the register. */
66656 #define ALT_USB_DEV_DAINT_INEPINT14_SET(value) (((value) << 14) & 0x00004000)
66657 
66658 /*
66659  * Field : inepint15
66660  *
66661  * IN Endpoint 15 Interrupt Bit
66662  *
66663  * Field Enumeration Values:
66664  *
66665  * Enum | Value | Description
66666  * :------------------------------------|:------|:-------------------------
66667  * ALT_USB_DEV_DAINT_INEPINT15_E_INACT | 0x0 | No Interrupt
66668  * ALT_USB_DEV_DAINT_INEPINT15_E_ACT | 0x1 | IN Endpoint 15 Interrupt
66669  *
66670  * Field Access Macros:
66671  *
66672  */
66673 /*
66674  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT15
66675  *
66676  * No Interrupt
66677  */
66678 #define ALT_USB_DEV_DAINT_INEPINT15_E_INACT 0x0
66679 /*
66680  * Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT15
66681  *
66682  * IN Endpoint 15 Interrupt
66683  */
66684 #define ALT_USB_DEV_DAINT_INEPINT15_E_ACT 0x1
66685 
66686 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT15 register field. */
66687 #define ALT_USB_DEV_DAINT_INEPINT15_LSB 15
66688 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT15 register field. */
66689 #define ALT_USB_DEV_DAINT_INEPINT15_MSB 15
66690 /* The width in bits of the ALT_USB_DEV_DAINT_INEPINT15 register field. */
66691 #define ALT_USB_DEV_DAINT_INEPINT15_WIDTH 1
66692 /* The mask used to set the ALT_USB_DEV_DAINT_INEPINT15 register field value. */
66693 #define ALT_USB_DEV_DAINT_INEPINT15_SET_MSK 0x00008000
66694 /* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT15 register field value. */
66695 #define ALT_USB_DEV_DAINT_INEPINT15_CLR_MSK 0xffff7fff
66696 /* The reset value of the ALT_USB_DEV_DAINT_INEPINT15 register field. */
66697 #define ALT_USB_DEV_DAINT_INEPINT15_RESET 0x0
66698 /* Extracts the ALT_USB_DEV_DAINT_INEPINT15 field value from a register. */
66699 #define ALT_USB_DEV_DAINT_INEPINT15_GET(value) (((value) & 0x00008000) >> 15)
66700 /* Produces a ALT_USB_DEV_DAINT_INEPINT15 register field value suitable for setting the register. */
66701 #define ALT_USB_DEV_DAINT_INEPINT15_SET(value) (((value) << 15) & 0x00008000)
66702 
66703 /*
66704  * Field : outepint0
66705  *
66706  * OUT Endpoint 0 Interrupt Bit
66707  *
66708  * Field Enumeration Values:
66709  *
66710  * Enum | Value | Description
66711  * :------------------------------------|:------|:-------------------------
66712  * ALT_USB_DEV_DAINT_OUTEPINT0_E_INACT | 0x0 | No Interrupt
66713  * ALT_USB_DEV_DAINT_OUTEPINT0_E_ACT | 0x1 | OUT Endpoint 0 Interrupt
66714  *
66715  * Field Access Macros:
66716  *
66717  */
66718 /*
66719  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT0
66720  *
66721  * No Interrupt
66722  */
66723 #define ALT_USB_DEV_DAINT_OUTEPINT0_E_INACT 0x0
66724 /*
66725  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT0
66726  *
66727  * OUT Endpoint 0 Interrupt
66728  */
66729 #define ALT_USB_DEV_DAINT_OUTEPINT0_E_ACT 0x1
66730 
66731 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */
66732 #define ALT_USB_DEV_DAINT_OUTEPINT0_LSB 16
66733 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */
66734 #define ALT_USB_DEV_DAINT_OUTEPINT0_MSB 16
66735 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */
66736 #define ALT_USB_DEV_DAINT_OUTEPINT0_WIDTH 1
66737 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT0 register field value. */
66738 #define ALT_USB_DEV_DAINT_OUTEPINT0_SET_MSK 0x00010000
66739 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT0 register field value. */
66740 #define ALT_USB_DEV_DAINT_OUTEPINT0_CLR_MSK 0xfffeffff
66741 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */
66742 #define ALT_USB_DEV_DAINT_OUTEPINT0_RESET 0x0
66743 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT0 field value from a register. */
66744 #define ALT_USB_DEV_DAINT_OUTEPINT0_GET(value) (((value) & 0x00010000) >> 16)
66745 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT0 register field value suitable for setting the register. */
66746 #define ALT_USB_DEV_DAINT_OUTEPINT0_SET(value) (((value) << 16) & 0x00010000)
66747 
66748 /*
66749  * Field : outepint1
66750  *
66751  * OUT Endpoint 1 Interrupt Bit
66752  *
66753  * Field Enumeration Values:
66754  *
66755  * Enum | Value | Description
66756  * :------------------------------------|:------|:-------------------------
66757  * ALT_USB_DEV_DAINT_OUTEPINT1_E_INACT | 0x0 | No Interrupt
66758  * ALT_USB_DEV_DAINT_OUTEPINT1_E_ACT | 0x1 | OUT Endpoint 1 Interrupt
66759  *
66760  * Field Access Macros:
66761  *
66762  */
66763 /*
66764  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT1
66765  *
66766  * No Interrupt
66767  */
66768 #define ALT_USB_DEV_DAINT_OUTEPINT1_E_INACT 0x0
66769 /*
66770  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT1
66771  *
66772  * OUT Endpoint 1 Interrupt
66773  */
66774 #define ALT_USB_DEV_DAINT_OUTEPINT1_E_ACT 0x1
66775 
66776 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */
66777 #define ALT_USB_DEV_DAINT_OUTEPINT1_LSB 17
66778 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */
66779 #define ALT_USB_DEV_DAINT_OUTEPINT1_MSB 17
66780 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */
66781 #define ALT_USB_DEV_DAINT_OUTEPINT1_WIDTH 1
66782 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT1 register field value. */
66783 #define ALT_USB_DEV_DAINT_OUTEPINT1_SET_MSK 0x00020000
66784 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT1 register field value. */
66785 #define ALT_USB_DEV_DAINT_OUTEPINT1_CLR_MSK 0xfffdffff
66786 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */
66787 #define ALT_USB_DEV_DAINT_OUTEPINT1_RESET 0x0
66788 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT1 field value from a register. */
66789 #define ALT_USB_DEV_DAINT_OUTEPINT1_GET(value) (((value) & 0x00020000) >> 17)
66790 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT1 register field value suitable for setting the register. */
66791 #define ALT_USB_DEV_DAINT_OUTEPINT1_SET(value) (((value) << 17) & 0x00020000)
66792 
66793 /*
66794  * Field : outepint2
66795  *
66796  * OUT Endpoint 2 Interrupt Bit
66797  *
66798  * Field Enumeration Values:
66799  *
66800  * Enum | Value | Description
66801  * :------------------------------------|:------|:-------------------------
66802  * ALT_USB_DEV_DAINT_OUTEPINT2_E_INACT | 0x0 | No Interrupt
66803  * ALT_USB_DEV_DAINT_OUTEPINT2_E_ACT | 0x1 | OUT Endpoint 2 Interrupt
66804  *
66805  * Field Access Macros:
66806  *
66807  */
66808 /*
66809  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT2
66810  *
66811  * No Interrupt
66812  */
66813 #define ALT_USB_DEV_DAINT_OUTEPINT2_E_INACT 0x0
66814 /*
66815  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT2
66816  *
66817  * OUT Endpoint 2 Interrupt
66818  */
66819 #define ALT_USB_DEV_DAINT_OUTEPINT2_E_ACT 0x1
66820 
66821 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */
66822 #define ALT_USB_DEV_DAINT_OUTEPINT2_LSB 18
66823 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */
66824 #define ALT_USB_DEV_DAINT_OUTEPINT2_MSB 18
66825 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */
66826 #define ALT_USB_DEV_DAINT_OUTEPINT2_WIDTH 1
66827 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT2 register field value. */
66828 #define ALT_USB_DEV_DAINT_OUTEPINT2_SET_MSK 0x00040000
66829 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT2 register field value. */
66830 #define ALT_USB_DEV_DAINT_OUTEPINT2_CLR_MSK 0xfffbffff
66831 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */
66832 #define ALT_USB_DEV_DAINT_OUTEPINT2_RESET 0x0
66833 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT2 field value from a register. */
66834 #define ALT_USB_DEV_DAINT_OUTEPINT2_GET(value) (((value) & 0x00040000) >> 18)
66835 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT2 register field value suitable for setting the register. */
66836 #define ALT_USB_DEV_DAINT_OUTEPINT2_SET(value) (((value) << 18) & 0x00040000)
66837 
66838 /*
66839  * Field : outepint3
66840  *
66841  * OUT Endpoint 3 Interrupt Bit
66842  *
66843  * Field Enumeration Values:
66844  *
66845  * Enum | Value | Description
66846  * :------------------------------------|:------|:-------------------------
66847  * ALT_USB_DEV_DAINT_OUTEPINT3_E_INACT | 0x0 | No Interrupt
66848  * ALT_USB_DEV_DAINT_OUTEPINT3_E_ACT | 0x1 | OUT Endpoint 3 Interrupt
66849  *
66850  * Field Access Macros:
66851  *
66852  */
66853 /*
66854  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT3
66855  *
66856  * No Interrupt
66857  */
66858 #define ALT_USB_DEV_DAINT_OUTEPINT3_E_INACT 0x0
66859 /*
66860  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT3
66861  *
66862  * OUT Endpoint 3 Interrupt
66863  */
66864 #define ALT_USB_DEV_DAINT_OUTEPINT3_E_ACT 0x1
66865 
66866 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */
66867 #define ALT_USB_DEV_DAINT_OUTEPINT3_LSB 19
66868 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */
66869 #define ALT_USB_DEV_DAINT_OUTEPINT3_MSB 19
66870 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */
66871 #define ALT_USB_DEV_DAINT_OUTEPINT3_WIDTH 1
66872 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT3 register field value. */
66873 #define ALT_USB_DEV_DAINT_OUTEPINT3_SET_MSK 0x00080000
66874 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT3 register field value. */
66875 #define ALT_USB_DEV_DAINT_OUTEPINT3_CLR_MSK 0xfff7ffff
66876 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */
66877 #define ALT_USB_DEV_DAINT_OUTEPINT3_RESET 0x0
66878 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT3 field value from a register. */
66879 #define ALT_USB_DEV_DAINT_OUTEPINT3_GET(value) (((value) & 0x00080000) >> 19)
66880 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT3 register field value suitable for setting the register. */
66881 #define ALT_USB_DEV_DAINT_OUTEPINT3_SET(value) (((value) << 19) & 0x00080000)
66882 
66883 /*
66884  * Field : outepint4
66885  *
66886  * OUT Endpoint 4 Interrupt Bit
66887  *
66888  * Field Enumeration Values:
66889  *
66890  * Enum | Value | Description
66891  * :------------------------------------|:------|:-------------------------
66892  * ALT_USB_DEV_DAINT_OUTEPINT4_E_INACT | 0x0 | No Interrupt
66893  * ALT_USB_DEV_DAINT_OUTEPINT4_E_ACT | 0x1 | OUT Endpoint 4 Interrupt
66894  *
66895  * Field Access Macros:
66896  *
66897  */
66898 /*
66899  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT4
66900  *
66901  * No Interrupt
66902  */
66903 #define ALT_USB_DEV_DAINT_OUTEPINT4_E_INACT 0x0
66904 /*
66905  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT4
66906  *
66907  * OUT Endpoint 4 Interrupt
66908  */
66909 #define ALT_USB_DEV_DAINT_OUTEPINT4_E_ACT 0x1
66910 
66911 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */
66912 #define ALT_USB_DEV_DAINT_OUTEPINT4_LSB 20
66913 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */
66914 #define ALT_USB_DEV_DAINT_OUTEPINT4_MSB 20
66915 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */
66916 #define ALT_USB_DEV_DAINT_OUTEPINT4_WIDTH 1
66917 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT4 register field value. */
66918 #define ALT_USB_DEV_DAINT_OUTEPINT4_SET_MSK 0x00100000
66919 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT4 register field value. */
66920 #define ALT_USB_DEV_DAINT_OUTEPINT4_CLR_MSK 0xffefffff
66921 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */
66922 #define ALT_USB_DEV_DAINT_OUTEPINT4_RESET 0x0
66923 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT4 field value from a register. */
66924 #define ALT_USB_DEV_DAINT_OUTEPINT4_GET(value) (((value) & 0x00100000) >> 20)
66925 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT4 register field value suitable for setting the register. */
66926 #define ALT_USB_DEV_DAINT_OUTEPINT4_SET(value) (((value) << 20) & 0x00100000)
66927 
66928 /*
66929  * Field : outepint5
66930  *
66931  * OUT Endpoint 5 Interrupt Bit
66932  *
66933  * Field Enumeration Values:
66934  *
66935  * Enum | Value | Description
66936  * :------------------------------------|:------|:-------------------------
66937  * ALT_USB_DEV_DAINT_OUTEPINT5_E_INACT | 0x0 | No Interrupt
66938  * ALT_USB_DEV_DAINT_OUTEPINT5_E_ACT | 0x1 | OUT Endpoint 5 Interrupt
66939  *
66940  * Field Access Macros:
66941  *
66942  */
66943 /*
66944  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT5
66945  *
66946  * No Interrupt
66947  */
66948 #define ALT_USB_DEV_DAINT_OUTEPINT5_E_INACT 0x0
66949 /*
66950  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT5
66951  *
66952  * OUT Endpoint 5 Interrupt
66953  */
66954 #define ALT_USB_DEV_DAINT_OUTEPINT5_E_ACT 0x1
66955 
66956 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */
66957 #define ALT_USB_DEV_DAINT_OUTEPINT5_LSB 21
66958 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */
66959 #define ALT_USB_DEV_DAINT_OUTEPINT5_MSB 21
66960 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */
66961 #define ALT_USB_DEV_DAINT_OUTEPINT5_WIDTH 1
66962 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT5 register field value. */
66963 #define ALT_USB_DEV_DAINT_OUTEPINT5_SET_MSK 0x00200000
66964 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT5 register field value. */
66965 #define ALT_USB_DEV_DAINT_OUTEPINT5_CLR_MSK 0xffdfffff
66966 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */
66967 #define ALT_USB_DEV_DAINT_OUTEPINT5_RESET 0x0
66968 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT5 field value from a register. */
66969 #define ALT_USB_DEV_DAINT_OUTEPINT5_GET(value) (((value) & 0x00200000) >> 21)
66970 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT5 register field value suitable for setting the register. */
66971 #define ALT_USB_DEV_DAINT_OUTEPINT5_SET(value) (((value) << 21) & 0x00200000)
66972 
66973 /*
66974  * Field : outepint6
66975  *
66976  * OUT Endpoint 6 Interrupt Bit
66977  *
66978  * Field Enumeration Values:
66979  *
66980  * Enum | Value | Description
66981  * :------------------------------------|:------|:-------------------------
66982  * ALT_USB_DEV_DAINT_OUTEPINT6_E_INACT | 0x0 | No Interrupt
66983  * ALT_USB_DEV_DAINT_OUTEPINT6_E_ACT | 0x1 | OUT Endpoint 6 Interrupt
66984  *
66985  * Field Access Macros:
66986  *
66987  */
66988 /*
66989  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT6
66990  *
66991  * No Interrupt
66992  */
66993 #define ALT_USB_DEV_DAINT_OUTEPINT6_E_INACT 0x0
66994 /*
66995  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT6
66996  *
66997  * OUT Endpoint 6 Interrupt
66998  */
66999 #define ALT_USB_DEV_DAINT_OUTEPINT6_E_ACT 0x1
67000 
67001 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */
67002 #define ALT_USB_DEV_DAINT_OUTEPINT6_LSB 22
67003 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */
67004 #define ALT_USB_DEV_DAINT_OUTEPINT6_MSB 22
67005 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */
67006 #define ALT_USB_DEV_DAINT_OUTEPINT6_WIDTH 1
67007 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT6 register field value. */
67008 #define ALT_USB_DEV_DAINT_OUTEPINT6_SET_MSK 0x00400000
67009 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT6 register field value. */
67010 #define ALT_USB_DEV_DAINT_OUTEPINT6_CLR_MSK 0xffbfffff
67011 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */
67012 #define ALT_USB_DEV_DAINT_OUTEPINT6_RESET 0x0
67013 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT6 field value from a register. */
67014 #define ALT_USB_DEV_DAINT_OUTEPINT6_GET(value) (((value) & 0x00400000) >> 22)
67015 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT6 register field value suitable for setting the register. */
67016 #define ALT_USB_DEV_DAINT_OUTEPINT6_SET(value) (((value) << 22) & 0x00400000)
67017 
67018 /*
67019  * Field : outepint7
67020  *
67021  * OUT Endpoint 7 Interrupt Bit
67022  *
67023  * Field Enumeration Values:
67024  *
67025  * Enum | Value | Description
67026  * :------------------------------------|:------|:-------------------------
67027  * ALT_USB_DEV_DAINT_OUTEPINT7_E_INACT | 0x0 | No Interrupt
67028  * ALT_USB_DEV_DAINT_OUTEPINT7_E_ACT | 0x1 | OUT Endpoint 7 Interrupt
67029  *
67030  * Field Access Macros:
67031  *
67032  */
67033 /*
67034  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT7
67035  *
67036  * No Interrupt
67037  */
67038 #define ALT_USB_DEV_DAINT_OUTEPINT7_E_INACT 0x0
67039 /*
67040  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT7
67041  *
67042  * OUT Endpoint 7 Interrupt
67043  */
67044 #define ALT_USB_DEV_DAINT_OUTEPINT7_E_ACT 0x1
67045 
67046 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */
67047 #define ALT_USB_DEV_DAINT_OUTEPINT7_LSB 23
67048 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */
67049 #define ALT_USB_DEV_DAINT_OUTEPINT7_MSB 23
67050 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */
67051 #define ALT_USB_DEV_DAINT_OUTEPINT7_WIDTH 1
67052 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT7 register field value. */
67053 #define ALT_USB_DEV_DAINT_OUTEPINT7_SET_MSK 0x00800000
67054 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT7 register field value. */
67055 #define ALT_USB_DEV_DAINT_OUTEPINT7_CLR_MSK 0xff7fffff
67056 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */
67057 #define ALT_USB_DEV_DAINT_OUTEPINT7_RESET 0x0
67058 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT7 field value from a register. */
67059 #define ALT_USB_DEV_DAINT_OUTEPINT7_GET(value) (((value) & 0x00800000) >> 23)
67060 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT7 register field value suitable for setting the register. */
67061 #define ALT_USB_DEV_DAINT_OUTEPINT7_SET(value) (((value) << 23) & 0x00800000)
67062 
67063 /*
67064  * Field : outepint8
67065  *
67066  * OUT Endpoint 8 Interrupt Bit
67067  *
67068  * Field Enumeration Values:
67069  *
67070  * Enum | Value | Description
67071  * :------------------------------------|:------|:-------------------------
67072  * ALT_USB_DEV_DAINT_OUTEPINT8_E_INACT | 0x0 | No Interrupt
67073  * ALT_USB_DEV_DAINT_OUTEPINT8_E_ACT | 0x1 | OUT Endpoint 8 Interrupt
67074  *
67075  * Field Access Macros:
67076  *
67077  */
67078 /*
67079  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT8
67080  *
67081  * No Interrupt
67082  */
67083 #define ALT_USB_DEV_DAINT_OUTEPINT8_E_INACT 0x0
67084 /*
67085  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT8
67086  *
67087  * OUT Endpoint 8 Interrupt
67088  */
67089 #define ALT_USB_DEV_DAINT_OUTEPINT8_E_ACT 0x1
67090 
67091 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */
67092 #define ALT_USB_DEV_DAINT_OUTEPINT8_LSB 24
67093 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */
67094 #define ALT_USB_DEV_DAINT_OUTEPINT8_MSB 24
67095 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */
67096 #define ALT_USB_DEV_DAINT_OUTEPINT8_WIDTH 1
67097 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT8 register field value. */
67098 #define ALT_USB_DEV_DAINT_OUTEPINT8_SET_MSK 0x01000000
67099 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT8 register field value. */
67100 #define ALT_USB_DEV_DAINT_OUTEPINT8_CLR_MSK 0xfeffffff
67101 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */
67102 #define ALT_USB_DEV_DAINT_OUTEPINT8_RESET 0x0
67103 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT8 field value from a register. */
67104 #define ALT_USB_DEV_DAINT_OUTEPINT8_GET(value) (((value) & 0x01000000) >> 24)
67105 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT8 register field value suitable for setting the register. */
67106 #define ALT_USB_DEV_DAINT_OUTEPINT8_SET(value) (((value) << 24) & 0x01000000)
67107 
67108 /*
67109  * Field : outepint9
67110  *
67111  * OUT Endpoint 9 Interrupt Bit
67112  *
67113  * Field Enumeration Values:
67114  *
67115  * Enum | Value | Description
67116  * :------------------------------------|:------|:-------------------------
67117  * ALT_USB_DEV_DAINT_OUTEPINT9_E_INACT | 0x0 | No Interrupt
67118  * ALT_USB_DEV_DAINT_OUTEPINT9_E_ACT | 0x1 | OUT Endpoint 9 Interrupt
67119  *
67120  * Field Access Macros:
67121  *
67122  */
67123 /*
67124  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT9
67125  *
67126  * No Interrupt
67127  */
67128 #define ALT_USB_DEV_DAINT_OUTEPINT9_E_INACT 0x0
67129 /*
67130  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT9
67131  *
67132  * OUT Endpoint 9 Interrupt
67133  */
67134 #define ALT_USB_DEV_DAINT_OUTEPINT9_E_ACT 0x1
67135 
67136 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */
67137 #define ALT_USB_DEV_DAINT_OUTEPINT9_LSB 25
67138 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */
67139 #define ALT_USB_DEV_DAINT_OUTEPINT9_MSB 25
67140 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */
67141 #define ALT_USB_DEV_DAINT_OUTEPINT9_WIDTH 1
67142 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT9 register field value. */
67143 #define ALT_USB_DEV_DAINT_OUTEPINT9_SET_MSK 0x02000000
67144 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT9 register field value. */
67145 #define ALT_USB_DEV_DAINT_OUTEPINT9_CLR_MSK 0xfdffffff
67146 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */
67147 #define ALT_USB_DEV_DAINT_OUTEPINT9_RESET 0x0
67148 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT9 field value from a register. */
67149 #define ALT_USB_DEV_DAINT_OUTEPINT9_GET(value) (((value) & 0x02000000) >> 25)
67150 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT9 register field value suitable for setting the register. */
67151 #define ALT_USB_DEV_DAINT_OUTEPINT9_SET(value) (((value) << 25) & 0x02000000)
67152 
67153 /*
67154  * Field : outepint10
67155  *
67156  * OUT Endpoint 10 Interrupt Bit
67157  *
67158  * Field Enumeration Values:
67159  *
67160  * Enum | Value | Description
67161  * :-------------------------------------|:------|:--------------------------
67162  * ALT_USB_DEV_DAINT_OUTEPINT10_E_INACT | 0x0 | No Interrupt
67163  * ALT_USB_DEV_DAINT_OUTEPINT10_E_ACT | 0x1 | OUT Endpoint 10 Interrupt
67164  *
67165  * Field Access Macros:
67166  *
67167  */
67168 /*
67169  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT10
67170  *
67171  * No Interrupt
67172  */
67173 #define ALT_USB_DEV_DAINT_OUTEPINT10_E_INACT 0x0
67174 /*
67175  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT10
67176  *
67177  * OUT Endpoint 10 Interrupt
67178  */
67179 #define ALT_USB_DEV_DAINT_OUTEPINT10_E_ACT 0x1
67180 
67181 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */
67182 #define ALT_USB_DEV_DAINT_OUTEPINT10_LSB 26
67183 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */
67184 #define ALT_USB_DEV_DAINT_OUTEPINT10_MSB 26
67185 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */
67186 #define ALT_USB_DEV_DAINT_OUTEPINT10_WIDTH 1
67187 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT10 register field value. */
67188 #define ALT_USB_DEV_DAINT_OUTEPINT10_SET_MSK 0x04000000
67189 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT10 register field value. */
67190 #define ALT_USB_DEV_DAINT_OUTEPINT10_CLR_MSK 0xfbffffff
67191 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */
67192 #define ALT_USB_DEV_DAINT_OUTEPINT10_RESET 0x0
67193 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT10 field value from a register. */
67194 #define ALT_USB_DEV_DAINT_OUTEPINT10_GET(value) (((value) & 0x04000000) >> 26)
67195 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT10 register field value suitable for setting the register. */
67196 #define ALT_USB_DEV_DAINT_OUTEPINT10_SET(value) (((value) << 26) & 0x04000000)
67197 
67198 /*
67199  * Field : outepint11
67200  *
67201  * OUT Endpoint 11 Interrupt Bit
67202  *
67203  * Field Enumeration Values:
67204  *
67205  * Enum | Value | Description
67206  * :-------------------------------------|:------|:--------------------------
67207  * ALT_USB_DEV_DAINT_OUTEPINT11_E_INACT | 0x0 | No Interrupt
67208  * ALT_USB_DEV_DAINT_OUTEPINT11_E_ACT | 0x1 | OUT Endpoint 11 Interrupt
67209  *
67210  * Field Access Macros:
67211  *
67212  */
67213 /*
67214  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT11
67215  *
67216  * No Interrupt
67217  */
67218 #define ALT_USB_DEV_DAINT_OUTEPINT11_E_INACT 0x0
67219 /*
67220  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT11
67221  *
67222  * OUT Endpoint 11 Interrupt
67223  */
67224 #define ALT_USB_DEV_DAINT_OUTEPINT11_E_ACT 0x1
67225 
67226 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */
67227 #define ALT_USB_DEV_DAINT_OUTEPINT11_LSB 27
67228 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */
67229 #define ALT_USB_DEV_DAINT_OUTEPINT11_MSB 27
67230 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */
67231 #define ALT_USB_DEV_DAINT_OUTEPINT11_WIDTH 1
67232 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT11 register field value. */
67233 #define ALT_USB_DEV_DAINT_OUTEPINT11_SET_MSK 0x08000000
67234 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT11 register field value. */
67235 #define ALT_USB_DEV_DAINT_OUTEPINT11_CLR_MSK 0xf7ffffff
67236 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */
67237 #define ALT_USB_DEV_DAINT_OUTEPINT11_RESET 0x0
67238 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT11 field value from a register. */
67239 #define ALT_USB_DEV_DAINT_OUTEPINT11_GET(value) (((value) & 0x08000000) >> 27)
67240 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT11 register field value suitable for setting the register. */
67241 #define ALT_USB_DEV_DAINT_OUTEPINT11_SET(value) (((value) << 27) & 0x08000000)
67242 
67243 /*
67244  * Field : outepint12
67245  *
67246  * OUT Endpoint 12 Interrupt Bit
67247  *
67248  * Field Enumeration Values:
67249  *
67250  * Enum | Value | Description
67251  * :-------------------------------------|:------|:--------------------------
67252  * ALT_USB_DEV_DAINT_OUTEPINT12_E_INACT | 0x0 | No Interrupt
67253  * ALT_USB_DEV_DAINT_OUTEPINT12_E_ACT | 0x1 | OUT Endpoint 12 Interrupt
67254  *
67255  * Field Access Macros:
67256  *
67257  */
67258 /*
67259  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT12
67260  *
67261  * No Interrupt
67262  */
67263 #define ALT_USB_DEV_DAINT_OUTEPINT12_E_INACT 0x0
67264 /*
67265  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT12
67266  *
67267  * OUT Endpoint 12 Interrupt
67268  */
67269 #define ALT_USB_DEV_DAINT_OUTEPINT12_E_ACT 0x1
67270 
67271 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */
67272 #define ALT_USB_DEV_DAINT_OUTEPINT12_LSB 28
67273 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */
67274 #define ALT_USB_DEV_DAINT_OUTEPINT12_MSB 28
67275 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */
67276 #define ALT_USB_DEV_DAINT_OUTEPINT12_WIDTH 1
67277 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT12 register field value. */
67278 #define ALT_USB_DEV_DAINT_OUTEPINT12_SET_MSK 0x10000000
67279 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT12 register field value. */
67280 #define ALT_USB_DEV_DAINT_OUTEPINT12_CLR_MSK 0xefffffff
67281 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */
67282 #define ALT_USB_DEV_DAINT_OUTEPINT12_RESET 0x0
67283 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT12 field value from a register. */
67284 #define ALT_USB_DEV_DAINT_OUTEPINT12_GET(value) (((value) & 0x10000000) >> 28)
67285 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT12 register field value suitable for setting the register. */
67286 #define ALT_USB_DEV_DAINT_OUTEPINT12_SET(value) (((value) << 28) & 0x10000000)
67287 
67288 /*
67289  * Field : outepint13
67290  *
67291  * OUT Endpoint 13 Interrupt Bit
67292  *
67293  * Field Enumeration Values:
67294  *
67295  * Enum | Value | Description
67296  * :-------------------------------------|:------|:--------------------------
67297  * ALT_USB_DEV_DAINT_OUTEPINT13_E_INACT | 0x0 | No Interrupt
67298  * ALT_USB_DEV_DAINT_OUTEPINT13_E_ACT | 0x1 | OUT Endpoint 13 Interrupt
67299  *
67300  * Field Access Macros:
67301  *
67302  */
67303 /*
67304  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT13
67305  *
67306  * No Interrupt
67307  */
67308 #define ALT_USB_DEV_DAINT_OUTEPINT13_E_INACT 0x0
67309 /*
67310  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT13
67311  *
67312  * OUT Endpoint 13 Interrupt
67313  */
67314 #define ALT_USB_DEV_DAINT_OUTEPINT13_E_ACT 0x1
67315 
67316 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */
67317 #define ALT_USB_DEV_DAINT_OUTEPINT13_LSB 29
67318 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */
67319 #define ALT_USB_DEV_DAINT_OUTEPINT13_MSB 29
67320 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */
67321 #define ALT_USB_DEV_DAINT_OUTEPINT13_WIDTH 1
67322 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT13 register field value. */
67323 #define ALT_USB_DEV_DAINT_OUTEPINT13_SET_MSK 0x20000000
67324 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT13 register field value. */
67325 #define ALT_USB_DEV_DAINT_OUTEPINT13_CLR_MSK 0xdfffffff
67326 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */
67327 #define ALT_USB_DEV_DAINT_OUTEPINT13_RESET 0x0
67328 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT13 field value from a register. */
67329 #define ALT_USB_DEV_DAINT_OUTEPINT13_GET(value) (((value) & 0x20000000) >> 29)
67330 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT13 register field value suitable for setting the register. */
67331 #define ALT_USB_DEV_DAINT_OUTEPINT13_SET(value) (((value) << 29) & 0x20000000)
67332 
67333 /*
67334  * Field : outepint14
67335  *
67336  * OUT Endpoint 14 Interrupt Bit
67337  *
67338  * Field Enumeration Values:
67339  *
67340  * Enum | Value | Description
67341  * :-------------------------------------|:------|:--------------------------
67342  * ALT_USB_DEV_DAINT_OUTEPINT14_E_INACT | 0x0 | No Interrupt
67343  * ALT_USB_DEV_DAINT_OUTEPINT14_E_ACT | 0x1 | OUT Endpoint 14 Interrupt
67344  *
67345  * Field Access Macros:
67346  *
67347  */
67348 /*
67349  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT14
67350  *
67351  * No Interrupt
67352  */
67353 #define ALT_USB_DEV_DAINT_OUTEPINT14_E_INACT 0x0
67354 /*
67355  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT14
67356  *
67357  * OUT Endpoint 14 Interrupt
67358  */
67359 #define ALT_USB_DEV_DAINT_OUTEPINT14_E_ACT 0x1
67360 
67361 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */
67362 #define ALT_USB_DEV_DAINT_OUTEPINT14_LSB 30
67363 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */
67364 #define ALT_USB_DEV_DAINT_OUTEPINT14_MSB 30
67365 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */
67366 #define ALT_USB_DEV_DAINT_OUTEPINT14_WIDTH 1
67367 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT14 register field value. */
67368 #define ALT_USB_DEV_DAINT_OUTEPINT14_SET_MSK 0x40000000
67369 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT14 register field value. */
67370 #define ALT_USB_DEV_DAINT_OUTEPINT14_CLR_MSK 0xbfffffff
67371 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */
67372 #define ALT_USB_DEV_DAINT_OUTEPINT14_RESET 0x0
67373 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT14 field value from a register. */
67374 #define ALT_USB_DEV_DAINT_OUTEPINT14_GET(value) (((value) & 0x40000000) >> 30)
67375 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT14 register field value suitable for setting the register. */
67376 #define ALT_USB_DEV_DAINT_OUTEPINT14_SET(value) (((value) << 30) & 0x40000000)
67377 
67378 /*
67379  * Field : outepint15
67380  *
67381  * OUT Endpoint 15 Interrupt Bit
67382  *
67383  * Field Enumeration Values:
67384  *
67385  * Enum | Value | Description
67386  * :-------------------------------------|:------|:--------------------------
67387  * ALT_USB_DEV_DAINT_OUTEPINT15_E_INACT | 0x0 | No Interrupt
67388  * ALT_USB_DEV_DAINT_OUTEPINT15_E_ACT | 0x1 | OUT Endpoint 15 Interrupt
67389  *
67390  * Field Access Macros:
67391  *
67392  */
67393 /*
67394  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT15
67395  *
67396  * No Interrupt
67397  */
67398 #define ALT_USB_DEV_DAINT_OUTEPINT15_E_INACT 0x0
67399 /*
67400  * Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT15
67401  *
67402  * OUT Endpoint 15 Interrupt
67403  */
67404 #define ALT_USB_DEV_DAINT_OUTEPINT15_E_ACT 0x1
67405 
67406 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */
67407 #define ALT_USB_DEV_DAINT_OUTEPINT15_LSB 31
67408 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */
67409 #define ALT_USB_DEV_DAINT_OUTEPINT15_MSB 31
67410 /* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */
67411 #define ALT_USB_DEV_DAINT_OUTEPINT15_WIDTH 1
67412 /* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT15 register field value. */
67413 #define ALT_USB_DEV_DAINT_OUTEPINT15_SET_MSK 0x80000000
67414 /* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT15 register field value. */
67415 #define ALT_USB_DEV_DAINT_OUTEPINT15_CLR_MSK 0x7fffffff
67416 /* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */
67417 #define ALT_USB_DEV_DAINT_OUTEPINT15_RESET 0x0
67418 /* Extracts the ALT_USB_DEV_DAINT_OUTEPINT15 field value from a register. */
67419 #define ALT_USB_DEV_DAINT_OUTEPINT15_GET(value) (((value) & 0x80000000) >> 31)
67420 /* Produces a ALT_USB_DEV_DAINT_OUTEPINT15 register field value suitable for setting the register. */
67421 #define ALT_USB_DEV_DAINT_OUTEPINT15_SET(value) (((value) << 31) & 0x80000000)
67422 
67423 #ifndef __ASSEMBLY__
67424 /*
67425  * WARNING: The C register and register group struct declarations are provided for
67426  * convenience and illustrative purposes. They should, however, be used with
67427  * caution as the C language standard provides no guarantees about the alignment or
67428  * atomicity of device memory accesses. The recommended practice for writing
67429  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
67430  * alt_write_word() functions.
67431  *
67432  * The struct declaration for register ALT_USB_DEV_DAINT.
67433  */
67434 struct ALT_USB_DEV_DAINT_s
67435 {
67436  const uint32_t inepint0 : 1; /* ALT_USB_DEV_DAINT_INEPINT0 */
67437  const uint32_t inepint1 : 1; /* ALT_USB_DEV_DAINT_INEPINT1 */
67438  const uint32_t inepint2 : 1; /* ALT_USB_DEV_DAINT_INEPINT2 */
67439  const uint32_t inepint3 : 1; /* ALT_USB_DEV_DAINT_INEPINT3 */
67440  const uint32_t inepint4 : 1; /* ALT_USB_DEV_DAINT_INEPINT4 */
67441  const uint32_t inepint5 : 1; /* ALT_USB_DEV_DAINT_INEPINT5 */
67442  const uint32_t inepint6 : 1; /* ALT_USB_DEV_DAINT_INEPINT6 */
67443  const uint32_t inepint7 : 1; /* ALT_USB_DEV_DAINT_INEPINT7 */
67444  const uint32_t inepint8 : 1; /* ALT_USB_DEV_DAINT_INEPINT8 */
67445  const uint32_t inepint9 : 1; /* ALT_USB_DEV_DAINT_INEPINT9 */
67446  const uint32_t inepint10 : 1; /* ALT_USB_DEV_DAINT_INEPINT10 */
67447  const uint32_t inepint11 : 1; /* ALT_USB_DEV_DAINT_INEPINT11 */
67448  const uint32_t inepint12 : 1; /* ALT_USB_DEV_DAINT_INEPINT12 */
67449  const uint32_t inepint13 : 1; /* ALT_USB_DEV_DAINT_INEPINT13 */
67450  const uint32_t inepint14 : 1; /* ALT_USB_DEV_DAINT_INEPINT14 */
67451  const uint32_t inepint15 : 1; /* ALT_USB_DEV_DAINT_INEPINT15 */
67452  const uint32_t outepint0 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT0 */
67453  const uint32_t outepint1 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT1 */
67454  const uint32_t outepint2 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT2 */
67455  const uint32_t outepint3 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT3 */
67456  const uint32_t outepint4 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT4 */
67457  const uint32_t outepint5 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT5 */
67458  const uint32_t outepint6 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT6 */
67459  const uint32_t outepint7 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT7 */
67460  const uint32_t outepint8 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT8 */
67461  const uint32_t outepint9 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT9 */
67462  const uint32_t outepint10 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT10 */
67463  const uint32_t outepint11 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT11 */
67464  const uint32_t outepint12 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT12 */
67465  const uint32_t outepint13 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT13 */
67466  const uint32_t outepint14 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT14 */
67467  const uint32_t outepint15 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT15 */
67468 };
67469 
67470 /* The typedef declaration for register ALT_USB_DEV_DAINT. */
67471 typedef volatile struct ALT_USB_DEV_DAINT_s ALT_USB_DEV_DAINT_t;
67472 #endif /* __ASSEMBLY__ */
67473 
67474 /* The reset value of the ALT_USB_DEV_DAINT register. */
67475 #define ALT_USB_DEV_DAINT_RESET 0x00000000
67476 /* The byte offset of the ALT_USB_DEV_DAINT register from the beginning of the component. */
67477 #define ALT_USB_DEV_DAINT_OFST 0x18
67478 /* The address of the ALT_USB_DEV_DAINT register. */
67479 #define ALT_USB_DEV_DAINT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DAINT_OFST))
67480 
67481 /*
67482  * Register : daintmsk
67483  *
67484  * Device All Endpoints Interrupt Mask Register
67485  *
67486  * Register Layout
67487  *
67488  * Bits | Access | Reset | Description
67489  * :-----|:-------|:------|:--------------------------------
67490  * [0] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK0
67491  * [1] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK1
67492  * [2] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK2
67493  * [3] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK3
67494  * [4] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK4
67495  * [5] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK5
67496  * [6] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK6
67497  * [7] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK7
67498  * [8] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK8
67499  * [9] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK9
67500  * [10] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK10
67501  * [11] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK11
67502  * [12] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK12
67503  * [13] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK13
67504  * [14] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK14
67505  * [15] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK15
67506  * [16] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK0
67507  * [17] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK1
67508  * [18] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK2
67509  * [19] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK3
67510  * [20] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK4
67511  * [21] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK5
67512  * [22] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK6
67513  * [23] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK7
67514  * [24] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK8
67515  * [25] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK9
67516  * [26] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK10
67517  * [27] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK11
67518  * [28] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK12
67519  * [29] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK13
67520  * [30] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK14
67521  * [31] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK15
67522  *
67523  */
67524 /*
67525  * Field : inepmsk0
67526  *
67527  * IN Endpoint 0 Interrupt mask Bit
67528  *
67529  * Field Enumeration Values:
67530  *
67531  * Enum | Value | Description
67532  * :--------------------------------------|:------|:-----------------------------
67533  * ALT_USB_DEV_DAINTMSK_INEPMSK0_E_MSK | 0x0 | IN Endpoint 0 Interrupt mask
67534  * ALT_USB_DEV_DAINTMSK_INEPMSK0_E_NOMSK | 0x1 | No Interrupt mask
67535  *
67536  * Field Access Macros:
67537  *
67538  */
67539 /*
67540  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK0
67541  *
67542  * IN Endpoint 0 Interrupt mask
67543  */
67544 #define ALT_USB_DEV_DAINTMSK_INEPMSK0_E_MSK 0x0
67545 /*
67546  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK0
67547  *
67548  * No Interrupt mask
67549  */
67550 #define ALT_USB_DEV_DAINTMSK_INEPMSK0_E_NOMSK 0x1
67551 
67552 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */
67553 #define ALT_USB_DEV_DAINTMSK_INEPMSK0_LSB 0
67554 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */
67555 #define ALT_USB_DEV_DAINTMSK_INEPMSK0_MSB 0
67556 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */
67557 #define ALT_USB_DEV_DAINTMSK_INEPMSK0_WIDTH 1
67558 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field value. */
67559 #define ALT_USB_DEV_DAINTMSK_INEPMSK0_SET_MSK 0x00000001
67560 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field value. */
67561 #define ALT_USB_DEV_DAINTMSK_INEPMSK0_CLR_MSK 0xfffffffe
67562 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */
67563 #define ALT_USB_DEV_DAINTMSK_INEPMSK0_RESET 0x0
67564 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK0 field value from a register. */
67565 #define ALT_USB_DEV_DAINTMSK_INEPMSK0_GET(value) (((value) & 0x00000001) >> 0)
67566 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK0 register field value suitable for setting the register. */
67567 #define ALT_USB_DEV_DAINTMSK_INEPMSK0_SET(value) (((value) << 0) & 0x00000001)
67568 
67569 /*
67570  * Field : inepmsk1
67571  *
67572  * IN Endpoint 1 Interrupt mask Bit
67573  *
67574  * Field Enumeration Values:
67575  *
67576  * Enum | Value | Description
67577  * :--------------------------------------|:------|:-----------------------------
67578  * ALT_USB_DEV_DAINTMSK_INEPMSK1_E_MSK | 0x0 | IN Endpoint 1 Interrupt mask
67579  * ALT_USB_DEV_DAINTMSK_INEPMSK1_E_NOMSK | 0x1 | No Interrupt mask
67580  *
67581  * Field Access Macros:
67582  *
67583  */
67584 /*
67585  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK1
67586  *
67587  * IN Endpoint 1 Interrupt mask
67588  */
67589 #define ALT_USB_DEV_DAINTMSK_INEPMSK1_E_MSK 0x0
67590 /*
67591  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK1
67592  *
67593  * No Interrupt mask
67594  */
67595 #define ALT_USB_DEV_DAINTMSK_INEPMSK1_E_NOMSK 0x1
67596 
67597 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */
67598 #define ALT_USB_DEV_DAINTMSK_INEPMSK1_LSB 1
67599 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */
67600 #define ALT_USB_DEV_DAINTMSK_INEPMSK1_MSB 1
67601 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */
67602 #define ALT_USB_DEV_DAINTMSK_INEPMSK1_WIDTH 1
67603 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field value. */
67604 #define ALT_USB_DEV_DAINTMSK_INEPMSK1_SET_MSK 0x00000002
67605 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field value. */
67606 #define ALT_USB_DEV_DAINTMSK_INEPMSK1_CLR_MSK 0xfffffffd
67607 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */
67608 #define ALT_USB_DEV_DAINTMSK_INEPMSK1_RESET 0x0
67609 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK1 field value from a register. */
67610 #define ALT_USB_DEV_DAINTMSK_INEPMSK1_GET(value) (((value) & 0x00000002) >> 1)
67611 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK1 register field value suitable for setting the register. */
67612 #define ALT_USB_DEV_DAINTMSK_INEPMSK1_SET(value) (((value) << 1) & 0x00000002)
67613 
67614 /*
67615  * Field : inepmsk2
67616  *
67617  * IN Endpoint 2 Interrupt mask Bit
67618  *
67619  * Field Enumeration Values:
67620  *
67621  * Enum | Value | Description
67622  * :--------------------------------------|:------|:-----------------------------
67623  * ALT_USB_DEV_DAINTMSK_INEPMSK2_E_MSK | 0x0 | IN Endpoint 2 Interrupt mask
67624  * ALT_USB_DEV_DAINTMSK_INEPMSK2_E_NOMSK | 0x1 | No Interrupt mask
67625  *
67626  * Field Access Macros:
67627  *
67628  */
67629 /*
67630  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK2
67631  *
67632  * IN Endpoint 2 Interrupt mask
67633  */
67634 #define ALT_USB_DEV_DAINTMSK_INEPMSK2_E_MSK 0x0
67635 /*
67636  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK2
67637  *
67638  * No Interrupt mask
67639  */
67640 #define ALT_USB_DEV_DAINTMSK_INEPMSK2_E_NOMSK 0x1
67641 
67642 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */
67643 #define ALT_USB_DEV_DAINTMSK_INEPMSK2_LSB 2
67644 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */
67645 #define ALT_USB_DEV_DAINTMSK_INEPMSK2_MSB 2
67646 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */
67647 #define ALT_USB_DEV_DAINTMSK_INEPMSK2_WIDTH 1
67648 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field value. */
67649 #define ALT_USB_DEV_DAINTMSK_INEPMSK2_SET_MSK 0x00000004
67650 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field value. */
67651 #define ALT_USB_DEV_DAINTMSK_INEPMSK2_CLR_MSK 0xfffffffb
67652 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */
67653 #define ALT_USB_DEV_DAINTMSK_INEPMSK2_RESET 0x0
67654 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK2 field value from a register. */
67655 #define ALT_USB_DEV_DAINTMSK_INEPMSK2_GET(value) (((value) & 0x00000004) >> 2)
67656 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK2 register field value suitable for setting the register. */
67657 #define ALT_USB_DEV_DAINTMSK_INEPMSK2_SET(value) (((value) << 2) & 0x00000004)
67658 
67659 /*
67660  * Field : inepmsk3
67661  *
67662  * IN Endpoint 3 Interrupt mask Bit
67663  *
67664  * Field Enumeration Values:
67665  *
67666  * Enum | Value | Description
67667  * :--------------------------------------|:------|:-----------------------------
67668  * ALT_USB_DEV_DAINTMSK_INEPMSK3_E_MSK | 0x0 | IN Endpoint 3 Interrupt mask
67669  * ALT_USB_DEV_DAINTMSK_INEPMSK3_E_NOMSK | 0x1 | No Interrupt mask
67670  *
67671  * Field Access Macros:
67672  *
67673  */
67674 /*
67675  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK3
67676  *
67677  * IN Endpoint 3 Interrupt mask
67678  */
67679 #define ALT_USB_DEV_DAINTMSK_INEPMSK3_E_MSK 0x0
67680 /*
67681  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK3
67682  *
67683  * No Interrupt mask
67684  */
67685 #define ALT_USB_DEV_DAINTMSK_INEPMSK3_E_NOMSK 0x1
67686 
67687 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */
67688 #define ALT_USB_DEV_DAINTMSK_INEPMSK3_LSB 3
67689 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */
67690 #define ALT_USB_DEV_DAINTMSK_INEPMSK3_MSB 3
67691 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */
67692 #define ALT_USB_DEV_DAINTMSK_INEPMSK3_WIDTH 1
67693 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field value. */
67694 #define ALT_USB_DEV_DAINTMSK_INEPMSK3_SET_MSK 0x00000008
67695 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field value. */
67696 #define ALT_USB_DEV_DAINTMSK_INEPMSK3_CLR_MSK 0xfffffff7
67697 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */
67698 #define ALT_USB_DEV_DAINTMSK_INEPMSK3_RESET 0x0
67699 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK3 field value from a register. */
67700 #define ALT_USB_DEV_DAINTMSK_INEPMSK3_GET(value) (((value) & 0x00000008) >> 3)
67701 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK3 register field value suitable for setting the register. */
67702 #define ALT_USB_DEV_DAINTMSK_INEPMSK3_SET(value) (((value) << 3) & 0x00000008)
67703 
67704 /*
67705  * Field : inepmsk4
67706  *
67707  * IN Endpoint 4 Interrupt mask Bit
67708  *
67709  * Field Enumeration Values:
67710  *
67711  * Enum | Value | Description
67712  * :--------------------------------------|:------|:-----------------------------
67713  * ALT_USB_DEV_DAINTMSK_INEPMSK4_E_MSK | 0x0 | IN Endpoint 4 Interrupt mask
67714  * ALT_USB_DEV_DAINTMSK_INEPMSK4_E_NOMSK | 0x1 | No Interrupt mask
67715  *
67716  * Field Access Macros:
67717  *
67718  */
67719 /*
67720  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK4
67721  *
67722  * IN Endpoint 4 Interrupt mask
67723  */
67724 #define ALT_USB_DEV_DAINTMSK_INEPMSK4_E_MSK 0x0
67725 /*
67726  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK4
67727  *
67728  * No Interrupt mask
67729  */
67730 #define ALT_USB_DEV_DAINTMSK_INEPMSK4_E_NOMSK 0x1
67731 
67732 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */
67733 #define ALT_USB_DEV_DAINTMSK_INEPMSK4_LSB 4
67734 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */
67735 #define ALT_USB_DEV_DAINTMSK_INEPMSK4_MSB 4
67736 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */
67737 #define ALT_USB_DEV_DAINTMSK_INEPMSK4_WIDTH 1
67738 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field value. */
67739 #define ALT_USB_DEV_DAINTMSK_INEPMSK4_SET_MSK 0x00000010
67740 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field value. */
67741 #define ALT_USB_DEV_DAINTMSK_INEPMSK4_CLR_MSK 0xffffffef
67742 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */
67743 #define ALT_USB_DEV_DAINTMSK_INEPMSK4_RESET 0x0
67744 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK4 field value from a register. */
67745 #define ALT_USB_DEV_DAINTMSK_INEPMSK4_GET(value) (((value) & 0x00000010) >> 4)
67746 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK4 register field value suitable for setting the register. */
67747 #define ALT_USB_DEV_DAINTMSK_INEPMSK4_SET(value) (((value) << 4) & 0x00000010)
67748 
67749 /*
67750  * Field : inepmsk5
67751  *
67752  * IN Endpoint 5 Interrupt mask Bit
67753  *
67754  * Field Enumeration Values:
67755  *
67756  * Enum | Value | Description
67757  * :--------------------------------------|:------|:-----------------------------
67758  * ALT_USB_DEV_DAINTMSK_INEPMSK5_E_MSK | 0x0 | IN Endpoint 5 Interrupt mask
67759  * ALT_USB_DEV_DAINTMSK_INEPMSK5_E_NOMSK | 0x1 | No Interrupt mask
67760  *
67761  * Field Access Macros:
67762  *
67763  */
67764 /*
67765  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK5
67766  *
67767  * IN Endpoint 5 Interrupt mask
67768  */
67769 #define ALT_USB_DEV_DAINTMSK_INEPMSK5_E_MSK 0x0
67770 /*
67771  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK5
67772  *
67773  * No Interrupt mask
67774  */
67775 #define ALT_USB_DEV_DAINTMSK_INEPMSK5_E_NOMSK 0x1
67776 
67777 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */
67778 #define ALT_USB_DEV_DAINTMSK_INEPMSK5_LSB 5
67779 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */
67780 #define ALT_USB_DEV_DAINTMSK_INEPMSK5_MSB 5
67781 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */
67782 #define ALT_USB_DEV_DAINTMSK_INEPMSK5_WIDTH 1
67783 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field value. */
67784 #define ALT_USB_DEV_DAINTMSK_INEPMSK5_SET_MSK 0x00000020
67785 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field value. */
67786 #define ALT_USB_DEV_DAINTMSK_INEPMSK5_CLR_MSK 0xffffffdf
67787 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */
67788 #define ALT_USB_DEV_DAINTMSK_INEPMSK5_RESET 0x0
67789 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK5 field value from a register. */
67790 #define ALT_USB_DEV_DAINTMSK_INEPMSK5_GET(value) (((value) & 0x00000020) >> 5)
67791 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK5 register field value suitable for setting the register. */
67792 #define ALT_USB_DEV_DAINTMSK_INEPMSK5_SET(value) (((value) << 5) & 0x00000020)
67793 
67794 /*
67795  * Field : inepmsk6
67796  *
67797  * IN Endpoint 6 Interrupt mask Bit
67798  *
67799  * Field Enumeration Values:
67800  *
67801  * Enum | Value | Description
67802  * :--------------------------------------|:------|:-----------------------------
67803  * ALT_USB_DEV_DAINTMSK_INEPMSK6_E_MSK | 0x0 | IN Endpoint 6 Interrupt mask
67804  * ALT_USB_DEV_DAINTMSK_INEPMSK6_E_NOMSK | 0x1 | No Interrupt mask
67805  *
67806  * Field Access Macros:
67807  *
67808  */
67809 /*
67810  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK6
67811  *
67812  * IN Endpoint 6 Interrupt mask
67813  */
67814 #define ALT_USB_DEV_DAINTMSK_INEPMSK6_E_MSK 0x0
67815 /*
67816  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK6
67817  *
67818  * No Interrupt mask
67819  */
67820 #define ALT_USB_DEV_DAINTMSK_INEPMSK6_E_NOMSK 0x1
67821 
67822 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */
67823 #define ALT_USB_DEV_DAINTMSK_INEPMSK6_LSB 6
67824 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */
67825 #define ALT_USB_DEV_DAINTMSK_INEPMSK6_MSB 6
67826 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */
67827 #define ALT_USB_DEV_DAINTMSK_INEPMSK6_WIDTH 1
67828 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field value. */
67829 #define ALT_USB_DEV_DAINTMSK_INEPMSK6_SET_MSK 0x00000040
67830 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field value. */
67831 #define ALT_USB_DEV_DAINTMSK_INEPMSK6_CLR_MSK 0xffffffbf
67832 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */
67833 #define ALT_USB_DEV_DAINTMSK_INEPMSK6_RESET 0x0
67834 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK6 field value from a register. */
67835 #define ALT_USB_DEV_DAINTMSK_INEPMSK6_GET(value) (((value) & 0x00000040) >> 6)
67836 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK6 register field value suitable for setting the register. */
67837 #define ALT_USB_DEV_DAINTMSK_INEPMSK6_SET(value) (((value) << 6) & 0x00000040)
67838 
67839 /*
67840  * Field : inepmsk7
67841  *
67842  * IN Endpoint 7 Interrupt mask Bit
67843  *
67844  * Field Enumeration Values:
67845  *
67846  * Enum | Value | Description
67847  * :--------------------------------------|:------|:-----------------------------
67848  * ALT_USB_DEV_DAINTMSK_INEPMSK7_E_MSK | 0x0 | IN Endpoint 7 Interrupt mask
67849  * ALT_USB_DEV_DAINTMSK_INEPMSK7_E_NOMSK | 0x1 | No Interrupt mask
67850  *
67851  * Field Access Macros:
67852  *
67853  */
67854 /*
67855  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK7
67856  *
67857  * IN Endpoint 7 Interrupt mask
67858  */
67859 #define ALT_USB_DEV_DAINTMSK_INEPMSK7_E_MSK 0x0
67860 /*
67861  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK7
67862  *
67863  * No Interrupt mask
67864  */
67865 #define ALT_USB_DEV_DAINTMSK_INEPMSK7_E_NOMSK 0x1
67866 
67867 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */
67868 #define ALT_USB_DEV_DAINTMSK_INEPMSK7_LSB 7
67869 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */
67870 #define ALT_USB_DEV_DAINTMSK_INEPMSK7_MSB 7
67871 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */
67872 #define ALT_USB_DEV_DAINTMSK_INEPMSK7_WIDTH 1
67873 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field value. */
67874 #define ALT_USB_DEV_DAINTMSK_INEPMSK7_SET_MSK 0x00000080
67875 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field value. */
67876 #define ALT_USB_DEV_DAINTMSK_INEPMSK7_CLR_MSK 0xffffff7f
67877 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */
67878 #define ALT_USB_DEV_DAINTMSK_INEPMSK7_RESET 0x0
67879 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK7 field value from a register. */
67880 #define ALT_USB_DEV_DAINTMSK_INEPMSK7_GET(value) (((value) & 0x00000080) >> 7)
67881 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK7 register field value suitable for setting the register. */
67882 #define ALT_USB_DEV_DAINTMSK_INEPMSK7_SET(value) (((value) << 7) & 0x00000080)
67883 
67884 /*
67885  * Field : inepmsk8
67886  *
67887  * IN Endpoint 8 Interrupt mask Bit
67888  *
67889  * Field Enumeration Values:
67890  *
67891  * Enum | Value | Description
67892  * :--------------------------------------|:------|:-----------------------------
67893  * ALT_USB_DEV_DAINTMSK_INEPMSK8_E_MSK | 0x0 | IN Endpoint 8 Interrupt mask
67894  * ALT_USB_DEV_DAINTMSK_INEPMSK8_E_NOMSK | 0x1 | No Interrupt mask
67895  *
67896  * Field Access Macros:
67897  *
67898  */
67899 /*
67900  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK8
67901  *
67902  * IN Endpoint 8 Interrupt mask
67903  */
67904 #define ALT_USB_DEV_DAINTMSK_INEPMSK8_E_MSK 0x0
67905 /*
67906  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK8
67907  *
67908  * No Interrupt mask
67909  */
67910 #define ALT_USB_DEV_DAINTMSK_INEPMSK8_E_NOMSK 0x1
67911 
67912 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */
67913 #define ALT_USB_DEV_DAINTMSK_INEPMSK8_LSB 8
67914 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */
67915 #define ALT_USB_DEV_DAINTMSK_INEPMSK8_MSB 8
67916 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */
67917 #define ALT_USB_DEV_DAINTMSK_INEPMSK8_WIDTH 1
67918 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field value. */
67919 #define ALT_USB_DEV_DAINTMSK_INEPMSK8_SET_MSK 0x00000100
67920 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field value. */
67921 #define ALT_USB_DEV_DAINTMSK_INEPMSK8_CLR_MSK 0xfffffeff
67922 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */
67923 #define ALT_USB_DEV_DAINTMSK_INEPMSK8_RESET 0x0
67924 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK8 field value from a register. */
67925 #define ALT_USB_DEV_DAINTMSK_INEPMSK8_GET(value) (((value) & 0x00000100) >> 8)
67926 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK8 register field value suitable for setting the register. */
67927 #define ALT_USB_DEV_DAINTMSK_INEPMSK8_SET(value) (((value) << 8) & 0x00000100)
67928 
67929 /*
67930  * Field : inepmsk9
67931  *
67932  * IN Endpoint 9 Interrupt mask Bit
67933  *
67934  * Field Enumeration Values:
67935  *
67936  * Enum | Value | Description
67937  * :--------------------------------------|:------|:-----------------------------
67938  * ALT_USB_DEV_DAINTMSK_INEPMSK9_E_MSK | 0x0 | IN Endpoint 0 Interrupt mask
67939  * ALT_USB_DEV_DAINTMSK_INEPMSK9_E_NOMSK | 0x1 | No Interrupt mask
67940  *
67941  * Field Access Macros:
67942  *
67943  */
67944 /*
67945  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK9
67946  *
67947  * IN Endpoint 0 Interrupt mask
67948  */
67949 #define ALT_USB_DEV_DAINTMSK_INEPMSK9_E_MSK 0x0
67950 /*
67951  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK9
67952  *
67953  * No Interrupt mask
67954  */
67955 #define ALT_USB_DEV_DAINTMSK_INEPMSK9_E_NOMSK 0x1
67956 
67957 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */
67958 #define ALT_USB_DEV_DAINTMSK_INEPMSK9_LSB 9
67959 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */
67960 #define ALT_USB_DEV_DAINTMSK_INEPMSK9_MSB 9
67961 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */
67962 #define ALT_USB_DEV_DAINTMSK_INEPMSK9_WIDTH 1
67963 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field value. */
67964 #define ALT_USB_DEV_DAINTMSK_INEPMSK9_SET_MSK 0x00000200
67965 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field value. */
67966 #define ALT_USB_DEV_DAINTMSK_INEPMSK9_CLR_MSK 0xfffffdff
67967 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */
67968 #define ALT_USB_DEV_DAINTMSK_INEPMSK9_RESET 0x0
67969 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK9 field value from a register. */
67970 #define ALT_USB_DEV_DAINTMSK_INEPMSK9_GET(value) (((value) & 0x00000200) >> 9)
67971 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK9 register field value suitable for setting the register. */
67972 #define ALT_USB_DEV_DAINTMSK_INEPMSK9_SET(value) (((value) << 9) & 0x00000200)
67973 
67974 /*
67975  * Field : inepmsk10
67976  *
67977  * IN Endpoint 10 Interrupt mask Bit
67978  *
67979  * Field Enumeration Values:
67980  *
67981  * Enum | Value | Description
67982  * :---------------------------------------|:------|:------------------------------
67983  * ALT_USB_DEV_DAINTMSK_INEPMSK10_E_MSK | 0x0 | IN Endpoint 10 Interrupt mask
67984  * ALT_USB_DEV_DAINTMSK_INEPMSK10_E_NOMSK | 0x1 | No Interrupt mask
67985  *
67986  * Field Access Macros:
67987  *
67988  */
67989 /*
67990  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK10
67991  *
67992  * IN Endpoint 10 Interrupt mask
67993  */
67994 #define ALT_USB_DEV_DAINTMSK_INEPMSK10_E_MSK 0x0
67995 /*
67996  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK10
67997  *
67998  * No Interrupt mask
67999  */
68000 #define ALT_USB_DEV_DAINTMSK_INEPMSK10_E_NOMSK 0x1
68001 
68002 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */
68003 #define ALT_USB_DEV_DAINTMSK_INEPMSK10_LSB 10
68004 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */
68005 #define ALT_USB_DEV_DAINTMSK_INEPMSK10_MSB 10
68006 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */
68007 #define ALT_USB_DEV_DAINTMSK_INEPMSK10_WIDTH 1
68008 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field value. */
68009 #define ALT_USB_DEV_DAINTMSK_INEPMSK10_SET_MSK 0x00000400
68010 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field value. */
68011 #define ALT_USB_DEV_DAINTMSK_INEPMSK10_CLR_MSK 0xfffffbff
68012 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */
68013 #define ALT_USB_DEV_DAINTMSK_INEPMSK10_RESET 0x0
68014 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK10 field value from a register. */
68015 #define ALT_USB_DEV_DAINTMSK_INEPMSK10_GET(value) (((value) & 0x00000400) >> 10)
68016 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK10 register field value suitable for setting the register. */
68017 #define ALT_USB_DEV_DAINTMSK_INEPMSK10_SET(value) (((value) << 10) & 0x00000400)
68018 
68019 /*
68020  * Field : inepmsk11
68021  *
68022  * IN Endpoint 11 Interrupt mask Bit
68023  *
68024  * Field Enumeration Values:
68025  *
68026  * Enum | Value | Description
68027  * :---------------------------------------|:------|:------------------------------
68028  * ALT_USB_DEV_DAINTMSK_INEPMSK11_E_MSK | 0x0 | IN Endpoint 11 Interrupt mask
68029  * ALT_USB_DEV_DAINTMSK_INEPMSK11_E_NOMSK | 0x1 | No Interrupt mask
68030  *
68031  * Field Access Macros:
68032  *
68033  */
68034 /*
68035  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK11
68036  *
68037  * IN Endpoint 11 Interrupt mask
68038  */
68039 #define ALT_USB_DEV_DAINTMSK_INEPMSK11_E_MSK 0x0
68040 /*
68041  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK11
68042  *
68043  * No Interrupt mask
68044  */
68045 #define ALT_USB_DEV_DAINTMSK_INEPMSK11_E_NOMSK 0x1
68046 
68047 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */
68048 #define ALT_USB_DEV_DAINTMSK_INEPMSK11_LSB 11
68049 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */
68050 #define ALT_USB_DEV_DAINTMSK_INEPMSK11_MSB 11
68051 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */
68052 #define ALT_USB_DEV_DAINTMSK_INEPMSK11_WIDTH 1
68053 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field value. */
68054 #define ALT_USB_DEV_DAINTMSK_INEPMSK11_SET_MSK 0x00000800
68055 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field value. */
68056 #define ALT_USB_DEV_DAINTMSK_INEPMSK11_CLR_MSK 0xfffff7ff
68057 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */
68058 #define ALT_USB_DEV_DAINTMSK_INEPMSK11_RESET 0x0
68059 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK11 field value from a register. */
68060 #define ALT_USB_DEV_DAINTMSK_INEPMSK11_GET(value) (((value) & 0x00000800) >> 11)
68061 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK11 register field value suitable for setting the register. */
68062 #define ALT_USB_DEV_DAINTMSK_INEPMSK11_SET(value) (((value) << 11) & 0x00000800)
68063 
68064 /*
68065  * Field : inepmsk12
68066  *
68067  * IN Endpoint 12 Interrupt mask Bit
68068  *
68069  * Field Enumeration Values:
68070  *
68071  * Enum | Value | Description
68072  * :---------------------------------------|:------|:------------------------------
68073  * ALT_USB_DEV_DAINTMSK_INEPMSK12_E_MSK | 0x0 | IN Endpoint 12 Interrupt mask
68074  * ALT_USB_DEV_DAINTMSK_INEPMSK12_E_NOMSK | 0x1 | No Interrupt mask
68075  *
68076  * Field Access Macros:
68077  *
68078  */
68079 /*
68080  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK12
68081  *
68082  * IN Endpoint 12 Interrupt mask
68083  */
68084 #define ALT_USB_DEV_DAINTMSK_INEPMSK12_E_MSK 0x0
68085 /*
68086  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK12
68087  *
68088  * No Interrupt mask
68089  */
68090 #define ALT_USB_DEV_DAINTMSK_INEPMSK12_E_NOMSK 0x1
68091 
68092 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */
68093 #define ALT_USB_DEV_DAINTMSK_INEPMSK12_LSB 12
68094 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */
68095 #define ALT_USB_DEV_DAINTMSK_INEPMSK12_MSB 12
68096 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */
68097 #define ALT_USB_DEV_DAINTMSK_INEPMSK12_WIDTH 1
68098 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field value. */
68099 #define ALT_USB_DEV_DAINTMSK_INEPMSK12_SET_MSK 0x00001000
68100 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field value. */
68101 #define ALT_USB_DEV_DAINTMSK_INEPMSK12_CLR_MSK 0xffffefff
68102 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */
68103 #define ALT_USB_DEV_DAINTMSK_INEPMSK12_RESET 0x0
68104 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK12 field value from a register. */
68105 #define ALT_USB_DEV_DAINTMSK_INEPMSK12_GET(value) (((value) & 0x00001000) >> 12)
68106 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK12 register field value suitable for setting the register. */
68107 #define ALT_USB_DEV_DAINTMSK_INEPMSK12_SET(value) (((value) << 12) & 0x00001000)
68108 
68109 /*
68110  * Field : inepmsk13
68111  *
68112  * IN Endpoint 13 Interrupt mask Bit
68113  *
68114  * Field Enumeration Values:
68115  *
68116  * Enum | Value | Description
68117  * :---------------------------------------|:------|:------------------------------
68118  * ALT_USB_DEV_DAINTMSK_INEPMSK13_E_MSK | 0x0 | IN Endpoint 13 Interrupt mask
68119  * ALT_USB_DEV_DAINTMSK_INEPMSK13_E_NOMSK | 0x1 | No Interrupt mask
68120  *
68121  * Field Access Macros:
68122  *
68123  */
68124 /*
68125  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK13
68126  *
68127  * IN Endpoint 13 Interrupt mask
68128  */
68129 #define ALT_USB_DEV_DAINTMSK_INEPMSK13_E_MSK 0x0
68130 /*
68131  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK13
68132  *
68133  * No Interrupt mask
68134  */
68135 #define ALT_USB_DEV_DAINTMSK_INEPMSK13_E_NOMSK 0x1
68136 
68137 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */
68138 #define ALT_USB_DEV_DAINTMSK_INEPMSK13_LSB 13
68139 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */
68140 #define ALT_USB_DEV_DAINTMSK_INEPMSK13_MSB 13
68141 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */
68142 #define ALT_USB_DEV_DAINTMSK_INEPMSK13_WIDTH 1
68143 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field value. */
68144 #define ALT_USB_DEV_DAINTMSK_INEPMSK13_SET_MSK 0x00002000
68145 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field value. */
68146 #define ALT_USB_DEV_DAINTMSK_INEPMSK13_CLR_MSK 0xffffdfff
68147 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */
68148 #define ALT_USB_DEV_DAINTMSK_INEPMSK13_RESET 0x0
68149 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK13 field value from a register. */
68150 #define ALT_USB_DEV_DAINTMSK_INEPMSK13_GET(value) (((value) & 0x00002000) >> 13)
68151 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK13 register field value suitable for setting the register. */
68152 #define ALT_USB_DEV_DAINTMSK_INEPMSK13_SET(value) (((value) << 13) & 0x00002000)
68153 
68154 /*
68155  * Field : inepmsk14
68156  *
68157  * IN Endpoint 14 Interrupt mask Bit
68158  *
68159  * Field Enumeration Values:
68160  *
68161  * Enum | Value | Description
68162  * :---------------------------------------|:------|:------------------------------
68163  * ALT_USB_DEV_DAINTMSK_INEPMSK14_E_MSK | 0x0 | IN Endpoint 14 Interrupt mask
68164  * ALT_USB_DEV_DAINTMSK_INEPMSK14_E_NOMSK | 0x1 | No Interrupt mask
68165  *
68166  * Field Access Macros:
68167  *
68168  */
68169 /*
68170  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK14
68171  *
68172  * IN Endpoint 14 Interrupt mask
68173  */
68174 #define ALT_USB_DEV_DAINTMSK_INEPMSK14_E_MSK 0x0
68175 /*
68176  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK14
68177  *
68178  * No Interrupt mask
68179  */
68180 #define ALT_USB_DEV_DAINTMSK_INEPMSK14_E_NOMSK 0x1
68181 
68182 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */
68183 #define ALT_USB_DEV_DAINTMSK_INEPMSK14_LSB 14
68184 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */
68185 #define ALT_USB_DEV_DAINTMSK_INEPMSK14_MSB 14
68186 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */
68187 #define ALT_USB_DEV_DAINTMSK_INEPMSK14_WIDTH 1
68188 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field value. */
68189 #define ALT_USB_DEV_DAINTMSK_INEPMSK14_SET_MSK 0x00004000
68190 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field value. */
68191 #define ALT_USB_DEV_DAINTMSK_INEPMSK14_CLR_MSK 0xffffbfff
68192 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */
68193 #define ALT_USB_DEV_DAINTMSK_INEPMSK14_RESET 0x0
68194 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK14 field value from a register. */
68195 #define ALT_USB_DEV_DAINTMSK_INEPMSK14_GET(value) (((value) & 0x00004000) >> 14)
68196 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK14 register field value suitable for setting the register. */
68197 #define ALT_USB_DEV_DAINTMSK_INEPMSK14_SET(value) (((value) << 14) & 0x00004000)
68198 
68199 /*
68200  * Field : inepmsk15
68201  *
68202  * IN Endpoint 15 Interrupt mask Bit
68203  *
68204  * Field Enumeration Values:
68205  *
68206  * Enum | Value | Description
68207  * :---------------------------------------|:------|:-----------------------------
68208  * ALT_USB_DEV_DAINTMSK_INEPMSK15_E_INACT | 0x0 | No Interrupt mask
68209  * ALT_USB_DEV_DAINTMSK_INEPMSK15_E_ACT | 0x1 | IN Endpoint 0 Interrupt mask
68210  *
68211  * Field Access Macros:
68212  *
68213  */
68214 /*
68215  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK15
68216  *
68217  * No Interrupt mask
68218  */
68219 #define ALT_USB_DEV_DAINTMSK_INEPMSK15_E_INACT 0x0
68220 /*
68221  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK15
68222  *
68223  * IN Endpoint 0 Interrupt mask
68224  */
68225 #define ALT_USB_DEV_DAINTMSK_INEPMSK15_E_ACT 0x1
68226 
68227 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */
68228 #define ALT_USB_DEV_DAINTMSK_INEPMSK15_LSB 15
68229 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */
68230 #define ALT_USB_DEV_DAINTMSK_INEPMSK15_MSB 15
68231 /* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */
68232 #define ALT_USB_DEV_DAINTMSK_INEPMSK15_WIDTH 1
68233 /* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field value. */
68234 #define ALT_USB_DEV_DAINTMSK_INEPMSK15_SET_MSK 0x00008000
68235 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field value. */
68236 #define ALT_USB_DEV_DAINTMSK_INEPMSK15_CLR_MSK 0xffff7fff
68237 /* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */
68238 #define ALT_USB_DEV_DAINTMSK_INEPMSK15_RESET 0x0
68239 /* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK15 field value from a register. */
68240 #define ALT_USB_DEV_DAINTMSK_INEPMSK15_GET(value) (((value) & 0x00008000) >> 15)
68241 /* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK15 register field value suitable for setting the register. */
68242 #define ALT_USB_DEV_DAINTMSK_INEPMSK15_SET(value) (((value) << 15) & 0x00008000)
68243 
68244 /*
68245  * Field : outepmsk0
68246  *
68247  * OUT Endpoint 0 Interrupt mask Bit
68248  *
68249  * Field Enumeration Values:
68250  *
68251  * Enum | Value | Description
68252  * :---------------------------------------|:------|:------------------------------
68253  * ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_MSK | 0x0 | OUT Endpoint 0 Interrupt mask
68254  * ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_NOMSK | 0x1 | No Interrupt mask
68255  *
68256  * Field Access Macros:
68257  *
68258  */
68259 /*
68260  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK0
68261  *
68262  * OUT Endpoint 0 Interrupt mask
68263  */
68264 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_MSK 0x0
68265 /*
68266  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK0
68267  *
68268  * No Interrupt mask
68269  */
68270 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_NOMSK 0x1
68271 
68272 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */
68273 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_LSB 16
68274 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */
68275 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_MSB 16
68276 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */
68277 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_WIDTH 1
68278 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field value. */
68279 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_SET_MSK 0x00010000
68280 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field value. */
68281 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_CLR_MSK 0xfffeffff
68282 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */
68283 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_RESET 0x0
68284 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 field value from a register. */
68285 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_GET(value) (((value) & 0x00010000) >> 16)
68286 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field value suitable for setting the register. */
68287 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_SET(value) (((value) << 16) & 0x00010000)
68288 
68289 /*
68290  * Field : outepmsk1
68291  *
68292  * OUT Endpoint 1 Interrupt mask Bit
68293  *
68294  * Field Enumeration Values:
68295  *
68296  * Enum | Value | Description
68297  * :---------------------------------------|:------|:------------------------------
68298  * ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_MSK | 0x0 | OUT Endpoint 1 Interrupt mask
68299  * ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_NOMSK | 0x1 | No Interrupt mask
68300  *
68301  * Field Access Macros:
68302  *
68303  */
68304 /*
68305  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK1
68306  *
68307  * OUT Endpoint 1 Interrupt mask
68308  */
68309 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_MSK 0x0
68310 /*
68311  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK1
68312  *
68313  * No Interrupt mask
68314  */
68315 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_NOMSK 0x1
68316 
68317 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */
68318 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_LSB 17
68319 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */
68320 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_MSB 17
68321 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */
68322 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_WIDTH 1
68323 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field value. */
68324 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_SET_MSK 0x00020000
68325 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field value. */
68326 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_CLR_MSK 0xfffdffff
68327 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */
68328 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_RESET 0x0
68329 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 field value from a register. */
68330 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_GET(value) (((value) & 0x00020000) >> 17)
68331 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field value suitable for setting the register. */
68332 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_SET(value) (((value) << 17) & 0x00020000)
68333 
68334 /*
68335  * Field : outepmsk2
68336  *
68337  * OUT Endpoint 2 Interrupt mask Bit
68338  *
68339  * Field Enumeration Values:
68340  *
68341  * Enum | Value | Description
68342  * :---------------------------------------|:------|:------------------------------
68343  * ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_MSK | 0x0 | OUT Endpoint 2 Interrupt mask
68344  * ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_NOMSK | 0x1 | No Interrupt mask
68345  *
68346  * Field Access Macros:
68347  *
68348  */
68349 /*
68350  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK2
68351  *
68352  * OUT Endpoint 2 Interrupt mask
68353  */
68354 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_MSK 0x0
68355 /*
68356  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK2
68357  *
68358  * No Interrupt mask
68359  */
68360 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_NOMSK 0x1
68361 
68362 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */
68363 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_LSB 18
68364 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */
68365 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_MSB 18
68366 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */
68367 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_WIDTH 1
68368 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field value. */
68369 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_SET_MSK 0x00040000
68370 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field value. */
68371 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_CLR_MSK 0xfffbffff
68372 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */
68373 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_RESET 0x0
68374 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 field value from a register. */
68375 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_GET(value) (((value) & 0x00040000) >> 18)
68376 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field value suitable for setting the register. */
68377 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_SET(value) (((value) << 18) & 0x00040000)
68378 
68379 /*
68380  * Field : outepmsk3
68381  *
68382  * OUT Endpoint 3 Interrupt mask Bit
68383  *
68384  * Field Enumeration Values:
68385  *
68386  * Enum | Value | Description
68387  * :---------------------------------------|:------|:------------------------------
68388  * ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_MSK | 0x0 | OUT Endpoint 3 Interrupt mask
68389  * ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_NOMSK | 0x1 | No Interrupt mask
68390  *
68391  * Field Access Macros:
68392  *
68393  */
68394 /*
68395  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK3
68396  *
68397  * OUT Endpoint 3 Interrupt mask
68398  */
68399 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_MSK 0x0
68400 /*
68401  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK3
68402  *
68403  * No Interrupt mask
68404  */
68405 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_NOMSK 0x1
68406 
68407 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */
68408 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_LSB 19
68409 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */
68410 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_MSB 19
68411 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */
68412 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_WIDTH 1
68413 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field value. */
68414 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_SET_MSK 0x00080000
68415 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field value. */
68416 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_CLR_MSK 0xfff7ffff
68417 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */
68418 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_RESET 0x0
68419 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 field value from a register. */
68420 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_GET(value) (((value) & 0x00080000) >> 19)
68421 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field value suitable for setting the register. */
68422 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_SET(value) (((value) << 19) & 0x00080000)
68423 
68424 /*
68425  * Field : outepmsk4
68426  *
68427  * OUT Endpoint 4 Interrupt mask Bit
68428  *
68429  * Field Enumeration Values:
68430  *
68431  * Enum | Value | Description
68432  * :---------------------------------------|:------|:------------------------------
68433  * ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_MSK | 0x0 | OUT Endpoint 4 Interrupt mask
68434  * ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_NOMSK | 0x1 | No Interrupt mask
68435  *
68436  * Field Access Macros:
68437  *
68438  */
68439 /*
68440  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK4
68441  *
68442  * OUT Endpoint 4 Interrupt mask
68443  */
68444 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_MSK 0x0
68445 /*
68446  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK4
68447  *
68448  * No Interrupt mask
68449  */
68450 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_NOMSK 0x1
68451 
68452 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */
68453 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_LSB 20
68454 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */
68455 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_MSB 20
68456 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */
68457 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_WIDTH 1
68458 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field value. */
68459 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_SET_MSK 0x00100000
68460 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field value. */
68461 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_CLR_MSK 0xffefffff
68462 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */
68463 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_RESET 0x0
68464 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 field value from a register. */
68465 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_GET(value) (((value) & 0x00100000) >> 20)
68466 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field value suitable for setting the register. */
68467 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_SET(value) (((value) << 20) & 0x00100000)
68468 
68469 /*
68470  * Field : outepmsk5
68471  *
68472  * OUT Endpoint 5 Interrupt mask Bit
68473  *
68474  * Field Enumeration Values:
68475  *
68476  * Enum | Value | Description
68477  * :---------------------------------------|:------|:------------------------------
68478  * ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_MSK | 0x0 | OUT Endpoint 5 Interrupt mask
68479  * ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_NOMSK | 0x1 | No Interrupt mask
68480  *
68481  * Field Access Macros:
68482  *
68483  */
68484 /*
68485  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK5
68486  *
68487  * OUT Endpoint 5 Interrupt mask
68488  */
68489 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_MSK 0x0
68490 /*
68491  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK5
68492  *
68493  * No Interrupt mask
68494  */
68495 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_NOMSK 0x1
68496 
68497 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */
68498 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_LSB 21
68499 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */
68500 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_MSB 21
68501 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */
68502 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_WIDTH 1
68503 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field value. */
68504 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_SET_MSK 0x00200000
68505 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field value. */
68506 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_CLR_MSK 0xffdfffff
68507 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */
68508 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_RESET 0x0
68509 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 field value from a register. */
68510 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_GET(value) (((value) & 0x00200000) >> 21)
68511 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field value suitable for setting the register. */
68512 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_SET(value) (((value) << 21) & 0x00200000)
68513 
68514 /*
68515  * Field : outepmsk6
68516  *
68517  * OUT Endpoint 6 Interrupt mask Bit
68518  *
68519  * Field Enumeration Values:
68520  *
68521  * Enum | Value | Description
68522  * :---------------------------------------|:------|:------------------------------
68523  * ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_MSK | 0x0 | OUT Endpoint 6 Interrupt mask
68524  * ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_NOMSK | 0x1 | No Interrupt mask
68525  *
68526  * Field Access Macros:
68527  *
68528  */
68529 /*
68530  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK6
68531  *
68532  * OUT Endpoint 6 Interrupt mask
68533  */
68534 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_MSK 0x0
68535 /*
68536  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK6
68537  *
68538  * No Interrupt mask
68539  */
68540 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_NOMSK 0x1
68541 
68542 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */
68543 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_LSB 22
68544 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */
68545 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_MSB 22
68546 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */
68547 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_WIDTH 1
68548 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field value. */
68549 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_SET_MSK 0x00400000
68550 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field value. */
68551 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_CLR_MSK 0xffbfffff
68552 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */
68553 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_RESET 0x0
68554 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 field value from a register. */
68555 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_GET(value) (((value) & 0x00400000) >> 22)
68556 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field value suitable for setting the register. */
68557 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_SET(value) (((value) << 22) & 0x00400000)
68558 
68559 /*
68560  * Field : outepmsk7
68561  *
68562  * OUT Endpoint 7 Interrupt mask Bit
68563  *
68564  * Field Enumeration Values:
68565  *
68566  * Enum | Value | Description
68567  * :---------------------------------------|:------|:------------------------------
68568  * ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_MSK | 0x0 | OUT Endpoint 7 Interrupt mask
68569  * ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_NOMSK | 0x1 | No Interrupt mask
68570  *
68571  * Field Access Macros:
68572  *
68573  */
68574 /*
68575  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK7
68576  *
68577  * OUT Endpoint 7 Interrupt mask
68578  */
68579 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_MSK 0x0
68580 /*
68581  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK7
68582  *
68583  * No Interrupt mask
68584  */
68585 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_NOMSK 0x1
68586 
68587 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */
68588 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_LSB 23
68589 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */
68590 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_MSB 23
68591 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */
68592 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_WIDTH 1
68593 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field value. */
68594 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_SET_MSK 0x00800000
68595 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field value. */
68596 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_CLR_MSK 0xff7fffff
68597 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */
68598 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_RESET 0x0
68599 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 field value from a register. */
68600 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_GET(value) (((value) & 0x00800000) >> 23)
68601 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field value suitable for setting the register. */
68602 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_SET(value) (((value) << 23) & 0x00800000)
68603 
68604 /*
68605  * Field : outepmsk8
68606  *
68607  * OUT Endpoint 8 Interrupt mask Bit
68608  *
68609  * Field Enumeration Values:
68610  *
68611  * Enum | Value | Description
68612  * :---------------------------------------|:------|:------------------------------
68613  * ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_MSK | 0x0 | OUT Endpoint 8 Interrupt mask
68614  * ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_NOMSK | 0x1 | No Interrupt mask
68615  *
68616  * Field Access Macros:
68617  *
68618  */
68619 /*
68620  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK8
68621  *
68622  * OUT Endpoint 8 Interrupt mask
68623  */
68624 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_MSK 0x0
68625 /*
68626  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK8
68627  *
68628  * No Interrupt mask
68629  */
68630 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_NOMSK 0x1
68631 
68632 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */
68633 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_LSB 24
68634 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */
68635 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_MSB 24
68636 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */
68637 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_WIDTH 1
68638 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field value. */
68639 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_SET_MSK 0x01000000
68640 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field value. */
68641 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_CLR_MSK 0xfeffffff
68642 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */
68643 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_RESET 0x0
68644 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 field value from a register. */
68645 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_GET(value) (((value) & 0x01000000) >> 24)
68646 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field value suitable for setting the register. */
68647 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_SET(value) (((value) << 24) & 0x01000000)
68648 
68649 /*
68650  * Field : outepmsk9
68651  *
68652  * OUT Endpoint 9 Interrupt mask Bit
68653  *
68654  * Field Enumeration Values:
68655  *
68656  * Enum | Value | Description
68657  * :---------------------------------------|:------|:------------------------------
68658  * ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_MSK | 0x0 | OUT Endpoint 9 Interrupt mask
68659  * ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_NOMSK | 0x1 | No Interrupt mask
68660  *
68661  * Field Access Macros:
68662  *
68663  */
68664 /*
68665  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK9
68666  *
68667  * OUT Endpoint 9 Interrupt mask
68668  */
68669 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_MSK 0x0
68670 /*
68671  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK9
68672  *
68673  * No Interrupt mask
68674  */
68675 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_NOMSK 0x1
68676 
68677 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */
68678 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_LSB 25
68679 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */
68680 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_MSB 25
68681 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */
68682 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_WIDTH 1
68683 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field value. */
68684 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_SET_MSK 0x02000000
68685 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field value. */
68686 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_CLR_MSK 0xfdffffff
68687 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */
68688 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_RESET 0x0
68689 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 field value from a register. */
68690 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_GET(value) (((value) & 0x02000000) >> 25)
68691 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field value suitable for setting the register. */
68692 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_SET(value) (((value) << 25) & 0x02000000)
68693 
68694 /*
68695  * Field : outepmsk10
68696  *
68697  * OUT Endpoint 10 Interrupt mask Bit
68698  *
68699  * Field Enumeration Values:
68700  *
68701  * Enum | Value | Description
68702  * :----------------------------------------|:------|:-------------------------------
68703  * ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_MSK | 0x0 | OUT Endpoint 10 Interrupt mask
68704  * ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_NOMSK | 0x1 | No Interrupt mask
68705  *
68706  * Field Access Macros:
68707  *
68708  */
68709 /*
68710  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK10
68711  *
68712  * OUT Endpoint 10 Interrupt mask
68713  */
68714 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_MSK 0x0
68715 /*
68716  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK10
68717  *
68718  * No Interrupt mask
68719  */
68720 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_NOMSK 0x1
68721 
68722 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */
68723 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_LSB 26
68724 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */
68725 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_MSB 26
68726 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */
68727 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_WIDTH 1
68728 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field value. */
68729 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_SET_MSK 0x04000000
68730 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field value. */
68731 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_CLR_MSK 0xfbffffff
68732 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */
68733 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_RESET 0x0
68734 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 field value from a register. */
68735 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_GET(value) (((value) & 0x04000000) >> 26)
68736 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field value suitable for setting the register. */
68737 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_SET(value) (((value) << 26) & 0x04000000)
68738 
68739 /*
68740  * Field : outepmsk11
68741  *
68742  * OUT Endpoint 11 Interrupt mask Bit
68743  *
68744  * Field Enumeration Values:
68745  *
68746  * Enum | Value | Description
68747  * :----------------------------------------|:------|:-------------------------------
68748  * ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_MSK | 0x0 | OUT Endpoint 11 Interrupt mask
68749  * ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_NOMSK | 0x1 | No Interrupt mask
68750  *
68751  * Field Access Macros:
68752  *
68753  */
68754 /*
68755  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK11
68756  *
68757  * OUT Endpoint 11 Interrupt mask
68758  */
68759 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_MSK 0x0
68760 /*
68761  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK11
68762  *
68763  * No Interrupt mask
68764  */
68765 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_NOMSK 0x1
68766 
68767 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */
68768 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_LSB 27
68769 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */
68770 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_MSB 27
68771 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */
68772 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_WIDTH 1
68773 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field value. */
68774 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_SET_MSK 0x08000000
68775 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field value. */
68776 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_CLR_MSK 0xf7ffffff
68777 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */
68778 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_RESET 0x0
68779 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 field value from a register. */
68780 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_GET(value) (((value) & 0x08000000) >> 27)
68781 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field value suitable for setting the register. */
68782 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_SET(value) (((value) << 27) & 0x08000000)
68783 
68784 /*
68785  * Field : outepmsk12
68786  *
68787  * OUT Endpoint 12 Interrupt mask Bit
68788  *
68789  * Field Enumeration Values:
68790  *
68791  * Enum | Value | Description
68792  * :----------------------------------------|:------|:-------------------------------
68793  * ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_MSK | 0x0 | OUT Endpoint 12 Interrupt mask
68794  * ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_NOMSK | 0x1 | No Interrupt mask
68795  *
68796  * Field Access Macros:
68797  *
68798  */
68799 /*
68800  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK12
68801  *
68802  * OUT Endpoint 12 Interrupt mask
68803  */
68804 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_MSK 0x0
68805 /*
68806  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK12
68807  *
68808  * No Interrupt mask
68809  */
68810 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_NOMSK 0x1
68811 
68812 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */
68813 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_LSB 28
68814 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */
68815 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_MSB 28
68816 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */
68817 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_WIDTH 1
68818 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field value. */
68819 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_SET_MSK 0x10000000
68820 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field value. */
68821 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_CLR_MSK 0xefffffff
68822 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */
68823 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_RESET 0x0
68824 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 field value from a register. */
68825 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_GET(value) (((value) & 0x10000000) >> 28)
68826 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field value suitable for setting the register. */
68827 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_SET(value) (((value) << 28) & 0x10000000)
68828 
68829 /*
68830  * Field : outepmsk13
68831  *
68832  * OUT Endpoint 13 Interrupt mask Bit
68833  *
68834  * Field Enumeration Values:
68835  *
68836  * Enum | Value | Description
68837  * :----------------------------------------|:------|:-------------------------------
68838  * ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_MSK | 0x0 | OUT Endpoint 13 Interrupt mask
68839  * ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_NOMSK | 0x1 | No Interrupt mask
68840  *
68841  * Field Access Macros:
68842  *
68843  */
68844 /*
68845  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK13
68846  *
68847  * OUT Endpoint 13 Interrupt mask
68848  */
68849 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_MSK 0x0
68850 /*
68851  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK13
68852  *
68853  * No Interrupt mask
68854  */
68855 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_NOMSK 0x1
68856 
68857 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */
68858 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_LSB 29
68859 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */
68860 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_MSB 29
68861 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */
68862 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_WIDTH 1
68863 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field value. */
68864 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_SET_MSK 0x20000000
68865 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field value. */
68866 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_CLR_MSK 0xdfffffff
68867 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */
68868 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_RESET 0x0
68869 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 field value from a register. */
68870 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_GET(value) (((value) & 0x20000000) >> 29)
68871 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field value suitable for setting the register. */
68872 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_SET(value) (((value) << 29) & 0x20000000)
68873 
68874 /*
68875  * Field : outepmsk14
68876  *
68877  * OUT Endpoint 14 Interrupt mask Bit
68878  *
68879  * Field Enumeration Values:
68880  *
68881  * Enum | Value | Description
68882  * :----------------------------------------|:------|:-------------------------------
68883  * ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_MSK | 0x0 | OUT Endpoint 14 Interrupt mask
68884  * ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_NOMSK | 0x1 | No Interrupt mask
68885  *
68886  * Field Access Macros:
68887  *
68888  */
68889 /*
68890  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK14
68891  *
68892  * OUT Endpoint 14 Interrupt mask
68893  */
68894 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_MSK 0x0
68895 /*
68896  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK14
68897  *
68898  * No Interrupt mask
68899  */
68900 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_NOMSK 0x1
68901 
68902 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */
68903 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_LSB 30
68904 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */
68905 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_MSB 30
68906 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */
68907 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_WIDTH 1
68908 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field value. */
68909 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_SET_MSK 0x40000000
68910 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field value. */
68911 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_CLR_MSK 0xbfffffff
68912 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */
68913 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_RESET 0x0
68914 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 field value from a register. */
68915 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_GET(value) (((value) & 0x40000000) >> 30)
68916 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field value suitable for setting the register. */
68917 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_SET(value) (((value) << 30) & 0x40000000)
68918 
68919 /*
68920  * Field : outepmsk15
68921  *
68922  * OUT Endpoint 15 Interrupt mask Bit
68923  *
68924  * Field Enumeration Values:
68925  *
68926  * Enum | Value | Description
68927  * :----------------------------------------|:------|:-------------------------------
68928  * ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_MSK | 0x0 | OUT Endpoint 15 Interrupt mask
68929  * ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_NOMSK | 0x1 | No Interrupt mask
68930  *
68931  * Field Access Macros:
68932  *
68933  */
68934 /*
68935  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK15
68936  *
68937  * OUT Endpoint 15 Interrupt mask
68938  */
68939 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_MSK 0x0
68940 /*
68941  * Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK15
68942  *
68943  * No Interrupt mask
68944  */
68945 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_NOMSK 0x1
68946 
68947 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */
68948 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_LSB 31
68949 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */
68950 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_MSB 31
68951 /* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */
68952 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_WIDTH 1
68953 /* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field value. */
68954 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_SET_MSK 0x80000000
68955 /* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field value. */
68956 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_CLR_MSK 0x7fffffff
68957 /* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */
68958 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_RESET 0x0
68959 /* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 field value from a register. */
68960 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_GET(value) (((value) & 0x80000000) >> 31)
68961 /* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field value suitable for setting the register. */
68962 #define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_SET(value) (((value) << 31) & 0x80000000)
68963 
68964 #ifndef __ASSEMBLY__
68965 /*
68966  * WARNING: The C register and register group struct declarations are provided for
68967  * convenience and illustrative purposes. They should, however, be used with
68968  * caution as the C language standard provides no guarantees about the alignment or
68969  * atomicity of device memory accesses. The recommended practice for writing
68970  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
68971  * alt_write_word() functions.
68972  *
68973  * The struct declaration for register ALT_USB_DEV_DAINTMSK.
68974  */
68975 struct ALT_USB_DEV_DAINTMSK_s
68976 {
68977  uint32_t inepmsk0 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK0 */
68978  uint32_t inepmsk1 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK1 */
68979  uint32_t inepmsk2 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK2 */
68980  uint32_t inepmsk3 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK3 */
68981  uint32_t inepmsk4 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK4 */
68982  uint32_t inepmsk5 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK5 */
68983  uint32_t inepmsk6 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK6 */
68984  uint32_t inepmsk7 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK7 */
68985  uint32_t inepmsk8 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK8 */
68986  uint32_t inepmsk9 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK9 */
68987  uint32_t inepmsk10 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK10 */
68988  uint32_t inepmsk11 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK11 */
68989  uint32_t inepmsk12 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK12 */
68990  uint32_t inepmsk13 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK13 */
68991  uint32_t inepmsk14 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK14 */
68992  uint32_t inepmsk15 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK15 */
68993  uint32_t outepmsk0 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK0 */
68994  uint32_t outepmsk1 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK1 */
68995  uint32_t outepmsk2 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK2 */
68996  uint32_t outepmsk3 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK3 */
68997  uint32_t outepmsk4 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK4 */
68998  uint32_t outepmsk5 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK5 */
68999  uint32_t outepmsk6 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK6 */
69000  uint32_t outepmsk7 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK7 */
69001  uint32_t outepmsk8 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK8 */
69002  uint32_t outepmsk9 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK9 */
69003  uint32_t outepmsk10 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK10 */
69004  uint32_t outepmsk11 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK11 */
69005  uint32_t outepmsk12 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK12 */
69006  uint32_t outepmsk13 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK13 */
69007  uint32_t outepmsk14 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK14 */
69008  uint32_t outepmsk15 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK15 */
69009 };
69010 
69011 /* The typedef declaration for register ALT_USB_DEV_DAINTMSK. */
69012 typedef volatile struct ALT_USB_DEV_DAINTMSK_s ALT_USB_DEV_DAINTMSK_t;
69013 #endif /* __ASSEMBLY__ */
69014 
69015 /* The reset value of the ALT_USB_DEV_DAINTMSK register. */
69016 #define ALT_USB_DEV_DAINTMSK_RESET 0x00000000
69017 /* The byte offset of the ALT_USB_DEV_DAINTMSK register from the beginning of the component. */
69018 #define ALT_USB_DEV_DAINTMSK_OFST 0x1c
69019 /* The address of the ALT_USB_DEV_DAINTMSK register. */
69020 #define ALT_USB_DEV_DAINTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DAINTMSK_OFST))
69021 
69022 /*
69023  * Register : dvbusdis
69024  *
69025  * Device VBUS Discharge Time Register
69026  *
69027  * Register Layout
69028  *
69029  * Bits | Access | Reset | Description
69030  * :--------|:-------|:-------|:------------------------------
69031  * [15:0] | RW | 0x17d7 | ALT_USB_DEV_DVBUSDIS_DVBUSDIS
69032  * [31:16] | ??? | 0x0 | *UNDEFINED*
69033  *
69034  */
69035 /*
69036  * Field : dvbusdis
69037  *
69038  * Device VBUS Discharge Time (DVBUSDis)
69039  *
69040  * Specifies the VBUS discharge time after VBUS pulsing during
69041  *
69042  * SRP. This value equals:
69043  *
69044  * VBUS discharge time in PHY clocks / 1, 024
69045  *
69046  * The value you use depends whether the PHY is operating at
69047  *
69048  * 30 MHz (16-bit data width) or 60 MHz (8-bit data width).
69049  *
69050  * Depending on your VBUS load, this value can need
69051  *
69052  * adjustment.
69053  *
69054  * Field Access Macros:
69055  *
69056  */
69057 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */
69058 #define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_LSB 0
69059 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */
69060 #define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_MSB 15
69061 /* The width in bits of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */
69062 #define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_WIDTH 16
69063 /* The mask used to set the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field value. */
69064 #define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_SET_MSK 0x0000ffff
69065 /* The mask used to clear the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field value. */
69066 #define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_CLR_MSK 0xffff0000
69067 /* The reset value of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */
69068 #define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_RESET 0x17d7
69069 /* Extracts the ALT_USB_DEV_DVBUSDIS_DVBUSDIS field value from a register. */
69070 #define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_GET(value) (((value) & 0x0000ffff) >> 0)
69071 /* Produces a ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field value suitable for setting the register. */
69072 #define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_SET(value) (((value) << 0) & 0x0000ffff)
69073 
69074 #ifndef __ASSEMBLY__
69075 /*
69076  * WARNING: The C register and register group struct declarations are provided for
69077  * convenience and illustrative purposes. They should, however, be used with
69078  * caution as the C language standard provides no guarantees about the alignment or
69079  * atomicity of device memory accesses. The recommended practice for writing
69080  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
69081  * alt_write_word() functions.
69082  *
69083  * The struct declaration for register ALT_USB_DEV_DVBUSDIS.
69084  */
69085 struct ALT_USB_DEV_DVBUSDIS_s
69086 {
69087  uint32_t dvbusdis : 16; /* ALT_USB_DEV_DVBUSDIS_DVBUSDIS */
69088  uint32_t : 16; /* *UNDEFINED* */
69089 };
69090 
69091 /* The typedef declaration for register ALT_USB_DEV_DVBUSDIS. */
69092 typedef volatile struct ALT_USB_DEV_DVBUSDIS_s ALT_USB_DEV_DVBUSDIS_t;
69093 #endif /* __ASSEMBLY__ */
69094 
69095 /* The reset value of the ALT_USB_DEV_DVBUSDIS register. */
69096 #define ALT_USB_DEV_DVBUSDIS_RESET 0x000017d7
69097 /* The byte offset of the ALT_USB_DEV_DVBUSDIS register from the beginning of the component. */
69098 #define ALT_USB_DEV_DVBUSDIS_OFST 0x28
69099 /* The address of the ALT_USB_DEV_DVBUSDIS register. */
69100 #define ALT_USB_DEV_DVBUSDIS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DVBUSDIS_OFST))
69101 
69102 /*
69103  * Register : dvbuspulse
69104  *
69105  * Device VBUS Pulsing Time Register
69106  *
69107  * Register Layout
69108  *
69109  * Bits | Access | Reset | Description
69110  * :--------|:-------|:------|:----------------------------------
69111  * [11:0] | RW | 0x5b8 | ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE
69112  * [31:12] | ??? | 0x0 | *UNDEFINED*
69113  *
69114  */
69115 /*
69116  * Field : dvbuspulse
69117  *
69118  * Device VBUS Pulsing Time (DVBUSPulse)
69119  *
69120  * Specifies the VBUS pulsing time during SRP. This value equals:
69121  *
69122  * VBUS pulsing time in PHY clocks / 1, 024
69123  *
69124  * The value you use depends whether the PHY is operating at 30
69125  *
69126  * MHz (16-bit data width) or 60 MHz (8-bit data width).
69127  *
69128  * Field Access Macros:
69129  *
69130  */
69131 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */
69132 #define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_LSB 0
69133 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */
69134 #define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_MSB 11
69135 /* The width in bits of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */
69136 #define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_WIDTH 12
69137 /* The mask used to set the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field value. */
69138 #define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_SET_MSK 0x00000fff
69139 /* The mask used to clear the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field value. */
69140 #define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_CLR_MSK 0xfffff000
69141 /* The reset value of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */
69142 #define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_RESET 0x5b8
69143 /* Extracts the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE field value from a register. */
69144 #define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_GET(value) (((value) & 0x00000fff) >> 0)
69145 /* Produces a ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field value suitable for setting the register. */
69146 #define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_SET(value) (((value) << 0) & 0x00000fff)
69147 
69148 #ifndef __ASSEMBLY__
69149 /*
69150  * WARNING: The C register and register group struct declarations are provided for
69151  * convenience and illustrative purposes. They should, however, be used with
69152  * caution as the C language standard provides no guarantees about the alignment or
69153  * atomicity of device memory accesses. The recommended practice for writing
69154  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
69155  * alt_write_word() functions.
69156  *
69157  * The struct declaration for register ALT_USB_DEV_DVBUSPULSE.
69158  */
69159 struct ALT_USB_DEV_DVBUSPULSE_s
69160 {
69161  uint32_t dvbuspulse : 12; /* ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE */
69162  uint32_t : 20; /* *UNDEFINED* */
69163 };
69164 
69165 /* The typedef declaration for register ALT_USB_DEV_DVBUSPULSE. */
69166 typedef volatile struct ALT_USB_DEV_DVBUSPULSE_s ALT_USB_DEV_DVBUSPULSE_t;
69167 #endif /* __ASSEMBLY__ */
69168 
69169 /* The reset value of the ALT_USB_DEV_DVBUSPULSE register. */
69170 #define ALT_USB_DEV_DVBUSPULSE_RESET 0x000005b8
69171 /* The byte offset of the ALT_USB_DEV_DVBUSPULSE register from the beginning of the component. */
69172 #define ALT_USB_DEV_DVBUSPULSE_OFST 0x2c
69173 /* The address of the ALT_USB_DEV_DVBUSPULSE register. */
69174 #define ALT_USB_DEV_DVBUSPULSE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DVBUSPULSE_OFST))
69175 
69176 /*
69177  * Register : dthrctl
69178  *
69179  * Device Threshold Control Register
69180  *
69181  * Register Layout
69182  *
69183  * Bits | Access | Reset | Description
69184  * :--------|:-------|:------|:--------------------------------
69185  * [0] | RW | 0x0 | ALT_USB_DEV_DTHRCTL_NONISOTHREN
69186  * [1] | RW | 0x0 | ALT_USB_DEV_DTHRCTL_ISOTHREN
69187  * [10:2] | RW | 0x8 | ALT_USB_DEV_DTHRCTL_TXTHRLEN
69188  * [12:11] | RW | 0x0 | ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
69189  * [15:13] | ??? | 0x0 | *UNDEFINED*
69190  * [16] | RW | 0x0 | ALT_USB_DEV_DTHRCTL_RXTHREN
69191  * [25:17] | RW | 0x8 | ALT_USB_DEV_DTHRCTL_RXTHRLEN
69192  * [26] | ??? | 0x1 | *UNDEFINED*
69193  * [27] | RW | 0x1 | ALT_USB_DEV_DTHRCTL_ARBPRKEN
69194  * [31:28] | ??? | 0x0 | *UNDEFINED*
69195  *
69196  */
69197 /*
69198  * Field : nonisothren
69199  *
69200  * Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn)
69201  *
69202  * When this bit is Set, the core enables thresholding For Non Isochronous IN
69203  *
69204  * endpoints.
69205  *
69206  * Field Enumeration Values:
69207  *
69208  * Enum | Value | Description
69209  * :---------------------------------------|:------|:--------------------
69210  * ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_DISD | 0x0 | No thresholding
69211  * ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_END | 0x1 | Enable thresholding
69212  *
69213  * Field Access Macros:
69214  *
69215  */
69216 /*
69217  * Enumerated value for register field ALT_USB_DEV_DTHRCTL_NONISOTHREN
69218  *
69219  * No thresholding
69220  */
69221 #define ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_DISD 0x0
69222 /*
69223  * Enumerated value for register field ALT_USB_DEV_DTHRCTL_NONISOTHREN
69224  *
69225  * Enable thresholding
69226  */
69227 #define ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_END 0x1
69228 
69229 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */
69230 #define ALT_USB_DEV_DTHRCTL_NONISOTHREN_LSB 0
69231 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */
69232 #define ALT_USB_DEV_DTHRCTL_NONISOTHREN_MSB 0
69233 /* The width in bits of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */
69234 #define ALT_USB_DEV_DTHRCTL_NONISOTHREN_WIDTH 1
69235 /* The mask used to set the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field value. */
69236 #define ALT_USB_DEV_DTHRCTL_NONISOTHREN_SET_MSK 0x00000001
69237 /* The mask used to clear the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field value. */
69238 #define ALT_USB_DEV_DTHRCTL_NONISOTHREN_CLR_MSK 0xfffffffe
69239 /* The reset value of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */
69240 #define ALT_USB_DEV_DTHRCTL_NONISOTHREN_RESET 0x0
69241 /* Extracts the ALT_USB_DEV_DTHRCTL_NONISOTHREN field value from a register. */
69242 #define ALT_USB_DEV_DTHRCTL_NONISOTHREN_GET(value) (((value) & 0x00000001) >> 0)
69243 /* Produces a ALT_USB_DEV_DTHRCTL_NONISOTHREN register field value suitable for setting the register. */
69244 #define ALT_USB_DEV_DTHRCTL_NONISOTHREN_SET(value) (((value) << 0) & 0x00000001)
69245 
69246 /*
69247  * Field : isothren
69248  *
69249  * ISO IN Endpoints Threshold Enable. (ISOThrEn)
69250  *
69251  * When this bit is Set, the core enables thresholding For isochronous IN
69252  *
69253  * endpoints.
69254  *
69255  * Field Enumeration Values:
69256  *
69257  * Enum | Value | Description
69258  * :------------------------------------|:------|:---------------------
69259  * ALT_USB_DEV_DTHRCTL_ISOTHREN_E_DISD | 0x0 | No thresholding
69260  * ALT_USB_DEV_DTHRCTL_ISOTHREN_E_END | 0x1 | Enables thresholding
69261  *
69262  * Field Access Macros:
69263  *
69264  */
69265 /*
69266  * Enumerated value for register field ALT_USB_DEV_DTHRCTL_ISOTHREN
69267  *
69268  * No thresholding
69269  */
69270 #define ALT_USB_DEV_DTHRCTL_ISOTHREN_E_DISD 0x0
69271 /*
69272  * Enumerated value for register field ALT_USB_DEV_DTHRCTL_ISOTHREN
69273  *
69274  * Enables thresholding
69275  */
69276 #define ALT_USB_DEV_DTHRCTL_ISOTHREN_E_END 0x1
69277 
69278 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */
69279 #define ALT_USB_DEV_DTHRCTL_ISOTHREN_LSB 1
69280 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */
69281 #define ALT_USB_DEV_DTHRCTL_ISOTHREN_MSB 1
69282 /* The width in bits of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */
69283 #define ALT_USB_DEV_DTHRCTL_ISOTHREN_WIDTH 1
69284 /* The mask used to set the ALT_USB_DEV_DTHRCTL_ISOTHREN register field value. */
69285 #define ALT_USB_DEV_DTHRCTL_ISOTHREN_SET_MSK 0x00000002
69286 /* The mask used to clear the ALT_USB_DEV_DTHRCTL_ISOTHREN register field value. */
69287 #define ALT_USB_DEV_DTHRCTL_ISOTHREN_CLR_MSK 0xfffffffd
69288 /* The reset value of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */
69289 #define ALT_USB_DEV_DTHRCTL_ISOTHREN_RESET 0x0
69290 /* Extracts the ALT_USB_DEV_DTHRCTL_ISOTHREN field value from a register. */
69291 #define ALT_USB_DEV_DTHRCTL_ISOTHREN_GET(value) (((value) & 0x00000002) >> 1)
69292 /* Produces a ALT_USB_DEV_DTHRCTL_ISOTHREN register field value suitable for setting the register. */
69293 #define ALT_USB_DEV_DTHRCTL_ISOTHREN_SET(value) (((value) << 1) & 0x00000002)
69294 
69295 /*
69296  * Field : txthrlen
69297  *
69298  * Transmit Threshold Length (TxThrLen)
69299  *
69300  * This field specifies Transmit thresholding size in DWORDS. This also forms
69301  *
69302  * the MAC threshold and specifies the amount of data in bytes to be in the
69303  *
69304  * corresponding endpoint transmit FIFO, before the core can start transmit
69305  *
69306  * on the USB. The threshold length has to be at least eight DWORDS when the
69307  *
69308  * value of AHBThrRatio is 2'h00. In case the AHBThrRatio is non zero the
69309  *
69310  * application needs to ensure that the AHB Threshold value does not go below
69311  *
69312  * the recommended eight DWORD. This field controls both isochronous and
69313  *
69314  * non-isochronous IN endpoint thresholds. The recommended value for ThrLen
69315  *
69316  * is to be the same as the programmed AHB Burst Length (GAHBCFG.HBstLen).
69317  *
69318  * Field Access Macros:
69319  *
69320  */
69321 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */
69322 #define ALT_USB_DEV_DTHRCTL_TXTHRLEN_LSB 2
69323 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */
69324 #define ALT_USB_DEV_DTHRCTL_TXTHRLEN_MSB 10
69325 /* The width in bits of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */
69326 #define ALT_USB_DEV_DTHRCTL_TXTHRLEN_WIDTH 9
69327 /* The mask used to set the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field value. */
69328 #define ALT_USB_DEV_DTHRCTL_TXTHRLEN_SET_MSK 0x000007fc
69329 /* The mask used to clear the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field value. */
69330 #define ALT_USB_DEV_DTHRCTL_TXTHRLEN_CLR_MSK 0xfffff803
69331 /* The reset value of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */
69332 #define ALT_USB_DEV_DTHRCTL_TXTHRLEN_RESET 0x8
69333 /* Extracts the ALT_USB_DEV_DTHRCTL_TXTHRLEN field value from a register. */
69334 #define ALT_USB_DEV_DTHRCTL_TXTHRLEN_GET(value) (((value) & 0x000007fc) >> 2)
69335 /* Produces a ALT_USB_DEV_DTHRCTL_TXTHRLEN register field value suitable for setting the register. */
69336 #define ALT_USB_DEV_DTHRCTL_TXTHRLEN_SET(value) (((value) << 2) & 0x000007fc)
69337 
69338 /*
69339  * Field : ahbthrratio
69340  *
69341  * AHB Threshold Ratio (AHBThrRatio)
69342  *
69343  * These bits define the ratio between the AHB threshold and the MAC threshold for
69344  * the
69345  *
69346  * transmit path only. The AHB threshold always remains less than or equal to the
69347  * USB
69348  *
69349  * threshold, because this does not increase overhead. Both the AHB and the MAC
69350  *
69351  * threshold must be DWORD-aligned. The application needs to program TxThrLen and
69352  * the
69353  *
69354  * AHBThrRatio to make the AHB Threshold value DWORD aligned. If the AHB threshold
69355  *
69356  * value is not DWORD aligned, the core might not behave correctly. When
69357  * programming
69358  *
69359  * the TxThrLen and AHBThrRatio, the application must ensure that the minimum AHB
69360  *
69361  * threshold value does not go below 8 DWORDS to meet the USB turnaround time
69362  *
69363  * requirements.
69364  *
69365  * 2'b00: AHB threshold = MAC threshold
69366  *
69367  * 2'b01: AHB threshold = MAC threshold / 2
69368  *
69369  * 2'b10: AHB threshold = MAC threshold / 4
69370  *
69371  * 2'b11: AHB threshold = MAC threshold / 8
69372  *
69373  * Field Enumeration Values:
69374  *
69375  * Enum | Value | Description
69376  * :---------------------------------------------|:------|:---------------------------------
69377  * ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESZERO | 0x0 | AHB threshold = MAC threshold
69378  * ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESONE | 0x1 | AHB threshold = MAC threshold /2
69379  * ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTWO | 0x2 | AHB threshold = MAC threshold /4
69380  * ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTHREE | 0x3 | AHB threshold = MAC threshold /
69381  *
69382  * Field Access Macros:
69383  *
69384  */
69385 /*
69386  * Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
69387  *
69388  * AHB threshold = MAC threshold
69389  */
69390 #define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESZERO 0x0
69391 /*
69392  * Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
69393  *
69394  * AHB threshold = MAC threshold /2
69395  */
69396 #define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESONE 0x1
69397 /*
69398  * Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
69399  *
69400  * AHB threshold = MAC threshold /4
69401  */
69402 #define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTWO 0x2
69403 /*
69404  * Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
69405  *
69406  * AHB threshold = MAC threshold /
69407  */
69408 #define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTHREE 0x3
69409 
69410 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */
69411 #define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_LSB 11
69412 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */
69413 #define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_MSB 12
69414 /* The width in bits of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */
69415 #define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_WIDTH 2
69416 /* The mask used to set the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field value. */
69417 #define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_SET_MSK 0x00001800
69418 /* The mask used to clear the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field value. */
69419 #define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_CLR_MSK 0xffffe7ff
69420 /* The reset value of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */
69421 #define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_RESET 0x0
69422 /* Extracts the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO field value from a register. */
69423 #define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_GET(value) (((value) & 0x00001800) >> 11)
69424 /* Produces a ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field value suitable for setting the register. */
69425 #define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_SET(value) (((value) << 11) & 0x00001800)
69426 
69427 /*
69428  * Field : rxthren
69429  *
69430  * Receive Threshold Enable (RxThrEn)
69431  *
69432  * When this bit is Set, the core enables thresholding in the receive direction.
69433  *
69434  * Note: We recommends that you do not enable RxThrEn, because it may cause
69435  *
69436  * issues in the RxFIFO especially during error conditions such as RxError and
69437  * Babble.
69438  *
69439  * Field Enumeration Values:
69440  *
69441  * Enum | Value | Description
69442  * :-----------------------------------|:------|:---------------------------------------------
69443  * ALT_USB_DEV_DTHRCTL_RXTHREN_E_DISD | 0x0 | Disable thresholding
69444  * ALT_USB_DEV_DTHRCTL_RXTHREN_E_END | 0x1 | Enable thresholding in the receive direction
69445  *
69446  * Field Access Macros:
69447  *
69448  */
69449 /*
69450  * Enumerated value for register field ALT_USB_DEV_DTHRCTL_RXTHREN
69451  *
69452  * Disable thresholding
69453  */
69454 #define ALT_USB_DEV_DTHRCTL_RXTHREN_E_DISD 0x0
69455 /*
69456  * Enumerated value for register field ALT_USB_DEV_DTHRCTL_RXTHREN
69457  *
69458  * Enable thresholding in the receive direction
69459  */
69460 #define ALT_USB_DEV_DTHRCTL_RXTHREN_E_END 0x1
69461 
69462 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */
69463 #define ALT_USB_DEV_DTHRCTL_RXTHREN_LSB 16
69464 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */
69465 #define ALT_USB_DEV_DTHRCTL_RXTHREN_MSB 16
69466 /* The width in bits of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */
69467 #define ALT_USB_DEV_DTHRCTL_RXTHREN_WIDTH 1
69468 /* The mask used to set the ALT_USB_DEV_DTHRCTL_RXTHREN register field value. */
69469 #define ALT_USB_DEV_DTHRCTL_RXTHREN_SET_MSK 0x00010000
69470 /* The mask used to clear the ALT_USB_DEV_DTHRCTL_RXTHREN register field value. */
69471 #define ALT_USB_DEV_DTHRCTL_RXTHREN_CLR_MSK 0xfffeffff
69472 /* The reset value of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */
69473 #define ALT_USB_DEV_DTHRCTL_RXTHREN_RESET 0x0
69474 /* Extracts the ALT_USB_DEV_DTHRCTL_RXTHREN field value from a register. */
69475 #define ALT_USB_DEV_DTHRCTL_RXTHREN_GET(value) (((value) & 0x00010000) >> 16)
69476 /* Produces a ALT_USB_DEV_DTHRCTL_RXTHREN register field value suitable for setting the register. */
69477 #define ALT_USB_DEV_DTHRCTL_RXTHREN_SET(value) (((value) << 16) & 0x00010000)
69478 
69479 /*
69480  * Field : rxthrlen
69481  *
69482  * Receive Threshold Length (RxThrLen)
69483  *
69484  * This field specifies Receive thresholding size in DWORDS.
69485  *
69486  * This field also specifies the amount of data received on the USB before the
69487  *
69488  * core can start transmitting on the AHB.
69489  *
69490  * The threshold length has to be at least eight DWORDS.
69491  *
69492  * The recommended value For ThrLen is to be the same as the programmed
69493  *
69494  * AHB Burst Length (GAHBCFG.HBstLen).
69495  *
69496  * Field Access Macros:
69497  *
69498  */
69499 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */
69500 #define ALT_USB_DEV_DTHRCTL_RXTHRLEN_LSB 17
69501 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */
69502 #define ALT_USB_DEV_DTHRCTL_RXTHRLEN_MSB 25
69503 /* The width in bits of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */
69504 #define ALT_USB_DEV_DTHRCTL_RXTHRLEN_WIDTH 9
69505 /* The mask used to set the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field value. */
69506 #define ALT_USB_DEV_DTHRCTL_RXTHRLEN_SET_MSK 0x03fe0000
69507 /* The mask used to clear the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field value. */
69508 #define ALT_USB_DEV_DTHRCTL_RXTHRLEN_CLR_MSK 0xfc01ffff
69509 /* The reset value of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */
69510 #define ALT_USB_DEV_DTHRCTL_RXTHRLEN_RESET 0x8
69511 /* Extracts the ALT_USB_DEV_DTHRCTL_RXTHRLEN field value from a register. */
69512 #define ALT_USB_DEV_DTHRCTL_RXTHRLEN_GET(value) (((value) & 0x03fe0000) >> 17)
69513 /* Produces a ALT_USB_DEV_DTHRCTL_RXTHRLEN register field value suitable for setting the register. */
69514 #define ALT_USB_DEV_DTHRCTL_RXTHRLEN_SET(value) (((value) << 17) & 0x03fe0000)
69515 
69516 /*
69517  * Field : arbprken
69518  *
69519  * Arbiter Parking Enable (ArbPrkEn)
69520  *
69521  * This bit controls internal DMA arbiter parking For IN endpoints. When
69522  *
69523  * thresholding is enabled and this bit is Set to one, Then the arbiter parks on
69524  * the
69525  *
69526  * IN endpoint For which there is a token received on the USB. This is done to
69527  *
69528  * avoid getting into underrun conditions. By Default the parking is enabled.
69529  *
69530  * Field Enumeration Values:
69531  *
69532  * Enum | Value | Description
69533  * :------------------------------------|:------|:--------------------------------------------
69534  * ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_DISD | 0x0 | Disable DMA arbiter parking
69535  * ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_END | 0x1 | Enable DMA arbiter parking for IN endpoints
69536  *
69537  * Field Access Macros:
69538  *
69539  */
69540 /*
69541  * Enumerated value for register field ALT_USB_DEV_DTHRCTL_ARBPRKEN
69542  *
69543  * Disable DMA arbiter parking
69544  */
69545 #define ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_DISD 0x0
69546 /*
69547  * Enumerated value for register field ALT_USB_DEV_DTHRCTL_ARBPRKEN
69548  *
69549  * Enable DMA arbiter parking for IN endpoints
69550  */
69551 #define ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_END 0x1
69552 
69553 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */
69554 #define ALT_USB_DEV_DTHRCTL_ARBPRKEN_LSB 27
69555 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */
69556 #define ALT_USB_DEV_DTHRCTL_ARBPRKEN_MSB 27
69557 /* The width in bits of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */
69558 #define ALT_USB_DEV_DTHRCTL_ARBPRKEN_WIDTH 1
69559 /* The mask used to set the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field value. */
69560 #define ALT_USB_DEV_DTHRCTL_ARBPRKEN_SET_MSK 0x08000000
69561 /* The mask used to clear the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field value. */
69562 #define ALT_USB_DEV_DTHRCTL_ARBPRKEN_CLR_MSK 0xf7ffffff
69563 /* The reset value of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */
69564 #define ALT_USB_DEV_DTHRCTL_ARBPRKEN_RESET 0x1
69565 /* Extracts the ALT_USB_DEV_DTHRCTL_ARBPRKEN field value from a register. */
69566 #define ALT_USB_DEV_DTHRCTL_ARBPRKEN_GET(value) (((value) & 0x08000000) >> 27)
69567 /* Produces a ALT_USB_DEV_DTHRCTL_ARBPRKEN register field value suitable for setting the register. */
69568 #define ALT_USB_DEV_DTHRCTL_ARBPRKEN_SET(value) (((value) << 27) & 0x08000000)
69569 
69570 #ifndef __ASSEMBLY__
69571 /*
69572  * WARNING: The C register and register group struct declarations are provided for
69573  * convenience and illustrative purposes. They should, however, be used with
69574  * caution as the C language standard provides no guarantees about the alignment or
69575  * atomicity of device memory accesses. The recommended practice for writing
69576  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
69577  * alt_write_word() functions.
69578  *
69579  * The struct declaration for register ALT_USB_DEV_DTHRCTL.
69580  */
69581 struct ALT_USB_DEV_DTHRCTL_s
69582 {
69583  uint32_t nonisothren : 1; /* ALT_USB_DEV_DTHRCTL_NONISOTHREN */
69584  uint32_t isothren : 1; /* ALT_USB_DEV_DTHRCTL_ISOTHREN */
69585  uint32_t txthrlen : 9; /* ALT_USB_DEV_DTHRCTL_TXTHRLEN */
69586  uint32_t ahbthrratio : 2; /* ALT_USB_DEV_DTHRCTL_AHBTHRRATIO */
69587  uint32_t : 3; /* *UNDEFINED* */
69588  uint32_t rxthren : 1; /* ALT_USB_DEV_DTHRCTL_RXTHREN */
69589  uint32_t rxthrlen : 9; /* ALT_USB_DEV_DTHRCTL_RXTHRLEN */
69590  uint32_t : 1; /* *UNDEFINED* */
69591  uint32_t arbprken : 1; /* ALT_USB_DEV_DTHRCTL_ARBPRKEN */
69592  uint32_t : 4; /* *UNDEFINED* */
69593 };
69594 
69595 /* The typedef declaration for register ALT_USB_DEV_DTHRCTL. */
69596 typedef volatile struct ALT_USB_DEV_DTHRCTL_s ALT_USB_DEV_DTHRCTL_t;
69597 #endif /* __ASSEMBLY__ */
69598 
69599 /* The reset value of the ALT_USB_DEV_DTHRCTL register. */
69600 #define ALT_USB_DEV_DTHRCTL_RESET 0x0c100020
69601 /* The byte offset of the ALT_USB_DEV_DTHRCTL register from the beginning of the component. */
69602 #define ALT_USB_DEV_DTHRCTL_OFST 0x30
69603 /* The address of the ALT_USB_DEV_DTHRCTL register. */
69604 #define ALT_USB_DEV_DTHRCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTHRCTL_OFST))
69605 
69606 /*
69607  * Register : diepempmsk
69608  *
69609  * Device IN Endpoint FIFO Empty Interrupt Mask Register
69610  *
69611  * Register Layout
69612  *
69613  * Bits | Access | Reset | Description
69614  * :--------|:-------|:------|:-------------------------------------------
69615  * [0] | RW | 0x0 | IN EP 0 Tx FIFO Empty Interrupt Mask Bits
69616  * [1] | RW | 0x0 | IN EP 1 Tx FIFO Empty Interrupt Mask Bits
69617  * [2] | RW | 0x0 | IN EP 2 Tx FIFO Empty Interrupt Mask Bits
69618  * [3] | RW | 0x0 | IN EP 3 Tx FIFO Empty Interrupt Mask Bits
69619  * [4] | RW | 0x0 | IN EP 4 Tx FIFO Empty Interrupt Mask Bits
69620  * [5] | RW | 0x0 | IN EP 5 Tx FIFO Empty Interrupt Mask Bits
69621  * [6] | RW | 0x0 | IN EP 6 Tx FIFO Empty Interrupt Mask Bits
69622  * [7] | RW | 0x0 | IN EP 7 Tx FIFO Empty Interrupt Mask Bits
69623  * [8] | RW | 0x0 | IN EP 8 Tx FIFO Empty Interrupt Mask Bits
69624  * [9] | RW | 0x0 | IN EP 9 Tx FIFO Empty Interrupt Mask Bits
69625  * [10] | RW | 0x0 | IN EP 10 Tx FIFO Empty Interrupt Mask Bits
69626  * [11] | RW | 0x0 | IN EP 11 Tx FIFO Empty Interrupt Mask Bits
69627  * [12] | RW | 0x0 | IN EP 12 Tx FIFO Empty Interrupt Mask Bits
69628  * [13] | RW | 0x0 | IN EP 13 Tx FIFO Empty Interrupt Mask Bits
69629  * [14] | RW | 0x0 | IN EP 14 Tx FIFO Empty Interrupt Mask Bits
69630  * [15] | RW | 0x0 | IN EP 15 Tx FIFO Empty Interrupt Mask Bits
69631  * [31:16] | ??? | 0x0 | *UNDEFINED*
69632  *
69633  */
69634 /*
69635  * Field : IN EP 0 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk0
69636  *
69637  * This bit acts as mask bits for DIEPINT0.
69638  *
69639  * Field Enumeration Values:
69640  *
69641  * Enum | Value | Description
69642  * :----------------------------------------------|:------|:---------------------------
69643  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_MSK | 0x0 | Mask End point 0 interrupt
69644  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_NOMSK | 0x1 | No mask
69645  *
69646  * Field Access Macros:
69647  *
69648  */
69649 /*
69650  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0
69651  *
69652  * Mask End point 0 interrupt
69653  */
69654 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_MSK 0x0
69655 /*
69656  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0
69657  *
69658  * No mask
69659  */
69660 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_NOMSK 0x1
69661 
69662 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */
69663 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_LSB 0
69664 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */
69665 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_MSB 0
69666 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */
69667 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_WIDTH 1
69668 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field value. */
69669 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_SET_MSK 0x00000001
69670 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field value. */
69671 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_CLR_MSK 0xfffffffe
69672 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */
69673 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_RESET 0x0
69674 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 field value from a register. */
69675 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_GET(value) (((value) & 0x00000001) >> 0)
69676 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field value suitable for setting the register. */
69677 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_SET(value) (((value) << 0) & 0x00000001)
69678 
69679 /*
69680  * Field : IN EP 1 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk1
69681  *
69682  * This bit acts as mask bits for DIEPINT1.
69683  *
69684  * Field Enumeration Values:
69685  *
69686  * Enum | Value | Description
69687  * :----------------------------------------------|:------|:---------------------------
69688  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_MSK | 0x0 | Mask End point 1 interrupt
69689  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_NOMSK | 0x1 | No mask
69690  *
69691  * Field Access Macros:
69692  *
69693  */
69694 /*
69695  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1
69696  *
69697  * Mask End point 1 interrupt
69698  */
69699 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_MSK 0x0
69700 /*
69701  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1
69702  *
69703  * No mask
69704  */
69705 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_NOMSK 0x1
69706 
69707 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */
69708 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_LSB 1
69709 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */
69710 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_MSB 1
69711 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */
69712 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_WIDTH 1
69713 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field value. */
69714 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_SET_MSK 0x00000002
69715 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field value. */
69716 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_CLR_MSK 0xfffffffd
69717 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */
69718 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_RESET 0x0
69719 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 field value from a register. */
69720 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_GET(value) (((value) & 0x00000002) >> 1)
69721 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field value suitable for setting the register. */
69722 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_SET(value) (((value) << 1) & 0x00000002)
69723 
69724 /*
69725  * Field : IN EP 2 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk2
69726  *
69727  * This bit acts as mask bits for DIEPINT2.
69728  *
69729  * Field Enumeration Values:
69730  *
69731  * Enum | Value | Description
69732  * :----------------------------------------------|:------|:---------------------------
69733  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_MSK | 0x0 | Mask End point 2 interrupt
69734  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_NOMSK | 0x1 | No mask
69735  *
69736  * Field Access Macros:
69737  *
69738  */
69739 /*
69740  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2
69741  *
69742  * Mask End point 2 interrupt
69743  */
69744 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_MSK 0x0
69745 /*
69746  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2
69747  *
69748  * No mask
69749  */
69750 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_NOMSK 0x1
69751 
69752 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */
69753 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_LSB 2
69754 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */
69755 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_MSB 2
69756 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */
69757 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_WIDTH 1
69758 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field value. */
69759 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_SET_MSK 0x00000004
69760 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field value. */
69761 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_CLR_MSK 0xfffffffb
69762 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */
69763 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_RESET 0x0
69764 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 field value from a register. */
69765 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_GET(value) (((value) & 0x00000004) >> 2)
69766 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field value suitable for setting the register. */
69767 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_SET(value) (((value) << 2) & 0x00000004)
69768 
69769 /*
69770  * Field : IN EP 3 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk3
69771  *
69772  * This bit acts as mask bits for DIEPINT3.
69773  *
69774  * Field Enumeration Values:
69775  *
69776  * Enum | Value | Description
69777  * :----------------------------------------------|:------|:---------------------------
69778  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_MSK | 0x0 | Mask End point 3 interrupt
69779  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_NOMSK | 0x1 | No mask
69780  *
69781  * Field Access Macros:
69782  *
69783  */
69784 /*
69785  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3
69786  *
69787  * Mask End point 3 interrupt
69788  */
69789 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_MSK 0x0
69790 /*
69791  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3
69792  *
69793  * No mask
69794  */
69795 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_NOMSK 0x1
69796 
69797 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */
69798 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_LSB 3
69799 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */
69800 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_MSB 3
69801 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */
69802 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_WIDTH 1
69803 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field value. */
69804 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_SET_MSK 0x00000008
69805 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field value. */
69806 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_CLR_MSK 0xfffffff7
69807 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */
69808 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_RESET 0x0
69809 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 field value from a register. */
69810 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_GET(value) (((value) & 0x00000008) >> 3)
69811 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field value suitable for setting the register. */
69812 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_SET(value) (((value) << 3) & 0x00000008)
69813 
69814 /*
69815  * Field : IN EP 4 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk4
69816  *
69817  * This bit acts as mask bits for DIEPINT4.
69818  *
69819  * Field Enumeration Values:
69820  *
69821  * Enum | Value | Description
69822  * :----------------------------------------------|:------|:---------------------------
69823  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_MSK | 0x0 | Mask End point 4 interrupt
69824  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_NOMSK | 0x1 | No mask
69825  *
69826  * Field Access Macros:
69827  *
69828  */
69829 /*
69830  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4
69831  *
69832  * Mask End point 4 interrupt
69833  */
69834 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_MSK 0x0
69835 /*
69836  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4
69837  *
69838  * No mask
69839  */
69840 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_NOMSK 0x1
69841 
69842 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */
69843 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_LSB 4
69844 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */
69845 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_MSB 4
69846 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */
69847 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_WIDTH 1
69848 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field value. */
69849 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_SET_MSK 0x00000010
69850 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field value. */
69851 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_CLR_MSK 0xffffffef
69852 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */
69853 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_RESET 0x0
69854 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 field value from a register. */
69855 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_GET(value) (((value) & 0x00000010) >> 4)
69856 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field value suitable for setting the register. */
69857 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_SET(value) (((value) << 4) & 0x00000010)
69858 
69859 /*
69860  * Field : IN EP 5 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk5
69861  *
69862  * This bit acts as mask bits for DIEPINT5.
69863  *
69864  * Field Enumeration Values:
69865  *
69866  * Enum | Value | Description
69867  * :----------------------------------------------|:------|:---------------------------
69868  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_MSK | 0x0 | Mask End point 5 interrupt
69869  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_NOMSK | 0x1 | No mask
69870  *
69871  * Field Access Macros:
69872  *
69873  */
69874 /*
69875  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5
69876  *
69877  * Mask End point 5 interrupt
69878  */
69879 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_MSK 0x0
69880 /*
69881  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5
69882  *
69883  * No mask
69884  */
69885 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_NOMSK 0x1
69886 
69887 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */
69888 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_LSB 5
69889 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */
69890 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_MSB 5
69891 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */
69892 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_WIDTH 1
69893 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field value. */
69894 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_SET_MSK 0x00000020
69895 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field value. */
69896 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_CLR_MSK 0xffffffdf
69897 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */
69898 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_RESET 0x0
69899 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 field value from a register. */
69900 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_GET(value) (((value) & 0x00000020) >> 5)
69901 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field value suitable for setting the register. */
69902 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_SET(value) (((value) << 5) & 0x00000020)
69903 
69904 /*
69905  * Field : IN EP 6 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk6
69906  *
69907  * This bit acts as mask bits for DIEPINT6.
69908  *
69909  * Field Enumeration Values:
69910  *
69911  * Enum | Value | Description
69912  * :----------------------------------------------|:------|:---------------------------
69913  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_MSK | 0x0 | Mask End point 6 interrupt
69914  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_NOMSK | 0x1 | No mask
69915  *
69916  * Field Access Macros:
69917  *
69918  */
69919 /*
69920  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6
69921  *
69922  * Mask End point 6 interrupt
69923  */
69924 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_MSK 0x0
69925 /*
69926  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6
69927  *
69928  * No mask
69929  */
69930 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_NOMSK 0x1
69931 
69932 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */
69933 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_LSB 6
69934 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */
69935 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_MSB 6
69936 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */
69937 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_WIDTH 1
69938 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field value. */
69939 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_SET_MSK 0x00000040
69940 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field value. */
69941 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_CLR_MSK 0xffffffbf
69942 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */
69943 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_RESET 0x0
69944 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 field value from a register. */
69945 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_GET(value) (((value) & 0x00000040) >> 6)
69946 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field value suitable for setting the register. */
69947 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_SET(value) (((value) << 6) & 0x00000040)
69948 
69949 /*
69950  * Field : IN EP 7 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk7
69951  *
69952  * This bit acts as mask bits for DIEPINT7.
69953  *
69954  * Field Enumeration Values:
69955  *
69956  * Enum | Value | Description
69957  * :----------------------------------------------|:------|:---------------------------
69958  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_MSK | 0x0 | Mask End point 7 interrupt
69959  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_NOMSK | 0x1 | No mask
69960  *
69961  * Field Access Macros:
69962  *
69963  */
69964 /*
69965  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7
69966  *
69967  * Mask End point 7 interrupt
69968  */
69969 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_MSK 0x0
69970 /*
69971  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7
69972  *
69973  * No mask
69974  */
69975 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_NOMSK 0x1
69976 
69977 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */
69978 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_LSB 7
69979 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */
69980 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_MSB 7
69981 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */
69982 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_WIDTH 1
69983 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field value. */
69984 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_SET_MSK 0x00000080
69985 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field value. */
69986 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_CLR_MSK 0xffffff7f
69987 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */
69988 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_RESET 0x0
69989 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 field value from a register. */
69990 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_GET(value) (((value) & 0x00000080) >> 7)
69991 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field value suitable for setting the register. */
69992 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_SET(value) (((value) << 7) & 0x00000080)
69993 
69994 /*
69995  * Field : IN EP 8 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk8
69996  *
69997  * This bit acts as mask bits for DIEPINT8.
69998  *
69999  * Field Enumeration Values:
70000  *
70001  * Enum | Value | Description
70002  * :----------------------------------------------|:------|:---------------------------
70003  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_MSK | 0x0 | Mask End point 8 interrupt
70004  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_NOMSK | 0x1 | No mask
70005  *
70006  * Field Access Macros:
70007  *
70008  */
70009 /*
70010  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8
70011  *
70012  * Mask End point 8 interrupt
70013  */
70014 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_MSK 0x0
70015 /*
70016  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8
70017  *
70018  * No mask
70019  */
70020 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_NOMSK 0x1
70021 
70022 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */
70023 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_LSB 8
70024 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */
70025 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_MSB 8
70026 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */
70027 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_WIDTH 1
70028 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field value. */
70029 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_SET_MSK 0x00000100
70030 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field value. */
70031 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_CLR_MSK 0xfffffeff
70032 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */
70033 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_RESET 0x0
70034 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 field value from a register. */
70035 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_GET(value) (((value) & 0x00000100) >> 8)
70036 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field value suitable for setting the register. */
70037 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_SET(value) (((value) << 8) & 0x00000100)
70038 
70039 /*
70040  * Field : IN EP 9 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk9
70041  *
70042  * This bit acts as mask bits for DIEPINT9.
70043  *
70044  * Field Enumeration Values:
70045  *
70046  * Enum | Value | Description
70047  * :----------------------------------------------|:------|:---------------------------
70048  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_MSK | 0x0 | Mask End point 9 interrupt
70049  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_NOMSK | 0x1 | No mask
70050  *
70051  * Field Access Macros:
70052  *
70053  */
70054 /*
70055  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9
70056  *
70057  * Mask End point 9 interrupt
70058  */
70059 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_MSK 0x0
70060 /*
70061  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9
70062  *
70063  * No mask
70064  */
70065 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_NOMSK 0x1
70066 
70067 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */
70068 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_LSB 9
70069 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */
70070 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_MSB 9
70071 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */
70072 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_WIDTH 1
70073 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field value. */
70074 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_SET_MSK 0x00000200
70075 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field value. */
70076 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_CLR_MSK 0xfffffdff
70077 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */
70078 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_RESET 0x0
70079 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 field value from a register. */
70080 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_GET(value) (((value) & 0x00000200) >> 9)
70081 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field value suitable for setting the register. */
70082 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_SET(value) (((value) << 9) & 0x00000200)
70083 
70084 /*
70085  * Field : IN EP 10 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk10
70086  *
70087  * This bit acts as mask bits for DIEPINT10.
70088  *
70089  * Field Enumeration Values:
70090  *
70091  * Enum | Value | Description
70092  * :-----------------------------------------------|:------|:----------------------------
70093  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_MSK | 0x0 | Mask End point 10 interrupt
70094  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_NOMSK | 0x1 | No mask
70095  *
70096  * Field Access Macros:
70097  *
70098  */
70099 /*
70100  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10
70101  *
70102  * Mask End point 10 interrupt
70103  */
70104 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_MSK 0x0
70105 /*
70106  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10
70107  *
70108  * No mask
70109  */
70110 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_NOMSK 0x1
70111 
70112 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */
70113 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_LSB 10
70114 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */
70115 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_MSB 10
70116 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */
70117 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_WIDTH 1
70118 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field value. */
70119 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_SET_MSK 0x00000400
70120 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field value. */
70121 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_CLR_MSK 0xfffffbff
70122 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */
70123 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_RESET 0x0
70124 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 field value from a register. */
70125 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_GET(value) (((value) & 0x00000400) >> 10)
70126 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field value suitable for setting the register. */
70127 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_SET(value) (((value) << 10) & 0x00000400)
70128 
70129 /*
70130  * Field : IN EP 11 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk11
70131  *
70132  * This bit acts as mask bits for DIEPINT11.
70133  *
70134  * Field Enumeration Values:
70135  *
70136  * Enum | Value | Description
70137  * :-----------------------------------------------|:------|:----------------------------
70138  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_MSK | 0x0 | Mask End point 11 interrupt
70139  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_NOMSK | 0x1 | No mask
70140  *
70141  * Field Access Macros:
70142  *
70143  */
70144 /*
70145  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11
70146  *
70147  * Mask End point 11 interrupt
70148  */
70149 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_MSK 0x0
70150 /*
70151  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11
70152  *
70153  * No mask
70154  */
70155 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_NOMSK 0x1
70156 
70157 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */
70158 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_LSB 11
70159 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */
70160 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_MSB 11
70161 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */
70162 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_WIDTH 1
70163 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field value. */
70164 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_SET_MSK 0x00000800
70165 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field value. */
70166 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_CLR_MSK 0xfffff7ff
70167 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */
70168 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_RESET 0x0
70169 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 field value from a register. */
70170 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_GET(value) (((value) & 0x00000800) >> 11)
70171 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field value suitable for setting the register. */
70172 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_SET(value) (((value) << 11) & 0x00000800)
70173 
70174 /*
70175  * Field : IN EP 12 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk12
70176  *
70177  * This bit acts as mask bits for DIEPINT12.
70178  *
70179  * Field Enumeration Values:
70180  *
70181  * Enum | Value | Description
70182  * :-----------------------------------------------|:------|:----------------------------
70183  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_MSK | 0x0 | Mask End point 12 interrupt
70184  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_NOMSK | 0x1 | No mask
70185  *
70186  * Field Access Macros:
70187  *
70188  */
70189 /*
70190  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12
70191  *
70192  * Mask End point 12 interrupt
70193  */
70194 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_MSK 0x0
70195 /*
70196  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12
70197  *
70198  * No mask
70199  */
70200 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_NOMSK 0x1
70201 
70202 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */
70203 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_LSB 12
70204 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */
70205 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_MSB 12
70206 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */
70207 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_WIDTH 1
70208 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field value. */
70209 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_SET_MSK 0x00001000
70210 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field value. */
70211 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_CLR_MSK 0xffffefff
70212 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */
70213 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_RESET 0x0
70214 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 field value from a register. */
70215 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_GET(value) (((value) & 0x00001000) >> 12)
70216 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field value suitable for setting the register. */
70217 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_SET(value) (((value) << 12) & 0x00001000)
70218 
70219 /*
70220  * Field : IN EP 13 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk13
70221  *
70222  * This bit acts as mask bits for DIEPINT13.
70223  *
70224  * Field Enumeration Values:
70225  *
70226  * Enum | Value | Description
70227  * :-----------------------------------------------|:------|:----------------------------
70228  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_MSK | 0x0 | Mask End point 12 interrupt
70229  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_NOMSK | 0x1 | No mask
70230  *
70231  * Field Access Macros:
70232  *
70233  */
70234 /*
70235  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13
70236  *
70237  * Mask End point 12 interrupt
70238  */
70239 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_MSK 0x0
70240 /*
70241  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13
70242  *
70243  * No mask
70244  */
70245 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_NOMSK 0x1
70246 
70247 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */
70248 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_LSB 13
70249 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */
70250 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_MSB 13
70251 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */
70252 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_WIDTH 1
70253 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field value. */
70254 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_SET_MSK 0x00002000
70255 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field value. */
70256 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_CLR_MSK 0xffffdfff
70257 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */
70258 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_RESET 0x0
70259 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 field value from a register. */
70260 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_GET(value) (((value) & 0x00002000) >> 13)
70261 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field value suitable for setting the register. */
70262 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_SET(value) (((value) << 13) & 0x00002000)
70263 
70264 /*
70265  * Field : IN EP 14 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk14
70266  *
70267  * This bit acts as mask bits for DIEPINT14.
70268  *
70269  * Field Enumeration Values:
70270  *
70271  * Enum | Value | Description
70272  * :-----------------------------------------------|:------|:----------------------------
70273  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_MSK | 0x0 | Mask End point 14 interrupt
70274  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_NOMSK | 0x1 | No mask
70275  *
70276  * Field Access Macros:
70277  *
70278  */
70279 /*
70280  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14
70281  *
70282  * Mask End point 14 interrupt
70283  */
70284 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_MSK 0x0
70285 /*
70286  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14
70287  *
70288  * No mask
70289  */
70290 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_NOMSK 0x1
70291 
70292 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */
70293 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_LSB 14
70294 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */
70295 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_MSB 14
70296 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */
70297 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_WIDTH 1
70298 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field value. */
70299 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_SET_MSK 0x00004000
70300 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field value. */
70301 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_CLR_MSK 0xffffbfff
70302 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */
70303 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_RESET 0x0
70304 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 field value from a register. */
70305 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_GET(value) (((value) & 0x00004000) >> 14)
70306 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field value suitable for setting the register. */
70307 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_SET(value) (((value) << 14) & 0x00004000)
70308 
70309 /*
70310  * Field : IN EP 15 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk15
70311  *
70312  * This bit acts as mask bits for DIEPINT15.
70313  *
70314  * Field Enumeration Values:
70315  *
70316  * Enum | Value | Description
70317  * :-----------------------------------------------|:------|:----------------------------
70318  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_MSK | 0x0 | Mask End point 15 interrupt
70319  * ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_NOMSK | 0x1 | No mask
70320  *
70321  * Field Access Macros:
70322  *
70323  */
70324 /*
70325  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15
70326  *
70327  * Mask End point 15 interrupt
70328  */
70329 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_MSK 0x0
70330 /*
70331  * Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15
70332  *
70333  * No mask
70334  */
70335 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_NOMSK 0x1
70336 
70337 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */
70338 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_LSB 15
70339 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */
70340 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_MSB 15
70341 /* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */
70342 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_WIDTH 1
70343 /* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field value. */
70344 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_SET_MSK 0x00008000
70345 /* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field value. */
70346 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_CLR_MSK 0xffff7fff
70347 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */
70348 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_RESET 0x0
70349 /* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 field value from a register. */
70350 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_GET(value) (((value) & 0x00008000) >> 15)
70351 /* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field value suitable for setting the register. */
70352 #define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_SET(value) (((value) << 15) & 0x00008000)
70353 
70354 #ifndef __ASSEMBLY__
70355 /*
70356  * WARNING: The C register and register group struct declarations are provided for
70357  * convenience and illustrative purposes. They should, however, be used with
70358  * caution as the C language standard provides no guarantees about the alignment or
70359  * atomicity of device memory accesses. The recommended practice for writing
70360  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
70361  * alt_write_word() functions.
70362  *
70363  * The struct declaration for register ALT_USB_DEV_DIEPEMPMSK.
70364  */
70365 struct ALT_USB_DEV_DIEPEMPMSK_s
70366 {
70367  uint32_t ineptxfempmsk0 : 1; /* IN EP 0 Tx FIFO Empty Interrupt Mask Bits */
70368  uint32_t ineptxfempmsk1 : 1; /* IN EP 1 Tx FIFO Empty Interrupt Mask Bits */
70369  uint32_t ineptxfempmsk2 : 1; /* IN EP 2 Tx FIFO Empty Interrupt Mask Bits */
70370  uint32_t ineptxfempmsk3 : 1; /* IN EP 3 Tx FIFO Empty Interrupt Mask Bits */
70371  uint32_t ineptxfempmsk4 : 1; /* IN EP 4 Tx FIFO Empty Interrupt Mask Bits */
70372  uint32_t ineptxfempmsk5 : 1; /* IN EP 5 Tx FIFO Empty Interrupt Mask Bits */
70373  uint32_t ineptxfempmsk6 : 1; /* IN EP 6 Tx FIFO Empty Interrupt Mask Bits */
70374  uint32_t ineptxfempmsk7 : 1; /* IN EP 7 Tx FIFO Empty Interrupt Mask Bits */
70375  uint32_t ineptxfempmsk8 : 1; /* IN EP 8 Tx FIFO Empty Interrupt Mask Bits */
70376  uint32_t ineptxfempmsk9 : 1; /* IN EP 9 Tx FIFO Empty Interrupt Mask Bits */
70377  uint32_t ineptxfempmsk10 : 1; /* IN EP 10 Tx FIFO Empty Interrupt Mask Bits */
70378  uint32_t ineptxfempmsk11 : 1; /* IN EP 11 Tx FIFO Empty Interrupt Mask Bits */
70379  uint32_t ineptxfempmsk12 : 1; /* IN EP 12 Tx FIFO Empty Interrupt Mask Bits */
70380  uint32_t ineptxfempmsk13 : 1; /* IN EP 13 Tx FIFO Empty Interrupt Mask Bits */
70381  uint32_t ineptxfempmsk14 : 1; /* IN EP 14 Tx FIFO Empty Interrupt Mask Bits */
70382  uint32_t ineptxfempmsk15 : 1; /* IN EP 15 Tx FIFO Empty Interrupt Mask Bits */
70383  uint32_t : 16; /* *UNDEFINED* */
70384 };
70385 
70386 /* The typedef declaration for register ALT_USB_DEV_DIEPEMPMSK. */
70387 typedef volatile struct ALT_USB_DEV_DIEPEMPMSK_s ALT_USB_DEV_DIEPEMPMSK_t;
70388 #endif /* __ASSEMBLY__ */
70389 
70390 /* The reset value of the ALT_USB_DEV_DIEPEMPMSK register. */
70391 #define ALT_USB_DEV_DIEPEMPMSK_RESET 0x00000000
70392 /* The byte offset of the ALT_USB_DEV_DIEPEMPMSK register from the beginning of the component. */
70393 #define ALT_USB_DEV_DIEPEMPMSK_OFST 0x34
70394 /* The address of the ALT_USB_DEV_DIEPEMPMSK register. */
70395 #define ALT_USB_DEV_DIEPEMPMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPEMPMSK_OFST))
70396 
70397 /*
70398  * Register : diepctl0
70399  *
70400  * Device Control IN Endpoint 0 Control Register
70401  *
70402  * Register Layout
70403  *
70404  * Bits | Access | Reset | Description
70405  * :--------|:---------|:------|:------------------------------
70406  * [1:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL0_MPS
70407  * [14:2] | ??? | 0x0 | *UNDEFINED*
70408  * [15] | R | 0x1 | ALT_USB_DEV_DIEPCTL0_USBACTEP
70409  * [16] | ??? | 0x0 | *UNDEFINED*
70410  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL0_NAKSTS
70411  * [19:18] | R | 0x0 | ALT_USB_DEV_DIEPCTL0_EPTYPE
70412  * [20] | ??? | 0x0 | *UNDEFINED*
70413  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL0_STALL
70414  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL0_TXFNUM
70415  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL0_CNAK
70416  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL0_SNAK
70417  * [29:28] | ??? | 0x0 | *UNDEFINED*
70418  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL0_EPDIS
70419  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL0_EPENA
70420  *
70421  */
70422 /*
70423  * Field : mps
70424  *
70425  * Maximum Packet Size (MPS)
70426  *
70427  * Applies to IN and OUT endpoints.
70428  *
70429  * The application must program this field with the maximum packet size For
70430  *
70431  * the current logical endpoint.
70432  *
70433  * 2'b00: 64 bytes
70434  *
70435  * 2'b01: 32 bytes
70436  *
70437  * 2'b10: 16 bytes
70438  *
70439  * 2'b11: 8 bytes
70440  *
70441  * Field Enumeration Values:
70442  *
70443  * Enum | Value | Description
70444  * :-----------------------------------|:------|:------------
70445  * ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES64 | 0x0 | 64 bytes
70446  * ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES32 | 0x1 | 32 bytes
70447  * ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES16 | 0x2 | 16 bytes
70448  * ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES8 | 0x3 | 8 bytes
70449  *
70450  * Field Access Macros:
70451  *
70452  */
70453 /*
70454  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS
70455  *
70456  * 64 bytes
70457  */
70458 #define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES64 0x0
70459 /*
70460  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS
70461  *
70462  * 32 bytes
70463  */
70464 #define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES32 0x1
70465 /*
70466  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS
70467  *
70468  * 16 bytes
70469  */
70470 #define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES16 0x2
70471 /*
70472  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS
70473  *
70474  * 8 bytes
70475  */
70476 #define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES8 0x3
70477 
70478 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_MPS register field. */
70479 #define ALT_USB_DEV_DIEPCTL0_MPS_LSB 0
70480 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_MPS register field. */
70481 #define ALT_USB_DEV_DIEPCTL0_MPS_MSB 1
70482 /* The width in bits of the ALT_USB_DEV_DIEPCTL0_MPS register field. */
70483 #define ALT_USB_DEV_DIEPCTL0_MPS_WIDTH 2
70484 /* The mask used to set the ALT_USB_DEV_DIEPCTL0_MPS register field value. */
70485 #define ALT_USB_DEV_DIEPCTL0_MPS_SET_MSK 0x00000003
70486 /* The mask used to clear the ALT_USB_DEV_DIEPCTL0_MPS register field value. */
70487 #define ALT_USB_DEV_DIEPCTL0_MPS_CLR_MSK 0xfffffffc
70488 /* The reset value of the ALT_USB_DEV_DIEPCTL0_MPS register field. */
70489 #define ALT_USB_DEV_DIEPCTL0_MPS_RESET 0x0
70490 /* Extracts the ALT_USB_DEV_DIEPCTL0_MPS field value from a register. */
70491 #define ALT_USB_DEV_DIEPCTL0_MPS_GET(value) (((value) & 0x00000003) >> 0)
70492 /* Produces a ALT_USB_DEV_DIEPCTL0_MPS register field value suitable for setting the register. */
70493 #define ALT_USB_DEV_DIEPCTL0_MPS_SET(value) (((value) << 0) & 0x00000003)
70494 
70495 /*
70496  * Field : usbactep
70497  *
70498  * USB Active Endpoint (USBActEP)
70499  *
70500  * This bit is always SET to 1, indicating that control endpoint 0 is always
70501  *
70502  * active in all configurations and interfaces.
70503  *
70504  * Field Enumeration Values:
70505  *
70506  * Enum | Value | Description
70507  * :-------------------------------------|:------|:----------------------------------
70508  * ALT_USB_DEV_DIEPCTL0_USBACTEP_E_ACT0 | 0x1 | Control endpoint is always active
70509  *
70510  * Field Access Macros:
70511  *
70512  */
70513 /*
70514  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_USBACTEP
70515  *
70516  * Control endpoint is always active
70517  */
70518 #define ALT_USB_DEV_DIEPCTL0_USBACTEP_E_ACT0 0x1
70519 
70520 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */
70521 #define ALT_USB_DEV_DIEPCTL0_USBACTEP_LSB 15
70522 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */
70523 #define ALT_USB_DEV_DIEPCTL0_USBACTEP_MSB 15
70524 /* The width in bits of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */
70525 #define ALT_USB_DEV_DIEPCTL0_USBACTEP_WIDTH 1
70526 /* The mask used to set the ALT_USB_DEV_DIEPCTL0_USBACTEP register field value. */
70527 #define ALT_USB_DEV_DIEPCTL0_USBACTEP_SET_MSK 0x00008000
70528 /* The mask used to clear the ALT_USB_DEV_DIEPCTL0_USBACTEP register field value. */
70529 #define ALT_USB_DEV_DIEPCTL0_USBACTEP_CLR_MSK 0xffff7fff
70530 /* The reset value of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */
70531 #define ALT_USB_DEV_DIEPCTL0_USBACTEP_RESET 0x1
70532 /* Extracts the ALT_USB_DEV_DIEPCTL0_USBACTEP field value from a register. */
70533 #define ALT_USB_DEV_DIEPCTL0_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
70534 /* Produces a ALT_USB_DEV_DIEPCTL0_USBACTEP register field value suitable for setting the register. */
70535 #define ALT_USB_DEV_DIEPCTL0_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
70536 
70537 /*
70538  * Field : naksts
70539  *
70540  * NAK Status (NAKSts)
70541  *
70542  * Indicates the following:
70543  *
70544  * 1'b0: The core is transmitting non-NAK handshakes based on the
70545  *
70546  * FIFO status
70547  *
70548  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
70549  *
70550  * When this bit is Set, either by the application or core, the core stops
70551  *
70552  * transmitting data, even If there is data available in the TxFIFO.
70553  *
70554  * Irrespective of this bit's setting, the core always responds to SETUP data
70555  *
70556  * packets with an ACK handshake.
70557  *
70558  * Field Enumeration Values:
70559  *
70560  * Enum | Value | Description
70561  * :------------------------------------|:------|:------------------------------------------------
70562  * ALT_USB_DEV_DIEPCTL0_NAKSTS_E_INACT | 0x0 | The core is transmitting non-NAK handshakes
70563  * : | | based on the FIFO status
70564  * ALT_USB_DEV_DIEPCTL0_NAKSTS_E_ACT | 0x1 | The core is transmitting NAK handshakes on this
70565  * : | | endpoint
70566  *
70567  * Field Access Macros:
70568  *
70569  */
70570 /*
70571  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_NAKSTS
70572  *
70573  * The core is transmitting non-NAK handshakes based on the FIFO status
70574  */
70575 #define ALT_USB_DEV_DIEPCTL0_NAKSTS_E_INACT 0x0
70576 /*
70577  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_NAKSTS
70578  *
70579  * The core is transmitting NAK handshakes on this endpoint
70580  */
70581 #define ALT_USB_DEV_DIEPCTL0_NAKSTS_E_ACT 0x1
70582 
70583 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */
70584 #define ALT_USB_DEV_DIEPCTL0_NAKSTS_LSB 17
70585 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */
70586 #define ALT_USB_DEV_DIEPCTL0_NAKSTS_MSB 17
70587 /* The width in bits of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */
70588 #define ALT_USB_DEV_DIEPCTL0_NAKSTS_WIDTH 1
70589 /* The mask used to set the ALT_USB_DEV_DIEPCTL0_NAKSTS register field value. */
70590 #define ALT_USB_DEV_DIEPCTL0_NAKSTS_SET_MSK 0x00020000
70591 /* The mask used to clear the ALT_USB_DEV_DIEPCTL0_NAKSTS register field value. */
70592 #define ALT_USB_DEV_DIEPCTL0_NAKSTS_CLR_MSK 0xfffdffff
70593 /* The reset value of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */
70594 #define ALT_USB_DEV_DIEPCTL0_NAKSTS_RESET 0x0
70595 /* Extracts the ALT_USB_DEV_DIEPCTL0_NAKSTS field value from a register. */
70596 #define ALT_USB_DEV_DIEPCTL0_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
70597 /* Produces a ALT_USB_DEV_DIEPCTL0_NAKSTS register field value suitable for setting the register. */
70598 #define ALT_USB_DEV_DIEPCTL0_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
70599 
70600 /*
70601  * Field : eptype
70602  *
70603  * Endpoint Type (EPType)
70604  *
70605  * Hardcoded to 00 For control.
70606  *
70607  * Field Enumeration Values:
70608  *
70609  * Enum | Value | Description
70610  * :----------------------------------|:------|:-------------------
70611  * ALT_USB_DEV_DIEPCTL0_EPTYPE_E_ACT | 0x0 | Endpoint Control 0
70612  *
70613  * Field Access Macros:
70614  *
70615  */
70616 /*
70617  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPTYPE
70618  *
70619  * Endpoint Control 0
70620  */
70621 #define ALT_USB_DEV_DIEPCTL0_EPTYPE_E_ACT 0x0
70622 
70623 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */
70624 #define ALT_USB_DEV_DIEPCTL0_EPTYPE_LSB 18
70625 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */
70626 #define ALT_USB_DEV_DIEPCTL0_EPTYPE_MSB 19
70627 /* The width in bits of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */
70628 #define ALT_USB_DEV_DIEPCTL0_EPTYPE_WIDTH 2
70629 /* The mask used to set the ALT_USB_DEV_DIEPCTL0_EPTYPE register field value. */
70630 #define ALT_USB_DEV_DIEPCTL0_EPTYPE_SET_MSK 0x000c0000
70631 /* The mask used to clear the ALT_USB_DEV_DIEPCTL0_EPTYPE register field value. */
70632 #define ALT_USB_DEV_DIEPCTL0_EPTYPE_CLR_MSK 0xfff3ffff
70633 /* The reset value of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */
70634 #define ALT_USB_DEV_DIEPCTL0_EPTYPE_RESET 0x0
70635 /* Extracts the ALT_USB_DEV_DIEPCTL0_EPTYPE field value from a register. */
70636 #define ALT_USB_DEV_DIEPCTL0_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
70637 /* Produces a ALT_USB_DEV_DIEPCTL0_EPTYPE register field value suitable for setting the register. */
70638 #define ALT_USB_DEV_DIEPCTL0_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
70639 
70640 /*
70641  * Field : stall
70642  *
70643  * STALL Handshake (Stall)
70644  *
70645  * The application can only Set this bit, and the core clears it, when a
70646  *
70647  * SETUP token is received For this endpoint. If a NAK bit, Global Nonperiodic
70648  *
70649  * IN NAK, or Global OUT NAK is Set along with this bit, the STALL
70650  *
70651  * bit takes priority.
70652  *
70653  * Field Enumeration Values:
70654  *
70655  * Enum | Value | Description
70656  * :-----------------------------------|:------|:----------------
70657  * ALT_USB_DEV_DIEPCTL0_STALL_E_INACT | 0x0 | No Stall
70658  * ALT_USB_DEV_DIEPCTL0_STALL_E_ACT | 0x1 | Stall Handshake
70659  *
70660  * Field Access Macros:
70661  *
70662  */
70663 /*
70664  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_STALL
70665  *
70666  * No Stall
70667  */
70668 #define ALT_USB_DEV_DIEPCTL0_STALL_E_INACT 0x0
70669 /*
70670  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_STALL
70671  *
70672  * Stall Handshake
70673  */
70674 #define ALT_USB_DEV_DIEPCTL0_STALL_E_ACT 0x1
70675 
70676 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_STALL register field. */
70677 #define ALT_USB_DEV_DIEPCTL0_STALL_LSB 21
70678 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_STALL register field. */
70679 #define ALT_USB_DEV_DIEPCTL0_STALL_MSB 21
70680 /* The width in bits of the ALT_USB_DEV_DIEPCTL0_STALL register field. */
70681 #define ALT_USB_DEV_DIEPCTL0_STALL_WIDTH 1
70682 /* The mask used to set the ALT_USB_DEV_DIEPCTL0_STALL register field value. */
70683 #define ALT_USB_DEV_DIEPCTL0_STALL_SET_MSK 0x00200000
70684 /* The mask used to clear the ALT_USB_DEV_DIEPCTL0_STALL register field value. */
70685 #define ALT_USB_DEV_DIEPCTL0_STALL_CLR_MSK 0xffdfffff
70686 /* The reset value of the ALT_USB_DEV_DIEPCTL0_STALL register field. */
70687 #define ALT_USB_DEV_DIEPCTL0_STALL_RESET 0x0
70688 /* Extracts the ALT_USB_DEV_DIEPCTL0_STALL field value from a register. */
70689 #define ALT_USB_DEV_DIEPCTL0_STALL_GET(value) (((value) & 0x00200000) >> 21)
70690 /* Produces a ALT_USB_DEV_DIEPCTL0_STALL register field value suitable for setting the register. */
70691 #define ALT_USB_DEV_DIEPCTL0_STALL_SET(value) (((value) << 21) & 0x00200000)
70692 
70693 /*
70694  * Field : txfnum
70695  *
70696  * TxFIFO Number (TxFNum)
70697  *
70698  * For Shared FIFO operation, this value is always Set to 0, indicating
70699  *
70700  * that control IN endpoint 0 data is always written in the Non-Periodic
70701  *
70702  * Transmit FIFO.
70703  *
70704  * For Dedicated FIFO operation, this value is Set to the FIFO number
70705  *
70706  * that is assigned to IN Endpoint 0.
70707  *
70708  * Field Access Macros:
70709  *
70710  */
70711 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */
70712 #define ALT_USB_DEV_DIEPCTL0_TXFNUM_LSB 22
70713 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */
70714 #define ALT_USB_DEV_DIEPCTL0_TXFNUM_MSB 25
70715 /* The width in bits of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */
70716 #define ALT_USB_DEV_DIEPCTL0_TXFNUM_WIDTH 4
70717 /* The mask used to set the ALT_USB_DEV_DIEPCTL0_TXFNUM register field value. */
70718 #define ALT_USB_DEV_DIEPCTL0_TXFNUM_SET_MSK 0x03c00000
70719 /* The mask used to clear the ALT_USB_DEV_DIEPCTL0_TXFNUM register field value. */
70720 #define ALT_USB_DEV_DIEPCTL0_TXFNUM_CLR_MSK 0xfc3fffff
70721 /* The reset value of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */
70722 #define ALT_USB_DEV_DIEPCTL0_TXFNUM_RESET 0x0
70723 /* Extracts the ALT_USB_DEV_DIEPCTL0_TXFNUM field value from a register. */
70724 #define ALT_USB_DEV_DIEPCTL0_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
70725 /* Produces a ALT_USB_DEV_DIEPCTL0_TXFNUM register field value suitable for setting the register. */
70726 #define ALT_USB_DEV_DIEPCTL0_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
70727 
70728 /*
70729  * Field : cnak
70730  *
70731  * Clear NAK (CNAK)
70732  *
70733  * A write to this bit clears the NAK bit For the endpoint.
70734  *
70735  * Field Enumeration Values:
70736  *
70737  * Enum | Value | Description
70738  * :----------------------------------|:------|:------------
70739  * ALT_USB_DEV_DIEPCTL0_CNAK_E_NOCLR | 0x0 | No action
70740  * ALT_USB_DEV_DIEPCTL0_CNAK_E_CLR | 0x1 | Clear NAK
70741  *
70742  * Field Access Macros:
70743  *
70744  */
70745 /*
70746  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_CNAK
70747  *
70748  * No action
70749  */
70750 #define ALT_USB_DEV_DIEPCTL0_CNAK_E_NOCLR 0x0
70751 /*
70752  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_CNAK
70753  *
70754  * Clear NAK
70755  */
70756 #define ALT_USB_DEV_DIEPCTL0_CNAK_E_CLR 0x1
70757 
70758 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */
70759 #define ALT_USB_DEV_DIEPCTL0_CNAK_LSB 26
70760 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */
70761 #define ALT_USB_DEV_DIEPCTL0_CNAK_MSB 26
70762 /* The width in bits of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */
70763 #define ALT_USB_DEV_DIEPCTL0_CNAK_WIDTH 1
70764 /* The mask used to set the ALT_USB_DEV_DIEPCTL0_CNAK register field value. */
70765 #define ALT_USB_DEV_DIEPCTL0_CNAK_SET_MSK 0x04000000
70766 /* The mask used to clear the ALT_USB_DEV_DIEPCTL0_CNAK register field value. */
70767 #define ALT_USB_DEV_DIEPCTL0_CNAK_CLR_MSK 0xfbffffff
70768 /* The reset value of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */
70769 #define ALT_USB_DEV_DIEPCTL0_CNAK_RESET 0x0
70770 /* Extracts the ALT_USB_DEV_DIEPCTL0_CNAK field value from a register. */
70771 #define ALT_USB_DEV_DIEPCTL0_CNAK_GET(value) (((value) & 0x04000000) >> 26)
70772 /* Produces a ALT_USB_DEV_DIEPCTL0_CNAK register field value suitable for setting the register. */
70773 #define ALT_USB_DEV_DIEPCTL0_CNAK_SET(value) (((value) << 26) & 0x04000000)
70774 
70775 /*
70776  * Field : snak
70777  *
70778  * Set NAK (SNAK)
70779  *
70780  * A write to this bit sets the NAK bit For the endpoint.
70781  *
70782  * Using this bit, the application can control the transmission of NAK
70783  *
70784  * handshakes on an endpoint. The core can also Set this bit For an
70785  *
70786  * endpoint after a SETUP packet is received on that endpoint.
70787  *
70788  * Field Enumeration Values:
70789  *
70790  * Enum | Value | Description
70791  * :----------------------------------|:------|:------------
70792  * ALT_USB_DEV_DIEPCTL0_SNAK_E_NOSET | 0x0 | No action
70793  * ALT_USB_DEV_DIEPCTL0_SNAK_E_SET | 0x1 | Set NAK
70794  *
70795  * Field Access Macros:
70796  *
70797  */
70798 /*
70799  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_SNAK
70800  *
70801  * No action
70802  */
70803 #define ALT_USB_DEV_DIEPCTL0_SNAK_E_NOSET 0x0
70804 /*
70805  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_SNAK
70806  *
70807  * Set NAK
70808  */
70809 #define ALT_USB_DEV_DIEPCTL0_SNAK_E_SET 0x1
70810 
70811 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */
70812 #define ALT_USB_DEV_DIEPCTL0_SNAK_LSB 27
70813 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */
70814 #define ALT_USB_DEV_DIEPCTL0_SNAK_MSB 27
70815 /* The width in bits of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */
70816 #define ALT_USB_DEV_DIEPCTL0_SNAK_WIDTH 1
70817 /* The mask used to set the ALT_USB_DEV_DIEPCTL0_SNAK register field value. */
70818 #define ALT_USB_DEV_DIEPCTL0_SNAK_SET_MSK 0x08000000
70819 /* The mask used to clear the ALT_USB_DEV_DIEPCTL0_SNAK register field value. */
70820 #define ALT_USB_DEV_DIEPCTL0_SNAK_CLR_MSK 0xf7ffffff
70821 /* The reset value of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */
70822 #define ALT_USB_DEV_DIEPCTL0_SNAK_RESET 0x0
70823 /* Extracts the ALT_USB_DEV_DIEPCTL0_SNAK field value from a register. */
70824 #define ALT_USB_DEV_DIEPCTL0_SNAK_GET(value) (((value) & 0x08000000) >> 27)
70825 /* Produces a ALT_USB_DEV_DIEPCTL0_SNAK register field value suitable for setting the register. */
70826 #define ALT_USB_DEV_DIEPCTL0_SNAK_SET(value) (((value) << 27) & 0x08000000)
70827 
70828 /*
70829  * Field : epdis
70830  *
70831  * Endpoint Disable (EPDis)
70832  *
70833  * The application sets this bit to stop transmitting data on an endpoint,
70834  *
70835  * even before the transfer For that endpoint is complete. The application
70836  *
70837  * must wait For the Endpoint Disabled interrupt before treating the endpoint
70838  *
70839  * as disabled. The core clears this bit before setting the Endpoint Disabled
70840  *
70841  * Interrupt. The application must Set this bit only If Endpoint Enable is
70842  *
70843  * already Set For this endpoint.
70844  *
70845  * Field Enumeration Values:
70846  *
70847  * Enum | Value | Description
70848  * :-----------------------------------|:------|:-----------------------------------
70849  * ALT_USB_DEV_DIEPCTL0_EPDIS_E_INACT | 0x0 | No action
70850  * ALT_USB_DEV_DIEPCTL0_EPDIS_E_ACT | 0x1 | Stop transmitting data on endpoint
70851  *
70852  * Field Access Macros:
70853  *
70854  */
70855 /*
70856  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPDIS
70857  *
70858  * No action
70859  */
70860 #define ALT_USB_DEV_DIEPCTL0_EPDIS_E_INACT 0x0
70861 /*
70862  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPDIS
70863  *
70864  * Stop transmitting data on endpoint
70865  */
70866 #define ALT_USB_DEV_DIEPCTL0_EPDIS_E_ACT 0x1
70867 
70868 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */
70869 #define ALT_USB_DEV_DIEPCTL0_EPDIS_LSB 30
70870 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */
70871 #define ALT_USB_DEV_DIEPCTL0_EPDIS_MSB 30
70872 /* The width in bits of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */
70873 #define ALT_USB_DEV_DIEPCTL0_EPDIS_WIDTH 1
70874 /* The mask used to set the ALT_USB_DEV_DIEPCTL0_EPDIS register field value. */
70875 #define ALT_USB_DEV_DIEPCTL0_EPDIS_SET_MSK 0x40000000
70876 /* The mask used to clear the ALT_USB_DEV_DIEPCTL0_EPDIS register field value. */
70877 #define ALT_USB_DEV_DIEPCTL0_EPDIS_CLR_MSK 0xbfffffff
70878 /* The reset value of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */
70879 #define ALT_USB_DEV_DIEPCTL0_EPDIS_RESET 0x0
70880 /* Extracts the ALT_USB_DEV_DIEPCTL0_EPDIS field value from a register. */
70881 #define ALT_USB_DEV_DIEPCTL0_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
70882 /* Produces a ALT_USB_DEV_DIEPCTL0_EPDIS register field value suitable for setting the register. */
70883 #define ALT_USB_DEV_DIEPCTL0_EPDIS_SET(value) (((value) << 30) & 0x40000000)
70884 
70885 /*
70886  * Field : epena
70887  *
70888  * Endpoint Enable (EPEna)
70889  *
70890  * When Scatter/Gather DMA mode is enabled, For IN endpoints this bit
70891  *
70892  * indicates that the descriptor structure and data buffer with data ready
70893  *
70894  * to transmit is setup.
70895  *
70896  * When Scatter/Gather DMA mode is disabled such as in buffer pointer
70897  *
70898  * based DMA mode this bit indicates that data is ready to be
70899  *
70900  * transmitted on the endpoint.
70901  *
70902  * The core clears this bit before setting the following interrupts on this
70903  *
70904  * endpoint:
70905  *
70906  * Endpoint Disabled
70907  *
70908  * Transfer Completed
70909  *
70910  * Field Enumeration Values:
70911  *
70912  * Enum | Value | Description
70913  * :-----------------------------------|:------|:-----------------
70914  * ALT_USB_DEV_DIEPCTL0_EPENA_E_INACT | 0x0 | No action
70915  * ALT_USB_DEV_DIEPCTL0_EPENA_E_ACT | 0x1 | Endpoint Enabled
70916  *
70917  * Field Access Macros:
70918  *
70919  */
70920 /*
70921  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPENA
70922  *
70923  * No action
70924  */
70925 #define ALT_USB_DEV_DIEPCTL0_EPENA_E_INACT 0x0
70926 /*
70927  * Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPENA
70928  *
70929  * Endpoint Enabled
70930  */
70931 #define ALT_USB_DEV_DIEPCTL0_EPENA_E_ACT 0x1
70932 
70933 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */
70934 #define ALT_USB_DEV_DIEPCTL0_EPENA_LSB 31
70935 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */
70936 #define ALT_USB_DEV_DIEPCTL0_EPENA_MSB 31
70937 /* The width in bits of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */
70938 #define ALT_USB_DEV_DIEPCTL0_EPENA_WIDTH 1
70939 /* The mask used to set the ALT_USB_DEV_DIEPCTL0_EPENA register field value. */
70940 #define ALT_USB_DEV_DIEPCTL0_EPENA_SET_MSK 0x80000000
70941 /* The mask used to clear the ALT_USB_DEV_DIEPCTL0_EPENA register field value. */
70942 #define ALT_USB_DEV_DIEPCTL0_EPENA_CLR_MSK 0x7fffffff
70943 /* The reset value of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */
70944 #define ALT_USB_DEV_DIEPCTL0_EPENA_RESET 0x0
70945 /* Extracts the ALT_USB_DEV_DIEPCTL0_EPENA field value from a register. */
70946 #define ALT_USB_DEV_DIEPCTL0_EPENA_GET(value) (((value) & 0x80000000) >> 31)
70947 /* Produces a ALT_USB_DEV_DIEPCTL0_EPENA register field value suitable for setting the register. */
70948 #define ALT_USB_DEV_DIEPCTL0_EPENA_SET(value) (((value) << 31) & 0x80000000)
70949 
70950 #ifndef __ASSEMBLY__
70951 /*
70952  * WARNING: The C register and register group struct declarations are provided for
70953  * convenience and illustrative purposes. They should, however, be used with
70954  * caution as the C language standard provides no guarantees about the alignment or
70955  * atomicity of device memory accesses. The recommended practice for writing
70956  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
70957  * alt_write_word() functions.
70958  *
70959  * The struct declaration for register ALT_USB_DEV_DIEPCTL0.
70960  */
70961 struct ALT_USB_DEV_DIEPCTL0_s
70962 {
70963  uint32_t mps : 2; /* ALT_USB_DEV_DIEPCTL0_MPS */
70964  uint32_t : 13; /* *UNDEFINED* */
70965  const uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL0_USBACTEP */
70966  uint32_t : 1; /* *UNDEFINED* */
70967  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL0_NAKSTS */
70968  const uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL0_EPTYPE */
70969  uint32_t : 1; /* *UNDEFINED* */
70970  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL0_STALL */
70971  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL0_TXFNUM */
70972  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL0_CNAK */
70973  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL0_SNAK */
70974  uint32_t : 2; /* *UNDEFINED* */
70975  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL0_EPDIS */
70976  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL0_EPENA */
70977 };
70978 
70979 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL0. */
70980 typedef volatile struct ALT_USB_DEV_DIEPCTL0_s ALT_USB_DEV_DIEPCTL0_t;
70981 #endif /* __ASSEMBLY__ */
70982 
70983 /* The reset value of the ALT_USB_DEV_DIEPCTL0 register. */
70984 #define ALT_USB_DEV_DIEPCTL0_RESET 0x00008000
70985 /* The byte offset of the ALT_USB_DEV_DIEPCTL0 register from the beginning of the component. */
70986 #define ALT_USB_DEV_DIEPCTL0_OFST 0x100
70987 /* The address of the ALT_USB_DEV_DIEPCTL0 register. */
70988 #define ALT_USB_DEV_DIEPCTL0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL0_OFST))
70989 
70990 /*
70991  * Register : diepint0
70992  *
70993  * Device IN Endpoint 0 Interrupt Register
70994  *
70995  * Register Layout
70996  *
70997  * Bits | Access | Reset | Description
70998  * :--------|:-------|:------|:---------------------------------
70999  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_XFERCOMPL
71000  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_EPDISBLD
71001  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_AHBERR
71002  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_TMO
71003  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_INTKNTXFEMP
71004  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_INTKNEPMIS
71005  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_INEPNAKEFF
71006  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT0_TXFEMP
71007  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN
71008  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_BNAINTR
71009  * [10] | ??? | 0x0 | *UNDEFINED*
71010  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_PKTDRPSTS
71011  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_BBLEERR
71012  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_NAKINTRPT
71013  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_NYETINTRPT
71014  * [31:15] | ??? | 0x0 | *UNDEFINED*
71015  *
71016  */
71017 /*
71018  * Field : xfercompl
71019  *
71020  * Transfer Completed Interrupt (XferCompl)
71021  *
71022  * Applies to IN and OUT endpoints.
71023  *
71024  * When Scatter/Gather DMA mode is enabled
71025  *
71026  * * For IN endpoint this field indicates that the requested data
71027  *
71028  * from the descriptor is moved from external system memory
71029  *
71030  * to internal FIFO.
71031  *
71032  * * For OUT endpoint this field indicates that the requested
71033  *
71034  * data from the internal FIFO is moved to external system
71035  *
71036  * memory. This interrupt is generated only when the
71037  *
71038  * corresponding endpoint descriptor is closed, and the IOC
71039  *
71040  * bit For the corresponding descriptor is Set.
71041  *
71042  * When Scatter/Gather DMA mode is disabled, this field
71043  *
71044  * indicates that the programmed transfer is complete on the
71045  *
71046  * AHB as well as on the USB, For this endpoint.
71047  *
71048  * Field Enumeration Values:
71049  *
71050  * Enum | Value | Description
71051  * :---------------------------------------|:------|:-----------------------------
71052  * ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_INACT | 0x0 | No Interrupt
71053  * ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
71054  *
71055  * Field Access Macros:
71056  *
71057  */
71058 /*
71059  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_XFERCOMPL
71060  *
71061  * No Interrupt
71062  */
71063 #define ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_INACT 0x0
71064 /*
71065  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_XFERCOMPL
71066  *
71067  * Transfer Completed Interrupt
71068  */
71069 #define ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_ACT 0x1
71070 
71071 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */
71072 #define ALT_USB_DEV_DIEPINT0_XFERCOMPL_LSB 0
71073 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */
71074 #define ALT_USB_DEV_DIEPINT0_XFERCOMPL_MSB 0
71075 /* The width in bits of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */
71076 #define ALT_USB_DEV_DIEPINT0_XFERCOMPL_WIDTH 1
71077 /* The mask used to set the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field value. */
71078 #define ALT_USB_DEV_DIEPINT0_XFERCOMPL_SET_MSK 0x00000001
71079 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field value. */
71080 #define ALT_USB_DEV_DIEPINT0_XFERCOMPL_CLR_MSK 0xfffffffe
71081 /* The reset value of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */
71082 #define ALT_USB_DEV_DIEPINT0_XFERCOMPL_RESET 0x0
71083 /* Extracts the ALT_USB_DEV_DIEPINT0_XFERCOMPL field value from a register. */
71084 #define ALT_USB_DEV_DIEPINT0_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
71085 /* Produces a ALT_USB_DEV_DIEPINT0_XFERCOMPL register field value suitable for setting the register. */
71086 #define ALT_USB_DEV_DIEPINT0_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
71087 
71088 /*
71089  * Field : epdisbld
71090  *
71091  * Endpoint Disabled Interrupt (EPDisbld)
71092  *
71093  * Applies to IN and OUT endpoints.
71094  *
71095  * This bit indicates that the endpoint is disabled per the
71096  *
71097  * application's request.
71098  *
71099  * Field Enumeration Values:
71100  *
71101  * Enum | Value | Description
71102  * :--------------------------------------|:------|:----------------------------
71103  * ALT_USB_DEV_DIEPINT0_EPDISBLD_E_INACT | 0x0 | No Interrupt
71104  * ALT_USB_DEV_DIEPINT0_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
71105  *
71106  * Field Access Macros:
71107  *
71108  */
71109 /*
71110  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_EPDISBLD
71111  *
71112  * No Interrupt
71113  */
71114 #define ALT_USB_DEV_DIEPINT0_EPDISBLD_E_INACT 0x0
71115 /*
71116  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_EPDISBLD
71117  *
71118  * Endpoint Disabled Interrupt
71119  */
71120 #define ALT_USB_DEV_DIEPINT0_EPDISBLD_E_ACT 0x1
71121 
71122 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */
71123 #define ALT_USB_DEV_DIEPINT0_EPDISBLD_LSB 1
71124 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */
71125 #define ALT_USB_DEV_DIEPINT0_EPDISBLD_MSB 1
71126 /* The width in bits of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */
71127 #define ALT_USB_DEV_DIEPINT0_EPDISBLD_WIDTH 1
71128 /* The mask used to set the ALT_USB_DEV_DIEPINT0_EPDISBLD register field value. */
71129 #define ALT_USB_DEV_DIEPINT0_EPDISBLD_SET_MSK 0x00000002
71130 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_EPDISBLD register field value. */
71131 #define ALT_USB_DEV_DIEPINT0_EPDISBLD_CLR_MSK 0xfffffffd
71132 /* The reset value of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */
71133 #define ALT_USB_DEV_DIEPINT0_EPDISBLD_RESET 0x0
71134 /* Extracts the ALT_USB_DEV_DIEPINT0_EPDISBLD field value from a register. */
71135 #define ALT_USB_DEV_DIEPINT0_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
71136 /* Produces a ALT_USB_DEV_DIEPINT0_EPDISBLD register field value suitable for setting the register. */
71137 #define ALT_USB_DEV_DIEPINT0_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
71138 
71139 /*
71140  * Field : ahberr
71141  *
71142  * AHB Error (AHBErr)
71143  *
71144  * Applies to IN and OUT endpoints.
71145  *
71146  * This is generated only in Internal DMA mode when there is an
71147  *
71148  * AHB error during an AHB read/write. The application can read
71149  *
71150  * the corresponding endpoint DMA address register to get the
71151  *
71152  * error address.
71153  *
71154  * Field Enumeration Values:
71155  *
71156  * Enum | Value | Description
71157  * :------------------------------------|:------|:--------------------
71158  * ALT_USB_DEV_DIEPINT0_AHBERR_E_INACT | 0x0 | No Interrupt
71159  * ALT_USB_DEV_DIEPINT0_AHBERR_E_ACT | 0x1 | AHB Error interrupt
71160  *
71161  * Field Access Macros:
71162  *
71163  */
71164 /*
71165  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_AHBERR
71166  *
71167  * No Interrupt
71168  */
71169 #define ALT_USB_DEV_DIEPINT0_AHBERR_E_INACT 0x0
71170 /*
71171  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_AHBERR
71172  *
71173  * AHB Error interrupt
71174  */
71175 #define ALT_USB_DEV_DIEPINT0_AHBERR_E_ACT 0x1
71176 
71177 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */
71178 #define ALT_USB_DEV_DIEPINT0_AHBERR_LSB 2
71179 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */
71180 #define ALT_USB_DEV_DIEPINT0_AHBERR_MSB 2
71181 /* The width in bits of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */
71182 #define ALT_USB_DEV_DIEPINT0_AHBERR_WIDTH 1
71183 /* The mask used to set the ALT_USB_DEV_DIEPINT0_AHBERR register field value. */
71184 #define ALT_USB_DEV_DIEPINT0_AHBERR_SET_MSK 0x00000004
71185 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_AHBERR register field value. */
71186 #define ALT_USB_DEV_DIEPINT0_AHBERR_CLR_MSK 0xfffffffb
71187 /* The reset value of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */
71188 #define ALT_USB_DEV_DIEPINT0_AHBERR_RESET 0x0
71189 /* Extracts the ALT_USB_DEV_DIEPINT0_AHBERR field value from a register. */
71190 #define ALT_USB_DEV_DIEPINT0_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
71191 /* Produces a ALT_USB_DEV_DIEPINT0_AHBERR register field value suitable for setting the register. */
71192 #define ALT_USB_DEV_DIEPINT0_AHBERR_SET(value) (((value) << 2) & 0x00000004)
71193 
71194 /*
71195  * Field : timeout
71196  *
71197  * Timeout Condition (TimeOUT)
71198  *
71199  * In shared TX FIFO mode, applies to non-isochronous IN
71200  *
71201  * endpoints only.
71202  *
71203  * In dedicated FIFO mode, applies only to Control IN
71204  *
71205  * endpoints.
71206  *
71207  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
71208  *
71209  * asserted.
71210  *
71211  * Indicates that the core has detected a timeout condition on the
71212  *
71213  * USB For the last IN token on this endpoint.
71214  *
71215  * Field Enumeration Values:
71216  *
71217  * Enum | Value | Description
71218  * :---------------------------------|:------|:------------------
71219  * ALT_USB_DEV_DIEPINT0_TMO_E_INACT | 0x0 | No interrupt
71220  * ALT_USB_DEV_DIEPINT0_TMO_E_ACT | 0x1 | Timeout interrupy
71221  *
71222  * Field Access Macros:
71223  *
71224  */
71225 /*
71226  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TMO
71227  *
71228  * No interrupt
71229  */
71230 #define ALT_USB_DEV_DIEPINT0_TMO_E_INACT 0x0
71231 /*
71232  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TMO
71233  *
71234  * Timeout interrupy
71235  */
71236 #define ALT_USB_DEV_DIEPINT0_TMO_E_ACT 0x1
71237 
71238 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_TMO register field. */
71239 #define ALT_USB_DEV_DIEPINT0_TMO_LSB 3
71240 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_TMO register field. */
71241 #define ALT_USB_DEV_DIEPINT0_TMO_MSB 3
71242 /* The width in bits of the ALT_USB_DEV_DIEPINT0_TMO register field. */
71243 #define ALT_USB_DEV_DIEPINT0_TMO_WIDTH 1
71244 /* The mask used to set the ALT_USB_DEV_DIEPINT0_TMO register field value. */
71245 #define ALT_USB_DEV_DIEPINT0_TMO_SET_MSK 0x00000008
71246 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_TMO register field value. */
71247 #define ALT_USB_DEV_DIEPINT0_TMO_CLR_MSK 0xfffffff7
71248 /* The reset value of the ALT_USB_DEV_DIEPINT0_TMO register field. */
71249 #define ALT_USB_DEV_DIEPINT0_TMO_RESET 0x0
71250 /* Extracts the ALT_USB_DEV_DIEPINT0_TMO field value from a register. */
71251 #define ALT_USB_DEV_DIEPINT0_TMO_GET(value) (((value) & 0x00000008) >> 3)
71252 /* Produces a ALT_USB_DEV_DIEPINT0_TMO register field value suitable for setting the register. */
71253 #define ALT_USB_DEV_DIEPINT0_TMO_SET(value) (((value) << 3) & 0x00000008)
71254 
71255 /*
71256  * Field : intkntxfemp
71257  *
71258  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
71259  *
71260  * Applies to non-periodic IN endpoints only.
71261  *
71262  * Indicates that an IN token was received when the associated
71263  *
71264  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
71265  *
71266  * asserted on the endpoint For which the IN token was received.
71267  *
71268  * Field Enumeration Values:
71269  *
71270  * Enum | Value | Description
71271  * :-----------------------------------------|:------|:----------------------------
71272  * ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
71273  * ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
71274  *
71275  * Field Access Macros:
71276  *
71277  */
71278 /*
71279  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNTXFEMP
71280  *
71281  * No interrupt
71282  */
71283 #define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_INACT 0x0
71284 /*
71285  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNTXFEMP
71286  *
71287  * IN Token Received Interrupt
71288  */
71289 #define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_ACT 0x1
71290 
71291 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */
71292 #define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_LSB 4
71293 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */
71294 #define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_MSB 4
71295 /* The width in bits of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */
71296 #define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_WIDTH 1
71297 /* The mask used to set the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field value. */
71298 #define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_SET_MSK 0x00000010
71299 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field value. */
71300 #define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_CLR_MSK 0xffffffef
71301 /* The reset value of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */
71302 #define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_RESET 0x0
71303 /* Extracts the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP field value from a register. */
71304 #define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
71305 /* Produces a ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field value suitable for setting the register. */
71306 #define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
71307 
71308 /*
71309  * Field : intknepmis
71310  *
71311  * IN Token Received with EP Mismatch (INTknEPMis)
71312  *
71313  * Applies to non-periodic IN endpoints only.
71314  *
71315  * Indicates that the data in the top of the non-periodic TxFIFO
71316  *
71317  * belongs to an endpoint other than the one For which the IN token
71318  *
71319  * was received. This interrupt is asserted on the endpoint For
71320  *
71321  * which the IN token was received.
71322  *
71323  * Field Enumeration Values:
71324  *
71325  * Enum | Value | Description
71326  * :----------------------------------------|:------|:---------------------------------------------
71327  * ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_INACT | 0x0 | No interrupt
71328  * ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
71329  *
71330  * Field Access Macros:
71331  *
71332  */
71333 /*
71334  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNEPMIS
71335  *
71336  * No interrupt
71337  */
71338 #define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_INACT 0x0
71339 /*
71340  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNEPMIS
71341  *
71342  * IN Token Received with EP Mismatch interrupt
71343  */
71344 #define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_ACT 0x1
71345 
71346 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */
71347 #define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_LSB 5
71348 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */
71349 #define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_MSB 5
71350 /* The width in bits of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */
71351 #define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_WIDTH 1
71352 /* The mask used to set the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field value. */
71353 #define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_SET_MSK 0x00000020
71354 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field value. */
71355 #define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_CLR_MSK 0xffffffdf
71356 /* The reset value of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */
71357 #define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_RESET 0x0
71358 /* Extracts the ALT_USB_DEV_DIEPINT0_INTKNEPMIS field value from a register. */
71359 #define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
71360 /* Produces a ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field value suitable for setting the register. */
71361 #define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
71362 
71363 /*
71364  * Field : inepnakeff
71365  *
71366  * IN Endpoint NAK Effective (INEPNakEff)
71367  *
71368  * Applies to periodic IN endpoints only.
71369  *
71370  * This bit can be cleared when the application clears the IN
71371  *
71372  * endpoint NAK by writing to DIEPCTLn.CNAK.
71373  *
71374  * This interrupt indicates that the core has sampled the NAK bit
71375  *
71376  * Set (either by the application or by the core). The interrupt
71377  *
71378  * indicates that the IN endpoint NAK bit Set by the application has
71379  *
71380  * taken effect in the core.
71381  *
71382  * This interrupt does not guarantee that a NAK handshake is sent
71383  *
71384  * on the USB. A STALL bit takes priority over a NAK bit.
71385  *
71386  * Field Enumeration Values:
71387  *
71388  * Enum | Value | Description
71389  * :----------------------------------------|:------|:------------------------------------
71390  * ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_INACT | 0x0 | No interrupt
71391  * ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
71392  *
71393  * Field Access Macros:
71394  *
71395  */
71396 /*
71397  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INEPNAKEFF
71398  *
71399  * No interrupt
71400  */
71401 #define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_INACT 0x0
71402 /*
71403  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_INEPNAKEFF
71404  *
71405  * IN Endpoint NAK Effective interrupt
71406  */
71407 #define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_ACT 0x1
71408 
71409 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */
71410 #define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_LSB 6
71411 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */
71412 #define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_MSB 6
71413 /* The width in bits of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */
71414 #define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_WIDTH 1
71415 /* The mask used to set the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field value. */
71416 #define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_SET_MSK 0x00000040
71417 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field value. */
71418 #define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_CLR_MSK 0xffffffbf
71419 /* The reset value of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */
71420 #define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_RESET 0x0
71421 /* Extracts the ALT_USB_DEV_DIEPINT0_INEPNAKEFF field value from a register. */
71422 #define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
71423 /* Produces a ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field value suitable for setting the register. */
71424 #define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
71425 
71426 /*
71427  * Field : txfemp
71428  *
71429  * Transmit FIFO Empty (TxFEmp)
71430  *
71431  * This bit is valid only For IN Endpoints
71432  *
71433  * This interrupt is asserted when the TxFIFO For this endpoint is
71434  *
71435  * either half or completely empty. The half or completely empty
71436  *
71437  * status is determined by the TxFIFO Empty Level bit in the Core
71438  *
71439  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
71440  *
71441  * Field Enumeration Values:
71442  *
71443  * Enum | Value | Description
71444  * :------------------------------------|:------|:------------------------------
71445  * ALT_USB_DEV_DIEPINT0_TXFEMP_E_INACT | 0x0 | No interrupt
71446  * ALT_USB_DEV_DIEPINT0_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
71447  *
71448  * Field Access Macros:
71449  *
71450  */
71451 /*
71452  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFEMP
71453  *
71454  * No interrupt
71455  */
71456 #define ALT_USB_DEV_DIEPINT0_TXFEMP_E_INACT 0x0
71457 /*
71458  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFEMP
71459  *
71460  * Transmit FIFO Empty interrupt
71461  */
71462 #define ALT_USB_DEV_DIEPINT0_TXFEMP_E_ACT 0x1
71463 
71464 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */
71465 #define ALT_USB_DEV_DIEPINT0_TXFEMP_LSB 7
71466 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */
71467 #define ALT_USB_DEV_DIEPINT0_TXFEMP_MSB 7
71468 /* The width in bits of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */
71469 #define ALT_USB_DEV_DIEPINT0_TXFEMP_WIDTH 1
71470 /* The mask used to set the ALT_USB_DEV_DIEPINT0_TXFEMP register field value. */
71471 #define ALT_USB_DEV_DIEPINT0_TXFEMP_SET_MSK 0x00000080
71472 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_TXFEMP register field value. */
71473 #define ALT_USB_DEV_DIEPINT0_TXFEMP_CLR_MSK 0xffffff7f
71474 /* The reset value of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */
71475 #define ALT_USB_DEV_DIEPINT0_TXFEMP_RESET 0x1
71476 /* Extracts the ALT_USB_DEV_DIEPINT0_TXFEMP field value from a register. */
71477 #define ALT_USB_DEV_DIEPINT0_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
71478 /* Produces a ALT_USB_DEV_DIEPINT0_TXFEMP register field value suitable for setting the register. */
71479 #define ALT_USB_DEV_DIEPINT0_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
71480 
71481 /*
71482  * Field : txfifoundrn
71483  *
71484  * Fifo Underrun (TxfifoUndrn)
71485  *
71486  * Applies to IN endpoints Only
71487  *
71488  * The core generates this interrupt when it detects a transmit FIFO
71489  *
71490  * underrun condition in threshold mode For this endpoint.
71491  *
71492  * Field Enumeration Values:
71493  *
71494  * Enum | Value | Description
71495  * :-----------------------------------------|:------|:------------------------
71496  * ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
71497  * ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
71498  *
71499  * Field Access Macros:
71500  *
71501  */
71502 /*
71503  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN
71504  *
71505  * No interrupt
71506  */
71507 #define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_INACT 0x0
71508 /*
71509  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN
71510  *
71511  * Fifo Underrun interrupt
71512  */
71513 #define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_ACT 0x1
71514 
71515 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */
71516 #define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_LSB 8
71517 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */
71518 #define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_MSB 8
71519 /* The width in bits of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */
71520 #define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_WIDTH 1
71521 /* The mask used to set the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field value. */
71522 #define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_SET_MSK 0x00000100
71523 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field value. */
71524 #define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_CLR_MSK 0xfffffeff
71525 /* The reset value of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */
71526 #define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_RESET 0x0
71527 /* Extracts the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN field value from a register. */
71528 #define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
71529 /* Produces a ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field value suitable for setting the register. */
71530 #define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
71531 
71532 /*
71533  * Field : bnaintr
71534  *
71535  * BNA (Buffer Not Available) Interrupt (BNAIntr)
71536  *
71537  * This bit is valid only when Scatter/Gather DMA mode is enabled.
71538  *
71539  * The core generates this interrupt when the descriptor accessed
71540  *
71541  * is not ready For the Core to process, such as Host busy or DMA
71542  *
71543  * done
71544  *
71545  * Field Enumeration Values:
71546  *
71547  * Enum | Value | Description
71548  * :-------------------------------------|:------|:--------------
71549  * ALT_USB_DEV_DIEPINT0_BNAINTR_E_INACT | 0x0 | No interrupt
71550  * ALT_USB_DEV_DIEPINT0_BNAINTR_E_ACT | 0x1 | BNA interrupt
71551  *
71552  * Field Access Macros:
71553  *
71554  */
71555 /*
71556  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_BNAINTR
71557  *
71558  * No interrupt
71559  */
71560 #define ALT_USB_DEV_DIEPINT0_BNAINTR_E_INACT 0x0
71561 /*
71562  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_BNAINTR
71563  *
71564  * BNA interrupt
71565  */
71566 #define ALT_USB_DEV_DIEPINT0_BNAINTR_E_ACT 0x1
71567 
71568 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */
71569 #define ALT_USB_DEV_DIEPINT0_BNAINTR_LSB 9
71570 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */
71571 #define ALT_USB_DEV_DIEPINT0_BNAINTR_MSB 9
71572 /* The width in bits of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */
71573 #define ALT_USB_DEV_DIEPINT0_BNAINTR_WIDTH 1
71574 /* The mask used to set the ALT_USB_DEV_DIEPINT0_BNAINTR register field value. */
71575 #define ALT_USB_DEV_DIEPINT0_BNAINTR_SET_MSK 0x00000200
71576 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_BNAINTR register field value. */
71577 #define ALT_USB_DEV_DIEPINT0_BNAINTR_CLR_MSK 0xfffffdff
71578 /* The reset value of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */
71579 #define ALT_USB_DEV_DIEPINT0_BNAINTR_RESET 0x0
71580 /* Extracts the ALT_USB_DEV_DIEPINT0_BNAINTR field value from a register. */
71581 #define ALT_USB_DEV_DIEPINT0_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
71582 /* Produces a ALT_USB_DEV_DIEPINT0_BNAINTR register field value suitable for setting the register. */
71583 #define ALT_USB_DEV_DIEPINT0_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
71584 
71585 /*
71586  * Field : pktdrpsts
71587  *
71588  * Packet Drop Status (PktDrpSts)
71589  *
71590  * This bit indicates to the application that an ISOC OUT packet has been dropped.
71591  * This
71592  *
71593  * bit does not have an associated mask bit and does not generate an interrupt.
71594  *
71595  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
71596  * transfer
71597  *
71598  * interrupt feature is selected.
71599  *
71600  * Field Enumeration Values:
71601  *
71602  * Enum | Value | Description
71603  * :---------------------------------------|:------|:-----------------------------
71604  * ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_INACT | 0x0 | No interrupt
71605  * ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
71606  *
71607  * Field Access Macros:
71608  *
71609  */
71610 /*
71611  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_PKTDRPSTS
71612  *
71613  * No interrupt
71614  */
71615 #define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_INACT 0x0
71616 /*
71617  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_PKTDRPSTS
71618  *
71619  * Packet Drop Status interrupt
71620  */
71621 #define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_ACT 0x1
71622 
71623 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */
71624 #define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_LSB 11
71625 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */
71626 #define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_MSB 11
71627 /* The width in bits of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */
71628 #define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_WIDTH 1
71629 /* The mask used to set the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field value. */
71630 #define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_SET_MSK 0x00000800
71631 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field value. */
71632 #define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_CLR_MSK 0xfffff7ff
71633 /* The reset value of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */
71634 #define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_RESET 0x0
71635 /* Extracts the ALT_USB_DEV_DIEPINT0_PKTDRPSTS field value from a register. */
71636 #define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
71637 /* Produces a ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field value suitable for setting the register. */
71638 #define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
71639 
71640 /*
71641  * Field : bbleerr
71642  *
71643  * NAK Interrupt (BbleErr)
71644  *
71645  * The core generates this interrupt when babble is received for the endpoint.
71646  *
71647  * Field Enumeration Values:
71648  *
71649  * Enum | Value | Description
71650  * :-------------------------------------|:------|:------------------
71651  * ALT_USB_DEV_DIEPINT0_BBLEERR_E_INACT | 0x0 | No interrupt
71652  * ALT_USB_DEV_DIEPINT0_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
71653  *
71654  * Field Access Macros:
71655  *
71656  */
71657 /*
71658  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_BBLEERR
71659  *
71660  * No interrupt
71661  */
71662 #define ALT_USB_DEV_DIEPINT0_BBLEERR_E_INACT 0x0
71663 /*
71664  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_BBLEERR
71665  *
71666  * BbleErr interrupt
71667  */
71668 #define ALT_USB_DEV_DIEPINT0_BBLEERR_E_ACT 0x1
71669 
71670 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */
71671 #define ALT_USB_DEV_DIEPINT0_BBLEERR_LSB 12
71672 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */
71673 #define ALT_USB_DEV_DIEPINT0_BBLEERR_MSB 12
71674 /* The width in bits of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */
71675 #define ALT_USB_DEV_DIEPINT0_BBLEERR_WIDTH 1
71676 /* The mask used to set the ALT_USB_DEV_DIEPINT0_BBLEERR register field value. */
71677 #define ALT_USB_DEV_DIEPINT0_BBLEERR_SET_MSK 0x00001000
71678 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_BBLEERR register field value. */
71679 #define ALT_USB_DEV_DIEPINT0_BBLEERR_CLR_MSK 0xffffefff
71680 /* The reset value of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */
71681 #define ALT_USB_DEV_DIEPINT0_BBLEERR_RESET 0x0
71682 /* Extracts the ALT_USB_DEV_DIEPINT0_BBLEERR field value from a register. */
71683 #define ALT_USB_DEV_DIEPINT0_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
71684 /* Produces a ALT_USB_DEV_DIEPINT0_BBLEERR register field value suitable for setting the register. */
71685 #define ALT_USB_DEV_DIEPINT0_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
71686 
71687 /*
71688  * Field : nakintrpt
71689  *
71690  * NAK Interrupt (NAKInterrupt)
71691  *
71692  * The core generates this interrupt when a NAK is transmitted or received by the
71693  * device.
71694  *
71695  * In case of isochronous IN endpoints the interrupt gets generated when a zero
71696  * length
71697  *
71698  * packet is transmitted due to un-availability of data in the TXFifo.
71699  *
71700  * Field Enumeration Values:
71701  *
71702  * Enum | Value | Description
71703  * :---------------------------------------|:------|:--------------
71704  * ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_INACT | 0x0 | No interrupt
71705  * ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
71706  *
71707  * Field Access Macros:
71708  *
71709  */
71710 /*
71711  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_NAKINTRPT
71712  *
71713  * No interrupt
71714  */
71715 #define ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_INACT 0x0
71716 /*
71717  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_NAKINTRPT
71718  *
71719  * NAK Interrupt
71720  */
71721 #define ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_ACT 0x1
71722 
71723 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */
71724 #define ALT_USB_DEV_DIEPINT0_NAKINTRPT_LSB 13
71725 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */
71726 #define ALT_USB_DEV_DIEPINT0_NAKINTRPT_MSB 13
71727 /* The width in bits of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */
71728 #define ALT_USB_DEV_DIEPINT0_NAKINTRPT_WIDTH 1
71729 /* The mask used to set the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field value. */
71730 #define ALT_USB_DEV_DIEPINT0_NAKINTRPT_SET_MSK 0x00002000
71731 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field value. */
71732 #define ALT_USB_DEV_DIEPINT0_NAKINTRPT_CLR_MSK 0xffffdfff
71733 /* The reset value of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */
71734 #define ALT_USB_DEV_DIEPINT0_NAKINTRPT_RESET 0x0
71735 /* Extracts the ALT_USB_DEV_DIEPINT0_NAKINTRPT field value from a register. */
71736 #define ALT_USB_DEV_DIEPINT0_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
71737 /* Produces a ALT_USB_DEV_DIEPINT0_NAKINTRPT register field value suitable for setting the register. */
71738 #define ALT_USB_DEV_DIEPINT0_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
71739 
71740 /*
71741  * Field : nyetintrpt
71742  *
71743  * NYET Interrupt (NYETIntrpt)
71744  *
71745  * The core generates this interrupt when a NYET response is transmitted for a non
71746  * isochronous OUT endpoint.
71747  *
71748  * Field Enumeration Values:
71749  *
71750  * Enum | Value | Description
71751  * :----------------------------------------|:------|:---------------
71752  * ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_INACT | 0x0 | No interrupt
71753  * ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
71754  *
71755  * Field Access Macros:
71756  *
71757  */
71758 /*
71759  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_NYETINTRPT
71760  *
71761  * No interrupt
71762  */
71763 #define ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_INACT 0x0
71764 /*
71765  * Enumerated value for register field ALT_USB_DEV_DIEPINT0_NYETINTRPT
71766  *
71767  * NYET Interrupt
71768  */
71769 #define ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_ACT 0x1
71770 
71771 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */
71772 #define ALT_USB_DEV_DIEPINT0_NYETINTRPT_LSB 14
71773 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */
71774 #define ALT_USB_DEV_DIEPINT0_NYETINTRPT_MSB 14
71775 /* The width in bits of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */
71776 #define ALT_USB_DEV_DIEPINT0_NYETINTRPT_WIDTH 1
71777 /* The mask used to set the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field value. */
71778 #define ALT_USB_DEV_DIEPINT0_NYETINTRPT_SET_MSK 0x00004000
71779 /* The mask used to clear the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field value. */
71780 #define ALT_USB_DEV_DIEPINT0_NYETINTRPT_CLR_MSK 0xffffbfff
71781 /* The reset value of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */
71782 #define ALT_USB_DEV_DIEPINT0_NYETINTRPT_RESET 0x0
71783 /* Extracts the ALT_USB_DEV_DIEPINT0_NYETINTRPT field value from a register. */
71784 #define ALT_USB_DEV_DIEPINT0_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
71785 /* Produces a ALT_USB_DEV_DIEPINT0_NYETINTRPT register field value suitable for setting the register. */
71786 #define ALT_USB_DEV_DIEPINT0_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
71787 
71788 #ifndef __ASSEMBLY__
71789 /*
71790  * WARNING: The C register and register group struct declarations are provided for
71791  * convenience and illustrative purposes. They should, however, be used with
71792  * caution as the C language standard provides no guarantees about the alignment or
71793  * atomicity of device memory accesses. The recommended practice for writing
71794  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
71795  * alt_write_word() functions.
71796  *
71797  * The struct declaration for register ALT_USB_DEV_DIEPINT0.
71798  */
71799 struct ALT_USB_DEV_DIEPINT0_s
71800 {
71801  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT0_XFERCOMPL */
71802  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT0_EPDISBLD */
71803  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT0_AHBERR */
71804  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT0_TMO */
71805  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT0_INTKNTXFEMP */
71806  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT0_INTKNEPMIS */
71807  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT0_INEPNAKEFF */
71808  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT0_TXFEMP */
71809  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN */
71810  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT0_BNAINTR */
71811  uint32_t : 1; /* *UNDEFINED* */
71812  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT0_PKTDRPSTS */
71813  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT0_BBLEERR */
71814  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT0_NAKINTRPT */
71815  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT0_NYETINTRPT */
71816  uint32_t : 17; /* *UNDEFINED* */
71817 };
71818 
71819 /* The typedef declaration for register ALT_USB_DEV_DIEPINT0. */
71820 typedef volatile struct ALT_USB_DEV_DIEPINT0_s ALT_USB_DEV_DIEPINT0_t;
71821 #endif /* __ASSEMBLY__ */
71822 
71823 /* The reset value of the ALT_USB_DEV_DIEPINT0 register. */
71824 #define ALT_USB_DEV_DIEPINT0_RESET 0x00000080
71825 /* The byte offset of the ALT_USB_DEV_DIEPINT0 register from the beginning of the component. */
71826 #define ALT_USB_DEV_DIEPINT0_OFST 0x108
71827 /* The address of the ALT_USB_DEV_DIEPINT0 register. */
71828 #define ALT_USB_DEV_DIEPINT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT0_OFST))
71829 
71830 /*
71831  * Register : dieptsiz0
71832  *
71833  * Device IN Endpoint 0 Transfer Size Register
71834  *
71835  * Register Layout
71836  *
71837  * Bits | Access | Reset | Description
71838  * :--------|:-------|:------|:-------------------------------
71839  * [6:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ0_XFERSIZE
71840  * [18:7] | ??? | 0x0 | *UNDEFINED*
71841  * [20:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ0_PKTCNT
71842  * [31:21] | ??? | 0x0 | *UNDEFINED*
71843  *
71844  */
71845 /*
71846  * Field : xfersize
71847  *
71848  * Transfer Size (XferSize)
71849  *
71850  * This field contains the transfer size in bytes for the current endpoint. The
71851  * transfer size
71852  *
71853  * (XferSize) = Sum of buffer sizes across all descriptors in the list for the
71854  * endpoint.
71855  *
71856  * In Buffer DMA, the core only interrupts the application after it has exhausted
71857  * the transfer
71858  *
71859  * size amount of data. The transfer size can be set to the maximum packet size of
71860  * the
71861  *
71862  * endpoint, to be interrupted at the end of each packet.
71863  *
71864  * IN Endpoints: The core decrements this field every time a packet from the
71865  * external
71866  *
71867  * memory is written to the TxFIFO.
71868  *
71869  * OUT Endpoints: The core decrements this field every time a packet is read from
71870  * the
71871  *
71872  * RxFIFO and written to the external memory.
71873  *
71874  * Field Access Macros:
71875  *
71876  */
71877 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */
71878 #define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_LSB 0
71879 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */
71880 #define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_MSB 6
71881 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */
71882 #define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_WIDTH 7
71883 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field value. */
71884 #define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_SET_MSK 0x0000007f
71885 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field value. */
71886 #define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_CLR_MSK 0xffffff80
71887 /* The reset value of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */
71888 #define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_RESET 0x0
71889 /* Extracts the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE field value from a register. */
71890 #define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_GET(value) (((value) & 0x0000007f) >> 0)
71891 /* Produces a ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field value suitable for setting the register. */
71892 #define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_SET(value) (((value) << 0) & 0x0000007f)
71893 
71894 /*
71895  * Field : pktcnt
71896  *
71897  * Packet Count (PktCnt)
71898  *
71899  * Indicates the total number of USB packets that constitute the
71900  *
71901  * Transfer Size amount of data For endpoint 0.
71902  *
71903  * In Endpoints : This field is decremented every time a packet (maximum size or
71904  *
71905  * short packet) is read from the TxFIFO.
71906  *
71907  * OUT Endpoints: This field is decremented every time a packet (maximum size or
71908  *
71909  * short packet) is written to the RxFIFO.
71910  *
71911  * Field Access Macros:
71912  *
71913  */
71914 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */
71915 #define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_LSB 19
71916 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */
71917 #define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_MSB 20
71918 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */
71919 #define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_WIDTH 2
71920 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field value. */
71921 #define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_SET_MSK 0x00180000
71922 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field value. */
71923 #define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_CLR_MSK 0xffe7ffff
71924 /* The reset value of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */
71925 #define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_RESET 0x0
71926 /* Extracts the ALT_USB_DEV_DIEPTSIZ0_PKTCNT field value from a register. */
71927 #define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_GET(value) (((value) & 0x00180000) >> 19)
71928 /* Produces a ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field value suitable for setting the register. */
71929 #define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_SET(value) (((value) << 19) & 0x00180000)
71930 
71931 #ifndef __ASSEMBLY__
71932 /*
71933  * WARNING: The C register and register group struct declarations are provided for
71934  * convenience and illustrative purposes. They should, however, be used with
71935  * caution as the C language standard provides no guarantees about the alignment or
71936  * atomicity of device memory accesses. The recommended practice for writing
71937  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
71938  * alt_write_word() functions.
71939  *
71940  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ0.
71941  */
71942 struct ALT_USB_DEV_DIEPTSIZ0_s
71943 {
71944  uint32_t xfersize : 7; /* ALT_USB_DEV_DIEPTSIZ0_XFERSIZE */
71945  uint32_t : 12; /* *UNDEFINED* */
71946  uint32_t pktcnt : 2; /* ALT_USB_DEV_DIEPTSIZ0_PKTCNT */
71947  uint32_t : 11; /* *UNDEFINED* */
71948 };
71949 
71950 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ0. */
71951 typedef volatile struct ALT_USB_DEV_DIEPTSIZ0_s ALT_USB_DEV_DIEPTSIZ0_t;
71952 #endif /* __ASSEMBLY__ */
71953 
71954 /* The reset value of the ALT_USB_DEV_DIEPTSIZ0 register. */
71955 #define ALT_USB_DEV_DIEPTSIZ0_RESET 0x00000000
71956 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ0 register from the beginning of the component. */
71957 #define ALT_USB_DEV_DIEPTSIZ0_OFST 0x110
71958 /* The address of the ALT_USB_DEV_DIEPTSIZ0 register. */
71959 #define ALT_USB_DEV_DIEPTSIZ0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ0_OFST))
71960 
71961 /*
71962  * Register : diepdma0
71963  *
71964  * Device IN Endpoint 0 DMA Address Register
71965  *
71966  * Register Layout
71967  *
71968  * Bits | Access | Reset | Description
71969  * :-------|:-------|:--------|:------------------------------
71970  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA0_DIEPDMA0
71971  *
71972  */
71973 /*
71974  * Field : diepdma0
71975  *
71976  * Holds the start address of the external memory for storing or fetching endpoint
71977  *
71978  * data.
71979  *
71980  * Note: For control endpoints, this field stores control OUT data packets as well
71981  * as
71982  *
71983  * SETUP transaction data packets. When more than three SETUP packets are
71984  *
71985  * received back-to-back, the SETUP data packet in the memory is overwritten.
71986  *
71987  * This register is incremented on every AHB transaction. The application can give
71988  *
71989  * only a DWORD-aligned address.
71990  *
71991  * When Scatter/Gather DMA mode is not enabled, the application programs the
71992  *
71993  * start address value in this field.
71994  *
71995  * When Scatter/Gather DMA mode is enabled, this field indicates the base
71996  *
71997  * pointer for the descriptor list.
71998  *
71999  * Field Access Macros:
72000  *
72001  */
72002 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field. */
72003 #define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_LSB 0
72004 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field. */
72005 #define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_MSB 31
72006 /* The width in bits of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field. */
72007 #define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_WIDTH 32
72008 /* The mask used to set the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field value. */
72009 #define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_SET_MSK 0xffffffff
72010 /* The mask used to clear the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field value. */
72011 #define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_CLR_MSK 0x00000000
72012 /* The reset value of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field is UNKNOWN. */
72013 #define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_RESET 0x0
72014 /* Extracts the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 field value from a register. */
72015 #define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_GET(value) (((value) & 0xffffffff) >> 0)
72016 /* Produces a ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field value suitable for setting the register. */
72017 #define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_SET(value) (((value) << 0) & 0xffffffff)
72018 
72019 #ifndef __ASSEMBLY__
72020 /*
72021  * WARNING: The C register and register group struct declarations are provided for
72022  * convenience and illustrative purposes. They should, however, be used with
72023  * caution as the C language standard provides no guarantees about the alignment or
72024  * atomicity of device memory accesses. The recommended practice for writing
72025  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
72026  * alt_write_word() functions.
72027  *
72028  * The struct declaration for register ALT_USB_DEV_DIEPDMA0.
72029  */
72030 struct ALT_USB_DEV_DIEPDMA0_s
72031 {
72032  uint32_t diepdma0 : 32; /* ALT_USB_DEV_DIEPDMA0_DIEPDMA0 */
72033 };
72034 
72035 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA0. */
72036 typedef volatile struct ALT_USB_DEV_DIEPDMA0_s ALT_USB_DEV_DIEPDMA0_t;
72037 #endif /* __ASSEMBLY__ */
72038 
72039 /* The reset value of the ALT_USB_DEV_DIEPDMA0 register. */
72040 #define ALT_USB_DEV_DIEPDMA0_RESET 0x00000000
72041 /* The byte offset of the ALT_USB_DEV_DIEPDMA0 register from the beginning of the component. */
72042 #define ALT_USB_DEV_DIEPDMA0_OFST 0x114
72043 /* The address of the ALT_USB_DEV_DIEPDMA0 register. */
72044 #define ALT_USB_DEV_DIEPDMA0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA0_OFST))
72045 
72046 /*
72047  * Register : dtxfsts0
72048  *
72049  * Device IN Endpoint Transmit FIFO Status Register 0
72050  *
72051  * Register Layout
72052  *
72053  * Bits | Access | Reset | Description
72054  * :--------|:-------|:-------|:-------------------------------------
72055  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL
72056  * [31:16] | ??? | 0x0 | *UNDEFINED*
72057  *
72058  */
72059 /*
72060  * Field : ineptxfspcavail
72061  *
72062  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
72063  *
72064  * Indicates the amount of free space available in the Endpoint
72065  *
72066  * TxFIFO.
72067  *
72068  * Values are in terms of 32-bit words.
72069  *
72070  * 16'h0: Endpoint TxFIFO is full
72071  *
72072  * 16'h1: 1 word available
72073  *
72074  * 16'h2: 2 words available
72075  *
72076  * 16'hn: n words available (where 0 n 32,768)
72077  *
72078  * 16'h8000: 32,768 words available
72079  *
72080  * Others: Reserved
72081  *
72082  * Field Access Macros:
72083  *
72084  */
72085 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */
72086 #define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_LSB 0
72087 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */
72088 #define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_MSB 15
72089 /* The width in bits of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */
72090 #define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_WIDTH 16
72091 /* The mask used to set the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field value. */
72092 #define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
72093 /* The mask used to clear the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field value. */
72094 #define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
72095 /* The reset value of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */
72096 #define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_RESET 0x2000
72097 /* Extracts the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL field value from a register. */
72098 #define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
72099 /* Produces a ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field value suitable for setting the register. */
72100 #define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
72101 
72102 #ifndef __ASSEMBLY__
72103 /*
72104  * WARNING: The C register and register group struct declarations are provided for
72105  * convenience and illustrative purposes. They should, however, be used with
72106  * caution as the C language standard provides no guarantees about the alignment or
72107  * atomicity of device memory accesses. The recommended practice for writing
72108  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
72109  * alt_write_word() functions.
72110  *
72111  * The struct declaration for register ALT_USB_DEV_DTXFSTS0.
72112  */
72113 struct ALT_USB_DEV_DTXFSTS0_s
72114 {
72115  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL */
72116  uint32_t : 16; /* *UNDEFINED* */
72117 };
72118 
72119 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS0. */
72120 typedef volatile struct ALT_USB_DEV_DTXFSTS0_s ALT_USB_DEV_DTXFSTS0_t;
72121 #endif /* __ASSEMBLY__ */
72122 
72123 /* The reset value of the ALT_USB_DEV_DTXFSTS0 register. */
72124 #define ALT_USB_DEV_DTXFSTS0_RESET 0x00002000
72125 /* The byte offset of the ALT_USB_DEV_DTXFSTS0 register from the beginning of the component. */
72126 #define ALT_USB_DEV_DTXFSTS0_OFST 0x118
72127 /* The address of the ALT_USB_DEV_DTXFSTS0 register. */
72128 #define ALT_USB_DEV_DTXFSTS0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS0_OFST))
72129 
72130 /*
72131  * Register : diepdmab0
72132  *
72133  * Device IN Endpoint 16 Buffer Address Register
72134  *
72135  * Register Layout
72136  *
72137  * Bits | Access | Reset | Description
72138  * :-------|:-------|:--------|:--------------------------------
72139  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0
72140  *
72141  */
72142 /*
72143  * Field : diepdmab0
72144  *
72145  * Holds the current buffer address.This register is updated as and when the data
72146  *
72147  * transfer for the corresponding end point is in progress.
72148  *
72149  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
72150  * is
72151  *
72152  * reserved.
72153  *
72154  * Field Access Macros:
72155  *
72156  */
72157 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field. */
72158 #define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_LSB 0
72159 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field. */
72160 #define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_MSB 31
72161 /* The width in bits of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field. */
72162 #define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_WIDTH 32
72163 /* The mask used to set the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field value. */
72164 #define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_SET_MSK 0xffffffff
72165 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field value. */
72166 #define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_CLR_MSK 0x00000000
72167 /* The reset value of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field is UNKNOWN. */
72168 #define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_RESET 0x0
72169 /* Extracts the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 field value from a register. */
72170 #define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_GET(value) (((value) & 0xffffffff) >> 0)
72171 /* Produces a ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field value suitable for setting the register. */
72172 #define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_SET(value) (((value) << 0) & 0xffffffff)
72173 
72174 #ifndef __ASSEMBLY__
72175 /*
72176  * WARNING: The C register and register group struct declarations are provided for
72177  * convenience and illustrative purposes. They should, however, be used with
72178  * caution as the C language standard provides no guarantees about the alignment or
72179  * atomicity of device memory accesses. The recommended practice for writing
72180  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
72181  * alt_write_word() functions.
72182  *
72183  * The struct declaration for register ALT_USB_DEV_DIEPDMAB0.
72184  */
72185 struct ALT_USB_DEV_DIEPDMAB0_s
72186 {
72187  const uint32_t diepdmab0 : 32; /* ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 */
72188 };
72189 
72190 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB0. */
72191 typedef volatile struct ALT_USB_DEV_DIEPDMAB0_s ALT_USB_DEV_DIEPDMAB0_t;
72192 #endif /* __ASSEMBLY__ */
72193 
72194 /* The reset value of the ALT_USB_DEV_DIEPDMAB0 register. */
72195 #define ALT_USB_DEV_DIEPDMAB0_RESET 0x00000000
72196 /* The byte offset of the ALT_USB_DEV_DIEPDMAB0 register from the beginning of the component. */
72197 #define ALT_USB_DEV_DIEPDMAB0_OFST 0x11c
72198 /* The address of the ALT_USB_DEV_DIEPDMAB0 register. */
72199 #define ALT_USB_DEV_DIEPDMAB0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB0_OFST))
72200 
72201 /*
72202  * Register : diepctl1
72203  *
72204  * Device Control IN Endpoint 1 Control Register
72205  *
72206  * Register Layout
72207  *
72208  * Bits | Access | Reset | Description
72209  * :--------|:---------|:------|:------------------------------
72210  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL1_MPS
72211  * [14:11] | ??? | 0x0 | *UNDEFINED*
72212  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL1_USBACTEP
72213  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL1_DPID
72214  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL1_NAKSTS
72215  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL1_EPTYPE
72216  * [20] | ??? | 0x0 | *UNDEFINED*
72217  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL1_STALL
72218  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL1_TXFNUM
72219  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL1_CNAK
72220  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL1_SNAK
72221  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL1_SETD0PID
72222  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL1_SETD1PID
72223  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL1_EPDIS
72224  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL1_EPENA
72225  *
72226  */
72227 /*
72228  * Field : mps
72229  *
72230  * Maximum Packet Size (MPS)
72231  *
72232  * The application must program this field with the maximum packet size for the
72233  * current
72234  *
72235  * logical endpoint. This value is in bytes.
72236  *
72237  * Field Access Macros:
72238  *
72239  */
72240 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_MPS register field. */
72241 #define ALT_USB_DEV_DIEPCTL1_MPS_LSB 0
72242 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_MPS register field. */
72243 #define ALT_USB_DEV_DIEPCTL1_MPS_MSB 10
72244 /* The width in bits of the ALT_USB_DEV_DIEPCTL1_MPS register field. */
72245 #define ALT_USB_DEV_DIEPCTL1_MPS_WIDTH 11
72246 /* The mask used to set the ALT_USB_DEV_DIEPCTL1_MPS register field value. */
72247 #define ALT_USB_DEV_DIEPCTL1_MPS_SET_MSK 0x000007ff
72248 /* The mask used to clear the ALT_USB_DEV_DIEPCTL1_MPS register field value. */
72249 #define ALT_USB_DEV_DIEPCTL1_MPS_CLR_MSK 0xfffff800
72250 /* The reset value of the ALT_USB_DEV_DIEPCTL1_MPS register field. */
72251 #define ALT_USB_DEV_DIEPCTL1_MPS_RESET 0x0
72252 /* Extracts the ALT_USB_DEV_DIEPCTL1_MPS field value from a register. */
72253 #define ALT_USB_DEV_DIEPCTL1_MPS_GET(value) (((value) & 0x000007ff) >> 0)
72254 /* Produces a ALT_USB_DEV_DIEPCTL1_MPS register field value suitable for setting the register. */
72255 #define ALT_USB_DEV_DIEPCTL1_MPS_SET(value) (((value) << 0) & 0x000007ff)
72256 
72257 /*
72258  * Field : usbactep
72259  *
72260  * USB Active Endpoint (USBActEP)
72261  *
72262  * Indicates whether this endpoint is active in the current configuration and
72263  * interface. The
72264  *
72265  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
72266  * reset. After
72267  *
72268  * receiving the SetConfiguration and SetInterface commands, the application must
72269  *
72270  * program endpoint registers accordingly and set this bit.
72271  *
72272  * Field Enumeration Values:
72273  *
72274  * Enum | Value | Description
72275  * :-------------------------------------|:------|:--------------------
72276  * ALT_USB_DEV_DIEPCTL1_USBACTEP_E_DISD | 0x0 | Not Active
72277  * ALT_USB_DEV_DIEPCTL1_USBACTEP_E_END | 0x1 | USB Active Endpoint
72278  *
72279  * Field Access Macros:
72280  *
72281  */
72282 /*
72283  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_USBACTEP
72284  *
72285  * Not Active
72286  */
72287 #define ALT_USB_DEV_DIEPCTL1_USBACTEP_E_DISD 0x0
72288 /*
72289  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_USBACTEP
72290  *
72291  * USB Active Endpoint
72292  */
72293 #define ALT_USB_DEV_DIEPCTL1_USBACTEP_E_END 0x1
72294 
72295 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */
72296 #define ALT_USB_DEV_DIEPCTL1_USBACTEP_LSB 15
72297 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */
72298 #define ALT_USB_DEV_DIEPCTL1_USBACTEP_MSB 15
72299 /* The width in bits of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */
72300 #define ALT_USB_DEV_DIEPCTL1_USBACTEP_WIDTH 1
72301 /* The mask used to set the ALT_USB_DEV_DIEPCTL1_USBACTEP register field value. */
72302 #define ALT_USB_DEV_DIEPCTL1_USBACTEP_SET_MSK 0x00008000
72303 /* The mask used to clear the ALT_USB_DEV_DIEPCTL1_USBACTEP register field value. */
72304 #define ALT_USB_DEV_DIEPCTL1_USBACTEP_CLR_MSK 0xffff7fff
72305 /* The reset value of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */
72306 #define ALT_USB_DEV_DIEPCTL1_USBACTEP_RESET 0x0
72307 /* Extracts the ALT_USB_DEV_DIEPCTL1_USBACTEP field value from a register. */
72308 #define ALT_USB_DEV_DIEPCTL1_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
72309 /* Produces a ALT_USB_DEV_DIEPCTL1_USBACTEP register field value suitable for setting the register. */
72310 #define ALT_USB_DEV_DIEPCTL1_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
72311 
72312 /*
72313  * Field : dpid
72314  *
72315  * Endpoint Data PID (DPID)
72316  *
72317  * Applies to interrupt/bulk IN and OUT endpoints only.
72318  *
72319  * Contains the PID of the packet to be received or transmitted on this endpoint.
72320  * The
72321  *
72322  * application must program the PID of the first packet to be received or
72323  * transmitted on
72324  *
72325  * this endpoint, after the endpoint is activated. The applications use the
72326  * SetD1PID and
72327  *
72328  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
72329  *
72330  * 1'b0: DATA0
72331  *
72332  * 1'b1: DATA1
72333  *
72334  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
72335  *
72336  * DMA mode.
72337  *
72338  * 1'b0 RO
72339  *
72340  * Even/Odd (Micro)Frame (EO_FrNum)
72341  *
72342  * In non-Scatter/Gather DMA mode:
72343  *
72344  * Applies to isochronous IN and OUT endpoints only.
72345  *
72346  * Indicates the (micro)frame number in which the core transmits/receives
72347  * isochronous
72348  *
72349  * data for this endpoint. The application must program the even/odd (micro) frame
72350  *
72351  * number in which it intends to transmit/receive isochronous data for this
72352  * endpoint using
72353  *
72354  * the SetEvnFr and SetOddFr fields in this register.
72355  *
72356  * 1'b0: Even (micro)frame
72357  *
72358  * 1'b1: Odd (micro)frame
72359  *
72360  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
72361  * number
72362  *
72363  * in which to send data is provided in the transmit descriptor structure. The
72364  * frame in
72365  *
72366  * which data is received is updated in receive descriptor structure.
72367  *
72368  * Field Enumeration Values:
72369  *
72370  * Enum | Value | Description
72371  * :----------------------------------|:------|:-----------------------------
72372  * ALT_USB_DEV_DIEPCTL1_DPID_E_INACT | 0x0 | Endpoint Data PID not active
72373  * ALT_USB_DEV_DIEPCTL1_DPID_E_ACT | 0x1 | Endpoint Data PID active
72374  *
72375  * Field Access Macros:
72376  *
72377  */
72378 /*
72379  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_DPID
72380  *
72381  * Endpoint Data PID not active
72382  */
72383 #define ALT_USB_DEV_DIEPCTL1_DPID_E_INACT 0x0
72384 /*
72385  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_DPID
72386  *
72387  * Endpoint Data PID active
72388  */
72389 #define ALT_USB_DEV_DIEPCTL1_DPID_E_ACT 0x1
72390 
72391 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_DPID register field. */
72392 #define ALT_USB_DEV_DIEPCTL1_DPID_LSB 16
72393 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_DPID register field. */
72394 #define ALT_USB_DEV_DIEPCTL1_DPID_MSB 16
72395 /* The width in bits of the ALT_USB_DEV_DIEPCTL1_DPID register field. */
72396 #define ALT_USB_DEV_DIEPCTL1_DPID_WIDTH 1
72397 /* The mask used to set the ALT_USB_DEV_DIEPCTL1_DPID register field value. */
72398 #define ALT_USB_DEV_DIEPCTL1_DPID_SET_MSK 0x00010000
72399 /* The mask used to clear the ALT_USB_DEV_DIEPCTL1_DPID register field value. */
72400 #define ALT_USB_DEV_DIEPCTL1_DPID_CLR_MSK 0xfffeffff
72401 /* The reset value of the ALT_USB_DEV_DIEPCTL1_DPID register field. */
72402 #define ALT_USB_DEV_DIEPCTL1_DPID_RESET 0x0
72403 /* Extracts the ALT_USB_DEV_DIEPCTL1_DPID field value from a register. */
72404 #define ALT_USB_DEV_DIEPCTL1_DPID_GET(value) (((value) & 0x00010000) >> 16)
72405 /* Produces a ALT_USB_DEV_DIEPCTL1_DPID register field value suitable for setting the register. */
72406 #define ALT_USB_DEV_DIEPCTL1_DPID_SET(value) (((value) << 16) & 0x00010000)
72407 
72408 /*
72409  * Field : naksts
72410  *
72411  * NAK Status (NAKSts)
72412  *
72413  * Indicates the following:
72414  *
72415  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
72416  *
72417  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
72418  *
72419  * When either the application or the core sets this bit:
72420  *
72421  * The core stops receiving any data on an OUT endpoint, even if there is space in
72422  *
72423  * the RxFIFO to accommodate the incoming packet.
72424  *
72425  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
72426  *
72427  * endpoint, even if there data is available in the TxFIFO.
72428  *
72429  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
72430  *
72431  * if there data is available in the TxFIFO.
72432  *
72433  * Irrespective of this bit's setting, the core always responds to SETUP data
72434  * packets with
72435  *
72436  * an ACK handshake.
72437  *
72438  * Field Enumeration Values:
72439  *
72440  * Enum | Value | Description
72441  * :-------------------------------------|:------|:------------------------------------------------
72442  * ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
72443  * : | | based on the FIFO status
72444  * ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
72445  * : | | endpoint
72446  *
72447  * Field Access Macros:
72448  *
72449  */
72450 /*
72451  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_NAKSTS
72452  *
72453  * The core is transmitting non-NAK handshakes based on the FIFO status
72454  */
72455 #define ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NONNAK 0x0
72456 /*
72457  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_NAKSTS
72458  *
72459  * The core is transmitting NAK handshakes on this endpoint
72460  */
72461 #define ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NAK 0x1
72462 
72463 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */
72464 #define ALT_USB_DEV_DIEPCTL1_NAKSTS_LSB 17
72465 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */
72466 #define ALT_USB_DEV_DIEPCTL1_NAKSTS_MSB 17
72467 /* The width in bits of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */
72468 #define ALT_USB_DEV_DIEPCTL1_NAKSTS_WIDTH 1
72469 /* The mask used to set the ALT_USB_DEV_DIEPCTL1_NAKSTS register field value. */
72470 #define ALT_USB_DEV_DIEPCTL1_NAKSTS_SET_MSK 0x00020000
72471 /* The mask used to clear the ALT_USB_DEV_DIEPCTL1_NAKSTS register field value. */
72472 #define ALT_USB_DEV_DIEPCTL1_NAKSTS_CLR_MSK 0xfffdffff
72473 /* The reset value of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */
72474 #define ALT_USB_DEV_DIEPCTL1_NAKSTS_RESET 0x0
72475 /* Extracts the ALT_USB_DEV_DIEPCTL1_NAKSTS field value from a register. */
72476 #define ALT_USB_DEV_DIEPCTL1_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
72477 /* Produces a ALT_USB_DEV_DIEPCTL1_NAKSTS register field value suitable for setting the register. */
72478 #define ALT_USB_DEV_DIEPCTL1_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
72479 
72480 /*
72481  * Field : eptype
72482  *
72483  * Endpoint Type (EPType)
72484  *
72485  * This is the transfer type supported by this logical endpoint.
72486  *
72487  * 2'b00: Control
72488  *
72489  * 2'b01: Isochronous
72490  *
72491  * 2'b10: Bulk
72492  *
72493  * 2'b11: Interrupt
72494  *
72495  * Field Enumeration Values:
72496  *
72497  * Enum | Value | Description
72498  * :------------------------------------------|:------|:------------
72499  * ALT_USB_DEV_DIEPCTL1_EPTYPE_E_CTL | 0x0 | Control
72500  * ALT_USB_DEV_DIEPCTL1_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
72501  * ALT_USB_DEV_DIEPCTL1_EPTYPE_E_BULK | 0x2 | Bulk
72502  * ALT_USB_DEV_DIEPCTL1_EPTYPE_E_INTERRUP | 0x3 | Interrupt
72503  *
72504  * Field Access Macros:
72505  *
72506  */
72507 /*
72508  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE
72509  *
72510  * Control
72511  */
72512 #define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_CTL 0x0
72513 /*
72514  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE
72515  *
72516  * Isochronous
72517  */
72518 #define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_ISOCHRONOUS 0x1
72519 /*
72520  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE
72521  *
72522  * Bulk
72523  */
72524 #define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_BULK 0x2
72525 /*
72526  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE
72527  *
72528  * Interrupt
72529  */
72530 #define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_INTERRUP 0x3
72531 
72532 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */
72533 #define ALT_USB_DEV_DIEPCTL1_EPTYPE_LSB 18
72534 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */
72535 #define ALT_USB_DEV_DIEPCTL1_EPTYPE_MSB 19
72536 /* The width in bits of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */
72537 #define ALT_USB_DEV_DIEPCTL1_EPTYPE_WIDTH 2
72538 /* The mask used to set the ALT_USB_DEV_DIEPCTL1_EPTYPE register field value. */
72539 #define ALT_USB_DEV_DIEPCTL1_EPTYPE_SET_MSK 0x000c0000
72540 /* The mask used to clear the ALT_USB_DEV_DIEPCTL1_EPTYPE register field value. */
72541 #define ALT_USB_DEV_DIEPCTL1_EPTYPE_CLR_MSK 0xfff3ffff
72542 /* The reset value of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */
72543 #define ALT_USB_DEV_DIEPCTL1_EPTYPE_RESET 0x0
72544 /* Extracts the ALT_USB_DEV_DIEPCTL1_EPTYPE field value from a register. */
72545 #define ALT_USB_DEV_DIEPCTL1_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
72546 /* Produces a ALT_USB_DEV_DIEPCTL1_EPTYPE register field value suitable for setting the register. */
72547 #define ALT_USB_DEV_DIEPCTL1_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
72548 
72549 /*
72550  * Field : stall
72551  *
72552  * STALL Handshake (Stall)
72553  *
72554  * Applies to non-control, non-isochronous IN and OUT endpoints only.
72555  *
72556  * The application sets this bit to stall all tokens from the USB host to this
72557  * endpoint. If a
72558  *
72559  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
72560  * bit, the
72561  *
72562  * STALL bit takes priority. Only the application can clear this bit, never the
72563  * core.
72564  *
72565  * 1'b0 R_W
72566  *
72567  * Applies to control endpoints only.
72568  *
72569  * The application can only set this bit, and the core clears it, when a SETUP
72570  * token is
72571  *
72572  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
72573  * OUT
72574  *
72575  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
72576  * this bit's
72577  *
72578  * setting, the core always responds to SETUP data packets with an ACK handshake.
72579  *
72580  * Field Enumeration Values:
72581  *
72582  * Enum | Value | Description
72583  * :-----------------------------------|:------|:----------------------------
72584  * ALT_USB_DEV_DIEPCTL1_STALL_E_INACT | 0x0 | STALL All Tokens not active
72585  * ALT_USB_DEV_DIEPCTL1_STALL_E_ACT | 0x1 | STALL All Tokens active
72586  *
72587  * Field Access Macros:
72588  *
72589  */
72590 /*
72591  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_STALL
72592  *
72593  * STALL All Tokens not active
72594  */
72595 #define ALT_USB_DEV_DIEPCTL1_STALL_E_INACT 0x0
72596 /*
72597  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_STALL
72598  *
72599  * STALL All Tokens active
72600  */
72601 #define ALT_USB_DEV_DIEPCTL1_STALL_E_ACT 0x1
72602 
72603 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_STALL register field. */
72604 #define ALT_USB_DEV_DIEPCTL1_STALL_LSB 21
72605 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_STALL register field. */
72606 #define ALT_USB_DEV_DIEPCTL1_STALL_MSB 21
72607 /* The width in bits of the ALT_USB_DEV_DIEPCTL1_STALL register field. */
72608 #define ALT_USB_DEV_DIEPCTL1_STALL_WIDTH 1
72609 /* The mask used to set the ALT_USB_DEV_DIEPCTL1_STALL register field value. */
72610 #define ALT_USB_DEV_DIEPCTL1_STALL_SET_MSK 0x00200000
72611 /* The mask used to clear the ALT_USB_DEV_DIEPCTL1_STALL register field value. */
72612 #define ALT_USB_DEV_DIEPCTL1_STALL_CLR_MSK 0xffdfffff
72613 /* The reset value of the ALT_USB_DEV_DIEPCTL1_STALL register field. */
72614 #define ALT_USB_DEV_DIEPCTL1_STALL_RESET 0x0
72615 /* Extracts the ALT_USB_DEV_DIEPCTL1_STALL field value from a register. */
72616 #define ALT_USB_DEV_DIEPCTL1_STALL_GET(value) (((value) & 0x00200000) >> 21)
72617 /* Produces a ALT_USB_DEV_DIEPCTL1_STALL register field value suitable for setting the register. */
72618 #define ALT_USB_DEV_DIEPCTL1_STALL_SET(value) (((value) << 21) & 0x00200000)
72619 
72620 /*
72621  * Field : txfnum
72622  *
72623  * TxFIFO Number (TxFNum)
72624  *
72625  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
72626  *
72627  * endpoints must map this to the corresponding Periodic TxFIFO number.
72628  *
72629  * 4'h0: Non-Periodic TxFIFO
72630  *
72631  * Others: Specified Periodic TxFIFO.number
72632  *
72633  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
72634  *
72635  * applications such as mass storage. The core treats an IN endpoint as a non-
72636  * periodic
72637  *
72638  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
72639  * must be
72640  *
72641  * allocated for an interrupt IN endpoint, and the number of this
72642  *
72643  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
72644  *
72645  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
72646  *
72647  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
72648  *
72649  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
72650  *
72651  * This field is valid only for IN endpoints.
72652  *
72653  * Field Access Macros:
72654  *
72655  */
72656 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */
72657 #define ALT_USB_DEV_DIEPCTL1_TXFNUM_LSB 22
72658 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */
72659 #define ALT_USB_DEV_DIEPCTL1_TXFNUM_MSB 25
72660 /* The width in bits of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */
72661 #define ALT_USB_DEV_DIEPCTL1_TXFNUM_WIDTH 4
72662 /* The mask used to set the ALT_USB_DEV_DIEPCTL1_TXFNUM register field value. */
72663 #define ALT_USB_DEV_DIEPCTL1_TXFNUM_SET_MSK 0x03c00000
72664 /* The mask used to clear the ALT_USB_DEV_DIEPCTL1_TXFNUM register field value. */
72665 #define ALT_USB_DEV_DIEPCTL1_TXFNUM_CLR_MSK 0xfc3fffff
72666 /* The reset value of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */
72667 #define ALT_USB_DEV_DIEPCTL1_TXFNUM_RESET 0x0
72668 /* Extracts the ALT_USB_DEV_DIEPCTL1_TXFNUM field value from a register. */
72669 #define ALT_USB_DEV_DIEPCTL1_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
72670 /* Produces a ALT_USB_DEV_DIEPCTL1_TXFNUM register field value suitable for setting the register. */
72671 #define ALT_USB_DEV_DIEPCTL1_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
72672 
72673 /*
72674  * Field : cnak
72675  *
72676  * Clear NAK (CNAK)
72677  *
72678  * A write to this bit clears the NAK bit For the endpoint.
72679  *
72680  * Field Enumeration Values:
72681  *
72682  * Enum | Value | Description
72683  * :----------------------------------|:------|:-------------
72684  * ALT_USB_DEV_DIEPCTL1_CNAK_E_INACT | 0x0 | No Clear NAK
72685  * ALT_USB_DEV_DIEPCTL1_CNAK_E_ACT | 0x1 | Clear NAK
72686  *
72687  * Field Access Macros:
72688  *
72689  */
72690 /*
72691  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_CNAK
72692  *
72693  * No Clear NAK
72694  */
72695 #define ALT_USB_DEV_DIEPCTL1_CNAK_E_INACT 0x0
72696 /*
72697  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_CNAK
72698  *
72699  * Clear NAK
72700  */
72701 #define ALT_USB_DEV_DIEPCTL1_CNAK_E_ACT 0x1
72702 
72703 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */
72704 #define ALT_USB_DEV_DIEPCTL1_CNAK_LSB 26
72705 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */
72706 #define ALT_USB_DEV_DIEPCTL1_CNAK_MSB 26
72707 /* The width in bits of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */
72708 #define ALT_USB_DEV_DIEPCTL1_CNAK_WIDTH 1
72709 /* The mask used to set the ALT_USB_DEV_DIEPCTL1_CNAK register field value. */
72710 #define ALT_USB_DEV_DIEPCTL1_CNAK_SET_MSK 0x04000000
72711 /* The mask used to clear the ALT_USB_DEV_DIEPCTL1_CNAK register field value. */
72712 #define ALT_USB_DEV_DIEPCTL1_CNAK_CLR_MSK 0xfbffffff
72713 /* The reset value of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */
72714 #define ALT_USB_DEV_DIEPCTL1_CNAK_RESET 0x0
72715 /* Extracts the ALT_USB_DEV_DIEPCTL1_CNAK field value from a register. */
72716 #define ALT_USB_DEV_DIEPCTL1_CNAK_GET(value) (((value) & 0x04000000) >> 26)
72717 /* Produces a ALT_USB_DEV_DIEPCTL1_CNAK register field value suitable for setting the register. */
72718 #define ALT_USB_DEV_DIEPCTL1_CNAK_SET(value) (((value) << 26) & 0x04000000)
72719 
72720 /*
72721  * Field : snak
72722  *
72723  * Set NAK (SNAK)
72724  *
72725  * A write to this bit sets the NAK bit For the endpoint.
72726  *
72727  * Using this bit, the application can control the transmission of NAK
72728  *
72729  * handshakes on an endpoint. The core can also Set this bit For an
72730  *
72731  * endpoint after a SETUP packet is received on that endpoint.
72732  *
72733  * Field Enumeration Values:
72734  *
72735  * Enum | Value | Description
72736  * :----------------------------------|:------|:------------
72737  * ALT_USB_DEV_DIEPCTL1_SNAK_E_INACT | 0x0 | No Set NAK
72738  * ALT_USB_DEV_DIEPCTL1_SNAK_E_ACT | 0x1 | Set NAK
72739  *
72740  * Field Access Macros:
72741  *
72742  */
72743 /*
72744  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SNAK
72745  *
72746  * No Set NAK
72747  */
72748 #define ALT_USB_DEV_DIEPCTL1_SNAK_E_INACT 0x0
72749 /*
72750  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SNAK
72751  *
72752  * Set NAK
72753  */
72754 #define ALT_USB_DEV_DIEPCTL1_SNAK_E_ACT 0x1
72755 
72756 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */
72757 #define ALT_USB_DEV_DIEPCTL1_SNAK_LSB 27
72758 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */
72759 #define ALT_USB_DEV_DIEPCTL1_SNAK_MSB 27
72760 /* The width in bits of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */
72761 #define ALT_USB_DEV_DIEPCTL1_SNAK_WIDTH 1
72762 /* The mask used to set the ALT_USB_DEV_DIEPCTL1_SNAK register field value. */
72763 #define ALT_USB_DEV_DIEPCTL1_SNAK_SET_MSK 0x08000000
72764 /* The mask used to clear the ALT_USB_DEV_DIEPCTL1_SNAK register field value. */
72765 #define ALT_USB_DEV_DIEPCTL1_SNAK_CLR_MSK 0xf7ffffff
72766 /* The reset value of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */
72767 #define ALT_USB_DEV_DIEPCTL1_SNAK_RESET 0x0
72768 /* Extracts the ALT_USB_DEV_DIEPCTL1_SNAK field value from a register. */
72769 #define ALT_USB_DEV_DIEPCTL1_SNAK_GET(value) (((value) & 0x08000000) >> 27)
72770 /* Produces a ALT_USB_DEV_DIEPCTL1_SNAK register field value suitable for setting the register. */
72771 #define ALT_USB_DEV_DIEPCTL1_SNAK_SET(value) (((value) << 27) & 0x08000000)
72772 
72773 /*
72774  * Field : setd0pid
72775  *
72776  * Set DATA0 PID (SetD0PID)
72777  *
72778  * Applies to interrupt/bulk IN and OUT endpoints only.
72779  *
72780  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
72781  * to DATA0.
72782  *
72783  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
72784  *
72785  * DMA mode.
72786  *
72787  * 1'b0 WO
72788  *
72789  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
72790  *
72791  * Applies to isochronous IN and OUT endpoints only.
72792  *
72793  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
72794  * (micro)
72795  *
72796  * frame.
72797  *
72798  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
72799  * number
72800  *
72801  * in which to send data is in the transmit descriptor structure. The frame in
72802  * which to
72803  *
72804  * receive data is updated in receive descriptor structure.
72805  *
72806  * Field Enumeration Values:
72807  *
72808  * Enum | Value | Description
72809  * :-------------------------------------|:------|:----------------------------
72810  * ALT_USB_DEV_DIEPCTL1_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
72811  * ALT_USB_DEV_DIEPCTL1_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
72812  *
72813  * Field Access Macros:
72814  *
72815  */
72816 /*
72817  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD0PID
72818  *
72819  * Disables Set DATA0 PID
72820  */
72821 #define ALT_USB_DEV_DIEPCTL1_SETD0PID_E_DISD 0x0
72822 /*
72823  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD0PID
72824  *
72825  * Endpoint Data PID to DATA0)
72826  */
72827 #define ALT_USB_DEV_DIEPCTL1_SETD0PID_E_END 0x1
72828 
72829 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */
72830 #define ALT_USB_DEV_DIEPCTL1_SETD0PID_LSB 28
72831 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */
72832 #define ALT_USB_DEV_DIEPCTL1_SETD0PID_MSB 28
72833 /* The width in bits of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */
72834 #define ALT_USB_DEV_DIEPCTL1_SETD0PID_WIDTH 1
72835 /* The mask used to set the ALT_USB_DEV_DIEPCTL1_SETD0PID register field value. */
72836 #define ALT_USB_DEV_DIEPCTL1_SETD0PID_SET_MSK 0x10000000
72837 /* The mask used to clear the ALT_USB_DEV_DIEPCTL1_SETD0PID register field value. */
72838 #define ALT_USB_DEV_DIEPCTL1_SETD0PID_CLR_MSK 0xefffffff
72839 /* The reset value of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */
72840 #define ALT_USB_DEV_DIEPCTL1_SETD0PID_RESET 0x0
72841 /* Extracts the ALT_USB_DEV_DIEPCTL1_SETD0PID field value from a register. */
72842 #define ALT_USB_DEV_DIEPCTL1_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
72843 /* Produces a ALT_USB_DEV_DIEPCTL1_SETD0PID register field value suitable for setting the register. */
72844 #define ALT_USB_DEV_DIEPCTL1_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
72845 
72846 /*
72847  * Field : setd1pid
72848  *
72849  * Set DATA1 PID (SetD1PID)
72850  *
72851  * Applies to interrupt/bulk IN and OUT endpoints only.
72852  *
72853  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
72854  * to DATA1.
72855  *
72856  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
72857  *
72858  * DMA mode.
72859  *
72860  * Set Odd (micro)frame (SetOddFr)
72861  *
72862  * Applies to isochronous IN and OUT endpoints only.
72863  *
72864  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
72865  *
72866  * (micro)frame.
72867  *
72868  * This field is not applicable for Scatter/Gather DMA mode.
72869  *
72870  * Field Enumeration Values:
72871  *
72872  * Enum | Value | Description
72873  * :-------------------------------------|:------|:-----------------------
72874  * ALT_USB_DEV_DIEPCTL1_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
72875  * ALT_USB_DEV_DIEPCTL1_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
72876  *
72877  * Field Access Macros:
72878  *
72879  */
72880 /*
72881  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD1PID
72882  *
72883  * Disables Set DATA1 PID
72884  */
72885 #define ALT_USB_DEV_DIEPCTL1_SETD1PID_E_DISD 0x0
72886 /*
72887  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD1PID
72888  *
72889  * Enables Set DATA1 PID
72890  */
72891 #define ALT_USB_DEV_DIEPCTL1_SETD1PID_E_END 0x1
72892 
72893 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */
72894 #define ALT_USB_DEV_DIEPCTL1_SETD1PID_LSB 29
72895 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */
72896 #define ALT_USB_DEV_DIEPCTL1_SETD1PID_MSB 29
72897 /* The width in bits of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */
72898 #define ALT_USB_DEV_DIEPCTL1_SETD1PID_WIDTH 1
72899 /* The mask used to set the ALT_USB_DEV_DIEPCTL1_SETD1PID register field value. */
72900 #define ALT_USB_DEV_DIEPCTL1_SETD1PID_SET_MSK 0x20000000
72901 /* The mask used to clear the ALT_USB_DEV_DIEPCTL1_SETD1PID register field value. */
72902 #define ALT_USB_DEV_DIEPCTL1_SETD1PID_CLR_MSK 0xdfffffff
72903 /* The reset value of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */
72904 #define ALT_USB_DEV_DIEPCTL1_SETD1PID_RESET 0x0
72905 /* Extracts the ALT_USB_DEV_DIEPCTL1_SETD1PID field value from a register. */
72906 #define ALT_USB_DEV_DIEPCTL1_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
72907 /* Produces a ALT_USB_DEV_DIEPCTL1_SETD1PID register field value suitable for setting the register. */
72908 #define ALT_USB_DEV_DIEPCTL1_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
72909 
72910 /*
72911  * Field : epdis
72912  *
72913  * Endpoint Disable (EPDis)
72914  *
72915  * Applies to IN and OUT endpoints.
72916  *
72917  * The application sets this bit to stop transmitting/receiving data on an
72918  * endpoint, even
72919  *
72920  * before the transfer for that endpoint is complete. The application must wait for
72921  * the
72922  *
72923  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
72924  * clears
72925  *
72926  * this bit before setting the Endpoint Disabled interrupt. The application must
72927  * set this bit
72928  *
72929  * only if Endpoint Enable is already set for this endpoint.
72930  *
72931  * Field Enumeration Values:
72932  *
72933  * Enum | Value | Description
72934  * :-----------------------------------|:------|:--------------------
72935  * ALT_USB_DEV_DIEPCTL1_EPDIS_E_INACT | 0x0 | No Endpoint Disable
72936  * ALT_USB_DEV_DIEPCTL1_EPDIS_E_ACT | 0x1 | Endpoint Disable
72937  *
72938  * Field Access Macros:
72939  *
72940  */
72941 /*
72942  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPDIS
72943  *
72944  * No Endpoint Disable
72945  */
72946 #define ALT_USB_DEV_DIEPCTL1_EPDIS_E_INACT 0x0
72947 /*
72948  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPDIS
72949  *
72950  * Endpoint Disable
72951  */
72952 #define ALT_USB_DEV_DIEPCTL1_EPDIS_E_ACT 0x1
72953 
72954 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */
72955 #define ALT_USB_DEV_DIEPCTL1_EPDIS_LSB 30
72956 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */
72957 #define ALT_USB_DEV_DIEPCTL1_EPDIS_MSB 30
72958 /* The width in bits of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */
72959 #define ALT_USB_DEV_DIEPCTL1_EPDIS_WIDTH 1
72960 /* The mask used to set the ALT_USB_DEV_DIEPCTL1_EPDIS register field value. */
72961 #define ALT_USB_DEV_DIEPCTL1_EPDIS_SET_MSK 0x40000000
72962 /* The mask used to clear the ALT_USB_DEV_DIEPCTL1_EPDIS register field value. */
72963 #define ALT_USB_DEV_DIEPCTL1_EPDIS_CLR_MSK 0xbfffffff
72964 /* The reset value of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */
72965 #define ALT_USB_DEV_DIEPCTL1_EPDIS_RESET 0x0
72966 /* Extracts the ALT_USB_DEV_DIEPCTL1_EPDIS field value from a register. */
72967 #define ALT_USB_DEV_DIEPCTL1_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
72968 /* Produces a ALT_USB_DEV_DIEPCTL1_EPDIS register field value suitable for setting the register. */
72969 #define ALT_USB_DEV_DIEPCTL1_EPDIS_SET(value) (((value) << 30) & 0x40000000)
72970 
72971 /*
72972  * Field : epena
72973  *
72974  * Endpoint Enable (EPEna)
72975  *
72976  * Applies to IN and OUT endpoints.
72977  *
72978  * When Scatter/Gather DMA mode is enabled,
72979  *
72980  * For IN endpoints this bit indicates that the descriptor structure and data
72981  * buffer with
72982  *
72983  * data ready to transmit is setup.
72984  *
72985  * For OUT endpoint it indicates that the descriptor structure and data buffer to
72986  *
72987  * receive data is setup.
72988  *
72989  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
72990  *
72991  * DMA mode:
72992  *
72993  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
72994  * the
72995  *
72996  * endpoint.
72997  *
72998  * * For OUT endpoints, this bit indicates that the application has allocated the
72999  *
73000  * memory to start receiving data from the USB.
73001  *
73002  * * The core clears this bit before setting any of the following interrupts on
73003  * this
73004  *
73005  * endpoint:
73006  *
73007  * SETUP Phase Done
73008  *
73009  * Endpoint Disabled
73010  *
73011  * Transfer Completed
73012  *
73013  * Note: For control endpoints in DMA mode, this bit must be set to be able to
73014  * transfer
73015  *
73016  * SETUP data packets in memory.
73017  *
73018  * Field Enumeration Values:
73019  *
73020  * Enum | Value | Description
73021  * :-----------------------------------|:------|:-------------------------
73022  * ALT_USB_DEV_DIEPCTL1_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
73023  * ALT_USB_DEV_DIEPCTL1_EPENA_E_ACT | 0x1 | Endpoint Enable active
73024  *
73025  * Field Access Macros:
73026  *
73027  */
73028 /*
73029  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPENA
73030  *
73031  * Endpoint Enable inactive
73032  */
73033 #define ALT_USB_DEV_DIEPCTL1_EPENA_E_INACT 0x0
73034 /*
73035  * Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPENA
73036  *
73037  * Endpoint Enable active
73038  */
73039 #define ALT_USB_DEV_DIEPCTL1_EPENA_E_ACT 0x1
73040 
73041 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */
73042 #define ALT_USB_DEV_DIEPCTL1_EPENA_LSB 31
73043 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */
73044 #define ALT_USB_DEV_DIEPCTL1_EPENA_MSB 31
73045 /* The width in bits of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */
73046 #define ALT_USB_DEV_DIEPCTL1_EPENA_WIDTH 1
73047 /* The mask used to set the ALT_USB_DEV_DIEPCTL1_EPENA register field value. */
73048 #define ALT_USB_DEV_DIEPCTL1_EPENA_SET_MSK 0x80000000
73049 /* The mask used to clear the ALT_USB_DEV_DIEPCTL1_EPENA register field value. */
73050 #define ALT_USB_DEV_DIEPCTL1_EPENA_CLR_MSK 0x7fffffff
73051 /* The reset value of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */
73052 #define ALT_USB_DEV_DIEPCTL1_EPENA_RESET 0x0
73053 /* Extracts the ALT_USB_DEV_DIEPCTL1_EPENA field value from a register. */
73054 #define ALT_USB_DEV_DIEPCTL1_EPENA_GET(value) (((value) & 0x80000000) >> 31)
73055 /* Produces a ALT_USB_DEV_DIEPCTL1_EPENA register field value suitable for setting the register. */
73056 #define ALT_USB_DEV_DIEPCTL1_EPENA_SET(value) (((value) << 31) & 0x80000000)
73057 
73058 #ifndef __ASSEMBLY__
73059 /*
73060  * WARNING: The C register and register group struct declarations are provided for
73061  * convenience and illustrative purposes. They should, however, be used with
73062  * caution as the C language standard provides no guarantees about the alignment or
73063  * atomicity of device memory accesses. The recommended practice for writing
73064  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
73065  * alt_write_word() functions.
73066  *
73067  * The struct declaration for register ALT_USB_DEV_DIEPCTL1.
73068  */
73069 struct ALT_USB_DEV_DIEPCTL1_s
73070 {
73071  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL1_MPS */
73072  uint32_t : 4; /* *UNDEFINED* */
73073  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL1_USBACTEP */
73074  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL1_DPID */
73075  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL1_NAKSTS */
73076  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL1_EPTYPE */
73077  uint32_t : 1; /* *UNDEFINED* */
73078  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL1_STALL */
73079  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL1_TXFNUM */
73080  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL1_CNAK */
73081  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL1_SNAK */
73082  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL1_SETD0PID */
73083  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL1_SETD1PID */
73084  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL1_EPDIS */
73085  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL1_EPENA */
73086 };
73087 
73088 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL1. */
73089 typedef volatile struct ALT_USB_DEV_DIEPCTL1_s ALT_USB_DEV_DIEPCTL1_t;
73090 #endif /* __ASSEMBLY__ */
73091 
73092 /* The reset value of the ALT_USB_DEV_DIEPCTL1 register. */
73093 #define ALT_USB_DEV_DIEPCTL1_RESET 0x00000000
73094 /* The byte offset of the ALT_USB_DEV_DIEPCTL1 register from the beginning of the component. */
73095 #define ALT_USB_DEV_DIEPCTL1_OFST 0x120
73096 /* The address of the ALT_USB_DEV_DIEPCTL1 register. */
73097 #define ALT_USB_DEV_DIEPCTL1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL1_OFST))
73098 
73099 /*
73100  * Register : diepint1
73101  *
73102  * Device IN Endpoint 1 Interrupt Register
73103  *
73104  * Register Layout
73105  *
73106  * Bits | Access | Reset | Description
73107  * :--------|:-------|:------|:---------------------------------
73108  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_XFERCOMPL
73109  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_EPDISBLD
73110  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_AHBERR
73111  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_TMO
73112  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_INTKNTXFEMP
73113  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_INTKNEPMIS
73114  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_INEPNAKEFF
73115  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT1_TXFEMP
73116  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN
73117  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_BNAINTR
73118  * [10] | ??? | 0x0 | *UNDEFINED*
73119  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_PKTDRPSTS
73120  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_BBLEERR
73121  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_NAKINTRPT
73122  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_NYETINTRPT
73123  * [31:15] | ??? | 0x0 | *UNDEFINED*
73124  *
73125  */
73126 /*
73127  * Field : xfercompl
73128  *
73129  * Transfer Completed Interrupt (XferCompl)
73130  *
73131  * Applies to IN and OUT endpoints.
73132  *
73133  * When Scatter/Gather DMA mode is enabled
73134  *
73135  * * For IN endpoint this field indicates that the requested data
73136  *
73137  * from the descriptor is moved from external system memory
73138  *
73139  * to internal FIFO.
73140  *
73141  * * For OUT endpoint this field indicates that the requested
73142  *
73143  * data from the internal FIFO is moved to external system
73144  *
73145  * memory. This interrupt is generated only when the
73146  *
73147  * corresponding endpoint descriptor is closed, and the IOC
73148  *
73149  * bit For the corresponding descriptor is Set.
73150  *
73151  * When Scatter/Gather DMA mode is disabled, this field
73152  *
73153  * indicates that the programmed transfer is complete on the
73154  *
73155  * AHB as well as on the USB, For this endpoint.
73156  *
73157  * Field Enumeration Values:
73158  *
73159  * Enum | Value | Description
73160  * :---------------------------------------|:------|:-----------------------------
73161  * ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_INACT | 0x0 | No Interrupt
73162  * ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
73163  *
73164  * Field Access Macros:
73165  *
73166  */
73167 /*
73168  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_XFERCOMPL
73169  *
73170  * No Interrupt
73171  */
73172 #define ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_INACT 0x0
73173 /*
73174  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_XFERCOMPL
73175  *
73176  * Transfer Completed Interrupt
73177  */
73178 #define ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_ACT 0x1
73179 
73180 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */
73181 #define ALT_USB_DEV_DIEPINT1_XFERCOMPL_LSB 0
73182 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */
73183 #define ALT_USB_DEV_DIEPINT1_XFERCOMPL_MSB 0
73184 /* The width in bits of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */
73185 #define ALT_USB_DEV_DIEPINT1_XFERCOMPL_WIDTH 1
73186 /* The mask used to set the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field value. */
73187 #define ALT_USB_DEV_DIEPINT1_XFERCOMPL_SET_MSK 0x00000001
73188 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field value. */
73189 #define ALT_USB_DEV_DIEPINT1_XFERCOMPL_CLR_MSK 0xfffffffe
73190 /* The reset value of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */
73191 #define ALT_USB_DEV_DIEPINT1_XFERCOMPL_RESET 0x0
73192 /* Extracts the ALT_USB_DEV_DIEPINT1_XFERCOMPL field value from a register. */
73193 #define ALT_USB_DEV_DIEPINT1_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
73194 /* Produces a ALT_USB_DEV_DIEPINT1_XFERCOMPL register field value suitable for setting the register. */
73195 #define ALT_USB_DEV_DIEPINT1_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
73196 
73197 /*
73198  * Field : epdisbld
73199  *
73200  * Endpoint Disabled Interrupt (EPDisbld)
73201  *
73202  * Applies to IN and OUT endpoints.
73203  *
73204  * This bit indicates that the endpoint is disabled per the
73205  *
73206  * application's request.
73207  *
73208  * Field Enumeration Values:
73209  *
73210  * Enum | Value | Description
73211  * :--------------------------------------|:------|:----------------------------
73212  * ALT_USB_DEV_DIEPINT1_EPDISBLD_E_INACT | 0x0 | No Interrupt
73213  * ALT_USB_DEV_DIEPINT1_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
73214  *
73215  * Field Access Macros:
73216  *
73217  */
73218 /*
73219  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_EPDISBLD
73220  *
73221  * No Interrupt
73222  */
73223 #define ALT_USB_DEV_DIEPINT1_EPDISBLD_E_INACT 0x0
73224 /*
73225  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_EPDISBLD
73226  *
73227  * Endpoint Disabled Interrupt
73228  */
73229 #define ALT_USB_DEV_DIEPINT1_EPDISBLD_E_ACT 0x1
73230 
73231 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */
73232 #define ALT_USB_DEV_DIEPINT1_EPDISBLD_LSB 1
73233 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */
73234 #define ALT_USB_DEV_DIEPINT1_EPDISBLD_MSB 1
73235 /* The width in bits of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */
73236 #define ALT_USB_DEV_DIEPINT1_EPDISBLD_WIDTH 1
73237 /* The mask used to set the ALT_USB_DEV_DIEPINT1_EPDISBLD register field value. */
73238 #define ALT_USB_DEV_DIEPINT1_EPDISBLD_SET_MSK 0x00000002
73239 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_EPDISBLD register field value. */
73240 #define ALT_USB_DEV_DIEPINT1_EPDISBLD_CLR_MSK 0xfffffffd
73241 /* The reset value of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */
73242 #define ALT_USB_DEV_DIEPINT1_EPDISBLD_RESET 0x0
73243 /* Extracts the ALT_USB_DEV_DIEPINT1_EPDISBLD field value from a register. */
73244 #define ALT_USB_DEV_DIEPINT1_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
73245 /* Produces a ALT_USB_DEV_DIEPINT1_EPDISBLD register field value suitable for setting the register. */
73246 #define ALT_USB_DEV_DIEPINT1_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
73247 
73248 /*
73249  * Field : ahberr
73250  *
73251  * AHB Error (AHBErr)
73252  *
73253  * Applies to IN and OUT endpoints.
73254  *
73255  * This is generated only in Internal DMA mode when there is an
73256  *
73257  * AHB error during an AHB read/write. The application can read
73258  *
73259  * the corresponding endpoint DMA address register to get the
73260  *
73261  * error address.
73262  *
73263  * Field Enumeration Values:
73264  *
73265  * Enum | Value | Description
73266  * :------------------------------------|:------|:--------------------
73267  * ALT_USB_DEV_DIEPINT1_AHBERR_E_INACT | 0x0 | No Interrupt
73268  * ALT_USB_DEV_DIEPINT1_AHBERR_E_ACT | 0x1 | AHB Error interrupt
73269  *
73270  * Field Access Macros:
73271  *
73272  */
73273 /*
73274  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_AHBERR
73275  *
73276  * No Interrupt
73277  */
73278 #define ALT_USB_DEV_DIEPINT1_AHBERR_E_INACT 0x0
73279 /*
73280  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_AHBERR
73281  *
73282  * AHB Error interrupt
73283  */
73284 #define ALT_USB_DEV_DIEPINT1_AHBERR_E_ACT 0x1
73285 
73286 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */
73287 #define ALT_USB_DEV_DIEPINT1_AHBERR_LSB 2
73288 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */
73289 #define ALT_USB_DEV_DIEPINT1_AHBERR_MSB 2
73290 /* The width in bits of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */
73291 #define ALT_USB_DEV_DIEPINT1_AHBERR_WIDTH 1
73292 /* The mask used to set the ALT_USB_DEV_DIEPINT1_AHBERR register field value. */
73293 #define ALT_USB_DEV_DIEPINT1_AHBERR_SET_MSK 0x00000004
73294 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_AHBERR register field value. */
73295 #define ALT_USB_DEV_DIEPINT1_AHBERR_CLR_MSK 0xfffffffb
73296 /* The reset value of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */
73297 #define ALT_USB_DEV_DIEPINT1_AHBERR_RESET 0x0
73298 /* Extracts the ALT_USB_DEV_DIEPINT1_AHBERR field value from a register. */
73299 #define ALT_USB_DEV_DIEPINT1_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
73300 /* Produces a ALT_USB_DEV_DIEPINT1_AHBERR register field value suitable for setting the register. */
73301 #define ALT_USB_DEV_DIEPINT1_AHBERR_SET(value) (((value) << 2) & 0x00000004)
73302 
73303 /*
73304  * Field : timeout
73305  *
73306  * Timeout Condition (TimeOUT)
73307  *
73308  * In shared TX FIFO mode, applies to non-isochronous IN
73309  *
73310  * endpoints only.
73311  *
73312  * In dedicated FIFO mode, applies only to Control IN
73313  *
73314  * endpoints.
73315  *
73316  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
73317  *
73318  * asserted.
73319  *
73320  * Indicates that the core has detected a timeout condition on the
73321  *
73322  * USB For the last IN token on this endpoint.
73323  *
73324  * Field Enumeration Values:
73325  *
73326  * Enum | Value | Description
73327  * :---------------------------------|:------|:------------------
73328  * ALT_USB_DEV_DIEPINT1_TMO_E_INACT | 0x0 | No interrupt
73329  * ALT_USB_DEV_DIEPINT1_TMO_E_ACT | 0x1 | Timeout interrupy
73330  *
73331  * Field Access Macros:
73332  *
73333  */
73334 /*
73335  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TMO
73336  *
73337  * No interrupt
73338  */
73339 #define ALT_USB_DEV_DIEPINT1_TMO_E_INACT 0x0
73340 /*
73341  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TMO
73342  *
73343  * Timeout interrupy
73344  */
73345 #define ALT_USB_DEV_DIEPINT1_TMO_E_ACT 0x1
73346 
73347 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_TMO register field. */
73348 #define ALT_USB_DEV_DIEPINT1_TMO_LSB 3
73349 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_TMO register field. */
73350 #define ALT_USB_DEV_DIEPINT1_TMO_MSB 3
73351 /* The width in bits of the ALT_USB_DEV_DIEPINT1_TMO register field. */
73352 #define ALT_USB_DEV_DIEPINT1_TMO_WIDTH 1
73353 /* The mask used to set the ALT_USB_DEV_DIEPINT1_TMO register field value. */
73354 #define ALT_USB_DEV_DIEPINT1_TMO_SET_MSK 0x00000008
73355 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_TMO register field value. */
73356 #define ALT_USB_DEV_DIEPINT1_TMO_CLR_MSK 0xfffffff7
73357 /* The reset value of the ALT_USB_DEV_DIEPINT1_TMO register field. */
73358 #define ALT_USB_DEV_DIEPINT1_TMO_RESET 0x0
73359 /* Extracts the ALT_USB_DEV_DIEPINT1_TMO field value from a register. */
73360 #define ALT_USB_DEV_DIEPINT1_TMO_GET(value) (((value) & 0x00000008) >> 3)
73361 /* Produces a ALT_USB_DEV_DIEPINT1_TMO register field value suitable for setting the register. */
73362 #define ALT_USB_DEV_DIEPINT1_TMO_SET(value) (((value) << 3) & 0x00000008)
73363 
73364 /*
73365  * Field : intkntxfemp
73366  *
73367  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
73368  *
73369  * Applies to non-periodic IN endpoints only.
73370  *
73371  * Indicates that an IN token was received when the associated
73372  *
73373  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
73374  *
73375  * asserted on the endpoint For which the IN token was received.
73376  *
73377  * Field Enumeration Values:
73378  *
73379  * Enum | Value | Description
73380  * :-----------------------------------------|:------|:----------------------------
73381  * ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
73382  * ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
73383  *
73384  * Field Access Macros:
73385  *
73386  */
73387 /*
73388  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNTXFEMP
73389  *
73390  * No interrupt
73391  */
73392 #define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_INACT 0x0
73393 /*
73394  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNTXFEMP
73395  *
73396  * IN Token Received Interrupt
73397  */
73398 #define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_ACT 0x1
73399 
73400 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */
73401 #define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_LSB 4
73402 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */
73403 #define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_MSB 4
73404 /* The width in bits of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */
73405 #define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_WIDTH 1
73406 /* The mask used to set the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field value. */
73407 #define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_SET_MSK 0x00000010
73408 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field value. */
73409 #define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_CLR_MSK 0xffffffef
73410 /* The reset value of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */
73411 #define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_RESET 0x0
73412 /* Extracts the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP field value from a register. */
73413 #define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
73414 /* Produces a ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field value suitable for setting the register. */
73415 #define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
73416 
73417 /*
73418  * Field : intknepmis
73419  *
73420  * IN Token Received with EP Mismatch (INTknEPMis)
73421  *
73422  * Applies to non-periodic IN endpoints only.
73423  *
73424  * Indicates that the data in the top of the non-periodic TxFIFO
73425  *
73426  * belongs to an endpoint other than the one For which the IN token
73427  *
73428  * was received. This interrupt is asserted on the endpoint For
73429  *
73430  * which the IN token was received.
73431  *
73432  * Field Enumeration Values:
73433  *
73434  * Enum | Value | Description
73435  * :----------------------------------------|:------|:---------------------------------------------
73436  * ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_INACT | 0x0 | No interrupt
73437  * ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
73438  *
73439  * Field Access Macros:
73440  *
73441  */
73442 /*
73443  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNEPMIS
73444  *
73445  * No interrupt
73446  */
73447 #define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_INACT 0x0
73448 /*
73449  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNEPMIS
73450  *
73451  * IN Token Received with EP Mismatch interrupt
73452  */
73453 #define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_ACT 0x1
73454 
73455 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */
73456 #define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_LSB 5
73457 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */
73458 #define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_MSB 5
73459 /* The width in bits of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */
73460 #define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_WIDTH 1
73461 /* The mask used to set the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field value. */
73462 #define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_SET_MSK 0x00000020
73463 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field value. */
73464 #define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_CLR_MSK 0xffffffdf
73465 /* The reset value of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */
73466 #define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_RESET 0x0
73467 /* Extracts the ALT_USB_DEV_DIEPINT1_INTKNEPMIS field value from a register. */
73468 #define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
73469 /* Produces a ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field value suitable for setting the register. */
73470 #define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
73471 
73472 /*
73473  * Field : inepnakeff
73474  *
73475  * IN Endpoint NAK Effective (INEPNakEff)
73476  *
73477  * Applies to periodic IN endpoints only.
73478  *
73479  * This bit can be cleared when the application clears the IN
73480  *
73481  * endpoint NAK by writing to DIEPCTLn.CNAK.
73482  *
73483  * This interrupt indicates that the core has sampled the NAK bit
73484  *
73485  * Set (either by the application or by the core). The interrupt
73486  *
73487  * indicates that the IN endpoint NAK bit Set by the application has
73488  *
73489  * taken effect in the core.
73490  *
73491  * This interrupt does not guarantee that a NAK handshake is sent
73492  *
73493  * on the USB. A STALL bit takes priority over a NAK bit.
73494  *
73495  * Field Enumeration Values:
73496  *
73497  * Enum | Value | Description
73498  * :----------------------------------------|:------|:------------------------------------
73499  * ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_INACT | 0x0 | No interrupt
73500  * ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
73501  *
73502  * Field Access Macros:
73503  *
73504  */
73505 /*
73506  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INEPNAKEFF
73507  *
73508  * No interrupt
73509  */
73510 #define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_INACT 0x0
73511 /*
73512  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_INEPNAKEFF
73513  *
73514  * IN Endpoint NAK Effective interrupt
73515  */
73516 #define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_ACT 0x1
73517 
73518 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */
73519 #define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_LSB 6
73520 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */
73521 #define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_MSB 6
73522 /* The width in bits of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */
73523 #define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_WIDTH 1
73524 /* The mask used to set the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field value. */
73525 #define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_SET_MSK 0x00000040
73526 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field value. */
73527 #define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_CLR_MSK 0xffffffbf
73528 /* The reset value of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */
73529 #define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_RESET 0x0
73530 /* Extracts the ALT_USB_DEV_DIEPINT1_INEPNAKEFF field value from a register. */
73531 #define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
73532 /* Produces a ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field value suitable for setting the register. */
73533 #define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
73534 
73535 /*
73536  * Field : txfemp
73537  *
73538  * Transmit FIFO Empty (TxFEmp)
73539  *
73540  * This bit is valid only For IN Endpoints
73541  *
73542  * This interrupt is asserted when the TxFIFO For this endpoint is
73543  *
73544  * either half or completely empty. The half or completely empty
73545  *
73546  * status is determined by the TxFIFO Empty Level bit in the Core
73547  *
73548  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
73549  *
73550  * Field Enumeration Values:
73551  *
73552  * Enum | Value | Description
73553  * :------------------------------------|:------|:------------------------------
73554  * ALT_USB_DEV_DIEPINT1_TXFEMP_E_INACT | 0x0 | No interrupt
73555  * ALT_USB_DEV_DIEPINT1_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
73556  *
73557  * Field Access Macros:
73558  *
73559  */
73560 /*
73561  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFEMP
73562  *
73563  * No interrupt
73564  */
73565 #define ALT_USB_DEV_DIEPINT1_TXFEMP_E_INACT 0x0
73566 /*
73567  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFEMP
73568  *
73569  * Transmit FIFO Empty interrupt
73570  */
73571 #define ALT_USB_DEV_DIEPINT1_TXFEMP_E_ACT 0x1
73572 
73573 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */
73574 #define ALT_USB_DEV_DIEPINT1_TXFEMP_LSB 7
73575 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */
73576 #define ALT_USB_DEV_DIEPINT1_TXFEMP_MSB 7
73577 /* The width in bits of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */
73578 #define ALT_USB_DEV_DIEPINT1_TXFEMP_WIDTH 1
73579 /* The mask used to set the ALT_USB_DEV_DIEPINT1_TXFEMP register field value. */
73580 #define ALT_USB_DEV_DIEPINT1_TXFEMP_SET_MSK 0x00000080
73581 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_TXFEMP register field value. */
73582 #define ALT_USB_DEV_DIEPINT1_TXFEMP_CLR_MSK 0xffffff7f
73583 /* The reset value of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */
73584 #define ALT_USB_DEV_DIEPINT1_TXFEMP_RESET 0x1
73585 /* Extracts the ALT_USB_DEV_DIEPINT1_TXFEMP field value from a register. */
73586 #define ALT_USB_DEV_DIEPINT1_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
73587 /* Produces a ALT_USB_DEV_DIEPINT1_TXFEMP register field value suitable for setting the register. */
73588 #define ALT_USB_DEV_DIEPINT1_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
73589 
73590 /*
73591  * Field : txfifoundrn
73592  *
73593  * Fifo Underrun (TxfifoUndrn)
73594  *
73595  * Applies to IN endpoints Only
73596  *
73597  * This bit is valid only If thresholding is enabled. The core generates this
73598  * interrupt when
73599  *
73600  * it detects a transmit FIFO underrun condition For this endpoint.
73601  *
73602  * Field Enumeration Values:
73603  *
73604  * Enum | Value | Description
73605  * :-----------------------------------------|:------|:------------------------
73606  * ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
73607  * ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
73608  *
73609  * Field Access Macros:
73610  *
73611  */
73612 /*
73613  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN
73614  *
73615  * No interrupt
73616  */
73617 #define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_INACT 0x0
73618 /*
73619  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN
73620  *
73621  * Fifo Underrun interrupt
73622  */
73623 #define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_ACT 0x1
73624 
73625 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */
73626 #define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_LSB 8
73627 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */
73628 #define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_MSB 8
73629 /* The width in bits of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */
73630 #define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_WIDTH 1
73631 /* The mask used to set the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field value. */
73632 #define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_SET_MSK 0x00000100
73633 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field value. */
73634 #define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_CLR_MSK 0xfffffeff
73635 /* The reset value of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */
73636 #define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_RESET 0x0
73637 /* Extracts the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN field value from a register. */
73638 #define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
73639 /* Produces a ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field value suitable for setting the register. */
73640 #define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
73641 
73642 /*
73643  * Field : bnaintr
73644  *
73645  * BNA (Buffer Not Available) Interrupt (BNAIntr)
73646  *
73647  * This bit is valid only when Scatter/Gather DMA mode is enabled.
73648  *
73649  * The core generates this interrupt when the descriptor accessed
73650  *
73651  * is not ready For the Core to process, such as Host busy or DMA
73652  *
73653  * done
73654  *
73655  * Field Enumeration Values:
73656  *
73657  * Enum | Value | Description
73658  * :-------------------------------------|:------|:--------------
73659  * ALT_USB_DEV_DIEPINT1_BNAINTR_E_INACT | 0x0 | No interrupt
73660  * ALT_USB_DEV_DIEPINT1_BNAINTR_E_ACT | 0x1 | BNA interrupt
73661  *
73662  * Field Access Macros:
73663  *
73664  */
73665 /*
73666  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_BNAINTR
73667  *
73668  * No interrupt
73669  */
73670 #define ALT_USB_DEV_DIEPINT1_BNAINTR_E_INACT 0x0
73671 /*
73672  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_BNAINTR
73673  *
73674  * BNA interrupt
73675  */
73676 #define ALT_USB_DEV_DIEPINT1_BNAINTR_E_ACT 0x1
73677 
73678 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */
73679 #define ALT_USB_DEV_DIEPINT1_BNAINTR_LSB 9
73680 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */
73681 #define ALT_USB_DEV_DIEPINT1_BNAINTR_MSB 9
73682 /* The width in bits of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */
73683 #define ALT_USB_DEV_DIEPINT1_BNAINTR_WIDTH 1
73684 /* The mask used to set the ALT_USB_DEV_DIEPINT1_BNAINTR register field value. */
73685 #define ALT_USB_DEV_DIEPINT1_BNAINTR_SET_MSK 0x00000200
73686 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_BNAINTR register field value. */
73687 #define ALT_USB_DEV_DIEPINT1_BNAINTR_CLR_MSK 0xfffffdff
73688 /* The reset value of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */
73689 #define ALT_USB_DEV_DIEPINT1_BNAINTR_RESET 0x0
73690 /* Extracts the ALT_USB_DEV_DIEPINT1_BNAINTR field value from a register. */
73691 #define ALT_USB_DEV_DIEPINT1_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
73692 /* Produces a ALT_USB_DEV_DIEPINT1_BNAINTR register field value suitable for setting the register. */
73693 #define ALT_USB_DEV_DIEPINT1_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
73694 
73695 /*
73696  * Field : pktdrpsts
73697  *
73698  * Packet Drop Status (PktDrpSts)
73699  *
73700  * This bit indicates to the application that an ISOC OUT packet has been dropped.
73701  * This
73702  *
73703  * bit does not have an associated mask bit and does not generate an interrupt.
73704  *
73705  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
73706  * transfer
73707  *
73708  * interrupt feature is selected.
73709  *
73710  * Field Enumeration Values:
73711  *
73712  * Enum | Value | Description
73713  * :---------------------------------------|:------|:-----------------------------
73714  * ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_INACT | 0x0 | No interrupt
73715  * ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
73716  *
73717  * Field Access Macros:
73718  *
73719  */
73720 /*
73721  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_PKTDRPSTS
73722  *
73723  * No interrupt
73724  */
73725 #define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_INACT 0x0
73726 /*
73727  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_PKTDRPSTS
73728  *
73729  * Packet Drop Status interrupt
73730  */
73731 #define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_ACT 0x1
73732 
73733 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */
73734 #define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_LSB 11
73735 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */
73736 #define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_MSB 11
73737 /* The width in bits of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */
73738 #define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_WIDTH 1
73739 /* The mask used to set the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field value. */
73740 #define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_SET_MSK 0x00000800
73741 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field value. */
73742 #define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_CLR_MSK 0xfffff7ff
73743 /* The reset value of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */
73744 #define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_RESET 0x0
73745 /* Extracts the ALT_USB_DEV_DIEPINT1_PKTDRPSTS field value from a register. */
73746 #define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
73747 /* Produces a ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field value suitable for setting the register. */
73748 #define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
73749 
73750 /*
73751  * Field : bbleerr
73752  *
73753  * NAK Interrupt (BbleErr)
73754  *
73755  * The core generates this interrupt when babble is received for the endpoint.
73756  *
73757  * Field Enumeration Values:
73758  *
73759  * Enum | Value | Description
73760  * :-------------------------------------|:------|:------------------
73761  * ALT_USB_DEV_DIEPINT1_BBLEERR_E_INACT | 0x0 | No interrupt
73762  * ALT_USB_DEV_DIEPINT1_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
73763  *
73764  * Field Access Macros:
73765  *
73766  */
73767 /*
73768  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_BBLEERR
73769  *
73770  * No interrupt
73771  */
73772 #define ALT_USB_DEV_DIEPINT1_BBLEERR_E_INACT 0x0
73773 /*
73774  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_BBLEERR
73775  *
73776  * BbleErr interrupt
73777  */
73778 #define ALT_USB_DEV_DIEPINT1_BBLEERR_E_ACT 0x1
73779 
73780 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */
73781 #define ALT_USB_DEV_DIEPINT1_BBLEERR_LSB 12
73782 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */
73783 #define ALT_USB_DEV_DIEPINT1_BBLEERR_MSB 12
73784 /* The width in bits of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */
73785 #define ALT_USB_DEV_DIEPINT1_BBLEERR_WIDTH 1
73786 /* The mask used to set the ALT_USB_DEV_DIEPINT1_BBLEERR register field value. */
73787 #define ALT_USB_DEV_DIEPINT1_BBLEERR_SET_MSK 0x00001000
73788 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_BBLEERR register field value. */
73789 #define ALT_USB_DEV_DIEPINT1_BBLEERR_CLR_MSK 0xffffefff
73790 /* The reset value of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */
73791 #define ALT_USB_DEV_DIEPINT1_BBLEERR_RESET 0x0
73792 /* Extracts the ALT_USB_DEV_DIEPINT1_BBLEERR field value from a register. */
73793 #define ALT_USB_DEV_DIEPINT1_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
73794 /* Produces a ALT_USB_DEV_DIEPINT1_BBLEERR register field value suitable for setting the register. */
73795 #define ALT_USB_DEV_DIEPINT1_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
73796 
73797 /*
73798  * Field : nakintrpt
73799  *
73800  * NAK Interrupt (NAKInterrupt)
73801  *
73802  * The core generates this interrupt when a NAK is transmitted or received by the
73803  * device.
73804  *
73805  * In case of isochronous IN endpoints the interrupt gets generated when a zero
73806  * length
73807  *
73808  * packet is transmitted due to un-availability of data in the TXFifo.
73809  *
73810  * Field Enumeration Values:
73811  *
73812  * Enum | Value | Description
73813  * :---------------------------------------|:------|:--------------
73814  * ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_INACT | 0x0 | No interrupt
73815  * ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
73816  *
73817  * Field Access Macros:
73818  *
73819  */
73820 /*
73821  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_NAKINTRPT
73822  *
73823  * No interrupt
73824  */
73825 #define ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_INACT 0x0
73826 /*
73827  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_NAKINTRPT
73828  *
73829  * NAK Interrupt
73830  */
73831 #define ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_ACT 0x1
73832 
73833 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */
73834 #define ALT_USB_DEV_DIEPINT1_NAKINTRPT_LSB 13
73835 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */
73836 #define ALT_USB_DEV_DIEPINT1_NAKINTRPT_MSB 13
73837 /* The width in bits of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */
73838 #define ALT_USB_DEV_DIEPINT1_NAKINTRPT_WIDTH 1
73839 /* The mask used to set the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field value. */
73840 #define ALT_USB_DEV_DIEPINT1_NAKINTRPT_SET_MSK 0x00002000
73841 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field value. */
73842 #define ALT_USB_DEV_DIEPINT1_NAKINTRPT_CLR_MSK 0xffffdfff
73843 /* The reset value of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */
73844 #define ALT_USB_DEV_DIEPINT1_NAKINTRPT_RESET 0x0
73845 /* Extracts the ALT_USB_DEV_DIEPINT1_NAKINTRPT field value from a register. */
73846 #define ALT_USB_DEV_DIEPINT1_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
73847 /* Produces a ALT_USB_DEV_DIEPINT1_NAKINTRPT register field value suitable for setting the register. */
73848 #define ALT_USB_DEV_DIEPINT1_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
73849 
73850 /*
73851  * Field : nyetintrpt
73852  *
73853  * NYET Interrupt (NYETIntrpt)
73854  *
73855  * The core generates this interrupt when a NYET response is transmitted for a non
73856  * isochronous OUT endpoint.
73857  *
73858  * Field Enumeration Values:
73859  *
73860  * Enum | Value | Description
73861  * :----------------------------------------|:------|:---------------
73862  * ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_INACT | 0x0 | No interrupt
73863  * ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
73864  *
73865  * Field Access Macros:
73866  *
73867  */
73868 /*
73869  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_NYETINTRPT
73870  *
73871  * No interrupt
73872  */
73873 #define ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_INACT 0x0
73874 /*
73875  * Enumerated value for register field ALT_USB_DEV_DIEPINT1_NYETINTRPT
73876  *
73877  * NYET Interrupt
73878  */
73879 #define ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_ACT 0x1
73880 
73881 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */
73882 #define ALT_USB_DEV_DIEPINT1_NYETINTRPT_LSB 14
73883 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */
73884 #define ALT_USB_DEV_DIEPINT1_NYETINTRPT_MSB 14
73885 /* The width in bits of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */
73886 #define ALT_USB_DEV_DIEPINT1_NYETINTRPT_WIDTH 1
73887 /* The mask used to set the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field value. */
73888 #define ALT_USB_DEV_DIEPINT1_NYETINTRPT_SET_MSK 0x00004000
73889 /* The mask used to clear the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field value. */
73890 #define ALT_USB_DEV_DIEPINT1_NYETINTRPT_CLR_MSK 0xffffbfff
73891 /* The reset value of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */
73892 #define ALT_USB_DEV_DIEPINT1_NYETINTRPT_RESET 0x0
73893 /* Extracts the ALT_USB_DEV_DIEPINT1_NYETINTRPT field value from a register. */
73894 #define ALT_USB_DEV_DIEPINT1_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
73895 /* Produces a ALT_USB_DEV_DIEPINT1_NYETINTRPT register field value suitable for setting the register. */
73896 #define ALT_USB_DEV_DIEPINT1_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
73897 
73898 #ifndef __ASSEMBLY__
73899 /*
73900  * WARNING: The C register and register group struct declarations are provided for
73901  * convenience and illustrative purposes. They should, however, be used with
73902  * caution as the C language standard provides no guarantees about the alignment or
73903  * atomicity of device memory accesses. The recommended practice for writing
73904  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
73905  * alt_write_word() functions.
73906  *
73907  * The struct declaration for register ALT_USB_DEV_DIEPINT1.
73908  */
73909 struct ALT_USB_DEV_DIEPINT1_s
73910 {
73911  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT1_XFERCOMPL */
73912  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT1_EPDISBLD */
73913  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT1_AHBERR */
73914  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT1_TMO */
73915  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT1_INTKNTXFEMP */
73916  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT1_INTKNEPMIS */
73917  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT1_INEPNAKEFF */
73918  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT1_TXFEMP */
73919  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN */
73920  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT1_BNAINTR */
73921  uint32_t : 1; /* *UNDEFINED* */
73922  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT1_PKTDRPSTS */
73923  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT1_BBLEERR */
73924  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT1_NAKINTRPT */
73925  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT1_NYETINTRPT */
73926  uint32_t : 17; /* *UNDEFINED* */
73927 };
73928 
73929 /* The typedef declaration for register ALT_USB_DEV_DIEPINT1. */
73930 typedef volatile struct ALT_USB_DEV_DIEPINT1_s ALT_USB_DEV_DIEPINT1_t;
73931 #endif /* __ASSEMBLY__ */
73932 
73933 /* The reset value of the ALT_USB_DEV_DIEPINT1 register. */
73934 #define ALT_USB_DEV_DIEPINT1_RESET 0x00000080
73935 /* The byte offset of the ALT_USB_DEV_DIEPINT1 register from the beginning of the component. */
73936 #define ALT_USB_DEV_DIEPINT1_OFST 0x128
73937 /* The address of the ALT_USB_DEV_DIEPINT1 register. */
73938 #define ALT_USB_DEV_DIEPINT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT1_OFST))
73939 
73940 /*
73941  * Register : dieptsiz1
73942  *
73943  * Device IN Endpoint 1 Transfer Size Register
73944  *
73945  * Register Layout
73946  *
73947  * Bits | Access | Reset | Description
73948  * :--------|:-------|:------|:-------------------------------
73949  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ1_XFERSIZE
73950  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ1_PKTCNT
73951  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ1_MC
73952  * [31] | ??? | 0x0 | *UNDEFINED*
73953  *
73954  */
73955 /*
73956  * Field : xfersize
73957  *
73958  * Transfer Size (XferSize)
73959  *
73960  * Indicates the transfer size in bytes For endpoint 0. The core
73961  *
73962  * interrupts the application only after it has exhausted the transfer
73963  *
73964  * size amount of data. The transfer size can be Set to the
73965  *
73966  * maximum packet size of the endpoint, to be interrupted at the
73967  *
73968  * end of each packet.
73969  *
73970  * The core decrements this field every time a packet from the
73971  *
73972  * external memory is written to the TxFIFO.
73973  *
73974  * Field Access Macros:
73975  *
73976  */
73977 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */
73978 #define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_LSB 0
73979 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */
73980 #define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_MSB 18
73981 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */
73982 #define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_WIDTH 19
73983 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field value. */
73984 #define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_SET_MSK 0x0007ffff
73985 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field value. */
73986 #define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_CLR_MSK 0xfff80000
73987 /* The reset value of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */
73988 #define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_RESET 0x0
73989 /* Extracts the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE field value from a register. */
73990 #define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
73991 /* Produces a ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field value suitable for setting the register. */
73992 #define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
73993 
73994 /*
73995  * Field : pktcnt
73996  *
73997  * Packet Count (PktCnt)
73998  *
73999  * Indicates the total number of USB packets that constitute the
74000  *
74001  * Transfer Size amount of data For endpoint 0.
74002  *
74003  * This field is decremented every time a packet (maximum size or
74004  *
74005  * short packet) is read from the TxFIFO.
74006  *
74007  * Field Access Macros:
74008  *
74009  */
74010 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */
74011 #define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_LSB 19
74012 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */
74013 #define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_MSB 28
74014 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */
74015 #define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_WIDTH 10
74016 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field value. */
74017 #define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_SET_MSK 0x1ff80000
74018 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field value. */
74019 #define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_CLR_MSK 0xe007ffff
74020 /* The reset value of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */
74021 #define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_RESET 0x0
74022 /* Extracts the ALT_USB_DEV_DIEPTSIZ1_PKTCNT field value from a register. */
74023 #define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
74024 /* Produces a ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field value suitable for setting the register. */
74025 #define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
74026 
74027 /*
74028  * Field : mc
74029  *
74030  * Applies to IN endpoints only.
74031  *
74032  * For periodic IN endpoints, this field indicates the number of packets that must
74033  * be transmitted per microframe on the USB. The core uses this field to calculate
74034  * the data PID for isochronous IN endpoints.
74035  *
74036  * 2'b01: 1 packet
74037  *
74038  * 2'b10: 2 packets
74039  *
74040  * 2'b11: 3 packets
74041  *
74042  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
74043  * specifies the number of packets the core must fetchfor an IN endpoint before it
74044  * switches to the endpoint pointed to by the Next Endpoint field of the Device
74045  * Endpoint-n Control register (DIEPCTLn.NextEp)
74046  *
74047  * Field Enumeration Values:
74048  *
74049  * Enum | Value | Description
74050  * :------------------------------------|:------|:------------
74051  * ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTONE | 0x1 | 1 packet
74052  * ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTWO | 0x2 | 2 packets
74053  * ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTHREE | 0x3 | 3 packets
74054  *
74055  * Field Access Macros:
74056  *
74057  */
74058 /*
74059  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ1_MC
74060  *
74061  * 1 packet
74062  */
74063 #define ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTONE 0x1
74064 /*
74065  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ1_MC
74066  *
74067  * 2 packets
74068  */
74069 #define ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTWO 0x2
74070 /*
74071  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ1_MC
74072  *
74073  * 3 packets
74074  */
74075 #define ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTHREE 0x3
74076 
74077 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */
74078 #define ALT_USB_DEV_DIEPTSIZ1_MC_LSB 29
74079 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */
74080 #define ALT_USB_DEV_DIEPTSIZ1_MC_MSB 30
74081 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */
74082 #define ALT_USB_DEV_DIEPTSIZ1_MC_WIDTH 2
74083 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ1_MC register field value. */
74084 #define ALT_USB_DEV_DIEPTSIZ1_MC_SET_MSK 0x60000000
74085 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ1_MC register field value. */
74086 #define ALT_USB_DEV_DIEPTSIZ1_MC_CLR_MSK 0x9fffffff
74087 /* The reset value of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */
74088 #define ALT_USB_DEV_DIEPTSIZ1_MC_RESET 0x0
74089 /* Extracts the ALT_USB_DEV_DIEPTSIZ1_MC field value from a register. */
74090 #define ALT_USB_DEV_DIEPTSIZ1_MC_GET(value) (((value) & 0x60000000) >> 29)
74091 /* Produces a ALT_USB_DEV_DIEPTSIZ1_MC register field value suitable for setting the register. */
74092 #define ALT_USB_DEV_DIEPTSIZ1_MC_SET(value) (((value) << 29) & 0x60000000)
74093 
74094 #ifndef __ASSEMBLY__
74095 /*
74096  * WARNING: The C register and register group struct declarations are provided for
74097  * convenience and illustrative purposes. They should, however, be used with
74098  * caution as the C language standard provides no guarantees about the alignment or
74099  * atomicity of device memory accesses. The recommended practice for writing
74100  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
74101  * alt_write_word() functions.
74102  *
74103  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ1.
74104  */
74105 struct ALT_USB_DEV_DIEPTSIZ1_s
74106 {
74107  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ1_XFERSIZE */
74108  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ1_PKTCNT */
74109  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ1_MC */
74110  uint32_t : 1; /* *UNDEFINED* */
74111 };
74112 
74113 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ1. */
74114 typedef volatile struct ALT_USB_DEV_DIEPTSIZ1_s ALT_USB_DEV_DIEPTSIZ1_t;
74115 #endif /* __ASSEMBLY__ */
74116 
74117 /* The reset value of the ALT_USB_DEV_DIEPTSIZ1 register. */
74118 #define ALT_USB_DEV_DIEPTSIZ1_RESET 0x00000000
74119 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ1 register from the beginning of the component. */
74120 #define ALT_USB_DEV_DIEPTSIZ1_OFST 0x130
74121 /* The address of the ALT_USB_DEV_DIEPTSIZ1 register. */
74122 #define ALT_USB_DEV_DIEPTSIZ1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ1_OFST))
74123 
74124 /*
74125  * Register : diepdma1
74126  *
74127  * Device IN Endpoint 1 DMA Address Register
74128  *
74129  * Register Layout
74130  *
74131  * Bits | Access | Reset | Description
74132  * :-------|:-------|:--------|:------------------------------
74133  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA1_DIEPDMA1
74134  *
74135  */
74136 /*
74137  * Field : diepdma1
74138  *
74139  * Holds the start address of the external memory for storing or fetching endpoint
74140  *
74141  * data.
74142  *
74143  * Note: For control endpoints, this field stores control OUT data packets as well
74144  * as
74145  *
74146  * SETUP transaction data packets. When more than three SETUP packets are
74147  *
74148  * received back-to-back, the SETUP data packet in the memory is overwritten.
74149  *
74150  * This register is incremented on every AHB transaction. The application can give
74151  *
74152  * only a DWORD-aligned address.
74153  *
74154  * When Scatter/Gather DMA mode is not enabled, the application programs the
74155  *
74156  * start address value in this field.
74157  *
74158  * When Scatter/Gather DMA mode is enabled, this field indicates the base
74159  *
74160  * pointer for the descriptor list.
74161  *
74162  * Field Access Macros:
74163  *
74164  */
74165 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field. */
74166 #define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_LSB 0
74167 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field. */
74168 #define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_MSB 31
74169 /* The width in bits of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field. */
74170 #define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_WIDTH 32
74171 /* The mask used to set the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field value. */
74172 #define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_SET_MSK 0xffffffff
74173 /* The mask used to clear the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field value. */
74174 #define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_CLR_MSK 0x00000000
74175 /* The reset value of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field is UNKNOWN. */
74176 #define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_RESET 0x0
74177 /* Extracts the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 field value from a register. */
74178 #define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_GET(value) (((value) & 0xffffffff) >> 0)
74179 /* Produces a ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field value suitable for setting the register. */
74180 #define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_SET(value) (((value) << 0) & 0xffffffff)
74181 
74182 #ifndef __ASSEMBLY__
74183 /*
74184  * WARNING: The C register and register group struct declarations are provided for
74185  * convenience and illustrative purposes. They should, however, be used with
74186  * caution as the C language standard provides no guarantees about the alignment or
74187  * atomicity of device memory accesses. The recommended practice for writing
74188  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
74189  * alt_write_word() functions.
74190  *
74191  * The struct declaration for register ALT_USB_DEV_DIEPDMA1.
74192  */
74193 struct ALT_USB_DEV_DIEPDMA1_s
74194 {
74195  uint32_t diepdma1 : 32; /* ALT_USB_DEV_DIEPDMA1_DIEPDMA1 */
74196 };
74197 
74198 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA1. */
74199 typedef volatile struct ALT_USB_DEV_DIEPDMA1_s ALT_USB_DEV_DIEPDMA1_t;
74200 #endif /* __ASSEMBLY__ */
74201 
74202 /* The reset value of the ALT_USB_DEV_DIEPDMA1 register. */
74203 #define ALT_USB_DEV_DIEPDMA1_RESET 0x00000000
74204 /* The byte offset of the ALT_USB_DEV_DIEPDMA1 register from the beginning of the component. */
74205 #define ALT_USB_DEV_DIEPDMA1_OFST 0x134
74206 /* The address of the ALT_USB_DEV_DIEPDMA1 register. */
74207 #define ALT_USB_DEV_DIEPDMA1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA1_OFST))
74208 
74209 /*
74210  * Register : dtxfsts1
74211  *
74212  * Device IN Endpoint Transmit FIFO Status Register 1
74213  *
74214  * Register Layout
74215  *
74216  * Bits | Access | Reset | Description
74217  * :--------|:-------|:-------|:-------------------------------------
74218  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL
74219  * [31:16] | ??? | 0x0 | *UNDEFINED*
74220  *
74221  */
74222 /*
74223  * Field : ineptxfspcavail
74224  *
74225  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
74226  *
74227  * Indicates the amount of free space available in the Endpoint
74228  *
74229  * TxFIFO.
74230  *
74231  * Values are in terms of 32-bit words.
74232  *
74233  * 16'h0: Endpoint TxFIFO is full
74234  *
74235  * 16'h1: 1 word available
74236  *
74237  * 16'h2: 2 words available
74238  *
74239  * 16'hn: n words available (where 0 n 32,768)
74240  *
74241  * 16'h8000: 32,768 words available
74242  *
74243  * Others: Reserved
74244  *
74245  * Field Access Macros:
74246  *
74247  */
74248 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */
74249 #define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_LSB 0
74250 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */
74251 #define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_MSB 15
74252 /* The width in bits of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */
74253 #define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_WIDTH 16
74254 /* The mask used to set the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field value. */
74255 #define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
74256 /* The mask used to clear the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field value. */
74257 #define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
74258 /* The reset value of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */
74259 #define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_RESET 0x2000
74260 /* Extracts the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL field value from a register. */
74261 #define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
74262 /* Produces a ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field value suitable for setting the register. */
74263 #define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
74264 
74265 #ifndef __ASSEMBLY__
74266 /*
74267  * WARNING: The C register and register group struct declarations are provided for
74268  * convenience and illustrative purposes. They should, however, be used with
74269  * caution as the C language standard provides no guarantees about the alignment or
74270  * atomicity of device memory accesses. The recommended practice for writing
74271  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
74272  * alt_write_word() functions.
74273  *
74274  * The struct declaration for register ALT_USB_DEV_DTXFSTS1.
74275  */
74276 struct ALT_USB_DEV_DTXFSTS1_s
74277 {
74278  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL */
74279  uint32_t : 16; /* *UNDEFINED* */
74280 };
74281 
74282 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS1. */
74283 typedef volatile struct ALT_USB_DEV_DTXFSTS1_s ALT_USB_DEV_DTXFSTS1_t;
74284 #endif /* __ASSEMBLY__ */
74285 
74286 /* The reset value of the ALT_USB_DEV_DTXFSTS1 register. */
74287 #define ALT_USB_DEV_DTXFSTS1_RESET 0x00002000
74288 /* The byte offset of the ALT_USB_DEV_DTXFSTS1 register from the beginning of the component. */
74289 #define ALT_USB_DEV_DTXFSTS1_OFST 0x138
74290 /* The address of the ALT_USB_DEV_DTXFSTS1 register. */
74291 #define ALT_USB_DEV_DTXFSTS1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS1_OFST))
74292 
74293 /*
74294  * Register : diepdmab1
74295  *
74296  * Device IN Endpoint 1 Buffer Address Register
74297  *
74298  * Register Layout
74299  *
74300  * Bits | Access | Reset | Description
74301  * :-------|:-------|:--------|:--------------------------------
74302  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1
74303  *
74304  */
74305 /*
74306  * Field : diepdmab1
74307  *
74308  * Holds the current buffer address.This register is updated as and when the data
74309  *
74310  * transfer for the corresponding end point is in progress.
74311  *
74312  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
74313  * is
74314  *
74315  * reserved.
74316  *
74317  * Field Access Macros:
74318  *
74319  */
74320 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field. */
74321 #define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_LSB 0
74322 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field. */
74323 #define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_MSB 31
74324 /* The width in bits of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field. */
74325 #define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_WIDTH 32
74326 /* The mask used to set the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field value. */
74327 #define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_SET_MSK 0xffffffff
74328 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field value. */
74329 #define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_CLR_MSK 0x00000000
74330 /* The reset value of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field is UNKNOWN. */
74331 #define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_RESET 0x0
74332 /* Extracts the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 field value from a register. */
74333 #define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_GET(value) (((value) & 0xffffffff) >> 0)
74334 /* Produces a ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field value suitable for setting the register. */
74335 #define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_SET(value) (((value) << 0) & 0xffffffff)
74336 
74337 #ifndef __ASSEMBLY__
74338 /*
74339  * WARNING: The C register and register group struct declarations are provided for
74340  * convenience and illustrative purposes. They should, however, be used with
74341  * caution as the C language standard provides no guarantees about the alignment or
74342  * atomicity of device memory accesses. The recommended practice for writing
74343  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
74344  * alt_write_word() functions.
74345  *
74346  * The struct declaration for register ALT_USB_DEV_DIEPDMAB1.
74347  */
74348 struct ALT_USB_DEV_DIEPDMAB1_s
74349 {
74350  const uint32_t diepdmab1 : 32; /* ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 */
74351 };
74352 
74353 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB1. */
74354 typedef volatile struct ALT_USB_DEV_DIEPDMAB1_s ALT_USB_DEV_DIEPDMAB1_t;
74355 #endif /* __ASSEMBLY__ */
74356 
74357 /* The reset value of the ALT_USB_DEV_DIEPDMAB1 register. */
74358 #define ALT_USB_DEV_DIEPDMAB1_RESET 0x00000000
74359 /* The byte offset of the ALT_USB_DEV_DIEPDMAB1 register from the beginning of the component. */
74360 #define ALT_USB_DEV_DIEPDMAB1_OFST 0x13c
74361 /* The address of the ALT_USB_DEV_DIEPDMAB1 register. */
74362 #define ALT_USB_DEV_DIEPDMAB1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB1_OFST))
74363 
74364 /*
74365  * Register : diepctl2
74366  *
74367  * Device Control IN Endpoint 2 Control Register
74368  *
74369  * Register Layout
74370  *
74371  * Bits | Access | Reset | Description
74372  * :--------|:---------|:------|:------------------------------
74373  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL2_MPS
74374  * [14:11] | ??? | 0x0 | *UNDEFINED*
74375  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL2_USBACTEP
74376  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL2_DPID
74377  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL2_NAKSTS
74378  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL2_EPTYPE
74379  * [20] | ??? | 0x0 | *UNDEFINED*
74380  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL2_STALL
74381  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL2_TXFNUM
74382  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL2_CNAK
74383  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL2_SNAK
74384  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL2_SETD0PID
74385  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL2_SETD1PID
74386  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL2_EPDIS
74387  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL2_EPENA
74388  *
74389  */
74390 /*
74391  * Field : mps
74392  *
74393  * Maximum Packet Size (MPS)
74394  *
74395  * The application must program this field with the maximum packet size for the
74396  * current
74397  *
74398  * logical endpoint. This value is in bytes.
74399  *
74400  * Field Access Macros:
74401  *
74402  */
74403 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_MPS register field. */
74404 #define ALT_USB_DEV_DIEPCTL2_MPS_LSB 0
74405 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_MPS register field. */
74406 #define ALT_USB_DEV_DIEPCTL2_MPS_MSB 10
74407 /* The width in bits of the ALT_USB_DEV_DIEPCTL2_MPS register field. */
74408 #define ALT_USB_DEV_DIEPCTL2_MPS_WIDTH 11
74409 /* The mask used to set the ALT_USB_DEV_DIEPCTL2_MPS register field value. */
74410 #define ALT_USB_DEV_DIEPCTL2_MPS_SET_MSK 0x000007ff
74411 /* The mask used to clear the ALT_USB_DEV_DIEPCTL2_MPS register field value. */
74412 #define ALT_USB_DEV_DIEPCTL2_MPS_CLR_MSK 0xfffff800
74413 /* The reset value of the ALT_USB_DEV_DIEPCTL2_MPS register field. */
74414 #define ALT_USB_DEV_DIEPCTL2_MPS_RESET 0x0
74415 /* Extracts the ALT_USB_DEV_DIEPCTL2_MPS field value from a register. */
74416 #define ALT_USB_DEV_DIEPCTL2_MPS_GET(value) (((value) & 0x000007ff) >> 0)
74417 /* Produces a ALT_USB_DEV_DIEPCTL2_MPS register field value suitable for setting the register. */
74418 #define ALT_USB_DEV_DIEPCTL2_MPS_SET(value) (((value) << 0) & 0x000007ff)
74419 
74420 /*
74421  * Field : usbactep
74422  *
74423  * USB Active Endpoint (USBActEP)
74424  *
74425  * Indicates whether this endpoint is active in the current configuration and
74426  * interface. The
74427  *
74428  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
74429  * reset. After
74430  *
74431  * receiving the SetConfiguration and SetInterface commands, the application must
74432  *
74433  * program endpoint registers accordingly and set this bit.
74434  *
74435  * Field Enumeration Values:
74436  *
74437  * Enum | Value | Description
74438  * :-------------------------------------|:------|:--------------------
74439  * ALT_USB_DEV_DIEPCTL2_USBACTEP_E_DISD | 0x0 | Not Active
74440  * ALT_USB_DEV_DIEPCTL2_USBACTEP_E_END | 0x1 | USB Active Endpoint
74441  *
74442  * Field Access Macros:
74443  *
74444  */
74445 /*
74446  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_USBACTEP
74447  *
74448  * Not Active
74449  */
74450 #define ALT_USB_DEV_DIEPCTL2_USBACTEP_E_DISD 0x0
74451 /*
74452  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_USBACTEP
74453  *
74454  * USB Active Endpoint
74455  */
74456 #define ALT_USB_DEV_DIEPCTL2_USBACTEP_E_END 0x1
74457 
74458 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */
74459 #define ALT_USB_DEV_DIEPCTL2_USBACTEP_LSB 15
74460 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */
74461 #define ALT_USB_DEV_DIEPCTL2_USBACTEP_MSB 15
74462 /* The width in bits of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */
74463 #define ALT_USB_DEV_DIEPCTL2_USBACTEP_WIDTH 1
74464 /* The mask used to set the ALT_USB_DEV_DIEPCTL2_USBACTEP register field value. */
74465 #define ALT_USB_DEV_DIEPCTL2_USBACTEP_SET_MSK 0x00008000
74466 /* The mask used to clear the ALT_USB_DEV_DIEPCTL2_USBACTEP register field value. */
74467 #define ALT_USB_DEV_DIEPCTL2_USBACTEP_CLR_MSK 0xffff7fff
74468 /* The reset value of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */
74469 #define ALT_USB_DEV_DIEPCTL2_USBACTEP_RESET 0x0
74470 /* Extracts the ALT_USB_DEV_DIEPCTL2_USBACTEP field value from a register. */
74471 #define ALT_USB_DEV_DIEPCTL2_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
74472 /* Produces a ALT_USB_DEV_DIEPCTL2_USBACTEP register field value suitable for setting the register. */
74473 #define ALT_USB_DEV_DIEPCTL2_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
74474 
74475 /*
74476  * Field : dpid
74477  *
74478  * Endpoint Data PID (DPID)
74479  *
74480  * Applies to interrupt/bulk IN and OUT endpoints only.
74481  *
74482  * Contains the PID of the packet to be received or transmitted on this endpoint.
74483  * The
74484  *
74485  * application must program the PID of the first packet to be received or
74486  * transmitted on
74487  *
74488  * this endpoint, after the endpoint is activated. The applications use the
74489  * SetD1PID and
74490  *
74491  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
74492  *
74493  * 1'b0: DATA0
74494  *
74495  * 1'b1: DATA1
74496  *
74497  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
74498  *
74499  * DMA mode.
74500  *
74501  * 1'b0 RO
74502  *
74503  * Even/Odd (Micro)Frame (EO_FrNum)
74504  *
74505  * In non-Scatter/Gather DMA mode:
74506  *
74507  * Applies to isochronous IN and OUT endpoints only.
74508  *
74509  * Indicates the (micro)frame number in which the core transmits/receives
74510  * isochronous
74511  *
74512  * data for this endpoint. The application must program the even/odd (micro) frame
74513  *
74514  * number in which it intends to transmit/receive isochronous data for this
74515  * endpoint using
74516  *
74517  * the SetEvnFr and SetOddFr fields in this register.
74518  *
74519  * 1'b0: Even (micro)frame
74520  *
74521  * 1'b1: Odd (micro)frame
74522  *
74523  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
74524  * number
74525  *
74526  * in which to send data is provided in the transmit descriptor structure. The
74527  * frame in
74528  *
74529  * which data is received is updated in receive descriptor structure.
74530  *
74531  * Field Enumeration Values:
74532  *
74533  * Enum | Value | Description
74534  * :----------------------------------|:------|:-----------------------------
74535  * ALT_USB_DEV_DIEPCTL2_DPID_E_INACT | 0x0 | Endpoint Data PID not active
74536  * ALT_USB_DEV_DIEPCTL2_DPID_E_ACT | 0x1 | Endpoint Data PID active
74537  *
74538  * Field Access Macros:
74539  *
74540  */
74541 /*
74542  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_DPID
74543  *
74544  * Endpoint Data PID not active
74545  */
74546 #define ALT_USB_DEV_DIEPCTL2_DPID_E_INACT 0x0
74547 /*
74548  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_DPID
74549  *
74550  * Endpoint Data PID active
74551  */
74552 #define ALT_USB_DEV_DIEPCTL2_DPID_E_ACT 0x1
74553 
74554 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_DPID register field. */
74555 #define ALT_USB_DEV_DIEPCTL2_DPID_LSB 16
74556 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_DPID register field. */
74557 #define ALT_USB_DEV_DIEPCTL2_DPID_MSB 16
74558 /* The width in bits of the ALT_USB_DEV_DIEPCTL2_DPID register field. */
74559 #define ALT_USB_DEV_DIEPCTL2_DPID_WIDTH 1
74560 /* The mask used to set the ALT_USB_DEV_DIEPCTL2_DPID register field value. */
74561 #define ALT_USB_DEV_DIEPCTL2_DPID_SET_MSK 0x00010000
74562 /* The mask used to clear the ALT_USB_DEV_DIEPCTL2_DPID register field value. */
74563 #define ALT_USB_DEV_DIEPCTL2_DPID_CLR_MSK 0xfffeffff
74564 /* The reset value of the ALT_USB_DEV_DIEPCTL2_DPID register field. */
74565 #define ALT_USB_DEV_DIEPCTL2_DPID_RESET 0x0
74566 /* Extracts the ALT_USB_DEV_DIEPCTL2_DPID field value from a register. */
74567 #define ALT_USB_DEV_DIEPCTL2_DPID_GET(value) (((value) & 0x00010000) >> 16)
74568 /* Produces a ALT_USB_DEV_DIEPCTL2_DPID register field value suitable for setting the register. */
74569 #define ALT_USB_DEV_DIEPCTL2_DPID_SET(value) (((value) << 16) & 0x00010000)
74570 
74571 /*
74572  * Field : naksts
74573  *
74574  * NAK Status (NAKSts)
74575  *
74576  * Indicates the following:
74577  *
74578  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
74579  *
74580  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
74581  *
74582  * When either the application or the core sets this bit:
74583  *
74584  * The core stops receiving any data on an OUT endpoint, even if there is space in
74585  *
74586  * the RxFIFO to accommodate the incoming packet.
74587  *
74588  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
74589  *
74590  * endpoint, even if there data is available in the TxFIFO.
74591  *
74592  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
74593  *
74594  * if there data is available in the TxFIFO.
74595  *
74596  * Irrespective of this bit's setting, the core always responds to SETUP data
74597  * packets with
74598  *
74599  * an ACK handshake.
74600  *
74601  * Field Enumeration Values:
74602  *
74603  * Enum | Value | Description
74604  * :-------------------------------------|:------|:------------------------------------------------
74605  * ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
74606  * : | | based on the FIFO status
74607  * ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
74608  * : | | endpoint
74609  *
74610  * Field Access Macros:
74611  *
74612  */
74613 /*
74614  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_NAKSTS
74615  *
74616  * The core is transmitting non-NAK handshakes based on the FIFO status
74617  */
74618 #define ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NONNAK 0x0
74619 /*
74620  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_NAKSTS
74621  *
74622  * The core is transmitting NAK handshakes on this endpoint
74623  */
74624 #define ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NAK 0x1
74625 
74626 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */
74627 #define ALT_USB_DEV_DIEPCTL2_NAKSTS_LSB 17
74628 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */
74629 #define ALT_USB_DEV_DIEPCTL2_NAKSTS_MSB 17
74630 /* The width in bits of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */
74631 #define ALT_USB_DEV_DIEPCTL2_NAKSTS_WIDTH 1
74632 /* The mask used to set the ALT_USB_DEV_DIEPCTL2_NAKSTS register field value. */
74633 #define ALT_USB_DEV_DIEPCTL2_NAKSTS_SET_MSK 0x00020000
74634 /* The mask used to clear the ALT_USB_DEV_DIEPCTL2_NAKSTS register field value. */
74635 #define ALT_USB_DEV_DIEPCTL2_NAKSTS_CLR_MSK 0xfffdffff
74636 /* The reset value of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */
74637 #define ALT_USB_DEV_DIEPCTL2_NAKSTS_RESET 0x0
74638 /* Extracts the ALT_USB_DEV_DIEPCTL2_NAKSTS field value from a register. */
74639 #define ALT_USB_DEV_DIEPCTL2_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
74640 /* Produces a ALT_USB_DEV_DIEPCTL2_NAKSTS register field value suitable for setting the register. */
74641 #define ALT_USB_DEV_DIEPCTL2_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
74642 
74643 /*
74644  * Field : eptype
74645  *
74646  * Endpoint Type (EPType)
74647  *
74648  * This is the transfer type supported by this logical endpoint.
74649  *
74650  * 2'b00: Control
74651  *
74652  * 2'b01: Isochronous
74653  *
74654  * 2'b10: Bulk
74655  *
74656  * 2'b11: Interrupt
74657  *
74658  * Field Enumeration Values:
74659  *
74660  * Enum | Value | Description
74661  * :------------------------------------------|:------|:------------
74662  * ALT_USB_DEV_DIEPCTL2_EPTYPE_E_CTL | 0x0 | Control
74663  * ALT_USB_DEV_DIEPCTL2_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
74664  * ALT_USB_DEV_DIEPCTL2_EPTYPE_E_BULK | 0x2 | Bulk
74665  * ALT_USB_DEV_DIEPCTL2_EPTYPE_E_INTERRUP | 0x3 | Interrupt
74666  *
74667  * Field Access Macros:
74668  *
74669  */
74670 /*
74671  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE
74672  *
74673  * Control
74674  */
74675 #define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_CTL 0x0
74676 /*
74677  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE
74678  *
74679  * Isochronous
74680  */
74681 #define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_ISOCHRONOUS 0x1
74682 /*
74683  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE
74684  *
74685  * Bulk
74686  */
74687 #define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_BULK 0x2
74688 /*
74689  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE
74690  *
74691  * Interrupt
74692  */
74693 #define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_INTERRUP 0x3
74694 
74695 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */
74696 #define ALT_USB_DEV_DIEPCTL2_EPTYPE_LSB 18
74697 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */
74698 #define ALT_USB_DEV_DIEPCTL2_EPTYPE_MSB 19
74699 /* The width in bits of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */
74700 #define ALT_USB_DEV_DIEPCTL2_EPTYPE_WIDTH 2
74701 /* The mask used to set the ALT_USB_DEV_DIEPCTL2_EPTYPE register field value. */
74702 #define ALT_USB_DEV_DIEPCTL2_EPTYPE_SET_MSK 0x000c0000
74703 /* The mask used to clear the ALT_USB_DEV_DIEPCTL2_EPTYPE register field value. */
74704 #define ALT_USB_DEV_DIEPCTL2_EPTYPE_CLR_MSK 0xfff3ffff
74705 /* The reset value of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */
74706 #define ALT_USB_DEV_DIEPCTL2_EPTYPE_RESET 0x0
74707 /* Extracts the ALT_USB_DEV_DIEPCTL2_EPTYPE field value from a register. */
74708 #define ALT_USB_DEV_DIEPCTL2_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
74709 /* Produces a ALT_USB_DEV_DIEPCTL2_EPTYPE register field value suitable for setting the register. */
74710 #define ALT_USB_DEV_DIEPCTL2_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
74711 
74712 /*
74713  * Field : stall
74714  *
74715  * STALL Handshake (Stall)
74716  *
74717  * Applies to non-control, non-isochronous IN and OUT endpoints only.
74718  *
74719  * The application sets this bit to stall all tokens from the USB host to this
74720  * endpoint. If a
74721  *
74722  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
74723  * bit, the
74724  *
74725  * STALL bit takes priority. Only the application can clear this bit, never the
74726  * core.
74727  *
74728  * 1'b0 R_W
74729  *
74730  * Applies to control endpoints only.
74731  *
74732  * The application can only set this bit, and the core clears it, when a SETUP
74733  * token is
74734  *
74735  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
74736  * OUT
74737  *
74738  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
74739  * this bit's
74740  *
74741  * setting, the core always responds to SETUP data packets with an ACK handshake.
74742  *
74743  * Field Enumeration Values:
74744  *
74745  * Enum | Value | Description
74746  * :-----------------------------------|:------|:----------------------------
74747  * ALT_USB_DEV_DIEPCTL2_STALL_E_INACT | 0x0 | STALL All Tokens not active
74748  * ALT_USB_DEV_DIEPCTL2_STALL_E_ACT | 0x1 | STALL All Tokens active
74749  *
74750  * Field Access Macros:
74751  *
74752  */
74753 /*
74754  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_STALL
74755  *
74756  * STALL All Tokens not active
74757  */
74758 #define ALT_USB_DEV_DIEPCTL2_STALL_E_INACT 0x0
74759 /*
74760  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_STALL
74761  *
74762  * STALL All Tokens active
74763  */
74764 #define ALT_USB_DEV_DIEPCTL2_STALL_E_ACT 0x1
74765 
74766 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_STALL register field. */
74767 #define ALT_USB_DEV_DIEPCTL2_STALL_LSB 21
74768 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_STALL register field. */
74769 #define ALT_USB_DEV_DIEPCTL2_STALL_MSB 21
74770 /* The width in bits of the ALT_USB_DEV_DIEPCTL2_STALL register field. */
74771 #define ALT_USB_DEV_DIEPCTL2_STALL_WIDTH 1
74772 /* The mask used to set the ALT_USB_DEV_DIEPCTL2_STALL register field value. */
74773 #define ALT_USB_DEV_DIEPCTL2_STALL_SET_MSK 0x00200000
74774 /* The mask used to clear the ALT_USB_DEV_DIEPCTL2_STALL register field value. */
74775 #define ALT_USB_DEV_DIEPCTL2_STALL_CLR_MSK 0xffdfffff
74776 /* The reset value of the ALT_USB_DEV_DIEPCTL2_STALL register field. */
74777 #define ALT_USB_DEV_DIEPCTL2_STALL_RESET 0x0
74778 /* Extracts the ALT_USB_DEV_DIEPCTL2_STALL field value from a register. */
74779 #define ALT_USB_DEV_DIEPCTL2_STALL_GET(value) (((value) & 0x00200000) >> 21)
74780 /* Produces a ALT_USB_DEV_DIEPCTL2_STALL register field value suitable for setting the register. */
74781 #define ALT_USB_DEV_DIEPCTL2_STALL_SET(value) (((value) << 21) & 0x00200000)
74782 
74783 /*
74784  * Field : txfnum
74785  *
74786  * TxFIFO Number (TxFNum)
74787  *
74788  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
74789  *
74790  * endpoints must map this to the corresponding Periodic TxFIFO number.
74791  *
74792  * 4'h0: Non-Periodic TxFIFO
74793  *
74794  * Others: Specified Periodic TxFIFO.number
74795  *
74796  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
74797  *
74798  * applications such as mass storage. The core treats an IN endpoint as a non-
74799  * periodic
74800  *
74801  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
74802  * must be
74803  *
74804  * allocated for an interrupt IN endpoint, and the number of this
74805  *
74806  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
74807  *
74808  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
74809  *
74810  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
74811  *
74812  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
74813  *
74814  * This field is valid only for IN endpoints.
74815  *
74816  * Field Access Macros:
74817  *
74818  */
74819 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */
74820 #define ALT_USB_DEV_DIEPCTL2_TXFNUM_LSB 22
74821 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */
74822 #define ALT_USB_DEV_DIEPCTL2_TXFNUM_MSB 25
74823 /* The width in bits of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */
74824 #define ALT_USB_DEV_DIEPCTL2_TXFNUM_WIDTH 4
74825 /* The mask used to set the ALT_USB_DEV_DIEPCTL2_TXFNUM register field value. */
74826 #define ALT_USB_DEV_DIEPCTL2_TXFNUM_SET_MSK 0x03c00000
74827 /* The mask used to clear the ALT_USB_DEV_DIEPCTL2_TXFNUM register field value. */
74828 #define ALT_USB_DEV_DIEPCTL2_TXFNUM_CLR_MSK 0xfc3fffff
74829 /* The reset value of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */
74830 #define ALT_USB_DEV_DIEPCTL2_TXFNUM_RESET 0x0
74831 /* Extracts the ALT_USB_DEV_DIEPCTL2_TXFNUM field value from a register. */
74832 #define ALT_USB_DEV_DIEPCTL2_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
74833 /* Produces a ALT_USB_DEV_DIEPCTL2_TXFNUM register field value suitable for setting the register. */
74834 #define ALT_USB_DEV_DIEPCTL2_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
74835 
74836 /*
74837  * Field : cnak
74838  *
74839  * Clear NAK (CNAK)
74840  *
74841  * A write to this bit clears the NAK bit For the endpoint.
74842  *
74843  * Field Enumeration Values:
74844  *
74845  * Enum | Value | Description
74846  * :----------------------------------|:------|:-------------
74847  * ALT_USB_DEV_DIEPCTL2_CNAK_E_INACT | 0x0 | No Clear NAK
74848  * ALT_USB_DEV_DIEPCTL2_CNAK_E_ACT | 0x1 | Clear NAK
74849  *
74850  * Field Access Macros:
74851  *
74852  */
74853 /*
74854  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_CNAK
74855  *
74856  * No Clear NAK
74857  */
74858 #define ALT_USB_DEV_DIEPCTL2_CNAK_E_INACT 0x0
74859 /*
74860  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_CNAK
74861  *
74862  * Clear NAK
74863  */
74864 #define ALT_USB_DEV_DIEPCTL2_CNAK_E_ACT 0x1
74865 
74866 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */
74867 #define ALT_USB_DEV_DIEPCTL2_CNAK_LSB 26
74868 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */
74869 #define ALT_USB_DEV_DIEPCTL2_CNAK_MSB 26
74870 /* The width in bits of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */
74871 #define ALT_USB_DEV_DIEPCTL2_CNAK_WIDTH 1
74872 /* The mask used to set the ALT_USB_DEV_DIEPCTL2_CNAK register field value. */
74873 #define ALT_USB_DEV_DIEPCTL2_CNAK_SET_MSK 0x04000000
74874 /* The mask used to clear the ALT_USB_DEV_DIEPCTL2_CNAK register field value. */
74875 #define ALT_USB_DEV_DIEPCTL2_CNAK_CLR_MSK 0xfbffffff
74876 /* The reset value of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */
74877 #define ALT_USB_DEV_DIEPCTL2_CNAK_RESET 0x0
74878 /* Extracts the ALT_USB_DEV_DIEPCTL2_CNAK field value from a register. */
74879 #define ALT_USB_DEV_DIEPCTL2_CNAK_GET(value) (((value) & 0x04000000) >> 26)
74880 /* Produces a ALT_USB_DEV_DIEPCTL2_CNAK register field value suitable for setting the register. */
74881 #define ALT_USB_DEV_DIEPCTL2_CNAK_SET(value) (((value) << 26) & 0x04000000)
74882 
74883 /*
74884  * Field : snak
74885  *
74886  * Set NAK (SNAK)
74887  *
74888  * A write to this bit sets the NAK bit For the endpoint.
74889  *
74890  * Using this bit, the application can control the transmission of NAK
74891  *
74892  * handshakes on an endpoint. The core can also Set this bit For an
74893  *
74894  * endpoint after a SETUP packet is received on that endpoint.
74895  *
74896  * Field Enumeration Values:
74897  *
74898  * Enum | Value | Description
74899  * :----------------------------------|:------|:------------
74900  * ALT_USB_DEV_DIEPCTL2_SNAK_E_INACT | 0x0 | No Set NAK
74901  * ALT_USB_DEV_DIEPCTL2_SNAK_E_ACT | 0x1 | Set NAK
74902  *
74903  * Field Access Macros:
74904  *
74905  */
74906 /*
74907  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SNAK
74908  *
74909  * No Set NAK
74910  */
74911 #define ALT_USB_DEV_DIEPCTL2_SNAK_E_INACT 0x0
74912 /*
74913  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SNAK
74914  *
74915  * Set NAK
74916  */
74917 #define ALT_USB_DEV_DIEPCTL2_SNAK_E_ACT 0x1
74918 
74919 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */
74920 #define ALT_USB_DEV_DIEPCTL2_SNAK_LSB 27
74921 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */
74922 #define ALT_USB_DEV_DIEPCTL2_SNAK_MSB 27
74923 /* The width in bits of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */
74924 #define ALT_USB_DEV_DIEPCTL2_SNAK_WIDTH 1
74925 /* The mask used to set the ALT_USB_DEV_DIEPCTL2_SNAK register field value. */
74926 #define ALT_USB_DEV_DIEPCTL2_SNAK_SET_MSK 0x08000000
74927 /* The mask used to clear the ALT_USB_DEV_DIEPCTL2_SNAK register field value. */
74928 #define ALT_USB_DEV_DIEPCTL2_SNAK_CLR_MSK 0xf7ffffff
74929 /* The reset value of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */
74930 #define ALT_USB_DEV_DIEPCTL2_SNAK_RESET 0x0
74931 /* Extracts the ALT_USB_DEV_DIEPCTL2_SNAK field value from a register. */
74932 #define ALT_USB_DEV_DIEPCTL2_SNAK_GET(value) (((value) & 0x08000000) >> 27)
74933 /* Produces a ALT_USB_DEV_DIEPCTL2_SNAK register field value suitable for setting the register. */
74934 #define ALT_USB_DEV_DIEPCTL2_SNAK_SET(value) (((value) << 27) & 0x08000000)
74935 
74936 /*
74937  * Field : setd0pid
74938  *
74939  * Set DATA0 PID (SetD0PID)
74940  *
74941  * Applies to interrupt/bulk IN and OUT endpoints only.
74942  *
74943  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
74944  * to DATA0.
74945  *
74946  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
74947  *
74948  * DMA mode.
74949  *
74950  * 1'b0 WO
74951  *
74952  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
74953  *
74954  * Applies to isochronous IN and OUT endpoints only.
74955  *
74956  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
74957  * (micro)
74958  *
74959  * frame.
74960  *
74961  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
74962  * number
74963  *
74964  * in which to send data is in the transmit descriptor structure. The frame in
74965  * which to
74966  *
74967  * receive data is updated in receive descriptor structure.
74968  *
74969  * Field Enumeration Values:
74970  *
74971  * Enum | Value | Description
74972  * :-------------------------------------|:------|:----------------------------
74973  * ALT_USB_DEV_DIEPCTL2_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
74974  * ALT_USB_DEV_DIEPCTL2_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
74975  *
74976  * Field Access Macros:
74977  *
74978  */
74979 /*
74980  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD0PID
74981  *
74982  * Disables Set DATA0 PID
74983  */
74984 #define ALT_USB_DEV_DIEPCTL2_SETD0PID_E_DISD 0x0
74985 /*
74986  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD0PID
74987  *
74988  * Endpoint Data PID to DATA0)
74989  */
74990 #define ALT_USB_DEV_DIEPCTL2_SETD0PID_E_END 0x1
74991 
74992 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */
74993 #define ALT_USB_DEV_DIEPCTL2_SETD0PID_LSB 28
74994 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */
74995 #define ALT_USB_DEV_DIEPCTL2_SETD0PID_MSB 28
74996 /* The width in bits of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */
74997 #define ALT_USB_DEV_DIEPCTL2_SETD0PID_WIDTH 1
74998 /* The mask used to set the ALT_USB_DEV_DIEPCTL2_SETD0PID register field value. */
74999 #define ALT_USB_DEV_DIEPCTL2_SETD0PID_SET_MSK 0x10000000
75000 /* The mask used to clear the ALT_USB_DEV_DIEPCTL2_SETD0PID register field value. */
75001 #define ALT_USB_DEV_DIEPCTL2_SETD0PID_CLR_MSK 0xefffffff
75002 /* The reset value of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */
75003 #define ALT_USB_DEV_DIEPCTL2_SETD0PID_RESET 0x0
75004 /* Extracts the ALT_USB_DEV_DIEPCTL2_SETD0PID field value from a register. */
75005 #define ALT_USB_DEV_DIEPCTL2_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
75006 /* Produces a ALT_USB_DEV_DIEPCTL2_SETD0PID register field value suitable for setting the register. */
75007 #define ALT_USB_DEV_DIEPCTL2_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
75008 
75009 /*
75010  * Field : setd1pid
75011  *
75012  * Set DATA1 PID (SetD1PID)
75013  *
75014  * Applies to interrupt/bulk IN and OUT endpoints only.
75015  *
75016  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
75017  * to DATA1.
75018  *
75019  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
75020  *
75021  * DMA mode.
75022  *
75023  * Set Odd (micro)frame (SetOddFr)
75024  *
75025  * Applies to isochronous IN and OUT endpoints only.
75026  *
75027  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
75028  *
75029  * (micro)frame.
75030  *
75031  * This field is not applicable for Scatter/Gather DMA mode.
75032  *
75033  * Field Enumeration Values:
75034  *
75035  * Enum | Value | Description
75036  * :-------------------------------------|:------|:-----------------------
75037  * ALT_USB_DEV_DIEPCTL2_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
75038  * ALT_USB_DEV_DIEPCTL2_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
75039  *
75040  * Field Access Macros:
75041  *
75042  */
75043 /*
75044  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD1PID
75045  *
75046  * Disables Set DATA1 PID
75047  */
75048 #define ALT_USB_DEV_DIEPCTL2_SETD1PID_E_DISD 0x0
75049 /*
75050  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD1PID
75051  *
75052  * Enables Set DATA1 PID
75053  */
75054 #define ALT_USB_DEV_DIEPCTL2_SETD1PID_E_END 0x1
75055 
75056 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */
75057 #define ALT_USB_DEV_DIEPCTL2_SETD1PID_LSB 29
75058 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */
75059 #define ALT_USB_DEV_DIEPCTL2_SETD1PID_MSB 29
75060 /* The width in bits of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */
75061 #define ALT_USB_DEV_DIEPCTL2_SETD1PID_WIDTH 1
75062 /* The mask used to set the ALT_USB_DEV_DIEPCTL2_SETD1PID register field value. */
75063 #define ALT_USB_DEV_DIEPCTL2_SETD1PID_SET_MSK 0x20000000
75064 /* The mask used to clear the ALT_USB_DEV_DIEPCTL2_SETD1PID register field value. */
75065 #define ALT_USB_DEV_DIEPCTL2_SETD1PID_CLR_MSK 0xdfffffff
75066 /* The reset value of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */
75067 #define ALT_USB_DEV_DIEPCTL2_SETD1PID_RESET 0x0
75068 /* Extracts the ALT_USB_DEV_DIEPCTL2_SETD1PID field value from a register. */
75069 #define ALT_USB_DEV_DIEPCTL2_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
75070 /* Produces a ALT_USB_DEV_DIEPCTL2_SETD1PID register field value suitable for setting the register. */
75071 #define ALT_USB_DEV_DIEPCTL2_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
75072 
75073 /*
75074  * Field : epdis
75075  *
75076  * Endpoint Disable (EPDis)
75077  *
75078  * Applies to IN and OUT endpoints.
75079  *
75080  * The application sets this bit to stop transmitting/receiving data on an
75081  * endpoint, even
75082  *
75083  * before the transfer for that endpoint is complete. The application must wait for
75084  * the
75085  *
75086  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
75087  * clears
75088  *
75089  * this bit before setting the Endpoint Disabled interrupt. The application must
75090  * set this bit
75091  *
75092  * only if Endpoint Enable is already set for this endpoint.
75093  *
75094  * Field Enumeration Values:
75095  *
75096  * Enum | Value | Description
75097  * :-----------------------------------|:------|:--------------------
75098  * ALT_USB_DEV_DIEPCTL2_EPDIS_E_INACT | 0x0 | No Endpoint Disable
75099  * ALT_USB_DEV_DIEPCTL2_EPDIS_E_ACT | 0x1 | Endpoint Disable
75100  *
75101  * Field Access Macros:
75102  *
75103  */
75104 /*
75105  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPDIS
75106  *
75107  * No Endpoint Disable
75108  */
75109 #define ALT_USB_DEV_DIEPCTL2_EPDIS_E_INACT 0x0
75110 /*
75111  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPDIS
75112  *
75113  * Endpoint Disable
75114  */
75115 #define ALT_USB_DEV_DIEPCTL2_EPDIS_E_ACT 0x1
75116 
75117 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */
75118 #define ALT_USB_DEV_DIEPCTL2_EPDIS_LSB 30
75119 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */
75120 #define ALT_USB_DEV_DIEPCTL2_EPDIS_MSB 30
75121 /* The width in bits of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */
75122 #define ALT_USB_DEV_DIEPCTL2_EPDIS_WIDTH 1
75123 /* The mask used to set the ALT_USB_DEV_DIEPCTL2_EPDIS register field value. */
75124 #define ALT_USB_DEV_DIEPCTL2_EPDIS_SET_MSK 0x40000000
75125 /* The mask used to clear the ALT_USB_DEV_DIEPCTL2_EPDIS register field value. */
75126 #define ALT_USB_DEV_DIEPCTL2_EPDIS_CLR_MSK 0xbfffffff
75127 /* The reset value of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */
75128 #define ALT_USB_DEV_DIEPCTL2_EPDIS_RESET 0x0
75129 /* Extracts the ALT_USB_DEV_DIEPCTL2_EPDIS field value from a register. */
75130 #define ALT_USB_DEV_DIEPCTL2_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
75131 /* Produces a ALT_USB_DEV_DIEPCTL2_EPDIS register field value suitable for setting the register. */
75132 #define ALT_USB_DEV_DIEPCTL2_EPDIS_SET(value) (((value) << 30) & 0x40000000)
75133 
75134 /*
75135  * Field : epena
75136  *
75137  * Endpoint Enable (EPEna)
75138  *
75139  * Applies to IN and OUT endpoints.
75140  *
75141  * When Scatter/Gather DMA mode is enabled,
75142  *
75143  * For IN endpoints this bit indicates that the descriptor structure and data
75144  * buffer with
75145  *
75146  * data ready to transmit is setup.
75147  *
75148  * For OUT endpoint it indicates that the descriptor structure and data buffer to
75149  *
75150  * receive data is setup.
75151  *
75152  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
75153  *
75154  * DMA mode:
75155  *
75156  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
75157  * the
75158  *
75159  * endpoint.
75160  *
75161  * * For OUT endpoints, this bit indicates that the application has allocated the
75162  *
75163  * memory to start receiving data from the USB.
75164  *
75165  * * The core clears this bit before setting any of the following interrupts on
75166  * this
75167  *
75168  * endpoint:
75169  *
75170  * SETUP Phase Done
75171  *
75172  * Endpoint Disabled
75173  *
75174  * Transfer Completed
75175  *
75176  * Note: For control endpoints in DMA mode, this bit must be set to be able to
75177  * transfer
75178  *
75179  * SETUP data packets in memory.
75180  *
75181  * Field Enumeration Values:
75182  *
75183  * Enum | Value | Description
75184  * :-----------------------------------|:------|:-------------------------
75185  * ALT_USB_DEV_DIEPCTL2_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
75186  * ALT_USB_DEV_DIEPCTL2_EPENA_E_ACT | 0x1 | Endpoint Enable active
75187  *
75188  * Field Access Macros:
75189  *
75190  */
75191 /*
75192  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPENA
75193  *
75194  * Endpoint Enable inactive
75195  */
75196 #define ALT_USB_DEV_DIEPCTL2_EPENA_E_INACT 0x0
75197 /*
75198  * Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPENA
75199  *
75200  * Endpoint Enable active
75201  */
75202 #define ALT_USB_DEV_DIEPCTL2_EPENA_E_ACT 0x1
75203 
75204 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */
75205 #define ALT_USB_DEV_DIEPCTL2_EPENA_LSB 31
75206 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */
75207 #define ALT_USB_DEV_DIEPCTL2_EPENA_MSB 31
75208 /* The width in bits of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */
75209 #define ALT_USB_DEV_DIEPCTL2_EPENA_WIDTH 1
75210 /* The mask used to set the ALT_USB_DEV_DIEPCTL2_EPENA register field value. */
75211 #define ALT_USB_DEV_DIEPCTL2_EPENA_SET_MSK 0x80000000
75212 /* The mask used to clear the ALT_USB_DEV_DIEPCTL2_EPENA register field value. */
75213 #define ALT_USB_DEV_DIEPCTL2_EPENA_CLR_MSK 0x7fffffff
75214 /* The reset value of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */
75215 #define ALT_USB_DEV_DIEPCTL2_EPENA_RESET 0x0
75216 /* Extracts the ALT_USB_DEV_DIEPCTL2_EPENA field value from a register. */
75217 #define ALT_USB_DEV_DIEPCTL2_EPENA_GET(value) (((value) & 0x80000000) >> 31)
75218 /* Produces a ALT_USB_DEV_DIEPCTL2_EPENA register field value suitable for setting the register. */
75219 #define ALT_USB_DEV_DIEPCTL2_EPENA_SET(value) (((value) << 31) & 0x80000000)
75220 
75221 #ifndef __ASSEMBLY__
75222 /*
75223  * WARNING: The C register and register group struct declarations are provided for
75224  * convenience and illustrative purposes. They should, however, be used with
75225  * caution as the C language standard provides no guarantees about the alignment or
75226  * atomicity of device memory accesses. The recommended practice for writing
75227  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
75228  * alt_write_word() functions.
75229  *
75230  * The struct declaration for register ALT_USB_DEV_DIEPCTL2.
75231  */
75232 struct ALT_USB_DEV_DIEPCTL2_s
75233 {
75234  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL2_MPS */
75235  uint32_t : 4; /* *UNDEFINED* */
75236  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL2_USBACTEP */
75237  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL2_DPID */
75238  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL2_NAKSTS */
75239  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL2_EPTYPE */
75240  uint32_t : 1; /* *UNDEFINED* */
75241  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL2_STALL */
75242  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL2_TXFNUM */
75243  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL2_CNAK */
75244  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL2_SNAK */
75245  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL2_SETD0PID */
75246  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL2_SETD1PID */
75247  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL2_EPDIS */
75248  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL2_EPENA */
75249 };
75250 
75251 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL2. */
75252 typedef volatile struct ALT_USB_DEV_DIEPCTL2_s ALT_USB_DEV_DIEPCTL2_t;
75253 #endif /* __ASSEMBLY__ */
75254 
75255 /* The reset value of the ALT_USB_DEV_DIEPCTL2 register. */
75256 #define ALT_USB_DEV_DIEPCTL2_RESET 0x00000000
75257 /* The byte offset of the ALT_USB_DEV_DIEPCTL2 register from the beginning of the component. */
75258 #define ALT_USB_DEV_DIEPCTL2_OFST 0x140
75259 /* The address of the ALT_USB_DEV_DIEPCTL2 register. */
75260 #define ALT_USB_DEV_DIEPCTL2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL2_OFST))
75261 
75262 /*
75263  * Register : diepint2
75264  *
75265  * Device IN Endpoint 2 Interrupt Register
75266  *
75267  * Register Layout
75268  *
75269  * Bits | Access | Reset | Description
75270  * :--------|:-------|:------|:---------------------------------
75271  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_XFERCOMPL
75272  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_EPDISBLD
75273  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_AHBERR
75274  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_TMO
75275  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_INTKNTXFEMP
75276  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_INTKNEPMIS
75277  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_INEPNAKEFF
75278  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT2_TXFEMP
75279  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN
75280  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_BNAINTR
75281  * [10] | ??? | 0x0 | *UNDEFINED*
75282  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_PKTDRPSTS
75283  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_BBLEERR
75284  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_NAKINTRPT
75285  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_NYETINTRPT
75286  * [31:15] | ??? | 0x0 | *UNDEFINED*
75287  *
75288  */
75289 /*
75290  * Field : xfercompl
75291  *
75292  * Transfer Completed Interrupt (XferCompl)
75293  *
75294  * Applies to IN and OUT endpoints.
75295  *
75296  * When Scatter/Gather DMA mode is enabled
75297  *
75298  * * For IN endpoint this field indicates that the requested data
75299  *
75300  * from the descriptor is moved from external system memory
75301  *
75302  * to internal FIFO.
75303  *
75304  * * For OUT endpoint this field indicates that the requested
75305  *
75306  * data from the internal FIFO is moved to external system
75307  *
75308  * memory. This interrupt is generated only when the
75309  *
75310  * corresponding endpoint descriptor is closed, and the IOC
75311  *
75312  * bit For the corresponding descriptor is Set.
75313  *
75314  * When Scatter/Gather DMA mode is disabled, this field
75315  *
75316  * indicates that the programmed transfer is complete on the
75317  *
75318  * AHB as well as on the USB, For this endpoint.
75319  *
75320  * Field Enumeration Values:
75321  *
75322  * Enum | Value | Description
75323  * :---------------------------------------|:------|:-----------------------------
75324  * ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_INACT | 0x0 | No Interrupt
75325  * ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
75326  *
75327  * Field Access Macros:
75328  *
75329  */
75330 /*
75331  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_XFERCOMPL
75332  *
75333  * No Interrupt
75334  */
75335 #define ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_INACT 0x0
75336 /*
75337  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_XFERCOMPL
75338  *
75339  * Transfer Completed Interrupt
75340  */
75341 #define ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_ACT 0x1
75342 
75343 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */
75344 #define ALT_USB_DEV_DIEPINT2_XFERCOMPL_LSB 0
75345 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */
75346 #define ALT_USB_DEV_DIEPINT2_XFERCOMPL_MSB 0
75347 /* The width in bits of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */
75348 #define ALT_USB_DEV_DIEPINT2_XFERCOMPL_WIDTH 1
75349 /* The mask used to set the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field value. */
75350 #define ALT_USB_DEV_DIEPINT2_XFERCOMPL_SET_MSK 0x00000001
75351 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field value. */
75352 #define ALT_USB_DEV_DIEPINT2_XFERCOMPL_CLR_MSK 0xfffffffe
75353 /* The reset value of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */
75354 #define ALT_USB_DEV_DIEPINT2_XFERCOMPL_RESET 0x0
75355 /* Extracts the ALT_USB_DEV_DIEPINT2_XFERCOMPL field value from a register. */
75356 #define ALT_USB_DEV_DIEPINT2_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
75357 /* Produces a ALT_USB_DEV_DIEPINT2_XFERCOMPL register field value suitable for setting the register. */
75358 #define ALT_USB_DEV_DIEPINT2_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
75359 
75360 /*
75361  * Field : epdisbld
75362  *
75363  * Endpoint Disabled Interrupt (EPDisbld)
75364  *
75365  * Applies to IN and OUT endpoints.
75366  *
75367  * This bit indicates that the endpoint is disabled per the
75368  *
75369  * application's request.
75370  *
75371  * Field Enumeration Values:
75372  *
75373  * Enum | Value | Description
75374  * :--------------------------------------|:------|:----------------------------
75375  * ALT_USB_DEV_DIEPINT2_EPDISBLD_E_INACT | 0x0 | No Interrupt
75376  * ALT_USB_DEV_DIEPINT2_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
75377  *
75378  * Field Access Macros:
75379  *
75380  */
75381 /*
75382  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_EPDISBLD
75383  *
75384  * No Interrupt
75385  */
75386 #define ALT_USB_DEV_DIEPINT2_EPDISBLD_E_INACT 0x0
75387 /*
75388  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_EPDISBLD
75389  *
75390  * Endpoint Disabled Interrupt
75391  */
75392 #define ALT_USB_DEV_DIEPINT2_EPDISBLD_E_ACT 0x1
75393 
75394 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */
75395 #define ALT_USB_DEV_DIEPINT2_EPDISBLD_LSB 1
75396 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */
75397 #define ALT_USB_DEV_DIEPINT2_EPDISBLD_MSB 1
75398 /* The width in bits of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */
75399 #define ALT_USB_DEV_DIEPINT2_EPDISBLD_WIDTH 1
75400 /* The mask used to set the ALT_USB_DEV_DIEPINT2_EPDISBLD register field value. */
75401 #define ALT_USB_DEV_DIEPINT2_EPDISBLD_SET_MSK 0x00000002
75402 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_EPDISBLD register field value. */
75403 #define ALT_USB_DEV_DIEPINT2_EPDISBLD_CLR_MSK 0xfffffffd
75404 /* The reset value of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */
75405 #define ALT_USB_DEV_DIEPINT2_EPDISBLD_RESET 0x0
75406 /* Extracts the ALT_USB_DEV_DIEPINT2_EPDISBLD field value from a register. */
75407 #define ALT_USB_DEV_DIEPINT2_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
75408 /* Produces a ALT_USB_DEV_DIEPINT2_EPDISBLD register field value suitable for setting the register. */
75409 #define ALT_USB_DEV_DIEPINT2_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
75410 
75411 /*
75412  * Field : ahberr
75413  *
75414  * AHB Error (AHBErr)
75415  *
75416  * Applies to IN and OUT endpoints.
75417  *
75418  * This is generated only in Internal DMA mode when there is an
75419  *
75420  * AHB error during an AHB read/write. The application can read
75421  *
75422  * the corresponding endpoint DMA address register to get the
75423  *
75424  * error address.
75425  *
75426  * Field Enumeration Values:
75427  *
75428  * Enum | Value | Description
75429  * :------------------------------------|:------|:--------------------
75430  * ALT_USB_DEV_DIEPINT2_AHBERR_E_INACT | 0x0 | No Interrupt
75431  * ALT_USB_DEV_DIEPINT2_AHBERR_E_ACT | 0x1 | AHB Error interrupt
75432  *
75433  * Field Access Macros:
75434  *
75435  */
75436 /*
75437  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_AHBERR
75438  *
75439  * No Interrupt
75440  */
75441 #define ALT_USB_DEV_DIEPINT2_AHBERR_E_INACT 0x0
75442 /*
75443  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_AHBERR
75444  *
75445  * AHB Error interrupt
75446  */
75447 #define ALT_USB_DEV_DIEPINT2_AHBERR_E_ACT 0x1
75448 
75449 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */
75450 #define ALT_USB_DEV_DIEPINT2_AHBERR_LSB 2
75451 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */
75452 #define ALT_USB_DEV_DIEPINT2_AHBERR_MSB 2
75453 /* The width in bits of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */
75454 #define ALT_USB_DEV_DIEPINT2_AHBERR_WIDTH 1
75455 /* The mask used to set the ALT_USB_DEV_DIEPINT2_AHBERR register field value. */
75456 #define ALT_USB_DEV_DIEPINT2_AHBERR_SET_MSK 0x00000004
75457 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_AHBERR register field value. */
75458 #define ALT_USB_DEV_DIEPINT2_AHBERR_CLR_MSK 0xfffffffb
75459 /* The reset value of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */
75460 #define ALT_USB_DEV_DIEPINT2_AHBERR_RESET 0x0
75461 /* Extracts the ALT_USB_DEV_DIEPINT2_AHBERR field value from a register. */
75462 #define ALT_USB_DEV_DIEPINT2_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
75463 /* Produces a ALT_USB_DEV_DIEPINT2_AHBERR register field value suitable for setting the register. */
75464 #define ALT_USB_DEV_DIEPINT2_AHBERR_SET(value) (((value) << 2) & 0x00000004)
75465 
75466 /*
75467  * Field : timeout
75468  *
75469  * Timeout Condition (TimeOUT)
75470  *
75471  * In shared TX FIFO mode, applies to non-isochronous IN
75472  *
75473  * endpoints only.
75474  *
75475  * In dedicated FIFO mode, applies only to Control IN
75476  *
75477  * endpoints.
75478  *
75479  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
75480  *
75481  * asserted.
75482  *
75483  * Indicates that the core has detected a timeout condition on the
75484  *
75485  * USB For the last IN token on this endpoint.
75486  *
75487  * Field Enumeration Values:
75488  *
75489  * Enum | Value | Description
75490  * :---------------------------------|:------|:------------------
75491  * ALT_USB_DEV_DIEPINT2_TMO_E_INACT | 0x0 | No interrupt
75492  * ALT_USB_DEV_DIEPINT2_TMO_E_ACT | 0x1 | Timeout interrupy
75493  *
75494  * Field Access Macros:
75495  *
75496  */
75497 /*
75498  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TMO
75499  *
75500  * No interrupt
75501  */
75502 #define ALT_USB_DEV_DIEPINT2_TMO_E_INACT 0x0
75503 /*
75504  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TMO
75505  *
75506  * Timeout interrupy
75507  */
75508 #define ALT_USB_DEV_DIEPINT2_TMO_E_ACT 0x1
75509 
75510 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_TMO register field. */
75511 #define ALT_USB_DEV_DIEPINT2_TMO_LSB 3
75512 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_TMO register field. */
75513 #define ALT_USB_DEV_DIEPINT2_TMO_MSB 3
75514 /* The width in bits of the ALT_USB_DEV_DIEPINT2_TMO register field. */
75515 #define ALT_USB_DEV_DIEPINT2_TMO_WIDTH 1
75516 /* The mask used to set the ALT_USB_DEV_DIEPINT2_TMO register field value. */
75517 #define ALT_USB_DEV_DIEPINT2_TMO_SET_MSK 0x00000008
75518 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_TMO register field value. */
75519 #define ALT_USB_DEV_DIEPINT2_TMO_CLR_MSK 0xfffffff7
75520 /* The reset value of the ALT_USB_DEV_DIEPINT2_TMO register field. */
75521 #define ALT_USB_DEV_DIEPINT2_TMO_RESET 0x0
75522 /* Extracts the ALT_USB_DEV_DIEPINT2_TMO field value from a register. */
75523 #define ALT_USB_DEV_DIEPINT2_TMO_GET(value) (((value) & 0x00000008) >> 3)
75524 /* Produces a ALT_USB_DEV_DIEPINT2_TMO register field value suitable for setting the register. */
75525 #define ALT_USB_DEV_DIEPINT2_TMO_SET(value) (((value) << 3) & 0x00000008)
75526 
75527 /*
75528  * Field : intkntxfemp
75529  *
75530  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
75531  *
75532  * Applies to non-periodic IN endpoints only.
75533  *
75534  * Indicates that an IN token was received when the associated
75535  *
75536  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
75537  *
75538  * asserted on the endpoint For which the IN token was received.
75539  *
75540  * Field Enumeration Values:
75541  *
75542  * Enum | Value | Description
75543  * :-----------------------------------------|:------|:----------------------------
75544  * ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
75545  * ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
75546  *
75547  * Field Access Macros:
75548  *
75549  */
75550 /*
75551  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNTXFEMP
75552  *
75553  * No interrupt
75554  */
75555 #define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_INACT 0x0
75556 /*
75557  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNTXFEMP
75558  *
75559  * IN Token Received Interrupt
75560  */
75561 #define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_ACT 0x1
75562 
75563 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */
75564 #define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_LSB 4
75565 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */
75566 #define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_MSB 4
75567 /* The width in bits of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */
75568 #define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_WIDTH 1
75569 /* The mask used to set the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field value. */
75570 #define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_SET_MSK 0x00000010
75571 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field value. */
75572 #define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_CLR_MSK 0xffffffef
75573 /* The reset value of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */
75574 #define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_RESET 0x0
75575 /* Extracts the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP field value from a register. */
75576 #define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
75577 /* Produces a ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field value suitable for setting the register. */
75578 #define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
75579 
75580 /*
75581  * Field : intknepmis
75582  *
75583  * IN Token Received with EP Mismatch (INTknEPMis)
75584  *
75585  * Applies to non-periodic IN endpoints only.
75586  *
75587  * Indicates that the data in the top of the non-periodic TxFIFO
75588  *
75589  * belongs to an endpoint other than the one For which the IN token
75590  *
75591  * was received. This interrupt is asserted on the endpoint For
75592  *
75593  * which the IN token was received.
75594  *
75595  * Field Enumeration Values:
75596  *
75597  * Enum | Value | Description
75598  * :----------------------------------------|:------|:---------------------------------------------
75599  * ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_INACT | 0x0 | No interrupt
75600  * ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
75601  *
75602  * Field Access Macros:
75603  *
75604  */
75605 /*
75606  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNEPMIS
75607  *
75608  * No interrupt
75609  */
75610 #define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_INACT 0x0
75611 /*
75612  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNEPMIS
75613  *
75614  * IN Token Received with EP Mismatch interrupt
75615  */
75616 #define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_ACT 0x1
75617 
75618 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */
75619 #define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_LSB 5
75620 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */
75621 #define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_MSB 5
75622 /* The width in bits of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */
75623 #define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_WIDTH 1
75624 /* The mask used to set the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field value. */
75625 #define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_SET_MSK 0x00000020
75626 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field value. */
75627 #define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_CLR_MSK 0xffffffdf
75628 /* The reset value of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */
75629 #define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_RESET 0x0
75630 /* Extracts the ALT_USB_DEV_DIEPINT2_INTKNEPMIS field value from a register. */
75631 #define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
75632 /* Produces a ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field value suitable for setting the register. */
75633 #define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
75634 
75635 /*
75636  * Field : inepnakeff
75637  *
75638  * IN Endpoint NAK Effective (INEPNakEff)
75639  *
75640  * Applies to periodic IN endpoints only.
75641  *
75642  * This bit can be cleared when the application clears the IN
75643  *
75644  * endpoint NAK by writing to DIEPCTLn.CNAK.
75645  *
75646  * This interrupt indicates that the core has sampled the NAK bit
75647  *
75648  * Set (either by the application or by the core). The interrupt
75649  *
75650  * indicates that the IN endpoint NAK bit Set by the application has
75651  *
75652  * taken effect in the core.
75653  *
75654  * This interrupt does not guarantee that a NAK handshake is sent
75655  *
75656  * on the USB. A STALL bit takes priority over a NAK bit.
75657  *
75658  * Field Enumeration Values:
75659  *
75660  * Enum | Value | Description
75661  * :----------------------------------------|:------|:------------------------------------
75662  * ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_INACT | 0x0 | No interrupt
75663  * ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
75664  *
75665  * Field Access Macros:
75666  *
75667  */
75668 /*
75669  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INEPNAKEFF
75670  *
75671  * No interrupt
75672  */
75673 #define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_INACT 0x0
75674 /*
75675  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_INEPNAKEFF
75676  *
75677  * IN Endpoint NAK Effective interrupt
75678  */
75679 #define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_ACT 0x1
75680 
75681 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */
75682 #define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_LSB 6
75683 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */
75684 #define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_MSB 6
75685 /* The width in bits of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */
75686 #define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_WIDTH 1
75687 /* The mask used to set the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field value. */
75688 #define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_SET_MSK 0x00000040
75689 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field value. */
75690 #define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_CLR_MSK 0xffffffbf
75691 /* The reset value of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */
75692 #define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_RESET 0x0
75693 /* Extracts the ALT_USB_DEV_DIEPINT2_INEPNAKEFF field value from a register. */
75694 #define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
75695 /* Produces a ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field value suitable for setting the register. */
75696 #define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
75697 
75698 /*
75699  * Field : txfemp
75700  *
75701  * Transmit FIFO Empty (TxFEmp)
75702  *
75703  * This bit is valid only For IN Endpoints
75704  *
75705  * This interrupt is asserted when the TxFIFO For this endpoint is
75706  *
75707  * either half or completely empty. The half or completely empty
75708  *
75709  * status is determined by the TxFIFO Empty Level bit in the Core
75710  *
75711  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
75712  *
75713  * Field Enumeration Values:
75714  *
75715  * Enum | Value | Description
75716  * :------------------------------------|:------|:------------------------------
75717  * ALT_USB_DEV_DIEPINT2_TXFEMP_E_INACT | 0x0 | No interrupt
75718  * ALT_USB_DEV_DIEPINT2_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
75719  *
75720  * Field Access Macros:
75721  *
75722  */
75723 /*
75724  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFEMP
75725  *
75726  * No interrupt
75727  */
75728 #define ALT_USB_DEV_DIEPINT2_TXFEMP_E_INACT 0x0
75729 /*
75730  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFEMP
75731  *
75732  * Transmit FIFO Empty interrupt
75733  */
75734 #define ALT_USB_DEV_DIEPINT2_TXFEMP_E_ACT 0x1
75735 
75736 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */
75737 #define ALT_USB_DEV_DIEPINT2_TXFEMP_LSB 7
75738 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */
75739 #define ALT_USB_DEV_DIEPINT2_TXFEMP_MSB 7
75740 /* The width in bits of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */
75741 #define ALT_USB_DEV_DIEPINT2_TXFEMP_WIDTH 1
75742 /* The mask used to set the ALT_USB_DEV_DIEPINT2_TXFEMP register field value. */
75743 #define ALT_USB_DEV_DIEPINT2_TXFEMP_SET_MSK 0x00000080
75744 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_TXFEMP register field value. */
75745 #define ALT_USB_DEV_DIEPINT2_TXFEMP_CLR_MSK 0xffffff7f
75746 /* The reset value of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */
75747 #define ALT_USB_DEV_DIEPINT2_TXFEMP_RESET 0x1
75748 /* Extracts the ALT_USB_DEV_DIEPINT2_TXFEMP field value from a register. */
75749 #define ALT_USB_DEV_DIEPINT2_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
75750 /* Produces a ALT_USB_DEV_DIEPINT2_TXFEMP register field value suitable for setting the register. */
75751 #define ALT_USB_DEV_DIEPINT2_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
75752 
75753 /*
75754  * Field : txfifoundrn
75755  *
75756  * Fifo Underrun (TxfifoUndrn)
75757  *
75758  * Applies to IN endpoints Only
75759  *
75760  * This bit is valid only If thresholding is enabled. The core generates this
75761  * interrupt when
75762  *
75763  * it detects a transmit FIFO underrun condition For this endpoint.
75764  *
75765  * Field Enumeration Values:
75766  *
75767  * Enum | Value | Description
75768  * :-----------------------------------------|:------|:------------------------
75769  * ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
75770  * ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
75771  *
75772  * Field Access Macros:
75773  *
75774  */
75775 /*
75776  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN
75777  *
75778  * No interrupt
75779  */
75780 #define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_INACT 0x0
75781 /*
75782  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN
75783  *
75784  * Fifo Underrun interrupt
75785  */
75786 #define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_ACT 0x1
75787 
75788 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */
75789 #define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_LSB 8
75790 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */
75791 #define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_MSB 8
75792 /* The width in bits of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */
75793 #define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_WIDTH 1
75794 /* The mask used to set the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field value. */
75795 #define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_SET_MSK 0x00000100
75796 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field value. */
75797 #define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_CLR_MSK 0xfffffeff
75798 /* The reset value of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */
75799 #define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_RESET 0x0
75800 /* Extracts the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN field value from a register. */
75801 #define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
75802 /* Produces a ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field value suitable for setting the register. */
75803 #define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
75804 
75805 /*
75806  * Field : bnaintr
75807  *
75808  * BNA (Buffer Not Available) Interrupt (BNAIntr)
75809  *
75810  * This bit is valid only when Scatter/Gather DMA mode is enabled.
75811  *
75812  * The core generates this interrupt when the descriptor accessed
75813  *
75814  * is not ready For the Core to process, such as Host busy or DMA
75815  *
75816  * done
75817  *
75818  * Field Enumeration Values:
75819  *
75820  * Enum | Value | Description
75821  * :-------------------------------------|:------|:--------------
75822  * ALT_USB_DEV_DIEPINT2_BNAINTR_E_INACT | 0x0 | No interrupt
75823  * ALT_USB_DEV_DIEPINT2_BNAINTR_E_ACT | 0x1 | BNA interrupt
75824  *
75825  * Field Access Macros:
75826  *
75827  */
75828 /*
75829  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_BNAINTR
75830  *
75831  * No interrupt
75832  */
75833 #define ALT_USB_DEV_DIEPINT2_BNAINTR_E_INACT 0x0
75834 /*
75835  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_BNAINTR
75836  *
75837  * BNA interrupt
75838  */
75839 #define ALT_USB_DEV_DIEPINT2_BNAINTR_E_ACT 0x1
75840 
75841 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */
75842 #define ALT_USB_DEV_DIEPINT2_BNAINTR_LSB 9
75843 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */
75844 #define ALT_USB_DEV_DIEPINT2_BNAINTR_MSB 9
75845 /* The width in bits of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */
75846 #define ALT_USB_DEV_DIEPINT2_BNAINTR_WIDTH 1
75847 /* The mask used to set the ALT_USB_DEV_DIEPINT2_BNAINTR register field value. */
75848 #define ALT_USB_DEV_DIEPINT2_BNAINTR_SET_MSK 0x00000200
75849 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_BNAINTR register field value. */
75850 #define ALT_USB_DEV_DIEPINT2_BNAINTR_CLR_MSK 0xfffffdff
75851 /* The reset value of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */
75852 #define ALT_USB_DEV_DIEPINT2_BNAINTR_RESET 0x0
75853 /* Extracts the ALT_USB_DEV_DIEPINT2_BNAINTR field value from a register. */
75854 #define ALT_USB_DEV_DIEPINT2_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
75855 /* Produces a ALT_USB_DEV_DIEPINT2_BNAINTR register field value suitable for setting the register. */
75856 #define ALT_USB_DEV_DIEPINT2_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
75857 
75858 /*
75859  * Field : pktdrpsts
75860  *
75861  * Packet Drop Status (PktDrpSts)
75862  *
75863  * This bit indicates to the application that an ISOC OUT packet has been dropped.
75864  * This
75865  *
75866  * bit does not have an associated mask bit and does not generate an interrupt.
75867  *
75868  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
75869  * transfer
75870  *
75871  * interrupt feature is selected.
75872  *
75873  * Field Enumeration Values:
75874  *
75875  * Enum | Value | Description
75876  * :---------------------------------------|:------|:-----------------------------
75877  * ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_INACT | 0x0 | No interrupt
75878  * ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
75879  *
75880  * Field Access Macros:
75881  *
75882  */
75883 /*
75884  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_PKTDRPSTS
75885  *
75886  * No interrupt
75887  */
75888 #define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_INACT 0x0
75889 /*
75890  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_PKTDRPSTS
75891  *
75892  * Packet Drop Status interrupt
75893  */
75894 #define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_ACT 0x1
75895 
75896 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */
75897 #define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_LSB 11
75898 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */
75899 #define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_MSB 11
75900 /* The width in bits of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */
75901 #define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_WIDTH 1
75902 /* The mask used to set the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field value. */
75903 #define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_SET_MSK 0x00000800
75904 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field value. */
75905 #define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_CLR_MSK 0xfffff7ff
75906 /* The reset value of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */
75907 #define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_RESET 0x0
75908 /* Extracts the ALT_USB_DEV_DIEPINT2_PKTDRPSTS field value from a register. */
75909 #define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
75910 /* Produces a ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field value suitable for setting the register. */
75911 #define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
75912 
75913 /*
75914  * Field : bbleerr
75915  *
75916  * NAK Interrupt (BbleErr)
75917  *
75918  * The core generates this interrupt when babble is received for the endpoint.
75919  *
75920  * Field Enumeration Values:
75921  *
75922  * Enum | Value | Description
75923  * :-------------------------------------|:------|:------------------
75924  * ALT_USB_DEV_DIEPINT2_BBLEERR_E_INACT | 0x0 | No interrupt
75925  * ALT_USB_DEV_DIEPINT2_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
75926  *
75927  * Field Access Macros:
75928  *
75929  */
75930 /*
75931  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_BBLEERR
75932  *
75933  * No interrupt
75934  */
75935 #define ALT_USB_DEV_DIEPINT2_BBLEERR_E_INACT 0x0
75936 /*
75937  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_BBLEERR
75938  *
75939  * BbleErr interrupt
75940  */
75941 #define ALT_USB_DEV_DIEPINT2_BBLEERR_E_ACT 0x1
75942 
75943 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */
75944 #define ALT_USB_DEV_DIEPINT2_BBLEERR_LSB 12
75945 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */
75946 #define ALT_USB_DEV_DIEPINT2_BBLEERR_MSB 12
75947 /* The width in bits of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */
75948 #define ALT_USB_DEV_DIEPINT2_BBLEERR_WIDTH 1
75949 /* The mask used to set the ALT_USB_DEV_DIEPINT2_BBLEERR register field value. */
75950 #define ALT_USB_DEV_DIEPINT2_BBLEERR_SET_MSK 0x00001000
75951 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_BBLEERR register field value. */
75952 #define ALT_USB_DEV_DIEPINT2_BBLEERR_CLR_MSK 0xffffefff
75953 /* The reset value of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */
75954 #define ALT_USB_DEV_DIEPINT2_BBLEERR_RESET 0x0
75955 /* Extracts the ALT_USB_DEV_DIEPINT2_BBLEERR field value from a register. */
75956 #define ALT_USB_DEV_DIEPINT2_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
75957 /* Produces a ALT_USB_DEV_DIEPINT2_BBLEERR register field value suitable for setting the register. */
75958 #define ALT_USB_DEV_DIEPINT2_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
75959 
75960 /*
75961  * Field : nakintrpt
75962  *
75963  * NAK Interrupt (NAKInterrupt)
75964  *
75965  * The core generates this interrupt when a NAK is transmitted or received by the
75966  * device.
75967  *
75968  * In case of isochronous IN endpoints the interrupt gets generated when a zero
75969  * length
75970  *
75971  * packet is transmitted due to un-availability of data in the TXFifo.
75972  *
75973  * Field Enumeration Values:
75974  *
75975  * Enum | Value | Description
75976  * :---------------------------------------|:------|:--------------
75977  * ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_INACT | 0x0 | No interrupt
75978  * ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
75979  *
75980  * Field Access Macros:
75981  *
75982  */
75983 /*
75984  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_NAKINTRPT
75985  *
75986  * No interrupt
75987  */
75988 #define ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_INACT 0x0
75989 /*
75990  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_NAKINTRPT
75991  *
75992  * NAK Interrupt
75993  */
75994 #define ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_ACT 0x1
75995 
75996 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */
75997 #define ALT_USB_DEV_DIEPINT2_NAKINTRPT_LSB 13
75998 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */
75999 #define ALT_USB_DEV_DIEPINT2_NAKINTRPT_MSB 13
76000 /* The width in bits of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */
76001 #define ALT_USB_DEV_DIEPINT2_NAKINTRPT_WIDTH 1
76002 /* The mask used to set the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field value. */
76003 #define ALT_USB_DEV_DIEPINT2_NAKINTRPT_SET_MSK 0x00002000
76004 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field value. */
76005 #define ALT_USB_DEV_DIEPINT2_NAKINTRPT_CLR_MSK 0xffffdfff
76006 /* The reset value of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */
76007 #define ALT_USB_DEV_DIEPINT2_NAKINTRPT_RESET 0x0
76008 /* Extracts the ALT_USB_DEV_DIEPINT2_NAKINTRPT field value from a register. */
76009 #define ALT_USB_DEV_DIEPINT2_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
76010 /* Produces a ALT_USB_DEV_DIEPINT2_NAKINTRPT register field value suitable for setting the register. */
76011 #define ALT_USB_DEV_DIEPINT2_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
76012 
76013 /*
76014  * Field : nyetintrpt
76015  *
76016  * NYET Interrupt (NYETIntrpt)
76017  *
76018  * The core generates this interrupt when a NYET response is transmitted for a non
76019  * isochronous OUT endpoint.
76020  *
76021  * Field Enumeration Values:
76022  *
76023  * Enum | Value | Description
76024  * :----------------------------------------|:------|:---------------
76025  * ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_INACT | 0x0 | No interrupt
76026  * ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
76027  *
76028  * Field Access Macros:
76029  *
76030  */
76031 /*
76032  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_NYETINTRPT
76033  *
76034  * No interrupt
76035  */
76036 #define ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_INACT 0x0
76037 /*
76038  * Enumerated value for register field ALT_USB_DEV_DIEPINT2_NYETINTRPT
76039  *
76040  * NYET Interrupt
76041  */
76042 #define ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_ACT 0x1
76043 
76044 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */
76045 #define ALT_USB_DEV_DIEPINT2_NYETINTRPT_LSB 14
76046 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */
76047 #define ALT_USB_DEV_DIEPINT2_NYETINTRPT_MSB 14
76048 /* The width in bits of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */
76049 #define ALT_USB_DEV_DIEPINT2_NYETINTRPT_WIDTH 1
76050 /* The mask used to set the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field value. */
76051 #define ALT_USB_DEV_DIEPINT2_NYETINTRPT_SET_MSK 0x00004000
76052 /* The mask used to clear the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field value. */
76053 #define ALT_USB_DEV_DIEPINT2_NYETINTRPT_CLR_MSK 0xffffbfff
76054 /* The reset value of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */
76055 #define ALT_USB_DEV_DIEPINT2_NYETINTRPT_RESET 0x0
76056 /* Extracts the ALT_USB_DEV_DIEPINT2_NYETINTRPT field value from a register. */
76057 #define ALT_USB_DEV_DIEPINT2_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
76058 /* Produces a ALT_USB_DEV_DIEPINT2_NYETINTRPT register field value suitable for setting the register. */
76059 #define ALT_USB_DEV_DIEPINT2_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
76060 
76061 #ifndef __ASSEMBLY__
76062 /*
76063  * WARNING: The C register and register group struct declarations are provided for
76064  * convenience and illustrative purposes. They should, however, be used with
76065  * caution as the C language standard provides no guarantees about the alignment or
76066  * atomicity of device memory accesses. The recommended practice for writing
76067  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
76068  * alt_write_word() functions.
76069  *
76070  * The struct declaration for register ALT_USB_DEV_DIEPINT2.
76071  */
76072 struct ALT_USB_DEV_DIEPINT2_s
76073 {
76074  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT2_XFERCOMPL */
76075  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT2_EPDISBLD */
76076  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT2_AHBERR */
76077  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT2_TMO */
76078  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT2_INTKNTXFEMP */
76079  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT2_INTKNEPMIS */
76080  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT2_INEPNAKEFF */
76081  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT2_TXFEMP */
76082  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN */
76083  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT2_BNAINTR */
76084  uint32_t : 1; /* *UNDEFINED* */
76085  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT2_PKTDRPSTS */
76086  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT2_BBLEERR */
76087  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT2_NAKINTRPT */
76088  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT2_NYETINTRPT */
76089  uint32_t : 17; /* *UNDEFINED* */
76090 };
76091 
76092 /* The typedef declaration for register ALT_USB_DEV_DIEPINT2. */
76093 typedef volatile struct ALT_USB_DEV_DIEPINT2_s ALT_USB_DEV_DIEPINT2_t;
76094 #endif /* __ASSEMBLY__ */
76095 
76096 /* The reset value of the ALT_USB_DEV_DIEPINT2 register. */
76097 #define ALT_USB_DEV_DIEPINT2_RESET 0x00000080
76098 /* The byte offset of the ALT_USB_DEV_DIEPINT2 register from the beginning of the component. */
76099 #define ALT_USB_DEV_DIEPINT2_OFST 0x148
76100 /* The address of the ALT_USB_DEV_DIEPINT2 register. */
76101 #define ALT_USB_DEV_DIEPINT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT2_OFST))
76102 
76103 /*
76104  * Register : dieptsiz2
76105  *
76106  * Device IN Endpoint 2 Transfer Size Register
76107  *
76108  * Register Layout
76109  *
76110  * Bits | Access | Reset | Description
76111  * :--------|:-------|:------|:-------------------------------
76112  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ2_XFERSIZE
76113  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ2_PKTCNT
76114  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ2_MC
76115  * [31] | ??? | 0x0 | *UNDEFINED*
76116  *
76117  */
76118 /*
76119  * Field : xfersize
76120  *
76121  * Transfer Size (XferSize)
76122  *
76123  * Indicates the transfer size in bytes For endpoint 0. The core
76124  *
76125  * interrupts the application only after it has exhausted the transfer
76126  *
76127  * size amount of data. The transfer size can be Set to the
76128  *
76129  * maximum packet size of the endpoint, to be interrupted at the
76130  *
76131  * end of each packet.
76132  *
76133  * The core decrements this field every time a packet from the
76134  *
76135  * external memory is written to the TxFIFO.
76136  *
76137  * Field Access Macros:
76138  *
76139  */
76140 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */
76141 #define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_LSB 0
76142 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */
76143 #define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_MSB 18
76144 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */
76145 #define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_WIDTH 19
76146 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field value. */
76147 #define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_SET_MSK 0x0007ffff
76148 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field value. */
76149 #define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_CLR_MSK 0xfff80000
76150 /* The reset value of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */
76151 #define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_RESET 0x0
76152 /* Extracts the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE field value from a register. */
76153 #define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
76154 /* Produces a ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field value suitable for setting the register. */
76155 #define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
76156 
76157 /*
76158  * Field : pktcnt
76159  *
76160  * Packet Count (PktCnt)
76161  *
76162  * Indicates the total number of USB packets that constitute the
76163  *
76164  * Transfer Size amount of data For endpoint 0.
76165  *
76166  * This field is decremented every time a packet (maximum size or
76167  *
76168  * short packet) is read from the TxFIFO.
76169  *
76170  * Field Access Macros:
76171  *
76172  */
76173 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */
76174 #define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_LSB 19
76175 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */
76176 #define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_MSB 28
76177 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */
76178 #define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_WIDTH 10
76179 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field value. */
76180 #define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_SET_MSK 0x1ff80000
76181 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field value. */
76182 #define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_CLR_MSK 0xe007ffff
76183 /* The reset value of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */
76184 #define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_RESET 0x0
76185 /* Extracts the ALT_USB_DEV_DIEPTSIZ2_PKTCNT field value from a register. */
76186 #define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
76187 /* Produces a ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field value suitable for setting the register. */
76188 #define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
76189 
76190 /*
76191  * Field : mc
76192  *
76193  * Applies to IN endpoints only.
76194  *
76195  * For periodic IN endpoints, this field indicates the number of packets that must
76196  * be transmitted per microframe on the USB. The core uses this field to calculate
76197  * the data PID for isochronous IN endpoints.
76198  *
76199  * 2'b01: 1 packet
76200  *
76201  * 2'b10: 2 packets
76202  *
76203  * 2'b11: 3 packets
76204  *
76205  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
76206  * specifies the number of packets the core must fetchfor an IN endpoint before it
76207  * switches to the endpoint pointed to by the Next Endpoint field of the Device
76208  * Endpoint-n Control register (DIEPCTLn.NextEp)
76209  *
76210  * Field Enumeration Values:
76211  *
76212  * Enum | Value | Description
76213  * :------------------------------------|:------|:------------
76214  * ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTONE | 0x1 | 1 packet
76215  * ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTWO | 0x2 | 2 packets
76216  * ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTHREE | 0x3 | 3 packets
76217  *
76218  * Field Access Macros:
76219  *
76220  */
76221 /*
76222  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ2_MC
76223  *
76224  * 1 packet
76225  */
76226 #define ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTONE 0x1
76227 /*
76228  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ2_MC
76229  *
76230  * 2 packets
76231  */
76232 #define ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTWO 0x2
76233 /*
76234  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ2_MC
76235  *
76236  * 3 packets
76237  */
76238 #define ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTHREE 0x3
76239 
76240 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */
76241 #define ALT_USB_DEV_DIEPTSIZ2_MC_LSB 29
76242 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */
76243 #define ALT_USB_DEV_DIEPTSIZ2_MC_MSB 30
76244 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */
76245 #define ALT_USB_DEV_DIEPTSIZ2_MC_WIDTH 2
76246 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ2_MC register field value. */
76247 #define ALT_USB_DEV_DIEPTSIZ2_MC_SET_MSK 0x60000000
76248 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ2_MC register field value. */
76249 #define ALT_USB_DEV_DIEPTSIZ2_MC_CLR_MSK 0x9fffffff
76250 /* The reset value of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */
76251 #define ALT_USB_DEV_DIEPTSIZ2_MC_RESET 0x0
76252 /* Extracts the ALT_USB_DEV_DIEPTSIZ2_MC field value from a register. */
76253 #define ALT_USB_DEV_DIEPTSIZ2_MC_GET(value) (((value) & 0x60000000) >> 29)
76254 /* Produces a ALT_USB_DEV_DIEPTSIZ2_MC register field value suitable for setting the register. */
76255 #define ALT_USB_DEV_DIEPTSIZ2_MC_SET(value) (((value) << 29) & 0x60000000)
76256 
76257 #ifndef __ASSEMBLY__
76258 /*
76259  * WARNING: The C register and register group struct declarations are provided for
76260  * convenience and illustrative purposes. They should, however, be used with
76261  * caution as the C language standard provides no guarantees about the alignment or
76262  * atomicity of device memory accesses. The recommended practice for writing
76263  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
76264  * alt_write_word() functions.
76265  *
76266  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ2.
76267  */
76268 struct ALT_USB_DEV_DIEPTSIZ2_s
76269 {
76270  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ2_XFERSIZE */
76271  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ2_PKTCNT */
76272  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ2_MC */
76273  uint32_t : 1; /* *UNDEFINED* */
76274 };
76275 
76276 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ2. */
76277 typedef volatile struct ALT_USB_DEV_DIEPTSIZ2_s ALT_USB_DEV_DIEPTSIZ2_t;
76278 #endif /* __ASSEMBLY__ */
76279 
76280 /* The reset value of the ALT_USB_DEV_DIEPTSIZ2 register. */
76281 #define ALT_USB_DEV_DIEPTSIZ2_RESET 0x00000000
76282 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ2 register from the beginning of the component. */
76283 #define ALT_USB_DEV_DIEPTSIZ2_OFST 0x150
76284 /* The address of the ALT_USB_DEV_DIEPTSIZ2 register. */
76285 #define ALT_USB_DEV_DIEPTSIZ2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ2_OFST))
76286 
76287 /*
76288  * Register : diepdma2
76289  *
76290  * Device IN Endpoint 2 DMA Address Register
76291  *
76292  * Register Layout
76293  *
76294  * Bits | Access | Reset | Description
76295  * :-------|:-------|:--------|:------------------------------
76296  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA2_DIEPDMA2
76297  *
76298  */
76299 /*
76300  * Field : diepdma2
76301  *
76302  * Holds the start address of the external memory for storing or fetching endpoint
76303  *
76304  * data.
76305  *
76306  * Note: For control endpoints, this field stores control OUT data packets as well
76307  * as
76308  *
76309  * SETUP transaction data packets. When more than three SETUP packets are
76310  *
76311  * received back-to-back, the SETUP data packet in the memory is overwritten.
76312  *
76313  * This register is incremented on every AHB transaction. The application can give
76314  *
76315  * only a DWORD-aligned address.
76316  *
76317  * When Scatter/Gather DMA mode is not enabled, the application programs the
76318  *
76319  * start address value in this field.
76320  *
76321  * When Scatter/Gather DMA mode is enabled, this field indicates the base
76322  *
76323  * pointer for the descriptor list.
76324  *
76325  * Field Access Macros:
76326  *
76327  */
76328 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field. */
76329 #define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_LSB 0
76330 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field. */
76331 #define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_MSB 31
76332 /* The width in bits of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field. */
76333 #define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_WIDTH 32
76334 /* The mask used to set the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field value. */
76335 #define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_SET_MSK 0xffffffff
76336 /* The mask used to clear the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field value. */
76337 #define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_CLR_MSK 0x00000000
76338 /* The reset value of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field is UNKNOWN. */
76339 #define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_RESET 0x0
76340 /* Extracts the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 field value from a register. */
76341 #define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_GET(value) (((value) & 0xffffffff) >> 0)
76342 /* Produces a ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field value suitable for setting the register. */
76343 #define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_SET(value) (((value) << 0) & 0xffffffff)
76344 
76345 #ifndef __ASSEMBLY__
76346 /*
76347  * WARNING: The C register and register group struct declarations are provided for
76348  * convenience and illustrative purposes. They should, however, be used with
76349  * caution as the C language standard provides no guarantees about the alignment or
76350  * atomicity of device memory accesses. The recommended practice for writing
76351  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
76352  * alt_write_word() functions.
76353  *
76354  * The struct declaration for register ALT_USB_DEV_DIEPDMA2.
76355  */
76356 struct ALT_USB_DEV_DIEPDMA2_s
76357 {
76358  uint32_t diepdma2 : 32; /* ALT_USB_DEV_DIEPDMA2_DIEPDMA2 */
76359 };
76360 
76361 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA2. */
76362 typedef volatile struct ALT_USB_DEV_DIEPDMA2_s ALT_USB_DEV_DIEPDMA2_t;
76363 #endif /* __ASSEMBLY__ */
76364 
76365 /* The reset value of the ALT_USB_DEV_DIEPDMA2 register. */
76366 #define ALT_USB_DEV_DIEPDMA2_RESET 0x00000000
76367 /* The byte offset of the ALT_USB_DEV_DIEPDMA2 register from the beginning of the component. */
76368 #define ALT_USB_DEV_DIEPDMA2_OFST 0x154
76369 /* The address of the ALT_USB_DEV_DIEPDMA2 register. */
76370 #define ALT_USB_DEV_DIEPDMA2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA2_OFST))
76371 
76372 /*
76373  * Register : dtxfsts2
76374  *
76375  * Device IN Endpoint Transmit FIFO Status Register 2
76376  *
76377  * Register Layout
76378  *
76379  * Bits | Access | Reset | Description
76380  * :--------|:-------|:-------|:-------------------------------------
76381  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL
76382  * [31:16] | ??? | 0x0 | *UNDEFINED*
76383  *
76384  */
76385 /*
76386  * Field : ineptxfspcavail
76387  *
76388  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
76389  *
76390  * Indicates the amount of free space available in the Endpoint
76391  *
76392  * TxFIFO.
76393  *
76394  * Values are in terms of 32-bit words.
76395  *
76396  * 16'h0: Endpoint TxFIFO is full
76397  *
76398  * 16'h1: 1 word available
76399  *
76400  * 16'h2: 2 words available
76401  *
76402  * 16'hn: n words available (where 0 n 32,768)
76403  *
76404  * 16'h8000: 32,768 words available
76405  *
76406  * Others: Reserved
76407  *
76408  * Field Access Macros:
76409  *
76410  */
76411 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */
76412 #define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_LSB 0
76413 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */
76414 #define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_MSB 15
76415 /* The width in bits of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */
76416 #define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_WIDTH 16
76417 /* The mask used to set the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field value. */
76418 #define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
76419 /* The mask used to clear the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field value. */
76420 #define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
76421 /* The reset value of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */
76422 #define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_RESET 0x2000
76423 /* Extracts the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL field value from a register. */
76424 #define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
76425 /* Produces a ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field value suitable for setting the register. */
76426 #define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
76427 
76428 #ifndef __ASSEMBLY__
76429 /*
76430  * WARNING: The C register and register group struct declarations are provided for
76431  * convenience and illustrative purposes. They should, however, be used with
76432  * caution as the C language standard provides no guarantees about the alignment or
76433  * atomicity of device memory accesses. The recommended practice for writing
76434  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
76435  * alt_write_word() functions.
76436  *
76437  * The struct declaration for register ALT_USB_DEV_DTXFSTS2.
76438  */
76439 struct ALT_USB_DEV_DTXFSTS2_s
76440 {
76441  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL */
76442  uint32_t : 16; /* *UNDEFINED* */
76443 };
76444 
76445 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS2. */
76446 typedef volatile struct ALT_USB_DEV_DTXFSTS2_s ALT_USB_DEV_DTXFSTS2_t;
76447 #endif /* __ASSEMBLY__ */
76448 
76449 /* The reset value of the ALT_USB_DEV_DTXFSTS2 register. */
76450 #define ALT_USB_DEV_DTXFSTS2_RESET 0x00002000
76451 /* The byte offset of the ALT_USB_DEV_DTXFSTS2 register from the beginning of the component. */
76452 #define ALT_USB_DEV_DTXFSTS2_OFST 0x158
76453 /* The address of the ALT_USB_DEV_DTXFSTS2 register. */
76454 #define ALT_USB_DEV_DTXFSTS2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS2_OFST))
76455 
76456 /*
76457  * Register : diepdmab2
76458  *
76459  * Device IN Endpoint 2 Buffer Address Register
76460  *
76461  * Register Layout
76462  *
76463  * Bits | Access | Reset | Description
76464  * :-------|:-------|:--------|:--------------------------------
76465  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2
76466  *
76467  */
76468 /*
76469  * Field : diepdmab2
76470  *
76471  * Holds the current buffer address.This register is updated as and when the data
76472  *
76473  * transfer for the corresponding end point is in progress.
76474  *
76475  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
76476  * is
76477  *
76478  * reserved.
76479  *
76480  * Field Access Macros:
76481  *
76482  */
76483 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field. */
76484 #define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_LSB 0
76485 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field. */
76486 #define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_MSB 31
76487 /* The width in bits of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field. */
76488 #define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_WIDTH 32
76489 /* The mask used to set the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field value. */
76490 #define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_SET_MSK 0xffffffff
76491 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field value. */
76492 #define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_CLR_MSK 0x00000000
76493 /* The reset value of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field is UNKNOWN. */
76494 #define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_RESET 0x0
76495 /* Extracts the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 field value from a register. */
76496 #define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_GET(value) (((value) & 0xffffffff) >> 0)
76497 /* Produces a ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field value suitable for setting the register. */
76498 #define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_SET(value) (((value) << 0) & 0xffffffff)
76499 
76500 #ifndef __ASSEMBLY__
76501 /*
76502  * WARNING: The C register and register group struct declarations are provided for
76503  * convenience and illustrative purposes. They should, however, be used with
76504  * caution as the C language standard provides no guarantees about the alignment or
76505  * atomicity of device memory accesses. The recommended practice for writing
76506  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
76507  * alt_write_word() functions.
76508  *
76509  * The struct declaration for register ALT_USB_DEV_DIEPDMAB2.
76510  */
76511 struct ALT_USB_DEV_DIEPDMAB2_s
76512 {
76513  const uint32_t diepdmab2 : 32; /* ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 */
76514 };
76515 
76516 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB2. */
76517 typedef volatile struct ALT_USB_DEV_DIEPDMAB2_s ALT_USB_DEV_DIEPDMAB2_t;
76518 #endif /* __ASSEMBLY__ */
76519 
76520 /* The reset value of the ALT_USB_DEV_DIEPDMAB2 register. */
76521 #define ALT_USB_DEV_DIEPDMAB2_RESET 0x00000000
76522 /* The byte offset of the ALT_USB_DEV_DIEPDMAB2 register from the beginning of the component. */
76523 #define ALT_USB_DEV_DIEPDMAB2_OFST 0x15c
76524 /* The address of the ALT_USB_DEV_DIEPDMAB2 register. */
76525 #define ALT_USB_DEV_DIEPDMAB2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB2_OFST))
76526 
76527 /*
76528  * Register : diepctl3
76529  *
76530  * Device Control IN Endpoint 3 Control Register
76531  *
76532  * Register Layout
76533  *
76534  * Bits | Access | Reset | Description
76535  * :--------|:---------|:------|:------------------------------
76536  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL3_MPS
76537  * [14:11] | ??? | 0x0 | *UNDEFINED*
76538  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL3_USBACTEP
76539  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL3_DPID
76540  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL3_NAKSTS
76541  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL3_EPTYPE
76542  * [20] | ??? | 0x0 | *UNDEFINED*
76543  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL3_STALL
76544  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL3_TXFNUM
76545  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL3_CNAK
76546  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL3_SNAK
76547  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL3_SETD0PID
76548  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL3_SETD1PID
76549  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL3_EPDIS
76550  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL3_EPENA
76551  *
76552  */
76553 /*
76554  * Field : mps
76555  *
76556  * Maximum Packet Size (MPS)
76557  *
76558  * The application must program this field with the maximum packet size for the
76559  * current
76560  *
76561  * logical endpoint. This value is in bytes.
76562  *
76563  * Field Access Macros:
76564  *
76565  */
76566 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_MPS register field. */
76567 #define ALT_USB_DEV_DIEPCTL3_MPS_LSB 0
76568 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_MPS register field. */
76569 #define ALT_USB_DEV_DIEPCTL3_MPS_MSB 10
76570 /* The width in bits of the ALT_USB_DEV_DIEPCTL3_MPS register field. */
76571 #define ALT_USB_DEV_DIEPCTL3_MPS_WIDTH 11
76572 /* The mask used to set the ALT_USB_DEV_DIEPCTL3_MPS register field value. */
76573 #define ALT_USB_DEV_DIEPCTL3_MPS_SET_MSK 0x000007ff
76574 /* The mask used to clear the ALT_USB_DEV_DIEPCTL3_MPS register field value. */
76575 #define ALT_USB_DEV_DIEPCTL3_MPS_CLR_MSK 0xfffff800
76576 /* The reset value of the ALT_USB_DEV_DIEPCTL3_MPS register field. */
76577 #define ALT_USB_DEV_DIEPCTL3_MPS_RESET 0x0
76578 /* Extracts the ALT_USB_DEV_DIEPCTL3_MPS field value from a register. */
76579 #define ALT_USB_DEV_DIEPCTL3_MPS_GET(value) (((value) & 0x000007ff) >> 0)
76580 /* Produces a ALT_USB_DEV_DIEPCTL3_MPS register field value suitable for setting the register. */
76581 #define ALT_USB_DEV_DIEPCTL3_MPS_SET(value) (((value) << 0) & 0x000007ff)
76582 
76583 /*
76584  * Field : usbactep
76585  *
76586  * USB Active Endpoint (USBActEP)
76587  *
76588  * Indicates whether this endpoint is active in the current configuration and
76589  * interface. The
76590  *
76591  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
76592  * reset. After
76593  *
76594  * receiving the SetConfiguration and SetInterface commands, the application must
76595  *
76596  * program endpoint registers accordingly and set this bit.
76597  *
76598  * Field Enumeration Values:
76599  *
76600  * Enum | Value | Description
76601  * :-------------------------------------|:------|:--------------------
76602  * ALT_USB_DEV_DIEPCTL3_USBACTEP_E_DISD | 0x0 | Not Active
76603  * ALT_USB_DEV_DIEPCTL3_USBACTEP_E_END | 0x1 | USB Active Endpoint
76604  *
76605  * Field Access Macros:
76606  *
76607  */
76608 /*
76609  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_USBACTEP
76610  *
76611  * Not Active
76612  */
76613 #define ALT_USB_DEV_DIEPCTL3_USBACTEP_E_DISD 0x0
76614 /*
76615  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_USBACTEP
76616  *
76617  * USB Active Endpoint
76618  */
76619 #define ALT_USB_DEV_DIEPCTL3_USBACTEP_E_END 0x1
76620 
76621 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */
76622 #define ALT_USB_DEV_DIEPCTL3_USBACTEP_LSB 15
76623 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */
76624 #define ALT_USB_DEV_DIEPCTL3_USBACTEP_MSB 15
76625 /* The width in bits of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */
76626 #define ALT_USB_DEV_DIEPCTL3_USBACTEP_WIDTH 1
76627 /* The mask used to set the ALT_USB_DEV_DIEPCTL3_USBACTEP register field value. */
76628 #define ALT_USB_DEV_DIEPCTL3_USBACTEP_SET_MSK 0x00008000
76629 /* The mask used to clear the ALT_USB_DEV_DIEPCTL3_USBACTEP register field value. */
76630 #define ALT_USB_DEV_DIEPCTL3_USBACTEP_CLR_MSK 0xffff7fff
76631 /* The reset value of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */
76632 #define ALT_USB_DEV_DIEPCTL3_USBACTEP_RESET 0x0
76633 /* Extracts the ALT_USB_DEV_DIEPCTL3_USBACTEP field value from a register. */
76634 #define ALT_USB_DEV_DIEPCTL3_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
76635 /* Produces a ALT_USB_DEV_DIEPCTL3_USBACTEP register field value suitable for setting the register. */
76636 #define ALT_USB_DEV_DIEPCTL3_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
76637 
76638 /*
76639  * Field : dpid
76640  *
76641  * Endpoint Data PID (DPID)
76642  *
76643  * Applies to interrupt/bulk IN and OUT endpoints only.
76644  *
76645  * Contains the PID of the packet to be received or transmitted on this endpoint.
76646  * The
76647  *
76648  * application must program the PID of the first packet to be received or
76649  * transmitted on
76650  *
76651  * this endpoint, after the endpoint is activated. The applications use the
76652  * SetD1PID and
76653  *
76654  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
76655  *
76656  * 1'b0: DATA0
76657  *
76658  * 1'b1: DATA1
76659  *
76660  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
76661  *
76662  * DMA mode.
76663  *
76664  * 1'b0 RO
76665  *
76666  * Even/Odd (Micro)Frame (EO_FrNum)
76667  *
76668  * In non-Scatter/Gather DMA mode:
76669  *
76670  * Applies to isochronous IN and OUT endpoints only.
76671  *
76672  * Indicates the (micro)frame number in which the core transmits/receives
76673  * isochronous
76674  *
76675  * data for this endpoint. The application must program the even/odd (micro) frame
76676  *
76677  * number in which it intends to transmit/receive isochronous data for this
76678  * endpoint using
76679  *
76680  * the SetEvnFr and SetOddFr fields in this register.
76681  *
76682  * 1'b0: Even (micro)frame
76683  *
76684  * 1'b1: Odd (micro)frame
76685  *
76686  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
76687  * number
76688  *
76689  * in which to send data is provided in the transmit descriptor structure. The
76690  * frame in
76691  *
76692  * which data is received is updated in receive descriptor structure.
76693  *
76694  * Field Enumeration Values:
76695  *
76696  * Enum | Value | Description
76697  * :----------------------------------|:------|:-----------------------------
76698  * ALT_USB_DEV_DIEPCTL3_DPID_E_INACT | 0x0 | Endpoint Data PID not active
76699  * ALT_USB_DEV_DIEPCTL3_DPID_E_ACT | 0x1 | Endpoint Data PID active
76700  *
76701  * Field Access Macros:
76702  *
76703  */
76704 /*
76705  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_DPID
76706  *
76707  * Endpoint Data PID not active
76708  */
76709 #define ALT_USB_DEV_DIEPCTL3_DPID_E_INACT 0x0
76710 /*
76711  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_DPID
76712  *
76713  * Endpoint Data PID active
76714  */
76715 #define ALT_USB_DEV_DIEPCTL3_DPID_E_ACT 0x1
76716 
76717 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_DPID register field. */
76718 #define ALT_USB_DEV_DIEPCTL3_DPID_LSB 16
76719 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_DPID register field. */
76720 #define ALT_USB_DEV_DIEPCTL3_DPID_MSB 16
76721 /* The width in bits of the ALT_USB_DEV_DIEPCTL3_DPID register field. */
76722 #define ALT_USB_DEV_DIEPCTL3_DPID_WIDTH 1
76723 /* The mask used to set the ALT_USB_DEV_DIEPCTL3_DPID register field value. */
76724 #define ALT_USB_DEV_DIEPCTL3_DPID_SET_MSK 0x00010000
76725 /* The mask used to clear the ALT_USB_DEV_DIEPCTL3_DPID register field value. */
76726 #define ALT_USB_DEV_DIEPCTL3_DPID_CLR_MSK 0xfffeffff
76727 /* The reset value of the ALT_USB_DEV_DIEPCTL3_DPID register field. */
76728 #define ALT_USB_DEV_DIEPCTL3_DPID_RESET 0x0
76729 /* Extracts the ALT_USB_DEV_DIEPCTL3_DPID field value from a register. */
76730 #define ALT_USB_DEV_DIEPCTL3_DPID_GET(value) (((value) & 0x00010000) >> 16)
76731 /* Produces a ALT_USB_DEV_DIEPCTL3_DPID register field value suitable for setting the register. */
76732 #define ALT_USB_DEV_DIEPCTL3_DPID_SET(value) (((value) << 16) & 0x00010000)
76733 
76734 /*
76735  * Field : naksts
76736  *
76737  * NAK Status (NAKSts)
76738  *
76739  * Indicates the following:
76740  *
76741  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
76742  *
76743  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
76744  *
76745  * When either the application or the core sets this bit:
76746  *
76747  * The core stops receiving any data on an OUT endpoint, even if there is space in
76748  *
76749  * the RxFIFO to accommodate the incoming packet.
76750  *
76751  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
76752  *
76753  * endpoint, even if there data is available in the TxFIFO.
76754  *
76755  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
76756  *
76757  * if there data is available in the TxFIFO.
76758  *
76759  * Irrespective of this bit's setting, the core always responds to SETUP data
76760  * packets with
76761  *
76762  * an ACK handshake.
76763  *
76764  * Field Enumeration Values:
76765  *
76766  * Enum | Value | Description
76767  * :-------------------------------------|:------|:------------------------------------------------
76768  * ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
76769  * : | | based on the FIFO status
76770  * ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
76771  * : | | endpoint
76772  *
76773  * Field Access Macros:
76774  *
76775  */
76776 /*
76777  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_NAKSTS
76778  *
76779  * The core is transmitting non-NAK handshakes based on the FIFO status
76780  */
76781 #define ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NONNAK 0x0
76782 /*
76783  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_NAKSTS
76784  *
76785  * The core is transmitting NAK handshakes on this endpoint
76786  */
76787 #define ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NAK 0x1
76788 
76789 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */
76790 #define ALT_USB_DEV_DIEPCTL3_NAKSTS_LSB 17
76791 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */
76792 #define ALT_USB_DEV_DIEPCTL3_NAKSTS_MSB 17
76793 /* The width in bits of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */
76794 #define ALT_USB_DEV_DIEPCTL3_NAKSTS_WIDTH 1
76795 /* The mask used to set the ALT_USB_DEV_DIEPCTL3_NAKSTS register field value. */
76796 #define ALT_USB_DEV_DIEPCTL3_NAKSTS_SET_MSK 0x00020000
76797 /* The mask used to clear the ALT_USB_DEV_DIEPCTL3_NAKSTS register field value. */
76798 #define ALT_USB_DEV_DIEPCTL3_NAKSTS_CLR_MSK 0xfffdffff
76799 /* The reset value of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */
76800 #define ALT_USB_DEV_DIEPCTL3_NAKSTS_RESET 0x0
76801 /* Extracts the ALT_USB_DEV_DIEPCTL3_NAKSTS field value from a register. */
76802 #define ALT_USB_DEV_DIEPCTL3_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
76803 /* Produces a ALT_USB_DEV_DIEPCTL3_NAKSTS register field value suitable for setting the register. */
76804 #define ALT_USB_DEV_DIEPCTL3_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
76805 
76806 /*
76807  * Field : eptype
76808  *
76809  * Endpoint Type (EPType)
76810  *
76811  * This is the transfer type supported by this logical endpoint.
76812  *
76813  * 2'b00: Control
76814  *
76815  * 2'b01: Isochronous
76816  *
76817  * 2'b10: Bulk
76818  *
76819  * 2'b11: Interrupt
76820  *
76821  * Field Enumeration Values:
76822  *
76823  * Enum | Value | Description
76824  * :------------------------------------------|:------|:------------
76825  * ALT_USB_DEV_DIEPCTL3_EPTYPE_E_CTL | 0x0 | Control
76826  * ALT_USB_DEV_DIEPCTL3_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
76827  * ALT_USB_DEV_DIEPCTL3_EPTYPE_E_BULK | 0x2 | Bulk
76828  * ALT_USB_DEV_DIEPCTL3_EPTYPE_E_INTERRUP | 0x3 | Interrupt
76829  *
76830  * Field Access Macros:
76831  *
76832  */
76833 /*
76834  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE
76835  *
76836  * Control
76837  */
76838 #define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_CTL 0x0
76839 /*
76840  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE
76841  *
76842  * Isochronous
76843  */
76844 #define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_ISOCHRONOUS 0x1
76845 /*
76846  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE
76847  *
76848  * Bulk
76849  */
76850 #define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_BULK 0x2
76851 /*
76852  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE
76853  *
76854  * Interrupt
76855  */
76856 #define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_INTERRUP 0x3
76857 
76858 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */
76859 #define ALT_USB_DEV_DIEPCTL3_EPTYPE_LSB 18
76860 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */
76861 #define ALT_USB_DEV_DIEPCTL3_EPTYPE_MSB 19
76862 /* The width in bits of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */
76863 #define ALT_USB_DEV_DIEPCTL3_EPTYPE_WIDTH 2
76864 /* The mask used to set the ALT_USB_DEV_DIEPCTL3_EPTYPE register field value. */
76865 #define ALT_USB_DEV_DIEPCTL3_EPTYPE_SET_MSK 0x000c0000
76866 /* The mask used to clear the ALT_USB_DEV_DIEPCTL3_EPTYPE register field value. */
76867 #define ALT_USB_DEV_DIEPCTL3_EPTYPE_CLR_MSK 0xfff3ffff
76868 /* The reset value of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */
76869 #define ALT_USB_DEV_DIEPCTL3_EPTYPE_RESET 0x0
76870 /* Extracts the ALT_USB_DEV_DIEPCTL3_EPTYPE field value from a register. */
76871 #define ALT_USB_DEV_DIEPCTL3_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
76872 /* Produces a ALT_USB_DEV_DIEPCTL3_EPTYPE register field value suitable for setting the register. */
76873 #define ALT_USB_DEV_DIEPCTL3_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
76874 
76875 /*
76876  * Field : stall
76877  *
76878  * STALL Handshake (Stall)
76879  *
76880  * Applies to non-control, non-isochronous IN and OUT endpoints only.
76881  *
76882  * The application sets this bit to stall all tokens from the USB host to this
76883  * endpoint. If a
76884  *
76885  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
76886  * bit, the
76887  *
76888  * STALL bit takes priority. Only the application can clear this bit, never the
76889  * core.
76890  *
76891  * 1'b0 R_W
76892  *
76893  * Applies to control endpoints only.
76894  *
76895  * The application can only set this bit, and the core clears it, when a SETUP
76896  * token is
76897  *
76898  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
76899  * OUT
76900  *
76901  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
76902  * this bit's
76903  *
76904  * setting, the core always responds to SETUP data packets with an ACK handshake.
76905  *
76906  * Field Enumeration Values:
76907  *
76908  * Enum | Value | Description
76909  * :-----------------------------------|:------|:----------------------------
76910  * ALT_USB_DEV_DIEPCTL3_STALL_E_INACT | 0x0 | STALL All Tokens not active
76911  * ALT_USB_DEV_DIEPCTL3_STALL_E_ACT | 0x1 | STALL All Tokens active
76912  *
76913  * Field Access Macros:
76914  *
76915  */
76916 /*
76917  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_STALL
76918  *
76919  * STALL All Tokens not active
76920  */
76921 #define ALT_USB_DEV_DIEPCTL3_STALL_E_INACT 0x0
76922 /*
76923  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_STALL
76924  *
76925  * STALL All Tokens active
76926  */
76927 #define ALT_USB_DEV_DIEPCTL3_STALL_E_ACT 0x1
76928 
76929 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_STALL register field. */
76930 #define ALT_USB_DEV_DIEPCTL3_STALL_LSB 21
76931 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_STALL register field. */
76932 #define ALT_USB_DEV_DIEPCTL3_STALL_MSB 21
76933 /* The width in bits of the ALT_USB_DEV_DIEPCTL3_STALL register field. */
76934 #define ALT_USB_DEV_DIEPCTL3_STALL_WIDTH 1
76935 /* The mask used to set the ALT_USB_DEV_DIEPCTL3_STALL register field value. */
76936 #define ALT_USB_DEV_DIEPCTL3_STALL_SET_MSK 0x00200000
76937 /* The mask used to clear the ALT_USB_DEV_DIEPCTL3_STALL register field value. */
76938 #define ALT_USB_DEV_DIEPCTL3_STALL_CLR_MSK 0xffdfffff
76939 /* The reset value of the ALT_USB_DEV_DIEPCTL3_STALL register field. */
76940 #define ALT_USB_DEV_DIEPCTL3_STALL_RESET 0x0
76941 /* Extracts the ALT_USB_DEV_DIEPCTL3_STALL field value from a register. */
76942 #define ALT_USB_DEV_DIEPCTL3_STALL_GET(value) (((value) & 0x00200000) >> 21)
76943 /* Produces a ALT_USB_DEV_DIEPCTL3_STALL register field value suitable for setting the register. */
76944 #define ALT_USB_DEV_DIEPCTL3_STALL_SET(value) (((value) << 21) & 0x00200000)
76945 
76946 /*
76947  * Field : txfnum
76948  *
76949  * TxFIFO Number (TxFNum)
76950  *
76951  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
76952  *
76953  * endpoints must map this to the corresponding Periodic TxFIFO number.
76954  *
76955  * 4'h0: Non-Periodic TxFIFO
76956  *
76957  * Others: Specified Periodic TxFIFO.number
76958  *
76959  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
76960  *
76961  * applications such as mass storage. The core treats an IN endpoint as a non-
76962  * periodic
76963  *
76964  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
76965  * must be
76966  *
76967  * allocated for an interrupt IN endpoint, and the number of this
76968  *
76969  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
76970  *
76971  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
76972  *
76973  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
76974  *
76975  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
76976  *
76977  * This field is valid only for IN endpoints.
76978  *
76979  * Field Access Macros:
76980  *
76981  */
76982 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */
76983 #define ALT_USB_DEV_DIEPCTL3_TXFNUM_LSB 22
76984 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */
76985 #define ALT_USB_DEV_DIEPCTL3_TXFNUM_MSB 25
76986 /* The width in bits of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */
76987 #define ALT_USB_DEV_DIEPCTL3_TXFNUM_WIDTH 4
76988 /* The mask used to set the ALT_USB_DEV_DIEPCTL3_TXFNUM register field value. */
76989 #define ALT_USB_DEV_DIEPCTL3_TXFNUM_SET_MSK 0x03c00000
76990 /* The mask used to clear the ALT_USB_DEV_DIEPCTL3_TXFNUM register field value. */
76991 #define ALT_USB_DEV_DIEPCTL3_TXFNUM_CLR_MSK 0xfc3fffff
76992 /* The reset value of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */
76993 #define ALT_USB_DEV_DIEPCTL3_TXFNUM_RESET 0x0
76994 /* Extracts the ALT_USB_DEV_DIEPCTL3_TXFNUM field value from a register. */
76995 #define ALT_USB_DEV_DIEPCTL3_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
76996 /* Produces a ALT_USB_DEV_DIEPCTL3_TXFNUM register field value suitable for setting the register. */
76997 #define ALT_USB_DEV_DIEPCTL3_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
76998 
76999 /*
77000  * Field : cnak
77001  *
77002  * Clear NAK (CNAK)
77003  *
77004  * A write to this bit clears the NAK bit For the endpoint.
77005  *
77006  * Field Enumeration Values:
77007  *
77008  * Enum | Value | Description
77009  * :----------------------------------|:------|:-------------
77010  * ALT_USB_DEV_DIEPCTL3_CNAK_E_INACT | 0x0 | No Clear NAK
77011  * ALT_USB_DEV_DIEPCTL3_CNAK_E_ACT | 0x1 | Clear NAK
77012  *
77013  * Field Access Macros:
77014  *
77015  */
77016 /*
77017  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_CNAK
77018  *
77019  * No Clear NAK
77020  */
77021 #define ALT_USB_DEV_DIEPCTL3_CNAK_E_INACT 0x0
77022 /*
77023  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_CNAK
77024  *
77025  * Clear NAK
77026  */
77027 #define ALT_USB_DEV_DIEPCTL3_CNAK_E_ACT 0x1
77028 
77029 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */
77030 #define ALT_USB_DEV_DIEPCTL3_CNAK_LSB 26
77031 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */
77032 #define ALT_USB_DEV_DIEPCTL3_CNAK_MSB 26
77033 /* The width in bits of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */
77034 #define ALT_USB_DEV_DIEPCTL3_CNAK_WIDTH 1
77035 /* The mask used to set the ALT_USB_DEV_DIEPCTL3_CNAK register field value. */
77036 #define ALT_USB_DEV_DIEPCTL3_CNAK_SET_MSK 0x04000000
77037 /* The mask used to clear the ALT_USB_DEV_DIEPCTL3_CNAK register field value. */
77038 #define ALT_USB_DEV_DIEPCTL3_CNAK_CLR_MSK 0xfbffffff
77039 /* The reset value of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */
77040 #define ALT_USB_DEV_DIEPCTL3_CNAK_RESET 0x0
77041 /* Extracts the ALT_USB_DEV_DIEPCTL3_CNAK field value from a register. */
77042 #define ALT_USB_DEV_DIEPCTL3_CNAK_GET(value) (((value) & 0x04000000) >> 26)
77043 /* Produces a ALT_USB_DEV_DIEPCTL3_CNAK register field value suitable for setting the register. */
77044 #define ALT_USB_DEV_DIEPCTL3_CNAK_SET(value) (((value) << 26) & 0x04000000)
77045 
77046 /*
77047  * Field : snak
77048  *
77049  * Set NAK (SNAK)
77050  *
77051  * A write to this bit sets the NAK bit For the endpoint.
77052  *
77053  * Using this bit, the application can control the transmission of NAK
77054  *
77055  * handshakes on an endpoint. The core can also Set this bit For an
77056  *
77057  * endpoint after a SETUP packet is received on that endpoint.
77058  *
77059  * Field Enumeration Values:
77060  *
77061  * Enum | Value | Description
77062  * :----------------------------------|:------|:------------
77063  * ALT_USB_DEV_DIEPCTL3_SNAK_E_INACT | 0x0 | No Set NAK
77064  * ALT_USB_DEV_DIEPCTL3_SNAK_E_ACT | 0x1 | Set NAK
77065  *
77066  * Field Access Macros:
77067  *
77068  */
77069 /*
77070  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SNAK
77071  *
77072  * No Set NAK
77073  */
77074 #define ALT_USB_DEV_DIEPCTL3_SNAK_E_INACT 0x0
77075 /*
77076  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SNAK
77077  *
77078  * Set NAK
77079  */
77080 #define ALT_USB_DEV_DIEPCTL3_SNAK_E_ACT 0x1
77081 
77082 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */
77083 #define ALT_USB_DEV_DIEPCTL3_SNAK_LSB 27
77084 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */
77085 #define ALT_USB_DEV_DIEPCTL3_SNAK_MSB 27
77086 /* The width in bits of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */
77087 #define ALT_USB_DEV_DIEPCTL3_SNAK_WIDTH 1
77088 /* The mask used to set the ALT_USB_DEV_DIEPCTL3_SNAK register field value. */
77089 #define ALT_USB_DEV_DIEPCTL3_SNAK_SET_MSK 0x08000000
77090 /* The mask used to clear the ALT_USB_DEV_DIEPCTL3_SNAK register field value. */
77091 #define ALT_USB_DEV_DIEPCTL3_SNAK_CLR_MSK 0xf7ffffff
77092 /* The reset value of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */
77093 #define ALT_USB_DEV_DIEPCTL3_SNAK_RESET 0x0
77094 /* Extracts the ALT_USB_DEV_DIEPCTL3_SNAK field value from a register. */
77095 #define ALT_USB_DEV_DIEPCTL3_SNAK_GET(value) (((value) & 0x08000000) >> 27)
77096 /* Produces a ALT_USB_DEV_DIEPCTL3_SNAK register field value suitable for setting the register. */
77097 #define ALT_USB_DEV_DIEPCTL3_SNAK_SET(value) (((value) << 27) & 0x08000000)
77098 
77099 /*
77100  * Field : setd0pid
77101  *
77102  * Set DATA0 PID (SetD0PID)
77103  *
77104  * Applies to interrupt/bulk IN and OUT endpoints only.
77105  *
77106  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
77107  * to DATA0.
77108  *
77109  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
77110  *
77111  * DMA mode.
77112  *
77113  * 1'b0 WO
77114  *
77115  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
77116  *
77117  * Applies to isochronous IN and OUT endpoints only.
77118  *
77119  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
77120  * (micro)
77121  *
77122  * frame.
77123  *
77124  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
77125  * number
77126  *
77127  * in which to send data is in the transmit descriptor structure. The frame in
77128  * which to
77129  *
77130  * receive data is updated in receive descriptor structure.
77131  *
77132  * Field Enumeration Values:
77133  *
77134  * Enum | Value | Description
77135  * :-------------------------------------|:------|:----------------------------
77136  * ALT_USB_DEV_DIEPCTL3_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
77137  * ALT_USB_DEV_DIEPCTL3_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
77138  *
77139  * Field Access Macros:
77140  *
77141  */
77142 /*
77143  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD0PID
77144  *
77145  * Disables Set DATA0 PID
77146  */
77147 #define ALT_USB_DEV_DIEPCTL3_SETD0PID_E_DISD 0x0
77148 /*
77149  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD0PID
77150  *
77151  * Endpoint Data PID to DATA0)
77152  */
77153 #define ALT_USB_DEV_DIEPCTL3_SETD0PID_E_END 0x1
77154 
77155 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */
77156 #define ALT_USB_DEV_DIEPCTL3_SETD0PID_LSB 28
77157 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */
77158 #define ALT_USB_DEV_DIEPCTL3_SETD0PID_MSB 28
77159 /* The width in bits of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */
77160 #define ALT_USB_DEV_DIEPCTL3_SETD0PID_WIDTH 1
77161 /* The mask used to set the ALT_USB_DEV_DIEPCTL3_SETD0PID register field value. */
77162 #define ALT_USB_DEV_DIEPCTL3_SETD0PID_SET_MSK 0x10000000
77163 /* The mask used to clear the ALT_USB_DEV_DIEPCTL3_SETD0PID register field value. */
77164 #define ALT_USB_DEV_DIEPCTL3_SETD0PID_CLR_MSK 0xefffffff
77165 /* The reset value of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */
77166 #define ALT_USB_DEV_DIEPCTL3_SETD0PID_RESET 0x0
77167 /* Extracts the ALT_USB_DEV_DIEPCTL3_SETD0PID field value from a register. */
77168 #define ALT_USB_DEV_DIEPCTL3_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
77169 /* Produces a ALT_USB_DEV_DIEPCTL3_SETD0PID register field value suitable for setting the register. */
77170 #define ALT_USB_DEV_DIEPCTL3_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
77171 
77172 /*
77173  * Field : setd1pid
77174  *
77175  * Set DATA1 PID (SetD1PID)
77176  *
77177  * Applies to interrupt/bulk IN and OUT endpoints only.
77178  *
77179  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
77180  * to DATA1.
77181  *
77182  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
77183  *
77184  * DMA mode.
77185  *
77186  * Set Odd (micro)frame (SetOddFr)
77187  *
77188  * Applies to isochronous IN and OUT endpoints only.
77189  *
77190  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
77191  *
77192  * (micro)frame.
77193  *
77194  * This field is not applicable for Scatter/Gather DMA mode.
77195  *
77196  * Field Enumeration Values:
77197  *
77198  * Enum | Value | Description
77199  * :-------------------------------------|:------|:-----------------------
77200  * ALT_USB_DEV_DIEPCTL3_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
77201  * ALT_USB_DEV_DIEPCTL3_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
77202  *
77203  * Field Access Macros:
77204  *
77205  */
77206 /*
77207  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD1PID
77208  *
77209  * Disables Set DATA1 PID
77210  */
77211 #define ALT_USB_DEV_DIEPCTL3_SETD1PID_E_DISD 0x0
77212 /*
77213  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD1PID
77214  *
77215  * Enables Set DATA1 PID
77216  */
77217 #define ALT_USB_DEV_DIEPCTL3_SETD1PID_E_END 0x1
77218 
77219 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */
77220 #define ALT_USB_DEV_DIEPCTL3_SETD1PID_LSB 29
77221 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */
77222 #define ALT_USB_DEV_DIEPCTL3_SETD1PID_MSB 29
77223 /* The width in bits of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */
77224 #define ALT_USB_DEV_DIEPCTL3_SETD1PID_WIDTH 1
77225 /* The mask used to set the ALT_USB_DEV_DIEPCTL3_SETD1PID register field value. */
77226 #define ALT_USB_DEV_DIEPCTL3_SETD1PID_SET_MSK 0x20000000
77227 /* The mask used to clear the ALT_USB_DEV_DIEPCTL3_SETD1PID register field value. */
77228 #define ALT_USB_DEV_DIEPCTL3_SETD1PID_CLR_MSK 0xdfffffff
77229 /* The reset value of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */
77230 #define ALT_USB_DEV_DIEPCTL3_SETD1PID_RESET 0x0
77231 /* Extracts the ALT_USB_DEV_DIEPCTL3_SETD1PID field value from a register. */
77232 #define ALT_USB_DEV_DIEPCTL3_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
77233 /* Produces a ALT_USB_DEV_DIEPCTL3_SETD1PID register field value suitable for setting the register. */
77234 #define ALT_USB_DEV_DIEPCTL3_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
77235 
77236 /*
77237  * Field : epdis
77238  *
77239  * Endpoint Disable (EPDis)
77240  *
77241  * Applies to IN and OUT endpoints.
77242  *
77243  * The application sets this bit to stop transmitting/receiving data on an
77244  * endpoint, even
77245  *
77246  * before the transfer for that endpoint is complete. The application must wait for
77247  * the
77248  *
77249  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
77250  * clears
77251  *
77252  * this bit before setting the Endpoint Disabled interrupt. The application must
77253  * set this bit
77254  *
77255  * only if Endpoint Enable is already set for this endpoint.
77256  *
77257  * Field Enumeration Values:
77258  *
77259  * Enum | Value | Description
77260  * :-----------------------------------|:------|:--------------------
77261  * ALT_USB_DEV_DIEPCTL3_EPDIS_E_INACT | 0x0 | No Endpoint Disable
77262  * ALT_USB_DEV_DIEPCTL3_EPDIS_E_ACT | 0x1 | Endpoint Disable
77263  *
77264  * Field Access Macros:
77265  *
77266  */
77267 /*
77268  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPDIS
77269  *
77270  * No Endpoint Disable
77271  */
77272 #define ALT_USB_DEV_DIEPCTL3_EPDIS_E_INACT 0x0
77273 /*
77274  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPDIS
77275  *
77276  * Endpoint Disable
77277  */
77278 #define ALT_USB_DEV_DIEPCTL3_EPDIS_E_ACT 0x1
77279 
77280 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */
77281 #define ALT_USB_DEV_DIEPCTL3_EPDIS_LSB 30
77282 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */
77283 #define ALT_USB_DEV_DIEPCTL3_EPDIS_MSB 30
77284 /* The width in bits of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */
77285 #define ALT_USB_DEV_DIEPCTL3_EPDIS_WIDTH 1
77286 /* The mask used to set the ALT_USB_DEV_DIEPCTL3_EPDIS register field value. */
77287 #define ALT_USB_DEV_DIEPCTL3_EPDIS_SET_MSK 0x40000000
77288 /* The mask used to clear the ALT_USB_DEV_DIEPCTL3_EPDIS register field value. */
77289 #define ALT_USB_DEV_DIEPCTL3_EPDIS_CLR_MSK 0xbfffffff
77290 /* The reset value of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */
77291 #define ALT_USB_DEV_DIEPCTL3_EPDIS_RESET 0x0
77292 /* Extracts the ALT_USB_DEV_DIEPCTL3_EPDIS field value from a register. */
77293 #define ALT_USB_DEV_DIEPCTL3_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
77294 /* Produces a ALT_USB_DEV_DIEPCTL3_EPDIS register field value suitable for setting the register. */
77295 #define ALT_USB_DEV_DIEPCTL3_EPDIS_SET(value) (((value) << 30) & 0x40000000)
77296 
77297 /*
77298  * Field : epena
77299  *
77300  * Endpoint Enable (EPEna)
77301  *
77302  * Applies to IN and OUT endpoints.
77303  *
77304  * When Scatter/Gather DMA mode is enabled,
77305  *
77306  * For IN endpoints this bit indicates that the descriptor structure and data
77307  * buffer with
77308  *
77309  * data ready to transmit is setup.
77310  *
77311  * For OUT endpoint it indicates that the descriptor structure and data buffer to
77312  *
77313  * receive data is setup.
77314  *
77315  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
77316  *
77317  * DMA mode:
77318  *
77319  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
77320  * the
77321  *
77322  * endpoint.
77323  *
77324  * * For OUT endpoints, this bit indicates that the application has allocated the
77325  *
77326  * memory to start receiving data from the USB.
77327  *
77328  * * The core clears this bit before setting any of the following interrupts on
77329  * this
77330  *
77331  * endpoint:
77332  *
77333  * SETUP Phase Done
77334  *
77335  * Endpoint Disabled
77336  *
77337  * Transfer Completed
77338  *
77339  * Note: For control endpoints in DMA mode, this bit must be set to be able to
77340  * transfer
77341  *
77342  * SETUP data packets in memory.
77343  *
77344  * Field Enumeration Values:
77345  *
77346  * Enum | Value | Description
77347  * :-----------------------------------|:------|:-------------------------
77348  * ALT_USB_DEV_DIEPCTL3_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
77349  * ALT_USB_DEV_DIEPCTL3_EPENA_E_ACT | 0x1 | Endpoint Enable active
77350  *
77351  * Field Access Macros:
77352  *
77353  */
77354 /*
77355  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPENA
77356  *
77357  * Endpoint Enable inactive
77358  */
77359 #define ALT_USB_DEV_DIEPCTL3_EPENA_E_INACT 0x0
77360 /*
77361  * Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPENA
77362  *
77363  * Endpoint Enable active
77364  */
77365 #define ALT_USB_DEV_DIEPCTL3_EPENA_E_ACT 0x1
77366 
77367 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */
77368 #define ALT_USB_DEV_DIEPCTL3_EPENA_LSB 31
77369 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */
77370 #define ALT_USB_DEV_DIEPCTL3_EPENA_MSB 31
77371 /* The width in bits of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */
77372 #define ALT_USB_DEV_DIEPCTL3_EPENA_WIDTH 1
77373 /* The mask used to set the ALT_USB_DEV_DIEPCTL3_EPENA register field value. */
77374 #define ALT_USB_DEV_DIEPCTL3_EPENA_SET_MSK 0x80000000
77375 /* The mask used to clear the ALT_USB_DEV_DIEPCTL3_EPENA register field value. */
77376 #define ALT_USB_DEV_DIEPCTL3_EPENA_CLR_MSK 0x7fffffff
77377 /* The reset value of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */
77378 #define ALT_USB_DEV_DIEPCTL3_EPENA_RESET 0x0
77379 /* Extracts the ALT_USB_DEV_DIEPCTL3_EPENA field value from a register. */
77380 #define ALT_USB_DEV_DIEPCTL3_EPENA_GET(value) (((value) & 0x80000000) >> 31)
77381 /* Produces a ALT_USB_DEV_DIEPCTL3_EPENA register field value suitable for setting the register. */
77382 #define ALT_USB_DEV_DIEPCTL3_EPENA_SET(value) (((value) << 31) & 0x80000000)
77383 
77384 #ifndef __ASSEMBLY__
77385 /*
77386  * WARNING: The C register and register group struct declarations are provided for
77387  * convenience and illustrative purposes. They should, however, be used with
77388  * caution as the C language standard provides no guarantees about the alignment or
77389  * atomicity of device memory accesses. The recommended practice for writing
77390  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
77391  * alt_write_word() functions.
77392  *
77393  * The struct declaration for register ALT_USB_DEV_DIEPCTL3.
77394  */
77395 struct ALT_USB_DEV_DIEPCTL3_s
77396 {
77397  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL3_MPS */
77398  uint32_t : 4; /* *UNDEFINED* */
77399  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL3_USBACTEP */
77400  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL3_DPID */
77401  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL3_NAKSTS */
77402  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL3_EPTYPE */
77403  uint32_t : 1; /* *UNDEFINED* */
77404  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL3_STALL */
77405  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL3_TXFNUM */
77406  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL3_CNAK */
77407  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL3_SNAK */
77408  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL3_SETD0PID */
77409  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL3_SETD1PID */
77410  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL3_EPDIS */
77411  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL3_EPENA */
77412 };
77413 
77414 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL3. */
77415 typedef volatile struct ALT_USB_DEV_DIEPCTL3_s ALT_USB_DEV_DIEPCTL3_t;
77416 #endif /* __ASSEMBLY__ */
77417 
77418 /* The reset value of the ALT_USB_DEV_DIEPCTL3 register. */
77419 #define ALT_USB_DEV_DIEPCTL3_RESET 0x00000000
77420 /* The byte offset of the ALT_USB_DEV_DIEPCTL3 register from the beginning of the component. */
77421 #define ALT_USB_DEV_DIEPCTL3_OFST 0x160
77422 /* The address of the ALT_USB_DEV_DIEPCTL3 register. */
77423 #define ALT_USB_DEV_DIEPCTL3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL3_OFST))
77424 
77425 /*
77426  * Register : diepint3
77427  *
77428  * Device IN Endpoint 3 Interrupt Register
77429  *
77430  * Register Layout
77431  *
77432  * Bits | Access | Reset | Description
77433  * :--------|:-------|:------|:---------------------------------
77434  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_XFERCOMPL
77435  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_EPDISBLD
77436  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_AHBERR
77437  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_TMO
77438  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_INTKNTXFEMP
77439  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_INTKNEPMIS
77440  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_INEPNAKEFF
77441  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT3_TXFEMP
77442  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN
77443  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_BNAINTR
77444  * [10] | ??? | 0x0 | *UNDEFINED*
77445  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_PKTDRPSTS
77446  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_BBLEERR
77447  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_NAKINTRPT
77448  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_NYETINTRPT
77449  * [31:15] | ??? | 0x0 | *UNDEFINED*
77450  *
77451  */
77452 /*
77453  * Field : xfercompl
77454  *
77455  * Transfer Completed Interrupt (XferCompl)
77456  *
77457  * Applies to IN and OUT endpoints.
77458  *
77459  * When Scatter/Gather DMA mode is enabled
77460  *
77461  * * For IN endpoint this field indicates that the requested data
77462  *
77463  * from the descriptor is moved from external system memory
77464  *
77465  * to internal FIFO.
77466  *
77467  * * For OUT endpoint this field indicates that the requested
77468  *
77469  * data from the internal FIFO is moved to external system
77470  *
77471  * memory. This interrupt is generated only when the
77472  *
77473  * corresponding endpoint descriptor is closed, and the IOC
77474  *
77475  * bit For the corresponding descriptor is Set.
77476  *
77477  * When Scatter/Gather DMA mode is disabled, this field
77478  *
77479  * indicates that the programmed transfer is complete on the
77480  *
77481  * AHB as well as on the USB, For this endpoint.
77482  *
77483  * Field Enumeration Values:
77484  *
77485  * Enum | Value | Description
77486  * :---------------------------------------|:------|:-----------------------------
77487  * ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_INACT | 0x0 | No Interrupt
77488  * ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
77489  *
77490  * Field Access Macros:
77491  *
77492  */
77493 /*
77494  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_XFERCOMPL
77495  *
77496  * No Interrupt
77497  */
77498 #define ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_INACT 0x0
77499 /*
77500  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_XFERCOMPL
77501  *
77502  * Transfer Completed Interrupt
77503  */
77504 #define ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_ACT 0x1
77505 
77506 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */
77507 #define ALT_USB_DEV_DIEPINT3_XFERCOMPL_LSB 0
77508 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */
77509 #define ALT_USB_DEV_DIEPINT3_XFERCOMPL_MSB 0
77510 /* The width in bits of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */
77511 #define ALT_USB_DEV_DIEPINT3_XFERCOMPL_WIDTH 1
77512 /* The mask used to set the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field value. */
77513 #define ALT_USB_DEV_DIEPINT3_XFERCOMPL_SET_MSK 0x00000001
77514 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field value. */
77515 #define ALT_USB_DEV_DIEPINT3_XFERCOMPL_CLR_MSK 0xfffffffe
77516 /* The reset value of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */
77517 #define ALT_USB_DEV_DIEPINT3_XFERCOMPL_RESET 0x0
77518 /* Extracts the ALT_USB_DEV_DIEPINT3_XFERCOMPL field value from a register. */
77519 #define ALT_USB_DEV_DIEPINT3_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
77520 /* Produces a ALT_USB_DEV_DIEPINT3_XFERCOMPL register field value suitable for setting the register. */
77521 #define ALT_USB_DEV_DIEPINT3_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
77522 
77523 /*
77524  * Field : epdisbld
77525  *
77526  * Endpoint Disabled Interrupt (EPDisbld)
77527  *
77528  * Applies to IN and OUT endpoints.
77529  *
77530  * This bit indicates that the endpoint is disabled per the
77531  *
77532  * application's request.
77533  *
77534  * Field Enumeration Values:
77535  *
77536  * Enum | Value | Description
77537  * :--------------------------------------|:------|:----------------------------
77538  * ALT_USB_DEV_DIEPINT3_EPDISBLD_E_INACT | 0x0 | No Interrupt
77539  * ALT_USB_DEV_DIEPINT3_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
77540  *
77541  * Field Access Macros:
77542  *
77543  */
77544 /*
77545  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_EPDISBLD
77546  *
77547  * No Interrupt
77548  */
77549 #define ALT_USB_DEV_DIEPINT3_EPDISBLD_E_INACT 0x0
77550 /*
77551  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_EPDISBLD
77552  *
77553  * Endpoint Disabled Interrupt
77554  */
77555 #define ALT_USB_DEV_DIEPINT3_EPDISBLD_E_ACT 0x1
77556 
77557 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */
77558 #define ALT_USB_DEV_DIEPINT3_EPDISBLD_LSB 1
77559 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */
77560 #define ALT_USB_DEV_DIEPINT3_EPDISBLD_MSB 1
77561 /* The width in bits of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */
77562 #define ALT_USB_DEV_DIEPINT3_EPDISBLD_WIDTH 1
77563 /* The mask used to set the ALT_USB_DEV_DIEPINT3_EPDISBLD register field value. */
77564 #define ALT_USB_DEV_DIEPINT3_EPDISBLD_SET_MSK 0x00000002
77565 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_EPDISBLD register field value. */
77566 #define ALT_USB_DEV_DIEPINT3_EPDISBLD_CLR_MSK 0xfffffffd
77567 /* The reset value of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */
77568 #define ALT_USB_DEV_DIEPINT3_EPDISBLD_RESET 0x0
77569 /* Extracts the ALT_USB_DEV_DIEPINT3_EPDISBLD field value from a register. */
77570 #define ALT_USB_DEV_DIEPINT3_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
77571 /* Produces a ALT_USB_DEV_DIEPINT3_EPDISBLD register field value suitable for setting the register. */
77572 #define ALT_USB_DEV_DIEPINT3_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
77573 
77574 /*
77575  * Field : ahberr
77576  *
77577  * AHB Error (AHBErr)
77578  *
77579  * Applies to IN and OUT endpoints.
77580  *
77581  * This is generated only in Internal DMA mode when there is an
77582  *
77583  * AHB error during an AHB read/write. The application can read
77584  *
77585  * the corresponding endpoint DMA address register to get the
77586  *
77587  * error address.
77588  *
77589  * Field Enumeration Values:
77590  *
77591  * Enum | Value | Description
77592  * :------------------------------------|:------|:--------------------
77593  * ALT_USB_DEV_DIEPINT3_AHBERR_E_INACT | 0x0 | No Interrupt
77594  * ALT_USB_DEV_DIEPINT3_AHBERR_E_ACT | 0x1 | AHB Error interrupt
77595  *
77596  * Field Access Macros:
77597  *
77598  */
77599 /*
77600  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_AHBERR
77601  *
77602  * No Interrupt
77603  */
77604 #define ALT_USB_DEV_DIEPINT3_AHBERR_E_INACT 0x0
77605 /*
77606  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_AHBERR
77607  *
77608  * AHB Error interrupt
77609  */
77610 #define ALT_USB_DEV_DIEPINT3_AHBERR_E_ACT 0x1
77611 
77612 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */
77613 #define ALT_USB_DEV_DIEPINT3_AHBERR_LSB 2
77614 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */
77615 #define ALT_USB_DEV_DIEPINT3_AHBERR_MSB 2
77616 /* The width in bits of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */
77617 #define ALT_USB_DEV_DIEPINT3_AHBERR_WIDTH 1
77618 /* The mask used to set the ALT_USB_DEV_DIEPINT3_AHBERR register field value. */
77619 #define ALT_USB_DEV_DIEPINT3_AHBERR_SET_MSK 0x00000004
77620 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_AHBERR register field value. */
77621 #define ALT_USB_DEV_DIEPINT3_AHBERR_CLR_MSK 0xfffffffb
77622 /* The reset value of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */
77623 #define ALT_USB_DEV_DIEPINT3_AHBERR_RESET 0x0
77624 /* Extracts the ALT_USB_DEV_DIEPINT3_AHBERR field value from a register. */
77625 #define ALT_USB_DEV_DIEPINT3_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
77626 /* Produces a ALT_USB_DEV_DIEPINT3_AHBERR register field value suitable for setting the register. */
77627 #define ALT_USB_DEV_DIEPINT3_AHBERR_SET(value) (((value) << 2) & 0x00000004)
77628 
77629 /*
77630  * Field : timeout
77631  *
77632  * Timeout Condition (TimeOUT)
77633  *
77634  * In shared TX FIFO mode, applies to non-isochronous IN
77635  *
77636  * endpoints only.
77637  *
77638  * In dedicated FIFO mode, applies only to Control IN
77639  *
77640  * endpoints.
77641  *
77642  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
77643  *
77644  * asserted.
77645  *
77646  * Indicates that the core has detected a timeout condition on the
77647  *
77648  * USB For the last IN token on this endpoint.
77649  *
77650  * Field Enumeration Values:
77651  *
77652  * Enum | Value | Description
77653  * :---------------------------------|:------|:------------------
77654  * ALT_USB_DEV_DIEPINT3_TMO_E_INACT | 0x0 | No interrupt
77655  * ALT_USB_DEV_DIEPINT3_TMO_E_ACT | 0x1 | Timeout interrupy
77656  *
77657  * Field Access Macros:
77658  *
77659  */
77660 /*
77661  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TMO
77662  *
77663  * No interrupt
77664  */
77665 #define ALT_USB_DEV_DIEPINT3_TMO_E_INACT 0x0
77666 /*
77667  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TMO
77668  *
77669  * Timeout interrupy
77670  */
77671 #define ALT_USB_DEV_DIEPINT3_TMO_E_ACT 0x1
77672 
77673 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_TMO register field. */
77674 #define ALT_USB_DEV_DIEPINT3_TMO_LSB 3
77675 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_TMO register field. */
77676 #define ALT_USB_DEV_DIEPINT3_TMO_MSB 3
77677 /* The width in bits of the ALT_USB_DEV_DIEPINT3_TMO register field. */
77678 #define ALT_USB_DEV_DIEPINT3_TMO_WIDTH 1
77679 /* The mask used to set the ALT_USB_DEV_DIEPINT3_TMO register field value. */
77680 #define ALT_USB_DEV_DIEPINT3_TMO_SET_MSK 0x00000008
77681 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_TMO register field value. */
77682 #define ALT_USB_DEV_DIEPINT3_TMO_CLR_MSK 0xfffffff7
77683 /* The reset value of the ALT_USB_DEV_DIEPINT3_TMO register field. */
77684 #define ALT_USB_DEV_DIEPINT3_TMO_RESET 0x0
77685 /* Extracts the ALT_USB_DEV_DIEPINT3_TMO field value from a register. */
77686 #define ALT_USB_DEV_DIEPINT3_TMO_GET(value) (((value) & 0x00000008) >> 3)
77687 /* Produces a ALT_USB_DEV_DIEPINT3_TMO register field value suitable for setting the register. */
77688 #define ALT_USB_DEV_DIEPINT3_TMO_SET(value) (((value) << 3) & 0x00000008)
77689 
77690 /*
77691  * Field : intkntxfemp
77692  *
77693  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
77694  *
77695  * Applies to non-periodic IN endpoints only.
77696  *
77697  * Indicates that an IN token was received when the associated
77698  *
77699  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
77700  *
77701  * asserted on the endpoint For which the IN token was received.
77702  *
77703  * Field Enumeration Values:
77704  *
77705  * Enum | Value | Description
77706  * :-----------------------------------------|:------|:----------------------------
77707  * ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
77708  * ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
77709  *
77710  * Field Access Macros:
77711  *
77712  */
77713 /*
77714  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNTXFEMP
77715  *
77716  * No interrupt
77717  */
77718 #define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_INACT 0x0
77719 /*
77720  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNTXFEMP
77721  *
77722  * IN Token Received Interrupt
77723  */
77724 #define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_ACT 0x1
77725 
77726 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */
77727 #define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_LSB 4
77728 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */
77729 #define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_MSB 4
77730 /* The width in bits of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */
77731 #define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_WIDTH 1
77732 /* The mask used to set the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field value. */
77733 #define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_SET_MSK 0x00000010
77734 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field value. */
77735 #define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_CLR_MSK 0xffffffef
77736 /* The reset value of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */
77737 #define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_RESET 0x0
77738 /* Extracts the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP field value from a register. */
77739 #define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
77740 /* Produces a ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field value suitable for setting the register. */
77741 #define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
77742 
77743 /*
77744  * Field : intknepmis
77745  *
77746  * IN Token Received with EP Mismatch (INTknEPMis)
77747  *
77748  * Applies to non-periodic IN endpoints only.
77749  *
77750  * Indicates that the data in the top of the non-periodic TxFIFO
77751  *
77752  * belongs to an endpoint other than the one For which the IN token
77753  *
77754  * was received. This interrupt is asserted on the endpoint For
77755  *
77756  * which the IN token was received.
77757  *
77758  * Field Enumeration Values:
77759  *
77760  * Enum | Value | Description
77761  * :----------------------------------------|:------|:---------------------------------------------
77762  * ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_INACT | 0x0 | No interrupt
77763  * ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
77764  *
77765  * Field Access Macros:
77766  *
77767  */
77768 /*
77769  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNEPMIS
77770  *
77771  * No interrupt
77772  */
77773 #define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_INACT 0x0
77774 /*
77775  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNEPMIS
77776  *
77777  * IN Token Received with EP Mismatch interrupt
77778  */
77779 #define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_ACT 0x1
77780 
77781 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */
77782 #define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_LSB 5
77783 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */
77784 #define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_MSB 5
77785 /* The width in bits of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */
77786 #define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_WIDTH 1
77787 /* The mask used to set the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field value. */
77788 #define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_SET_MSK 0x00000020
77789 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field value. */
77790 #define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_CLR_MSK 0xffffffdf
77791 /* The reset value of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */
77792 #define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_RESET 0x0
77793 /* Extracts the ALT_USB_DEV_DIEPINT3_INTKNEPMIS field value from a register. */
77794 #define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
77795 /* Produces a ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field value suitable for setting the register. */
77796 #define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
77797 
77798 /*
77799  * Field : inepnakeff
77800  *
77801  * IN Endpoint NAK Effective (INEPNakEff)
77802  *
77803  * Applies to periodic IN endpoints only.
77804  *
77805  * This bit can be cleared when the application clears the IN
77806  *
77807  * endpoint NAK by writing to DIEPCTLn.CNAK.
77808  *
77809  * This interrupt indicates that the core has sampled the NAK bit
77810  *
77811  * Set (either by the application or by the core). The interrupt
77812  *
77813  * indicates that the IN endpoint NAK bit Set by the application has
77814  *
77815  * taken effect in the core.
77816  *
77817  * This interrupt does not guarantee that a NAK handshake is sent
77818  *
77819  * on the USB. A STALL bit takes priority over a NAK bit.
77820  *
77821  * Field Enumeration Values:
77822  *
77823  * Enum | Value | Description
77824  * :----------------------------------------|:------|:------------------------------------
77825  * ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_INACT | 0x0 | No interrupt
77826  * ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
77827  *
77828  * Field Access Macros:
77829  *
77830  */
77831 /*
77832  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INEPNAKEFF
77833  *
77834  * No interrupt
77835  */
77836 #define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_INACT 0x0
77837 /*
77838  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_INEPNAKEFF
77839  *
77840  * IN Endpoint NAK Effective interrupt
77841  */
77842 #define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_ACT 0x1
77843 
77844 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */
77845 #define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_LSB 6
77846 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */
77847 #define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_MSB 6
77848 /* The width in bits of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */
77849 #define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_WIDTH 1
77850 /* The mask used to set the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field value. */
77851 #define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_SET_MSK 0x00000040
77852 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field value. */
77853 #define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_CLR_MSK 0xffffffbf
77854 /* The reset value of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */
77855 #define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_RESET 0x0
77856 /* Extracts the ALT_USB_DEV_DIEPINT3_INEPNAKEFF field value from a register. */
77857 #define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
77858 /* Produces a ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field value suitable for setting the register. */
77859 #define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
77860 
77861 /*
77862  * Field : txfemp
77863  *
77864  * Transmit FIFO Empty (TxFEmp)
77865  *
77866  * This bit is valid only For IN Endpoints
77867  *
77868  * This interrupt is asserted when the TxFIFO For this endpoint is
77869  *
77870  * either half or completely empty. The half or completely empty
77871  *
77872  * status is determined by the TxFIFO Empty Level bit in the Core
77873  *
77874  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
77875  *
77876  * Field Enumeration Values:
77877  *
77878  * Enum | Value | Description
77879  * :------------------------------------|:------|:------------------------------
77880  * ALT_USB_DEV_DIEPINT3_TXFEMP_E_INACT | 0x0 | No interrupt
77881  * ALT_USB_DEV_DIEPINT3_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
77882  *
77883  * Field Access Macros:
77884  *
77885  */
77886 /*
77887  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFEMP
77888  *
77889  * No interrupt
77890  */
77891 #define ALT_USB_DEV_DIEPINT3_TXFEMP_E_INACT 0x0
77892 /*
77893  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFEMP
77894  *
77895  * Transmit FIFO Empty interrupt
77896  */
77897 #define ALT_USB_DEV_DIEPINT3_TXFEMP_E_ACT 0x1
77898 
77899 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */
77900 #define ALT_USB_DEV_DIEPINT3_TXFEMP_LSB 7
77901 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */
77902 #define ALT_USB_DEV_DIEPINT3_TXFEMP_MSB 7
77903 /* The width in bits of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */
77904 #define ALT_USB_DEV_DIEPINT3_TXFEMP_WIDTH 1
77905 /* The mask used to set the ALT_USB_DEV_DIEPINT3_TXFEMP register field value. */
77906 #define ALT_USB_DEV_DIEPINT3_TXFEMP_SET_MSK 0x00000080
77907 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_TXFEMP register field value. */
77908 #define ALT_USB_DEV_DIEPINT3_TXFEMP_CLR_MSK 0xffffff7f
77909 /* The reset value of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */
77910 #define ALT_USB_DEV_DIEPINT3_TXFEMP_RESET 0x1
77911 /* Extracts the ALT_USB_DEV_DIEPINT3_TXFEMP field value from a register. */
77912 #define ALT_USB_DEV_DIEPINT3_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
77913 /* Produces a ALT_USB_DEV_DIEPINT3_TXFEMP register field value suitable for setting the register. */
77914 #define ALT_USB_DEV_DIEPINT3_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
77915 
77916 /*
77917  * Field : txfifoundrn
77918  *
77919  * Fifo Underrun (TxfifoUndrn)
77920  *
77921  * Applies to IN endpoints Only
77922  *
77923  * This bit is valid only If thresholding is enabled. The core generates this
77924  * interrupt when
77925  *
77926  * it detects a transmit FIFO underrun condition For this endpoint.
77927  *
77928  * Field Enumeration Values:
77929  *
77930  * Enum | Value | Description
77931  * :-----------------------------------------|:------|:------------------------
77932  * ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
77933  * ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
77934  *
77935  * Field Access Macros:
77936  *
77937  */
77938 /*
77939  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN
77940  *
77941  * No interrupt
77942  */
77943 #define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_INACT 0x0
77944 /*
77945  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN
77946  *
77947  * Fifo Underrun interrupt
77948  */
77949 #define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_ACT 0x1
77950 
77951 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */
77952 #define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_LSB 8
77953 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */
77954 #define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_MSB 8
77955 /* The width in bits of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */
77956 #define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_WIDTH 1
77957 /* The mask used to set the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field value. */
77958 #define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_SET_MSK 0x00000100
77959 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field value. */
77960 #define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_CLR_MSK 0xfffffeff
77961 /* The reset value of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */
77962 #define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_RESET 0x0
77963 /* Extracts the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN field value from a register. */
77964 #define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
77965 /* Produces a ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field value suitable for setting the register. */
77966 #define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
77967 
77968 /*
77969  * Field : bnaintr
77970  *
77971  * BNA (Buffer Not Available) Interrupt (BNAIntr)
77972  *
77973  * This bit is valid only when Scatter/Gather DMA mode is enabled.
77974  *
77975  * The core generates this interrupt when the descriptor accessed
77976  *
77977  * is not ready For the Core to process, such as Host busy or DMA
77978  *
77979  * done
77980  *
77981  * Field Enumeration Values:
77982  *
77983  * Enum | Value | Description
77984  * :-------------------------------------|:------|:--------------
77985  * ALT_USB_DEV_DIEPINT3_BNAINTR_E_INACT | 0x0 | No interrupt
77986  * ALT_USB_DEV_DIEPINT3_BNAINTR_E_ACT | 0x1 | BNA interrupt
77987  *
77988  * Field Access Macros:
77989  *
77990  */
77991 /*
77992  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_BNAINTR
77993  *
77994  * No interrupt
77995  */
77996 #define ALT_USB_DEV_DIEPINT3_BNAINTR_E_INACT 0x0
77997 /*
77998  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_BNAINTR
77999  *
78000  * BNA interrupt
78001  */
78002 #define ALT_USB_DEV_DIEPINT3_BNAINTR_E_ACT 0x1
78003 
78004 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */
78005 #define ALT_USB_DEV_DIEPINT3_BNAINTR_LSB 9
78006 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */
78007 #define ALT_USB_DEV_DIEPINT3_BNAINTR_MSB 9
78008 /* The width in bits of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */
78009 #define ALT_USB_DEV_DIEPINT3_BNAINTR_WIDTH 1
78010 /* The mask used to set the ALT_USB_DEV_DIEPINT3_BNAINTR register field value. */
78011 #define ALT_USB_DEV_DIEPINT3_BNAINTR_SET_MSK 0x00000200
78012 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_BNAINTR register field value. */
78013 #define ALT_USB_DEV_DIEPINT3_BNAINTR_CLR_MSK 0xfffffdff
78014 /* The reset value of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */
78015 #define ALT_USB_DEV_DIEPINT3_BNAINTR_RESET 0x0
78016 /* Extracts the ALT_USB_DEV_DIEPINT3_BNAINTR field value from a register. */
78017 #define ALT_USB_DEV_DIEPINT3_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
78018 /* Produces a ALT_USB_DEV_DIEPINT3_BNAINTR register field value suitable for setting the register. */
78019 #define ALT_USB_DEV_DIEPINT3_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
78020 
78021 /*
78022  * Field : pktdrpsts
78023  *
78024  * Packet Drop Status (PktDrpSts)
78025  *
78026  * This bit indicates to the application that an ISOC OUT packet has been dropped.
78027  * This
78028  *
78029  * bit does not have an associated mask bit and does not generate an interrupt.
78030  *
78031  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
78032  * transfer
78033  *
78034  * interrupt feature is selected.
78035  *
78036  * Field Enumeration Values:
78037  *
78038  * Enum | Value | Description
78039  * :---------------------------------------|:------|:-----------------------------
78040  * ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_INACT | 0x0 | No interrupt
78041  * ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
78042  *
78043  * Field Access Macros:
78044  *
78045  */
78046 /*
78047  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_PKTDRPSTS
78048  *
78049  * No interrupt
78050  */
78051 #define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_INACT 0x0
78052 /*
78053  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_PKTDRPSTS
78054  *
78055  * Packet Drop Status interrupt
78056  */
78057 #define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_ACT 0x1
78058 
78059 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */
78060 #define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_LSB 11
78061 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */
78062 #define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_MSB 11
78063 /* The width in bits of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */
78064 #define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_WIDTH 1
78065 /* The mask used to set the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field value. */
78066 #define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_SET_MSK 0x00000800
78067 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field value. */
78068 #define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_CLR_MSK 0xfffff7ff
78069 /* The reset value of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */
78070 #define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_RESET 0x0
78071 /* Extracts the ALT_USB_DEV_DIEPINT3_PKTDRPSTS field value from a register. */
78072 #define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
78073 /* Produces a ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field value suitable for setting the register. */
78074 #define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
78075 
78076 /*
78077  * Field : bbleerr
78078  *
78079  * NAK Interrupt (BbleErr)
78080  *
78081  * The core generates this interrupt when babble is received for the endpoint.
78082  *
78083  * Field Enumeration Values:
78084  *
78085  * Enum | Value | Description
78086  * :-------------------------------------|:------|:------------------
78087  * ALT_USB_DEV_DIEPINT3_BBLEERR_E_INACT | 0x0 | No interrupt
78088  * ALT_USB_DEV_DIEPINT3_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
78089  *
78090  * Field Access Macros:
78091  *
78092  */
78093 /*
78094  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_BBLEERR
78095  *
78096  * No interrupt
78097  */
78098 #define ALT_USB_DEV_DIEPINT3_BBLEERR_E_INACT 0x0
78099 /*
78100  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_BBLEERR
78101  *
78102  * BbleErr interrupt
78103  */
78104 #define ALT_USB_DEV_DIEPINT3_BBLEERR_E_ACT 0x1
78105 
78106 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */
78107 #define ALT_USB_DEV_DIEPINT3_BBLEERR_LSB 12
78108 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */
78109 #define ALT_USB_DEV_DIEPINT3_BBLEERR_MSB 12
78110 /* The width in bits of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */
78111 #define ALT_USB_DEV_DIEPINT3_BBLEERR_WIDTH 1
78112 /* The mask used to set the ALT_USB_DEV_DIEPINT3_BBLEERR register field value. */
78113 #define ALT_USB_DEV_DIEPINT3_BBLEERR_SET_MSK 0x00001000
78114 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_BBLEERR register field value. */
78115 #define ALT_USB_DEV_DIEPINT3_BBLEERR_CLR_MSK 0xffffefff
78116 /* The reset value of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */
78117 #define ALT_USB_DEV_DIEPINT3_BBLEERR_RESET 0x0
78118 /* Extracts the ALT_USB_DEV_DIEPINT3_BBLEERR field value from a register. */
78119 #define ALT_USB_DEV_DIEPINT3_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
78120 /* Produces a ALT_USB_DEV_DIEPINT3_BBLEERR register field value suitable for setting the register. */
78121 #define ALT_USB_DEV_DIEPINT3_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
78122 
78123 /*
78124  * Field : nakintrpt
78125  *
78126  * NAK Interrupt (NAKInterrupt)
78127  *
78128  * The core generates this interrupt when a NAK is transmitted or received by the
78129  * device.
78130  *
78131  * In case of isochronous IN endpoints the interrupt gets generated when a zero
78132  * length
78133  *
78134  * packet is transmitted due to un-availability of data in the TXFifo.
78135  *
78136  * Field Enumeration Values:
78137  *
78138  * Enum | Value | Description
78139  * :---------------------------------------|:------|:--------------
78140  * ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_INACT | 0x0 | No interrupt
78141  * ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
78142  *
78143  * Field Access Macros:
78144  *
78145  */
78146 /*
78147  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_NAKINTRPT
78148  *
78149  * No interrupt
78150  */
78151 #define ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_INACT 0x0
78152 /*
78153  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_NAKINTRPT
78154  *
78155  * NAK Interrupt
78156  */
78157 #define ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_ACT 0x1
78158 
78159 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */
78160 #define ALT_USB_DEV_DIEPINT3_NAKINTRPT_LSB 13
78161 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */
78162 #define ALT_USB_DEV_DIEPINT3_NAKINTRPT_MSB 13
78163 /* The width in bits of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */
78164 #define ALT_USB_DEV_DIEPINT3_NAKINTRPT_WIDTH 1
78165 /* The mask used to set the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field value. */
78166 #define ALT_USB_DEV_DIEPINT3_NAKINTRPT_SET_MSK 0x00002000
78167 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field value. */
78168 #define ALT_USB_DEV_DIEPINT3_NAKINTRPT_CLR_MSK 0xffffdfff
78169 /* The reset value of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */
78170 #define ALT_USB_DEV_DIEPINT3_NAKINTRPT_RESET 0x0
78171 /* Extracts the ALT_USB_DEV_DIEPINT3_NAKINTRPT field value from a register. */
78172 #define ALT_USB_DEV_DIEPINT3_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
78173 /* Produces a ALT_USB_DEV_DIEPINT3_NAKINTRPT register field value suitable for setting the register. */
78174 #define ALT_USB_DEV_DIEPINT3_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
78175 
78176 /*
78177  * Field : nyetintrpt
78178  *
78179  * NYET Interrupt (NYETIntrpt)
78180  *
78181  * The core generates this interrupt when a NYET response is transmitted for a non
78182  * isochronous OUT endpoint.
78183  *
78184  * Field Enumeration Values:
78185  *
78186  * Enum | Value | Description
78187  * :----------------------------------------|:------|:---------------
78188  * ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_INACT | 0x0 | No interrupt
78189  * ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
78190  *
78191  * Field Access Macros:
78192  *
78193  */
78194 /*
78195  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_NYETINTRPT
78196  *
78197  * No interrupt
78198  */
78199 #define ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_INACT 0x0
78200 /*
78201  * Enumerated value for register field ALT_USB_DEV_DIEPINT3_NYETINTRPT
78202  *
78203  * NYET Interrupt
78204  */
78205 #define ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_ACT 0x1
78206 
78207 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */
78208 #define ALT_USB_DEV_DIEPINT3_NYETINTRPT_LSB 14
78209 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */
78210 #define ALT_USB_DEV_DIEPINT3_NYETINTRPT_MSB 14
78211 /* The width in bits of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */
78212 #define ALT_USB_DEV_DIEPINT3_NYETINTRPT_WIDTH 1
78213 /* The mask used to set the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field value. */
78214 #define ALT_USB_DEV_DIEPINT3_NYETINTRPT_SET_MSK 0x00004000
78215 /* The mask used to clear the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field value. */
78216 #define ALT_USB_DEV_DIEPINT3_NYETINTRPT_CLR_MSK 0xffffbfff
78217 /* The reset value of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */
78218 #define ALT_USB_DEV_DIEPINT3_NYETINTRPT_RESET 0x0
78219 /* Extracts the ALT_USB_DEV_DIEPINT3_NYETINTRPT field value from a register. */
78220 #define ALT_USB_DEV_DIEPINT3_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
78221 /* Produces a ALT_USB_DEV_DIEPINT3_NYETINTRPT register field value suitable for setting the register. */
78222 #define ALT_USB_DEV_DIEPINT3_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
78223 
78224 #ifndef __ASSEMBLY__
78225 /*
78226  * WARNING: The C register and register group struct declarations are provided for
78227  * convenience and illustrative purposes. They should, however, be used with
78228  * caution as the C language standard provides no guarantees about the alignment or
78229  * atomicity of device memory accesses. The recommended practice for writing
78230  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
78231  * alt_write_word() functions.
78232  *
78233  * The struct declaration for register ALT_USB_DEV_DIEPINT3.
78234  */
78235 struct ALT_USB_DEV_DIEPINT3_s
78236 {
78237  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT3_XFERCOMPL */
78238  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT3_EPDISBLD */
78239  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT3_AHBERR */
78240  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT3_TMO */
78241  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT3_INTKNTXFEMP */
78242  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT3_INTKNEPMIS */
78243  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT3_INEPNAKEFF */
78244  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT3_TXFEMP */
78245  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN */
78246  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT3_BNAINTR */
78247  uint32_t : 1; /* *UNDEFINED* */
78248  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT3_PKTDRPSTS */
78249  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT3_BBLEERR */
78250  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT3_NAKINTRPT */
78251  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT3_NYETINTRPT */
78252  uint32_t : 17; /* *UNDEFINED* */
78253 };
78254 
78255 /* The typedef declaration for register ALT_USB_DEV_DIEPINT3. */
78256 typedef volatile struct ALT_USB_DEV_DIEPINT3_s ALT_USB_DEV_DIEPINT3_t;
78257 #endif /* __ASSEMBLY__ */
78258 
78259 /* The reset value of the ALT_USB_DEV_DIEPINT3 register. */
78260 #define ALT_USB_DEV_DIEPINT3_RESET 0x00000080
78261 /* The byte offset of the ALT_USB_DEV_DIEPINT3 register from the beginning of the component. */
78262 #define ALT_USB_DEV_DIEPINT3_OFST 0x168
78263 /* The address of the ALT_USB_DEV_DIEPINT3 register. */
78264 #define ALT_USB_DEV_DIEPINT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT3_OFST))
78265 
78266 /*
78267  * Register : dieptsiz3
78268  *
78269  * Device IN Endpoint 3 Transfer Size Register
78270  *
78271  * Register Layout
78272  *
78273  * Bits | Access | Reset | Description
78274  * :--------|:-------|:------|:-------------------------------
78275  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ3_XFERSIZE
78276  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ3_PKTCNT
78277  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ3_MC
78278  * [31] | ??? | 0x0 | *UNDEFINED*
78279  *
78280  */
78281 /*
78282  * Field : xfersize
78283  *
78284  * Transfer Size (XferSize)
78285  *
78286  * Indicates the transfer size in bytes For endpoint 0. The core
78287  *
78288  * interrupts the application only after it has exhausted the transfer
78289  *
78290  * size amount of data. The transfer size can be Set to the
78291  *
78292  * maximum packet size of the endpoint, to be interrupted at the
78293  *
78294  * end of each packet.
78295  *
78296  * The core decrements this field every time a packet from the
78297  *
78298  * external memory is written to the TxFIFO.
78299  *
78300  * Field Access Macros:
78301  *
78302  */
78303 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */
78304 #define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_LSB 0
78305 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */
78306 #define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_MSB 18
78307 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */
78308 #define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_WIDTH 19
78309 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field value. */
78310 #define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_SET_MSK 0x0007ffff
78311 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field value. */
78312 #define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_CLR_MSK 0xfff80000
78313 /* The reset value of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */
78314 #define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_RESET 0x0
78315 /* Extracts the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE field value from a register. */
78316 #define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
78317 /* Produces a ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field value suitable for setting the register. */
78318 #define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
78319 
78320 /*
78321  * Field : pktcnt
78322  *
78323  * Packet Count (PktCnt)
78324  *
78325  * Indicates the total number of USB packets that constitute the
78326  *
78327  * Transfer Size amount of data For endpoint 0.
78328  *
78329  * This field is decremented every time a packet (maximum size or
78330  *
78331  * short packet) is read from the TxFIFO.
78332  *
78333  * Field Access Macros:
78334  *
78335  */
78336 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */
78337 #define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_LSB 19
78338 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */
78339 #define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_MSB 28
78340 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */
78341 #define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_WIDTH 10
78342 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field value. */
78343 #define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_SET_MSK 0x1ff80000
78344 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field value. */
78345 #define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_CLR_MSK 0xe007ffff
78346 /* The reset value of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */
78347 #define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_RESET 0x0
78348 /* Extracts the ALT_USB_DEV_DIEPTSIZ3_PKTCNT field value from a register. */
78349 #define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
78350 /* Produces a ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field value suitable for setting the register. */
78351 #define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
78352 
78353 /*
78354  * Field : mc
78355  *
78356  * Applies to IN endpoints only.
78357  *
78358  * For periodic IN endpoints, this field indicates the number of packets that must
78359  * be transmitted per microframe on the USB. The core uses this field to calculate
78360  * the data PID for isochronous IN endpoints.
78361  *
78362  * 2'b01: 1 packet
78363  *
78364  * 2'b10: 2 packets
78365  *
78366  * 2'b11: 3 packets
78367  *
78368  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
78369  * specifies the number of packets the core must fetchfor an IN endpoint before it
78370  * switches to the endpoint pointed to by the Next Endpoint field of the Device
78371  * Endpoint-n Control register (DIEPCTLn.NextEp)
78372  *
78373  * Field Enumeration Values:
78374  *
78375  * Enum | Value | Description
78376  * :------------------------------------|:------|:------------
78377  * ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTONE | 0x1 | 1 packet
78378  * ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTWO | 0x2 | 2 packets
78379  * ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTHREE | 0x3 | 3 packets
78380  *
78381  * Field Access Macros:
78382  *
78383  */
78384 /*
78385  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ3_MC
78386  *
78387  * 1 packet
78388  */
78389 #define ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTONE 0x1
78390 /*
78391  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ3_MC
78392  *
78393  * 2 packets
78394  */
78395 #define ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTWO 0x2
78396 /*
78397  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ3_MC
78398  *
78399  * 3 packets
78400  */
78401 #define ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTHREE 0x3
78402 
78403 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */
78404 #define ALT_USB_DEV_DIEPTSIZ3_MC_LSB 29
78405 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */
78406 #define ALT_USB_DEV_DIEPTSIZ3_MC_MSB 30
78407 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */
78408 #define ALT_USB_DEV_DIEPTSIZ3_MC_WIDTH 2
78409 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ3_MC register field value. */
78410 #define ALT_USB_DEV_DIEPTSIZ3_MC_SET_MSK 0x60000000
78411 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ3_MC register field value. */
78412 #define ALT_USB_DEV_DIEPTSIZ3_MC_CLR_MSK 0x9fffffff
78413 /* The reset value of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */
78414 #define ALT_USB_DEV_DIEPTSIZ3_MC_RESET 0x0
78415 /* Extracts the ALT_USB_DEV_DIEPTSIZ3_MC field value from a register. */
78416 #define ALT_USB_DEV_DIEPTSIZ3_MC_GET(value) (((value) & 0x60000000) >> 29)
78417 /* Produces a ALT_USB_DEV_DIEPTSIZ3_MC register field value suitable for setting the register. */
78418 #define ALT_USB_DEV_DIEPTSIZ3_MC_SET(value) (((value) << 29) & 0x60000000)
78419 
78420 #ifndef __ASSEMBLY__
78421 /*
78422  * WARNING: The C register and register group struct declarations are provided for
78423  * convenience and illustrative purposes. They should, however, be used with
78424  * caution as the C language standard provides no guarantees about the alignment or
78425  * atomicity of device memory accesses. The recommended practice for writing
78426  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
78427  * alt_write_word() functions.
78428  *
78429  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ3.
78430  */
78431 struct ALT_USB_DEV_DIEPTSIZ3_s
78432 {
78433  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ3_XFERSIZE */
78434  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ3_PKTCNT */
78435  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ3_MC */
78436  uint32_t : 1; /* *UNDEFINED* */
78437 };
78438 
78439 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ3. */
78440 typedef volatile struct ALT_USB_DEV_DIEPTSIZ3_s ALT_USB_DEV_DIEPTSIZ3_t;
78441 #endif /* __ASSEMBLY__ */
78442 
78443 /* The reset value of the ALT_USB_DEV_DIEPTSIZ3 register. */
78444 #define ALT_USB_DEV_DIEPTSIZ3_RESET 0x00000000
78445 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ3 register from the beginning of the component. */
78446 #define ALT_USB_DEV_DIEPTSIZ3_OFST 0x170
78447 /* The address of the ALT_USB_DEV_DIEPTSIZ3 register. */
78448 #define ALT_USB_DEV_DIEPTSIZ3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ3_OFST))
78449 
78450 /*
78451  * Register : diepdma3
78452  *
78453  * Device IN Endpoint 3 DMA Address Register
78454  *
78455  * Register Layout
78456  *
78457  * Bits | Access | Reset | Description
78458  * :-------|:-------|:--------|:------------------------------
78459  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA3_DIEPDMA3
78460  *
78461  */
78462 /*
78463  * Field : diepdma3
78464  *
78465  * Holds the start address of the external memory for storing or fetching endpoint
78466  *
78467  * data.
78468  *
78469  * Note: For control endpoints, this field stores control OUT data packets as well
78470  * as
78471  *
78472  * SETUP transaction data packets. When more than three SETUP packets are
78473  *
78474  * received back-to-back, the SETUP data packet in the memory is overwritten.
78475  *
78476  * This register is incremented on every AHB transaction. The application can give
78477  *
78478  * only a DWORD-aligned address.
78479  *
78480  * When Scatter/Gather DMA mode is not enabled, the application programs the
78481  *
78482  * start address value in this field.
78483  *
78484  * When Scatter/Gather DMA mode is enabled, this field indicates the base
78485  *
78486  * pointer for the descriptor list.
78487  *
78488  * Field Access Macros:
78489  *
78490  */
78491 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field. */
78492 #define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_LSB 0
78493 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field. */
78494 #define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_MSB 31
78495 /* The width in bits of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field. */
78496 #define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_WIDTH 32
78497 /* The mask used to set the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field value. */
78498 #define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_SET_MSK 0xffffffff
78499 /* The mask used to clear the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field value. */
78500 #define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_CLR_MSK 0x00000000
78501 /* The reset value of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field is UNKNOWN. */
78502 #define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_RESET 0x0
78503 /* Extracts the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 field value from a register. */
78504 #define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_GET(value) (((value) & 0xffffffff) >> 0)
78505 /* Produces a ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field value suitable for setting the register. */
78506 #define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_SET(value) (((value) << 0) & 0xffffffff)
78507 
78508 #ifndef __ASSEMBLY__
78509 /*
78510  * WARNING: The C register and register group struct declarations are provided for
78511  * convenience and illustrative purposes. They should, however, be used with
78512  * caution as the C language standard provides no guarantees about the alignment or
78513  * atomicity of device memory accesses. The recommended practice for writing
78514  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
78515  * alt_write_word() functions.
78516  *
78517  * The struct declaration for register ALT_USB_DEV_DIEPDMA3.
78518  */
78519 struct ALT_USB_DEV_DIEPDMA3_s
78520 {
78521  uint32_t diepdma3 : 32; /* ALT_USB_DEV_DIEPDMA3_DIEPDMA3 */
78522 };
78523 
78524 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA3. */
78525 typedef volatile struct ALT_USB_DEV_DIEPDMA3_s ALT_USB_DEV_DIEPDMA3_t;
78526 #endif /* __ASSEMBLY__ */
78527 
78528 /* The reset value of the ALT_USB_DEV_DIEPDMA3 register. */
78529 #define ALT_USB_DEV_DIEPDMA3_RESET 0x00000000
78530 /* The byte offset of the ALT_USB_DEV_DIEPDMA3 register from the beginning of the component. */
78531 #define ALT_USB_DEV_DIEPDMA3_OFST 0x174
78532 /* The address of the ALT_USB_DEV_DIEPDMA3 register. */
78533 #define ALT_USB_DEV_DIEPDMA3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA3_OFST))
78534 
78535 /*
78536  * Register : dtxfsts3
78537  *
78538  * Device IN Endpoint Transmit FIFO Status Register 3
78539  *
78540  * Register Layout
78541  *
78542  * Bits | Access | Reset | Description
78543  * :--------|:-------|:-------|:-------------------------------------
78544  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL
78545  * [31:16] | ??? | 0x0 | *UNDEFINED*
78546  *
78547  */
78548 /*
78549  * Field : ineptxfspcavail
78550  *
78551  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
78552  *
78553  * Indicates the amount of free space available in the Endpoint
78554  *
78555  * TxFIFO.
78556  *
78557  * Values are in terms of 32-bit words.
78558  *
78559  * 16'h0: Endpoint TxFIFO is full
78560  *
78561  * 16'h1: 1 word available
78562  *
78563  * 16'h2: 2 words available
78564  *
78565  * 16'hn: n words available (where 0 n 32,768)
78566  *
78567  * 16'h8000: 32,768 words available
78568  *
78569  * Others: Reserved
78570  *
78571  * Field Access Macros:
78572  *
78573  */
78574 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */
78575 #define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_LSB 0
78576 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */
78577 #define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_MSB 15
78578 /* The width in bits of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */
78579 #define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_WIDTH 16
78580 /* The mask used to set the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field value. */
78581 #define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
78582 /* The mask used to clear the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field value. */
78583 #define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
78584 /* The reset value of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */
78585 #define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_RESET 0x2000
78586 /* Extracts the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL field value from a register. */
78587 #define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
78588 /* Produces a ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field value suitable for setting the register. */
78589 #define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
78590 
78591 #ifndef __ASSEMBLY__
78592 /*
78593  * WARNING: The C register and register group struct declarations are provided for
78594  * convenience and illustrative purposes. They should, however, be used with
78595  * caution as the C language standard provides no guarantees about the alignment or
78596  * atomicity of device memory accesses. The recommended practice for writing
78597  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
78598  * alt_write_word() functions.
78599  *
78600  * The struct declaration for register ALT_USB_DEV_DTXFSTS3.
78601  */
78602 struct ALT_USB_DEV_DTXFSTS3_s
78603 {
78604  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL */
78605  uint32_t : 16; /* *UNDEFINED* */
78606 };
78607 
78608 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS3. */
78609 typedef volatile struct ALT_USB_DEV_DTXFSTS3_s ALT_USB_DEV_DTXFSTS3_t;
78610 #endif /* __ASSEMBLY__ */
78611 
78612 /* The reset value of the ALT_USB_DEV_DTXFSTS3 register. */
78613 #define ALT_USB_DEV_DTXFSTS3_RESET 0x00002000
78614 /* The byte offset of the ALT_USB_DEV_DTXFSTS3 register from the beginning of the component. */
78615 #define ALT_USB_DEV_DTXFSTS3_OFST 0x178
78616 /* The address of the ALT_USB_DEV_DTXFSTS3 register. */
78617 #define ALT_USB_DEV_DTXFSTS3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS3_OFST))
78618 
78619 /*
78620  * Register : diepdmab3
78621  *
78622  * Device IN Endpoint 3 Buffer Address Register
78623  *
78624  * Register Layout
78625  *
78626  * Bits | Access | Reset | Description
78627  * :-------|:-------|:--------|:--------------------------------
78628  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3
78629  *
78630  */
78631 /*
78632  * Field : diepdmab3
78633  *
78634  * Holds the current buffer address.This register is updated as and when the data
78635  *
78636  * transfer for the corresponding end point is in progress.
78637  *
78638  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
78639  * is
78640  *
78641  * reserved.
78642  *
78643  * Field Access Macros:
78644  *
78645  */
78646 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field. */
78647 #define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_LSB 0
78648 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field. */
78649 #define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_MSB 31
78650 /* The width in bits of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field. */
78651 #define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_WIDTH 32
78652 /* The mask used to set the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field value. */
78653 #define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_SET_MSK 0xffffffff
78654 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field value. */
78655 #define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_CLR_MSK 0x00000000
78656 /* The reset value of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field is UNKNOWN. */
78657 #define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_RESET 0x0
78658 /* Extracts the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 field value from a register. */
78659 #define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_GET(value) (((value) & 0xffffffff) >> 0)
78660 /* Produces a ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field value suitable for setting the register. */
78661 #define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_SET(value) (((value) << 0) & 0xffffffff)
78662 
78663 #ifndef __ASSEMBLY__
78664 /*
78665  * WARNING: The C register and register group struct declarations are provided for
78666  * convenience and illustrative purposes. They should, however, be used with
78667  * caution as the C language standard provides no guarantees about the alignment or
78668  * atomicity of device memory accesses. The recommended practice for writing
78669  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
78670  * alt_write_word() functions.
78671  *
78672  * The struct declaration for register ALT_USB_DEV_DIEPDMAB3.
78673  */
78674 struct ALT_USB_DEV_DIEPDMAB3_s
78675 {
78676  const uint32_t diepdmab3 : 32; /* ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 */
78677 };
78678 
78679 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB3. */
78680 typedef volatile struct ALT_USB_DEV_DIEPDMAB3_s ALT_USB_DEV_DIEPDMAB3_t;
78681 #endif /* __ASSEMBLY__ */
78682 
78683 /* The reset value of the ALT_USB_DEV_DIEPDMAB3 register. */
78684 #define ALT_USB_DEV_DIEPDMAB3_RESET 0x00000000
78685 /* The byte offset of the ALT_USB_DEV_DIEPDMAB3 register from the beginning of the component. */
78686 #define ALT_USB_DEV_DIEPDMAB3_OFST 0x17c
78687 /* The address of the ALT_USB_DEV_DIEPDMAB3 register. */
78688 #define ALT_USB_DEV_DIEPDMAB3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB3_OFST))
78689 
78690 /*
78691  * Register : diepctl4
78692  *
78693  * Device Control IN Endpoint 4 Control Register
78694  *
78695  * Register Layout
78696  *
78697  * Bits | Access | Reset | Description
78698  * :--------|:---------|:------|:------------------------------
78699  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL4_MPS
78700  * [14:11] | ??? | 0x0 | *UNDEFINED*
78701  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL4_USBACTEP
78702  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL4_DPID
78703  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL4_NAKSTS
78704  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL4_EPTYPE
78705  * [20] | ??? | 0x0 | *UNDEFINED*
78706  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL4_STALL
78707  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL4_TXFNUM
78708  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL4_CNAK
78709  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL4_SNAK
78710  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL4_SETD0PID
78711  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL4_SETD1PID
78712  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL4_EPDIS
78713  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL4_EPENA
78714  *
78715  */
78716 /*
78717  * Field : mps
78718  *
78719  * Maximum Packet Size (MPS)
78720  *
78721  * The application must program this field with the maximum packet size for the
78722  * current
78723  *
78724  * logical endpoint. This value is in bytes.
78725  *
78726  * Field Access Macros:
78727  *
78728  */
78729 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_MPS register field. */
78730 #define ALT_USB_DEV_DIEPCTL4_MPS_LSB 0
78731 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_MPS register field. */
78732 #define ALT_USB_DEV_DIEPCTL4_MPS_MSB 10
78733 /* The width in bits of the ALT_USB_DEV_DIEPCTL4_MPS register field. */
78734 #define ALT_USB_DEV_DIEPCTL4_MPS_WIDTH 11
78735 /* The mask used to set the ALT_USB_DEV_DIEPCTL4_MPS register field value. */
78736 #define ALT_USB_DEV_DIEPCTL4_MPS_SET_MSK 0x000007ff
78737 /* The mask used to clear the ALT_USB_DEV_DIEPCTL4_MPS register field value. */
78738 #define ALT_USB_DEV_DIEPCTL4_MPS_CLR_MSK 0xfffff800
78739 /* The reset value of the ALT_USB_DEV_DIEPCTL4_MPS register field. */
78740 #define ALT_USB_DEV_DIEPCTL4_MPS_RESET 0x0
78741 /* Extracts the ALT_USB_DEV_DIEPCTL4_MPS field value from a register. */
78742 #define ALT_USB_DEV_DIEPCTL4_MPS_GET(value) (((value) & 0x000007ff) >> 0)
78743 /* Produces a ALT_USB_DEV_DIEPCTL4_MPS register field value suitable for setting the register. */
78744 #define ALT_USB_DEV_DIEPCTL4_MPS_SET(value) (((value) << 0) & 0x000007ff)
78745 
78746 /*
78747  * Field : usbactep
78748  *
78749  * USB Active Endpoint (USBActEP)
78750  *
78751  * Indicates whether this endpoint is active in the current configuration and
78752  * interface. The
78753  *
78754  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
78755  * reset. After
78756  *
78757  * receiving the SetConfiguration and SetInterface commands, the application must
78758  *
78759  * program endpoint registers accordingly and set this bit.
78760  *
78761  * Field Enumeration Values:
78762  *
78763  * Enum | Value | Description
78764  * :-------------------------------------|:------|:--------------------
78765  * ALT_USB_DEV_DIEPCTL4_USBACTEP_E_DISD | 0x0 | Not Active
78766  * ALT_USB_DEV_DIEPCTL4_USBACTEP_E_END | 0x1 | USB Active Endpoint
78767  *
78768  * Field Access Macros:
78769  *
78770  */
78771 /*
78772  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_USBACTEP
78773  *
78774  * Not Active
78775  */
78776 #define ALT_USB_DEV_DIEPCTL4_USBACTEP_E_DISD 0x0
78777 /*
78778  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_USBACTEP
78779  *
78780  * USB Active Endpoint
78781  */
78782 #define ALT_USB_DEV_DIEPCTL4_USBACTEP_E_END 0x1
78783 
78784 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */
78785 #define ALT_USB_DEV_DIEPCTL4_USBACTEP_LSB 15
78786 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */
78787 #define ALT_USB_DEV_DIEPCTL4_USBACTEP_MSB 15
78788 /* The width in bits of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */
78789 #define ALT_USB_DEV_DIEPCTL4_USBACTEP_WIDTH 1
78790 /* The mask used to set the ALT_USB_DEV_DIEPCTL4_USBACTEP register field value. */
78791 #define ALT_USB_DEV_DIEPCTL4_USBACTEP_SET_MSK 0x00008000
78792 /* The mask used to clear the ALT_USB_DEV_DIEPCTL4_USBACTEP register field value. */
78793 #define ALT_USB_DEV_DIEPCTL4_USBACTEP_CLR_MSK 0xffff7fff
78794 /* The reset value of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */
78795 #define ALT_USB_DEV_DIEPCTL4_USBACTEP_RESET 0x0
78796 /* Extracts the ALT_USB_DEV_DIEPCTL4_USBACTEP field value from a register. */
78797 #define ALT_USB_DEV_DIEPCTL4_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
78798 /* Produces a ALT_USB_DEV_DIEPCTL4_USBACTEP register field value suitable for setting the register. */
78799 #define ALT_USB_DEV_DIEPCTL4_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
78800 
78801 /*
78802  * Field : dpid
78803  *
78804  * Endpoint Data PID (DPID)
78805  *
78806  * Applies to interrupt/bulk IN and OUT endpoints only.
78807  *
78808  * Contains the PID of the packet to be received or transmitted on this endpoint.
78809  * The
78810  *
78811  * application must program the PID of the first packet to be received or
78812  * transmitted on
78813  *
78814  * this endpoint, after the endpoint is activated. The applications use the
78815  * SetD1PID and
78816  *
78817  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
78818  *
78819  * 1'b0: DATA0
78820  *
78821  * 1'b1: DATA1
78822  *
78823  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
78824  *
78825  * DMA mode.
78826  *
78827  * 1'b0 RO
78828  *
78829  * Even/Odd (Micro)Frame (EO_FrNum)
78830  *
78831  * In non-Scatter/Gather DMA mode:
78832  *
78833  * Applies to isochronous IN and OUT endpoints only.
78834  *
78835  * Indicates the (micro)frame number in which the core transmits/receives
78836  * isochronous
78837  *
78838  * data for this endpoint. The application must program the even/odd (micro) frame
78839  *
78840  * number in which it intends to transmit/receive isochronous data for this
78841  * endpoint using
78842  *
78843  * the SetEvnFr and SetOddFr fields in this register.
78844  *
78845  * 1'b0: Even (micro)frame
78846  *
78847  * 1'b1: Odd (micro)frame
78848  *
78849  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
78850  * number
78851  *
78852  * in which to send data is provided in the transmit descriptor structure. The
78853  * frame in
78854  *
78855  * which data is received is updated in receive descriptor structure.
78856  *
78857  * Field Enumeration Values:
78858  *
78859  * Enum | Value | Description
78860  * :----------------------------------|:------|:-----------------------------
78861  * ALT_USB_DEV_DIEPCTL4_DPID_E_INACT | 0x0 | Endpoint Data PID not active
78862  * ALT_USB_DEV_DIEPCTL4_DPID_E_ACT | 0x1 | Endpoint Data PID active
78863  *
78864  * Field Access Macros:
78865  *
78866  */
78867 /*
78868  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_DPID
78869  *
78870  * Endpoint Data PID not active
78871  */
78872 #define ALT_USB_DEV_DIEPCTL4_DPID_E_INACT 0x0
78873 /*
78874  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_DPID
78875  *
78876  * Endpoint Data PID active
78877  */
78878 #define ALT_USB_DEV_DIEPCTL4_DPID_E_ACT 0x1
78879 
78880 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_DPID register field. */
78881 #define ALT_USB_DEV_DIEPCTL4_DPID_LSB 16
78882 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_DPID register field. */
78883 #define ALT_USB_DEV_DIEPCTL4_DPID_MSB 16
78884 /* The width in bits of the ALT_USB_DEV_DIEPCTL4_DPID register field. */
78885 #define ALT_USB_DEV_DIEPCTL4_DPID_WIDTH 1
78886 /* The mask used to set the ALT_USB_DEV_DIEPCTL4_DPID register field value. */
78887 #define ALT_USB_DEV_DIEPCTL4_DPID_SET_MSK 0x00010000
78888 /* The mask used to clear the ALT_USB_DEV_DIEPCTL4_DPID register field value. */
78889 #define ALT_USB_DEV_DIEPCTL4_DPID_CLR_MSK 0xfffeffff
78890 /* The reset value of the ALT_USB_DEV_DIEPCTL4_DPID register field. */
78891 #define ALT_USB_DEV_DIEPCTL4_DPID_RESET 0x0
78892 /* Extracts the ALT_USB_DEV_DIEPCTL4_DPID field value from a register. */
78893 #define ALT_USB_DEV_DIEPCTL4_DPID_GET(value) (((value) & 0x00010000) >> 16)
78894 /* Produces a ALT_USB_DEV_DIEPCTL4_DPID register field value suitable for setting the register. */
78895 #define ALT_USB_DEV_DIEPCTL4_DPID_SET(value) (((value) << 16) & 0x00010000)
78896 
78897 /*
78898  * Field : naksts
78899  *
78900  * NAK Status (NAKSts)
78901  *
78902  * Indicates the following:
78903  *
78904  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
78905  *
78906  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
78907  *
78908  * When either the application or the core sets this bit:
78909  *
78910  * The core stops receiving any data on an OUT endpoint, even if there is space in
78911  *
78912  * the RxFIFO to accommodate the incoming packet.
78913  *
78914  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
78915  *
78916  * endpoint, even if there data is available in the TxFIFO.
78917  *
78918  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
78919  *
78920  * if there data is available in the TxFIFO.
78921  *
78922  * Irrespective of this bit's setting, the core always responds to SETUP data
78923  * packets with
78924  *
78925  * an ACK handshake.
78926  *
78927  * Field Enumeration Values:
78928  *
78929  * Enum | Value | Description
78930  * :-------------------------------------|:------|:------------------------------------------------
78931  * ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
78932  * : | | based on the FIFO status
78933  * ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
78934  * : | | endpoint
78935  *
78936  * Field Access Macros:
78937  *
78938  */
78939 /*
78940  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_NAKSTS
78941  *
78942  * The core is transmitting non-NAK handshakes based on the FIFO status
78943  */
78944 #define ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NONNAK 0x0
78945 /*
78946  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_NAKSTS
78947  *
78948  * The core is transmitting NAK handshakes on this endpoint
78949  */
78950 #define ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NAK 0x1
78951 
78952 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */
78953 #define ALT_USB_DEV_DIEPCTL4_NAKSTS_LSB 17
78954 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */
78955 #define ALT_USB_DEV_DIEPCTL4_NAKSTS_MSB 17
78956 /* The width in bits of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */
78957 #define ALT_USB_DEV_DIEPCTL4_NAKSTS_WIDTH 1
78958 /* The mask used to set the ALT_USB_DEV_DIEPCTL4_NAKSTS register field value. */
78959 #define ALT_USB_DEV_DIEPCTL4_NAKSTS_SET_MSK 0x00020000
78960 /* The mask used to clear the ALT_USB_DEV_DIEPCTL4_NAKSTS register field value. */
78961 #define ALT_USB_DEV_DIEPCTL4_NAKSTS_CLR_MSK 0xfffdffff
78962 /* The reset value of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */
78963 #define ALT_USB_DEV_DIEPCTL4_NAKSTS_RESET 0x0
78964 /* Extracts the ALT_USB_DEV_DIEPCTL4_NAKSTS field value from a register. */
78965 #define ALT_USB_DEV_DIEPCTL4_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
78966 /* Produces a ALT_USB_DEV_DIEPCTL4_NAKSTS register field value suitable for setting the register. */
78967 #define ALT_USB_DEV_DIEPCTL4_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
78968 
78969 /*
78970  * Field : eptype
78971  *
78972  * Endpoint Type (EPType)
78973  *
78974  * This is the transfer type supported by this logical endpoint.
78975  *
78976  * 2'b00: Control
78977  *
78978  * 2'b01: Isochronous
78979  *
78980  * 2'b10: Bulk
78981  *
78982  * 2'b11: Interrupt
78983  *
78984  * Field Enumeration Values:
78985  *
78986  * Enum | Value | Description
78987  * :------------------------------------------|:------|:------------
78988  * ALT_USB_DEV_DIEPCTL4_EPTYPE_E_CTL | 0x0 | Control
78989  * ALT_USB_DEV_DIEPCTL4_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
78990  * ALT_USB_DEV_DIEPCTL4_EPTYPE_E_BULK | 0x2 | Bulk
78991  * ALT_USB_DEV_DIEPCTL4_EPTYPE_E_INTERRUP | 0x3 | Interrupt
78992  *
78993  * Field Access Macros:
78994  *
78995  */
78996 /*
78997  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE
78998  *
78999  * Control
79000  */
79001 #define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_CTL 0x0
79002 /*
79003  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE
79004  *
79005  * Isochronous
79006  */
79007 #define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_ISOCHRONOUS 0x1
79008 /*
79009  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE
79010  *
79011  * Bulk
79012  */
79013 #define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_BULK 0x2
79014 /*
79015  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE
79016  *
79017  * Interrupt
79018  */
79019 #define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_INTERRUP 0x3
79020 
79021 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */
79022 #define ALT_USB_DEV_DIEPCTL4_EPTYPE_LSB 18
79023 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */
79024 #define ALT_USB_DEV_DIEPCTL4_EPTYPE_MSB 19
79025 /* The width in bits of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */
79026 #define ALT_USB_DEV_DIEPCTL4_EPTYPE_WIDTH 2
79027 /* The mask used to set the ALT_USB_DEV_DIEPCTL4_EPTYPE register field value. */
79028 #define ALT_USB_DEV_DIEPCTL4_EPTYPE_SET_MSK 0x000c0000
79029 /* The mask used to clear the ALT_USB_DEV_DIEPCTL4_EPTYPE register field value. */
79030 #define ALT_USB_DEV_DIEPCTL4_EPTYPE_CLR_MSK 0xfff3ffff
79031 /* The reset value of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */
79032 #define ALT_USB_DEV_DIEPCTL4_EPTYPE_RESET 0x0
79033 /* Extracts the ALT_USB_DEV_DIEPCTL4_EPTYPE field value from a register. */
79034 #define ALT_USB_DEV_DIEPCTL4_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
79035 /* Produces a ALT_USB_DEV_DIEPCTL4_EPTYPE register field value suitable for setting the register. */
79036 #define ALT_USB_DEV_DIEPCTL4_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
79037 
79038 /*
79039  * Field : stall
79040  *
79041  * STALL Handshake (Stall)
79042  *
79043  * Applies to non-control, non-isochronous IN and OUT endpoints only.
79044  *
79045  * The application sets this bit to stall all tokens from the USB host to this
79046  * endpoint. If a
79047  *
79048  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
79049  * bit, the
79050  *
79051  * STALL bit takes priority. Only the application can clear this bit, never the
79052  * core.
79053  *
79054  * 1'b0 R_W
79055  *
79056  * Applies to control endpoints only.
79057  *
79058  * The application can only set this bit, and the core clears it, when a SETUP
79059  * token is
79060  *
79061  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
79062  * OUT
79063  *
79064  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
79065  * this bit's
79066  *
79067  * setting, the core always responds to SETUP data packets with an ACK handshake.
79068  *
79069  * Field Enumeration Values:
79070  *
79071  * Enum | Value | Description
79072  * :-----------------------------------|:------|:----------------------------
79073  * ALT_USB_DEV_DIEPCTL4_STALL_E_INACT | 0x0 | STALL All Tokens not active
79074  * ALT_USB_DEV_DIEPCTL4_STALL_E_ACT | 0x1 | STALL All Tokens active
79075  *
79076  * Field Access Macros:
79077  *
79078  */
79079 /*
79080  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_STALL
79081  *
79082  * STALL All Tokens not active
79083  */
79084 #define ALT_USB_DEV_DIEPCTL4_STALL_E_INACT 0x0
79085 /*
79086  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_STALL
79087  *
79088  * STALL All Tokens active
79089  */
79090 #define ALT_USB_DEV_DIEPCTL4_STALL_E_ACT 0x1
79091 
79092 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_STALL register field. */
79093 #define ALT_USB_DEV_DIEPCTL4_STALL_LSB 21
79094 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_STALL register field. */
79095 #define ALT_USB_DEV_DIEPCTL4_STALL_MSB 21
79096 /* The width in bits of the ALT_USB_DEV_DIEPCTL4_STALL register field. */
79097 #define ALT_USB_DEV_DIEPCTL4_STALL_WIDTH 1
79098 /* The mask used to set the ALT_USB_DEV_DIEPCTL4_STALL register field value. */
79099 #define ALT_USB_DEV_DIEPCTL4_STALL_SET_MSK 0x00200000
79100 /* The mask used to clear the ALT_USB_DEV_DIEPCTL4_STALL register field value. */
79101 #define ALT_USB_DEV_DIEPCTL4_STALL_CLR_MSK 0xffdfffff
79102 /* The reset value of the ALT_USB_DEV_DIEPCTL4_STALL register field. */
79103 #define ALT_USB_DEV_DIEPCTL4_STALL_RESET 0x0
79104 /* Extracts the ALT_USB_DEV_DIEPCTL4_STALL field value from a register. */
79105 #define ALT_USB_DEV_DIEPCTL4_STALL_GET(value) (((value) & 0x00200000) >> 21)
79106 /* Produces a ALT_USB_DEV_DIEPCTL4_STALL register field value suitable for setting the register. */
79107 #define ALT_USB_DEV_DIEPCTL4_STALL_SET(value) (((value) << 21) & 0x00200000)
79108 
79109 /*
79110  * Field : txfnum
79111  *
79112  * TxFIFO Number (TxFNum)
79113  *
79114  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
79115  *
79116  * endpoints must map this to the corresponding Periodic TxFIFO number.
79117  *
79118  * 4'h0: Non-Periodic TxFIFO
79119  *
79120  * Others: Specified Periodic TxFIFO.number
79121  *
79122  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
79123  *
79124  * applications such as mass storage. The core treats an IN endpoint as a non-
79125  * periodic
79126  *
79127  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
79128  * must be
79129  *
79130  * allocated for an interrupt IN endpoint, and the number of this
79131  *
79132  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
79133  *
79134  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
79135  *
79136  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
79137  *
79138  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
79139  *
79140  * This field is valid only for IN endpoints.
79141  *
79142  * Field Access Macros:
79143  *
79144  */
79145 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */
79146 #define ALT_USB_DEV_DIEPCTL4_TXFNUM_LSB 22
79147 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */
79148 #define ALT_USB_DEV_DIEPCTL4_TXFNUM_MSB 25
79149 /* The width in bits of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */
79150 #define ALT_USB_DEV_DIEPCTL4_TXFNUM_WIDTH 4
79151 /* The mask used to set the ALT_USB_DEV_DIEPCTL4_TXFNUM register field value. */
79152 #define ALT_USB_DEV_DIEPCTL4_TXFNUM_SET_MSK 0x03c00000
79153 /* The mask used to clear the ALT_USB_DEV_DIEPCTL4_TXFNUM register field value. */
79154 #define ALT_USB_DEV_DIEPCTL4_TXFNUM_CLR_MSK 0xfc3fffff
79155 /* The reset value of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */
79156 #define ALT_USB_DEV_DIEPCTL4_TXFNUM_RESET 0x0
79157 /* Extracts the ALT_USB_DEV_DIEPCTL4_TXFNUM field value from a register. */
79158 #define ALT_USB_DEV_DIEPCTL4_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
79159 /* Produces a ALT_USB_DEV_DIEPCTL4_TXFNUM register field value suitable for setting the register. */
79160 #define ALT_USB_DEV_DIEPCTL4_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
79161 
79162 /*
79163  * Field : cnak
79164  *
79165  * Clear NAK (CNAK)
79166  *
79167  * A write to this bit clears the NAK bit For the endpoint.
79168  *
79169  * Field Enumeration Values:
79170  *
79171  * Enum | Value | Description
79172  * :----------------------------------|:------|:-------------
79173  * ALT_USB_DEV_DIEPCTL4_CNAK_E_INACT | 0x0 | No Clear NAK
79174  * ALT_USB_DEV_DIEPCTL4_CNAK_E_ACT | 0x1 | Clear NAK
79175  *
79176  * Field Access Macros:
79177  *
79178  */
79179 /*
79180  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_CNAK
79181  *
79182  * No Clear NAK
79183  */
79184 #define ALT_USB_DEV_DIEPCTL4_CNAK_E_INACT 0x0
79185 /*
79186  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_CNAK
79187  *
79188  * Clear NAK
79189  */
79190 #define ALT_USB_DEV_DIEPCTL4_CNAK_E_ACT 0x1
79191 
79192 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */
79193 #define ALT_USB_DEV_DIEPCTL4_CNAK_LSB 26
79194 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */
79195 #define ALT_USB_DEV_DIEPCTL4_CNAK_MSB 26
79196 /* The width in bits of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */
79197 #define ALT_USB_DEV_DIEPCTL4_CNAK_WIDTH 1
79198 /* The mask used to set the ALT_USB_DEV_DIEPCTL4_CNAK register field value. */
79199 #define ALT_USB_DEV_DIEPCTL4_CNAK_SET_MSK 0x04000000
79200 /* The mask used to clear the ALT_USB_DEV_DIEPCTL4_CNAK register field value. */
79201 #define ALT_USB_DEV_DIEPCTL4_CNAK_CLR_MSK 0xfbffffff
79202 /* The reset value of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */
79203 #define ALT_USB_DEV_DIEPCTL4_CNAK_RESET 0x0
79204 /* Extracts the ALT_USB_DEV_DIEPCTL4_CNAK field value from a register. */
79205 #define ALT_USB_DEV_DIEPCTL4_CNAK_GET(value) (((value) & 0x04000000) >> 26)
79206 /* Produces a ALT_USB_DEV_DIEPCTL4_CNAK register field value suitable for setting the register. */
79207 #define ALT_USB_DEV_DIEPCTL4_CNAK_SET(value) (((value) << 26) & 0x04000000)
79208 
79209 /*
79210  * Field : snak
79211  *
79212  * Set NAK (SNAK)
79213  *
79214  * A write to this bit sets the NAK bit For the endpoint.
79215  *
79216  * Using this bit, the application can control the transmission of NAK
79217  *
79218  * handshakes on an endpoint. The core can also Set this bit For an
79219  *
79220  * endpoint after a SETUP packet is received on that endpoint.
79221  *
79222  * Field Enumeration Values:
79223  *
79224  * Enum | Value | Description
79225  * :----------------------------------|:------|:------------
79226  * ALT_USB_DEV_DIEPCTL4_SNAK_E_INACT | 0x0 | No Set NAK
79227  * ALT_USB_DEV_DIEPCTL4_SNAK_E_ACT | 0x1 | Set NAK
79228  *
79229  * Field Access Macros:
79230  *
79231  */
79232 /*
79233  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SNAK
79234  *
79235  * No Set NAK
79236  */
79237 #define ALT_USB_DEV_DIEPCTL4_SNAK_E_INACT 0x0
79238 /*
79239  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SNAK
79240  *
79241  * Set NAK
79242  */
79243 #define ALT_USB_DEV_DIEPCTL4_SNAK_E_ACT 0x1
79244 
79245 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */
79246 #define ALT_USB_DEV_DIEPCTL4_SNAK_LSB 27
79247 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */
79248 #define ALT_USB_DEV_DIEPCTL4_SNAK_MSB 27
79249 /* The width in bits of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */
79250 #define ALT_USB_DEV_DIEPCTL4_SNAK_WIDTH 1
79251 /* The mask used to set the ALT_USB_DEV_DIEPCTL4_SNAK register field value. */
79252 #define ALT_USB_DEV_DIEPCTL4_SNAK_SET_MSK 0x08000000
79253 /* The mask used to clear the ALT_USB_DEV_DIEPCTL4_SNAK register field value. */
79254 #define ALT_USB_DEV_DIEPCTL4_SNAK_CLR_MSK 0xf7ffffff
79255 /* The reset value of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */
79256 #define ALT_USB_DEV_DIEPCTL4_SNAK_RESET 0x0
79257 /* Extracts the ALT_USB_DEV_DIEPCTL4_SNAK field value from a register. */
79258 #define ALT_USB_DEV_DIEPCTL4_SNAK_GET(value) (((value) & 0x08000000) >> 27)
79259 /* Produces a ALT_USB_DEV_DIEPCTL4_SNAK register field value suitable for setting the register. */
79260 #define ALT_USB_DEV_DIEPCTL4_SNAK_SET(value) (((value) << 27) & 0x08000000)
79261 
79262 /*
79263  * Field : setd0pid
79264  *
79265  * Set DATA0 PID (SetD0PID)
79266  *
79267  * Applies to interrupt/bulk IN and OUT endpoints only.
79268  *
79269  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
79270  * to DATA0.
79271  *
79272  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
79273  *
79274  * DMA mode.
79275  *
79276  * 1'b0 WO
79277  *
79278  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
79279  *
79280  * Applies to isochronous IN and OUT endpoints only.
79281  *
79282  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
79283  * (micro)
79284  *
79285  * frame.
79286  *
79287  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
79288  * number
79289  *
79290  * in which to send data is in the transmit descriptor structure. The frame in
79291  * which to
79292  *
79293  * receive data is updated in receive descriptor structure.
79294  *
79295  * Field Enumeration Values:
79296  *
79297  * Enum | Value | Description
79298  * :-------------------------------------|:------|:----------------------------
79299  * ALT_USB_DEV_DIEPCTL4_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
79300  * ALT_USB_DEV_DIEPCTL4_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
79301  *
79302  * Field Access Macros:
79303  *
79304  */
79305 /*
79306  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD0PID
79307  *
79308  * Disables Set DATA0 PID
79309  */
79310 #define ALT_USB_DEV_DIEPCTL4_SETD0PID_E_DISD 0x0
79311 /*
79312  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD0PID
79313  *
79314  * Endpoint Data PID to DATA0)
79315  */
79316 #define ALT_USB_DEV_DIEPCTL4_SETD0PID_E_END 0x1
79317 
79318 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */
79319 #define ALT_USB_DEV_DIEPCTL4_SETD0PID_LSB 28
79320 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */
79321 #define ALT_USB_DEV_DIEPCTL4_SETD0PID_MSB 28
79322 /* The width in bits of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */
79323 #define ALT_USB_DEV_DIEPCTL4_SETD0PID_WIDTH 1
79324 /* The mask used to set the ALT_USB_DEV_DIEPCTL4_SETD0PID register field value. */
79325 #define ALT_USB_DEV_DIEPCTL4_SETD0PID_SET_MSK 0x10000000
79326 /* The mask used to clear the ALT_USB_DEV_DIEPCTL4_SETD0PID register field value. */
79327 #define ALT_USB_DEV_DIEPCTL4_SETD0PID_CLR_MSK 0xefffffff
79328 /* The reset value of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */
79329 #define ALT_USB_DEV_DIEPCTL4_SETD0PID_RESET 0x0
79330 /* Extracts the ALT_USB_DEV_DIEPCTL4_SETD0PID field value from a register. */
79331 #define ALT_USB_DEV_DIEPCTL4_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
79332 /* Produces a ALT_USB_DEV_DIEPCTL4_SETD0PID register field value suitable for setting the register. */
79333 #define ALT_USB_DEV_DIEPCTL4_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
79334 
79335 /*
79336  * Field : setd1pid
79337  *
79338  * Set DATA1 PID (SetD1PID)
79339  *
79340  * Applies to interrupt/bulk IN and OUT endpoints only.
79341  *
79342  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
79343  * to DATA1.
79344  *
79345  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
79346  *
79347  * DMA mode.
79348  *
79349  * Set Odd (micro)frame (SetOddFr)
79350  *
79351  * Applies to isochronous IN and OUT endpoints only.
79352  *
79353  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
79354  *
79355  * (micro)frame.
79356  *
79357  * This field is not applicable for Scatter/Gather DMA mode.
79358  *
79359  * Field Enumeration Values:
79360  *
79361  * Enum | Value | Description
79362  * :-------------------------------------|:------|:-----------------------
79363  * ALT_USB_DEV_DIEPCTL4_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
79364  * ALT_USB_DEV_DIEPCTL4_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
79365  *
79366  * Field Access Macros:
79367  *
79368  */
79369 /*
79370  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD1PID
79371  *
79372  * Disables Set DATA1 PID
79373  */
79374 #define ALT_USB_DEV_DIEPCTL4_SETD1PID_E_DISD 0x0
79375 /*
79376  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD1PID
79377  *
79378  * Enables Set DATA1 PID
79379  */
79380 #define ALT_USB_DEV_DIEPCTL4_SETD1PID_E_END 0x1
79381 
79382 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */
79383 #define ALT_USB_DEV_DIEPCTL4_SETD1PID_LSB 29
79384 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */
79385 #define ALT_USB_DEV_DIEPCTL4_SETD1PID_MSB 29
79386 /* The width in bits of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */
79387 #define ALT_USB_DEV_DIEPCTL4_SETD1PID_WIDTH 1
79388 /* The mask used to set the ALT_USB_DEV_DIEPCTL4_SETD1PID register field value. */
79389 #define ALT_USB_DEV_DIEPCTL4_SETD1PID_SET_MSK 0x20000000
79390 /* The mask used to clear the ALT_USB_DEV_DIEPCTL4_SETD1PID register field value. */
79391 #define ALT_USB_DEV_DIEPCTL4_SETD1PID_CLR_MSK 0xdfffffff
79392 /* The reset value of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */
79393 #define ALT_USB_DEV_DIEPCTL4_SETD1PID_RESET 0x0
79394 /* Extracts the ALT_USB_DEV_DIEPCTL4_SETD1PID field value from a register. */
79395 #define ALT_USB_DEV_DIEPCTL4_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
79396 /* Produces a ALT_USB_DEV_DIEPCTL4_SETD1PID register field value suitable for setting the register. */
79397 #define ALT_USB_DEV_DIEPCTL4_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
79398 
79399 /*
79400  * Field : epdis
79401  *
79402  * Endpoint Disable (EPDis)
79403  *
79404  * Applies to IN and OUT endpoints.
79405  *
79406  * The application sets this bit to stop transmitting/receiving data on an
79407  * endpoint, even
79408  *
79409  * before the transfer for that endpoint is complete. The application must wait for
79410  * the
79411  *
79412  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
79413  * clears
79414  *
79415  * this bit before setting the Endpoint Disabled interrupt. The application must
79416  * set this bit
79417  *
79418  * only if Endpoint Enable is already set for this endpoint.
79419  *
79420  * Field Enumeration Values:
79421  *
79422  * Enum | Value | Description
79423  * :-----------------------------------|:------|:--------------------
79424  * ALT_USB_DEV_DIEPCTL4_EPDIS_E_INACT | 0x0 | No Endpoint Disable
79425  * ALT_USB_DEV_DIEPCTL4_EPDIS_E_ACT | 0x1 | Endpoint Disable
79426  *
79427  * Field Access Macros:
79428  *
79429  */
79430 /*
79431  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPDIS
79432  *
79433  * No Endpoint Disable
79434  */
79435 #define ALT_USB_DEV_DIEPCTL4_EPDIS_E_INACT 0x0
79436 /*
79437  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPDIS
79438  *
79439  * Endpoint Disable
79440  */
79441 #define ALT_USB_DEV_DIEPCTL4_EPDIS_E_ACT 0x1
79442 
79443 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */
79444 #define ALT_USB_DEV_DIEPCTL4_EPDIS_LSB 30
79445 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */
79446 #define ALT_USB_DEV_DIEPCTL4_EPDIS_MSB 30
79447 /* The width in bits of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */
79448 #define ALT_USB_DEV_DIEPCTL4_EPDIS_WIDTH 1
79449 /* The mask used to set the ALT_USB_DEV_DIEPCTL4_EPDIS register field value. */
79450 #define ALT_USB_DEV_DIEPCTL4_EPDIS_SET_MSK 0x40000000
79451 /* The mask used to clear the ALT_USB_DEV_DIEPCTL4_EPDIS register field value. */
79452 #define ALT_USB_DEV_DIEPCTL4_EPDIS_CLR_MSK 0xbfffffff
79453 /* The reset value of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */
79454 #define ALT_USB_DEV_DIEPCTL4_EPDIS_RESET 0x0
79455 /* Extracts the ALT_USB_DEV_DIEPCTL4_EPDIS field value from a register. */
79456 #define ALT_USB_DEV_DIEPCTL4_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
79457 /* Produces a ALT_USB_DEV_DIEPCTL4_EPDIS register field value suitable for setting the register. */
79458 #define ALT_USB_DEV_DIEPCTL4_EPDIS_SET(value) (((value) << 30) & 0x40000000)
79459 
79460 /*
79461  * Field : epena
79462  *
79463  * Endpoint Enable (EPEna)
79464  *
79465  * Applies to IN and OUT endpoints.
79466  *
79467  * When Scatter/Gather DMA mode is enabled,
79468  *
79469  * For IN endpoints this bit indicates that the descriptor structure and data
79470  * buffer with
79471  *
79472  * data ready to transmit is setup.
79473  *
79474  * For OUT endpoint it indicates that the descriptor structure and data buffer to
79475  *
79476  * receive data is setup.
79477  *
79478  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
79479  *
79480  * DMA mode:
79481  *
79482  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
79483  * the
79484  *
79485  * endpoint.
79486  *
79487  * * For OUT endpoints, this bit indicates that the application has allocated the
79488  *
79489  * memory to start receiving data from the USB.
79490  *
79491  * * The core clears this bit before setting any of the following interrupts on
79492  * this
79493  *
79494  * endpoint:
79495  *
79496  * SETUP Phase Done
79497  *
79498  * Endpoint Disabled
79499  *
79500  * Transfer Completed
79501  *
79502  * Note: For control endpoints in DMA mode, this bit must be set to be able to
79503  * transfer
79504  *
79505  * SETUP data packets in memory.
79506  *
79507  * Field Enumeration Values:
79508  *
79509  * Enum | Value | Description
79510  * :-----------------------------------|:------|:-------------------------
79511  * ALT_USB_DEV_DIEPCTL4_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
79512  * ALT_USB_DEV_DIEPCTL4_EPENA_E_ACT | 0x1 | Endpoint Enable active
79513  *
79514  * Field Access Macros:
79515  *
79516  */
79517 /*
79518  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPENA
79519  *
79520  * Endpoint Enable inactive
79521  */
79522 #define ALT_USB_DEV_DIEPCTL4_EPENA_E_INACT 0x0
79523 /*
79524  * Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPENA
79525  *
79526  * Endpoint Enable active
79527  */
79528 #define ALT_USB_DEV_DIEPCTL4_EPENA_E_ACT 0x1
79529 
79530 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */
79531 #define ALT_USB_DEV_DIEPCTL4_EPENA_LSB 31
79532 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */
79533 #define ALT_USB_DEV_DIEPCTL4_EPENA_MSB 31
79534 /* The width in bits of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */
79535 #define ALT_USB_DEV_DIEPCTL4_EPENA_WIDTH 1
79536 /* The mask used to set the ALT_USB_DEV_DIEPCTL4_EPENA register field value. */
79537 #define ALT_USB_DEV_DIEPCTL4_EPENA_SET_MSK 0x80000000
79538 /* The mask used to clear the ALT_USB_DEV_DIEPCTL4_EPENA register field value. */
79539 #define ALT_USB_DEV_DIEPCTL4_EPENA_CLR_MSK 0x7fffffff
79540 /* The reset value of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */
79541 #define ALT_USB_DEV_DIEPCTL4_EPENA_RESET 0x0
79542 /* Extracts the ALT_USB_DEV_DIEPCTL4_EPENA field value from a register. */
79543 #define ALT_USB_DEV_DIEPCTL4_EPENA_GET(value) (((value) & 0x80000000) >> 31)
79544 /* Produces a ALT_USB_DEV_DIEPCTL4_EPENA register field value suitable for setting the register. */
79545 #define ALT_USB_DEV_DIEPCTL4_EPENA_SET(value) (((value) << 31) & 0x80000000)
79546 
79547 #ifndef __ASSEMBLY__
79548 /*
79549  * WARNING: The C register and register group struct declarations are provided for
79550  * convenience and illustrative purposes. They should, however, be used with
79551  * caution as the C language standard provides no guarantees about the alignment or
79552  * atomicity of device memory accesses. The recommended practice for writing
79553  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
79554  * alt_write_word() functions.
79555  *
79556  * The struct declaration for register ALT_USB_DEV_DIEPCTL4.
79557  */
79558 struct ALT_USB_DEV_DIEPCTL4_s
79559 {
79560  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL4_MPS */
79561  uint32_t : 4; /* *UNDEFINED* */
79562  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL4_USBACTEP */
79563  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL4_DPID */
79564  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL4_NAKSTS */
79565  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL4_EPTYPE */
79566  uint32_t : 1; /* *UNDEFINED* */
79567  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL4_STALL */
79568  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL4_TXFNUM */
79569  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL4_CNAK */
79570  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL4_SNAK */
79571  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL4_SETD0PID */
79572  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL4_SETD1PID */
79573  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL4_EPDIS */
79574  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL4_EPENA */
79575 };
79576 
79577 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL4. */
79578 typedef volatile struct ALT_USB_DEV_DIEPCTL4_s ALT_USB_DEV_DIEPCTL4_t;
79579 #endif /* __ASSEMBLY__ */
79580 
79581 /* The reset value of the ALT_USB_DEV_DIEPCTL4 register. */
79582 #define ALT_USB_DEV_DIEPCTL4_RESET 0x00000000
79583 /* The byte offset of the ALT_USB_DEV_DIEPCTL4 register from the beginning of the component. */
79584 #define ALT_USB_DEV_DIEPCTL4_OFST 0x180
79585 /* The address of the ALT_USB_DEV_DIEPCTL4 register. */
79586 #define ALT_USB_DEV_DIEPCTL4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL4_OFST))
79587 
79588 /*
79589  * Register : diepint4
79590  *
79591  * Device IN Endpoint 4 Interrupt Register
79592  *
79593  * Register Layout
79594  *
79595  * Bits | Access | Reset | Description
79596  * :--------|:-------|:------|:---------------------------------
79597  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_XFERCOMPL
79598  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_EPDISBLD
79599  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_AHBERR
79600  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_TMO
79601  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_INTKNTXFEMP
79602  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_INTKNEPMIS
79603  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_INEPNAKEFF
79604  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT4_TXFEMP
79605  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN
79606  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_BNAINTR
79607  * [10] | ??? | 0x0 | *UNDEFINED*
79608  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_PKTDRPSTS
79609  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_BBLEERR
79610  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_NAKINTRPT
79611  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_NYETINTRPT
79612  * [31:15] | ??? | 0x0 | *UNDEFINED*
79613  *
79614  */
79615 /*
79616  * Field : xfercompl
79617  *
79618  * Transfer Completed Interrupt (XferCompl)
79619  *
79620  * Applies to IN and OUT endpoints.
79621  *
79622  * When Scatter/Gather DMA mode is enabled
79623  *
79624  * * For IN endpoint this field indicates that the requested data
79625  *
79626  * from the descriptor is moved from external system memory
79627  *
79628  * to internal FIFO.
79629  *
79630  * * For OUT endpoint this field indicates that the requested
79631  *
79632  * data from the internal FIFO is moved to external system
79633  *
79634  * memory. This interrupt is generated only when the
79635  *
79636  * corresponding endpoint descriptor is closed, and the IOC
79637  *
79638  * bit For the corresponding descriptor is Set.
79639  *
79640  * When Scatter/Gather DMA mode is disabled, this field
79641  *
79642  * indicates that the programmed transfer is complete on the
79643  *
79644  * AHB as well as on the USB, For this endpoint.
79645  *
79646  * Field Enumeration Values:
79647  *
79648  * Enum | Value | Description
79649  * :---------------------------------------|:------|:-----------------------------
79650  * ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_INACT | 0x0 | No Interrupt
79651  * ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
79652  *
79653  * Field Access Macros:
79654  *
79655  */
79656 /*
79657  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_XFERCOMPL
79658  *
79659  * No Interrupt
79660  */
79661 #define ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_INACT 0x0
79662 /*
79663  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_XFERCOMPL
79664  *
79665  * Transfer Completed Interrupt
79666  */
79667 #define ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_ACT 0x1
79668 
79669 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */
79670 #define ALT_USB_DEV_DIEPINT4_XFERCOMPL_LSB 0
79671 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */
79672 #define ALT_USB_DEV_DIEPINT4_XFERCOMPL_MSB 0
79673 /* The width in bits of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */
79674 #define ALT_USB_DEV_DIEPINT4_XFERCOMPL_WIDTH 1
79675 /* The mask used to set the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field value. */
79676 #define ALT_USB_DEV_DIEPINT4_XFERCOMPL_SET_MSK 0x00000001
79677 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field value. */
79678 #define ALT_USB_DEV_DIEPINT4_XFERCOMPL_CLR_MSK 0xfffffffe
79679 /* The reset value of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */
79680 #define ALT_USB_DEV_DIEPINT4_XFERCOMPL_RESET 0x0
79681 /* Extracts the ALT_USB_DEV_DIEPINT4_XFERCOMPL field value from a register. */
79682 #define ALT_USB_DEV_DIEPINT4_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
79683 /* Produces a ALT_USB_DEV_DIEPINT4_XFERCOMPL register field value suitable for setting the register. */
79684 #define ALT_USB_DEV_DIEPINT4_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
79685 
79686 /*
79687  * Field : epdisbld
79688  *
79689  * Endpoint Disabled Interrupt (EPDisbld)
79690  *
79691  * Applies to IN and OUT endpoints.
79692  *
79693  * This bit indicates that the endpoint is disabled per the
79694  *
79695  * application's request.
79696  *
79697  * Field Enumeration Values:
79698  *
79699  * Enum | Value | Description
79700  * :--------------------------------------|:------|:----------------------------
79701  * ALT_USB_DEV_DIEPINT4_EPDISBLD_E_INACT | 0x0 | No Interrupt
79702  * ALT_USB_DEV_DIEPINT4_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
79703  *
79704  * Field Access Macros:
79705  *
79706  */
79707 /*
79708  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_EPDISBLD
79709  *
79710  * No Interrupt
79711  */
79712 #define ALT_USB_DEV_DIEPINT4_EPDISBLD_E_INACT 0x0
79713 /*
79714  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_EPDISBLD
79715  *
79716  * Endpoint Disabled Interrupt
79717  */
79718 #define ALT_USB_DEV_DIEPINT4_EPDISBLD_E_ACT 0x1
79719 
79720 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */
79721 #define ALT_USB_DEV_DIEPINT4_EPDISBLD_LSB 1
79722 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */
79723 #define ALT_USB_DEV_DIEPINT4_EPDISBLD_MSB 1
79724 /* The width in bits of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */
79725 #define ALT_USB_DEV_DIEPINT4_EPDISBLD_WIDTH 1
79726 /* The mask used to set the ALT_USB_DEV_DIEPINT4_EPDISBLD register field value. */
79727 #define ALT_USB_DEV_DIEPINT4_EPDISBLD_SET_MSK 0x00000002
79728 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_EPDISBLD register field value. */
79729 #define ALT_USB_DEV_DIEPINT4_EPDISBLD_CLR_MSK 0xfffffffd
79730 /* The reset value of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */
79731 #define ALT_USB_DEV_DIEPINT4_EPDISBLD_RESET 0x0
79732 /* Extracts the ALT_USB_DEV_DIEPINT4_EPDISBLD field value from a register. */
79733 #define ALT_USB_DEV_DIEPINT4_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
79734 /* Produces a ALT_USB_DEV_DIEPINT4_EPDISBLD register field value suitable for setting the register. */
79735 #define ALT_USB_DEV_DIEPINT4_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
79736 
79737 /*
79738  * Field : ahberr
79739  *
79740  * AHB Error (AHBErr)
79741  *
79742  * Applies to IN and OUT endpoints.
79743  *
79744  * This is generated only in Internal DMA mode when there is an
79745  *
79746  * AHB error during an AHB read/write. The application can read
79747  *
79748  * the corresponding endpoint DMA address register to get the
79749  *
79750  * error address.
79751  *
79752  * Field Enumeration Values:
79753  *
79754  * Enum | Value | Description
79755  * :------------------------------------|:------|:--------------------
79756  * ALT_USB_DEV_DIEPINT4_AHBERR_E_INACT | 0x0 | No Interrupt
79757  * ALT_USB_DEV_DIEPINT4_AHBERR_E_ACT | 0x1 | AHB Error interrupt
79758  *
79759  * Field Access Macros:
79760  *
79761  */
79762 /*
79763  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_AHBERR
79764  *
79765  * No Interrupt
79766  */
79767 #define ALT_USB_DEV_DIEPINT4_AHBERR_E_INACT 0x0
79768 /*
79769  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_AHBERR
79770  *
79771  * AHB Error interrupt
79772  */
79773 #define ALT_USB_DEV_DIEPINT4_AHBERR_E_ACT 0x1
79774 
79775 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */
79776 #define ALT_USB_DEV_DIEPINT4_AHBERR_LSB 2
79777 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */
79778 #define ALT_USB_DEV_DIEPINT4_AHBERR_MSB 2
79779 /* The width in bits of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */
79780 #define ALT_USB_DEV_DIEPINT4_AHBERR_WIDTH 1
79781 /* The mask used to set the ALT_USB_DEV_DIEPINT4_AHBERR register field value. */
79782 #define ALT_USB_DEV_DIEPINT4_AHBERR_SET_MSK 0x00000004
79783 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_AHBERR register field value. */
79784 #define ALT_USB_DEV_DIEPINT4_AHBERR_CLR_MSK 0xfffffffb
79785 /* The reset value of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */
79786 #define ALT_USB_DEV_DIEPINT4_AHBERR_RESET 0x0
79787 /* Extracts the ALT_USB_DEV_DIEPINT4_AHBERR field value from a register. */
79788 #define ALT_USB_DEV_DIEPINT4_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
79789 /* Produces a ALT_USB_DEV_DIEPINT4_AHBERR register field value suitable for setting the register. */
79790 #define ALT_USB_DEV_DIEPINT4_AHBERR_SET(value) (((value) << 2) & 0x00000004)
79791 
79792 /*
79793  * Field : timeout
79794  *
79795  * Timeout Condition (TimeOUT)
79796  *
79797  * In shared TX FIFO mode, applies to non-isochronous IN
79798  *
79799  * endpoints only.
79800  *
79801  * In dedicated FIFO mode, applies only to Control IN
79802  *
79803  * endpoints.
79804  *
79805  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
79806  *
79807  * asserted.
79808  *
79809  * Indicates that the core has detected a timeout condition on the
79810  *
79811  * USB For the last IN token on this endpoint.
79812  *
79813  * Field Enumeration Values:
79814  *
79815  * Enum | Value | Description
79816  * :---------------------------------|:------|:------------------
79817  * ALT_USB_DEV_DIEPINT4_TMO_E_INACT | 0x0 | No interrupt
79818  * ALT_USB_DEV_DIEPINT4_TMO_E_ACT | 0x1 | Timeout interrupy
79819  *
79820  * Field Access Macros:
79821  *
79822  */
79823 /*
79824  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TMO
79825  *
79826  * No interrupt
79827  */
79828 #define ALT_USB_DEV_DIEPINT4_TMO_E_INACT 0x0
79829 /*
79830  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TMO
79831  *
79832  * Timeout interrupy
79833  */
79834 #define ALT_USB_DEV_DIEPINT4_TMO_E_ACT 0x1
79835 
79836 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_TMO register field. */
79837 #define ALT_USB_DEV_DIEPINT4_TMO_LSB 3
79838 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_TMO register field. */
79839 #define ALT_USB_DEV_DIEPINT4_TMO_MSB 3
79840 /* The width in bits of the ALT_USB_DEV_DIEPINT4_TMO register field. */
79841 #define ALT_USB_DEV_DIEPINT4_TMO_WIDTH 1
79842 /* The mask used to set the ALT_USB_DEV_DIEPINT4_TMO register field value. */
79843 #define ALT_USB_DEV_DIEPINT4_TMO_SET_MSK 0x00000008
79844 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_TMO register field value. */
79845 #define ALT_USB_DEV_DIEPINT4_TMO_CLR_MSK 0xfffffff7
79846 /* The reset value of the ALT_USB_DEV_DIEPINT4_TMO register field. */
79847 #define ALT_USB_DEV_DIEPINT4_TMO_RESET 0x0
79848 /* Extracts the ALT_USB_DEV_DIEPINT4_TMO field value from a register. */
79849 #define ALT_USB_DEV_DIEPINT4_TMO_GET(value) (((value) & 0x00000008) >> 3)
79850 /* Produces a ALT_USB_DEV_DIEPINT4_TMO register field value suitable for setting the register. */
79851 #define ALT_USB_DEV_DIEPINT4_TMO_SET(value) (((value) << 3) & 0x00000008)
79852 
79853 /*
79854  * Field : intkntxfemp
79855  *
79856  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
79857  *
79858  * Applies to non-periodic IN endpoints only.
79859  *
79860  * Indicates that an IN token was received when the associated
79861  *
79862  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
79863  *
79864  * asserted on the endpoint For which the IN token was received.
79865  *
79866  * Field Enumeration Values:
79867  *
79868  * Enum | Value | Description
79869  * :-----------------------------------------|:------|:----------------------------
79870  * ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
79871  * ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
79872  *
79873  * Field Access Macros:
79874  *
79875  */
79876 /*
79877  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNTXFEMP
79878  *
79879  * No interrupt
79880  */
79881 #define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_INACT 0x0
79882 /*
79883  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNTXFEMP
79884  *
79885  * IN Token Received Interrupt
79886  */
79887 #define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_ACT 0x1
79888 
79889 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */
79890 #define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_LSB 4
79891 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */
79892 #define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_MSB 4
79893 /* The width in bits of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */
79894 #define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_WIDTH 1
79895 /* The mask used to set the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field value. */
79896 #define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_SET_MSK 0x00000010
79897 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field value. */
79898 #define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_CLR_MSK 0xffffffef
79899 /* The reset value of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */
79900 #define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_RESET 0x0
79901 /* Extracts the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP field value from a register. */
79902 #define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
79903 /* Produces a ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field value suitable for setting the register. */
79904 #define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
79905 
79906 /*
79907  * Field : intknepmis
79908  *
79909  * IN Token Received with EP Mismatch (INTknEPMis)
79910  *
79911  * Applies to non-periodic IN endpoints only.
79912  *
79913  * Indicates that the data in the top of the non-periodic TxFIFO
79914  *
79915  * belongs to an endpoint other than the one For which the IN token
79916  *
79917  * was received. This interrupt is asserted on the endpoint For
79918  *
79919  * which the IN token was received.
79920  *
79921  * Field Enumeration Values:
79922  *
79923  * Enum | Value | Description
79924  * :----------------------------------------|:------|:---------------------------------------------
79925  * ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_INACT | 0x0 | No interrupt
79926  * ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
79927  *
79928  * Field Access Macros:
79929  *
79930  */
79931 /*
79932  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNEPMIS
79933  *
79934  * No interrupt
79935  */
79936 #define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_INACT 0x0
79937 /*
79938  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNEPMIS
79939  *
79940  * IN Token Received with EP Mismatch interrupt
79941  */
79942 #define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_ACT 0x1
79943 
79944 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */
79945 #define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_LSB 5
79946 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */
79947 #define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_MSB 5
79948 /* The width in bits of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */
79949 #define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_WIDTH 1
79950 /* The mask used to set the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field value. */
79951 #define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_SET_MSK 0x00000020
79952 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field value. */
79953 #define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_CLR_MSK 0xffffffdf
79954 /* The reset value of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */
79955 #define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_RESET 0x0
79956 /* Extracts the ALT_USB_DEV_DIEPINT4_INTKNEPMIS field value from a register. */
79957 #define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
79958 /* Produces a ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field value suitable for setting the register. */
79959 #define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
79960 
79961 /*
79962  * Field : inepnakeff
79963  *
79964  * IN Endpoint NAK Effective (INEPNakEff)
79965  *
79966  * Applies to periodic IN endpoints only.
79967  *
79968  * This bit can be cleared when the application clears the IN
79969  *
79970  * endpoint NAK by writing to DIEPCTLn.CNAK.
79971  *
79972  * This interrupt indicates that the core has sampled the NAK bit
79973  *
79974  * Set (either by the application or by the core). The interrupt
79975  *
79976  * indicates that the IN endpoint NAK bit Set by the application has
79977  *
79978  * taken effect in the core.
79979  *
79980  * This interrupt does not guarantee that a NAK handshake is sent
79981  *
79982  * on the USB. A STALL bit takes priority over a NAK bit.
79983  *
79984  * Field Enumeration Values:
79985  *
79986  * Enum | Value | Description
79987  * :----------------------------------------|:------|:------------------------------------
79988  * ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_INACT | 0x0 | No interrupt
79989  * ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
79990  *
79991  * Field Access Macros:
79992  *
79993  */
79994 /*
79995  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INEPNAKEFF
79996  *
79997  * No interrupt
79998  */
79999 #define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_INACT 0x0
80000 /*
80001  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_INEPNAKEFF
80002  *
80003  * IN Endpoint NAK Effective interrupt
80004  */
80005 #define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_ACT 0x1
80006 
80007 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */
80008 #define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_LSB 6
80009 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */
80010 #define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_MSB 6
80011 /* The width in bits of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */
80012 #define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_WIDTH 1
80013 /* The mask used to set the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field value. */
80014 #define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_SET_MSK 0x00000040
80015 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field value. */
80016 #define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_CLR_MSK 0xffffffbf
80017 /* The reset value of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */
80018 #define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_RESET 0x0
80019 /* Extracts the ALT_USB_DEV_DIEPINT4_INEPNAKEFF field value from a register. */
80020 #define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
80021 /* Produces a ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field value suitable for setting the register. */
80022 #define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
80023 
80024 /*
80025  * Field : txfemp
80026  *
80027  * Transmit FIFO Empty (TxFEmp)
80028  *
80029  * This bit is valid only For IN Endpoints
80030  *
80031  * This interrupt is asserted when the TxFIFO For this endpoint is
80032  *
80033  * either half or completely empty. The half or completely empty
80034  *
80035  * status is determined by the TxFIFO Empty Level bit in the Core
80036  *
80037  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
80038  *
80039  * Field Enumeration Values:
80040  *
80041  * Enum | Value | Description
80042  * :------------------------------------|:------|:------------------------------
80043  * ALT_USB_DEV_DIEPINT4_TXFEMP_E_INACT | 0x0 | No interrupt
80044  * ALT_USB_DEV_DIEPINT4_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
80045  *
80046  * Field Access Macros:
80047  *
80048  */
80049 /*
80050  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFEMP
80051  *
80052  * No interrupt
80053  */
80054 #define ALT_USB_DEV_DIEPINT4_TXFEMP_E_INACT 0x0
80055 /*
80056  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFEMP
80057  *
80058  * Transmit FIFO Empty interrupt
80059  */
80060 #define ALT_USB_DEV_DIEPINT4_TXFEMP_E_ACT 0x1
80061 
80062 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */
80063 #define ALT_USB_DEV_DIEPINT4_TXFEMP_LSB 7
80064 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */
80065 #define ALT_USB_DEV_DIEPINT4_TXFEMP_MSB 7
80066 /* The width in bits of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */
80067 #define ALT_USB_DEV_DIEPINT4_TXFEMP_WIDTH 1
80068 /* The mask used to set the ALT_USB_DEV_DIEPINT4_TXFEMP register field value. */
80069 #define ALT_USB_DEV_DIEPINT4_TXFEMP_SET_MSK 0x00000080
80070 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_TXFEMP register field value. */
80071 #define ALT_USB_DEV_DIEPINT4_TXFEMP_CLR_MSK 0xffffff7f
80072 /* The reset value of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */
80073 #define ALT_USB_DEV_DIEPINT4_TXFEMP_RESET 0x1
80074 /* Extracts the ALT_USB_DEV_DIEPINT4_TXFEMP field value from a register. */
80075 #define ALT_USB_DEV_DIEPINT4_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
80076 /* Produces a ALT_USB_DEV_DIEPINT4_TXFEMP register field value suitable for setting the register. */
80077 #define ALT_USB_DEV_DIEPINT4_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
80078 
80079 /*
80080  * Field : txfifoundrn
80081  *
80082  * Fifo Underrun (TxfifoUndrn)
80083  *
80084  * Applies to IN endpoints Only
80085  *
80086  * This bit is valid only If thresholding is enabled. The core generates this
80087  * interrupt when
80088  *
80089  * it detects a transmit FIFO underrun condition For this endpoint.
80090  *
80091  * Field Enumeration Values:
80092  *
80093  * Enum | Value | Description
80094  * :-----------------------------------------|:------|:------------------------
80095  * ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
80096  * ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
80097  *
80098  * Field Access Macros:
80099  *
80100  */
80101 /*
80102  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN
80103  *
80104  * No interrupt
80105  */
80106 #define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_INACT 0x0
80107 /*
80108  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN
80109  *
80110  * Fifo Underrun interrupt
80111  */
80112 #define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_ACT 0x1
80113 
80114 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */
80115 #define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_LSB 8
80116 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */
80117 #define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_MSB 8
80118 /* The width in bits of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */
80119 #define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_WIDTH 1
80120 /* The mask used to set the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field value. */
80121 #define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_SET_MSK 0x00000100
80122 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field value. */
80123 #define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_CLR_MSK 0xfffffeff
80124 /* The reset value of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */
80125 #define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_RESET 0x0
80126 /* Extracts the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN field value from a register. */
80127 #define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
80128 /* Produces a ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field value suitable for setting the register. */
80129 #define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
80130 
80131 /*
80132  * Field : bnaintr
80133  *
80134  * BNA (Buffer Not Available) Interrupt (BNAIntr)
80135  *
80136  * This bit is valid only when Scatter/Gather DMA mode is enabled.
80137  *
80138  * The core generates this interrupt when the descriptor accessed
80139  *
80140  * is not ready For the Core to process, such as Host busy or DMA
80141  *
80142  * done
80143  *
80144  * Field Enumeration Values:
80145  *
80146  * Enum | Value | Description
80147  * :-------------------------------------|:------|:--------------
80148  * ALT_USB_DEV_DIEPINT4_BNAINTR_E_INACT | 0x0 | No interrupt
80149  * ALT_USB_DEV_DIEPINT4_BNAINTR_E_ACT | 0x1 | BNA interrupt
80150  *
80151  * Field Access Macros:
80152  *
80153  */
80154 /*
80155  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_BNAINTR
80156  *
80157  * No interrupt
80158  */
80159 #define ALT_USB_DEV_DIEPINT4_BNAINTR_E_INACT 0x0
80160 /*
80161  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_BNAINTR
80162  *
80163  * BNA interrupt
80164  */
80165 #define ALT_USB_DEV_DIEPINT4_BNAINTR_E_ACT 0x1
80166 
80167 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */
80168 #define ALT_USB_DEV_DIEPINT4_BNAINTR_LSB 9
80169 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */
80170 #define ALT_USB_DEV_DIEPINT4_BNAINTR_MSB 9
80171 /* The width in bits of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */
80172 #define ALT_USB_DEV_DIEPINT4_BNAINTR_WIDTH 1
80173 /* The mask used to set the ALT_USB_DEV_DIEPINT4_BNAINTR register field value. */
80174 #define ALT_USB_DEV_DIEPINT4_BNAINTR_SET_MSK 0x00000200
80175 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_BNAINTR register field value. */
80176 #define ALT_USB_DEV_DIEPINT4_BNAINTR_CLR_MSK 0xfffffdff
80177 /* The reset value of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */
80178 #define ALT_USB_DEV_DIEPINT4_BNAINTR_RESET 0x0
80179 /* Extracts the ALT_USB_DEV_DIEPINT4_BNAINTR field value from a register. */
80180 #define ALT_USB_DEV_DIEPINT4_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
80181 /* Produces a ALT_USB_DEV_DIEPINT4_BNAINTR register field value suitable for setting the register. */
80182 #define ALT_USB_DEV_DIEPINT4_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
80183 
80184 /*
80185  * Field : pktdrpsts
80186  *
80187  * Packet Drop Status (PktDrpSts)
80188  *
80189  * This bit indicates to the application that an ISOC OUT packet has been dropped.
80190  * This
80191  *
80192  * bit does not have an associated mask bit and does not generate an interrupt.
80193  *
80194  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
80195  * transfer
80196  *
80197  * interrupt feature is selected.
80198  *
80199  * Field Enumeration Values:
80200  *
80201  * Enum | Value | Description
80202  * :---------------------------------------|:------|:-----------------------------
80203  * ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_INACT | 0x0 | No interrupt
80204  * ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
80205  *
80206  * Field Access Macros:
80207  *
80208  */
80209 /*
80210  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_PKTDRPSTS
80211  *
80212  * No interrupt
80213  */
80214 #define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_INACT 0x0
80215 /*
80216  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_PKTDRPSTS
80217  *
80218  * Packet Drop Status interrupt
80219  */
80220 #define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_ACT 0x1
80221 
80222 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */
80223 #define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_LSB 11
80224 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */
80225 #define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_MSB 11
80226 /* The width in bits of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */
80227 #define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_WIDTH 1
80228 /* The mask used to set the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field value. */
80229 #define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_SET_MSK 0x00000800
80230 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field value. */
80231 #define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_CLR_MSK 0xfffff7ff
80232 /* The reset value of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */
80233 #define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_RESET 0x0
80234 /* Extracts the ALT_USB_DEV_DIEPINT4_PKTDRPSTS field value from a register. */
80235 #define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
80236 /* Produces a ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field value suitable for setting the register. */
80237 #define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
80238 
80239 /*
80240  * Field : bbleerr
80241  *
80242  * NAK Interrupt (BbleErr)
80243  *
80244  * The core generates this interrupt when babble is received for the endpoint.
80245  *
80246  * Field Enumeration Values:
80247  *
80248  * Enum | Value | Description
80249  * :-------------------------------------|:------|:------------------
80250  * ALT_USB_DEV_DIEPINT4_BBLEERR_E_INACT | 0x0 | No interrupt
80251  * ALT_USB_DEV_DIEPINT4_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
80252  *
80253  * Field Access Macros:
80254  *
80255  */
80256 /*
80257  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_BBLEERR
80258  *
80259  * No interrupt
80260  */
80261 #define ALT_USB_DEV_DIEPINT4_BBLEERR_E_INACT 0x0
80262 /*
80263  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_BBLEERR
80264  *
80265  * BbleErr interrupt
80266  */
80267 #define ALT_USB_DEV_DIEPINT4_BBLEERR_E_ACT 0x1
80268 
80269 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */
80270 #define ALT_USB_DEV_DIEPINT4_BBLEERR_LSB 12
80271 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */
80272 #define ALT_USB_DEV_DIEPINT4_BBLEERR_MSB 12
80273 /* The width in bits of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */
80274 #define ALT_USB_DEV_DIEPINT4_BBLEERR_WIDTH 1
80275 /* The mask used to set the ALT_USB_DEV_DIEPINT4_BBLEERR register field value. */
80276 #define ALT_USB_DEV_DIEPINT4_BBLEERR_SET_MSK 0x00001000
80277 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_BBLEERR register field value. */
80278 #define ALT_USB_DEV_DIEPINT4_BBLEERR_CLR_MSK 0xffffefff
80279 /* The reset value of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */
80280 #define ALT_USB_DEV_DIEPINT4_BBLEERR_RESET 0x0
80281 /* Extracts the ALT_USB_DEV_DIEPINT4_BBLEERR field value from a register. */
80282 #define ALT_USB_DEV_DIEPINT4_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
80283 /* Produces a ALT_USB_DEV_DIEPINT4_BBLEERR register field value suitable for setting the register. */
80284 #define ALT_USB_DEV_DIEPINT4_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
80285 
80286 /*
80287  * Field : nakintrpt
80288  *
80289  * NAK Interrupt (NAKInterrupt)
80290  *
80291  * The core generates this interrupt when a NAK is transmitted or received by the
80292  * device.
80293  *
80294  * In case of isochronous IN endpoints the interrupt gets generated when a zero
80295  * length
80296  *
80297  * packet is transmitted due to un-availability of data in the TXFifo.
80298  *
80299  * Field Enumeration Values:
80300  *
80301  * Enum | Value | Description
80302  * :---------------------------------------|:------|:--------------
80303  * ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_INACT | 0x0 | No interrupt
80304  * ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
80305  *
80306  * Field Access Macros:
80307  *
80308  */
80309 /*
80310  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_NAKINTRPT
80311  *
80312  * No interrupt
80313  */
80314 #define ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_INACT 0x0
80315 /*
80316  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_NAKINTRPT
80317  *
80318  * NAK Interrupt
80319  */
80320 #define ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_ACT 0x1
80321 
80322 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */
80323 #define ALT_USB_DEV_DIEPINT4_NAKINTRPT_LSB 13
80324 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */
80325 #define ALT_USB_DEV_DIEPINT4_NAKINTRPT_MSB 13
80326 /* The width in bits of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */
80327 #define ALT_USB_DEV_DIEPINT4_NAKINTRPT_WIDTH 1
80328 /* The mask used to set the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field value. */
80329 #define ALT_USB_DEV_DIEPINT4_NAKINTRPT_SET_MSK 0x00002000
80330 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field value. */
80331 #define ALT_USB_DEV_DIEPINT4_NAKINTRPT_CLR_MSK 0xffffdfff
80332 /* The reset value of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */
80333 #define ALT_USB_DEV_DIEPINT4_NAKINTRPT_RESET 0x0
80334 /* Extracts the ALT_USB_DEV_DIEPINT4_NAKINTRPT field value from a register. */
80335 #define ALT_USB_DEV_DIEPINT4_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
80336 /* Produces a ALT_USB_DEV_DIEPINT4_NAKINTRPT register field value suitable for setting the register. */
80337 #define ALT_USB_DEV_DIEPINT4_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
80338 
80339 /*
80340  * Field : nyetintrpt
80341  *
80342  * NYET Interrupt (NYETIntrpt)
80343  *
80344  * The core generates this interrupt when a NYET response is transmitted for a non
80345  * isochronous OUT endpoint.
80346  *
80347  * Field Enumeration Values:
80348  *
80349  * Enum | Value | Description
80350  * :----------------------------------------|:------|:---------------
80351  * ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_INACT | 0x0 | No interrupt
80352  * ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
80353  *
80354  * Field Access Macros:
80355  *
80356  */
80357 /*
80358  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_NYETINTRPT
80359  *
80360  * No interrupt
80361  */
80362 #define ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_INACT 0x0
80363 /*
80364  * Enumerated value for register field ALT_USB_DEV_DIEPINT4_NYETINTRPT
80365  *
80366  * NYET Interrupt
80367  */
80368 #define ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_ACT 0x1
80369 
80370 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */
80371 #define ALT_USB_DEV_DIEPINT4_NYETINTRPT_LSB 14
80372 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */
80373 #define ALT_USB_DEV_DIEPINT4_NYETINTRPT_MSB 14
80374 /* The width in bits of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */
80375 #define ALT_USB_DEV_DIEPINT4_NYETINTRPT_WIDTH 1
80376 /* The mask used to set the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field value. */
80377 #define ALT_USB_DEV_DIEPINT4_NYETINTRPT_SET_MSK 0x00004000
80378 /* The mask used to clear the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field value. */
80379 #define ALT_USB_DEV_DIEPINT4_NYETINTRPT_CLR_MSK 0xffffbfff
80380 /* The reset value of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */
80381 #define ALT_USB_DEV_DIEPINT4_NYETINTRPT_RESET 0x0
80382 /* Extracts the ALT_USB_DEV_DIEPINT4_NYETINTRPT field value from a register. */
80383 #define ALT_USB_DEV_DIEPINT4_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
80384 /* Produces a ALT_USB_DEV_DIEPINT4_NYETINTRPT register field value suitable for setting the register. */
80385 #define ALT_USB_DEV_DIEPINT4_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
80386 
80387 #ifndef __ASSEMBLY__
80388 /*
80389  * WARNING: The C register and register group struct declarations are provided for
80390  * convenience and illustrative purposes. They should, however, be used with
80391  * caution as the C language standard provides no guarantees about the alignment or
80392  * atomicity of device memory accesses. The recommended practice for writing
80393  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
80394  * alt_write_word() functions.
80395  *
80396  * The struct declaration for register ALT_USB_DEV_DIEPINT4.
80397  */
80398 struct ALT_USB_DEV_DIEPINT4_s
80399 {
80400  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT4_XFERCOMPL */
80401  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT4_EPDISBLD */
80402  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT4_AHBERR */
80403  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT4_TMO */
80404  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT4_INTKNTXFEMP */
80405  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT4_INTKNEPMIS */
80406  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT4_INEPNAKEFF */
80407  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT4_TXFEMP */
80408  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN */
80409  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT4_BNAINTR */
80410  uint32_t : 1; /* *UNDEFINED* */
80411  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT4_PKTDRPSTS */
80412  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT4_BBLEERR */
80413  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT4_NAKINTRPT */
80414  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT4_NYETINTRPT */
80415  uint32_t : 17; /* *UNDEFINED* */
80416 };
80417 
80418 /* The typedef declaration for register ALT_USB_DEV_DIEPINT4. */
80419 typedef volatile struct ALT_USB_DEV_DIEPINT4_s ALT_USB_DEV_DIEPINT4_t;
80420 #endif /* __ASSEMBLY__ */
80421 
80422 /* The reset value of the ALT_USB_DEV_DIEPINT4 register. */
80423 #define ALT_USB_DEV_DIEPINT4_RESET 0x00000080
80424 /* The byte offset of the ALT_USB_DEV_DIEPINT4 register from the beginning of the component. */
80425 #define ALT_USB_DEV_DIEPINT4_OFST 0x188
80426 /* The address of the ALT_USB_DEV_DIEPINT4 register. */
80427 #define ALT_USB_DEV_DIEPINT4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT4_OFST))
80428 
80429 /*
80430  * Register : dieptsiz4
80431  *
80432  * Device IN Endpoint 4 Transfer Size Register
80433  *
80434  * Register Layout
80435  *
80436  * Bits | Access | Reset | Description
80437  * :--------|:-------|:------|:-------------------------------
80438  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ4_XFERSIZE
80439  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ4_PKTCNT
80440  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ4_MC
80441  * [31] | ??? | 0x0 | *UNDEFINED*
80442  *
80443  */
80444 /*
80445  * Field : xfersize
80446  *
80447  * Transfer Size (XferSize)
80448  *
80449  * Indicates the transfer size in bytes For endpoint 0. The core
80450  *
80451  * interrupts the application only after it has exhausted the transfer
80452  *
80453  * size amount of data. The transfer size can be Set to the
80454  *
80455  * maximum packet size of the endpoint, to be interrupted at the
80456  *
80457  * end of each packet.
80458  *
80459  * The core decrements this field every time a packet from the
80460  *
80461  * external memory is written to the TxFIFO.
80462  *
80463  * Field Access Macros:
80464  *
80465  */
80466 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */
80467 #define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_LSB 0
80468 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */
80469 #define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_MSB 18
80470 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */
80471 #define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_WIDTH 19
80472 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field value. */
80473 #define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_SET_MSK 0x0007ffff
80474 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field value. */
80475 #define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_CLR_MSK 0xfff80000
80476 /* The reset value of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */
80477 #define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_RESET 0x0
80478 /* Extracts the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE field value from a register. */
80479 #define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
80480 /* Produces a ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field value suitable for setting the register. */
80481 #define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
80482 
80483 /*
80484  * Field : pktcnt
80485  *
80486  * Packet Count (PktCnt)
80487  *
80488  * Indicates the total number of USB packets that constitute the
80489  *
80490  * Transfer Size amount of data For endpoint 0.
80491  *
80492  * This field is decremented every time a packet (maximum size or
80493  *
80494  * short packet) is read from the TxFIFO.
80495  *
80496  * Field Access Macros:
80497  *
80498  */
80499 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */
80500 #define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_LSB 19
80501 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */
80502 #define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_MSB 28
80503 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */
80504 #define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_WIDTH 10
80505 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field value. */
80506 #define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_SET_MSK 0x1ff80000
80507 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field value. */
80508 #define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_CLR_MSK 0xe007ffff
80509 /* The reset value of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */
80510 #define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_RESET 0x0
80511 /* Extracts the ALT_USB_DEV_DIEPTSIZ4_PKTCNT field value from a register. */
80512 #define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
80513 /* Produces a ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field value suitable for setting the register. */
80514 #define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
80515 
80516 /*
80517  * Field : mc
80518  *
80519  * Applies to IN endpoints only.
80520  *
80521  * For periodic IN endpoints, this field indicates the number of packets that must
80522  * be transmitted per microframe on the USB. The core uses this field to calculate
80523  * the data PID for isochronous IN endpoints.
80524  *
80525  * 2'b01: 1 packet
80526  *
80527  * 2'b10: 2 packets
80528  *
80529  * 2'b11: 3 packets
80530  *
80531  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
80532  * specifies the number of packets the core must fetchfor an IN endpoint before it
80533  * switches to the endpoint pointed to by the Next Endpoint field of the Device
80534  * Endpoint-n Control register (DIEPCTLn.NextEp)
80535  *
80536  * Field Enumeration Values:
80537  *
80538  * Enum | Value | Description
80539  * :------------------------------------|:------|:------------
80540  * ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTONE | 0x1 | 1 packet
80541  * ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTWO | 0x2 | 2 packets
80542  * ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTHREE | 0x3 | 3 packets
80543  *
80544  * Field Access Macros:
80545  *
80546  */
80547 /*
80548  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ4_MC
80549  *
80550  * 1 packet
80551  */
80552 #define ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTONE 0x1
80553 /*
80554  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ4_MC
80555  *
80556  * 2 packets
80557  */
80558 #define ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTWO 0x2
80559 /*
80560  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ4_MC
80561  *
80562  * 3 packets
80563  */
80564 #define ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTHREE 0x3
80565 
80566 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */
80567 #define ALT_USB_DEV_DIEPTSIZ4_MC_LSB 29
80568 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */
80569 #define ALT_USB_DEV_DIEPTSIZ4_MC_MSB 30
80570 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */
80571 #define ALT_USB_DEV_DIEPTSIZ4_MC_WIDTH 2
80572 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ4_MC register field value. */
80573 #define ALT_USB_DEV_DIEPTSIZ4_MC_SET_MSK 0x60000000
80574 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ4_MC register field value. */
80575 #define ALT_USB_DEV_DIEPTSIZ4_MC_CLR_MSK 0x9fffffff
80576 /* The reset value of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */
80577 #define ALT_USB_DEV_DIEPTSIZ4_MC_RESET 0x0
80578 /* Extracts the ALT_USB_DEV_DIEPTSIZ4_MC field value from a register. */
80579 #define ALT_USB_DEV_DIEPTSIZ4_MC_GET(value) (((value) & 0x60000000) >> 29)
80580 /* Produces a ALT_USB_DEV_DIEPTSIZ4_MC register field value suitable for setting the register. */
80581 #define ALT_USB_DEV_DIEPTSIZ4_MC_SET(value) (((value) << 29) & 0x60000000)
80582 
80583 #ifndef __ASSEMBLY__
80584 /*
80585  * WARNING: The C register and register group struct declarations are provided for
80586  * convenience and illustrative purposes. They should, however, be used with
80587  * caution as the C language standard provides no guarantees about the alignment or
80588  * atomicity of device memory accesses. The recommended practice for writing
80589  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
80590  * alt_write_word() functions.
80591  *
80592  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ4.
80593  */
80594 struct ALT_USB_DEV_DIEPTSIZ4_s
80595 {
80596  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ4_XFERSIZE */
80597  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ4_PKTCNT */
80598  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ4_MC */
80599  uint32_t : 1; /* *UNDEFINED* */
80600 };
80601 
80602 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ4. */
80603 typedef volatile struct ALT_USB_DEV_DIEPTSIZ4_s ALT_USB_DEV_DIEPTSIZ4_t;
80604 #endif /* __ASSEMBLY__ */
80605 
80606 /* The reset value of the ALT_USB_DEV_DIEPTSIZ4 register. */
80607 #define ALT_USB_DEV_DIEPTSIZ4_RESET 0x00000000
80608 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ4 register from the beginning of the component. */
80609 #define ALT_USB_DEV_DIEPTSIZ4_OFST 0x190
80610 /* The address of the ALT_USB_DEV_DIEPTSIZ4 register. */
80611 #define ALT_USB_DEV_DIEPTSIZ4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ4_OFST))
80612 
80613 /*
80614  * Register : diepdma4
80615  *
80616  * Device IN Endpoint 4 DMA Address Register
80617  *
80618  * Register Layout
80619  *
80620  * Bits | Access | Reset | Description
80621  * :-------|:-------|:--------|:------------------------------
80622  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA4_DIEPDMA4
80623  *
80624  */
80625 /*
80626  * Field : diepdma4
80627  *
80628  * Holds the start address of the external memory for storing or fetching endpoint
80629  *
80630  * data.
80631  *
80632  * Note: For control endpoints, this field stores control OUT data packets as well
80633  * as
80634  *
80635  * SETUP transaction data packets. When more than three SETUP packets are
80636  *
80637  * received back-to-back, the SETUP data packet in the memory is overwritten.
80638  *
80639  * This register is incremented on every AHB transaction. The application can give
80640  *
80641  * only a DWORD-aligned address.
80642  *
80643  * When Scatter/Gather DMA mode is not enabled, the application programs the
80644  *
80645  * start address value in this field.
80646  *
80647  * When Scatter/Gather DMA mode is enabled, this field indicates the base
80648  *
80649  * pointer for the descriptor list.
80650  *
80651  * Field Access Macros:
80652  *
80653  */
80654 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field. */
80655 #define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_LSB 0
80656 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field. */
80657 #define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_MSB 31
80658 /* The width in bits of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field. */
80659 #define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_WIDTH 32
80660 /* The mask used to set the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field value. */
80661 #define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_SET_MSK 0xffffffff
80662 /* The mask used to clear the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field value. */
80663 #define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_CLR_MSK 0x00000000
80664 /* The reset value of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field is UNKNOWN. */
80665 #define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_RESET 0x0
80666 /* Extracts the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 field value from a register. */
80667 #define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_GET(value) (((value) & 0xffffffff) >> 0)
80668 /* Produces a ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field value suitable for setting the register. */
80669 #define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_SET(value) (((value) << 0) & 0xffffffff)
80670 
80671 #ifndef __ASSEMBLY__
80672 /*
80673  * WARNING: The C register and register group struct declarations are provided for
80674  * convenience and illustrative purposes. They should, however, be used with
80675  * caution as the C language standard provides no guarantees about the alignment or
80676  * atomicity of device memory accesses. The recommended practice for writing
80677  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
80678  * alt_write_word() functions.
80679  *
80680  * The struct declaration for register ALT_USB_DEV_DIEPDMA4.
80681  */
80682 struct ALT_USB_DEV_DIEPDMA4_s
80683 {
80684  uint32_t diepdma4 : 32; /* ALT_USB_DEV_DIEPDMA4_DIEPDMA4 */
80685 };
80686 
80687 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA4. */
80688 typedef volatile struct ALT_USB_DEV_DIEPDMA4_s ALT_USB_DEV_DIEPDMA4_t;
80689 #endif /* __ASSEMBLY__ */
80690 
80691 /* The reset value of the ALT_USB_DEV_DIEPDMA4 register. */
80692 #define ALT_USB_DEV_DIEPDMA4_RESET 0x00000000
80693 /* The byte offset of the ALT_USB_DEV_DIEPDMA4 register from the beginning of the component. */
80694 #define ALT_USB_DEV_DIEPDMA4_OFST 0x194
80695 /* The address of the ALT_USB_DEV_DIEPDMA4 register. */
80696 #define ALT_USB_DEV_DIEPDMA4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA4_OFST))
80697 
80698 /*
80699  * Register : dtxfsts4
80700  *
80701  * Device IN Endpoint Transmit FIFO Status Register 4
80702  *
80703  * Register Layout
80704  *
80705  * Bits | Access | Reset | Description
80706  * :--------|:-------|:-------|:-------------------------------------
80707  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL
80708  * [31:16] | ??? | 0x0 | *UNDEFINED*
80709  *
80710  */
80711 /*
80712  * Field : ineptxfspcavail
80713  *
80714  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
80715  *
80716  * Indicates the amount of free space available in the Endpoint
80717  *
80718  * TxFIFO.
80719  *
80720  * Values are in terms of 32-bit words.
80721  *
80722  * 16'h0: Endpoint TxFIFO is full
80723  *
80724  * 16'h1: 1 word available
80725  *
80726  * 16'h2: 2 words available
80727  *
80728  * 16'hn: n words available (where 0 n 32,768)
80729  *
80730  * 16'h8000: 32,768 words available
80731  *
80732  * Others: Reserved
80733  *
80734  * Field Access Macros:
80735  *
80736  */
80737 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */
80738 #define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_LSB 0
80739 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */
80740 #define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_MSB 15
80741 /* The width in bits of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */
80742 #define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_WIDTH 16
80743 /* The mask used to set the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field value. */
80744 #define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
80745 /* The mask used to clear the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field value. */
80746 #define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
80747 /* The reset value of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */
80748 #define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_RESET 0x2000
80749 /* Extracts the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL field value from a register. */
80750 #define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
80751 /* Produces a ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field value suitable for setting the register. */
80752 #define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
80753 
80754 #ifndef __ASSEMBLY__
80755 /*
80756  * WARNING: The C register and register group struct declarations are provided for
80757  * convenience and illustrative purposes. They should, however, be used with
80758  * caution as the C language standard provides no guarantees about the alignment or
80759  * atomicity of device memory accesses. The recommended practice for writing
80760  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
80761  * alt_write_word() functions.
80762  *
80763  * The struct declaration for register ALT_USB_DEV_DTXFSTS4.
80764  */
80765 struct ALT_USB_DEV_DTXFSTS4_s
80766 {
80767  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL */
80768  uint32_t : 16; /* *UNDEFINED* */
80769 };
80770 
80771 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS4. */
80772 typedef volatile struct ALT_USB_DEV_DTXFSTS4_s ALT_USB_DEV_DTXFSTS4_t;
80773 #endif /* __ASSEMBLY__ */
80774 
80775 /* The reset value of the ALT_USB_DEV_DTXFSTS4 register. */
80776 #define ALT_USB_DEV_DTXFSTS4_RESET 0x00002000
80777 /* The byte offset of the ALT_USB_DEV_DTXFSTS4 register from the beginning of the component. */
80778 #define ALT_USB_DEV_DTXFSTS4_OFST 0x198
80779 /* The address of the ALT_USB_DEV_DTXFSTS4 register. */
80780 #define ALT_USB_DEV_DTXFSTS4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS4_OFST))
80781 
80782 /*
80783  * Register : diepdmab4
80784  *
80785  * Device IN Endpoint 4 Buffer Address Register
80786  *
80787  * Register Layout
80788  *
80789  * Bits | Access | Reset | Description
80790  * :-------|:-------|:--------|:--------------------------------
80791  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4
80792  *
80793  */
80794 /*
80795  * Field : diepdmab4
80796  *
80797  * Holds the current buffer address.This register is updated as and when the data
80798  *
80799  * transfer for the corresponding end point is in progress.
80800  *
80801  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
80802  * is
80803  *
80804  * reserved.
80805  *
80806  * Field Access Macros:
80807  *
80808  */
80809 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field. */
80810 #define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_LSB 0
80811 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field. */
80812 #define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_MSB 31
80813 /* The width in bits of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field. */
80814 #define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_WIDTH 32
80815 /* The mask used to set the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field value. */
80816 #define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_SET_MSK 0xffffffff
80817 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field value. */
80818 #define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_CLR_MSK 0x00000000
80819 /* The reset value of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field is UNKNOWN. */
80820 #define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_RESET 0x0
80821 /* Extracts the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 field value from a register. */
80822 #define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_GET(value) (((value) & 0xffffffff) >> 0)
80823 /* Produces a ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field value suitable for setting the register. */
80824 #define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_SET(value) (((value) << 0) & 0xffffffff)
80825 
80826 #ifndef __ASSEMBLY__
80827 /*
80828  * WARNING: The C register and register group struct declarations are provided for
80829  * convenience and illustrative purposes. They should, however, be used with
80830  * caution as the C language standard provides no guarantees about the alignment or
80831  * atomicity of device memory accesses. The recommended practice for writing
80832  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
80833  * alt_write_word() functions.
80834  *
80835  * The struct declaration for register ALT_USB_DEV_DIEPDMAB4.
80836  */
80837 struct ALT_USB_DEV_DIEPDMAB4_s
80838 {
80839  const uint32_t diepdmab4 : 32; /* ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 */
80840 };
80841 
80842 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB4. */
80843 typedef volatile struct ALT_USB_DEV_DIEPDMAB4_s ALT_USB_DEV_DIEPDMAB4_t;
80844 #endif /* __ASSEMBLY__ */
80845 
80846 /* The reset value of the ALT_USB_DEV_DIEPDMAB4 register. */
80847 #define ALT_USB_DEV_DIEPDMAB4_RESET 0x00000000
80848 /* The byte offset of the ALT_USB_DEV_DIEPDMAB4 register from the beginning of the component. */
80849 #define ALT_USB_DEV_DIEPDMAB4_OFST 0x19c
80850 /* The address of the ALT_USB_DEV_DIEPDMAB4 register. */
80851 #define ALT_USB_DEV_DIEPDMAB4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB4_OFST))
80852 
80853 /*
80854  * Register : diepctl5
80855  *
80856  * Device Control IN Endpoint 5 Control Register
80857  *
80858  * Register Layout
80859  *
80860  * Bits | Access | Reset | Description
80861  * :--------|:---------|:------|:------------------------------
80862  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL5_MPS
80863  * [14:11] | ??? | 0x0 | *UNDEFINED*
80864  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL5_USBACTEP
80865  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL5_DPID
80866  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL5_NAKSTS
80867  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL5_EPTYPE
80868  * [20] | ??? | 0x0 | *UNDEFINED*
80869  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL5_STALL
80870  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL5_TXFNUM
80871  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL5_CNAK
80872  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL5_SNAK
80873  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL5_SETD0PID
80874  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL5_SETD1PID
80875  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL5_EPDIS
80876  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL5_EPENA
80877  *
80878  */
80879 /*
80880  * Field : mps
80881  *
80882  * Maximum Packet Size (MPS)
80883  *
80884  * The application must program this field with the maximum packet size for the
80885  * current
80886  *
80887  * logical endpoint. This value is in bytes.
80888  *
80889  * Field Access Macros:
80890  *
80891  */
80892 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_MPS register field. */
80893 #define ALT_USB_DEV_DIEPCTL5_MPS_LSB 0
80894 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_MPS register field. */
80895 #define ALT_USB_DEV_DIEPCTL5_MPS_MSB 10
80896 /* The width in bits of the ALT_USB_DEV_DIEPCTL5_MPS register field. */
80897 #define ALT_USB_DEV_DIEPCTL5_MPS_WIDTH 11
80898 /* The mask used to set the ALT_USB_DEV_DIEPCTL5_MPS register field value. */
80899 #define ALT_USB_DEV_DIEPCTL5_MPS_SET_MSK 0x000007ff
80900 /* The mask used to clear the ALT_USB_DEV_DIEPCTL5_MPS register field value. */
80901 #define ALT_USB_DEV_DIEPCTL5_MPS_CLR_MSK 0xfffff800
80902 /* The reset value of the ALT_USB_DEV_DIEPCTL5_MPS register field. */
80903 #define ALT_USB_DEV_DIEPCTL5_MPS_RESET 0x0
80904 /* Extracts the ALT_USB_DEV_DIEPCTL5_MPS field value from a register. */
80905 #define ALT_USB_DEV_DIEPCTL5_MPS_GET(value) (((value) & 0x000007ff) >> 0)
80906 /* Produces a ALT_USB_DEV_DIEPCTL5_MPS register field value suitable for setting the register. */
80907 #define ALT_USB_DEV_DIEPCTL5_MPS_SET(value) (((value) << 0) & 0x000007ff)
80908 
80909 /*
80910  * Field : usbactep
80911  *
80912  * USB Active Endpoint (USBActEP)
80913  *
80914  * Indicates whether this endpoint is active in the current configuration and
80915  * interface. The
80916  *
80917  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
80918  * reset. After
80919  *
80920  * receiving the SetConfiguration and SetInterface commands, the application must
80921  *
80922  * program endpoint registers accordingly and set this bit.
80923  *
80924  * Field Enumeration Values:
80925  *
80926  * Enum | Value | Description
80927  * :-------------------------------------|:------|:--------------------
80928  * ALT_USB_DEV_DIEPCTL5_USBACTEP_E_DISD | 0x0 | Not Active
80929  * ALT_USB_DEV_DIEPCTL5_USBACTEP_E_END | 0x1 | USB Active Endpoint
80930  *
80931  * Field Access Macros:
80932  *
80933  */
80934 /*
80935  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_USBACTEP
80936  *
80937  * Not Active
80938  */
80939 #define ALT_USB_DEV_DIEPCTL5_USBACTEP_E_DISD 0x0
80940 /*
80941  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_USBACTEP
80942  *
80943  * USB Active Endpoint
80944  */
80945 #define ALT_USB_DEV_DIEPCTL5_USBACTEP_E_END 0x1
80946 
80947 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */
80948 #define ALT_USB_DEV_DIEPCTL5_USBACTEP_LSB 15
80949 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */
80950 #define ALT_USB_DEV_DIEPCTL5_USBACTEP_MSB 15
80951 /* The width in bits of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */
80952 #define ALT_USB_DEV_DIEPCTL5_USBACTEP_WIDTH 1
80953 /* The mask used to set the ALT_USB_DEV_DIEPCTL5_USBACTEP register field value. */
80954 #define ALT_USB_DEV_DIEPCTL5_USBACTEP_SET_MSK 0x00008000
80955 /* The mask used to clear the ALT_USB_DEV_DIEPCTL5_USBACTEP register field value. */
80956 #define ALT_USB_DEV_DIEPCTL5_USBACTEP_CLR_MSK 0xffff7fff
80957 /* The reset value of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */
80958 #define ALT_USB_DEV_DIEPCTL5_USBACTEP_RESET 0x0
80959 /* Extracts the ALT_USB_DEV_DIEPCTL5_USBACTEP field value from a register. */
80960 #define ALT_USB_DEV_DIEPCTL5_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
80961 /* Produces a ALT_USB_DEV_DIEPCTL5_USBACTEP register field value suitable for setting the register. */
80962 #define ALT_USB_DEV_DIEPCTL5_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
80963 
80964 /*
80965  * Field : dpid
80966  *
80967  * Endpoint Data PID (DPID)
80968  *
80969  * Applies to interrupt/bulk IN and OUT endpoints only.
80970  *
80971  * Contains the PID of the packet to be received or transmitted on this endpoint.
80972  * The
80973  *
80974  * application must program the PID of the first packet to be received or
80975  * transmitted on
80976  *
80977  * this endpoint, after the endpoint is activated. The applications use the
80978  * SetD1PID and
80979  *
80980  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
80981  *
80982  * 1'b0: DATA0
80983  *
80984  * 1'b1: DATA1
80985  *
80986  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
80987  *
80988  * DMA mode.
80989  *
80990  * 1'b0 RO
80991  *
80992  * Even/Odd (Micro)Frame (EO_FrNum)
80993  *
80994  * In non-Scatter/Gather DMA mode:
80995  *
80996  * Applies to isochronous IN and OUT endpoints only.
80997  *
80998  * Indicates the (micro)frame number in which the core transmits/receives
80999  * isochronous
81000  *
81001  * data for this endpoint. The application must program the even/odd (micro) frame
81002  *
81003  * number in which it intends to transmit/receive isochronous data for this
81004  * endpoint using
81005  *
81006  * the SetEvnFr and SetOddFr fields in this register.
81007  *
81008  * 1'b0: Even (micro)frame
81009  *
81010  * 1'b1: Odd (micro)frame
81011  *
81012  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
81013  * number
81014  *
81015  * in which to send data is provided in the transmit descriptor structure. The
81016  * frame in
81017  *
81018  * which data is received is updated in receive descriptor structure.
81019  *
81020  * Field Enumeration Values:
81021  *
81022  * Enum | Value | Description
81023  * :----------------------------------|:------|:-----------------------------
81024  * ALT_USB_DEV_DIEPCTL5_DPID_E_INACT | 0x0 | Endpoint Data PID not active
81025  * ALT_USB_DEV_DIEPCTL5_DPID_E_ACT | 0x1 | Endpoint Data PID active
81026  *
81027  * Field Access Macros:
81028  *
81029  */
81030 /*
81031  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_DPID
81032  *
81033  * Endpoint Data PID not active
81034  */
81035 #define ALT_USB_DEV_DIEPCTL5_DPID_E_INACT 0x0
81036 /*
81037  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_DPID
81038  *
81039  * Endpoint Data PID active
81040  */
81041 #define ALT_USB_DEV_DIEPCTL5_DPID_E_ACT 0x1
81042 
81043 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_DPID register field. */
81044 #define ALT_USB_DEV_DIEPCTL5_DPID_LSB 16
81045 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_DPID register field. */
81046 #define ALT_USB_DEV_DIEPCTL5_DPID_MSB 16
81047 /* The width in bits of the ALT_USB_DEV_DIEPCTL5_DPID register field. */
81048 #define ALT_USB_DEV_DIEPCTL5_DPID_WIDTH 1
81049 /* The mask used to set the ALT_USB_DEV_DIEPCTL5_DPID register field value. */
81050 #define ALT_USB_DEV_DIEPCTL5_DPID_SET_MSK 0x00010000
81051 /* The mask used to clear the ALT_USB_DEV_DIEPCTL5_DPID register field value. */
81052 #define ALT_USB_DEV_DIEPCTL5_DPID_CLR_MSK 0xfffeffff
81053 /* The reset value of the ALT_USB_DEV_DIEPCTL5_DPID register field. */
81054 #define ALT_USB_DEV_DIEPCTL5_DPID_RESET 0x0
81055 /* Extracts the ALT_USB_DEV_DIEPCTL5_DPID field value from a register. */
81056 #define ALT_USB_DEV_DIEPCTL5_DPID_GET(value) (((value) & 0x00010000) >> 16)
81057 /* Produces a ALT_USB_DEV_DIEPCTL5_DPID register field value suitable for setting the register. */
81058 #define ALT_USB_DEV_DIEPCTL5_DPID_SET(value) (((value) << 16) & 0x00010000)
81059 
81060 /*
81061  * Field : naksts
81062  *
81063  * NAK Status (NAKSts)
81064  *
81065  * Indicates the following:
81066  *
81067  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
81068  *
81069  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
81070  *
81071  * When either the application or the core sets this bit:
81072  *
81073  * The core stops receiving any data on an OUT endpoint, even if there is space in
81074  *
81075  * the RxFIFO to accommodate the incoming packet.
81076  *
81077  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
81078  *
81079  * endpoint, even if there data is available in the TxFIFO.
81080  *
81081  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
81082  *
81083  * if there data is available in the TxFIFO.
81084  *
81085  * Irrespective of this bit's setting, the core always responds to SETUP data
81086  * packets with
81087  *
81088  * an ACK handshake.
81089  *
81090  * Field Enumeration Values:
81091  *
81092  * Enum | Value | Description
81093  * :-------------------------------------|:------|:------------------------------------------------
81094  * ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
81095  * : | | based on the FIFO status
81096  * ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
81097  * : | | endpoint
81098  *
81099  * Field Access Macros:
81100  *
81101  */
81102 /*
81103  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_NAKSTS
81104  *
81105  * The core is transmitting non-NAK handshakes based on the FIFO status
81106  */
81107 #define ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NONNAK 0x0
81108 /*
81109  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_NAKSTS
81110  *
81111  * The core is transmitting NAK handshakes on this endpoint
81112  */
81113 #define ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NAK 0x1
81114 
81115 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */
81116 #define ALT_USB_DEV_DIEPCTL5_NAKSTS_LSB 17
81117 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */
81118 #define ALT_USB_DEV_DIEPCTL5_NAKSTS_MSB 17
81119 /* The width in bits of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */
81120 #define ALT_USB_DEV_DIEPCTL5_NAKSTS_WIDTH 1
81121 /* The mask used to set the ALT_USB_DEV_DIEPCTL5_NAKSTS register field value. */
81122 #define ALT_USB_DEV_DIEPCTL5_NAKSTS_SET_MSK 0x00020000
81123 /* The mask used to clear the ALT_USB_DEV_DIEPCTL5_NAKSTS register field value. */
81124 #define ALT_USB_DEV_DIEPCTL5_NAKSTS_CLR_MSK 0xfffdffff
81125 /* The reset value of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */
81126 #define ALT_USB_DEV_DIEPCTL5_NAKSTS_RESET 0x0
81127 /* Extracts the ALT_USB_DEV_DIEPCTL5_NAKSTS field value from a register. */
81128 #define ALT_USB_DEV_DIEPCTL5_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
81129 /* Produces a ALT_USB_DEV_DIEPCTL5_NAKSTS register field value suitable for setting the register. */
81130 #define ALT_USB_DEV_DIEPCTL5_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
81131 
81132 /*
81133  * Field : eptype
81134  *
81135  * Endpoint Type (EPType)
81136  *
81137  * This is the transfer type supported by this logical endpoint.
81138  *
81139  * 2'b00: Control
81140  *
81141  * 2'b01: Isochronous
81142  *
81143  * 2'b10: Bulk
81144  *
81145  * 2'b11: Interrupt
81146  *
81147  * Field Enumeration Values:
81148  *
81149  * Enum | Value | Description
81150  * :------------------------------------------|:------|:------------
81151  * ALT_USB_DEV_DIEPCTL5_EPTYPE_E_CTL | 0x0 | Control
81152  * ALT_USB_DEV_DIEPCTL5_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
81153  * ALT_USB_DEV_DIEPCTL5_EPTYPE_E_BULK | 0x2 | Bulk
81154  * ALT_USB_DEV_DIEPCTL5_EPTYPE_E_INTERRUP | 0x3 | Interrupt
81155  *
81156  * Field Access Macros:
81157  *
81158  */
81159 /*
81160  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE
81161  *
81162  * Control
81163  */
81164 #define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_CTL 0x0
81165 /*
81166  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE
81167  *
81168  * Isochronous
81169  */
81170 #define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_ISOCHRONOUS 0x1
81171 /*
81172  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE
81173  *
81174  * Bulk
81175  */
81176 #define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_BULK 0x2
81177 /*
81178  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE
81179  *
81180  * Interrupt
81181  */
81182 #define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_INTERRUP 0x3
81183 
81184 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */
81185 #define ALT_USB_DEV_DIEPCTL5_EPTYPE_LSB 18
81186 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */
81187 #define ALT_USB_DEV_DIEPCTL5_EPTYPE_MSB 19
81188 /* The width in bits of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */
81189 #define ALT_USB_DEV_DIEPCTL5_EPTYPE_WIDTH 2
81190 /* The mask used to set the ALT_USB_DEV_DIEPCTL5_EPTYPE register field value. */
81191 #define ALT_USB_DEV_DIEPCTL5_EPTYPE_SET_MSK 0x000c0000
81192 /* The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPTYPE register field value. */
81193 #define ALT_USB_DEV_DIEPCTL5_EPTYPE_CLR_MSK 0xfff3ffff
81194 /* The reset value of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */
81195 #define ALT_USB_DEV_DIEPCTL5_EPTYPE_RESET 0x0
81196 /* Extracts the ALT_USB_DEV_DIEPCTL5_EPTYPE field value from a register. */
81197 #define ALT_USB_DEV_DIEPCTL5_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
81198 /* Produces a ALT_USB_DEV_DIEPCTL5_EPTYPE register field value suitable for setting the register. */
81199 #define ALT_USB_DEV_DIEPCTL5_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
81200 
81201 /*
81202  * Field : stall
81203  *
81204  * STALL Handshake (Stall)
81205  *
81206  * Applies to non-control, non-isochronous IN and OUT endpoints only.
81207  *
81208  * The application sets this bit to stall all tokens from the USB host to this
81209  * endpoint. If a
81210  *
81211  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
81212  * bit, the
81213  *
81214  * STALL bit takes priority. Only the application can clear this bit, never the
81215  * core.
81216  *
81217  * 1'b0 R_W
81218  *
81219  * Applies to control endpoints only.
81220  *
81221  * The application can only set this bit, and the core clears it, when a SETUP
81222  * token is
81223  *
81224  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
81225  * OUT
81226  *
81227  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
81228  * this bit's
81229  *
81230  * setting, the core always responds to SETUP data packets with an ACK handshake.
81231  *
81232  * Field Enumeration Values:
81233  *
81234  * Enum | Value | Description
81235  * :-----------------------------------|:------|:----------------------------
81236  * ALT_USB_DEV_DIEPCTL5_STALL_E_INACT | 0x0 | STALL All Tokens not active
81237  * ALT_USB_DEV_DIEPCTL5_STALL_E_ACT | 0x1 | STALL All Tokens active
81238  *
81239  * Field Access Macros:
81240  *
81241  */
81242 /*
81243  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_STALL
81244  *
81245  * STALL All Tokens not active
81246  */
81247 #define ALT_USB_DEV_DIEPCTL5_STALL_E_INACT 0x0
81248 /*
81249  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_STALL
81250  *
81251  * STALL All Tokens active
81252  */
81253 #define ALT_USB_DEV_DIEPCTL5_STALL_E_ACT 0x1
81254 
81255 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_STALL register field. */
81256 #define ALT_USB_DEV_DIEPCTL5_STALL_LSB 21
81257 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_STALL register field. */
81258 #define ALT_USB_DEV_DIEPCTL5_STALL_MSB 21
81259 /* The width in bits of the ALT_USB_DEV_DIEPCTL5_STALL register field. */
81260 #define ALT_USB_DEV_DIEPCTL5_STALL_WIDTH 1
81261 /* The mask used to set the ALT_USB_DEV_DIEPCTL5_STALL register field value. */
81262 #define ALT_USB_DEV_DIEPCTL5_STALL_SET_MSK 0x00200000
81263 /* The mask used to clear the ALT_USB_DEV_DIEPCTL5_STALL register field value. */
81264 #define ALT_USB_DEV_DIEPCTL5_STALL_CLR_MSK 0xffdfffff
81265 /* The reset value of the ALT_USB_DEV_DIEPCTL5_STALL register field. */
81266 #define ALT_USB_DEV_DIEPCTL5_STALL_RESET 0x0
81267 /* Extracts the ALT_USB_DEV_DIEPCTL5_STALL field value from a register. */
81268 #define ALT_USB_DEV_DIEPCTL5_STALL_GET(value) (((value) & 0x00200000) >> 21)
81269 /* Produces a ALT_USB_DEV_DIEPCTL5_STALL register field value suitable for setting the register. */
81270 #define ALT_USB_DEV_DIEPCTL5_STALL_SET(value) (((value) << 21) & 0x00200000)
81271 
81272 /*
81273  * Field : txfnum
81274  *
81275  * TxFIFO Number (TxFNum)
81276  *
81277  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
81278  *
81279  * endpoints must map this to the corresponding Periodic TxFIFO number.
81280  *
81281  * 4'h0: Non-Periodic TxFIFO
81282  *
81283  * Others: Specified Periodic TxFIFO.number
81284  *
81285  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
81286  *
81287  * applications such as mass storage. The core treats an IN endpoint as a non-
81288  * periodic
81289  *
81290  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
81291  * must be
81292  *
81293  * allocated for an interrupt IN endpoint, and the number of this
81294  *
81295  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
81296  *
81297  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
81298  *
81299  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
81300  *
81301  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
81302  *
81303  * This field is valid only for IN endpoints.
81304  *
81305  * Field Access Macros:
81306  *
81307  */
81308 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */
81309 #define ALT_USB_DEV_DIEPCTL5_TXFNUM_LSB 22
81310 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */
81311 #define ALT_USB_DEV_DIEPCTL5_TXFNUM_MSB 25
81312 /* The width in bits of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */
81313 #define ALT_USB_DEV_DIEPCTL5_TXFNUM_WIDTH 4
81314 /* The mask used to set the ALT_USB_DEV_DIEPCTL5_TXFNUM register field value. */
81315 #define ALT_USB_DEV_DIEPCTL5_TXFNUM_SET_MSK 0x03c00000
81316 /* The mask used to clear the ALT_USB_DEV_DIEPCTL5_TXFNUM register field value. */
81317 #define ALT_USB_DEV_DIEPCTL5_TXFNUM_CLR_MSK 0xfc3fffff
81318 /* The reset value of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */
81319 #define ALT_USB_DEV_DIEPCTL5_TXFNUM_RESET 0x0
81320 /* Extracts the ALT_USB_DEV_DIEPCTL5_TXFNUM field value from a register. */
81321 #define ALT_USB_DEV_DIEPCTL5_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
81322 /* Produces a ALT_USB_DEV_DIEPCTL5_TXFNUM register field value suitable for setting the register. */
81323 #define ALT_USB_DEV_DIEPCTL5_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
81324 
81325 /*
81326  * Field : cnak
81327  *
81328  * Clear NAK (CNAK)
81329  *
81330  * A write to this bit clears the NAK bit For the endpoint.
81331  *
81332  * Field Enumeration Values:
81333  *
81334  * Enum | Value | Description
81335  * :----------------------------------|:------|:-------------
81336  * ALT_USB_DEV_DIEPCTL5_CNAK_E_INACT | 0x0 | No Clear NAK
81337  * ALT_USB_DEV_DIEPCTL5_CNAK_E_ACT | 0x1 | Clear NAK
81338  *
81339  * Field Access Macros:
81340  *
81341  */
81342 /*
81343  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_CNAK
81344  *
81345  * No Clear NAK
81346  */
81347 #define ALT_USB_DEV_DIEPCTL5_CNAK_E_INACT 0x0
81348 /*
81349  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_CNAK
81350  *
81351  * Clear NAK
81352  */
81353 #define ALT_USB_DEV_DIEPCTL5_CNAK_E_ACT 0x1
81354 
81355 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */
81356 #define ALT_USB_DEV_DIEPCTL5_CNAK_LSB 26
81357 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */
81358 #define ALT_USB_DEV_DIEPCTL5_CNAK_MSB 26
81359 /* The width in bits of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */
81360 #define ALT_USB_DEV_DIEPCTL5_CNAK_WIDTH 1
81361 /* The mask used to set the ALT_USB_DEV_DIEPCTL5_CNAK register field value. */
81362 #define ALT_USB_DEV_DIEPCTL5_CNAK_SET_MSK 0x04000000
81363 /* The mask used to clear the ALT_USB_DEV_DIEPCTL5_CNAK register field value. */
81364 #define ALT_USB_DEV_DIEPCTL5_CNAK_CLR_MSK 0xfbffffff
81365 /* The reset value of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */
81366 #define ALT_USB_DEV_DIEPCTL5_CNAK_RESET 0x0
81367 /* Extracts the ALT_USB_DEV_DIEPCTL5_CNAK field value from a register. */
81368 #define ALT_USB_DEV_DIEPCTL5_CNAK_GET(value) (((value) & 0x04000000) >> 26)
81369 /* Produces a ALT_USB_DEV_DIEPCTL5_CNAK register field value suitable for setting the register. */
81370 #define ALT_USB_DEV_DIEPCTL5_CNAK_SET(value) (((value) << 26) & 0x04000000)
81371 
81372 /*
81373  * Field : snak
81374  *
81375  * Set NAK (SNAK)
81376  *
81377  * A write to this bit sets the NAK bit For the endpoint.
81378  *
81379  * Using this bit, the application can control the transmission of NAK
81380  *
81381  * handshakes on an endpoint. The core can also Set this bit For an
81382  *
81383  * endpoint after a SETUP packet is received on that endpoint.
81384  *
81385  * Field Enumeration Values:
81386  *
81387  * Enum | Value | Description
81388  * :----------------------------------|:------|:------------
81389  * ALT_USB_DEV_DIEPCTL5_SNAK_E_INACT | 0x0 | No Set NAK
81390  * ALT_USB_DEV_DIEPCTL5_SNAK_E_ACT | 0x1 | Set NAK
81391  *
81392  * Field Access Macros:
81393  *
81394  */
81395 /*
81396  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SNAK
81397  *
81398  * No Set NAK
81399  */
81400 #define ALT_USB_DEV_DIEPCTL5_SNAK_E_INACT 0x0
81401 /*
81402  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SNAK
81403  *
81404  * Set NAK
81405  */
81406 #define ALT_USB_DEV_DIEPCTL5_SNAK_E_ACT 0x1
81407 
81408 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */
81409 #define ALT_USB_DEV_DIEPCTL5_SNAK_LSB 27
81410 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */
81411 #define ALT_USB_DEV_DIEPCTL5_SNAK_MSB 27
81412 /* The width in bits of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */
81413 #define ALT_USB_DEV_DIEPCTL5_SNAK_WIDTH 1
81414 /* The mask used to set the ALT_USB_DEV_DIEPCTL5_SNAK register field value. */
81415 #define ALT_USB_DEV_DIEPCTL5_SNAK_SET_MSK 0x08000000
81416 /* The mask used to clear the ALT_USB_DEV_DIEPCTL5_SNAK register field value. */
81417 #define ALT_USB_DEV_DIEPCTL5_SNAK_CLR_MSK 0xf7ffffff
81418 /* The reset value of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */
81419 #define ALT_USB_DEV_DIEPCTL5_SNAK_RESET 0x0
81420 /* Extracts the ALT_USB_DEV_DIEPCTL5_SNAK field value from a register. */
81421 #define ALT_USB_DEV_DIEPCTL5_SNAK_GET(value) (((value) & 0x08000000) >> 27)
81422 /* Produces a ALT_USB_DEV_DIEPCTL5_SNAK register field value suitable for setting the register. */
81423 #define ALT_USB_DEV_DIEPCTL5_SNAK_SET(value) (((value) << 27) & 0x08000000)
81424 
81425 /*
81426  * Field : setd0pid
81427  *
81428  * Set DATA0 PID (SetD0PID)
81429  *
81430  * Applies to interrupt/bulk IN and OUT endpoints only.
81431  *
81432  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
81433  * to DATA0.
81434  *
81435  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
81436  *
81437  * DMA mode.
81438  *
81439  * 1'b0 WO
81440  *
81441  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
81442  *
81443  * Applies to isochronous IN and OUT endpoints only.
81444  *
81445  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
81446  * (micro)
81447  *
81448  * frame.
81449  *
81450  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
81451  * number
81452  *
81453  * in which to send data is in the transmit descriptor structure. The frame in
81454  * which to
81455  *
81456  * receive data is updated in receive descriptor structure.
81457  *
81458  * Field Enumeration Values:
81459  *
81460  * Enum | Value | Description
81461  * :-------------------------------------|:------|:----------------------------
81462  * ALT_USB_DEV_DIEPCTL5_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
81463  * ALT_USB_DEV_DIEPCTL5_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
81464  *
81465  * Field Access Macros:
81466  *
81467  */
81468 /*
81469  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD0PID
81470  *
81471  * Disables Set DATA0 PID
81472  */
81473 #define ALT_USB_DEV_DIEPCTL5_SETD0PID_E_DISD 0x0
81474 /*
81475  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD0PID
81476  *
81477  * Endpoint Data PID to DATA0)
81478  */
81479 #define ALT_USB_DEV_DIEPCTL5_SETD0PID_E_END 0x1
81480 
81481 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */
81482 #define ALT_USB_DEV_DIEPCTL5_SETD0PID_LSB 28
81483 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */
81484 #define ALT_USB_DEV_DIEPCTL5_SETD0PID_MSB 28
81485 /* The width in bits of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */
81486 #define ALT_USB_DEV_DIEPCTL5_SETD0PID_WIDTH 1
81487 /* The mask used to set the ALT_USB_DEV_DIEPCTL5_SETD0PID register field value. */
81488 #define ALT_USB_DEV_DIEPCTL5_SETD0PID_SET_MSK 0x10000000
81489 /* The mask used to clear the ALT_USB_DEV_DIEPCTL5_SETD0PID register field value. */
81490 #define ALT_USB_DEV_DIEPCTL5_SETD0PID_CLR_MSK 0xefffffff
81491 /* The reset value of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */
81492 #define ALT_USB_DEV_DIEPCTL5_SETD0PID_RESET 0x0
81493 /* Extracts the ALT_USB_DEV_DIEPCTL5_SETD0PID field value from a register. */
81494 #define ALT_USB_DEV_DIEPCTL5_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
81495 /* Produces a ALT_USB_DEV_DIEPCTL5_SETD0PID register field value suitable for setting the register. */
81496 #define ALT_USB_DEV_DIEPCTL5_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
81497 
81498 /*
81499  * Field : setd1pid
81500  *
81501  * Set DATA1 PID (SetD1PID)
81502  *
81503  * Applies to interrupt/bulk IN and OUT endpoints only.
81504  *
81505  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
81506  * to DATA1.
81507  *
81508  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
81509  *
81510  * DMA mode.
81511  *
81512  * Set Odd (micro)frame (SetOddFr)
81513  *
81514  * Applies to isochronous IN and OUT endpoints only.
81515  *
81516  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
81517  *
81518  * (micro)frame.
81519  *
81520  * This field is not applicable for Scatter/Gather DMA mode.
81521  *
81522  * Field Enumeration Values:
81523  *
81524  * Enum | Value | Description
81525  * :-------------------------------------|:------|:-----------------------
81526  * ALT_USB_DEV_DIEPCTL5_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
81527  * ALT_USB_DEV_DIEPCTL5_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
81528  *
81529  * Field Access Macros:
81530  *
81531  */
81532 /*
81533  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD1PID
81534  *
81535  * Disables Set DATA1 PID
81536  */
81537 #define ALT_USB_DEV_DIEPCTL5_SETD1PID_E_DISD 0x0
81538 /*
81539  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD1PID
81540  *
81541  * Enables Set DATA1 PID
81542  */
81543 #define ALT_USB_DEV_DIEPCTL5_SETD1PID_E_END 0x1
81544 
81545 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */
81546 #define ALT_USB_DEV_DIEPCTL5_SETD1PID_LSB 29
81547 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */
81548 #define ALT_USB_DEV_DIEPCTL5_SETD1PID_MSB 29
81549 /* The width in bits of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */
81550 #define ALT_USB_DEV_DIEPCTL5_SETD1PID_WIDTH 1
81551 /* The mask used to set the ALT_USB_DEV_DIEPCTL5_SETD1PID register field value. */
81552 #define ALT_USB_DEV_DIEPCTL5_SETD1PID_SET_MSK 0x20000000
81553 /* The mask used to clear the ALT_USB_DEV_DIEPCTL5_SETD1PID register field value. */
81554 #define ALT_USB_DEV_DIEPCTL5_SETD1PID_CLR_MSK 0xdfffffff
81555 /* The reset value of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */
81556 #define ALT_USB_DEV_DIEPCTL5_SETD1PID_RESET 0x0
81557 /* Extracts the ALT_USB_DEV_DIEPCTL5_SETD1PID field value from a register. */
81558 #define ALT_USB_DEV_DIEPCTL5_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
81559 /* Produces a ALT_USB_DEV_DIEPCTL5_SETD1PID register field value suitable for setting the register. */
81560 #define ALT_USB_DEV_DIEPCTL5_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
81561 
81562 /*
81563  * Field : epdis
81564  *
81565  * Endpoint Disable (EPDis)
81566  *
81567  * Applies to IN and OUT endpoints.
81568  *
81569  * The application sets this bit to stop transmitting/receiving data on an
81570  * endpoint, even
81571  *
81572  * before the transfer for that endpoint is complete. The application must wait for
81573  * the
81574  *
81575  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
81576  * clears
81577  *
81578  * this bit before setting the Endpoint Disabled interrupt. The application must
81579  * set this bit
81580  *
81581  * only if Endpoint Enable is already set for this endpoint.
81582  *
81583  * Field Enumeration Values:
81584  *
81585  * Enum | Value | Description
81586  * :-----------------------------------|:------|:--------------------
81587  * ALT_USB_DEV_DIEPCTL5_EPDIS_E_INACT | 0x0 | No Endpoint Disable
81588  * ALT_USB_DEV_DIEPCTL5_EPDIS_E_ACT | 0x1 | Endpoint Disable
81589  *
81590  * Field Access Macros:
81591  *
81592  */
81593 /*
81594  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPDIS
81595  *
81596  * No Endpoint Disable
81597  */
81598 #define ALT_USB_DEV_DIEPCTL5_EPDIS_E_INACT 0x0
81599 /*
81600  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPDIS
81601  *
81602  * Endpoint Disable
81603  */
81604 #define ALT_USB_DEV_DIEPCTL5_EPDIS_E_ACT 0x1
81605 
81606 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */
81607 #define ALT_USB_DEV_DIEPCTL5_EPDIS_LSB 30
81608 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */
81609 #define ALT_USB_DEV_DIEPCTL5_EPDIS_MSB 30
81610 /* The width in bits of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */
81611 #define ALT_USB_DEV_DIEPCTL5_EPDIS_WIDTH 1
81612 /* The mask used to set the ALT_USB_DEV_DIEPCTL5_EPDIS register field value. */
81613 #define ALT_USB_DEV_DIEPCTL5_EPDIS_SET_MSK 0x40000000
81614 /* The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPDIS register field value. */
81615 #define ALT_USB_DEV_DIEPCTL5_EPDIS_CLR_MSK 0xbfffffff
81616 /* The reset value of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */
81617 #define ALT_USB_DEV_DIEPCTL5_EPDIS_RESET 0x0
81618 /* Extracts the ALT_USB_DEV_DIEPCTL5_EPDIS field value from a register. */
81619 #define ALT_USB_DEV_DIEPCTL5_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
81620 /* Produces a ALT_USB_DEV_DIEPCTL5_EPDIS register field value suitable for setting the register. */
81621 #define ALT_USB_DEV_DIEPCTL5_EPDIS_SET(value) (((value) << 30) & 0x40000000)
81622 
81623 /*
81624  * Field : epena
81625  *
81626  * Endpoint Enable (EPEna)
81627  *
81628  * Applies to IN and OUT endpoints.
81629  *
81630  * When Scatter/Gather DMA mode is enabled,
81631  *
81632  * For IN endpoints this bit indicates that the descriptor structure and data
81633  * buffer with
81634  *
81635  * data ready to transmit is setup.
81636  *
81637  * For OUT endpoint it indicates that the descriptor structure and data buffer to
81638  *
81639  * receive data is setup.
81640  *
81641  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
81642  *
81643  * DMA mode:
81644  *
81645  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
81646  * the
81647  *
81648  * endpoint.
81649  *
81650  * * For OUT endpoints, this bit indicates that the application has allocated the
81651  *
81652  * memory to start receiving data from the USB.
81653  *
81654  * * The core clears this bit before setting any of the following interrupts on
81655  * this
81656  *
81657  * endpoint:
81658  *
81659  * SETUP Phase Done
81660  *
81661  * Endpoint Disabled
81662  *
81663  * Transfer Completed
81664  *
81665  * Note: For control endpoints in DMA mode, this bit must be set to be able to
81666  * transfer
81667  *
81668  * SETUP data packets in memory.
81669  *
81670  * Field Enumeration Values:
81671  *
81672  * Enum | Value | Description
81673  * :-----------------------------------|:------|:-------------------------
81674  * ALT_USB_DEV_DIEPCTL5_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
81675  * ALT_USB_DEV_DIEPCTL5_EPENA_E_ACT | 0x1 | Endpoint Enable active
81676  *
81677  * Field Access Macros:
81678  *
81679  */
81680 /*
81681  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPENA
81682  *
81683  * Endpoint Enable inactive
81684  */
81685 #define ALT_USB_DEV_DIEPCTL5_EPENA_E_INACT 0x0
81686 /*
81687  * Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPENA
81688  *
81689  * Endpoint Enable active
81690  */
81691 #define ALT_USB_DEV_DIEPCTL5_EPENA_E_ACT 0x1
81692 
81693 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */
81694 #define ALT_USB_DEV_DIEPCTL5_EPENA_LSB 31
81695 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */
81696 #define ALT_USB_DEV_DIEPCTL5_EPENA_MSB 31
81697 /* The width in bits of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */
81698 #define ALT_USB_DEV_DIEPCTL5_EPENA_WIDTH 1
81699 /* The mask used to set the ALT_USB_DEV_DIEPCTL5_EPENA register field value. */
81700 #define ALT_USB_DEV_DIEPCTL5_EPENA_SET_MSK 0x80000000
81701 /* The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPENA register field value. */
81702 #define ALT_USB_DEV_DIEPCTL5_EPENA_CLR_MSK 0x7fffffff
81703 /* The reset value of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */
81704 #define ALT_USB_DEV_DIEPCTL5_EPENA_RESET 0x0
81705 /* Extracts the ALT_USB_DEV_DIEPCTL5_EPENA field value from a register. */
81706 #define ALT_USB_DEV_DIEPCTL5_EPENA_GET(value) (((value) & 0x80000000) >> 31)
81707 /* Produces a ALT_USB_DEV_DIEPCTL5_EPENA register field value suitable for setting the register. */
81708 #define ALT_USB_DEV_DIEPCTL5_EPENA_SET(value) (((value) << 31) & 0x80000000)
81709 
81710 #ifndef __ASSEMBLY__
81711 /*
81712  * WARNING: The C register and register group struct declarations are provided for
81713  * convenience and illustrative purposes. They should, however, be used with
81714  * caution as the C language standard provides no guarantees about the alignment or
81715  * atomicity of device memory accesses. The recommended practice for writing
81716  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
81717  * alt_write_word() functions.
81718  *
81719  * The struct declaration for register ALT_USB_DEV_DIEPCTL5.
81720  */
81721 struct ALT_USB_DEV_DIEPCTL5_s
81722 {
81723  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL5_MPS */
81724  uint32_t : 4; /* *UNDEFINED* */
81725  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL5_USBACTEP */
81726  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL5_DPID */
81727  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL5_NAKSTS */
81728  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL5_EPTYPE */
81729  uint32_t : 1; /* *UNDEFINED* */
81730  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL5_STALL */
81731  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL5_TXFNUM */
81732  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL5_CNAK */
81733  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL5_SNAK */
81734  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL5_SETD0PID */
81735  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL5_SETD1PID */
81736  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL5_EPDIS */
81737  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL5_EPENA */
81738 };
81739 
81740 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL5. */
81741 typedef volatile struct ALT_USB_DEV_DIEPCTL5_s ALT_USB_DEV_DIEPCTL5_t;
81742 #endif /* __ASSEMBLY__ */
81743 
81744 /* The reset value of the ALT_USB_DEV_DIEPCTL5 register. */
81745 #define ALT_USB_DEV_DIEPCTL5_RESET 0x00000000
81746 /* The byte offset of the ALT_USB_DEV_DIEPCTL5 register from the beginning of the component. */
81747 #define ALT_USB_DEV_DIEPCTL5_OFST 0x1a0
81748 /* The address of the ALT_USB_DEV_DIEPCTL5 register. */
81749 #define ALT_USB_DEV_DIEPCTL5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL5_OFST))
81750 
81751 /*
81752  * Register : diepint5
81753  *
81754  * Device IN Endpoint 5 Interrupt Register
81755  *
81756  * Register Layout
81757  *
81758  * Bits | Access | Reset | Description
81759  * :--------|:-------|:------|:---------------------------------
81760  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_XFERCOMPL
81761  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_EPDISBLD
81762  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_AHBERR
81763  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_TMO
81764  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_INTKNTXFEMP
81765  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_INTKNEPMIS
81766  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_INEPNAKEFF
81767  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT5_TXFEMP
81768  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN
81769  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_BNAINTR
81770  * [10] | ??? | 0x0 | *UNDEFINED*
81771  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_PKTDRPSTS
81772  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_BBLEERR
81773  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_NAKINTRPT
81774  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_NYETINTRPT
81775  * [31:15] | ??? | 0x0 | *UNDEFINED*
81776  *
81777  */
81778 /*
81779  * Field : xfercompl
81780  *
81781  * Transfer Completed Interrupt (XferCompl)
81782  *
81783  * Applies to IN and OUT endpoints.
81784  *
81785  * When Scatter/Gather DMA mode is enabled
81786  *
81787  * * For IN endpoint this field indicates that the requested data
81788  *
81789  * from the descriptor is moved from external system memory
81790  *
81791  * to internal FIFO.
81792  *
81793  * * For OUT endpoint this field indicates that the requested
81794  *
81795  * data from the internal FIFO is moved to external system
81796  *
81797  * memory. This interrupt is generated only when the
81798  *
81799  * corresponding endpoint descriptor is closed, and the IOC
81800  *
81801  * bit For the corresponding descriptor is Set.
81802  *
81803  * When Scatter/Gather DMA mode is disabled, this field
81804  *
81805  * indicates that the programmed transfer is complete on the
81806  *
81807  * AHB as well as on the USB, For this endpoint.
81808  *
81809  * Field Enumeration Values:
81810  *
81811  * Enum | Value | Description
81812  * :---------------------------------------|:------|:-----------------------------
81813  * ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_INACT | 0x0 | No Interrupt
81814  * ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
81815  *
81816  * Field Access Macros:
81817  *
81818  */
81819 /*
81820  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_XFERCOMPL
81821  *
81822  * No Interrupt
81823  */
81824 #define ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_INACT 0x0
81825 /*
81826  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_XFERCOMPL
81827  *
81828  * Transfer Completed Interrupt
81829  */
81830 #define ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_ACT 0x1
81831 
81832 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */
81833 #define ALT_USB_DEV_DIEPINT5_XFERCOMPL_LSB 0
81834 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */
81835 #define ALT_USB_DEV_DIEPINT5_XFERCOMPL_MSB 0
81836 /* The width in bits of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */
81837 #define ALT_USB_DEV_DIEPINT5_XFERCOMPL_WIDTH 1
81838 /* The mask used to set the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field value. */
81839 #define ALT_USB_DEV_DIEPINT5_XFERCOMPL_SET_MSK 0x00000001
81840 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field value. */
81841 #define ALT_USB_DEV_DIEPINT5_XFERCOMPL_CLR_MSK 0xfffffffe
81842 /* The reset value of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */
81843 #define ALT_USB_DEV_DIEPINT5_XFERCOMPL_RESET 0x0
81844 /* Extracts the ALT_USB_DEV_DIEPINT5_XFERCOMPL field value from a register. */
81845 #define ALT_USB_DEV_DIEPINT5_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
81846 /* Produces a ALT_USB_DEV_DIEPINT5_XFERCOMPL register field value suitable for setting the register. */
81847 #define ALT_USB_DEV_DIEPINT5_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
81848 
81849 /*
81850  * Field : epdisbld
81851  *
81852  * Endpoint Disabled Interrupt (EPDisbld)
81853  *
81854  * Applies to IN and OUT endpoints.
81855  *
81856  * This bit indicates that the endpoint is disabled per the
81857  *
81858  * application's request.
81859  *
81860  * Field Enumeration Values:
81861  *
81862  * Enum | Value | Description
81863  * :--------------------------------------|:------|:----------------------------
81864  * ALT_USB_DEV_DIEPINT5_EPDISBLD_E_INACT | 0x0 | No Interrupt
81865  * ALT_USB_DEV_DIEPINT5_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
81866  *
81867  * Field Access Macros:
81868  *
81869  */
81870 /*
81871  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_EPDISBLD
81872  *
81873  * No Interrupt
81874  */
81875 #define ALT_USB_DEV_DIEPINT5_EPDISBLD_E_INACT 0x0
81876 /*
81877  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_EPDISBLD
81878  *
81879  * Endpoint Disabled Interrupt
81880  */
81881 #define ALT_USB_DEV_DIEPINT5_EPDISBLD_E_ACT 0x1
81882 
81883 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */
81884 #define ALT_USB_DEV_DIEPINT5_EPDISBLD_LSB 1
81885 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */
81886 #define ALT_USB_DEV_DIEPINT5_EPDISBLD_MSB 1
81887 /* The width in bits of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */
81888 #define ALT_USB_DEV_DIEPINT5_EPDISBLD_WIDTH 1
81889 /* The mask used to set the ALT_USB_DEV_DIEPINT5_EPDISBLD register field value. */
81890 #define ALT_USB_DEV_DIEPINT5_EPDISBLD_SET_MSK 0x00000002
81891 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_EPDISBLD register field value. */
81892 #define ALT_USB_DEV_DIEPINT5_EPDISBLD_CLR_MSK 0xfffffffd
81893 /* The reset value of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */
81894 #define ALT_USB_DEV_DIEPINT5_EPDISBLD_RESET 0x0
81895 /* Extracts the ALT_USB_DEV_DIEPINT5_EPDISBLD field value from a register. */
81896 #define ALT_USB_DEV_DIEPINT5_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
81897 /* Produces a ALT_USB_DEV_DIEPINT5_EPDISBLD register field value suitable for setting the register. */
81898 #define ALT_USB_DEV_DIEPINT5_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
81899 
81900 /*
81901  * Field : ahberr
81902  *
81903  * AHB Error (AHBErr)
81904  *
81905  * Applies to IN and OUT endpoints.
81906  *
81907  * This is generated only in Internal DMA mode when there is an
81908  *
81909  * AHB error during an AHB read/write. The application can read
81910  *
81911  * the corresponding endpoint DMA address register to get the
81912  *
81913  * error address.
81914  *
81915  * Field Enumeration Values:
81916  *
81917  * Enum | Value | Description
81918  * :------------------------------------|:------|:--------------------
81919  * ALT_USB_DEV_DIEPINT5_AHBERR_E_INACT | 0x0 | No Interrupt
81920  * ALT_USB_DEV_DIEPINT5_AHBERR_E_ACT | 0x1 | AHB Error interrupt
81921  *
81922  * Field Access Macros:
81923  *
81924  */
81925 /*
81926  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_AHBERR
81927  *
81928  * No Interrupt
81929  */
81930 #define ALT_USB_DEV_DIEPINT5_AHBERR_E_INACT 0x0
81931 /*
81932  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_AHBERR
81933  *
81934  * AHB Error interrupt
81935  */
81936 #define ALT_USB_DEV_DIEPINT5_AHBERR_E_ACT 0x1
81937 
81938 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */
81939 #define ALT_USB_DEV_DIEPINT5_AHBERR_LSB 2
81940 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */
81941 #define ALT_USB_DEV_DIEPINT5_AHBERR_MSB 2
81942 /* The width in bits of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */
81943 #define ALT_USB_DEV_DIEPINT5_AHBERR_WIDTH 1
81944 /* The mask used to set the ALT_USB_DEV_DIEPINT5_AHBERR register field value. */
81945 #define ALT_USB_DEV_DIEPINT5_AHBERR_SET_MSK 0x00000004
81946 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_AHBERR register field value. */
81947 #define ALT_USB_DEV_DIEPINT5_AHBERR_CLR_MSK 0xfffffffb
81948 /* The reset value of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */
81949 #define ALT_USB_DEV_DIEPINT5_AHBERR_RESET 0x0
81950 /* Extracts the ALT_USB_DEV_DIEPINT5_AHBERR field value from a register. */
81951 #define ALT_USB_DEV_DIEPINT5_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
81952 /* Produces a ALT_USB_DEV_DIEPINT5_AHBERR register field value suitable for setting the register. */
81953 #define ALT_USB_DEV_DIEPINT5_AHBERR_SET(value) (((value) << 2) & 0x00000004)
81954 
81955 /*
81956  * Field : timeout
81957  *
81958  * Timeout Condition (TimeOUT)
81959  *
81960  * In shared TX FIFO mode, applies to non-isochronous IN
81961  *
81962  * endpoints only.
81963  *
81964  * In dedicated FIFO mode, applies only to Control IN
81965  *
81966  * endpoints.
81967  *
81968  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
81969  *
81970  * asserted.
81971  *
81972  * Indicates that the core has detected a timeout condition on the
81973  *
81974  * USB For the last IN token on this endpoint.
81975  *
81976  * Field Enumeration Values:
81977  *
81978  * Enum | Value | Description
81979  * :---------------------------------|:------|:------------------
81980  * ALT_USB_DEV_DIEPINT5_TMO_E_INACT | 0x0 | No interrupt
81981  * ALT_USB_DEV_DIEPINT5_TMO_E_ACT | 0x1 | Timeout interrupy
81982  *
81983  * Field Access Macros:
81984  *
81985  */
81986 /*
81987  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TMO
81988  *
81989  * No interrupt
81990  */
81991 #define ALT_USB_DEV_DIEPINT5_TMO_E_INACT 0x0
81992 /*
81993  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TMO
81994  *
81995  * Timeout interrupy
81996  */
81997 #define ALT_USB_DEV_DIEPINT5_TMO_E_ACT 0x1
81998 
81999 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_TMO register field. */
82000 #define ALT_USB_DEV_DIEPINT5_TMO_LSB 3
82001 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_TMO register field. */
82002 #define ALT_USB_DEV_DIEPINT5_TMO_MSB 3
82003 /* The width in bits of the ALT_USB_DEV_DIEPINT5_TMO register field. */
82004 #define ALT_USB_DEV_DIEPINT5_TMO_WIDTH 1
82005 /* The mask used to set the ALT_USB_DEV_DIEPINT5_TMO register field value. */
82006 #define ALT_USB_DEV_DIEPINT5_TMO_SET_MSK 0x00000008
82007 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_TMO register field value. */
82008 #define ALT_USB_DEV_DIEPINT5_TMO_CLR_MSK 0xfffffff7
82009 /* The reset value of the ALT_USB_DEV_DIEPINT5_TMO register field. */
82010 #define ALT_USB_DEV_DIEPINT5_TMO_RESET 0x0
82011 /* Extracts the ALT_USB_DEV_DIEPINT5_TMO field value from a register. */
82012 #define ALT_USB_DEV_DIEPINT5_TMO_GET(value) (((value) & 0x00000008) >> 3)
82013 /* Produces a ALT_USB_DEV_DIEPINT5_TMO register field value suitable for setting the register. */
82014 #define ALT_USB_DEV_DIEPINT5_TMO_SET(value) (((value) << 3) & 0x00000008)
82015 
82016 /*
82017  * Field : intkntxfemp
82018  *
82019  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
82020  *
82021  * Applies to non-periodic IN endpoints only.
82022  *
82023  * Indicates that an IN token was received when the associated
82024  *
82025  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
82026  *
82027  * asserted on the endpoint For which the IN token was received.
82028  *
82029  * Field Enumeration Values:
82030  *
82031  * Enum | Value | Description
82032  * :-----------------------------------------|:------|:----------------------------
82033  * ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
82034  * ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
82035  *
82036  * Field Access Macros:
82037  *
82038  */
82039 /*
82040  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNTXFEMP
82041  *
82042  * No interrupt
82043  */
82044 #define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_INACT 0x0
82045 /*
82046  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNTXFEMP
82047  *
82048  * IN Token Received Interrupt
82049  */
82050 #define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_ACT 0x1
82051 
82052 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */
82053 #define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_LSB 4
82054 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */
82055 #define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_MSB 4
82056 /* The width in bits of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */
82057 #define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_WIDTH 1
82058 /* The mask used to set the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field value. */
82059 #define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_SET_MSK 0x00000010
82060 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field value. */
82061 #define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_CLR_MSK 0xffffffef
82062 /* The reset value of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */
82063 #define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_RESET 0x0
82064 /* Extracts the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP field value from a register. */
82065 #define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
82066 /* Produces a ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field value suitable for setting the register. */
82067 #define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
82068 
82069 /*
82070  * Field : intknepmis
82071  *
82072  * IN Token Received with EP Mismatch (INTknEPMis)
82073  *
82074  * Applies to non-periodic IN endpoints only.
82075  *
82076  * Indicates that the data in the top of the non-periodic TxFIFO
82077  *
82078  * belongs to an endpoint other than the one For which the IN token
82079  *
82080  * was received. This interrupt is asserted on the endpoint For
82081  *
82082  * which the IN token was received.
82083  *
82084  * Field Enumeration Values:
82085  *
82086  * Enum | Value | Description
82087  * :----------------------------------------|:------|:---------------------------------------------
82088  * ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_INACT | 0x0 | No interrupt
82089  * ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
82090  *
82091  * Field Access Macros:
82092  *
82093  */
82094 /*
82095  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNEPMIS
82096  *
82097  * No interrupt
82098  */
82099 #define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_INACT 0x0
82100 /*
82101  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNEPMIS
82102  *
82103  * IN Token Received with EP Mismatch interrupt
82104  */
82105 #define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_ACT 0x1
82106 
82107 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */
82108 #define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_LSB 5
82109 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */
82110 #define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_MSB 5
82111 /* The width in bits of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */
82112 #define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_WIDTH 1
82113 /* The mask used to set the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field value. */
82114 #define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_SET_MSK 0x00000020
82115 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field value. */
82116 #define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_CLR_MSK 0xffffffdf
82117 /* The reset value of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */
82118 #define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_RESET 0x0
82119 /* Extracts the ALT_USB_DEV_DIEPINT5_INTKNEPMIS field value from a register. */
82120 #define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
82121 /* Produces a ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field value suitable for setting the register. */
82122 #define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
82123 
82124 /*
82125  * Field : inepnakeff
82126  *
82127  * IN Endpoint NAK Effective (INEPNakEff)
82128  *
82129  * Applies to periodic IN endpoints only.
82130  *
82131  * This bit can be cleared when the application clears the IN
82132  *
82133  * endpoint NAK by writing to DIEPCTLn.CNAK.
82134  *
82135  * This interrupt indicates that the core has sampled the NAK bit
82136  *
82137  * Set (either by the application or by the core). The interrupt
82138  *
82139  * indicates that the IN endpoint NAK bit Set by the application has
82140  *
82141  * taken effect in the core.
82142  *
82143  * This interrupt does not guarantee that a NAK handshake is sent
82144  *
82145  * on the USB. A STALL bit takes priority over a NAK bit.
82146  *
82147  * Field Enumeration Values:
82148  *
82149  * Enum | Value | Description
82150  * :----------------------------------------|:------|:------------------------------------
82151  * ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_INACT | 0x0 | No interrupt
82152  * ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
82153  *
82154  * Field Access Macros:
82155  *
82156  */
82157 /*
82158  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INEPNAKEFF
82159  *
82160  * No interrupt
82161  */
82162 #define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_INACT 0x0
82163 /*
82164  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_INEPNAKEFF
82165  *
82166  * IN Endpoint NAK Effective interrupt
82167  */
82168 #define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_ACT 0x1
82169 
82170 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */
82171 #define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_LSB 6
82172 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */
82173 #define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_MSB 6
82174 /* The width in bits of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */
82175 #define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_WIDTH 1
82176 /* The mask used to set the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field value. */
82177 #define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_SET_MSK 0x00000040
82178 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field value. */
82179 #define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_CLR_MSK 0xffffffbf
82180 /* The reset value of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */
82181 #define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_RESET 0x0
82182 /* Extracts the ALT_USB_DEV_DIEPINT5_INEPNAKEFF field value from a register. */
82183 #define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
82184 /* Produces a ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field value suitable for setting the register. */
82185 #define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
82186 
82187 /*
82188  * Field : txfemp
82189  *
82190  * Transmit FIFO Empty (TxFEmp)
82191  *
82192  * This bit is valid only For IN Endpoints
82193  *
82194  * This interrupt is asserted when the TxFIFO For this endpoint is
82195  *
82196  * either half or completely empty. The half or completely empty
82197  *
82198  * status is determined by the TxFIFO Empty Level bit in the Core
82199  *
82200  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
82201  *
82202  * Field Enumeration Values:
82203  *
82204  * Enum | Value | Description
82205  * :------------------------------------|:------|:------------------------------
82206  * ALT_USB_DEV_DIEPINT5_TXFEMP_E_INACT | 0x0 | No interrupt
82207  * ALT_USB_DEV_DIEPINT5_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
82208  *
82209  * Field Access Macros:
82210  *
82211  */
82212 /*
82213  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFEMP
82214  *
82215  * No interrupt
82216  */
82217 #define ALT_USB_DEV_DIEPINT5_TXFEMP_E_INACT 0x0
82218 /*
82219  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFEMP
82220  *
82221  * Transmit FIFO Empty interrupt
82222  */
82223 #define ALT_USB_DEV_DIEPINT5_TXFEMP_E_ACT 0x1
82224 
82225 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */
82226 #define ALT_USB_DEV_DIEPINT5_TXFEMP_LSB 7
82227 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */
82228 #define ALT_USB_DEV_DIEPINT5_TXFEMP_MSB 7
82229 /* The width in bits of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */
82230 #define ALT_USB_DEV_DIEPINT5_TXFEMP_WIDTH 1
82231 /* The mask used to set the ALT_USB_DEV_DIEPINT5_TXFEMP register field value. */
82232 #define ALT_USB_DEV_DIEPINT5_TXFEMP_SET_MSK 0x00000080
82233 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_TXFEMP register field value. */
82234 #define ALT_USB_DEV_DIEPINT5_TXFEMP_CLR_MSK 0xffffff7f
82235 /* The reset value of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */
82236 #define ALT_USB_DEV_DIEPINT5_TXFEMP_RESET 0x1
82237 /* Extracts the ALT_USB_DEV_DIEPINT5_TXFEMP field value from a register. */
82238 #define ALT_USB_DEV_DIEPINT5_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
82239 /* Produces a ALT_USB_DEV_DIEPINT5_TXFEMP register field value suitable for setting the register. */
82240 #define ALT_USB_DEV_DIEPINT5_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
82241 
82242 /*
82243  * Field : txfifoundrn
82244  *
82245  * Fifo Underrun (TxfifoUndrn)
82246  *
82247  * Applies to IN endpoints Only
82248  *
82249  * This bit is valid only If thresholding is enabled. The core generates this
82250  * interrupt when
82251  *
82252  * it detects a transmit FIFO underrun condition For this endpoint.
82253  *
82254  * Field Enumeration Values:
82255  *
82256  * Enum | Value | Description
82257  * :-----------------------------------------|:------|:------------------------
82258  * ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
82259  * ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
82260  *
82261  * Field Access Macros:
82262  *
82263  */
82264 /*
82265  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN
82266  *
82267  * No interrupt
82268  */
82269 #define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_INACT 0x0
82270 /*
82271  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN
82272  *
82273  * Fifo Underrun interrupt
82274  */
82275 #define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_ACT 0x1
82276 
82277 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */
82278 #define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_LSB 8
82279 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */
82280 #define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_MSB 8
82281 /* The width in bits of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */
82282 #define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_WIDTH 1
82283 /* The mask used to set the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field value. */
82284 #define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_SET_MSK 0x00000100
82285 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field value. */
82286 #define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_CLR_MSK 0xfffffeff
82287 /* The reset value of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */
82288 #define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_RESET 0x0
82289 /* Extracts the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN field value from a register. */
82290 #define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
82291 /* Produces a ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field value suitable for setting the register. */
82292 #define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
82293 
82294 /*
82295  * Field : bnaintr
82296  *
82297  * BNA (Buffer Not Available) Interrupt (BNAIntr)
82298  *
82299  * This bit is valid only when Scatter/Gather DMA mode is enabled.
82300  *
82301  * The core generates this interrupt when the descriptor accessed
82302  *
82303  * is not ready For the Core to process, such as Host busy or DMA
82304  *
82305  * done
82306  *
82307  * Field Enumeration Values:
82308  *
82309  * Enum | Value | Description
82310  * :-------------------------------------|:------|:--------------
82311  * ALT_USB_DEV_DIEPINT5_BNAINTR_E_INACT | 0x0 | No interrupt
82312  * ALT_USB_DEV_DIEPINT5_BNAINTR_E_ACT | 0x1 | BNA interrupt
82313  *
82314  * Field Access Macros:
82315  *
82316  */
82317 /*
82318  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_BNAINTR
82319  *
82320  * No interrupt
82321  */
82322 #define ALT_USB_DEV_DIEPINT5_BNAINTR_E_INACT 0x0
82323 /*
82324  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_BNAINTR
82325  *
82326  * BNA interrupt
82327  */
82328 #define ALT_USB_DEV_DIEPINT5_BNAINTR_E_ACT 0x1
82329 
82330 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */
82331 #define ALT_USB_DEV_DIEPINT5_BNAINTR_LSB 9
82332 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */
82333 #define ALT_USB_DEV_DIEPINT5_BNAINTR_MSB 9
82334 /* The width in bits of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */
82335 #define ALT_USB_DEV_DIEPINT5_BNAINTR_WIDTH 1
82336 /* The mask used to set the ALT_USB_DEV_DIEPINT5_BNAINTR register field value. */
82337 #define ALT_USB_DEV_DIEPINT5_BNAINTR_SET_MSK 0x00000200
82338 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_BNAINTR register field value. */
82339 #define ALT_USB_DEV_DIEPINT5_BNAINTR_CLR_MSK 0xfffffdff
82340 /* The reset value of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */
82341 #define ALT_USB_DEV_DIEPINT5_BNAINTR_RESET 0x0
82342 /* Extracts the ALT_USB_DEV_DIEPINT5_BNAINTR field value from a register. */
82343 #define ALT_USB_DEV_DIEPINT5_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
82344 /* Produces a ALT_USB_DEV_DIEPINT5_BNAINTR register field value suitable for setting the register. */
82345 #define ALT_USB_DEV_DIEPINT5_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
82346 
82347 /*
82348  * Field : pktdrpsts
82349  *
82350  * Packet Drop Status (PktDrpSts)
82351  *
82352  * This bit indicates to the application that an ISOC OUT packet has been dropped.
82353  * This
82354  *
82355  * bit does not have an associated mask bit and does not generate an interrupt.
82356  *
82357  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
82358  * transfer
82359  *
82360  * interrupt feature is selected.
82361  *
82362  * Field Enumeration Values:
82363  *
82364  * Enum | Value | Description
82365  * :---------------------------------------|:------|:-----------------------------
82366  * ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_INACT | 0x0 | No interrupt
82367  * ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
82368  *
82369  * Field Access Macros:
82370  *
82371  */
82372 /*
82373  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_PKTDRPSTS
82374  *
82375  * No interrupt
82376  */
82377 #define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_INACT 0x0
82378 /*
82379  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_PKTDRPSTS
82380  *
82381  * Packet Drop Status interrupt
82382  */
82383 #define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_ACT 0x1
82384 
82385 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */
82386 #define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_LSB 11
82387 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */
82388 #define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_MSB 11
82389 /* The width in bits of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */
82390 #define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_WIDTH 1
82391 /* The mask used to set the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field value. */
82392 #define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_SET_MSK 0x00000800
82393 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field value. */
82394 #define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_CLR_MSK 0xfffff7ff
82395 /* The reset value of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */
82396 #define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_RESET 0x0
82397 /* Extracts the ALT_USB_DEV_DIEPINT5_PKTDRPSTS field value from a register. */
82398 #define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
82399 /* Produces a ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field value suitable for setting the register. */
82400 #define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
82401 
82402 /*
82403  * Field : bbleerr
82404  *
82405  * NAK Interrupt (BbleErr)
82406  *
82407  * The core generates this interrupt when babble is received for the endpoint.
82408  *
82409  * Field Enumeration Values:
82410  *
82411  * Enum | Value | Description
82412  * :-------------------------------------|:------|:------------------
82413  * ALT_USB_DEV_DIEPINT5_BBLEERR_E_INACT | 0x0 | No interrupt
82414  * ALT_USB_DEV_DIEPINT5_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
82415  *
82416  * Field Access Macros:
82417  *
82418  */
82419 /*
82420  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_BBLEERR
82421  *
82422  * No interrupt
82423  */
82424 #define ALT_USB_DEV_DIEPINT5_BBLEERR_E_INACT 0x0
82425 /*
82426  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_BBLEERR
82427  *
82428  * BbleErr interrupt
82429  */
82430 #define ALT_USB_DEV_DIEPINT5_BBLEERR_E_ACT 0x1
82431 
82432 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */
82433 #define ALT_USB_DEV_DIEPINT5_BBLEERR_LSB 12
82434 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */
82435 #define ALT_USB_DEV_DIEPINT5_BBLEERR_MSB 12
82436 /* The width in bits of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */
82437 #define ALT_USB_DEV_DIEPINT5_BBLEERR_WIDTH 1
82438 /* The mask used to set the ALT_USB_DEV_DIEPINT5_BBLEERR register field value. */
82439 #define ALT_USB_DEV_DIEPINT5_BBLEERR_SET_MSK 0x00001000
82440 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_BBLEERR register field value. */
82441 #define ALT_USB_DEV_DIEPINT5_BBLEERR_CLR_MSK 0xffffefff
82442 /* The reset value of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */
82443 #define ALT_USB_DEV_DIEPINT5_BBLEERR_RESET 0x0
82444 /* Extracts the ALT_USB_DEV_DIEPINT5_BBLEERR field value from a register. */
82445 #define ALT_USB_DEV_DIEPINT5_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
82446 /* Produces a ALT_USB_DEV_DIEPINT5_BBLEERR register field value suitable for setting the register. */
82447 #define ALT_USB_DEV_DIEPINT5_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
82448 
82449 /*
82450  * Field : nakintrpt
82451  *
82452  * NAK Interrupt (NAKInterrupt)
82453  *
82454  * The core generates this interrupt when a NAK is transmitted or received by the
82455  * device.
82456  *
82457  * In case of isochronous IN endpoints the interrupt gets generated when a zero
82458  * length
82459  *
82460  * packet is transmitted due to un-availability of data in the TXFifo.
82461  *
82462  * Field Enumeration Values:
82463  *
82464  * Enum | Value | Description
82465  * :---------------------------------------|:------|:--------------
82466  * ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_INACT | 0x0 | No interrupt
82467  * ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
82468  *
82469  * Field Access Macros:
82470  *
82471  */
82472 /*
82473  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_NAKINTRPT
82474  *
82475  * No interrupt
82476  */
82477 #define ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_INACT 0x0
82478 /*
82479  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_NAKINTRPT
82480  *
82481  * NAK Interrupt
82482  */
82483 #define ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_ACT 0x1
82484 
82485 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */
82486 #define ALT_USB_DEV_DIEPINT5_NAKINTRPT_LSB 13
82487 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */
82488 #define ALT_USB_DEV_DIEPINT5_NAKINTRPT_MSB 13
82489 /* The width in bits of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */
82490 #define ALT_USB_DEV_DIEPINT5_NAKINTRPT_WIDTH 1
82491 /* The mask used to set the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field value. */
82492 #define ALT_USB_DEV_DIEPINT5_NAKINTRPT_SET_MSK 0x00002000
82493 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field value. */
82494 #define ALT_USB_DEV_DIEPINT5_NAKINTRPT_CLR_MSK 0xffffdfff
82495 /* The reset value of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */
82496 #define ALT_USB_DEV_DIEPINT5_NAKINTRPT_RESET 0x0
82497 /* Extracts the ALT_USB_DEV_DIEPINT5_NAKINTRPT field value from a register. */
82498 #define ALT_USB_DEV_DIEPINT5_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
82499 /* Produces a ALT_USB_DEV_DIEPINT5_NAKINTRPT register field value suitable for setting the register. */
82500 #define ALT_USB_DEV_DIEPINT5_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
82501 
82502 /*
82503  * Field : nyetintrpt
82504  *
82505  * NYET Interrupt (NYETIntrpt)
82506  *
82507  * The core generates this interrupt when a NYET response is transmitted for a non
82508  * isochronous OUT endpoint.
82509  *
82510  * Field Enumeration Values:
82511  *
82512  * Enum | Value | Description
82513  * :----------------------------------------|:------|:---------------
82514  * ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_INACT | 0x0 | No interrupt
82515  * ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
82516  *
82517  * Field Access Macros:
82518  *
82519  */
82520 /*
82521  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_NYETINTRPT
82522  *
82523  * No interrupt
82524  */
82525 #define ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_INACT 0x0
82526 /*
82527  * Enumerated value for register field ALT_USB_DEV_DIEPINT5_NYETINTRPT
82528  *
82529  * NYET Interrupt
82530  */
82531 #define ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_ACT 0x1
82532 
82533 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */
82534 #define ALT_USB_DEV_DIEPINT5_NYETINTRPT_LSB 14
82535 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */
82536 #define ALT_USB_DEV_DIEPINT5_NYETINTRPT_MSB 14
82537 /* The width in bits of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */
82538 #define ALT_USB_DEV_DIEPINT5_NYETINTRPT_WIDTH 1
82539 /* The mask used to set the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field value. */
82540 #define ALT_USB_DEV_DIEPINT5_NYETINTRPT_SET_MSK 0x00004000
82541 /* The mask used to clear the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field value. */
82542 #define ALT_USB_DEV_DIEPINT5_NYETINTRPT_CLR_MSK 0xffffbfff
82543 /* The reset value of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */
82544 #define ALT_USB_DEV_DIEPINT5_NYETINTRPT_RESET 0x0
82545 /* Extracts the ALT_USB_DEV_DIEPINT5_NYETINTRPT field value from a register. */
82546 #define ALT_USB_DEV_DIEPINT5_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
82547 /* Produces a ALT_USB_DEV_DIEPINT5_NYETINTRPT register field value suitable for setting the register. */
82548 #define ALT_USB_DEV_DIEPINT5_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
82549 
82550 #ifndef __ASSEMBLY__
82551 /*
82552  * WARNING: The C register and register group struct declarations are provided for
82553  * convenience and illustrative purposes. They should, however, be used with
82554  * caution as the C language standard provides no guarantees about the alignment or
82555  * atomicity of device memory accesses. The recommended practice for writing
82556  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
82557  * alt_write_word() functions.
82558  *
82559  * The struct declaration for register ALT_USB_DEV_DIEPINT5.
82560  */
82561 struct ALT_USB_DEV_DIEPINT5_s
82562 {
82563  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT5_XFERCOMPL */
82564  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT5_EPDISBLD */
82565  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT5_AHBERR */
82566  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT5_TMO */
82567  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT5_INTKNTXFEMP */
82568  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT5_INTKNEPMIS */
82569  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT5_INEPNAKEFF */
82570  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT5_TXFEMP */
82571  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN */
82572  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT5_BNAINTR */
82573  uint32_t : 1; /* *UNDEFINED* */
82574  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT5_PKTDRPSTS */
82575  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT5_BBLEERR */
82576  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT5_NAKINTRPT */
82577  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT5_NYETINTRPT */
82578  uint32_t : 17; /* *UNDEFINED* */
82579 };
82580 
82581 /* The typedef declaration for register ALT_USB_DEV_DIEPINT5. */
82582 typedef volatile struct ALT_USB_DEV_DIEPINT5_s ALT_USB_DEV_DIEPINT5_t;
82583 #endif /* __ASSEMBLY__ */
82584 
82585 /* The reset value of the ALT_USB_DEV_DIEPINT5 register. */
82586 #define ALT_USB_DEV_DIEPINT5_RESET 0x00000080
82587 /* The byte offset of the ALT_USB_DEV_DIEPINT5 register from the beginning of the component. */
82588 #define ALT_USB_DEV_DIEPINT5_OFST 0x1a8
82589 /* The address of the ALT_USB_DEV_DIEPINT5 register. */
82590 #define ALT_USB_DEV_DIEPINT5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT5_OFST))
82591 
82592 /*
82593  * Register : dieptsiz5
82594  *
82595  * Device IN Endpoint 5 Transfer Size Register
82596  *
82597  * Register Layout
82598  *
82599  * Bits | Access | Reset | Description
82600  * :--------|:-------|:------|:-------------------------------
82601  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ5_XFERSIZE
82602  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ5_PKTCNT
82603  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ5_MC
82604  * [31] | ??? | 0x0 | *UNDEFINED*
82605  *
82606  */
82607 /*
82608  * Field : xfersize
82609  *
82610  * Transfer Size (XferSize)
82611  *
82612  * Indicates the transfer size in bytes For endpoint 0. The core
82613  *
82614  * interrupts the application only after it has exhausted the transfer
82615  *
82616  * size amount of data. The transfer size can be Set to the
82617  *
82618  * maximum packet size of the endpoint, to be interrupted at the
82619  *
82620  * end of each packet.
82621  *
82622  * The core decrements this field every time a packet from the
82623  *
82624  * external memory is written to the TxFIFO.
82625  *
82626  * Field Access Macros:
82627  *
82628  */
82629 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */
82630 #define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_LSB 0
82631 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */
82632 #define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_MSB 18
82633 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */
82634 #define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_WIDTH 19
82635 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field value. */
82636 #define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_SET_MSK 0x0007ffff
82637 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field value. */
82638 #define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_CLR_MSK 0xfff80000
82639 /* The reset value of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */
82640 #define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_RESET 0x0
82641 /* Extracts the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE field value from a register. */
82642 #define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
82643 /* Produces a ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field value suitable for setting the register. */
82644 #define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
82645 
82646 /*
82647  * Field : pktcnt
82648  *
82649  * Packet Count (PktCnt)
82650  *
82651  * Indicates the total number of USB packets that constitute the
82652  *
82653  * Transfer Size amount of data For endpoint 0.
82654  *
82655  * This field is decremented every time a packet (maximum size or
82656  *
82657  * short packet) is read from the TxFIFO.
82658  *
82659  * Field Access Macros:
82660  *
82661  */
82662 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */
82663 #define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_LSB 19
82664 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */
82665 #define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_MSB 28
82666 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */
82667 #define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_WIDTH 10
82668 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field value. */
82669 #define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_SET_MSK 0x1ff80000
82670 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field value. */
82671 #define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_CLR_MSK 0xe007ffff
82672 /* The reset value of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */
82673 #define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_RESET 0x0
82674 /* Extracts the ALT_USB_DEV_DIEPTSIZ5_PKTCNT field value from a register. */
82675 #define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
82676 /* Produces a ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field value suitable for setting the register. */
82677 #define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
82678 
82679 /*
82680  * Field : mc
82681  *
82682  * Applies to IN endpoints only.
82683  *
82684  * For periodic IN endpoints, this field indicates the number of packets that must
82685  * be transmitted per microframe on the USB. The core uses this field to calculate
82686  * the data PID for isochronous IN endpoints.
82687  *
82688  * 2'b01: 1 packet
82689  *
82690  * 2'b10: 2 packets
82691  *
82692  * 2'b11: 3 packets
82693  *
82694  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
82695  * specifies the number of packets the core must fetchfor an IN endpoint before it
82696  * switches to the endpoint pointed to by the Next Endpoint field of the Device
82697  * Endpoint-n Control register (DIEPCTLn.NextEp)
82698  *
82699  * Field Enumeration Values:
82700  *
82701  * Enum | Value | Description
82702  * :------------------------------------|:------|:------------
82703  * ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTONE | 0x1 | 1 packet
82704  * ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTWO | 0x2 | 2 packets
82705  * ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTHREE | 0x3 | 3 packets
82706  *
82707  * Field Access Macros:
82708  *
82709  */
82710 /*
82711  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ5_MC
82712  *
82713  * 1 packet
82714  */
82715 #define ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTONE 0x1
82716 /*
82717  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ5_MC
82718  *
82719  * 2 packets
82720  */
82721 #define ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTWO 0x2
82722 /*
82723  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ5_MC
82724  *
82725  * 3 packets
82726  */
82727 #define ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTHREE 0x3
82728 
82729 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */
82730 #define ALT_USB_DEV_DIEPTSIZ5_MC_LSB 29
82731 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */
82732 #define ALT_USB_DEV_DIEPTSIZ5_MC_MSB 30
82733 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */
82734 #define ALT_USB_DEV_DIEPTSIZ5_MC_WIDTH 2
82735 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ5_MC register field value. */
82736 #define ALT_USB_DEV_DIEPTSIZ5_MC_SET_MSK 0x60000000
82737 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ5_MC register field value. */
82738 #define ALT_USB_DEV_DIEPTSIZ5_MC_CLR_MSK 0x9fffffff
82739 /* The reset value of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */
82740 #define ALT_USB_DEV_DIEPTSIZ5_MC_RESET 0x0
82741 /* Extracts the ALT_USB_DEV_DIEPTSIZ5_MC field value from a register. */
82742 #define ALT_USB_DEV_DIEPTSIZ5_MC_GET(value) (((value) & 0x60000000) >> 29)
82743 /* Produces a ALT_USB_DEV_DIEPTSIZ5_MC register field value suitable for setting the register. */
82744 #define ALT_USB_DEV_DIEPTSIZ5_MC_SET(value) (((value) << 29) & 0x60000000)
82745 
82746 #ifndef __ASSEMBLY__
82747 /*
82748  * WARNING: The C register and register group struct declarations are provided for
82749  * convenience and illustrative purposes. They should, however, be used with
82750  * caution as the C language standard provides no guarantees about the alignment or
82751  * atomicity of device memory accesses. The recommended practice for writing
82752  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
82753  * alt_write_word() functions.
82754  *
82755  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ5.
82756  */
82757 struct ALT_USB_DEV_DIEPTSIZ5_s
82758 {
82759  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ5_XFERSIZE */
82760  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ5_PKTCNT */
82761  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ5_MC */
82762  uint32_t : 1; /* *UNDEFINED* */
82763 };
82764 
82765 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ5. */
82766 typedef volatile struct ALT_USB_DEV_DIEPTSIZ5_s ALT_USB_DEV_DIEPTSIZ5_t;
82767 #endif /* __ASSEMBLY__ */
82768 
82769 /* The reset value of the ALT_USB_DEV_DIEPTSIZ5 register. */
82770 #define ALT_USB_DEV_DIEPTSIZ5_RESET 0x00000000
82771 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ5 register from the beginning of the component. */
82772 #define ALT_USB_DEV_DIEPTSIZ5_OFST 0x1b0
82773 /* The address of the ALT_USB_DEV_DIEPTSIZ5 register. */
82774 #define ALT_USB_DEV_DIEPTSIZ5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ5_OFST))
82775 
82776 /*
82777  * Register : diepdma5
82778  *
82779  * Device IN Endpoint 5 DMA Address Register
82780  *
82781  * Register Layout
82782  *
82783  * Bits | Access | Reset | Description
82784  * :-------|:-------|:--------|:------------------------------
82785  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA5_DIEPDMA5
82786  *
82787  */
82788 /*
82789  * Field : diepdma5
82790  *
82791  * Holds the start address of the external memory for storing or fetching endpoint
82792  *
82793  * data.
82794  *
82795  * Note: For control endpoints, this field stores control OUT data packets as well
82796  * as
82797  *
82798  * SETUP transaction data packets. When more than three SETUP packets are
82799  *
82800  * received back-to-back, the SETUP data packet in the memory is overwritten.
82801  *
82802  * This register is incremented on every AHB transaction. The application can give
82803  *
82804  * only a DWORD-aligned address.
82805  *
82806  * When Scatter/Gather DMA mode is not enabled, the application programs the
82807  *
82808  * start address value in this field.
82809  *
82810  * When Scatter/Gather DMA mode is enabled, this field indicates the base
82811  *
82812  * pointer for the descriptor list.
82813  *
82814  * Field Access Macros:
82815  *
82816  */
82817 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field. */
82818 #define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_LSB 0
82819 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field. */
82820 #define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_MSB 31
82821 /* The width in bits of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field. */
82822 #define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_WIDTH 32
82823 /* The mask used to set the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field value. */
82824 #define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_SET_MSK 0xffffffff
82825 /* The mask used to clear the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field value. */
82826 #define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_CLR_MSK 0x00000000
82827 /* The reset value of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field is UNKNOWN. */
82828 #define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_RESET 0x0
82829 /* Extracts the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 field value from a register. */
82830 #define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_GET(value) (((value) & 0xffffffff) >> 0)
82831 /* Produces a ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field value suitable for setting the register. */
82832 #define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_SET(value) (((value) << 0) & 0xffffffff)
82833 
82834 #ifndef __ASSEMBLY__
82835 /*
82836  * WARNING: The C register and register group struct declarations are provided for
82837  * convenience and illustrative purposes. They should, however, be used with
82838  * caution as the C language standard provides no guarantees about the alignment or
82839  * atomicity of device memory accesses. The recommended practice for writing
82840  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
82841  * alt_write_word() functions.
82842  *
82843  * The struct declaration for register ALT_USB_DEV_DIEPDMA5.
82844  */
82845 struct ALT_USB_DEV_DIEPDMA5_s
82846 {
82847  uint32_t diepdma5 : 32; /* ALT_USB_DEV_DIEPDMA5_DIEPDMA5 */
82848 };
82849 
82850 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA5. */
82851 typedef volatile struct ALT_USB_DEV_DIEPDMA5_s ALT_USB_DEV_DIEPDMA5_t;
82852 #endif /* __ASSEMBLY__ */
82853 
82854 /* The reset value of the ALT_USB_DEV_DIEPDMA5 register. */
82855 #define ALT_USB_DEV_DIEPDMA5_RESET 0x00000000
82856 /* The byte offset of the ALT_USB_DEV_DIEPDMA5 register from the beginning of the component. */
82857 #define ALT_USB_DEV_DIEPDMA5_OFST 0x1b4
82858 /* The address of the ALT_USB_DEV_DIEPDMA5 register. */
82859 #define ALT_USB_DEV_DIEPDMA5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA5_OFST))
82860 
82861 /*
82862  * Register : dtxfsts5
82863  *
82864  * Device IN Endpoint Transmit FIFO Status Register 5
82865  *
82866  * Register Layout
82867  *
82868  * Bits | Access | Reset | Description
82869  * :--------|:-------|:-------|:-------------------------------------
82870  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL
82871  * [31:16] | ??? | 0x0 | *UNDEFINED*
82872  *
82873  */
82874 /*
82875  * Field : ineptxfspcavail
82876  *
82877  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
82878  *
82879  * Indicates the amount of free space available in the Endpoint
82880  *
82881  * TxFIFO.
82882  *
82883  * Values are in terms of 32-bit words.
82884  *
82885  * 16'h0: Endpoint TxFIFO is full
82886  *
82887  * 16'h1: 1 word available
82888  *
82889  * 16'h2: 2 words available
82890  *
82891  * 16'hn: n words available (where 0 n 32,768)
82892  *
82893  * 16'h8000: 32,768 words available
82894  *
82895  * Others: Reserved
82896  *
82897  * Field Access Macros:
82898  *
82899  */
82900 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */
82901 #define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_LSB 0
82902 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */
82903 #define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_MSB 15
82904 /* The width in bits of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */
82905 #define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_WIDTH 16
82906 /* The mask used to set the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field value. */
82907 #define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
82908 /* The mask used to clear the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field value. */
82909 #define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
82910 /* The reset value of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */
82911 #define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_RESET 0x2000
82912 /* Extracts the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL field value from a register. */
82913 #define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
82914 /* Produces a ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field value suitable for setting the register. */
82915 #define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
82916 
82917 #ifndef __ASSEMBLY__
82918 /*
82919  * WARNING: The C register and register group struct declarations are provided for
82920  * convenience and illustrative purposes. They should, however, be used with
82921  * caution as the C language standard provides no guarantees about the alignment or
82922  * atomicity of device memory accesses. The recommended practice for writing
82923  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
82924  * alt_write_word() functions.
82925  *
82926  * The struct declaration for register ALT_USB_DEV_DTXFSTS5.
82927  */
82928 struct ALT_USB_DEV_DTXFSTS5_s
82929 {
82930  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL */
82931  uint32_t : 16; /* *UNDEFINED* */
82932 };
82933 
82934 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS5. */
82935 typedef volatile struct ALT_USB_DEV_DTXFSTS5_s ALT_USB_DEV_DTXFSTS5_t;
82936 #endif /* __ASSEMBLY__ */
82937 
82938 /* The reset value of the ALT_USB_DEV_DTXFSTS5 register. */
82939 #define ALT_USB_DEV_DTXFSTS5_RESET 0x00002000
82940 /* The byte offset of the ALT_USB_DEV_DTXFSTS5 register from the beginning of the component. */
82941 #define ALT_USB_DEV_DTXFSTS5_OFST 0x1b8
82942 /* The address of the ALT_USB_DEV_DTXFSTS5 register. */
82943 #define ALT_USB_DEV_DTXFSTS5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS5_OFST))
82944 
82945 /*
82946  * Register : diepdmab5
82947  *
82948  * Device IN Endpoint 5 Buffer Address Register
82949  *
82950  * Register Layout
82951  *
82952  * Bits | Access | Reset | Description
82953  * :-------|:-------|:--------|:--------------------------------
82954  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5
82955  *
82956  */
82957 /*
82958  * Field : diepdmab5
82959  *
82960  * Holds the current buffer address.This register is updated as and when the data
82961  *
82962  * transfer for the corresponding end point is in progress.
82963  *
82964  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
82965  * is
82966  *
82967  * reserved.
82968  *
82969  * Field Access Macros:
82970  *
82971  */
82972 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field. */
82973 #define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_LSB 0
82974 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field. */
82975 #define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_MSB 31
82976 /* The width in bits of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field. */
82977 #define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_WIDTH 32
82978 /* The mask used to set the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field value. */
82979 #define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_SET_MSK 0xffffffff
82980 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field value. */
82981 #define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_CLR_MSK 0x00000000
82982 /* The reset value of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field is UNKNOWN. */
82983 #define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_RESET 0x0
82984 /* Extracts the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 field value from a register. */
82985 #define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_GET(value) (((value) & 0xffffffff) >> 0)
82986 /* Produces a ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field value suitable for setting the register. */
82987 #define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_SET(value) (((value) << 0) & 0xffffffff)
82988 
82989 #ifndef __ASSEMBLY__
82990 /*
82991  * WARNING: The C register and register group struct declarations are provided for
82992  * convenience and illustrative purposes. They should, however, be used with
82993  * caution as the C language standard provides no guarantees about the alignment or
82994  * atomicity of device memory accesses. The recommended practice for writing
82995  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
82996  * alt_write_word() functions.
82997  *
82998  * The struct declaration for register ALT_USB_DEV_DIEPDMAB5.
82999  */
83000 struct ALT_USB_DEV_DIEPDMAB5_s
83001 {
83002  const uint32_t diepdmab5 : 32; /* ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 */
83003 };
83004 
83005 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB5. */
83006 typedef volatile struct ALT_USB_DEV_DIEPDMAB5_s ALT_USB_DEV_DIEPDMAB5_t;
83007 #endif /* __ASSEMBLY__ */
83008 
83009 /* The reset value of the ALT_USB_DEV_DIEPDMAB5 register. */
83010 #define ALT_USB_DEV_DIEPDMAB5_RESET 0x00000000
83011 /* The byte offset of the ALT_USB_DEV_DIEPDMAB5 register from the beginning of the component. */
83012 #define ALT_USB_DEV_DIEPDMAB5_OFST 0x1bc
83013 /* The address of the ALT_USB_DEV_DIEPDMAB5 register. */
83014 #define ALT_USB_DEV_DIEPDMAB5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB5_OFST))
83015 
83016 /*
83017  * Register : diepctl6
83018  *
83019  * Device Control IN Endpoint 6 Control Register
83020  *
83021  * Register Layout
83022  *
83023  * Bits | Access | Reset | Description
83024  * :--------|:---------|:------|:------------------------------
83025  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL6_MPS
83026  * [14:11] | ??? | 0x0 | *UNDEFINED*
83027  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL6_USBACTEP
83028  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL6_DPID
83029  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL6_NAKSTS
83030  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL6_EPTYPE
83031  * [20] | ??? | 0x0 | *UNDEFINED*
83032  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL6_STALL
83033  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL6_TXFNUM
83034  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL6_CNAK
83035  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL6_SNAK
83036  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL6_SETD0PID
83037  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL6_SETD1PID
83038  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL6_EPDIS
83039  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL6_EPENA
83040  *
83041  */
83042 /*
83043  * Field : mps
83044  *
83045  * Maximum Packet Size (MPS)
83046  *
83047  * The application must program this field with the maximum packet size for the
83048  * current
83049  *
83050  * logical endpoint. This value is in bytes.
83051  *
83052  * Field Access Macros:
83053  *
83054  */
83055 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_MPS register field. */
83056 #define ALT_USB_DEV_DIEPCTL6_MPS_LSB 0
83057 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_MPS register field. */
83058 #define ALT_USB_DEV_DIEPCTL6_MPS_MSB 10
83059 /* The width in bits of the ALT_USB_DEV_DIEPCTL6_MPS register field. */
83060 #define ALT_USB_DEV_DIEPCTL6_MPS_WIDTH 11
83061 /* The mask used to set the ALT_USB_DEV_DIEPCTL6_MPS register field value. */
83062 #define ALT_USB_DEV_DIEPCTL6_MPS_SET_MSK 0x000007ff
83063 /* The mask used to clear the ALT_USB_DEV_DIEPCTL6_MPS register field value. */
83064 #define ALT_USB_DEV_DIEPCTL6_MPS_CLR_MSK 0xfffff800
83065 /* The reset value of the ALT_USB_DEV_DIEPCTL6_MPS register field. */
83066 #define ALT_USB_DEV_DIEPCTL6_MPS_RESET 0x0
83067 /* Extracts the ALT_USB_DEV_DIEPCTL6_MPS field value from a register. */
83068 #define ALT_USB_DEV_DIEPCTL6_MPS_GET(value) (((value) & 0x000007ff) >> 0)
83069 /* Produces a ALT_USB_DEV_DIEPCTL6_MPS register field value suitable for setting the register. */
83070 #define ALT_USB_DEV_DIEPCTL6_MPS_SET(value) (((value) << 0) & 0x000007ff)
83071 
83072 /*
83073  * Field : usbactep
83074  *
83075  * USB Active Endpoint (USBActEP)
83076  *
83077  * Indicates whether this endpoint is active in the current configuration and
83078  * interface. The
83079  *
83080  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
83081  * reset. After
83082  *
83083  * receiving the SetConfiguration and SetInterface commands, the application must
83084  *
83085  * program endpoint registers accordingly and set this bit.
83086  *
83087  * Field Enumeration Values:
83088  *
83089  * Enum | Value | Description
83090  * :-------------------------------------|:------|:--------------------
83091  * ALT_USB_DEV_DIEPCTL6_USBACTEP_E_DISD | 0x0 | Not Active
83092  * ALT_USB_DEV_DIEPCTL6_USBACTEP_E_END | 0x1 | USB Active Endpoint
83093  *
83094  * Field Access Macros:
83095  *
83096  */
83097 /*
83098  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_USBACTEP
83099  *
83100  * Not Active
83101  */
83102 #define ALT_USB_DEV_DIEPCTL6_USBACTEP_E_DISD 0x0
83103 /*
83104  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_USBACTEP
83105  *
83106  * USB Active Endpoint
83107  */
83108 #define ALT_USB_DEV_DIEPCTL6_USBACTEP_E_END 0x1
83109 
83110 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */
83111 #define ALT_USB_DEV_DIEPCTL6_USBACTEP_LSB 15
83112 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */
83113 #define ALT_USB_DEV_DIEPCTL6_USBACTEP_MSB 15
83114 /* The width in bits of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */
83115 #define ALT_USB_DEV_DIEPCTL6_USBACTEP_WIDTH 1
83116 /* The mask used to set the ALT_USB_DEV_DIEPCTL6_USBACTEP register field value. */
83117 #define ALT_USB_DEV_DIEPCTL6_USBACTEP_SET_MSK 0x00008000
83118 /* The mask used to clear the ALT_USB_DEV_DIEPCTL6_USBACTEP register field value. */
83119 #define ALT_USB_DEV_DIEPCTL6_USBACTEP_CLR_MSK 0xffff7fff
83120 /* The reset value of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */
83121 #define ALT_USB_DEV_DIEPCTL6_USBACTEP_RESET 0x0
83122 /* Extracts the ALT_USB_DEV_DIEPCTL6_USBACTEP field value from a register. */
83123 #define ALT_USB_DEV_DIEPCTL6_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
83124 /* Produces a ALT_USB_DEV_DIEPCTL6_USBACTEP register field value suitable for setting the register. */
83125 #define ALT_USB_DEV_DIEPCTL6_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
83126 
83127 /*
83128  * Field : dpid
83129  *
83130  * Endpoint Data PID (DPID)
83131  *
83132  * Applies to interrupt/bulk IN and OUT endpoints only.
83133  *
83134  * Contains the PID of the packet to be received or transmitted on this endpoint.
83135  * The
83136  *
83137  * application must program the PID of the first packet to be received or
83138  * transmitted on
83139  *
83140  * this endpoint, after the endpoint is activated. The applications use the
83141  * SetD1PID and
83142  *
83143  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
83144  *
83145  * 1'b0: DATA0
83146  *
83147  * 1'b1: DATA1
83148  *
83149  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
83150  *
83151  * DMA mode.
83152  *
83153  * 1'b0 RO
83154  *
83155  * Even/Odd (Micro)Frame (EO_FrNum)
83156  *
83157  * In non-Scatter/Gather DMA mode:
83158  *
83159  * Applies to isochronous IN and OUT endpoints only.
83160  *
83161  * Indicates the (micro)frame number in which the core transmits/receives
83162  * isochronous
83163  *
83164  * data for this endpoint. The application must program the even/odd (micro) frame
83165  *
83166  * number in which it intends to transmit/receive isochronous data for this
83167  * endpoint using
83168  *
83169  * the SetEvnFr and SetOddFr fields in this register.
83170  *
83171  * 1'b0: Even (micro)frame
83172  *
83173  * 1'b1: Odd (micro)frame
83174  *
83175  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
83176  * number
83177  *
83178  * in which to send data is provided in the transmit descriptor structure. The
83179  * frame in
83180  *
83181  * which data is received is updated in receive descriptor structure.
83182  *
83183  * Field Enumeration Values:
83184  *
83185  * Enum | Value | Description
83186  * :----------------------------------|:------|:-----------------------------
83187  * ALT_USB_DEV_DIEPCTL6_DPID_E_INACT | 0x0 | Endpoint Data PID not active
83188  * ALT_USB_DEV_DIEPCTL6_DPID_E_ACT | 0x1 | Endpoint Data PID active
83189  *
83190  * Field Access Macros:
83191  *
83192  */
83193 /*
83194  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_DPID
83195  *
83196  * Endpoint Data PID not active
83197  */
83198 #define ALT_USB_DEV_DIEPCTL6_DPID_E_INACT 0x0
83199 /*
83200  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_DPID
83201  *
83202  * Endpoint Data PID active
83203  */
83204 #define ALT_USB_DEV_DIEPCTL6_DPID_E_ACT 0x1
83205 
83206 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_DPID register field. */
83207 #define ALT_USB_DEV_DIEPCTL6_DPID_LSB 16
83208 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_DPID register field. */
83209 #define ALT_USB_DEV_DIEPCTL6_DPID_MSB 16
83210 /* The width in bits of the ALT_USB_DEV_DIEPCTL6_DPID register field. */
83211 #define ALT_USB_DEV_DIEPCTL6_DPID_WIDTH 1
83212 /* The mask used to set the ALT_USB_DEV_DIEPCTL6_DPID register field value. */
83213 #define ALT_USB_DEV_DIEPCTL6_DPID_SET_MSK 0x00010000
83214 /* The mask used to clear the ALT_USB_DEV_DIEPCTL6_DPID register field value. */
83215 #define ALT_USB_DEV_DIEPCTL6_DPID_CLR_MSK 0xfffeffff
83216 /* The reset value of the ALT_USB_DEV_DIEPCTL6_DPID register field. */
83217 #define ALT_USB_DEV_DIEPCTL6_DPID_RESET 0x0
83218 /* Extracts the ALT_USB_DEV_DIEPCTL6_DPID field value from a register. */
83219 #define ALT_USB_DEV_DIEPCTL6_DPID_GET(value) (((value) & 0x00010000) >> 16)
83220 /* Produces a ALT_USB_DEV_DIEPCTL6_DPID register field value suitable for setting the register. */
83221 #define ALT_USB_DEV_DIEPCTL6_DPID_SET(value) (((value) << 16) & 0x00010000)
83222 
83223 /*
83224  * Field : naksts
83225  *
83226  * NAK Status (NAKSts)
83227  *
83228  * Indicates the following:
83229  *
83230  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
83231  *
83232  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
83233  *
83234  * When either the application or the core sets this bit:
83235  *
83236  * The core stops receiving any data on an OUT endpoint, even if there is space in
83237  *
83238  * the RxFIFO to accommodate the incoming packet.
83239  *
83240  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
83241  *
83242  * endpoint, even if there data is available in the TxFIFO.
83243  *
83244  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
83245  *
83246  * if there data is available in the TxFIFO.
83247  *
83248  * Irrespective of this bit's setting, the core always responds to SETUP data
83249  * packets with
83250  *
83251  * an ACK handshake.
83252  *
83253  * Field Enumeration Values:
83254  *
83255  * Enum | Value | Description
83256  * :-------------------------------------|:------|:------------------------------------------------
83257  * ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
83258  * : | | based on the FIFO status
83259  * ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
83260  * : | | endpoint
83261  *
83262  * Field Access Macros:
83263  *
83264  */
83265 /*
83266  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_NAKSTS
83267  *
83268  * The core is transmitting non-NAK handshakes based on the FIFO status
83269  */
83270 #define ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NONNAK 0x0
83271 /*
83272  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_NAKSTS
83273  *
83274  * The core is transmitting NAK handshakes on this endpoint
83275  */
83276 #define ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NAK 0x1
83277 
83278 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */
83279 #define ALT_USB_DEV_DIEPCTL6_NAKSTS_LSB 17
83280 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */
83281 #define ALT_USB_DEV_DIEPCTL6_NAKSTS_MSB 17
83282 /* The width in bits of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */
83283 #define ALT_USB_DEV_DIEPCTL6_NAKSTS_WIDTH 1
83284 /* The mask used to set the ALT_USB_DEV_DIEPCTL6_NAKSTS register field value. */
83285 #define ALT_USB_DEV_DIEPCTL6_NAKSTS_SET_MSK 0x00020000
83286 /* The mask used to clear the ALT_USB_DEV_DIEPCTL6_NAKSTS register field value. */
83287 #define ALT_USB_DEV_DIEPCTL6_NAKSTS_CLR_MSK 0xfffdffff
83288 /* The reset value of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */
83289 #define ALT_USB_DEV_DIEPCTL6_NAKSTS_RESET 0x0
83290 /* Extracts the ALT_USB_DEV_DIEPCTL6_NAKSTS field value from a register. */
83291 #define ALT_USB_DEV_DIEPCTL6_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
83292 /* Produces a ALT_USB_DEV_DIEPCTL6_NAKSTS register field value suitable for setting the register. */
83293 #define ALT_USB_DEV_DIEPCTL6_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
83294 
83295 /*
83296  * Field : eptype
83297  *
83298  * Endpoint Type (EPType)
83299  *
83300  * This is the transfer type supported by this logical endpoint.
83301  *
83302  * 2'b00: Control
83303  *
83304  * 2'b01: Isochronous
83305  *
83306  * 2'b10: Bulk
83307  *
83308  * 2'b11: Interrupt
83309  *
83310  * Field Enumeration Values:
83311  *
83312  * Enum | Value | Description
83313  * :------------------------------------------|:------|:------------
83314  * ALT_USB_DEV_DIEPCTL6_EPTYPE_E_CTL | 0x0 | Control
83315  * ALT_USB_DEV_DIEPCTL6_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
83316  * ALT_USB_DEV_DIEPCTL6_EPTYPE_E_BULK | 0x2 | Bulk
83317  * ALT_USB_DEV_DIEPCTL6_EPTYPE_E_INTERRUP | 0x3 | Interrupt
83318  *
83319  * Field Access Macros:
83320  *
83321  */
83322 /*
83323  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE
83324  *
83325  * Control
83326  */
83327 #define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_CTL 0x0
83328 /*
83329  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE
83330  *
83331  * Isochronous
83332  */
83333 #define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_ISOCHRONOUS 0x1
83334 /*
83335  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE
83336  *
83337  * Bulk
83338  */
83339 #define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_BULK 0x2
83340 /*
83341  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE
83342  *
83343  * Interrupt
83344  */
83345 #define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_INTERRUP 0x3
83346 
83347 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */
83348 #define ALT_USB_DEV_DIEPCTL6_EPTYPE_LSB 18
83349 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */
83350 #define ALT_USB_DEV_DIEPCTL6_EPTYPE_MSB 19
83351 /* The width in bits of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */
83352 #define ALT_USB_DEV_DIEPCTL6_EPTYPE_WIDTH 2
83353 /* The mask used to set the ALT_USB_DEV_DIEPCTL6_EPTYPE register field value. */
83354 #define ALT_USB_DEV_DIEPCTL6_EPTYPE_SET_MSK 0x000c0000
83355 /* The mask used to clear the ALT_USB_DEV_DIEPCTL6_EPTYPE register field value. */
83356 #define ALT_USB_DEV_DIEPCTL6_EPTYPE_CLR_MSK 0xfff3ffff
83357 /* The reset value of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */
83358 #define ALT_USB_DEV_DIEPCTL6_EPTYPE_RESET 0x0
83359 /* Extracts the ALT_USB_DEV_DIEPCTL6_EPTYPE field value from a register. */
83360 #define ALT_USB_DEV_DIEPCTL6_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
83361 /* Produces a ALT_USB_DEV_DIEPCTL6_EPTYPE register field value suitable for setting the register. */
83362 #define ALT_USB_DEV_DIEPCTL6_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
83363 
83364 /*
83365  * Field : stall
83366  *
83367  * STALL Handshake (Stall)
83368  *
83369  * Applies to non-control, non-isochronous IN and OUT endpoints only.
83370  *
83371  * The application sets this bit to stall all tokens from the USB host to this
83372  * endpoint. If a
83373  *
83374  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
83375  * bit, the
83376  *
83377  * STALL bit takes priority. Only the application can clear this bit, never the
83378  * core.
83379  *
83380  * 1'b0 R_W
83381  *
83382  * Applies to control endpoints only.
83383  *
83384  * The application can only set this bit, and the core clears it, when a SETUP
83385  * token is
83386  *
83387  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
83388  * OUT
83389  *
83390  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
83391  * this bit's
83392  *
83393  * setting, the core always responds to SETUP data packets with an ACK handshake.
83394  *
83395  * Field Enumeration Values:
83396  *
83397  * Enum | Value | Description
83398  * :-----------------------------------|:------|:----------------------------
83399  * ALT_USB_DEV_DIEPCTL6_STALL_E_INACT | 0x0 | STALL All Tokens not active
83400  * ALT_USB_DEV_DIEPCTL6_STALL_E_ACT | 0x1 | STALL All Tokens active
83401  *
83402  * Field Access Macros:
83403  *
83404  */
83405 /*
83406  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_STALL
83407  *
83408  * STALL All Tokens not active
83409  */
83410 #define ALT_USB_DEV_DIEPCTL6_STALL_E_INACT 0x0
83411 /*
83412  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_STALL
83413  *
83414  * STALL All Tokens active
83415  */
83416 #define ALT_USB_DEV_DIEPCTL6_STALL_E_ACT 0x1
83417 
83418 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_STALL register field. */
83419 #define ALT_USB_DEV_DIEPCTL6_STALL_LSB 21
83420 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_STALL register field. */
83421 #define ALT_USB_DEV_DIEPCTL6_STALL_MSB 21
83422 /* The width in bits of the ALT_USB_DEV_DIEPCTL6_STALL register field. */
83423 #define ALT_USB_DEV_DIEPCTL6_STALL_WIDTH 1
83424 /* The mask used to set the ALT_USB_DEV_DIEPCTL6_STALL register field value. */
83425 #define ALT_USB_DEV_DIEPCTL6_STALL_SET_MSK 0x00200000
83426 /* The mask used to clear the ALT_USB_DEV_DIEPCTL6_STALL register field value. */
83427 #define ALT_USB_DEV_DIEPCTL6_STALL_CLR_MSK 0xffdfffff
83428 /* The reset value of the ALT_USB_DEV_DIEPCTL6_STALL register field. */
83429 #define ALT_USB_DEV_DIEPCTL6_STALL_RESET 0x0
83430 /* Extracts the ALT_USB_DEV_DIEPCTL6_STALL field value from a register. */
83431 #define ALT_USB_DEV_DIEPCTL6_STALL_GET(value) (((value) & 0x00200000) >> 21)
83432 /* Produces a ALT_USB_DEV_DIEPCTL6_STALL register field value suitable for setting the register. */
83433 #define ALT_USB_DEV_DIEPCTL6_STALL_SET(value) (((value) << 21) & 0x00200000)
83434 
83435 /*
83436  * Field : txfnum
83437  *
83438  * TxFIFO Number (TxFNum)
83439  *
83440  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
83441  *
83442  * endpoints must map this to the corresponding Periodic TxFIFO number.
83443  *
83444  * 4'h0: Non-Periodic TxFIFO
83445  *
83446  * Others: Specified Periodic TxFIFO.number
83447  *
83448  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
83449  *
83450  * applications such as mass storage. The core treats an IN endpoint as a non-
83451  * periodic
83452  *
83453  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
83454  * must be
83455  *
83456  * allocated for an interrupt IN endpoint, and the number of this
83457  *
83458  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
83459  *
83460  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
83461  *
83462  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
83463  *
83464  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
83465  *
83466  * This field is valid only for IN endpoints.
83467  *
83468  * Field Access Macros:
83469  *
83470  */
83471 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */
83472 #define ALT_USB_DEV_DIEPCTL6_TXFNUM_LSB 22
83473 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */
83474 #define ALT_USB_DEV_DIEPCTL6_TXFNUM_MSB 25
83475 /* The width in bits of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */
83476 #define ALT_USB_DEV_DIEPCTL6_TXFNUM_WIDTH 4
83477 /* The mask used to set the ALT_USB_DEV_DIEPCTL6_TXFNUM register field value. */
83478 #define ALT_USB_DEV_DIEPCTL6_TXFNUM_SET_MSK 0x03c00000
83479 /* The mask used to clear the ALT_USB_DEV_DIEPCTL6_TXFNUM register field value. */
83480 #define ALT_USB_DEV_DIEPCTL6_TXFNUM_CLR_MSK 0xfc3fffff
83481 /* The reset value of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */
83482 #define ALT_USB_DEV_DIEPCTL6_TXFNUM_RESET 0x0
83483 /* Extracts the ALT_USB_DEV_DIEPCTL6_TXFNUM field value from a register. */
83484 #define ALT_USB_DEV_DIEPCTL6_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
83485 /* Produces a ALT_USB_DEV_DIEPCTL6_TXFNUM register field value suitable for setting the register. */
83486 #define ALT_USB_DEV_DIEPCTL6_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
83487 
83488 /*
83489  * Field : cnak
83490  *
83491  * Clear NAK (CNAK)
83492  *
83493  * A write to this bit clears the NAK bit For the endpoint.
83494  *
83495  * Field Enumeration Values:
83496  *
83497  * Enum | Value | Description
83498  * :----------------------------------|:------|:-------------
83499  * ALT_USB_DEV_DIEPCTL6_CNAK_E_INACT | 0x0 | No Clear NAK
83500  * ALT_USB_DEV_DIEPCTL6_CNAK_E_ACT | 0x1 | Clear NAK
83501  *
83502  * Field Access Macros:
83503  *
83504  */
83505 /*
83506  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_CNAK
83507  *
83508  * No Clear NAK
83509  */
83510 #define ALT_USB_DEV_DIEPCTL6_CNAK_E_INACT 0x0
83511 /*
83512  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_CNAK
83513  *
83514  * Clear NAK
83515  */
83516 #define ALT_USB_DEV_DIEPCTL6_CNAK_E_ACT 0x1
83517 
83518 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */
83519 #define ALT_USB_DEV_DIEPCTL6_CNAK_LSB 26
83520 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */
83521 #define ALT_USB_DEV_DIEPCTL6_CNAK_MSB 26
83522 /* The width in bits of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */
83523 #define ALT_USB_DEV_DIEPCTL6_CNAK_WIDTH 1
83524 /* The mask used to set the ALT_USB_DEV_DIEPCTL6_CNAK register field value. */
83525 #define ALT_USB_DEV_DIEPCTL6_CNAK_SET_MSK 0x04000000
83526 /* The mask used to clear the ALT_USB_DEV_DIEPCTL6_CNAK register field value. */
83527 #define ALT_USB_DEV_DIEPCTL6_CNAK_CLR_MSK 0xfbffffff
83528 /* The reset value of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */
83529 #define ALT_USB_DEV_DIEPCTL6_CNAK_RESET 0x0
83530 /* Extracts the ALT_USB_DEV_DIEPCTL6_CNAK field value from a register. */
83531 #define ALT_USB_DEV_DIEPCTL6_CNAK_GET(value) (((value) & 0x04000000) >> 26)
83532 /* Produces a ALT_USB_DEV_DIEPCTL6_CNAK register field value suitable for setting the register. */
83533 #define ALT_USB_DEV_DIEPCTL6_CNAK_SET(value) (((value) << 26) & 0x04000000)
83534 
83535 /*
83536  * Field : snak
83537  *
83538  * Set NAK (SNAK)
83539  *
83540  * A write to this bit sets the NAK bit For the endpoint.
83541  *
83542  * Using this bit, the application can control the transmission of NAK
83543  *
83544  * handshakes on an endpoint. The core can also Set this bit For an
83545  *
83546  * endpoint after a SETUP packet is received on that endpoint.
83547  *
83548  * Field Enumeration Values:
83549  *
83550  * Enum | Value | Description
83551  * :----------------------------------|:------|:------------
83552  * ALT_USB_DEV_DIEPCTL6_SNAK_E_INACT | 0x0 | No Set NAK
83553  * ALT_USB_DEV_DIEPCTL6_SNAK_E_ACT | 0x1 | Set NAK
83554  *
83555  * Field Access Macros:
83556  *
83557  */
83558 /*
83559  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SNAK
83560  *
83561  * No Set NAK
83562  */
83563 #define ALT_USB_DEV_DIEPCTL6_SNAK_E_INACT 0x0
83564 /*
83565  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SNAK
83566  *
83567  * Set NAK
83568  */
83569 #define ALT_USB_DEV_DIEPCTL6_SNAK_E_ACT 0x1
83570 
83571 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */
83572 #define ALT_USB_DEV_DIEPCTL6_SNAK_LSB 27
83573 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */
83574 #define ALT_USB_DEV_DIEPCTL6_SNAK_MSB 27
83575 /* The width in bits of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */
83576 #define ALT_USB_DEV_DIEPCTL6_SNAK_WIDTH 1
83577 /* The mask used to set the ALT_USB_DEV_DIEPCTL6_SNAK register field value. */
83578 #define ALT_USB_DEV_DIEPCTL6_SNAK_SET_MSK 0x08000000
83579 /* The mask used to clear the ALT_USB_DEV_DIEPCTL6_SNAK register field value. */
83580 #define ALT_USB_DEV_DIEPCTL6_SNAK_CLR_MSK 0xf7ffffff
83581 /* The reset value of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */
83582 #define ALT_USB_DEV_DIEPCTL6_SNAK_RESET 0x0
83583 /* Extracts the ALT_USB_DEV_DIEPCTL6_SNAK field value from a register. */
83584 #define ALT_USB_DEV_DIEPCTL6_SNAK_GET(value) (((value) & 0x08000000) >> 27)
83585 /* Produces a ALT_USB_DEV_DIEPCTL6_SNAK register field value suitable for setting the register. */
83586 #define ALT_USB_DEV_DIEPCTL6_SNAK_SET(value) (((value) << 27) & 0x08000000)
83587 
83588 /*
83589  * Field : setd0pid
83590  *
83591  * Set DATA0 PID (SetD0PID)
83592  *
83593  * Applies to interrupt/bulk IN and OUT endpoints only.
83594  *
83595  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
83596  * to DATA0.
83597  *
83598  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
83599  *
83600  * DMA mode.
83601  *
83602  * 1'b0 WO
83603  *
83604  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
83605  *
83606  * Applies to isochronous IN and OUT endpoints only.
83607  *
83608  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
83609  * (micro)
83610  *
83611  * frame.
83612  *
83613  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
83614  * number
83615  *
83616  * in which to send data is in the transmit descriptor structure. The frame in
83617  * which to
83618  *
83619  * receive data is updated in receive descriptor structure.
83620  *
83621  * Field Enumeration Values:
83622  *
83623  * Enum | Value | Description
83624  * :-------------------------------------|:------|:----------------------------
83625  * ALT_USB_DEV_DIEPCTL6_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
83626  * ALT_USB_DEV_DIEPCTL6_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
83627  *
83628  * Field Access Macros:
83629  *
83630  */
83631 /*
83632  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD0PID
83633  *
83634  * Disables Set DATA0 PID
83635  */
83636 #define ALT_USB_DEV_DIEPCTL6_SETD0PID_E_DISD 0x0
83637 /*
83638  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD0PID
83639  *
83640  * Endpoint Data PID to DATA0)
83641  */
83642 #define ALT_USB_DEV_DIEPCTL6_SETD0PID_E_END 0x1
83643 
83644 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */
83645 #define ALT_USB_DEV_DIEPCTL6_SETD0PID_LSB 28
83646 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */
83647 #define ALT_USB_DEV_DIEPCTL6_SETD0PID_MSB 28
83648 /* The width in bits of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */
83649 #define ALT_USB_DEV_DIEPCTL6_SETD0PID_WIDTH 1
83650 /* The mask used to set the ALT_USB_DEV_DIEPCTL6_SETD0PID register field value. */
83651 #define ALT_USB_DEV_DIEPCTL6_SETD0PID_SET_MSK 0x10000000
83652 /* The mask used to clear the ALT_USB_DEV_DIEPCTL6_SETD0PID register field value. */
83653 #define ALT_USB_DEV_DIEPCTL6_SETD0PID_CLR_MSK 0xefffffff
83654 /* The reset value of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */
83655 #define ALT_USB_DEV_DIEPCTL6_SETD0PID_RESET 0x0
83656 /* Extracts the ALT_USB_DEV_DIEPCTL6_SETD0PID field value from a register. */
83657 #define ALT_USB_DEV_DIEPCTL6_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
83658 /* Produces a ALT_USB_DEV_DIEPCTL6_SETD0PID register field value suitable for setting the register. */
83659 #define ALT_USB_DEV_DIEPCTL6_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
83660 
83661 /*
83662  * Field : setd1pid
83663  *
83664  * Set DATA1 PID (SetD1PID)
83665  *
83666  * Applies to interrupt/bulk IN and OUT endpoints only.
83667  *
83668  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
83669  * to DATA1.
83670  *
83671  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
83672  *
83673  * DMA mode.
83674  *
83675  * Set Odd (micro)frame (SetOddFr)
83676  *
83677  * Applies to isochronous IN and OUT endpoints only.
83678  *
83679  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
83680  *
83681  * (micro)frame.
83682  *
83683  * This field is not applicable for Scatter/Gather DMA mode.
83684  *
83685  * Field Enumeration Values:
83686  *
83687  * Enum | Value | Description
83688  * :-------------------------------------|:------|:-----------------------
83689  * ALT_USB_DEV_DIEPCTL6_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
83690  * ALT_USB_DEV_DIEPCTL6_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
83691  *
83692  * Field Access Macros:
83693  *
83694  */
83695 /*
83696  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD1PID
83697  *
83698  * Disables Set DATA1 PID
83699  */
83700 #define ALT_USB_DEV_DIEPCTL6_SETD1PID_E_DISD 0x0
83701 /*
83702  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD1PID
83703  *
83704  * Enables Set DATA1 PID
83705  */
83706 #define ALT_USB_DEV_DIEPCTL6_SETD1PID_E_END 0x1
83707 
83708 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */
83709 #define ALT_USB_DEV_DIEPCTL6_SETD1PID_LSB 29
83710 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */
83711 #define ALT_USB_DEV_DIEPCTL6_SETD1PID_MSB 29
83712 /* The width in bits of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */
83713 #define ALT_USB_DEV_DIEPCTL6_SETD1PID_WIDTH 1
83714 /* The mask used to set the ALT_USB_DEV_DIEPCTL6_SETD1PID register field value. */
83715 #define ALT_USB_DEV_DIEPCTL6_SETD1PID_SET_MSK 0x20000000
83716 /* The mask used to clear the ALT_USB_DEV_DIEPCTL6_SETD1PID register field value. */
83717 #define ALT_USB_DEV_DIEPCTL6_SETD1PID_CLR_MSK 0xdfffffff
83718 /* The reset value of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */
83719 #define ALT_USB_DEV_DIEPCTL6_SETD1PID_RESET 0x0
83720 /* Extracts the ALT_USB_DEV_DIEPCTL6_SETD1PID field value from a register. */
83721 #define ALT_USB_DEV_DIEPCTL6_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
83722 /* Produces a ALT_USB_DEV_DIEPCTL6_SETD1PID register field value suitable for setting the register. */
83723 #define ALT_USB_DEV_DIEPCTL6_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
83724 
83725 /*
83726  * Field : epdis
83727  *
83728  * Endpoint Disable (EPDis)
83729  *
83730  * Applies to IN and OUT endpoints.
83731  *
83732  * The application sets this bit to stop transmitting/receiving data on an
83733  * endpoint, even
83734  *
83735  * before the transfer for that endpoint is complete. The application must wait for
83736  * the
83737  *
83738  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
83739  * clears
83740  *
83741  * this bit before setting the Endpoint Disabled interrupt. The application must
83742  * set this bit
83743  *
83744  * only if Endpoint Enable is already set for this endpoint.
83745  *
83746  * Field Enumeration Values:
83747  *
83748  * Enum | Value | Description
83749  * :-----------------------------------|:------|:--------------------
83750  * ALT_USB_DEV_DIEPCTL6_EPDIS_E_INACT | 0x0 | No Endpoint Disable
83751  * ALT_USB_DEV_DIEPCTL6_EPDIS_E_ACT | 0x1 | Endpoint Disable
83752  *
83753  * Field Access Macros:
83754  *
83755  */
83756 /*
83757  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPDIS
83758  *
83759  * No Endpoint Disable
83760  */
83761 #define ALT_USB_DEV_DIEPCTL6_EPDIS_E_INACT 0x0
83762 /*
83763  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPDIS
83764  *
83765  * Endpoint Disable
83766  */
83767 #define ALT_USB_DEV_DIEPCTL6_EPDIS_E_ACT 0x1
83768 
83769 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */
83770 #define ALT_USB_DEV_DIEPCTL6_EPDIS_LSB 30
83771 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */
83772 #define ALT_USB_DEV_DIEPCTL6_EPDIS_MSB 30
83773 /* The width in bits of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */
83774 #define ALT_USB_DEV_DIEPCTL6_EPDIS_WIDTH 1
83775 /* The mask used to set the ALT_USB_DEV_DIEPCTL6_EPDIS register field value. */
83776 #define ALT_USB_DEV_DIEPCTL6_EPDIS_SET_MSK 0x40000000
83777 /* The mask used to clear the ALT_USB_DEV_DIEPCTL6_EPDIS register field value. */
83778 #define ALT_USB_DEV_DIEPCTL6_EPDIS_CLR_MSK 0xbfffffff
83779 /* The reset value of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */
83780 #define ALT_USB_DEV_DIEPCTL6_EPDIS_RESET 0x0
83781 /* Extracts the ALT_USB_DEV_DIEPCTL6_EPDIS field value from a register. */
83782 #define ALT_USB_DEV_DIEPCTL6_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
83783 /* Produces a ALT_USB_DEV_DIEPCTL6_EPDIS register field value suitable for setting the register. */
83784 #define ALT_USB_DEV_DIEPCTL6_EPDIS_SET(value) (((value) << 30) & 0x40000000)
83785 
83786 /*
83787  * Field : epena
83788  *
83789  * Endpoint Enable (EPEna)
83790  *
83791  * Applies to IN and OUT endpoints.
83792  *
83793  * When Scatter/Gather DMA mode is enabled,
83794  *
83795  * For IN endpoints this bit indicates that the descriptor structure and data
83796  * buffer with
83797  *
83798  * data ready to transmit is setup.
83799  *
83800  * For OUT endpoint it indicates that the descriptor structure and data buffer to
83801  *
83802  * receive data is setup.
83803  *
83804  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
83805  *
83806  * DMA mode:
83807  *
83808  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
83809  * the
83810  *
83811  * endpoint.
83812  *
83813  * * For OUT endpoints, this bit indicates that the application has allocated the
83814  *
83815  * memory to start receiving data from the USB.
83816  *
83817  * * The core clears this bit before setting any of the following interrupts on
83818  * this
83819  *
83820  * endpoint:
83821  *
83822  * SETUP Phase Done
83823  *
83824  * Endpoint Disabled
83825  *
83826  * Transfer Completed
83827  *
83828  * Note: For control endpoints in DMA mode, this bit must be set to be able to
83829  * transfer
83830  *
83831  * SETUP data packets in memory.
83832  *
83833  * Field Enumeration Values:
83834  *
83835  * Enum | Value | Description
83836  * :-----------------------------------|:------|:-------------------------
83837  * ALT_USB_DEV_DIEPCTL6_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
83838  * ALT_USB_DEV_DIEPCTL6_EPENA_E_ACT | 0x1 | Endpoint Enable active
83839  *
83840  * Field Access Macros:
83841  *
83842  */
83843 /*
83844  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPENA
83845  *
83846  * Endpoint Enable inactive
83847  */
83848 #define ALT_USB_DEV_DIEPCTL6_EPENA_E_INACT 0x0
83849 /*
83850  * Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPENA
83851  *
83852  * Endpoint Enable active
83853  */
83854 #define ALT_USB_DEV_DIEPCTL6_EPENA_E_ACT 0x1
83855 
83856 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */
83857 #define ALT_USB_DEV_DIEPCTL6_EPENA_LSB 31
83858 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */
83859 #define ALT_USB_DEV_DIEPCTL6_EPENA_MSB 31
83860 /* The width in bits of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */
83861 #define ALT_USB_DEV_DIEPCTL6_EPENA_WIDTH 1
83862 /* The mask used to set the ALT_USB_DEV_DIEPCTL6_EPENA register field value. */
83863 #define ALT_USB_DEV_DIEPCTL6_EPENA_SET_MSK 0x80000000
83864 /* The mask used to clear the ALT_USB_DEV_DIEPCTL6_EPENA register field value. */
83865 #define ALT_USB_DEV_DIEPCTL6_EPENA_CLR_MSK 0x7fffffff
83866 /* The reset value of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */
83867 #define ALT_USB_DEV_DIEPCTL6_EPENA_RESET 0x0
83868 /* Extracts the ALT_USB_DEV_DIEPCTL6_EPENA field value from a register. */
83869 #define ALT_USB_DEV_DIEPCTL6_EPENA_GET(value) (((value) & 0x80000000) >> 31)
83870 /* Produces a ALT_USB_DEV_DIEPCTL6_EPENA register field value suitable for setting the register. */
83871 #define ALT_USB_DEV_DIEPCTL6_EPENA_SET(value) (((value) << 31) & 0x80000000)
83872 
83873 #ifndef __ASSEMBLY__
83874 /*
83875  * WARNING: The C register and register group struct declarations are provided for
83876  * convenience and illustrative purposes. They should, however, be used with
83877  * caution as the C language standard provides no guarantees about the alignment or
83878  * atomicity of device memory accesses. The recommended practice for writing
83879  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
83880  * alt_write_word() functions.
83881  *
83882  * The struct declaration for register ALT_USB_DEV_DIEPCTL6.
83883  */
83884 struct ALT_USB_DEV_DIEPCTL6_s
83885 {
83886  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL6_MPS */
83887  uint32_t : 4; /* *UNDEFINED* */
83888  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL6_USBACTEP */
83889  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL6_DPID */
83890  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL6_NAKSTS */
83891  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL6_EPTYPE */
83892  uint32_t : 1; /* *UNDEFINED* */
83893  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL6_STALL */
83894  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL6_TXFNUM */
83895  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL6_CNAK */
83896  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL6_SNAK */
83897  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL6_SETD0PID */
83898  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL6_SETD1PID */
83899  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL6_EPDIS */
83900  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL6_EPENA */
83901 };
83902 
83903 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL6. */
83904 typedef volatile struct ALT_USB_DEV_DIEPCTL6_s ALT_USB_DEV_DIEPCTL6_t;
83905 #endif /* __ASSEMBLY__ */
83906 
83907 /* The reset value of the ALT_USB_DEV_DIEPCTL6 register. */
83908 #define ALT_USB_DEV_DIEPCTL6_RESET 0x00000000
83909 /* The byte offset of the ALT_USB_DEV_DIEPCTL6 register from the beginning of the component. */
83910 #define ALT_USB_DEV_DIEPCTL6_OFST 0x1c0
83911 /* The address of the ALT_USB_DEV_DIEPCTL6 register. */
83912 #define ALT_USB_DEV_DIEPCTL6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL6_OFST))
83913 
83914 /*
83915  * Register : diepint6
83916  *
83917  * Device IN Endpoint 6 Interrupt Register
83918  *
83919  * Register Layout
83920  *
83921  * Bits | Access | Reset | Description
83922  * :--------|:-------|:------|:---------------------------------
83923  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_XFERCOMPL
83924  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_EPDISBLD
83925  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_AHBERR
83926  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_TMO
83927  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_INTKNTXFEMP
83928  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_INTKNEPMIS
83929  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_INEPNAKEFF
83930  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT6_TXFEMP
83931  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN
83932  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_BNAINTR
83933  * [10] | ??? | 0x0 | *UNDEFINED*
83934  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_PKTDRPSTS
83935  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_BBLEERR
83936  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_NAKINTRPT
83937  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_NYETINTRPT
83938  * [31:15] | ??? | 0x0 | *UNDEFINED*
83939  *
83940  */
83941 /*
83942  * Field : xfercompl
83943  *
83944  * Transfer Completed Interrupt (XferCompl)
83945  *
83946  * Applies to IN and OUT endpoints.
83947  *
83948  * When Scatter/Gather DMA mode is enabled
83949  *
83950  * * For IN endpoint this field indicates that the requested data
83951  *
83952  * from the descriptor is moved from external system memory
83953  *
83954  * to internal FIFO.
83955  *
83956  * * For OUT endpoint this field indicates that the requested
83957  *
83958  * data from the internal FIFO is moved to external system
83959  *
83960  * memory. This interrupt is generated only when the
83961  *
83962  * corresponding endpoint descriptor is closed, and the IOC
83963  *
83964  * bit For the corresponding descriptor is Set.
83965  *
83966  * When Scatter/Gather DMA mode is disabled, this field
83967  *
83968  * indicates that the programmed transfer is complete on the
83969  *
83970  * AHB as well as on the USB, For this endpoint.
83971  *
83972  * Field Enumeration Values:
83973  *
83974  * Enum | Value | Description
83975  * :---------------------------------------|:------|:-----------------------------
83976  * ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_INACT | 0x0 | No Interrupt
83977  * ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
83978  *
83979  * Field Access Macros:
83980  *
83981  */
83982 /*
83983  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_XFERCOMPL
83984  *
83985  * No Interrupt
83986  */
83987 #define ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_INACT 0x0
83988 /*
83989  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_XFERCOMPL
83990  *
83991  * Transfer Completed Interrupt
83992  */
83993 #define ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_ACT 0x1
83994 
83995 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */
83996 #define ALT_USB_DEV_DIEPINT6_XFERCOMPL_LSB 0
83997 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */
83998 #define ALT_USB_DEV_DIEPINT6_XFERCOMPL_MSB 0
83999 /* The width in bits of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */
84000 #define ALT_USB_DEV_DIEPINT6_XFERCOMPL_WIDTH 1
84001 /* The mask used to set the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field value. */
84002 #define ALT_USB_DEV_DIEPINT6_XFERCOMPL_SET_MSK 0x00000001
84003 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field value. */
84004 #define ALT_USB_DEV_DIEPINT6_XFERCOMPL_CLR_MSK 0xfffffffe
84005 /* The reset value of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */
84006 #define ALT_USB_DEV_DIEPINT6_XFERCOMPL_RESET 0x0
84007 /* Extracts the ALT_USB_DEV_DIEPINT6_XFERCOMPL field value from a register. */
84008 #define ALT_USB_DEV_DIEPINT6_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
84009 /* Produces a ALT_USB_DEV_DIEPINT6_XFERCOMPL register field value suitable for setting the register. */
84010 #define ALT_USB_DEV_DIEPINT6_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
84011 
84012 /*
84013  * Field : epdisbld
84014  *
84015  * Endpoint Disabled Interrupt (EPDisbld)
84016  *
84017  * Applies to IN and OUT endpoints.
84018  *
84019  * This bit indicates that the endpoint is disabled per the
84020  *
84021  * application's request.
84022  *
84023  * Field Enumeration Values:
84024  *
84025  * Enum | Value | Description
84026  * :--------------------------------------|:------|:----------------------------
84027  * ALT_USB_DEV_DIEPINT6_EPDISBLD_E_INACT | 0x0 | No Interrupt
84028  * ALT_USB_DEV_DIEPINT6_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
84029  *
84030  * Field Access Macros:
84031  *
84032  */
84033 /*
84034  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_EPDISBLD
84035  *
84036  * No Interrupt
84037  */
84038 #define ALT_USB_DEV_DIEPINT6_EPDISBLD_E_INACT 0x0
84039 /*
84040  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_EPDISBLD
84041  *
84042  * Endpoint Disabled Interrupt
84043  */
84044 #define ALT_USB_DEV_DIEPINT6_EPDISBLD_E_ACT 0x1
84045 
84046 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */
84047 #define ALT_USB_DEV_DIEPINT6_EPDISBLD_LSB 1
84048 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */
84049 #define ALT_USB_DEV_DIEPINT6_EPDISBLD_MSB 1
84050 /* The width in bits of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */
84051 #define ALT_USB_DEV_DIEPINT6_EPDISBLD_WIDTH 1
84052 /* The mask used to set the ALT_USB_DEV_DIEPINT6_EPDISBLD register field value. */
84053 #define ALT_USB_DEV_DIEPINT6_EPDISBLD_SET_MSK 0x00000002
84054 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_EPDISBLD register field value. */
84055 #define ALT_USB_DEV_DIEPINT6_EPDISBLD_CLR_MSK 0xfffffffd
84056 /* The reset value of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */
84057 #define ALT_USB_DEV_DIEPINT6_EPDISBLD_RESET 0x0
84058 /* Extracts the ALT_USB_DEV_DIEPINT6_EPDISBLD field value from a register. */
84059 #define ALT_USB_DEV_DIEPINT6_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
84060 /* Produces a ALT_USB_DEV_DIEPINT6_EPDISBLD register field value suitable for setting the register. */
84061 #define ALT_USB_DEV_DIEPINT6_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
84062 
84063 /*
84064  * Field : ahberr
84065  *
84066  * AHB Error (AHBErr)
84067  *
84068  * Applies to IN and OUT endpoints.
84069  *
84070  * This is generated only in Internal DMA mode when there is an
84071  *
84072  * AHB error during an AHB read/write. The application can read
84073  *
84074  * the corresponding endpoint DMA address register to get the
84075  *
84076  * error address.
84077  *
84078  * Field Enumeration Values:
84079  *
84080  * Enum | Value | Description
84081  * :------------------------------------|:------|:--------------------
84082  * ALT_USB_DEV_DIEPINT6_AHBERR_E_INACT | 0x0 | No Interrupt
84083  * ALT_USB_DEV_DIEPINT6_AHBERR_E_ACT | 0x1 | AHB Error interrupt
84084  *
84085  * Field Access Macros:
84086  *
84087  */
84088 /*
84089  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_AHBERR
84090  *
84091  * No Interrupt
84092  */
84093 #define ALT_USB_DEV_DIEPINT6_AHBERR_E_INACT 0x0
84094 /*
84095  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_AHBERR
84096  *
84097  * AHB Error interrupt
84098  */
84099 #define ALT_USB_DEV_DIEPINT6_AHBERR_E_ACT 0x1
84100 
84101 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */
84102 #define ALT_USB_DEV_DIEPINT6_AHBERR_LSB 2
84103 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */
84104 #define ALT_USB_DEV_DIEPINT6_AHBERR_MSB 2
84105 /* The width in bits of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */
84106 #define ALT_USB_DEV_DIEPINT6_AHBERR_WIDTH 1
84107 /* The mask used to set the ALT_USB_DEV_DIEPINT6_AHBERR register field value. */
84108 #define ALT_USB_DEV_DIEPINT6_AHBERR_SET_MSK 0x00000004
84109 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_AHBERR register field value. */
84110 #define ALT_USB_DEV_DIEPINT6_AHBERR_CLR_MSK 0xfffffffb
84111 /* The reset value of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */
84112 #define ALT_USB_DEV_DIEPINT6_AHBERR_RESET 0x0
84113 /* Extracts the ALT_USB_DEV_DIEPINT6_AHBERR field value from a register. */
84114 #define ALT_USB_DEV_DIEPINT6_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
84115 /* Produces a ALT_USB_DEV_DIEPINT6_AHBERR register field value suitable for setting the register. */
84116 #define ALT_USB_DEV_DIEPINT6_AHBERR_SET(value) (((value) << 2) & 0x00000004)
84117 
84118 /*
84119  * Field : timeout
84120  *
84121  * Timeout Condition (TimeOUT)
84122  *
84123  * In shared TX FIFO mode, applies to non-isochronous IN
84124  *
84125  * endpoints only.
84126  *
84127  * In dedicated FIFO mode, applies only to Control IN
84128  *
84129  * endpoints.
84130  *
84131  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
84132  *
84133  * asserted.
84134  *
84135  * Indicates that the core has detected a timeout condition on the
84136  *
84137  * USB For the last IN token on this endpoint.
84138  *
84139  * Field Enumeration Values:
84140  *
84141  * Enum | Value | Description
84142  * :---------------------------------|:------|:------------------
84143  * ALT_USB_DEV_DIEPINT6_TMO_E_INACT | 0x0 | No interrupt
84144  * ALT_USB_DEV_DIEPINT6_TMO_E_ACT | 0x1 | Timeout interrupy
84145  *
84146  * Field Access Macros:
84147  *
84148  */
84149 /*
84150  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TMO
84151  *
84152  * No interrupt
84153  */
84154 #define ALT_USB_DEV_DIEPINT6_TMO_E_INACT 0x0
84155 /*
84156  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TMO
84157  *
84158  * Timeout interrupy
84159  */
84160 #define ALT_USB_DEV_DIEPINT6_TMO_E_ACT 0x1
84161 
84162 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_TMO register field. */
84163 #define ALT_USB_DEV_DIEPINT6_TMO_LSB 3
84164 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_TMO register field. */
84165 #define ALT_USB_DEV_DIEPINT6_TMO_MSB 3
84166 /* The width in bits of the ALT_USB_DEV_DIEPINT6_TMO register field. */
84167 #define ALT_USB_DEV_DIEPINT6_TMO_WIDTH 1
84168 /* The mask used to set the ALT_USB_DEV_DIEPINT6_TMO register field value. */
84169 #define ALT_USB_DEV_DIEPINT6_TMO_SET_MSK 0x00000008
84170 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_TMO register field value. */
84171 #define ALT_USB_DEV_DIEPINT6_TMO_CLR_MSK 0xfffffff7
84172 /* The reset value of the ALT_USB_DEV_DIEPINT6_TMO register field. */
84173 #define ALT_USB_DEV_DIEPINT6_TMO_RESET 0x0
84174 /* Extracts the ALT_USB_DEV_DIEPINT6_TMO field value from a register. */
84175 #define ALT_USB_DEV_DIEPINT6_TMO_GET(value) (((value) & 0x00000008) >> 3)
84176 /* Produces a ALT_USB_DEV_DIEPINT6_TMO register field value suitable for setting the register. */
84177 #define ALT_USB_DEV_DIEPINT6_TMO_SET(value) (((value) << 3) & 0x00000008)
84178 
84179 /*
84180  * Field : intkntxfemp
84181  *
84182  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
84183  *
84184  * Applies to non-periodic IN endpoints only.
84185  *
84186  * Indicates that an IN token was received when the associated
84187  *
84188  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
84189  *
84190  * asserted on the endpoint For which the IN token was received.
84191  *
84192  * Field Enumeration Values:
84193  *
84194  * Enum | Value | Description
84195  * :-----------------------------------------|:------|:----------------------------
84196  * ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
84197  * ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
84198  *
84199  * Field Access Macros:
84200  *
84201  */
84202 /*
84203  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNTXFEMP
84204  *
84205  * No interrupt
84206  */
84207 #define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_INACT 0x0
84208 /*
84209  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNTXFEMP
84210  *
84211  * IN Token Received Interrupt
84212  */
84213 #define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_ACT 0x1
84214 
84215 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */
84216 #define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_LSB 4
84217 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */
84218 #define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_MSB 4
84219 /* The width in bits of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */
84220 #define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_WIDTH 1
84221 /* The mask used to set the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field value. */
84222 #define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_SET_MSK 0x00000010
84223 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field value. */
84224 #define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_CLR_MSK 0xffffffef
84225 /* The reset value of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */
84226 #define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_RESET 0x0
84227 /* Extracts the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP field value from a register. */
84228 #define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
84229 /* Produces a ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field value suitable for setting the register. */
84230 #define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
84231 
84232 /*
84233  * Field : intknepmis
84234  *
84235  * IN Token Received with EP Mismatch (INTknEPMis)
84236  *
84237  * Applies to non-periodic IN endpoints only.
84238  *
84239  * Indicates that the data in the top of the non-periodic TxFIFO
84240  *
84241  * belongs to an endpoint other than the one For which the IN token
84242  *
84243  * was received. This interrupt is asserted on the endpoint For
84244  *
84245  * which the IN token was received.
84246  *
84247  * Field Enumeration Values:
84248  *
84249  * Enum | Value | Description
84250  * :----------------------------------------|:------|:---------------------------------------------
84251  * ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_INACT | 0x0 | No interrupt
84252  * ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
84253  *
84254  * Field Access Macros:
84255  *
84256  */
84257 /*
84258  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNEPMIS
84259  *
84260  * No interrupt
84261  */
84262 #define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_INACT 0x0
84263 /*
84264  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNEPMIS
84265  *
84266  * IN Token Received with EP Mismatch interrupt
84267  */
84268 #define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_ACT 0x1
84269 
84270 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */
84271 #define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_LSB 5
84272 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */
84273 #define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_MSB 5
84274 /* The width in bits of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */
84275 #define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_WIDTH 1
84276 /* The mask used to set the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field value. */
84277 #define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_SET_MSK 0x00000020
84278 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field value. */
84279 #define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_CLR_MSK 0xffffffdf
84280 /* The reset value of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */
84281 #define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_RESET 0x0
84282 /* Extracts the ALT_USB_DEV_DIEPINT6_INTKNEPMIS field value from a register. */
84283 #define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
84284 /* Produces a ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field value suitable for setting the register. */
84285 #define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
84286 
84287 /*
84288  * Field : inepnakeff
84289  *
84290  * IN Endpoint NAK Effective (INEPNakEff)
84291  *
84292  * Applies to periodic IN endpoints only.
84293  *
84294  * This bit can be cleared when the application clears the IN
84295  *
84296  * endpoint NAK by writing to DIEPCTLn.CNAK.
84297  *
84298  * This interrupt indicates that the core has sampled the NAK bit
84299  *
84300  * Set (either by the application or by the core). The interrupt
84301  *
84302  * indicates that the IN endpoint NAK bit Set by the application has
84303  *
84304  * taken effect in the core.
84305  *
84306  * This interrupt does not guarantee that a NAK handshake is sent
84307  *
84308  * on the USB. A STALL bit takes priority over a NAK bit.
84309  *
84310  * Field Enumeration Values:
84311  *
84312  * Enum | Value | Description
84313  * :----------------------------------------|:------|:------------------------------------
84314  * ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_INACT | 0x0 | No interrupt
84315  * ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
84316  *
84317  * Field Access Macros:
84318  *
84319  */
84320 /*
84321  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INEPNAKEFF
84322  *
84323  * No interrupt
84324  */
84325 #define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_INACT 0x0
84326 /*
84327  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_INEPNAKEFF
84328  *
84329  * IN Endpoint NAK Effective interrupt
84330  */
84331 #define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_ACT 0x1
84332 
84333 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */
84334 #define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_LSB 6
84335 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */
84336 #define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_MSB 6
84337 /* The width in bits of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */
84338 #define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_WIDTH 1
84339 /* The mask used to set the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field value. */
84340 #define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_SET_MSK 0x00000040
84341 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field value. */
84342 #define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_CLR_MSK 0xffffffbf
84343 /* The reset value of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */
84344 #define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_RESET 0x0
84345 /* Extracts the ALT_USB_DEV_DIEPINT6_INEPNAKEFF field value from a register. */
84346 #define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
84347 /* Produces a ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field value suitable for setting the register. */
84348 #define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
84349 
84350 /*
84351  * Field : txfemp
84352  *
84353  * Transmit FIFO Empty (TxFEmp)
84354  *
84355  * This bit is valid only For IN Endpoints
84356  *
84357  * This interrupt is asserted when the TxFIFO For this endpoint is
84358  *
84359  * either half or completely empty. The half or completely empty
84360  *
84361  * status is determined by the TxFIFO Empty Level bit in the Core
84362  *
84363  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
84364  *
84365  * Field Enumeration Values:
84366  *
84367  * Enum | Value | Description
84368  * :------------------------------------|:------|:------------------------------
84369  * ALT_USB_DEV_DIEPINT6_TXFEMP_E_INACT | 0x0 | No interrupt
84370  * ALT_USB_DEV_DIEPINT6_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
84371  *
84372  * Field Access Macros:
84373  *
84374  */
84375 /*
84376  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFEMP
84377  *
84378  * No interrupt
84379  */
84380 #define ALT_USB_DEV_DIEPINT6_TXFEMP_E_INACT 0x0
84381 /*
84382  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFEMP
84383  *
84384  * Transmit FIFO Empty interrupt
84385  */
84386 #define ALT_USB_DEV_DIEPINT6_TXFEMP_E_ACT 0x1
84387 
84388 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */
84389 #define ALT_USB_DEV_DIEPINT6_TXFEMP_LSB 7
84390 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */
84391 #define ALT_USB_DEV_DIEPINT6_TXFEMP_MSB 7
84392 /* The width in bits of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */
84393 #define ALT_USB_DEV_DIEPINT6_TXFEMP_WIDTH 1
84394 /* The mask used to set the ALT_USB_DEV_DIEPINT6_TXFEMP register field value. */
84395 #define ALT_USB_DEV_DIEPINT6_TXFEMP_SET_MSK 0x00000080
84396 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_TXFEMP register field value. */
84397 #define ALT_USB_DEV_DIEPINT6_TXFEMP_CLR_MSK 0xffffff7f
84398 /* The reset value of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */
84399 #define ALT_USB_DEV_DIEPINT6_TXFEMP_RESET 0x1
84400 /* Extracts the ALT_USB_DEV_DIEPINT6_TXFEMP field value from a register. */
84401 #define ALT_USB_DEV_DIEPINT6_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
84402 /* Produces a ALT_USB_DEV_DIEPINT6_TXFEMP register field value suitable for setting the register. */
84403 #define ALT_USB_DEV_DIEPINT6_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
84404 
84405 /*
84406  * Field : txfifoundrn
84407  *
84408  * Fifo Underrun (TxfifoUndrn)
84409  *
84410  * Applies to IN endpoints Only
84411  *
84412  * This bit is valid only If thresholding is enabled. The core generates this
84413  * interrupt when
84414  *
84415  * it detects a transmit FIFO underrun condition For this endpoint.
84416  *
84417  * Field Enumeration Values:
84418  *
84419  * Enum | Value | Description
84420  * :-----------------------------------------|:------|:------------------------
84421  * ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
84422  * ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
84423  *
84424  * Field Access Macros:
84425  *
84426  */
84427 /*
84428  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN
84429  *
84430  * No interrupt
84431  */
84432 #define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_INACT 0x0
84433 /*
84434  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN
84435  *
84436  * Fifo Underrun interrupt
84437  */
84438 #define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_ACT 0x1
84439 
84440 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */
84441 #define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_LSB 8
84442 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */
84443 #define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_MSB 8
84444 /* The width in bits of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */
84445 #define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_WIDTH 1
84446 /* The mask used to set the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field value. */
84447 #define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_SET_MSK 0x00000100
84448 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field value. */
84449 #define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_CLR_MSK 0xfffffeff
84450 /* The reset value of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */
84451 #define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_RESET 0x0
84452 /* Extracts the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN field value from a register. */
84453 #define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
84454 /* Produces a ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field value suitable for setting the register. */
84455 #define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
84456 
84457 /*
84458  * Field : bnaintr
84459  *
84460  * BNA (Buffer Not Available) Interrupt (BNAIntr)
84461  *
84462  * This bit is valid only when Scatter/Gather DMA mode is enabled.
84463  *
84464  * The core generates this interrupt when the descriptor accessed
84465  *
84466  * is not ready For the Core to process, such as Host busy or DMA
84467  *
84468  * done
84469  *
84470  * Field Enumeration Values:
84471  *
84472  * Enum | Value | Description
84473  * :-------------------------------------|:------|:--------------
84474  * ALT_USB_DEV_DIEPINT6_BNAINTR_E_INACT | 0x0 | No interrupt
84475  * ALT_USB_DEV_DIEPINT6_BNAINTR_E_ACT | 0x1 | BNA interrupt
84476  *
84477  * Field Access Macros:
84478  *
84479  */
84480 /*
84481  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_BNAINTR
84482  *
84483  * No interrupt
84484  */
84485 #define ALT_USB_DEV_DIEPINT6_BNAINTR_E_INACT 0x0
84486 /*
84487  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_BNAINTR
84488  *
84489  * BNA interrupt
84490  */
84491 #define ALT_USB_DEV_DIEPINT6_BNAINTR_E_ACT 0x1
84492 
84493 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */
84494 #define ALT_USB_DEV_DIEPINT6_BNAINTR_LSB 9
84495 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */
84496 #define ALT_USB_DEV_DIEPINT6_BNAINTR_MSB 9
84497 /* The width in bits of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */
84498 #define ALT_USB_DEV_DIEPINT6_BNAINTR_WIDTH 1
84499 /* The mask used to set the ALT_USB_DEV_DIEPINT6_BNAINTR register field value. */
84500 #define ALT_USB_DEV_DIEPINT6_BNAINTR_SET_MSK 0x00000200
84501 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_BNAINTR register field value. */
84502 #define ALT_USB_DEV_DIEPINT6_BNAINTR_CLR_MSK 0xfffffdff
84503 /* The reset value of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */
84504 #define ALT_USB_DEV_DIEPINT6_BNAINTR_RESET 0x0
84505 /* Extracts the ALT_USB_DEV_DIEPINT6_BNAINTR field value from a register. */
84506 #define ALT_USB_DEV_DIEPINT6_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
84507 /* Produces a ALT_USB_DEV_DIEPINT6_BNAINTR register field value suitable for setting the register. */
84508 #define ALT_USB_DEV_DIEPINT6_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
84509 
84510 /*
84511  * Field : pktdrpsts
84512  *
84513  * Packet Drop Status (PktDrpSts)
84514  *
84515  * This bit indicates to the application that an ISOC OUT packet has been dropped.
84516  * This
84517  *
84518  * bit does not have an associated mask bit and does not generate an interrupt.
84519  *
84520  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
84521  * transfer
84522  *
84523  * interrupt feature is selected.
84524  *
84525  * Field Enumeration Values:
84526  *
84527  * Enum | Value | Description
84528  * :---------------------------------------|:------|:-----------------------------
84529  * ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_INACT | 0x0 | No interrupt
84530  * ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
84531  *
84532  * Field Access Macros:
84533  *
84534  */
84535 /*
84536  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_PKTDRPSTS
84537  *
84538  * No interrupt
84539  */
84540 #define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_INACT 0x0
84541 /*
84542  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_PKTDRPSTS
84543  *
84544  * Packet Drop Status interrupt
84545  */
84546 #define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_ACT 0x1
84547 
84548 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */
84549 #define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_LSB 11
84550 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */
84551 #define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_MSB 11
84552 /* The width in bits of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */
84553 #define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_WIDTH 1
84554 /* The mask used to set the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field value. */
84555 #define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_SET_MSK 0x00000800
84556 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field value. */
84557 #define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_CLR_MSK 0xfffff7ff
84558 /* The reset value of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */
84559 #define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_RESET 0x0
84560 /* Extracts the ALT_USB_DEV_DIEPINT6_PKTDRPSTS field value from a register. */
84561 #define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
84562 /* Produces a ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field value suitable for setting the register. */
84563 #define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
84564 
84565 /*
84566  * Field : bbleerr
84567  *
84568  * NAK Interrupt (BbleErr)
84569  *
84570  * The core generates this interrupt when babble is received for the endpoint.
84571  *
84572  * Field Enumeration Values:
84573  *
84574  * Enum | Value | Description
84575  * :-------------------------------------|:------|:------------------
84576  * ALT_USB_DEV_DIEPINT6_BBLEERR_E_INACT | 0x0 | No interrupt
84577  * ALT_USB_DEV_DIEPINT6_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
84578  *
84579  * Field Access Macros:
84580  *
84581  */
84582 /*
84583  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_BBLEERR
84584  *
84585  * No interrupt
84586  */
84587 #define ALT_USB_DEV_DIEPINT6_BBLEERR_E_INACT 0x0
84588 /*
84589  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_BBLEERR
84590  *
84591  * BbleErr interrupt
84592  */
84593 #define ALT_USB_DEV_DIEPINT6_BBLEERR_E_ACT 0x1
84594 
84595 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */
84596 #define ALT_USB_DEV_DIEPINT6_BBLEERR_LSB 12
84597 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */
84598 #define ALT_USB_DEV_DIEPINT6_BBLEERR_MSB 12
84599 /* The width in bits of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */
84600 #define ALT_USB_DEV_DIEPINT6_BBLEERR_WIDTH 1
84601 /* The mask used to set the ALT_USB_DEV_DIEPINT6_BBLEERR register field value. */
84602 #define ALT_USB_DEV_DIEPINT6_BBLEERR_SET_MSK 0x00001000
84603 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_BBLEERR register field value. */
84604 #define ALT_USB_DEV_DIEPINT6_BBLEERR_CLR_MSK 0xffffefff
84605 /* The reset value of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */
84606 #define ALT_USB_DEV_DIEPINT6_BBLEERR_RESET 0x0
84607 /* Extracts the ALT_USB_DEV_DIEPINT6_BBLEERR field value from a register. */
84608 #define ALT_USB_DEV_DIEPINT6_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
84609 /* Produces a ALT_USB_DEV_DIEPINT6_BBLEERR register field value suitable for setting the register. */
84610 #define ALT_USB_DEV_DIEPINT6_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
84611 
84612 /*
84613  * Field : nakintrpt
84614  *
84615  * NAK Interrupt (NAKInterrupt)
84616  *
84617  * The core generates this interrupt when a NAK is transmitted or received by the
84618  * device.
84619  *
84620  * In case of isochronous IN endpoints the interrupt gets generated when a zero
84621  * length
84622  *
84623  * packet is transmitted due to un-availability of data in the TXFifo.
84624  *
84625  * Field Enumeration Values:
84626  *
84627  * Enum | Value | Description
84628  * :---------------------------------------|:------|:--------------
84629  * ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_INACT | 0x0 | No interrupt
84630  * ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
84631  *
84632  * Field Access Macros:
84633  *
84634  */
84635 /*
84636  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_NAKINTRPT
84637  *
84638  * No interrupt
84639  */
84640 #define ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_INACT 0x0
84641 /*
84642  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_NAKINTRPT
84643  *
84644  * NAK Interrupt
84645  */
84646 #define ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_ACT 0x1
84647 
84648 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */
84649 #define ALT_USB_DEV_DIEPINT6_NAKINTRPT_LSB 13
84650 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */
84651 #define ALT_USB_DEV_DIEPINT6_NAKINTRPT_MSB 13
84652 /* The width in bits of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */
84653 #define ALT_USB_DEV_DIEPINT6_NAKINTRPT_WIDTH 1
84654 /* The mask used to set the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field value. */
84655 #define ALT_USB_DEV_DIEPINT6_NAKINTRPT_SET_MSK 0x00002000
84656 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field value. */
84657 #define ALT_USB_DEV_DIEPINT6_NAKINTRPT_CLR_MSK 0xffffdfff
84658 /* The reset value of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */
84659 #define ALT_USB_DEV_DIEPINT6_NAKINTRPT_RESET 0x0
84660 /* Extracts the ALT_USB_DEV_DIEPINT6_NAKINTRPT field value from a register. */
84661 #define ALT_USB_DEV_DIEPINT6_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
84662 /* Produces a ALT_USB_DEV_DIEPINT6_NAKINTRPT register field value suitable for setting the register. */
84663 #define ALT_USB_DEV_DIEPINT6_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
84664 
84665 /*
84666  * Field : nyetintrpt
84667  *
84668  * NYET Interrupt (NYETIntrpt)
84669  *
84670  * The core generates this interrupt when a NYET response is transmitted for a non
84671  * isochronous OUT endpoint.
84672  *
84673  * Field Enumeration Values:
84674  *
84675  * Enum | Value | Description
84676  * :----------------------------------------|:------|:---------------
84677  * ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_INACT | 0x0 | No interrupt
84678  * ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
84679  *
84680  * Field Access Macros:
84681  *
84682  */
84683 /*
84684  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_NYETINTRPT
84685  *
84686  * No interrupt
84687  */
84688 #define ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_INACT 0x0
84689 /*
84690  * Enumerated value for register field ALT_USB_DEV_DIEPINT6_NYETINTRPT
84691  *
84692  * NYET Interrupt
84693  */
84694 #define ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_ACT 0x1
84695 
84696 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */
84697 #define ALT_USB_DEV_DIEPINT6_NYETINTRPT_LSB 14
84698 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */
84699 #define ALT_USB_DEV_DIEPINT6_NYETINTRPT_MSB 14
84700 /* The width in bits of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */
84701 #define ALT_USB_DEV_DIEPINT6_NYETINTRPT_WIDTH 1
84702 /* The mask used to set the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field value. */
84703 #define ALT_USB_DEV_DIEPINT6_NYETINTRPT_SET_MSK 0x00004000
84704 /* The mask used to clear the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field value. */
84705 #define ALT_USB_DEV_DIEPINT6_NYETINTRPT_CLR_MSK 0xffffbfff
84706 /* The reset value of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */
84707 #define ALT_USB_DEV_DIEPINT6_NYETINTRPT_RESET 0x0
84708 /* Extracts the ALT_USB_DEV_DIEPINT6_NYETINTRPT field value from a register. */
84709 #define ALT_USB_DEV_DIEPINT6_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
84710 /* Produces a ALT_USB_DEV_DIEPINT6_NYETINTRPT register field value suitable for setting the register. */
84711 #define ALT_USB_DEV_DIEPINT6_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
84712 
84713 #ifndef __ASSEMBLY__
84714 /*
84715  * WARNING: The C register and register group struct declarations are provided for
84716  * convenience and illustrative purposes. They should, however, be used with
84717  * caution as the C language standard provides no guarantees about the alignment or
84718  * atomicity of device memory accesses. The recommended practice for writing
84719  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
84720  * alt_write_word() functions.
84721  *
84722  * The struct declaration for register ALT_USB_DEV_DIEPINT6.
84723  */
84724 struct ALT_USB_DEV_DIEPINT6_s
84725 {
84726  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT6_XFERCOMPL */
84727  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT6_EPDISBLD */
84728  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT6_AHBERR */
84729  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT6_TMO */
84730  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT6_INTKNTXFEMP */
84731  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT6_INTKNEPMIS */
84732  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT6_INEPNAKEFF */
84733  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT6_TXFEMP */
84734  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN */
84735  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT6_BNAINTR */
84736  uint32_t : 1; /* *UNDEFINED* */
84737  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT6_PKTDRPSTS */
84738  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT6_BBLEERR */
84739  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT6_NAKINTRPT */
84740  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT6_NYETINTRPT */
84741  uint32_t : 17; /* *UNDEFINED* */
84742 };
84743 
84744 /* The typedef declaration for register ALT_USB_DEV_DIEPINT6. */
84745 typedef volatile struct ALT_USB_DEV_DIEPINT6_s ALT_USB_DEV_DIEPINT6_t;
84746 #endif /* __ASSEMBLY__ */
84747 
84748 /* The reset value of the ALT_USB_DEV_DIEPINT6 register. */
84749 #define ALT_USB_DEV_DIEPINT6_RESET 0x00000080
84750 /* The byte offset of the ALT_USB_DEV_DIEPINT6 register from the beginning of the component. */
84751 #define ALT_USB_DEV_DIEPINT6_OFST 0x1c8
84752 /* The address of the ALT_USB_DEV_DIEPINT6 register. */
84753 #define ALT_USB_DEV_DIEPINT6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT6_OFST))
84754 
84755 /*
84756  * Register : dieptsiz6
84757  *
84758  * Device IN Endpoint 6 Transfer Size Register
84759  *
84760  * Register Layout
84761  *
84762  * Bits | Access | Reset | Description
84763  * :--------|:-------|:------|:-------------------------------
84764  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ6_XFERSIZE
84765  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ6_PKTCNT
84766  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ6_MC
84767  * [31] | ??? | 0x0 | *UNDEFINED*
84768  *
84769  */
84770 /*
84771  * Field : xfersize
84772  *
84773  * Transfer Size (XferSize)
84774  *
84775  * Indicates the transfer size in bytes For endpoint 0. The core
84776  *
84777  * interrupts the application only after it has exhausted the transfer
84778  *
84779  * size amount of data. The transfer size can be Set to the
84780  *
84781  * maximum packet size of the endpoint, to be interrupted at the
84782  *
84783  * end of each packet.
84784  *
84785  * The core decrements this field every time a packet from the
84786  *
84787  * external memory is written to the TxFIFO.
84788  *
84789  * Field Access Macros:
84790  *
84791  */
84792 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */
84793 #define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_LSB 0
84794 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */
84795 #define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_MSB 18
84796 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */
84797 #define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_WIDTH 19
84798 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field value. */
84799 #define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_SET_MSK 0x0007ffff
84800 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field value. */
84801 #define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_CLR_MSK 0xfff80000
84802 /* The reset value of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */
84803 #define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_RESET 0x0
84804 /* Extracts the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE field value from a register. */
84805 #define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
84806 /* Produces a ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field value suitable for setting the register. */
84807 #define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
84808 
84809 /*
84810  * Field : pktcnt
84811  *
84812  * Packet Count (PktCnt)
84813  *
84814  * Indicates the total number of USB packets that constitute the
84815  *
84816  * Transfer Size amount of data For endpoint 0.
84817  *
84818  * This field is decremented every time a packet (maximum size or
84819  *
84820  * short packet) is read from the TxFIFO.
84821  *
84822  * Field Access Macros:
84823  *
84824  */
84825 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */
84826 #define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_LSB 19
84827 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */
84828 #define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_MSB 28
84829 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */
84830 #define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_WIDTH 10
84831 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field value. */
84832 #define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_SET_MSK 0x1ff80000
84833 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field value. */
84834 #define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_CLR_MSK 0xe007ffff
84835 /* The reset value of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */
84836 #define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_RESET 0x0
84837 /* Extracts the ALT_USB_DEV_DIEPTSIZ6_PKTCNT field value from a register. */
84838 #define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
84839 /* Produces a ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field value suitable for setting the register. */
84840 #define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
84841 
84842 /*
84843  * Field : mc
84844  *
84845  * Applies to IN endpoints only.
84846  *
84847  * For periodic IN endpoints, this field indicates the number of packets that must
84848  * be transmitted per microframe on the USB. The core uses this field to calculate
84849  * the data PID for isochronous IN endpoints.
84850  *
84851  * 2'b01: 1 packet
84852  *
84853  * 2'b10: 2 packets
84854  *
84855  * 2'b11: 3 packets
84856  *
84857  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
84858  * specifies the number of packets the core must fetchfor an IN endpoint before it
84859  * switches to the endpoint pointed to by the Next Endpoint field of the Device
84860  * Endpoint-n Control register (DIEPCTLn.NextEp)
84861  *
84862  * Field Enumeration Values:
84863  *
84864  * Enum | Value | Description
84865  * :------------------------------------|:------|:------------
84866  * ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTONE | 0x1 | 1 packet
84867  * ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTWO | 0x2 | 2 packets
84868  * ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTHREE | 0x3 | 3 packets
84869  *
84870  * Field Access Macros:
84871  *
84872  */
84873 /*
84874  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ6_MC
84875  *
84876  * 1 packet
84877  */
84878 #define ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTONE 0x1
84879 /*
84880  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ6_MC
84881  *
84882  * 2 packets
84883  */
84884 #define ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTWO 0x2
84885 /*
84886  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ6_MC
84887  *
84888  * 3 packets
84889  */
84890 #define ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTHREE 0x3
84891 
84892 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */
84893 #define ALT_USB_DEV_DIEPTSIZ6_MC_LSB 29
84894 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */
84895 #define ALT_USB_DEV_DIEPTSIZ6_MC_MSB 30
84896 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */
84897 #define ALT_USB_DEV_DIEPTSIZ6_MC_WIDTH 2
84898 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ6_MC register field value. */
84899 #define ALT_USB_DEV_DIEPTSIZ6_MC_SET_MSK 0x60000000
84900 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ6_MC register field value. */
84901 #define ALT_USB_DEV_DIEPTSIZ6_MC_CLR_MSK 0x9fffffff
84902 /* The reset value of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */
84903 #define ALT_USB_DEV_DIEPTSIZ6_MC_RESET 0x0
84904 /* Extracts the ALT_USB_DEV_DIEPTSIZ6_MC field value from a register. */
84905 #define ALT_USB_DEV_DIEPTSIZ6_MC_GET(value) (((value) & 0x60000000) >> 29)
84906 /* Produces a ALT_USB_DEV_DIEPTSIZ6_MC register field value suitable for setting the register. */
84907 #define ALT_USB_DEV_DIEPTSIZ6_MC_SET(value) (((value) << 29) & 0x60000000)
84908 
84909 #ifndef __ASSEMBLY__
84910 /*
84911  * WARNING: The C register and register group struct declarations are provided for
84912  * convenience and illustrative purposes. They should, however, be used with
84913  * caution as the C language standard provides no guarantees about the alignment or
84914  * atomicity of device memory accesses. The recommended practice for writing
84915  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
84916  * alt_write_word() functions.
84917  *
84918  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ6.
84919  */
84920 struct ALT_USB_DEV_DIEPTSIZ6_s
84921 {
84922  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ6_XFERSIZE */
84923  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ6_PKTCNT */
84924  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ6_MC */
84925  uint32_t : 1; /* *UNDEFINED* */
84926 };
84927 
84928 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ6. */
84929 typedef volatile struct ALT_USB_DEV_DIEPTSIZ6_s ALT_USB_DEV_DIEPTSIZ6_t;
84930 #endif /* __ASSEMBLY__ */
84931 
84932 /* The reset value of the ALT_USB_DEV_DIEPTSIZ6 register. */
84933 #define ALT_USB_DEV_DIEPTSIZ6_RESET 0x00000000
84934 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ6 register from the beginning of the component. */
84935 #define ALT_USB_DEV_DIEPTSIZ6_OFST 0x1d0
84936 /* The address of the ALT_USB_DEV_DIEPTSIZ6 register. */
84937 #define ALT_USB_DEV_DIEPTSIZ6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ6_OFST))
84938 
84939 /*
84940  * Register : diepdma6
84941  *
84942  * Device IN Endpoint 6 DMA Address Register
84943  *
84944  * Register Layout
84945  *
84946  * Bits | Access | Reset | Description
84947  * :-------|:-------|:--------|:------------------------------
84948  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA6_DIEPDMA6
84949  *
84950  */
84951 /*
84952  * Field : diepdma6
84953  *
84954  * Holds the start address of the external memory for storing or fetching endpoint
84955  *
84956  * data.
84957  *
84958  * Note: For control endpoints, this field stores control OUT data packets as well
84959  * as
84960  *
84961  * SETUP transaction data packets. When more than three SETUP packets are
84962  *
84963  * received back-to-back, the SETUP data packet in the memory is overwritten.
84964  *
84965  * This register is incremented on every AHB transaction. The application can give
84966  *
84967  * only a DWORD-aligned address.
84968  *
84969  * When Scatter/Gather DMA mode is not enabled, the application programs the
84970  *
84971  * start address value in this field.
84972  *
84973  * When Scatter/Gather DMA mode is enabled, this field indicates the base
84974  *
84975  * pointer for the descriptor list.
84976  *
84977  * Field Access Macros:
84978  *
84979  */
84980 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field. */
84981 #define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_LSB 0
84982 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field. */
84983 #define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_MSB 31
84984 /* The width in bits of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field. */
84985 #define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_WIDTH 32
84986 /* The mask used to set the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field value. */
84987 #define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_SET_MSK 0xffffffff
84988 /* The mask used to clear the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field value. */
84989 #define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_CLR_MSK 0x00000000
84990 /* The reset value of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field is UNKNOWN. */
84991 #define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_RESET 0x0
84992 /* Extracts the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 field value from a register. */
84993 #define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_GET(value) (((value) & 0xffffffff) >> 0)
84994 /* Produces a ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field value suitable for setting the register. */
84995 #define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_SET(value) (((value) << 0) & 0xffffffff)
84996 
84997 #ifndef __ASSEMBLY__
84998 /*
84999  * WARNING: The C register and register group struct declarations are provided for
85000  * convenience and illustrative purposes. They should, however, be used with
85001  * caution as the C language standard provides no guarantees about the alignment or
85002  * atomicity of device memory accesses. The recommended practice for writing
85003  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
85004  * alt_write_word() functions.
85005  *
85006  * The struct declaration for register ALT_USB_DEV_DIEPDMA6.
85007  */
85008 struct ALT_USB_DEV_DIEPDMA6_s
85009 {
85010  uint32_t diepdma6 : 32; /* ALT_USB_DEV_DIEPDMA6_DIEPDMA6 */
85011 };
85012 
85013 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA6. */
85014 typedef volatile struct ALT_USB_DEV_DIEPDMA6_s ALT_USB_DEV_DIEPDMA6_t;
85015 #endif /* __ASSEMBLY__ */
85016 
85017 /* The reset value of the ALT_USB_DEV_DIEPDMA6 register. */
85018 #define ALT_USB_DEV_DIEPDMA6_RESET 0x00000000
85019 /* The byte offset of the ALT_USB_DEV_DIEPDMA6 register from the beginning of the component. */
85020 #define ALT_USB_DEV_DIEPDMA6_OFST 0x1d4
85021 /* The address of the ALT_USB_DEV_DIEPDMA6 register. */
85022 #define ALT_USB_DEV_DIEPDMA6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA6_OFST))
85023 
85024 /*
85025  * Register : dtxfsts6
85026  *
85027  * Device IN Endpoint Transmit FIFO Status Register 6
85028  *
85029  * Register Layout
85030  *
85031  * Bits | Access | Reset | Description
85032  * :--------|:-------|:-------|:-------------------------------------
85033  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL
85034  * [31:16] | ??? | 0x0 | *UNDEFINED*
85035  *
85036  */
85037 /*
85038  * Field : ineptxfspcavail
85039  *
85040  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
85041  *
85042  * Indicates the amount of free space available in the Endpoint
85043  *
85044  * TxFIFO.
85045  *
85046  * Values are in terms of 32-bit words.
85047  *
85048  * 16'h0: Endpoint TxFIFO is full
85049  *
85050  * 16'h1: 1 word available
85051  *
85052  * 16'h2: 2 words available
85053  *
85054  * 16'hn: n words available (where 0 n 32,768)
85055  *
85056  * 16'h8000: 32,768 words available
85057  *
85058  * Others: Reserved
85059  *
85060  * Field Access Macros:
85061  *
85062  */
85063 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */
85064 #define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_LSB 0
85065 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */
85066 #define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_MSB 15
85067 /* The width in bits of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */
85068 #define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_WIDTH 16
85069 /* The mask used to set the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field value. */
85070 #define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
85071 /* The mask used to clear the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field value. */
85072 #define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
85073 /* The reset value of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */
85074 #define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_RESET 0x2000
85075 /* Extracts the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL field value from a register. */
85076 #define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
85077 /* Produces a ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field value suitable for setting the register. */
85078 #define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
85079 
85080 #ifndef __ASSEMBLY__
85081 /*
85082  * WARNING: The C register and register group struct declarations are provided for
85083  * convenience and illustrative purposes. They should, however, be used with
85084  * caution as the C language standard provides no guarantees about the alignment or
85085  * atomicity of device memory accesses. The recommended practice for writing
85086  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
85087  * alt_write_word() functions.
85088  *
85089  * The struct declaration for register ALT_USB_DEV_DTXFSTS6.
85090  */
85091 struct ALT_USB_DEV_DTXFSTS6_s
85092 {
85093  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL */
85094  uint32_t : 16; /* *UNDEFINED* */
85095 };
85096 
85097 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS6. */
85098 typedef volatile struct ALT_USB_DEV_DTXFSTS6_s ALT_USB_DEV_DTXFSTS6_t;
85099 #endif /* __ASSEMBLY__ */
85100 
85101 /* The reset value of the ALT_USB_DEV_DTXFSTS6 register. */
85102 #define ALT_USB_DEV_DTXFSTS6_RESET 0x00002000
85103 /* The byte offset of the ALT_USB_DEV_DTXFSTS6 register from the beginning of the component. */
85104 #define ALT_USB_DEV_DTXFSTS6_OFST 0x1d8
85105 /* The address of the ALT_USB_DEV_DTXFSTS6 register. */
85106 #define ALT_USB_DEV_DTXFSTS6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS6_OFST))
85107 
85108 /*
85109  * Register : diepdmab6
85110  *
85111  * Device IN Endpoint 6 Buffer Address Register
85112  *
85113  * Register Layout
85114  *
85115  * Bits | Access | Reset | Description
85116  * :-------|:-------|:--------|:--------------------------------
85117  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6
85118  *
85119  */
85120 /*
85121  * Field : diepdmab6
85122  *
85123  * Holds the current buffer address.This register is updated as and when the data
85124  *
85125  * transfer for the corresponding end point is in progress.
85126  *
85127  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
85128  * is
85129  *
85130  * reserved.
85131  *
85132  * Field Access Macros:
85133  *
85134  */
85135 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field. */
85136 #define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_LSB 0
85137 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field. */
85138 #define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_MSB 31
85139 /* The width in bits of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field. */
85140 #define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_WIDTH 32
85141 /* The mask used to set the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field value. */
85142 #define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_SET_MSK 0xffffffff
85143 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field value. */
85144 #define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_CLR_MSK 0x00000000
85145 /* The reset value of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field is UNKNOWN. */
85146 #define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_RESET 0x0
85147 /* Extracts the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 field value from a register. */
85148 #define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_GET(value) (((value) & 0xffffffff) >> 0)
85149 /* Produces a ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field value suitable for setting the register. */
85150 #define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_SET(value) (((value) << 0) & 0xffffffff)
85151 
85152 #ifndef __ASSEMBLY__
85153 /*
85154  * WARNING: The C register and register group struct declarations are provided for
85155  * convenience and illustrative purposes. They should, however, be used with
85156  * caution as the C language standard provides no guarantees about the alignment or
85157  * atomicity of device memory accesses. The recommended practice for writing
85158  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
85159  * alt_write_word() functions.
85160  *
85161  * The struct declaration for register ALT_USB_DEV_DIEPDMAB6.
85162  */
85163 struct ALT_USB_DEV_DIEPDMAB6_s
85164 {
85165  const uint32_t diepdmab6 : 32; /* ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 */
85166 };
85167 
85168 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB6. */
85169 typedef volatile struct ALT_USB_DEV_DIEPDMAB6_s ALT_USB_DEV_DIEPDMAB6_t;
85170 #endif /* __ASSEMBLY__ */
85171 
85172 /* The reset value of the ALT_USB_DEV_DIEPDMAB6 register. */
85173 #define ALT_USB_DEV_DIEPDMAB6_RESET 0x00000000
85174 /* The byte offset of the ALT_USB_DEV_DIEPDMAB6 register from the beginning of the component. */
85175 #define ALT_USB_DEV_DIEPDMAB6_OFST 0x1dc
85176 /* The address of the ALT_USB_DEV_DIEPDMAB6 register. */
85177 #define ALT_USB_DEV_DIEPDMAB6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB6_OFST))
85178 
85179 /*
85180  * Register : diepctl7
85181  *
85182  * Device Control IN Endpoint 7 Control Register
85183  *
85184  * Register Layout
85185  *
85186  * Bits | Access | Reset | Description
85187  * :--------|:---------|:------|:------------------------------
85188  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL7_MPS
85189  * [14:11] | ??? | 0x0 | *UNDEFINED*
85190  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL7_USBACTEP
85191  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL7_DPID
85192  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL7_NAKSTS
85193  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL7_EPTYPE
85194  * [20] | ??? | 0x0 | *UNDEFINED*
85195  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL7_STALL
85196  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL7_TXFNUM
85197  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL7_CNAK
85198  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL7_SNAK
85199  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL7_SETD0PID
85200  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL7_SETD1PID
85201  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL7_EPDIS
85202  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL7_EPENA
85203  *
85204  */
85205 /*
85206  * Field : mps
85207  *
85208  * Maximum Packet Size (MPS)
85209  *
85210  * The application must program this field with the maximum packet size for the
85211  * current
85212  *
85213  * logical endpoint. This value is in bytes.
85214  *
85215  * Field Access Macros:
85216  *
85217  */
85218 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_MPS register field. */
85219 #define ALT_USB_DEV_DIEPCTL7_MPS_LSB 0
85220 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_MPS register field. */
85221 #define ALT_USB_DEV_DIEPCTL7_MPS_MSB 10
85222 /* The width in bits of the ALT_USB_DEV_DIEPCTL7_MPS register field. */
85223 #define ALT_USB_DEV_DIEPCTL7_MPS_WIDTH 11
85224 /* The mask used to set the ALT_USB_DEV_DIEPCTL7_MPS register field value. */
85225 #define ALT_USB_DEV_DIEPCTL7_MPS_SET_MSK 0x000007ff
85226 /* The mask used to clear the ALT_USB_DEV_DIEPCTL7_MPS register field value. */
85227 #define ALT_USB_DEV_DIEPCTL7_MPS_CLR_MSK 0xfffff800
85228 /* The reset value of the ALT_USB_DEV_DIEPCTL7_MPS register field. */
85229 #define ALT_USB_DEV_DIEPCTL7_MPS_RESET 0x0
85230 /* Extracts the ALT_USB_DEV_DIEPCTL7_MPS field value from a register. */
85231 #define ALT_USB_DEV_DIEPCTL7_MPS_GET(value) (((value) & 0x000007ff) >> 0)
85232 /* Produces a ALT_USB_DEV_DIEPCTL7_MPS register field value suitable for setting the register. */
85233 #define ALT_USB_DEV_DIEPCTL7_MPS_SET(value) (((value) << 0) & 0x000007ff)
85234 
85235 /*
85236  * Field : usbactep
85237  *
85238  * USB Active Endpoint (USBActEP)
85239  *
85240  * Indicates whether this endpoint is active in the current configuration and
85241  * interface. The
85242  *
85243  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
85244  * reset. After
85245  *
85246  * receiving the SetConfiguration and SetInterface commands, the application must
85247  *
85248  * program endpoint registers accordingly and set this bit.
85249  *
85250  * Field Enumeration Values:
85251  *
85252  * Enum | Value | Description
85253  * :-------------------------------------|:------|:--------------------
85254  * ALT_USB_DEV_DIEPCTL7_USBACTEP_E_DISD | 0x0 | Not Active
85255  * ALT_USB_DEV_DIEPCTL7_USBACTEP_E_END | 0x1 | USB Active Endpoint
85256  *
85257  * Field Access Macros:
85258  *
85259  */
85260 /*
85261  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_USBACTEP
85262  *
85263  * Not Active
85264  */
85265 #define ALT_USB_DEV_DIEPCTL7_USBACTEP_E_DISD 0x0
85266 /*
85267  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_USBACTEP
85268  *
85269  * USB Active Endpoint
85270  */
85271 #define ALT_USB_DEV_DIEPCTL7_USBACTEP_E_END 0x1
85272 
85273 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */
85274 #define ALT_USB_DEV_DIEPCTL7_USBACTEP_LSB 15
85275 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */
85276 #define ALT_USB_DEV_DIEPCTL7_USBACTEP_MSB 15
85277 /* The width in bits of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */
85278 #define ALT_USB_DEV_DIEPCTL7_USBACTEP_WIDTH 1
85279 /* The mask used to set the ALT_USB_DEV_DIEPCTL7_USBACTEP register field value. */
85280 #define ALT_USB_DEV_DIEPCTL7_USBACTEP_SET_MSK 0x00008000
85281 /* The mask used to clear the ALT_USB_DEV_DIEPCTL7_USBACTEP register field value. */
85282 #define ALT_USB_DEV_DIEPCTL7_USBACTEP_CLR_MSK 0xffff7fff
85283 /* The reset value of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */
85284 #define ALT_USB_DEV_DIEPCTL7_USBACTEP_RESET 0x0
85285 /* Extracts the ALT_USB_DEV_DIEPCTL7_USBACTEP field value from a register. */
85286 #define ALT_USB_DEV_DIEPCTL7_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
85287 /* Produces a ALT_USB_DEV_DIEPCTL7_USBACTEP register field value suitable for setting the register. */
85288 #define ALT_USB_DEV_DIEPCTL7_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
85289 
85290 /*
85291  * Field : dpid
85292  *
85293  * Endpoint Data PID (DPID)
85294  *
85295  * Applies to interrupt/bulk IN and OUT endpoints only.
85296  *
85297  * Contains the PID of the packet to be received or transmitted on this endpoint.
85298  * The
85299  *
85300  * application must program the PID of the first packet to be received or
85301  * transmitted on
85302  *
85303  * this endpoint, after the endpoint is activated. The applications use the
85304  * SetD1PID and
85305  *
85306  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
85307  *
85308  * 1'b0: DATA0
85309  *
85310  * 1'b1: DATA1
85311  *
85312  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
85313  *
85314  * DMA mode.
85315  *
85316  * 1'b0 RO
85317  *
85318  * Even/Odd (Micro)Frame (EO_FrNum)
85319  *
85320  * In non-Scatter/Gather DMA mode:
85321  *
85322  * Applies to isochronous IN and OUT endpoints only.
85323  *
85324  * Indicates the (micro)frame number in which the core transmits/receives
85325  * isochronous
85326  *
85327  * data for this endpoint. The application must program the even/odd (micro) frame
85328  *
85329  * number in which it intends to transmit/receive isochronous data for this
85330  * endpoint using
85331  *
85332  * the SetEvnFr and SetOddFr fields in this register.
85333  *
85334  * 1'b0: Even (micro)frame
85335  *
85336  * 1'b1: Odd (micro)frame
85337  *
85338  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
85339  * number
85340  *
85341  * in which to send data is provided in the transmit descriptor structure. The
85342  * frame in
85343  *
85344  * which data is received is updated in receive descriptor structure.
85345  *
85346  * Field Enumeration Values:
85347  *
85348  * Enum | Value | Description
85349  * :----------------------------------|:------|:-----------------------------
85350  * ALT_USB_DEV_DIEPCTL7_DPID_E_INACT | 0x0 | Endpoint Data PID not active
85351  * ALT_USB_DEV_DIEPCTL7_DPID_E_ACT | 0x1 | Endpoint Data PID active
85352  *
85353  * Field Access Macros:
85354  *
85355  */
85356 /*
85357  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_DPID
85358  *
85359  * Endpoint Data PID not active
85360  */
85361 #define ALT_USB_DEV_DIEPCTL7_DPID_E_INACT 0x0
85362 /*
85363  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_DPID
85364  *
85365  * Endpoint Data PID active
85366  */
85367 #define ALT_USB_DEV_DIEPCTL7_DPID_E_ACT 0x1
85368 
85369 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_DPID register field. */
85370 #define ALT_USB_DEV_DIEPCTL7_DPID_LSB 16
85371 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_DPID register field. */
85372 #define ALT_USB_DEV_DIEPCTL7_DPID_MSB 16
85373 /* The width in bits of the ALT_USB_DEV_DIEPCTL7_DPID register field. */
85374 #define ALT_USB_DEV_DIEPCTL7_DPID_WIDTH 1
85375 /* The mask used to set the ALT_USB_DEV_DIEPCTL7_DPID register field value. */
85376 #define ALT_USB_DEV_DIEPCTL7_DPID_SET_MSK 0x00010000
85377 /* The mask used to clear the ALT_USB_DEV_DIEPCTL7_DPID register field value. */
85378 #define ALT_USB_DEV_DIEPCTL7_DPID_CLR_MSK 0xfffeffff
85379 /* The reset value of the ALT_USB_DEV_DIEPCTL7_DPID register field. */
85380 #define ALT_USB_DEV_DIEPCTL7_DPID_RESET 0x0
85381 /* Extracts the ALT_USB_DEV_DIEPCTL7_DPID field value from a register. */
85382 #define ALT_USB_DEV_DIEPCTL7_DPID_GET(value) (((value) & 0x00010000) >> 16)
85383 /* Produces a ALT_USB_DEV_DIEPCTL7_DPID register field value suitable for setting the register. */
85384 #define ALT_USB_DEV_DIEPCTL7_DPID_SET(value) (((value) << 16) & 0x00010000)
85385 
85386 /*
85387  * Field : naksts
85388  *
85389  * NAK Status (NAKSts)
85390  *
85391  * Indicates the following:
85392  *
85393  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
85394  *
85395  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
85396  *
85397  * When either the application or the core sets this bit:
85398  *
85399  * The core stops receiving any data on an OUT endpoint, even if there is space in
85400  *
85401  * the RxFIFO to accommodate the incoming packet.
85402  *
85403  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
85404  *
85405  * endpoint, even if there data is available in the TxFIFO.
85406  *
85407  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
85408  *
85409  * if there data is available in the TxFIFO.
85410  *
85411  * Irrespective of this bit's setting, the core always responds to SETUP data
85412  * packets with
85413  *
85414  * an ACK handshake.
85415  *
85416  * Field Enumeration Values:
85417  *
85418  * Enum | Value | Description
85419  * :-------------------------------------|:------|:------------------------------------------------
85420  * ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
85421  * : | | based on the FIFO status
85422  * ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
85423  * : | | endpoint
85424  *
85425  * Field Access Macros:
85426  *
85427  */
85428 /*
85429  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_NAKSTS
85430  *
85431  * The core is transmitting non-NAK handshakes based on the FIFO status
85432  */
85433 #define ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NONNAK 0x0
85434 /*
85435  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_NAKSTS
85436  *
85437  * The core is transmitting NAK handshakes on this endpoint
85438  */
85439 #define ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NAK 0x1
85440 
85441 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */
85442 #define ALT_USB_DEV_DIEPCTL7_NAKSTS_LSB 17
85443 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */
85444 #define ALT_USB_DEV_DIEPCTL7_NAKSTS_MSB 17
85445 /* The width in bits of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */
85446 #define ALT_USB_DEV_DIEPCTL7_NAKSTS_WIDTH 1
85447 /* The mask used to set the ALT_USB_DEV_DIEPCTL7_NAKSTS register field value. */
85448 #define ALT_USB_DEV_DIEPCTL7_NAKSTS_SET_MSK 0x00020000
85449 /* The mask used to clear the ALT_USB_DEV_DIEPCTL7_NAKSTS register field value. */
85450 #define ALT_USB_DEV_DIEPCTL7_NAKSTS_CLR_MSK 0xfffdffff
85451 /* The reset value of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */
85452 #define ALT_USB_DEV_DIEPCTL7_NAKSTS_RESET 0x0
85453 /* Extracts the ALT_USB_DEV_DIEPCTL7_NAKSTS field value from a register. */
85454 #define ALT_USB_DEV_DIEPCTL7_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
85455 /* Produces a ALT_USB_DEV_DIEPCTL7_NAKSTS register field value suitable for setting the register. */
85456 #define ALT_USB_DEV_DIEPCTL7_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
85457 
85458 /*
85459  * Field : eptype
85460  *
85461  * Endpoint Type (EPType)
85462  *
85463  * This is the transfer type supported by this logical endpoint.
85464  *
85465  * 2'b00: Control
85466  *
85467  * 2'b01: Isochronous
85468  *
85469  * 2'b10: Bulk
85470  *
85471  * 2'b11: Interrupt
85472  *
85473  * Field Enumeration Values:
85474  *
85475  * Enum | Value | Description
85476  * :------------------------------------------|:------|:------------
85477  * ALT_USB_DEV_DIEPCTL7_EPTYPE_E_CTL | 0x0 | Control
85478  * ALT_USB_DEV_DIEPCTL7_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
85479  * ALT_USB_DEV_DIEPCTL7_EPTYPE_E_BULK | 0x2 | Bulk
85480  * ALT_USB_DEV_DIEPCTL7_EPTYPE_E_INTERRUP | 0x3 | Interrupt
85481  *
85482  * Field Access Macros:
85483  *
85484  */
85485 /*
85486  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE
85487  *
85488  * Control
85489  */
85490 #define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_CTL 0x0
85491 /*
85492  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE
85493  *
85494  * Isochronous
85495  */
85496 #define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_ISOCHRONOUS 0x1
85497 /*
85498  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE
85499  *
85500  * Bulk
85501  */
85502 #define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_BULK 0x2
85503 /*
85504  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE
85505  *
85506  * Interrupt
85507  */
85508 #define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_INTERRUP 0x3
85509 
85510 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */
85511 #define ALT_USB_DEV_DIEPCTL7_EPTYPE_LSB 18
85512 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */
85513 #define ALT_USB_DEV_DIEPCTL7_EPTYPE_MSB 19
85514 /* The width in bits of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */
85515 #define ALT_USB_DEV_DIEPCTL7_EPTYPE_WIDTH 2
85516 /* The mask used to set the ALT_USB_DEV_DIEPCTL7_EPTYPE register field value. */
85517 #define ALT_USB_DEV_DIEPCTL7_EPTYPE_SET_MSK 0x000c0000
85518 /* The mask used to clear the ALT_USB_DEV_DIEPCTL7_EPTYPE register field value. */
85519 #define ALT_USB_DEV_DIEPCTL7_EPTYPE_CLR_MSK 0xfff3ffff
85520 /* The reset value of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */
85521 #define ALT_USB_DEV_DIEPCTL7_EPTYPE_RESET 0x0
85522 /* Extracts the ALT_USB_DEV_DIEPCTL7_EPTYPE field value from a register. */
85523 #define ALT_USB_DEV_DIEPCTL7_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
85524 /* Produces a ALT_USB_DEV_DIEPCTL7_EPTYPE register field value suitable for setting the register. */
85525 #define ALT_USB_DEV_DIEPCTL7_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
85526 
85527 /*
85528  * Field : stall
85529  *
85530  * STALL Handshake (Stall)
85531  *
85532  * Applies to non-control, non-isochronous IN and OUT endpoints only.
85533  *
85534  * The application sets this bit to stall all tokens from the USB host to this
85535  * endpoint. If a
85536  *
85537  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
85538  * bit, the
85539  *
85540  * STALL bit takes priority. Only the application can clear this bit, never the
85541  * core.
85542  *
85543  * 1'b0 R_W
85544  *
85545  * Applies to control endpoints only.
85546  *
85547  * The application can only set this bit, and the core clears it, when a SETUP
85548  * token is
85549  *
85550  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
85551  * OUT
85552  *
85553  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
85554  * this bit's
85555  *
85556  * setting, the core always responds to SETUP data packets with an ACK handshake.
85557  *
85558  * Field Enumeration Values:
85559  *
85560  * Enum | Value | Description
85561  * :-----------------------------------|:------|:----------------------------
85562  * ALT_USB_DEV_DIEPCTL7_STALL_E_INACT | 0x0 | STALL All Tokens not active
85563  * ALT_USB_DEV_DIEPCTL7_STALL_E_ACT | 0x1 | STALL All Tokens active
85564  *
85565  * Field Access Macros:
85566  *
85567  */
85568 /*
85569  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_STALL
85570  *
85571  * STALL All Tokens not active
85572  */
85573 #define ALT_USB_DEV_DIEPCTL7_STALL_E_INACT 0x0
85574 /*
85575  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_STALL
85576  *
85577  * STALL All Tokens active
85578  */
85579 #define ALT_USB_DEV_DIEPCTL7_STALL_E_ACT 0x1
85580 
85581 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_STALL register field. */
85582 #define ALT_USB_DEV_DIEPCTL7_STALL_LSB 21
85583 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_STALL register field. */
85584 #define ALT_USB_DEV_DIEPCTL7_STALL_MSB 21
85585 /* The width in bits of the ALT_USB_DEV_DIEPCTL7_STALL register field. */
85586 #define ALT_USB_DEV_DIEPCTL7_STALL_WIDTH 1
85587 /* The mask used to set the ALT_USB_DEV_DIEPCTL7_STALL register field value. */
85588 #define ALT_USB_DEV_DIEPCTL7_STALL_SET_MSK 0x00200000
85589 /* The mask used to clear the ALT_USB_DEV_DIEPCTL7_STALL register field value. */
85590 #define ALT_USB_DEV_DIEPCTL7_STALL_CLR_MSK 0xffdfffff
85591 /* The reset value of the ALT_USB_DEV_DIEPCTL7_STALL register field. */
85592 #define ALT_USB_DEV_DIEPCTL7_STALL_RESET 0x0
85593 /* Extracts the ALT_USB_DEV_DIEPCTL7_STALL field value from a register. */
85594 #define ALT_USB_DEV_DIEPCTL7_STALL_GET(value) (((value) & 0x00200000) >> 21)
85595 /* Produces a ALT_USB_DEV_DIEPCTL7_STALL register field value suitable for setting the register. */
85596 #define ALT_USB_DEV_DIEPCTL7_STALL_SET(value) (((value) << 21) & 0x00200000)
85597 
85598 /*
85599  * Field : txfnum
85600  *
85601  * TxFIFO Number (TxFNum)
85602  *
85603  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
85604  *
85605  * endpoints must map this to the corresponding Periodic TxFIFO number.
85606  *
85607  * 4'h0: Non-Periodic TxFIFO
85608  *
85609  * Others: Specified Periodic TxFIFO.number
85610  *
85611  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
85612  *
85613  * applications such as mass storage. The core treats an IN endpoint as a non-
85614  * periodic
85615  *
85616  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
85617  * must be
85618  *
85619  * allocated for an interrupt IN endpoint, and the number of this
85620  *
85621  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
85622  *
85623  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
85624  *
85625  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
85626  *
85627  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
85628  *
85629  * This field is valid only for IN endpoints.
85630  *
85631  * Field Access Macros:
85632  *
85633  */
85634 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */
85635 #define ALT_USB_DEV_DIEPCTL7_TXFNUM_LSB 22
85636 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */
85637 #define ALT_USB_DEV_DIEPCTL7_TXFNUM_MSB 25
85638 /* The width in bits of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */
85639 #define ALT_USB_DEV_DIEPCTL7_TXFNUM_WIDTH 4
85640 /* The mask used to set the ALT_USB_DEV_DIEPCTL7_TXFNUM register field value. */
85641 #define ALT_USB_DEV_DIEPCTL7_TXFNUM_SET_MSK 0x03c00000
85642 /* The mask used to clear the ALT_USB_DEV_DIEPCTL7_TXFNUM register field value. */
85643 #define ALT_USB_DEV_DIEPCTL7_TXFNUM_CLR_MSK 0xfc3fffff
85644 /* The reset value of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */
85645 #define ALT_USB_DEV_DIEPCTL7_TXFNUM_RESET 0x0
85646 /* Extracts the ALT_USB_DEV_DIEPCTL7_TXFNUM field value from a register. */
85647 #define ALT_USB_DEV_DIEPCTL7_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
85648 /* Produces a ALT_USB_DEV_DIEPCTL7_TXFNUM register field value suitable for setting the register. */
85649 #define ALT_USB_DEV_DIEPCTL7_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
85650 
85651 /*
85652  * Field : cnak
85653  *
85654  * Clear NAK (CNAK)
85655  *
85656  * A write to this bit clears the NAK bit For the endpoint.
85657  *
85658  * Field Enumeration Values:
85659  *
85660  * Enum | Value | Description
85661  * :----------------------------------|:------|:-------------
85662  * ALT_USB_DEV_DIEPCTL7_CNAK_E_INACT | 0x0 | No Clear NAK
85663  * ALT_USB_DEV_DIEPCTL7_CNAK_E_ACT | 0x1 | Clear NAK
85664  *
85665  * Field Access Macros:
85666  *
85667  */
85668 /*
85669  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_CNAK
85670  *
85671  * No Clear NAK
85672  */
85673 #define ALT_USB_DEV_DIEPCTL7_CNAK_E_INACT 0x0
85674 /*
85675  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_CNAK
85676  *
85677  * Clear NAK
85678  */
85679 #define ALT_USB_DEV_DIEPCTL7_CNAK_E_ACT 0x1
85680 
85681 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */
85682 #define ALT_USB_DEV_DIEPCTL7_CNAK_LSB 26
85683 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */
85684 #define ALT_USB_DEV_DIEPCTL7_CNAK_MSB 26
85685 /* The width in bits of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */
85686 #define ALT_USB_DEV_DIEPCTL7_CNAK_WIDTH 1
85687 /* The mask used to set the ALT_USB_DEV_DIEPCTL7_CNAK register field value. */
85688 #define ALT_USB_DEV_DIEPCTL7_CNAK_SET_MSK 0x04000000
85689 /* The mask used to clear the ALT_USB_DEV_DIEPCTL7_CNAK register field value. */
85690 #define ALT_USB_DEV_DIEPCTL7_CNAK_CLR_MSK 0xfbffffff
85691 /* The reset value of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */
85692 #define ALT_USB_DEV_DIEPCTL7_CNAK_RESET 0x0
85693 /* Extracts the ALT_USB_DEV_DIEPCTL7_CNAK field value from a register. */
85694 #define ALT_USB_DEV_DIEPCTL7_CNAK_GET(value) (((value) & 0x04000000) >> 26)
85695 /* Produces a ALT_USB_DEV_DIEPCTL7_CNAK register field value suitable for setting the register. */
85696 #define ALT_USB_DEV_DIEPCTL7_CNAK_SET(value) (((value) << 26) & 0x04000000)
85697 
85698 /*
85699  * Field : snak
85700  *
85701  * Set NAK (SNAK)
85702  *
85703  * A write to this bit sets the NAK bit For the endpoint.
85704  *
85705  * Using this bit, the application can control the transmission of NAK
85706  *
85707  * handshakes on an endpoint. The core can also Set this bit For an
85708  *
85709  * endpoint after a SETUP packet is received on that endpoint.
85710  *
85711  * Field Enumeration Values:
85712  *
85713  * Enum | Value | Description
85714  * :----------------------------------|:------|:------------
85715  * ALT_USB_DEV_DIEPCTL7_SNAK_E_INACT | 0x0 | No Set NAK
85716  * ALT_USB_DEV_DIEPCTL7_SNAK_E_ACT | 0x1 | Set NAK
85717  *
85718  * Field Access Macros:
85719  *
85720  */
85721 /*
85722  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SNAK
85723  *
85724  * No Set NAK
85725  */
85726 #define ALT_USB_DEV_DIEPCTL7_SNAK_E_INACT 0x0
85727 /*
85728  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SNAK
85729  *
85730  * Set NAK
85731  */
85732 #define ALT_USB_DEV_DIEPCTL7_SNAK_E_ACT 0x1
85733 
85734 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */
85735 #define ALT_USB_DEV_DIEPCTL7_SNAK_LSB 27
85736 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */
85737 #define ALT_USB_DEV_DIEPCTL7_SNAK_MSB 27
85738 /* The width in bits of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */
85739 #define ALT_USB_DEV_DIEPCTL7_SNAK_WIDTH 1
85740 /* The mask used to set the ALT_USB_DEV_DIEPCTL7_SNAK register field value. */
85741 #define ALT_USB_DEV_DIEPCTL7_SNAK_SET_MSK 0x08000000
85742 /* The mask used to clear the ALT_USB_DEV_DIEPCTL7_SNAK register field value. */
85743 #define ALT_USB_DEV_DIEPCTL7_SNAK_CLR_MSK 0xf7ffffff
85744 /* The reset value of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */
85745 #define ALT_USB_DEV_DIEPCTL7_SNAK_RESET 0x0
85746 /* Extracts the ALT_USB_DEV_DIEPCTL7_SNAK field value from a register. */
85747 #define ALT_USB_DEV_DIEPCTL7_SNAK_GET(value) (((value) & 0x08000000) >> 27)
85748 /* Produces a ALT_USB_DEV_DIEPCTL7_SNAK register field value suitable for setting the register. */
85749 #define ALT_USB_DEV_DIEPCTL7_SNAK_SET(value) (((value) << 27) & 0x08000000)
85750 
85751 /*
85752  * Field : setd0pid
85753  *
85754  * Set DATA0 PID (SetD0PID)
85755  *
85756  * Applies to interrupt/bulk IN and OUT endpoints only.
85757  *
85758  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
85759  * to DATA0.
85760  *
85761  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
85762  *
85763  * DMA mode.
85764  *
85765  * 1'b0 WO
85766  *
85767  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
85768  *
85769  * Applies to isochronous IN and OUT endpoints only.
85770  *
85771  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
85772  * (micro)
85773  *
85774  * frame.
85775  *
85776  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
85777  * number
85778  *
85779  * in which to send data is in the transmit descriptor structure. The frame in
85780  * which to
85781  *
85782  * receive data is updated in receive descriptor structure.
85783  *
85784  * Field Enumeration Values:
85785  *
85786  * Enum | Value | Description
85787  * :-------------------------------------|:------|:----------------------------
85788  * ALT_USB_DEV_DIEPCTL7_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
85789  * ALT_USB_DEV_DIEPCTL7_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
85790  *
85791  * Field Access Macros:
85792  *
85793  */
85794 /*
85795  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD0PID
85796  *
85797  * Disables Set DATA0 PID
85798  */
85799 #define ALT_USB_DEV_DIEPCTL7_SETD0PID_E_DISD 0x0
85800 /*
85801  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD0PID
85802  *
85803  * Endpoint Data PID to DATA0)
85804  */
85805 #define ALT_USB_DEV_DIEPCTL7_SETD0PID_E_END 0x1
85806 
85807 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */
85808 #define ALT_USB_DEV_DIEPCTL7_SETD0PID_LSB 28
85809 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */
85810 #define ALT_USB_DEV_DIEPCTL7_SETD0PID_MSB 28
85811 /* The width in bits of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */
85812 #define ALT_USB_DEV_DIEPCTL7_SETD0PID_WIDTH 1
85813 /* The mask used to set the ALT_USB_DEV_DIEPCTL7_SETD0PID register field value. */
85814 #define ALT_USB_DEV_DIEPCTL7_SETD0PID_SET_MSK 0x10000000
85815 /* The mask used to clear the ALT_USB_DEV_DIEPCTL7_SETD0PID register field value. */
85816 #define ALT_USB_DEV_DIEPCTL7_SETD0PID_CLR_MSK 0xefffffff
85817 /* The reset value of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */
85818 #define ALT_USB_DEV_DIEPCTL7_SETD0PID_RESET 0x0
85819 /* Extracts the ALT_USB_DEV_DIEPCTL7_SETD0PID field value from a register. */
85820 #define ALT_USB_DEV_DIEPCTL7_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
85821 /* Produces a ALT_USB_DEV_DIEPCTL7_SETD0PID register field value suitable for setting the register. */
85822 #define ALT_USB_DEV_DIEPCTL7_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
85823 
85824 /*
85825  * Field : setd1pid
85826  *
85827  * Set DATA1 PID (SetD1PID)
85828  *
85829  * Applies to interrupt/bulk IN and OUT endpoints only.
85830  *
85831  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
85832  * to DATA1.
85833  *
85834  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
85835  *
85836  * DMA mode.
85837  *
85838  * Set Odd (micro)frame (SetOddFr)
85839  *
85840  * Applies to isochronous IN and OUT endpoints only.
85841  *
85842  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
85843  *
85844  * (micro)frame.
85845  *
85846  * This field is not applicable for Scatter/Gather DMA mode.
85847  *
85848  * Field Enumeration Values:
85849  *
85850  * Enum | Value | Description
85851  * :-------------------------------------|:------|:-----------------------
85852  * ALT_USB_DEV_DIEPCTL7_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
85853  * ALT_USB_DEV_DIEPCTL7_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
85854  *
85855  * Field Access Macros:
85856  *
85857  */
85858 /*
85859  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD1PID
85860  *
85861  * Disables Set DATA1 PID
85862  */
85863 #define ALT_USB_DEV_DIEPCTL7_SETD1PID_E_DISD 0x0
85864 /*
85865  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD1PID
85866  *
85867  * Enables Set DATA1 PID
85868  */
85869 #define ALT_USB_DEV_DIEPCTL7_SETD1PID_E_END 0x1
85870 
85871 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */
85872 #define ALT_USB_DEV_DIEPCTL7_SETD1PID_LSB 29
85873 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */
85874 #define ALT_USB_DEV_DIEPCTL7_SETD1PID_MSB 29
85875 /* The width in bits of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */
85876 #define ALT_USB_DEV_DIEPCTL7_SETD1PID_WIDTH 1
85877 /* The mask used to set the ALT_USB_DEV_DIEPCTL7_SETD1PID register field value. */
85878 #define ALT_USB_DEV_DIEPCTL7_SETD1PID_SET_MSK 0x20000000
85879 /* The mask used to clear the ALT_USB_DEV_DIEPCTL7_SETD1PID register field value. */
85880 #define ALT_USB_DEV_DIEPCTL7_SETD1PID_CLR_MSK 0xdfffffff
85881 /* The reset value of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */
85882 #define ALT_USB_DEV_DIEPCTL7_SETD1PID_RESET 0x0
85883 /* Extracts the ALT_USB_DEV_DIEPCTL7_SETD1PID field value from a register. */
85884 #define ALT_USB_DEV_DIEPCTL7_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
85885 /* Produces a ALT_USB_DEV_DIEPCTL7_SETD1PID register field value suitable for setting the register. */
85886 #define ALT_USB_DEV_DIEPCTL7_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
85887 
85888 /*
85889  * Field : epdis
85890  *
85891  * Endpoint Disable (EPDis)
85892  *
85893  * Applies to IN and OUT endpoints.
85894  *
85895  * The application sets this bit to stop transmitting/receiving data on an
85896  * endpoint, even
85897  *
85898  * before the transfer for that endpoint is complete. The application must wait for
85899  * the
85900  *
85901  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
85902  * clears
85903  *
85904  * this bit before setting the Endpoint Disabled interrupt. The application must
85905  * set this bit
85906  *
85907  * only if Endpoint Enable is already set for this endpoint.
85908  *
85909  * Field Enumeration Values:
85910  *
85911  * Enum | Value | Description
85912  * :-----------------------------------|:------|:--------------------
85913  * ALT_USB_DEV_DIEPCTL7_EPDIS_E_INACT | 0x0 | No Endpoint Disable
85914  * ALT_USB_DEV_DIEPCTL7_EPDIS_E_ACT | 0x1 | Endpoint Disable
85915  *
85916  * Field Access Macros:
85917  *
85918  */
85919 /*
85920  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPDIS
85921  *
85922  * No Endpoint Disable
85923  */
85924 #define ALT_USB_DEV_DIEPCTL7_EPDIS_E_INACT 0x0
85925 /*
85926  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPDIS
85927  *
85928  * Endpoint Disable
85929  */
85930 #define ALT_USB_DEV_DIEPCTL7_EPDIS_E_ACT 0x1
85931 
85932 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */
85933 #define ALT_USB_DEV_DIEPCTL7_EPDIS_LSB 30
85934 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */
85935 #define ALT_USB_DEV_DIEPCTL7_EPDIS_MSB 30
85936 /* The width in bits of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */
85937 #define ALT_USB_DEV_DIEPCTL7_EPDIS_WIDTH 1
85938 /* The mask used to set the ALT_USB_DEV_DIEPCTL7_EPDIS register field value. */
85939 #define ALT_USB_DEV_DIEPCTL7_EPDIS_SET_MSK 0x40000000
85940 /* The mask used to clear the ALT_USB_DEV_DIEPCTL7_EPDIS register field value. */
85941 #define ALT_USB_DEV_DIEPCTL7_EPDIS_CLR_MSK 0xbfffffff
85942 /* The reset value of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */
85943 #define ALT_USB_DEV_DIEPCTL7_EPDIS_RESET 0x0
85944 /* Extracts the ALT_USB_DEV_DIEPCTL7_EPDIS field value from a register. */
85945 #define ALT_USB_DEV_DIEPCTL7_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
85946 /* Produces a ALT_USB_DEV_DIEPCTL7_EPDIS register field value suitable for setting the register. */
85947 #define ALT_USB_DEV_DIEPCTL7_EPDIS_SET(value) (((value) << 30) & 0x40000000)
85948 
85949 /*
85950  * Field : epena
85951  *
85952  * Endpoint Enable (EPEna)
85953  *
85954  * Applies to IN and OUT endpoints.
85955  *
85956  * When Scatter/Gather DMA mode is enabled,
85957  *
85958  * For IN endpoints this bit indicates that the descriptor structure and data
85959  * buffer with
85960  *
85961  * data ready to transmit is setup.
85962  *
85963  * For OUT endpoint it indicates that the descriptor structure and data buffer to
85964  *
85965  * receive data is setup.
85966  *
85967  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
85968  *
85969  * DMA mode:
85970  *
85971  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
85972  * the
85973  *
85974  * endpoint.
85975  *
85976  * * For OUT endpoints, this bit indicates that the application has allocated the
85977  *
85978  * memory to start receiving data from the USB.
85979  *
85980  * * The core clears this bit before setting any of the following interrupts on
85981  * this
85982  *
85983  * endpoint:
85984  *
85985  * SETUP Phase Done
85986  *
85987  * Endpoint Disabled
85988  *
85989  * Transfer Completed
85990  *
85991  * Note: For control endpoints in DMA mode, this bit must be set to be able to
85992  * transfer
85993  *
85994  * SETUP data packets in memory.
85995  *
85996  * Field Enumeration Values:
85997  *
85998  * Enum | Value | Description
85999  * :-----------------------------------|:------|:-------------------------
86000  * ALT_USB_DEV_DIEPCTL7_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
86001  * ALT_USB_DEV_DIEPCTL7_EPENA_E_ACT | 0x1 | Endpoint Enable active
86002  *
86003  * Field Access Macros:
86004  *
86005  */
86006 /*
86007  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPENA
86008  *
86009  * Endpoint Enable inactive
86010  */
86011 #define ALT_USB_DEV_DIEPCTL7_EPENA_E_INACT 0x0
86012 /*
86013  * Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPENA
86014  *
86015  * Endpoint Enable active
86016  */
86017 #define ALT_USB_DEV_DIEPCTL7_EPENA_E_ACT 0x1
86018 
86019 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */
86020 #define ALT_USB_DEV_DIEPCTL7_EPENA_LSB 31
86021 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */
86022 #define ALT_USB_DEV_DIEPCTL7_EPENA_MSB 31
86023 /* The width in bits of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */
86024 #define ALT_USB_DEV_DIEPCTL7_EPENA_WIDTH 1
86025 /* The mask used to set the ALT_USB_DEV_DIEPCTL7_EPENA register field value. */
86026 #define ALT_USB_DEV_DIEPCTL7_EPENA_SET_MSK 0x80000000
86027 /* The mask used to clear the ALT_USB_DEV_DIEPCTL7_EPENA register field value. */
86028 #define ALT_USB_DEV_DIEPCTL7_EPENA_CLR_MSK 0x7fffffff
86029 /* The reset value of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */
86030 #define ALT_USB_DEV_DIEPCTL7_EPENA_RESET 0x0
86031 /* Extracts the ALT_USB_DEV_DIEPCTL7_EPENA field value from a register. */
86032 #define ALT_USB_DEV_DIEPCTL7_EPENA_GET(value) (((value) & 0x80000000) >> 31)
86033 /* Produces a ALT_USB_DEV_DIEPCTL7_EPENA register field value suitable for setting the register. */
86034 #define ALT_USB_DEV_DIEPCTL7_EPENA_SET(value) (((value) << 31) & 0x80000000)
86035 
86036 #ifndef __ASSEMBLY__
86037 /*
86038  * WARNING: The C register and register group struct declarations are provided for
86039  * convenience and illustrative purposes. They should, however, be used with
86040  * caution as the C language standard provides no guarantees about the alignment or
86041  * atomicity of device memory accesses. The recommended practice for writing
86042  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
86043  * alt_write_word() functions.
86044  *
86045  * The struct declaration for register ALT_USB_DEV_DIEPCTL7.
86046  */
86047 struct ALT_USB_DEV_DIEPCTL7_s
86048 {
86049  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL7_MPS */
86050  uint32_t : 4; /* *UNDEFINED* */
86051  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL7_USBACTEP */
86052  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL7_DPID */
86053  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL7_NAKSTS */
86054  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL7_EPTYPE */
86055  uint32_t : 1; /* *UNDEFINED* */
86056  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL7_STALL */
86057  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL7_TXFNUM */
86058  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL7_CNAK */
86059  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL7_SNAK */
86060  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL7_SETD0PID */
86061  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL7_SETD1PID */
86062  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL7_EPDIS */
86063  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL7_EPENA */
86064 };
86065 
86066 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL7. */
86067 typedef volatile struct ALT_USB_DEV_DIEPCTL7_s ALT_USB_DEV_DIEPCTL7_t;
86068 #endif /* __ASSEMBLY__ */
86069 
86070 /* The reset value of the ALT_USB_DEV_DIEPCTL7 register. */
86071 #define ALT_USB_DEV_DIEPCTL7_RESET 0x00000000
86072 /* The byte offset of the ALT_USB_DEV_DIEPCTL7 register from the beginning of the component. */
86073 #define ALT_USB_DEV_DIEPCTL7_OFST 0x1e0
86074 /* The address of the ALT_USB_DEV_DIEPCTL7 register. */
86075 #define ALT_USB_DEV_DIEPCTL7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL7_OFST))
86076 
86077 /*
86078  * Register : diepint7
86079  *
86080  * Device IN Endpoint 7 Interrupt Register
86081  *
86082  * Register Layout
86083  *
86084  * Bits | Access | Reset | Description
86085  * :--------|:-------|:------|:---------------------------------
86086  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_XFERCOMPL
86087  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_EPDISBLD
86088  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_AHBERR
86089  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_TMO
86090  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_INTKNTXFEMP
86091  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_INTKNEPMIS
86092  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_INEPNAKEFF
86093  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT7_TXFEMP
86094  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN
86095  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_BNAINTR
86096  * [10] | ??? | 0x0 | *UNDEFINED*
86097  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_PKTDRPSTS
86098  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_BBLEERR
86099  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_NAKINTRPT
86100  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_NYETINTRPT
86101  * [31:15] | ??? | 0x0 | *UNDEFINED*
86102  *
86103  */
86104 /*
86105  * Field : xfercompl
86106  *
86107  * Transfer Completed Interrupt (XferCompl)
86108  *
86109  * Applies to IN and OUT endpoints.
86110  *
86111  * When Scatter/Gather DMA mode is enabled
86112  *
86113  * * For IN endpoint this field indicates that the requested data
86114  *
86115  * from the descriptor is moved from external system memory
86116  *
86117  * to internal FIFO.
86118  *
86119  * * For OUT endpoint this field indicates that the requested
86120  *
86121  * data from the internal FIFO is moved to external system
86122  *
86123  * memory. This interrupt is generated only when the
86124  *
86125  * corresponding endpoint descriptor is closed, and the IOC
86126  *
86127  * bit For the corresponding descriptor is Set.
86128  *
86129  * When Scatter/Gather DMA mode is disabled, this field
86130  *
86131  * indicates that the programmed transfer is complete on the
86132  *
86133  * AHB as well as on the USB, For this endpoint.
86134  *
86135  * Field Enumeration Values:
86136  *
86137  * Enum | Value | Description
86138  * :---------------------------------------|:------|:-----------------------------
86139  * ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_INACT | 0x0 | No Interrupt
86140  * ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
86141  *
86142  * Field Access Macros:
86143  *
86144  */
86145 /*
86146  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_XFERCOMPL
86147  *
86148  * No Interrupt
86149  */
86150 #define ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_INACT 0x0
86151 /*
86152  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_XFERCOMPL
86153  *
86154  * Transfer Completed Interrupt
86155  */
86156 #define ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_ACT 0x1
86157 
86158 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */
86159 #define ALT_USB_DEV_DIEPINT7_XFERCOMPL_LSB 0
86160 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */
86161 #define ALT_USB_DEV_DIEPINT7_XFERCOMPL_MSB 0
86162 /* The width in bits of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */
86163 #define ALT_USB_DEV_DIEPINT7_XFERCOMPL_WIDTH 1
86164 /* The mask used to set the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field value. */
86165 #define ALT_USB_DEV_DIEPINT7_XFERCOMPL_SET_MSK 0x00000001
86166 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field value. */
86167 #define ALT_USB_DEV_DIEPINT7_XFERCOMPL_CLR_MSK 0xfffffffe
86168 /* The reset value of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */
86169 #define ALT_USB_DEV_DIEPINT7_XFERCOMPL_RESET 0x0
86170 /* Extracts the ALT_USB_DEV_DIEPINT7_XFERCOMPL field value from a register. */
86171 #define ALT_USB_DEV_DIEPINT7_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
86172 /* Produces a ALT_USB_DEV_DIEPINT7_XFERCOMPL register field value suitable for setting the register. */
86173 #define ALT_USB_DEV_DIEPINT7_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
86174 
86175 /*
86176  * Field : epdisbld
86177  *
86178  * Endpoint Disabled Interrupt (EPDisbld)
86179  *
86180  * Applies to IN and OUT endpoints.
86181  *
86182  * This bit indicates that the endpoint is disabled per the
86183  *
86184  * application's request.
86185  *
86186  * Field Enumeration Values:
86187  *
86188  * Enum | Value | Description
86189  * :--------------------------------------|:------|:----------------------------
86190  * ALT_USB_DEV_DIEPINT7_EPDISBLD_E_INACT | 0x0 | No Interrupt
86191  * ALT_USB_DEV_DIEPINT7_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
86192  *
86193  * Field Access Macros:
86194  *
86195  */
86196 /*
86197  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_EPDISBLD
86198  *
86199  * No Interrupt
86200  */
86201 #define ALT_USB_DEV_DIEPINT7_EPDISBLD_E_INACT 0x0
86202 /*
86203  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_EPDISBLD
86204  *
86205  * Endpoint Disabled Interrupt
86206  */
86207 #define ALT_USB_DEV_DIEPINT7_EPDISBLD_E_ACT 0x1
86208 
86209 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */
86210 #define ALT_USB_DEV_DIEPINT7_EPDISBLD_LSB 1
86211 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */
86212 #define ALT_USB_DEV_DIEPINT7_EPDISBLD_MSB 1
86213 /* The width in bits of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */
86214 #define ALT_USB_DEV_DIEPINT7_EPDISBLD_WIDTH 1
86215 /* The mask used to set the ALT_USB_DEV_DIEPINT7_EPDISBLD register field value. */
86216 #define ALT_USB_DEV_DIEPINT7_EPDISBLD_SET_MSK 0x00000002
86217 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_EPDISBLD register field value. */
86218 #define ALT_USB_DEV_DIEPINT7_EPDISBLD_CLR_MSK 0xfffffffd
86219 /* The reset value of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */
86220 #define ALT_USB_DEV_DIEPINT7_EPDISBLD_RESET 0x0
86221 /* Extracts the ALT_USB_DEV_DIEPINT7_EPDISBLD field value from a register. */
86222 #define ALT_USB_DEV_DIEPINT7_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
86223 /* Produces a ALT_USB_DEV_DIEPINT7_EPDISBLD register field value suitable for setting the register. */
86224 #define ALT_USB_DEV_DIEPINT7_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
86225 
86226 /*
86227  * Field : ahberr
86228  *
86229  * AHB Error (AHBErr)
86230  *
86231  * Applies to IN and OUT endpoints.
86232  *
86233  * This is generated only in Internal DMA mode when there is an
86234  *
86235  * AHB error during an AHB read/write. The application can read
86236  *
86237  * the corresponding endpoint DMA address register to get the
86238  *
86239  * error address.
86240  *
86241  * Field Enumeration Values:
86242  *
86243  * Enum | Value | Description
86244  * :------------------------------------|:------|:--------------------
86245  * ALT_USB_DEV_DIEPINT7_AHBERR_E_INACT | 0x0 | No Interrupt
86246  * ALT_USB_DEV_DIEPINT7_AHBERR_E_ACT | 0x1 | AHB Error interrupt
86247  *
86248  * Field Access Macros:
86249  *
86250  */
86251 /*
86252  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_AHBERR
86253  *
86254  * No Interrupt
86255  */
86256 #define ALT_USB_DEV_DIEPINT7_AHBERR_E_INACT 0x0
86257 /*
86258  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_AHBERR
86259  *
86260  * AHB Error interrupt
86261  */
86262 #define ALT_USB_DEV_DIEPINT7_AHBERR_E_ACT 0x1
86263 
86264 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */
86265 #define ALT_USB_DEV_DIEPINT7_AHBERR_LSB 2
86266 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */
86267 #define ALT_USB_DEV_DIEPINT7_AHBERR_MSB 2
86268 /* The width in bits of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */
86269 #define ALT_USB_DEV_DIEPINT7_AHBERR_WIDTH 1
86270 /* The mask used to set the ALT_USB_DEV_DIEPINT7_AHBERR register field value. */
86271 #define ALT_USB_DEV_DIEPINT7_AHBERR_SET_MSK 0x00000004
86272 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_AHBERR register field value. */
86273 #define ALT_USB_DEV_DIEPINT7_AHBERR_CLR_MSK 0xfffffffb
86274 /* The reset value of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */
86275 #define ALT_USB_DEV_DIEPINT7_AHBERR_RESET 0x0
86276 /* Extracts the ALT_USB_DEV_DIEPINT7_AHBERR field value from a register. */
86277 #define ALT_USB_DEV_DIEPINT7_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
86278 /* Produces a ALT_USB_DEV_DIEPINT7_AHBERR register field value suitable for setting the register. */
86279 #define ALT_USB_DEV_DIEPINT7_AHBERR_SET(value) (((value) << 2) & 0x00000004)
86280 
86281 /*
86282  * Field : timeout
86283  *
86284  * Timeout Condition (TimeOUT)
86285  *
86286  * In shared TX FIFO mode, applies to non-isochronous IN
86287  *
86288  * endpoints only.
86289  *
86290  * In dedicated FIFO mode, applies only to Control IN
86291  *
86292  * endpoints.
86293  *
86294  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
86295  *
86296  * asserted.
86297  *
86298  * Indicates that the core has detected a timeout condition on the
86299  *
86300  * USB For the last IN token on this endpoint.
86301  *
86302  * Field Enumeration Values:
86303  *
86304  * Enum | Value | Description
86305  * :---------------------------------|:------|:------------------
86306  * ALT_USB_DEV_DIEPINT7_TMO_E_INACT | 0x0 | No interrupt
86307  * ALT_USB_DEV_DIEPINT7_TMO_E_ACT | 0x1 | Timeout interrupy
86308  *
86309  * Field Access Macros:
86310  *
86311  */
86312 /*
86313  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TMO
86314  *
86315  * No interrupt
86316  */
86317 #define ALT_USB_DEV_DIEPINT7_TMO_E_INACT 0x0
86318 /*
86319  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TMO
86320  *
86321  * Timeout interrupy
86322  */
86323 #define ALT_USB_DEV_DIEPINT7_TMO_E_ACT 0x1
86324 
86325 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_TMO register field. */
86326 #define ALT_USB_DEV_DIEPINT7_TMO_LSB 3
86327 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_TMO register field. */
86328 #define ALT_USB_DEV_DIEPINT7_TMO_MSB 3
86329 /* The width in bits of the ALT_USB_DEV_DIEPINT7_TMO register field. */
86330 #define ALT_USB_DEV_DIEPINT7_TMO_WIDTH 1
86331 /* The mask used to set the ALT_USB_DEV_DIEPINT7_TMO register field value. */
86332 #define ALT_USB_DEV_DIEPINT7_TMO_SET_MSK 0x00000008
86333 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_TMO register field value. */
86334 #define ALT_USB_DEV_DIEPINT7_TMO_CLR_MSK 0xfffffff7
86335 /* The reset value of the ALT_USB_DEV_DIEPINT7_TMO register field. */
86336 #define ALT_USB_DEV_DIEPINT7_TMO_RESET 0x0
86337 /* Extracts the ALT_USB_DEV_DIEPINT7_TMO field value from a register. */
86338 #define ALT_USB_DEV_DIEPINT7_TMO_GET(value) (((value) & 0x00000008) >> 3)
86339 /* Produces a ALT_USB_DEV_DIEPINT7_TMO register field value suitable for setting the register. */
86340 #define ALT_USB_DEV_DIEPINT7_TMO_SET(value) (((value) << 3) & 0x00000008)
86341 
86342 /*
86343  * Field : intkntxfemp
86344  *
86345  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
86346  *
86347  * Applies to non-periodic IN endpoints only.
86348  *
86349  * Indicates that an IN token was received when the associated
86350  *
86351  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
86352  *
86353  * asserted on the endpoint For which the IN token was received.
86354  *
86355  * Field Enumeration Values:
86356  *
86357  * Enum | Value | Description
86358  * :-----------------------------------------|:------|:----------------------------
86359  * ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
86360  * ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
86361  *
86362  * Field Access Macros:
86363  *
86364  */
86365 /*
86366  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNTXFEMP
86367  *
86368  * No interrupt
86369  */
86370 #define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_INACT 0x0
86371 /*
86372  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNTXFEMP
86373  *
86374  * IN Token Received Interrupt
86375  */
86376 #define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_ACT 0x1
86377 
86378 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */
86379 #define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_LSB 4
86380 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */
86381 #define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_MSB 4
86382 /* The width in bits of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */
86383 #define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_WIDTH 1
86384 /* The mask used to set the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field value. */
86385 #define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_SET_MSK 0x00000010
86386 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field value. */
86387 #define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_CLR_MSK 0xffffffef
86388 /* The reset value of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */
86389 #define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_RESET 0x0
86390 /* Extracts the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP field value from a register. */
86391 #define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
86392 /* Produces a ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field value suitable for setting the register. */
86393 #define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
86394 
86395 /*
86396  * Field : intknepmis
86397  *
86398  * IN Token Received with EP Mismatch (INTknEPMis)
86399  *
86400  * Applies to non-periodic IN endpoints only.
86401  *
86402  * Indicates that the data in the top of the non-periodic TxFIFO
86403  *
86404  * belongs to an endpoint other than the one For which the IN token
86405  *
86406  * was received. This interrupt is asserted on the endpoint For
86407  *
86408  * which the IN token was received.
86409  *
86410  * Field Enumeration Values:
86411  *
86412  * Enum | Value | Description
86413  * :----------------------------------------|:------|:---------------------------------------------
86414  * ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_INACT | 0x0 | No interrupt
86415  * ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
86416  *
86417  * Field Access Macros:
86418  *
86419  */
86420 /*
86421  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNEPMIS
86422  *
86423  * No interrupt
86424  */
86425 #define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_INACT 0x0
86426 /*
86427  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNEPMIS
86428  *
86429  * IN Token Received with EP Mismatch interrupt
86430  */
86431 #define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_ACT 0x1
86432 
86433 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */
86434 #define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_LSB 5
86435 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */
86436 #define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_MSB 5
86437 /* The width in bits of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */
86438 #define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_WIDTH 1
86439 /* The mask used to set the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field value. */
86440 #define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_SET_MSK 0x00000020
86441 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field value. */
86442 #define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_CLR_MSK 0xffffffdf
86443 /* The reset value of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */
86444 #define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_RESET 0x0
86445 /* Extracts the ALT_USB_DEV_DIEPINT7_INTKNEPMIS field value from a register. */
86446 #define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
86447 /* Produces a ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field value suitable for setting the register. */
86448 #define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
86449 
86450 /*
86451  * Field : inepnakeff
86452  *
86453  * IN Endpoint NAK Effective (INEPNakEff)
86454  *
86455  * Applies to periodic IN endpoints only.
86456  *
86457  * This bit can be cleared when the application clears the IN
86458  *
86459  * endpoint NAK by writing to DIEPCTLn.CNAK.
86460  *
86461  * This interrupt indicates that the core has sampled the NAK bit
86462  *
86463  * Set (either by the application or by the core). The interrupt
86464  *
86465  * indicates that the IN endpoint NAK bit Set by the application has
86466  *
86467  * taken effect in the core.
86468  *
86469  * This interrupt does not guarantee that a NAK handshake is sent
86470  *
86471  * on the USB. A STALL bit takes priority over a NAK bit.
86472  *
86473  * Field Enumeration Values:
86474  *
86475  * Enum | Value | Description
86476  * :----------------------------------------|:------|:------------------------------------
86477  * ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_INACT | 0x0 | No interrupt
86478  * ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
86479  *
86480  * Field Access Macros:
86481  *
86482  */
86483 /*
86484  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INEPNAKEFF
86485  *
86486  * No interrupt
86487  */
86488 #define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_INACT 0x0
86489 /*
86490  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_INEPNAKEFF
86491  *
86492  * IN Endpoint NAK Effective interrupt
86493  */
86494 #define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_ACT 0x1
86495 
86496 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */
86497 #define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_LSB 6
86498 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */
86499 #define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_MSB 6
86500 /* The width in bits of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */
86501 #define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_WIDTH 1
86502 /* The mask used to set the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field value. */
86503 #define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_SET_MSK 0x00000040
86504 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field value. */
86505 #define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_CLR_MSK 0xffffffbf
86506 /* The reset value of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */
86507 #define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_RESET 0x0
86508 /* Extracts the ALT_USB_DEV_DIEPINT7_INEPNAKEFF field value from a register. */
86509 #define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
86510 /* Produces a ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field value suitable for setting the register. */
86511 #define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
86512 
86513 /*
86514  * Field : txfemp
86515  *
86516  * Transmit FIFO Empty (TxFEmp)
86517  *
86518  * This bit is valid only For IN Endpoints
86519  *
86520  * This interrupt is asserted when the TxFIFO For this endpoint is
86521  *
86522  * either half or completely empty. The half or completely empty
86523  *
86524  * status is determined by the TxFIFO Empty Level bit in the Core
86525  *
86526  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
86527  *
86528  * Field Enumeration Values:
86529  *
86530  * Enum | Value | Description
86531  * :------------------------------------|:------|:------------------------------
86532  * ALT_USB_DEV_DIEPINT7_TXFEMP_E_INACT | 0x0 | No interrupt
86533  * ALT_USB_DEV_DIEPINT7_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
86534  *
86535  * Field Access Macros:
86536  *
86537  */
86538 /*
86539  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFEMP
86540  *
86541  * No interrupt
86542  */
86543 #define ALT_USB_DEV_DIEPINT7_TXFEMP_E_INACT 0x0
86544 /*
86545  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFEMP
86546  *
86547  * Transmit FIFO Empty interrupt
86548  */
86549 #define ALT_USB_DEV_DIEPINT7_TXFEMP_E_ACT 0x1
86550 
86551 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */
86552 #define ALT_USB_DEV_DIEPINT7_TXFEMP_LSB 7
86553 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */
86554 #define ALT_USB_DEV_DIEPINT7_TXFEMP_MSB 7
86555 /* The width in bits of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */
86556 #define ALT_USB_DEV_DIEPINT7_TXFEMP_WIDTH 1
86557 /* The mask used to set the ALT_USB_DEV_DIEPINT7_TXFEMP register field value. */
86558 #define ALT_USB_DEV_DIEPINT7_TXFEMP_SET_MSK 0x00000080
86559 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_TXFEMP register field value. */
86560 #define ALT_USB_DEV_DIEPINT7_TXFEMP_CLR_MSK 0xffffff7f
86561 /* The reset value of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */
86562 #define ALT_USB_DEV_DIEPINT7_TXFEMP_RESET 0x1
86563 /* Extracts the ALT_USB_DEV_DIEPINT7_TXFEMP field value from a register. */
86564 #define ALT_USB_DEV_DIEPINT7_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
86565 /* Produces a ALT_USB_DEV_DIEPINT7_TXFEMP register field value suitable for setting the register. */
86566 #define ALT_USB_DEV_DIEPINT7_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
86567 
86568 /*
86569  * Field : txfifoundrn
86570  *
86571  * Fifo Underrun (TxfifoUndrn)
86572  *
86573  * Applies to IN endpoints Only
86574  *
86575  * This bit is valid only If thresholding is enabled. The core generates this
86576  * interrupt when
86577  *
86578  * it detects a transmit FIFO underrun condition For this endpoint.
86579  *
86580  * Field Enumeration Values:
86581  *
86582  * Enum | Value | Description
86583  * :-----------------------------------------|:------|:------------------------
86584  * ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
86585  * ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
86586  *
86587  * Field Access Macros:
86588  *
86589  */
86590 /*
86591  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN
86592  *
86593  * No interrupt
86594  */
86595 #define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_INACT 0x0
86596 /*
86597  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN
86598  *
86599  * Fifo Underrun interrupt
86600  */
86601 #define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_ACT 0x1
86602 
86603 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */
86604 #define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_LSB 8
86605 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */
86606 #define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_MSB 8
86607 /* The width in bits of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */
86608 #define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_WIDTH 1
86609 /* The mask used to set the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field value. */
86610 #define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_SET_MSK 0x00000100
86611 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field value. */
86612 #define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_CLR_MSK 0xfffffeff
86613 /* The reset value of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */
86614 #define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_RESET 0x0
86615 /* Extracts the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN field value from a register. */
86616 #define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
86617 /* Produces a ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field value suitable for setting the register. */
86618 #define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
86619 
86620 /*
86621  * Field : bnaintr
86622  *
86623  * BNA (Buffer Not Available) Interrupt (BNAIntr)
86624  *
86625  * This bit is valid only when Scatter/Gather DMA mode is enabled.
86626  *
86627  * The core generates this interrupt when the descriptor accessed
86628  *
86629  * is not ready For the Core to process, such as Host busy or DMA
86630  *
86631  * done
86632  *
86633  * Field Enumeration Values:
86634  *
86635  * Enum | Value | Description
86636  * :-------------------------------------|:------|:--------------
86637  * ALT_USB_DEV_DIEPINT7_BNAINTR_E_INACT | 0x0 | No interrupt
86638  * ALT_USB_DEV_DIEPINT7_BNAINTR_E_ACT | 0x1 | BNA interrupt
86639  *
86640  * Field Access Macros:
86641  *
86642  */
86643 /*
86644  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_BNAINTR
86645  *
86646  * No interrupt
86647  */
86648 #define ALT_USB_DEV_DIEPINT7_BNAINTR_E_INACT 0x0
86649 /*
86650  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_BNAINTR
86651  *
86652  * BNA interrupt
86653  */
86654 #define ALT_USB_DEV_DIEPINT7_BNAINTR_E_ACT 0x1
86655 
86656 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */
86657 #define ALT_USB_DEV_DIEPINT7_BNAINTR_LSB 9
86658 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */
86659 #define ALT_USB_DEV_DIEPINT7_BNAINTR_MSB 9
86660 /* The width in bits of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */
86661 #define ALT_USB_DEV_DIEPINT7_BNAINTR_WIDTH 1
86662 /* The mask used to set the ALT_USB_DEV_DIEPINT7_BNAINTR register field value. */
86663 #define ALT_USB_DEV_DIEPINT7_BNAINTR_SET_MSK 0x00000200
86664 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_BNAINTR register field value. */
86665 #define ALT_USB_DEV_DIEPINT7_BNAINTR_CLR_MSK 0xfffffdff
86666 /* The reset value of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */
86667 #define ALT_USB_DEV_DIEPINT7_BNAINTR_RESET 0x0
86668 /* Extracts the ALT_USB_DEV_DIEPINT7_BNAINTR field value from a register. */
86669 #define ALT_USB_DEV_DIEPINT7_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
86670 /* Produces a ALT_USB_DEV_DIEPINT7_BNAINTR register field value suitable for setting the register. */
86671 #define ALT_USB_DEV_DIEPINT7_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
86672 
86673 /*
86674  * Field : pktdrpsts
86675  *
86676  * Packet Drop Status (PktDrpSts)
86677  *
86678  * This bit indicates to the application that an ISOC OUT packet has been dropped.
86679  * This
86680  *
86681  * bit does not have an associated mask bit and does not generate an interrupt.
86682  *
86683  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
86684  * transfer
86685  *
86686  * interrupt feature is selected.
86687  *
86688  * Field Enumeration Values:
86689  *
86690  * Enum | Value | Description
86691  * :---------------------------------------|:------|:-----------------------------
86692  * ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_INACT | 0x0 | No interrupt
86693  * ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
86694  *
86695  * Field Access Macros:
86696  *
86697  */
86698 /*
86699  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_PKTDRPSTS
86700  *
86701  * No interrupt
86702  */
86703 #define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_INACT 0x0
86704 /*
86705  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_PKTDRPSTS
86706  *
86707  * Packet Drop Status interrupt
86708  */
86709 #define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_ACT 0x1
86710 
86711 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */
86712 #define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_LSB 11
86713 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */
86714 #define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_MSB 11
86715 /* The width in bits of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */
86716 #define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_WIDTH 1
86717 /* The mask used to set the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field value. */
86718 #define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_SET_MSK 0x00000800
86719 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field value. */
86720 #define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_CLR_MSK 0xfffff7ff
86721 /* The reset value of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */
86722 #define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_RESET 0x0
86723 /* Extracts the ALT_USB_DEV_DIEPINT7_PKTDRPSTS field value from a register. */
86724 #define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
86725 /* Produces a ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field value suitable for setting the register. */
86726 #define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
86727 
86728 /*
86729  * Field : bbleerr
86730  *
86731  * NAK Interrupt (BbleErr)
86732  *
86733  * The core generates this interrupt when babble is received for the endpoint.
86734  *
86735  * Field Enumeration Values:
86736  *
86737  * Enum | Value | Description
86738  * :-------------------------------------|:------|:------------------
86739  * ALT_USB_DEV_DIEPINT7_BBLEERR_E_INACT | 0x0 | No interrupt
86740  * ALT_USB_DEV_DIEPINT7_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
86741  *
86742  * Field Access Macros:
86743  *
86744  */
86745 /*
86746  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_BBLEERR
86747  *
86748  * No interrupt
86749  */
86750 #define ALT_USB_DEV_DIEPINT7_BBLEERR_E_INACT 0x0
86751 /*
86752  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_BBLEERR
86753  *
86754  * BbleErr interrupt
86755  */
86756 #define ALT_USB_DEV_DIEPINT7_BBLEERR_E_ACT 0x1
86757 
86758 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */
86759 #define ALT_USB_DEV_DIEPINT7_BBLEERR_LSB 12
86760 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */
86761 #define ALT_USB_DEV_DIEPINT7_BBLEERR_MSB 12
86762 /* The width in bits of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */
86763 #define ALT_USB_DEV_DIEPINT7_BBLEERR_WIDTH 1
86764 /* The mask used to set the ALT_USB_DEV_DIEPINT7_BBLEERR register field value. */
86765 #define ALT_USB_DEV_DIEPINT7_BBLEERR_SET_MSK 0x00001000
86766 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_BBLEERR register field value. */
86767 #define ALT_USB_DEV_DIEPINT7_BBLEERR_CLR_MSK 0xffffefff
86768 /* The reset value of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */
86769 #define ALT_USB_DEV_DIEPINT7_BBLEERR_RESET 0x0
86770 /* Extracts the ALT_USB_DEV_DIEPINT7_BBLEERR field value from a register. */
86771 #define ALT_USB_DEV_DIEPINT7_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
86772 /* Produces a ALT_USB_DEV_DIEPINT7_BBLEERR register field value suitable for setting the register. */
86773 #define ALT_USB_DEV_DIEPINT7_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
86774 
86775 /*
86776  * Field : nakintrpt
86777  *
86778  * NAK Interrupt (NAKInterrupt)
86779  *
86780  * The core generates this interrupt when a NAK is transmitted or received by the
86781  * device.
86782  *
86783  * In case of isochronous IN endpoints the interrupt gets generated when a zero
86784  * length
86785  *
86786  * packet is transmitted due to un-availability of data in the TXFifo.
86787  *
86788  * Field Enumeration Values:
86789  *
86790  * Enum | Value | Description
86791  * :---------------------------------------|:------|:--------------
86792  * ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_INACT | 0x0 | No interrupt
86793  * ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
86794  *
86795  * Field Access Macros:
86796  *
86797  */
86798 /*
86799  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_NAKINTRPT
86800  *
86801  * No interrupt
86802  */
86803 #define ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_INACT 0x0
86804 /*
86805  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_NAKINTRPT
86806  *
86807  * NAK Interrupt
86808  */
86809 #define ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_ACT 0x1
86810 
86811 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */
86812 #define ALT_USB_DEV_DIEPINT7_NAKINTRPT_LSB 13
86813 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */
86814 #define ALT_USB_DEV_DIEPINT7_NAKINTRPT_MSB 13
86815 /* The width in bits of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */
86816 #define ALT_USB_DEV_DIEPINT7_NAKINTRPT_WIDTH 1
86817 /* The mask used to set the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field value. */
86818 #define ALT_USB_DEV_DIEPINT7_NAKINTRPT_SET_MSK 0x00002000
86819 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field value. */
86820 #define ALT_USB_DEV_DIEPINT7_NAKINTRPT_CLR_MSK 0xffffdfff
86821 /* The reset value of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */
86822 #define ALT_USB_DEV_DIEPINT7_NAKINTRPT_RESET 0x0
86823 /* Extracts the ALT_USB_DEV_DIEPINT7_NAKINTRPT field value from a register. */
86824 #define ALT_USB_DEV_DIEPINT7_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
86825 /* Produces a ALT_USB_DEV_DIEPINT7_NAKINTRPT register field value suitable for setting the register. */
86826 #define ALT_USB_DEV_DIEPINT7_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
86827 
86828 /*
86829  * Field : nyetintrpt
86830  *
86831  * NYET Interrupt (NYETIntrpt)
86832  *
86833  * The core generates this interrupt when a NYET response is transmitted for a non
86834  * isochronous OUT endpoint.
86835  *
86836  * Field Enumeration Values:
86837  *
86838  * Enum | Value | Description
86839  * :----------------------------------------|:------|:---------------
86840  * ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_INACT | 0x0 | No interrupt
86841  * ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
86842  *
86843  * Field Access Macros:
86844  *
86845  */
86846 /*
86847  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_NYETINTRPT
86848  *
86849  * No interrupt
86850  */
86851 #define ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_INACT 0x0
86852 /*
86853  * Enumerated value for register field ALT_USB_DEV_DIEPINT7_NYETINTRPT
86854  *
86855  * NYET Interrupt
86856  */
86857 #define ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_ACT 0x1
86858 
86859 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */
86860 #define ALT_USB_DEV_DIEPINT7_NYETINTRPT_LSB 14
86861 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */
86862 #define ALT_USB_DEV_DIEPINT7_NYETINTRPT_MSB 14
86863 /* The width in bits of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */
86864 #define ALT_USB_DEV_DIEPINT7_NYETINTRPT_WIDTH 1
86865 /* The mask used to set the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field value. */
86866 #define ALT_USB_DEV_DIEPINT7_NYETINTRPT_SET_MSK 0x00004000
86867 /* The mask used to clear the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field value. */
86868 #define ALT_USB_DEV_DIEPINT7_NYETINTRPT_CLR_MSK 0xffffbfff
86869 /* The reset value of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */
86870 #define ALT_USB_DEV_DIEPINT7_NYETINTRPT_RESET 0x0
86871 /* Extracts the ALT_USB_DEV_DIEPINT7_NYETINTRPT field value from a register. */
86872 #define ALT_USB_DEV_DIEPINT7_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
86873 /* Produces a ALT_USB_DEV_DIEPINT7_NYETINTRPT register field value suitable for setting the register. */
86874 #define ALT_USB_DEV_DIEPINT7_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
86875 
86876 #ifndef __ASSEMBLY__
86877 /*
86878  * WARNING: The C register and register group struct declarations are provided for
86879  * convenience and illustrative purposes. They should, however, be used with
86880  * caution as the C language standard provides no guarantees about the alignment or
86881  * atomicity of device memory accesses. The recommended practice for writing
86882  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
86883  * alt_write_word() functions.
86884  *
86885  * The struct declaration for register ALT_USB_DEV_DIEPINT7.
86886  */
86887 struct ALT_USB_DEV_DIEPINT7_s
86888 {
86889  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT7_XFERCOMPL */
86890  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT7_EPDISBLD */
86891  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT7_AHBERR */
86892  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT7_TMO */
86893  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT7_INTKNTXFEMP */
86894  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT7_INTKNEPMIS */
86895  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT7_INEPNAKEFF */
86896  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT7_TXFEMP */
86897  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN */
86898  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT7_BNAINTR */
86899  uint32_t : 1; /* *UNDEFINED* */
86900  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT7_PKTDRPSTS */
86901  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT7_BBLEERR */
86902  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT7_NAKINTRPT */
86903  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT7_NYETINTRPT */
86904  uint32_t : 17; /* *UNDEFINED* */
86905 };
86906 
86907 /* The typedef declaration for register ALT_USB_DEV_DIEPINT7. */
86908 typedef volatile struct ALT_USB_DEV_DIEPINT7_s ALT_USB_DEV_DIEPINT7_t;
86909 #endif /* __ASSEMBLY__ */
86910 
86911 /* The reset value of the ALT_USB_DEV_DIEPINT7 register. */
86912 #define ALT_USB_DEV_DIEPINT7_RESET 0x00000080
86913 /* The byte offset of the ALT_USB_DEV_DIEPINT7 register from the beginning of the component. */
86914 #define ALT_USB_DEV_DIEPINT7_OFST 0x1e8
86915 /* The address of the ALT_USB_DEV_DIEPINT7 register. */
86916 #define ALT_USB_DEV_DIEPINT7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT7_OFST))
86917 
86918 /*
86919  * Register : dieptsiz7
86920  *
86921  * Device IN Endpoint 7 Transfer Size Register
86922  *
86923  * Register Layout
86924  *
86925  * Bits | Access | Reset | Description
86926  * :--------|:-------|:------|:-------------------------------
86927  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ7_XFERSIZE
86928  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ7_PKTCNT
86929  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ7_MC
86930  * [31] | ??? | 0x0 | *UNDEFINED*
86931  *
86932  */
86933 /*
86934  * Field : xfersize
86935  *
86936  * Transfer Size (XferSize)
86937  *
86938  * Indicates the transfer size in bytes For endpoint 0. The core
86939  *
86940  * interrupts the application only after it has exhausted the transfer
86941  *
86942  * size amount of data. The transfer size can be Set to the
86943  *
86944  * maximum packet size of the endpoint, to be interrupted at the
86945  *
86946  * end of each packet.
86947  *
86948  * The core decrements this field every time a packet from the
86949  *
86950  * external memory is written to the TxFIFO.
86951  *
86952  * Field Access Macros:
86953  *
86954  */
86955 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */
86956 #define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_LSB 0
86957 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */
86958 #define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_MSB 18
86959 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */
86960 #define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_WIDTH 19
86961 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field value. */
86962 #define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_SET_MSK 0x0007ffff
86963 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field value. */
86964 #define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_CLR_MSK 0xfff80000
86965 /* The reset value of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */
86966 #define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_RESET 0x0
86967 /* Extracts the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE field value from a register. */
86968 #define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
86969 /* Produces a ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field value suitable for setting the register. */
86970 #define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
86971 
86972 /*
86973  * Field : pktcnt
86974  *
86975  * Packet Count (PktCnt)
86976  *
86977  * Indicates the total number of USB packets that constitute the
86978  *
86979  * Transfer Size amount of data For endpoint 0.
86980  *
86981  * This field is decremented every time a packet (maximum size or
86982  *
86983  * short packet) is read from the TxFIFO.
86984  *
86985  * Field Access Macros:
86986  *
86987  */
86988 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */
86989 #define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_LSB 19
86990 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */
86991 #define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_MSB 28
86992 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */
86993 #define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_WIDTH 10
86994 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field value. */
86995 #define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_SET_MSK 0x1ff80000
86996 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field value. */
86997 #define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_CLR_MSK 0xe007ffff
86998 /* The reset value of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */
86999 #define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_RESET 0x0
87000 /* Extracts the ALT_USB_DEV_DIEPTSIZ7_PKTCNT field value from a register. */
87001 #define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
87002 /* Produces a ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field value suitable for setting the register. */
87003 #define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
87004 
87005 /*
87006  * Field : mc
87007  *
87008  * Applies to IN endpoints only.
87009  *
87010  * For periodic IN endpoints, this field indicates the number of packets that must
87011  * be transmitted per microframe on the USB. The core uses this field to calculate
87012  * the data PID for isochronous IN endpoints.
87013  *
87014  * 2'b01: 1 packet
87015  *
87016  * 2'b10: 2 packets
87017  *
87018  * 2'b11: 3 packets
87019  *
87020  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
87021  * specifies the number of packets the core must fetchfor an IN endpoint before it
87022  * switches to the endpoint pointed to by the Next Endpoint field of the Device
87023  * Endpoint-n Control register (DIEPCTLn.NextEp)
87024  *
87025  * Field Enumeration Values:
87026  *
87027  * Enum | Value | Description
87028  * :------------------------------------|:------|:------------
87029  * ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTONE | 0x1 | 1 packet
87030  * ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTWO | 0x2 | 2 packets
87031  * ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTHREE | 0x3 | 3 packets
87032  *
87033  * Field Access Macros:
87034  *
87035  */
87036 /*
87037  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ7_MC
87038  *
87039  * 1 packet
87040  */
87041 #define ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTONE 0x1
87042 /*
87043  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ7_MC
87044  *
87045  * 2 packets
87046  */
87047 #define ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTWO 0x2
87048 /*
87049  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ7_MC
87050  *
87051  * 3 packets
87052  */
87053 #define ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTHREE 0x3
87054 
87055 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */
87056 #define ALT_USB_DEV_DIEPTSIZ7_MC_LSB 29
87057 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */
87058 #define ALT_USB_DEV_DIEPTSIZ7_MC_MSB 30
87059 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */
87060 #define ALT_USB_DEV_DIEPTSIZ7_MC_WIDTH 2
87061 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ7_MC register field value. */
87062 #define ALT_USB_DEV_DIEPTSIZ7_MC_SET_MSK 0x60000000
87063 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ7_MC register field value. */
87064 #define ALT_USB_DEV_DIEPTSIZ7_MC_CLR_MSK 0x9fffffff
87065 /* The reset value of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */
87066 #define ALT_USB_DEV_DIEPTSIZ7_MC_RESET 0x0
87067 /* Extracts the ALT_USB_DEV_DIEPTSIZ7_MC field value from a register. */
87068 #define ALT_USB_DEV_DIEPTSIZ7_MC_GET(value) (((value) & 0x60000000) >> 29)
87069 /* Produces a ALT_USB_DEV_DIEPTSIZ7_MC register field value suitable for setting the register. */
87070 #define ALT_USB_DEV_DIEPTSIZ7_MC_SET(value) (((value) << 29) & 0x60000000)
87071 
87072 #ifndef __ASSEMBLY__
87073 /*
87074  * WARNING: The C register and register group struct declarations are provided for
87075  * convenience and illustrative purposes. They should, however, be used with
87076  * caution as the C language standard provides no guarantees about the alignment or
87077  * atomicity of device memory accesses. The recommended practice for writing
87078  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
87079  * alt_write_word() functions.
87080  *
87081  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ7.
87082  */
87083 struct ALT_USB_DEV_DIEPTSIZ7_s
87084 {
87085  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ7_XFERSIZE */
87086  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ7_PKTCNT */
87087  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ7_MC */
87088  uint32_t : 1; /* *UNDEFINED* */
87089 };
87090 
87091 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ7. */
87092 typedef volatile struct ALT_USB_DEV_DIEPTSIZ7_s ALT_USB_DEV_DIEPTSIZ7_t;
87093 #endif /* __ASSEMBLY__ */
87094 
87095 /* The reset value of the ALT_USB_DEV_DIEPTSIZ7 register. */
87096 #define ALT_USB_DEV_DIEPTSIZ7_RESET 0x00000000
87097 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ7 register from the beginning of the component. */
87098 #define ALT_USB_DEV_DIEPTSIZ7_OFST 0x1f0
87099 /* The address of the ALT_USB_DEV_DIEPTSIZ7 register. */
87100 #define ALT_USB_DEV_DIEPTSIZ7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ7_OFST))
87101 
87102 /*
87103  * Register : diepdma7
87104  *
87105  * Device IN Endpoint 7 DMA Address Register
87106  *
87107  * Register Layout
87108  *
87109  * Bits | Access | Reset | Description
87110  * :-------|:-------|:--------|:------------------------------
87111  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA7_DIEPDMA7
87112  *
87113  */
87114 /*
87115  * Field : diepdma7
87116  *
87117  * Holds the start address of the external memory for storing or fetching endpoint
87118  *
87119  * data.
87120  *
87121  * Note: For control endpoints, this field stores control OUT data packets as well
87122  * as
87123  *
87124  * SETUP transaction data packets. When more than three SETUP packets are
87125  *
87126  * received back-to-back, the SETUP data packet in the memory is overwritten.
87127  *
87128  * This register is incremented on every AHB transaction. The application can give
87129  *
87130  * only a DWORD-aligned address.
87131  *
87132  * When Scatter/Gather DMA mode is not enabled, the application programs the
87133  *
87134  * start address value in this field.
87135  *
87136  * When Scatter/Gather DMA mode is enabled, this field indicates the base
87137  *
87138  * pointer for the descriptor list.
87139  *
87140  * Field Access Macros:
87141  *
87142  */
87143 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field. */
87144 #define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_LSB 0
87145 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field. */
87146 #define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_MSB 31
87147 /* The width in bits of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field. */
87148 #define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_WIDTH 32
87149 /* The mask used to set the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field value. */
87150 #define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_SET_MSK 0xffffffff
87151 /* The mask used to clear the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field value. */
87152 #define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_CLR_MSK 0x00000000
87153 /* The reset value of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field is UNKNOWN. */
87154 #define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_RESET 0x0
87155 /* Extracts the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 field value from a register. */
87156 #define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_GET(value) (((value) & 0xffffffff) >> 0)
87157 /* Produces a ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field value suitable for setting the register. */
87158 #define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_SET(value) (((value) << 0) & 0xffffffff)
87159 
87160 #ifndef __ASSEMBLY__
87161 /*
87162  * WARNING: The C register and register group struct declarations are provided for
87163  * convenience and illustrative purposes. They should, however, be used with
87164  * caution as the C language standard provides no guarantees about the alignment or
87165  * atomicity of device memory accesses. The recommended practice for writing
87166  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
87167  * alt_write_word() functions.
87168  *
87169  * The struct declaration for register ALT_USB_DEV_DIEPDMA7.
87170  */
87171 struct ALT_USB_DEV_DIEPDMA7_s
87172 {
87173  uint32_t diepdma7 : 32; /* ALT_USB_DEV_DIEPDMA7_DIEPDMA7 */
87174 };
87175 
87176 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA7. */
87177 typedef volatile struct ALT_USB_DEV_DIEPDMA7_s ALT_USB_DEV_DIEPDMA7_t;
87178 #endif /* __ASSEMBLY__ */
87179 
87180 /* The reset value of the ALT_USB_DEV_DIEPDMA7 register. */
87181 #define ALT_USB_DEV_DIEPDMA7_RESET 0x00000000
87182 /* The byte offset of the ALT_USB_DEV_DIEPDMA7 register from the beginning of the component. */
87183 #define ALT_USB_DEV_DIEPDMA7_OFST 0x1f4
87184 /* The address of the ALT_USB_DEV_DIEPDMA7 register. */
87185 #define ALT_USB_DEV_DIEPDMA7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA7_OFST))
87186 
87187 /*
87188  * Register : dtxfsts7
87189  *
87190  * Device IN Endpoint Transmit FIFO Status Register 7
87191  *
87192  * Register Layout
87193  *
87194  * Bits | Access | Reset | Description
87195  * :--------|:-------|:-------|:-------------------------------------
87196  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL
87197  * [31:16] | ??? | 0x0 | *UNDEFINED*
87198  *
87199  */
87200 /*
87201  * Field : ineptxfspcavail
87202  *
87203  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
87204  *
87205  * Indicates the amount of free space available in the Endpoint
87206  *
87207  * TxFIFO.
87208  *
87209  * Values are in terms of 32-bit words.
87210  *
87211  * 16'h0: Endpoint TxFIFO is full
87212  *
87213  * 16'h1: 1 word available
87214  *
87215  * 16'h2: 2 words available
87216  *
87217  * 16'hn: n words available (where 0 n 32,768)
87218  *
87219  * 16'h8000: 32,768 words available
87220  *
87221  * Others: Reserved
87222  *
87223  * Field Access Macros:
87224  *
87225  */
87226 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */
87227 #define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_LSB 0
87228 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */
87229 #define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_MSB 15
87230 /* The width in bits of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */
87231 #define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_WIDTH 16
87232 /* The mask used to set the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field value. */
87233 #define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
87234 /* The mask used to clear the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field value. */
87235 #define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
87236 /* The reset value of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */
87237 #define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_RESET 0x2000
87238 /* Extracts the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL field value from a register. */
87239 #define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
87240 /* Produces a ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field value suitable for setting the register. */
87241 #define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
87242 
87243 #ifndef __ASSEMBLY__
87244 /*
87245  * WARNING: The C register and register group struct declarations are provided for
87246  * convenience and illustrative purposes. They should, however, be used with
87247  * caution as the C language standard provides no guarantees about the alignment or
87248  * atomicity of device memory accesses. The recommended practice for writing
87249  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
87250  * alt_write_word() functions.
87251  *
87252  * The struct declaration for register ALT_USB_DEV_DTXFSTS7.
87253  */
87254 struct ALT_USB_DEV_DTXFSTS7_s
87255 {
87256  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL */
87257  uint32_t : 16; /* *UNDEFINED* */
87258 };
87259 
87260 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS7. */
87261 typedef volatile struct ALT_USB_DEV_DTXFSTS7_s ALT_USB_DEV_DTXFSTS7_t;
87262 #endif /* __ASSEMBLY__ */
87263 
87264 /* The reset value of the ALT_USB_DEV_DTXFSTS7 register. */
87265 #define ALT_USB_DEV_DTXFSTS7_RESET 0x00002000
87266 /* The byte offset of the ALT_USB_DEV_DTXFSTS7 register from the beginning of the component. */
87267 #define ALT_USB_DEV_DTXFSTS7_OFST 0x1f8
87268 /* The address of the ALT_USB_DEV_DTXFSTS7 register. */
87269 #define ALT_USB_DEV_DTXFSTS7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS7_OFST))
87270 
87271 /*
87272  * Register : diepdmab7
87273  *
87274  * Device IN Endpoint 7 Buffer Address Register
87275  *
87276  * Register Layout
87277  *
87278  * Bits | Access | Reset | Description
87279  * :-------|:-------|:--------|:--------------------------------
87280  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7
87281  *
87282  */
87283 /*
87284  * Field : diepdmab7
87285  *
87286  * Holds the current buffer address.This register is updated as and when the data
87287  *
87288  * transfer for the corresponding end point is in progress.
87289  *
87290  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
87291  * is
87292  *
87293  * reserved.
87294  *
87295  * Field Access Macros:
87296  *
87297  */
87298 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field. */
87299 #define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_LSB 0
87300 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field. */
87301 #define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_MSB 31
87302 /* The width in bits of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field. */
87303 #define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_WIDTH 32
87304 /* The mask used to set the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field value. */
87305 #define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_SET_MSK 0xffffffff
87306 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field value. */
87307 #define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_CLR_MSK 0x00000000
87308 /* The reset value of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field is UNKNOWN. */
87309 #define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_RESET 0x0
87310 /* Extracts the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 field value from a register. */
87311 #define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_GET(value) (((value) & 0xffffffff) >> 0)
87312 /* Produces a ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field value suitable for setting the register. */
87313 #define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_SET(value) (((value) << 0) & 0xffffffff)
87314 
87315 #ifndef __ASSEMBLY__
87316 /*
87317  * WARNING: The C register and register group struct declarations are provided for
87318  * convenience and illustrative purposes. They should, however, be used with
87319  * caution as the C language standard provides no guarantees about the alignment or
87320  * atomicity of device memory accesses. The recommended practice for writing
87321  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
87322  * alt_write_word() functions.
87323  *
87324  * The struct declaration for register ALT_USB_DEV_DIEPDMAB7.
87325  */
87326 struct ALT_USB_DEV_DIEPDMAB7_s
87327 {
87328  const uint32_t diepdmab7 : 32; /* ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 */
87329 };
87330 
87331 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB7. */
87332 typedef volatile struct ALT_USB_DEV_DIEPDMAB7_s ALT_USB_DEV_DIEPDMAB7_t;
87333 #endif /* __ASSEMBLY__ */
87334 
87335 /* The reset value of the ALT_USB_DEV_DIEPDMAB7 register. */
87336 #define ALT_USB_DEV_DIEPDMAB7_RESET 0x00000000
87337 /* The byte offset of the ALT_USB_DEV_DIEPDMAB7 register from the beginning of the component. */
87338 #define ALT_USB_DEV_DIEPDMAB7_OFST 0x1fc
87339 /* The address of the ALT_USB_DEV_DIEPDMAB7 register. */
87340 #define ALT_USB_DEV_DIEPDMAB7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB7_OFST))
87341 
87342 /*
87343  * Register : diepctl8
87344  *
87345  * Device Control IN Endpoint 8 Control Register
87346  *
87347  * Register Layout
87348  *
87349  * Bits | Access | Reset | Description
87350  * :--------|:---------|:------|:------------------------------
87351  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL8_MPS
87352  * [14:11] | ??? | 0x0 | *UNDEFINED*
87353  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL8_USBACTEP
87354  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL8_DPID
87355  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL8_NAKSTS
87356  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL8_EPTYPE
87357  * [20] | ??? | 0x0 | *UNDEFINED*
87358  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL8_STALL
87359  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL8_TXFNUM
87360  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL8_CNAK
87361  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL8_SNAK
87362  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL8_SETD0PID
87363  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL8_SETD1PID
87364  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL8_EPDIS
87365  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL8_EPENA
87366  *
87367  */
87368 /*
87369  * Field : mps
87370  *
87371  * Maximum Packet Size (MPS)
87372  *
87373  * The application must program this field with the maximum packet size for the
87374  * current
87375  *
87376  * logical endpoint. This value is in bytes.
87377  *
87378  * Field Access Macros:
87379  *
87380  */
87381 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_MPS register field. */
87382 #define ALT_USB_DEV_DIEPCTL8_MPS_LSB 0
87383 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_MPS register field. */
87384 #define ALT_USB_DEV_DIEPCTL8_MPS_MSB 10
87385 /* The width in bits of the ALT_USB_DEV_DIEPCTL8_MPS register field. */
87386 #define ALT_USB_DEV_DIEPCTL8_MPS_WIDTH 11
87387 /* The mask used to set the ALT_USB_DEV_DIEPCTL8_MPS register field value. */
87388 #define ALT_USB_DEV_DIEPCTL8_MPS_SET_MSK 0x000007ff
87389 /* The mask used to clear the ALT_USB_DEV_DIEPCTL8_MPS register field value. */
87390 #define ALT_USB_DEV_DIEPCTL8_MPS_CLR_MSK 0xfffff800
87391 /* The reset value of the ALT_USB_DEV_DIEPCTL8_MPS register field. */
87392 #define ALT_USB_DEV_DIEPCTL8_MPS_RESET 0x0
87393 /* Extracts the ALT_USB_DEV_DIEPCTL8_MPS field value from a register. */
87394 #define ALT_USB_DEV_DIEPCTL8_MPS_GET(value) (((value) & 0x000007ff) >> 0)
87395 /* Produces a ALT_USB_DEV_DIEPCTL8_MPS register field value suitable for setting the register. */
87396 #define ALT_USB_DEV_DIEPCTL8_MPS_SET(value) (((value) << 0) & 0x000007ff)
87397 
87398 /*
87399  * Field : usbactep
87400  *
87401  * USB Active Endpoint (USBActEP)
87402  *
87403  * Indicates whether this endpoint is active in the current configuration and
87404  * interface. The
87405  *
87406  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
87407  * reset. After
87408  *
87409  * receiving the SetConfiguration and SetInterface commands, the application must
87410  *
87411  * program endpoint registers accordingly and set this bit.
87412  *
87413  * Field Enumeration Values:
87414  *
87415  * Enum | Value | Description
87416  * :-------------------------------------|:------|:--------------------
87417  * ALT_USB_DEV_DIEPCTL8_USBACTEP_E_DISD | 0x0 | Not Active
87418  * ALT_USB_DEV_DIEPCTL8_USBACTEP_E_END | 0x1 | USB Active Endpoint
87419  *
87420  * Field Access Macros:
87421  *
87422  */
87423 /*
87424  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_USBACTEP
87425  *
87426  * Not Active
87427  */
87428 #define ALT_USB_DEV_DIEPCTL8_USBACTEP_E_DISD 0x0
87429 /*
87430  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_USBACTEP
87431  *
87432  * USB Active Endpoint
87433  */
87434 #define ALT_USB_DEV_DIEPCTL8_USBACTEP_E_END 0x1
87435 
87436 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */
87437 #define ALT_USB_DEV_DIEPCTL8_USBACTEP_LSB 15
87438 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */
87439 #define ALT_USB_DEV_DIEPCTL8_USBACTEP_MSB 15
87440 /* The width in bits of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */
87441 #define ALT_USB_DEV_DIEPCTL8_USBACTEP_WIDTH 1
87442 /* The mask used to set the ALT_USB_DEV_DIEPCTL8_USBACTEP register field value. */
87443 #define ALT_USB_DEV_DIEPCTL8_USBACTEP_SET_MSK 0x00008000
87444 /* The mask used to clear the ALT_USB_DEV_DIEPCTL8_USBACTEP register field value. */
87445 #define ALT_USB_DEV_DIEPCTL8_USBACTEP_CLR_MSK 0xffff7fff
87446 /* The reset value of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */
87447 #define ALT_USB_DEV_DIEPCTL8_USBACTEP_RESET 0x0
87448 /* Extracts the ALT_USB_DEV_DIEPCTL8_USBACTEP field value from a register. */
87449 #define ALT_USB_DEV_DIEPCTL8_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
87450 /* Produces a ALT_USB_DEV_DIEPCTL8_USBACTEP register field value suitable for setting the register. */
87451 #define ALT_USB_DEV_DIEPCTL8_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
87452 
87453 /*
87454  * Field : dpid
87455  *
87456  * Endpoint Data PID (DPID)
87457  *
87458  * Applies to interrupt/bulk IN and OUT endpoints only.
87459  *
87460  * Contains the PID of the packet to be received or transmitted on this endpoint.
87461  * The
87462  *
87463  * application must program the PID of the first packet to be received or
87464  * transmitted on
87465  *
87466  * this endpoint, after the endpoint is activated. The applications use the
87467  * SetD1PID and
87468  *
87469  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
87470  *
87471  * 1'b0: DATA0
87472  *
87473  * 1'b1: DATA1
87474  *
87475  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
87476  *
87477  * DMA mode.
87478  *
87479  * 1'b0 RO
87480  *
87481  * Even/Odd (Micro)Frame (EO_FrNum)
87482  *
87483  * In non-Scatter/Gather DMA mode:
87484  *
87485  * Applies to isochronous IN and OUT endpoints only.
87486  *
87487  * Indicates the (micro)frame number in which the core transmits/receives
87488  * isochronous
87489  *
87490  * data for this endpoint. The application must program the even/odd (micro) frame
87491  *
87492  * number in which it intends to transmit/receive isochronous data for this
87493  * endpoint using
87494  *
87495  * the SetEvnFr and SetOddFr fields in this register.
87496  *
87497  * 1'b0: Even (micro)frame
87498  *
87499  * 1'b1: Odd (micro)frame
87500  *
87501  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
87502  * number
87503  *
87504  * in which to send data is provided in the transmit descriptor structure. The
87505  * frame in
87506  *
87507  * which data is received is updated in receive descriptor structure.
87508  *
87509  * Field Enumeration Values:
87510  *
87511  * Enum | Value | Description
87512  * :----------------------------------|:------|:-----------------------------
87513  * ALT_USB_DEV_DIEPCTL8_DPID_E_INACT | 0x0 | Endpoint Data PID not active
87514  * ALT_USB_DEV_DIEPCTL8_DPID_E_ACT | 0x1 | Endpoint Data PID active
87515  *
87516  * Field Access Macros:
87517  *
87518  */
87519 /*
87520  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_DPID
87521  *
87522  * Endpoint Data PID not active
87523  */
87524 #define ALT_USB_DEV_DIEPCTL8_DPID_E_INACT 0x0
87525 /*
87526  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_DPID
87527  *
87528  * Endpoint Data PID active
87529  */
87530 #define ALT_USB_DEV_DIEPCTL8_DPID_E_ACT 0x1
87531 
87532 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_DPID register field. */
87533 #define ALT_USB_DEV_DIEPCTL8_DPID_LSB 16
87534 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_DPID register field. */
87535 #define ALT_USB_DEV_DIEPCTL8_DPID_MSB 16
87536 /* The width in bits of the ALT_USB_DEV_DIEPCTL8_DPID register field. */
87537 #define ALT_USB_DEV_DIEPCTL8_DPID_WIDTH 1
87538 /* The mask used to set the ALT_USB_DEV_DIEPCTL8_DPID register field value. */
87539 #define ALT_USB_DEV_DIEPCTL8_DPID_SET_MSK 0x00010000
87540 /* The mask used to clear the ALT_USB_DEV_DIEPCTL8_DPID register field value. */
87541 #define ALT_USB_DEV_DIEPCTL8_DPID_CLR_MSK 0xfffeffff
87542 /* The reset value of the ALT_USB_DEV_DIEPCTL8_DPID register field. */
87543 #define ALT_USB_DEV_DIEPCTL8_DPID_RESET 0x0
87544 /* Extracts the ALT_USB_DEV_DIEPCTL8_DPID field value from a register. */
87545 #define ALT_USB_DEV_DIEPCTL8_DPID_GET(value) (((value) & 0x00010000) >> 16)
87546 /* Produces a ALT_USB_DEV_DIEPCTL8_DPID register field value suitable for setting the register. */
87547 #define ALT_USB_DEV_DIEPCTL8_DPID_SET(value) (((value) << 16) & 0x00010000)
87548 
87549 /*
87550  * Field : naksts
87551  *
87552  * NAK Status (NAKSts)
87553  *
87554  * Indicates the following:
87555  *
87556  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
87557  *
87558  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
87559  *
87560  * When either the application or the core sets this bit:
87561  *
87562  * The core stops receiving any data on an OUT endpoint, even if there is space in
87563  *
87564  * the RxFIFO to accommodate the incoming packet.
87565  *
87566  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
87567  *
87568  * endpoint, even if there data is available in the TxFIFO.
87569  *
87570  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
87571  *
87572  * if there data is available in the TxFIFO.
87573  *
87574  * Irrespective of this bit's setting, the core always responds to SETUP data
87575  * packets with
87576  *
87577  * an ACK handshake.
87578  *
87579  * Field Enumeration Values:
87580  *
87581  * Enum | Value | Description
87582  * :-------------------------------------|:------|:------------------------------------------------
87583  * ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
87584  * : | | based on the FIFO status
87585  * ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
87586  * : | | endpoint
87587  *
87588  * Field Access Macros:
87589  *
87590  */
87591 /*
87592  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_NAKSTS
87593  *
87594  * The core is transmitting non-NAK handshakes based on the FIFO status
87595  */
87596 #define ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NONNAK 0x0
87597 /*
87598  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_NAKSTS
87599  *
87600  * The core is transmitting NAK handshakes on this endpoint
87601  */
87602 #define ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NAK 0x1
87603 
87604 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */
87605 #define ALT_USB_DEV_DIEPCTL8_NAKSTS_LSB 17
87606 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */
87607 #define ALT_USB_DEV_DIEPCTL8_NAKSTS_MSB 17
87608 /* The width in bits of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */
87609 #define ALT_USB_DEV_DIEPCTL8_NAKSTS_WIDTH 1
87610 /* The mask used to set the ALT_USB_DEV_DIEPCTL8_NAKSTS register field value. */
87611 #define ALT_USB_DEV_DIEPCTL8_NAKSTS_SET_MSK 0x00020000
87612 /* The mask used to clear the ALT_USB_DEV_DIEPCTL8_NAKSTS register field value. */
87613 #define ALT_USB_DEV_DIEPCTL8_NAKSTS_CLR_MSK 0xfffdffff
87614 /* The reset value of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */
87615 #define ALT_USB_DEV_DIEPCTL8_NAKSTS_RESET 0x0
87616 /* Extracts the ALT_USB_DEV_DIEPCTL8_NAKSTS field value from a register. */
87617 #define ALT_USB_DEV_DIEPCTL8_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
87618 /* Produces a ALT_USB_DEV_DIEPCTL8_NAKSTS register field value suitable for setting the register. */
87619 #define ALT_USB_DEV_DIEPCTL8_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
87620 
87621 /*
87622  * Field : eptype
87623  *
87624  * Endpoint Type (EPType)
87625  *
87626  * This is the transfer type supported by this logical endpoint.
87627  *
87628  * 2'b00: Control
87629  *
87630  * 2'b01: Isochronous
87631  *
87632  * 2'b10: Bulk
87633  *
87634  * 2'b11: Interrupt
87635  *
87636  * Field Enumeration Values:
87637  *
87638  * Enum | Value | Description
87639  * :------------------------------------------|:------|:------------
87640  * ALT_USB_DEV_DIEPCTL8_EPTYPE_E_CTL | 0x0 | Control
87641  * ALT_USB_DEV_DIEPCTL8_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
87642  * ALT_USB_DEV_DIEPCTL8_EPTYPE_E_BULK | 0x2 | Bulk
87643  * ALT_USB_DEV_DIEPCTL8_EPTYPE_E_INTERRUP | 0x3 | Interrupt
87644  *
87645  * Field Access Macros:
87646  *
87647  */
87648 /*
87649  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE
87650  *
87651  * Control
87652  */
87653 #define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_CTL 0x0
87654 /*
87655  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE
87656  *
87657  * Isochronous
87658  */
87659 #define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_ISOCHRONOUS 0x1
87660 /*
87661  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE
87662  *
87663  * Bulk
87664  */
87665 #define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_BULK 0x2
87666 /*
87667  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE
87668  *
87669  * Interrupt
87670  */
87671 #define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_INTERRUP 0x3
87672 
87673 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */
87674 #define ALT_USB_DEV_DIEPCTL8_EPTYPE_LSB 18
87675 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */
87676 #define ALT_USB_DEV_DIEPCTL8_EPTYPE_MSB 19
87677 /* The width in bits of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */
87678 #define ALT_USB_DEV_DIEPCTL8_EPTYPE_WIDTH 2
87679 /* The mask used to set the ALT_USB_DEV_DIEPCTL8_EPTYPE register field value. */
87680 #define ALT_USB_DEV_DIEPCTL8_EPTYPE_SET_MSK 0x000c0000
87681 /* The mask used to clear the ALT_USB_DEV_DIEPCTL8_EPTYPE register field value. */
87682 #define ALT_USB_DEV_DIEPCTL8_EPTYPE_CLR_MSK 0xfff3ffff
87683 /* The reset value of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */
87684 #define ALT_USB_DEV_DIEPCTL8_EPTYPE_RESET 0x0
87685 /* Extracts the ALT_USB_DEV_DIEPCTL8_EPTYPE field value from a register. */
87686 #define ALT_USB_DEV_DIEPCTL8_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
87687 /* Produces a ALT_USB_DEV_DIEPCTL8_EPTYPE register field value suitable for setting the register. */
87688 #define ALT_USB_DEV_DIEPCTL8_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
87689 
87690 /*
87691  * Field : stall
87692  *
87693  * STALL Handshake (Stall)
87694  *
87695  * Applies to non-control, non-isochronous IN and OUT endpoints only.
87696  *
87697  * The application sets this bit to stall all tokens from the USB host to this
87698  * endpoint. If a
87699  *
87700  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
87701  * bit, the
87702  *
87703  * STALL bit takes priority. Only the application can clear this bit, never the
87704  * core.
87705  *
87706  * 1'b0 R_W
87707  *
87708  * Applies to control endpoints only.
87709  *
87710  * The application can only set this bit, and the core clears it, when a SETUP
87711  * token is
87712  *
87713  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
87714  * OUT
87715  *
87716  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
87717  * this bit's
87718  *
87719  * setting, the core always responds to SETUP data packets with an ACK handshake.
87720  *
87721  * Field Enumeration Values:
87722  *
87723  * Enum | Value | Description
87724  * :-----------------------------------|:------|:----------------------------
87725  * ALT_USB_DEV_DIEPCTL8_STALL_E_INACT | 0x0 | STALL All Tokens not active
87726  * ALT_USB_DEV_DIEPCTL8_STALL_E_ACT | 0x1 | STALL All Tokens active
87727  *
87728  * Field Access Macros:
87729  *
87730  */
87731 /*
87732  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_STALL
87733  *
87734  * STALL All Tokens not active
87735  */
87736 #define ALT_USB_DEV_DIEPCTL8_STALL_E_INACT 0x0
87737 /*
87738  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_STALL
87739  *
87740  * STALL All Tokens active
87741  */
87742 #define ALT_USB_DEV_DIEPCTL8_STALL_E_ACT 0x1
87743 
87744 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_STALL register field. */
87745 #define ALT_USB_DEV_DIEPCTL8_STALL_LSB 21
87746 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_STALL register field. */
87747 #define ALT_USB_DEV_DIEPCTL8_STALL_MSB 21
87748 /* The width in bits of the ALT_USB_DEV_DIEPCTL8_STALL register field. */
87749 #define ALT_USB_DEV_DIEPCTL8_STALL_WIDTH 1
87750 /* The mask used to set the ALT_USB_DEV_DIEPCTL8_STALL register field value. */
87751 #define ALT_USB_DEV_DIEPCTL8_STALL_SET_MSK 0x00200000
87752 /* The mask used to clear the ALT_USB_DEV_DIEPCTL8_STALL register field value. */
87753 #define ALT_USB_DEV_DIEPCTL8_STALL_CLR_MSK 0xffdfffff
87754 /* The reset value of the ALT_USB_DEV_DIEPCTL8_STALL register field. */
87755 #define ALT_USB_DEV_DIEPCTL8_STALL_RESET 0x0
87756 /* Extracts the ALT_USB_DEV_DIEPCTL8_STALL field value from a register. */
87757 #define ALT_USB_DEV_DIEPCTL8_STALL_GET(value) (((value) & 0x00200000) >> 21)
87758 /* Produces a ALT_USB_DEV_DIEPCTL8_STALL register field value suitable for setting the register. */
87759 #define ALT_USB_DEV_DIEPCTL8_STALL_SET(value) (((value) << 21) & 0x00200000)
87760 
87761 /*
87762  * Field : txfnum
87763  *
87764  * TxFIFO Number (TxFNum)
87765  *
87766  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
87767  *
87768  * endpoints must map this to the corresponding Periodic TxFIFO number.
87769  *
87770  * 4'h0: Non-Periodic TxFIFO
87771  *
87772  * Others: Specified Periodic TxFIFO.number
87773  *
87774  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
87775  *
87776  * applications such as mass storage. The core treats an IN endpoint as a non-
87777  * periodic
87778  *
87779  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
87780  * must be
87781  *
87782  * allocated for an interrupt IN endpoint, and the number of this
87783  *
87784  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
87785  *
87786  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
87787  *
87788  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
87789  *
87790  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
87791  *
87792  * This field is valid only for IN endpoints.
87793  *
87794  * Field Access Macros:
87795  *
87796  */
87797 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */
87798 #define ALT_USB_DEV_DIEPCTL8_TXFNUM_LSB 22
87799 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */
87800 #define ALT_USB_DEV_DIEPCTL8_TXFNUM_MSB 25
87801 /* The width in bits of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */
87802 #define ALT_USB_DEV_DIEPCTL8_TXFNUM_WIDTH 4
87803 /* The mask used to set the ALT_USB_DEV_DIEPCTL8_TXFNUM register field value. */
87804 #define ALT_USB_DEV_DIEPCTL8_TXFNUM_SET_MSK 0x03c00000
87805 /* The mask used to clear the ALT_USB_DEV_DIEPCTL8_TXFNUM register field value. */
87806 #define ALT_USB_DEV_DIEPCTL8_TXFNUM_CLR_MSK 0xfc3fffff
87807 /* The reset value of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */
87808 #define ALT_USB_DEV_DIEPCTL8_TXFNUM_RESET 0x0
87809 /* Extracts the ALT_USB_DEV_DIEPCTL8_TXFNUM field value from a register. */
87810 #define ALT_USB_DEV_DIEPCTL8_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
87811 /* Produces a ALT_USB_DEV_DIEPCTL8_TXFNUM register field value suitable for setting the register. */
87812 #define ALT_USB_DEV_DIEPCTL8_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
87813 
87814 /*
87815  * Field : cnak
87816  *
87817  * Clear NAK (CNAK)
87818  *
87819  * A write to this bit clears the NAK bit For the endpoint.
87820  *
87821  * Field Enumeration Values:
87822  *
87823  * Enum | Value | Description
87824  * :----------------------------------|:------|:-------------
87825  * ALT_USB_DEV_DIEPCTL8_CNAK_E_INACT | 0x0 | No Clear NAK
87826  * ALT_USB_DEV_DIEPCTL8_CNAK_E_ACT | 0x1 | Clear NAK
87827  *
87828  * Field Access Macros:
87829  *
87830  */
87831 /*
87832  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_CNAK
87833  *
87834  * No Clear NAK
87835  */
87836 #define ALT_USB_DEV_DIEPCTL8_CNAK_E_INACT 0x0
87837 /*
87838  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_CNAK
87839  *
87840  * Clear NAK
87841  */
87842 #define ALT_USB_DEV_DIEPCTL8_CNAK_E_ACT 0x1
87843 
87844 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */
87845 #define ALT_USB_DEV_DIEPCTL8_CNAK_LSB 26
87846 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */
87847 #define ALT_USB_DEV_DIEPCTL8_CNAK_MSB 26
87848 /* The width in bits of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */
87849 #define ALT_USB_DEV_DIEPCTL8_CNAK_WIDTH 1
87850 /* The mask used to set the ALT_USB_DEV_DIEPCTL8_CNAK register field value. */
87851 #define ALT_USB_DEV_DIEPCTL8_CNAK_SET_MSK 0x04000000
87852 /* The mask used to clear the ALT_USB_DEV_DIEPCTL8_CNAK register field value. */
87853 #define ALT_USB_DEV_DIEPCTL8_CNAK_CLR_MSK 0xfbffffff
87854 /* The reset value of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */
87855 #define ALT_USB_DEV_DIEPCTL8_CNAK_RESET 0x0
87856 /* Extracts the ALT_USB_DEV_DIEPCTL8_CNAK field value from a register. */
87857 #define ALT_USB_DEV_DIEPCTL8_CNAK_GET(value) (((value) & 0x04000000) >> 26)
87858 /* Produces a ALT_USB_DEV_DIEPCTL8_CNAK register field value suitable for setting the register. */
87859 #define ALT_USB_DEV_DIEPCTL8_CNAK_SET(value) (((value) << 26) & 0x04000000)
87860 
87861 /*
87862  * Field : snak
87863  *
87864  * Set NAK (SNAK)
87865  *
87866  * A write to this bit sets the NAK bit For the endpoint.
87867  *
87868  * Using this bit, the application can control the transmission of NAK
87869  *
87870  * handshakes on an endpoint. The core can also Set this bit For an
87871  *
87872  * endpoint after a SETUP packet is received on that endpoint.
87873  *
87874  * Field Enumeration Values:
87875  *
87876  * Enum | Value | Description
87877  * :----------------------------------|:------|:------------
87878  * ALT_USB_DEV_DIEPCTL8_SNAK_E_INACT | 0x0 | No Set NAK
87879  * ALT_USB_DEV_DIEPCTL8_SNAK_E_ACT | 0x1 | Set NAK
87880  *
87881  * Field Access Macros:
87882  *
87883  */
87884 /*
87885  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SNAK
87886  *
87887  * No Set NAK
87888  */
87889 #define ALT_USB_DEV_DIEPCTL8_SNAK_E_INACT 0x0
87890 /*
87891  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SNAK
87892  *
87893  * Set NAK
87894  */
87895 #define ALT_USB_DEV_DIEPCTL8_SNAK_E_ACT 0x1
87896 
87897 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */
87898 #define ALT_USB_DEV_DIEPCTL8_SNAK_LSB 27
87899 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */
87900 #define ALT_USB_DEV_DIEPCTL8_SNAK_MSB 27
87901 /* The width in bits of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */
87902 #define ALT_USB_DEV_DIEPCTL8_SNAK_WIDTH 1
87903 /* The mask used to set the ALT_USB_DEV_DIEPCTL8_SNAK register field value. */
87904 #define ALT_USB_DEV_DIEPCTL8_SNAK_SET_MSK 0x08000000
87905 /* The mask used to clear the ALT_USB_DEV_DIEPCTL8_SNAK register field value. */
87906 #define ALT_USB_DEV_DIEPCTL8_SNAK_CLR_MSK 0xf7ffffff
87907 /* The reset value of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */
87908 #define ALT_USB_DEV_DIEPCTL8_SNAK_RESET 0x0
87909 /* Extracts the ALT_USB_DEV_DIEPCTL8_SNAK field value from a register. */
87910 #define ALT_USB_DEV_DIEPCTL8_SNAK_GET(value) (((value) & 0x08000000) >> 27)
87911 /* Produces a ALT_USB_DEV_DIEPCTL8_SNAK register field value suitable for setting the register. */
87912 #define ALT_USB_DEV_DIEPCTL8_SNAK_SET(value) (((value) << 27) & 0x08000000)
87913 
87914 /*
87915  * Field : setd0pid
87916  *
87917  * Set DATA0 PID (SetD0PID)
87918  *
87919  * Applies to interrupt/bulk IN and OUT endpoints only.
87920  *
87921  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
87922  * to DATA0.
87923  *
87924  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
87925  *
87926  * DMA mode.
87927  *
87928  * 1'b0 WO
87929  *
87930  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
87931  *
87932  * Applies to isochronous IN and OUT endpoints only.
87933  *
87934  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
87935  * (micro)
87936  *
87937  * frame.
87938  *
87939  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
87940  * number
87941  *
87942  * in which to send data is in the transmit descriptor structure. The frame in
87943  * which to
87944  *
87945  * receive data is updated in receive descriptor structure.
87946  *
87947  * Field Enumeration Values:
87948  *
87949  * Enum | Value | Description
87950  * :-------------------------------------|:------|:----------------------------
87951  * ALT_USB_DEV_DIEPCTL8_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
87952  * ALT_USB_DEV_DIEPCTL8_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
87953  *
87954  * Field Access Macros:
87955  *
87956  */
87957 /*
87958  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD0PID
87959  *
87960  * Disables Set DATA0 PID
87961  */
87962 #define ALT_USB_DEV_DIEPCTL8_SETD0PID_E_DISD 0x0
87963 /*
87964  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD0PID
87965  *
87966  * Endpoint Data PID to DATA0)
87967  */
87968 #define ALT_USB_DEV_DIEPCTL8_SETD0PID_E_END 0x1
87969 
87970 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */
87971 #define ALT_USB_DEV_DIEPCTL8_SETD0PID_LSB 28
87972 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */
87973 #define ALT_USB_DEV_DIEPCTL8_SETD0PID_MSB 28
87974 /* The width in bits of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */
87975 #define ALT_USB_DEV_DIEPCTL8_SETD0PID_WIDTH 1
87976 /* The mask used to set the ALT_USB_DEV_DIEPCTL8_SETD0PID register field value. */
87977 #define ALT_USB_DEV_DIEPCTL8_SETD0PID_SET_MSK 0x10000000
87978 /* The mask used to clear the ALT_USB_DEV_DIEPCTL8_SETD0PID register field value. */
87979 #define ALT_USB_DEV_DIEPCTL8_SETD0PID_CLR_MSK 0xefffffff
87980 /* The reset value of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */
87981 #define ALT_USB_DEV_DIEPCTL8_SETD0PID_RESET 0x0
87982 /* Extracts the ALT_USB_DEV_DIEPCTL8_SETD0PID field value from a register. */
87983 #define ALT_USB_DEV_DIEPCTL8_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
87984 /* Produces a ALT_USB_DEV_DIEPCTL8_SETD0PID register field value suitable for setting the register. */
87985 #define ALT_USB_DEV_DIEPCTL8_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
87986 
87987 /*
87988  * Field : setd1pid
87989  *
87990  * Set DATA1 PID (SetD1PID)
87991  *
87992  * Applies to interrupt/bulk IN and OUT endpoints only.
87993  *
87994  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
87995  * to DATA1.
87996  *
87997  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
87998  *
87999  * DMA mode.
88000  *
88001  * Set Odd (micro)frame (SetOddFr)
88002  *
88003  * Applies to isochronous IN and OUT endpoints only.
88004  *
88005  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
88006  *
88007  * (micro)frame.
88008  *
88009  * This field is not applicable for Scatter/Gather DMA mode.
88010  *
88011  * Field Enumeration Values:
88012  *
88013  * Enum | Value | Description
88014  * :-------------------------------------|:------|:-----------------------
88015  * ALT_USB_DEV_DIEPCTL8_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
88016  * ALT_USB_DEV_DIEPCTL8_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
88017  *
88018  * Field Access Macros:
88019  *
88020  */
88021 /*
88022  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD1PID
88023  *
88024  * Disables Set DATA1 PID
88025  */
88026 #define ALT_USB_DEV_DIEPCTL8_SETD1PID_E_DISD 0x0
88027 /*
88028  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD1PID
88029  *
88030  * Enables Set DATA1 PID
88031  */
88032 #define ALT_USB_DEV_DIEPCTL8_SETD1PID_E_END 0x1
88033 
88034 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */
88035 #define ALT_USB_DEV_DIEPCTL8_SETD1PID_LSB 29
88036 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */
88037 #define ALT_USB_DEV_DIEPCTL8_SETD1PID_MSB 29
88038 /* The width in bits of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */
88039 #define ALT_USB_DEV_DIEPCTL8_SETD1PID_WIDTH 1
88040 /* The mask used to set the ALT_USB_DEV_DIEPCTL8_SETD1PID register field value. */
88041 #define ALT_USB_DEV_DIEPCTL8_SETD1PID_SET_MSK 0x20000000
88042 /* The mask used to clear the ALT_USB_DEV_DIEPCTL8_SETD1PID register field value. */
88043 #define ALT_USB_DEV_DIEPCTL8_SETD1PID_CLR_MSK 0xdfffffff
88044 /* The reset value of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */
88045 #define ALT_USB_DEV_DIEPCTL8_SETD1PID_RESET 0x0
88046 /* Extracts the ALT_USB_DEV_DIEPCTL8_SETD1PID field value from a register. */
88047 #define ALT_USB_DEV_DIEPCTL8_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
88048 /* Produces a ALT_USB_DEV_DIEPCTL8_SETD1PID register field value suitable for setting the register. */
88049 #define ALT_USB_DEV_DIEPCTL8_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
88050 
88051 /*
88052  * Field : epdis
88053  *
88054  * Endpoint Disable (EPDis)
88055  *
88056  * Applies to IN and OUT endpoints.
88057  *
88058  * The application sets this bit to stop transmitting/receiving data on an
88059  * endpoint, even
88060  *
88061  * before the transfer for that endpoint is complete. The application must wait for
88062  * the
88063  *
88064  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
88065  * clears
88066  *
88067  * this bit before setting the Endpoint Disabled interrupt. The application must
88068  * set this bit
88069  *
88070  * only if Endpoint Enable is already set for this endpoint.
88071  *
88072  * Field Enumeration Values:
88073  *
88074  * Enum | Value | Description
88075  * :-----------------------------------|:------|:--------------------
88076  * ALT_USB_DEV_DIEPCTL8_EPDIS_E_INACT | 0x0 | No Endpoint Disable
88077  * ALT_USB_DEV_DIEPCTL8_EPDIS_E_ACT | 0x1 | Endpoint Disable
88078  *
88079  * Field Access Macros:
88080  *
88081  */
88082 /*
88083  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPDIS
88084  *
88085  * No Endpoint Disable
88086  */
88087 #define ALT_USB_DEV_DIEPCTL8_EPDIS_E_INACT 0x0
88088 /*
88089  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPDIS
88090  *
88091  * Endpoint Disable
88092  */
88093 #define ALT_USB_DEV_DIEPCTL8_EPDIS_E_ACT 0x1
88094 
88095 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */
88096 #define ALT_USB_DEV_DIEPCTL8_EPDIS_LSB 30
88097 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */
88098 #define ALT_USB_DEV_DIEPCTL8_EPDIS_MSB 30
88099 /* The width in bits of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */
88100 #define ALT_USB_DEV_DIEPCTL8_EPDIS_WIDTH 1
88101 /* The mask used to set the ALT_USB_DEV_DIEPCTL8_EPDIS register field value. */
88102 #define ALT_USB_DEV_DIEPCTL8_EPDIS_SET_MSK 0x40000000
88103 /* The mask used to clear the ALT_USB_DEV_DIEPCTL8_EPDIS register field value. */
88104 #define ALT_USB_DEV_DIEPCTL8_EPDIS_CLR_MSK 0xbfffffff
88105 /* The reset value of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */
88106 #define ALT_USB_DEV_DIEPCTL8_EPDIS_RESET 0x0
88107 /* Extracts the ALT_USB_DEV_DIEPCTL8_EPDIS field value from a register. */
88108 #define ALT_USB_DEV_DIEPCTL8_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
88109 /* Produces a ALT_USB_DEV_DIEPCTL8_EPDIS register field value suitable for setting the register. */
88110 #define ALT_USB_DEV_DIEPCTL8_EPDIS_SET(value) (((value) << 30) & 0x40000000)
88111 
88112 /*
88113  * Field : epena
88114  *
88115  * Endpoint Enable (EPEna)
88116  *
88117  * Applies to IN and OUT endpoints.
88118  *
88119  * When Scatter/Gather DMA mode is enabled,
88120  *
88121  * For IN endpoints this bit indicates that the descriptor structure and data
88122  * buffer with
88123  *
88124  * data ready to transmit is setup.
88125  *
88126  * For OUT endpoint it indicates that the descriptor structure and data buffer to
88127  *
88128  * receive data is setup.
88129  *
88130  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
88131  *
88132  * DMA mode:
88133  *
88134  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
88135  * the
88136  *
88137  * endpoint.
88138  *
88139  * * For OUT endpoints, this bit indicates that the application has allocated the
88140  *
88141  * memory to start receiving data from the USB.
88142  *
88143  * * The core clears this bit before setting any of the following interrupts on
88144  * this
88145  *
88146  * endpoint:
88147  *
88148  * SETUP Phase Done
88149  *
88150  * Endpoint Disabled
88151  *
88152  * Transfer Completed
88153  *
88154  * Note: For control endpoints in DMA mode, this bit must be set to be able to
88155  * transfer
88156  *
88157  * SETUP data packets in memory.
88158  *
88159  * Field Enumeration Values:
88160  *
88161  * Enum | Value | Description
88162  * :-----------------------------------|:------|:-------------------------
88163  * ALT_USB_DEV_DIEPCTL8_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
88164  * ALT_USB_DEV_DIEPCTL8_EPENA_E_ACT | 0x1 | Endpoint Enable active
88165  *
88166  * Field Access Macros:
88167  *
88168  */
88169 /*
88170  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPENA
88171  *
88172  * Endpoint Enable inactive
88173  */
88174 #define ALT_USB_DEV_DIEPCTL8_EPENA_E_INACT 0x0
88175 /*
88176  * Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPENA
88177  *
88178  * Endpoint Enable active
88179  */
88180 #define ALT_USB_DEV_DIEPCTL8_EPENA_E_ACT 0x1
88181 
88182 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */
88183 #define ALT_USB_DEV_DIEPCTL8_EPENA_LSB 31
88184 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */
88185 #define ALT_USB_DEV_DIEPCTL8_EPENA_MSB 31
88186 /* The width in bits of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */
88187 #define ALT_USB_DEV_DIEPCTL8_EPENA_WIDTH 1
88188 /* The mask used to set the ALT_USB_DEV_DIEPCTL8_EPENA register field value. */
88189 #define ALT_USB_DEV_DIEPCTL8_EPENA_SET_MSK 0x80000000
88190 /* The mask used to clear the ALT_USB_DEV_DIEPCTL8_EPENA register field value. */
88191 #define ALT_USB_DEV_DIEPCTL8_EPENA_CLR_MSK 0x7fffffff
88192 /* The reset value of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */
88193 #define ALT_USB_DEV_DIEPCTL8_EPENA_RESET 0x0
88194 /* Extracts the ALT_USB_DEV_DIEPCTL8_EPENA field value from a register. */
88195 #define ALT_USB_DEV_DIEPCTL8_EPENA_GET(value) (((value) & 0x80000000) >> 31)
88196 /* Produces a ALT_USB_DEV_DIEPCTL8_EPENA register field value suitable for setting the register. */
88197 #define ALT_USB_DEV_DIEPCTL8_EPENA_SET(value) (((value) << 31) & 0x80000000)
88198 
88199 #ifndef __ASSEMBLY__
88200 /*
88201  * WARNING: The C register and register group struct declarations are provided for
88202  * convenience and illustrative purposes. They should, however, be used with
88203  * caution as the C language standard provides no guarantees about the alignment or
88204  * atomicity of device memory accesses. The recommended practice for writing
88205  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
88206  * alt_write_word() functions.
88207  *
88208  * The struct declaration for register ALT_USB_DEV_DIEPCTL8.
88209  */
88210 struct ALT_USB_DEV_DIEPCTL8_s
88211 {
88212  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL8_MPS */
88213  uint32_t : 4; /* *UNDEFINED* */
88214  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL8_USBACTEP */
88215  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL8_DPID */
88216  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL8_NAKSTS */
88217  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL8_EPTYPE */
88218  uint32_t : 1; /* *UNDEFINED* */
88219  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL8_STALL */
88220  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL8_TXFNUM */
88221  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL8_CNAK */
88222  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL8_SNAK */
88223  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL8_SETD0PID */
88224  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL8_SETD1PID */
88225  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL8_EPDIS */
88226  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL8_EPENA */
88227 };
88228 
88229 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL8. */
88230 typedef volatile struct ALT_USB_DEV_DIEPCTL8_s ALT_USB_DEV_DIEPCTL8_t;
88231 #endif /* __ASSEMBLY__ */
88232 
88233 /* The reset value of the ALT_USB_DEV_DIEPCTL8 register. */
88234 #define ALT_USB_DEV_DIEPCTL8_RESET 0x00000000
88235 /* The byte offset of the ALT_USB_DEV_DIEPCTL8 register from the beginning of the component. */
88236 #define ALT_USB_DEV_DIEPCTL8_OFST 0x200
88237 /* The address of the ALT_USB_DEV_DIEPCTL8 register. */
88238 #define ALT_USB_DEV_DIEPCTL8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL8_OFST))
88239 
88240 /*
88241  * Register : diepint8
88242  *
88243  * Device IN Endpoint 8 Interrupt Register
88244  *
88245  * Register Layout
88246  *
88247  * Bits | Access | Reset | Description
88248  * :--------|:-------|:------|:---------------------------------
88249  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_XFERCOMPL
88250  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_EPDISBLD
88251  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_AHBERR
88252  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_TMO
88253  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_INTKNTXFEMP
88254  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_INTKNEPMIS
88255  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_INEPNAKEFF
88256  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT8_TXFEMP
88257  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN
88258  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_BNAINTR
88259  * [10] | ??? | 0x0 | *UNDEFINED*
88260  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_PKTDRPSTS
88261  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_BBLEERR
88262  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_NAKINTRPT
88263  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_NYETINTRPT
88264  * [31:15] | ??? | 0x0 | *UNDEFINED*
88265  *
88266  */
88267 /*
88268  * Field : xfercompl
88269  *
88270  * Transfer Completed Interrupt (XferCompl)
88271  *
88272  * Applies to IN and OUT endpoints.
88273  *
88274  * When Scatter/Gather DMA mode is enabled
88275  *
88276  * * For IN endpoint this field indicates that the requested data
88277  *
88278  * from the descriptor is moved from external system memory
88279  *
88280  * to internal FIFO.
88281  *
88282  * * For OUT endpoint this field indicates that the requested
88283  *
88284  * data from the internal FIFO is moved to external system
88285  *
88286  * memory. This interrupt is generated only when the
88287  *
88288  * corresponding endpoint descriptor is closed, and the IOC
88289  *
88290  * bit For the corresponding descriptor is Set.
88291  *
88292  * When Scatter/Gather DMA mode is disabled, this field
88293  *
88294  * indicates that the programmed transfer is complete on the
88295  *
88296  * AHB as well as on the USB, For this endpoint.
88297  *
88298  * Field Enumeration Values:
88299  *
88300  * Enum | Value | Description
88301  * :---------------------------------------|:------|:-----------------------------
88302  * ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_INACT | 0x0 | No Interrupt
88303  * ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
88304  *
88305  * Field Access Macros:
88306  *
88307  */
88308 /*
88309  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_XFERCOMPL
88310  *
88311  * No Interrupt
88312  */
88313 #define ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_INACT 0x0
88314 /*
88315  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_XFERCOMPL
88316  *
88317  * Transfer Completed Interrupt
88318  */
88319 #define ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_ACT 0x1
88320 
88321 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */
88322 #define ALT_USB_DEV_DIEPINT8_XFERCOMPL_LSB 0
88323 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */
88324 #define ALT_USB_DEV_DIEPINT8_XFERCOMPL_MSB 0
88325 /* The width in bits of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */
88326 #define ALT_USB_DEV_DIEPINT8_XFERCOMPL_WIDTH 1
88327 /* The mask used to set the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field value. */
88328 #define ALT_USB_DEV_DIEPINT8_XFERCOMPL_SET_MSK 0x00000001
88329 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field value. */
88330 #define ALT_USB_DEV_DIEPINT8_XFERCOMPL_CLR_MSK 0xfffffffe
88331 /* The reset value of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */
88332 #define ALT_USB_DEV_DIEPINT8_XFERCOMPL_RESET 0x0
88333 /* Extracts the ALT_USB_DEV_DIEPINT8_XFERCOMPL field value from a register. */
88334 #define ALT_USB_DEV_DIEPINT8_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
88335 /* Produces a ALT_USB_DEV_DIEPINT8_XFERCOMPL register field value suitable for setting the register. */
88336 #define ALT_USB_DEV_DIEPINT8_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
88337 
88338 /*
88339  * Field : epdisbld
88340  *
88341  * Endpoint Disabled Interrupt (EPDisbld)
88342  *
88343  * Applies to IN and OUT endpoints.
88344  *
88345  * This bit indicates that the endpoint is disabled per the
88346  *
88347  * application's request.
88348  *
88349  * Field Enumeration Values:
88350  *
88351  * Enum | Value | Description
88352  * :--------------------------------------|:------|:----------------------------
88353  * ALT_USB_DEV_DIEPINT8_EPDISBLD_E_INACT | 0x0 | No Interrupt
88354  * ALT_USB_DEV_DIEPINT8_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
88355  *
88356  * Field Access Macros:
88357  *
88358  */
88359 /*
88360  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_EPDISBLD
88361  *
88362  * No Interrupt
88363  */
88364 #define ALT_USB_DEV_DIEPINT8_EPDISBLD_E_INACT 0x0
88365 /*
88366  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_EPDISBLD
88367  *
88368  * Endpoint Disabled Interrupt
88369  */
88370 #define ALT_USB_DEV_DIEPINT8_EPDISBLD_E_ACT 0x1
88371 
88372 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */
88373 #define ALT_USB_DEV_DIEPINT8_EPDISBLD_LSB 1
88374 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */
88375 #define ALT_USB_DEV_DIEPINT8_EPDISBLD_MSB 1
88376 /* The width in bits of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */
88377 #define ALT_USB_DEV_DIEPINT8_EPDISBLD_WIDTH 1
88378 /* The mask used to set the ALT_USB_DEV_DIEPINT8_EPDISBLD register field value. */
88379 #define ALT_USB_DEV_DIEPINT8_EPDISBLD_SET_MSK 0x00000002
88380 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_EPDISBLD register field value. */
88381 #define ALT_USB_DEV_DIEPINT8_EPDISBLD_CLR_MSK 0xfffffffd
88382 /* The reset value of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */
88383 #define ALT_USB_DEV_DIEPINT8_EPDISBLD_RESET 0x0
88384 /* Extracts the ALT_USB_DEV_DIEPINT8_EPDISBLD field value from a register. */
88385 #define ALT_USB_DEV_DIEPINT8_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
88386 /* Produces a ALT_USB_DEV_DIEPINT8_EPDISBLD register field value suitable for setting the register. */
88387 #define ALT_USB_DEV_DIEPINT8_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
88388 
88389 /*
88390  * Field : ahberr
88391  *
88392  * AHB Error (AHBErr)
88393  *
88394  * Applies to IN and OUT endpoints.
88395  *
88396  * This is generated only in Internal DMA mode when there is an
88397  *
88398  * AHB error during an AHB read/write. The application can read
88399  *
88400  * the corresponding endpoint DMA address register to get the
88401  *
88402  * error address.
88403  *
88404  * Field Enumeration Values:
88405  *
88406  * Enum | Value | Description
88407  * :------------------------------------|:------|:--------------------
88408  * ALT_USB_DEV_DIEPINT8_AHBERR_E_INACT | 0x0 | No Interrupt
88409  * ALT_USB_DEV_DIEPINT8_AHBERR_E_ACT | 0x1 | AHB Error interrupt
88410  *
88411  * Field Access Macros:
88412  *
88413  */
88414 /*
88415  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_AHBERR
88416  *
88417  * No Interrupt
88418  */
88419 #define ALT_USB_DEV_DIEPINT8_AHBERR_E_INACT 0x0
88420 /*
88421  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_AHBERR
88422  *
88423  * AHB Error interrupt
88424  */
88425 #define ALT_USB_DEV_DIEPINT8_AHBERR_E_ACT 0x1
88426 
88427 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */
88428 #define ALT_USB_DEV_DIEPINT8_AHBERR_LSB 2
88429 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */
88430 #define ALT_USB_DEV_DIEPINT8_AHBERR_MSB 2
88431 /* The width in bits of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */
88432 #define ALT_USB_DEV_DIEPINT8_AHBERR_WIDTH 1
88433 /* The mask used to set the ALT_USB_DEV_DIEPINT8_AHBERR register field value. */
88434 #define ALT_USB_DEV_DIEPINT8_AHBERR_SET_MSK 0x00000004
88435 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_AHBERR register field value. */
88436 #define ALT_USB_DEV_DIEPINT8_AHBERR_CLR_MSK 0xfffffffb
88437 /* The reset value of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */
88438 #define ALT_USB_DEV_DIEPINT8_AHBERR_RESET 0x0
88439 /* Extracts the ALT_USB_DEV_DIEPINT8_AHBERR field value from a register. */
88440 #define ALT_USB_DEV_DIEPINT8_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
88441 /* Produces a ALT_USB_DEV_DIEPINT8_AHBERR register field value suitable for setting the register. */
88442 #define ALT_USB_DEV_DIEPINT8_AHBERR_SET(value) (((value) << 2) & 0x00000004)
88443 
88444 /*
88445  * Field : timeout
88446  *
88447  * Timeout Condition (TimeOUT)
88448  *
88449  * In shared TX FIFO mode, applies to non-isochronous IN
88450  *
88451  * endpoints only.
88452  *
88453  * In dedicated FIFO mode, applies only to Control IN
88454  *
88455  * endpoints.
88456  *
88457  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
88458  *
88459  * asserted.
88460  *
88461  * Indicates that the core has detected a timeout condition on the
88462  *
88463  * USB For the last IN token on this endpoint.
88464  *
88465  * Field Enumeration Values:
88466  *
88467  * Enum | Value | Description
88468  * :---------------------------------|:------|:------------------
88469  * ALT_USB_DEV_DIEPINT8_TMO_E_INACT | 0x0 | No interrupt
88470  * ALT_USB_DEV_DIEPINT8_TMO_E_ACT | 0x1 | Timeout interrupy
88471  *
88472  * Field Access Macros:
88473  *
88474  */
88475 /*
88476  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TMO
88477  *
88478  * No interrupt
88479  */
88480 #define ALT_USB_DEV_DIEPINT8_TMO_E_INACT 0x0
88481 /*
88482  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TMO
88483  *
88484  * Timeout interrupy
88485  */
88486 #define ALT_USB_DEV_DIEPINT8_TMO_E_ACT 0x1
88487 
88488 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_TMO register field. */
88489 #define ALT_USB_DEV_DIEPINT8_TMO_LSB 3
88490 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_TMO register field. */
88491 #define ALT_USB_DEV_DIEPINT8_TMO_MSB 3
88492 /* The width in bits of the ALT_USB_DEV_DIEPINT8_TMO register field. */
88493 #define ALT_USB_DEV_DIEPINT8_TMO_WIDTH 1
88494 /* The mask used to set the ALT_USB_DEV_DIEPINT8_TMO register field value. */
88495 #define ALT_USB_DEV_DIEPINT8_TMO_SET_MSK 0x00000008
88496 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_TMO register field value. */
88497 #define ALT_USB_DEV_DIEPINT8_TMO_CLR_MSK 0xfffffff7
88498 /* The reset value of the ALT_USB_DEV_DIEPINT8_TMO register field. */
88499 #define ALT_USB_DEV_DIEPINT8_TMO_RESET 0x0
88500 /* Extracts the ALT_USB_DEV_DIEPINT8_TMO field value from a register. */
88501 #define ALT_USB_DEV_DIEPINT8_TMO_GET(value) (((value) & 0x00000008) >> 3)
88502 /* Produces a ALT_USB_DEV_DIEPINT8_TMO register field value suitable for setting the register. */
88503 #define ALT_USB_DEV_DIEPINT8_TMO_SET(value) (((value) << 3) & 0x00000008)
88504 
88505 /*
88506  * Field : intkntxfemp
88507  *
88508  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
88509  *
88510  * Applies to non-periodic IN endpoints only.
88511  *
88512  * Indicates that an IN token was received when the associated
88513  *
88514  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
88515  *
88516  * asserted on the endpoint For which the IN token was received.
88517  *
88518  * Field Enumeration Values:
88519  *
88520  * Enum | Value | Description
88521  * :-----------------------------------------|:------|:----------------------------
88522  * ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
88523  * ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
88524  *
88525  * Field Access Macros:
88526  *
88527  */
88528 /*
88529  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNTXFEMP
88530  *
88531  * No interrupt
88532  */
88533 #define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_INACT 0x0
88534 /*
88535  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNTXFEMP
88536  *
88537  * IN Token Received Interrupt
88538  */
88539 #define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_ACT 0x1
88540 
88541 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */
88542 #define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_LSB 4
88543 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */
88544 #define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_MSB 4
88545 /* The width in bits of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */
88546 #define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_WIDTH 1
88547 /* The mask used to set the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field value. */
88548 #define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_SET_MSK 0x00000010
88549 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field value. */
88550 #define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_CLR_MSK 0xffffffef
88551 /* The reset value of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */
88552 #define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_RESET 0x0
88553 /* Extracts the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP field value from a register. */
88554 #define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
88555 /* Produces a ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field value suitable for setting the register. */
88556 #define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
88557 
88558 /*
88559  * Field : intknepmis
88560  *
88561  * IN Token Received with EP Mismatch (INTknEPMis)
88562  *
88563  * Applies to non-periodic IN endpoints only.
88564  *
88565  * Indicates that the data in the top of the non-periodic TxFIFO
88566  *
88567  * belongs to an endpoint other than the one For which the IN token
88568  *
88569  * was received. This interrupt is asserted on the endpoint For
88570  *
88571  * which the IN token was received.
88572  *
88573  * Field Enumeration Values:
88574  *
88575  * Enum | Value | Description
88576  * :----------------------------------------|:------|:---------------------------------------------
88577  * ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_INACT | 0x0 | No interrupt
88578  * ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
88579  *
88580  * Field Access Macros:
88581  *
88582  */
88583 /*
88584  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNEPMIS
88585  *
88586  * No interrupt
88587  */
88588 #define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_INACT 0x0
88589 /*
88590  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNEPMIS
88591  *
88592  * IN Token Received with EP Mismatch interrupt
88593  */
88594 #define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_ACT 0x1
88595 
88596 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */
88597 #define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_LSB 5
88598 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */
88599 #define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_MSB 5
88600 /* The width in bits of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */
88601 #define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_WIDTH 1
88602 /* The mask used to set the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field value. */
88603 #define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_SET_MSK 0x00000020
88604 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field value. */
88605 #define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_CLR_MSK 0xffffffdf
88606 /* The reset value of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */
88607 #define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_RESET 0x0
88608 /* Extracts the ALT_USB_DEV_DIEPINT8_INTKNEPMIS field value from a register. */
88609 #define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
88610 /* Produces a ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field value suitable for setting the register. */
88611 #define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
88612 
88613 /*
88614  * Field : inepnakeff
88615  *
88616  * IN Endpoint NAK Effective (INEPNakEff)
88617  *
88618  * Applies to periodic IN endpoints only.
88619  *
88620  * This bit can be cleared when the application clears the IN
88621  *
88622  * endpoint NAK by writing to DIEPCTLn.CNAK.
88623  *
88624  * This interrupt indicates that the core has sampled the NAK bit
88625  *
88626  * Set (either by the application or by the core). The interrupt
88627  *
88628  * indicates that the IN endpoint NAK bit Set by the application has
88629  *
88630  * taken effect in the core.
88631  *
88632  * This interrupt does not guarantee that a NAK handshake is sent
88633  *
88634  * on the USB. A STALL bit takes priority over a NAK bit.
88635  *
88636  * Field Enumeration Values:
88637  *
88638  * Enum | Value | Description
88639  * :----------------------------------------|:------|:------------------------------------
88640  * ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_INACT | 0x0 | No interrupt
88641  * ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
88642  *
88643  * Field Access Macros:
88644  *
88645  */
88646 /*
88647  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INEPNAKEFF
88648  *
88649  * No interrupt
88650  */
88651 #define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_INACT 0x0
88652 /*
88653  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_INEPNAKEFF
88654  *
88655  * IN Endpoint NAK Effective interrupt
88656  */
88657 #define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_ACT 0x1
88658 
88659 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */
88660 #define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_LSB 6
88661 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */
88662 #define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_MSB 6
88663 /* The width in bits of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */
88664 #define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_WIDTH 1
88665 /* The mask used to set the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field value. */
88666 #define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_SET_MSK 0x00000040
88667 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field value. */
88668 #define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_CLR_MSK 0xffffffbf
88669 /* The reset value of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */
88670 #define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_RESET 0x0
88671 /* Extracts the ALT_USB_DEV_DIEPINT8_INEPNAKEFF field value from a register. */
88672 #define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
88673 /* Produces a ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field value suitable for setting the register. */
88674 #define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
88675 
88676 /*
88677  * Field : txfemp
88678  *
88679  * Transmit FIFO Empty (TxFEmp)
88680  *
88681  * This bit is valid only For IN Endpoints
88682  *
88683  * This interrupt is asserted when the TxFIFO For this endpoint is
88684  *
88685  * either half or completely empty. The half or completely empty
88686  *
88687  * status is determined by the TxFIFO Empty Level bit in the Core
88688  *
88689  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
88690  *
88691  * Field Enumeration Values:
88692  *
88693  * Enum | Value | Description
88694  * :------------------------------------|:------|:------------------------------
88695  * ALT_USB_DEV_DIEPINT8_TXFEMP_E_INACT | 0x0 | No interrupt
88696  * ALT_USB_DEV_DIEPINT8_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
88697  *
88698  * Field Access Macros:
88699  *
88700  */
88701 /*
88702  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFEMP
88703  *
88704  * No interrupt
88705  */
88706 #define ALT_USB_DEV_DIEPINT8_TXFEMP_E_INACT 0x0
88707 /*
88708  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFEMP
88709  *
88710  * Transmit FIFO Empty interrupt
88711  */
88712 #define ALT_USB_DEV_DIEPINT8_TXFEMP_E_ACT 0x1
88713 
88714 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */
88715 #define ALT_USB_DEV_DIEPINT8_TXFEMP_LSB 7
88716 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */
88717 #define ALT_USB_DEV_DIEPINT8_TXFEMP_MSB 7
88718 /* The width in bits of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */
88719 #define ALT_USB_DEV_DIEPINT8_TXFEMP_WIDTH 1
88720 /* The mask used to set the ALT_USB_DEV_DIEPINT8_TXFEMP register field value. */
88721 #define ALT_USB_DEV_DIEPINT8_TXFEMP_SET_MSK 0x00000080
88722 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_TXFEMP register field value. */
88723 #define ALT_USB_DEV_DIEPINT8_TXFEMP_CLR_MSK 0xffffff7f
88724 /* The reset value of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */
88725 #define ALT_USB_DEV_DIEPINT8_TXFEMP_RESET 0x1
88726 /* Extracts the ALT_USB_DEV_DIEPINT8_TXFEMP field value from a register. */
88727 #define ALT_USB_DEV_DIEPINT8_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
88728 /* Produces a ALT_USB_DEV_DIEPINT8_TXFEMP register field value suitable for setting the register. */
88729 #define ALT_USB_DEV_DIEPINT8_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
88730 
88731 /*
88732  * Field : txfifoundrn
88733  *
88734  * Fifo Underrun (TxfifoUndrn)
88735  *
88736  * Applies to IN endpoints Only
88737  *
88738  * This bit is valid only If thresholding is enabled. The core generates this
88739  * interrupt when
88740  *
88741  * it detects a transmit FIFO underrun condition For this endpoint.
88742  *
88743  * Field Enumeration Values:
88744  *
88745  * Enum | Value | Description
88746  * :-----------------------------------------|:------|:------------------------
88747  * ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
88748  * ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
88749  *
88750  * Field Access Macros:
88751  *
88752  */
88753 /*
88754  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN
88755  *
88756  * No interrupt
88757  */
88758 #define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_INACT 0x0
88759 /*
88760  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN
88761  *
88762  * Fifo Underrun interrupt
88763  */
88764 #define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_ACT 0x1
88765 
88766 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */
88767 #define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_LSB 8
88768 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */
88769 #define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_MSB 8
88770 /* The width in bits of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */
88771 #define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_WIDTH 1
88772 /* The mask used to set the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field value. */
88773 #define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_SET_MSK 0x00000100
88774 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field value. */
88775 #define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_CLR_MSK 0xfffffeff
88776 /* The reset value of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */
88777 #define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_RESET 0x0
88778 /* Extracts the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN field value from a register. */
88779 #define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
88780 /* Produces a ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field value suitable for setting the register. */
88781 #define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
88782 
88783 /*
88784  * Field : bnaintr
88785  *
88786  * BNA (Buffer Not Available) Interrupt (BNAIntr)
88787  *
88788  * This bit is valid only when Scatter/Gather DMA mode is enabled.
88789  *
88790  * The core generates this interrupt when the descriptor accessed
88791  *
88792  * is not ready For the Core to process, such as Host busy or DMA
88793  *
88794  * done
88795  *
88796  * Field Enumeration Values:
88797  *
88798  * Enum | Value | Description
88799  * :-------------------------------------|:------|:--------------
88800  * ALT_USB_DEV_DIEPINT8_BNAINTR_E_INACT | 0x0 | No interrupt
88801  * ALT_USB_DEV_DIEPINT8_BNAINTR_E_ACT | 0x1 | BNA interrupt
88802  *
88803  * Field Access Macros:
88804  *
88805  */
88806 /*
88807  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_BNAINTR
88808  *
88809  * No interrupt
88810  */
88811 #define ALT_USB_DEV_DIEPINT8_BNAINTR_E_INACT 0x0
88812 /*
88813  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_BNAINTR
88814  *
88815  * BNA interrupt
88816  */
88817 #define ALT_USB_DEV_DIEPINT8_BNAINTR_E_ACT 0x1
88818 
88819 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */
88820 #define ALT_USB_DEV_DIEPINT8_BNAINTR_LSB 9
88821 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */
88822 #define ALT_USB_DEV_DIEPINT8_BNAINTR_MSB 9
88823 /* The width in bits of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */
88824 #define ALT_USB_DEV_DIEPINT8_BNAINTR_WIDTH 1
88825 /* The mask used to set the ALT_USB_DEV_DIEPINT8_BNAINTR register field value. */
88826 #define ALT_USB_DEV_DIEPINT8_BNAINTR_SET_MSK 0x00000200
88827 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_BNAINTR register field value. */
88828 #define ALT_USB_DEV_DIEPINT8_BNAINTR_CLR_MSK 0xfffffdff
88829 /* The reset value of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */
88830 #define ALT_USB_DEV_DIEPINT8_BNAINTR_RESET 0x0
88831 /* Extracts the ALT_USB_DEV_DIEPINT8_BNAINTR field value from a register. */
88832 #define ALT_USB_DEV_DIEPINT8_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
88833 /* Produces a ALT_USB_DEV_DIEPINT8_BNAINTR register field value suitable for setting the register. */
88834 #define ALT_USB_DEV_DIEPINT8_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
88835 
88836 /*
88837  * Field : pktdrpsts
88838  *
88839  * Packet Drop Status (PktDrpSts)
88840  *
88841  * This bit indicates to the application that an ISOC OUT packet has been dropped.
88842  * This
88843  *
88844  * bit does not have an associated mask bit and does not generate an interrupt.
88845  *
88846  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
88847  * transfer
88848  *
88849  * interrupt feature is selected.
88850  *
88851  * Field Enumeration Values:
88852  *
88853  * Enum | Value | Description
88854  * :---------------------------------------|:------|:-----------------------------
88855  * ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_INACT | 0x0 | No interrupt
88856  * ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
88857  *
88858  * Field Access Macros:
88859  *
88860  */
88861 /*
88862  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_PKTDRPSTS
88863  *
88864  * No interrupt
88865  */
88866 #define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_INACT 0x0
88867 /*
88868  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_PKTDRPSTS
88869  *
88870  * Packet Drop Status interrupt
88871  */
88872 #define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_ACT 0x1
88873 
88874 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */
88875 #define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_LSB 11
88876 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */
88877 #define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_MSB 11
88878 /* The width in bits of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */
88879 #define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_WIDTH 1
88880 /* The mask used to set the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field value. */
88881 #define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_SET_MSK 0x00000800
88882 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field value. */
88883 #define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_CLR_MSK 0xfffff7ff
88884 /* The reset value of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */
88885 #define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_RESET 0x0
88886 /* Extracts the ALT_USB_DEV_DIEPINT8_PKTDRPSTS field value from a register. */
88887 #define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
88888 /* Produces a ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field value suitable for setting the register. */
88889 #define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
88890 
88891 /*
88892  * Field : bbleerr
88893  *
88894  * NAK Interrupt (BbleErr)
88895  *
88896  * The core generates this interrupt when babble is received for the endpoint.
88897  *
88898  * Field Enumeration Values:
88899  *
88900  * Enum | Value | Description
88901  * :-------------------------------------|:------|:------------------
88902  * ALT_USB_DEV_DIEPINT8_BBLEERR_E_INACT | 0x0 | No interrupt
88903  * ALT_USB_DEV_DIEPINT8_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
88904  *
88905  * Field Access Macros:
88906  *
88907  */
88908 /*
88909  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_BBLEERR
88910  *
88911  * No interrupt
88912  */
88913 #define ALT_USB_DEV_DIEPINT8_BBLEERR_E_INACT 0x0
88914 /*
88915  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_BBLEERR
88916  *
88917  * BbleErr interrupt
88918  */
88919 #define ALT_USB_DEV_DIEPINT8_BBLEERR_E_ACT 0x1
88920 
88921 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */
88922 #define ALT_USB_DEV_DIEPINT8_BBLEERR_LSB 12
88923 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */
88924 #define ALT_USB_DEV_DIEPINT8_BBLEERR_MSB 12
88925 /* The width in bits of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */
88926 #define ALT_USB_DEV_DIEPINT8_BBLEERR_WIDTH 1
88927 /* The mask used to set the ALT_USB_DEV_DIEPINT8_BBLEERR register field value. */
88928 #define ALT_USB_DEV_DIEPINT8_BBLEERR_SET_MSK 0x00001000
88929 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_BBLEERR register field value. */
88930 #define ALT_USB_DEV_DIEPINT8_BBLEERR_CLR_MSK 0xffffefff
88931 /* The reset value of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */
88932 #define ALT_USB_DEV_DIEPINT8_BBLEERR_RESET 0x0
88933 /* Extracts the ALT_USB_DEV_DIEPINT8_BBLEERR field value from a register. */
88934 #define ALT_USB_DEV_DIEPINT8_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
88935 /* Produces a ALT_USB_DEV_DIEPINT8_BBLEERR register field value suitable for setting the register. */
88936 #define ALT_USB_DEV_DIEPINT8_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
88937 
88938 /*
88939  * Field : nakintrpt
88940  *
88941  * NAK Interrupt (NAKInterrupt)
88942  *
88943  * The core generates this interrupt when a NAK is transmitted or received by the
88944  * device.
88945  *
88946  * In case of isochronous IN endpoints the interrupt gets generated when a zero
88947  * length
88948  *
88949  * packet is transmitted due to un-availability of data in the TXFifo.
88950  *
88951  * Field Enumeration Values:
88952  *
88953  * Enum | Value | Description
88954  * :---------------------------------------|:------|:--------------
88955  * ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_INACT | 0x0 | No interrupt
88956  * ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
88957  *
88958  * Field Access Macros:
88959  *
88960  */
88961 /*
88962  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_NAKINTRPT
88963  *
88964  * No interrupt
88965  */
88966 #define ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_INACT 0x0
88967 /*
88968  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_NAKINTRPT
88969  *
88970  * NAK Interrupt
88971  */
88972 #define ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_ACT 0x1
88973 
88974 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */
88975 #define ALT_USB_DEV_DIEPINT8_NAKINTRPT_LSB 13
88976 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */
88977 #define ALT_USB_DEV_DIEPINT8_NAKINTRPT_MSB 13
88978 /* The width in bits of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */
88979 #define ALT_USB_DEV_DIEPINT8_NAKINTRPT_WIDTH 1
88980 /* The mask used to set the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field value. */
88981 #define ALT_USB_DEV_DIEPINT8_NAKINTRPT_SET_MSK 0x00002000
88982 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field value. */
88983 #define ALT_USB_DEV_DIEPINT8_NAKINTRPT_CLR_MSK 0xffffdfff
88984 /* The reset value of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */
88985 #define ALT_USB_DEV_DIEPINT8_NAKINTRPT_RESET 0x0
88986 /* Extracts the ALT_USB_DEV_DIEPINT8_NAKINTRPT field value from a register. */
88987 #define ALT_USB_DEV_DIEPINT8_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
88988 /* Produces a ALT_USB_DEV_DIEPINT8_NAKINTRPT register field value suitable for setting the register. */
88989 #define ALT_USB_DEV_DIEPINT8_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
88990 
88991 /*
88992  * Field : nyetintrpt
88993  *
88994  * NYET Interrupt (NYETIntrpt)
88995  *
88996  * The core generates this interrupt when a NYET response is transmitted for a non
88997  * isochronous OUT endpoint.
88998  *
88999  * Field Enumeration Values:
89000  *
89001  * Enum | Value | Description
89002  * :----------------------------------------|:------|:---------------
89003  * ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_INACT | 0x0 | No interrupt
89004  * ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
89005  *
89006  * Field Access Macros:
89007  *
89008  */
89009 /*
89010  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_NYETINTRPT
89011  *
89012  * No interrupt
89013  */
89014 #define ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_INACT 0x0
89015 /*
89016  * Enumerated value for register field ALT_USB_DEV_DIEPINT8_NYETINTRPT
89017  *
89018  * NYET Interrupt
89019  */
89020 #define ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_ACT 0x1
89021 
89022 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */
89023 #define ALT_USB_DEV_DIEPINT8_NYETINTRPT_LSB 14
89024 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */
89025 #define ALT_USB_DEV_DIEPINT8_NYETINTRPT_MSB 14
89026 /* The width in bits of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */
89027 #define ALT_USB_DEV_DIEPINT8_NYETINTRPT_WIDTH 1
89028 /* The mask used to set the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field value. */
89029 #define ALT_USB_DEV_DIEPINT8_NYETINTRPT_SET_MSK 0x00004000
89030 /* The mask used to clear the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field value. */
89031 #define ALT_USB_DEV_DIEPINT8_NYETINTRPT_CLR_MSK 0xffffbfff
89032 /* The reset value of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */
89033 #define ALT_USB_DEV_DIEPINT8_NYETINTRPT_RESET 0x0
89034 /* Extracts the ALT_USB_DEV_DIEPINT8_NYETINTRPT field value from a register. */
89035 #define ALT_USB_DEV_DIEPINT8_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
89036 /* Produces a ALT_USB_DEV_DIEPINT8_NYETINTRPT register field value suitable for setting the register. */
89037 #define ALT_USB_DEV_DIEPINT8_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
89038 
89039 #ifndef __ASSEMBLY__
89040 /*
89041  * WARNING: The C register and register group struct declarations are provided for
89042  * convenience and illustrative purposes. They should, however, be used with
89043  * caution as the C language standard provides no guarantees about the alignment or
89044  * atomicity of device memory accesses. The recommended practice for writing
89045  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
89046  * alt_write_word() functions.
89047  *
89048  * The struct declaration for register ALT_USB_DEV_DIEPINT8.
89049  */
89050 struct ALT_USB_DEV_DIEPINT8_s
89051 {
89052  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT8_XFERCOMPL */
89053  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT8_EPDISBLD */
89054  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT8_AHBERR */
89055  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT8_TMO */
89056  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT8_INTKNTXFEMP */
89057  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT8_INTKNEPMIS */
89058  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT8_INEPNAKEFF */
89059  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT8_TXFEMP */
89060  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN */
89061  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT8_BNAINTR */
89062  uint32_t : 1; /* *UNDEFINED* */
89063  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT8_PKTDRPSTS */
89064  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT8_BBLEERR */
89065  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT8_NAKINTRPT */
89066  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT8_NYETINTRPT */
89067  uint32_t : 17; /* *UNDEFINED* */
89068 };
89069 
89070 /* The typedef declaration for register ALT_USB_DEV_DIEPINT8. */
89071 typedef volatile struct ALT_USB_DEV_DIEPINT8_s ALT_USB_DEV_DIEPINT8_t;
89072 #endif /* __ASSEMBLY__ */
89073 
89074 /* The reset value of the ALT_USB_DEV_DIEPINT8 register. */
89075 #define ALT_USB_DEV_DIEPINT8_RESET 0x00000080
89076 /* The byte offset of the ALT_USB_DEV_DIEPINT8 register from the beginning of the component. */
89077 #define ALT_USB_DEV_DIEPINT8_OFST 0x208
89078 /* The address of the ALT_USB_DEV_DIEPINT8 register. */
89079 #define ALT_USB_DEV_DIEPINT8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT8_OFST))
89080 
89081 /*
89082  * Register : dieptsiz8
89083  *
89084  * Device IN Endpoint 8 Transfer Size Register
89085  *
89086  * Register Layout
89087  *
89088  * Bits | Access | Reset | Description
89089  * :--------|:-------|:------|:-------------------------------
89090  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ8_XFERSIZE
89091  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ8_PKTCNT
89092  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ8_MC
89093  * [31] | ??? | 0x0 | *UNDEFINED*
89094  *
89095  */
89096 /*
89097  * Field : xfersize
89098  *
89099  * Transfer Size (XferSize)
89100  *
89101  * Indicates the transfer size in bytes For endpoint 0. The core
89102  *
89103  * interrupts the application only after it has exhausted the transfer
89104  *
89105  * size amount of data. The transfer size can be Set to the
89106  *
89107  * maximum packet size of the endpoint, to be interrupted at the
89108  *
89109  * end of each packet.
89110  *
89111  * The core decrements this field every time a packet from the
89112  *
89113  * external memory is written to the TxFIFO.
89114  *
89115  * Field Access Macros:
89116  *
89117  */
89118 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */
89119 #define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_LSB 0
89120 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */
89121 #define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_MSB 18
89122 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */
89123 #define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_WIDTH 19
89124 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field value. */
89125 #define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_SET_MSK 0x0007ffff
89126 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field value. */
89127 #define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_CLR_MSK 0xfff80000
89128 /* The reset value of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */
89129 #define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_RESET 0x0
89130 /* Extracts the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE field value from a register. */
89131 #define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
89132 /* Produces a ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field value suitable for setting the register. */
89133 #define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
89134 
89135 /*
89136  * Field : pktcnt
89137  *
89138  * Packet Count (PktCnt)
89139  *
89140  * Indicates the total number of USB packets that constitute the
89141  *
89142  * Transfer Size amount of data For endpoint 0.
89143  *
89144  * This field is decremented every time a packet (maximum size or
89145  *
89146  * short packet) is read from the TxFIFO.
89147  *
89148  * Field Access Macros:
89149  *
89150  */
89151 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */
89152 #define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_LSB 19
89153 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */
89154 #define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_MSB 28
89155 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */
89156 #define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_WIDTH 10
89157 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field value. */
89158 #define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_SET_MSK 0x1ff80000
89159 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field value. */
89160 #define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_CLR_MSK 0xe007ffff
89161 /* The reset value of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */
89162 #define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_RESET 0x0
89163 /* Extracts the ALT_USB_DEV_DIEPTSIZ8_PKTCNT field value from a register. */
89164 #define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
89165 /* Produces a ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field value suitable for setting the register. */
89166 #define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
89167 
89168 /*
89169  * Field : mc
89170  *
89171  * Applies to IN endpoints only.
89172  *
89173  * For periodic IN endpoints, this field indicates the number of packets that must
89174  * be transmitted per microframe on the USB. The core uses this field to calculate
89175  * the data PID for isochronous IN endpoints.
89176  *
89177  * 2'b01: 1 packet
89178  *
89179  * 2'b10: 2 packets
89180  *
89181  * 2'b11: 3 packets
89182  *
89183  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
89184  * specifies the number of packets the core must fetchfor an IN endpoint before it
89185  * switches to the endpoint pointed to by the Next Endpoint field of the Device
89186  * Endpoint-n Control register (DIEPCTLn.NextEp)
89187  *
89188  * Field Enumeration Values:
89189  *
89190  * Enum | Value | Description
89191  * :------------------------------------|:------|:------------
89192  * ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTONE | 0x1 | 1 packet
89193  * ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTWO | 0x2 | 2 packets
89194  * ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTHREE | 0x3 | 3 packets
89195  *
89196  * Field Access Macros:
89197  *
89198  */
89199 /*
89200  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ8_MC
89201  *
89202  * 1 packet
89203  */
89204 #define ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTONE 0x1
89205 /*
89206  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ8_MC
89207  *
89208  * 2 packets
89209  */
89210 #define ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTWO 0x2
89211 /*
89212  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ8_MC
89213  *
89214  * 3 packets
89215  */
89216 #define ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTHREE 0x3
89217 
89218 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */
89219 #define ALT_USB_DEV_DIEPTSIZ8_MC_LSB 29
89220 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */
89221 #define ALT_USB_DEV_DIEPTSIZ8_MC_MSB 30
89222 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */
89223 #define ALT_USB_DEV_DIEPTSIZ8_MC_WIDTH 2
89224 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ8_MC register field value. */
89225 #define ALT_USB_DEV_DIEPTSIZ8_MC_SET_MSK 0x60000000
89226 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ8_MC register field value. */
89227 #define ALT_USB_DEV_DIEPTSIZ8_MC_CLR_MSK 0x9fffffff
89228 /* The reset value of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */
89229 #define ALT_USB_DEV_DIEPTSIZ8_MC_RESET 0x0
89230 /* Extracts the ALT_USB_DEV_DIEPTSIZ8_MC field value from a register. */
89231 #define ALT_USB_DEV_DIEPTSIZ8_MC_GET(value) (((value) & 0x60000000) >> 29)
89232 /* Produces a ALT_USB_DEV_DIEPTSIZ8_MC register field value suitable for setting the register. */
89233 #define ALT_USB_DEV_DIEPTSIZ8_MC_SET(value) (((value) << 29) & 0x60000000)
89234 
89235 #ifndef __ASSEMBLY__
89236 /*
89237  * WARNING: The C register and register group struct declarations are provided for
89238  * convenience and illustrative purposes. They should, however, be used with
89239  * caution as the C language standard provides no guarantees about the alignment or
89240  * atomicity of device memory accesses. The recommended practice for writing
89241  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
89242  * alt_write_word() functions.
89243  *
89244  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ8.
89245  */
89246 struct ALT_USB_DEV_DIEPTSIZ8_s
89247 {
89248  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ8_XFERSIZE */
89249  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ8_PKTCNT */
89250  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ8_MC */
89251  uint32_t : 1; /* *UNDEFINED* */
89252 };
89253 
89254 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ8. */
89255 typedef volatile struct ALT_USB_DEV_DIEPTSIZ8_s ALT_USB_DEV_DIEPTSIZ8_t;
89256 #endif /* __ASSEMBLY__ */
89257 
89258 /* The reset value of the ALT_USB_DEV_DIEPTSIZ8 register. */
89259 #define ALT_USB_DEV_DIEPTSIZ8_RESET 0x00000000
89260 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ8 register from the beginning of the component. */
89261 #define ALT_USB_DEV_DIEPTSIZ8_OFST 0x210
89262 /* The address of the ALT_USB_DEV_DIEPTSIZ8 register. */
89263 #define ALT_USB_DEV_DIEPTSIZ8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ8_OFST))
89264 
89265 /*
89266  * Register : diepdma8
89267  *
89268  * Device IN Endpoint 8 DMA Address Register
89269  *
89270  * Register Layout
89271  *
89272  * Bits | Access | Reset | Description
89273  * :-------|:-------|:--------|:------------------------------
89274  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA8_DIEPDMA8
89275  *
89276  */
89277 /*
89278  * Field : diepdma8
89279  *
89280  * Holds the start address of the external memory for storing or fetching endpoint
89281  *
89282  * data.
89283  *
89284  * Note: For control endpoints, this field stores control OUT data packets as well
89285  * as
89286  *
89287  * SETUP transaction data packets. When more than three SETUP packets are
89288  *
89289  * received back-to-back, the SETUP data packet in the memory is overwritten.
89290  *
89291  * This register is incremented on every AHB transaction. The application can give
89292  *
89293  * only a DWORD-aligned address.
89294  *
89295  * When Scatter/Gather DMA mode is not enabled, the application programs the
89296  *
89297  * start address value in this field.
89298  *
89299  * When Scatter/Gather DMA mode is enabled, this field indicates the base
89300  *
89301  * pointer for the descriptor list.
89302  *
89303  * Field Access Macros:
89304  *
89305  */
89306 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field. */
89307 #define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_LSB 0
89308 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field. */
89309 #define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_MSB 31
89310 /* The width in bits of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field. */
89311 #define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_WIDTH 32
89312 /* The mask used to set the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field value. */
89313 #define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_SET_MSK 0xffffffff
89314 /* The mask used to clear the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field value. */
89315 #define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_CLR_MSK 0x00000000
89316 /* The reset value of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field is UNKNOWN. */
89317 #define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_RESET 0x0
89318 /* Extracts the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 field value from a register. */
89319 #define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_GET(value) (((value) & 0xffffffff) >> 0)
89320 /* Produces a ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field value suitable for setting the register. */
89321 #define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_SET(value) (((value) << 0) & 0xffffffff)
89322 
89323 #ifndef __ASSEMBLY__
89324 /*
89325  * WARNING: The C register and register group struct declarations are provided for
89326  * convenience and illustrative purposes. They should, however, be used with
89327  * caution as the C language standard provides no guarantees about the alignment or
89328  * atomicity of device memory accesses. The recommended practice for writing
89329  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
89330  * alt_write_word() functions.
89331  *
89332  * The struct declaration for register ALT_USB_DEV_DIEPDMA8.
89333  */
89334 struct ALT_USB_DEV_DIEPDMA8_s
89335 {
89336  uint32_t diepdma8 : 32; /* ALT_USB_DEV_DIEPDMA8_DIEPDMA8 */
89337 };
89338 
89339 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA8. */
89340 typedef volatile struct ALT_USB_DEV_DIEPDMA8_s ALT_USB_DEV_DIEPDMA8_t;
89341 #endif /* __ASSEMBLY__ */
89342 
89343 /* The reset value of the ALT_USB_DEV_DIEPDMA8 register. */
89344 #define ALT_USB_DEV_DIEPDMA8_RESET 0x00000000
89345 /* The byte offset of the ALT_USB_DEV_DIEPDMA8 register from the beginning of the component. */
89346 #define ALT_USB_DEV_DIEPDMA8_OFST 0x214
89347 /* The address of the ALT_USB_DEV_DIEPDMA8 register. */
89348 #define ALT_USB_DEV_DIEPDMA8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA8_OFST))
89349 
89350 /*
89351  * Register : dtxfsts8
89352  *
89353  * Device IN Endpoint Transmit FIFO Status Register 8
89354  *
89355  * Register Layout
89356  *
89357  * Bits | Access | Reset | Description
89358  * :--------|:-------|:-------|:-------------------------------------
89359  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL
89360  * [31:16] | ??? | 0x0 | *UNDEFINED*
89361  *
89362  */
89363 /*
89364  * Field : ineptxfspcavail
89365  *
89366  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
89367  *
89368  * Indicates the amount of free space available in the Endpoint
89369  *
89370  * TxFIFO.
89371  *
89372  * Values are in terms of 32-bit words.
89373  *
89374  * 16'h0: Endpoint TxFIFO is full
89375  *
89376  * 16'h1: 1 word available
89377  *
89378  * 16'h2: 2 words available
89379  *
89380  * 16'hn: n words available (where 0 n 32,768)
89381  *
89382  * 16'h8000: 32,768 words available
89383  *
89384  * Others: Reserved
89385  *
89386  * Field Access Macros:
89387  *
89388  */
89389 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */
89390 #define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_LSB 0
89391 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */
89392 #define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_MSB 15
89393 /* The width in bits of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */
89394 #define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_WIDTH 16
89395 /* The mask used to set the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field value. */
89396 #define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
89397 /* The mask used to clear the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field value. */
89398 #define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
89399 /* The reset value of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */
89400 #define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_RESET 0x2000
89401 /* Extracts the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL field value from a register. */
89402 #define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
89403 /* Produces a ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field value suitable for setting the register. */
89404 #define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
89405 
89406 #ifndef __ASSEMBLY__
89407 /*
89408  * WARNING: The C register and register group struct declarations are provided for
89409  * convenience and illustrative purposes. They should, however, be used with
89410  * caution as the C language standard provides no guarantees about the alignment or
89411  * atomicity of device memory accesses. The recommended practice for writing
89412  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
89413  * alt_write_word() functions.
89414  *
89415  * The struct declaration for register ALT_USB_DEV_DTXFSTS8.
89416  */
89417 struct ALT_USB_DEV_DTXFSTS8_s
89418 {
89419  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL */
89420  uint32_t : 16; /* *UNDEFINED* */
89421 };
89422 
89423 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS8. */
89424 typedef volatile struct ALT_USB_DEV_DTXFSTS8_s ALT_USB_DEV_DTXFSTS8_t;
89425 #endif /* __ASSEMBLY__ */
89426 
89427 /* The reset value of the ALT_USB_DEV_DTXFSTS8 register. */
89428 #define ALT_USB_DEV_DTXFSTS8_RESET 0x00002000
89429 /* The byte offset of the ALT_USB_DEV_DTXFSTS8 register from the beginning of the component. */
89430 #define ALT_USB_DEV_DTXFSTS8_OFST 0x218
89431 /* The address of the ALT_USB_DEV_DTXFSTS8 register. */
89432 #define ALT_USB_DEV_DTXFSTS8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS8_OFST))
89433 
89434 /*
89435  * Register : diepdmab8
89436  *
89437  * Device IN Endpoint 8 Buffer Address Register
89438  *
89439  * Register Layout
89440  *
89441  * Bits | Access | Reset | Description
89442  * :-------|:-------|:--------|:--------------------------------
89443  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8
89444  *
89445  */
89446 /*
89447  * Field : diepdmab8
89448  *
89449  * Holds the current buffer address.This register is updated as and when the data
89450  *
89451  * transfer for the corresponding end point is in progress.
89452  *
89453  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
89454  * is
89455  *
89456  * reserved.
89457  *
89458  * Field Access Macros:
89459  *
89460  */
89461 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field. */
89462 #define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_LSB 0
89463 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field. */
89464 #define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_MSB 31
89465 /* The width in bits of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field. */
89466 #define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_WIDTH 32
89467 /* The mask used to set the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field value. */
89468 #define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_SET_MSK 0xffffffff
89469 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field value. */
89470 #define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_CLR_MSK 0x00000000
89471 /* The reset value of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field is UNKNOWN. */
89472 #define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_RESET 0x0
89473 /* Extracts the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 field value from a register. */
89474 #define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_GET(value) (((value) & 0xffffffff) >> 0)
89475 /* Produces a ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field value suitable for setting the register. */
89476 #define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_SET(value) (((value) << 0) & 0xffffffff)
89477 
89478 #ifndef __ASSEMBLY__
89479 /*
89480  * WARNING: The C register and register group struct declarations are provided for
89481  * convenience and illustrative purposes. They should, however, be used with
89482  * caution as the C language standard provides no guarantees about the alignment or
89483  * atomicity of device memory accesses. The recommended practice for writing
89484  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
89485  * alt_write_word() functions.
89486  *
89487  * The struct declaration for register ALT_USB_DEV_DIEPDMAB8.
89488  */
89489 struct ALT_USB_DEV_DIEPDMAB8_s
89490 {
89491  const uint32_t diepdmab8 : 32; /* ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 */
89492 };
89493 
89494 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB8. */
89495 typedef volatile struct ALT_USB_DEV_DIEPDMAB8_s ALT_USB_DEV_DIEPDMAB8_t;
89496 #endif /* __ASSEMBLY__ */
89497 
89498 /* The reset value of the ALT_USB_DEV_DIEPDMAB8 register. */
89499 #define ALT_USB_DEV_DIEPDMAB8_RESET 0x00000000
89500 /* The byte offset of the ALT_USB_DEV_DIEPDMAB8 register from the beginning of the component. */
89501 #define ALT_USB_DEV_DIEPDMAB8_OFST 0x21c
89502 /* The address of the ALT_USB_DEV_DIEPDMAB8 register. */
89503 #define ALT_USB_DEV_DIEPDMAB8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB8_OFST))
89504 
89505 /*
89506  * Register : diepctl9
89507  *
89508  * Device Control IN Endpoint 9 Control Register
89509  *
89510  * Register Layout
89511  *
89512  * Bits | Access | Reset | Description
89513  * :--------|:---------|:------|:------------------------------
89514  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL9_MPS
89515  * [14:11] | ??? | 0x0 | *UNDEFINED*
89516  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL9_USBACTEP
89517  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL9_DPID
89518  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL9_NAKSTS
89519  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL9_EPTYPE
89520  * [20] | ??? | 0x0 | *UNDEFINED*
89521  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL9_STALL
89522  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL9_TXFNUM
89523  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL9_CNAK
89524  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL9_SNAK
89525  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL9_SETD0PID
89526  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL9_SETD1PID
89527  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL9_EPDIS
89528  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL9_EPENA
89529  *
89530  */
89531 /*
89532  * Field : mps
89533  *
89534  * Maximum Packet Size (MPS)
89535  *
89536  * The application must program this field with the maximum packet size for the
89537  * current
89538  *
89539  * logical endpoint. This value is in bytes.
89540  *
89541  * Field Access Macros:
89542  *
89543  */
89544 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_MPS register field. */
89545 #define ALT_USB_DEV_DIEPCTL9_MPS_LSB 0
89546 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_MPS register field. */
89547 #define ALT_USB_DEV_DIEPCTL9_MPS_MSB 10
89548 /* The width in bits of the ALT_USB_DEV_DIEPCTL9_MPS register field. */
89549 #define ALT_USB_DEV_DIEPCTL9_MPS_WIDTH 11
89550 /* The mask used to set the ALT_USB_DEV_DIEPCTL9_MPS register field value. */
89551 #define ALT_USB_DEV_DIEPCTL9_MPS_SET_MSK 0x000007ff
89552 /* The mask used to clear the ALT_USB_DEV_DIEPCTL9_MPS register field value. */
89553 #define ALT_USB_DEV_DIEPCTL9_MPS_CLR_MSK 0xfffff800
89554 /* The reset value of the ALT_USB_DEV_DIEPCTL9_MPS register field. */
89555 #define ALT_USB_DEV_DIEPCTL9_MPS_RESET 0x0
89556 /* Extracts the ALT_USB_DEV_DIEPCTL9_MPS field value from a register. */
89557 #define ALT_USB_DEV_DIEPCTL9_MPS_GET(value) (((value) & 0x000007ff) >> 0)
89558 /* Produces a ALT_USB_DEV_DIEPCTL9_MPS register field value suitable for setting the register. */
89559 #define ALT_USB_DEV_DIEPCTL9_MPS_SET(value) (((value) << 0) & 0x000007ff)
89560 
89561 /*
89562  * Field : usbactep
89563  *
89564  * USB Active Endpoint (USBActEP)
89565  *
89566  * Indicates whether this endpoint is active in the current configuration and
89567  * interface. The
89568  *
89569  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
89570  * reset. After
89571  *
89572  * receiving the SetConfiguration and SetInterface commands, the application must
89573  *
89574  * program endpoint registers accordingly and set this bit.
89575  *
89576  * Field Enumeration Values:
89577  *
89578  * Enum | Value | Description
89579  * :-------------------------------------|:------|:--------------------
89580  * ALT_USB_DEV_DIEPCTL9_USBACTEP_E_DISD | 0x0 | Not Active
89581  * ALT_USB_DEV_DIEPCTL9_USBACTEP_E_END | 0x1 | USB Active Endpoint
89582  *
89583  * Field Access Macros:
89584  *
89585  */
89586 /*
89587  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_USBACTEP
89588  *
89589  * Not Active
89590  */
89591 #define ALT_USB_DEV_DIEPCTL9_USBACTEP_E_DISD 0x0
89592 /*
89593  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_USBACTEP
89594  *
89595  * USB Active Endpoint
89596  */
89597 #define ALT_USB_DEV_DIEPCTL9_USBACTEP_E_END 0x1
89598 
89599 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */
89600 #define ALT_USB_DEV_DIEPCTL9_USBACTEP_LSB 15
89601 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */
89602 #define ALT_USB_DEV_DIEPCTL9_USBACTEP_MSB 15
89603 /* The width in bits of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */
89604 #define ALT_USB_DEV_DIEPCTL9_USBACTEP_WIDTH 1
89605 /* The mask used to set the ALT_USB_DEV_DIEPCTL9_USBACTEP register field value. */
89606 #define ALT_USB_DEV_DIEPCTL9_USBACTEP_SET_MSK 0x00008000
89607 /* The mask used to clear the ALT_USB_DEV_DIEPCTL9_USBACTEP register field value. */
89608 #define ALT_USB_DEV_DIEPCTL9_USBACTEP_CLR_MSK 0xffff7fff
89609 /* The reset value of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */
89610 #define ALT_USB_DEV_DIEPCTL9_USBACTEP_RESET 0x0
89611 /* Extracts the ALT_USB_DEV_DIEPCTL9_USBACTEP field value from a register. */
89612 #define ALT_USB_DEV_DIEPCTL9_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
89613 /* Produces a ALT_USB_DEV_DIEPCTL9_USBACTEP register field value suitable for setting the register. */
89614 #define ALT_USB_DEV_DIEPCTL9_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
89615 
89616 /*
89617  * Field : dpid
89618  *
89619  * Endpoint Data PID (DPID)
89620  *
89621  * Applies to interrupt/bulk IN and OUT endpoints only.
89622  *
89623  * Contains the PID of the packet to be received or transmitted on this endpoint.
89624  * The
89625  *
89626  * application must program the PID of the first packet to be received or
89627  * transmitted on
89628  *
89629  * this endpoint, after the endpoint is activated. The applications use the
89630  * SetD1PID and
89631  *
89632  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
89633  *
89634  * 1'b0: DATA0
89635  *
89636  * 1'b1: DATA1
89637  *
89638  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
89639  *
89640  * DMA mode.
89641  *
89642  * 1'b0 RO
89643  *
89644  * Even/Odd (Micro)Frame (EO_FrNum)
89645  *
89646  * In non-Scatter/Gather DMA mode:
89647  *
89648  * Applies to isochronous IN and OUT endpoints only.
89649  *
89650  * Indicates the (micro)frame number in which the core transmits/receives
89651  * isochronous
89652  *
89653  * data for this endpoint. The application must program the even/odd (micro) frame
89654  *
89655  * number in which it intends to transmit/receive isochronous data for this
89656  * endpoint using
89657  *
89658  * the SetEvnFr and SetOddFr fields in this register.
89659  *
89660  * 1'b0: Even (micro)frame
89661  *
89662  * 1'b1: Odd (micro)frame
89663  *
89664  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
89665  * number
89666  *
89667  * in which to send data is provided in the transmit descriptor structure. The
89668  * frame in
89669  *
89670  * which data is received is updated in receive descriptor structure.
89671  *
89672  * Field Enumeration Values:
89673  *
89674  * Enum | Value | Description
89675  * :----------------------------------|:------|:-----------------------------
89676  * ALT_USB_DEV_DIEPCTL9_DPID_E_INACT | 0x0 | Endpoint Data PID not active
89677  * ALT_USB_DEV_DIEPCTL9_DPID_E_ACT | 0x1 | Endpoint Data PID active
89678  *
89679  * Field Access Macros:
89680  *
89681  */
89682 /*
89683  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_DPID
89684  *
89685  * Endpoint Data PID not active
89686  */
89687 #define ALT_USB_DEV_DIEPCTL9_DPID_E_INACT 0x0
89688 /*
89689  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_DPID
89690  *
89691  * Endpoint Data PID active
89692  */
89693 #define ALT_USB_DEV_DIEPCTL9_DPID_E_ACT 0x1
89694 
89695 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_DPID register field. */
89696 #define ALT_USB_DEV_DIEPCTL9_DPID_LSB 16
89697 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_DPID register field. */
89698 #define ALT_USB_DEV_DIEPCTL9_DPID_MSB 16
89699 /* The width in bits of the ALT_USB_DEV_DIEPCTL9_DPID register field. */
89700 #define ALT_USB_DEV_DIEPCTL9_DPID_WIDTH 1
89701 /* The mask used to set the ALT_USB_DEV_DIEPCTL9_DPID register field value. */
89702 #define ALT_USB_DEV_DIEPCTL9_DPID_SET_MSK 0x00010000
89703 /* The mask used to clear the ALT_USB_DEV_DIEPCTL9_DPID register field value. */
89704 #define ALT_USB_DEV_DIEPCTL9_DPID_CLR_MSK 0xfffeffff
89705 /* The reset value of the ALT_USB_DEV_DIEPCTL9_DPID register field. */
89706 #define ALT_USB_DEV_DIEPCTL9_DPID_RESET 0x0
89707 /* Extracts the ALT_USB_DEV_DIEPCTL9_DPID field value from a register. */
89708 #define ALT_USB_DEV_DIEPCTL9_DPID_GET(value) (((value) & 0x00010000) >> 16)
89709 /* Produces a ALT_USB_DEV_DIEPCTL9_DPID register field value suitable for setting the register. */
89710 #define ALT_USB_DEV_DIEPCTL9_DPID_SET(value) (((value) << 16) & 0x00010000)
89711 
89712 /*
89713  * Field : naksts
89714  *
89715  * NAK Status (NAKSts)
89716  *
89717  * Indicates the following:
89718  *
89719  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
89720  *
89721  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
89722  *
89723  * When either the application or the core sets this bit:
89724  *
89725  * The core stops receiving any data on an OUT endpoint, even if there is space in
89726  *
89727  * the RxFIFO to accommodate the incoming packet.
89728  *
89729  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
89730  *
89731  * endpoint, even if there data is available in the TxFIFO.
89732  *
89733  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
89734  *
89735  * if there data is available in the TxFIFO.
89736  *
89737  * Irrespective of this bit's setting, the core always responds to SETUP data
89738  * packets with
89739  *
89740  * an ACK handshake.
89741  *
89742  * Field Enumeration Values:
89743  *
89744  * Enum | Value | Description
89745  * :-------------------------------------|:------|:------------------------------------------------
89746  * ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
89747  * : | | based on the FIFO status
89748  * ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
89749  * : | | endpoint
89750  *
89751  * Field Access Macros:
89752  *
89753  */
89754 /*
89755  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_NAKSTS
89756  *
89757  * The core is transmitting non-NAK handshakes based on the FIFO status
89758  */
89759 #define ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NONNAK 0x0
89760 /*
89761  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_NAKSTS
89762  *
89763  * The core is transmitting NAK handshakes on this endpoint
89764  */
89765 #define ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NAK 0x1
89766 
89767 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */
89768 #define ALT_USB_DEV_DIEPCTL9_NAKSTS_LSB 17
89769 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */
89770 #define ALT_USB_DEV_DIEPCTL9_NAKSTS_MSB 17
89771 /* The width in bits of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */
89772 #define ALT_USB_DEV_DIEPCTL9_NAKSTS_WIDTH 1
89773 /* The mask used to set the ALT_USB_DEV_DIEPCTL9_NAKSTS register field value. */
89774 #define ALT_USB_DEV_DIEPCTL9_NAKSTS_SET_MSK 0x00020000
89775 /* The mask used to clear the ALT_USB_DEV_DIEPCTL9_NAKSTS register field value. */
89776 #define ALT_USB_DEV_DIEPCTL9_NAKSTS_CLR_MSK 0xfffdffff
89777 /* The reset value of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */
89778 #define ALT_USB_DEV_DIEPCTL9_NAKSTS_RESET 0x0
89779 /* Extracts the ALT_USB_DEV_DIEPCTL9_NAKSTS field value from a register. */
89780 #define ALT_USB_DEV_DIEPCTL9_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
89781 /* Produces a ALT_USB_DEV_DIEPCTL9_NAKSTS register field value suitable for setting the register. */
89782 #define ALT_USB_DEV_DIEPCTL9_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
89783 
89784 /*
89785  * Field : eptype
89786  *
89787  * Endpoint Type (EPType)
89788  *
89789  * This is the transfer type supported by this logical endpoint.
89790  *
89791  * 2'b00: Control
89792  *
89793  * 2'b01: Isochronous
89794  *
89795  * 2'b10: Bulk
89796  *
89797  * 2'b11: Interrupt
89798  *
89799  * Field Enumeration Values:
89800  *
89801  * Enum | Value | Description
89802  * :------------------------------------------|:------|:------------
89803  * ALT_USB_DEV_DIEPCTL9_EPTYPE_E_CTL | 0x0 | Control
89804  * ALT_USB_DEV_DIEPCTL9_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
89805  * ALT_USB_DEV_DIEPCTL9_EPTYPE_E_BULK | 0x2 | Bulk
89806  * ALT_USB_DEV_DIEPCTL9_EPTYPE_E_INTERRUP | 0x3 | Interrupt
89807  *
89808  * Field Access Macros:
89809  *
89810  */
89811 /*
89812  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE
89813  *
89814  * Control
89815  */
89816 #define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_CTL 0x0
89817 /*
89818  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE
89819  *
89820  * Isochronous
89821  */
89822 #define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_ISOCHRONOUS 0x1
89823 /*
89824  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE
89825  *
89826  * Bulk
89827  */
89828 #define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_BULK 0x2
89829 /*
89830  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE
89831  *
89832  * Interrupt
89833  */
89834 #define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_INTERRUP 0x3
89835 
89836 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */
89837 #define ALT_USB_DEV_DIEPCTL9_EPTYPE_LSB 18
89838 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */
89839 #define ALT_USB_DEV_DIEPCTL9_EPTYPE_MSB 19
89840 /* The width in bits of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */
89841 #define ALT_USB_DEV_DIEPCTL9_EPTYPE_WIDTH 2
89842 /* The mask used to set the ALT_USB_DEV_DIEPCTL9_EPTYPE register field value. */
89843 #define ALT_USB_DEV_DIEPCTL9_EPTYPE_SET_MSK 0x000c0000
89844 /* The mask used to clear the ALT_USB_DEV_DIEPCTL9_EPTYPE register field value. */
89845 #define ALT_USB_DEV_DIEPCTL9_EPTYPE_CLR_MSK 0xfff3ffff
89846 /* The reset value of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */
89847 #define ALT_USB_DEV_DIEPCTL9_EPTYPE_RESET 0x0
89848 /* Extracts the ALT_USB_DEV_DIEPCTL9_EPTYPE field value from a register. */
89849 #define ALT_USB_DEV_DIEPCTL9_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
89850 /* Produces a ALT_USB_DEV_DIEPCTL9_EPTYPE register field value suitable for setting the register. */
89851 #define ALT_USB_DEV_DIEPCTL9_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
89852 
89853 /*
89854  * Field : stall
89855  *
89856  * STALL Handshake (Stall)
89857  *
89858  * Applies to non-control, non-isochronous IN and OUT endpoints only.
89859  *
89860  * The application sets this bit to stall all tokens from the USB host to this
89861  * endpoint. If a
89862  *
89863  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
89864  * bit, the
89865  *
89866  * STALL bit takes priority. Only the application can clear this bit, never the
89867  * core.
89868  *
89869  * 1'b0 R_W
89870  *
89871  * Applies to control endpoints only.
89872  *
89873  * The application can only set this bit, and the core clears it, when a SETUP
89874  * token is
89875  *
89876  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
89877  * OUT
89878  *
89879  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
89880  * this bit's
89881  *
89882  * setting, the core always responds to SETUP data packets with an ACK handshake.
89883  *
89884  * Field Enumeration Values:
89885  *
89886  * Enum | Value | Description
89887  * :-----------------------------------|:------|:----------------------------
89888  * ALT_USB_DEV_DIEPCTL9_STALL_E_INACT | 0x0 | STALL All Tokens not active
89889  * ALT_USB_DEV_DIEPCTL9_STALL_E_ACT | 0x1 | STALL All Tokens active
89890  *
89891  * Field Access Macros:
89892  *
89893  */
89894 /*
89895  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_STALL
89896  *
89897  * STALL All Tokens not active
89898  */
89899 #define ALT_USB_DEV_DIEPCTL9_STALL_E_INACT 0x0
89900 /*
89901  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_STALL
89902  *
89903  * STALL All Tokens active
89904  */
89905 #define ALT_USB_DEV_DIEPCTL9_STALL_E_ACT 0x1
89906 
89907 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_STALL register field. */
89908 #define ALT_USB_DEV_DIEPCTL9_STALL_LSB 21
89909 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_STALL register field. */
89910 #define ALT_USB_DEV_DIEPCTL9_STALL_MSB 21
89911 /* The width in bits of the ALT_USB_DEV_DIEPCTL9_STALL register field. */
89912 #define ALT_USB_DEV_DIEPCTL9_STALL_WIDTH 1
89913 /* The mask used to set the ALT_USB_DEV_DIEPCTL9_STALL register field value. */
89914 #define ALT_USB_DEV_DIEPCTL9_STALL_SET_MSK 0x00200000
89915 /* The mask used to clear the ALT_USB_DEV_DIEPCTL9_STALL register field value. */
89916 #define ALT_USB_DEV_DIEPCTL9_STALL_CLR_MSK 0xffdfffff
89917 /* The reset value of the ALT_USB_DEV_DIEPCTL9_STALL register field. */
89918 #define ALT_USB_DEV_DIEPCTL9_STALL_RESET 0x0
89919 /* Extracts the ALT_USB_DEV_DIEPCTL9_STALL field value from a register. */
89920 #define ALT_USB_DEV_DIEPCTL9_STALL_GET(value) (((value) & 0x00200000) >> 21)
89921 /* Produces a ALT_USB_DEV_DIEPCTL9_STALL register field value suitable for setting the register. */
89922 #define ALT_USB_DEV_DIEPCTL9_STALL_SET(value) (((value) << 21) & 0x00200000)
89923 
89924 /*
89925  * Field : txfnum
89926  *
89927  * TxFIFO Number (TxFNum)
89928  *
89929  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
89930  *
89931  * endpoints must map this to the corresponding Periodic TxFIFO number.
89932  *
89933  * 4'h0: Non-Periodic TxFIFO
89934  *
89935  * Others: Specified Periodic TxFIFO.number
89936  *
89937  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
89938  *
89939  * applications such as mass storage. The core treats an IN endpoint as a non-
89940  * periodic
89941  *
89942  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
89943  * must be
89944  *
89945  * allocated for an interrupt IN endpoint, and the number of this
89946  *
89947  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
89948  *
89949  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
89950  *
89951  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
89952  *
89953  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
89954  *
89955  * This field is valid only for IN endpoints.
89956  *
89957  * Field Access Macros:
89958  *
89959  */
89960 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */
89961 #define ALT_USB_DEV_DIEPCTL9_TXFNUM_LSB 22
89962 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */
89963 #define ALT_USB_DEV_DIEPCTL9_TXFNUM_MSB 25
89964 /* The width in bits of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */
89965 #define ALT_USB_DEV_DIEPCTL9_TXFNUM_WIDTH 4
89966 /* The mask used to set the ALT_USB_DEV_DIEPCTL9_TXFNUM register field value. */
89967 #define ALT_USB_DEV_DIEPCTL9_TXFNUM_SET_MSK 0x03c00000
89968 /* The mask used to clear the ALT_USB_DEV_DIEPCTL9_TXFNUM register field value. */
89969 #define ALT_USB_DEV_DIEPCTL9_TXFNUM_CLR_MSK 0xfc3fffff
89970 /* The reset value of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */
89971 #define ALT_USB_DEV_DIEPCTL9_TXFNUM_RESET 0x0
89972 /* Extracts the ALT_USB_DEV_DIEPCTL9_TXFNUM field value from a register. */
89973 #define ALT_USB_DEV_DIEPCTL9_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
89974 /* Produces a ALT_USB_DEV_DIEPCTL9_TXFNUM register field value suitable for setting the register. */
89975 #define ALT_USB_DEV_DIEPCTL9_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
89976 
89977 /*
89978  * Field : cnak
89979  *
89980  * Clear NAK (CNAK)
89981  *
89982  * A write to this bit clears the NAK bit For the endpoint.
89983  *
89984  * Field Enumeration Values:
89985  *
89986  * Enum | Value | Description
89987  * :----------------------------------|:------|:-------------
89988  * ALT_USB_DEV_DIEPCTL9_CNAK_E_INACT | 0x0 | No Clear NAK
89989  * ALT_USB_DEV_DIEPCTL9_CNAK_E_ACT | 0x1 | Clear NAK
89990  *
89991  * Field Access Macros:
89992  *
89993  */
89994 /*
89995  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_CNAK
89996  *
89997  * No Clear NAK
89998  */
89999 #define ALT_USB_DEV_DIEPCTL9_CNAK_E_INACT 0x0
90000 /*
90001  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_CNAK
90002  *
90003  * Clear NAK
90004  */
90005 #define ALT_USB_DEV_DIEPCTL9_CNAK_E_ACT 0x1
90006 
90007 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */
90008 #define ALT_USB_DEV_DIEPCTL9_CNAK_LSB 26
90009 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */
90010 #define ALT_USB_DEV_DIEPCTL9_CNAK_MSB 26
90011 /* The width in bits of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */
90012 #define ALT_USB_DEV_DIEPCTL9_CNAK_WIDTH 1
90013 /* The mask used to set the ALT_USB_DEV_DIEPCTL9_CNAK register field value. */
90014 #define ALT_USB_DEV_DIEPCTL9_CNAK_SET_MSK 0x04000000
90015 /* The mask used to clear the ALT_USB_DEV_DIEPCTL9_CNAK register field value. */
90016 #define ALT_USB_DEV_DIEPCTL9_CNAK_CLR_MSK 0xfbffffff
90017 /* The reset value of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */
90018 #define ALT_USB_DEV_DIEPCTL9_CNAK_RESET 0x0
90019 /* Extracts the ALT_USB_DEV_DIEPCTL9_CNAK field value from a register. */
90020 #define ALT_USB_DEV_DIEPCTL9_CNAK_GET(value) (((value) & 0x04000000) >> 26)
90021 /* Produces a ALT_USB_DEV_DIEPCTL9_CNAK register field value suitable for setting the register. */
90022 #define ALT_USB_DEV_DIEPCTL9_CNAK_SET(value) (((value) << 26) & 0x04000000)
90023 
90024 /*
90025  * Field : snak
90026  *
90027  * Set NAK (SNAK)
90028  *
90029  * A write to this bit sets the NAK bit For the endpoint.
90030  *
90031  * Using this bit, the application can control the transmission of NAK
90032  *
90033  * handshakes on an endpoint. The core can also Set this bit For an
90034  *
90035  * endpoint after a SETUP packet is received on that endpoint.
90036  *
90037  * Field Enumeration Values:
90038  *
90039  * Enum | Value | Description
90040  * :----------------------------------|:------|:------------
90041  * ALT_USB_DEV_DIEPCTL9_SNAK_E_INACT | 0x0 | No Set NAK
90042  * ALT_USB_DEV_DIEPCTL9_SNAK_E_ACT | 0x1 | Set NAK
90043  *
90044  * Field Access Macros:
90045  *
90046  */
90047 /*
90048  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SNAK
90049  *
90050  * No Set NAK
90051  */
90052 #define ALT_USB_DEV_DIEPCTL9_SNAK_E_INACT 0x0
90053 /*
90054  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SNAK
90055  *
90056  * Set NAK
90057  */
90058 #define ALT_USB_DEV_DIEPCTL9_SNAK_E_ACT 0x1
90059 
90060 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */
90061 #define ALT_USB_DEV_DIEPCTL9_SNAK_LSB 27
90062 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */
90063 #define ALT_USB_DEV_DIEPCTL9_SNAK_MSB 27
90064 /* The width in bits of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */
90065 #define ALT_USB_DEV_DIEPCTL9_SNAK_WIDTH 1
90066 /* The mask used to set the ALT_USB_DEV_DIEPCTL9_SNAK register field value. */
90067 #define ALT_USB_DEV_DIEPCTL9_SNAK_SET_MSK 0x08000000
90068 /* The mask used to clear the ALT_USB_DEV_DIEPCTL9_SNAK register field value. */
90069 #define ALT_USB_DEV_DIEPCTL9_SNAK_CLR_MSK 0xf7ffffff
90070 /* The reset value of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */
90071 #define ALT_USB_DEV_DIEPCTL9_SNAK_RESET 0x0
90072 /* Extracts the ALT_USB_DEV_DIEPCTL9_SNAK field value from a register. */
90073 #define ALT_USB_DEV_DIEPCTL9_SNAK_GET(value) (((value) & 0x08000000) >> 27)
90074 /* Produces a ALT_USB_DEV_DIEPCTL9_SNAK register field value suitable for setting the register. */
90075 #define ALT_USB_DEV_DIEPCTL9_SNAK_SET(value) (((value) << 27) & 0x08000000)
90076 
90077 /*
90078  * Field : setd0pid
90079  *
90080  * Set DATA0 PID (SetD0PID)
90081  *
90082  * Applies to interrupt/bulk IN and OUT endpoints only.
90083  *
90084  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
90085  * to DATA0.
90086  *
90087  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
90088  *
90089  * DMA mode.
90090  *
90091  * 1'b0 WO
90092  *
90093  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
90094  *
90095  * Applies to isochronous IN and OUT endpoints only.
90096  *
90097  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
90098  * (micro)
90099  *
90100  * frame.
90101  *
90102  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
90103  * number
90104  *
90105  * in which to send data is in the transmit descriptor structure. The frame in
90106  * which to
90107  *
90108  * receive data is updated in receive descriptor structure.
90109  *
90110  * Field Enumeration Values:
90111  *
90112  * Enum | Value | Description
90113  * :-------------------------------------|:------|:----------------------------
90114  * ALT_USB_DEV_DIEPCTL9_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
90115  * ALT_USB_DEV_DIEPCTL9_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
90116  *
90117  * Field Access Macros:
90118  *
90119  */
90120 /*
90121  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD0PID
90122  *
90123  * Disables Set DATA0 PID
90124  */
90125 #define ALT_USB_DEV_DIEPCTL9_SETD0PID_E_DISD 0x0
90126 /*
90127  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD0PID
90128  *
90129  * Endpoint Data PID to DATA0)
90130  */
90131 #define ALT_USB_DEV_DIEPCTL9_SETD0PID_E_END 0x1
90132 
90133 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */
90134 #define ALT_USB_DEV_DIEPCTL9_SETD0PID_LSB 28
90135 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */
90136 #define ALT_USB_DEV_DIEPCTL9_SETD0PID_MSB 28
90137 /* The width in bits of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */
90138 #define ALT_USB_DEV_DIEPCTL9_SETD0PID_WIDTH 1
90139 /* The mask used to set the ALT_USB_DEV_DIEPCTL9_SETD0PID register field value. */
90140 #define ALT_USB_DEV_DIEPCTL9_SETD0PID_SET_MSK 0x10000000
90141 /* The mask used to clear the ALT_USB_DEV_DIEPCTL9_SETD0PID register field value. */
90142 #define ALT_USB_DEV_DIEPCTL9_SETD0PID_CLR_MSK 0xefffffff
90143 /* The reset value of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */
90144 #define ALT_USB_DEV_DIEPCTL9_SETD0PID_RESET 0x0
90145 /* Extracts the ALT_USB_DEV_DIEPCTL9_SETD0PID field value from a register. */
90146 #define ALT_USB_DEV_DIEPCTL9_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
90147 /* Produces a ALT_USB_DEV_DIEPCTL9_SETD0PID register field value suitable for setting the register. */
90148 #define ALT_USB_DEV_DIEPCTL9_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
90149 
90150 /*
90151  * Field : setd1pid
90152  *
90153  * Set DATA1 PID (SetD1PID)
90154  *
90155  * Applies to interrupt/bulk IN and OUT endpoints only.
90156  *
90157  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
90158  * to DATA1.
90159  *
90160  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
90161  *
90162  * DMA mode.
90163  *
90164  * Set Odd (micro)frame (SetOddFr)
90165  *
90166  * Applies to isochronous IN and OUT endpoints only.
90167  *
90168  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
90169  *
90170  * (micro)frame.
90171  *
90172  * This field is not applicable for Scatter/Gather DMA mode.
90173  *
90174  * Field Enumeration Values:
90175  *
90176  * Enum | Value | Description
90177  * :-------------------------------------|:------|:-----------------------
90178  * ALT_USB_DEV_DIEPCTL9_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
90179  * ALT_USB_DEV_DIEPCTL9_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
90180  *
90181  * Field Access Macros:
90182  *
90183  */
90184 /*
90185  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD1PID
90186  *
90187  * Disables Set DATA1 PID
90188  */
90189 #define ALT_USB_DEV_DIEPCTL9_SETD1PID_E_DISD 0x0
90190 /*
90191  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD1PID
90192  *
90193  * Enables Set DATA1 PID
90194  */
90195 #define ALT_USB_DEV_DIEPCTL9_SETD1PID_E_END 0x1
90196 
90197 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */
90198 #define ALT_USB_DEV_DIEPCTL9_SETD1PID_LSB 29
90199 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */
90200 #define ALT_USB_DEV_DIEPCTL9_SETD1PID_MSB 29
90201 /* The width in bits of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */
90202 #define ALT_USB_DEV_DIEPCTL9_SETD1PID_WIDTH 1
90203 /* The mask used to set the ALT_USB_DEV_DIEPCTL9_SETD1PID register field value. */
90204 #define ALT_USB_DEV_DIEPCTL9_SETD1PID_SET_MSK 0x20000000
90205 /* The mask used to clear the ALT_USB_DEV_DIEPCTL9_SETD1PID register field value. */
90206 #define ALT_USB_DEV_DIEPCTL9_SETD1PID_CLR_MSK 0xdfffffff
90207 /* The reset value of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */
90208 #define ALT_USB_DEV_DIEPCTL9_SETD1PID_RESET 0x0
90209 /* Extracts the ALT_USB_DEV_DIEPCTL9_SETD1PID field value from a register. */
90210 #define ALT_USB_DEV_DIEPCTL9_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
90211 /* Produces a ALT_USB_DEV_DIEPCTL9_SETD1PID register field value suitable for setting the register. */
90212 #define ALT_USB_DEV_DIEPCTL9_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
90213 
90214 /*
90215  * Field : epdis
90216  *
90217  * Endpoint Disable (EPDis)
90218  *
90219  * Applies to IN and OUT endpoints.
90220  *
90221  * The application sets this bit to stop transmitting/receiving data on an
90222  * endpoint, even
90223  *
90224  * before the transfer for that endpoint is complete. The application must wait for
90225  * the
90226  *
90227  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
90228  * clears
90229  *
90230  * this bit before setting the Endpoint Disabled interrupt. The application must
90231  * set this bit
90232  *
90233  * only if Endpoint Enable is already set for this endpoint.
90234  *
90235  * Field Enumeration Values:
90236  *
90237  * Enum | Value | Description
90238  * :-----------------------------------|:------|:--------------------
90239  * ALT_USB_DEV_DIEPCTL9_EPDIS_E_INACT | 0x0 | No Endpoint Disable
90240  * ALT_USB_DEV_DIEPCTL9_EPDIS_E_ACT | 0x1 | Endpoint Disable
90241  *
90242  * Field Access Macros:
90243  *
90244  */
90245 /*
90246  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPDIS
90247  *
90248  * No Endpoint Disable
90249  */
90250 #define ALT_USB_DEV_DIEPCTL9_EPDIS_E_INACT 0x0
90251 /*
90252  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPDIS
90253  *
90254  * Endpoint Disable
90255  */
90256 #define ALT_USB_DEV_DIEPCTL9_EPDIS_E_ACT 0x1
90257 
90258 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */
90259 #define ALT_USB_DEV_DIEPCTL9_EPDIS_LSB 30
90260 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */
90261 #define ALT_USB_DEV_DIEPCTL9_EPDIS_MSB 30
90262 /* The width in bits of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */
90263 #define ALT_USB_DEV_DIEPCTL9_EPDIS_WIDTH 1
90264 /* The mask used to set the ALT_USB_DEV_DIEPCTL9_EPDIS register field value. */
90265 #define ALT_USB_DEV_DIEPCTL9_EPDIS_SET_MSK 0x40000000
90266 /* The mask used to clear the ALT_USB_DEV_DIEPCTL9_EPDIS register field value. */
90267 #define ALT_USB_DEV_DIEPCTL9_EPDIS_CLR_MSK 0xbfffffff
90268 /* The reset value of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */
90269 #define ALT_USB_DEV_DIEPCTL9_EPDIS_RESET 0x0
90270 /* Extracts the ALT_USB_DEV_DIEPCTL9_EPDIS field value from a register. */
90271 #define ALT_USB_DEV_DIEPCTL9_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
90272 /* Produces a ALT_USB_DEV_DIEPCTL9_EPDIS register field value suitable for setting the register. */
90273 #define ALT_USB_DEV_DIEPCTL9_EPDIS_SET(value) (((value) << 30) & 0x40000000)
90274 
90275 /*
90276  * Field : epena
90277  *
90278  * Endpoint Enable (EPEna)
90279  *
90280  * Applies to IN and OUT endpoints.
90281  *
90282  * When Scatter/Gather DMA mode is enabled,
90283  *
90284  * For IN endpoints this bit indicates that the descriptor structure and data
90285  * buffer with
90286  *
90287  * data ready to transmit is setup.
90288  *
90289  * For OUT endpoint it indicates that the descriptor structure and data buffer to
90290  *
90291  * receive data is setup.
90292  *
90293  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
90294  *
90295  * DMA mode:
90296  *
90297  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
90298  * the
90299  *
90300  * endpoint.
90301  *
90302  * * For OUT endpoints, this bit indicates that the application has allocated the
90303  *
90304  * memory to start receiving data from the USB.
90305  *
90306  * * The core clears this bit before setting any of the following interrupts on
90307  * this
90308  *
90309  * endpoint:
90310  *
90311  * SETUP Phase Done
90312  *
90313  * Endpoint Disabled
90314  *
90315  * Transfer Completed
90316  *
90317  * Note: For control endpoints in DMA mode, this bit must be set to be able to
90318  * transfer
90319  *
90320  * SETUP data packets in memory.
90321  *
90322  * Field Enumeration Values:
90323  *
90324  * Enum | Value | Description
90325  * :-----------------------------------|:------|:-------------------------
90326  * ALT_USB_DEV_DIEPCTL9_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
90327  * ALT_USB_DEV_DIEPCTL9_EPENA_E_ACT | 0x1 | Endpoint Enable active
90328  *
90329  * Field Access Macros:
90330  *
90331  */
90332 /*
90333  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPENA
90334  *
90335  * Endpoint Enable inactive
90336  */
90337 #define ALT_USB_DEV_DIEPCTL9_EPENA_E_INACT 0x0
90338 /*
90339  * Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPENA
90340  *
90341  * Endpoint Enable active
90342  */
90343 #define ALT_USB_DEV_DIEPCTL9_EPENA_E_ACT 0x1
90344 
90345 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */
90346 #define ALT_USB_DEV_DIEPCTL9_EPENA_LSB 31
90347 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */
90348 #define ALT_USB_DEV_DIEPCTL9_EPENA_MSB 31
90349 /* The width in bits of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */
90350 #define ALT_USB_DEV_DIEPCTL9_EPENA_WIDTH 1
90351 /* The mask used to set the ALT_USB_DEV_DIEPCTL9_EPENA register field value. */
90352 #define ALT_USB_DEV_DIEPCTL9_EPENA_SET_MSK 0x80000000
90353 /* The mask used to clear the ALT_USB_DEV_DIEPCTL9_EPENA register field value. */
90354 #define ALT_USB_DEV_DIEPCTL9_EPENA_CLR_MSK 0x7fffffff
90355 /* The reset value of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */
90356 #define ALT_USB_DEV_DIEPCTL9_EPENA_RESET 0x0
90357 /* Extracts the ALT_USB_DEV_DIEPCTL9_EPENA field value from a register. */
90358 #define ALT_USB_DEV_DIEPCTL9_EPENA_GET(value) (((value) & 0x80000000) >> 31)
90359 /* Produces a ALT_USB_DEV_DIEPCTL9_EPENA register field value suitable for setting the register. */
90360 #define ALT_USB_DEV_DIEPCTL9_EPENA_SET(value) (((value) << 31) & 0x80000000)
90361 
90362 #ifndef __ASSEMBLY__
90363 /*
90364  * WARNING: The C register and register group struct declarations are provided for
90365  * convenience and illustrative purposes. They should, however, be used with
90366  * caution as the C language standard provides no guarantees about the alignment or
90367  * atomicity of device memory accesses. The recommended practice for writing
90368  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
90369  * alt_write_word() functions.
90370  *
90371  * The struct declaration for register ALT_USB_DEV_DIEPCTL9.
90372  */
90373 struct ALT_USB_DEV_DIEPCTL9_s
90374 {
90375  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL9_MPS */
90376  uint32_t : 4; /* *UNDEFINED* */
90377  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL9_USBACTEP */
90378  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL9_DPID */
90379  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL9_NAKSTS */
90380  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL9_EPTYPE */
90381  uint32_t : 1; /* *UNDEFINED* */
90382  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL9_STALL */
90383  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL9_TXFNUM */
90384  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL9_CNAK */
90385  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL9_SNAK */
90386  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL9_SETD0PID */
90387  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL9_SETD1PID */
90388  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL9_EPDIS */
90389  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL9_EPENA */
90390 };
90391 
90392 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL9. */
90393 typedef volatile struct ALT_USB_DEV_DIEPCTL9_s ALT_USB_DEV_DIEPCTL9_t;
90394 #endif /* __ASSEMBLY__ */
90395 
90396 /* The reset value of the ALT_USB_DEV_DIEPCTL9 register. */
90397 #define ALT_USB_DEV_DIEPCTL9_RESET 0x00000000
90398 /* The byte offset of the ALT_USB_DEV_DIEPCTL9 register from the beginning of the component. */
90399 #define ALT_USB_DEV_DIEPCTL9_OFST 0x220
90400 /* The address of the ALT_USB_DEV_DIEPCTL9 register. */
90401 #define ALT_USB_DEV_DIEPCTL9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL9_OFST))
90402 
90403 /*
90404  * Register : diepint9
90405  *
90406  * Device IN Endpoint 9 Interrupt Register
90407  *
90408  * Register Layout
90409  *
90410  * Bits | Access | Reset | Description
90411  * :--------|:-------|:------|:---------------------------------
90412  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_XFERCOMPL
90413  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_EPDISBLD
90414  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_AHBERR
90415  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_TMO
90416  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_INTKNTXFEMP
90417  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_INTKNEPMIS
90418  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_INEPNAKEFF
90419  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT9_TXFEMP
90420  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN
90421  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_BNAINTR
90422  * [10] | ??? | 0x0 | *UNDEFINED*
90423  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_PKTDRPSTS
90424  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_BBLEERR
90425  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_NAKINTRPT
90426  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_NYETINTRPT
90427  * [31:15] | ??? | 0x0 | *UNDEFINED*
90428  *
90429  */
90430 /*
90431  * Field : xfercompl
90432  *
90433  * Transfer Completed Interrupt (XferCompl)
90434  *
90435  * Applies to IN and OUT endpoints.
90436  *
90437  * When Scatter/Gather DMA mode is enabled
90438  *
90439  * * For IN endpoint this field indicates that the requested data
90440  *
90441  * from the descriptor is moved from external system memory
90442  *
90443  * to internal FIFO.
90444  *
90445  * * For OUT endpoint this field indicates that the requested
90446  *
90447  * data from the internal FIFO is moved to external system
90448  *
90449  * memory. This interrupt is generated only when the
90450  *
90451  * corresponding endpoint descriptor is closed, and the IOC
90452  *
90453  * bit For the corresponding descriptor is Set.
90454  *
90455  * When Scatter/Gather DMA mode is disabled, this field
90456  *
90457  * indicates that the programmed transfer is complete on the
90458  *
90459  * AHB as well as on the USB, For this endpoint.
90460  *
90461  * Field Enumeration Values:
90462  *
90463  * Enum | Value | Description
90464  * :---------------------------------------|:------|:-----------------------------
90465  * ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_INACT | 0x0 | No Interrupt
90466  * ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
90467  *
90468  * Field Access Macros:
90469  *
90470  */
90471 /*
90472  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_XFERCOMPL
90473  *
90474  * No Interrupt
90475  */
90476 #define ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_INACT 0x0
90477 /*
90478  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_XFERCOMPL
90479  *
90480  * Transfer Completed Interrupt
90481  */
90482 #define ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_ACT 0x1
90483 
90484 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */
90485 #define ALT_USB_DEV_DIEPINT9_XFERCOMPL_LSB 0
90486 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */
90487 #define ALT_USB_DEV_DIEPINT9_XFERCOMPL_MSB 0
90488 /* The width in bits of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */
90489 #define ALT_USB_DEV_DIEPINT9_XFERCOMPL_WIDTH 1
90490 /* The mask used to set the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field value. */
90491 #define ALT_USB_DEV_DIEPINT9_XFERCOMPL_SET_MSK 0x00000001
90492 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field value. */
90493 #define ALT_USB_DEV_DIEPINT9_XFERCOMPL_CLR_MSK 0xfffffffe
90494 /* The reset value of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */
90495 #define ALT_USB_DEV_DIEPINT9_XFERCOMPL_RESET 0x0
90496 /* Extracts the ALT_USB_DEV_DIEPINT9_XFERCOMPL field value from a register. */
90497 #define ALT_USB_DEV_DIEPINT9_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
90498 /* Produces a ALT_USB_DEV_DIEPINT9_XFERCOMPL register field value suitable for setting the register. */
90499 #define ALT_USB_DEV_DIEPINT9_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
90500 
90501 /*
90502  * Field : epdisbld
90503  *
90504  * Endpoint Disabled Interrupt (EPDisbld)
90505  *
90506  * Applies to IN and OUT endpoints.
90507  *
90508  * This bit indicates that the endpoint is disabled per the
90509  *
90510  * application's request.
90511  *
90512  * Field Enumeration Values:
90513  *
90514  * Enum | Value | Description
90515  * :--------------------------------------|:------|:----------------------------
90516  * ALT_USB_DEV_DIEPINT9_EPDISBLD_E_INACT | 0x0 | No Interrupt
90517  * ALT_USB_DEV_DIEPINT9_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
90518  *
90519  * Field Access Macros:
90520  *
90521  */
90522 /*
90523  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_EPDISBLD
90524  *
90525  * No Interrupt
90526  */
90527 #define ALT_USB_DEV_DIEPINT9_EPDISBLD_E_INACT 0x0
90528 /*
90529  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_EPDISBLD
90530  *
90531  * Endpoint Disabled Interrupt
90532  */
90533 #define ALT_USB_DEV_DIEPINT9_EPDISBLD_E_ACT 0x1
90534 
90535 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */
90536 #define ALT_USB_DEV_DIEPINT9_EPDISBLD_LSB 1
90537 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */
90538 #define ALT_USB_DEV_DIEPINT9_EPDISBLD_MSB 1
90539 /* The width in bits of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */
90540 #define ALT_USB_DEV_DIEPINT9_EPDISBLD_WIDTH 1
90541 /* The mask used to set the ALT_USB_DEV_DIEPINT9_EPDISBLD register field value. */
90542 #define ALT_USB_DEV_DIEPINT9_EPDISBLD_SET_MSK 0x00000002
90543 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_EPDISBLD register field value. */
90544 #define ALT_USB_DEV_DIEPINT9_EPDISBLD_CLR_MSK 0xfffffffd
90545 /* The reset value of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */
90546 #define ALT_USB_DEV_DIEPINT9_EPDISBLD_RESET 0x0
90547 /* Extracts the ALT_USB_DEV_DIEPINT9_EPDISBLD field value from a register. */
90548 #define ALT_USB_DEV_DIEPINT9_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
90549 /* Produces a ALT_USB_DEV_DIEPINT9_EPDISBLD register field value suitable for setting the register. */
90550 #define ALT_USB_DEV_DIEPINT9_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
90551 
90552 /*
90553  * Field : ahberr
90554  *
90555  * AHB Error (AHBErr)
90556  *
90557  * Applies to IN and OUT endpoints.
90558  *
90559  * This is generated only in Internal DMA mode when there is an
90560  *
90561  * AHB error during an AHB read/write. The application can read
90562  *
90563  * the corresponding endpoint DMA address register to get the
90564  *
90565  * error address.
90566  *
90567  * Field Enumeration Values:
90568  *
90569  * Enum | Value | Description
90570  * :------------------------------------|:------|:--------------------
90571  * ALT_USB_DEV_DIEPINT9_AHBERR_E_INACT | 0x0 | No Interrupt
90572  * ALT_USB_DEV_DIEPINT9_AHBERR_E_ACT | 0x1 | AHB Error interrupt
90573  *
90574  * Field Access Macros:
90575  *
90576  */
90577 /*
90578  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_AHBERR
90579  *
90580  * No Interrupt
90581  */
90582 #define ALT_USB_DEV_DIEPINT9_AHBERR_E_INACT 0x0
90583 /*
90584  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_AHBERR
90585  *
90586  * AHB Error interrupt
90587  */
90588 #define ALT_USB_DEV_DIEPINT9_AHBERR_E_ACT 0x1
90589 
90590 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */
90591 #define ALT_USB_DEV_DIEPINT9_AHBERR_LSB 2
90592 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */
90593 #define ALT_USB_DEV_DIEPINT9_AHBERR_MSB 2
90594 /* The width in bits of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */
90595 #define ALT_USB_DEV_DIEPINT9_AHBERR_WIDTH 1
90596 /* The mask used to set the ALT_USB_DEV_DIEPINT9_AHBERR register field value. */
90597 #define ALT_USB_DEV_DIEPINT9_AHBERR_SET_MSK 0x00000004
90598 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_AHBERR register field value. */
90599 #define ALT_USB_DEV_DIEPINT9_AHBERR_CLR_MSK 0xfffffffb
90600 /* The reset value of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */
90601 #define ALT_USB_DEV_DIEPINT9_AHBERR_RESET 0x0
90602 /* Extracts the ALT_USB_DEV_DIEPINT9_AHBERR field value from a register. */
90603 #define ALT_USB_DEV_DIEPINT9_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
90604 /* Produces a ALT_USB_DEV_DIEPINT9_AHBERR register field value suitable for setting the register. */
90605 #define ALT_USB_DEV_DIEPINT9_AHBERR_SET(value) (((value) << 2) & 0x00000004)
90606 
90607 /*
90608  * Field : timeout
90609  *
90610  * Timeout Condition (TimeOUT)
90611  *
90612  * In shared TX FIFO mode, applies to non-isochronous IN
90613  *
90614  * endpoints only.
90615  *
90616  * In dedicated FIFO mode, applies only to Control IN
90617  *
90618  * endpoints.
90619  *
90620  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
90621  *
90622  * asserted.
90623  *
90624  * Indicates that the core has detected a timeout condition on the
90625  *
90626  * USB For the last IN token on this endpoint.
90627  *
90628  * Field Enumeration Values:
90629  *
90630  * Enum | Value | Description
90631  * :---------------------------------|:------|:------------------
90632  * ALT_USB_DEV_DIEPINT9_TMO_E_INACT | 0x0 | No interrupt
90633  * ALT_USB_DEV_DIEPINT9_TMO_E_ACT | 0x1 | Timeout interrupy
90634  *
90635  * Field Access Macros:
90636  *
90637  */
90638 /*
90639  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TMO
90640  *
90641  * No interrupt
90642  */
90643 #define ALT_USB_DEV_DIEPINT9_TMO_E_INACT 0x0
90644 /*
90645  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TMO
90646  *
90647  * Timeout interrupy
90648  */
90649 #define ALT_USB_DEV_DIEPINT9_TMO_E_ACT 0x1
90650 
90651 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_TMO register field. */
90652 #define ALT_USB_DEV_DIEPINT9_TMO_LSB 3
90653 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_TMO register field. */
90654 #define ALT_USB_DEV_DIEPINT9_TMO_MSB 3
90655 /* The width in bits of the ALT_USB_DEV_DIEPINT9_TMO register field. */
90656 #define ALT_USB_DEV_DIEPINT9_TMO_WIDTH 1
90657 /* The mask used to set the ALT_USB_DEV_DIEPINT9_TMO register field value. */
90658 #define ALT_USB_DEV_DIEPINT9_TMO_SET_MSK 0x00000008
90659 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_TMO register field value. */
90660 #define ALT_USB_DEV_DIEPINT9_TMO_CLR_MSK 0xfffffff7
90661 /* The reset value of the ALT_USB_DEV_DIEPINT9_TMO register field. */
90662 #define ALT_USB_DEV_DIEPINT9_TMO_RESET 0x0
90663 /* Extracts the ALT_USB_DEV_DIEPINT9_TMO field value from a register. */
90664 #define ALT_USB_DEV_DIEPINT9_TMO_GET(value) (((value) & 0x00000008) >> 3)
90665 /* Produces a ALT_USB_DEV_DIEPINT9_TMO register field value suitable for setting the register. */
90666 #define ALT_USB_DEV_DIEPINT9_TMO_SET(value) (((value) << 3) & 0x00000008)
90667 
90668 /*
90669  * Field : intkntxfemp
90670  *
90671  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
90672  *
90673  * Applies to non-periodic IN endpoints only.
90674  *
90675  * Indicates that an IN token was received when the associated
90676  *
90677  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
90678  *
90679  * asserted on the endpoint For which the IN token was received.
90680  *
90681  * Field Enumeration Values:
90682  *
90683  * Enum | Value | Description
90684  * :-----------------------------------------|:------|:----------------------------
90685  * ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
90686  * ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
90687  *
90688  * Field Access Macros:
90689  *
90690  */
90691 /*
90692  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNTXFEMP
90693  *
90694  * No interrupt
90695  */
90696 #define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_INACT 0x0
90697 /*
90698  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNTXFEMP
90699  *
90700  * IN Token Received Interrupt
90701  */
90702 #define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_ACT 0x1
90703 
90704 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */
90705 #define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_LSB 4
90706 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */
90707 #define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_MSB 4
90708 /* The width in bits of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */
90709 #define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_WIDTH 1
90710 /* The mask used to set the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field value. */
90711 #define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_SET_MSK 0x00000010
90712 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field value. */
90713 #define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_CLR_MSK 0xffffffef
90714 /* The reset value of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */
90715 #define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_RESET 0x0
90716 /* Extracts the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP field value from a register. */
90717 #define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
90718 /* Produces a ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field value suitable for setting the register. */
90719 #define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
90720 
90721 /*
90722  * Field : intknepmis
90723  *
90724  * IN Token Received with EP Mismatch (INTknEPMis)
90725  *
90726  * Applies to non-periodic IN endpoints only.
90727  *
90728  * Indicates that the data in the top of the non-periodic TxFIFO
90729  *
90730  * belongs to an endpoint other than the one For which the IN token
90731  *
90732  * was received. This interrupt is asserted on the endpoint For
90733  *
90734  * which the IN token was received.
90735  *
90736  * Field Enumeration Values:
90737  *
90738  * Enum | Value | Description
90739  * :----------------------------------------|:------|:---------------------------------------------
90740  * ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_INACT | 0x0 | No interrupt
90741  * ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
90742  *
90743  * Field Access Macros:
90744  *
90745  */
90746 /*
90747  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNEPMIS
90748  *
90749  * No interrupt
90750  */
90751 #define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_INACT 0x0
90752 /*
90753  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNEPMIS
90754  *
90755  * IN Token Received with EP Mismatch interrupt
90756  */
90757 #define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_ACT 0x1
90758 
90759 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */
90760 #define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_LSB 5
90761 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */
90762 #define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_MSB 5
90763 /* The width in bits of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */
90764 #define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_WIDTH 1
90765 /* The mask used to set the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field value. */
90766 #define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_SET_MSK 0x00000020
90767 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field value. */
90768 #define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_CLR_MSK 0xffffffdf
90769 /* The reset value of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */
90770 #define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_RESET 0x0
90771 /* Extracts the ALT_USB_DEV_DIEPINT9_INTKNEPMIS field value from a register. */
90772 #define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
90773 /* Produces a ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field value suitable for setting the register. */
90774 #define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
90775 
90776 /*
90777  * Field : inepnakeff
90778  *
90779  * IN Endpoint NAK Effective (INEPNakEff)
90780  *
90781  * Applies to periodic IN endpoints only.
90782  *
90783  * This bit can be cleared when the application clears the IN
90784  *
90785  * endpoint NAK by writing to DIEPCTLn.CNAK.
90786  *
90787  * This interrupt indicates that the core has sampled the NAK bit
90788  *
90789  * Set (either by the application or by the core). The interrupt
90790  *
90791  * indicates that the IN endpoint NAK bit Set by the application has
90792  *
90793  * taken effect in the core.
90794  *
90795  * This interrupt does not guarantee that a NAK handshake is sent
90796  *
90797  * on the USB. A STALL bit takes priority over a NAK bit.
90798  *
90799  * Field Enumeration Values:
90800  *
90801  * Enum | Value | Description
90802  * :----------------------------------------|:------|:------------------------------------
90803  * ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_INACT | 0x0 | No interrupt
90804  * ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
90805  *
90806  * Field Access Macros:
90807  *
90808  */
90809 /*
90810  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INEPNAKEFF
90811  *
90812  * No interrupt
90813  */
90814 #define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_INACT 0x0
90815 /*
90816  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_INEPNAKEFF
90817  *
90818  * IN Endpoint NAK Effective interrupt
90819  */
90820 #define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_ACT 0x1
90821 
90822 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */
90823 #define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_LSB 6
90824 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */
90825 #define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_MSB 6
90826 /* The width in bits of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */
90827 #define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_WIDTH 1
90828 /* The mask used to set the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field value. */
90829 #define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_SET_MSK 0x00000040
90830 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field value. */
90831 #define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_CLR_MSK 0xffffffbf
90832 /* The reset value of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */
90833 #define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_RESET 0x0
90834 /* Extracts the ALT_USB_DEV_DIEPINT9_INEPNAKEFF field value from a register. */
90835 #define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
90836 /* Produces a ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field value suitable for setting the register. */
90837 #define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
90838 
90839 /*
90840  * Field : txfemp
90841  *
90842  * Transmit FIFO Empty (TxFEmp)
90843  *
90844  * This bit is valid only For IN Endpoints
90845  *
90846  * This interrupt is asserted when the TxFIFO For this endpoint is
90847  *
90848  * either half or completely empty. The half or completely empty
90849  *
90850  * status is determined by the TxFIFO Empty Level bit in the Core
90851  *
90852  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
90853  *
90854  * Field Enumeration Values:
90855  *
90856  * Enum | Value | Description
90857  * :------------------------------------|:------|:------------------------------
90858  * ALT_USB_DEV_DIEPINT9_TXFEMP_E_INACT | 0x0 | No interrupt
90859  * ALT_USB_DEV_DIEPINT9_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
90860  *
90861  * Field Access Macros:
90862  *
90863  */
90864 /*
90865  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFEMP
90866  *
90867  * No interrupt
90868  */
90869 #define ALT_USB_DEV_DIEPINT9_TXFEMP_E_INACT 0x0
90870 /*
90871  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFEMP
90872  *
90873  * Transmit FIFO Empty interrupt
90874  */
90875 #define ALT_USB_DEV_DIEPINT9_TXFEMP_E_ACT 0x1
90876 
90877 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */
90878 #define ALT_USB_DEV_DIEPINT9_TXFEMP_LSB 7
90879 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */
90880 #define ALT_USB_DEV_DIEPINT9_TXFEMP_MSB 7
90881 /* The width in bits of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */
90882 #define ALT_USB_DEV_DIEPINT9_TXFEMP_WIDTH 1
90883 /* The mask used to set the ALT_USB_DEV_DIEPINT9_TXFEMP register field value. */
90884 #define ALT_USB_DEV_DIEPINT9_TXFEMP_SET_MSK 0x00000080
90885 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_TXFEMP register field value. */
90886 #define ALT_USB_DEV_DIEPINT9_TXFEMP_CLR_MSK 0xffffff7f
90887 /* The reset value of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */
90888 #define ALT_USB_DEV_DIEPINT9_TXFEMP_RESET 0x1
90889 /* Extracts the ALT_USB_DEV_DIEPINT9_TXFEMP field value from a register. */
90890 #define ALT_USB_DEV_DIEPINT9_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
90891 /* Produces a ALT_USB_DEV_DIEPINT9_TXFEMP register field value suitable for setting the register. */
90892 #define ALT_USB_DEV_DIEPINT9_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
90893 
90894 /*
90895  * Field : txfifoundrn
90896  *
90897  * Fifo Underrun (TxfifoUndrn)
90898  *
90899  * Applies to IN endpoints Only
90900  *
90901  * This bit is valid only If thresholding is enabled. The core generates this
90902  * interrupt when
90903  *
90904  * it detects a transmit FIFO underrun condition For this endpoint.
90905  *
90906  * Field Enumeration Values:
90907  *
90908  * Enum | Value | Description
90909  * :-----------------------------------------|:------|:------------------------
90910  * ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
90911  * ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
90912  *
90913  * Field Access Macros:
90914  *
90915  */
90916 /*
90917  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN
90918  *
90919  * No interrupt
90920  */
90921 #define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_INACT 0x0
90922 /*
90923  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN
90924  *
90925  * Fifo Underrun interrupt
90926  */
90927 #define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_ACT 0x1
90928 
90929 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */
90930 #define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_LSB 8
90931 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */
90932 #define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_MSB 8
90933 /* The width in bits of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */
90934 #define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_WIDTH 1
90935 /* The mask used to set the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field value. */
90936 #define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_SET_MSK 0x00000100
90937 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field value. */
90938 #define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_CLR_MSK 0xfffffeff
90939 /* The reset value of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */
90940 #define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_RESET 0x0
90941 /* Extracts the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN field value from a register. */
90942 #define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
90943 /* Produces a ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field value suitable for setting the register. */
90944 #define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
90945 
90946 /*
90947  * Field : bnaintr
90948  *
90949  * BNA (Buffer Not Available) Interrupt (BNAIntr)
90950  *
90951  * This bit is valid only when Scatter/Gather DMA mode is enabled.
90952  *
90953  * The core generates this interrupt when the descriptor accessed
90954  *
90955  * is not ready For the Core to process, such as Host busy or DMA
90956  *
90957  * done
90958  *
90959  * Field Enumeration Values:
90960  *
90961  * Enum | Value | Description
90962  * :-------------------------------------|:------|:--------------
90963  * ALT_USB_DEV_DIEPINT9_BNAINTR_E_INACT | 0x0 | No interrupt
90964  * ALT_USB_DEV_DIEPINT9_BNAINTR_E_ACT | 0x1 | BNA interrupt
90965  *
90966  * Field Access Macros:
90967  *
90968  */
90969 /*
90970  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_BNAINTR
90971  *
90972  * No interrupt
90973  */
90974 #define ALT_USB_DEV_DIEPINT9_BNAINTR_E_INACT 0x0
90975 /*
90976  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_BNAINTR
90977  *
90978  * BNA interrupt
90979  */
90980 #define ALT_USB_DEV_DIEPINT9_BNAINTR_E_ACT 0x1
90981 
90982 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */
90983 #define ALT_USB_DEV_DIEPINT9_BNAINTR_LSB 9
90984 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */
90985 #define ALT_USB_DEV_DIEPINT9_BNAINTR_MSB 9
90986 /* The width in bits of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */
90987 #define ALT_USB_DEV_DIEPINT9_BNAINTR_WIDTH 1
90988 /* The mask used to set the ALT_USB_DEV_DIEPINT9_BNAINTR register field value. */
90989 #define ALT_USB_DEV_DIEPINT9_BNAINTR_SET_MSK 0x00000200
90990 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_BNAINTR register field value. */
90991 #define ALT_USB_DEV_DIEPINT9_BNAINTR_CLR_MSK 0xfffffdff
90992 /* The reset value of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */
90993 #define ALT_USB_DEV_DIEPINT9_BNAINTR_RESET 0x0
90994 /* Extracts the ALT_USB_DEV_DIEPINT9_BNAINTR field value from a register. */
90995 #define ALT_USB_DEV_DIEPINT9_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
90996 /* Produces a ALT_USB_DEV_DIEPINT9_BNAINTR register field value suitable for setting the register. */
90997 #define ALT_USB_DEV_DIEPINT9_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
90998 
90999 /*
91000  * Field : pktdrpsts
91001  *
91002  * Packet Drop Status (PktDrpSts)
91003  *
91004  * This bit indicates to the application that an ISOC OUT packet has been dropped.
91005  * This
91006  *
91007  * bit does not have an associated mask bit and does not generate an interrupt.
91008  *
91009  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
91010  * transfer
91011  *
91012  * interrupt feature is selected.
91013  *
91014  * Field Enumeration Values:
91015  *
91016  * Enum | Value | Description
91017  * :---------------------------------------|:------|:-----------------------------
91018  * ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_INACT | 0x0 | No interrupt
91019  * ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
91020  *
91021  * Field Access Macros:
91022  *
91023  */
91024 /*
91025  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_PKTDRPSTS
91026  *
91027  * No interrupt
91028  */
91029 #define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_INACT 0x0
91030 /*
91031  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_PKTDRPSTS
91032  *
91033  * Packet Drop Status interrupt
91034  */
91035 #define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_ACT 0x1
91036 
91037 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */
91038 #define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_LSB 11
91039 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */
91040 #define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_MSB 11
91041 /* The width in bits of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */
91042 #define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_WIDTH 1
91043 /* The mask used to set the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field value. */
91044 #define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_SET_MSK 0x00000800
91045 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field value. */
91046 #define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_CLR_MSK 0xfffff7ff
91047 /* The reset value of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */
91048 #define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_RESET 0x0
91049 /* Extracts the ALT_USB_DEV_DIEPINT9_PKTDRPSTS field value from a register. */
91050 #define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
91051 /* Produces a ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field value suitable for setting the register. */
91052 #define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
91053 
91054 /*
91055  * Field : bbleerr
91056  *
91057  * NAK Interrupt (BbleErr)
91058  *
91059  * The core generates this interrupt when babble is received for the endpoint.
91060  *
91061  * Field Enumeration Values:
91062  *
91063  * Enum | Value | Description
91064  * :-------------------------------------|:------|:------------------
91065  * ALT_USB_DEV_DIEPINT9_BBLEERR_E_INACT | 0x0 | No interrupt
91066  * ALT_USB_DEV_DIEPINT9_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
91067  *
91068  * Field Access Macros:
91069  *
91070  */
91071 /*
91072  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_BBLEERR
91073  *
91074  * No interrupt
91075  */
91076 #define ALT_USB_DEV_DIEPINT9_BBLEERR_E_INACT 0x0
91077 /*
91078  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_BBLEERR
91079  *
91080  * BbleErr interrupt
91081  */
91082 #define ALT_USB_DEV_DIEPINT9_BBLEERR_E_ACT 0x1
91083 
91084 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */
91085 #define ALT_USB_DEV_DIEPINT9_BBLEERR_LSB 12
91086 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */
91087 #define ALT_USB_DEV_DIEPINT9_BBLEERR_MSB 12
91088 /* The width in bits of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */
91089 #define ALT_USB_DEV_DIEPINT9_BBLEERR_WIDTH 1
91090 /* The mask used to set the ALT_USB_DEV_DIEPINT9_BBLEERR register field value. */
91091 #define ALT_USB_DEV_DIEPINT9_BBLEERR_SET_MSK 0x00001000
91092 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_BBLEERR register field value. */
91093 #define ALT_USB_DEV_DIEPINT9_BBLEERR_CLR_MSK 0xffffefff
91094 /* The reset value of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */
91095 #define ALT_USB_DEV_DIEPINT9_BBLEERR_RESET 0x0
91096 /* Extracts the ALT_USB_DEV_DIEPINT9_BBLEERR field value from a register. */
91097 #define ALT_USB_DEV_DIEPINT9_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
91098 /* Produces a ALT_USB_DEV_DIEPINT9_BBLEERR register field value suitable for setting the register. */
91099 #define ALT_USB_DEV_DIEPINT9_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
91100 
91101 /*
91102  * Field : nakintrpt
91103  *
91104  * NAK Interrupt (NAKInterrupt)
91105  *
91106  * The core generates this interrupt when a NAK is transmitted or received by the
91107  * device.
91108  *
91109  * In case of isochronous IN endpoints the interrupt gets generated when a zero
91110  * length
91111  *
91112  * packet is transmitted due to un-availability of data in the TXFifo.
91113  *
91114  * Field Enumeration Values:
91115  *
91116  * Enum | Value | Description
91117  * :---------------------------------------|:------|:--------------
91118  * ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_INACT | 0x0 | No interrupt
91119  * ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
91120  *
91121  * Field Access Macros:
91122  *
91123  */
91124 /*
91125  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_NAKINTRPT
91126  *
91127  * No interrupt
91128  */
91129 #define ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_INACT 0x0
91130 /*
91131  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_NAKINTRPT
91132  *
91133  * NAK Interrupt
91134  */
91135 #define ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_ACT 0x1
91136 
91137 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */
91138 #define ALT_USB_DEV_DIEPINT9_NAKINTRPT_LSB 13
91139 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */
91140 #define ALT_USB_DEV_DIEPINT9_NAKINTRPT_MSB 13
91141 /* The width in bits of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */
91142 #define ALT_USB_DEV_DIEPINT9_NAKINTRPT_WIDTH 1
91143 /* The mask used to set the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field value. */
91144 #define ALT_USB_DEV_DIEPINT9_NAKINTRPT_SET_MSK 0x00002000
91145 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field value. */
91146 #define ALT_USB_DEV_DIEPINT9_NAKINTRPT_CLR_MSK 0xffffdfff
91147 /* The reset value of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */
91148 #define ALT_USB_DEV_DIEPINT9_NAKINTRPT_RESET 0x0
91149 /* Extracts the ALT_USB_DEV_DIEPINT9_NAKINTRPT field value from a register. */
91150 #define ALT_USB_DEV_DIEPINT9_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
91151 /* Produces a ALT_USB_DEV_DIEPINT9_NAKINTRPT register field value suitable for setting the register. */
91152 #define ALT_USB_DEV_DIEPINT9_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
91153 
91154 /*
91155  * Field : nyetintrpt
91156  *
91157  * NYET Interrupt (NYETIntrpt)
91158  *
91159  * The core generates this interrupt when a NYET response is transmitted for a non
91160  * isochronous OUT endpoint.
91161  *
91162  * Field Enumeration Values:
91163  *
91164  * Enum | Value | Description
91165  * :----------------------------------------|:------|:---------------
91166  * ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_INACT | 0x0 | No interrupt
91167  * ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
91168  *
91169  * Field Access Macros:
91170  *
91171  */
91172 /*
91173  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_NYETINTRPT
91174  *
91175  * No interrupt
91176  */
91177 #define ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_INACT 0x0
91178 /*
91179  * Enumerated value for register field ALT_USB_DEV_DIEPINT9_NYETINTRPT
91180  *
91181  * NYET Interrupt
91182  */
91183 #define ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_ACT 0x1
91184 
91185 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */
91186 #define ALT_USB_DEV_DIEPINT9_NYETINTRPT_LSB 14
91187 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */
91188 #define ALT_USB_DEV_DIEPINT9_NYETINTRPT_MSB 14
91189 /* The width in bits of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */
91190 #define ALT_USB_DEV_DIEPINT9_NYETINTRPT_WIDTH 1
91191 /* The mask used to set the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field value. */
91192 #define ALT_USB_DEV_DIEPINT9_NYETINTRPT_SET_MSK 0x00004000
91193 /* The mask used to clear the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field value. */
91194 #define ALT_USB_DEV_DIEPINT9_NYETINTRPT_CLR_MSK 0xffffbfff
91195 /* The reset value of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */
91196 #define ALT_USB_DEV_DIEPINT9_NYETINTRPT_RESET 0x0
91197 /* Extracts the ALT_USB_DEV_DIEPINT9_NYETINTRPT field value from a register. */
91198 #define ALT_USB_DEV_DIEPINT9_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
91199 /* Produces a ALT_USB_DEV_DIEPINT9_NYETINTRPT register field value suitable for setting the register. */
91200 #define ALT_USB_DEV_DIEPINT9_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
91201 
91202 #ifndef __ASSEMBLY__
91203 /*
91204  * WARNING: The C register and register group struct declarations are provided for
91205  * convenience and illustrative purposes. They should, however, be used with
91206  * caution as the C language standard provides no guarantees about the alignment or
91207  * atomicity of device memory accesses. The recommended practice for writing
91208  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
91209  * alt_write_word() functions.
91210  *
91211  * The struct declaration for register ALT_USB_DEV_DIEPINT9.
91212  */
91213 struct ALT_USB_DEV_DIEPINT9_s
91214 {
91215  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT9_XFERCOMPL */
91216  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT9_EPDISBLD */
91217  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT9_AHBERR */
91218  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT9_TMO */
91219  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT9_INTKNTXFEMP */
91220  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT9_INTKNEPMIS */
91221  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT9_INEPNAKEFF */
91222  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT9_TXFEMP */
91223  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN */
91224  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT9_BNAINTR */
91225  uint32_t : 1; /* *UNDEFINED* */
91226  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT9_PKTDRPSTS */
91227  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT9_BBLEERR */
91228  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT9_NAKINTRPT */
91229  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT9_NYETINTRPT */
91230  uint32_t : 17; /* *UNDEFINED* */
91231 };
91232 
91233 /* The typedef declaration for register ALT_USB_DEV_DIEPINT9. */
91234 typedef volatile struct ALT_USB_DEV_DIEPINT9_s ALT_USB_DEV_DIEPINT9_t;
91235 #endif /* __ASSEMBLY__ */
91236 
91237 /* The reset value of the ALT_USB_DEV_DIEPINT9 register. */
91238 #define ALT_USB_DEV_DIEPINT9_RESET 0x00000080
91239 /* The byte offset of the ALT_USB_DEV_DIEPINT9 register from the beginning of the component. */
91240 #define ALT_USB_DEV_DIEPINT9_OFST 0x228
91241 /* The address of the ALT_USB_DEV_DIEPINT9 register. */
91242 #define ALT_USB_DEV_DIEPINT9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT9_OFST))
91243 
91244 /*
91245  * Register : dieptsiz9
91246  *
91247  * Device IN Endpoint 9 Transfer Size Register
91248  *
91249  * Register Layout
91250  *
91251  * Bits | Access | Reset | Description
91252  * :--------|:-------|:------|:-------------------------------
91253  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ9_XFERSIZE
91254  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ9_PKTCNT
91255  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ9_MC
91256  * [31] | ??? | 0x0 | *UNDEFINED*
91257  *
91258  */
91259 /*
91260  * Field : xfersize
91261  *
91262  * Transfer Size (XferSize)
91263  *
91264  * Indicates the transfer size in bytes For endpoint 0. The core
91265  *
91266  * interrupts the application only after it has exhausted the transfer
91267  *
91268  * size amount of data. The transfer size can be Set to the
91269  *
91270  * maximum packet size of the endpoint, to be interrupted at the
91271  *
91272  * end of each packet.
91273  *
91274  * The core decrements this field every time a packet from the
91275  *
91276  * external memory is written to the TxFIFO.
91277  *
91278  * Field Access Macros:
91279  *
91280  */
91281 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */
91282 #define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_LSB 0
91283 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */
91284 #define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_MSB 18
91285 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */
91286 #define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_WIDTH 19
91287 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field value. */
91288 #define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_SET_MSK 0x0007ffff
91289 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field value. */
91290 #define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_CLR_MSK 0xfff80000
91291 /* The reset value of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */
91292 #define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_RESET 0x0
91293 /* Extracts the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE field value from a register. */
91294 #define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
91295 /* Produces a ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field value suitable for setting the register. */
91296 #define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
91297 
91298 /*
91299  * Field : pktcnt
91300  *
91301  * Packet Count (PktCnt)
91302  *
91303  * Indicates the total number of USB packets that constitute the
91304  *
91305  * Transfer Size amount of data For endpoint 0.
91306  *
91307  * This field is decremented every time a packet (maximum size or
91308  *
91309  * short packet) is read from the TxFIFO.
91310  *
91311  * Field Access Macros:
91312  *
91313  */
91314 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */
91315 #define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_LSB 19
91316 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */
91317 #define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_MSB 28
91318 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */
91319 #define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_WIDTH 10
91320 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field value. */
91321 #define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_SET_MSK 0x1ff80000
91322 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field value. */
91323 #define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_CLR_MSK 0xe007ffff
91324 /* The reset value of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */
91325 #define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_RESET 0x0
91326 /* Extracts the ALT_USB_DEV_DIEPTSIZ9_PKTCNT field value from a register. */
91327 #define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
91328 /* Produces a ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field value suitable for setting the register. */
91329 #define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
91330 
91331 /*
91332  * Field : mc
91333  *
91334  * Applies to IN endpoints only.
91335  *
91336  * For periodic IN endpoints, this field indicates the number of packets that must
91337  * be transmitted per microframe on the USB. The core uses this field to calculate
91338  * the data PID for isochronous IN endpoints.
91339  *
91340  * 2'b01: 1 packet
91341  *
91342  * 2'b10: 2 packets
91343  *
91344  * 2'b11: 3 packets
91345  *
91346  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
91347  * specifies the number of packets the core must fetchfor an IN endpoint before it
91348  * switches to the endpoint pointed to by the Next Endpoint field of the Device
91349  * Endpoint-n Control register (DIEPCTLn.NextEp)
91350  *
91351  * Field Enumeration Values:
91352  *
91353  * Enum | Value | Description
91354  * :------------------------------------|:------|:------------
91355  * ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTONE | 0x1 | 1 packet
91356  * ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTWO | 0x2 | 2 packets
91357  * ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTHREE | 0x3 | 3 packets
91358  *
91359  * Field Access Macros:
91360  *
91361  */
91362 /*
91363  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ9_MC
91364  *
91365  * 1 packet
91366  */
91367 #define ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTONE 0x1
91368 /*
91369  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ9_MC
91370  *
91371  * 2 packets
91372  */
91373 #define ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTWO 0x2
91374 /*
91375  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ9_MC
91376  *
91377  * 3 packets
91378  */
91379 #define ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTHREE 0x3
91380 
91381 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */
91382 #define ALT_USB_DEV_DIEPTSIZ9_MC_LSB 29
91383 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */
91384 #define ALT_USB_DEV_DIEPTSIZ9_MC_MSB 30
91385 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */
91386 #define ALT_USB_DEV_DIEPTSIZ9_MC_WIDTH 2
91387 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ9_MC register field value. */
91388 #define ALT_USB_DEV_DIEPTSIZ9_MC_SET_MSK 0x60000000
91389 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ9_MC register field value. */
91390 #define ALT_USB_DEV_DIEPTSIZ9_MC_CLR_MSK 0x9fffffff
91391 /* The reset value of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */
91392 #define ALT_USB_DEV_DIEPTSIZ9_MC_RESET 0x0
91393 /* Extracts the ALT_USB_DEV_DIEPTSIZ9_MC field value from a register. */
91394 #define ALT_USB_DEV_DIEPTSIZ9_MC_GET(value) (((value) & 0x60000000) >> 29)
91395 /* Produces a ALT_USB_DEV_DIEPTSIZ9_MC register field value suitable for setting the register. */
91396 #define ALT_USB_DEV_DIEPTSIZ9_MC_SET(value) (((value) << 29) & 0x60000000)
91397 
91398 #ifndef __ASSEMBLY__
91399 /*
91400  * WARNING: The C register and register group struct declarations are provided for
91401  * convenience and illustrative purposes. They should, however, be used with
91402  * caution as the C language standard provides no guarantees about the alignment or
91403  * atomicity of device memory accesses. The recommended practice for writing
91404  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
91405  * alt_write_word() functions.
91406  *
91407  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ9.
91408  */
91409 struct ALT_USB_DEV_DIEPTSIZ9_s
91410 {
91411  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ9_XFERSIZE */
91412  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ9_PKTCNT */
91413  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ9_MC */
91414  uint32_t : 1; /* *UNDEFINED* */
91415 };
91416 
91417 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ9. */
91418 typedef volatile struct ALT_USB_DEV_DIEPTSIZ9_s ALT_USB_DEV_DIEPTSIZ9_t;
91419 #endif /* __ASSEMBLY__ */
91420 
91421 /* The reset value of the ALT_USB_DEV_DIEPTSIZ9 register. */
91422 #define ALT_USB_DEV_DIEPTSIZ9_RESET 0x00000000
91423 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ9 register from the beginning of the component. */
91424 #define ALT_USB_DEV_DIEPTSIZ9_OFST 0x230
91425 /* The address of the ALT_USB_DEV_DIEPTSIZ9 register. */
91426 #define ALT_USB_DEV_DIEPTSIZ9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ9_OFST))
91427 
91428 /*
91429  * Register : diepdma9
91430  *
91431  * Device IN Endpoint 9 DMA Address Register
91432  *
91433  * Register Layout
91434  *
91435  * Bits | Access | Reset | Description
91436  * :-------|:-------|:--------|:------------------------------
91437  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA9_DIEPDMA9
91438  *
91439  */
91440 /*
91441  * Field : diepdma9
91442  *
91443  * Holds the start address of the external memory for storing or fetching endpoint
91444  *
91445  * data.
91446  *
91447  * Note: For control endpoints, this field stores control OUT data packets as well
91448  * as
91449  *
91450  * SETUP transaction data packets. When more than three SETUP packets are
91451  *
91452  * received back-to-back, the SETUP data packet in the memory is overwritten.
91453  *
91454  * This register is incremented on every AHB transaction. The application can give
91455  *
91456  * only a DWORD-aligned address.
91457  *
91458  * When Scatter/Gather DMA mode is not enabled, the application programs the
91459  *
91460  * start address value in this field.
91461  *
91462  * When Scatter/Gather DMA mode is enabled, this field indicates the base
91463  *
91464  * pointer for the descriptor list.
91465  *
91466  * Field Access Macros:
91467  *
91468  */
91469 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field. */
91470 #define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_LSB 0
91471 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field. */
91472 #define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_MSB 31
91473 /* The width in bits of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field. */
91474 #define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_WIDTH 32
91475 /* The mask used to set the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field value. */
91476 #define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_SET_MSK 0xffffffff
91477 /* The mask used to clear the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field value. */
91478 #define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_CLR_MSK 0x00000000
91479 /* The reset value of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field is UNKNOWN. */
91480 #define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_RESET 0x0
91481 /* Extracts the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 field value from a register. */
91482 #define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_GET(value) (((value) & 0xffffffff) >> 0)
91483 /* Produces a ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field value suitable for setting the register. */
91484 #define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_SET(value) (((value) << 0) & 0xffffffff)
91485 
91486 #ifndef __ASSEMBLY__
91487 /*
91488  * WARNING: The C register and register group struct declarations are provided for
91489  * convenience and illustrative purposes. They should, however, be used with
91490  * caution as the C language standard provides no guarantees about the alignment or
91491  * atomicity of device memory accesses. The recommended practice for writing
91492  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
91493  * alt_write_word() functions.
91494  *
91495  * The struct declaration for register ALT_USB_DEV_DIEPDMA9.
91496  */
91497 struct ALT_USB_DEV_DIEPDMA9_s
91498 {
91499  uint32_t diepdma9 : 32; /* ALT_USB_DEV_DIEPDMA9_DIEPDMA9 */
91500 };
91501 
91502 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA9. */
91503 typedef volatile struct ALT_USB_DEV_DIEPDMA9_s ALT_USB_DEV_DIEPDMA9_t;
91504 #endif /* __ASSEMBLY__ */
91505 
91506 /* The reset value of the ALT_USB_DEV_DIEPDMA9 register. */
91507 #define ALT_USB_DEV_DIEPDMA9_RESET 0x00000000
91508 /* The byte offset of the ALT_USB_DEV_DIEPDMA9 register from the beginning of the component. */
91509 #define ALT_USB_DEV_DIEPDMA9_OFST 0x234
91510 /* The address of the ALT_USB_DEV_DIEPDMA9 register. */
91511 #define ALT_USB_DEV_DIEPDMA9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA9_OFST))
91512 
91513 /*
91514  * Register : dtxfsts9
91515  *
91516  * Device IN Endpoint Transmit FIFO Status Register 9
91517  *
91518  * Register Layout
91519  *
91520  * Bits | Access | Reset | Description
91521  * :--------|:-------|:-------|:-------------------------------------
91522  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL
91523  * [31:16] | ??? | 0x0 | *UNDEFINED*
91524  *
91525  */
91526 /*
91527  * Field : ineptxfspcavail
91528  *
91529  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
91530  *
91531  * Indicates the amount of free space available in the Endpoint
91532  *
91533  * TxFIFO.
91534  *
91535  * Values are in terms of 32-bit words.
91536  *
91537  * 16'h0: Endpoint TxFIFO is full
91538  *
91539  * 16'h1: 1 word available
91540  *
91541  * 16'h2: 2 words available
91542  *
91543  * 16'hn: n words available (where 0 n 32,768)
91544  *
91545  * 16'h8000: 32,768 words available
91546  *
91547  * Others: Reserved
91548  *
91549  * Field Access Macros:
91550  *
91551  */
91552 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */
91553 #define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_LSB 0
91554 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */
91555 #define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_MSB 15
91556 /* The width in bits of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */
91557 #define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_WIDTH 16
91558 /* The mask used to set the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field value. */
91559 #define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
91560 /* The mask used to clear the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field value. */
91561 #define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
91562 /* The reset value of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */
91563 #define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_RESET 0x2000
91564 /* Extracts the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL field value from a register. */
91565 #define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
91566 /* Produces a ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field value suitable for setting the register. */
91567 #define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
91568 
91569 #ifndef __ASSEMBLY__
91570 /*
91571  * WARNING: The C register and register group struct declarations are provided for
91572  * convenience and illustrative purposes. They should, however, be used with
91573  * caution as the C language standard provides no guarantees about the alignment or
91574  * atomicity of device memory accesses. The recommended practice for writing
91575  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
91576  * alt_write_word() functions.
91577  *
91578  * The struct declaration for register ALT_USB_DEV_DTXFSTS9.
91579  */
91580 struct ALT_USB_DEV_DTXFSTS9_s
91581 {
91582  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL */
91583  uint32_t : 16; /* *UNDEFINED* */
91584 };
91585 
91586 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS9. */
91587 typedef volatile struct ALT_USB_DEV_DTXFSTS9_s ALT_USB_DEV_DTXFSTS9_t;
91588 #endif /* __ASSEMBLY__ */
91589 
91590 /* The reset value of the ALT_USB_DEV_DTXFSTS9 register. */
91591 #define ALT_USB_DEV_DTXFSTS9_RESET 0x00002000
91592 /* The byte offset of the ALT_USB_DEV_DTXFSTS9 register from the beginning of the component. */
91593 #define ALT_USB_DEV_DTXFSTS9_OFST 0x238
91594 /* The address of the ALT_USB_DEV_DTXFSTS9 register. */
91595 #define ALT_USB_DEV_DTXFSTS9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS9_OFST))
91596 
91597 /*
91598  * Register : diepdmab9
91599  *
91600  * Device IN Endpoint 9 Buffer Address Register
91601  *
91602  * Register Layout
91603  *
91604  * Bits | Access | Reset | Description
91605  * :-------|:-------|:--------|:--------------------------------
91606  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9
91607  *
91608  */
91609 /*
91610  * Field : diepdmab9
91611  *
91612  * Holds the current buffer address.This register is updated as and when the data
91613  *
91614  * transfer for the corresponding end point is in progress.
91615  *
91616  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
91617  * is
91618  *
91619  * reserved.
91620  *
91621  * Field Access Macros:
91622  *
91623  */
91624 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field. */
91625 #define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_LSB 0
91626 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field. */
91627 #define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_MSB 31
91628 /* The width in bits of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field. */
91629 #define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_WIDTH 32
91630 /* The mask used to set the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field value. */
91631 #define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_SET_MSK 0xffffffff
91632 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field value. */
91633 #define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_CLR_MSK 0x00000000
91634 /* The reset value of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field is UNKNOWN. */
91635 #define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_RESET 0x0
91636 /* Extracts the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 field value from a register. */
91637 #define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_GET(value) (((value) & 0xffffffff) >> 0)
91638 /* Produces a ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field value suitable for setting the register. */
91639 #define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_SET(value) (((value) << 0) & 0xffffffff)
91640 
91641 #ifndef __ASSEMBLY__
91642 /*
91643  * WARNING: The C register and register group struct declarations are provided for
91644  * convenience and illustrative purposes. They should, however, be used with
91645  * caution as the C language standard provides no guarantees about the alignment or
91646  * atomicity of device memory accesses. The recommended practice for writing
91647  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
91648  * alt_write_word() functions.
91649  *
91650  * The struct declaration for register ALT_USB_DEV_DIEPDMAB9.
91651  */
91652 struct ALT_USB_DEV_DIEPDMAB9_s
91653 {
91654  const uint32_t diepdmab9 : 32; /* ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 */
91655 };
91656 
91657 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB9. */
91658 typedef volatile struct ALT_USB_DEV_DIEPDMAB9_s ALT_USB_DEV_DIEPDMAB9_t;
91659 #endif /* __ASSEMBLY__ */
91660 
91661 /* The reset value of the ALT_USB_DEV_DIEPDMAB9 register. */
91662 #define ALT_USB_DEV_DIEPDMAB9_RESET 0x00000000
91663 /* The byte offset of the ALT_USB_DEV_DIEPDMAB9 register from the beginning of the component. */
91664 #define ALT_USB_DEV_DIEPDMAB9_OFST 0x23c
91665 /* The address of the ALT_USB_DEV_DIEPDMAB9 register. */
91666 #define ALT_USB_DEV_DIEPDMAB9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB9_OFST))
91667 
91668 /*
91669  * Register : diepctl10
91670  *
91671  * Device Control IN Endpoint 10 Control Register
91672  *
91673  * Register Layout
91674  *
91675  * Bits | Access | Reset | Description
91676  * :--------|:---------|:------|:-------------------------------
91677  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL10_MPS
91678  * [14:11] | ??? | 0x0 | *UNDEFINED*
91679  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL10_USBACTEP
91680  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL10_DPID
91681  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL10_NAKSTS
91682  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL10_EPTYPE
91683  * [20] | ??? | 0x0 | *UNDEFINED*
91684  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL10_STALL
91685  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL10_TXFNUM
91686  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL10_CNAK
91687  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL10_SNAK
91688  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL10_SETD0PID
91689  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL10_SETD1PID
91690  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL10_EPDIS
91691  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL10_EPENA
91692  *
91693  */
91694 /*
91695  * Field : mps
91696  *
91697  * Maximum Packet Size (MPS)
91698  *
91699  * The application must program this field with the maximum packet size for the
91700  * current
91701  *
91702  * logical endpoint. This value is in bytes.
91703  *
91704  * Field Access Macros:
91705  *
91706  */
91707 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_MPS register field. */
91708 #define ALT_USB_DEV_DIEPCTL10_MPS_LSB 0
91709 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_MPS register field. */
91710 #define ALT_USB_DEV_DIEPCTL10_MPS_MSB 10
91711 /* The width in bits of the ALT_USB_DEV_DIEPCTL10_MPS register field. */
91712 #define ALT_USB_DEV_DIEPCTL10_MPS_WIDTH 11
91713 /* The mask used to set the ALT_USB_DEV_DIEPCTL10_MPS register field value. */
91714 #define ALT_USB_DEV_DIEPCTL10_MPS_SET_MSK 0x000007ff
91715 /* The mask used to clear the ALT_USB_DEV_DIEPCTL10_MPS register field value. */
91716 #define ALT_USB_DEV_DIEPCTL10_MPS_CLR_MSK 0xfffff800
91717 /* The reset value of the ALT_USB_DEV_DIEPCTL10_MPS register field. */
91718 #define ALT_USB_DEV_DIEPCTL10_MPS_RESET 0x0
91719 /* Extracts the ALT_USB_DEV_DIEPCTL10_MPS field value from a register. */
91720 #define ALT_USB_DEV_DIEPCTL10_MPS_GET(value) (((value) & 0x000007ff) >> 0)
91721 /* Produces a ALT_USB_DEV_DIEPCTL10_MPS register field value suitable for setting the register. */
91722 #define ALT_USB_DEV_DIEPCTL10_MPS_SET(value) (((value) << 0) & 0x000007ff)
91723 
91724 /*
91725  * Field : usbactep
91726  *
91727  * USB Active Endpoint (USBActEP)
91728  *
91729  * Indicates whether this endpoint is active in the current configuration and
91730  * interface. The
91731  *
91732  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
91733  * reset. After
91734  *
91735  * receiving the SetConfiguration and SetInterface commands, the application must
91736  *
91737  * program endpoint registers accordingly and set this bit.
91738  *
91739  * Field Enumeration Values:
91740  *
91741  * Enum | Value | Description
91742  * :--------------------------------------|:------|:--------------------
91743  * ALT_USB_DEV_DIEPCTL10_USBACTEP_E_DISD | 0x0 | Not Active
91744  * ALT_USB_DEV_DIEPCTL10_USBACTEP_E_END | 0x1 | USB Active Endpoint
91745  *
91746  * Field Access Macros:
91747  *
91748  */
91749 /*
91750  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_USBACTEP
91751  *
91752  * Not Active
91753  */
91754 #define ALT_USB_DEV_DIEPCTL10_USBACTEP_E_DISD 0x0
91755 /*
91756  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_USBACTEP
91757  *
91758  * USB Active Endpoint
91759  */
91760 #define ALT_USB_DEV_DIEPCTL10_USBACTEP_E_END 0x1
91761 
91762 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */
91763 #define ALT_USB_DEV_DIEPCTL10_USBACTEP_LSB 15
91764 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */
91765 #define ALT_USB_DEV_DIEPCTL10_USBACTEP_MSB 15
91766 /* The width in bits of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */
91767 #define ALT_USB_DEV_DIEPCTL10_USBACTEP_WIDTH 1
91768 /* The mask used to set the ALT_USB_DEV_DIEPCTL10_USBACTEP register field value. */
91769 #define ALT_USB_DEV_DIEPCTL10_USBACTEP_SET_MSK 0x00008000
91770 /* The mask used to clear the ALT_USB_DEV_DIEPCTL10_USBACTEP register field value. */
91771 #define ALT_USB_DEV_DIEPCTL10_USBACTEP_CLR_MSK 0xffff7fff
91772 /* The reset value of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */
91773 #define ALT_USB_DEV_DIEPCTL10_USBACTEP_RESET 0x0
91774 /* Extracts the ALT_USB_DEV_DIEPCTL10_USBACTEP field value from a register. */
91775 #define ALT_USB_DEV_DIEPCTL10_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
91776 /* Produces a ALT_USB_DEV_DIEPCTL10_USBACTEP register field value suitable for setting the register. */
91777 #define ALT_USB_DEV_DIEPCTL10_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
91778 
91779 /*
91780  * Field : dpid
91781  *
91782  * Endpoint Data PID (DPID)
91783  *
91784  * Applies to interrupt/bulk IN and OUT endpoints only.
91785  *
91786  * Contains the PID of the packet to be received or transmitted on this endpoint.
91787  * The
91788  *
91789  * application must program the PID of the first packet to be received or
91790  * transmitted on
91791  *
91792  * this endpoint, after the endpoint is activated. The applications use the
91793  * SetD1PID and
91794  *
91795  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
91796  *
91797  * 1'b0: DATA0
91798  *
91799  * 1'b1: DATA1
91800  *
91801  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
91802  *
91803  * DMA mode.
91804  *
91805  * 1'b0 RO
91806  *
91807  * Even/Odd (Micro)Frame (EO_FrNum)
91808  *
91809  * In non-Scatter/Gather DMA mode:
91810  *
91811  * Applies to isochronous IN and OUT endpoints only.
91812  *
91813  * Indicates the (micro)frame number in which the core transmits/receives
91814  * isochronous
91815  *
91816  * data for this endpoint. The application must program the even/odd (micro) frame
91817  *
91818  * number in which it intends to transmit/receive isochronous data for this
91819  * endpoint using
91820  *
91821  * the SetEvnFr and SetOddFr fields in this register.
91822  *
91823  * 1'b0: Even (micro)frame
91824  *
91825  * 1'b1: Odd (micro)frame
91826  *
91827  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
91828  * number
91829  *
91830  * in which to send data is provided in the transmit descriptor structure. The
91831  * frame in
91832  *
91833  * which data is received is updated in receive descriptor structure.
91834  *
91835  * Field Enumeration Values:
91836  *
91837  * Enum | Value | Description
91838  * :-----------------------------------|:------|:-----------------------------
91839  * ALT_USB_DEV_DIEPCTL10_DPID_E_INACT | 0x0 | Endpoint Data PID not active
91840  * ALT_USB_DEV_DIEPCTL10_DPID_E_ACT | 0x1 | Endpoint Data PID active
91841  *
91842  * Field Access Macros:
91843  *
91844  */
91845 /*
91846  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_DPID
91847  *
91848  * Endpoint Data PID not active
91849  */
91850 #define ALT_USB_DEV_DIEPCTL10_DPID_E_INACT 0x0
91851 /*
91852  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_DPID
91853  *
91854  * Endpoint Data PID active
91855  */
91856 #define ALT_USB_DEV_DIEPCTL10_DPID_E_ACT 0x1
91857 
91858 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_DPID register field. */
91859 #define ALT_USB_DEV_DIEPCTL10_DPID_LSB 16
91860 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_DPID register field. */
91861 #define ALT_USB_DEV_DIEPCTL10_DPID_MSB 16
91862 /* The width in bits of the ALT_USB_DEV_DIEPCTL10_DPID register field. */
91863 #define ALT_USB_DEV_DIEPCTL10_DPID_WIDTH 1
91864 /* The mask used to set the ALT_USB_DEV_DIEPCTL10_DPID register field value. */
91865 #define ALT_USB_DEV_DIEPCTL10_DPID_SET_MSK 0x00010000
91866 /* The mask used to clear the ALT_USB_DEV_DIEPCTL10_DPID register field value. */
91867 #define ALT_USB_DEV_DIEPCTL10_DPID_CLR_MSK 0xfffeffff
91868 /* The reset value of the ALT_USB_DEV_DIEPCTL10_DPID register field. */
91869 #define ALT_USB_DEV_DIEPCTL10_DPID_RESET 0x0
91870 /* Extracts the ALT_USB_DEV_DIEPCTL10_DPID field value from a register. */
91871 #define ALT_USB_DEV_DIEPCTL10_DPID_GET(value) (((value) & 0x00010000) >> 16)
91872 /* Produces a ALT_USB_DEV_DIEPCTL10_DPID register field value suitable for setting the register. */
91873 #define ALT_USB_DEV_DIEPCTL10_DPID_SET(value) (((value) << 16) & 0x00010000)
91874 
91875 /*
91876  * Field : naksts
91877  *
91878  * NAK Status (NAKSts)
91879  *
91880  * Indicates the following:
91881  *
91882  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
91883  *
91884  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
91885  *
91886  * When either the application or the core sets this bit:
91887  *
91888  * The core stops receiving any data on an OUT endpoint, even if there is space in
91889  *
91890  * the RxFIFO to accommodate the incoming packet.
91891  *
91892  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
91893  *
91894  * endpoint, even if there data is available in the TxFIFO.
91895  *
91896  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
91897  *
91898  * if there data is available in the TxFIFO.
91899  *
91900  * Irrespective of this bit's setting, the core always responds to SETUP data
91901  * packets with
91902  *
91903  * an ACK handshake.
91904  *
91905  * Field Enumeration Values:
91906  *
91907  * Enum | Value | Description
91908  * :--------------------------------------|:------|:------------------------------------------------
91909  * ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
91910  * : | | based on the FIFO status
91911  * ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
91912  * : | | endpoint
91913  *
91914  * Field Access Macros:
91915  *
91916  */
91917 /*
91918  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_NAKSTS
91919  *
91920  * The core is transmitting non-NAK handshakes based on the FIFO status
91921  */
91922 #define ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NONNAK 0x0
91923 /*
91924  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_NAKSTS
91925  *
91926  * The core is transmitting NAK handshakes on this endpoint
91927  */
91928 #define ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NAK 0x1
91929 
91930 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */
91931 #define ALT_USB_DEV_DIEPCTL10_NAKSTS_LSB 17
91932 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */
91933 #define ALT_USB_DEV_DIEPCTL10_NAKSTS_MSB 17
91934 /* The width in bits of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */
91935 #define ALT_USB_DEV_DIEPCTL10_NAKSTS_WIDTH 1
91936 /* The mask used to set the ALT_USB_DEV_DIEPCTL10_NAKSTS register field value. */
91937 #define ALT_USB_DEV_DIEPCTL10_NAKSTS_SET_MSK 0x00020000
91938 /* The mask used to clear the ALT_USB_DEV_DIEPCTL10_NAKSTS register field value. */
91939 #define ALT_USB_DEV_DIEPCTL10_NAKSTS_CLR_MSK 0xfffdffff
91940 /* The reset value of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */
91941 #define ALT_USB_DEV_DIEPCTL10_NAKSTS_RESET 0x0
91942 /* Extracts the ALT_USB_DEV_DIEPCTL10_NAKSTS field value from a register. */
91943 #define ALT_USB_DEV_DIEPCTL10_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
91944 /* Produces a ALT_USB_DEV_DIEPCTL10_NAKSTS register field value suitable for setting the register. */
91945 #define ALT_USB_DEV_DIEPCTL10_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
91946 
91947 /*
91948  * Field : eptype
91949  *
91950  * Endpoint Type (EPType)
91951  *
91952  * This is the transfer type supported by this logical endpoint.
91953  *
91954  * 2'b00: Control
91955  *
91956  * 2'b01: Isochronous
91957  *
91958  * 2'b10: Bulk
91959  *
91960  * 2'b11: Interrupt
91961  *
91962  * Field Enumeration Values:
91963  *
91964  * Enum | Value | Description
91965  * :-------------------------------------------|:------|:------------
91966  * ALT_USB_DEV_DIEPCTL10_EPTYPE_E_CTL | 0x0 | Control
91967  * ALT_USB_DEV_DIEPCTL10_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
91968  * ALT_USB_DEV_DIEPCTL10_EPTYPE_E_BULK | 0x2 | Bulk
91969  * ALT_USB_DEV_DIEPCTL10_EPTYPE_E_INTERRUP | 0x3 | Interrupt
91970  *
91971  * Field Access Macros:
91972  *
91973  */
91974 /*
91975  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE
91976  *
91977  * Control
91978  */
91979 #define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_CTL 0x0
91980 /*
91981  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE
91982  *
91983  * Isochronous
91984  */
91985 #define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_ISOCHRONOUS 0x1
91986 /*
91987  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE
91988  *
91989  * Bulk
91990  */
91991 #define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_BULK 0x2
91992 /*
91993  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE
91994  *
91995  * Interrupt
91996  */
91997 #define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_INTERRUP 0x3
91998 
91999 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */
92000 #define ALT_USB_DEV_DIEPCTL10_EPTYPE_LSB 18
92001 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */
92002 #define ALT_USB_DEV_DIEPCTL10_EPTYPE_MSB 19
92003 /* The width in bits of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */
92004 #define ALT_USB_DEV_DIEPCTL10_EPTYPE_WIDTH 2
92005 /* The mask used to set the ALT_USB_DEV_DIEPCTL10_EPTYPE register field value. */
92006 #define ALT_USB_DEV_DIEPCTL10_EPTYPE_SET_MSK 0x000c0000
92007 /* The mask used to clear the ALT_USB_DEV_DIEPCTL10_EPTYPE register field value. */
92008 #define ALT_USB_DEV_DIEPCTL10_EPTYPE_CLR_MSK 0xfff3ffff
92009 /* The reset value of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */
92010 #define ALT_USB_DEV_DIEPCTL10_EPTYPE_RESET 0x0
92011 /* Extracts the ALT_USB_DEV_DIEPCTL10_EPTYPE field value from a register. */
92012 #define ALT_USB_DEV_DIEPCTL10_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
92013 /* Produces a ALT_USB_DEV_DIEPCTL10_EPTYPE register field value suitable for setting the register. */
92014 #define ALT_USB_DEV_DIEPCTL10_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
92015 
92016 /*
92017  * Field : stall
92018  *
92019  * STALL Handshake (Stall)
92020  *
92021  * Applies to non-control, non-isochronous IN and OUT endpoints only.
92022  *
92023  * The application sets this bit to stall all tokens from the USB host to this
92024  * endpoint. If a
92025  *
92026  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
92027  * bit, the
92028  *
92029  * STALL bit takes priority. Only the application can clear this bit, never the
92030  * core.
92031  *
92032  * 1'b0 R_W
92033  *
92034  * Applies to control endpoints only.
92035  *
92036  * The application can only set this bit, and the core clears it, when a SETUP
92037  * token is
92038  *
92039  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
92040  * OUT
92041  *
92042  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
92043  * this bit's
92044  *
92045  * setting, the core always responds to SETUP data packets with an ACK handshake.
92046  *
92047  * Field Enumeration Values:
92048  *
92049  * Enum | Value | Description
92050  * :------------------------------------|:------|:----------------------------
92051  * ALT_USB_DEV_DIEPCTL10_STALL_E_INACT | 0x0 | STALL All Tokens not active
92052  * ALT_USB_DEV_DIEPCTL10_STALL_E_ACT | 0x1 | STALL All Tokens active
92053  *
92054  * Field Access Macros:
92055  *
92056  */
92057 /*
92058  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_STALL
92059  *
92060  * STALL All Tokens not active
92061  */
92062 #define ALT_USB_DEV_DIEPCTL10_STALL_E_INACT 0x0
92063 /*
92064  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_STALL
92065  *
92066  * STALL All Tokens active
92067  */
92068 #define ALT_USB_DEV_DIEPCTL10_STALL_E_ACT 0x1
92069 
92070 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_STALL register field. */
92071 #define ALT_USB_DEV_DIEPCTL10_STALL_LSB 21
92072 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_STALL register field. */
92073 #define ALT_USB_DEV_DIEPCTL10_STALL_MSB 21
92074 /* The width in bits of the ALT_USB_DEV_DIEPCTL10_STALL register field. */
92075 #define ALT_USB_DEV_DIEPCTL10_STALL_WIDTH 1
92076 /* The mask used to set the ALT_USB_DEV_DIEPCTL10_STALL register field value. */
92077 #define ALT_USB_DEV_DIEPCTL10_STALL_SET_MSK 0x00200000
92078 /* The mask used to clear the ALT_USB_DEV_DIEPCTL10_STALL register field value. */
92079 #define ALT_USB_DEV_DIEPCTL10_STALL_CLR_MSK 0xffdfffff
92080 /* The reset value of the ALT_USB_DEV_DIEPCTL10_STALL register field. */
92081 #define ALT_USB_DEV_DIEPCTL10_STALL_RESET 0x0
92082 /* Extracts the ALT_USB_DEV_DIEPCTL10_STALL field value from a register. */
92083 #define ALT_USB_DEV_DIEPCTL10_STALL_GET(value) (((value) & 0x00200000) >> 21)
92084 /* Produces a ALT_USB_DEV_DIEPCTL10_STALL register field value suitable for setting the register. */
92085 #define ALT_USB_DEV_DIEPCTL10_STALL_SET(value) (((value) << 21) & 0x00200000)
92086 
92087 /*
92088  * Field : txfnum
92089  *
92090  * TxFIFO Number (TxFNum)
92091  *
92092  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
92093  *
92094  * endpoints must map this to the corresponding Periodic TxFIFO number.
92095  *
92096  * 4'h0: Non-Periodic TxFIFO
92097  *
92098  * Others: Specified Periodic TxFIFO.number
92099  *
92100  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
92101  *
92102  * applications such as mass storage. The core treats an IN endpoint as a non-
92103  * periodic
92104  *
92105  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
92106  * must be
92107  *
92108  * allocated for an interrupt IN endpoint, and the number of this
92109  *
92110  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
92111  *
92112  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
92113  *
92114  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
92115  *
92116  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
92117  *
92118  * This field is valid only for IN endpoints.
92119  *
92120  * Field Access Macros:
92121  *
92122  */
92123 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */
92124 #define ALT_USB_DEV_DIEPCTL10_TXFNUM_LSB 22
92125 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */
92126 #define ALT_USB_DEV_DIEPCTL10_TXFNUM_MSB 25
92127 /* The width in bits of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */
92128 #define ALT_USB_DEV_DIEPCTL10_TXFNUM_WIDTH 4
92129 /* The mask used to set the ALT_USB_DEV_DIEPCTL10_TXFNUM register field value. */
92130 #define ALT_USB_DEV_DIEPCTL10_TXFNUM_SET_MSK 0x03c00000
92131 /* The mask used to clear the ALT_USB_DEV_DIEPCTL10_TXFNUM register field value. */
92132 #define ALT_USB_DEV_DIEPCTL10_TXFNUM_CLR_MSK 0xfc3fffff
92133 /* The reset value of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */
92134 #define ALT_USB_DEV_DIEPCTL10_TXFNUM_RESET 0x0
92135 /* Extracts the ALT_USB_DEV_DIEPCTL10_TXFNUM field value from a register. */
92136 #define ALT_USB_DEV_DIEPCTL10_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
92137 /* Produces a ALT_USB_DEV_DIEPCTL10_TXFNUM register field value suitable for setting the register. */
92138 #define ALT_USB_DEV_DIEPCTL10_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
92139 
92140 /*
92141  * Field : cnak
92142  *
92143  * Clear NAK (CNAK)
92144  *
92145  * A write to this bit clears the NAK bit For the endpoint.
92146  *
92147  * Field Enumeration Values:
92148  *
92149  * Enum | Value | Description
92150  * :-----------------------------------|:------|:-------------
92151  * ALT_USB_DEV_DIEPCTL10_CNAK_E_INACT | 0x0 | No Clear NAK
92152  * ALT_USB_DEV_DIEPCTL10_CNAK_E_ACT | 0x1 | Clear NAK
92153  *
92154  * Field Access Macros:
92155  *
92156  */
92157 /*
92158  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_CNAK
92159  *
92160  * No Clear NAK
92161  */
92162 #define ALT_USB_DEV_DIEPCTL10_CNAK_E_INACT 0x0
92163 /*
92164  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_CNAK
92165  *
92166  * Clear NAK
92167  */
92168 #define ALT_USB_DEV_DIEPCTL10_CNAK_E_ACT 0x1
92169 
92170 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */
92171 #define ALT_USB_DEV_DIEPCTL10_CNAK_LSB 26
92172 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */
92173 #define ALT_USB_DEV_DIEPCTL10_CNAK_MSB 26
92174 /* The width in bits of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */
92175 #define ALT_USB_DEV_DIEPCTL10_CNAK_WIDTH 1
92176 /* The mask used to set the ALT_USB_DEV_DIEPCTL10_CNAK register field value. */
92177 #define ALT_USB_DEV_DIEPCTL10_CNAK_SET_MSK 0x04000000
92178 /* The mask used to clear the ALT_USB_DEV_DIEPCTL10_CNAK register field value. */
92179 #define ALT_USB_DEV_DIEPCTL10_CNAK_CLR_MSK 0xfbffffff
92180 /* The reset value of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */
92181 #define ALT_USB_DEV_DIEPCTL10_CNAK_RESET 0x0
92182 /* Extracts the ALT_USB_DEV_DIEPCTL10_CNAK field value from a register. */
92183 #define ALT_USB_DEV_DIEPCTL10_CNAK_GET(value) (((value) & 0x04000000) >> 26)
92184 /* Produces a ALT_USB_DEV_DIEPCTL10_CNAK register field value suitable for setting the register. */
92185 #define ALT_USB_DEV_DIEPCTL10_CNAK_SET(value) (((value) << 26) & 0x04000000)
92186 
92187 /*
92188  * Field : snak
92189  *
92190  * Set NAK (SNAK)
92191  *
92192  * A write to this bit sets the NAK bit For the endpoint.
92193  *
92194  * Using this bit, the application can control the transmission of NAK
92195  *
92196  * handshakes on an endpoint. The core can also Set this bit For an
92197  *
92198  * endpoint after a SETUP packet is received on that endpoint.
92199  *
92200  * Field Enumeration Values:
92201  *
92202  * Enum | Value | Description
92203  * :-----------------------------------|:------|:------------
92204  * ALT_USB_DEV_DIEPCTL10_SNAK_E_INACT | 0x0 | No Set NAK
92205  * ALT_USB_DEV_DIEPCTL10_SNAK_E_ACT | 0x1 | Set NAK
92206  *
92207  * Field Access Macros:
92208  *
92209  */
92210 /*
92211  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SNAK
92212  *
92213  * No Set NAK
92214  */
92215 #define ALT_USB_DEV_DIEPCTL10_SNAK_E_INACT 0x0
92216 /*
92217  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SNAK
92218  *
92219  * Set NAK
92220  */
92221 #define ALT_USB_DEV_DIEPCTL10_SNAK_E_ACT 0x1
92222 
92223 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */
92224 #define ALT_USB_DEV_DIEPCTL10_SNAK_LSB 27
92225 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */
92226 #define ALT_USB_DEV_DIEPCTL10_SNAK_MSB 27
92227 /* The width in bits of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */
92228 #define ALT_USB_DEV_DIEPCTL10_SNAK_WIDTH 1
92229 /* The mask used to set the ALT_USB_DEV_DIEPCTL10_SNAK register field value. */
92230 #define ALT_USB_DEV_DIEPCTL10_SNAK_SET_MSK 0x08000000
92231 /* The mask used to clear the ALT_USB_DEV_DIEPCTL10_SNAK register field value. */
92232 #define ALT_USB_DEV_DIEPCTL10_SNAK_CLR_MSK 0xf7ffffff
92233 /* The reset value of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */
92234 #define ALT_USB_DEV_DIEPCTL10_SNAK_RESET 0x0
92235 /* Extracts the ALT_USB_DEV_DIEPCTL10_SNAK field value from a register. */
92236 #define ALT_USB_DEV_DIEPCTL10_SNAK_GET(value) (((value) & 0x08000000) >> 27)
92237 /* Produces a ALT_USB_DEV_DIEPCTL10_SNAK register field value suitable for setting the register. */
92238 #define ALT_USB_DEV_DIEPCTL10_SNAK_SET(value) (((value) << 27) & 0x08000000)
92239 
92240 /*
92241  * Field : setd0pid
92242  *
92243  * Set DATA0 PID (SetD0PID)
92244  *
92245  * Applies to interrupt/bulk IN and OUT endpoints only.
92246  *
92247  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
92248  * to DATA0.
92249  *
92250  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
92251  *
92252  * DMA mode.
92253  *
92254  * 1'b0 WO
92255  *
92256  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
92257  *
92258  * Applies to isochronous IN and OUT endpoints only.
92259  *
92260  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
92261  * (micro)
92262  *
92263  * frame.
92264  *
92265  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
92266  * number
92267  *
92268  * in which to send data is in the transmit descriptor structure. The frame in
92269  * which to
92270  *
92271  * receive data is updated in receive descriptor structure.
92272  *
92273  * Field Enumeration Values:
92274  *
92275  * Enum | Value | Description
92276  * :--------------------------------------|:------|:----------------------------
92277  * ALT_USB_DEV_DIEPCTL10_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
92278  * ALT_USB_DEV_DIEPCTL10_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
92279  *
92280  * Field Access Macros:
92281  *
92282  */
92283 /*
92284  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD0PID
92285  *
92286  * Disables Set DATA0 PID
92287  */
92288 #define ALT_USB_DEV_DIEPCTL10_SETD0PID_E_DISD 0x0
92289 /*
92290  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD0PID
92291  *
92292  * Endpoint Data PID to DATA0)
92293  */
92294 #define ALT_USB_DEV_DIEPCTL10_SETD0PID_E_END 0x1
92295 
92296 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */
92297 #define ALT_USB_DEV_DIEPCTL10_SETD0PID_LSB 28
92298 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */
92299 #define ALT_USB_DEV_DIEPCTL10_SETD0PID_MSB 28
92300 /* The width in bits of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */
92301 #define ALT_USB_DEV_DIEPCTL10_SETD0PID_WIDTH 1
92302 /* The mask used to set the ALT_USB_DEV_DIEPCTL10_SETD0PID register field value. */
92303 #define ALT_USB_DEV_DIEPCTL10_SETD0PID_SET_MSK 0x10000000
92304 /* The mask used to clear the ALT_USB_DEV_DIEPCTL10_SETD0PID register field value. */
92305 #define ALT_USB_DEV_DIEPCTL10_SETD0PID_CLR_MSK 0xefffffff
92306 /* The reset value of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */
92307 #define ALT_USB_DEV_DIEPCTL10_SETD0PID_RESET 0x0
92308 /* Extracts the ALT_USB_DEV_DIEPCTL10_SETD0PID field value from a register. */
92309 #define ALT_USB_DEV_DIEPCTL10_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
92310 /* Produces a ALT_USB_DEV_DIEPCTL10_SETD0PID register field value suitable for setting the register. */
92311 #define ALT_USB_DEV_DIEPCTL10_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
92312 
92313 /*
92314  * Field : setd1pid
92315  *
92316  * Set DATA1 PID (SetD1PID)
92317  *
92318  * Applies to interrupt/bulk IN and OUT endpoints only.
92319  *
92320  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
92321  * to DATA1.
92322  *
92323  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
92324  *
92325  * DMA mode.
92326  *
92327  * Set Odd (micro)frame (SetOddFr)
92328  *
92329  * Applies to isochronous IN and OUT endpoints only.
92330  *
92331  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
92332  *
92333  * (micro)frame.
92334  *
92335  * This field is not applicable for Scatter/Gather DMA mode.
92336  *
92337  * Field Enumeration Values:
92338  *
92339  * Enum | Value | Description
92340  * :--------------------------------------|:------|:-----------------------
92341  * ALT_USB_DEV_DIEPCTL10_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
92342  * ALT_USB_DEV_DIEPCTL10_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
92343  *
92344  * Field Access Macros:
92345  *
92346  */
92347 /*
92348  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD1PID
92349  *
92350  * Disables Set DATA1 PID
92351  */
92352 #define ALT_USB_DEV_DIEPCTL10_SETD1PID_E_DISD 0x0
92353 /*
92354  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD1PID
92355  *
92356  * Enables Set DATA1 PID
92357  */
92358 #define ALT_USB_DEV_DIEPCTL10_SETD1PID_E_END 0x1
92359 
92360 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */
92361 #define ALT_USB_DEV_DIEPCTL10_SETD1PID_LSB 29
92362 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */
92363 #define ALT_USB_DEV_DIEPCTL10_SETD1PID_MSB 29
92364 /* The width in bits of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */
92365 #define ALT_USB_DEV_DIEPCTL10_SETD1PID_WIDTH 1
92366 /* The mask used to set the ALT_USB_DEV_DIEPCTL10_SETD1PID register field value. */
92367 #define ALT_USB_DEV_DIEPCTL10_SETD1PID_SET_MSK 0x20000000
92368 /* The mask used to clear the ALT_USB_DEV_DIEPCTL10_SETD1PID register field value. */
92369 #define ALT_USB_DEV_DIEPCTL10_SETD1PID_CLR_MSK 0xdfffffff
92370 /* The reset value of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */
92371 #define ALT_USB_DEV_DIEPCTL10_SETD1PID_RESET 0x0
92372 /* Extracts the ALT_USB_DEV_DIEPCTL10_SETD1PID field value from a register. */
92373 #define ALT_USB_DEV_DIEPCTL10_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
92374 /* Produces a ALT_USB_DEV_DIEPCTL10_SETD1PID register field value suitable for setting the register. */
92375 #define ALT_USB_DEV_DIEPCTL10_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
92376 
92377 /*
92378  * Field : epdis
92379  *
92380  * Endpoint Disable (EPDis)
92381  *
92382  * Applies to IN and OUT endpoints.
92383  *
92384  * The application sets this bit to stop transmitting/receiving data on an
92385  * endpoint, even
92386  *
92387  * before the transfer for that endpoint is complete. The application must wait for
92388  * the
92389  *
92390  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
92391  * clears
92392  *
92393  * this bit before setting the Endpoint Disabled interrupt. The application must
92394  * set this bit
92395  *
92396  * only if Endpoint Enable is already set for this endpoint.
92397  *
92398  * Field Enumeration Values:
92399  *
92400  * Enum | Value | Description
92401  * :------------------------------------|:------|:--------------------
92402  * ALT_USB_DEV_DIEPCTL10_EPDIS_E_INACT | 0x0 | No Endpoint Disable
92403  * ALT_USB_DEV_DIEPCTL10_EPDIS_E_ACT | 0x1 | Endpoint Disable
92404  *
92405  * Field Access Macros:
92406  *
92407  */
92408 /*
92409  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPDIS
92410  *
92411  * No Endpoint Disable
92412  */
92413 #define ALT_USB_DEV_DIEPCTL10_EPDIS_E_INACT 0x0
92414 /*
92415  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPDIS
92416  *
92417  * Endpoint Disable
92418  */
92419 #define ALT_USB_DEV_DIEPCTL10_EPDIS_E_ACT 0x1
92420 
92421 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */
92422 #define ALT_USB_DEV_DIEPCTL10_EPDIS_LSB 30
92423 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */
92424 #define ALT_USB_DEV_DIEPCTL10_EPDIS_MSB 30
92425 /* The width in bits of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */
92426 #define ALT_USB_DEV_DIEPCTL10_EPDIS_WIDTH 1
92427 /* The mask used to set the ALT_USB_DEV_DIEPCTL10_EPDIS register field value. */
92428 #define ALT_USB_DEV_DIEPCTL10_EPDIS_SET_MSK 0x40000000
92429 /* The mask used to clear the ALT_USB_DEV_DIEPCTL10_EPDIS register field value. */
92430 #define ALT_USB_DEV_DIEPCTL10_EPDIS_CLR_MSK 0xbfffffff
92431 /* The reset value of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */
92432 #define ALT_USB_DEV_DIEPCTL10_EPDIS_RESET 0x0
92433 /* Extracts the ALT_USB_DEV_DIEPCTL10_EPDIS field value from a register. */
92434 #define ALT_USB_DEV_DIEPCTL10_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
92435 /* Produces a ALT_USB_DEV_DIEPCTL10_EPDIS register field value suitable for setting the register. */
92436 #define ALT_USB_DEV_DIEPCTL10_EPDIS_SET(value) (((value) << 30) & 0x40000000)
92437 
92438 /*
92439  * Field : epena
92440  *
92441  * Endpoint Enable (EPEna)
92442  *
92443  * Applies to IN and OUT endpoints.
92444  *
92445  * When Scatter/Gather DMA mode is enabled,
92446  *
92447  * For IN endpoints this bit indicates that the descriptor structure and data
92448  * buffer with
92449  *
92450  * data ready to transmit is setup.
92451  *
92452  * For OUT endpoint it indicates that the descriptor structure and data buffer to
92453  *
92454  * receive data is setup.
92455  *
92456  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
92457  *
92458  * DMA mode:
92459  *
92460  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
92461  * the
92462  *
92463  * endpoint.
92464  *
92465  * * For OUT endpoints, this bit indicates that the application has allocated the
92466  *
92467  * memory to start receiving data from the USB.
92468  *
92469  * * The core clears this bit before setting any of the following interrupts on
92470  * this
92471  *
92472  * endpoint:
92473  *
92474  * SETUP Phase Done
92475  *
92476  * Endpoint Disabled
92477  *
92478  * Transfer Completed
92479  *
92480  * Note: For control endpoints in DMA mode, this bit must be set to be able to
92481  * transfer
92482  *
92483  * SETUP data packets in memory.
92484  *
92485  * Field Enumeration Values:
92486  *
92487  * Enum | Value | Description
92488  * :------------------------------------|:------|:-------------------------
92489  * ALT_USB_DEV_DIEPCTL10_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
92490  * ALT_USB_DEV_DIEPCTL10_EPENA_E_ACT | 0x1 | Endpoint Enable active
92491  *
92492  * Field Access Macros:
92493  *
92494  */
92495 /*
92496  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPENA
92497  *
92498  * Endpoint Enable inactive
92499  */
92500 #define ALT_USB_DEV_DIEPCTL10_EPENA_E_INACT 0x0
92501 /*
92502  * Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPENA
92503  *
92504  * Endpoint Enable active
92505  */
92506 #define ALT_USB_DEV_DIEPCTL10_EPENA_E_ACT 0x1
92507 
92508 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */
92509 #define ALT_USB_DEV_DIEPCTL10_EPENA_LSB 31
92510 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */
92511 #define ALT_USB_DEV_DIEPCTL10_EPENA_MSB 31
92512 /* The width in bits of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */
92513 #define ALT_USB_DEV_DIEPCTL10_EPENA_WIDTH 1
92514 /* The mask used to set the ALT_USB_DEV_DIEPCTL10_EPENA register field value. */
92515 #define ALT_USB_DEV_DIEPCTL10_EPENA_SET_MSK 0x80000000
92516 /* The mask used to clear the ALT_USB_DEV_DIEPCTL10_EPENA register field value. */
92517 #define ALT_USB_DEV_DIEPCTL10_EPENA_CLR_MSK 0x7fffffff
92518 /* The reset value of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */
92519 #define ALT_USB_DEV_DIEPCTL10_EPENA_RESET 0x0
92520 /* Extracts the ALT_USB_DEV_DIEPCTL10_EPENA field value from a register. */
92521 #define ALT_USB_DEV_DIEPCTL10_EPENA_GET(value) (((value) & 0x80000000) >> 31)
92522 /* Produces a ALT_USB_DEV_DIEPCTL10_EPENA register field value suitable for setting the register. */
92523 #define ALT_USB_DEV_DIEPCTL10_EPENA_SET(value) (((value) << 31) & 0x80000000)
92524 
92525 #ifndef __ASSEMBLY__
92526 /*
92527  * WARNING: The C register and register group struct declarations are provided for
92528  * convenience and illustrative purposes. They should, however, be used with
92529  * caution as the C language standard provides no guarantees about the alignment or
92530  * atomicity of device memory accesses. The recommended practice for writing
92531  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
92532  * alt_write_word() functions.
92533  *
92534  * The struct declaration for register ALT_USB_DEV_DIEPCTL10.
92535  */
92536 struct ALT_USB_DEV_DIEPCTL10_s
92537 {
92538  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL10_MPS */
92539  uint32_t : 4; /* *UNDEFINED* */
92540  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL10_USBACTEP */
92541  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL10_DPID */
92542  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL10_NAKSTS */
92543  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL10_EPTYPE */
92544  uint32_t : 1; /* *UNDEFINED* */
92545  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL10_STALL */
92546  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL10_TXFNUM */
92547  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL10_CNAK */
92548  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL10_SNAK */
92549  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL10_SETD0PID */
92550  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL10_SETD1PID */
92551  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL10_EPDIS */
92552  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL10_EPENA */
92553 };
92554 
92555 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL10. */
92556 typedef volatile struct ALT_USB_DEV_DIEPCTL10_s ALT_USB_DEV_DIEPCTL10_t;
92557 #endif /* __ASSEMBLY__ */
92558 
92559 /* The reset value of the ALT_USB_DEV_DIEPCTL10 register. */
92560 #define ALT_USB_DEV_DIEPCTL10_RESET 0x00000000
92561 /* The byte offset of the ALT_USB_DEV_DIEPCTL10 register from the beginning of the component. */
92562 #define ALT_USB_DEV_DIEPCTL10_OFST 0x240
92563 /* The address of the ALT_USB_DEV_DIEPCTL10 register. */
92564 #define ALT_USB_DEV_DIEPCTL10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL10_OFST))
92565 
92566 /*
92567  * Register : diepint10
92568  *
92569  * Device IN Endpoint 10 Interrupt Register
92570  *
92571  * Register Layout
92572  *
92573  * Bits | Access | Reset | Description
92574  * :--------|:-------|:------|:----------------------------------
92575  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_XFERCOMPL
92576  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_EPDISBLD
92577  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_AHBERR
92578  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_TMO
92579  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_INTKNTXFEMP
92580  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_INTKNEPMIS
92581  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_INEPNAKEFF
92582  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT10_TXFEMP
92583  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN
92584  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_BNAINTR
92585  * [10] | ??? | 0x0 | *UNDEFINED*
92586  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_PKTDRPSTS
92587  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_BBLEERR
92588  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_NAKINTRPT
92589  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_NYETINTRPT
92590  * [31:15] | ??? | 0x0 | *UNDEFINED*
92591  *
92592  */
92593 /*
92594  * Field : xfercompl
92595  *
92596  * Transfer Completed Interrupt (XferCompl)
92597  *
92598  * Applies to IN and OUT endpoints.
92599  *
92600  * When Scatter/Gather DMA mode is enabled
92601  *
92602  * * For IN endpoint this field indicates that the requested data
92603  *
92604  * from the descriptor is moved from external system memory
92605  *
92606  * to internal FIFO.
92607  *
92608  * * For OUT endpoint this field indicates that the requested
92609  *
92610  * data from the internal FIFO is moved to external system
92611  *
92612  * memory. This interrupt is generated only when the
92613  *
92614  * corresponding endpoint descriptor is closed, and the IOC
92615  *
92616  * bit For the corresponding descriptor is Set.
92617  *
92618  * When Scatter/Gather DMA mode is disabled, this field
92619  *
92620  * indicates that the programmed transfer is complete on the
92621  *
92622  * AHB as well as on the USB, For this endpoint.
92623  *
92624  * Field Enumeration Values:
92625  *
92626  * Enum | Value | Description
92627  * :----------------------------------------|:------|:-----------------------------
92628  * ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_INACT | 0x0 | No Interrupt
92629  * ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
92630  *
92631  * Field Access Macros:
92632  *
92633  */
92634 /*
92635  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_XFERCOMPL
92636  *
92637  * No Interrupt
92638  */
92639 #define ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_INACT 0x0
92640 /*
92641  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_XFERCOMPL
92642  *
92643  * Transfer Completed Interrupt
92644  */
92645 #define ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_ACT 0x1
92646 
92647 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */
92648 #define ALT_USB_DEV_DIEPINT10_XFERCOMPL_LSB 0
92649 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */
92650 #define ALT_USB_DEV_DIEPINT10_XFERCOMPL_MSB 0
92651 /* The width in bits of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */
92652 #define ALT_USB_DEV_DIEPINT10_XFERCOMPL_WIDTH 1
92653 /* The mask used to set the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field value. */
92654 #define ALT_USB_DEV_DIEPINT10_XFERCOMPL_SET_MSK 0x00000001
92655 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field value. */
92656 #define ALT_USB_DEV_DIEPINT10_XFERCOMPL_CLR_MSK 0xfffffffe
92657 /* The reset value of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */
92658 #define ALT_USB_DEV_DIEPINT10_XFERCOMPL_RESET 0x0
92659 /* Extracts the ALT_USB_DEV_DIEPINT10_XFERCOMPL field value from a register. */
92660 #define ALT_USB_DEV_DIEPINT10_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
92661 /* Produces a ALT_USB_DEV_DIEPINT10_XFERCOMPL register field value suitable for setting the register. */
92662 #define ALT_USB_DEV_DIEPINT10_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
92663 
92664 /*
92665  * Field : epdisbld
92666  *
92667  * Endpoint Disabled Interrupt (EPDisbld)
92668  *
92669  * Applies to IN and OUT endpoints.
92670  *
92671  * This bit indicates that the endpoint is disabled per the
92672  *
92673  * application's request.
92674  *
92675  * Field Enumeration Values:
92676  *
92677  * Enum | Value | Description
92678  * :---------------------------------------|:------|:----------------------------
92679  * ALT_USB_DEV_DIEPINT10_EPDISBLD_E_INACT | 0x0 | No Interrupt
92680  * ALT_USB_DEV_DIEPINT10_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
92681  *
92682  * Field Access Macros:
92683  *
92684  */
92685 /*
92686  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_EPDISBLD
92687  *
92688  * No Interrupt
92689  */
92690 #define ALT_USB_DEV_DIEPINT10_EPDISBLD_E_INACT 0x0
92691 /*
92692  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_EPDISBLD
92693  *
92694  * Endpoint Disabled Interrupt
92695  */
92696 #define ALT_USB_DEV_DIEPINT10_EPDISBLD_E_ACT 0x1
92697 
92698 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */
92699 #define ALT_USB_DEV_DIEPINT10_EPDISBLD_LSB 1
92700 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */
92701 #define ALT_USB_DEV_DIEPINT10_EPDISBLD_MSB 1
92702 /* The width in bits of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */
92703 #define ALT_USB_DEV_DIEPINT10_EPDISBLD_WIDTH 1
92704 /* The mask used to set the ALT_USB_DEV_DIEPINT10_EPDISBLD register field value. */
92705 #define ALT_USB_DEV_DIEPINT10_EPDISBLD_SET_MSK 0x00000002
92706 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_EPDISBLD register field value. */
92707 #define ALT_USB_DEV_DIEPINT10_EPDISBLD_CLR_MSK 0xfffffffd
92708 /* The reset value of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */
92709 #define ALT_USB_DEV_DIEPINT10_EPDISBLD_RESET 0x0
92710 /* Extracts the ALT_USB_DEV_DIEPINT10_EPDISBLD field value from a register. */
92711 #define ALT_USB_DEV_DIEPINT10_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
92712 /* Produces a ALT_USB_DEV_DIEPINT10_EPDISBLD register field value suitable for setting the register. */
92713 #define ALT_USB_DEV_DIEPINT10_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
92714 
92715 /*
92716  * Field : ahberr
92717  *
92718  * AHB Error (AHBErr)
92719  *
92720  * Applies to IN and OUT endpoints.
92721  *
92722  * This is generated only in Internal DMA mode when there is an
92723  *
92724  * AHB error during an AHB read/write. The application can read
92725  *
92726  * the corresponding endpoint DMA address register to get the
92727  *
92728  * error address.
92729  *
92730  * Field Enumeration Values:
92731  *
92732  * Enum | Value | Description
92733  * :-------------------------------------|:------|:--------------------
92734  * ALT_USB_DEV_DIEPINT10_AHBERR_E_INACT | 0x0 | No Interrupt
92735  * ALT_USB_DEV_DIEPINT10_AHBERR_E_ACT | 0x1 | AHB Error interrupt
92736  *
92737  * Field Access Macros:
92738  *
92739  */
92740 /*
92741  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_AHBERR
92742  *
92743  * No Interrupt
92744  */
92745 #define ALT_USB_DEV_DIEPINT10_AHBERR_E_INACT 0x0
92746 /*
92747  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_AHBERR
92748  *
92749  * AHB Error interrupt
92750  */
92751 #define ALT_USB_DEV_DIEPINT10_AHBERR_E_ACT 0x1
92752 
92753 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */
92754 #define ALT_USB_DEV_DIEPINT10_AHBERR_LSB 2
92755 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */
92756 #define ALT_USB_DEV_DIEPINT10_AHBERR_MSB 2
92757 /* The width in bits of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */
92758 #define ALT_USB_DEV_DIEPINT10_AHBERR_WIDTH 1
92759 /* The mask used to set the ALT_USB_DEV_DIEPINT10_AHBERR register field value. */
92760 #define ALT_USB_DEV_DIEPINT10_AHBERR_SET_MSK 0x00000004
92761 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_AHBERR register field value. */
92762 #define ALT_USB_DEV_DIEPINT10_AHBERR_CLR_MSK 0xfffffffb
92763 /* The reset value of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */
92764 #define ALT_USB_DEV_DIEPINT10_AHBERR_RESET 0x0
92765 /* Extracts the ALT_USB_DEV_DIEPINT10_AHBERR field value from a register. */
92766 #define ALT_USB_DEV_DIEPINT10_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
92767 /* Produces a ALT_USB_DEV_DIEPINT10_AHBERR register field value suitable for setting the register. */
92768 #define ALT_USB_DEV_DIEPINT10_AHBERR_SET(value) (((value) << 2) & 0x00000004)
92769 
92770 /*
92771  * Field : timeout
92772  *
92773  * Timeout Condition (TimeOUT)
92774  *
92775  * In shared TX FIFO mode, applies to non-isochronous IN
92776  *
92777  * endpoints only.
92778  *
92779  * In dedicated FIFO mode, applies only to Control IN
92780  *
92781  * endpoints.
92782  *
92783  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
92784  *
92785  * asserted.
92786  *
92787  * Indicates that the core has detected a timeout condition on the
92788  *
92789  * USB For the last IN token on this endpoint.
92790  *
92791  * Field Enumeration Values:
92792  *
92793  * Enum | Value | Description
92794  * :----------------------------------|:------|:------------------
92795  * ALT_USB_DEV_DIEPINT10_TMO_E_INACT | 0x0 | No interrupt
92796  * ALT_USB_DEV_DIEPINT10_TMO_E_ACT | 0x1 | Timeout interrupy
92797  *
92798  * Field Access Macros:
92799  *
92800  */
92801 /*
92802  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TMO
92803  *
92804  * No interrupt
92805  */
92806 #define ALT_USB_DEV_DIEPINT10_TMO_E_INACT 0x0
92807 /*
92808  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TMO
92809  *
92810  * Timeout interrupy
92811  */
92812 #define ALT_USB_DEV_DIEPINT10_TMO_E_ACT 0x1
92813 
92814 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_TMO register field. */
92815 #define ALT_USB_DEV_DIEPINT10_TMO_LSB 3
92816 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_TMO register field. */
92817 #define ALT_USB_DEV_DIEPINT10_TMO_MSB 3
92818 /* The width in bits of the ALT_USB_DEV_DIEPINT10_TMO register field. */
92819 #define ALT_USB_DEV_DIEPINT10_TMO_WIDTH 1
92820 /* The mask used to set the ALT_USB_DEV_DIEPINT10_TMO register field value. */
92821 #define ALT_USB_DEV_DIEPINT10_TMO_SET_MSK 0x00000008
92822 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_TMO register field value. */
92823 #define ALT_USB_DEV_DIEPINT10_TMO_CLR_MSK 0xfffffff7
92824 /* The reset value of the ALT_USB_DEV_DIEPINT10_TMO register field. */
92825 #define ALT_USB_DEV_DIEPINT10_TMO_RESET 0x0
92826 /* Extracts the ALT_USB_DEV_DIEPINT10_TMO field value from a register. */
92827 #define ALT_USB_DEV_DIEPINT10_TMO_GET(value) (((value) & 0x00000008) >> 3)
92828 /* Produces a ALT_USB_DEV_DIEPINT10_TMO register field value suitable for setting the register. */
92829 #define ALT_USB_DEV_DIEPINT10_TMO_SET(value) (((value) << 3) & 0x00000008)
92830 
92831 /*
92832  * Field : intkntxfemp
92833  *
92834  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
92835  *
92836  * Applies to non-periodic IN endpoints only.
92837  *
92838  * Indicates that an IN token was received when the associated
92839  *
92840  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
92841  *
92842  * asserted on the endpoint For which the IN token was received.
92843  *
92844  * Field Enumeration Values:
92845  *
92846  * Enum | Value | Description
92847  * :------------------------------------------|:------|:----------------------------
92848  * ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
92849  * ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
92850  *
92851  * Field Access Macros:
92852  *
92853  */
92854 /*
92855  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNTXFEMP
92856  *
92857  * No interrupt
92858  */
92859 #define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_INACT 0x0
92860 /*
92861  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNTXFEMP
92862  *
92863  * IN Token Received Interrupt
92864  */
92865 #define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_ACT 0x1
92866 
92867 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */
92868 #define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_LSB 4
92869 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */
92870 #define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_MSB 4
92871 /* The width in bits of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */
92872 #define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_WIDTH 1
92873 /* The mask used to set the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field value. */
92874 #define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_SET_MSK 0x00000010
92875 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field value. */
92876 #define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_CLR_MSK 0xffffffef
92877 /* The reset value of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */
92878 #define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_RESET 0x0
92879 /* Extracts the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP field value from a register. */
92880 #define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
92881 /* Produces a ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field value suitable for setting the register. */
92882 #define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
92883 
92884 /*
92885  * Field : intknepmis
92886  *
92887  * IN Token Received with EP Mismatch (INTknEPMis)
92888  *
92889  * Applies to non-periodic IN endpoints only.
92890  *
92891  * Indicates that the data in the top of the non-periodic TxFIFO
92892  *
92893  * belongs to an endpoint other than the one For which the IN token
92894  *
92895  * was received. This interrupt is asserted on the endpoint For
92896  *
92897  * which the IN token was received.
92898  *
92899  * Field Enumeration Values:
92900  *
92901  * Enum | Value | Description
92902  * :-----------------------------------------|:------|:---------------------------------------------
92903  * ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_INACT | 0x0 | No interrupt
92904  * ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
92905  *
92906  * Field Access Macros:
92907  *
92908  */
92909 /*
92910  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNEPMIS
92911  *
92912  * No interrupt
92913  */
92914 #define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_INACT 0x0
92915 /*
92916  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNEPMIS
92917  *
92918  * IN Token Received with EP Mismatch interrupt
92919  */
92920 #define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_ACT 0x1
92921 
92922 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */
92923 #define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_LSB 5
92924 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */
92925 #define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_MSB 5
92926 /* The width in bits of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */
92927 #define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_WIDTH 1
92928 /* The mask used to set the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field value. */
92929 #define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_SET_MSK 0x00000020
92930 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field value. */
92931 #define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_CLR_MSK 0xffffffdf
92932 /* The reset value of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */
92933 #define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_RESET 0x0
92934 /* Extracts the ALT_USB_DEV_DIEPINT10_INTKNEPMIS field value from a register. */
92935 #define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
92936 /* Produces a ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field value suitable for setting the register. */
92937 #define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
92938 
92939 /*
92940  * Field : inepnakeff
92941  *
92942  * IN Endpoint NAK Effective (INEPNakEff)
92943  *
92944  * Applies to periodic IN endpoints only.
92945  *
92946  * This bit can be cleared when the application clears the IN
92947  *
92948  * endpoint NAK by writing to DIEPCTLn.CNAK.
92949  *
92950  * This interrupt indicates that the core has sampled the NAK bit
92951  *
92952  * Set (either by the application or by the core). The interrupt
92953  *
92954  * indicates that the IN endpoint NAK bit Set by the application has
92955  *
92956  * taken effect in the core.
92957  *
92958  * This interrupt does not guarantee that a NAK handshake is sent
92959  *
92960  * on the USB. A STALL bit takes priority over a NAK bit.
92961  *
92962  * Field Enumeration Values:
92963  *
92964  * Enum | Value | Description
92965  * :-----------------------------------------|:------|:------------------------------------
92966  * ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_INACT | 0x0 | No interrupt
92967  * ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
92968  *
92969  * Field Access Macros:
92970  *
92971  */
92972 /*
92973  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INEPNAKEFF
92974  *
92975  * No interrupt
92976  */
92977 #define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_INACT 0x0
92978 /*
92979  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_INEPNAKEFF
92980  *
92981  * IN Endpoint NAK Effective interrupt
92982  */
92983 #define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_ACT 0x1
92984 
92985 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */
92986 #define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_LSB 6
92987 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */
92988 #define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_MSB 6
92989 /* The width in bits of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */
92990 #define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_WIDTH 1
92991 /* The mask used to set the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field value. */
92992 #define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_SET_MSK 0x00000040
92993 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field value. */
92994 #define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_CLR_MSK 0xffffffbf
92995 /* The reset value of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */
92996 #define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_RESET 0x0
92997 /* Extracts the ALT_USB_DEV_DIEPINT10_INEPNAKEFF field value from a register. */
92998 #define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
92999 /* Produces a ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field value suitable for setting the register. */
93000 #define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
93001 
93002 /*
93003  * Field : txfemp
93004  *
93005  * Transmit FIFO Empty (TxFEmp)
93006  *
93007  * This bit is valid only For IN Endpoints
93008  *
93009  * This interrupt is asserted when the TxFIFO For this endpoint is
93010  *
93011  * either half or completely empty. The half or completely empty
93012  *
93013  * status is determined by the TxFIFO Empty Level bit in the Core
93014  *
93015  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
93016  *
93017  * Field Enumeration Values:
93018  *
93019  * Enum | Value | Description
93020  * :-------------------------------------|:------|:------------------------------
93021  * ALT_USB_DEV_DIEPINT10_TXFEMP_E_INACT | 0x0 | No interrupt
93022  * ALT_USB_DEV_DIEPINT10_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
93023  *
93024  * Field Access Macros:
93025  *
93026  */
93027 /*
93028  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFEMP
93029  *
93030  * No interrupt
93031  */
93032 #define ALT_USB_DEV_DIEPINT10_TXFEMP_E_INACT 0x0
93033 /*
93034  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFEMP
93035  *
93036  * Transmit FIFO Empty interrupt
93037  */
93038 #define ALT_USB_DEV_DIEPINT10_TXFEMP_E_ACT 0x1
93039 
93040 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */
93041 #define ALT_USB_DEV_DIEPINT10_TXFEMP_LSB 7
93042 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */
93043 #define ALT_USB_DEV_DIEPINT10_TXFEMP_MSB 7
93044 /* The width in bits of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */
93045 #define ALT_USB_DEV_DIEPINT10_TXFEMP_WIDTH 1
93046 /* The mask used to set the ALT_USB_DEV_DIEPINT10_TXFEMP register field value. */
93047 #define ALT_USB_DEV_DIEPINT10_TXFEMP_SET_MSK 0x00000080
93048 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_TXFEMP register field value. */
93049 #define ALT_USB_DEV_DIEPINT10_TXFEMP_CLR_MSK 0xffffff7f
93050 /* The reset value of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */
93051 #define ALT_USB_DEV_DIEPINT10_TXFEMP_RESET 0x1
93052 /* Extracts the ALT_USB_DEV_DIEPINT10_TXFEMP field value from a register. */
93053 #define ALT_USB_DEV_DIEPINT10_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
93054 /* Produces a ALT_USB_DEV_DIEPINT10_TXFEMP register field value suitable for setting the register. */
93055 #define ALT_USB_DEV_DIEPINT10_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
93056 
93057 /*
93058  * Field : txfifoundrn
93059  *
93060  * Fifo Underrun (TxfifoUndrn)
93061  *
93062  * Applies to IN endpoints Only
93063  *
93064  * This bit is valid only If thresholding is enabled. The core generates this
93065  * interrupt when
93066  *
93067  * it detects a transmit FIFO underrun condition For this endpoint.
93068  *
93069  * Field Enumeration Values:
93070  *
93071  * Enum | Value | Description
93072  * :------------------------------------------|:------|:------------------------
93073  * ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
93074  * ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
93075  *
93076  * Field Access Macros:
93077  *
93078  */
93079 /*
93080  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN
93081  *
93082  * No interrupt
93083  */
93084 #define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_INACT 0x0
93085 /*
93086  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN
93087  *
93088  * Fifo Underrun interrupt
93089  */
93090 #define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_ACT 0x1
93091 
93092 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */
93093 #define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_LSB 8
93094 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */
93095 #define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_MSB 8
93096 /* The width in bits of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */
93097 #define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_WIDTH 1
93098 /* The mask used to set the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field value. */
93099 #define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_SET_MSK 0x00000100
93100 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field value. */
93101 #define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_CLR_MSK 0xfffffeff
93102 /* The reset value of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */
93103 #define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_RESET 0x0
93104 /* Extracts the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN field value from a register. */
93105 #define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
93106 /* Produces a ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field value suitable for setting the register. */
93107 #define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
93108 
93109 /*
93110  * Field : bnaintr
93111  *
93112  * BNA (Buffer Not Available) Interrupt (BNAIntr)
93113  *
93114  * This bit is valid only when Scatter/Gather DMA mode is enabled.
93115  *
93116  * The core generates this interrupt when the descriptor accessed
93117  *
93118  * is not ready For the Core to process, such as Host busy or DMA
93119  *
93120  * done
93121  *
93122  * Field Enumeration Values:
93123  *
93124  * Enum | Value | Description
93125  * :--------------------------------------|:------|:--------------
93126  * ALT_USB_DEV_DIEPINT10_BNAINTR_E_INACT | 0x0 | No interrupt
93127  * ALT_USB_DEV_DIEPINT10_BNAINTR_E_ACT | 0x1 | BNA interrupt
93128  *
93129  * Field Access Macros:
93130  *
93131  */
93132 /*
93133  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_BNAINTR
93134  *
93135  * No interrupt
93136  */
93137 #define ALT_USB_DEV_DIEPINT10_BNAINTR_E_INACT 0x0
93138 /*
93139  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_BNAINTR
93140  *
93141  * BNA interrupt
93142  */
93143 #define ALT_USB_DEV_DIEPINT10_BNAINTR_E_ACT 0x1
93144 
93145 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */
93146 #define ALT_USB_DEV_DIEPINT10_BNAINTR_LSB 9
93147 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */
93148 #define ALT_USB_DEV_DIEPINT10_BNAINTR_MSB 9
93149 /* The width in bits of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */
93150 #define ALT_USB_DEV_DIEPINT10_BNAINTR_WIDTH 1
93151 /* The mask used to set the ALT_USB_DEV_DIEPINT10_BNAINTR register field value. */
93152 #define ALT_USB_DEV_DIEPINT10_BNAINTR_SET_MSK 0x00000200
93153 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_BNAINTR register field value. */
93154 #define ALT_USB_DEV_DIEPINT10_BNAINTR_CLR_MSK 0xfffffdff
93155 /* The reset value of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */
93156 #define ALT_USB_DEV_DIEPINT10_BNAINTR_RESET 0x0
93157 /* Extracts the ALT_USB_DEV_DIEPINT10_BNAINTR field value from a register. */
93158 #define ALT_USB_DEV_DIEPINT10_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
93159 /* Produces a ALT_USB_DEV_DIEPINT10_BNAINTR register field value suitable for setting the register. */
93160 #define ALT_USB_DEV_DIEPINT10_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
93161 
93162 /*
93163  * Field : pktdrpsts
93164  *
93165  * Packet Drop Status (PktDrpSts)
93166  *
93167  * This bit indicates to the application that an ISOC OUT packet has been dropped.
93168  * This
93169  *
93170  * bit does not have an associated mask bit and does not generate an interrupt.
93171  *
93172  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
93173  * transfer
93174  *
93175  * interrupt feature is selected.
93176  *
93177  * Field Enumeration Values:
93178  *
93179  * Enum | Value | Description
93180  * :----------------------------------------|:------|:-----------------------------
93181  * ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_INACT | 0x0 | No interrupt
93182  * ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
93183  *
93184  * Field Access Macros:
93185  *
93186  */
93187 /*
93188  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_PKTDRPSTS
93189  *
93190  * No interrupt
93191  */
93192 #define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_INACT 0x0
93193 /*
93194  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_PKTDRPSTS
93195  *
93196  * Packet Drop Status interrupt
93197  */
93198 #define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_ACT 0x1
93199 
93200 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */
93201 #define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_LSB 11
93202 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */
93203 #define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_MSB 11
93204 /* The width in bits of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */
93205 #define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_WIDTH 1
93206 /* The mask used to set the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field value. */
93207 #define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_SET_MSK 0x00000800
93208 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field value. */
93209 #define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_CLR_MSK 0xfffff7ff
93210 /* The reset value of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */
93211 #define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_RESET 0x0
93212 /* Extracts the ALT_USB_DEV_DIEPINT10_PKTDRPSTS field value from a register. */
93213 #define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
93214 /* Produces a ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field value suitable for setting the register. */
93215 #define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
93216 
93217 /*
93218  * Field : bbleerr
93219  *
93220  * NAK Interrupt (BbleErr)
93221  *
93222  * The core generates this interrupt when babble is received for the endpoint.
93223  *
93224  * Field Enumeration Values:
93225  *
93226  * Enum | Value | Description
93227  * :--------------------------------------|:------|:------------------
93228  * ALT_USB_DEV_DIEPINT10_BBLEERR_E_INACT | 0x0 | No interrupt
93229  * ALT_USB_DEV_DIEPINT10_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
93230  *
93231  * Field Access Macros:
93232  *
93233  */
93234 /*
93235  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_BBLEERR
93236  *
93237  * No interrupt
93238  */
93239 #define ALT_USB_DEV_DIEPINT10_BBLEERR_E_INACT 0x0
93240 /*
93241  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_BBLEERR
93242  *
93243  * BbleErr interrupt
93244  */
93245 #define ALT_USB_DEV_DIEPINT10_BBLEERR_E_ACT 0x1
93246 
93247 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */
93248 #define ALT_USB_DEV_DIEPINT10_BBLEERR_LSB 12
93249 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */
93250 #define ALT_USB_DEV_DIEPINT10_BBLEERR_MSB 12
93251 /* The width in bits of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */
93252 #define ALT_USB_DEV_DIEPINT10_BBLEERR_WIDTH 1
93253 /* The mask used to set the ALT_USB_DEV_DIEPINT10_BBLEERR register field value. */
93254 #define ALT_USB_DEV_DIEPINT10_BBLEERR_SET_MSK 0x00001000
93255 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_BBLEERR register field value. */
93256 #define ALT_USB_DEV_DIEPINT10_BBLEERR_CLR_MSK 0xffffefff
93257 /* The reset value of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */
93258 #define ALT_USB_DEV_DIEPINT10_BBLEERR_RESET 0x0
93259 /* Extracts the ALT_USB_DEV_DIEPINT10_BBLEERR field value from a register. */
93260 #define ALT_USB_DEV_DIEPINT10_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
93261 /* Produces a ALT_USB_DEV_DIEPINT10_BBLEERR register field value suitable for setting the register. */
93262 #define ALT_USB_DEV_DIEPINT10_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
93263 
93264 /*
93265  * Field : nakintrpt
93266  *
93267  * NAK Interrupt (NAKInterrupt)
93268  *
93269  * The core generates this interrupt when a NAK is transmitted or received by the
93270  * device.
93271  *
93272  * In case of isochronous IN endpoints the interrupt gets generated when a zero
93273  * length
93274  *
93275  * packet is transmitted due to un-availability of data in the TXFifo.
93276  *
93277  * Field Enumeration Values:
93278  *
93279  * Enum | Value | Description
93280  * :----------------------------------------|:------|:--------------
93281  * ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_INACT | 0x0 | No interrupt
93282  * ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
93283  *
93284  * Field Access Macros:
93285  *
93286  */
93287 /*
93288  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_NAKINTRPT
93289  *
93290  * No interrupt
93291  */
93292 #define ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_INACT 0x0
93293 /*
93294  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_NAKINTRPT
93295  *
93296  * NAK Interrupt
93297  */
93298 #define ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_ACT 0x1
93299 
93300 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */
93301 #define ALT_USB_DEV_DIEPINT10_NAKINTRPT_LSB 13
93302 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */
93303 #define ALT_USB_DEV_DIEPINT10_NAKINTRPT_MSB 13
93304 /* The width in bits of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */
93305 #define ALT_USB_DEV_DIEPINT10_NAKINTRPT_WIDTH 1
93306 /* The mask used to set the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field value. */
93307 #define ALT_USB_DEV_DIEPINT10_NAKINTRPT_SET_MSK 0x00002000
93308 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field value. */
93309 #define ALT_USB_DEV_DIEPINT10_NAKINTRPT_CLR_MSK 0xffffdfff
93310 /* The reset value of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */
93311 #define ALT_USB_DEV_DIEPINT10_NAKINTRPT_RESET 0x0
93312 /* Extracts the ALT_USB_DEV_DIEPINT10_NAKINTRPT field value from a register. */
93313 #define ALT_USB_DEV_DIEPINT10_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
93314 /* Produces a ALT_USB_DEV_DIEPINT10_NAKINTRPT register field value suitable for setting the register. */
93315 #define ALT_USB_DEV_DIEPINT10_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
93316 
93317 /*
93318  * Field : nyetintrpt
93319  *
93320  * NYET Interrupt (NYETIntrpt)
93321  *
93322  * The core generates this interrupt when a NYET response is transmitted for a non
93323  * isochronous OUT endpoint.
93324  *
93325  * Field Enumeration Values:
93326  *
93327  * Enum | Value | Description
93328  * :-----------------------------------------|:------|:---------------
93329  * ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_INACT | 0x0 | No interrupt
93330  * ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
93331  *
93332  * Field Access Macros:
93333  *
93334  */
93335 /*
93336  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_NYETINTRPT
93337  *
93338  * No interrupt
93339  */
93340 #define ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_INACT 0x0
93341 /*
93342  * Enumerated value for register field ALT_USB_DEV_DIEPINT10_NYETINTRPT
93343  *
93344  * NYET Interrupt
93345  */
93346 #define ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_ACT 0x1
93347 
93348 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */
93349 #define ALT_USB_DEV_DIEPINT10_NYETINTRPT_LSB 14
93350 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */
93351 #define ALT_USB_DEV_DIEPINT10_NYETINTRPT_MSB 14
93352 /* The width in bits of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */
93353 #define ALT_USB_DEV_DIEPINT10_NYETINTRPT_WIDTH 1
93354 /* The mask used to set the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field value. */
93355 #define ALT_USB_DEV_DIEPINT10_NYETINTRPT_SET_MSK 0x00004000
93356 /* The mask used to clear the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field value. */
93357 #define ALT_USB_DEV_DIEPINT10_NYETINTRPT_CLR_MSK 0xffffbfff
93358 /* The reset value of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */
93359 #define ALT_USB_DEV_DIEPINT10_NYETINTRPT_RESET 0x0
93360 /* Extracts the ALT_USB_DEV_DIEPINT10_NYETINTRPT field value from a register. */
93361 #define ALT_USB_DEV_DIEPINT10_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
93362 /* Produces a ALT_USB_DEV_DIEPINT10_NYETINTRPT register field value suitable for setting the register. */
93363 #define ALT_USB_DEV_DIEPINT10_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
93364 
93365 #ifndef __ASSEMBLY__
93366 /*
93367  * WARNING: The C register and register group struct declarations are provided for
93368  * convenience and illustrative purposes. They should, however, be used with
93369  * caution as the C language standard provides no guarantees about the alignment or
93370  * atomicity of device memory accesses. The recommended practice for writing
93371  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
93372  * alt_write_word() functions.
93373  *
93374  * The struct declaration for register ALT_USB_DEV_DIEPINT10.
93375  */
93376 struct ALT_USB_DEV_DIEPINT10_s
93377 {
93378  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT10_XFERCOMPL */
93379  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT10_EPDISBLD */
93380  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT10_AHBERR */
93381  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT10_TMO */
93382  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT10_INTKNTXFEMP */
93383  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT10_INTKNEPMIS */
93384  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT10_INEPNAKEFF */
93385  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT10_TXFEMP */
93386  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN */
93387  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT10_BNAINTR */
93388  uint32_t : 1; /* *UNDEFINED* */
93389  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT10_PKTDRPSTS */
93390  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT10_BBLEERR */
93391  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT10_NAKINTRPT */
93392  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT10_NYETINTRPT */
93393  uint32_t : 17; /* *UNDEFINED* */
93394 };
93395 
93396 /* The typedef declaration for register ALT_USB_DEV_DIEPINT10. */
93397 typedef volatile struct ALT_USB_DEV_DIEPINT10_s ALT_USB_DEV_DIEPINT10_t;
93398 #endif /* __ASSEMBLY__ */
93399 
93400 /* The reset value of the ALT_USB_DEV_DIEPINT10 register. */
93401 #define ALT_USB_DEV_DIEPINT10_RESET 0x00000080
93402 /* The byte offset of the ALT_USB_DEV_DIEPINT10 register from the beginning of the component. */
93403 #define ALT_USB_DEV_DIEPINT10_OFST 0x248
93404 /* The address of the ALT_USB_DEV_DIEPINT10 register. */
93405 #define ALT_USB_DEV_DIEPINT10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT10_OFST))
93406 
93407 /*
93408  * Register : dieptsiz10
93409  *
93410  * Device IN Endpoint 10 Transfer Size Register
93411  *
93412  * Register Layout
93413  *
93414  * Bits | Access | Reset | Description
93415  * :--------|:-------|:------|:--------------------------------
93416  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ10_XFERSIZE
93417  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ10_PKTCNT
93418  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ10_MC
93419  * [31] | ??? | 0x0 | *UNDEFINED*
93420  *
93421  */
93422 /*
93423  * Field : xfersize
93424  *
93425  * Transfer Size (XferSize)
93426  *
93427  * Indicates the transfer size in bytes For endpoint 0. The core
93428  *
93429  * interrupts the application only after it has exhausted the transfer
93430  *
93431  * size amount of data. The transfer size can be Set to the
93432  *
93433  * maximum packet size of the endpoint, to be interrupted at the
93434  *
93435  * end of each packet.
93436  *
93437  * The core decrements this field every time a packet from the
93438  *
93439  * external memory is written to the TxFIFO.
93440  *
93441  * Field Access Macros:
93442  *
93443  */
93444 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */
93445 #define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_LSB 0
93446 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */
93447 #define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_MSB 18
93448 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */
93449 #define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_WIDTH 19
93450 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field value. */
93451 #define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_SET_MSK 0x0007ffff
93452 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field value. */
93453 #define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_CLR_MSK 0xfff80000
93454 /* The reset value of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */
93455 #define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_RESET 0x0
93456 /* Extracts the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE field value from a register. */
93457 #define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
93458 /* Produces a ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field value suitable for setting the register. */
93459 #define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
93460 
93461 /*
93462  * Field : pktcnt
93463  *
93464  * Packet Count (PktCnt)
93465  *
93466  * Indicates the total number of USB packets that constitute the
93467  *
93468  * Transfer Size amount of data For endpoint 0.
93469  *
93470  * This field is decremented every time a packet (maximum size or
93471  *
93472  * short packet) is read from the TxFIFO.
93473  *
93474  * Field Access Macros:
93475  *
93476  */
93477 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */
93478 #define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_LSB 19
93479 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */
93480 #define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_MSB 28
93481 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */
93482 #define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_WIDTH 10
93483 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field value. */
93484 #define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_SET_MSK 0x1ff80000
93485 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field value. */
93486 #define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_CLR_MSK 0xe007ffff
93487 /* The reset value of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */
93488 #define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_RESET 0x0
93489 /* Extracts the ALT_USB_DEV_DIEPTSIZ10_PKTCNT field value from a register. */
93490 #define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
93491 /* Produces a ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field value suitable for setting the register. */
93492 #define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
93493 
93494 /*
93495  * Field : mc
93496  *
93497  * Applies to IN endpoints only.
93498  *
93499  * For periodic IN endpoints, this field indicates the number of packets that must
93500  * be transmitted per microframe on the USB. The core uses this field to calculate
93501  * the data PID for isochronous IN endpoints.
93502  *
93503  * 2'b01: 1 packet
93504  *
93505  * 2'b10: 2 packets
93506  *
93507  * 2'b11: 3 packets
93508  *
93509  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
93510  * specifies the number of packets the core must fetchfor an IN endpoint before it
93511  * switches to the endpoint pointed to by the Next Endpoint field of the Device
93512  * Endpoint-n Control register (DIEPCTLn.NextEp)
93513  *
93514  * Field Enumeration Values:
93515  *
93516  * Enum | Value | Description
93517  * :-------------------------------------|:------|:------------
93518  * ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTONE | 0x1 | 1 packet
93519  * ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTWO | 0x2 | 2 packets
93520  * ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTHREE | 0x3 | 3 packets
93521  *
93522  * Field Access Macros:
93523  *
93524  */
93525 /*
93526  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ10_MC
93527  *
93528  * 1 packet
93529  */
93530 #define ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTONE 0x1
93531 /*
93532  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ10_MC
93533  *
93534  * 2 packets
93535  */
93536 #define ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTWO 0x2
93537 /*
93538  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ10_MC
93539  *
93540  * 3 packets
93541  */
93542 #define ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTHREE 0x3
93543 
93544 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */
93545 #define ALT_USB_DEV_DIEPTSIZ10_MC_LSB 29
93546 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */
93547 #define ALT_USB_DEV_DIEPTSIZ10_MC_MSB 30
93548 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */
93549 #define ALT_USB_DEV_DIEPTSIZ10_MC_WIDTH 2
93550 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ10_MC register field value. */
93551 #define ALT_USB_DEV_DIEPTSIZ10_MC_SET_MSK 0x60000000
93552 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ10_MC register field value. */
93553 #define ALT_USB_DEV_DIEPTSIZ10_MC_CLR_MSK 0x9fffffff
93554 /* The reset value of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */
93555 #define ALT_USB_DEV_DIEPTSIZ10_MC_RESET 0x0
93556 /* Extracts the ALT_USB_DEV_DIEPTSIZ10_MC field value from a register. */
93557 #define ALT_USB_DEV_DIEPTSIZ10_MC_GET(value) (((value) & 0x60000000) >> 29)
93558 /* Produces a ALT_USB_DEV_DIEPTSIZ10_MC register field value suitable for setting the register. */
93559 #define ALT_USB_DEV_DIEPTSIZ10_MC_SET(value) (((value) << 29) & 0x60000000)
93560 
93561 #ifndef __ASSEMBLY__
93562 /*
93563  * WARNING: The C register and register group struct declarations are provided for
93564  * convenience and illustrative purposes. They should, however, be used with
93565  * caution as the C language standard provides no guarantees about the alignment or
93566  * atomicity of device memory accesses. The recommended practice for writing
93567  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
93568  * alt_write_word() functions.
93569  *
93570  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ10.
93571  */
93572 struct ALT_USB_DEV_DIEPTSIZ10_s
93573 {
93574  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ10_XFERSIZE */
93575  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ10_PKTCNT */
93576  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ10_MC */
93577  uint32_t : 1; /* *UNDEFINED* */
93578 };
93579 
93580 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ10. */
93581 typedef volatile struct ALT_USB_DEV_DIEPTSIZ10_s ALT_USB_DEV_DIEPTSIZ10_t;
93582 #endif /* __ASSEMBLY__ */
93583 
93584 /* The reset value of the ALT_USB_DEV_DIEPTSIZ10 register. */
93585 #define ALT_USB_DEV_DIEPTSIZ10_RESET 0x00000000
93586 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ10 register from the beginning of the component. */
93587 #define ALT_USB_DEV_DIEPTSIZ10_OFST 0x250
93588 /* The address of the ALT_USB_DEV_DIEPTSIZ10 register. */
93589 #define ALT_USB_DEV_DIEPTSIZ10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ10_OFST))
93590 
93591 /*
93592  * Register : diepdma10
93593  *
93594  * Device IN Endpoint 10 DMA Address Register
93595  *
93596  * Register Layout
93597  *
93598  * Bits | Access | Reset | Description
93599  * :-------|:-------|:--------|:--------------------------------
93600  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA10_DIEPDMA10
93601  *
93602  */
93603 /*
93604  * Field : diepdma10
93605  *
93606  * Holds the start address of the external memory for storing or fetching endpoint
93607  *
93608  * data.
93609  *
93610  * Note: For control endpoints, this field stores control OUT data packets as well
93611  * as
93612  *
93613  * SETUP transaction data packets. When more than three SETUP packets are
93614  *
93615  * received back-to-back, the SETUP data packet in the memory is overwritten.
93616  *
93617  * This register is incremented on every AHB transaction. The application can give
93618  *
93619  * only a DWORD-aligned address.
93620  *
93621  * When Scatter/Gather DMA mode is not enabled, the application programs the
93622  *
93623  * start address value in this field.
93624  *
93625  * When Scatter/Gather DMA mode is enabled, this field indicates the base
93626  *
93627  * pointer for the descriptor list.
93628  *
93629  * Field Access Macros:
93630  *
93631  */
93632 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field. */
93633 #define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_LSB 0
93634 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field. */
93635 #define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_MSB 31
93636 /* The width in bits of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field. */
93637 #define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_WIDTH 32
93638 /* The mask used to set the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field value. */
93639 #define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_SET_MSK 0xffffffff
93640 /* The mask used to clear the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field value. */
93641 #define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_CLR_MSK 0x00000000
93642 /* The reset value of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field is UNKNOWN. */
93643 #define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_RESET 0x0
93644 /* Extracts the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 field value from a register. */
93645 #define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_GET(value) (((value) & 0xffffffff) >> 0)
93646 /* Produces a ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field value suitable for setting the register. */
93647 #define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_SET(value) (((value) << 0) & 0xffffffff)
93648 
93649 #ifndef __ASSEMBLY__
93650 /*
93651  * WARNING: The C register and register group struct declarations are provided for
93652  * convenience and illustrative purposes. They should, however, be used with
93653  * caution as the C language standard provides no guarantees about the alignment or
93654  * atomicity of device memory accesses. The recommended practice for writing
93655  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
93656  * alt_write_word() functions.
93657  *
93658  * The struct declaration for register ALT_USB_DEV_DIEPDMA10.
93659  */
93660 struct ALT_USB_DEV_DIEPDMA10_s
93661 {
93662  uint32_t diepdma10 : 32; /* ALT_USB_DEV_DIEPDMA10_DIEPDMA10 */
93663 };
93664 
93665 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA10. */
93666 typedef volatile struct ALT_USB_DEV_DIEPDMA10_s ALT_USB_DEV_DIEPDMA10_t;
93667 #endif /* __ASSEMBLY__ */
93668 
93669 /* The reset value of the ALT_USB_DEV_DIEPDMA10 register. */
93670 #define ALT_USB_DEV_DIEPDMA10_RESET 0x00000000
93671 /* The byte offset of the ALT_USB_DEV_DIEPDMA10 register from the beginning of the component. */
93672 #define ALT_USB_DEV_DIEPDMA10_OFST 0x254
93673 /* The address of the ALT_USB_DEV_DIEPDMA10 register. */
93674 #define ALT_USB_DEV_DIEPDMA10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA10_OFST))
93675 
93676 /*
93677  * Register : dtxfsts10
93678  *
93679  * Device IN Endpoint Transmit FIFO Status Register 10
93680  *
93681  * Register Layout
93682  *
93683  * Bits | Access | Reset | Description
93684  * :--------|:-------|:-------|:--------------------------------------
93685  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL
93686  * [31:16] | ??? | 0x0 | *UNDEFINED*
93687  *
93688  */
93689 /*
93690  * Field : ineptxfspcavail
93691  *
93692  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
93693  *
93694  * Indicates the amount of free space available in the Endpoint
93695  *
93696  * TxFIFO.
93697  *
93698  * Values are in terms of 32-bit words.
93699  *
93700  * 16'h0: Endpoint TxFIFO is full
93701  *
93702  * 16'h1: 1 word available
93703  *
93704  * 16'h2: 2 words available
93705  *
93706  * 16'hn: n words available (where 0 n 32,768)
93707  *
93708  * 16'h8000: 32,768 words available
93709  *
93710  * Others: Reserved
93711  *
93712  * Field Access Macros:
93713  *
93714  */
93715 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */
93716 #define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_LSB 0
93717 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */
93718 #define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_MSB 15
93719 /* The width in bits of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */
93720 #define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_WIDTH 16
93721 /* The mask used to set the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field value. */
93722 #define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
93723 /* The mask used to clear the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field value. */
93724 #define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
93725 /* The reset value of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */
93726 #define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_RESET 0x2000
93727 /* Extracts the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL field value from a register. */
93728 #define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
93729 /* Produces a ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field value suitable for setting the register. */
93730 #define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
93731 
93732 #ifndef __ASSEMBLY__
93733 /*
93734  * WARNING: The C register and register group struct declarations are provided for
93735  * convenience and illustrative purposes. They should, however, be used with
93736  * caution as the C language standard provides no guarantees about the alignment or
93737  * atomicity of device memory accesses. The recommended practice for writing
93738  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
93739  * alt_write_word() functions.
93740  *
93741  * The struct declaration for register ALT_USB_DEV_DTXFSTS10.
93742  */
93743 struct ALT_USB_DEV_DTXFSTS10_s
93744 {
93745  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL */
93746  uint32_t : 16; /* *UNDEFINED* */
93747 };
93748 
93749 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS10. */
93750 typedef volatile struct ALT_USB_DEV_DTXFSTS10_s ALT_USB_DEV_DTXFSTS10_t;
93751 #endif /* __ASSEMBLY__ */
93752 
93753 /* The reset value of the ALT_USB_DEV_DTXFSTS10 register. */
93754 #define ALT_USB_DEV_DTXFSTS10_RESET 0x00002000
93755 /* The byte offset of the ALT_USB_DEV_DTXFSTS10 register from the beginning of the component. */
93756 #define ALT_USB_DEV_DTXFSTS10_OFST 0x258
93757 /* The address of the ALT_USB_DEV_DTXFSTS10 register. */
93758 #define ALT_USB_DEV_DTXFSTS10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS10_OFST))
93759 
93760 /*
93761  * Register : diepdmab10
93762  *
93763  * Device IN Endpoint 10 Buffer Address Register
93764  *
93765  * Register Layout
93766  *
93767  * Bits | Access | Reset | Description
93768  * :-------|:-------|:--------|:----------------------------------
93769  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10
93770  *
93771  */
93772 /*
93773  * Field : diepdmab10
93774  *
93775  * Holds the current buffer address.This register is updated as and when the data
93776  *
93777  * transfer for the corresponding end point is in progress.
93778  *
93779  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
93780  * is
93781  *
93782  * reserved.
93783  *
93784  * Field Access Macros:
93785  *
93786  */
93787 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field. */
93788 #define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_LSB 0
93789 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field. */
93790 #define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_MSB 31
93791 /* The width in bits of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field. */
93792 #define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_WIDTH 32
93793 /* The mask used to set the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field value. */
93794 #define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_SET_MSK 0xffffffff
93795 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field value. */
93796 #define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_CLR_MSK 0x00000000
93797 /* The reset value of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field is UNKNOWN. */
93798 #define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_RESET 0x0
93799 /* Extracts the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 field value from a register. */
93800 #define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_GET(value) (((value) & 0xffffffff) >> 0)
93801 /* Produces a ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field value suitable for setting the register. */
93802 #define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_SET(value) (((value) << 0) & 0xffffffff)
93803 
93804 #ifndef __ASSEMBLY__
93805 /*
93806  * WARNING: The C register and register group struct declarations are provided for
93807  * convenience and illustrative purposes. They should, however, be used with
93808  * caution as the C language standard provides no guarantees about the alignment or
93809  * atomicity of device memory accesses. The recommended practice for writing
93810  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
93811  * alt_write_word() functions.
93812  *
93813  * The struct declaration for register ALT_USB_DEV_DIEPDMAB10.
93814  */
93815 struct ALT_USB_DEV_DIEPDMAB10_s
93816 {
93817  const uint32_t diepdmab10 : 32; /* ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 */
93818 };
93819 
93820 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB10. */
93821 typedef volatile struct ALT_USB_DEV_DIEPDMAB10_s ALT_USB_DEV_DIEPDMAB10_t;
93822 #endif /* __ASSEMBLY__ */
93823 
93824 /* The reset value of the ALT_USB_DEV_DIEPDMAB10 register. */
93825 #define ALT_USB_DEV_DIEPDMAB10_RESET 0x00000000
93826 /* The byte offset of the ALT_USB_DEV_DIEPDMAB10 register from the beginning of the component. */
93827 #define ALT_USB_DEV_DIEPDMAB10_OFST 0x25c
93828 /* The address of the ALT_USB_DEV_DIEPDMAB10 register. */
93829 #define ALT_USB_DEV_DIEPDMAB10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB10_OFST))
93830 
93831 /*
93832  * Register : diepctl11
93833  *
93834  * Device Control IN Endpoint 11 Control Register
93835  *
93836  * Register Layout
93837  *
93838  * Bits | Access | Reset | Description
93839  * :--------|:---------|:------|:-------------------------------
93840  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL11_MPS
93841  * [14:11] | ??? | 0x0 | *UNDEFINED*
93842  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL11_USBACTEP
93843  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL11_DPID
93844  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL11_NAKSTS
93845  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL11_EPTYPE
93846  * [20] | ??? | 0x0 | *UNDEFINED*
93847  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL11_STALL
93848  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL11_TXFNUM
93849  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL11_CNAK
93850  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL11_SNAK
93851  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL11_SETD0PID
93852  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL11_SETD1PID
93853  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL11_EPDIS
93854  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL11_EPENA
93855  *
93856  */
93857 /*
93858  * Field : mps
93859  *
93860  * Maximum Packet Size (MPS)
93861  *
93862  * The application must program this field with the maximum packet size for the
93863  * current
93864  *
93865  * logical endpoint. This value is in bytes.
93866  *
93867  * Field Access Macros:
93868  *
93869  */
93870 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_MPS register field. */
93871 #define ALT_USB_DEV_DIEPCTL11_MPS_LSB 0
93872 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_MPS register field. */
93873 #define ALT_USB_DEV_DIEPCTL11_MPS_MSB 10
93874 /* The width in bits of the ALT_USB_DEV_DIEPCTL11_MPS register field. */
93875 #define ALT_USB_DEV_DIEPCTL11_MPS_WIDTH 11
93876 /* The mask used to set the ALT_USB_DEV_DIEPCTL11_MPS register field value. */
93877 #define ALT_USB_DEV_DIEPCTL11_MPS_SET_MSK 0x000007ff
93878 /* The mask used to clear the ALT_USB_DEV_DIEPCTL11_MPS register field value. */
93879 #define ALT_USB_DEV_DIEPCTL11_MPS_CLR_MSK 0xfffff800
93880 /* The reset value of the ALT_USB_DEV_DIEPCTL11_MPS register field. */
93881 #define ALT_USB_DEV_DIEPCTL11_MPS_RESET 0x0
93882 /* Extracts the ALT_USB_DEV_DIEPCTL11_MPS field value from a register. */
93883 #define ALT_USB_DEV_DIEPCTL11_MPS_GET(value) (((value) & 0x000007ff) >> 0)
93884 /* Produces a ALT_USB_DEV_DIEPCTL11_MPS register field value suitable for setting the register. */
93885 #define ALT_USB_DEV_DIEPCTL11_MPS_SET(value) (((value) << 0) & 0x000007ff)
93886 
93887 /*
93888  * Field : usbactep
93889  *
93890  * USB Active Endpoint (USBActEP)
93891  *
93892  * Indicates whether this endpoint is active in the current configuration and
93893  * interface. The
93894  *
93895  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
93896  * reset. After
93897  *
93898  * receiving the SetConfiguration and SetInterface commands, the application must
93899  *
93900  * program endpoint registers accordingly and set this bit.
93901  *
93902  * Field Enumeration Values:
93903  *
93904  * Enum | Value | Description
93905  * :--------------------------------------|:------|:--------------------
93906  * ALT_USB_DEV_DIEPCTL11_USBACTEP_E_DISD | 0x0 | Not Active
93907  * ALT_USB_DEV_DIEPCTL11_USBACTEP_E_END | 0x1 | USB Active Endpoint
93908  *
93909  * Field Access Macros:
93910  *
93911  */
93912 /*
93913  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_USBACTEP
93914  *
93915  * Not Active
93916  */
93917 #define ALT_USB_DEV_DIEPCTL11_USBACTEP_E_DISD 0x0
93918 /*
93919  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_USBACTEP
93920  *
93921  * USB Active Endpoint
93922  */
93923 #define ALT_USB_DEV_DIEPCTL11_USBACTEP_E_END 0x1
93924 
93925 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */
93926 #define ALT_USB_DEV_DIEPCTL11_USBACTEP_LSB 15
93927 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */
93928 #define ALT_USB_DEV_DIEPCTL11_USBACTEP_MSB 15
93929 /* The width in bits of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */
93930 #define ALT_USB_DEV_DIEPCTL11_USBACTEP_WIDTH 1
93931 /* The mask used to set the ALT_USB_DEV_DIEPCTL11_USBACTEP register field value. */
93932 #define ALT_USB_DEV_DIEPCTL11_USBACTEP_SET_MSK 0x00008000
93933 /* The mask used to clear the ALT_USB_DEV_DIEPCTL11_USBACTEP register field value. */
93934 #define ALT_USB_DEV_DIEPCTL11_USBACTEP_CLR_MSK 0xffff7fff
93935 /* The reset value of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */
93936 #define ALT_USB_DEV_DIEPCTL11_USBACTEP_RESET 0x0
93937 /* Extracts the ALT_USB_DEV_DIEPCTL11_USBACTEP field value from a register. */
93938 #define ALT_USB_DEV_DIEPCTL11_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
93939 /* Produces a ALT_USB_DEV_DIEPCTL11_USBACTEP register field value suitable for setting the register. */
93940 #define ALT_USB_DEV_DIEPCTL11_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
93941 
93942 /*
93943  * Field : dpid
93944  *
93945  * Endpoint Data PID (DPID)
93946  *
93947  * Applies to interrupt/bulk IN and OUT endpoints only.
93948  *
93949  * Contains the PID of the packet to be received or transmitted on this endpoint.
93950  * The
93951  *
93952  * application must program the PID of the first packet to be received or
93953  * transmitted on
93954  *
93955  * this endpoint, after the endpoint is activated. The applications use the
93956  * SetD1PID and
93957  *
93958  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
93959  *
93960  * 1'b0: DATA0
93961  *
93962  * 1'b1: DATA1
93963  *
93964  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
93965  *
93966  * DMA mode.
93967  *
93968  * 1'b0 RO
93969  *
93970  * Even/Odd (Micro)Frame (EO_FrNum)
93971  *
93972  * In non-Scatter/Gather DMA mode:
93973  *
93974  * Applies to isochronous IN and OUT endpoints only.
93975  *
93976  * Indicates the (micro)frame number in which the core transmits/receives
93977  * isochronous
93978  *
93979  * data for this endpoint. The application must program the even/odd (micro) frame
93980  *
93981  * number in which it intends to transmit/receive isochronous data for this
93982  * endpoint using
93983  *
93984  * the SetEvnFr and SetOddFr fields in this register.
93985  *
93986  * 1'b0: Even (micro)frame
93987  *
93988  * 1'b1: Odd (micro)frame
93989  *
93990  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
93991  * number
93992  *
93993  * in which to send data is provided in the transmit descriptor structure. The
93994  * frame in
93995  *
93996  * which data is received is updated in receive descriptor structure.
93997  *
93998  * Field Enumeration Values:
93999  *
94000  * Enum | Value | Description
94001  * :-----------------------------------|:------|:-----------------------------
94002  * ALT_USB_DEV_DIEPCTL11_DPID_E_INACT | 0x0 | Endpoint Data PID not active
94003  * ALT_USB_DEV_DIEPCTL11_DPID_E_ACT | 0x1 | Endpoint Data PID active
94004  *
94005  * Field Access Macros:
94006  *
94007  */
94008 /*
94009  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_DPID
94010  *
94011  * Endpoint Data PID not active
94012  */
94013 #define ALT_USB_DEV_DIEPCTL11_DPID_E_INACT 0x0
94014 /*
94015  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_DPID
94016  *
94017  * Endpoint Data PID active
94018  */
94019 #define ALT_USB_DEV_DIEPCTL11_DPID_E_ACT 0x1
94020 
94021 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_DPID register field. */
94022 #define ALT_USB_DEV_DIEPCTL11_DPID_LSB 16
94023 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_DPID register field. */
94024 #define ALT_USB_DEV_DIEPCTL11_DPID_MSB 16
94025 /* The width in bits of the ALT_USB_DEV_DIEPCTL11_DPID register field. */
94026 #define ALT_USB_DEV_DIEPCTL11_DPID_WIDTH 1
94027 /* The mask used to set the ALT_USB_DEV_DIEPCTL11_DPID register field value. */
94028 #define ALT_USB_DEV_DIEPCTL11_DPID_SET_MSK 0x00010000
94029 /* The mask used to clear the ALT_USB_DEV_DIEPCTL11_DPID register field value. */
94030 #define ALT_USB_DEV_DIEPCTL11_DPID_CLR_MSK 0xfffeffff
94031 /* The reset value of the ALT_USB_DEV_DIEPCTL11_DPID register field. */
94032 #define ALT_USB_DEV_DIEPCTL11_DPID_RESET 0x0
94033 /* Extracts the ALT_USB_DEV_DIEPCTL11_DPID field value from a register. */
94034 #define ALT_USB_DEV_DIEPCTL11_DPID_GET(value) (((value) & 0x00010000) >> 16)
94035 /* Produces a ALT_USB_DEV_DIEPCTL11_DPID register field value suitable for setting the register. */
94036 #define ALT_USB_DEV_DIEPCTL11_DPID_SET(value) (((value) << 16) & 0x00010000)
94037 
94038 /*
94039  * Field : naksts
94040  *
94041  * NAK Status (NAKSts)
94042  *
94043  * Indicates the following:
94044  *
94045  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
94046  *
94047  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
94048  *
94049  * When either the application or the core sets this bit:
94050  *
94051  * The core stops receiving any data on an OUT endpoint, even if there is space in
94052  *
94053  * the RxFIFO to accommodate the incoming packet.
94054  *
94055  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
94056  *
94057  * endpoint, even if there data is available in the TxFIFO.
94058  *
94059  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
94060  *
94061  * if there data is available in the TxFIFO.
94062  *
94063  * Irrespective of this bit's setting, the core always responds to SETUP data
94064  * packets with
94065  *
94066  * an ACK handshake.
94067  *
94068  * Field Enumeration Values:
94069  *
94070  * Enum | Value | Description
94071  * :--------------------------------------|:------|:------------------------------------------------
94072  * ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
94073  * : | | based on the FIFO status
94074  * ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
94075  * : | | endpoint
94076  *
94077  * Field Access Macros:
94078  *
94079  */
94080 /*
94081  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_NAKSTS
94082  *
94083  * The core is transmitting non-NAK handshakes based on the FIFO status
94084  */
94085 #define ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NONNAK 0x0
94086 /*
94087  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_NAKSTS
94088  *
94089  * The core is transmitting NAK handshakes on this endpoint
94090  */
94091 #define ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NAK 0x1
94092 
94093 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */
94094 #define ALT_USB_DEV_DIEPCTL11_NAKSTS_LSB 17
94095 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */
94096 #define ALT_USB_DEV_DIEPCTL11_NAKSTS_MSB 17
94097 /* The width in bits of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */
94098 #define ALT_USB_DEV_DIEPCTL11_NAKSTS_WIDTH 1
94099 /* The mask used to set the ALT_USB_DEV_DIEPCTL11_NAKSTS register field value. */
94100 #define ALT_USB_DEV_DIEPCTL11_NAKSTS_SET_MSK 0x00020000
94101 /* The mask used to clear the ALT_USB_DEV_DIEPCTL11_NAKSTS register field value. */
94102 #define ALT_USB_DEV_DIEPCTL11_NAKSTS_CLR_MSK 0xfffdffff
94103 /* The reset value of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */
94104 #define ALT_USB_DEV_DIEPCTL11_NAKSTS_RESET 0x0
94105 /* Extracts the ALT_USB_DEV_DIEPCTL11_NAKSTS field value from a register. */
94106 #define ALT_USB_DEV_DIEPCTL11_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
94107 /* Produces a ALT_USB_DEV_DIEPCTL11_NAKSTS register field value suitable for setting the register. */
94108 #define ALT_USB_DEV_DIEPCTL11_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
94109 
94110 /*
94111  * Field : eptype
94112  *
94113  * Endpoint Type (EPType)
94114  *
94115  * This is the transfer type supported by this logical endpoint.
94116  *
94117  * 2'b00: Control
94118  *
94119  * 2'b01: Isochronous
94120  *
94121  * 2'b10: Bulk
94122  *
94123  * 2'b11: Interrupt
94124  *
94125  * Field Enumeration Values:
94126  *
94127  * Enum | Value | Description
94128  * :-------------------------------------------|:------|:------------
94129  * ALT_USB_DEV_DIEPCTL11_EPTYPE_E_CTL | 0x0 | Control
94130  * ALT_USB_DEV_DIEPCTL11_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
94131  * ALT_USB_DEV_DIEPCTL11_EPTYPE_E_BULK | 0x2 | Bulk
94132  * ALT_USB_DEV_DIEPCTL11_EPTYPE_E_INTERRUP | 0x3 | Interrupt
94133  *
94134  * Field Access Macros:
94135  *
94136  */
94137 /*
94138  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE
94139  *
94140  * Control
94141  */
94142 #define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_CTL 0x0
94143 /*
94144  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE
94145  *
94146  * Isochronous
94147  */
94148 #define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_ISOCHRONOUS 0x1
94149 /*
94150  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE
94151  *
94152  * Bulk
94153  */
94154 #define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_BULK 0x2
94155 /*
94156  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE
94157  *
94158  * Interrupt
94159  */
94160 #define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_INTERRUP 0x3
94161 
94162 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */
94163 #define ALT_USB_DEV_DIEPCTL11_EPTYPE_LSB 18
94164 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */
94165 #define ALT_USB_DEV_DIEPCTL11_EPTYPE_MSB 19
94166 /* The width in bits of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */
94167 #define ALT_USB_DEV_DIEPCTL11_EPTYPE_WIDTH 2
94168 /* The mask used to set the ALT_USB_DEV_DIEPCTL11_EPTYPE register field value. */
94169 #define ALT_USB_DEV_DIEPCTL11_EPTYPE_SET_MSK 0x000c0000
94170 /* The mask used to clear the ALT_USB_DEV_DIEPCTL11_EPTYPE register field value. */
94171 #define ALT_USB_DEV_DIEPCTL11_EPTYPE_CLR_MSK 0xfff3ffff
94172 /* The reset value of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */
94173 #define ALT_USB_DEV_DIEPCTL11_EPTYPE_RESET 0x0
94174 /* Extracts the ALT_USB_DEV_DIEPCTL11_EPTYPE field value from a register. */
94175 #define ALT_USB_DEV_DIEPCTL11_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
94176 /* Produces a ALT_USB_DEV_DIEPCTL11_EPTYPE register field value suitable for setting the register. */
94177 #define ALT_USB_DEV_DIEPCTL11_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
94178 
94179 /*
94180  * Field : stall
94181  *
94182  * STALL Handshake (Stall)
94183  *
94184  * Applies to non-control, non-isochronous IN and OUT endpoints only.
94185  *
94186  * The application sets this bit to stall all tokens from the USB host to this
94187  * endpoint. If a
94188  *
94189  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
94190  * bit, the
94191  *
94192  * STALL bit takes priority. Only the application can clear this bit, never the
94193  * core.
94194  *
94195  * 1'b0 R_W
94196  *
94197  * Applies to control endpoints only.
94198  *
94199  * The application can only set this bit, and the core clears it, when a SETUP
94200  * token is
94201  *
94202  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
94203  * OUT
94204  *
94205  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
94206  * this bit's
94207  *
94208  * setting, the core always responds to SETUP data packets with an ACK handshake.
94209  *
94210  * Field Enumeration Values:
94211  *
94212  * Enum | Value | Description
94213  * :------------------------------------|:------|:----------------------------
94214  * ALT_USB_DEV_DIEPCTL11_STALL_E_INACT | 0x0 | STALL All Tokens not active
94215  * ALT_USB_DEV_DIEPCTL11_STALL_E_ACT | 0x1 | STALL All Tokens active
94216  *
94217  * Field Access Macros:
94218  *
94219  */
94220 /*
94221  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_STALL
94222  *
94223  * STALL All Tokens not active
94224  */
94225 #define ALT_USB_DEV_DIEPCTL11_STALL_E_INACT 0x0
94226 /*
94227  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_STALL
94228  *
94229  * STALL All Tokens active
94230  */
94231 #define ALT_USB_DEV_DIEPCTL11_STALL_E_ACT 0x1
94232 
94233 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_STALL register field. */
94234 #define ALT_USB_DEV_DIEPCTL11_STALL_LSB 21
94235 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_STALL register field. */
94236 #define ALT_USB_DEV_DIEPCTL11_STALL_MSB 21
94237 /* The width in bits of the ALT_USB_DEV_DIEPCTL11_STALL register field. */
94238 #define ALT_USB_DEV_DIEPCTL11_STALL_WIDTH 1
94239 /* The mask used to set the ALT_USB_DEV_DIEPCTL11_STALL register field value. */
94240 #define ALT_USB_DEV_DIEPCTL11_STALL_SET_MSK 0x00200000
94241 /* The mask used to clear the ALT_USB_DEV_DIEPCTL11_STALL register field value. */
94242 #define ALT_USB_DEV_DIEPCTL11_STALL_CLR_MSK 0xffdfffff
94243 /* The reset value of the ALT_USB_DEV_DIEPCTL11_STALL register field. */
94244 #define ALT_USB_DEV_DIEPCTL11_STALL_RESET 0x0
94245 /* Extracts the ALT_USB_DEV_DIEPCTL11_STALL field value from a register. */
94246 #define ALT_USB_DEV_DIEPCTL11_STALL_GET(value) (((value) & 0x00200000) >> 21)
94247 /* Produces a ALT_USB_DEV_DIEPCTL11_STALL register field value suitable for setting the register. */
94248 #define ALT_USB_DEV_DIEPCTL11_STALL_SET(value) (((value) << 21) & 0x00200000)
94249 
94250 /*
94251  * Field : txfnum
94252  *
94253  * TxFIFO Number (TxFNum)
94254  *
94255  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
94256  *
94257  * endpoints must map this to the corresponding Periodic TxFIFO number.
94258  *
94259  * 4'h0: Non-Periodic TxFIFO
94260  *
94261  * Others: Specified Periodic TxFIFO.number
94262  *
94263  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
94264  *
94265  * applications such as mass storage. The core treats an IN endpoint as a non-
94266  * periodic
94267  *
94268  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
94269  * must be
94270  *
94271  * allocated for an interrupt IN endpoint, and the number of this
94272  *
94273  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
94274  *
94275  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
94276  *
94277  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
94278  *
94279  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
94280  *
94281  * This field is valid only for IN endpoints.
94282  *
94283  * Field Access Macros:
94284  *
94285  */
94286 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */
94287 #define ALT_USB_DEV_DIEPCTL11_TXFNUM_LSB 22
94288 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */
94289 #define ALT_USB_DEV_DIEPCTL11_TXFNUM_MSB 25
94290 /* The width in bits of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */
94291 #define ALT_USB_DEV_DIEPCTL11_TXFNUM_WIDTH 4
94292 /* The mask used to set the ALT_USB_DEV_DIEPCTL11_TXFNUM register field value. */
94293 #define ALT_USB_DEV_DIEPCTL11_TXFNUM_SET_MSK 0x03c00000
94294 /* The mask used to clear the ALT_USB_DEV_DIEPCTL11_TXFNUM register field value. */
94295 #define ALT_USB_DEV_DIEPCTL11_TXFNUM_CLR_MSK 0xfc3fffff
94296 /* The reset value of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */
94297 #define ALT_USB_DEV_DIEPCTL11_TXFNUM_RESET 0x0
94298 /* Extracts the ALT_USB_DEV_DIEPCTL11_TXFNUM field value from a register. */
94299 #define ALT_USB_DEV_DIEPCTL11_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
94300 /* Produces a ALT_USB_DEV_DIEPCTL11_TXFNUM register field value suitable for setting the register. */
94301 #define ALT_USB_DEV_DIEPCTL11_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
94302 
94303 /*
94304  * Field : cnak
94305  *
94306  * Clear NAK (CNAK)
94307  *
94308  * A write to this bit clears the NAK bit For the endpoint.
94309  *
94310  * Field Enumeration Values:
94311  *
94312  * Enum | Value | Description
94313  * :-----------------------------------|:------|:-------------
94314  * ALT_USB_DEV_DIEPCTL11_CNAK_E_INACT | 0x0 | No Clear NAK
94315  * ALT_USB_DEV_DIEPCTL11_CNAK_E_ACT | 0x1 | Clear NAK
94316  *
94317  * Field Access Macros:
94318  *
94319  */
94320 /*
94321  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_CNAK
94322  *
94323  * No Clear NAK
94324  */
94325 #define ALT_USB_DEV_DIEPCTL11_CNAK_E_INACT 0x0
94326 /*
94327  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_CNAK
94328  *
94329  * Clear NAK
94330  */
94331 #define ALT_USB_DEV_DIEPCTL11_CNAK_E_ACT 0x1
94332 
94333 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */
94334 #define ALT_USB_DEV_DIEPCTL11_CNAK_LSB 26
94335 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */
94336 #define ALT_USB_DEV_DIEPCTL11_CNAK_MSB 26
94337 /* The width in bits of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */
94338 #define ALT_USB_DEV_DIEPCTL11_CNAK_WIDTH 1
94339 /* The mask used to set the ALT_USB_DEV_DIEPCTL11_CNAK register field value. */
94340 #define ALT_USB_DEV_DIEPCTL11_CNAK_SET_MSK 0x04000000
94341 /* The mask used to clear the ALT_USB_DEV_DIEPCTL11_CNAK register field value. */
94342 #define ALT_USB_DEV_DIEPCTL11_CNAK_CLR_MSK 0xfbffffff
94343 /* The reset value of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */
94344 #define ALT_USB_DEV_DIEPCTL11_CNAK_RESET 0x0
94345 /* Extracts the ALT_USB_DEV_DIEPCTL11_CNAK field value from a register. */
94346 #define ALT_USB_DEV_DIEPCTL11_CNAK_GET(value) (((value) & 0x04000000) >> 26)
94347 /* Produces a ALT_USB_DEV_DIEPCTL11_CNAK register field value suitable for setting the register. */
94348 #define ALT_USB_DEV_DIEPCTL11_CNAK_SET(value) (((value) << 26) & 0x04000000)
94349 
94350 /*
94351  * Field : snak
94352  *
94353  * Set NAK (SNAK)
94354  *
94355  * A write to this bit sets the NAK bit For the endpoint.
94356  *
94357  * Using this bit, the application can control the transmission of NAK
94358  *
94359  * handshakes on an endpoint. The core can also Set this bit For an
94360  *
94361  * endpoint after a SETUP packet is received on that endpoint.
94362  *
94363  * Field Enumeration Values:
94364  *
94365  * Enum | Value | Description
94366  * :-----------------------------------|:------|:------------
94367  * ALT_USB_DEV_DIEPCTL11_SNAK_E_INACT | 0x0 | No Set NAK
94368  * ALT_USB_DEV_DIEPCTL11_SNAK_E_ACT | 0x1 | Set NAK
94369  *
94370  * Field Access Macros:
94371  *
94372  */
94373 /*
94374  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SNAK
94375  *
94376  * No Set NAK
94377  */
94378 #define ALT_USB_DEV_DIEPCTL11_SNAK_E_INACT 0x0
94379 /*
94380  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SNAK
94381  *
94382  * Set NAK
94383  */
94384 #define ALT_USB_DEV_DIEPCTL11_SNAK_E_ACT 0x1
94385 
94386 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */
94387 #define ALT_USB_DEV_DIEPCTL11_SNAK_LSB 27
94388 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */
94389 #define ALT_USB_DEV_DIEPCTL11_SNAK_MSB 27
94390 /* The width in bits of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */
94391 #define ALT_USB_DEV_DIEPCTL11_SNAK_WIDTH 1
94392 /* The mask used to set the ALT_USB_DEV_DIEPCTL11_SNAK register field value. */
94393 #define ALT_USB_DEV_DIEPCTL11_SNAK_SET_MSK 0x08000000
94394 /* The mask used to clear the ALT_USB_DEV_DIEPCTL11_SNAK register field value. */
94395 #define ALT_USB_DEV_DIEPCTL11_SNAK_CLR_MSK 0xf7ffffff
94396 /* The reset value of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */
94397 #define ALT_USB_DEV_DIEPCTL11_SNAK_RESET 0x0
94398 /* Extracts the ALT_USB_DEV_DIEPCTL11_SNAK field value from a register. */
94399 #define ALT_USB_DEV_DIEPCTL11_SNAK_GET(value) (((value) & 0x08000000) >> 27)
94400 /* Produces a ALT_USB_DEV_DIEPCTL11_SNAK register field value suitable for setting the register. */
94401 #define ALT_USB_DEV_DIEPCTL11_SNAK_SET(value) (((value) << 27) & 0x08000000)
94402 
94403 /*
94404  * Field : setd0pid
94405  *
94406  * Set DATA0 PID (SetD0PID)
94407  *
94408  * Applies to interrupt/bulk IN and OUT endpoints only.
94409  *
94410  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
94411  * to DATA0.
94412  *
94413  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
94414  *
94415  * DMA mode.
94416  *
94417  * 1'b0 WO
94418  *
94419  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
94420  *
94421  * Applies to isochronous IN and OUT endpoints only.
94422  *
94423  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
94424  * (micro)
94425  *
94426  * frame.
94427  *
94428  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
94429  * number
94430  *
94431  * in which to send data is in the transmit descriptor structure. The frame in
94432  * which to
94433  *
94434  * receive data is updated in receive descriptor structure.
94435  *
94436  * Field Enumeration Values:
94437  *
94438  * Enum | Value | Description
94439  * :--------------------------------------|:------|:----------------------------
94440  * ALT_USB_DEV_DIEPCTL11_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
94441  * ALT_USB_DEV_DIEPCTL11_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
94442  *
94443  * Field Access Macros:
94444  *
94445  */
94446 /*
94447  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD0PID
94448  *
94449  * Disables Set DATA0 PID
94450  */
94451 #define ALT_USB_DEV_DIEPCTL11_SETD0PID_E_DISD 0x0
94452 /*
94453  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD0PID
94454  *
94455  * Endpoint Data PID to DATA0)
94456  */
94457 #define ALT_USB_DEV_DIEPCTL11_SETD0PID_E_END 0x1
94458 
94459 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */
94460 #define ALT_USB_DEV_DIEPCTL11_SETD0PID_LSB 28
94461 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */
94462 #define ALT_USB_DEV_DIEPCTL11_SETD0PID_MSB 28
94463 /* The width in bits of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */
94464 #define ALT_USB_DEV_DIEPCTL11_SETD0PID_WIDTH 1
94465 /* The mask used to set the ALT_USB_DEV_DIEPCTL11_SETD0PID register field value. */
94466 #define ALT_USB_DEV_DIEPCTL11_SETD0PID_SET_MSK 0x10000000
94467 /* The mask used to clear the ALT_USB_DEV_DIEPCTL11_SETD0PID register field value. */
94468 #define ALT_USB_DEV_DIEPCTL11_SETD0PID_CLR_MSK 0xefffffff
94469 /* The reset value of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */
94470 #define ALT_USB_DEV_DIEPCTL11_SETD0PID_RESET 0x0
94471 /* Extracts the ALT_USB_DEV_DIEPCTL11_SETD0PID field value from a register. */
94472 #define ALT_USB_DEV_DIEPCTL11_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
94473 /* Produces a ALT_USB_DEV_DIEPCTL11_SETD0PID register field value suitable for setting the register. */
94474 #define ALT_USB_DEV_DIEPCTL11_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
94475 
94476 /*
94477  * Field : setd1pid
94478  *
94479  * Set DATA1 PID (SetD1PID)
94480  *
94481  * Applies to interrupt/bulk IN and OUT endpoints only.
94482  *
94483  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
94484  * to DATA1.
94485  *
94486  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
94487  *
94488  * DMA mode.
94489  *
94490  * Set Odd (micro)frame (SetOddFr)
94491  *
94492  * Applies to isochronous IN and OUT endpoints only.
94493  *
94494  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
94495  *
94496  * (micro)frame.
94497  *
94498  * This field is not applicable for Scatter/Gather DMA mode.
94499  *
94500  * Field Enumeration Values:
94501  *
94502  * Enum | Value | Description
94503  * :--------------------------------------|:------|:-----------------------
94504  * ALT_USB_DEV_DIEPCTL11_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
94505  * ALT_USB_DEV_DIEPCTL11_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
94506  *
94507  * Field Access Macros:
94508  *
94509  */
94510 /*
94511  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD1PID
94512  *
94513  * Disables Set DATA1 PID
94514  */
94515 #define ALT_USB_DEV_DIEPCTL11_SETD1PID_E_DISD 0x0
94516 /*
94517  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD1PID
94518  *
94519  * Enables Set DATA1 PID
94520  */
94521 #define ALT_USB_DEV_DIEPCTL11_SETD1PID_E_END 0x1
94522 
94523 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */
94524 #define ALT_USB_DEV_DIEPCTL11_SETD1PID_LSB 29
94525 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */
94526 #define ALT_USB_DEV_DIEPCTL11_SETD1PID_MSB 29
94527 /* The width in bits of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */
94528 #define ALT_USB_DEV_DIEPCTL11_SETD1PID_WIDTH 1
94529 /* The mask used to set the ALT_USB_DEV_DIEPCTL11_SETD1PID register field value. */
94530 #define ALT_USB_DEV_DIEPCTL11_SETD1PID_SET_MSK 0x20000000
94531 /* The mask used to clear the ALT_USB_DEV_DIEPCTL11_SETD1PID register field value. */
94532 #define ALT_USB_DEV_DIEPCTL11_SETD1PID_CLR_MSK 0xdfffffff
94533 /* The reset value of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */
94534 #define ALT_USB_DEV_DIEPCTL11_SETD1PID_RESET 0x0
94535 /* Extracts the ALT_USB_DEV_DIEPCTL11_SETD1PID field value from a register. */
94536 #define ALT_USB_DEV_DIEPCTL11_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
94537 /* Produces a ALT_USB_DEV_DIEPCTL11_SETD1PID register field value suitable for setting the register. */
94538 #define ALT_USB_DEV_DIEPCTL11_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
94539 
94540 /*
94541  * Field : epdis
94542  *
94543  * Endpoint Disable (EPDis)
94544  *
94545  * Applies to IN and OUT endpoints.
94546  *
94547  * The application sets this bit to stop transmitting/receiving data on an
94548  * endpoint, even
94549  *
94550  * before the transfer for that endpoint is complete. The application must wait for
94551  * the
94552  *
94553  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
94554  * clears
94555  *
94556  * this bit before setting the Endpoint Disabled interrupt. The application must
94557  * set this bit
94558  *
94559  * only if Endpoint Enable is already set for this endpoint.
94560  *
94561  * Field Enumeration Values:
94562  *
94563  * Enum | Value | Description
94564  * :------------------------------------|:------|:--------------------
94565  * ALT_USB_DEV_DIEPCTL11_EPDIS_E_INACT | 0x0 | No Endpoint Disable
94566  * ALT_USB_DEV_DIEPCTL11_EPDIS_E_ACT | 0x1 | Endpoint Disable
94567  *
94568  * Field Access Macros:
94569  *
94570  */
94571 /*
94572  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPDIS
94573  *
94574  * No Endpoint Disable
94575  */
94576 #define ALT_USB_DEV_DIEPCTL11_EPDIS_E_INACT 0x0
94577 /*
94578  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPDIS
94579  *
94580  * Endpoint Disable
94581  */
94582 #define ALT_USB_DEV_DIEPCTL11_EPDIS_E_ACT 0x1
94583 
94584 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */
94585 #define ALT_USB_DEV_DIEPCTL11_EPDIS_LSB 30
94586 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */
94587 #define ALT_USB_DEV_DIEPCTL11_EPDIS_MSB 30
94588 /* The width in bits of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */
94589 #define ALT_USB_DEV_DIEPCTL11_EPDIS_WIDTH 1
94590 /* The mask used to set the ALT_USB_DEV_DIEPCTL11_EPDIS register field value. */
94591 #define ALT_USB_DEV_DIEPCTL11_EPDIS_SET_MSK 0x40000000
94592 /* The mask used to clear the ALT_USB_DEV_DIEPCTL11_EPDIS register field value. */
94593 #define ALT_USB_DEV_DIEPCTL11_EPDIS_CLR_MSK 0xbfffffff
94594 /* The reset value of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */
94595 #define ALT_USB_DEV_DIEPCTL11_EPDIS_RESET 0x0
94596 /* Extracts the ALT_USB_DEV_DIEPCTL11_EPDIS field value from a register. */
94597 #define ALT_USB_DEV_DIEPCTL11_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
94598 /* Produces a ALT_USB_DEV_DIEPCTL11_EPDIS register field value suitable for setting the register. */
94599 #define ALT_USB_DEV_DIEPCTL11_EPDIS_SET(value) (((value) << 30) & 0x40000000)
94600 
94601 /*
94602  * Field : epena
94603  *
94604  * Endpoint Enable (EPEna)
94605  *
94606  * Applies to IN and OUT endpoints.
94607  *
94608  * When Scatter/Gather DMA mode is enabled,
94609  *
94610  * For IN endpoints this bit indicates that the descriptor structure and data
94611  * buffer with
94612  *
94613  * data ready to transmit is setup.
94614  *
94615  * For OUT endpoint it indicates that the descriptor structure and data buffer to
94616  *
94617  * receive data is setup.
94618  *
94619  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
94620  *
94621  * DMA mode:
94622  *
94623  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
94624  * the
94625  *
94626  * endpoint.
94627  *
94628  * * For OUT endpoints, this bit indicates that the application has allocated the
94629  *
94630  * memory to start receiving data from the USB.
94631  *
94632  * * The core clears this bit before setting any of the following interrupts on
94633  * this
94634  *
94635  * endpoint:
94636  *
94637  * SETUP Phase Done
94638  *
94639  * Endpoint Disabled
94640  *
94641  * Transfer Completed
94642  *
94643  * Note: For control endpoints in DMA mode, this bit must be set to be able to
94644  * transfer
94645  *
94646  * SETUP data packets in memory.
94647  *
94648  * Field Enumeration Values:
94649  *
94650  * Enum | Value | Description
94651  * :------------------------------------|:------|:-------------------------
94652  * ALT_USB_DEV_DIEPCTL11_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
94653  * ALT_USB_DEV_DIEPCTL11_EPENA_E_ACT | 0x1 | Endpoint Enable active
94654  *
94655  * Field Access Macros:
94656  *
94657  */
94658 /*
94659  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPENA
94660  *
94661  * Endpoint Enable inactive
94662  */
94663 #define ALT_USB_DEV_DIEPCTL11_EPENA_E_INACT 0x0
94664 /*
94665  * Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPENA
94666  *
94667  * Endpoint Enable active
94668  */
94669 #define ALT_USB_DEV_DIEPCTL11_EPENA_E_ACT 0x1
94670 
94671 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */
94672 #define ALT_USB_DEV_DIEPCTL11_EPENA_LSB 31
94673 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */
94674 #define ALT_USB_DEV_DIEPCTL11_EPENA_MSB 31
94675 /* The width in bits of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */
94676 #define ALT_USB_DEV_DIEPCTL11_EPENA_WIDTH 1
94677 /* The mask used to set the ALT_USB_DEV_DIEPCTL11_EPENA register field value. */
94678 #define ALT_USB_DEV_DIEPCTL11_EPENA_SET_MSK 0x80000000
94679 /* The mask used to clear the ALT_USB_DEV_DIEPCTL11_EPENA register field value. */
94680 #define ALT_USB_DEV_DIEPCTL11_EPENA_CLR_MSK 0x7fffffff
94681 /* The reset value of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */
94682 #define ALT_USB_DEV_DIEPCTL11_EPENA_RESET 0x0
94683 /* Extracts the ALT_USB_DEV_DIEPCTL11_EPENA field value from a register. */
94684 #define ALT_USB_DEV_DIEPCTL11_EPENA_GET(value) (((value) & 0x80000000) >> 31)
94685 /* Produces a ALT_USB_DEV_DIEPCTL11_EPENA register field value suitable for setting the register. */
94686 #define ALT_USB_DEV_DIEPCTL11_EPENA_SET(value) (((value) << 31) & 0x80000000)
94687 
94688 #ifndef __ASSEMBLY__
94689 /*
94690  * WARNING: The C register and register group struct declarations are provided for
94691  * convenience and illustrative purposes. They should, however, be used with
94692  * caution as the C language standard provides no guarantees about the alignment or
94693  * atomicity of device memory accesses. The recommended practice for writing
94694  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
94695  * alt_write_word() functions.
94696  *
94697  * The struct declaration for register ALT_USB_DEV_DIEPCTL11.
94698  */
94699 struct ALT_USB_DEV_DIEPCTL11_s
94700 {
94701  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL11_MPS */
94702  uint32_t : 4; /* *UNDEFINED* */
94703  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL11_USBACTEP */
94704  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL11_DPID */
94705  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL11_NAKSTS */
94706  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL11_EPTYPE */
94707  uint32_t : 1; /* *UNDEFINED* */
94708  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL11_STALL */
94709  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL11_TXFNUM */
94710  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL11_CNAK */
94711  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL11_SNAK */
94712  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL11_SETD0PID */
94713  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL11_SETD1PID */
94714  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL11_EPDIS */
94715  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL11_EPENA */
94716 };
94717 
94718 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL11. */
94719 typedef volatile struct ALT_USB_DEV_DIEPCTL11_s ALT_USB_DEV_DIEPCTL11_t;
94720 #endif /* __ASSEMBLY__ */
94721 
94722 /* The reset value of the ALT_USB_DEV_DIEPCTL11 register. */
94723 #define ALT_USB_DEV_DIEPCTL11_RESET 0x00000000
94724 /* The byte offset of the ALT_USB_DEV_DIEPCTL11 register from the beginning of the component. */
94725 #define ALT_USB_DEV_DIEPCTL11_OFST 0x260
94726 /* The address of the ALT_USB_DEV_DIEPCTL11 register. */
94727 #define ALT_USB_DEV_DIEPCTL11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL11_OFST))
94728 
94729 /*
94730  * Register : diepint11
94731  *
94732  * Device IN Endpoint 11 Interrupt Register
94733  *
94734  * Register Layout
94735  *
94736  * Bits | Access | Reset | Description
94737  * :--------|:-------|:------|:----------------------------------
94738  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_XFERCOMPL
94739  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_EPDISBLD
94740  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_AHBERR
94741  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_TMO
94742  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_INTKNTXFEMP
94743  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_INTKNEPMIS
94744  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_INEPNAKEFF
94745  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT11_TXFEMP
94746  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN
94747  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_BNAINTR
94748  * [10] | ??? | 0x0 | *UNDEFINED*
94749  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_PKTDRPSTS
94750  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_BBLEERR
94751  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_NAKINTRPT
94752  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_NYETINTRPT
94753  * [31:15] | ??? | 0x0 | *UNDEFINED*
94754  *
94755  */
94756 /*
94757  * Field : xfercompl
94758  *
94759  * Transfer Completed Interrupt (XferCompl)
94760  *
94761  * Applies to IN and OUT endpoints.
94762  *
94763  * When Scatter/Gather DMA mode is enabled
94764  *
94765  * * For IN endpoint this field indicates that the requested data
94766  *
94767  * from the descriptor is moved from external system memory
94768  *
94769  * to internal FIFO.
94770  *
94771  * * For OUT endpoint this field indicates that the requested
94772  *
94773  * data from the internal FIFO is moved to external system
94774  *
94775  * memory. This interrupt is generated only when the
94776  *
94777  * corresponding endpoint descriptor is closed, and the IOC
94778  *
94779  * bit For the corresponding descriptor is Set.
94780  *
94781  * When Scatter/Gather DMA mode is disabled, this field
94782  *
94783  * indicates that the programmed transfer is complete on the
94784  *
94785  * AHB as well as on the USB, For this endpoint.
94786  *
94787  * Field Enumeration Values:
94788  *
94789  * Enum | Value | Description
94790  * :----------------------------------------|:------|:-----------------------------
94791  * ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_INACT | 0x0 | No Interrupt
94792  * ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
94793  *
94794  * Field Access Macros:
94795  *
94796  */
94797 /*
94798  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_XFERCOMPL
94799  *
94800  * No Interrupt
94801  */
94802 #define ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_INACT 0x0
94803 /*
94804  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_XFERCOMPL
94805  *
94806  * Transfer Completed Interrupt
94807  */
94808 #define ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_ACT 0x1
94809 
94810 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */
94811 #define ALT_USB_DEV_DIEPINT11_XFERCOMPL_LSB 0
94812 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */
94813 #define ALT_USB_DEV_DIEPINT11_XFERCOMPL_MSB 0
94814 /* The width in bits of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */
94815 #define ALT_USB_DEV_DIEPINT11_XFERCOMPL_WIDTH 1
94816 /* The mask used to set the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field value. */
94817 #define ALT_USB_DEV_DIEPINT11_XFERCOMPL_SET_MSK 0x00000001
94818 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field value. */
94819 #define ALT_USB_DEV_DIEPINT11_XFERCOMPL_CLR_MSK 0xfffffffe
94820 /* The reset value of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */
94821 #define ALT_USB_DEV_DIEPINT11_XFERCOMPL_RESET 0x0
94822 /* Extracts the ALT_USB_DEV_DIEPINT11_XFERCOMPL field value from a register. */
94823 #define ALT_USB_DEV_DIEPINT11_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
94824 /* Produces a ALT_USB_DEV_DIEPINT11_XFERCOMPL register field value suitable for setting the register. */
94825 #define ALT_USB_DEV_DIEPINT11_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
94826 
94827 /*
94828  * Field : epdisbld
94829  *
94830  * Endpoint Disabled Interrupt (EPDisbld)
94831  *
94832  * Applies to IN and OUT endpoints.
94833  *
94834  * This bit indicates that the endpoint is disabled per the
94835  *
94836  * application's request.
94837  *
94838  * Field Enumeration Values:
94839  *
94840  * Enum | Value | Description
94841  * :---------------------------------------|:------|:----------------------------
94842  * ALT_USB_DEV_DIEPINT11_EPDISBLD_E_INACT | 0x0 | No Interrupt
94843  * ALT_USB_DEV_DIEPINT11_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
94844  *
94845  * Field Access Macros:
94846  *
94847  */
94848 /*
94849  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_EPDISBLD
94850  *
94851  * No Interrupt
94852  */
94853 #define ALT_USB_DEV_DIEPINT11_EPDISBLD_E_INACT 0x0
94854 /*
94855  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_EPDISBLD
94856  *
94857  * Endpoint Disabled Interrupt
94858  */
94859 #define ALT_USB_DEV_DIEPINT11_EPDISBLD_E_ACT 0x1
94860 
94861 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */
94862 #define ALT_USB_DEV_DIEPINT11_EPDISBLD_LSB 1
94863 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */
94864 #define ALT_USB_DEV_DIEPINT11_EPDISBLD_MSB 1
94865 /* The width in bits of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */
94866 #define ALT_USB_DEV_DIEPINT11_EPDISBLD_WIDTH 1
94867 /* The mask used to set the ALT_USB_DEV_DIEPINT11_EPDISBLD register field value. */
94868 #define ALT_USB_DEV_DIEPINT11_EPDISBLD_SET_MSK 0x00000002
94869 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_EPDISBLD register field value. */
94870 #define ALT_USB_DEV_DIEPINT11_EPDISBLD_CLR_MSK 0xfffffffd
94871 /* The reset value of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */
94872 #define ALT_USB_DEV_DIEPINT11_EPDISBLD_RESET 0x0
94873 /* Extracts the ALT_USB_DEV_DIEPINT11_EPDISBLD field value from a register. */
94874 #define ALT_USB_DEV_DIEPINT11_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
94875 /* Produces a ALT_USB_DEV_DIEPINT11_EPDISBLD register field value suitable for setting the register. */
94876 #define ALT_USB_DEV_DIEPINT11_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
94877 
94878 /*
94879  * Field : ahberr
94880  *
94881  * AHB Error (AHBErr)
94882  *
94883  * Applies to IN and OUT endpoints.
94884  *
94885  * This is generated only in Internal DMA mode when there is an
94886  *
94887  * AHB error during an AHB read/write. The application can read
94888  *
94889  * the corresponding endpoint DMA address register to get the
94890  *
94891  * error address.
94892  *
94893  * Field Enumeration Values:
94894  *
94895  * Enum | Value | Description
94896  * :-------------------------------------|:------|:--------------------
94897  * ALT_USB_DEV_DIEPINT11_AHBERR_E_INACT | 0x0 | No Interrupt
94898  * ALT_USB_DEV_DIEPINT11_AHBERR_E_ACT | 0x1 | AHB Error interrupt
94899  *
94900  * Field Access Macros:
94901  *
94902  */
94903 /*
94904  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_AHBERR
94905  *
94906  * No Interrupt
94907  */
94908 #define ALT_USB_DEV_DIEPINT11_AHBERR_E_INACT 0x0
94909 /*
94910  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_AHBERR
94911  *
94912  * AHB Error interrupt
94913  */
94914 #define ALT_USB_DEV_DIEPINT11_AHBERR_E_ACT 0x1
94915 
94916 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */
94917 #define ALT_USB_DEV_DIEPINT11_AHBERR_LSB 2
94918 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */
94919 #define ALT_USB_DEV_DIEPINT11_AHBERR_MSB 2
94920 /* The width in bits of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */
94921 #define ALT_USB_DEV_DIEPINT11_AHBERR_WIDTH 1
94922 /* The mask used to set the ALT_USB_DEV_DIEPINT11_AHBERR register field value. */
94923 #define ALT_USB_DEV_DIEPINT11_AHBERR_SET_MSK 0x00000004
94924 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_AHBERR register field value. */
94925 #define ALT_USB_DEV_DIEPINT11_AHBERR_CLR_MSK 0xfffffffb
94926 /* The reset value of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */
94927 #define ALT_USB_DEV_DIEPINT11_AHBERR_RESET 0x0
94928 /* Extracts the ALT_USB_DEV_DIEPINT11_AHBERR field value from a register. */
94929 #define ALT_USB_DEV_DIEPINT11_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
94930 /* Produces a ALT_USB_DEV_DIEPINT11_AHBERR register field value suitable for setting the register. */
94931 #define ALT_USB_DEV_DIEPINT11_AHBERR_SET(value) (((value) << 2) & 0x00000004)
94932 
94933 /*
94934  * Field : timeout
94935  *
94936  * Timeout Condition (TimeOUT)
94937  *
94938  * In shared TX FIFO mode, applies to non-isochronous IN
94939  *
94940  * endpoints only.
94941  *
94942  * In dedicated FIFO mode, applies only to Control IN
94943  *
94944  * endpoints.
94945  *
94946  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
94947  *
94948  * asserted.
94949  *
94950  * Indicates that the core has detected a timeout condition on the
94951  *
94952  * USB For the last IN token on this endpoint.
94953  *
94954  * Field Enumeration Values:
94955  *
94956  * Enum | Value | Description
94957  * :----------------------------------|:------|:------------------
94958  * ALT_USB_DEV_DIEPINT11_TMO_E_INACT | 0x0 | No interrupt
94959  * ALT_USB_DEV_DIEPINT11_TMO_E_ACT | 0x1 | Timeout interrupy
94960  *
94961  * Field Access Macros:
94962  *
94963  */
94964 /*
94965  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TMO
94966  *
94967  * No interrupt
94968  */
94969 #define ALT_USB_DEV_DIEPINT11_TMO_E_INACT 0x0
94970 /*
94971  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TMO
94972  *
94973  * Timeout interrupy
94974  */
94975 #define ALT_USB_DEV_DIEPINT11_TMO_E_ACT 0x1
94976 
94977 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_TMO register field. */
94978 #define ALT_USB_DEV_DIEPINT11_TMO_LSB 3
94979 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_TMO register field. */
94980 #define ALT_USB_DEV_DIEPINT11_TMO_MSB 3
94981 /* The width in bits of the ALT_USB_DEV_DIEPINT11_TMO register field. */
94982 #define ALT_USB_DEV_DIEPINT11_TMO_WIDTH 1
94983 /* The mask used to set the ALT_USB_DEV_DIEPINT11_TMO register field value. */
94984 #define ALT_USB_DEV_DIEPINT11_TMO_SET_MSK 0x00000008
94985 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_TMO register field value. */
94986 #define ALT_USB_DEV_DIEPINT11_TMO_CLR_MSK 0xfffffff7
94987 /* The reset value of the ALT_USB_DEV_DIEPINT11_TMO register field. */
94988 #define ALT_USB_DEV_DIEPINT11_TMO_RESET 0x0
94989 /* Extracts the ALT_USB_DEV_DIEPINT11_TMO field value from a register. */
94990 #define ALT_USB_DEV_DIEPINT11_TMO_GET(value) (((value) & 0x00000008) >> 3)
94991 /* Produces a ALT_USB_DEV_DIEPINT11_TMO register field value suitable for setting the register. */
94992 #define ALT_USB_DEV_DIEPINT11_TMO_SET(value) (((value) << 3) & 0x00000008)
94993 
94994 /*
94995  * Field : intkntxfemp
94996  *
94997  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
94998  *
94999  * Applies to non-periodic IN endpoints only.
95000  *
95001  * Indicates that an IN token was received when the associated
95002  *
95003  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
95004  *
95005  * asserted on the endpoint For which the IN token was received.
95006  *
95007  * Field Enumeration Values:
95008  *
95009  * Enum | Value | Description
95010  * :------------------------------------------|:------|:----------------------------
95011  * ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
95012  * ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
95013  *
95014  * Field Access Macros:
95015  *
95016  */
95017 /*
95018  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNTXFEMP
95019  *
95020  * No interrupt
95021  */
95022 #define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_INACT 0x0
95023 /*
95024  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNTXFEMP
95025  *
95026  * IN Token Received Interrupt
95027  */
95028 #define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_ACT 0x1
95029 
95030 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */
95031 #define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_LSB 4
95032 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */
95033 #define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_MSB 4
95034 /* The width in bits of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */
95035 #define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_WIDTH 1
95036 /* The mask used to set the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field value. */
95037 #define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_SET_MSK 0x00000010
95038 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field value. */
95039 #define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_CLR_MSK 0xffffffef
95040 /* The reset value of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */
95041 #define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_RESET 0x0
95042 /* Extracts the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP field value from a register. */
95043 #define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
95044 /* Produces a ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field value suitable for setting the register. */
95045 #define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
95046 
95047 /*
95048  * Field : intknepmis
95049  *
95050  * IN Token Received with EP Mismatch (INTknEPMis)
95051  *
95052  * Applies to non-periodic IN endpoints only.
95053  *
95054  * Indicates that the data in the top of the non-periodic TxFIFO
95055  *
95056  * belongs to an endpoint other than the one For which the IN token
95057  *
95058  * was received. This interrupt is asserted on the endpoint For
95059  *
95060  * which the IN token was received.
95061  *
95062  * Field Enumeration Values:
95063  *
95064  * Enum | Value | Description
95065  * :-----------------------------------------|:------|:---------------------------------------------
95066  * ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_INACT | 0x0 | No interrupt
95067  * ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
95068  *
95069  * Field Access Macros:
95070  *
95071  */
95072 /*
95073  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNEPMIS
95074  *
95075  * No interrupt
95076  */
95077 #define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_INACT 0x0
95078 /*
95079  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNEPMIS
95080  *
95081  * IN Token Received with EP Mismatch interrupt
95082  */
95083 #define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_ACT 0x1
95084 
95085 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */
95086 #define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_LSB 5
95087 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */
95088 #define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_MSB 5
95089 /* The width in bits of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */
95090 #define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_WIDTH 1
95091 /* The mask used to set the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field value. */
95092 #define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_SET_MSK 0x00000020
95093 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field value. */
95094 #define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_CLR_MSK 0xffffffdf
95095 /* The reset value of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */
95096 #define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_RESET 0x0
95097 /* Extracts the ALT_USB_DEV_DIEPINT11_INTKNEPMIS field value from a register. */
95098 #define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
95099 /* Produces a ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field value suitable for setting the register. */
95100 #define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
95101 
95102 /*
95103  * Field : inepnakeff
95104  *
95105  * IN Endpoint NAK Effective (INEPNakEff)
95106  *
95107  * Applies to periodic IN endpoints only.
95108  *
95109  * This bit can be cleared when the application clears the IN
95110  *
95111  * endpoint NAK by writing to DIEPCTLn.CNAK.
95112  *
95113  * This interrupt indicates that the core has sampled the NAK bit
95114  *
95115  * Set (either by the application or by the core). The interrupt
95116  *
95117  * indicates that the IN endpoint NAK bit Set by the application has
95118  *
95119  * taken effect in the core.
95120  *
95121  * This interrupt does not guarantee that a NAK handshake is sent
95122  *
95123  * on the USB. A STALL bit takes priority over a NAK bit.
95124  *
95125  * Field Enumeration Values:
95126  *
95127  * Enum | Value | Description
95128  * :-----------------------------------------|:------|:------------------------------------
95129  * ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_INACT | 0x0 | No interrupt
95130  * ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
95131  *
95132  * Field Access Macros:
95133  *
95134  */
95135 /*
95136  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INEPNAKEFF
95137  *
95138  * No interrupt
95139  */
95140 #define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_INACT 0x0
95141 /*
95142  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_INEPNAKEFF
95143  *
95144  * IN Endpoint NAK Effective interrupt
95145  */
95146 #define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_ACT 0x1
95147 
95148 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */
95149 #define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_LSB 6
95150 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */
95151 #define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_MSB 6
95152 /* The width in bits of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */
95153 #define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_WIDTH 1
95154 /* The mask used to set the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field value. */
95155 #define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_SET_MSK 0x00000040
95156 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field value. */
95157 #define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_CLR_MSK 0xffffffbf
95158 /* The reset value of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */
95159 #define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_RESET 0x0
95160 /* Extracts the ALT_USB_DEV_DIEPINT11_INEPNAKEFF field value from a register. */
95161 #define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
95162 /* Produces a ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field value suitable for setting the register. */
95163 #define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
95164 
95165 /*
95166  * Field : txfemp
95167  *
95168  * Transmit FIFO Empty (TxFEmp)
95169  *
95170  * This bit is valid only For IN Endpoints
95171  *
95172  * This interrupt is asserted when the TxFIFO For this endpoint is
95173  *
95174  * either half or completely empty. The half or completely empty
95175  *
95176  * status is determined by the TxFIFO Empty Level bit in the Core
95177  *
95178  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
95179  *
95180  * Field Enumeration Values:
95181  *
95182  * Enum | Value | Description
95183  * :-------------------------------------|:------|:------------------------------
95184  * ALT_USB_DEV_DIEPINT11_TXFEMP_E_INACT | 0x0 | No interrupt
95185  * ALT_USB_DEV_DIEPINT11_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
95186  *
95187  * Field Access Macros:
95188  *
95189  */
95190 /*
95191  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFEMP
95192  *
95193  * No interrupt
95194  */
95195 #define ALT_USB_DEV_DIEPINT11_TXFEMP_E_INACT 0x0
95196 /*
95197  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFEMP
95198  *
95199  * Transmit FIFO Empty interrupt
95200  */
95201 #define ALT_USB_DEV_DIEPINT11_TXFEMP_E_ACT 0x1
95202 
95203 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */
95204 #define ALT_USB_DEV_DIEPINT11_TXFEMP_LSB 7
95205 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */
95206 #define ALT_USB_DEV_DIEPINT11_TXFEMP_MSB 7
95207 /* The width in bits of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */
95208 #define ALT_USB_DEV_DIEPINT11_TXFEMP_WIDTH 1
95209 /* The mask used to set the ALT_USB_DEV_DIEPINT11_TXFEMP register field value. */
95210 #define ALT_USB_DEV_DIEPINT11_TXFEMP_SET_MSK 0x00000080
95211 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_TXFEMP register field value. */
95212 #define ALT_USB_DEV_DIEPINT11_TXFEMP_CLR_MSK 0xffffff7f
95213 /* The reset value of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */
95214 #define ALT_USB_DEV_DIEPINT11_TXFEMP_RESET 0x1
95215 /* Extracts the ALT_USB_DEV_DIEPINT11_TXFEMP field value from a register. */
95216 #define ALT_USB_DEV_DIEPINT11_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
95217 /* Produces a ALT_USB_DEV_DIEPINT11_TXFEMP register field value suitable for setting the register. */
95218 #define ALT_USB_DEV_DIEPINT11_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
95219 
95220 /*
95221  * Field : txfifoundrn
95222  *
95223  * Fifo Underrun (TxfifoUndrn)
95224  *
95225  * Applies to IN endpoints Only
95226  *
95227  * This bit is valid only If thresholding is enabled. The core generates this
95228  * interrupt when
95229  *
95230  * it detects a transmit FIFO underrun condition For this endpoint.
95231  *
95232  * Field Enumeration Values:
95233  *
95234  * Enum | Value | Description
95235  * :------------------------------------------|:------|:------------------------
95236  * ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
95237  * ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
95238  *
95239  * Field Access Macros:
95240  *
95241  */
95242 /*
95243  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN
95244  *
95245  * No interrupt
95246  */
95247 #define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_INACT 0x0
95248 /*
95249  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN
95250  *
95251  * Fifo Underrun interrupt
95252  */
95253 #define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_ACT 0x1
95254 
95255 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */
95256 #define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_LSB 8
95257 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */
95258 #define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_MSB 8
95259 /* The width in bits of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */
95260 #define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_WIDTH 1
95261 /* The mask used to set the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field value. */
95262 #define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_SET_MSK 0x00000100
95263 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field value. */
95264 #define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_CLR_MSK 0xfffffeff
95265 /* The reset value of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */
95266 #define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_RESET 0x0
95267 /* Extracts the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN field value from a register. */
95268 #define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
95269 /* Produces a ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field value suitable for setting the register. */
95270 #define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
95271 
95272 /*
95273  * Field : bnaintr
95274  *
95275  * BNA (Buffer Not Available) Interrupt (BNAIntr)
95276  *
95277  * This bit is valid only when Scatter/Gather DMA mode is enabled.
95278  *
95279  * The core generates this interrupt when the descriptor accessed
95280  *
95281  * is not ready For the Core to process, such as Host busy or DMA
95282  *
95283  * done
95284  *
95285  * Field Enumeration Values:
95286  *
95287  * Enum | Value | Description
95288  * :--------------------------------------|:------|:--------------
95289  * ALT_USB_DEV_DIEPINT11_BNAINTR_E_INACT | 0x0 | No interrupt
95290  * ALT_USB_DEV_DIEPINT11_BNAINTR_E_ACT | 0x1 | BNA interrupt
95291  *
95292  * Field Access Macros:
95293  *
95294  */
95295 /*
95296  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_BNAINTR
95297  *
95298  * No interrupt
95299  */
95300 #define ALT_USB_DEV_DIEPINT11_BNAINTR_E_INACT 0x0
95301 /*
95302  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_BNAINTR
95303  *
95304  * BNA interrupt
95305  */
95306 #define ALT_USB_DEV_DIEPINT11_BNAINTR_E_ACT 0x1
95307 
95308 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */
95309 #define ALT_USB_DEV_DIEPINT11_BNAINTR_LSB 9
95310 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */
95311 #define ALT_USB_DEV_DIEPINT11_BNAINTR_MSB 9
95312 /* The width in bits of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */
95313 #define ALT_USB_DEV_DIEPINT11_BNAINTR_WIDTH 1
95314 /* The mask used to set the ALT_USB_DEV_DIEPINT11_BNAINTR register field value. */
95315 #define ALT_USB_DEV_DIEPINT11_BNAINTR_SET_MSK 0x00000200
95316 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_BNAINTR register field value. */
95317 #define ALT_USB_DEV_DIEPINT11_BNAINTR_CLR_MSK 0xfffffdff
95318 /* The reset value of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */
95319 #define ALT_USB_DEV_DIEPINT11_BNAINTR_RESET 0x0
95320 /* Extracts the ALT_USB_DEV_DIEPINT11_BNAINTR field value from a register. */
95321 #define ALT_USB_DEV_DIEPINT11_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
95322 /* Produces a ALT_USB_DEV_DIEPINT11_BNAINTR register field value suitable for setting the register. */
95323 #define ALT_USB_DEV_DIEPINT11_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
95324 
95325 /*
95326  * Field : pktdrpsts
95327  *
95328  * Packet Drop Status (PktDrpSts)
95329  *
95330  * This bit indicates to the application that an ISOC OUT packet has been dropped.
95331  * This
95332  *
95333  * bit does not have an associated mask bit and does not generate an interrupt.
95334  *
95335  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
95336  * transfer
95337  *
95338  * interrupt feature is selected.
95339  *
95340  * Field Enumeration Values:
95341  *
95342  * Enum | Value | Description
95343  * :----------------------------------------|:------|:-----------------------------
95344  * ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_INACT | 0x0 | No interrupt
95345  * ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
95346  *
95347  * Field Access Macros:
95348  *
95349  */
95350 /*
95351  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_PKTDRPSTS
95352  *
95353  * No interrupt
95354  */
95355 #define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_INACT 0x0
95356 /*
95357  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_PKTDRPSTS
95358  *
95359  * Packet Drop Status interrupt
95360  */
95361 #define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_ACT 0x1
95362 
95363 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */
95364 #define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_LSB 11
95365 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */
95366 #define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_MSB 11
95367 /* The width in bits of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */
95368 #define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_WIDTH 1
95369 /* The mask used to set the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field value. */
95370 #define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_SET_MSK 0x00000800
95371 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field value. */
95372 #define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_CLR_MSK 0xfffff7ff
95373 /* The reset value of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */
95374 #define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_RESET 0x0
95375 /* Extracts the ALT_USB_DEV_DIEPINT11_PKTDRPSTS field value from a register. */
95376 #define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
95377 /* Produces a ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field value suitable for setting the register. */
95378 #define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
95379 
95380 /*
95381  * Field : bbleerr
95382  *
95383  * NAK Interrupt (BbleErr)
95384  *
95385  * The core generates this interrupt when babble is received for the endpoint.
95386  *
95387  * Field Enumeration Values:
95388  *
95389  * Enum | Value | Description
95390  * :--------------------------------------|:------|:------------------
95391  * ALT_USB_DEV_DIEPINT11_BBLEERR_E_INACT | 0x0 | No interrupt
95392  * ALT_USB_DEV_DIEPINT11_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
95393  *
95394  * Field Access Macros:
95395  *
95396  */
95397 /*
95398  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_BBLEERR
95399  *
95400  * No interrupt
95401  */
95402 #define ALT_USB_DEV_DIEPINT11_BBLEERR_E_INACT 0x0
95403 /*
95404  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_BBLEERR
95405  *
95406  * BbleErr interrupt
95407  */
95408 #define ALT_USB_DEV_DIEPINT11_BBLEERR_E_ACT 0x1
95409 
95410 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */
95411 #define ALT_USB_DEV_DIEPINT11_BBLEERR_LSB 12
95412 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */
95413 #define ALT_USB_DEV_DIEPINT11_BBLEERR_MSB 12
95414 /* The width in bits of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */
95415 #define ALT_USB_DEV_DIEPINT11_BBLEERR_WIDTH 1
95416 /* The mask used to set the ALT_USB_DEV_DIEPINT11_BBLEERR register field value. */
95417 #define ALT_USB_DEV_DIEPINT11_BBLEERR_SET_MSK 0x00001000
95418 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_BBLEERR register field value. */
95419 #define ALT_USB_DEV_DIEPINT11_BBLEERR_CLR_MSK 0xffffefff
95420 /* The reset value of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */
95421 #define ALT_USB_DEV_DIEPINT11_BBLEERR_RESET 0x0
95422 /* Extracts the ALT_USB_DEV_DIEPINT11_BBLEERR field value from a register. */
95423 #define ALT_USB_DEV_DIEPINT11_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
95424 /* Produces a ALT_USB_DEV_DIEPINT11_BBLEERR register field value suitable for setting the register. */
95425 #define ALT_USB_DEV_DIEPINT11_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
95426 
95427 /*
95428  * Field : nakintrpt
95429  *
95430  * NAK Interrupt (NAKInterrupt)
95431  *
95432  * The core generates this interrupt when a NAK is transmitted or received by the
95433  * device.
95434  *
95435  * In case of isochronous IN endpoints the interrupt gets generated when a zero
95436  * length
95437  *
95438  * packet is transmitted due to un-availability of data in the TXFifo.
95439  *
95440  * Field Enumeration Values:
95441  *
95442  * Enum | Value | Description
95443  * :----------------------------------------|:------|:--------------
95444  * ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_INACT | 0x0 | No interrupt
95445  * ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
95446  *
95447  * Field Access Macros:
95448  *
95449  */
95450 /*
95451  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_NAKINTRPT
95452  *
95453  * No interrupt
95454  */
95455 #define ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_INACT 0x0
95456 /*
95457  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_NAKINTRPT
95458  *
95459  * NAK Interrupt
95460  */
95461 #define ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_ACT 0x1
95462 
95463 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */
95464 #define ALT_USB_DEV_DIEPINT11_NAKINTRPT_LSB 13
95465 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */
95466 #define ALT_USB_DEV_DIEPINT11_NAKINTRPT_MSB 13
95467 /* The width in bits of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */
95468 #define ALT_USB_DEV_DIEPINT11_NAKINTRPT_WIDTH 1
95469 /* The mask used to set the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field value. */
95470 #define ALT_USB_DEV_DIEPINT11_NAKINTRPT_SET_MSK 0x00002000
95471 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field value. */
95472 #define ALT_USB_DEV_DIEPINT11_NAKINTRPT_CLR_MSK 0xffffdfff
95473 /* The reset value of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */
95474 #define ALT_USB_DEV_DIEPINT11_NAKINTRPT_RESET 0x0
95475 /* Extracts the ALT_USB_DEV_DIEPINT11_NAKINTRPT field value from a register. */
95476 #define ALT_USB_DEV_DIEPINT11_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
95477 /* Produces a ALT_USB_DEV_DIEPINT11_NAKINTRPT register field value suitable for setting the register. */
95478 #define ALT_USB_DEV_DIEPINT11_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
95479 
95480 /*
95481  * Field : nyetintrpt
95482  *
95483  * NYET Interrupt (NYETIntrpt)
95484  *
95485  * The core generates this interrupt when a NYET response is transmitted for a non
95486  * isochronous OUT endpoint.
95487  *
95488  * Field Enumeration Values:
95489  *
95490  * Enum | Value | Description
95491  * :-----------------------------------------|:------|:---------------
95492  * ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_INACT | 0x0 | No interrupt
95493  * ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
95494  *
95495  * Field Access Macros:
95496  *
95497  */
95498 /*
95499  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_NYETINTRPT
95500  *
95501  * No interrupt
95502  */
95503 #define ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_INACT 0x0
95504 /*
95505  * Enumerated value for register field ALT_USB_DEV_DIEPINT11_NYETINTRPT
95506  *
95507  * NYET Interrupt
95508  */
95509 #define ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_ACT 0x1
95510 
95511 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */
95512 #define ALT_USB_DEV_DIEPINT11_NYETINTRPT_LSB 14
95513 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */
95514 #define ALT_USB_DEV_DIEPINT11_NYETINTRPT_MSB 14
95515 /* The width in bits of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */
95516 #define ALT_USB_DEV_DIEPINT11_NYETINTRPT_WIDTH 1
95517 /* The mask used to set the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field value. */
95518 #define ALT_USB_DEV_DIEPINT11_NYETINTRPT_SET_MSK 0x00004000
95519 /* The mask used to clear the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field value. */
95520 #define ALT_USB_DEV_DIEPINT11_NYETINTRPT_CLR_MSK 0xffffbfff
95521 /* The reset value of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */
95522 #define ALT_USB_DEV_DIEPINT11_NYETINTRPT_RESET 0x0
95523 /* Extracts the ALT_USB_DEV_DIEPINT11_NYETINTRPT field value from a register. */
95524 #define ALT_USB_DEV_DIEPINT11_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
95525 /* Produces a ALT_USB_DEV_DIEPINT11_NYETINTRPT register field value suitable for setting the register. */
95526 #define ALT_USB_DEV_DIEPINT11_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
95527 
95528 #ifndef __ASSEMBLY__
95529 /*
95530  * WARNING: The C register and register group struct declarations are provided for
95531  * convenience and illustrative purposes. They should, however, be used with
95532  * caution as the C language standard provides no guarantees about the alignment or
95533  * atomicity of device memory accesses. The recommended practice for writing
95534  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
95535  * alt_write_word() functions.
95536  *
95537  * The struct declaration for register ALT_USB_DEV_DIEPINT11.
95538  */
95539 struct ALT_USB_DEV_DIEPINT11_s
95540 {
95541  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT11_XFERCOMPL */
95542  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT11_EPDISBLD */
95543  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT11_AHBERR */
95544  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT11_TMO */
95545  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT11_INTKNTXFEMP */
95546  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT11_INTKNEPMIS */
95547  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT11_INEPNAKEFF */
95548  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT11_TXFEMP */
95549  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN */
95550  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT11_BNAINTR */
95551  uint32_t : 1; /* *UNDEFINED* */
95552  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT11_PKTDRPSTS */
95553  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT11_BBLEERR */
95554  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT11_NAKINTRPT */
95555  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT11_NYETINTRPT */
95556  uint32_t : 17; /* *UNDEFINED* */
95557 };
95558 
95559 /* The typedef declaration for register ALT_USB_DEV_DIEPINT11. */
95560 typedef volatile struct ALT_USB_DEV_DIEPINT11_s ALT_USB_DEV_DIEPINT11_t;
95561 #endif /* __ASSEMBLY__ */
95562 
95563 /* The reset value of the ALT_USB_DEV_DIEPINT11 register. */
95564 #define ALT_USB_DEV_DIEPINT11_RESET 0x00000080
95565 /* The byte offset of the ALT_USB_DEV_DIEPINT11 register from the beginning of the component. */
95566 #define ALT_USB_DEV_DIEPINT11_OFST 0x268
95567 /* The address of the ALT_USB_DEV_DIEPINT11 register. */
95568 #define ALT_USB_DEV_DIEPINT11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT11_OFST))
95569 
95570 /*
95571  * Register : dieptsiz11
95572  *
95573  * Device IN Endpoint 11 Transfer Size Register
95574  *
95575  * Register Layout
95576  *
95577  * Bits | Access | Reset | Description
95578  * :--------|:-------|:------|:--------------------------------
95579  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ11_XFERSIZE
95580  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ11_PKTCNT
95581  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ11_MC
95582  * [31] | ??? | 0x0 | *UNDEFINED*
95583  *
95584  */
95585 /*
95586  * Field : xfersize
95587  *
95588  * Transfer Size (XferSize)
95589  *
95590  * Indicates the transfer size in bytes For endpoint 0. The core
95591  *
95592  * interrupts the application only after it has exhausted the transfer
95593  *
95594  * size amount of data. The transfer size can be Set to the
95595  *
95596  * maximum packet size of the endpoint, to be interrupted at the
95597  *
95598  * end of each packet.
95599  *
95600  * The core decrements this field every time a packet from the
95601  *
95602  * external memory is written to the TxFIFO.
95603  *
95604  * Field Access Macros:
95605  *
95606  */
95607 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */
95608 #define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_LSB 0
95609 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */
95610 #define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_MSB 18
95611 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */
95612 #define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_WIDTH 19
95613 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field value. */
95614 #define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_SET_MSK 0x0007ffff
95615 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field value. */
95616 #define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_CLR_MSK 0xfff80000
95617 /* The reset value of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */
95618 #define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_RESET 0x0
95619 /* Extracts the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE field value from a register. */
95620 #define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
95621 /* Produces a ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field value suitable for setting the register. */
95622 #define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
95623 
95624 /*
95625  * Field : pktcnt
95626  *
95627  * Packet Count (PktCnt)
95628  *
95629  * Indicates the total number of USB packets that constitute the
95630  *
95631  * Transfer Size amount of data For endpoint 0.
95632  *
95633  * This field is decremented every time a packet (maximum size or
95634  *
95635  * short packet) is read from the TxFIFO.
95636  *
95637  * Field Access Macros:
95638  *
95639  */
95640 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */
95641 #define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_LSB 19
95642 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */
95643 #define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_MSB 28
95644 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */
95645 #define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_WIDTH 10
95646 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field value. */
95647 #define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_SET_MSK 0x1ff80000
95648 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field value. */
95649 #define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_CLR_MSK 0xe007ffff
95650 /* The reset value of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */
95651 #define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_RESET 0x0
95652 /* Extracts the ALT_USB_DEV_DIEPTSIZ11_PKTCNT field value from a register. */
95653 #define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
95654 /* Produces a ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field value suitable for setting the register. */
95655 #define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
95656 
95657 /*
95658  * Field : mc
95659  *
95660  * Applies to IN endpoints only.
95661  *
95662  * For periodic IN endpoints, this field indicates the number of packets that must
95663  * be transmitted per microframe on the USB. The core uses this field to calculate
95664  * the data PID for isochronous IN endpoints.
95665  *
95666  * 2'b01: 1 packet
95667  *
95668  * 2'b10: 2 packets
95669  *
95670  * 2'b11: 3 packets
95671  *
95672  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
95673  * specifies the number of packets the core must fetchfor an IN endpoint before it
95674  * switches to the endpoint pointed to by the Next Endpoint field of the Device
95675  * Endpoint-n Control register (DIEPCTLn.NextEp)
95676  *
95677  * Field Enumeration Values:
95678  *
95679  * Enum | Value | Description
95680  * :-------------------------------------|:------|:------------
95681  * ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTONE | 0x1 | 1 packet
95682  * ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTWO | 0x2 | 2 packets
95683  * ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTHREE | 0x3 | 3 packets
95684  *
95685  * Field Access Macros:
95686  *
95687  */
95688 /*
95689  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ11_MC
95690  *
95691  * 1 packet
95692  */
95693 #define ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTONE 0x1
95694 /*
95695  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ11_MC
95696  *
95697  * 2 packets
95698  */
95699 #define ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTWO 0x2
95700 /*
95701  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ11_MC
95702  *
95703  * 3 packets
95704  */
95705 #define ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTHREE 0x3
95706 
95707 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */
95708 #define ALT_USB_DEV_DIEPTSIZ11_MC_LSB 29
95709 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */
95710 #define ALT_USB_DEV_DIEPTSIZ11_MC_MSB 30
95711 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */
95712 #define ALT_USB_DEV_DIEPTSIZ11_MC_WIDTH 2
95713 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ11_MC register field value. */
95714 #define ALT_USB_DEV_DIEPTSIZ11_MC_SET_MSK 0x60000000
95715 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ11_MC register field value. */
95716 #define ALT_USB_DEV_DIEPTSIZ11_MC_CLR_MSK 0x9fffffff
95717 /* The reset value of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */
95718 #define ALT_USB_DEV_DIEPTSIZ11_MC_RESET 0x0
95719 /* Extracts the ALT_USB_DEV_DIEPTSIZ11_MC field value from a register. */
95720 #define ALT_USB_DEV_DIEPTSIZ11_MC_GET(value) (((value) & 0x60000000) >> 29)
95721 /* Produces a ALT_USB_DEV_DIEPTSIZ11_MC register field value suitable for setting the register. */
95722 #define ALT_USB_DEV_DIEPTSIZ11_MC_SET(value) (((value) << 29) & 0x60000000)
95723 
95724 #ifndef __ASSEMBLY__
95725 /*
95726  * WARNING: The C register and register group struct declarations are provided for
95727  * convenience and illustrative purposes. They should, however, be used with
95728  * caution as the C language standard provides no guarantees about the alignment or
95729  * atomicity of device memory accesses. The recommended practice for writing
95730  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
95731  * alt_write_word() functions.
95732  *
95733  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ11.
95734  */
95735 struct ALT_USB_DEV_DIEPTSIZ11_s
95736 {
95737  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ11_XFERSIZE */
95738  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ11_PKTCNT */
95739  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ11_MC */
95740  uint32_t : 1; /* *UNDEFINED* */
95741 };
95742 
95743 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ11. */
95744 typedef volatile struct ALT_USB_DEV_DIEPTSIZ11_s ALT_USB_DEV_DIEPTSIZ11_t;
95745 #endif /* __ASSEMBLY__ */
95746 
95747 /* The reset value of the ALT_USB_DEV_DIEPTSIZ11 register. */
95748 #define ALT_USB_DEV_DIEPTSIZ11_RESET 0x00000000
95749 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ11 register from the beginning of the component. */
95750 #define ALT_USB_DEV_DIEPTSIZ11_OFST 0x270
95751 /* The address of the ALT_USB_DEV_DIEPTSIZ11 register. */
95752 #define ALT_USB_DEV_DIEPTSIZ11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ11_OFST))
95753 
95754 /*
95755  * Register : diepdma11
95756  *
95757  * Device IN Endpoint 11 DMA Address Register
95758  *
95759  * Register Layout
95760  *
95761  * Bits | Access | Reset | Description
95762  * :-------|:-------|:--------|:--------------------------------
95763  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA11_DIEPDMA11
95764  *
95765  */
95766 /*
95767  * Field : diepdma11
95768  *
95769  * Holds the start address of the external memory for storing or fetching endpoint
95770  *
95771  * data.
95772  *
95773  * Note: For control endpoints, this field stores control OUT data packets as well
95774  * as
95775  *
95776  * SETUP transaction data packets. When more than three SETUP packets are
95777  *
95778  * received back-to-back, the SETUP data packet in the memory is overwritten.
95779  *
95780  * This register is incremented on every AHB transaction. The application can give
95781  *
95782  * only a DWORD-aligned address.
95783  *
95784  * When Scatter/Gather DMA mode is not enabled, the application programs the
95785  *
95786  * start address value in this field.
95787  *
95788  * When Scatter/Gather DMA mode is enabled, this field indicates the base
95789  *
95790  * pointer for the descriptor list.
95791  *
95792  * Field Access Macros:
95793  *
95794  */
95795 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field. */
95796 #define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_LSB 0
95797 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field. */
95798 #define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_MSB 31
95799 /* The width in bits of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field. */
95800 #define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_WIDTH 32
95801 /* The mask used to set the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field value. */
95802 #define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_SET_MSK 0xffffffff
95803 /* The mask used to clear the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field value. */
95804 #define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_CLR_MSK 0x00000000
95805 /* The reset value of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field is UNKNOWN. */
95806 #define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_RESET 0x0
95807 /* Extracts the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 field value from a register. */
95808 #define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_GET(value) (((value) & 0xffffffff) >> 0)
95809 /* Produces a ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field value suitable for setting the register. */
95810 #define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_SET(value) (((value) << 0) & 0xffffffff)
95811 
95812 #ifndef __ASSEMBLY__
95813 /*
95814  * WARNING: The C register and register group struct declarations are provided for
95815  * convenience and illustrative purposes. They should, however, be used with
95816  * caution as the C language standard provides no guarantees about the alignment or
95817  * atomicity of device memory accesses. The recommended practice for writing
95818  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
95819  * alt_write_word() functions.
95820  *
95821  * The struct declaration for register ALT_USB_DEV_DIEPDMA11.
95822  */
95823 struct ALT_USB_DEV_DIEPDMA11_s
95824 {
95825  uint32_t diepdma11 : 32; /* ALT_USB_DEV_DIEPDMA11_DIEPDMA11 */
95826 };
95827 
95828 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA11. */
95829 typedef volatile struct ALT_USB_DEV_DIEPDMA11_s ALT_USB_DEV_DIEPDMA11_t;
95830 #endif /* __ASSEMBLY__ */
95831 
95832 /* The reset value of the ALT_USB_DEV_DIEPDMA11 register. */
95833 #define ALT_USB_DEV_DIEPDMA11_RESET 0x00000000
95834 /* The byte offset of the ALT_USB_DEV_DIEPDMA11 register from the beginning of the component. */
95835 #define ALT_USB_DEV_DIEPDMA11_OFST 0x274
95836 /* The address of the ALT_USB_DEV_DIEPDMA11 register. */
95837 #define ALT_USB_DEV_DIEPDMA11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA11_OFST))
95838 
95839 /*
95840  * Register : dtxfsts11
95841  *
95842  * Device IN Endpoint Transmit FIFO Status Register 11
95843  *
95844  * Register Layout
95845  *
95846  * Bits | Access | Reset | Description
95847  * :--------|:-------|:-------|:--------------------------------------
95848  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL
95849  * [31:16] | ??? | 0x0 | *UNDEFINED*
95850  *
95851  */
95852 /*
95853  * Field : ineptxfspcavail
95854  *
95855  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
95856  *
95857  * Indicates the amount of free space available in the Endpoint
95858  *
95859  * TxFIFO.
95860  *
95861  * Values are in terms of 32-bit words.
95862  *
95863  * 16'h0: Endpoint TxFIFO is full
95864  *
95865  * 16'h1: 1 word available
95866  *
95867  * 16'h2: 2 words available
95868  *
95869  * 16'hn: n words available (where 0 n 32,768)
95870  *
95871  * 16'h8000: 32,768 words available
95872  *
95873  * Others: Reserved
95874  *
95875  * Field Access Macros:
95876  *
95877  */
95878 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */
95879 #define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_LSB 0
95880 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */
95881 #define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_MSB 15
95882 /* The width in bits of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */
95883 #define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_WIDTH 16
95884 /* The mask used to set the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field value. */
95885 #define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
95886 /* The mask used to clear the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field value. */
95887 #define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
95888 /* The reset value of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */
95889 #define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_RESET 0x2000
95890 /* Extracts the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL field value from a register. */
95891 #define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
95892 /* Produces a ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field value suitable for setting the register. */
95893 #define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
95894 
95895 #ifndef __ASSEMBLY__
95896 /*
95897  * WARNING: The C register and register group struct declarations are provided for
95898  * convenience and illustrative purposes. They should, however, be used with
95899  * caution as the C language standard provides no guarantees about the alignment or
95900  * atomicity of device memory accesses. The recommended practice for writing
95901  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
95902  * alt_write_word() functions.
95903  *
95904  * The struct declaration for register ALT_USB_DEV_DTXFSTS11.
95905  */
95906 struct ALT_USB_DEV_DTXFSTS11_s
95907 {
95908  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL */
95909  uint32_t : 16; /* *UNDEFINED* */
95910 };
95911 
95912 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS11. */
95913 typedef volatile struct ALT_USB_DEV_DTXFSTS11_s ALT_USB_DEV_DTXFSTS11_t;
95914 #endif /* __ASSEMBLY__ */
95915 
95916 /* The reset value of the ALT_USB_DEV_DTXFSTS11 register. */
95917 #define ALT_USB_DEV_DTXFSTS11_RESET 0x00002000
95918 /* The byte offset of the ALT_USB_DEV_DTXFSTS11 register from the beginning of the component. */
95919 #define ALT_USB_DEV_DTXFSTS11_OFST 0x278
95920 /* The address of the ALT_USB_DEV_DTXFSTS11 register. */
95921 #define ALT_USB_DEV_DTXFSTS11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS11_OFST))
95922 
95923 /*
95924  * Register : diepdmab11
95925  *
95926  * Device IN Endpoint 11 Buffer Address Register
95927  *
95928  * Register Layout
95929  *
95930  * Bits | Access | Reset | Description
95931  * :-------|:-------|:--------|:----------------------------------
95932  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11
95933  *
95934  */
95935 /*
95936  * Field : diepdmab11
95937  *
95938  * Holds the current buffer address.This register is updated as and when the data
95939  *
95940  * transfer for the corresponding end point is in progress.
95941  *
95942  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
95943  * is
95944  *
95945  * reserved.
95946  *
95947  * Field Access Macros:
95948  *
95949  */
95950 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field. */
95951 #define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_LSB 0
95952 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field. */
95953 #define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_MSB 31
95954 /* The width in bits of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field. */
95955 #define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_WIDTH 32
95956 /* The mask used to set the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field value. */
95957 #define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_SET_MSK 0xffffffff
95958 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field value. */
95959 #define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_CLR_MSK 0x00000000
95960 /* The reset value of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field is UNKNOWN. */
95961 #define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_RESET 0x0
95962 /* Extracts the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 field value from a register. */
95963 #define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_GET(value) (((value) & 0xffffffff) >> 0)
95964 /* Produces a ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field value suitable for setting the register. */
95965 #define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_SET(value) (((value) << 0) & 0xffffffff)
95966 
95967 #ifndef __ASSEMBLY__
95968 /*
95969  * WARNING: The C register and register group struct declarations are provided for
95970  * convenience and illustrative purposes. They should, however, be used with
95971  * caution as the C language standard provides no guarantees about the alignment or
95972  * atomicity of device memory accesses. The recommended practice for writing
95973  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
95974  * alt_write_word() functions.
95975  *
95976  * The struct declaration for register ALT_USB_DEV_DIEPDMAB11.
95977  */
95978 struct ALT_USB_DEV_DIEPDMAB11_s
95979 {
95980  const uint32_t diepdmab11 : 32; /* ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 */
95981 };
95982 
95983 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB11. */
95984 typedef volatile struct ALT_USB_DEV_DIEPDMAB11_s ALT_USB_DEV_DIEPDMAB11_t;
95985 #endif /* __ASSEMBLY__ */
95986 
95987 /* The reset value of the ALT_USB_DEV_DIEPDMAB11 register. */
95988 #define ALT_USB_DEV_DIEPDMAB11_RESET 0x00000000
95989 /* The byte offset of the ALT_USB_DEV_DIEPDMAB11 register from the beginning of the component. */
95990 #define ALT_USB_DEV_DIEPDMAB11_OFST 0x27c
95991 /* The address of the ALT_USB_DEV_DIEPDMAB11 register. */
95992 #define ALT_USB_DEV_DIEPDMAB11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB11_OFST))
95993 
95994 /*
95995  * Register : diepctl12
95996  *
95997  * Device Control IN Endpoint 12 Control Register
95998  *
95999  * Register Layout
96000  *
96001  * Bits | Access | Reset | Description
96002  * :--------|:---------|:------|:-------------------------------
96003  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL12_MPS
96004  * [14:11] | ??? | 0x0 | *UNDEFINED*
96005  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL12_USBACTEP
96006  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL12_DPID
96007  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL12_NAKSTS
96008  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL12_EPTYPE
96009  * [20] | ??? | 0x0 | *UNDEFINED*
96010  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL12_STALL
96011  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL12_TXFNUM
96012  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL12_CNAK
96013  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL12_SNAK
96014  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL12_SETD0PID
96015  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL12_SETD1PID
96016  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL12_EPDIS
96017  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL12_EPENA
96018  *
96019  */
96020 /*
96021  * Field : mps
96022  *
96023  * Maximum Packet Size (MPS)
96024  *
96025  * The application must program this field with the maximum packet size for the
96026  * current
96027  *
96028  * logical endpoint. This value is in bytes.
96029  *
96030  * Field Access Macros:
96031  *
96032  */
96033 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_MPS register field. */
96034 #define ALT_USB_DEV_DIEPCTL12_MPS_LSB 0
96035 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_MPS register field. */
96036 #define ALT_USB_DEV_DIEPCTL12_MPS_MSB 10
96037 /* The width in bits of the ALT_USB_DEV_DIEPCTL12_MPS register field. */
96038 #define ALT_USB_DEV_DIEPCTL12_MPS_WIDTH 11
96039 /* The mask used to set the ALT_USB_DEV_DIEPCTL12_MPS register field value. */
96040 #define ALT_USB_DEV_DIEPCTL12_MPS_SET_MSK 0x000007ff
96041 /* The mask used to clear the ALT_USB_DEV_DIEPCTL12_MPS register field value. */
96042 #define ALT_USB_DEV_DIEPCTL12_MPS_CLR_MSK 0xfffff800
96043 /* The reset value of the ALT_USB_DEV_DIEPCTL12_MPS register field. */
96044 #define ALT_USB_DEV_DIEPCTL12_MPS_RESET 0x0
96045 /* Extracts the ALT_USB_DEV_DIEPCTL12_MPS field value from a register. */
96046 #define ALT_USB_DEV_DIEPCTL12_MPS_GET(value) (((value) & 0x000007ff) >> 0)
96047 /* Produces a ALT_USB_DEV_DIEPCTL12_MPS register field value suitable for setting the register. */
96048 #define ALT_USB_DEV_DIEPCTL12_MPS_SET(value) (((value) << 0) & 0x000007ff)
96049 
96050 /*
96051  * Field : usbactep
96052  *
96053  * USB Active Endpoint (USBActEP)
96054  *
96055  * Indicates whether this endpoint is active in the current configuration and
96056  * interface. The
96057  *
96058  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
96059  * reset. After
96060  *
96061  * receiving the SetConfiguration and SetInterface commands, the application must
96062  *
96063  * program endpoint registers accordingly and set this bit.
96064  *
96065  * Field Enumeration Values:
96066  *
96067  * Enum | Value | Description
96068  * :--------------------------------------|:------|:--------------------
96069  * ALT_USB_DEV_DIEPCTL12_USBACTEP_E_DISD | 0x0 | Not Active
96070  * ALT_USB_DEV_DIEPCTL12_USBACTEP_E_END | 0x1 | USB Active Endpoint
96071  *
96072  * Field Access Macros:
96073  *
96074  */
96075 /*
96076  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_USBACTEP
96077  *
96078  * Not Active
96079  */
96080 #define ALT_USB_DEV_DIEPCTL12_USBACTEP_E_DISD 0x0
96081 /*
96082  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_USBACTEP
96083  *
96084  * USB Active Endpoint
96085  */
96086 #define ALT_USB_DEV_DIEPCTL12_USBACTEP_E_END 0x1
96087 
96088 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */
96089 #define ALT_USB_DEV_DIEPCTL12_USBACTEP_LSB 15
96090 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */
96091 #define ALT_USB_DEV_DIEPCTL12_USBACTEP_MSB 15
96092 /* The width in bits of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */
96093 #define ALT_USB_DEV_DIEPCTL12_USBACTEP_WIDTH 1
96094 /* The mask used to set the ALT_USB_DEV_DIEPCTL12_USBACTEP register field value. */
96095 #define ALT_USB_DEV_DIEPCTL12_USBACTEP_SET_MSK 0x00008000
96096 /* The mask used to clear the ALT_USB_DEV_DIEPCTL12_USBACTEP register field value. */
96097 #define ALT_USB_DEV_DIEPCTL12_USBACTEP_CLR_MSK 0xffff7fff
96098 /* The reset value of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */
96099 #define ALT_USB_DEV_DIEPCTL12_USBACTEP_RESET 0x0
96100 /* Extracts the ALT_USB_DEV_DIEPCTL12_USBACTEP field value from a register. */
96101 #define ALT_USB_DEV_DIEPCTL12_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
96102 /* Produces a ALT_USB_DEV_DIEPCTL12_USBACTEP register field value suitable for setting the register. */
96103 #define ALT_USB_DEV_DIEPCTL12_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
96104 
96105 /*
96106  * Field : dpid
96107  *
96108  * Endpoint Data PID (DPID)
96109  *
96110  * Applies to interrupt/bulk IN and OUT endpoints only.
96111  *
96112  * Contains the PID of the packet to be received or transmitted on this endpoint.
96113  * The
96114  *
96115  * application must program the PID of the first packet to be received or
96116  * transmitted on
96117  *
96118  * this endpoint, after the endpoint is activated. The applications use the
96119  * SetD1PID and
96120  *
96121  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
96122  *
96123  * 1'b0: DATA0
96124  *
96125  * 1'b1: DATA1
96126  *
96127  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
96128  *
96129  * DMA mode.
96130  *
96131  * 1'b0 RO
96132  *
96133  * Even/Odd (Micro)Frame (EO_FrNum)
96134  *
96135  * In non-Scatter/Gather DMA mode:
96136  *
96137  * Applies to isochronous IN and OUT endpoints only.
96138  *
96139  * Indicates the (micro)frame number in which the core transmits/receives
96140  * isochronous
96141  *
96142  * data for this endpoint. The application must program the even/odd (micro) frame
96143  *
96144  * number in which it intends to transmit/receive isochronous data for this
96145  * endpoint using
96146  *
96147  * the SetEvnFr and SetOddFr fields in this register.
96148  *
96149  * 1'b0: Even (micro)frame
96150  *
96151  * 1'b1: Odd (micro)frame
96152  *
96153  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
96154  * number
96155  *
96156  * in which to send data is provided in the transmit descriptor structure. The
96157  * frame in
96158  *
96159  * which data is received is updated in receive descriptor structure.
96160  *
96161  * Field Enumeration Values:
96162  *
96163  * Enum | Value | Description
96164  * :-----------------------------------|:------|:-----------------------------
96165  * ALT_USB_DEV_DIEPCTL12_DPID_E_INACT | 0x0 | Endpoint Data PID not active
96166  * ALT_USB_DEV_DIEPCTL12_DPID_E_ACT | 0x1 | Endpoint Data PID active
96167  *
96168  * Field Access Macros:
96169  *
96170  */
96171 /*
96172  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_DPID
96173  *
96174  * Endpoint Data PID not active
96175  */
96176 #define ALT_USB_DEV_DIEPCTL12_DPID_E_INACT 0x0
96177 /*
96178  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_DPID
96179  *
96180  * Endpoint Data PID active
96181  */
96182 #define ALT_USB_DEV_DIEPCTL12_DPID_E_ACT 0x1
96183 
96184 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_DPID register field. */
96185 #define ALT_USB_DEV_DIEPCTL12_DPID_LSB 16
96186 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_DPID register field. */
96187 #define ALT_USB_DEV_DIEPCTL12_DPID_MSB 16
96188 /* The width in bits of the ALT_USB_DEV_DIEPCTL12_DPID register field. */
96189 #define ALT_USB_DEV_DIEPCTL12_DPID_WIDTH 1
96190 /* The mask used to set the ALT_USB_DEV_DIEPCTL12_DPID register field value. */
96191 #define ALT_USB_DEV_DIEPCTL12_DPID_SET_MSK 0x00010000
96192 /* The mask used to clear the ALT_USB_DEV_DIEPCTL12_DPID register field value. */
96193 #define ALT_USB_DEV_DIEPCTL12_DPID_CLR_MSK 0xfffeffff
96194 /* The reset value of the ALT_USB_DEV_DIEPCTL12_DPID register field. */
96195 #define ALT_USB_DEV_DIEPCTL12_DPID_RESET 0x0
96196 /* Extracts the ALT_USB_DEV_DIEPCTL12_DPID field value from a register. */
96197 #define ALT_USB_DEV_DIEPCTL12_DPID_GET(value) (((value) & 0x00010000) >> 16)
96198 /* Produces a ALT_USB_DEV_DIEPCTL12_DPID register field value suitable for setting the register. */
96199 #define ALT_USB_DEV_DIEPCTL12_DPID_SET(value) (((value) << 16) & 0x00010000)
96200 
96201 /*
96202  * Field : naksts
96203  *
96204  * NAK Status (NAKSts)
96205  *
96206  * Indicates the following:
96207  *
96208  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
96209  *
96210  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
96211  *
96212  * When either the application or the core sets this bit:
96213  *
96214  * The core stops receiving any data on an OUT endpoint, even if there is space in
96215  *
96216  * the RxFIFO to accommodate the incoming packet.
96217  *
96218  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
96219  *
96220  * endpoint, even if there data is available in the TxFIFO.
96221  *
96222  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
96223  *
96224  * if there data is available in the TxFIFO.
96225  *
96226  * Irrespective of this bit's setting, the core always responds to SETUP data
96227  * packets with
96228  *
96229  * an ACK handshake.
96230  *
96231  * Field Enumeration Values:
96232  *
96233  * Enum | Value | Description
96234  * :--------------------------------------|:------|:------------------------------------------------
96235  * ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
96236  * : | | based on the FIFO status
96237  * ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
96238  * : | | endpoint
96239  *
96240  * Field Access Macros:
96241  *
96242  */
96243 /*
96244  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_NAKSTS
96245  *
96246  * The core is transmitting non-NAK handshakes based on the FIFO status
96247  */
96248 #define ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NONNAK 0x0
96249 /*
96250  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_NAKSTS
96251  *
96252  * The core is transmitting NAK handshakes on this endpoint
96253  */
96254 #define ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NAK 0x1
96255 
96256 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */
96257 #define ALT_USB_DEV_DIEPCTL12_NAKSTS_LSB 17
96258 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */
96259 #define ALT_USB_DEV_DIEPCTL12_NAKSTS_MSB 17
96260 /* The width in bits of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */
96261 #define ALT_USB_DEV_DIEPCTL12_NAKSTS_WIDTH 1
96262 /* The mask used to set the ALT_USB_DEV_DIEPCTL12_NAKSTS register field value. */
96263 #define ALT_USB_DEV_DIEPCTL12_NAKSTS_SET_MSK 0x00020000
96264 /* The mask used to clear the ALT_USB_DEV_DIEPCTL12_NAKSTS register field value. */
96265 #define ALT_USB_DEV_DIEPCTL12_NAKSTS_CLR_MSK 0xfffdffff
96266 /* The reset value of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */
96267 #define ALT_USB_DEV_DIEPCTL12_NAKSTS_RESET 0x0
96268 /* Extracts the ALT_USB_DEV_DIEPCTL12_NAKSTS field value from a register. */
96269 #define ALT_USB_DEV_DIEPCTL12_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
96270 /* Produces a ALT_USB_DEV_DIEPCTL12_NAKSTS register field value suitable for setting the register. */
96271 #define ALT_USB_DEV_DIEPCTL12_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
96272 
96273 /*
96274  * Field : eptype
96275  *
96276  * Endpoint Type (EPType)
96277  *
96278  * This is the transfer type supported by this logical endpoint.
96279  *
96280  * 2'b00: Control
96281  *
96282  * 2'b01: Isochronous
96283  *
96284  * 2'b10: Bulk
96285  *
96286  * 2'b11: Interrupt
96287  *
96288  * Field Enumeration Values:
96289  *
96290  * Enum | Value | Description
96291  * :-------------------------------------------|:------|:------------
96292  * ALT_USB_DEV_DIEPCTL12_EPTYPE_E_CTL | 0x0 | Control
96293  * ALT_USB_DEV_DIEPCTL12_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
96294  * ALT_USB_DEV_DIEPCTL12_EPTYPE_E_BULK | 0x2 | Bulk
96295  * ALT_USB_DEV_DIEPCTL12_EPTYPE_E_INTERRUP | 0x3 | Interrupt
96296  *
96297  * Field Access Macros:
96298  *
96299  */
96300 /*
96301  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE
96302  *
96303  * Control
96304  */
96305 #define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_CTL 0x0
96306 /*
96307  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE
96308  *
96309  * Isochronous
96310  */
96311 #define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_ISOCHRONOUS 0x1
96312 /*
96313  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE
96314  *
96315  * Bulk
96316  */
96317 #define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_BULK 0x2
96318 /*
96319  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE
96320  *
96321  * Interrupt
96322  */
96323 #define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_INTERRUP 0x3
96324 
96325 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */
96326 #define ALT_USB_DEV_DIEPCTL12_EPTYPE_LSB 18
96327 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */
96328 #define ALT_USB_DEV_DIEPCTL12_EPTYPE_MSB 19
96329 /* The width in bits of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */
96330 #define ALT_USB_DEV_DIEPCTL12_EPTYPE_WIDTH 2
96331 /* The mask used to set the ALT_USB_DEV_DIEPCTL12_EPTYPE register field value. */
96332 #define ALT_USB_DEV_DIEPCTL12_EPTYPE_SET_MSK 0x000c0000
96333 /* The mask used to clear the ALT_USB_DEV_DIEPCTL12_EPTYPE register field value. */
96334 #define ALT_USB_DEV_DIEPCTL12_EPTYPE_CLR_MSK 0xfff3ffff
96335 /* The reset value of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */
96336 #define ALT_USB_DEV_DIEPCTL12_EPTYPE_RESET 0x0
96337 /* Extracts the ALT_USB_DEV_DIEPCTL12_EPTYPE field value from a register. */
96338 #define ALT_USB_DEV_DIEPCTL12_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
96339 /* Produces a ALT_USB_DEV_DIEPCTL12_EPTYPE register field value suitable for setting the register. */
96340 #define ALT_USB_DEV_DIEPCTL12_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
96341 
96342 /*
96343  * Field : stall
96344  *
96345  * STALL Handshake (Stall)
96346  *
96347  * Applies to non-control, non-isochronous IN and OUT endpoints only.
96348  *
96349  * The application sets this bit to stall all tokens from the USB host to this
96350  * endpoint. If a
96351  *
96352  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
96353  * bit, the
96354  *
96355  * STALL bit takes priority. Only the application can clear this bit, never the
96356  * core.
96357  *
96358  * 1'b0 R_W
96359  *
96360  * Applies to control endpoints only.
96361  *
96362  * The application can only set this bit, and the core clears it, when a SETUP
96363  * token is
96364  *
96365  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
96366  * OUT
96367  *
96368  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
96369  * this bit's
96370  *
96371  * setting, the core always responds to SETUP data packets with an ACK handshake.
96372  *
96373  * Field Enumeration Values:
96374  *
96375  * Enum | Value | Description
96376  * :------------------------------------|:------|:----------------------------
96377  * ALT_USB_DEV_DIEPCTL12_STALL_E_INACT | 0x0 | STALL All Tokens not active
96378  * ALT_USB_DEV_DIEPCTL12_STALL_E_ACT | 0x1 | STALL All Tokens active
96379  *
96380  * Field Access Macros:
96381  *
96382  */
96383 /*
96384  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_STALL
96385  *
96386  * STALL All Tokens not active
96387  */
96388 #define ALT_USB_DEV_DIEPCTL12_STALL_E_INACT 0x0
96389 /*
96390  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_STALL
96391  *
96392  * STALL All Tokens active
96393  */
96394 #define ALT_USB_DEV_DIEPCTL12_STALL_E_ACT 0x1
96395 
96396 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_STALL register field. */
96397 #define ALT_USB_DEV_DIEPCTL12_STALL_LSB 21
96398 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_STALL register field. */
96399 #define ALT_USB_DEV_DIEPCTL12_STALL_MSB 21
96400 /* The width in bits of the ALT_USB_DEV_DIEPCTL12_STALL register field. */
96401 #define ALT_USB_DEV_DIEPCTL12_STALL_WIDTH 1
96402 /* The mask used to set the ALT_USB_DEV_DIEPCTL12_STALL register field value. */
96403 #define ALT_USB_DEV_DIEPCTL12_STALL_SET_MSK 0x00200000
96404 /* The mask used to clear the ALT_USB_DEV_DIEPCTL12_STALL register field value. */
96405 #define ALT_USB_DEV_DIEPCTL12_STALL_CLR_MSK 0xffdfffff
96406 /* The reset value of the ALT_USB_DEV_DIEPCTL12_STALL register field. */
96407 #define ALT_USB_DEV_DIEPCTL12_STALL_RESET 0x0
96408 /* Extracts the ALT_USB_DEV_DIEPCTL12_STALL field value from a register. */
96409 #define ALT_USB_DEV_DIEPCTL12_STALL_GET(value) (((value) & 0x00200000) >> 21)
96410 /* Produces a ALT_USB_DEV_DIEPCTL12_STALL register field value suitable for setting the register. */
96411 #define ALT_USB_DEV_DIEPCTL12_STALL_SET(value) (((value) << 21) & 0x00200000)
96412 
96413 /*
96414  * Field : txfnum
96415  *
96416  * TxFIFO Number (TxFNum)
96417  *
96418  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
96419  *
96420  * endpoints must map this to the corresponding Periodic TxFIFO number.
96421  *
96422  * 4'h0: Non-Periodic TxFIFO
96423  *
96424  * Others: Specified Periodic TxFIFO.number
96425  *
96426  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
96427  *
96428  * applications such as mass storage. The core treats an IN endpoint as a non-
96429  * periodic
96430  *
96431  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
96432  * must be
96433  *
96434  * allocated for an interrupt IN endpoint, and the number of this
96435  *
96436  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
96437  *
96438  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
96439  *
96440  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
96441  *
96442  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
96443  *
96444  * This field is valid only for IN endpoints.
96445  *
96446  * Field Access Macros:
96447  *
96448  */
96449 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */
96450 #define ALT_USB_DEV_DIEPCTL12_TXFNUM_LSB 22
96451 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */
96452 #define ALT_USB_DEV_DIEPCTL12_TXFNUM_MSB 25
96453 /* The width in bits of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */
96454 #define ALT_USB_DEV_DIEPCTL12_TXFNUM_WIDTH 4
96455 /* The mask used to set the ALT_USB_DEV_DIEPCTL12_TXFNUM register field value. */
96456 #define ALT_USB_DEV_DIEPCTL12_TXFNUM_SET_MSK 0x03c00000
96457 /* The mask used to clear the ALT_USB_DEV_DIEPCTL12_TXFNUM register field value. */
96458 #define ALT_USB_DEV_DIEPCTL12_TXFNUM_CLR_MSK 0xfc3fffff
96459 /* The reset value of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */
96460 #define ALT_USB_DEV_DIEPCTL12_TXFNUM_RESET 0x0
96461 /* Extracts the ALT_USB_DEV_DIEPCTL12_TXFNUM field value from a register. */
96462 #define ALT_USB_DEV_DIEPCTL12_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
96463 /* Produces a ALT_USB_DEV_DIEPCTL12_TXFNUM register field value suitable for setting the register. */
96464 #define ALT_USB_DEV_DIEPCTL12_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
96465 
96466 /*
96467  * Field : cnak
96468  *
96469  * Clear NAK (CNAK)
96470  *
96471  * A write to this bit clears the NAK bit For the endpoint.
96472  *
96473  * Field Enumeration Values:
96474  *
96475  * Enum | Value | Description
96476  * :-----------------------------------|:------|:-------------
96477  * ALT_USB_DEV_DIEPCTL12_CNAK_E_INACT | 0x0 | No Clear NAK
96478  * ALT_USB_DEV_DIEPCTL12_CNAK_E_ACT | 0x1 | Clear NAK
96479  *
96480  * Field Access Macros:
96481  *
96482  */
96483 /*
96484  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_CNAK
96485  *
96486  * No Clear NAK
96487  */
96488 #define ALT_USB_DEV_DIEPCTL12_CNAK_E_INACT 0x0
96489 /*
96490  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_CNAK
96491  *
96492  * Clear NAK
96493  */
96494 #define ALT_USB_DEV_DIEPCTL12_CNAK_E_ACT 0x1
96495 
96496 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */
96497 #define ALT_USB_DEV_DIEPCTL12_CNAK_LSB 26
96498 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */
96499 #define ALT_USB_DEV_DIEPCTL12_CNAK_MSB 26
96500 /* The width in bits of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */
96501 #define ALT_USB_DEV_DIEPCTL12_CNAK_WIDTH 1
96502 /* The mask used to set the ALT_USB_DEV_DIEPCTL12_CNAK register field value. */
96503 #define ALT_USB_DEV_DIEPCTL12_CNAK_SET_MSK 0x04000000
96504 /* The mask used to clear the ALT_USB_DEV_DIEPCTL12_CNAK register field value. */
96505 #define ALT_USB_DEV_DIEPCTL12_CNAK_CLR_MSK 0xfbffffff
96506 /* The reset value of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */
96507 #define ALT_USB_DEV_DIEPCTL12_CNAK_RESET 0x0
96508 /* Extracts the ALT_USB_DEV_DIEPCTL12_CNAK field value from a register. */
96509 #define ALT_USB_DEV_DIEPCTL12_CNAK_GET(value) (((value) & 0x04000000) >> 26)
96510 /* Produces a ALT_USB_DEV_DIEPCTL12_CNAK register field value suitable for setting the register. */
96511 #define ALT_USB_DEV_DIEPCTL12_CNAK_SET(value) (((value) << 26) & 0x04000000)
96512 
96513 /*
96514  * Field : snak
96515  *
96516  * Set NAK (SNAK)
96517  *
96518  * A write to this bit sets the NAK bit For the endpoint.
96519  *
96520  * Using this bit, the application can control the transmission of NAK
96521  *
96522  * handshakes on an endpoint. The core can also Set this bit For an
96523  *
96524  * endpoint after a SETUP packet is received on that endpoint.
96525  *
96526  * Field Enumeration Values:
96527  *
96528  * Enum | Value | Description
96529  * :-----------------------------------|:------|:------------
96530  * ALT_USB_DEV_DIEPCTL12_SNAK_E_INACT | 0x0 | No Set NAK
96531  * ALT_USB_DEV_DIEPCTL12_SNAK_E_ACT | 0x1 | Set NAK
96532  *
96533  * Field Access Macros:
96534  *
96535  */
96536 /*
96537  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SNAK
96538  *
96539  * No Set NAK
96540  */
96541 #define ALT_USB_DEV_DIEPCTL12_SNAK_E_INACT 0x0
96542 /*
96543  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SNAK
96544  *
96545  * Set NAK
96546  */
96547 #define ALT_USB_DEV_DIEPCTL12_SNAK_E_ACT 0x1
96548 
96549 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */
96550 #define ALT_USB_DEV_DIEPCTL12_SNAK_LSB 27
96551 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */
96552 #define ALT_USB_DEV_DIEPCTL12_SNAK_MSB 27
96553 /* The width in bits of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */
96554 #define ALT_USB_DEV_DIEPCTL12_SNAK_WIDTH 1
96555 /* The mask used to set the ALT_USB_DEV_DIEPCTL12_SNAK register field value. */
96556 #define ALT_USB_DEV_DIEPCTL12_SNAK_SET_MSK 0x08000000
96557 /* The mask used to clear the ALT_USB_DEV_DIEPCTL12_SNAK register field value. */
96558 #define ALT_USB_DEV_DIEPCTL12_SNAK_CLR_MSK 0xf7ffffff
96559 /* The reset value of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */
96560 #define ALT_USB_DEV_DIEPCTL12_SNAK_RESET 0x0
96561 /* Extracts the ALT_USB_DEV_DIEPCTL12_SNAK field value from a register. */
96562 #define ALT_USB_DEV_DIEPCTL12_SNAK_GET(value) (((value) & 0x08000000) >> 27)
96563 /* Produces a ALT_USB_DEV_DIEPCTL12_SNAK register field value suitable for setting the register. */
96564 #define ALT_USB_DEV_DIEPCTL12_SNAK_SET(value) (((value) << 27) & 0x08000000)
96565 
96566 /*
96567  * Field : setd0pid
96568  *
96569  * Set DATA0 PID (SetD0PID)
96570  *
96571  * Applies to interrupt/bulk IN and OUT endpoints only.
96572  *
96573  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
96574  * to DATA0.
96575  *
96576  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
96577  *
96578  * DMA mode.
96579  *
96580  * 1'b0 WO
96581  *
96582  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
96583  *
96584  * Applies to isochronous IN and OUT endpoints only.
96585  *
96586  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
96587  * (micro)
96588  *
96589  * frame.
96590  *
96591  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
96592  * number
96593  *
96594  * in which to send data is in the transmit descriptor structure. The frame in
96595  * which to
96596  *
96597  * receive data is updated in receive descriptor structure.
96598  *
96599  * Field Enumeration Values:
96600  *
96601  * Enum | Value | Description
96602  * :--------------------------------------|:------|:----------------------------
96603  * ALT_USB_DEV_DIEPCTL12_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
96604  * ALT_USB_DEV_DIEPCTL12_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
96605  *
96606  * Field Access Macros:
96607  *
96608  */
96609 /*
96610  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD0PID
96611  *
96612  * Disables Set DATA0 PID
96613  */
96614 #define ALT_USB_DEV_DIEPCTL12_SETD0PID_E_DISD 0x0
96615 /*
96616  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD0PID
96617  *
96618  * Endpoint Data PID to DATA0)
96619  */
96620 #define ALT_USB_DEV_DIEPCTL12_SETD0PID_E_END 0x1
96621 
96622 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */
96623 #define ALT_USB_DEV_DIEPCTL12_SETD0PID_LSB 28
96624 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */
96625 #define ALT_USB_DEV_DIEPCTL12_SETD0PID_MSB 28
96626 /* The width in bits of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */
96627 #define ALT_USB_DEV_DIEPCTL12_SETD0PID_WIDTH 1
96628 /* The mask used to set the ALT_USB_DEV_DIEPCTL12_SETD0PID register field value. */
96629 #define ALT_USB_DEV_DIEPCTL12_SETD0PID_SET_MSK 0x10000000
96630 /* The mask used to clear the ALT_USB_DEV_DIEPCTL12_SETD0PID register field value. */
96631 #define ALT_USB_DEV_DIEPCTL12_SETD0PID_CLR_MSK 0xefffffff
96632 /* The reset value of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */
96633 #define ALT_USB_DEV_DIEPCTL12_SETD0PID_RESET 0x0
96634 /* Extracts the ALT_USB_DEV_DIEPCTL12_SETD0PID field value from a register. */
96635 #define ALT_USB_DEV_DIEPCTL12_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
96636 /* Produces a ALT_USB_DEV_DIEPCTL12_SETD0PID register field value suitable for setting the register. */
96637 #define ALT_USB_DEV_DIEPCTL12_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
96638 
96639 /*
96640  * Field : setd1pid
96641  *
96642  * Set DATA1 PID (SetD1PID)
96643  *
96644  * Applies to interrupt/bulk IN and OUT endpoints only.
96645  *
96646  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
96647  * to DATA1.
96648  *
96649  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
96650  *
96651  * DMA mode.
96652  *
96653  * Set Odd (micro)frame (SetOddFr)
96654  *
96655  * Applies to isochronous IN and OUT endpoints only.
96656  *
96657  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
96658  *
96659  * (micro)frame.
96660  *
96661  * This field is not applicable for Scatter/Gather DMA mode.
96662  *
96663  * Field Enumeration Values:
96664  *
96665  * Enum | Value | Description
96666  * :--------------------------------------|:------|:-----------------------
96667  * ALT_USB_DEV_DIEPCTL12_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
96668  * ALT_USB_DEV_DIEPCTL12_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
96669  *
96670  * Field Access Macros:
96671  *
96672  */
96673 /*
96674  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD1PID
96675  *
96676  * Disables Set DATA1 PID
96677  */
96678 #define ALT_USB_DEV_DIEPCTL12_SETD1PID_E_DISD 0x0
96679 /*
96680  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD1PID
96681  *
96682  * Enables Set DATA1 PID
96683  */
96684 #define ALT_USB_DEV_DIEPCTL12_SETD1PID_E_END 0x1
96685 
96686 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */
96687 #define ALT_USB_DEV_DIEPCTL12_SETD1PID_LSB 29
96688 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */
96689 #define ALT_USB_DEV_DIEPCTL12_SETD1PID_MSB 29
96690 /* The width in bits of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */
96691 #define ALT_USB_DEV_DIEPCTL12_SETD1PID_WIDTH 1
96692 /* The mask used to set the ALT_USB_DEV_DIEPCTL12_SETD1PID register field value. */
96693 #define ALT_USB_DEV_DIEPCTL12_SETD1PID_SET_MSK 0x20000000
96694 /* The mask used to clear the ALT_USB_DEV_DIEPCTL12_SETD1PID register field value. */
96695 #define ALT_USB_DEV_DIEPCTL12_SETD1PID_CLR_MSK 0xdfffffff
96696 /* The reset value of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */
96697 #define ALT_USB_DEV_DIEPCTL12_SETD1PID_RESET 0x0
96698 /* Extracts the ALT_USB_DEV_DIEPCTL12_SETD1PID field value from a register. */
96699 #define ALT_USB_DEV_DIEPCTL12_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
96700 /* Produces a ALT_USB_DEV_DIEPCTL12_SETD1PID register field value suitable for setting the register. */
96701 #define ALT_USB_DEV_DIEPCTL12_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
96702 
96703 /*
96704  * Field : epdis
96705  *
96706  * Endpoint Disable (EPDis)
96707  *
96708  * Applies to IN and OUT endpoints.
96709  *
96710  * The application sets this bit to stop transmitting/receiving data on an
96711  * endpoint, even
96712  *
96713  * before the transfer for that endpoint is complete. The application must wait for
96714  * the
96715  *
96716  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
96717  * clears
96718  *
96719  * this bit before setting the Endpoint Disabled interrupt. The application must
96720  * set this bit
96721  *
96722  * only if Endpoint Enable is already set for this endpoint.
96723  *
96724  * Field Enumeration Values:
96725  *
96726  * Enum | Value | Description
96727  * :------------------------------------|:------|:--------------------
96728  * ALT_USB_DEV_DIEPCTL12_EPDIS_E_INACT | 0x0 | No Endpoint Disable
96729  * ALT_USB_DEV_DIEPCTL12_EPDIS_E_ACT | 0x1 | Endpoint Disable
96730  *
96731  * Field Access Macros:
96732  *
96733  */
96734 /*
96735  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPDIS
96736  *
96737  * No Endpoint Disable
96738  */
96739 #define ALT_USB_DEV_DIEPCTL12_EPDIS_E_INACT 0x0
96740 /*
96741  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPDIS
96742  *
96743  * Endpoint Disable
96744  */
96745 #define ALT_USB_DEV_DIEPCTL12_EPDIS_E_ACT 0x1
96746 
96747 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */
96748 #define ALT_USB_DEV_DIEPCTL12_EPDIS_LSB 30
96749 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */
96750 #define ALT_USB_DEV_DIEPCTL12_EPDIS_MSB 30
96751 /* The width in bits of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */
96752 #define ALT_USB_DEV_DIEPCTL12_EPDIS_WIDTH 1
96753 /* The mask used to set the ALT_USB_DEV_DIEPCTL12_EPDIS register field value. */
96754 #define ALT_USB_DEV_DIEPCTL12_EPDIS_SET_MSK 0x40000000
96755 /* The mask used to clear the ALT_USB_DEV_DIEPCTL12_EPDIS register field value. */
96756 #define ALT_USB_DEV_DIEPCTL12_EPDIS_CLR_MSK 0xbfffffff
96757 /* The reset value of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */
96758 #define ALT_USB_DEV_DIEPCTL12_EPDIS_RESET 0x0
96759 /* Extracts the ALT_USB_DEV_DIEPCTL12_EPDIS field value from a register. */
96760 #define ALT_USB_DEV_DIEPCTL12_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
96761 /* Produces a ALT_USB_DEV_DIEPCTL12_EPDIS register field value suitable for setting the register. */
96762 #define ALT_USB_DEV_DIEPCTL12_EPDIS_SET(value) (((value) << 30) & 0x40000000)
96763 
96764 /*
96765  * Field : epena
96766  *
96767  * Endpoint Enable (EPEna)
96768  *
96769  * Applies to IN and OUT endpoints.
96770  *
96771  * When Scatter/Gather DMA mode is enabled,
96772  *
96773  * For IN endpoints this bit indicates that the descriptor structure and data
96774  * buffer with
96775  *
96776  * data ready to transmit is setup.
96777  *
96778  * For OUT endpoint it indicates that the descriptor structure and data buffer to
96779  *
96780  * receive data is setup.
96781  *
96782  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
96783  *
96784  * DMA mode:
96785  *
96786  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
96787  * the
96788  *
96789  * endpoint.
96790  *
96791  * * For OUT endpoints, this bit indicates that the application has allocated the
96792  *
96793  * memory to start receiving data from the USB.
96794  *
96795  * * The core clears this bit before setting any of the following interrupts on
96796  * this
96797  *
96798  * endpoint:
96799  *
96800  * SETUP Phase Done
96801  *
96802  * Endpoint Disabled
96803  *
96804  * Transfer Completed
96805  *
96806  * Note: For control endpoints in DMA mode, this bit must be set to be able to
96807  * transfer
96808  *
96809  * SETUP data packets in memory.
96810  *
96811  * Field Enumeration Values:
96812  *
96813  * Enum | Value | Description
96814  * :------------------------------------|:------|:-------------------------
96815  * ALT_USB_DEV_DIEPCTL12_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
96816  * ALT_USB_DEV_DIEPCTL12_EPENA_E_ACT | 0x1 | Endpoint Enable active
96817  *
96818  * Field Access Macros:
96819  *
96820  */
96821 /*
96822  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPENA
96823  *
96824  * Endpoint Enable inactive
96825  */
96826 #define ALT_USB_DEV_DIEPCTL12_EPENA_E_INACT 0x0
96827 /*
96828  * Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPENA
96829  *
96830  * Endpoint Enable active
96831  */
96832 #define ALT_USB_DEV_DIEPCTL12_EPENA_E_ACT 0x1
96833 
96834 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */
96835 #define ALT_USB_DEV_DIEPCTL12_EPENA_LSB 31
96836 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */
96837 #define ALT_USB_DEV_DIEPCTL12_EPENA_MSB 31
96838 /* The width in bits of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */
96839 #define ALT_USB_DEV_DIEPCTL12_EPENA_WIDTH 1
96840 /* The mask used to set the ALT_USB_DEV_DIEPCTL12_EPENA register field value. */
96841 #define ALT_USB_DEV_DIEPCTL12_EPENA_SET_MSK 0x80000000
96842 /* The mask used to clear the ALT_USB_DEV_DIEPCTL12_EPENA register field value. */
96843 #define ALT_USB_DEV_DIEPCTL12_EPENA_CLR_MSK 0x7fffffff
96844 /* The reset value of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */
96845 #define ALT_USB_DEV_DIEPCTL12_EPENA_RESET 0x0
96846 /* Extracts the ALT_USB_DEV_DIEPCTL12_EPENA field value from a register. */
96847 #define ALT_USB_DEV_DIEPCTL12_EPENA_GET(value) (((value) & 0x80000000) >> 31)
96848 /* Produces a ALT_USB_DEV_DIEPCTL12_EPENA register field value suitable for setting the register. */
96849 #define ALT_USB_DEV_DIEPCTL12_EPENA_SET(value) (((value) << 31) & 0x80000000)
96850 
96851 #ifndef __ASSEMBLY__
96852 /*
96853  * WARNING: The C register and register group struct declarations are provided for
96854  * convenience and illustrative purposes. They should, however, be used with
96855  * caution as the C language standard provides no guarantees about the alignment or
96856  * atomicity of device memory accesses. The recommended practice for writing
96857  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
96858  * alt_write_word() functions.
96859  *
96860  * The struct declaration for register ALT_USB_DEV_DIEPCTL12.
96861  */
96862 struct ALT_USB_DEV_DIEPCTL12_s
96863 {
96864  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL12_MPS */
96865  uint32_t : 4; /* *UNDEFINED* */
96866  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL12_USBACTEP */
96867  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL12_DPID */
96868  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL12_NAKSTS */
96869  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL12_EPTYPE */
96870  uint32_t : 1; /* *UNDEFINED* */
96871  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL12_STALL */
96872  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL12_TXFNUM */
96873  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL12_CNAK */
96874  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL12_SNAK */
96875  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL12_SETD0PID */
96876  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL12_SETD1PID */
96877  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL12_EPDIS */
96878  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL12_EPENA */
96879 };
96880 
96881 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL12. */
96882 typedef volatile struct ALT_USB_DEV_DIEPCTL12_s ALT_USB_DEV_DIEPCTL12_t;
96883 #endif /* __ASSEMBLY__ */
96884 
96885 /* The reset value of the ALT_USB_DEV_DIEPCTL12 register. */
96886 #define ALT_USB_DEV_DIEPCTL12_RESET 0x00000000
96887 /* The byte offset of the ALT_USB_DEV_DIEPCTL12 register from the beginning of the component. */
96888 #define ALT_USB_DEV_DIEPCTL12_OFST 0x280
96889 /* The address of the ALT_USB_DEV_DIEPCTL12 register. */
96890 #define ALT_USB_DEV_DIEPCTL12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL12_OFST))
96891 
96892 /*
96893  * Register : diepint12
96894  *
96895  * Device IN Endpoint 12 Interrupt Register
96896  *
96897  * Register Layout
96898  *
96899  * Bits | Access | Reset | Description
96900  * :--------|:-------|:------|:----------------------------------
96901  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_XFERCOMPL
96902  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_EPDISBLD
96903  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_AHBERR
96904  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_TMO
96905  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_INTKNTXFEMP
96906  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_INTKNEPMIS
96907  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_INEPNAKEFF
96908  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT12_TXFEMP
96909  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN
96910  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_BNAINTR
96911  * [10] | ??? | 0x0 | *UNDEFINED*
96912  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_PKTDRPSTS
96913  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_BBLEERR
96914  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_NAKINTRPT
96915  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_NYETINTRPT
96916  * [31:15] | ??? | 0x0 | *UNDEFINED*
96917  *
96918  */
96919 /*
96920  * Field : xfercompl
96921  *
96922  * Transfer Completed Interrupt (XferCompl)
96923  *
96924  * Applies to IN and OUT endpoints.
96925  *
96926  * When Scatter/Gather DMA mode is enabled
96927  *
96928  * * For IN endpoint this field indicates that the requested data
96929  *
96930  * from the descriptor is moved from external system memory
96931  *
96932  * to internal FIFO.
96933  *
96934  * * For OUT endpoint this field indicates that the requested
96935  *
96936  * data from the internal FIFO is moved to external system
96937  *
96938  * memory. This interrupt is generated only when the
96939  *
96940  * corresponding endpoint descriptor is closed, and the IOC
96941  *
96942  * bit For the corresponding descriptor is Set.
96943  *
96944  * When Scatter/Gather DMA mode is disabled, this field
96945  *
96946  * indicates that the programmed transfer is complete on the
96947  *
96948  * AHB as well as on the USB, For this endpoint.
96949  *
96950  * Field Enumeration Values:
96951  *
96952  * Enum | Value | Description
96953  * :----------------------------------------|:------|:-----------------------------
96954  * ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_INACT | 0x0 | No Interrupt
96955  * ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
96956  *
96957  * Field Access Macros:
96958  *
96959  */
96960 /*
96961  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_XFERCOMPL
96962  *
96963  * No Interrupt
96964  */
96965 #define ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_INACT 0x0
96966 /*
96967  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_XFERCOMPL
96968  *
96969  * Transfer Completed Interrupt
96970  */
96971 #define ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_ACT 0x1
96972 
96973 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */
96974 #define ALT_USB_DEV_DIEPINT12_XFERCOMPL_LSB 0
96975 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */
96976 #define ALT_USB_DEV_DIEPINT12_XFERCOMPL_MSB 0
96977 /* The width in bits of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */
96978 #define ALT_USB_DEV_DIEPINT12_XFERCOMPL_WIDTH 1
96979 /* The mask used to set the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field value. */
96980 #define ALT_USB_DEV_DIEPINT12_XFERCOMPL_SET_MSK 0x00000001
96981 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field value. */
96982 #define ALT_USB_DEV_DIEPINT12_XFERCOMPL_CLR_MSK 0xfffffffe
96983 /* The reset value of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */
96984 #define ALT_USB_DEV_DIEPINT12_XFERCOMPL_RESET 0x0
96985 /* Extracts the ALT_USB_DEV_DIEPINT12_XFERCOMPL field value from a register. */
96986 #define ALT_USB_DEV_DIEPINT12_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
96987 /* Produces a ALT_USB_DEV_DIEPINT12_XFERCOMPL register field value suitable for setting the register. */
96988 #define ALT_USB_DEV_DIEPINT12_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
96989 
96990 /*
96991  * Field : epdisbld
96992  *
96993  * Endpoint Disabled Interrupt (EPDisbld)
96994  *
96995  * Applies to IN and OUT endpoints.
96996  *
96997  * This bit indicates that the endpoint is disabled per the
96998  *
96999  * application's request.
97000  *
97001  * Field Enumeration Values:
97002  *
97003  * Enum | Value | Description
97004  * :---------------------------------------|:------|:----------------------------
97005  * ALT_USB_DEV_DIEPINT12_EPDISBLD_E_INACT | 0x0 | No Interrupt
97006  * ALT_USB_DEV_DIEPINT12_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
97007  *
97008  * Field Access Macros:
97009  *
97010  */
97011 /*
97012  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_EPDISBLD
97013  *
97014  * No Interrupt
97015  */
97016 #define ALT_USB_DEV_DIEPINT12_EPDISBLD_E_INACT 0x0
97017 /*
97018  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_EPDISBLD
97019  *
97020  * Endpoint Disabled Interrupt
97021  */
97022 #define ALT_USB_DEV_DIEPINT12_EPDISBLD_E_ACT 0x1
97023 
97024 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */
97025 #define ALT_USB_DEV_DIEPINT12_EPDISBLD_LSB 1
97026 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */
97027 #define ALT_USB_DEV_DIEPINT12_EPDISBLD_MSB 1
97028 /* The width in bits of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */
97029 #define ALT_USB_DEV_DIEPINT12_EPDISBLD_WIDTH 1
97030 /* The mask used to set the ALT_USB_DEV_DIEPINT12_EPDISBLD register field value. */
97031 #define ALT_USB_DEV_DIEPINT12_EPDISBLD_SET_MSK 0x00000002
97032 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_EPDISBLD register field value. */
97033 #define ALT_USB_DEV_DIEPINT12_EPDISBLD_CLR_MSK 0xfffffffd
97034 /* The reset value of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */
97035 #define ALT_USB_DEV_DIEPINT12_EPDISBLD_RESET 0x0
97036 /* Extracts the ALT_USB_DEV_DIEPINT12_EPDISBLD field value from a register. */
97037 #define ALT_USB_DEV_DIEPINT12_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
97038 /* Produces a ALT_USB_DEV_DIEPINT12_EPDISBLD register field value suitable for setting the register. */
97039 #define ALT_USB_DEV_DIEPINT12_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
97040 
97041 /*
97042  * Field : ahberr
97043  *
97044  * AHB Error (AHBErr)
97045  *
97046  * Applies to IN and OUT endpoints.
97047  *
97048  * This is generated only in Internal DMA mode when there is an
97049  *
97050  * AHB error during an AHB read/write. The application can read
97051  *
97052  * the corresponding endpoint DMA address register to get the
97053  *
97054  * error address.
97055  *
97056  * Field Enumeration Values:
97057  *
97058  * Enum | Value | Description
97059  * :-------------------------------------|:------|:--------------------
97060  * ALT_USB_DEV_DIEPINT12_AHBERR_E_INACT | 0x0 | No Interrupt
97061  * ALT_USB_DEV_DIEPINT12_AHBERR_E_ACT | 0x1 | AHB Error interrupt
97062  *
97063  * Field Access Macros:
97064  *
97065  */
97066 /*
97067  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_AHBERR
97068  *
97069  * No Interrupt
97070  */
97071 #define ALT_USB_DEV_DIEPINT12_AHBERR_E_INACT 0x0
97072 /*
97073  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_AHBERR
97074  *
97075  * AHB Error interrupt
97076  */
97077 #define ALT_USB_DEV_DIEPINT12_AHBERR_E_ACT 0x1
97078 
97079 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */
97080 #define ALT_USB_DEV_DIEPINT12_AHBERR_LSB 2
97081 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */
97082 #define ALT_USB_DEV_DIEPINT12_AHBERR_MSB 2
97083 /* The width in bits of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */
97084 #define ALT_USB_DEV_DIEPINT12_AHBERR_WIDTH 1
97085 /* The mask used to set the ALT_USB_DEV_DIEPINT12_AHBERR register field value. */
97086 #define ALT_USB_DEV_DIEPINT12_AHBERR_SET_MSK 0x00000004
97087 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_AHBERR register field value. */
97088 #define ALT_USB_DEV_DIEPINT12_AHBERR_CLR_MSK 0xfffffffb
97089 /* The reset value of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */
97090 #define ALT_USB_DEV_DIEPINT12_AHBERR_RESET 0x0
97091 /* Extracts the ALT_USB_DEV_DIEPINT12_AHBERR field value from a register. */
97092 #define ALT_USB_DEV_DIEPINT12_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
97093 /* Produces a ALT_USB_DEV_DIEPINT12_AHBERR register field value suitable for setting the register. */
97094 #define ALT_USB_DEV_DIEPINT12_AHBERR_SET(value) (((value) << 2) & 0x00000004)
97095 
97096 /*
97097  * Field : timeout
97098  *
97099  * Timeout Condition (TimeOUT)
97100  *
97101  * In shared TX FIFO mode, applies to non-isochronous IN
97102  *
97103  * endpoints only.
97104  *
97105  * In dedicated FIFO mode, applies only to Control IN
97106  *
97107  * endpoints.
97108  *
97109  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
97110  *
97111  * asserted.
97112  *
97113  * Indicates that the core has detected a timeout condition on the
97114  *
97115  * USB For the last IN token on this endpoint.
97116  *
97117  * Field Enumeration Values:
97118  *
97119  * Enum | Value | Description
97120  * :----------------------------------|:------|:------------------
97121  * ALT_USB_DEV_DIEPINT12_TMO_E_INACT | 0x0 | No interrupt
97122  * ALT_USB_DEV_DIEPINT12_TMO_E_ACT | 0x1 | Timeout interrupy
97123  *
97124  * Field Access Macros:
97125  *
97126  */
97127 /*
97128  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TMO
97129  *
97130  * No interrupt
97131  */
97132 #define ALT_USB_DEV_DIEPINT12_TMO_E_INACT 0x0
97133 /*
97134  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TMO
97135  *
97136  * Timeout interrupy
97137  */
97138 #define ALT_USB_DEV_DIEPINT12_TMO_E_ACT 0x1
97139 
97140 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_TMO register field. */
97141 #define ALT_USB_DEV_DIEPINT12_TMO_LSB 3
97142 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_TMO register field. */
97143 #define ALT_USB_DEV_DIEPINT12_TMO_MSB 3
97144 /* The width in bits of the ALT_USB_DEV_DIEPINT12_TMO register field. */
97145 #define ALT_USB_DEV_DIEPINT12_TMO_WIDTH 1
97146 /* The mask used to set the ALT_USB_DEV_DIEPINT12_TMO register field value. */
97147 #define ALT_USB_DEV_DIEPINT12_TMO_SET_MSK 0x00000008
97148 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_TMO register field value. */
97149 #define ALT_USB_DEV_DIEPINT12_TMO_CLR_MSK 0xfffffff7
97150 /* The reset value of the ALT_USB_DEV_DIEPINT12_TMO register field. */
97151 #define ALT_USB_DEV_DIEPINT12_TMO_RESET 0x0
97152 /* Extracts the ALT_USB_DEV_DIEPINT12_TMO field value from a register. */
97153 #define ALT_USB_DEV_DIEPINT12_TMO_GET(value) (((value) & 0x00000008) >> 3)
97154 /* Produces a ALT_USB_DEV_DIEPINT12_TMO register field value suitable for setting the register. */
97155 #define ALT_USB_DEV_DIEPINT12_TMO_SET(value) (((value) << 3) & 0x00000008)
97156 
97157 /*
97158  * Field : intkntxfemp
97159  *
97160  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
97161  *
97162  * Applies to non-periodic IN endpoints only.
97163  *
97164  * Indicates that an IN token was received when the associated
97165  *
97166  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
97167  *
97168  * asserted on the endpoint For which the IN token was received.
97169  *
97170  * Field Enumeration Values:
97171  *
97172  * Enum | Value | Description
97173  * :------------------------------------------|:------|:----------------------------
97174  * ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
97175  * ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
97176  *
97177  * Field Access Macros:
97178  *
97179  */
97180 /*
97181  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNTXFEMP
97182  *
97183  * No interrupt
97184  */
97185 #define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_INACT 0x0
97186 /*
97187  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNTXFEMP
97188  *
97189  * IN Token Received Interrupt
97190  */
97191 #define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_ACT 0x1
97192 
97193 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */
97194 #define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_LSB 4
97195 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */
97196 #define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_MSB 4
97197 /* The width in bits of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */
97198 #define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_WIDTH 1
97199 /* The mask used to set the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field value. */
97200 #define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_SET_MSK 0x00000010
97201 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field value. */
97202 #define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_CLR_MSK 0xffffffef
97203 /* The reset value of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */
97204 #define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_RESET 0x0
97205 /* Extracts the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP field value from a register. */
97206 #define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
97207 /* Produces a ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field value suitable for setting the register. */
97208 #define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
97209 
97210 /*
97211  * Field : intknepmis
97212  *
97213  * IN Token Received with EP Mismatch (INTknEPMis)
97214  *
97215  * Applies to non-periodic IN endpoints only.
97216  *
97217  * Indicates that the data in the top of the non-periodic TxFIFO
97218  *
97219  * belongs to an endpoint other than the one For which the IN token
97220  *
97221  * was received. This interrupt is asserted on the endpoint For
97222  *
97223  * which the IN token was received.
97224  *
97225  * Field Enumeration Values:
97226  *
97227  * Enum | Value | Description
97228  * :-----------------------------------------|:------|:---------------------------------------------
97229  * ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_INACT | 0x0 | No interrupt
97230  * ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
97231  *
97232  * Field Access Macros:
97233  *
97234  */
97235 /*
97236  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNEPMIS
97237  *
97238  * No interrupt
97239  */
97240 #define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_INACT 0x0
97241 /*
97242  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNEPMIS
97243  *
97244  * IN Token Received with EP Mismatch interrupt
97245  */
97246 #define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_ACT 0x1
97247 
97248 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */
97249 #define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_LSB 5
97250 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */
97251 #define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_MSB 5
97252 /* The width in bits of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */
97253 #define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_WIDTH 1
97254 /* The mask used to set the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field value. */
97255 #define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_SET_MSK 0x00000020
97256 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field value. */
97257 #define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_CLR_MSK 0xffffffdf
97258 /* The reset value of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */
97259 #define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_RESET 0x0
97260 /* Extracts the ALT_USB_DEV_DIEPINT12_INTKNEPMIS field value from a register. */
97261 #define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
97262 /* Produces a ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field value suitable for setting the register. */
97263 #define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
97264 
97265 /*
97266  * Field : inepnakeff
97267  *
97268  * IN Endpoint NAK Effective (INEPNakEff)
97269  *
97270  * Applies to periodic IN endpoints only.
97271  *
97272  * This bit can be cleared when the application clears the IN
97273  *
97274  * endpoint NAK by writing to DIEPCTLn.CNAK.
97275  *
97276  * This interrupt indicates that the core has sampled the NAK bit
97277  *
97278  * Set (either by the application or by the core). The interrupt
97279  *
97280  * indicates that the IN endpoint NAK bit Set by the application has
97281  *
97282  * taken effect in the core.
97283  *
97284  * This interrupt does not guarantee that a NAK handshake is sent
97285  *
97286  * on the USB. A STALL bit takes priority over a NAK bit.
97287  *
97288  * Field Enumeration Values:
97289  *
97290  * Enum | Value | Description
97291  * :-----------------------------------------|:------|:------------------------------------
97292  * ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_INACT | 0x0 | No interrupt
97293  * ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
97294  *
97295  * Field Access Macros:
97296  *
97297  */
97298 /*
97299  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INEPNAKEFF
97300  *
97301  * No interrupt
97302  */
97303 #define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_INACT 0x0
97304 /*
97305  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_INEPNAKEFF
97306  *
97307  * IN Endpoint NAK Effective interrupt
97308  */
97309 #define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_ACT 0x1
97310 
97311 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */
97312 #define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_LSB 6
97313 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */
97314 #define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_MSB 6
97315 /* The width in bits of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */
97316 #define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_WIDTH 1
97317 /* The mask used to set the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field value. */
97318 #define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_SET_MSK 0x00000040
97319 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field value. */
97320 #define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_CLR_MSK 0xffffffbf
97321 /* The reset value of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */
97322 #define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_RESET 0x0
97323 /* Extracts the ALT_USB_DEV_DIEPINT12_INEPNAKEFF field value from a register. */
97324 #define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
97325 /* Produces a ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field value suitable for setting the register. */
97326 #define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
97327 
97328 /*
97329  * Field : txfemp
97330  *
97331  * Transmit FIFO Empty (TxFEmp)
97332  *
97333  * This bit is valid only For IN Endpoints
97334  *
97335  * This interrupt is asserted when the TxFIFO For this endpoint is
97336  *
97337  * either half or completely empty. The half or completely empty
97338  *
97339  * status is determined by the TxFIFO Empty Level bit in the Core
97340  *
97341  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
97342  *
97343  * Field Enumeration Values:
97344  *
97345  * Enum | Value | Description
97346  * :-------------------------------------|:------|:------------------------------
97347  * ALT_USB_DEV_DIEPINT12_TXFEMP_E_INACT | 0x0 | No interrupt
97348  * ALT_USB_DEV_DIEPINT12_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
97349  *
97350  * Field Access Macros:
97351  *
97352  */
97353 /*
97354  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFEMP
97355  *
97356  * No interrupt
97357  */
97358 #define ALT_USB_DEV_DIEPINT12_TXFEMP_E_INACT 0x0
97359 /*
97360  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFEMP
97361  *
97362  * Transmit FIFO Empty interrupt
97363  */
97364 #define ALT_USB_DEV_DIEPINT12_TXFEMP_E_ACT 0x1
97365 
97366 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */
97367 #define ALT_USB_DEV_DIEPINT12_TXFEMP_LSB 7
97368 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */
97369 #define ALT_USB_DEV_DIEPINT12_TXFEMP_MSB 7
97370 /* The width in bits of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */
97371 #define ALT_USB_DEV_DIEPINT12_TXFEMP_WIDTH 1
97372 /* The mask used to set the ALT_USB_DEV_DIEPINT12_TXFEMP register field value. */
97373 #define ALT_USB_DEV_DIEPINT12_TXFEMP_SET_MSK 0x00000080
97374 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_TXFEMP register field value. */
97375 #define ALT_USB_DEV_DIEPINT12_TXFEMP_CLR_MSK 0xffffff7f
97376 /* The reset value of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */
97377 #define ALT_USB_DEV_DIEPINT12_TXFEMP_RESET 0x1
97378 /* Extracts the ALT_USB_DEV_DIEPINT12_TXFEMP field value from a register. */
97379 #define ALT_USB_DEV_DIEPINT12_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
97380 /* Produces a ALT_USB_DEV_DIEPINT12_TXFEMP register field value suitable for setting the register. */
97381 #define ALT_USB_DEV_DIEPINT12_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
97382 
97383 /*
97384  * Field : txfifoundrn
97385  *
97386  * Fifo Underrun (TxfifoUndrn)
97387  *
97388  * Applies to IN endpoints Only
97389  *
97390  * This bit is valid only If thresholding is enabled. The core generates this
97391  * interrupt when
97392  *
97393  * it detects a transmit FIFO underrun condition For this endpoint.
97394  *
97395  * Field Enumeration Values:
97396  *
97397  * Enum | Value | Description
97398  * :------------------------------------------|:------|:------------------------
97399  * ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
97400  * ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
97401  *
97402  * Field Access Macros:
97403  *
97404  */
97405 /*
97406  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN
97407  *
97408  * No interrupt
97409  */
97410 #define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_INACT 0x0
97411 /*
97412  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN
97413  *
97414  * Fifo Underrun interrupt
97415  */
97416 #define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_ACT 0x1
97417 
97418 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */
97419 #define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_LSB 8
97420 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */
97421 #define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_MSB 8
97422 /* The width in bits of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */
97423 #define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_WIDTH 1
97424 /* The mask used to set the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field value. */
97425 #define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_SET_MSK 0x00000100
97426 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field value. */
97427 #define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_CLR_MSK 0xfffffeff
97428 /* The reset value of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */
97429 #define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_RESET 0x0
97430 /* Extracts the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN field value from a register. */
97431 #define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
97432 /* Produces a ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field value suitable for setting the register. */
97433 #define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
97434 
97435 /*
97436  * Field : bnaintr
97437  *
97438  * BNA (Buffer Not Available) Interrupt (BNAIntr)
97439  *
97440  * This bit is valid only when Scatter/Gather DMA mode is enabled.
97441  *
97442  * The core generates this interrupt when the descriptor accessed
97443  *
97444  * is not ready For the Core to process, such as Host busy or DMA
97445  *
97446  * done
97447  *
97448  * Field Enumeration Values:
97449  *
97450  * Enum | Value | Description
97451  * :--------------------------------------|:------|:--------------
97452  * ALT_USB_DEV_DIEPINT12_BNAINTR_E_INACT | 0x0 | No interrupt
97453  * ALT_USB_DEV_DIEPINT12_BNAINTR_E_ACT | 0x1 | BNA interrupt
97454  *
97455  * Field Access Macros:
97456  *
97457  */
97458 /*
97459  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_BNAINTR
97460  *
97461  * No interrupt
97462  */
97463 #define ALT_USB_DEV_DIEPINT12_BNAINTR_E_INACT 0x0
97464 /*
97465  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_BNAINTR
97466  *
97467  * BNA interrupt
97468  */
97469 #define ALT_USB_DEV_DIEPINT12_BNAINTR_E_ACT 0x1
97470 
97471 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */
97472 #define ALT_USB_DEV_DIEPINT12_BNAINTR_LSB 9
97473 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */
97474 #define ALT_USB_DEV_DIEPINT12_BNAINTR_MSB 9
97475 /* The width in bits of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */
97476 #define ALT_USB_DEV_DIEPINT12_BNAINTR_WIDTH 1
97477 /* The mask used to set the ALT_USB_DEV_DIEPINT12_BNAINTR register field value. */
97478 #define ALT_USB_DEV_DIEPINT12_BNAINTR_SET_MSK 0x00000200
97479 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_BNAINTR register field value. */
97480 #define ALT_USB_DEV_DIEPINT12_BNAINTR_CLR_MSK 0xfffffdff
97481 /* The reset value of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */
97482 #define ALT_USB_DEV_DIEPINT12_BNAINTR_RESET 0x0
97483 /* Extracts the ALT_USB_DEV_DIEPINT12_BNAINTR field value from a register. */
97484 #define ALT_USB_DEV_DIEPINT12_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
97485 /* Produces a ALT_USB_DEV_DIEPINT12_BNAINTR register field value suitable for setting the register. */
97486 #define ALT_USB_DEV_DIEPINT12_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
97487 
97488 /*
97489  * Field : pktdrpsts
97490  *
97491  * Packet Drop Status (PktDrpSts)
97492  *
97493  * This bit indicates to the application that an ISOC OUT packet has been dropped.
97494  * This
97495  *
97496  * bit does not have an associated mask bit and does not generate an interrupt.
97497  *
97498  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
97499  * transfer
97500  *
97501  * interrupt feature is selected.
97502  *
97503  * Field Enumeration Values:
97504  *
97505  * Enum | Value | Description
97506  * :----------------------------------------|:------|:-----------------------------
97507  * ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_INACT | 0x0 | No interrupt
97508  * ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
97509  *
97510  * Field Access Macros:
97511  *
97512  */
97513 /*
97514  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_PKTDRPSTS
97515  *
97516  * No interrupt
97517  */
97518 #define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_INACT 0x0
97519 /*
97520  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_PKTDRPSTS
97521  *
97522  * Packet Drop Status interrupt
97523  */
97524 #define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_ACT 0x1
97525 
97526 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */
97527 #define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_LSB 11
97528 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */
97529 #define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_MSB 11
97530 /* The width in bits of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */
97531 #define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_WIDTH 1
97532 /* The mask used to set the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field value. */
97533 #define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_SET_MSK 0x00000800
97534 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field value. */
97535 #define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_CLR_MSK 0xfffff7ff
97536 /* The reset value of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */
97537 #define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_RESET 0x0
97538 /* Extracts the ALT_USB_DEV_DIEPINT12_PKTDRPSTS field value from a register. */
97539 #define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
97540 /* Produces a ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field value suitable for setting the register. */
97541 #define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
97542 
97543 /*
97544  * Field : bbleerr
97545  *
97546  * NAK Interrupt (BbleErr)
97547  *
97548  * The core generates this interrupt when babble is received for the endpoint.
97549  *
97550  * Field Enumeration Values:
97551  *
97552  * Enum | Value | Description
97553  * :--------------------------------------|:------|:------------------
97554  * ALT_USB_DEV_DIEPINT12_BBLEERR_E_INACT | 0x0 | No interrupt
97555  * ALT_USB_DEV_DIEPINT12_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
97556  *
97557  * Field Access Macros:
97558  *
97559  */
97560 /*
97561  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_BBLEERR
97562  *
97563  * No interrupt
97564  */
97565 #define ALT_USB_DEV_DIEPINT12_BBLEERR_E_INACT 0x0
97566 /*
97567  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_BBLEERR
97568  *
97569  * BbleErr interrupt
97570  */
97571 #define ALT_USB_DEV_DIEPINT12_BBLEERR_E_ACT 0x1
97572 
97573 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */
97574 #define ALT_USB_DEV_DIEPINT12_BBLEERR_LSB 12
97575 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */
97576 #define ALT_USB_DEV_DIEPINT12_BBLEERR_MSB 12
97577 /* The width in bits of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */
97578 #define ALT_USB_DEV_DIEPINT12_BBLEERR_WIDTH 1
97579 /* The mask used to set the ALT_USB_DEV_DIEPINT12_BBLEERR register field value. */
97580 #define ALT_USB_DEV_DIEPINT12_BBLEERR_SET_MSK 0x00001000
97581 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_BBLEERR register field value. */
97582 #define ALT_USB_DEV_DIEPINT12_BBLEERR_CLR_MSK 0xffffefff
97583 /* The reset value of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */
97584 #define ALT_USB_DEV_DIEPINT12_BBLEERR_RESET 0x0
97585 /* Extracts the ALT_USB_DEV_DIEPINT12_BBLEERR field value from a register. */
97586 #define ALT_USB_DEV_DIEPINT12_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
97587 /* Produces a ALT_USB_DEV_DIEPINT12_BBLEERR register field value suitable for setting the register. */
97588 #define ALT_USB_DEV_DIEPINT12_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
97589 
97590 /*
97591  * Field : nakintrpt
97592  *
97593  * NAK Interrupt (NAKInterrupt)
97594  *
97595  * The core generates this interrupt when a NAK is transmitted or received by the
97596  * device.
97597  *
97598  * In case of isochronous IN endpoints the interrupt gets generated when a zero
97599  * length
97600  *
97601  * packet is transmitted due to un-availability of data in the TXFifo.
97602  *
97603  * Field Enumeration Values:
97604  *
97605  * Enum | Value | Description
97606  * :----------------------------------------|:------|:--------------
97607  * ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_INACT | 0x0 | No interrupt
97608  * ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
97609  *
97610  * Field Access Macros:
97611  *
97612  */
97613 /*
97614  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_NAKINTRPT
97615  *
97616  * No interrupt
97617  */
97618 #define ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_INACT 0x0
97619 /*
97620  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_NAKINTRPT
97621  *
97622  * NAK Interrupt
97623  */
97624 #define ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_ACT 0x1
97625 
97626 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */
97627 #define ALT_USB_DEV_DIEPINT12_NAKINTRPT_LSB 13
97628 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */
97629 #define ALT_USB_DEV_DIEPINT12_NAKINTRPT_MSB 13
97630 /* The width in bits of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */
97631 #define ALT_USB_DEV_DIEPINT12_NAKINTRPT_WIDTH 1
97632 /* The mask used to set the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field value. */
97633 #define ALT_USB_DEV_DIEPINT12_NAKINTRPT_SET_MSK 0x00002000
97634 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field value. */
97635 #define ALT_USB_DEV_DIEPINT12_NAKINTRPT_CLR_MSK 0xffffdfff
97636 /* The reset value of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */
97637 #define ALT_USB_DEV_DIEPINT12_NAKINTRPT_RESET 0x0
97638 /* Extracts the ALT_USB_DEV_DIEPINT12_NAKINTRPT field value from a register. */
97639 #define ALT_USB_DEV_DIEPINT12_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
97640 /* Produces a ALT_USB_DEV_DIEPINT12_NAKINTRPT register field value suitable for setting the register. */
97641 #define ALT_USB_DEV_DIEPINT12_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
97642 
97643 /*
97644  * Field : nyetintrpt
97645  *
97646  * NYET Interrupt (NYETIntrpt)
97647  *
97648  * The core generates this interrupt when a NYET response is transmitted for a non
97649  * isochronous OUT endpoint.
97650  *
97651  * Field Enumeration Values:
97652  *
97653  * Enum | Value | Description
97654  * :-----------------------------------------|:------|:---------------
97655  * ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_INACT | 0x0 | No interrupt
97656  * ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
97657  *
97658  * Field Access Macros:
97659  *
97660  */
97661 /*
97662  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_NYETINTRPT
97663  *
97664  * No interrupt
97665  */
97666 #define ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_INACT 0x0
97667 /*
97668  * Enumerated value for register field ALT_USB_DEV_DIEPINT12_NYETINTRPT
97669  *
97670  * NYET Interrupt
97671  */
97672 #define ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_ACT 0x1
97673 
97674 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */
97675 #define ALT_USB_DEV_DIEPINT12_NYETINTRPT_LSB 14
97676 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */
97677 #define ALT_USB_DEV_DIEPINT12_NYETINTRPT_MSB 14
97678 /* The width in bits of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */
97679 #define ALT_USB_DEV_DIEPINT12_NYETINTRPT_WIDTH 1
97680 /* The mask used to set the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field value. */
97681 #define ALT_USB_DEV_DIEPINT12_NYETINTRPT_SET_MSK 0x00004000
97682 /* The mask used to clear the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field value. */
97683 #define ALT_USB_DEV_DIEPINT12_NYETINTRPT_CLR_MSK 0xffffbfff
97684 /* The reset value of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */
97685 #define ALT_USB_DEV_DIEPINT12_NYETINTRPT_RESET 0x0
97686 /* Extracts the ALT_USB_DEV_DIEPINT12_NYETINTRPT field value from a register. */
97687 #define ALT_USB_DEV_DIEPINT12_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
97688 /* Produces a ALT_USB_DEV_DIEPINT12_NYETINTRPT register field value suitable for setting the register. */
97689 #define ALT_USB_DEV_DIEPINT12_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
97690 
97691 #ifndef __ASSEMBLY__
97692 /*
97693  * WARNING: The C register and register group struct declarations are provided for
97694  * convenience and illustrative purposes. They should, however, be used with
97695  * caution as the C language standard provides no guarantees about the alignment or
97696  * atomicity of device memory accesses. The recommended practice for writing
97697  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
97698  * alt_write_word() functions.
97699  *
97700  * The struct declaration for register ALT_USB_DEV_DIEPINT12.
97701  */
97702 struct ALT_USB_DEV_DIEPINT12_s
97703 {
97704  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT12_XFERCOMPL */
97705  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT12_EPDISBLD */
97706  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT12_AHBERR */
97707  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT12_TMO */
97708  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT12_INTKNTXFEMP */
97709  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT12_INTKNEPMIS */
97710  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT12_INEPNAKEFF */
97711  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT12_TXFEMP */
97712  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN */
97713  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT12_BNAINTR */
97714  uint32_t : 1; /* *UNDEFINED* */
97715  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT12_PKTDRPSTS */
97716  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT12_BBLEERR */
97717  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT12_NAKINTRPT */
97718  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT12_NYETINTRPT */
97719  uint32_t : 17; /* *UNDEFINED* */
97720 };
97721 
97722 /* The typedef declaration for register ALT_USB_DEV_DIEPINT12. */
97723 typedef volatile struct ALT_USB_DEV_DIEPINT12_s ALT_USB_DEV_DIEPINT12_t;
97724 #endif /* __ASSEMBLY__ */
97725 
97726 /* The reset value of the ALT_USB_DEV_DIEPINT12 register. */
97727 #define ALT_USB_DEV_DIEPINT12_RESET 0x00000080
97728 /* The byte offset of the ALT_USB_DEV_DIEPINT12 register from the beginning of the component. */
97729 #define ALT_USB_DEV_DIEPINT12_OFST 0x288
97730 /* The address of the ALT_USB_DEV_DIEPINT12 register. */
97731 #define ALT_USB_DEV_DIEPINT12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT12_OFST))
97732 
97733 /*
97734  * Register : dieptsiz12
97735  *
97736  * Device IN Endpoint 12 Transfer Size Register
97737  *
97738  * Register Layout
97739  *
97740  * Bits | Access | Reset | Description
97741  * :--------|:-------|:------|:--------------------------------
97742  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ12_XFERSIZE
97743  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ12_PKTCNT
97744  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ12_MC
97745  * [31] | ??? | 0x0 | *UNDEFINED*
97746  *
97747  */
97748 /*
97749  * Field : xfersize
97750  *
97751  * Transfer Size (XferSize)
97752  *
97753  * Indicates the transfer size in bytes For endpoint 0. The core
97754  *
97755  * interrupts the application only after it has exhausted the transfer
97756  *
97757  * size amount of data. The transfer size can be Set to the
97758  *
97759  * maximum packet size of the endpoint, to be interrupted at the
97760  *
97761  * end of each packet.
97762  *
97763  * The core decrements this field every time a packet from the
97764  *
97765  * external memory is written to the TxFIFO.
97766  *
97767  * Field Access Macros:
97768  *
97769  */
97770 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */
97771 #define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_LSB 0
97772 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */
97773 #define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_MSB 18
97774 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */
97775 #define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_WIDTH 19
97776 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field value. */
97777 #define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_SET_MSK 0x0007ffff
97778 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field value. */
97779 #define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_CLR_MSK 0xfff80000
97780 /* The reset value of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */
97781 #define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_RESET 0x0
97782 /* Extracts the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE field value from a register. */
97783 #define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
97784 /* Produces a ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field value suitable for setting the register. */
97785 #define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
97786 
97787 /*
97788  * Field : pktcnt
97789  *
97790  * Packet Count (PktCnt)
97791  *
97792  * Indicates the total number of USB packets that constitute the
97793  *
97794  * Transfer Size amount of data For endpoint 0.
97795  *
97796  * This field is decremented every time a packet (maximum size or
97797  *
97798  * short packet) is read from the TxFIFO.
97799  *
97800  * Field Access Macros:
97801  *
97802  */
97803 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */
97804 #define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_LSB 19
97805 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */
97806 #define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_MSB 28
97807 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */
97808 #define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_WIDTH 10
97809 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field value. */
97810 #define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_SET_MSK 0x1ff80000
97811 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field value. */
97812 #define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_CLR_MSK 0xe007ffff
97813 /* The reset value of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */
97814 #define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_RESET 0x0
97815 /* Extracts the ALT_USB_DEV_DIEPTSIZ12_PKTCNT field value from a register. */
97816 #define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
97817 /* Produces a ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field value suitable for setting the register. */
97818 #define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
97819 
97820 /*
97821  * Field : mc
97822  *
97823  * Applies to IN endpoints only.
97824  *
97825  * For periodic IN endpoints, this field indicates the number of packets that must
97826  * be transmitted per microframe on the USB. The core uses this field to calculate
97827  * the data PID for isochronous IN endpoints.
97828  *
97829  * 2'b01: 1 packet
97830  *
97831  * 2'b10: 2 packets
97832  *
97833  * 2'b11: 3 packets
97834  *
97835  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
97836  * specifies the number of packets the core must fetchfor an IN endpoint before it
97837  * switches to the endpoint pointed to by the Next Endpoint field of the Device
97838  * Endpoint-n Control register (DIEPCTLn.NextEp)
97839  *
97840  * Field Enumeration Values:
97841  *
97842  * Enum | Value | Description
97843  * :-------------------------------------|:------|:------------
97844  * ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTONE | 0x1 | 1 packet
97845  * ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTWO | 0x2 | 2 packets
97846  * ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTHREE | 0x3 | 3 packets
97847  *
97848  * Field Access Macros:
97849  *
97850  */
97851 /*
97852  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ12_MC
97853  *
97854  * 1 packet
97855  */
97856 #define ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTONE 0x1
97857 /*
97858  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ12_MC
97859  *
97860  * 2 packets
97861  */
97862 #define ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTWO 0x2
97863 /*
97864  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ12_MC
97865  *
97866  * 3 packets
97867  */
97868 #define ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTHREE 0x3
97869 
97870 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */
97871 #define ALT_USB_DEV_DIEPTSIZ12_MC_LSB 29
97872 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */
97873 #define ALT_USB_DEV_DIEPTSIZ12_MC_MSB 30
97874 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */
97875 #define ALT_USB_DEV_DIEPTSIZ12_MC_WIDTH 2
97876 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ12_MC register field value. */
97877 #define ALT_USB_DEV_DIEPTSIZ12_MC_SET_MSK 0x60000000
97878 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ12_MC register field value. */
97879 #define ALT_USB_DEV_DIEPTSIZ12_MC_CLR_MSK 0x9fffffff
97880 /* The reset value of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */
97881 #define ALT_USB_DEV_DIEPTSIZ12_MC_RESET 0x0
97882 /* Extracts the ALT_USB_DEV_DIEPTSIZ12_MC field value from a register. */
97883 #define ALT_USB_DEV_DIEPTSIZ12_MC_GET(value) (((value) & 0x60000000) >> 29)
97884 /* Produces a ALT_USB_DEV_DIEPTSIZ12_MC register field value suitable for setting the register. */
97885 #define ALT_USB_DEV_DIEPTSIZ12_MC_SET(value) (((value) << 29) & 0x60000000)
97886 
97887 #ifndef __ASSEMBLY__
97888 /*
97889  * WARNING: The C register and register group struct declarations are provided for
97890  * convenience and illustrative purposes. They should, however, be used with
97891  * caution as the C language standard provides no guarantees about the alignment or
97892  * atomicity of device memory accesses. The recommended practice for writing
97893  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
97894  * alt_write_word() functions.
97895  *
97896  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ12.
97897  */
97898 struct ALT_USB_DEV_DIEPTSIZ12_s
97899 {
97900  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ12_XFERSIZE */
97901  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ12_PKTCNT */
97902  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ12_MC */
97903  uint32_t : 1; /* *UNDEFINED* */
97904 };
97905 
97906 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ12. */
97907 typedef volatile struct ALT_USB_DEV_DIEPTSIZ12_s ALT_USB_DEV_DIEPTSIZ12_t;
97908 #endif /* __ASSEMBLY__ */
97909 
97910 /* The reset value of the ALT_USB_DEV_DIEPTSIZ12 register. */
97911 #define ALT_USB_DEV_DIEPTSIZ12_RESET 0x00000000
97912 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ12 register from the beginning of the component. */
97913 #define ALT_USB_DEV_DIEPTSIZ12_OFST 0x290
97914 /* The address of the ALT_USB_DEV_DIEPTSIZ12 register. */
97915 #define ALT_USB_DEV_DIEPTSIZ12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ12_OFST))
97916 
97917 /*
97918  * Register : diepdma12
97919  *
97920  * Device IN Endpoint 12 DMA Address Register
97921  *
97922  * Register Layout
97923  *
97924  * Bits | Access | Reset | Description
97925  * :-------|:-------|:--------|:--------------------------------
97926  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA12_DIEPDMA12
97927  *
97928  */
97929 /*
97930  * Field : diepdma12
97931  *
97932  * Holds the start address of the external memory for storing or fetching endpoint
97933  *
97934  * data.
97935  *
97936  * Note: For control endpoints, this field stores control OUT data packets as well
97937  * as
97938  *
97939  * SETUP transaction data packets. When more than three SETUP packets are
97940  *
97941  * received back-to-back, the SETUP data packet in the memory is overwritten.
97942  *
97943  * This register is incremented on every AHB transaction. The application can give
97944  *
97945  * only a DWORD-aligned address.
97946  *
97947  * When Scatter/Gather DMA mode is not enabled, the application programs the
97948  *
97949  * start address value in this field.
97950  *
97951  * When Scatter/Gather DMA mode is enabled, this field indicates the base
97952  *
97953  * pointer for the descriptor list.
97954  *
97955  * Field Access Macros:
97956  *
97957  */
97958 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field. */
97959 #define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_LSB 0
97960 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field. */
97961 #define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_MSB 31
97962 /* The width in bits of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field. */
97963 #define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_WIDTH 32
97964 /* The mask used to set the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field value. */
97965 #define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_SET_MSK 0xffffffff
97966 /* The mask used to clear the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field value. */
97967 #define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_CLR_MSK 0x00000000
97968 /* The reset value of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field is UNKNOWN. */
97969 #define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_RESET 0x0
97970 /* Extracts the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 field value from a register. */
97971 #define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_GET(value) (((value) & 0xffffffff) >> 0)
97972 /* Produces a ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field value suitable for setting the register. */
97973 #define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_SET(value) (((value) << 0) & 0xffffffff)
97974 
97975 #ifndef __ASSEMBLY__
97976 /*
97977  * WARNING: The C register and register group struct declarations are provided for
97978  * convenience and illustrative purposes. They should, however, be used with
97979  * caution as the C language standard provides no guarantees about the alignment or
97980  * atomicity of device memory accesses. The recommended practice for writing
97981  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
97982  * alt_write_word() functions.
97983  *
97984  * The struct declaration for register ALT_USB_DEV_DIEPDMA12.
97985  */
97986 struct ALT_USB_DEV_DIEPDMA12_s
97987 {
97988  uint32_t diepdma12 : 32; /* ALT_USB_DEV_DIEPDMA12_DIEPDMA12 */
97989 };
97990 
97991 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA12. */
97992 typedef volatile struct ALT_USB_DEV_DIEPDMA12_s ALT_USB_DEV_DIEPDMA12_t;
97993 #endif /* __ASSEMBLY__ */
97994 
97995 /* The reset value of the ALT_USB_DEV_DIEPDMA12 register. */
97996 #define ALT_USB_DEV_DIEPDMA12_RESET 0x00000000
97997 /* The byte offset of the ALT_USB_DEV_DIEPDMA12 register from the beginning of the component. */
97998 #define ALT_USB_DEV_DIEPDMA12_OFST 0x294
97999 /* The address of the ALT_USB_DEV_DIEPDMA12 register. */
98000 #define ALT_USB_DEV_DIEPDMA12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA12_OFST))
98001 
98002 /*
98003  * Register : dtxfsts12
98004  *
98005  * Device IN Endpoint Transmit FIFO Status Register 12
98006  *
98007  * Register Layout
98008  *
98009  * Bits | Access | Reset | Description
98010  * :--------|:-------|:-------|:--------------------------------------
98011  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL
98012  * [31:16] | ??? | 0x0 | *UNDEFINED*
98013  *
98014  */
98015 /*
98016  * Field : ineptxfspcavail
98017  *
98018  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
98019  *
98020  * Indicates the amount of free space available in the Endpoint
98021  *
98022  * TxFIFO.
98023  *
98024  * Values are in terms of 32-bit words.
98025  *
98026  * 16'h0: Endpoint TxFIFO is full
98027  *
98028  * 16'h1: 1 word available
98029  *
98030  * 16'h2: 2 words available
98031  *
98032  * 16'hn: n words available (where 0 n 32,768)
98033  *
98034  * 16'h8000: 32,768 words available
98035  *
98036  * Others: Reserved
98037  *
98038  * Field Access Macros:
98039  *
98040  */
98041 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */
98042 #define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_LSB 0
98043 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */
98044 #define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_MSB 15
98045 /* The width in bits of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */
98046 #define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_WIDTH 16
98047 /* The mask used to set the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field value. */
98048 #define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
98049 /* The mask used to clear the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field value. */
98050 #define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
98051 /* The reset value of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */
98052 #define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_RESET 0x2000
98053 /* Extracts the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL field value from a register. */
98054 #define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
98055 /* Produces a ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field value suitable for setting the register. */
98056 #define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
98057 
98058 #ifndef __ASSEMBLY__
98059 /*
98060  * WARNING: The C register and register group struct declarations are provided for
98061  * convenience and illustrative purposes. They should, however, be used with
98062  * caution as the C language standard provides no guarantees about the alignment or
98063  * atomicity of device memory accesses. The recommended practice for writing
98064  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
98065  * alt_write_word() functions.
98066  *
98067  * The struct declaration for register ALT_USB_DEV_DTXFSTS12.
98068  */
98069 struct ALT_USB_DEV_DTXFSTS12_s
98070 {
98071  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL */
98072  uint32_t : 16; /* *UNDEFINED* */
98073 };
98074 
98075 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS12. */
98076 typedef volatile struct ALT_USB_DEV_DTXFSTS12_s ALT_USB_DEV_DTXFSTS12_t;
98077 #endif /* __ASSEMBLY__ */
98078 
98079 /* The reset value of the ALT_USB_DEV_DTXFSTS12 register. */
98080 #define ALT_USB_DEV_DTXFSTS12_RESET 0x00002000
98081 /* The byte offset of the ALT_USB_DEV_DTXFSTS12 register from the beginning of the component. */
98082 #define ALT_USB_DEV_DTXFSTS12_OFST 0x298
98083 /* The address of the ALT_USB_DEV_DTXFSTS12 register. */
98084 #define ALT_USB_DEV_DTXFSTS12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS12_OFST))
98085 
98086 /*
98087  * Register : diepdmab12
98088  *
98089  * Device IN Endpoint 12 Buffer Address Register
98090  *
98091  * Register Layout
98092  *
98093  * Bits | Access | Reset | Description
98094  * :-------|:-------|:--------|:----------------------------------
98095  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12
98096  *
98097  */
98098 /*
98099  * Field : diepdmab12
98100  *
98101  * Holds the current buffer address.This register is updated as and when the data
98102  *
98103  * transfer for the corresponding end point is in progress.
98104  *
98105  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
98106  * is
98107  *
98108  * reserved.
98109  *
98110  * Field Access Macros:
98111  *
98112  */
98113 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field. */
98114 #define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_LSB 0
98115 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field. */
98116 #define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_MSB 31
98117 /* The width in bits of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field. */
98118 #define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_WIDTH 32
98119 /* The mask used to set the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field value. */
98120 #define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_SET_MSK 0xffffffff
98121 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field value. */
98122 #define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_CLR_MSK 0x00000000
98123 /* The reset value of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field is UNKNOWN. */
98124 #define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_RESET 0x0
98125 /* Extracts the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 field value from a register. */
98126 #define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_GET(value) (((value) & 0xffffffff) >> 0)
98127 /* Produces a ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field value suitable for setting the register. */
98128 #define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_SET(value) (((value) << 0) & 0xffffffff)
98129 
98130 #ifndef __ASSEMBLY__
98131 /*
98132  * WARNING: The C register and register group struct declarations are provided for
98133  * convenience and illustrative purposes. They should, however, be used with
98134  * caution as the C language standard provides no guarantees about the alignment or
98135  * atomicity of device memory accesses. The recommended practice for writing
98136  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
98137  * alt_write_word() functions.
98138  *
98139  * The struct declaration for register ALT_USB_DEV_DIEPDMAB12.
98140  */
98141 struct ALT_USB_DEV_DIEPDMAB12_s
98142 {
98143  const uint32_t diepdmab12 : 32; /* ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 */
98144 };
98145 
98146 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB12. */
98147 typedef volatile struct ALT_USB_DEV_DIEPDMAB12_s ALT_USB_DEV_DIEPDMAB12_t;
98148 #endif /* __ASSEMBLY__ */
98149 
98150 /* The reset value of the ALT_USB_DEV_DIEPDMAB12 register. */
98151 #define ALT_USB_DEV_DIEPDMAB12_RESET 0x00000000
98152 /* The byte offset of the ALT_USB_DEV_DIEPDMAB12 register from the beginning of the component. */
98153 #define ALT_USB_DEV_DIEPDMAB12_OFST 0x29c
98154 /* The address of the ALT_USB_DEV_DIEPDMAB12 register. */
98155 #define ALT_USB_DEV_DIEPDMAB12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB12_OFST))
98156 
98157 /*
98158  * Register : diepctl13
98159  *
98160  * Device Control IN Endpoint 13 Control Register
98161  *
98162  * Register Layout
98163  *
98164  * Bits | Access | Reset | Description
98165  * :--------|:---------|:------|:-------------------------------
98166  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL13_MPS
98167  * [14:11] | ??? | 0x0 | *UNDEFINED*
98168  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL13_USBACTEP
98169  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL13_DPID
98170  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL13_NAKSTS
98171  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL13_EPTYPE
98172  * [20] | ??? | 0x0 | *UNDEFINED*
98173  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL13_STALL
98174  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL13_TXFNUM
98175  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL13_CNAK
98176  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL13_SNAK
98177  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL13_SETD0PID
98178  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL13_SETD1PID
98179  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL13_EPDIS
98180  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL13_EPENA
98181  *
98182  */
98183 /*
98184  * Field : mps
98185  *
98186  * Maximum Packet Size (MPS)
98187  *
98188  * The application must program this field with the maximum packet size for the
98189  * current
98190  *
98191  * logical endpoint. This value is in bytes.
98192  *
98193  * Field Access Macros:
98194  *
98195  */
98196 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_MPS register field. */
98197 #define ALT_USB_DEV_DIEPCTL13_MPS_LSB 0
98198 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_MPS register field. */
98199 #define ALT_USB_DEV_DIEPCTL13_MPS_MSB 10
98200 /* The width in bits of the ALT_USB_DEV_DIEPCTL13_MPS register field. */
98201 #define ALT_USB_DEV_DIEPCTL13_MPS_WIDTH 11
98202 /* The mask used to set the ALT_USB_DEV_DIEPCTL13_MPS register field value. */
98203 #define ALT_USB_DEV_DIEPCTL13_MPS_SET_MSK 0x000007ff
98204 /* The mask used to clear the ALT_USB_DEV_DIEPCTL13_MPS register field value. */
98205 #define ALT_USB_DEV_DIEPCTL13_MPS_CLR_MSK 0xfffff800
98206 /* The reset value of the ALT_USB_DEV_DIEPCTL13_MPS register field. */
98207 #define ALT_USB_DEV_DIEPCTL13_MPS_RESET 0x0
98208 /* Extracts the ALT_USB_DEV_DIEPCTL13_MPS field value from a register. */
98209 #define ALT_USB_DEV_DIEPCTL13_MPS_GET(value) (((value) & 0x000007ff) >> 0)
98210 /* Produces a ALT_USB_DEV_DIEPCTL13_MPS register field value suitable for setting the register. */
98211 #define ALT_USB_DEV_DIEPCTL13_MPS_SET(value) (((value) << 0) & 0x000007ff)
98212 
98213 /*
98214  * Field : usbactep
98215  *
98216  * USB Active Endpoint (USBActEP)
98217  *
98218  * Indicates whether this endpoint is active in the current configuration and
98219  * interface. The
98220  *
98221  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
98222  * reset. After
98223  *
98224  * receiving the SetConfiguration and SetInterface commands, the application must
98225  *
98226  * program endpoint registers accordingly and set this bit.
98227  *
98228  * Field Enumeration Values:
98229  *
98230  * Enum | Value | Description
98231  * :--------------------------------------|:------|:--------------------
98232  * ALT_USB_DEV_DIEPCTL13_USBACTEP_E_DISD | 0x0 | Not Active
98233  * ALT_USB_DEV_DIEPCTL13_USBACTEP_E_END | 0x1 | USB Active Endpoint
98234  *
98235  * Field Access Macros:
98236  *
98237  */
98238 /*
98239  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_USBACTEP
98240  *
98241  * Not Active
98242  */
98243 #define ALT_USB_DEV_DIEPCTL13_USBACTEP_E_DISD 0x0
98244 /*
98245  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_USBACTEP
98246  *
98247  * USB Active Endpoint
98248  */
98249 #define ALT_USB_DEV_DIEPCTL13_USBACTEP_E_END 0x1
98250 
98251 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */
98252 #define ALT_USB_DEV_DIEPCTL13_USBACTEP_LSB 15
98253 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */
98254 #define ALT_USB_DEV_DIEPCTL13_USBACTEP_MSB 15
98255 /* The width in bits of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */
98256 #define ALT_USB_DEV_DIEPCTL13_USBACTEP_WIDTH 1
98257 /* The mask used to set the ALT_USB_DEV_DIEPCTL13_USBACTEP register field value. */
98258 #define ALT_USB_DEV_DIEPCTL13_USBACTEP_SET_MSK 0x00008000
98259 /* The mask used to clear the ALT_USB_DEV_DIEPCTL13_USBACTEP register field value. */
98260 #define ALT_USB_DEV_DIEPCTL13_USBACTEP_CLR_MSK 0xffff7fff
98261 /* The reset value of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */
98262 #define ALT_USB_DEV_DIEPCTL13_USBACTEP_RESET 0x0
98263 /* Extracts the ALT_USB_DEV_DIEPCTL13_USBACTEP field value from a register. */
98264 #define ALT_USB_DEV_DIEPCTL13_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
98265 /* Produces a ALT_USB_DEV_DIEPCTL13_USBACTEP register field value suitable for setting the register. */
98266 #define ALT_USB_DEV_DIEPCTL13_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
98267 
98268 /*
98269  * Field : dpid
98270  *
98271  * Endpoint Data PID (DPID)
98272  *
98273  * Applies to interrupt/bulk IN and OUT endpoints only.
98274  *
98275  * Contains the PID of the packet to be received or transmitted on this endpoint.
98276  * The
98277  *
98278  * application must program the PID of the first packet to be received or
98279  * transmitted on
98280  *
98281  * this endpoint, after the endpoint is activated. The applications use the
98282  * SetD1PID and
98283  *
98284  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
98285  *
98286  * 1'b0: DATA0
98287  *
98288  * 1'b1: DATA1
98289  *
98290  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
98291  *
98292  * DMA mode.
98293  *
98294  * 1'b0 RO
98295  *
98296  * Even/Odd (Micro)Frame (EO_FrNum)
98297  *
98298  * In non-Scatter/Gather DMA mode:
98299  *
98300  * Applies to isochronous IN and OUT endpoints only.
98301  *
98302  * Indicates the (micro)frame number in which the core transmits/receives
98303  * isochronous
98304  *
98305  * data for this endpoint. The application must program the even/odd (micro) frame
98306  *
98307  * number in which it intends to transmit/receive isochronous data for this
98308  * endpoint using
98309  *
98310  * the SetEvnFr and SetOddFr fields in this register.
98311  *
98312  * 1'b0: Even (micro)frame
98313  *
98314  * 1'b1: Odd (micro)frame
98315  *
98316  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
98317  * number
98318  *
98319  * in which to send data is provided in the transmit descriptor structure. The
98320  * frame in
98321  *
98322  * which data is received is updated in receive descriptor structure.
98323  *
98324  * Field Enumeration Values:
98325  *
98326  * Enum | Value | Description
98327  * :-----------------------------------|:------|:-----------------------------
98328  * ALT_USB_DEV_DIEPCTL13_DPID_E_INACT | 0x0 | Endpoint Data PID not active
98329  * ALT_USB_DEV_DIEPCTL13_DPID_E_ACT | 0x1 | Endpoint Data PID active
98330  *
98331  * Field Access Macros:
98332  *
98333  */
98334 /*
98335  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_DPID
98336  *
98337  * Endpoint Data PID not active
98338  */
98339 #define ALT_USB_DEV_DIEPCTL13_DPID_E_INACT 0x0
98340 /*
98341  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_DPID
98342  *
98343  * Endpoint Data PID active
98344  */
98345 #define ALT_USB_DEV_DIEPCTL13_DPID_E_ACT 0x1
98346 
98347 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_DPID register field. */
98348 #define ALT_USB_DEV_DIEPCTL13_DPID_LSB 16
98349 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_DPID register field. */
98350 #define ALT_USB_DEV_DIEPCTL13_DPID_MSB 16
98351 /* The width in bits of the ALT_USB_DEV_DIEPCTL13_DPID register field. */
98352 #define ALT_USB_DEV_DIEPCTL13_DPID_WIDTH 1
98353 /* The mask used to set the ALT_USB_DEV_DIEPCTL13_DPID register field value. */
98354 #define ALT_USB_DEV_DIEPCTL13_DPID_SET_MSK 0x00010000
98355 /* The mask used to clear the ALT_USB_DEV_DIEPCTL13_DPID register field value. */
98356 #define ALT_USB_DEV_DIEPCTL13_DPID_CLR_MSK 0xfffeffff
98357 /* The reset value of the ALT_USB_DEV_DIEPCTL13_DPID register field. */
98358 #define ALT_USB_DEV_DIEPCTL13_DPID_RESET 0x0
98359 /* Extracts the ALT_USB_DEV_DIEPCTL13_DPID field value from a register. */
98360 #define ALT_USB_DEV_DIEPCTL13_DPID_GET(value) (((value) & 0x00010000) >> 16)
98361 /* Produces a ALT_USB_DEV_DIEPCTL13_DPID register field value suitable for setting the register. */
98362 #define ALT_USB_DEV_DIEPCTL13_DPID_SET(value) (((value) << 16) & 0x00010000)
98363 
98364 /*
98365  * Field : naksts
98366  *
98367  * NAK Status (NAKSts)
98368  *
98369  * Indicates the following:
98370  *
98371  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
98372  *
98373  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
98374  *
98375  * When either the application or the core sets this bit:
98376  *
98377  * The core stops receiving any data on an OUT endpoint, even if there is space in
98378  *
98379  * the RxFIFO to accommodate the incoming packet.
98380  *
98381  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
98382  *
98383  * endpoint, even if there data is available in the TxFIFO.
98384  *
98385  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
98386  *
98387  * if there data is available in the TxFIFO.
98388  *
98389  * Irrespective of this bit's setting, the core always responds to SETUP data
98390  * packets with
98391  *
98392  * an ACK handshake.
98393  *
98394  * Field Enumeration Values:
98395  *
98396  * Enum | Value | Description
98397  * :--------------------------------------|:------|:------------------------------------------------
98398  * ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
98399  * : | | based on the FIFO status
98400  * ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
98401  * : | | endpoint
98402  *
98403  * Field Access Macros:
98404  *
98405  */
98406 /*
98407  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_NAKSTS
98408  *
98409  * The core is transmitting non-NAK handshakes based on the FIFO status
98410  */
98411 #define ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NONNAK 0x0
98412 /*
98413  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_NAKSTS
98414  *
98415  * The core is transmitting NAK handshakes on this endpoint
98416  */
98417 #define ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NAK 0x1
98418 
98419 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */
98420 #define ALT_USB_DEV_DIEPCTL13_NAKSTS_LSB 17
98421 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */
98422 #define ALT_USB_DEV_DIEPCTL13_NAKSTS_MSB 17
98423 /* The width in bits of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */
98424 #define ALT_USB_DEV_DIEPCTL13_NAKSTS_WIDTH 1
98425 /* The mask used to set the ALT_USB_DEV_DIEPCTL13_NAKSTS register field value. */
98426 #define ALT_USB_DEV_DIEPCTL13_NAKSTS_SET_MSK 0x00020000
98427 /* The mask used to clear the ALT_USB_DEV_DIEPCTL13_NAKSTS register field value. */
98428 #define ALT_USB_DEV_DIEPCTL13_NAKSTS_CLR_MSK 0xfffdffff
98429 /* The reset value of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */
98430 #define ALT_USB_DEV_DIEPCTL13_NAKSTS_RESET 0x0
98431 /* Extracts the ALT_USB_DEV_DIEPCTL13_NAKSTS field value from a register. */
98432 #define ALT_USB_DEV_DIEPCTL13_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
98433 /* Produces a ALT_USB_DEV_DIEPCTL13_NAKSTS register field value suitable for setting the register. */
98434 #define ALT_USB_DEV_DIEPCTL13_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
98435 
98436 /*
98437  * Field : eptype
98438  *
98439  * Endpoint Type (EPType)
98440  *
98441  * This is the transfer type supported by this logical endpoint.
98442  *
98443  * 2'b00: Control
98444  *
98445  * 2'b01: Isochronous
98446  *
98447  * 2'b10: Bulk
98448  *
98449  * 2'b11: Interrupt
98450  *
98451  * Field Enumeration Values:
98452  *
98453  * Enum | Value | Description
98454  * :-------------------------------------------|:------|:------------
98455  * ALT_USB_DEV_DIEPCTL13_EPTYPE_E_CTL | 0x0 | Control
98456  * ALT_USB_DEV_DIEPCTL13_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
98457  * ALT_USB_DEV_DIEPCTL13_EPTYPE_E_BULK | 0x2 | Bulk
98458  * ALT_USB_DEV_DIEPCTL13_EPTYPE_E_INTERRUP | 0x3 | Interrupt
98459  *
98460  * Field Access Macros:
98461  *
98462  */
98463 /*
98464  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE
98465  *
98466  * Control
98467  */
98468 #define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_CTL 0x0
98469 /*
98470  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE
98471  *
98472  * Isochronous
98473  */
98474 #define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_ISOCHRONOUS 0x1
98475 /*
98476  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE
98477  *
98478  * Bulk
98479  */
98480 #define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_BULK 0x2
98481 /*
98482  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE
98483  *
98484  * Interrupt
98485  */
98486 #define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_INTERRUP 0x3
98487 
98488 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */
98489 #define ALT_USB_DEV_DIEPCTL13_EPTYPE_LSB 18
98490 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */
98491 #define ALT_USB_DEV_DIEPCTL13_EPTYPE_MSB 19
98492 /* The width in bits of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */
98493 #define ALT_USB_DEV_DIEPCTL13_EPTYPE_WIDTH 2
98494 /* The mask used to set the ALT_USB_DEV_DIEPCTL13_EPTYPE register field value. */
98495 #define ALT_USB_DEV_DIEPCTL13_EPTYPE_SET_MSK 0x000c0000
98496 /* The mask used to clear the ALT_USB_DEV_DIEPCTL13_EPTYPE register field value. */
98497 #define ALT_USB_DEV_DIEPCTL13_EPTYPE_CLR_MSK 0xfff3ffff
98498 /* The reset value of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */
98499 #define ALT_USB_DEV_DIEPCTL13_EPTYPE_RESET 0x0
98500 /* Extracts the ALT_USB_DEV_DIEPCTL13_EPTYPE field value from a register. */
98501 #define ALT_USB_DEV_DIEPCTL13_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
98502 /* Produces a ALT_USB_DEV_DIEPCTL13_EPTYPE register field value suitable for setting the register. */
98503 #define ALT_USB_DEV_DIEPCTL13_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
98504 
98505 /*
98506  * Field : stall
98507  *
98508  * STALL Handshake (Stall)
98509  *
98510  * Applies to non-control, non-isochronous IN and OUT endpoints only.
98511  *
98512  * The application sets this bit to stall all tokens from the USB host to this
98513  * endpoint. If a
98514  *
98515  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
98516  * bit, the
98517  *
98518  * STALL bit takes priority. Only the application can clear this bit, never the
98519  * core.
98520  *
98521  * 1'b0 R_W
98522  *
98523  * Applies to control endpoints only.
98524  *
98525  * The application can only set this bit, and the core clears it, when a SETUP
98526  * token is
98527  *
98528  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
98529  * OUT
98530  *
98531  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
98532  * this bit's
98533  *
98534  * setting, the core always responds to SETUP data packets with an ACK handshake.
98535  *
98536  * Field Enumeration Values:
98537  *
98538  * Enum | Value | Description
98539  * :------------------------------------|:------|:----------------------------
98540  * ALT_USB_DEV_DIEPCTL13_STALL_E_INACT | 0x0 | STALL All Tokens not active
98541  * ALT_USB_DEV_DIEPCTL13_STALL_E_ACT | 0x1 | STALL All Tokens active
98542  *
98543  * Field Access Macros:
98544  *
98545  */
98546 /*
98547  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_STALL
98548  *
98549  * STALL All Tokens not active
98550  */
98551 #define ALT_USB_DEV_DIEPCTL13_STALL_E_INACT 0x0
98552 /*
98553  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_STALL
98554  *
98555  * STALL All Tokens active
98556  */
98557 #define ALT_USB_DEV_DIEPCTL13_STALL_E_ACT 0x1
98558 
98559 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_STALL register field. */
98560 #define ALT_USB_DEV_DIEPCTL13_STALL_LSB 21
98561 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_STALL register field. */
98562 #define ALT_USB_DEV_DIEPCTL13_STALL_MSB 21
98563 /* The width in bits of the ALT_USB_DEV_DIEPCTL13_STALL register field. */
98564 #define ALT_USB_DEV_DIEPCTL13_STALL_WIDTH 1
98565 /* The mask used to set the ALT_USB_DEV_DIEPCTL13_STALL register field value. */
98566 #define ALT_USB_DEV_DIEPCTL13_STALL_SET_MSK 0x00200000
98567 /* The mask used to clear the ALT_USB_DEV_DIEPCTL13_STALL register field value. */
98568 #define ALT_USB_DEV_DIEPCTL13_STALL_CLR_MSK 0xffdfffff
98569 /* The reset value of the ALT_USB_DEV_DIEPCTL13_STALL register field. */
98570 #define ALT_USB_DEV_DIEPCTL13_STALL_RESET 0x0
98571 /* Extracts the ALT_USB_DEV_DIEPCTL13_STALL field value from a register. */
98572 #define ALT_USB_DEV_DIEPCTL13_STALL_GET(value) (((value) & 0x00200000) >> 21)
98573 /* Produces a ALT_USB_DEV_DIEPCTL13_STALL register field value suitable for setting the register. */
98574 #define ALT_USB_DEV_DIEPCTL13_STALL_SET(value) (((value) << 21) & 0x00200000)
98575 
98576 /*
98577  * Field : txfnum
98578  *
98579  * TxFIFO Number (TxFNum)
98580  *
98581  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
98582  *
98583  * endpoints must map this to the corresponding Periodic TxFIFO number.
98584  *
98585  * 4'h0: Non-Periodic TxFIFO
98586  *
98587  * Others: Specified Periodic TxFIFO.number
98588  *
98589  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
98590  *
98591  * applications such as mass storage. The core treats an IN endpoint as a non-
98592  * periodic
98593  *
98594  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
98595  * must be
98596  *
98597  * allocated for an interrupt IN endpoint, and the number of this
98598  *
98599  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
98600  *
98601  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
98602  *
98603  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
98604  *
98605  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
98606  *
98607  * This field is valid only for IN endpoints.
98608  *
98609  * Field Access Macros:
98610  *
98611  */
98612 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */
98613 #define ALT_USB_DEV_DIEPCTL13_TXFNUM_LSB 22
98614 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */
98615 #define ALT_USB_DEV_DIEPCTL13_TXFNUM_MSB 25
98616 /* The width in bits of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */
98617 #define ALT_USB_DEV_DIEPCTL13_TXFNUM_WIDTH 4
98618 /* The mask used to set the ALT_USB_DEV_DIEPCTL13_TXFNUM register field value. */
98619 #define ALT_USB_DEV_DIEPCTL13_TXFNUM_SET_MSK 0x03c00000
98620 /* The mask used to clear the ALT_USB_DEV_DIEPCTL13_TXFNUM register field value. */
98621 #define ALT_USB_DEV_DIEPCTL13_TXFNUM_CLR_MSK 0xfc3fffff
98622 /* The reset value of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */
98623 #define ALT_USB_DEV_DIEPCTL13_TXFNUM_RESET 0x0
98624 /* Extracts the ALT_USB_DEV_DIEPCTL13_TXFNUM field value from a register. */
98625 #define ALT_USB_DEV_DIEPCTL13_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
98626 /* Produces a ALT_USB_DEV_DIEPCTL13_TXFNUM register field value suitable for setting the register. */
98627 #define ALT_USB_DEV_DIEPCTL13_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
98628 
98629 /*
98630  * Field : cnak
98631  *
98632  * Clear NAK (CNAK)
98633  *
98634  * A write to this bit clears the NAK bit For the endpoint.
98635  *
98636  * Field Enumeration Values:
98637  *
98638  * Enum | Value | Description
98639  * :-----------------------------------|:------|:-------------
98640  * ALT_USB_DEV_DIEPCTL13_CNAK_E_INACT | 0x0 | No Clear NAK
98641  * ALT_USB_DEV_DIEPCTL13_CNAK_E_ACT | 0x1 | Clear NAK
98642  *
98643  * Field Access Macros:
98644  *
98645  */
98646 /*
98647  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_CNAK
98648  *
98649  * No Clear NAK
98650  */
98651 #define ALT_USB_DEV_DIEPCTL13_CNAK_E_INACT 0x0
98652 /*
98653  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_CNAK
98654  *
98655  * Clear NAK
98656  */
98657 #define ALT_USB_DEV_DIEPCTL13_CNAK_E_ACT 0x1
98658 
98659 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */
98660 #define ALT_USB_DEV_DIEPCTL13_CNAK_LSB 26
98661 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */
98662 #define ALT_USB_DEV_DIEPCTL13_CNAK_MSB 26
98663 /* The width in bits of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */
98664 #define ALT_USB_DEV_DIEPCTL13_CNAK_WIDTH 1
98665 /* The mask used to set the ALT_USB_DEV_DIEPCTL13_CNAK register field value. */
98666 #define ALT_USB_DEV_DIEPCTL13_CNAK_SET_MSK 0x04000000
98667 /* The mask used to clear the ALT_USB_DEV_DIEPCTL13_CNAK register field value. */
98668 #define ALT_USB_DEV_DIEPCTL13_CNAK_CLR_MSK 0xfbffffff
98669 /* The reset value of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */
98670 #define ALT_USB_DEV_DIEPCTL13_CNAK_RESET 0x0
98671 /* Extracts the ALT_USB_DEV_DIEPCTL13_CNAK field value from a register. */
98672 #define ALT_USB_DEV_DIEPCTL13_CNAK_GET(value) (((value) & 0x04000000) >> 26)
98673 /* Produces a ALT_USB_DEV_DIEPCTL13_CNAK register field value suitable for setting the register. */
98674 #define ALT_USB_DEV_DIEPCTL13_CNAK_SET(value) (((value) << 26) & 0x04000000)
98675 
98676 /*
98677  * Field : snak
98678  *
98679  * Set NAK (SNAK)
98680  *
98681  * A write to this bit sets the NAK bit For the endpoint.
98682  *
98683  * Using this bit, the application can control the transmission of NAK
98684  *
98685  * handshakes on an endpoint. The core can also Set this bit For an
98686  *
98687  * endpoint after a SETUP packet is received on that endpoint.
98688  *
98689  * Field Enumeration Values:
98690  *
98691  * Enum | Value | Description
98692  * :-----------------------------------|:------|:------------
98693  * ALT_USB_DEV_DIEPCTL13_SNAK_E_INACT | 0x0 | No Set NAK
98694  * ALT_USB_DEV_DIEPCTL13_SNAK_E_ACT | 0x1 | Set NAK
98695  *
98696  * Field Access Macros:
98697  *
98698  */
98699 /*
98700  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SNAK
98701  *
98702  * No Set NAK
98703  */
98704 #define ALT_USB_DEV_DIEPCTL13_SNAK_E_INACT 0x0
98705 /*
98706  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SNAK
98707  *
98708  * Set NAK
98709  */
98710 #define ALT_USB_DEV_DIEPCTL13_SNAK_E_ACT 0x1
98711 
98712 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */
98713 #define ALT_USB_DEV_DIEPCTL13_SNAK_LSB 27
98714 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */
98715 #define ALT_USB_DEV_DIEPCTL13_SNAK_MSB 27
98716 /* The width in bits of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */
98717 #define ALT_USB_DEV_DIEPCTL13_SNAK_WIDTH 1
98718 /* The mask used to set the ALT_USB_DEV_DIEPCTL13_SNAK register field value. */
98719 #define ALT_USB_DEV_DIEPCTL13_SNAK_SET_MSK 0x08000000
98720 /* The mask used to clear the ALT_USB_DEV_DIEPCTL13_SNAK register field value. */
98721 #define ALT_USB_DEV_DIEPCTL13_SNAK_CLR_MSK 0xf7ffffff
98722 /* The reset value of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */
98723 #define ALT_USB_DEV_DIEPCTL13_SNAK_RESET 0x0
98724 /* Extracts the ALT_USB_DEV_DIEPCTL13_SNAK field value from a register. */
98725 #define ALT_USB_DEV_DIEPCTL13_SNAK_GET(value) (((value) & 0x08000000) >> 27)
98726 /* Produces a ALT_USB_DEV_DIEPCTL13_SNAK register field value suitable for setting the register. */
98727 #define ALT_USB_DEV_DIEPCTL13_SNAK_SET(value) (((value) << 27) & 0x08000000)
98728 
98729 /*
98730  * Field : setd0pid
98731  *
98732  * Set DATA0 PID (SetD0PID)
98733  *
98734  * Applies to interrupt/bulk IN and OUT endpoints only.
98735  *
98736  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
98737  * to DATA0.
98738  *
98739  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
98740  *
98741  * DMA mode.
98742  *
98743  * 1'b0 WO
98744  *
98745  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
98746  *
98747  * Applies to isochronous IN and OUT endpoints only.
98748  *
98749  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
98750  * (micro)
98751  *
98752  * frame.
98753  *
98754  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
98755  * number
98756  *
98757  * in which to send data is in the transmit descriptor structure. The frame in
98758  * which to
98759  *
98760  * receive data is updated in receive descriptor structure.
98761  *
98762  * Field Enumeration Values:
98763  *
98764  * Enum | Value | Description
98765  * :--------------------------------------|:------|:----------------------------
98766  * ALT_USB_DEV_DIEPCTL13_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
98767  * ALT_USB_DEV_DIEPCTL13_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
98768  *
98769  * Field Access Macros:
98770  *
98771  */
98772 /*
98773  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD0PID
98774  *
98775  * Disables Set DATA0 PID
98776  */
98777 #define ALT_USB_DEV_DIEPCTL13_SETD0PID_E_DISD 0x0
98778 /*
98779  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD0PID
98780  *
98781  * Endpoint Data PID to DATA0)
98782  */
98783 #define ALT_USB_DEV_DIEPCTL13_SETD0PID_E_END 0x1
98784 
98785 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */
98786 #define ALT_USB_DEV_DIEPCTL13_SETD0PID_LSB 28
98787 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */
98788 #define ALT_USB_DEV_DIEPCTL13_SETD0PID_MSB 28
98789 /* The width in bits of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */
98790 #define ALT_USB_DEV_DIEPCTL13_SETD0PID_WIDTH 1
98791 /* The mask used to set the ALT_USB_DEV_DIEPCTL13_SETD0PID register field value. */
98792 #define ALT_USB_DEV_DIEPCTL13_SETD0PID_SET_MSK 0x10000000
98793 /* The mask used to clear the ALT_USB_DEV_DIEPCTL13_SETD0PID register field value. */
98794 #define ALT_USB_DEV_DIEPCTL13_SETD0PID_CLR_MSK 0xefffffff
98795 /* The reset value of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */
98796 #define ALT_USB_DEV_DIEPCTL13_SETD0PID_RESET 0x0
98797 /* Extracts the ALT_USB_DEV_DIEPCTL13_SETD0PID field value from a register. */
98798 #define ALT_USB_DEV_DIEPCTL13_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
98799 /* Produces a ALT_USB_DEV_DIEPCTL13_SETD0PID register field value suitable for setting the register. */
98800 #define ALT_USB_DEV_DIEPCTL13_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
98801 
98802 /*
98803  * Field : setd1pid
98804  *
98805  * Set DATA1 PID (SetD1PID)
98806  *
98807  * Applies to interrupt/bulk IN and OUT endpoints only.
98808  *
98809  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
98810  * to DATA1.
98811  *
98812  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
98813  *
98814  * DMA mode.
98815  *
98816  * Set Odd (micro)frame (SetOddFr)
98817  *
98818  * Applies to isochronous IN and OUT endpoints only.
98819  *
98820  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
98821  *
98822  * (micro)frame.
98823  *
98824  * This field is not applicable for Scatter/Gather DMA mode.
98825  *
98826  * Field Enumeration Values:
98827  *
98828  * Enum | Value | Description
98829  * :--------------------------------------|:------|:-----------------------
98830  * ALT_USB_DEV_DIEPCTL13_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
98831  * ALT_USB_DEV_DIEPCTL13_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
98832  *
98833  * Field Access Macros:
98834  *
98835  */
98836 /*
98837  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD1PID
98838  *
98839  * Disables Set DATA1 PID
98840  */
98841 #define ALT_USB_DEV_DIEPCTL13_SETD1PID_E_DISD 0x0
98842 /*
98843  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD1PID
98844  *
98845  * Enables Set DATA1 PID
98846  */
98847 #define ALT_USB_DEV_DIEPCTL13_SETD1PID_E_END 0x1
98848 
98849 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */
98850 #define ALT_USB_DEV_DIEPCTL13_SETD1PID_LSB 29
98851 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */
98852 #define ALT_USB_DEV_DIEPCTL13_SETD1PID_MSB 29
98853 /* The width in bits of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */
98854 #define ALT_USB_DEV_DIEPCTL13_SETD1PID_WIDTH 1
98855 /* The mask used to set the ALT_USB_DEV_DIEPCTL13_SETD1PID register field value. */
98856 #define ALT_USB_DEV_DIEPCTL13_SETD1PID_SET_MSK 0x20000000
98857 /* The mask used to clear the ALT_USB_DEV_DIEPCTL13_SETD1PID register field value. */
98858 #define ALT_USB_DEV_DIEPCTL13_SETD1PID_CLR_MSK 0xdfffffff
98859 /* The reset value of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */
98860 #define ALT_USB_DEV_DIEPCTL13_SETD1PID_RESET 0x0
98861 /* Extracts the ALT_USB_DEV_DIEPCTL13_SETD1PID field value from a register. */
98862 #define ALT_USB_DEV_DIEPCTL13_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
98863 /* Produces a ALT_USB_DEV_DIEPCTL13_SETD1PID register field value suitable for setting the register. */
98864 #define ALT_USB_DEV_DIEPCTL13_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
98865 
98866 /*
98867  * Field : epdis
98868  *
98869  * Endpoint Disable (EPDis)
98870  *
98871  * Applies to IN and OUT endpoints.
98872  *
98873  * The application sets this bit to stop transmitting/receiving data on an
98874  * endpoint, even
98875  *
98876  * before the transfer for that endpoint is complete. The application must wait for
98877  * the
98878  *
98879  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
98880  * clears
98881  *
98882  * this bit before setting the Endpoint Disabled interrupt. The application must
98883  * set this bit
98884  *
98885  * only if Endpoint Enable is already set for this endpoint.
98886  *
98887  * Field Enumeration Values:
98888  *
98889  * Enum | Value | Description
98890  * :------------------------------------|:------|:--------------------
98891  * ALT_USB_DEV_DIEPCTL13_EPDIS_E_INACT | 0x0 | No Endpoint Disable
98892  * ALT_USB_DEV_DIEPCTL13_EPDIS_E_ACT | 0x1 | Endpoint Disable
98893  *
98894  * Field Access Macros:
98895  *
98896  */
98897 /*
98898  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPDIS
98899  *
98900  * No Endpoint Disable
98901  */
98902 #define ALT_USB_DEV_DIEPCTL13_EPDIS_E_INACT 0x0
98903 /*
98904  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPDIS
98905  *
98906  * Endpoint Disable
98907  */
98908 #define ALT_USB_DEV_DIEPCTL13_EPDIS_E_ACT 0x1
98909 
98910 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */
98911 #define ALT_USB_DEV_DIEPCTL13_EPDIS_LSB 30
98912 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */
98913 #define ALT_USB_DEV_DIEPCTL13_EPDIS_MSB 30
98914 /* The width in bits of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */
98915 #define ALT_USB_DEV_DIEPCTL13_EPDIS_WIDTH 1
98916 /* The mask used to set the ALT_USB_DEV_DIEPCTL13_EPDIS register field value. */
98917 #define ALT_USB_DEV_DIEPCTL13_EPDIS_SET_MSK 0x40000000
98918 /* The mask used to clear the ALT_USB_DEV_DIEPCTL13_EPDIS register field value. */
98919 #define ALT_USB_DEV_DIEPCTL13_EPDIS_CLR_MSK 0xbfffffff
98920 /* The reset value of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */
98921 #define ALT_USB_DEV_DIEPCTL13_EPDIS_RESET 0x0
98922 /* Extracts the ALT_USB_DEV_DIEPCTL13_EPDIS field value from a register. */
98923 #define ALT_USB_DEV_DIEPCTL13_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
98924 /* Produces a ALT_USB_DEV_DIEPCTL13_EPDIS register field value suitable for setting the register. */
98925 #define ALT_USB_DEV_DIEPCTL13_EPDIS_SET(value) (((value) << 30) & 0x40000000)
98926 
98927 /*
98928  * Field : epena
98929  *
98930  * Endpoint Enable (EPEna)
98931  *
98932  * Applies to IN and OUT endpoints.
98933  *
98934  * When Scatter/Gather DMA mode is enabled,
98935  *
98936  * For IN endpoints this bit indicates that the descriptor structure and data
98937  * buffer with
98938  *
98939  * data ready to transmit is setup.
98940  *
98941  * For OUT endpoint it indicates that the descriptor structure and data buffer to
98942  *
98943  * receive data is setup.
98944  *
98945  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
98946  *
98947  * DMA mode:
98948  *
98949  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
98950  * the
98951  *
98952  * endpoint.
98953  *
98954  * * For OUT endpoints, this bit indicates that the application has allocated the
98955  *
98956  * memory to start receiving data from the USB.
98957  *
98958  * * The core clears this bit before setting any of the following interrupts on
98959  * this
98960  *
98961  * endpoint:
98962  *
98963  * SETUP Phase Done
98964  *
98965  * Endpoint Disabled
98966  *
98967  * Transfer Completed
98968  *
98969  * Note: For control endpoints in DMA mode, this bit must be set to be able to
98970  * transfer
98971  *
98972  * SETUP data packets in memory.
98973  *
98974  * Field Enumeration Values:
98975  *
98976  * Enum | Value | Description
98977  * :------------------------------------|:------|:-------------------------
98978  * ALT_USB_DEV_DIEPCTL13_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
98979  * ALT_USB_DEV_DIEPCTL13_EPENA_E_ACT | 0x1 | Endpoint Enable active
98980  *
98981  * Field Access Macros:
98982  *
98983  */
98984 /*
98985  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPENA
98986  *
98987  * Endpoint Enable inactive
98988  */
98989 #define ALT_USB_DEV_DIEPCTL13_EPENA_E_INACT 0x0
98990 /*
98991  * Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPENA
98992  *
98993  * Endpoint Enable active
98994  */
98995 #define ALT_USB_DEV_DIEPCTL13_EPENA_E_ACT 0x1
98996 
98997 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */
98998 #define ALT_USB_DEV_DIEPCTL13_EPENA_LSB 31
98999 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */
99000 #define ALT_USB_DEV_DIEPCTL13_EPENA_MSB 31
99001 /* The width in bits of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */
99002 #define ALT_USB_DEV_DIEPCTL13_EPENA_WIDTH 1
99003 /* The mask used to set the ALT_USB_DEV_DIEPCTL13_EPENA register field value. */
99004 #define ALT_USB_DEV_DIEPCTL13_EPENA_SET_MSK 0x80000000
99005 /* The mask used to clear the ALT_USB_DEV_DIEPCTL13_EPENA register field value. */
99006 #define ALT_USB_DEV_DIEPCTL13_EPENA_CLR_MSK 0x7fffffff
99007 /* The reset value of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */
99008 #define ALT_USB_DEV_DIEPCTL13_EPENA_RESET 0x0
99009 /* Extracts the ALT_USB_DEV_DIEPCTL13_EPENA field value from a register. */
99010 #define ALT_USB_DEV_DIEPCTL13_EPENA_GET(value) (((value) & 0x80000000) >> 31)
99011 /* Produces a ALT_USB_DEV_DIEPCTL13_EPENA register field value suitable for setting the register. */
99012 #define ALT_USB_DEV_DIEPCTL13_EPENA_SET(value) (((value) << 31) & 0x80000000)
99013 
99014 #ifndef __ASSEMBLY__
99015 /*
99016  * WARNING: The C register and register group struct declarations are provided for
99017  * convenience and illustrative purposes. They should, however, be used with
99018  * caution as the C language standard provides no guarantees about the alignment or
99019  * atomicity of device memory accesses. The recommended practice for writing
99020  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
99021  * alt_write_word() functions.
99022  *
99023  * The struct declaration for register ALT_USB_DEV_DIEPCTL13.
99024  */
99025 struct ALT_USB_DEV_DIEPCTL13_s
99026 {
99027  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL13_MPS */
99028  uint32_t : 4; /* *UNDEFINED* */
99029  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL13_USBACTEP */
99030  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL13_DPID */
99031  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL13_NAKSTS */
99032  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL13_EPTYPE */
99033  uint32_t : 1; /* *UNDEFINED* */
99034  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL13_STALL */
99035  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL13_TXFNUM */
99036  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL13_CNAK */
99037  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL13_SNAK */
99038  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL13_SETD0PID */
99039  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL13_SETD1PID */
99040  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL13_EPDIS */
99041  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL13_EPENA */
99042 };
99043 
99044 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL13. */
99045 typedef volatile struct ALT_USB_DEV_DIEPCTL13_s ALT_USB_DEV_DIEPCTL13_t;
99046 #endif /* __ASSEMBLY__ */
99047 
99048 /* The reset value of the ALT_USB_DEV_DIEPCTL13 register. */
99049 #define ALT_USB_DEV_DIEPCTL13_RESET 0x00000000
99050 /* The byte offset of the ALT_USB_DEV_DIEPCTL13 register from the beginning of the component. */
99051 #define ALT_USB_DEV_DIEPCTL13_OFST 0x2a0
99052 /* The address of the ALT_USB_DEV_DIEPCTL13 register. */
99053 #define ALT_USB_DEV_DIEPCTL13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL13_OFST))
99054 
99055 /*
99056  * Register : diepint13
99057  *
99058  * Device IN Endpoint 13 Interrupt Register
99059  *
99060  * Register Layout
99061  *
99062  * Bits | Access | Reset | Description
99063  * :--------|:-------|:------|:----------------------------------
99064  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_XFERCOMPL
99065  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_EPDISBLD
99066  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_AHBERR
99067  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_TMO
99068  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_INTKNTXFEMP
99069  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_INTKNEPMIS
99070  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_INEPNAKEFF
99071  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT13_TXFEMP
99072  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN
99073  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_BNAINTR
99074  * [10] | ??? | 0x0 | *UNDEFINED*
99075  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_PKTDRPSTS
99076  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_BBLEERR
99077  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_NAKINTRPT
99078  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_NYETINTRPT
99079  * [31:15] | ??? | 0x0 | *UNDEFINED*
99080  *
99081  */
99082 /*
99083  * Field : xfercompl
99084  *
99085  * Transfer Completed Interrupt (XferCompl)
99086  *
99087  * Applies to IN and OUT endpoints.
99088  *
99089  * When Scatter/Gather DMA mode is enabled
99090  *
99091  * * For IN endpoint this field indicates that the requested data
99092  *
99093  * from the descriptor is moved from external system memory
99094  *
99095  * to internal FIFO.
99096  *
99097  * * For OUT endpoint this field indicates that the requested
99098  *
99099  * data from the internal FIFO is moved to external system
99100  *
99101  * memory. This interrupt is generated only when the
99102  *
99103  * corresponding endpoint descriptor is closed, and the IOC
99104  *
99105  * bit For the corresponding descriptor is Set.
99106  *
99107  * When Scatter/Gather DMA mode is disabled, this field
99108  *
99109  * indicates that the programmed transfer is complete on the
99110  *
99111  * AHB as well as on the USB, For this endpoint.
99112  *
99113  * Field Enumeration Values:
99114  *
99115  * Enum | Value | Description
99116  * :----------------------------------------|:------|:-----------------------------
99117  * ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_INACT | 0x0 | No Interrupt
99118  * ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
99119  *
99120  * Field Access Macros:
99121  *
99122  */
99123 /*
99124  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_XFERCOMPL
99125  *
99126  * No Interrupt
99127  */
99128 #define ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_INACT 0x0
99129 /*
99130  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_XFERCOMPL
99131  *
99132  * Transfer Completed Interrupt
99133  */
99134 #define ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_ACT 0x1
99135 
99136 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */
99137 #define ALT_USB_DEV_DIEPINT13_XFERCOMPL_LSB 0
99138 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */
99139 #define ALT_USB_DEV_DIEPINT13_XFERCOMPL_MSB 0
99140 /* The width in bits of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */
99141 #define ALT_USB_DEV_DIEPINT13_XFERCOMPL_WIDTH 1
99142 /* The mask used to set the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field value. */
99143 #define ALT_USB_DEV_DIEPINT13_XFERCOMPL_SET_MSK 0x00000001
99144 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field value. */
99145 #define ALT_USB_DEV_DIEPINT13_XFERCOMPL_CLR_MSK 0xfffffffe
99146 /* The reset value of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */
99147 #define ALT_USB_DEV_DIEPINT13_XFERCOMPL_RESET 0x0
99148 /* Extracts the ALT_USB_DEV_DIEPINT13_XFERCOMPL field value from a register. */
99149 #define ALT_USB_DEV_DIEPINT13_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
99150 /* Produces a ALT_USB_DEV_DIEPINT13_XFERCOMPL register field value suitable for setting the register. */
99151 #define ALT_USB_DEV_DIEPINT13_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
99152 
99153 /*
99154  * Field : epdisbld
99155  *
99156  * Endpoint Disabled Interrupt (EPDisbld)
99157  *
99158  * Applies to IN and OUT endpoints.
99159  *
99160  * This bit indicates that the endpoint is disabled per the
99161  *
99162  * application's request.
99163  *
99164  * Field Enumeration Values:
99165  *
99166  * Enum | Value | Description
99167  * :---------------------------------------|:------|:----------------------------
99168  * ALT_USB_DEV_DIEPINT13_EPDISBLD_E_INACT | 0x0 | No Interrupt
99169  * ALT_USB_DEV_DIEPINT13_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
99170  *
99171  * Field Access Macros:
99172  *
99173  */
99174 /*
99175  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_EPDISBLD
99176  *
99177  * No Interrupt
99178  */
99179 #define ALT_USB_DEV_DIEPINT13_EPDISBLD_E_INACT 0x0
99180 /*
99181  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_EPDISBLD
99182  *
99183  * Endpoint Disabled Interrupt
99184  */
99185 #define ALT_USB_DEV_DIEPINT13_EPDISBLD_E_ACT 0x1
99186 
99187 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */
99188 #define ALT_USB_DEV_DIEPINT13_EPDISBLD_LSB 1
99189 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */
99190 #define ALT_USB_DEV_DIEPINT13_EPDISBLD_MSB 1
99191 /* The width in bits of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */
99192 #define ALT_USB_DEV_DIEPINT13_EPDISBLD_WIDTH 1
99193 /* The mask used to set the ALT_USB_DEV_DIEPINT13_EPDISBLD register field value. */
99194 #define ALT_USB_DEV_DIEPINT13_EPDISBLD_SET_MSK 0x00000002
99195 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_EPDISBLD register field value. */
99196 #define ALT_USB_DEV_DIEPINT13_EPDISBLD_CLR_MSK 0xfffffffd
99197 /* The reset value of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */
99198 #define ALT_USB_DEV_DIEPINT13_EPDISBLD_RESET 0x0
99199 /* Extracts the ALT_USB_DEV_DIEPINT13_EPDISBLD field value from a register. */
99200 #define ALT_USB_DEV_DIEPINT13_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
99201 /* Produces a ALT_USB_DEV_DIEPINT13_EPDISBLD register field value suitable for setting the register. */
99202 #define ALT_USB_DEV_DIEPINT13_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
99203 
99204 /*
99205  * Field : ahberr
99206  *
99207  * AHB Error (AHBErr)
99208  *
99209  * Applies to IN and OUT endpoints.
99210  *
99211  * This is generated only in Internal DMA mode when there is an
99212  *
99213  * AHB error during an AHB read/write. The application can read
99214  *
99215  * the corresponding endpoint DMA address register to get the
99216  *
99217  * error address.
99218  *
99219  * Field Enumeration Values:
99220  *
99221  * Enum | Value | Description
99222  * :-------------------------------------|:------|:--------------------
99223  * ALT_USB_DEV_DIEPINT13_AHBERR_E_INACT | 0x0 | No Interrupt
99224  * ALT_USB_DEV_DIEPINT13_AHBERR_E_ACT | 0x1 | AHB Error interrupt
99225  *
99226  * Field Access Macros:
99227  *
99228  */
99229 /*
99230  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_AHBERR
99231  *
99232  * No Interrupt
99233  */
99234 #define ALT_USB_DEV_DIEPINT13_AHBERR_E_INACT 0x0
99235 /*
99236  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_AHBERR
99237  *
99238  * AHB Error interrupt
99239  */
99240 #define ALT_USB_DEV_DIEPINT13_AHBERR_E_ACT 0x1
99241 
99242 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */
99243 #define ALT_USB_DEV_DIEPINT13_AHBERR_LSB 2
99244 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */
99245 #define ALT_USB_DEV_DIEPINT13_AHBERR_MSB 2
99246 /* The width in bits of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */
99247 #define ALT_USB_DEV_DIEPINT13_AHBERR_WIDTH 1
99248 /* The mask used to set the ALT_USB_DEV_DIEPINT13_AHBERR register field value. */
99249 #define ALT_USB_DEV_DIEPINT13_AHBERR_SET_MSK 0x00000004
99250 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_AHBERR register field value. */
99251 #define ALT_USB_DEV_DIEPINT13_AHBERR_CLR_MSK 0xfffffffb
99252 /* The reset value of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */
99253 #define ALT_USB_DEV_DIEPINT13_AHBERR_RESET 0x0
99254 /* Extracts the ALT_USB_DEV_DIEPINT13_AHBERR field value from a register. */
99255 #define ALT_USB_DEV_DIEPINT13_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
99256 /* Produces a ALT_USB_DEV_DIEPINT13_AHBERR register field value suitable for setting the register. */
99257 #define ALT_USB_DEV_DIEPINT13_AHBERR_SET(value) (((value) << 2) & 0x00000004)
99258 
99259 /*
99260  * Field : timeout
99261  *
99262  * Timeout Condition (TimeOUT)
99263  *
99264  * In shared TX FIFO mode, applies to non-isochronous IN
99265  *
99266  * endpoints only.
99267  *
99268  * In dedicated FIFO mode, applies only to Control IN
99269  *
99270  * endpoints.
99271  *
99272  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
99273  *
99274  * asserted.
99275  *
99276  * Indicates that the core has detected a timeout condition on the
99277  *
99278  * USB For the last IN token on this endpoint.
99279  *
99280  * Field Enumeration Values:
99281  *
99282  * Enum | Value | Description
99283  * :----------------------------------|:------|:------------------
99284  * ALT_USB_DEV_DIEPINT13_TMO_E_INACT | 0x0 | No interrupt
99285  * ALT_USB_DEV_DIEPINT13_TMO_E_ACT | 0x1 | Timeout interrupy
99286  *
99287  * Field Access Macros:
99288  *
99289  */
99290 /*
99291  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TMO
99292  *
99293  * No interrupt
99294  */
99295 #define ALT_USB_DEV_DIEPINT13_TMO_E_INACT 0x0
99296 /*
99297  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TMO
99298  *
99299  * Timeout interrupy
99300  */
99301 #define ALT_USB_DEV_DIEPINT13_TMO_E_ACT 0x1
99302 
99303 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_TMO register field. */
99304 #define ALT_USB_DEV_DIEPINT13_TMO_LSB 3
99305 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_TMO register field. */
99306 #define ALT_USB_DEV_DIEPINT13_TMO_MSB 3
99307 /* The width in bits of the ALT_USB_DEV_DIEPINT13_TMO register field. */
99308 #define ALT_USB_DEV_DIEPINT13_TMO_WIDTH 1
99309 /* The mask used to set the ALT_USB_DEV_DIEPINT13_TMO register field value. */
99310 #define ALT_USB_DEV_DIEPINT13_TMO_SET_MSK 0x00000008
99311 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_TMO register field value. */
99312 #define ALT_USB_DEV_DIEPINT13_TMO_CLR_MSK 0xfffffff7
99313 /* The reset value of the ALT_USB_DEV_DIEPINT13_TMO register field. */
99314 #define ALT_USB_DEV_DIEPINT13_TMO_RESET 0x0
99315 /* Extracts the ALT_USB_DEV_DIEPINT13_TMO field value from a register. */
99316 #define ALT_USB_DEV_DIEPINT13_TMO_GET(value) (((value) & 0x00000008) >> 3)
99317 /* Produces a ALT_USB_DEV_DIEPINT13_TMO register field value suitable for setting the register. */
99318 #define ALT_USB_DEV_DIEPINT13_TMO_SET(value) (((value) << 3) & 0x00000008)
99319 
99320 /*
99321  * Field : intkntxfemp
99322  *
99323  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
99324  *
99325  * Applies to non-periodic IN endpoints only.
99326  *
99327  * Indicates that an IN token was received when the associated
99328  *
99329  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
99330  *
99331  * asserted on the endpoint For which the IN token was received.
99332  *
99333  * Field Enumeration Values:
99334  *
99335  * Enum | Value | Description
99336  * :------------------------------------------|:------|:----------------------------
99337  * ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
99338  * ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
99339  *
99340  * Field Access Macros:
99341  *
99342  */
99343 /*
99344  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNTXFEMP
99345  *
99346  * No interrupt
99347  */
99348 #define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_INACT 0x0
99349 /*
99350  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNTXFEMP
99351  *
99352  * IN Token Received Interrupt
99353  */
99354 #define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_ACT 0x1
99355 
99356 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */
99357 #define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_LSB 4
99358 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */
99359 #define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_MSB 4
99360 /* The width in bits of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */
99361 #define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_WIDTH 1
99362 /* The mask used to set the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field value. */
99363 #define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_SET_MSK 0x00000010
99364 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field value. */
99365 #define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_CLR_MSK 0xffffffef
99366 /* The reset value of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */
99367 #define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_RESET 0x0
99368 /* Extracts the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP field value from a register. */
99369 #define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
99370 /* Produces a ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field value suitable for setting the register. */
99371 #define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
99372 
99373 /*
99374  * Field : intknepmis
99375  *
99376  * IN Token Received with EP Mismatch (INTknEPMis)
99377  *
99378  * Applies to non-periodic IN endpoints only.
99379  *
99380  * Indicates that the data in the top of the non-periodic TxFIFO
99381  *
99382  * belongs to an endpoint other than the one For which the IN token
99383  *
99384  * was received. This interrupt is asserted on the endpoint For
99385  *
99386  * which the IN token was received.
99387  *
99388  * Field Enumeration Values:
99389  *
99390  * Enum | Value | Description
99391  * :-----------------------------------------|:------|:---------------------------------------------
99392  * ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_INACT | 0x0 | No interrupt
99393  * ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
99394  *
99395  * Field Access Macros:
99396  *
99397  */
99398 /*
99399  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNEPMIS
99400  *
99401  * No interrupt
99402  */
99403 #define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_INACT 0x0
99404 /*
99405  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNEPMIS
99406  *
99407  * IN Token Received with EP Mismatch interrupt
99408  */
99409 #define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_ACT 0x1
99410 
99411 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */
99412 #define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_LSB 5
99413 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */
99414 #define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_MSB 5
99415 /* The width in bits of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */
99416 #define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_WIDTH 1
99417 /* The mask used to set the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field value. */
99418 #define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_SET_MSK 0x00000020
99419 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field value. */
99420 #define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_CLR_MSK 0xffffffdf
99421 /* The reset value of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */
99422 #define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_RESET 0x0
99423 /* Extracts the ALT_USB_DEV_DIEPINT13_INTKNEPMIS field value from a register. */
99424 #define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
99425 /* Produces a ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field value suitable for setting the register. */
99426 #define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
99427 
99428 /*
99429  * Field : inepnakeff
99430  *
99431  * IN Endpoint NAK Effective (INEPNakEff)
99432  *
99433  * Applies to periodic IN endpoints only.
99434  *
99435  * This bit can be cleared when the application clears the IN
99436  *
99437  * endpoint NAK by writing to DIEPCTLn.CNAK.
99438  *
99439  * This interrupt indicates that the core has sampled the NAK bit
99440  *
99441  * Set (either by the application or by the core). The interrupt
99442  *
99443  * indicates that the IN endpoint NAK bit Set by the application has
99444  *
99445  * taken effect in the core.
99446  *
99447  * This interrupt does not guarantee that a NAK handshake is sent
99448  *
99449  * on the USB. A STALL bit takes priority over a NAK bit.
99450  *
99451  * Field Enumeration Values:
99452  *
99453  * Enum | Value | Description
99454  * :-----------------------------------------|:------|:------------------------------------
99455  * ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_INACT | 0x0 | No interrupt
99456  * ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
99457  *
99458  * Field Access Macros:
99459  *
99460  */
99461 /*
99462  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INEPNAKEFF
99463  *
99464  * No interrupt
99465  */
99466 #define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_INACT 0x0
99467 /*
99468  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_INEPNAKEFF
99469  *
99470  * IN Endpoint NAK Effective interrupt
99471  */
99472 #define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_ACT 0x1
99473 
99474 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */
99475 #define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_LSB 6
99476 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */
99477 #define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_MSB 6
99478 /* The width in bits of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */
99479 #define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_WIDTH 1
99480 /* The mask used to set the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field value. */
99481 #define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_SET_MSK 0x00000040
99482 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field value. */
99483 #define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_CLR_MSK 0xffffffbf
99484 /* The reset value of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */
99485 #define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_RESET 0x0
99486 /* Extracts the ALT_USB_DEV_DIEPINT13_INEPNAKEFF field value from a register. */
99487 #define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
99488 /* Produces a ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field value suitable for setting the register. */
99489 #define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
99490 
99491 /*
99492  * Field : txfemp
99493  *
99494  * Transmit FIFO Empty (TxFEmp)
99495  *
99496  * This bit is valid only For IN Endpoints
99497  *
99498  * This interrupt is asserted when the TxFIFO For this endpoint is
99499  *
99500  * either half or completely empty. The half or completely empty
99501  *
99502  * status is determined by the TxFIFO Empty Level bit in the Core
99503  *
99504  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
99505  *
99506  * Field Enumeration Values:
99507  *
99508  * Enum | Value | Description
99509  * :-------------------------------------|:------|:------------------------------
99510  * ALT_USB_DEV_DIEPINT13_TXFEMP_E_INACT | 0x0 | No interrupt
99511  * ALT_USB_DEV_DIEPINT13_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
99512  *
99513  * Field Access Macros:
99514  *
99515  */
99516 /*
99517  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFEMP
99518  *
99519  * No interrupt
99520  */
99521 #define ALT_USB_DEV_DIEPINT13_TXFEMP_E_INACT 0x0
99522 /*
99523  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFEMP
99524  *
99525  * Transmit FIFO Empty interrupt
99526  */
99527 #define ALT_USB_DEV_DIEPINT13_TXFEMP_E_ACT 0x1
99528 
99529 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */
99530 #define ALT_USB_DEV_DIEPINT13_TXFEMP_LSB 7
99531 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */
99532 #define ALT_USB_DEV_DIEPINT13_TXFEMP_MSB 7
99533 /* The width in bits of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */
99534 #define ALT_USB_DEV_DIEPINT13_TXFEMP_WIDTH 1
99535 /* The mask used to set the ALT_USB_DEV_DIEPINT13_TXFEMP register field value. */
99536 #define ALT_USB_DEV_DIEPINT13_TXFEMP_SET_MSK 0x00000080
99537 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_TXFEMP register field value. */
99538 #define ALT_USB_DEV_DIEPINT13_TXFEMP_CLR_MSK 0xffffff7f
99539 /* The reset value of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */
99540 #define ALT_USB_DEV_DIEPINT13_TXFEMP_RESET 0x1
99541 /* Extracts the ALT_USB_DEV_DIEPINT13_TXFEMP field value from a register. */
99542 #define ALT_USB_DEV_DIEPINT13_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
99543 /* Produces a ALT_USB_DEV_DIEPINT13_TXFEMP register field value suitable for setting the register. */
99544 #define ALT_USB_DEV_DIEPINT13_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
99545 
99546 /*
99547  * Field : txfifoundrn
99548  *
99549  * Fifo Underrun (TxfifoUndrn)
99550  *
99551  * Applies to IN endpoints Only
99552  *
99553  * This bit is valid only If thresholding is enabled. The core generates this
99554  * interrupt when
99555  *
99556  * it detects a transmit FIFO underrun condition For this endpoint.
99557  *
99558  * Field Enumeration Values:
99559  *
99560  * Enum | Value | Description
99561  * :------------------------------------------|:------|:------------------------
99562  * ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
99563  * ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
99564  *
99565  * Field Access Macros:
99566  *
99567  */
99568 /*
99569  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN
99570  *
99571  * No interrupt
99572  */
99573 #define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_INACT 0x0
99574 /*
99575  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN
99576  *
99577  * Fifo Underrun interrupt
99578  */
99579 #define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_ACT 0x1
99580 
99581 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */
99582 #define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_LSB 8
99583 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */
99584 #define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_MSB 8
99585 /* The width in bits of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */
99586 #define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_WIDTH 1
99587 /* The mask used to set the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field value. */
99588 #define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_SET_MSK 0x00000100
99589 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field value. */
99590 #define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_CLR_MSK 0xfffffeff
99591 /* The reset value of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */
99592 #define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_RESET 0x0
99593 /* Extracts the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN field value from a register. */
99594 #define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
99595 /* Produces a ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field value suitable for setting the register. */
99596 #define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
99597 
99598 /*
99599  * Field : bnaintr
99600  *
99601  * BNA (Buffer Not Available) Interrupt (BNAIntr)
99602  *
99603  * This bit is valid only when Scatter/Gather DMA mode is enabled.
99604  *
99605  * The core generates this interrupt when the descriptor accessed
99606  *
99607  * is not ready For the Core to process, such as Host busy or DMA
99608  *
99609  * done
99610  *
99611  * Field Enumeration Values:
99612  *
99613  * Enum | Value | Description
99614  * :--------------------------------------|:------|:--------------
99615  * ALT_USB_DEV_DIEPINT13_BNAINTR_E_INACT | 0x0 | No interrupt
99616  * ALT_USB_DEV_DIEPINT13_BNAINTR_E_ACT | 0x1 | BNA interrupt
99617  *
99618  * Field Access Macros:
99619  *
99620  */
99621 /*
99622  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_BNAINTR
99623  *
99624  * No interrupt
99625  */
99626 #define ALT_USB_DEV_DIEPINT13_BNAINTR_E_INACT 0x0
99627 /*
99628  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_BNAINTR
99629  *
99630  * BNA interrupt
99631  */
99632 #define ALT_USB_DEV_DIEPINT13_BNAINTR_E_ACT 0x1
99633 
99634 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */
99635 #define ALT_USB_DEV_DIEPINT13_BNAINTR_LSB 9
99636 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */
99637 #define ALT_USB_DEV_DIEPINT13_BNAINTR_MSB 9
99638 /* The width in bits of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */
99639 #define ALT_USB_DEV_DIEPINT13_BNAINTR_WIDTH 1
99640 /* The mask used to set the ALT_USB_DEV_DIEPINT13_BNAINTR register field value. */
99641 #define ALT_USB_DEV_DIEPINT13_BNAINTR_SET_MSK 0x00000200
99642 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_BNAINTR register field value. */
99643 #define ALT_USB_DEV_DIEPINT13_BNAINTR_CLR_MSK 0xfffffdff
99644 /* The reset value of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */
99645 #define ALT_USB_DEV_DIEPINT13_BNAINTR_RESET 0x0
99646 /* Extracts the ALT_USB_DEV_DIEPINT13_BNAINTR field value from a register. */
99647 #define ALT_USB_DEV_DIEPINT13_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
99648 /* Produces a ALT_USB_DEV_DIEPINT13_BNAINTR register field value suitable for setting the register. */
99649 #define ALT_USB_DEV_DIEPINT13_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
99650 
99651 /*
99652  * Field : pktdrpsts
99653  *
99654  * Packet Drop Status (PktDrpSts)
99655  *
99656  * This bit indicates to the application that an ISOC OUT packet has been dropped.
99657  * This
99658  *
99659  * bit does not have an associated mask bit and does not generate an interrupt.
99660  *
99661  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
99662  * transfer
99663  *
99664  * interrupt feature is selected.
99665  *
99666  * Field Enumeration Values:
99667  *
99668  * Enum | Value | Description
99669  * :----------------------------------------|:------|:-----------------------------
99670  * ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_INACT | 0x0 | No interrupt
99671  * ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
99672  *
99673  * Field Access Macros:
99674  *
99675  */
99676 /*
99677  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_PKTDRPSTS
99678  *
99679  * No interrupt
99680  */
99681 #define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_INACT 0x0
99682 /*
99683  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_PKTDRPSTS
99684  *
99685  * Packet Drop Status interrupt
99686  */
99687 #define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_ACT 0x1
99688 
99689 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */
99690 #define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_LSB 11
99691 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */
99692 #define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_MSB 11
99693 /* The width in bits of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */
99694 #define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_WIDTH 1
99695 /* The mask used to set the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field value. */
99696 #define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_SET_MSK 0x00000800
99697 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field value. */
99698 #define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_CLR_MSK 0xfffff7ff
99699 /* The reset value of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */
99700 #define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_RESET 0x0
99701 /* Extracts the ALT_USB_DEV_DIEPINT13_PKTDRPSTS field value from a register. */
99702 #define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
99703 /* Produces a ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field value suitable for setting the register. */
99704 #define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
99705 
99706 /*
99707  * Field : bbleerr
99708  *
99709  * NAK Interrupt (BbleErr)
99710  *
99711  * The core generates this interrupt when babble is received for the endpoint.
99712  *
99713  * Field Enumeration Values:
99714  *
99715  * Enum | Value | Description
99716  * :--------------------------------------|:------|:------------------
99717  * ALT_USB_DEV_DIEPINT13_BBLEERR_E_INACT | 0x0 | No interrupt
99718  * ALT_USB_DEV_DIEPINT13_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
99719  *
99720  * Field Access Macros:
99721  *
99722  */
99723 /*
99724  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_BBLEERR
99725  *
99726  * No interrupt
99727  */
99728 #define ALT_USB_DEV_DIEPINT13_BBLEERR_E_INACT 0x0
99729 /*
99730  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_BBLEERR
99731  *
99732  * BbleErr interrupt
99733  */
99734 #define ALT_USB_DEV_DIEPINT13_BBLEERR_E_ACT 0x1
99735 
99736 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */
99737 #define ALT_USB_DEV_DIEPINT13_BBLEERR_LSB 12
99738 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */
99739 #define ALT_USB_DEV_DIEPINT13_BBLEERR_MSB 12
99740 /* The width in bits of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */
99741 #define ALT_USB_DEV_DIEPINT13_BBLEERR_WIDTH 1
99742 /* The mask used to set the ALT_USB_DEV_DIEPINT13_BBLEERR register field value. */
99743 #define ALT_USB_DEV_DIEPINT13_BBLEERR_SET_MSK 0x00001000
99744 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_BBLEERR register field value. */
99745 #define ALT_USB_DEV_DIEPINT13_BBLEERR_CLR_MSK 0xffffefff
99746 /* The reset value of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */
99747 #define ALT_USB_DEV_DIEPINT13_BBLEERR_RESET 0x0
99748 /* Extracts the ALT_USB_DEV_DIEPINT13_BBLEERR field value from a register. */
99749 #define ALT_USB_DEV_DIEPINT13_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
99750 /* Produces a ALT_USB_DEV_DIEPINT13_BBLEERR register field value suitable for setting the register. */
99751 #define ALT_USB_DEV_DIEPINT13_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
99752 
99753 /*
99754  * Field : nakintrpt
99755  *
99756  * NAK Interrupt (NAKInterrupt)
99757  *
99758  * The core generates this interrupt when a NAK is transmitted or received by the
99759  * device.
99760  *
99761  * In case of isochronous IN endpoints the interrupt gets generated when a zero
99762  * length
99763  *
99764  * packet is transmitted due to un-availability of data in the TXFifo.
99765  *
99766  * Field Enumeration Values:
99767  *
99768  * Enum | Value | Description
99769  * :----------------------------------------|:------|:--------------
99770  * ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_INACT | 0x0 | No interrupt
99771  * ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
99772  *
99773  * Field Access Macros:
99774  *
99775  */
99776 /*
99777  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_NAKINTRPT
99778  *
99779  * No interrupt
99780  */
99781 #define ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_INACT 0x0
99782 /*
99783  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_NAKINTRPT
99784  *
99785  * NAK Interrupt
99786  */
99787 #define ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_ACT 0x1
99788 
99789 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */
99790 #define ALT_USB_DEV_DIEPINT13_NAKINTRPT_LSB 13
99791 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */
99792 #define ALT_USB_DEV_DIEPINT13_NAKINTRPT_MSB 13
99793 /* The width in bits of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */
99794 #define ALT_USB_DEV_DIEPINT13_NAKINTRPT_WIDTH 1
99795 /* The mask used to set the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field value. */
99796 #define ALT_USB_DEV_DIEPINT13_NAKINTRPT_SET_MSK 0x00002000
99797 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field value. */
99798 #define ALT_USB_DEV_DIEPINT13_NAKINTRPT_CLR_MSK 0xffffdfff
99799 /* The reset value of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */
99800 #define ALT_USB_DEV_DIEPINT13_NAKINTRPT_RESET 0x0
99801 /* Extracts the ALT_USB_DEV_DIEPINT13_NAKINTRPT field value from a register. */
99802 #define ALT_USB_DEV_DIEPINT13_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
99803 /* Produces a ALT_USB_DEV_DIEPINT13_NAKINTRPT register field value suitable for setting the register. */
99804 #define ALT_USB_DEV_DIEPINT13_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
99805 
99806 /*
99807  * Field : nyetintrpt
99808  *
99809  * NYET Interrupt (NYETIntrpt)
99810  *
99811  * The core generates this interrupt when a NYET response is transmitted for a non
99812  * isochronous OUT endpoint.
99813  *
99814  * Field Enumeration Values:
99815  *
99816  * Enum | Value | Description
99817  * :-----------------------------------------|:------|:---------------
99818  * ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_INACT | 0x0 | No interrupt
99819  * ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
99820  *
99821  * Field Access Macros:
99822  *
99823  */
99824 /*
99825  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_NYETINTRPT
99826  *
99827  * No interrupt
99828  */
99829 #define ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_INACT 0x0
99830 /*
99831  * Enumerated value for register field ALT_USB_DEV_DIEPINT13_NYETINTRPT
99832  *
99833  * NYET Interrupt
99834  */
99835 #define ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_ACT 0x1
99836 
99837 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */
99838 #define ALT_USB_DEV_DIEPINT13_NYETINTRPT_LSB 14
99839 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */
99840 #define ALT_USB_DEV_DIEPINT13_NYETINTRPT_MSB 14
99841 /* The width in bits of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */
99842 #define ALT_USB_DEV_DIEPINT13_NYETINTRPT_WIDTH 1
99843 /* The mask used to set the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field value. */
99844 #define ALT_USB_DEV_DIEPINT13_NYETINTRPT_SET_MSK 0x00004000
99845 /* The mask used to clear the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field value. */
99846 #define ALT_USB_DEV_DIEPINT13_NYETINTRPT_CLR_MSK 0xffffbfff
99847 /* The reset value of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */
99848 #define ALT_USB_DEV_DIEPINT13_NYETINTRPT_RESET 0x0
99849 /* Extracts the ALT_USB_DEV_DIEPINT13_NYETINTRPT field value from a register. */
99850 #define ALT_USB_DEV_DIEPINT13_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
99851 /* Produces a ALT_USB_DEV_DIEPINT13_NYETINTRPT register field value suitable for setting the register. */
99852 #define ALT_USB_DEV_DIEPINT13_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
99853 
99854 #ifndef __ASSEMBLY__
99855 /*
99856  * WARNING: The C register and register group struct declarations are provided for
99857  * convenience and illustrative purposes. They should, however, be used with
99858  * caution as the C language standard provides no guarantees about the alignment or
99859  * atomicity of device memory accesses. The recommended practice for writing
99860  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
99861  * alt_write_word() functions.
99862  *
99863  * The struct declaration for register ALT_USB_DEV_DIEPINT13.
99864  */
99865 struct ALT_USB_DEV_DIEPINT13_s
99866 {
99867  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT13_XFERCOMPL */
99868  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT13_EPDISBLD */
99869  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT13_AHBERR */
99870  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT13_TMO */
99871  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT13_INTKNTXFEMP */
99872  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT13_INTKNEPMIS */
99873  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT13_INEPNAKEFF */
99874  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT13_TXFEMP */
99875  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN */
99876  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT13_BNAINTR */
99877  uint32_t : 1; /* *UNDEFINED* */
99878  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT13_PKTDRPSTS */
99879  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT13_BBLEERR */
99880  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT13_NAKINTRPT */
99881  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT13_NYETINTRPT */
99882  uint32_t : 17; /* *UNDEFINED* */
99883 };
99884 
99885 /* The typedef declaration for register ALT_USB_DEV_DIEPINT13. */
99886 typedef volatile struct ALT_USB_DEV_DIEPINT13_s ALT_USB_DEV_DIEPINT13_t;
99887 #endif /* __ASSEMBLY__ */
99888 
99889 /* The reset value of the ALT_USB_DEV_DIEPINT13 register. */
99890 #define ALT_USB_DEV_DIEPINT13_RESET 0x00000080
99891 /* The byte offset of the ALT_USB_DEV_DIEPINT13 register from the beginning of the component. */
99892 #define ALT_USB_DEV_DIEPINT13_OFST 0x2a8
99893 /* The address of the ALT_USB_DEV_DIEPINT13 register. */
99894 #define ALT_USB_DEV_DIEPINT13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT13_OFST))
99895 
99896 /*
99897  * Register : dieptsiz13
99898  *
99899  * Device IN Endpoint 13 Transfer Size Register
99900  *
99901  * Register Layout
99902  *
99903  * Bits | Access | Reset | Description
99904  * :--------|:-------|:------|:--------------------------------
99905  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ13_XFERSIZE
99906  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ13_PKTCNT
99907  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ13_MC
99908  * [31] | ??? | 0x0 | *UNDEFINED*
99909  *
99910  */
99911 /*
99912  * Field : xfersize
99913  *
99914  * Transfer Size (XferSize)
99915  *
99916  * Indicates the transfer size in bytes For endpoint 0. The core
99917  *
99918  * interrupts the application only after it has exhausted the transfer
99919  *
99920  * size amount of data. The transfer size can be Set to the
99921  *
99922  * maximum packet size of the endpoint, to be interrupted at the
99923  *
99924  * end of each packet.
99925  *
99926  * The core decrements this field every time a packet from the
99927  *
99928  * external memory is written to the TxFIFO.
99929  *
99930  * Field Access Macros:
99931  *
99932  */
99933 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */
99934 #define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_LSB 0
99935 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */
99936 #define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_MSB 18
99937 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */
99938 #define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_WIDTH 19
99939 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field value. */
99940 #define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_SET_MSK 0x0007ffff
99941 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field value. */
99942 #define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_CLR_MSK 0xfff80000
99943 /* The reset value of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */
99944 #define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_RESET 0x0
99945 /* Extracts the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE field value from a register. */
99946 #define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
99947 /* Produces a ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field value suitable for setting the register. */
99948 #define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
99949 
99950 /*
99951  * Field : pktcnt
99952  *
99953  * Packet Count (PktCnt)
99954  *
99955  * Indicates the total number of USB packets that constitute the
99956  *
99957  * Transfer Size amount of data For endpoint 0.
99958  *
99959  * This field is decremented every time a packet (maximum size or
99960  *
99961  * short packet) is read from the TxFIFO.
99962  *
99963  * Field Access Macros:
99964  *
99965  */
99966 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */
99967 #define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_LSB 19
99968 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */
99969 #define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_MSB 28
99970 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */
99971 #define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_WIDTH 10
99972 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field value. */
99973 #define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_SET_MSK 0x1ff80000
99974 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field value. */
99975 #define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_CLR_MSK 0xe007ffff
99976 /* The reset value of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */
99977 #define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_RESET 0x0
99978 /* Extracts the ALT_USB_DEV_DIEPTSIZ13_PKTCNT field value from a register. */
99979 #define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
99980 /* Produces a ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field value suitable for setting the register. */
99981 #define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
99982 
99983 /*
99984  * Field : mc
99985  *
99986  * Applies to IN endpoints only.
99987  *
99988  * For periodic IN endpoints, this field indicates the number of packets that must
99989  * be transmitted per microframe on the USB. The core uses this field to calculate
99990  * the data PID for isochronous IN endpoints.
99991  *
99992  * 2'b01: 1 packet
99993  *
99994  * 2'b10: 2 packets
99995  *
99996  * 2'b11: 3 packets
99997  *
99998  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
99999  * specifies the number of packets the core must fetchfor an IN endpoint before it
100000  * switches to the endpoint pointed to by the Next Endpoint field of the Device
100001  * Endpoint-n Control register (DIEPCTLn.NextEp)
100002  *
100003  * Field Enumeration Values:
100004  *
100005  * Enum | Value | Description
100006  * :-------------------------------------|:------|:------------
100007  * ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTONE | 0x1 | 1 packet
100008  * ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTWO | 0x2 | 2 packets
100009  * ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTHREE | 0x3 | 3 packets
100010  *
100011  * Field Access Macros:
100012  *
100013  */
100014 /*
100015  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ13_MC
100016  *
100017  * 1 packet
100018  */
100019 #define ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTONE 0x1
100020 /*
100021  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ13_MC
100022  *
100023  * 2 packets
100024  */
100025 #define ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTWO 0x2
100026 /*
100027  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ13_MC
100028  *
100029  * 3 packets
100030  */
100031 #define ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTHREE 0x3
100032 
100033 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */
100034 #define ALT_USB_DEV_DIEPTSIZ13_MC_LSB 29
100035 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */
100036 #define ALT_USB_DEV_DIEPTSIZ13_MC_MSB 30
100037 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */
100038 #define ALT_USB_DEV_DIEPTSIZ13_MC_WIDTH 2
100039 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ13_MC register field value. */
100040 #define ALT_USB_DEV_DIEPTSIZ13_MC_SET_MSK 0x60000000
100041 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ13_MC register field value. */
100042 #define ALT_USB_DEV_DIEPTSIZ13_MC_CLR_MSK 0x9fffffff
100043 /* The reset value of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */
100044 #define ALT_USB_DEV_DIEPTSIZ13_MC_RESET 0x0
100045 /* Extracts the ALT_USB_DEV_DIEPTSIZ13_MC field value from a register. */
100046 #define ALT_USB_DEV_DIEPTSIZ13_MC_GET(value) (((value) & 0x60000000) >> 29)
100047 /* Produces a ALT_USB_DEV_DIEPTSIZ13_MC register field value suitable for setting the register. */
100048 #define ALT_USB_DEV_DIEPTSIZ13_MC_SET(value) (((value) << 29) & 0x60000000)
100049 
100050 #ifndef __ASSEMBLY__
100051 /*
100052  * WARNING: The C register and register group struct declarations are provided for
100053  * convenience and illustrative purposes. They should, however, be used with
100054  * caution as the C language standard provides no guarantees about the alignment or
100055  * atomicity of device memory accesses. The recommended practice for writing
100056  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
100057  * alt_write_word() functions.
100058  *
100059  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ13.
100060  */
100061 struct ALT_USB_DEV_DIEPTSIZ13_s
100062 {
100063  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ13_XFERSIZE */
100064  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ13_PKTCNT */
100065  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ13_MC */
100066  uint32_t : 1; /* *UNDEFINED* */
100067 };
100068 
100069 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ13. */
100070 typedef volatile struct ALT_USB_DEV_DIEPTSIZ13_s ALT_USB_DEV_DIEPTSIZ13_t;
100071 #endif /* __ASSEMBLY__ */
100072 
100073 /* The reset value of the ALT_USB_DEV_DIEPTSIZ13 register. */
100074 #define ALT_USB_DEV_DIEPTSIZ13_RESET 0x00000000
100075 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ13 register from the beginning of the component. */
100076 #define ALT_USB_DEV_DIEPTSIZ13_OFST 0x2b0
100077 /* The address of the ALT_USB_DEV_DIEPTSIZ13 register. */
100078 #define ALT_USB_DEV_DIEPTSIZ13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ13_OFST))
100079 
100080 /*
100081  * Register : diepdma13
100082  *
100083  * Device IN Endpoint 13 DMA Address Register
100084  *
100085  * Register Layout
100086  *
100087  * Bits | Access | Reset | Description
100088  * :-------|:-------|:--------|:--------------------------------
100089  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA13_DIEPDMA13
100090  *
100091  */
100092 /*
100093  * Field : diepdma13
100094  *
100095  * Holds the start address of the external memory for storing or fetching endpoint
100096  *
100097  * data.
100098  *
100099  * Note: For control endpoints, this field stores control OUT data packets as well
100100  * as
100101  *
100102  * SETUP transaction data packets. When more than three SETUP packets are
100103  *
100104  * received back-to-back, the SETUP data packet in the memory is overwritten.
100105  *
100106  * This register is incremented on every AHB transaction. The application can give
100107  *
100108  * only a DWORD-aligned address.
100109  *
100110  * When Scatter/Gather DMA mode is not enabled, the application programs the
100111  *
100112  * start address value in this field.
100113  *
100114  * When Scatter/Gather DMA mode is enabled, this field indicates the base
100115  *
100116  * pointer for the descriptor list.
100117  *
100118  * Field Access Macros:
100119  *
100120  */
100121 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field. */
100122 #define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_LSB 0
100123 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field. */
100124 #define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_MSB 31
100125 /* The width in bits of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field. */
100126 #define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_WIDTH 32
100127 /* The mask used to set the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field value. */
100128 #define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_SET_MSK 0xffffffff
100129 /* The mask used to clear the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field value. */
100130 #define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_CLR_MSK 0x00000000
100131 /* The reset value of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field is UNKNOWN. */
100132 #define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_RESET 0x0
100133 /* Extracts the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 field value from a register. */
100134 #define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_GET(value) (((value) & 0xffffffff) >> 0)
100135 /* Produces a ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field value suitable for setting the register. */
100136 #define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_SET(value) (((value) << 0) & 0xffffffff)
100137 
100138 #ifndef __ASSEMBLY__
100139 /*
100140  * WARNING: The C register and register group struct declarations are provided for
100141  * convenience and illustrative purposes. They should, however, be used with
100142  * caution as the C language standard provides no guarantees about the alignment or
100143  * atomicity of device memory accesses. The recommended practice for writing
100144  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
100145  * alt_write_word() functions.
100146  *
100147  * The struct declaration for register ALT_USB_DEV_DIEPDMA13.
100148  */
100149 struct ALT_USB_DEV_DIEPDMA13_s
100150 {
100151  uint32_t diepdma13 : 32; /* ALT_USB_DEV_DIEPDMA13_DIEPDMA13 */
100152 };
100153 
100154 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA13. */
100155 typedef volatile struct ALT_USB_DEV_DIEPDMA13_s ALT_USB_DEV_DIEPDMA13_t;
100156 #endif /* __ASSEMBLY__ */
100157 
100158 /* The reset value of the ALT_USB_DEV_DIEPDMA13 register. */
100159 #define ALT_USB_DEV_DIEPDMA13_RESET 0x00000000
100160 /* The byte offset of the ALT_USB_DEV_DIEPDMA13 register from the beginning of the component. */
100161 #define ALT_USB_DEV_DIEPDMA13_OFST 0x2b4
100162 /* The address of the ALT_USB_DEV_DIEPDMA13 register. */
100163 #define ALT_USB_DEV_DIEPDMA13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA13_OFST))
100164 
100165 /*
100166  * Register : dtxfsts13
100167  *
100168  * Device IN Endpoint Transmit FIFO Status Register 13
100169  *
100170  * Register Layout
100171  *
100172  * Bits | Access | Reset | Description
100173  * :--------|:-------|:-------|:--------------------------------------
100174  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL
100175  * [31:16] | ??? | 0x0 | *UNDEFINED*
100176  *
100177  */
100178 /*
100179  * Field : ineptxfspcavail
100180  *
100181  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
100182  *
100183  * Indicates the amount of free space available in the Endpoint
100184  *
100185  * TxFIFO.
100186  *
100187  * Values are in terms of 32-bit words.
100188  *
100189  * 16'h0: Endpoint TxFIFO is full
100190  *
100191  * 16'h1: 1 word available
100192  *
100193  * 16'h2: 2 words available
100194  *
100195  * 16'hn: n words available (where 0 n 32,768)
100196  *
100197  * 16'h8000: 32,768 words available
100198  *
100199  * Others: Reserved
100200  *
100201  * Field Access Macros:
100202  *
100203  */
100204 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */
100205 #define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_LSB 0
100206 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */
100207 #define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_MSB 15
100208 /* The width in bits of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */
100209 #define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_WIDTH 16
100210 /* The mask used to set the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field value. */
100211 #define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
100212 /* The mask used to clear the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field value. */
100213 #define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
100214 /* The reset value of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */
100215 #define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_RESET 0x2000
100216 /* Extracts the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL field value from a register. */
100217 #define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
100218 /* Produces a ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field value suitable for setting the register. */
100219 #define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
100220 
100221 #ifndef __ASSEMBLY__
100222 /*
100223  * WARNING: The C register and register group struct declarations are provided for
100224  * convenience and illustrative purposes. They should, however, be used with
100225  * caution as the C language standard provides no guarantees about the alignment or
100226  * atomicity of device memory accesses. The recommended practice for writing
100227  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
100228  * alt_write_word() functions.
100229  *
100230  * The struct declaration for register ALT_USB_DEV_DTXFSTS13.
100231  */
100232 struct ALT_USB_DEV_DTXFSTS13_s
100233 {
100234  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL */
100235  uint32_t : 16; /* *UNDEFINED* */
100236 };
100237 
100238 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS13. */
100239 typedef volatile struct ALT_USB_DEV_DTXFSTS13_s ALT_USB_DEV_DTXFSTS13_t;
100240 #endif /* __ASSEMBLY__ */
100241 
100242 /* The reset value of the ALT_USB_DEV_DTXFSTS13 register. */
100243 #define ALT_USB_DEV_DTXFSTS13_RESET 0x00002000
100244 /* The byte offset of the ALT_USB_DEV_DTXFSTS13 register from the beginning of the component. */
100245 #define ALT_USB_DEV_DTXFSTS13_OFST 0x2b8
100246 /* The address of the ALT_USB_DEV_DTXFSTS13 register. */
100247 #define ALT_USB_DEV_DTXFSTS13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS13_OFST))
100248 
100249 /*
100250  * Register : diepdmab13
100251  *
100252  * Device IN Endpoint 13 Buffer Address Register
100253  *
100254  * Register Layout
100255  *
100256  * Bits | Access | Reset | Description
100257  * :-------|:-------|:--------|:----------------------------------
100258  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13
100259  *
100260  */
100261 /*
100262  * Field : diepdmab13
100263  *
100264  * Holds the current buffer address.This register is updated as and when the data
100265  *
100266  * transfer for the corresponding end point is in progress.
100267  *
100268  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
100269  * is
100270  *
100271  * reserved.
100272  *
100273  * Field Access Macros:
100274  *
100275  */
100276 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field. */
100277 #define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_LSB 0
100278 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field. */
100279 #define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_MSB 31
100280 /* The width in bits of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field. */
100281 #define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_WIDTH 32
100282 /* The mask used to set the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field value. */
100283 #define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_SET_MSK 0xffffffff
100284 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field value. */
100285 #define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_CLR_MSK 0x00000000
100286 /* The reset value of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field is UNKNOWN. */
100287 #define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_RESET 0x0
100288 /* Extracts the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 field value from a register. */
100289 #define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_GET(value) (((value) & 0xffffffff) >> 0)
100290 /* Produces a ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field value suitable for setting the register. */
100291 #define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_SET(value) (((value) << 0) & 0xffffffff)
100292 
100293 #ifndef __ASSEMBLY__
100294 /*
100295  * WARNING: The C register and register group struct declarations are provided for
100296  * convenience and illustrative purposes. They should, however, be used with
100297  * caution as the C language standard provides no guarantees about the alignment or
100298  * atomicity of device memory accesses. The recommended practice for writing
100299  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
100300  * alt_write_word() functions.
100301  *
100302  * The struct declaration for register ALT_USB_DEV_DIEPDMAB13.
100303  */
100304 struct ALT_USB_DEV_DIEPDMAB13_s
100305 {
100306  const uint32_t diepdmab13 : 32; /* ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 */
100307 };
100308 
100309 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB13. */
100310 typedef volatile struct ALT_USB_DEV_DIEPDMAB13_s ALT_USB_DEV_DIEPDMAB13_t;
100311 #endif /* __ASSEMBLY__ */
100312 
100313 /* The reset value of the ALT_USB_DEV_DIEPDMAB13 register. */
100314 #define ALT_USB_DEV_DIEPDMAB13_RESET 0x00000000
100315 /* The byte offset of the ALT_USB_DEV_DIEPDMAB13 register from the beginning of the component. */
100316 #define ALT_USB_DEV_DIEPDMAB13_OFST 0x2bc
100317 /* The address of the ALT_USB_DEV_DIEPDMAB13 register. */
100318 #define ALT_USB_DEV_DIEPDMAB13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB13_OFST))
100319 
100320 /*
100321  * Register : diepctl14
100322  *
100323  * Device Control IN Endpoint 14 Control Register
100324  *
100325  * Register Layout
100326  *
100327  * Bits | Access | Reset | Description
100328  * :--------|:---------|:------|:-------------------------------
100329  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL14_MPS
100330  * [14:11] | ??? | 0x0 | *UNDEFINED*
100331  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL14_USBACTEP
100332  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL14_DPID
100333  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL14_NAKSTS
100334  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL14_EPTYPE
100335  * [20] | ??? | 0x0 | *UNDEFINED*
100336  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL14_STALL
100337  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL14_TXFNUM
100338  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL14_CNAK
100339  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL14_SNAK
100340  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL14_SETD0PID
100341  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL14_SETD1PID
100342  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL14_EPDIS
100343  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL14_EPENA
100344  *
100345  */
100346 /*
100347  * Field : mps
100348  *
100349  * Maximum Packet Size (MPS)
100350  *
100351  * The application must program this field with the maximum packet size for the
100352  * current
100353  *
100354  * logical endpoint. This value is in bytes.
100355  *
100356  * Field Access Macros:
100357  *
100358  */
100359 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_MPS register field. */
100360 #define ALT_USB_DEV_DIEPCTL14_MPS_LSB 0
100361 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_MPS register field. */
100362 #define ALT_USB_DEV_DIEPCTL14_MPS_MSB 10
100363 /* The width in bits of the ALT_USB_DEV_DIEPCTL14_MPS register field. */
100364 #define ALT_USB_DEV_DIEPCTL14_MPS_WIDTH 11
100365 /* The mask used to set the ALT_USB_DEV_DIEPCTL14_MPS register field value. */
100366 #define ALT_USB_DEV_DIEPCTL14_MPS_SET_MSK 0x000007ff
100367 /* The mask used to clear the ALT_USB_DEV_DIEPCTL14_MPS register field value. */
100368 #define ALT_USB_DEV_DIEPCTL14_MPS_CLR_MSK 0xfffff800
100369 /* The reset value of the ALT_USB_DEV_DIEPCTL14_MPS register field. */
100370 #define ALT_USB_DEV_DIEPCTL14_MPS_RESET 0x0
100371 /* Extracts the ALT_USB_DEV_DIEPCTL14_MPS field value from a register. */
100372 #define ALT_USB_DEV_DIEPCTL14_MPS_GET(value) (((value) & 0x000007ff) >> 0)
100373 /* Produces a ALT_USB_DEV_DIEPCTL14_MPS register field value suitable for setting the register. */
100374 #define ALT_USB_DEV_DIEPCTL14_MPS_SET(value) (((value) << 0) & 0x000007ff)
100375 
100376 /*
100377  * Field : usbactep
100378  *
100379  * USB Active Endpoint (USBActEP)
100380  *
100381  * Indicates whether this endpoint is active in the current configuration and
100382  * interface. The
100383  *
100384  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
100385  * reset. After
100386  *
100387  * receiving the SetConfiguration and SetInterface commands, the application must
100388  *
100389  * program endpoint registers accordingly and set this bit.
100390  *
100391  * Field Enumeration Values:
100392  *
100393  * Enum | Value | Description
100394  * :--------------------------------------|:------|:--------------------
100395  * ALT_USB_DEV_DIEPCTL14_USBACTEP_E_DISD | 0x0 | Not Active
100396  * ALT_USB_DEV_DIEPCTL14_USBACTEP_E_END | 0x1 | USB Active Endpoint
100397  *
100398  * Field Access Macros:
100399  *
100400  */
100401 /*
100402  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_USBACTEP
100403  *
100404  * Not Active
100405  */
100406 #define ALT_USB_DEV_DIEPCTL14_USBACTEP_E_DISD 0x0
100407 /*
100408  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_USBACTEP
100409  *
100410  * USB Active Endpoint
100411  */
100412 #define ALT_USB_DEV_DIEPCTL14_USBACTEP_E_END 0x1
100413 
100414 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */
100415 #define ALT_USB_DEV_DIEPCTL14_USBACTEP_LSB 15
100416 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */
100417 #define ALT_USB_DEV_DIEPCTL14_USBACTEP_MSB 15
100418 /* The width in bits of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */
100419 #define ALT_USB_DEV_DIEPCTL14_USBACTEP_WIDTH 1
100420 /* The mask used to set the ALT_USB_DEV_DIEPCTL14_USBACTEP register field value. */
100421 #define ALT_USB_DEV_DIEPCTL14_USBACTEP_SET_MSK 0x00008000
100422 /* The mask used to clear the ALT_USB_DEV_DIEPCTL14_USBACTEP register field value. */
100423 #define ALT_USB_DEV_DIEPCTL14_USBACTEP_CLR_MSK 0xffff7fff
100424 /* The reset value of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */
100425 #define ALT_USB_DEV_DIEPCTL14_USBACTEP_RESET 0x0
100426 /* Extracts the ALT_USB_DEV_DIEPCTL14_USBACTEP field value from a register. */
100427 #define ALT_USB_DEV_DIEPCTL14_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
100428 /* Produces a ALT_USB_DEV_DIEPCTL14_USBACTEP register field value suitable for setting the register. */
100429 #define ALT_USB_DEV_DIEPCTL14_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
100430 
100431 /*
100432  * Field : dpid
100433  *
100434  * Endpoint Data PID (DPID)
100435  *
100436  * Applies to interrupt/bulk IN and OUT endpoints only.
100437  *
100438  * Contains the PID of the packet to be received or transmitted on this endpoint.
100439  * The
100440  *
100441  * application must program the PID of the first packet to be received or
100442  * transmitted on
100443  *
100444  * this endpoint, after the endpoint is activated. The applications use the
100445  * SetD1PID and
100446  *
100447  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
100448  *
100449  * 1'b0: DATA0
100450  *
100451  * 1'b1: DATA1
100452  *
100453  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
100454  *
100455  * DMA mode.
100456  *
100457  * 1'b0 RO
100458  *
100459  * Even/Odd (Micro)Frame (EO_FrNum)
100460  *
100461  * In non-Scatter/Gather DMA mode:
100462  *
100463  * Applies to isochronous IN and OUT endpoints only.
100464  *
100465  * Indicates the (micro)frame number in which the core transmits/receives
100466  * isochronous
100467  *
100468  * data for this endpoint. The application must program the even/odd (micro) frame
100469  *
100470  * number in which it intends to transmit/receive isochronous data for this
100471  * endpoint using
100472  *
100473  * the SetEvnFr and SetOddFr fields in this register.
100474  *
100475  * 1'b0: Even (micro)frame
100476  *
100477  * 1'b1: Odd (micro)frame
100478  *
100479  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
100480  * number
100481  *
100482  * in which to send data is provided in the transmit descriptor structure. The
100483  * frame in
100484  *
100485  * which data is received is updated in receive descriptor structure.
100486  *
100487  * Field Enumeration Values:
100488  *
100489  * Enum | Value | Description
100490  * :-----------------------------------|:------|:-----------------------------
100491  * ALT_USB_DEV_DIEPCTL14_DPID_E_INACT | 0x0 | Endpoint Data PID not active
100492  * ALT_USB_DEV_DIEPCTL14_DPID_E_ACT | 0x1 | Endpoint Data PID active
100493  *
100494  * Field Access Macros:
100495  *
100496  */
100497 /*
100498  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_DPID
100499  *
100500  * Endpoint Data PID not active
100501  */
100502 #define ALT_USB_DEV_DIEPCTL14_DPID_E_INACT 0x0
100503 /*
100504  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_DPID
100505  *
100506  * Endpoint Data PID active
100507  */
100508 #define ALT_USB_DEV_DIEPCTL14_DPID_E_ACT 0x1
100509 
100510 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_DPID register field. */
100511 #define ALT_USB_DEV_DIEPCTL14_DPID_LSB 16
100512 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_DPID register field. */
100513 #define ALT_USB_DEV_DIEPCTL14_DPID_MSB 16
100514 /* The width in bits of the ALT_USB_DEV_DIEPCTL14_DPID register field. */
100515 #define ALT_USB_DEV_DIEPCTL14_DPID_WIDTH 1
100516 /* The mask used to set the ALT_USB_DEV_DIEPCTL14_DPID register field value. */
100517 #define ALT_USB_DEV_DIEPCTL14_DPID_SET_MSK 0x00010000
100518 /* The mask used to clear the ALT_USB_DEV_DIEPCTL14_DPID register field value. */
100519 #define ALT_USB_DEV_DIEPCTL14_DPID_CLR_MSK 0xfffeffff
100520 /* The reset value of the ALT_USB_DEV_DIEPCTL14_DPID register field. */
100521 #define ALT_USB_DEV_DIEPCTL14_DPID_RESET 0x0
100522 /* Extracts the ALT_USB_DEV_DIEPCTL14_DPID field value from a register. */
100523 #define ALT_USB_DEV_DIEPCTL14_DPID_GET(value) (((value) & 0x00010000) >> 16)
100524 /* Produces a ALT_USB_DEV_DIEPCTL14_DPID register field value suitable for setting the register. */
100525 #define ALT_USB_DEV_DIEPCTL14_DPID_SET(value) (((value) << 16) & 0x00010000)
100526 
100527 /*
100528  * Field : naksts
100529  *
100530  * NAK Status (NAKSts)
100531  *
100532  * Indicates the following:
100533  *
100534  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
100535  *
100536  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
100537  *
100538  * When either the application or the core sets this bit:
100539  *
100540  * The core stops receiving any data on an OUT endpoint, even if there is space in
100541  *
100542  * the RxFIFO to accommodate the incoming packet.
100543  *
100544  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
100545  *
100546  * endpoint, even if there data is available in the TxFIFO.
100547  *
100548  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
100549  *
100550  * if there data is available in the TxFIFO.
100551  *
100552  * Irrespective of this bit's setting, the core always responds to SETUP data
100553  * packets with
100554  *
100555  * an ACK handshake.
100556  *
100557  * Field Enumeration Values:
100558  *
100559  * Enum | Value | Description
100560  * :--------------------------------------|:------|:------------------------------------------------
100561  * ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
100562  * : | | based on the FIFO status
100563  * ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
100564  * : | | endpoint
100565  *
100566  * Field Access Macros:
100567  *
100568  */
100569 /*
100570  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_NAKSTS
100571  *
100572  * The core is transmitting non-NAK handshakes based on the FIFO status
100573  */
100574 #define ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NONNAK 0x0
100575 /*
100576  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_NAKSTS
100577  *
100578  * The core is transmitting NAK handshakes on this endpoint
100579  */
100580 #define ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NAK 0x1
100581 
100582 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */
100583 #define ALT_USB_DEV_DIEPCTL14_NAKSTS_LSB 17
100584 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */
100585 #define ALT_USB_DEV_DIEPCTL14_NAKSTS_MSB 17
100586 /* The width in bits of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */
100587 #define ALT_USB_DEV_DIEPCTL14_NAKSTS_WIDTH 1
100588 /* The mask used to set the ALT_USB_DEV_DIEPCTL14_NAKSTS register field value. */
100589 #define ALT_USB_DEV_DIEPCTL14_NAKSTS_SET_MSK 0x00020000
100590 /* The mask used to clear the ALT_USB_DEV_DIEPCTL14_NAKSTS register field value. */
100591 #define ALT_USB_DEV_DIEPCTL14_NAKSTS_CLR_MSK 0xfffdffff
100592 /* The reset value of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */
100593 #define ALT_USB_DEV_DIEPCTL14_NAKSTS_RESET 0x0
100594 /* Extracts the ALT_USB_DEV_DIEPCTL14_NAKSTS field value from a register. */
100595 #define ALT_USB_DEV_DIEPCTL14_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
100596 /* Produces a ALT_USB_DEV_DIEPCTL14_NAKSTS register field value suitable for setting the register. */
100597 #define ALT_USB_DEV_DIEPCTL14_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
100598 
100599 /*
100600  * Field : eptype
100601  *
100602  * Endpoint Type (EPType)
100603  *
100604  * This is the transfer type supported by this logical endpoint.
100605  *
100606  * 2'b00: Control
100607  *
100608  * 2'b01: Isochronous
100609  *
100610  * 2'b10: Bulk
100611  *
100612  * 2'b11: Interrupt
100613  *
100614  * Field Enumeration Values:
100615  *
100616  * Enum | Value | Description
100617  * :-------------------------------------------|:------|:------------
100618  * ALT_USB_DEV_DIEPCTL14_EPTYPE_E_CTL | 0x0 | Control
100619  * ALT_USB_DEV_DIEPCTL14_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
100620  * ALT_USB_DEV_DIEPCTL14_EPTYPE_E_BULK | 0x2 | Bulk
100621  * ALT_USB_DEV_DIEPCTL14_EPTYPE_E_INTERRUP | 0x3 | Interrupt
100622  *
100623  * Field Access Macros:
100624  *
100625  */
100626 /*
100627  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE
100628  *
100629  * Control
100630  */
100631 #define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_CTL 0x0
100632 /*
100633  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE
100634  *
100635  * Isochronous
100636  */
100637 #define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_ISOCHRONOUS 0x1
100638 /*
100639  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE
100640  *
100641  * Bulk
100642  */
100643 #define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_BULK 0x2
100644 /*
100645  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE
100646  *
100647  * Interrupt
100648  */
100649 #define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_INTERRUP 0x3
100650 
100651 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */
100652 #define ALT_USB_DEV_DIEPCTL14_EPTYPE_LSB 18
100653 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */
100654 #define ALT_USB_DEV_DIEPCTL14_EPTYPE_MSB 19
100655 /* The width in bits of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */
100656 #define ALT_USB_DEV_DIEPCTL14_EPTYPE_WIDTH 2
100657 /* The mask used to set the ALT_USB_DEV_DIEPCTL14_EPTYPE register field value. */
100658 #define ALT_USB_DEV_DIEPCTL14_EPTYPE_SET_MSK 0x000c0000
100659 /* The mask used to clear the ALT_USB_DEV_DIEPCTL14_EPTYPE register field value. */
100660 #define ALT_USB_DEV_DIEPCTL14_EPTYPE_CLR_MSK 0xfff3ffff
100661 /* The reset value of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */
100662 #define ALT_USB_DEV_DIEPCTL14_EPTYPE_RESET 0x0
100663 /* Extracts the ALT_USB_DEV_DIEPCTL14_EPTYPE field value from a register. */
100664 #define ALT_USB_DEV_DIEPCTL14_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
100665 /* Produces a ALT_USB_DEV_DIEPCTL14_EPTYPE register field value suitable for setting the register. */
100666 #define ALT_USB_DEV_DIEPCTL14_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
100667 
100668 /*
100669  * Field : stall
100670  *
100671  * STALL Handshake (Stall)
100672  *
100673  * Applies to non-control, non-isochronous IN and OUT endpoints only.
100674  *
100675  * The application sets this bit to stall all tokens from the USB host to this
100676  * endpoint. If a
100677  *
100678  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
100679  * bit, the
100680  *
100681  * STALL bit takes priority. Only the application can clear this bit, never the
100682  * core.
100683  *
100684  * 1'b0 R_W
100685  *
100686  * Applies to control endpoints only.
100687  *
100688  * The application can only set this bit, and the core clears it, when a SETUP
100689  * token is
100690  *
100691  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
100692  * OUT
100693  *
100694  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
100695  * this bit's
100696  *
100697  * setting, the core always responds to SETUP data packets with an ACK handshake.
100698  *
100699  * Field Enumeration Values:
100700  *
100701  * Enum | Value | Description
100702  * :------------------------------------|:------|:----------------------------
100703  * ALT_USB_DEV_DIEPCTL14_STALL_E_INACT | 0x0 | STALL All Tokens not active
100704  * ALT_USB_DEV_DIEPCTL14_STALL_E_ACT | 0x1 | STALL All Tokens active
100705  *
100706  * Field Access Macros:
100707  *
100708  */
100709 /*
100710  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_STALL
100711  *
100712  * STALL All Tokens not active
100713  */
100714 #define ALT_USB_DEV_DIEPCTL14_STALL_E_INACT 0x0
100715 /*
100716  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_STALL
100717  *
100718  * STALL All Tokens active
100719  */
100720 #define ALT_USB_DEV_DIEPCTL14_STALL_E_ACT 0x1
100721 
100722 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_STALL register field. */
100723 #define ALT_USB_DEV_DIEPCTL14_STALL_LSB 21
100724 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_STALL register field. */
100725 #define ALT_USB_DEV_DIEPCTL14_STALL_MSB 21
100726 /* The width in bits of the ALT_USB_DEV_DIEPCTL14_STALL register field. */
100727 #define ALT_USB_DEV_DIEPCTL14_STALL_WIDTH 1
100728 /* The mask used to set the ALT_USB_DEV_DIEPCTL14_STALL register field value. */
100729 #define ALT_USB_DEV_DIEPCTL14_STALL_SET_MSK 0x00200000
100730 /* The mask used to clear the ALT_USB_DEV_DIEPCTL14_STALL register field value. */
100731 #define ALT_USB_DEV_DIEPCTL14_STALL_CLR_MSK 0xffdfffff
100732 /* The reset value of the ALT_USB_DEV_DIEPCTL14_STALL register field. */
100733 #define ALT_USB_DEV_DIEPCTL14_STALL_RESET 0x0
100734 /* Extracts the ALT_USB_DEV_DIEPCTL14_STALL field value from a register. */
100735 #define ALT_USB_DEV_DIEPCTL14_STALL_GET(value) (((value) & 0x00200000) >> 21)
100736 /* Produces a ALT_USB_DEV_DIEPCTL14_STALL register field value suitable for setting the register. */
100737 #define ALT_USB_DEV_DIEPCTL14_STALL_SET(value) (((value) << 21) & 0x00200000)
100738 
100739 /*
100740  * Field : txfnum
100741  *
100742  * TxFIFO Number (TxFNum)
100743  *
100744  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
100745  *
100746  * endpoints must map this to the corresponding Periodic TxFIFO number.
100747  *
100748  * 4'h0: Non-Periodic TxFIFO
100749  *
100750  * Others: Specified Periodic TxFIFO.number
100751  *
100752  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
100753  *
100754  * applications such as mass storage. The core treats an IN endpoint as a non-
100755  * periodic
100756  *
100757  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
100758  * must be
100759  *
100760  * allocated for an interrupt IN endpoint, and the number of this
100761  *
100762  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
100763  *
100764  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
100765  *
100766  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
100767  *
100768  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
100769  *
100770  * This field is valid only for IN endpoints.
100771  *
100772  * Field Access Macros:
100773  *
100774  */
100775 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */
100776 #define ALT_USB_DEV_DIEPCTL14_TXFNUM_LSB 22
100777 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */
100778 #define ALT_USB_DEV_DIEPCTL14_TXFNUM_MSB 25
100779 /* The width in bits of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */
100780 #define ALT_USB_DEV_DIEPCTL14_TXFNUM_WIDTH 4
100781 /* The mask used to set the ALT_USB_DEV_DIEPCTL14_TXFNUM register field value. */
100782 #define ALT_USB_DEV_DIEPCTL14_TXFNUM_SET_MSK 0x03c00000
100783 /* The mask used to clear the ALT_USB_DEV_DIEPCTL14_TXFNUM register field value. */
100784 #define ALT_USB_DEV_DIEPCTL14_TXFNUM_CLR_MSK 0xfc3fffff
100785 /* The reset value of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */
100786 #define ALT_USB_DEV_DIEPCTL14_TXFNUM_RESET 0x0
100787 /* Extracts the ALT_USB_DEV_DIEPCTL14_TXFNUM field value from a register. */
100788 #define ALT_USB_DEV_DIEPCTL14_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
100789 /* Produces a ALT_USB_DEV_DIEPCTL14_TXFNUM register field value suitable for setting the register. */
100790 #define ALT_USB_DEV_DIEPCTL14_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
100791 
100792 /*
100793  * Field : cnak
100794  *
100795  * Clear NAK (CNAK)
100796  *
100797  * A write to this bit clears the NAK bit For the endpoint.
100798  *
100799  * Field Enumeration Values:
100800  *
100801  * Enum | Value | Description
100802  * :-----------------------------------|:------|:-------------
100803  * ALT_USB_DEV_DIEPCTL14_CNAK_E_INACT | 0x0 | No Clear NAK
100804  * ALT_USB_DEV_DIEPCTL14_CNAK_E_ACT | 0x1 | Clear NAK
100805  *
100806  * Field Access Macros:
100807  *
100808  */
100809 /*
100810  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_CNAK
100811  *
100812  * No Clear NAK
100813  */
100814 #define ALT_USB_DEV_DIEPCTL14_CNAK_E_INACT 0x0
100815 /*
100816  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_CNAK
100817  *
100818  * Clear NAK
100819  */
100820 #define ALT_USB_DEV_DIEPCTL14_CNAK_E_ACT 0x1
100821 
100822 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */
100823 #define ALT_USB_DEV_DIEPCTL14_CNAK_LSB 26
100824 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */
100825 #define ALT_USB_DEV_DIEPCTL14_CNAK_MSB 26
100826 /* The width in bits of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */
100827 #define ALT_USB_DEV_DIEPCTL14_CNAK_WIDTH 1
100828 /* The mask used to set the ALT_USB_DEV_DIEPCTL14_CNAK register field value. */
100829 #define ALT_USB_DEV_DIEPCTL14_CNAK_SET_MSK 0x04000000
100830 /* The mask used to clear the ALT_USB_DEV_DIEPCTL14_CNAK register field value. */
100831 #define ALT_USB_DEV_DIEPCTL14_CNAK_CLR_MSK 0xfbffffff
100832 /* The reset value of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */
100833 #define ALT_USB_DEV_DIEPCTL14_CNAK_RESET 0x0
100834 /* Extracts the ALT_USB_DEV_DIEPCTL14_CNAK field value from a register. */
100835 #define ALT_USB_DEV_DIEPCTL14_CNAK_GET(value) (((value) & 0x04000000) >> 26)
100836 /* Produces a ALT_USB_DEV_DIEPCTL14_CNAK register field value suitable for setting the register. */
100837 #define ALT_USB_DEV_DIEPCTL14_CNAK_SET(value) (((value) << 26) & 0x04000000)
100838 
100839 /*
100840  * Field : snak
100841  *
100842  * Set NAK (SNAK)
100843  *
100844  * A write to this bit sets the NAK bit For the endpoint.
100845  *
100846  * Using this bit, the application can control the transmission of NAK
100847  *
100848  * handshakes on an endpoint. The core can also Set this bit For an
100849  *
100850  * endpoint after a SETUP packet is received on that endpoint.
100851  *
100852  * Field Enumeration Values:
100853  *
100854  * Enum | Value | Description
100855  * :-----------------------------------|:------|:------------
100856  * ALT_USB_DEV_DIEPCTL14_SNAK_E_INACT | 0x0 | No Set NAK
100857  * ALT_USB_DEV_DIEPCTL14_SNAK_E_ACT | 0x1 | Set NAK
100858  *
100859  * Field Access Macros:
100860  *
100861  */
100862 /*
100863  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SNAK
100864  *
100865  * No Set NAK
100866  */
100867 #define ALT_USB_DEV_DIEPCTL14_SNAK_E_INACT 0x0
100868 /*
100869  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SNAK
100870  *
100871  * Set NAK
100872  */
100873 #define ALT_USB_DEV_DIEPCTL14_SNAK_E_ACT 0x1
100874 
100875 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */
100876 #define ALT_USB_DEV_DIEPCTL14_SNAK_LSB 27
100877 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */
100878 #define ALT_USB_DEV_DIEPCTL14_SNAK_MSB 27
100879 /* The width in bits of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */
100880 #define ALT_USB_DEV_DIEPCTL14_SNAK_WIDTH 1
100881 /* The mask used to set the ALT_USB_DEV_DIEPCTL14_SNAK register field value. */
100882 #define ALT_USB_DEV_DIEPCTL14_SNAK_SET_MSK 0x08000000
100883 /* The mask used to clear the ALT_USB_DEV_DIEPCTL14_SNAK register field value. */
100884 #define ALT_USB_DEV_DIEPCTL14_SNAK_CLR_MSK 0xf7ffffff
100885 /* The reset value of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */
100886 #define ALT_USB_DEV_DIEPCTL14_SNAK_RESET 0x0
100887 /* Extracts the ALT_USB_DEV_DIEPCTL14_SNAK field value from a register. */
100888 #define ALT_USB_DEV_DIEPCTL14_SNAK_GET(value) (((value) & 0x08000000) >> 27)
100889 /* Produces a ALT_USB_DEV_DIEPCTL14_SNAK register field value suitable for setting the register. */
100890 #define ALT_USB_DEV_DIEPCTL14_SNAK_SET(value) (((value) << 27) & 0x08000000)
100891 
100892 /*
100893  * Field : setd0pid
100894  *
100895  * Set DATA0 PID (SetD0PID)
100896  *
100897  * Applies to interrupt/bulk IN and OUT endpoints only.
100898  *
100899  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
100900  * to DATA0.
100901  *
100902  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
100903  *
100904  * DMA mode.
100905  *
100906  * 1'b0 WO
100907  *
100908  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
100909  *
100910  * Applies to isochronous IN and OUT endpoints only.
100911  *
100912  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
100913  * (micro)
100914  *
100915  * frame.
100916  *
100917  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
100918  * number
100919  *
100920  * in which to send data is in the transmit descriptor structure. The frame in
100921  * which to
100922  *
100923  * receive data is updated in receive descriptor structure.
100924  *
100925  * Field Enumeration Values:
100926  *
100927  * Enum | Value | Description
100928  * :--------------------------------------|:------|:----------------------------
100929  * ALT_USB_DEV_DIEPCTL14_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
100930  * ALT_USB_DEV_DIEPCTL14_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
100931  *
100932  * Field Access Macros:
100933  *
100934  */
100935 /*
100936  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD0PID
100937  *
100938  * Disables Set DATA0 PID
100939  */
100940 #define ALT_USB_DEV_DIEPCTL14_SETD0PID_E_DISD 0x0
100941 /*
100942  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD0PID
100943  *
100944  * Endpoint Data PID to DATA0)
100945  */
100946 #define ALT_USB_DEV_DIEPCTL14_SETD0PID_E_END 0x1
100947 
100948 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */
100949 #define ALT_USB_DEV_DIEPCTL14_SETD0PID_LSB 28
100950 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */
100951 #define ALT_USB_DEV_DIEPCTL14_SETD0PID_MSB 28
100952 /* The width in bits of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */
100953 #define ALT_USB_DEV_DIEPCTL14_SETD0PID_WIDTH 1
100954 /* The mask used to set the ALT_USB_DEV_DIEPCTL14_SETD0PID register field value. */
100955 #define ALT_USB_DEV_DIEPCTL14_SETD0PID_SET_MSK 0x10000000
100956 /* The mask used to clear the ALT_USB_DEV_DIEPCTL14_SETD0PID register field value. */
100957 #define ALT_USB_DEV_DIEPCTL14_SETD0PID_CLR_MSK 0xefffffff
100958 /* The reset value of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */
100959 #define ALT_USB_DEV_DIEPCTL14_SETD0PID_RESET 0x0
100960 /* Extracts the ALT_USB_DEV_DIEPCTL14_SETD0PID field value from a register. */
100961 #define ALT_USB_DEV_DIEPCTL14_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
100962 /* Produces a ALT_USB_DEV_DIEPCTL14_SETD0PID register field value suitable for setting the register. */
100963 #define ALT_USB_DEV_DIEPCTL14_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
100964 
100965 /*
100966  * Field : setd1pid
100967  *
100968  * Set DATA1 PID (SetD1PID)
100969  *
100970  * Applies to interrupt/bulk IN and OUT endpoints only.
100971  *
100972  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
100973  * to DATA1.
100974  *
100975  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
100976  *
100977  * DMA mode.
100978  *
100979  * Set Odd (micro)frame (SetOddFr)
100980  *
100981  * Applies to isochronous IN and OUT endpoints only.
100982  *
100983  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
100984  *
100985  * (micro)frame.
100986  *
100987  * This field is not applicable for Scatter/Gather DMA mode.
100988  *
100989  * Field Enumeration Values:
100990  *
100991  * Enum | Value | Description
100992  * :--------------------------------------|:------|:-----------------------
100993  * ALT_USB_DEV_DIEPCTL14_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
100994  * ALT_USB_DEV_DIEPCTL14_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
100995  *
100996  * Field Access Macros:
100997  *
100998  */
100999 /*
101000  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD1PID
101001  *
101002  * Disables Set DATA1 PID
101003  */
101004 #define ALT_USB_DEV_DIEPCTL14_SETD1PID_E_DISD 0x0
101005 /*
101006  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD1PID
101007  *
101008  * Enables Set DATA1 PID
101009  */
101010 #define ALT_USB_DEV_DIEPCTL14_SETD1PID_E_END 0x1
101011 
101012 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */
101013 #define ALT_USB_DEV_DIEPCTL14_SETD1PID_LSB 29
101014 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */
101015 #define ALT_USB_DEV_DIEPCTL14_SETD1PID_MSB 29
101016 /* The width in bits of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */
101017 #define ALT_USB_DEV_DIEPCTL14_SETD1PID_WIDTH 1
101018 /* The mask used to set the ALT_USB_DEV_DIEPCTL14_SETD1PID register field value. */
101019 #define ALT_USB_DEV_DIEPCTL14_SETD1PID_SET_MSK 0x20000000
101020 /* The mask used to clear the ALT_USB_DEV_DIEPCTL14_SETD1PID register field value. */
101021 #define ALT_USB_DEV_DIEPCTL14_SETD1PID_CLR_MSK 0xdfffffff
101022 /* The reset value of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */
101023 #define ALT_USB_DEV_DIEPCTL14_SETD1PID_RESET 0x0
101024 /* Extracts the ALT_USB_DEV_DIEPCTL14_SETD1PID field value from a register. */
101025 #define ALT_USB_DEV_DIEPCTL14_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
101026 /* Produces a ALT_USB_DEV_DIEPCTL14_SETD1PID register field value suitable for setting the register. */
101027 #define ALT_USB_DEV_DIEPCTL14_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
101028 
101029 /*
101030  * Field : epdis
101031  *
101032  * Endpoint Disable (EPDis)
101033  *
101034  * Applies to IN and OUT endpoints.
101035  *
101036  * The application sets this bit to stop transmitting/receiving data on an
101037  * endpoint, even
101038  *
101039  * before the transfer for that endpoint is complete. The application must wait for
101040  * the
101041  *
101042  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
101043  * clears
101044  *
101045  * this bit before setting the Endpoint Disabled interrupt. The application must
101046  * set this bit
101047  *
101048  * only if Endpoint Enable is already set for this endpoint.
101049  *
101050  * Field Enumeration Values:
101051  *
101052  * Enum | Value | Description
101053  * :------------------------------------|:------|:--------------------
101054  * ALT_USB_DEV_DIEPCTL14_EPDIS_E_INACT | 0x0 | No Endpoint Disable
101055  * ALT_USB_DEV_DIEPCTL14_EPDIS_E_ACT | 0x1 | Endpoint Disable
101056  *
101057  * Field Access Macros:
101058  *
101059  */
101060 /*
101061  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPDIS
101062  *
101063  * No Endpoint Disable
101064  */
101065 #define ALT_USB_DEV_DIEPCTL14_EPDIS_E_INACT 0x0
101066 /*
101067  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPDIS
101068  *
101069  * Endpoint Disable
101070  */
101071 #define ALT_USB_DEV_DIEPCTL14_EPDIS_E_ACT 0x1
101072 
101073 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */
101074 #define ALT_USB_DEV_DIEPCTL14_EPDIS_LSB 30
101075 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */
101076 #define ALT_USB_DEV_DIEPCTL14_EPDIS_MSB 30
101077 /* The width in bits of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */
101078 #define ALT_USB_DEV_DIEPCTL14_EPDIS_WIDTH 1
101079 /* The mask used to set the ALT_USB_DEV_DIEPCTL14_EPDIS register field value. */
101080 #define ALT_USB_DEV_DIEPCTL14_EPDIS_SET_MSK 0x40000000
101081 /* The mask used to clear the ALT_USB_DEV_DIEPCTL14_EPDIS register field value. */
101082 #define ALT_USB_DEV_DIEPCTL14_EPDIS_CLR_MSK 0xbfffffff
101083 /* The reset value of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */
101084 #define ALT_USB_DEV_DIEPCTL14_EPDIS_RESET 0x0
101085 /* Extracts the ALT_USB_DEV_DIEPCTL14_EPDIS field value from a register. */
101086 #define ALT_USB_DEV_DIEPCTL14_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
101087 /* Produces a ALT_USB_DEV_DIEPCTL14_EPDIS register field value suitable for setting the register. */
101088 #define ALT_USB_DEV_DIEPCTL14_EPDIS_SET(value) (((value) << 30) & 0x40000000)
101089 
101090 /*
101091  * Field : epena
101092  *
101093  * Endpoint Enable (EPEna)
101094  *
101095  * Applies to IN and OUT endpoints.
101096  *
101097  * When Scatter/Gather DMA mode is enabled,
101098  *
101099  * For IN endpoints this bit indicates that the descriptor structure and data
101100  * buffer with
101101  *
101102  * data ready to transmit is setup.
101103  *
101104  * For OUT endpoint it indicates that the descriptor structure and data buffer to
101105  *
101106  * receive data is setup.
101107  *
101108  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
101109  *
101110  * DMA mode:
101111  *
101112  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
101113  * the
101114  *
101115  * endpoint.
101116  *
101117  * * For OUT endpoints, this bit indicates that the application has allocated the
101118  *
101119  * memory to start receiving data from the USB.
101120  *
101121  * * The core clears this bit before setting any of the following interrupts on
101122  * this
101123  *
101124  * endpoint:
101125  *
101126  * SETUP Phase Done
101127  *
101128  * Endpoint Disabled
101129  *
101130  * Transfer Completed
101131  *
101132  * Note: For control endpoints in DMA mode, this bit must be set to be able to
101133  * transfer
101134  *
101135  * SETUP data packets in memory.
101136  *
101137  * Field Enumeration Values:
101138  *
101139  * Enum | Value | Description
101140  * :------------------------------------|:------|:-------------------------
101141  * ALT_USB_DEV_DIEPCTL14_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
101142  * ALT_USB_DEV_DIEPCTL14_EPENA_E_ACT | 0x1 | Endpoint Enable active
101143  *
101144  * Field Access Macros:
101145  *
101146  */
101147 /*
101148  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPENA
101149  *
101150  * Endpoint Enable inactive
101151  */
101152 #define ALT_USB_DEV_DIEPCTL14_EPENA_E_INACT 0x0
101153 /*
101154  * Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPENA
101155  *
101156  * Endpoint Enable active
101157  */
101158 #define ALT_USB_DEV_DIEPCTL14_EPENA_E_ACT 0x1
101159 
101160 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */
101161 #define ALT_USB_DEV_DIEPCTL14_EPENA_LSB 31
101162 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */
101163 #define ALT_USB_DEV_DIEPCTL14_EPENA_MSB 31
101164 /* The width in bits of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */
101165 #define ALT_USB_DEV_DIEPCTL14_EPENA_WIDTH 1
101166 /* The mask used to set the ALT_USB_DEV_DIEPCTL14_EPENA register field value. */
101167 #define ALT_USB_DEV_DIEPCTL14_EPENA_SET_MSK 0x80000000
101168 /* The mask used to clear the ALT_USB_DEV_DIEPCTL14_EPENA register field value. */
101169 #define ALT_USB_DEV_DIEPCTL14_EPENA_CLR_MSK 0x7fffffff
101170 /* The reset value of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */
101171 #define ALT_USB_DEV_DIEPCTL14_EPENA_RESET 0x0
101172 /* Extracts the ALT_USB_DEV_DIEPCTL14_EPENA field value from a register. */
101173 #define ALT_USB_DEV_DIEPCTL14_EPENA_GET(value) (((value) & 0x80000000) >> 31)
101174 /* Produces a ALT_USB_DEV_DIEPCTL14_EPENA register field value suitable for setting the register. */
101175 #define ALT_USB_DEV_DIEPCTL14_EPENA_SET(value) (((value) << 31) & 0x80000000)
101176 
101177 #ifndef __ASSEMBLY__
101178 /*
101179  * WARNING: The C register and register group struct declarations are provided for
101180  * convenience and illustrative purposes. They should, however, be used with
101181  * caution as the C language standard provides no guarantees about the alignment or
101182  * atomicity of device memory accesses. The recommended practice for writing
101183  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
101184  * alt_write_word() functions.
101185  *
101186  * The struct declaration for register ALT_USB_DEV_DIEPCTL14.
101187  */
101188 struct ALT_USB_DEV_DIEPCTL14_s
101189 {
101190  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL14_MPS */
101191  uint32_t : 4; /* *UNDEFINED* */
101192  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL14_USBACTEP */
101193  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL14_DPID */
101194  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL14_NAKSTS */
101195  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL14_EPTYPE */
101196  uint32_t : 1; /* *UNDEFINED* */
101197  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL14_STALL */
101198  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL14_TXFNUM */
101199  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL14_CNAK */
101200  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL14_SNAK */
101201  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL14_SETD0PID */
101202  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL14_SETD1PID */
101203  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL14_EPDIS */
101204  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL14_EPENA */
101205 };
101206 
101207 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL14. */
101208 typedef volatile struct ALT_USB_DEV_DIEPCTL14_s ALT_USB_DEV_DIEPCTL14_t;
101209 #endif /* __ASSEMBLY__ */
101210 
101211 /* The reset value of the ALT_USB_DEV_DIEPCTL14 register. */
101212 #define ALT_USB_DEV_DIEPCTL14_RESET 0x00000000
101213 /* The byte offset of the ALT_USB_DEV_DIEPCTL14 register from the beginning of the component. */
101214 #define ALT_USB_DEV_DIEPCTL14_OFST 0x2c0
101215 /* The address of the ALT_USB_DEV_DIEPCTL14 register. */
101216 #define ALT_USB_DEV_DIEPCTL14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL14_OFST))
101217 
101218 /*
101219  * Register : diepint14
101220  *
101221  * Device IN Endpoint 14 Interrupt Register
101222  *
101223  * Register Layout
101224  *
101225  * Bits | Access | Reset | Description
101226  * :--------|:-------|:------|:----------------------------------
101227  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_XFERCOMPL
101228  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_EPDISBLD
101229  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_AHBERR
101230  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_TMO
101231  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_INTKNTXFEMP
101232  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_INTKNEPMIS
101233  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_INEPNAKEFF
101234  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT14_TXFEMP
101235  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN
101236  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_BNAINTR
101237  * [10] | ??? | 0x0 | *UNDEFINED*
101238  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_PKTDRPSTS
101239  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_BBLEERR
101240  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_NAKINTRPT
101241  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_NYETINTRPT
101242  * [31:15] | ??? | 0x0 | *UNDEFINED*
101243  *
101244  */
101245 /*
101246  * Field : xfercompl
101247  *
101248  * Transfer Completed Interrupt (XferCompl)
101249  *
101250  * Applies to IN and OUT endpoints.
101251  *
101252  * When Scatter/Gather DMA mode is enabled
101253  *
101254  * * For IN endpoint this field indicates that the requested data
101255  *
101256  * from the descriptor is moved from external system memory
101257  *
101258  * to internal FIFO.
101259  *
101260  * * For OUT endpoint this field indicates that the requested
101261  *
101262  * data from the internal FIFO is moved to external system
101263  *
101264  * memory. This interrupt is generated only when the
101265  *
101266  * corresponding endpoint descriptor is closed, and the IOC
101267  *
101268  * bit For the corresponding descriptor is Set.
101269  *
101270  * When Scatter/Gather DMA mode is disabled, this field
101271  *
101272  * indicates that the programmed transfer is complete on the
101273  *
101274  * AHB as well as on the USB, For this endpoint.
101275  *
101276  * Field Enumeration Values:
101277  *
101278  * Enum | Value | Description
101279  * :----------------------------------------|:------|:-----------------------------
101280  * ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_INACT | 0x0 | No Interrupt
101281  * ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
101282  *
101283  * Field Access Macros:
101284  *
101285  */
101286 /*
101287  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_XFERCOMPL
101288  *
101289  * No Interrupt
101290  */
101291 #define ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_INACT 0x0
101292 /*
101293  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_XFERCOMPL
101294  *
101295  * Transfer Completed Interrupt
101296  */
101297 #define ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_ACT 0x1
101298 
101299 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */
101300 #define ALT_USB_DEV_DIEPINT14_XFERCOMPL_LSB 0
101301 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */
101302 #define ALT_USB_DEV_DIEPINT14_XFERCOMPL_MSB 0
101303 /* The width in bits of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */
101304 #define ALT_USB_DEV_DIEPINT14_XFERCOMPL_WIDTH 1
101305 /* The mask used to set the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field value. */
101306 #define ALT_USB_DEV_DIEPINT14_XFERCOMPL_SET_MSK 0x00000001
101307 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field value. */
101308 #define ALT_USB_DEV_DIEPINT14_XFERCOMPL_CLR_MSK 0xfffffffe
101309 /* The reset value of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */
101310 #define ALT_USB_DEV_DIEPINT14_XFERCOMPL_RESET 0x0
101311 /* Extracts the ALT_USB_DEV_DIEPINT14_XFERCOMPL field value from a register. */
101312 #define ALT_USB_DEV_DIEPINT14_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
101313 /* Produces a ALT_USB_DEV_DIEPINT14_XFERCOMPL register field value suitable for setting the register. */
101314 #define ALT_USB_DEV_DIEPINT14_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
101315 
101316 /*
101317  * Field : epdisbld
101318  *
101319  * Endpoint Disabled Interrupt (EPDisbld)
101320  *
101321  * Applies to IN and OUT endpoints.
101322  *
101323  * This bit indicates that the endpoint is disabled per the
101324  *
101325  * application's request.
101326  *
101327  * Field Enumeration Values:
101328  *
101329  * Enum | Value | Description
101330  * :---------------------------------------|:------|:----------------------------
101331  * ALT_USB_DEV_DIEPINT14_EPDISBLD_E_INACT | 0x0 | No Interrupt
101332  * ALT_USB_DEV_DIEPINT14_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
101333  *
101334  * Field Access Macros:
101335  *
101336  */
101337 /*
101338  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_EPDISBLD
101339  *
101340  * No Interrupt
101341  */
101342 #define ALT_USB_DEV_DIEPINT14_EPDISBLD_E_INACT 0x0
101343 /*
101344  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_EPDISBLD
101345  *
101346  * Endpoint Disabled Interrupt
101347  */
101348 #define ALT_USB_DEV_DIEPINT14_EPDISBLD_E_ACT 0x1
101349 
101350 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */
101351 #define ALT_USB_DEV_DIEPINT14_EPDISBLD_LSB 1
101352 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */
101353 #define ALT_USB_DEV_DIEPINT14_EPDISBLD_MSB 1
101354 /* The width in bits of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */
101355 #define ALT_USB_DEV_DIEPINT14_EPDISBLD_WIDTH 1
101356 /* The mask used to set the ALT_USB_DEV_DIEPINT14_EPDISBLD register field value. */
101357 #define ALT_USB_DEV_DIEPINT14_EPDISBLD_SET_MSK 0x00000002
101358 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_EPDISBLD register field value. */
101359 #define ALT_USB_DEV_DIEPINT14_EPDISBLD_CLR_MSK 0xfffffffd
101360 /* The reset value of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */
101361 #define ALT_USB_DEV_DIEPINT14_EPDISBLD_RESET 0x0
101362 /* Extracts the ALT_USB_DEV_DIEPINT14_EPDISBLD field value from a register. */
101363 #define ALT_USB_DEV_DIEPINT14_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
101364 /* Produces a ALT_USB_DEV_DIEPINT14_EPDISBLD register field value suitable for setting the register. */
101365 #define ALT_USB_DEV_DIEPINT14_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
101366 
101367 /*
101368  * Field : ahberr
101369  *
101370  * AHB Error (AHBErr)
101371  *
101372  * Applies to IN and OUT endpoints.
101373  *
101374  * This is generated only in Internal DMA mode when there is an
101375  *
101376  * AHB error during an AHB read/write. The application can read
101377  *
101378  * the corresponding endpoint DMA address register to get the
101379  *
101380  * error address.
101381  *
101382  * Field Enumeration Values:
101383  *
101384  * Enum | Value | Description
101385  * :-------------------------------------|:------|:--------------------
101386  * ALT_USB_DEV_DIEPINT14_AHBERR_E_INACT | 0x0 | No Interrupt
101387  * ALT_USB_DEV_DIEPINT14_AHBERR_E_ACT | 0x1 | AHB Error interrupt
101388  *
101389  * Field Access Macros:
101390  *
101391  */
101392 /*
101393  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_AHBERR
101394  *
101395  * No Interrupt
101396  */
101397 #define ALT_USB_DEV_DIEPINT14_AHBERR_E_INACT 0x0
101398 /*
101399  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_AHBERR
101400  *
101401  * AHB Error interrupt
101402  */
101403 #define ALT_USB_DEV_DIEPINT14_AHBERR_E_ACT 0x1
101404 
101405 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */
101406 #define ALT_USB_DEV_DIEPINT14_AHBERR_LSB 2
101407 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */
101408 #define ALT_USB_DEV_DIEPINT14_AHBERR_MSB 2
101409 /* The width in bits of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */
101410 #define ALT_USB_DEV_DIEPINT14_AHBERR_WIDTH 1
101411 /* The mask used to set the ALT_USB_DEV_DIEPINT14_AHBERR register field value. */
101412 #define ALT_USB_DEV_DIEPINT14_AHBERR_SET_MSK 0x00000004
101413 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_AHBERR register field value. */
101414 #define ALT_USB_DEV_DIEPINT14_AHBERR_CLR_MSK 0xfffffffb
101415 /* The reset value of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */
101416 #define ALT_USB_DEV_DIEPINT14_AHBERR_RESET 0x0
101417 /* Extracts the ALT_USB_DEV_DIEPINT14_AHBERR field value from a register. */
101418 #define ALT_USB_DEV_DIEPINT14_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
101419 /* Produces a ALT_USB_DEV_DIEPINT14_AHBERR register field value suitable for setting the register. */
101420 #define ALT_USB_DEV_DIEPINT14_AHBERR_SET(value) (((value) << 2) & 0x00000004)
101421 
101422 /*
101423  * Field : timeout
101424  *
101425  * Timeout Condition (TimeOUT)
101426  *
101427  * In shared TX FIFO mode, applies to non-isochronous IN
101428  *
101429  * endpoints only.
101430  *
101431  * In dedicated FIFO mode, applies only to Control IN
101432  *
101433  * endpoints.
101434  *
101435  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
101436  *
101437  * asserted.
101438  *
101439  * Indicates that the core has detected a timeout condition on the
101440  *
101441  * USB For the last IN token on this endpoint.
101442  *
101443  * Field Enumeration Values:
101444  *
101445  * Enum | Value | Description
101446  * :----------------------------------|:------|:------------------
101447  * ALT_USB_DEV_DIEPINT14_TMO_E_INACT | 0x0 | No interrupt
101448  * ALT_USB_DEV_DIEPINT14_TMO_E_ACT | 0x1 | Timeout interrupy
101449  *
101450  * Field Access Macros:
101451  *
101452  */
101453 /*
101454  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TMO
101455  *
101456  * No interrupt
101457  */
101458 #define ALT_USB_DEV_DIEPINT14_TMO_E_INACT 0x0
101459 /*
101460  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TMO
101461  *
101462  * Timeout interrupy
101463  */
101464 #define ALT_USB_DEV_DIEPINT14_TMO_E_ACT 0x1
101465 
101466 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_TMO register field. */
101467 #define ALT_USB_DEV_DIEPINT14_TMO_LSB 3
101468 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_TMO register field. */
101469 #define ALT_USB_DEV_DIEPINT14_TMO_MSB 3
101470 /* The width in bits of the ALT_USB_DEV_DIEPINT14_TMO register field. */
101471 #define ALT_USB_DEV_DIEPINT14_TMO_WIDTH 1
101472 /* The mask used to set the ALT_USB_DEV_DIEPINT14_TMO register field value. */
101473 #define ALT_USB_DEV_DIEPINT14_TMO_SET_MSK 0x00000008
101474 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_TMO register field value. */
101475 #define ALT_USB_DEV_DIEPINT14_TMO_CLR_MSK 0xfffffff7
101476 /* The reset value of the ALT_USB_DEV_DIEPINT14_TMO register field. */
101477 #define ALT_USB_DEV_DIEPINT14_TMO_RESET 0x0
101478 /* Extracts the ALT_USB_DEV_DIEPINT14_TMO field value from a register. */
101479 #define ALT_USB_DEV_DIEPINT14_TMO_GET(value) (((value) & 0x00000008) >> 3)
101480 /* Produces a ALT_USB_DEV_DIEPINT14_TMO register field value suitable for setting the register. */
101481 #define ALT_USB_DEV_DIEPINT14_TMO_SET(value) (((value) << 3) & 0x00000008)
101482 
101483 /*
101484  * Field : intkntxfemp
101485  *
101486  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
101487  *
101488  * Applies to non-periodic IN endpoints only.
101489  *
101490  * Indicates that an IN token was received when the associated
101491  *
101492  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
101493  *
101494  * asserted on the endpoint For which the IN token was received.
101495  *
101496  * Field Enumeration Values:
101497  *
101498  * Enum | Value | Description
101499  * :------------------------------------------|:------|:----------------------------
101500  * ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
101501  * ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
101502  *
101503  * Field Access Macros:
101504  *
101505  */
101506 /*
101507  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNTXFEMP
101508  *
101509  * No interrupt
101510  */
101511 #define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_INACT 0x0
101512 /*
101513  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNTXFEMP
101514  *
101515  * IN Token Received Interrupt
101516  */
101517 #define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_ACT 0x1
101518 
101519 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */
101520 #define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_LSB 4
101521 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */
101522 #define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_MSB 4
101523 /* The width in bits of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */
101524 #define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_WIDTH 1
101525 /* The mask used to set the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field value. */
101526 #define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_SET_MSK 0x00000010
101527 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field value. */
101528 #define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_CLR_MSK 0xffffffef
101529 /* The reset value of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */
101530 #define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_RESET 0x0
101531 /* Extracts the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP field value from a register. */
101532 #define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
101533 /* Produces a ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field value suitable for setting the register. */
101534 #define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
101535 
101536 /*
101537  * Field : intknepmis
101538  *
101539  * IN Token Received with EP Mismatch (INTknEPMis)
101540  *
101541  * Applies to non-periodic IN endpoints only.
101542  *
101543  * Indicates that the data in the top of the non-periodic TxFIFO
101544  *
101545  * belongs to an endpoint other than the one For which the IN token
101546  *
101547  * was received. This interrupt is asserted on the endpoint For
101548  *
101549  * which the IN token was received.
101550  *
101551  * Field Enumeration Values:
101552  *
101553  * Enum | Value | Description
101554  * :-----------------------------------------|:------|:---------------------------------------------
101555  * ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_INACT | 0x0 | No interrupt
101556  * ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
101557  *
101558  * Field Access Macros:
101559  *
101560  */
101561 /*
101562  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNEPMIS
101563  *
101564  * No interrupt
101565  */
101566 #define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_INACT 0x0
101567 /*
101568  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNEPMIS
101569  *
101570  * IN Token Received with EP Mismatch interrupt
101571  */
101572 #define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_ACT 0x1
101573 
101574 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */
101575 #define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_LSB 5
101576 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */
101577 #define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_MSB 5
101578 /* The width in bits of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */
101579 #define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_WIDTH 1
101580 /* The mask used to set the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field value. */
101581 #define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_SET_MSK 0x00000020
101582 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field value. */
101583 #define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_CLR_MSK 0xffffffdf
101584 /* The reset value of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */
101585 #define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_RESET 0x0
101586 /* Extracts the ALT_USB_DEV_DIEPINT14_INTKNEPMIS field value from a register. */
101587 #define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
101588 /* Produces a ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field value suitable for setting the register. */
101589 #define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
101590 
101591 /*
101592  * Field : inepnakeff
101593  *
101594  * IN Endpoint NAK Effective (INEPNakEff)
101595  *
101596  * Applies to periodic IN endpoints only.
101597  *
101598  * This bit can be cleared when the application clears the IN
101599  *
101600  * endpoint NAK by writing to DIEPCTLn.CNAK.
101601  *
101602  * This interrupt indicates that the core has sampled the NAK bit
101603  *
101604  * Set (either by the application or by the core). The interrupt
101605  *
101606  * indicates that the IN endpoint NAK bit Set by the application has
101607  *
101608  * taken effect in the core.
101609  *
101610  * This interrupt does not guarantee that a NAK handshake is sent
101611  *
101612  * on the USB. A STALL bit takes priority over a NAK bit.
101613  *
101614  * Field Enumeration Values:
101615  *
101616  * Enum | Value | Description
101617  * :-----------------------------------------|:------|:------------------------------------
101618  * ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_INACT | 0x0 | No interrupt
101619  * ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
101620  *
101621  * Field Access Macros:
101622  *
101623  */
101624 /*
101625  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INEPNAKEFF
101626  *
101627  * No interrupt
101628  */
101629 #define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_INACT 0x0
101630 /*
101631  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_INEPNAKEFF
101632  *
101633  * IN Endpoint NAK Effective interrupt
101634  */
101635 #define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_ACT 0x1
101636 
101637 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */
101638 #define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_LSB 6
101639 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */
101640 #define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_MSB 6
101641 /* The width in bits of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */
101642 #define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_WIDTH 1
101643 /* The mask used to set the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field value. */
101644 #define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_SET_MSK 0x00000040
101645 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field value. */
101646 #define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_CLR_MSK 0xffffffbf
101647 /* The reset value of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */
101648 #define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_RESET 0x0
101649 /* Extracts the ALT_USB_DEV_DIEPINT14_INEPNAKEFF field value from a register. */
101650 #define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
101651 /* Produces a ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field value suitable for setting the register. */
101652 #define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
101653 
101654 /*
101655  * Field : txfemp
101656  *
101657  * Transmit FIFO Empty (TxFEmp)
101658  *
101659  * This bit is valid only For IN Endpoints
101660  *
101661  * This interrupt is asserted when the TxFIFO For this endpoint is
101662  *
101663  * either half or completely empty. The half or completely empty
101664  *
101665  * status is determined by the TxFIFO Empty Level bit in the Core
101666  *
101667  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
101668  *
101669  * Field Enumeration Values:
101670  *
101671  * Enum | Value | Description
101672  * :-------------------------------------|:------|:------------------------------
101673  * ALT_USB_DEV_DIEPINT14_TXFEMP_E_INACT | 0x0 | No interrupt
101674  * ALT_USB_DEV_DIEPINT14_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
101675  *
101676  * Field Access Macros:
101677  *
101678  */
101679 /*
101680  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFEMP
101681  *
101682  * No interrupt
101683  */
101684 #define ALT_USB_DEV_DIEPINT14_TXFEMP_E_INACT 0x0
101685 /*
101686  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFEMP
101687  *
101688  * Transmit FIFO Empty interrupt
101689  */
101690 #define ALT_USB_DEV_DIEPINT14_TXFEMP_E_ACT 0x1
101691 
101692 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */
101693 #define ALT_USB_DEV_DIEPINT14_TXFEMP_LSB 7
101694 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */
101695 #define ALT_USB_DEV_DIEPINT14_TXFEMP_MSB 7
101696 /* The width in bits of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */
101697 #define ALT_USB_DEV_DIEPINT14_TXFEMP_WIDTH 1
101698 /* The mask used to set the ALT_USB_DEV_DIEPINT14_TXFEMP register field value. */
101699 #define ALT_USB_DEV_DIEPINT14_TXFEMP_SET_MSK 0x00000080
101700 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_TXFEMP register field value. */
101701 #define ALT_USB_DEV_DIEPINT14_TXFEMP_CLR_MSK 0xffffff7f
101702 /* The reset value of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */
101703 #define ALT_USB_DEV_DIEPINT14_TXFEMP_RESET 0x1
101704 /* Extracts the ALT_USB_DEV_DIEPINT14_TXFEMP field value from a register. */
101705 #define ALT_USB_DEV_DIEPINT14_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
101706 /* Produces a ALT_USB_DEV_DIEPINT14_TXFEMP register field value suitable for setting the register. */
101707 #define ALT_USB_DEV_DIEPINT14_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
101708 
101709 /*
101710  * Field : txfifoundrn
101711  *
101712  * Fifo Underrun (TxfifoUndrn)
101713  *
101714  * Applies to IN endpoints Only
101715  *
101716  * This bit is valid only If thresholding is enabled. The core generates this
101717  * interrupt when
101718  *
101719  * it detects a transmit FIFO underrun condition For this endpoint.
101720  *
101721  * Field Enumeration Values:
101722  *
101723  * Enum | Value | Description
101724  * :------------------------------------------|:------|:------------------------
101725  * ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
101726  * ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
101727  *
101728  * Field Access Macros:
101729  *
101730  */
101731 /*
101732  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN
101733  *
101734  * No interrupt
101735  */
101736 #define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_INACT 0x0
101737 /*
101738  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN
101739  *
101740  * Fifo Underrun interrupt
101741  */
101742 #define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_ACT 0x1
101743 
101744 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */
101745 #define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_LSB 8
101746 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */
101747 #define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_MSB 8
101748 /* The width in bits of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */
101749 #define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_WIDTH 1
101750 /* The mask used to set the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field value. */
101751 #define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_SET_MSK 0x00000100
101752 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field value. */
101753 #define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_CLR_MSK 0xfffffeff
101754 /* The reset value of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */
101755 #define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_RESET 0x0
101756 /* Extracts the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN field value from a register. */
101757 #define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
101758 /* Produces a ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field value suitable for setting the register. */
101759 #define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
101760 
101761 /*
101762  * Field : bnaintr
101763  *
101764  * BNA (Buffer Not Available) Interrupt (BNAIntr)
101765  *
101766  * This bit is valid only when Scatter/Gather DMA mode is enabled.
101767  *
101768  * The core generates this interrupt when the descriptor accessed
101769  *
101770  * is not ready For the Core to process, such as Host busy or DMA
101771  *
101772  * done
101773  *
101774  * Field Enumeration Values:
101775  *
101776  * Enum | Value | Description
101777  * :--------------------------------------|:------|:--------------
101778  * ALT_USB_DEV_DIEPINT14_BNAINTR_E_INACT | 0x0 | No interrupt
101779  * ALT_USB_DEV_DIEPINT14_BNAINTR_E_ACT | 0x1 | BNA interrupt
101780  *
101781  * Field Access Macros:
101782  *
101783  */
101784 /*
101785  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_BNAINTR
101786  *
101787  * No interrupt
101788  */
101789 #define ALT_USB_DEV_DIEPINT14_BNAINTR_E_INACT 0x0
101790 /*
101791  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_BNAINTR
101792  *
101793  * BNA interrupt
101794  */
101795 #define ALT_USB_DEV_DIEPINT14_BNAINTR_E_ACT 0x1
101796 
101797 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */
101798 #define ALT_USB_DEV_DIEPINT14_BNAINTR_LSB 9
101799 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */
101800 #define ALT_USB_DEV_DIEPINT14_BNAINTR_MSB 9
101801 /* The width in bits of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */
101802 #define ALT_USB_DEV_DIEPINT14_BNAINTR_WIDTH 1
101803 /* The mask used to set the ALT_USB_DEV_DIEPINT14_BNAINTR register field value. */
101804 #define ALT_USB_DEV_DIEPINT14_BNAINTR_SET_MSK 0x00000200
101805 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_BNAINTR register field value. */
101806 #define ALT_USB_DEV_DIEPINT14_BNAINTR_CLR_MSK 0xfffffdff
101807 /* The reset value of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */
101808 #define ALT_USB_DEV_DIEPINT14_BNAINTR_RESET 0x0
101809 /* Extracts the ALT_USB_DEV_DIEPINT14_BNAINTR field value from a register. */
101810 #define ALT_USB_DEV_DIEPINT14_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
101811 /* Produces a ALT_USB_DEV_DIEPINT14_BNAINTR register field value suitable for setting the register. */
101812 #define ALT_USB_DEV_DIEPINT14_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
101813 
101814 /*
101815  * Field : pktdrpsts
101816  *
101817  * Packet Drop Status (PktDrpSts)
101818  *
101819  * This bit indicates to the application that an ISOC OUT packet has been dropped.
101820  * This
101821  *
101822  * bit does not have an associated mask bit and does not generate an interrupt.
101823  *
101824  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
101825  * transfer
101826  *
101827  * interrupt feature is selected.
101828  *
101829  * Field Enumeration Values:
101830  *
101831  * Enum | Value | Description
101832  * :----------------------------------------|:------|:-----------------------------
101833  * ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_INACT | 0x0 | No interrupt
101834  * ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
101835  *
101836  * Field Access Macros:
101837  *
101838  */
101839 /*
101840  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_PKTDRPSTS
101841  *
101842  * No interrupt
101843  */
101844 #define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_INACT 0x0
101845 /*
101846  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_PKTDRPSTS
101847  *
101848  * Packet Drop Status interrupt
101849  */
101850 #define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_ACT 0x1
101851 
101852 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */
101853 #define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_LSB 11
101854 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */
101855 #define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_MSB 11
101856 /* The width in bits of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */
101857 #define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_WIDTH 1
101858 /* The mask used to set the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field value. */
101859 #define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_SET_MSK 0x00000800
101860 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field value. */
101861 #define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_CLR_MSK 0xfffff7ff
101862 /* The reset value of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */
101863 #define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_RESET 0x0
101864 /* Extracts the ALT_USB_DEV_DIEPINT14_PKTDRPSTS field value from a register. */
101865 #define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
101866 /* Produces a ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field value suitable for setting the register. */
101867 #define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
101868 
101869 /*
101870  * Field : bbleerr
101871  *
101872  * NAK Interrupt (BbleErr)
101873  *
101874  * The core generates this interrupt when babble is received for the endpoint.
101875  *
101876  * Field Enumeration Values:
101877  *
101878  * Enum | Value | Description
101879  * :--------------------------------------|:------|:------------------
101880  * ALT_USB_DEV_DIEPINT14_BBLEERR_E_INACT | 0x0 | No interrupt
101881  * ALT_USB_DEV_DIEPINT14_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
101882  *
101883  * Field Access Macros:
101884  *
101885  */
101886 /*
101887  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_BBLEERR
101888  *
101889  * No interrupt
101890  */
101891 #define ALT_USB_DEV_DIEPINT14_BBLEERR_E_INACT 0x0
101892 /*
101893  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_BBLEERR
101894  *
101895  * BbleErr interrupt
101896  */
101897 #define ALT_USB_DEV_DIEPINT14_BBLEERR_E_ACT 0x1
101898 
101899 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */
101900 #define ALT_USB_DEV_DIEPINT14_BBLEERR_LSB 12
101901 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */
101902 #define ALT_USB_DEV_DIEPINT14_BBLEERR_MSB 12
101903 /* The width in bits of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */
101904 #define ALT_USB_DEV_DIEPINT14_BBLEERR_WIDTH 1
101905 /* The mask used to set the ALT_USB_DEV_DIEPINT14_BBLEERR register field value. */
101906 #define ALT_USB_DEV_DIEPINT14_BBLEERR_SET_MSK 0x00001000
101907 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_BBLEERR register field value. */
101908 #define ALT_USB_DEV_DIEPINT14_BBLEERR_CLR_MSK 0xffffefff
101909 /* The reset value of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */
101910 #define ALT_USB_DEV_DIEPINT14_BBLEERR_RESET 0x0
101911 /* Extracts the ALT_USB_DEV_DIEPINT14_BBLEERR field value from a register. */
101912 #define ALT_USB_DEV_DIEPINT14_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
101913 /* Produces a ALT_USB_DEV_DIEPINT14_BBLEERR register field value suitable for setting the register. */
101914 #define ALT_USB_DEV_DIEPINT14_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
101915 
101916 /*
101917  * Field : nakintrpt
101918  *
101919  * NAK Interrupt (NAKInterrupt)
101920  *
101921  * The core generates this interrupt when a NAK is transmitted or received by the
101922  * device.
101923  *
101924  * In case of isochronous IN endpoints the interrupt gets generated when a zero
101925  * length
101926  *
101927  * packet is transmitted due to un-availability of data in the TXFifo.
101928  *
101929  * Field Enumeration Values:
101930  *
101931  * Enum | Value | Description
101932  * :----------------------------------------|:------|:--------------
101933  * ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_INACT | 0x0 | No interrupt
101934  * ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
101935  *
101936  * Field Access Macros:
101937  *
101938  */
101939 /*
101940  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_NAKINTRPT
101941  *
101942  * No interrupt
101943  */
101944 #define ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_INACT 0x0
101945 /*
101946  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_NAKINTRPT
101947  *
101948  * NAK Interrupt
101949  */
101950 #define ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_ACT 0x1
101951 
101952 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */
101953 #define ALT_USB_DEV_DIEPINT14_NAKINTRPT_LSB 13
101954 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */
101955 #define ALT_USB_DEV_DIEPINT14_NAKINTRPT_MSB 13
101956 /* The width in bits of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */
101957 #define ALT_USB_DEV_DIEPINT14_NAKINTRPT_WIDTH 1
101958 /* The mask used to set the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field value. */
101959 #define ALT_USB_DEV_DIEPINT14_NAKINTRPT_SET_MSK 0x00002000
101960 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field value. */
101961 #define ALT_USB_DEV_DIEPINT14_NAKINTRPT_CLR_MSK 0xffffdfff
101962 /* The reset value of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */
101963 #define ALT_USB_DEV_DIEPINT14_NAKINTRPT_RESET 0x0
101964 /* Extracts the ALT_USB_DEV_DIEPINT14_NAKINTRPT field value from a register. */
101965 #define ALT_USB_DEV_DIEPINT14_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
101966 /* Produces a ALT_USB_DEV_DIEPINT14_NAKINTRPT register field value suitable for setting the register. */
101967 #define ALT_USB_DEV_DIEPINT14_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
101968 
101969 /*
101970  * Field : nyetintrpt
101971  *
101972  * NYET Interrupt (NYETIntrpt)
101973  *
101974  * The core generates this interrupt when a NYET response is transmitted for a non
101975  * isochronous OUT endpoint.
101976  *
101977  * Field Enumeration Values:
101978  *
101979  * Enum | Value | Description
101980  * :-----------------------------------------|:------|:---------------
101981  * ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_INACT | 0x0 | No interrupt
101982  * ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
101983  *
101984  * Field Access Macros:
101985  *
101986  */
101987 /*
101988  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_NYETINTRPT
101989  *
101990  * No interrupt
101991  */
101992 #define ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_INACT 0x0
101993 /*
101994  * Enumerated value for register field ALT_USB_DEV_DIEPINT14_NYETINTRPT
101995  *
101996  * NYET Interrupt
101997  */
101998 #define ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_ACT 0x1
101999 
102000 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */
102001 #define ALT_USB_DEV_DIEPINT14_NYETINTRPT_LSB 14
102002 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */
102003 #define ALT_USB_DEV_DIEPINT14_NYETINTRPT_MSB 14
102004 /* The width in bits of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */
102005 #define ALT_USB_DEV_DIEPINT14_NYETINTRPT_WIDTH 1
102006 /* The mask used to set the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field value. */
102007 #define ALT_USB_DEV_DIEPINT14_NYETINTRPT_SET_MSK 0x00004000
102008 /* The mask used to clear the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field value. */
102009 #define ALT_USB_DEV_DIEPINT14_NYETINTRPT_CLR_MSK 0xffffbfff
102010 /* The reset value of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */
102011 #define ALT_USB_DEV_DIEPINT14_NYETINTRPT_RESET 0x0
102012 /* Extracts the ALT_USB_DEV_DIEPINT14_NYETINTRPT field value from a register. */
102013 #define ALT_USB_DEV_DIEPINT14_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
102014 /* Produces a ALT_USB_DEV_DIEPINT14_NYETINTRPT register field value suitable for setting the register. */
102015 #define ALT_USB_DEV_DIEPINT14_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
102016 
102017 #ifndef __ASSEMBLY__
102018 /*
102019  * WARNING: The C register and register group struct declarations are provided for
102020  * convenience and illustrative purposes. They should, however, be used with
102021  * caution as the C language standard provides no guarantees about the alignment or
102022  * atomicity of device memory accesses. The recommended practice for writing
102023  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
102024  * alt_write_word() functions.
102025  *
102026  * The struct declaration for register ALT_USB_DEV_DIEPINT14.
102027  */
102028 struct ALT_USB_DEV_DIEPINT14_s
102029 {
102030  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT14_XFERCOMPL */
102031  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT14_EPDISBLD */
102032  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT14_AHBERR */
102033  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT14_TMO */
102034  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT14_INTKNTXFEMP */
102035  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT14_INTKNEPMIS */
102036  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT14_INEPNAKEFF */
102037  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT14_TXFEMP */
102038  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN */
102039  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT14_BNAINTR */
102040  uint32_t : 1; /* *UNDEFINED* */
102041  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT14_PKTDRPSTS */
102042  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT14_BBLEERR */
102043  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT14_NAKINTRPT */
102044  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT14_NYETINTRPT */
102045  uint32_t : 17; /* *UNDEFINED* */
102046 };
102047 
102048 /* The typedef declaration for register ALT_USB_DEV_DIEPINT14. */
102049 typedef volatile struct ALT_USB_DEV_DIEPINT14_s ALT_USB_DEV_DIEPINT14_t;
102050 #endif /* __ASSEMBLY__ */
102051 
102052 /* The reset value of the ALT_USB_DEV_DIEPINT14 register. */
102053 #define ALT_USB_DEV_DIEPINT14_RESET 0x00000080
102054 /* The byte offset of the ALT_USB_DEV_DIEPINT14 register from the beginning of the component. */
102055 #define ALT_USB_DEV_DIEPINT14_OFST 0x2c8
102056 /* The address of the ALT_USB_DEV_DIEPINT14 register. */
102057 #define ALT_USB_DEV_DIEPINT14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT14_OFST))
102058 
102059 /*
102060  * Register : dieptsiz14
102061  *
102062  * Device IN Endpoint 14 Transfer Size Register
102063  *
102064  * Register Layout
102065  *
102066  * Bits | Access | Reset | Description
102067  * :--------|:-------|:------|:--------------------------------
102068  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ14_XFERSIZE
102069  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ14_PKTCNT
102070  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ14_MC
102071  * [31] | ??? | 0x0 | *UNDEFINED*
102072  *
102073  */
102074 /*
102075  * Field : xfersize
102076  *
102077  * Transfer Size (XferSize)
102078  *
102079  * Indicates the transfer size in bytes For endpoint 0. The core
102080  *
102081  * interrupts the application only after it has exhausted the transfer
102082  *
102083  * size amount of data. The transfer size can be Set to the
102084  *
102085  * maximum packet size of the endpoint, to be interrupted at the
102086  *
102087  * end of each packet.
102088  *
102089  * The core decrements this field every time a packet from the
102090  *
102091  * external memory is written to the TxFIFO.
102092  *
102093  * Field Access Macros:
102094  *
102095  */
102096 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */
102097 #define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_LSB 0
102098 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */
102099 #define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_MSB 18
102100 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */
102101 #define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_WIDTH 19
102102 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field value. */
102103 #define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_SET_MSK 0x0007ffff
102104 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field value. */
102105 #define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_CLR_MSK 0xfff80000
102106 /* The reset value of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */
102107 #define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_RESET 0x0
102108 /* Extracts the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE field value from a register. */
102109 #define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
102110 /* Produces a ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field value suitable for setting the register. */
102111 #define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
102112 
102113 /*
102114  * Field : pktcnt
102115  *
102116  * Packet Count (PktCnt)
102117  *
102118  * Indicates the total number of USB packets that constitute the
102119  *
102120  * Transfer Size amount of data For endpoint 0.
102121  *
102122  * This field is decremented every time a packet (maximum size or
102123  *
102124  * short packet) is read from the TxFIFO.
102125  *
102126  * Field Access Macros:
102127  *
102128  */
102129 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */
102130 #define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_LSB 19
102131 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */
102132 #define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_MSB 28
102133 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */
102134 #define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_WIDTH 10
102135 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field value. */
102136 #define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_SET_MSK 0x1ff80000
102137 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field value. */
102138 #define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_CLR_MSK 0xe007ffff
102139 /* The reset value of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */
102140 #define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_RESET 0x0
102141 /* Extracts the ALT_USB_DEV_DIEPTSIZ14_PKTCNT field value from a register. */
102142 #define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
102143 /* Produces a ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field value suitable for setting the register. */
102144 #define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
102145 
102146 /*
102147  * Field : mc
102148  *
102149  * Applies to IN endpoints only.
102150  *
102151  * For periodic IN endpoints, this field indicates the number of packets that must
102152  * be transmitted per microframe on the USB. The core uses this field to calculate
102153  * the data PID for isochronous IN endpoints.
102154  *
102155  * 2'b01: 1 packet
102156  *
102157  * 2'b10: 2 packets
102158  *
102159  * 2'b11: 3 packets
102160  *
102161  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
102162  * specifies the number of packets the core must fetchfor an IN endpoint before it
102163  * switches to the endpoint pointed to by the Next Endpoint field of the Device
102164  * Endpoint-n Control register (DIEPCTLn.NextEp)
102165  *
102166  * Field Enumeration Values:
102167  *
102168  * Enum | Value | Description
102169  * :-------------------------------------|:------|:------------
102170  * ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTONE | 0x1 | 1 packet
102171  * ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTWO | 0x2 | 2 packets
102172  * ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTHREE | 0x3 | 3 packets
102173  *
102174  * Field Access Macros:
102175  *
102176  */
102177 /*
102178  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ14_MC
102179  *
102180  * 1 packet
102181  */
102182 #define ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTONE 0x1
102183 /*
102184  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ14_MC
102185  *
102186  * 2 packets
102187  */
102188 #define ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTWO 0x2
102189 /*
102190  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ14_MC
102191  *
102192  * 3 packets
102193  */
102194 #define ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTHREE 0x3
102195 
102196 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */
102197 #define ALT_USB_DEV_DIEPTSIZ14_MC_LSB 29
102198 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */
102199 #define ALT_USB_DEV_DIEPTSIZ14_MC_MSB 30
102200 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */
102201 #define ALT_USB_DEV_DIEPTSIZ14_MC_WIDTH 2
102202 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ14_MC register field value. */
102203 #define ALT_USB_DEV_DIEPTSIZ14_MC_SET_MSK 0x60000000
102204 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ14_MC register field value. */
102205 #define ALT_USB_DEV_DIEPTSIZ14_MC_CLR_MSK 0x9fffffff
102206 /* The reset value of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */
102207 #define ALT_USB_DEV_DIEPTSIZ14_MC_RESET 0x0
102208 /* Extracts the ALT_USB_DEV_DIEPTSIZ14_MC field value from a register. */
102209 #define ALT_USB_DEV_DIEPTSIZ14_MC_GET(value) (((value) & 0x60000000) >> 29)
102210 /* Produces a ALT_USB_DEV_DIEPTSIZ14_MC register field value suitable for setting the register. */
102211 #define ALT_USB_DEV_DIEPTSIZ14_MC_SET(value) (((value) << 29) & 0x60000000)
102212 
102213 #ifndef __ASSEMBLY__
102214 /*
102215  * WARNING: The C register and register group struct declarations are provided for
102216  * convenience and illustrative purposes. They should, however, be used with
102217  * caution as the C language standard provides no guarantees about the alignment or
102218  * atomicity of device memory accesses. The recommended practice for writing
102219  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
102220  * alt_write_word() functions.
102221  *
102222  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ14.
102223  */
102224 struct ALT_USB_DEV_DIEPTSIZ14_s
102225 {
102226  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ14_XFERSIZE */
102227  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ14_PKTCNT */
102228  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ14_MC */
102229  uint32_t : 1; /* *UNDEFINED* */
102230 };
102231 
102232 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ14. */
102233 typedef volatile struct ALT_USB_DEV_DIEPTSIZ14_s ALT_USB_DEV_DIEPTSIZ14_t;
102234 #endif /* __ASSEMBLY__ */
102235 
102236 /* The reset value of the ALT_USB_DEV_DIEPTSIZ14 register. */
102237 #define ALT_USB_DEV_DIEPTSIZ14_RESET 0x00000000
102238 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ14 register from the beginning of the component. */
102239 #define ALT_USB_DEV_DIEPTSIZ14_OFST 0x2d0
102240 /* The address of the ALT_USB_DEV_DIEPTSIZ14 register. */
102241 #define ALT_USB_DEV_DIEPTSIZ14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ14_OFST))
102242 
102243 /*
102244  * Register : diepdma14
102245  *
102246  * Device IN Endpoint 14 DMA Address Register
102247  *
102248  * Register Layout
102249  *
102250  * Bits | Access | Reset | Description
102251  * :-------|:-------|:--------|:--------------------------------
102252  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA14_DIEPDMA14
102253  *
102254  */
102255 /*
102256  * Field : diepdma14
102257  *
102258  * Holds the start address of the external memory for storing or fetching endpoint
102259  *
102260  * data.
102261  *
102262  * Note: For control endpoints, this field stores control OUT data packets as well
102263  * as
102264  *
102265  * SETUP transaction data packets. When more than three SETUP packets are
102266  *
102267  * received back-to-back, the SETUP data packet in the memory is overwritten.
102268  *
102269  * This register is incremented on every AHB transaction. The application can give
102270  *
102271  * only a DWORD-aligned address.
102272  *
102273  * When Scatter/Gather DMA mode is not enabled, the application programs the
102274  *
102275  * start address value in this field.
102276  *
102277  * When Scatter/Gather DMA mode is enabled, this field indicates the base
102278  *
102279  * pointer for the descriptor list.
102280  *
102281  * Field Access Macros:
102282  *
102283  */
102284 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field. */
102285 #define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_LSB 0
102286 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field. */
102287 #define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_MSB 31
102288 /* The width in bits of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field. */
102289 #define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_WIDTH 32
102290 /* The mask used to set the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field value. */
102291 #define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_SET_MSK 0xffffffff
102292 /* The mask used to clear the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field value. */
102293 #define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_CLR_MSK 0x00000000
102294 /* The reset value of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field is UNKNOWN. */
102295 #define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_RESET 0x0
102296 /* Extracts the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 field value from a register. */
102297 #define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_GET(value) (((value) & 0xffffffff) >> 0)
102298 /* Produces a ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field value suitable for setting the register. */
102299 #define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_SET(value) (((value) << 0) & 0xffffffff)
102300 
102301 #ifndef __ASSEMBLY__
102302 /*
102303  * WARNING: The C register and register group struct declarations are provided for
102304  * convenience and illustrative purposes. They should, however, be used with
102305  * caution as the C language standard provides no guarantees about the alignment or
102306  * atomicity of device memory accesses. The recommended practice for writing
102307  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
102308  * alt_write_word() functions.
102309  *
102310  * The struct declaration for register ALT_USB_DEV_DIEPDMA14.
102311  */
102312 struct ALT_USB_DEV_DIEPDMA14_s
102313 {
102314  uint32_t diepdma14 : 32; /* ALT_USB_DEV_DIEPDMA14_DIEPDMA14 */
102315 };
102316 
102317 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA14. */
102318 typedef volatile struct ALT_USB_DEV_DIEPDMA14_s ALT_USB_DEV_DIEPDMA14_t;
102319 #endif /* __ASSEMBLY__ */
102320 
102321 /* The reset value of the ALT_USB_DEV_DIEPDMA14 register. */
102322 #define ALT_USB_DEV_DIEPDMA14_RESET 0x00000000
102323 /* The byte offset of the ALT_USB_DEV_DIEPDMA14 register from the beginning of the component. */
102324 #define ALT_USB_DEV_DIEPDMA14_OFST 0x2d4
102325 /* The address of the ALT_USB_DEV_DIEPDMA14 register. */
102326 #define ALT_USB_DEV_DIEPDMA14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA14_OFST))
102327 
102328 /*
102329  * Register : dtxfsts14
102330  *
102331  * Device IN Endpoint Transmit FIFO Status Register 14
102332  *
102333  * Register Layout
102334  *
102335  * Bits | Access | Reset | Description
102336  * :--------|:-------|:-------|:--------------------------------------
102337  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL
102338  * [31:16] | ??? | 0x0 | *UNDEFINED*
102339  *
102340  */
102341 /*
102342  * Field : ineptxfspcavail
102343  *
102344  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
102345  *
102346  * Indicates the amount of free space available in the Endpoint
102347  *
102348  * TxFIFO.
102349  *
102350  * Values are in terms of 32-bit words.
102351  *
102352  * 16'h0: Endpoint TxFIFO is full
102353  *
102354  * 16'h1: 1 word available
102355  *
102356  * 16'h2: 2 words available
102357  *
102358  * 16'hn: n words available (where 0 n 32,768)
102359  *
102360  * 16'h8000: 32,768 words available
102361  *
102362  * Others: Reserved
102363  *
102364  * Field Access Macros:
102365  *
102366  */
102367 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */
102368 #define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_LSB 0
102369 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */
102370 #define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_MSB 15
102371 /* The width in bits of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */
102372 #define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_WIDTH 16
102373 /* The mask used to set the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field value. */
102374 #define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
102375 /* The mask used to clear the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field value. */
102376 #define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
102377 /* The reset value of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */
102378 #define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_RESET 0x2000
102379 /* Extracts the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL field value from a register. */
102380 #define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
102381 /* Produces a ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field value suitable for setting the register. */
102382 #define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
102383 
102384 #ifndef __ASSEMBLY__
102385 /*
102386  * WARNING: The C register and register group struct declarations are provided for
102387  * convenience and illustrative purposes. They should, however, be used with
102388  * caution as the C language standard provides no guarantees about the alignment or
102389  * atomicity of device memory accesses. The recommended practice for writing
102390  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
102391  * alt_write_word() functions.
102392  *
102393  * The struct declaration for register ALT_USB_DEV_DTXFSTS14.
102394  */
102395 struct ALT_USB_DEV_DTXFSTS14_s
102396 {
102397  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL */
102398  uint32_t : 16; /* *UNDEFINED* */
102399 };
102400 
102401 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS14. */
102402 typedef volatile struct ALT_USB_DEV_DTXFSTS14_s ALT_USB_DEV_DTXFSTS14_t;
102403 #endif /* __ASSEMBLY__ */
102404 
102405 /* The reset value of the ALT_USB_DEV_DTXFSTS14 register. */
102406 #define ALT_USB_DEV_DTXFSTS14_RESET 0x00002000
102407 /* The byte offset of the ALT_USB_DEV_DTXFSTS14 register from the beginning of the component. */
102408 #define ALT_USB_DEV_DTXFSTS14_OFST 0x2d8
102409 /* The address of the ALT_USB_DEV_DTXFSTS14 register. */
102410 #define ALT_USB_DEV_DTXFSTS14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS14_OFST))
102411 
102412 /*
102413  * Register : diepdmab14
102414  *
102415  * Device IN Endpoint 14 Buffer Address Register
102416  *
102417  * Register Layout
102418  *
102419  * Bits | Access | Reset | Description
102420  * :-------|:-------|:--------|:----------------------------------
102421  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14
102422  *
102423  */
102424 /*
102425  * Field : diepdmab14
102426  *
102427  * Holds the current buffer address.This register is updated as and when the data
102428  *
102429  * transfer for the corresponding end point is in progress.
102430  *
102431  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
102432  * is
102433  *
102434  * reserved.
102435  *
102436  * Field Access Macros:
102437  *
102438  */
102439 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field. */
102440 #define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_LSB 0
102441 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field. */
102442 #define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_MSB 31
102443 /* The width in bits of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field. */
102444 #define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_WIDTH 32
102445 /* The mask used to set the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field value. */
102446 #define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_SET_MSK 0xffffffff
102447 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field value. */
102448 #define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_CLR_MSK 0x00000000
102449 /* The reset value of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field is UNKNOWN. */
102450 #define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_RESET 0x0
102451 /* Extracts the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 field value from a register. */
102452 #define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_GET(value) (((value) & 0xffffffff) >> 0)
102453 /* Produces a ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field value suitable for setting the register. */
102454 #define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_SET(value) (((value) << 0) & 0xffffffff)
102455 
102456 #ifndef __ASSEMBLY__
102457 /*
102458  * WARNING: The C register and register group struct declarations are provided for
102459  * convenience and illustrative purposes. They should, however, be used with
102460  * caution as the C language standard provides no guarantees about the alignment or
102461  * atomicity of device memory accesses. The recommended practice for writing
102462  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
102463  * alt_write_word() functions.
102464  *
102465  * The struct declaration for register ALT_USB_DEV_DIEPDMAB14.
102466  */
102467 struct ALT_USB_DEV_DIEPDMAB14_s
102468 {
102469  const uint32_t diepdmab14 : 32; /* ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 */
102470 };
102471 
102472 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB14. */
102473 typedef volatile struct ALT_USB_DEV_DIEPDMAB14_s ALT_USB_DEV_DIEPDMAB14_t;
102474 #endif /* __ASSEMBLY__ */
102475 
102476 /* The reset value of the ALT_USB_DEV_DIEPDMAB14 register. */
102477 #define ALT_USB_DEV_DIEPDMAB14_RESET 0x00000000
102478 /* The byte offset of the ALT_USB_DEV_DIEPDMAB14 register from the beginning of the component. */
102479 #define ALT_USB_DEV_DIEPDMAB14_OFST 0x2dc
102480 /* The address of the ALT_USB_DEV_DIEPDMAB14 register. */
102481 #define ALT_USB_DEV_DIEPDMAB14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB14_OFST))
102482 
102483 /*
102484  * Register : diepctl15
102485  *
102486  * Device Control IN Endpoint 15 Control Register
102487  *
102488  * Register Layout
102489  *
102490  * Bits | Access | Reset | Description
102491  * :--------|:---------|:------|:-------------------------------
102492  * [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL15_MPS
102493  * [14:11] | ??? | 0x0 | *UNDEFINED*
102494  * [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL15_USBACTEP
102495  * [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL15_DPID
102496  * [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL15_NAKSTS
102497  * [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL15_EPTYPE
102498  * [20] | ??? | 0x0 | *UNDEFINED*
102499  * [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL15_STALL
102500  * [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL15_TXFNUM
102501  * [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL15_CNAK
102502  * [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL15_SNAK
102503  * [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL15_SETD0PID
102504  * [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL15_SETD1PID
102505  * [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL15_EPDIS
102506  * [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL15_EPENA
102507  *
102508  */
102509 /*
102510  * Field : mps
102511  *
102512  * Maximum Packet Size (MPS)
102513  *
102514  * The application must program this field with the maximum packet size for the
102515  * current
102516  *
102517  * logical endpoint. This value is in bytes.
102518  *
102519  * Field Access Macros:
102520  *
102521  */
102522 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_MPS register field. */
102523 #define ALT_USB_DEV_DIEPCTL15_MPS_LSB 0
102524 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_MPS register field. */
102525 #define ALT_USB_DEV_DIEPCTL15_MPS_MSB 10
102526 /* The width in bits of the ALT_USB_DEV_DIEPCTL15_MPS register field. */
102527 #define ALT_USB_DEV_DIEPCTL15_MPS_WIDTH 11
102528 /* The mask used to set the ALT_USB_DEV_DIEPCTL15_MPS register field value. */
102529 #define ALT_USB_DEV_DIEPCTL15_MPS_SET_MSK 0x000007ff
102530 /* The mask used to clear the ALT_USB_DEV_DIEPCTL15_MPS register field value. */
102531 #define ALT_USB_DEV_DIEPCTL15_MPS_CLR_MSK 0xfffff800
102532 /* The reset value of the ALT_USB_DEV_DIEPCTL15_MPS register field. */
102533 #define ALT_USB_DEV_DIEPCTL15_MPS_RESET 0x0
102534 /* Extracts the ALT_USB_DEV_DIEPCTL15_MPS field value from a register. */
102535 #define ALT_USB_DEV_DIEPCTL15_MPS_GET(value) (((value) & 0x000007ff) >> 0)
102536 /* Produces a ALT_USB_DEV_DIEPCTL15_MPS register field value suitable for setting the register. */
102537 #define ALT_USB_DEV_DIEPCTL15_MPS_SET(value) (((value) << 0) & 0x000007ff)
102538 
102539 /*
102540  * Field : usbactep
102541  *
102542  * USB Active Endpoint (USBActEP)
102543  *
102544  * Indicates whether this endpoint is active in the current configuration and
102545  * interface. The
102546  *
102547  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
102548  * reset. After
102549  *
102550  * receiving the SetConfiguration and SetInterface commands, the application must
102551  *
102552  * program endpoint registers accordingly and set this bit.
102553  *
102554  * Field Enumeration Values:
102555  *
102556  * Enum | Value | Description
102557  * :--------------------------------------|:------|:--------------------
102558  * ALT_USB_DEV_DIEPCTL15_USBACTEP_E_DISD | 0x0 | Not Active
102559  * ALT_USB_DEV_DIEPCTL15_USBACTEP_E_END | 0x1 | USB Active Endpoint
102560  *
102561  * Field Access Macros:
102562  *
102563  */
102564 /*
102565  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_USBACTEP
102566  *
102567  * Not Active
102568  */
102569 #define ALT_USB_DEV_DIEPCTL15_USBACTEP_E_DISD 0x0
102570 /*
102571  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_USBACTEP
102572  *
102573  * USB Active Endpoint
102574  */
102575 #define ALT_USB_DEV_DIEPCTL15_USBACTEP_E_END 0x1
102576 
102577 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */
102578 #define ALT_USB_DEV_DIEPCTL15_USBACTEP_LSB 15
102579 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */
102580 #define ALT_USB_DEV_DIEPCTL15_USBACTEP_MSB 15
102581 /* The width in bits of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */
102582 #define ALT_USB_DEV_DIEPCTL15_USBACTEP_WIDTH 1
102583 /* The mask used to set the ALT_USB_DEV_DIEPCTL15_USBACTEP register field value. */
102584 #define ALT_USB_DEV_DIEPCTL15_USBACTEP_SET_MSK 0x00008000
102585 /* The mask used to clear the ALT_USB_DEV_DIEPCTL15_USBACTEP register field value. */
102586 #define ALT_USB_DEV_DIEPCTL15_USBACTEP_CLR_MSK 0xffff7fff
102587 /* The reset value of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */
102588 #define ALT_USB_DEV_DIEPCTL15_USBACTEP_RESET 0x0
102589 /* Extracts the ALT_USB_DEV_DIEPCTL15_USBACTEP field value from a register. */
102590 #define ALT_USB_DEV_DIEPCTL15_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
102591 /* Produces a ALT_USB_DEV_DIEPCTL15_USBACTEP register field value suitable for setting the register. */
102592 #define ALT_USB_DEV_DIEPCTL15_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
102593 
102594 /*
102595  * Field : dpid
102596  *
102597  * Endpoint Data PID (DPID)
102598  *
102599  * Applies to interrupt/bulk IN and OUT endpoints only.
102600  *
102601  * Contains the PID of the packet to be received or transmitted on this endpoint.
102602  * The
102603  *
102604  * application must program the PID of the first packet to be received or
102605  * transmitted on
102606  *
102607  * this endpoint, after the endpoint is activated. The applications use the
102608  * SetD1PID and
102609  *
102610  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
102611  *
102612  * 1'b0: DATA0
102613  *
102614  * 1'b1: DATA1
102615  *
102616  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
102617  *
102618  * DMA mode.
102619  *
102620  * 1'b0 RO
102621  *
102622  * Even/Odd (Micro)Frame (EO_FrNum)
102623  *
102624  * In non-Scatter/Gather DMA mode:
102625  *
102626  * Applies to isochronous IN and OUT endpoints only.
102627  *
102628  * Indicates the (micro)frame number in which the core transmits/receives
102629  * isochronous
102630  *
102631  * data for this endpoint. The application must program the even/odd (micro) frame
102632  *
102633  * number in which it intends to transmit/receive isochronous data for this
102634  * endpoint using
102635  *
102636  * the SetEvnFr and SetOddFr fields in this register.
102637  *
102638  * 1'b0: Even (micro)frame
102639  *
102640  * 1'b1: Odd (micro)frame
102641  *
102642  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
102643  * number
102644  *
102645  * in which to send data is provided in the transmit descriptor structure. The
102646  * frame in
102647  *
102648  * which data is received is updated in receive descriptor structure.
102649  *
102650  * Field Enumeration Values:
102651  *
102652  * Enum | Value | Description
102653  * :-----------------------------------|:------|:-----------------------------
102654  * ALT_USB_DEV_DIEPCTL15_DPID_E_INACT | 0x0 | Endpoint Data PID not active
102655  * ALT_USB_DEV_DIEPCTL15_DPID_E_ACT | 0x1 | Endpoint Data PID active
102656  *
102657  * Field Access Macros:
102658  *
102659  */
102660 /*
102661  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_DPID
102662  *
102663  * Endpoint Data PID not active
102664  */
102665 #define ALT_USB_DEV_DIEPCTL15_DPID_E_INACT 0x0
102666 /*
102667  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_DPID
102668  *
102669  * Endpoint Data PID active
102670  */
102671 #define ALT_USB_DEV_DIEPCTL15_DPID_E_ACT 0x1
102672 
102673 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_DPID register field. */
102674 #define ALT_USB_DEV_DIEPCTL15_DPID_LSB 16
102675 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_DPID register field. */
102676 #define ALT_USB_DEV_DIEPCTL15_DPID_MSB 16
102677 /* The width in bits of the ALT_USB_DEV_DIEPCTL15_DPID register field. */
102678 #define ALT_USB_DEV_DIEPCTL15_DPID_WIDTH 1
102679 /* The mask used to set the ALT_USB_DEV_DIEPCTL15_DPID register field value. */
102680 #define ALT_USB_DEV_DIEPCTL15_DPID_SET_MSK 0x00010000
102681 /* The mask used to clear the ALT_USB_DEV_DIEPCTL15_DPID register field value. */
102682 #define ALT_USB_DEV_DIEPCTL15_DPID_CLR_MSK 0xfffeffff
102683 /* The reset value of the ALT_USB_DEV_DIEPCTL15_DPID register field. */
102684 #define ALT_USB_DEV_DIEPCTL15_DPID_RESET 0x0
102685 /* Extracts the ALT_USB_DEV_DIEPCTL15_DPID field value from a register. */
102686 #define ALT_USB_DEV_DIEPCTL15_DPID_GET(value) (((value) & 0x00010000) >> 16)
102687 /* Produces a ALT_USB_DEV_DIEPCTL15_DPID register field value suitable for setting the register. */
102688 #define ALT_USB_DEV_DIEPCTL15_DPID_SET(value) (((value) << 16) & 0x00010000)
102689 
102690 /*
102691  * Field : naksts
102692  *
102693  * NAK Status (NAKSts)
102694  *
102695  * Indicates the following:
102696  *
102697  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
102698  *
102699  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
102700  *
102701  * When either the application or the core sets this bit:
102702  *
102703  * The core stops receiving any data on an OUT endpoint, even if there is space in
102704  *
102705  * the RxFIFO to accommodate the incoming packet.
102706  *
102707  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
102708  *
102709  * endpoint, even if there data is available in the TxFIFO.
102710  *
102711  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
102712  *
102713  * if there data is available in the TxFIFO.
102714  *
102715  * Irrespective of this bit's setting, the core always responds to SETUP data
102716  * packets with
102717  *
102718  * an ACK handshake.
102719  *
102720  * Field Enumeration Values:
102721  *
102722  * Enum | Value | Description
102723  * :--------------------------------------|:------|:------------------------------------------------
102724  * ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
102725  * : | | based on the FIFO status
102726  * ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
102727  * : | | endpoint
102728  *
102729  * Field Access Macros:
102730  *
102731  */
102732 /*
102733  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_NAKSTS
102734  *
102735  * The core is transmitting non-NAK handshakes based on the FIFO status
102736  */
102737 #define ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NONNAK 0x0
102738 /*
102739  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_NAKSTS
102740  *
102741  * The core is transmitting NAK handshakes on this endpoint
102742  */
102743 #define ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NAK 0x1
102744 
102745 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */
102746 #define ALT_USB_DEV_DIEPCTL15_NAKSTS_LSB 17
102747 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */
102748 #define ALT_USB_DEV_DIEPCTL15_NAKSTS_MSB 17
102749 /* The width in bits of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */
102750 #define ALT_USB_DEV_DIEPCTL15_NAKSTS_WIDTH 1
102751 /* The mask used to set the ALT_USB_DEV_DIEPCTL15_NAKSTS register field value. */
102752 #define ALT_USB_DEV_DIEPCTL15_NAKSTS_SET_MSK 0x00020000
102753 /* The mask used to clear the ALT_USB_DEV_DIEPCTL15_NAKSTS register field value. */
102754 #define ALT_USB_DEV_DIEPCTL15_NAKSTS_CLR_MSK 0xfffdffff
102755 /* The reset value of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */
102756 #define ALT_USB_DEV_DIEPCTL15_NAKSTS_RESET 0x0
102757 /* Extracts the ALT_USB_DEV_DIEPCTL15_NAKSTS field value from a register. */
102758 #define ALT_USB_DEV_DIEPCTL15_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
102759 /* Produces a ALT_USB_DEV_DIEPCTL15_NAKSTS register field value suitable for setting the register. */
102760 #define ALT_USB_DEV_DIEPCTL15_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
102761 
102762 /*
102763  * Field : eptype
102764  *
102765  * Endpoint Type (EPType)
102766  *
102767  * This is the transfer type supported by this logical endpoint.
102768  *
102769  * 2'b00: Control
102770  *
102771  * 2'b01: Isochronous
102772  *
102773  * 2'b10: Bulk
102774  *
102775  * 2'b11: Interrupt
102776  *
102777  * Field Enumeration Values:
102778  *
102779  * Enum | Value | Description
102780  * :-------------------------------------------|:------|:------------
102781  * ALT_USB_DEV_DIEPCTL15_EPTYPE_E_CTL | 0x0 | Control
102782  * ALT_USB_DEV_DIEPCTL15_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
102783  * ALT_USB_DEV_DIEPCTL15_EPTYPE_E_BULK | 0x2 | Bulk
102784  * ALT_USB_DEV_DIEPCTL15_EPTYPE_E_INTERRUP | 0x3 | Interrupt
102785  *
102786  * Field Access Macros:
102787  *
102788  */
102789 /*
102790  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
102791  *
102792  * Control
102793  */
102794 #define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_CTL 0x0
102795 /*
102796  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
102797  *
102798  * Isochronous
102799  */
102800 #define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_ISOCHRONOUS 0x1
102801 /*
102802  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
102803  *
102804  * Bulk
102805  */
102806 #define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_BULK 0x2
102807 /*
102808  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
102809  *
102810  * Interrupt
102811  */
102812 #define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_INTERRUP 0x3
102813 
102814 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */
102815 #define ALT_USB_DEV_DIEPCTL15_EPTYPE_LSB 18
102816 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */
102817 #define ALT_USB_DEV_DIEPCTL15_EPTYPE_MSB 19
102818 /* The width in bits of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */
102819 #define ALT_USB_DEV_DIEPCTL15_EPTYPE_WIDTH 2
102820 /* The mask used to set the ALT_USB_DEV_DIEPCTL15_EPTYPE register field value. */
102821 #define ALT_USB_DEV_DIEPCTL15_EPTYPE_SET_MSK 0x000c0000
102822 /* The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPTYPE register field value. */
102823 #define ALT_USB_DEV_DIEPCTL15_EPTYPE_CLR_MSK 0xfff3ffff
102824 /* The reset value of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */
102825 #define ALT_USB_DEV_DIEPCTL15_EPTYPE_RESET 0x0
102826 /* Extracts the ALT_USB_DEV_DIEPCTL15_EPTYPE field value from a register. */
102827 #define ALT_USB_DEV_DIEPCTL15_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
102828 /* Produces a ALT_USB_DEV_DIEPCTL15_EPTYPE register field value suitable for setting the register. */
102829 #define ALT_USB_DEV_DIEPCTL15_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
102830 
102831 /*
102832  * Field : stall
102833  *
102834  * STALL Handshake (Stall)
102835  *
102836  * Applies to non-control, non-isochronous IN and OUT endpoints only.
102837  *
102838  * The application sets this bit to stall all tokens from the USB host to this
102839  * endpoint. If a
102840  *
102841  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
102842  * bit, the
102843  *
102844  * STALL bit takes priority. Only the application can clear this bit, never the
102845  * core.
102846  *
102847  * 1'b0 R_W
102848  *
102849  * Applies to control endpoints only.
102850  *
102851  * The application can only set this bit, and the core clears it, when a SETUP
102852  * token is
102853  *
102854  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
102855  * OUT
102856  *
102857  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
102858  * this bit's
102859  *
102860  * setting, the core always responds to SETUP data packets with an ACK handshake.
102861  *
102862  * Field Enumeration Values:
102863  *
102864  * Enum | Value | Description
102865  * :------------------------------------|:------|:----------------------------
102866  * ALT_USB_DEV_DIEPCTL15_STALL_E_INACT | 0x0 | STALL All Tokens not active
102867  * ALT_USB_DEV_DIEPCTL15_STALL_E_ACT | 0x1 | STALL All Tokens active
102868  *
102869  * Field Access Macros:
102870  *
102871  */
102872 /*
102873  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_STALL
102874  *
102875  * STALL All Tokens not active
102876  */
102877 #define ALT_USB_DEV_DIEPCTL15_STALL_E_INACT 0x0
102878 /*
102879  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_STALL
102880  *
102881  * STALL All Tokens active
102882  */
102883 #define ALT_USB_DEV_DIEPCTL15_STALL_E_ACT 0x1
102884 
102885 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_STALL register field. */
102886 #define ALT_USB_DEV_DIEPCTL15_STALL_LSB 21
102887 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_STALL register field. */
102888 #define ALT_USB_DEV_DIEPCTL15_STALL_MSB 21
102889 /* The width in bits of the ALT_USB_DEV_DIEPCTL15_STALL register field. */
102890 #define ALT_USB_DEV_DIEPCTL15_STALL_WIDTH 1
102891 /* The mask used to set the ALT_USB_DEV_DIEPCTL15_STALL register field value. */
102892 #define ALT_USB_DEV_DIEPCTL15_STALL_SET_MSK 0x00200000
102893 /* The mask used to clear the ALT_USB_DEV_DIEPCTL15_STALL register field value. */
102894 #define ALT_USB_DEV_DIEPCTL15_STALL_CLR_MSK 0xffdfffff
102895 /* The reset value of the ALT_USB_DEV_DIEPCTL15_STALL register field. */
102896 #define ALT_USB_DEV_DIEPCTL15_STALL_RESET 0x0
102897 /* Extracts the ALT_USB_DEV_DIEPCTL15_STALL field value from a register. */
102898 #define ALT_USB_DEV_DIEPCTL15_STALL_GET(value) (((value) & 0x00200000) >> 21)
102899 /* Produces a ALT_USB_DEV_DIEPCTL15_STALL register field value suitable for setting the register. */
102900 #define ALT_USB_DEV_DIEPCTL15_STALL_SET(value) (((value) << 21) & 0x00200000)
102901 
102902 /*
102903  * Field : txfnum
102904  *
102905  * TxFIFO Number (TxFNum)
102906  *
102907  * Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
102908  *
102909  * endpoints must map this to the corresponding Periodic TxFIFO number.
102910  *
102911  * 4'h0: Non-Periodic TxFIFO
102912  *
102913  * Others: Specified Periodic TxFIFO.number
102914  *
102915  * Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
102916  *
102917  * applications such as mass storage. The core treats an IN endpoint as a non-
102918  * periodic
102919  *
102920  * endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
102921  * must be
102922  *
102923  * allocated for an interrupt IN endpoint, and the number of this
102924  *
102925  * FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
102926  *
102927  * endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
102928  *
102929  * Dedicated FIFO Operationthese bits specify the FIFO number associated with this
102930  *
102931  * endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
102932  *
102933  * This field is valid only for IN endpoints.
102934  *
102935  * Field Access Macros:
102936  *
102937  */
102938 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */
102939 #define ALT_USB_DEV_DIEPCTL15_TXFNUM_LSB 22
102940 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */
102941 #define ALT_USB_DEV_DIEPCTL15_TXFNUM_MSB 25
102942 /* The width in bits of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */
102943 #define ALT_USB_DEV_DIEPCTL15_TXFNUM_WIDTH 4
102944 /* The mask used to set the ALT_USB_DEV_DIEPCTL15_TXFNUM register field value. */
102945 #define ALT_USB_DEV_DIEPCTL15_TXFNUM_SET_MSK 0x03c00000
102946 /* The mask used to clear the ALT_USB_DEV_DIEPCTL15_TXFNUM register field value. */
102947 #define ALT_USB_DEV_DIEPCTL15_TXFNUM_CLR_MSK 0xfc3fffff
102948 /* The reset value of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */
102949 #define ALT_USB_DEV_DIEPCTL15_TXFNUM_RESET 0x0
102950 /* Extracts the ALT_USB_DEV_DIEPCTL15_TXFNUM field value from a register. */
102951 #define ALT_USB_DEV_DIEPCTL15_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
102952 /* Produces a ALT_USB_DEV_DIEPCTL15_TXFNUM register field value suitable for setting the register. */
102953 #define ALT_USB_DEV_DIEPCTL15_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
102954 
102955 /*
102956  * Field : cnak
102957  *
102958  * Clear NAK (CNAK)
102959  *
102960  * A write to this bit clears the NAK bit For the endpoint.
102961  *
102962  * Field Enumeration Values:
102963  *
102964  * Enum | Value | Description
102965  * :-----------------------------------|:------|:-------------
102966  * ALT_USB_DEV_DIEPCTL15_CNAK_E_INACT | 0x0 | No Clear NAK
102967  * ALT_USB_DEV_DIEPCTL15_CNAK_E_ACT | 0x1 | Clear NAK
102968  *
102969  * Field Access Macros:
102970  *
102971  */
102972 /*
102973  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_CNAK
102974  *
102975  * No Clear NAK
102976  */
102977 #define ALT_USB_DEV_DIEPCTL15_CNAK_E_INACT 0x0
102978 /*
102979  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_CNAK
102980  *
102981  * Clear NAK
102982  */
102983 #define ALT_USB_DEV_DIEPCTL15_CNAK_E_ACT 0x1
102984 
102985 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */
102986 #define ALT_USB_DEV_DIEPCTL15_CNAK_LSB 26
102987 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */
102988 #define ALT_USB_DEV_DIEPCTL15_CNAK_MSB 26
102989 /* The width in bits of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */
102990 #define ALT_USB_DEV_DIEPCTL15_CNAK_WIDTH 1
102991 /* The mask used to set the ALT_USB_DEV_DIEPCTL15_CNAK register field value. */
102992 #define ALT_USB_DEV_DIEPCTL15_CNAK_SET_MSK 0x04000000
102993 /* The mask used to clear the ALT_USB_DEV_DIEPCTL15_CNAK register field value. */
102994 #define ALT_USB_DEV_DIEPCTL15_CNAK_CLR_MSK 0xfbffffff
102995 /* The reset value of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */
102996 #define ALT_USB_DEV_DIEPCTL15_CNAK_RESET 0x0
102997 /* Extracts the ALT_USB_DEV_DIEPCTL15_CNAK field value from a register. */
102998 #define ALT_USB_DEV_DIEPCTL15_CNAK_GET(value) (((value) & 0x04000000) >> 26)
102999 /* Produces a ALT_USB_DEV_DIEPCTL15_CNAK register field value suitable for setting the register. */
103000 #define ALT_USB_DEV_DIEPCTL15_CNAK_SET(value) (((value) << 26) & 0x04000000)
103001 
103002 /*
103003  * Field : snak
103004  *
103005  * Set NAK (SNAK)
103006  *
103007  * A write to this bit sets the NAK bit For the endpoint.
103008  *
103009  * Using this bit, the application can control the transmission of NAK
103010  *
103011  * handshakes on an endpoint. The core can also Set this bit For an
103012  *
103013  * endpoint after a SETUP packet is received on that endpoint.
103014  *
103015  * Field Enumeration Values:
103016  *
103017  * Enum | Value | Description
103018  * :-----------------------------------|:------|:------------
103019  * ALT_USB_DEV_DIEPCTL15_SNAK_E_INACT | 0x0 | No Set NAK
103020  * ALT_USB_DEV_DIEPCTL15_SNAK_E_ACT | 0x1 | Set NAK
103021  *
103022  * Field Access Macros:
103023  *
103024  */
103025 /*
103026  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SNAK
103027  *
103028  * No Set NAK
103029  */
103030 #define ALT_USB_DEV_DIEPCTL15_SNAK_E_INACT 0x0
103031 /*
103032  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SNAK
103033  *
103034  * Set NAK
103035  */
103036 #define ALT_USB_DEV_DIEPCTL15_SNAK_E_ACT 0x1
103037 
103038 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */
103039 #define ALT_USB_DEV_DIEPCTL15_SNAK_LSB 27
103040 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */
103041 #define ALT_USB_DEV_DIEPCTL15_SNAK_MSB 27
103042 /* The width in bits of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */
103043 #define ALT_USB_DEV_DIEPCTL15_SNAK_WIDTH 1
103044 /* The mask used to set the ALT_USB_DEV_DIEPCTL15_SNAK register field value. */
103045 #define ALT_USB_DEV_DIEPCTL15_SNAK_SET_MSK 0x08000000
103046 /* The mask used to clear the ALT_USB_DEV_DIEPCTL15_SNAK register field value. */
103047 #define ALT_USB_DEV_DIEPCTL15_SNAK_CLR_MSK 0xf7ffffff
103048 /* The reset value of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */
103049 #define ALT_USB_DEV_DIEPCTL15_SNAK_RESET 0x0
103050 /* Extracts the ALT_USB_DEV_DIEPCTL15_SNAK field value from a register. */
103051 #define ALT_USB_DEV_DIEPCTL15_SNAK_GET(value) (((value) & 0x08000000) >> 27)
103052 /* Produces a ALT_USB_DEV_DIEPCTL15_SNAK register field value suitable for setting the register. */
103053 #define ALT_USB_DEV_DIEPCTL15_SNAK_SET(value) (((value) << 27) & 0x08000000)
103054 
103055 /*
103056  * Field : setd0pid
103057  *
103058  * Set DATA0 PID (SetD0PID)
103059  *
103060  * Applies to interrupt/bulk IN and OUT endpoints only.
103061  *
103062  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
103063  * to DATA0.
103064  *
103065  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
103066  *
103067  * DMA mode.
103068  *
103069  * 1'b0 WO
103070  *
103071  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
103072  *
103073  * Applies to isochronous IN and OUT endpoints only.
103074  *
103075  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
103076  * (micro)
103077  *
103078  * frame.
103079  *
103080  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
103081  * number
103082  *
103083  * in which to send data is in the transmit descriptor structure. The frame in
103084  * which to
103085  *
103086  * receive data is updated in receive descriptor structure.
103087  *
103088  * Field Enumeration Values:
103089  *
103090  * Enum | Value | Description
103091  * :--------------------------------------|:------|:----------------------------
103092  * ALT_USB_DEV_DIEPCTL15_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
103093  * ALT_USB_DEV_DIEPCTL15_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
103094  *
103095  * Field Access Macros:
103096  *
103097  */
103098 /*
103099  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD0PID
103100  *
103101  * Disables Set DATA0 PID
103102  */
103103 #define ALT_USB_DEV_DIEPCTL15_SETD0PID_E_DISD 0x0
103104 /*
103105  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD0PID
103106  *
103107  * Endpoint Data PID to DATA0)
103108  */
103109 #define ALT_USB_DEV_DIEPCTL15_SETD0PID_E_END 0x1
103110 
103111 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */
103112 #define ALT_USB_DEV_DIEPCTL15_SETD0PID_LSB 28
103113 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */
103114 #define ALT_USB_DEV_DIEPCTL15_SETD0PID_MSB 28
103115 /* The width in bits of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */
103116 #define ALT_USB_DEV_DIEPCTL15_SETD0PID_WIDTH 1
103117 /* The mask used to set the ALT_USB_DEV_DIEPCTL15_SETD0PID register field value. */
103118 #define ALT_USB_DEV_DIEPCTL15_SETD0PID_SET_MSK 0x10000000
103119 /* The mask used to clear the ALT_USB_DEV_DIEPCTL15_SETD0PID register field value. */
103120 #define ALT_USB_DEV_DIEPCTL15_SETD0PID_CLR_MSK 0xefffffff
103121 /* The reset value of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */
103122 #define ALT_USB_DEV_DIEPCTL15_SETD0PID_RESET 0x0
103123 /* Extracts the ALT_USB_DEV_DIEPCTL15_SETD0PID field value from a register. */
103124 #define ALT_USB_DEV_DIEPCTL15_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
103125 /* Produces a ALT_USB_DEV_DIEPCTL15_SETD0PID register field value suitable for setting the register. */
103126 #define ALT_USB_DEV_DIEPCTL15_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
103127 
103128 /*
103129  * Field : setd1pid
103130  *
103131  * Set DATA1 PID (SetD1PID)
103132  *
103133  * Applies to interrupt/bulk IN and OUT endpoints only.
103134  *
103135  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
103136  * to DATA1.
103137  *
103138  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
103139  *
103140  * DMA mode.
103141  *
103142  * Set Odd (micro)frame (SetOddFr)
103143  *
103144  * Applies to isochronous IN and OUT endpoints only.
103145  *
103146  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
103147  *
103148  * (micro)frame.
103149  *
103150  * This field is not applicable for Scatter/Gather DMA mode.
103151  *
103152  * Field Enumeration Values:
103153  *
103154  * Enum | Value | Description
103155  * :--------------------------------------|:------|:-----------------------
103156  * ALT_USB_DEV_DIEPCTL15_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
103157  * ALT_USB_DEV_DIEPCTL15_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
103158  *
103159  * Field Access Macros:
103160  *
103161  */
103162 /*
103163  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD1PID
103164  *
103165  * Disables Set DATA1 PID
103166  */
103167 #define ALT_USB_DEV_DIEPCTL15_SETD1PID_E_DISD 0x0
103168 /*
103169  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD1PID
103170  *
103171  * Enables Set DATA1 PID
103172  */
103173 #define ALT_USB_DEV_DIEPCTL15_SETD1PID_E_END 0x1
103174 
103175 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */
103176 #define ALT_USB_DEV_DIEPCTL15_SETD1PID_LSB 29
103177 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */
103178 #define ALT_USB_DEV_DIEPCTL15_SETD1PID_MSB 29
103179 /* The width in bits of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */
103180 #define ALT_USB_DEV_DIEPCTL15_SETD1PID_WIDTH 1
103181 /* The mask used to set the ALT_USB_DEV_DIEPCTL15_SETD1PID register field value. */
103182 #define ALT_USB_DEV_DIEPCTL15_SETD1PID_SET_MSK 0x20000000
103183 /* The mask used to clear the ALT_USB_DEV_DIEPCTL15_SETD1PID register field value. */
103184 #define ALT_USB_DEV_DIEPCTL15_SETD1PID_CLR_MSK 0xdfffffff
103185 /* The reset value of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */
103186 #define ALT_USB_DEV_DIEPCTL15_SETD1PID_RESET 0x0
103187 /* Extracts the ALT_USB_DEV_DIEPCTL15_SETD1PID field value from a register. */
103188 #define ALT_USB_DEV_DIEPCTL15_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
103189 /* Produces a ALT_USB_DEV_DIEPCTL15_SETD1PID register field value suitable for setting the register. */
103190 #define ALT_USB_DEV_DIEPCTL15_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
103191 
103192 /*
103193  * Field : epdis
103194  *
103195  * Endpoint Disable (EPDis)
103196  *
103197  * Applies to IN and OUT endpoints.
103198  *
103199  * The application sets this bit to stop transmitting/receiving data on an
103200  * endpoint, even
103201  *
103202  * before the transfer for that endpoint is complete. The application must wait for
103203  * the
103204  *
103205  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
103206  * clears
103207  *
103208  * this bit before setting the Endpoint Disabled interrupt. The application must
103209  * set this bit
103210  *
103211  * only if Endpoint Enable is already set for this endpoint.
103212  *
103213  * Field Enumeration Values:
103214  *
103215  * Enum | Value | Description
103216  * :------------------------------------|:------|:--------------------
103217  * ALT_USB_DEV_DIEPCTL15_EPDIS_E_INACT | 0x0 | No Endpoint Disable
103218  * ALT_USB_DEV_DIEPCTL15_EPDIS_E_ACT | 0x1 | Endpoint Disable
103219  *
103220  * Field Access Macros:
103221  *
103222  */
103223 /*
103224  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPDIS
103225  *
103226  * No Endpoint Disable
103227  */
103228 #define ALT_USB_DEV_DIEPCTL15_EPDIS_E_INACT 0x0
103229 /*
103230  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPDIS
103231  *
103232  * Endpoint Disable
103233  */
103234 #define ALT_USB_DEV_DIEPCTL15_EPDIS_E_ACT 0x1
103235 
103236 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */
103237 #define ALT_USB_DEV_DIEPCTL15_EPDIS_LSB 30
103238 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */
103239 #define ALT_USB_DEV_DIEPCTL15_EPDIS_MSB 30
103240 /* The width in bits of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */
103241 #define ALT_USB_DEV_DIEPCTL15_EPDIS_WIDTH 1
103242 /* The mask used to set the ALT_USB_DEV_DIEPCTL15_EPDIS register field value. */
103243 #define ALT_USB_DEV_DIEPCTL15_EPDIS_SET_MSK 0x40000000
103244 /* The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPDIS register field value. */
103245 #define ALT_USB_DEV_DIEPCTL15_EPDIS_CLR_MSK 0xbfffffff
103246 /* The reset value of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */
103247 #define ALT_USB_DEV_DIEPCTL15_EPDIS_RESET 0x0
103248 /* Extracts the ALT_USB_DEV_DIEPCTL15_EPDIS field value from a register. */
103249 #define ALT_USB_DEV_DIEPCTL15_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
103250 /* Produces a ALT_USB_DEV_DIEPCTL15_EPDIS register field value suitable for setting the register. */
103251 #define ALT_USB_DEV_DIEPCTL15_EPDIS_SET(value) (((value) << 30) & 0x40000000)
103252 
103253 /*
103254  * Field : epena
103255  *
103256  * Endpoint Enable (EPEna)
103257  *
103258  * Applies to IN and OUT endpoints.
103259  *
103260  * When Scatter/Gather DMA mode is enabled,
103261  *
103262  * For IN endpoints this bit indicates that the descriptor structure and data
103263  * buffer with
103264  *
103265  * data ready to transmit is setup.
103266  *
103267  * For OUT endpoint it indicates that the descriptor structure and data buffer to
103268  *
103269  * receive data is setup.
103270  *
103271  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
103272  *
103273  * DMA mode:
103274  *
103275  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
103276  * the
103277  *
103278  * endpoint.
103279  *
103280  * * For OUT endpoints, this bit indicates that the application has allocated the
103281  *
103282  * memory to start receiving data from the USB.
103283  *
103284  * * The core clears this bit before setting any of the following interrupts on
103285  * this
103286  *
103287  * endpoint:
103288  *
103289  * SETUP Phase Done
103290  *
103291  * Endpoint Disabled
103292  *
103293  * Transfer Completed
103294  *
103295  * Note: For control endpoints in DMA mode, this bit must be set to be able to
103296  * transfer
103297  *
103298  * SETUP data packets in memory.
103299  *
103300  * Field Enumeration Values:
103301  *
103302  * Enum | Value | Description
103303  * :------------------------------------|:------|:-------------------------
103304  * ALT_USB_DEV_DIEPCTL15_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
103305  * ALT_USB_DEV_DIEPCTL15_EPENA_E_ACT | 0x1 | Endpoint Enable active
103306  *
103307  * Field Access Macros:
103308  *
103309  */
103310 /*
103311  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPENA
103312  *
103313  * Endpoint Enable inactive
103314  */
103315 #define ALT_USB_DEV_DIEPCTL15_EPENA_E_INACT 0x0
103316 /*
103317  * Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPENA
103318  *
103319  * Endpoint Enable active
103320  */
103321 #define ALT_USB_DEV_DIEPCTL15_EPENA_E_ACT 0x1
103322 
103323 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */
103324 #define ALT_USB_DEV_DIEPCTL15_EPENA_LSB 31
103325 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */
103326 #define ALT_USB_DEV_DIEPCTL15_EPENA_MSB 31
103327 /* The width in bits of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */
103328 #define ALT_USB_DEV_DIEPCTL15_EPENA_WIDTH 1
103329 /* The mask used to set the ALT_USB_DEV_DIEPCTL15_EPENA register field value. */
103330 #define ALT_USB_DEV_DIEPCTL15_EPENA_SET_MSK 0x80000000
103331 /* The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPENA register field value. */
103332 #define ALT_USB_DEV_DIEPCTL15_EPENA_CLR_MSK 0x7fffffff
103333 /* The reset value of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */
103334 #define ALT_USB_DEV_DIEPCTL15_EPENA_RESET 0x0
103335 /* Extracts the ALT_USB_DEV_DIEPCTL15_EPENA field value from a register. */
103336 #define ALT_USB_DEV_DIEPCTL15_EPENA_GET(value) (((value) & 0x80000000) >> 31)
103337 /* Produces a ALT_USB_DEV_DIEPCTL15_EPENA register field value suitable for setting the register. */
103338 #define ALT_USB_DEV_DIEPCTL15_EPENA_SET(value) (((value) << 31) & 0x80000000)
103339 
103340 #ifndef __ASSEMBLY__
103341 /*
103342  * WARNING: The C register and register group struct declarations are provided for
103343  * convenience and illustrative purposes. They should, however, be used with
103344  * caution as the C language standard provides no guarantees about the alignment or
103345  * atomicity of device memory accesses. The recommended practice for writing
103346  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
103347  * alt_write_word() functions.
103348  *
103349  * The struct declaration for register ALT_USB_DEV_DIEPCTL15.
103350  */
103351 struct ALT_USB_DEV_DIEPCTL15_s
103352 {
103353  uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL15_MPS */
103354  uint32_t : 4; /* *UNDEFINED* */
103355  uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL15_USBACTEP */
103356  const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL15_DPID */
103357  const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL15_NAKSTS */
103358  uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL15_EPTYPE */
103359  uint32_t : 1; /* *UNDEFINED* */
103360  uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL15_STALL */
103361  uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL15_TXFNUM */
103362  uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL15_CNAK */
103363  uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL15_SNAK */
103364  uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL15_SETD0PID */
103365  uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL15_SETD1PID */
103366  uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL15_EPDIS */
103367  uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL15_EPENA */
103368 };
103369 
103370 /* The typedef declaration for register ALT_USB_DEV_DIEPCTL15. */
103371 typedef volatile struct ALT_USB_DEV_DIEPCTL15_s ALT_USB_DEV_DIEPCTL15_t;
103372 #endif /* __ASSEMBLY__ */
103373 
103374 /* The reset value of the ALT_USB_DEV_DIEPCTL15 register. */
103375 #define ALT_USB_DEV_DIEPCTL15_RESET 0x00000000
103376 /* The byte offset of the ALT_USB_DEV_DIEPCTL15 register from the beginning of the component. */
103377 #define ALT_USB_DEV_DIEPCTL15_OFST 0x2e0
103378 /* The address of the ALT_USB_DEV_DIEPCTL15 register. */
103379 #define ALT_USB_DEV_DIEPCTL15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL15_OFST))
103380 
103381 /*
103382  * Register : diepint15
103383  *
103384  * Device IN Endpoint 15 Interrupt Register
103385  *
103386  * Register Layout
103387  *
103388  * Bits | Access | Reset | Description
103389  * :--------|:-------|:------|:----------------------------------
103390  * [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_XFERCOMPL
103391  * [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_EPDISBLD
103392  * [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_AHBERR
103393  * [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_TMO
103394  * [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_INTKNTXFEMP
103395  * [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_INTKNEPMIS
103396  * [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_INEPNAKEFF
103397  * [7] | R | 0x1 | ALT_USB_DEV_DIEPINT15_TXFEMP
103398  * [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN
103399  * [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_BNAINTR
103400  * [10] | ??? | 0x0 | *UNDEFINED*
103401  * [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_PKTDRPSTS
103402  * [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_BBLEERR
103403  * [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_NAKINTRPT
103404  * [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_NYETINTRPT
103405  * [31:15] | ??? | 0x0 | *UNDEFINED*
103406  *
103407  */
103408 /*
103409  * Field : xfercompl
103410  *
103411  * Transfer Completed Interrupt (XferCompl)
103412  *
103413  * Applies to IN and OUT endpoints.
103414  *
103415  * When Scatter/Gather DMA mode is enabled
103416  *
103417  * * For IN endpoint this field indicates that the requested data
103418  *
103419  * from the descriptor is moved from external system memory
103420  *
103421  * to internal FIFO.
103422  *
103423  * * For OUT endpoint this field indicates that the requested
103424  *
103425  * data from the internal FIFO is moved to external system
103426  *
103427  * memory. This interrupt is generated only when the
103428  *
103429  * corresponding endpoint descriptor is closed, and the IOC
103430  *
103431  * bit For the corresponding descriptor is Set.
103432  *
103433  * When Scatter/Gather DMA mode is disabled, this field
103434  *
103435  * indicates that the programmed transfer is complete on the
103436  *
103437  * AHB as well as on the USB, For this endpoint.
103438  *
103439  * Field Enumeration Values:
103440  *
103441  * Enum | Value | Description
103442  * :----------------------------------------|:------|:-----------------------------
103443  * ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_INACT | 0x0 | No Interrupt
103444  * ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
103445  *
103446  * Field Access Macros:
103447  *
103448  */
103449 /*
103450  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_XFERCOMPL
103451  *
103452  * No Interrupt
103453  */
103454 #define ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_INACT 0x0
103455 /*
103456  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_XFERCOMPL
103457  *
103458  * Transfer Completed Interrupt
103459  */
103460 #define ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_ACT 0x1
103461 
103462 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */
103463 #define ALT_USB_DEV_DIEPINT15_XFERCOMPL_LSB 0
103464 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */
103465 #define ALT_USB_DEV_DIEPINT15_XFERCOMPL_MSB 0
103466 /* The width in bits of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */
103467 #define ALT_USB_DEV_DIEPINT15_XFERCOMPL_WIDTH 1
103468 /* The mask used to set the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field value. */
103469 #define ALT_USB_DEV_DIEPINT15_XFERCOMPL_SET_MSK 0x00000001
103470 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field value. */
103471 #define ALT_USB_DEV_DIEPINT15_XFERCOMPL_CLR_MSK 0xfffffffe
103472 /* The reset value of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */
103473 #define ALT_USB_DEV_DIEPINT15_XFERCOMPL_RESET 0x0
103474 /* Extracts the ALT_USB_DEV_DIEPINT15_XFERCOMPL field value from a register. */
103475 #define ALT_USB_DEV_DIEPINT15_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
103476 /* Produces a ALT_USB_DEV_DIEPINT15_XFERCOMPL register field value suitable for setting the register. */
103477 #define ALT_USB_DEV_DIEPINT15_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
103478 
103479 /*
103480  * Field : epdisbld
103481  *
103482  * Endpoint Disabled Interrupt (EPDisbld)
103483  *
103484  * Applies to IN and OUT endpoints.
103485  *
103486  * This bit indicates that the endpoint is disabled per the
103487  *
103488  * application's request.
103489  *
103490  * Field Enumeration Values:
103491  *
103492  * Enum | Value | Description
103493  * :---------------------------------------|:------|:----------------------------
103494  * ALT_USB_DEV_DIEPINT15_EPDISBLD_E_INACT | 0x0 | No Interrupt
103495  * ALT_USB_DEV_DIEPINT15_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
103496  *
103497  * Field Access Macros:
103498  *
103499  */
103500 /*
103501  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_EPDISBLD
103502  *
103503  * No Interrupt
103504  */
103505 #define ALT_USB_DEV_DIEPINT15_EPDISBLD_E_INACT 0x0
103506 /*
103507  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_EPDISBLD
103508  *
103509  * Endpoint Disabled Interrupt
103510  */
103511 #define ALT_USB_DEV_DIEPINT15_EPDISBLD_E_ACT 0x1
103512 
103513 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */
103514 #define ALT_USB_DEV_DIEPINT15_EPDISBLD_LSB 1
103515 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */
103516 #define ALT_USB_DEV_DIEPINT15_EPDISBLD_MSB 1
103517 /* The width in bits of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */
103518 #define ALT_USB_DEV_DIEPINT15_EPDISBLD_WIDTH 1
103519 /* The mask used to set the ALT_USB_DEV_DIEPINT15_EPDISBLD register field value. */
103520 #define ALT_USB_DEV_DIEPINT15_EPDISBLD_SET_MSK 0x00000002
103521 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_EPDISBLD register field value. */
103522 #define ALT_USB_DEV_DIEPINT15_EPDISBLD_CLR_MSK 0xfffffffd
103523 /* The reset value of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */
103524 #define ALT_USB_DEV_DIEPINT15_EPDISBLD_RESET 0x0
103525 /* Extracts the ALT_USB_DEV_DIEPINT15_EPDISBLD field value from a register. */
103526 #define ALT_USB_DEV_DIEPINT15_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
103527 /* Produces a ALT_USB_DEV_DIEPINT15_EPDISBLD register field value suitable for setting the register. */
103528 #define ALT_USB_DEV_DIEPINT15_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
103529 
103530 /*
103531  * Field : ahberr
103532  *
103533  * AHB Error (AHBErr)
103534  *
103535  * Applies to IN and OUT endpoints.
103536  *
103537  * This is generated only in Internal DMA mode when there is an
103538  *
103539  * AHB error during an AHB read/write. The application can read
103540  *
103541  * the corresponding endpoint DMA address register to get the
103542  *
103543  * error address.
103544  *
103545  * Field Enumeration Values:
103546  *
103547  * Enum | Value | Description
103548  * :-------------------------------------|:------|:--------------------
103549  * ALT_USB_DEV_DIEPINT15_AHBERR_E_INACT | 0x0 | No Interrupt
103550  * ALT_USB_DEV_DIEPINT15_AHBERR_E_ACT | 0x1 | AHB Error interrupt
103551  *
103552  * Field Access Macros:
103553  *
103554  */
103555 /*
103556  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_AHBERR
103557  *
103558  * No Interrupt
103559  */
103560 #define ALT_USB_DEV_DIEPINT15_AHBERR_E_INACT 0x0
103561 /*
103562  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_AHBERR
103563  *
103564  * AHB Error interrupt
103565  */
103566 #define ALT_USB_DEV_DIEPINT15_AHBERR_E_ACT 0x1
103567 
103568 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */
103569 #define ALT_USB_DEV_DIEPINT15_AHBERR_LSB 2
103570 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */
103571 #define ALT_USB_DEV_DIEPINT15_AHBERR_MSB 2
103572 /* The width in bits of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */
103573 #define ALT_USB_DEV_DIEPINT15_AHBERR_WIDTH 1
103574 /* The mask used to set the ALT_USB_DEV_DIEPINT15_AHBERR register field value. */
103575 #define ALT_USB_DEV_DIEPINT15_AHBERR_SET_MSK 0x00000004
103576 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_AHBERR register field value. */
103577 #define ALT_USB_DEV_DIEPINT15_AHBERR_CLR_MSK 0xfffffffb
103578 /* The reset value of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */
103579 #define ALT_USB_DEV_DIEPINT15_AHBERR_RESET 0x0
103580 /* Extracts the ALT_USB_DEV_DIEPINT15_AHBERR field value from a register. */
103581 #define ALT_USB_DEV_DIEPINT15_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
103582 /* Produces a ALT_USB_DEV_DIEPINT15_AHBERR register field value suitable for setting the register. */
103583 #define ALT_USB_DEV_DIEPINT15_AHBERR_SET(value) (((value) << 2) & 0x00000004)
103584 
103585 /*
103586  * Field : timeout
103587  *
103588  * Timeout Condition (TimeOUT)
103589  *
103590  * In shared TX FIFO mode, applies to non-isochronous IN
103591  *
103592  * endpoints only.
103593  *
103594  * In dedicated FIFO mode, applies only to Control IN
103595  *
103596  * endpoints.
103597  *
103598  * In Scatter/Gather DMA mode, the TimeOUT interrupt is not
103599  *
103600  * asserted.
103601  *
103602  * Indicates that the core has detected a timeout condition on the
103603  *
103604  * USB For the last IN token on this endpoint.
103605  *
103606  * Field Enumeration Values:
103607  *
103608  * Enum | Value | Description
103609  * :----------------------------------|:------|:------------------
103610  * ALT_USB_DEV_DIEPINT15_TMO_E_INACT | 0x0 | No interrupt
103611  * ALT_USB_DEV_DIEPINT15_TMO_E_ACT | 0x1 | Timeout interrupy
103612  *
103613  * Field Access Macros:
103614  *
103615  */
103616 /*
103617  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TMO
103618  *
103619  * No interrupt
103620  */
103621 #define ALT_USB_DEV_DIEPINT15_TMO_E_INACT 0x0
103622 /*
103623  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TMO
103624  *
103625  * Timeout interrupy
103626  */
103627 #define ALT_USB_DEV_DIEPINT15_TMO_E_ACT 0x1
103628 
103629 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_TMO register field. */
103630 #define ALT_USB_DEV_DIEPINT15_TMO_LSB 3
103631 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_TMO register field. */
103632 #define ALT_USB_DEV_DIEPINT15_TMO_MSB 3
103633 /* The width in bits of the ALT_USB_DEV_DIEPINT15_TMO register field. */
103634 #define ALT_USB_DEV_DIEPINT15_TMO_WIDTH 1
103635 /* The mask used to set the ALT_USB_DEV_DIEPINT15_TMO register field value. */
103636 #define ALT_USB_DEV_DIEPINT15_TMO_SET_MSK 0x00000008
103637 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_TMO register field value. */
103638 #define ALT_USB_DEV_DIEPINT15_TMO_CLR_MSK 0xfffffff7
103639 /* The reset value of the ALT_USB_DEV_DIEPINT15_TMO register field. */
103640 #define ALT_USB_DEV_DIEPINT15_TMO_RESET 0x0
103641 /* Extracts the ALT_USB_DEV_DIEPINT15_TMO field value from a register. */
103642 #define ALT_USB_DEV_DIEPINT15_TMO_GET(value) (((value) & 0x00000008) >> 3)
103643 /* Produces a ALT_USB_DEV_DIEPINT15_TMO register field value suitable for setting the register. */
103644 #define ALT_USB_DEV_DIEPINT15_TMO_SET(value) (((value) << 3) & 0x00000008)
103645 
103646 /*
103647  * Field : intkntxfemp
103648  *
103649  * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
103650  *
103651  * Applies to non-periodic IN endpoints only.
103652  *
103653  * Indicates that an IN token was received when the associated
103654  *
103655  * TxFIFO (periodic/non-periodic) was empty. This interrupt is
103656  *
103657  * asserted on the endpoint For which the IN token was received.
103658  *
103659  * Field Enumeration Values:
103660  *
103661  * Enum | Value | Description
103662  * :------------------------------------------|:------|:----------------------------
103663  * ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
103664  * ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
103665  *
103666  * Field Access Macros:
103667  *
103668  */
103669 /*
103670  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNTXFEMP
103671  *
103672  * No interrupt
103673  */
103674 #define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_INACT 0x0
103675 /*
103676  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNTXFEMP
103677  *
103678  * IN Token Received Interrupt
103679  */
103680 #define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_ACT 0x1
103681 
103682 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */
103683 #define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_LSB 4
103684 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */
103685 #define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_MSB 4
103686 /* The width in bits of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */
103687 #define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_WIDTH 1
103688 /* The mask used to set the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field value. */
103689 #define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_SET_MSK 0x00000010
103690 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field value. */
103691 #define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_CLR_MSK 0xffffffef
103692 /* The reset value of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */
103693 #define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_RESET 0x0
103694 /* Extracts the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP field value from a register. */
103695 #define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
103696 /* Produces a ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field value suitable for setting the register. */
103697 #define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
103698 
103699 /*
103700  * Field : intknepmis
103701  *
103702  * IN Token Received with EP Mismatch (INTknEPMis)
103703  *
103704  * Applies to non-periodic IN endpoints only.
103705  *
103706  * Indicates that the data in the top of the non-periodic TxFIFO
103707  *
103708  * belongs to an endpoint other than the one For which the IN token
103709  *
103710  * was received. This interrupt is asserted on the endpoint For
103711  *
103712  * which the IN token was received.
103713  *
103714  * Field Enumeration Values:
103715  *
103716  * Enum | Value | Description
103717  * :-----------------------------------------|:------|:---------------------------------------------
103718  * ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_INACT | 0x0 | No interrupt
103719  * ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
103720  *
103721  * Field Access Macros:
103722  *
103723  */
103724 /*
103725  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNEPMIS
103726  *
103727  * No interrupt
103728  */
103729 #define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_INACT 0x0
103730 /*
103731  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNEPMIS
103732  *
103733  * IN Token Received with EP Mismatch interrupt
103734  */
103735 #define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_ACT 0x1
103736 
103737 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */
103738 #define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_LSB 5
103739 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */
103740 #define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_MSB 5
103741 /* The width in bits of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */
103742 #define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_WIDTH 1
103743 /* The mask used to set the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field value. */
103744 #define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_SET_MSK 0x00000020
103745 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field value. */
103746 #define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_CLR_MSK 0xffffffdf
103747 /* The reset value of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */
103748 #define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_RESET 0x0
103749 /* Extracts the ALT_USB_DEV_DIEPINT15_INTKNEPMIS field value from a register. */
103750 #define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
103751 /* Produces a ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field value suitable for setting the register. */
103752 #define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
103753 
103754 /*
103755  * Field : inepnakeff
103756  *
103757  * IN Endpoint NAK Effective (INEPNakEff)
103758  *
103759  * Applies to periodic IN endpoints only.
103760  *
103761  * This bit can be cleared when the application clears the IN
103762  *
103763  * endpoint NAK by writing to DIEPCTLn.CNAK.
103764  *
103765  * This interrupt indicates that the core has sampled the NAK bit
103766  *
103767  * Set (either by the application or by the core). The interrupt
103768  *
103769  * indicates that the IN endpoint NAK bit Set by the application has
103770  *
103771  * taken effect in the core.
103772  *
103773  * This interrupt does not guarantee that a NAK handshake is sent
103774  *
103775  * on the USB. A STALL bit takes priority over a NAK bit.
103776  *
103777  * Field Enumeration Values:
103778  *
103779  * Enum | Value | Description
103780  * :-----------------------------------------|:------|:------------------------------------
103781  * ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_INACT | 0x0 | No interrupt
103782  * ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
103783  *
103784  * Field Access Macros:
103785  *
103786  */
103787 /*
103788  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INEPNAKEFF
103789  *
103790  * No interrupt
103791  */
103792 #define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_INACT 0x0
103793 /*
103794  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_INEPNAKEFF
103795  *
103796  * IN Endpoint NAK Effective interrupt
103797  */
103798 #define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_ACT 0x1
103799 
103800 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */
103801 #define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_LSB 6
103802 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */
103803 #define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_MSB 6
103804 /* The width in bits of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */
103805 #define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_WIDTH 1
103806 /* The mask used to set the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field value. */
103807 #define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_SET_MSK 0x00000040
103808 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field value. */
103809 #define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_CLR_MSK 0xffffffbf
103810 /* The reset value of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */
103811 #define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_RESET 0x0
103812 /* Extracts the ALT_USB_DEV_DIEPINT15_INEPNAKEFF field value from a register. */
103813 #define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
103814 /* Produces a ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field value suitable for setting the register. */
103815 #define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
103816 
103817 /*
103818  * Field : txfemp
103819  *
103820  * Transmit FIFO Empty (TxFEmp)
103821  *
103822  * This bit is valid only For IN Endpoints
103823  *
103824  * This interrupt is asserted when the TxFIFO For this endpoint is
103825  *
103826  * either half or completely empty. The half or completely empty
103827  *
103828  * status is determined by the TxFIFO Empty Level bit in the Core
103829  *
103830  * AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
103831  *
103832  * Field Enumeration Values:
103833  *
103834  * Enum | Value | Description
103835  * :-------------------------------------|:------|:------------------------------
103836  * ALT_USB_DEV_DIEPINT15_TXFEMP_E_INACT | 0x0 | No interrupt
103837  * ALT_USB_DEV_DIEPINT15_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
103838  *
103839  * Field Access Macros:
103840  *
103841  */
103842 /*
103843  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFEMP
103844  *
103845  * No interrupt
103846  */
103847 #define ALT_USB_DEV_DIEPINT15_TXFEMP_E_INACT 0x0
103848 /*
103849  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFEMP
103850  *
103851  * Transmit FIFO Empty interrupt
103852  */
103853 #define ALT_USB_DEV_DIEPINT15_TXFEMP_E_ACT 0x1
103854 
103855 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */
103856 #define ALT_USB_DEV_DIEPINT15_TXFEMP_LSB 7
103857 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */
103858 #define ALT_USB_DEV_DIEPINT15_TXFEMP_MSB 7
103859 /* The width in bits of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */
103860 #define ALT_USB_DEV_DIEPINT15_TXFEMP_WIDTH 1
103861 /* The mask used to set the ALT_USB_DEV_DIEPINT15_TXFEMP register field value. */
103862 #define ALT_USB_DEV_DIEPINT15_TXFEMP_SET_MSK 0x00000080
103863 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_TXFEMP register field value. */
103864 #define ALT_USB_DEV_DIEPINT15_TXFEMP_CLR_MSK 0xffffff7f
103865 /* The reset value of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */
103866 #define ALT_USB_DEV_DIEPINT15_TXFEMP_RESET 0x1
103867 /* Extracts the ALT_USB_DEV_DIEPINT15_TXFEMP field value from a register. */
103868 #define ALT_USB_DEV_DIEPINT15_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
103869 /* Produces a ALT_USB_DEV_DIEPINT15_TXFEMP register field value suitable for setting the register. */
103870 #define ALT_USB_DEV_DIEPINT15_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
103871 
103872 /*
103873  * Field : txfifoundrn
103874  *
103875  * Fifo Underrun (TxfifoUndrn)
103876  *
103877  * Applies to IN endpoints Only
103878  *
103879  * This bit is valid only If thresholding is enabled. The core generates this
103880  * interrupt when
103881  *
103882  * it detects a transmit FIFO underrun condition For this endpoint.
103883  *
103884  * Field Enumeration Values:
103885  *
103886  * Enum | Value | Description
103887  * :------------------------------------------|:------|:------------------------
103888  * ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
103889  * ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
103890  *
103891  * Field Access Macros:
103892  *
103893  */
103894 /*
103895  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN
103896  *
103897  * No interrupt
103898  */
103899 #define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_INACT 0x0
103900 /*
103901  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN
103902  *
103903  * Fifo Underrun interrupt
103904  */
103905 #define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_ACT 0x1
103906 
103907 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */
103908 #define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_LSB 8
103909 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */
103910 #define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_MSB 8
103911 /* The width in bits of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */
103912 #define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_WIDTH 1
103913 /* The mask used to set the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field value. */
103914 #define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_SET_MSK 0x00000100
103915 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field value. */
103916 #define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_CLR_MSK 0xfffffeff
103917 /* The reset value of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */
103918 #define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_RESET 0x0
103919 /* Extracts the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN field value from a register. */
103920 #define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
103921 /* Produces a ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field value suitable for setting the register. */
103922 #define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
103923 
103924 /*
103925  * Field : bnaintr
103926  *
103927  * BNA (Buffer Not Available) Interrupt (BNAIntr)
103928  *
103929  * This bit is valid only when Scatter/Gather DMA mode is enabled.
103930  *
103931  * The core generates this interrupt when the descriptor accessed
103932  *
103933  * is not ready For the Core to process, such as Host busy or DMA
103934  *
103935  * done
103936  *
103937  * Field Enumeration Values:
103938  *
103939  * Enum | Value | Description
103940  * :--------------------------------------|:------|:--------------
103941  * ALT_USB_DEV_DIEPINT15_BNAINTR_E_INACT | 0x0 | No interrupt
103942  * ALT_USB_DEV_DIEPINT15_BNAINTR_E_ACT | 0x1 | BNA interrupt
103943  *
103944  * Field Access Macros:
103945  *
103946  */
103947 /*
103948  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_BNAINTR
103949  *
103950  * No interrupt
103951  */
103952 #define ALT_USB_DEV_DIEPINT15_BNAINTR_E_INACT 0x0
103953 /*
103954  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_BNAINTR
103955  *
103956  * BNA interrupt
103957  */
103958 #define ALT_USB_DEV_DIEPINT15_BNAINTR_E_ACT 0x1
103959 
103960 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */
103961 #define ALT_USB_DEV_DIEPINT15_BNAINTR_LSB 9
103962 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */
103963 #define ALT_USB_DEV_DIEPINT15_BNAINTR_MSB 9
103964 /* The width in bits of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */
103965 #define ALT_USB_DEV_DIEPINT15_BNAINTR_WIDTH 1
103966 /* The mask used to set the ALT_USB_DEV_DIEPINT15_BNAINTR register field value. */
103967 #define ALT_USB_DEV_DIEPINT15_BNAINTR_SET_MSK 0x00000200
103968 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_BNAINTR register field value. */
103969 #define ALT_USB_DEV_DIEPINT15_BNAINTR_CLR_MSK 0xfffffdff
103970 /* The reset value of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */
103971 #define ALT_USB_DEV_DIEPINT15_BNAINTR_RESET 0x0
103972 /* Extracts the ALT_USB_DEV_DIEPINT15_BNAINTR field value from a register. */
103973 #define ALT_USB_DEV_DIEPINT15_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
103974 /* Produces a ALT_USB_DEV_DIEPINT15_BNAINTR register field value suitable for setting the register. */
103975 #define ALT_USB_DEV_DIEPINT15_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
103976 
103977 /*
103978  * Field : pktdrpsts
103979  *
103980  * Packet Drop Status (PktDrpSts)
103981  *
103982  * This bit indicates to the application that an ISOC OUT packet has been dropped.
103983  * This
103984  *
103985  * bit does not have an associated mask bit and does not generate an interrupt.
103986  *
103987  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
103988  * transfer
103989  *
103990  * interrupt feature is selected.
103991  *
103992  * Field Enumeration Values:
103993  *
103994  * Enum | Value | Description
103995  * :----------------------------------------|:------|:-----------------------------
103996  * ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_INACT | 0x0 | No interrupt
103997  * ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
103998  *
103999  * Field Access Macros:
104000  *
104001  */
104002 /*
104003  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_PKTDRPSTS
104004  *
104005  * No interrupt
104006  */
104007 #define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_INACT 0x0
104008 /*
104009  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_PKTDRPSTS
104010  *
104011  * Packet Drop Status interrupt
104012  */
104013 #define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_ACT 0x1
104014 
104015 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */
104016 #define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_LSB 11
104017 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */
104018 #define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_MSB 11
104019 /* The width in bits of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */
104020 #define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_WIDTH 1
104021 /* The mask used to set the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field value. */
104022 #define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_SET_MSK 0x00000800
104023 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field value. */
104024 #define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_CLR_MSK 0xfffff7ff
104025 /* The reset value of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */
104026 #define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_RESET 0x0
104027 /* Extracts the ALT_USB_DEV_DIEPINT15_PKTDRPSTS field value from a register. */
104028 #define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
104029 /* Produces a ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field value suitable for setting the register. */
104030 #define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
104031 
104032 /*
104033  * Field : bbleerr
104034  *
104035  * NAK Interrupt (BbleErr)
104036  *
104037  * The core generates this interrupt when babble is received for the endpoint.
104038  *
104039  * Field Enumeration Values:
104040  *
104041  * Enum | Value | Description
104042  * :--------------------------------------|:------|:------------------
104043  * ALT_USB_DEV_DIEPINT15_BBLEERR_E_INACT | 0x0 | No interrupt
104044  * ALT_USB_DEV_DIEPINT15_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
104045  *
104046  * Field Access Macros:
104047  *
104048  */
104049 /*
104050  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_BBLEERR
104051  *
104052  * No interrupt
104053  */
104054 #define ALT_USB_DEV_DIEPINT15_BBLEERR_E_INACT 0x0
104055 /*
104056  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_BBLEERR
104057  *
104058  * BbleErr interrupt
104059  */
104060 #define ALT_USB_DEV_DIEPINT15_BBLEERR_E_ACT 0x1
104061 
104062 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */
104063 #define ALT_USB_DEV_DIEPINT15_BBLEERR_LSB 12
104064 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */
104065 #define ALT_USB_DEV_DIEPINT15_BBLEERR_MSB 12
104066 /* The width in bits of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */
104067 #define ALT_USB_DEV_DIEPINT15_BBLEERR_WIDTH 1
104068 /* The mask used to set the ALT_USB_DEV_DIEPINT15_BBLEERR register field value. */
104069 #define ALT_USB_DEV_DIEPINT15_BBLEERR_SET_MSK 0x00001000
104070 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_BBLEERR register field value. */
104071 #define ALT_USB_DEV_DIEPINT15_BBLEERR_CLR_MSK 0xffffefff
104072 /* The reset value of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */
104073 #define ALT_USB_DEV_DIEPINT15_BBLEERR_RESET 0x0
104074 /* Extracts the ALT_USB_DEV_DIEPINT15_BBLEERR field value from a register. */
104075 #define ALT_USB_DEV_DIEPINT15_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
104076 /* Produces a ALT_USB_DEV_DIEPINT15_BBLEERR register field value suitable for setting the register. */
104077 #define ALT_USB_DEV_DIEPINT15_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
104078 
104079 /*
104080  * Field : nakintrpt
104081  *
104082  * NAK Interrupt (NAKInterrupt)
104083  *
104084  * The core generates this interrupt when a NAK is transmitted or received by the
104085  * device.
104086  *
104087  * In case of isochronous IN endpoints the interrupt gets generated when a zero
104088  * length
104089  *
104090  * packet is transmitted due to un-availability of data in the TXFifo.
104091  *
104092  * Field Enumeration Values:
104093  *
104094  * Enum | Value | Description
104095  * :----------------------------------------|:------|:--------------
104096  * ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_INACT | 0x0 | No interrupt
104097  * ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
104098  *
104099  * Field Access Macros:
104100  *
104101  */
104102 /*
104103  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_NAKINTRPT
104104  *
104105  * No interrupt
104106  */
104107 #define ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_INACT 0x0
104108 /*
104109  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_NAKINTRPT
104110  *
104111  * NAK Interrupt
104112  */
104113 #define ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_ACT 0x1
104114 
104115 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */
104116 #define ALT_USB_DEV_DIEPINT15_NAKINTRPT_LSB 13
104117 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */
104118 #define ALT_USB_DEV_DIEPINT15_NAKINTRPT_MSB 13
104119 /* The width in bits of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */
104120 #define ALT_USB_DEV_DIEPINT15_NAKINTRPT_WIDTH 1
104121 /* The mask used to set the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field value. */
104122 #define ALT_USB_DEV_DIEPINT15_NAKINTRPT_SET_MSK 0x00002000
104123 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field value. */
104124 #define ALT_USB_DEV_DIEPINT15_NAKINTRPT_CLR_MSK 0xffffdfff
104125 /* The reset value of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */
104126 #define ALT_USB_DEV_DIEPINT15_NAKINTRPT_RESET 0x0
104127 /* Extracts the ALT_USB_DEV_DIEPINT15_NAKINTRPT field value from a register. */
104128 #define ALT_USB_DEV_DIEPINT15_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
104129 /* Produces a ALT_USB_DEV_DIEPINT15_NAKINTRPT register field value suitable for setting the register. */
104130 #define ALT_USB_DEV_DIEPINT15_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
104131 
104132 /*
104133  * Field : nyetintrpt
104134  *
104135  * NYET Interrupt (NYETIntrpt)
104136  *
104137  * The core generates this interrupt when a NYET response is transmitted for a non
104138  * isochronous OUT endpoint.
104139  *
104140  * Field Enumeration Values:
104141  *
104142  * Enum | Value | Description
104143  * :-----------------------------------------|:------|:---------------
104144  * ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_INACT | 0x0 | No interrupt
104145  * ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
104146  *
104147  * Field Access Macros:
104148  *
104149  */
104150 /*
104151  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_NYETINTRPT
104152  *
104153  * No interrupt
104154  */
104155 #define ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_INACT 0x0
104156 /*
104157  * Enumerated value for register field ALT_USB_DEV_DIEPINT15_NYETINTRPT
104158  *
104159  * NYET Interrupt
104160  */
104161 #define ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_ACT 0x1
104162 
104163 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */
104164 #define ALT_USB_DEV_DIEPINT15_NYETINTRPT_LSB 14
104165 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */
104166 #define ALT_USB_DEV_DIEPINT15_NYETINTRPT_MSB 14
104167 /* The width in bits of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */
104168 #define ALT_USB_DEV_DIEPINT15_NYETINTRPT_WIDTH 1
104169 /* The mask used to set the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field value. */
104170 #define ALT_USB_DEV_DIEPINT15_NYETINTRPT_SET_MSK 0x00004000
104171 /* The mask used to clear the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field value. */
104172 #define ALT_USB_DEV_DIEPINT15_NYETINTRPT_CLR_MSK 0xffffbfff
104173 /* The reset value of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */
104174 #define ALT_USB_DEV_DIEPINT15_NYETINTRPT_RESET 0x0
104175 /* Extracts the ALT_USB_DEV_DIEPINT15_NYETINTRPT field value from a register. */
104176 #define ALT_USB_DEV_DIEPINT15_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
104177 /* Produces a ALT_USB_DEV_DIEPINT15_NYETINTRPT register field value suitable for setting the register. */
104178 #define ALT_USB_DEV_DIEPINT15_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
104179 
104180 #ifndef __ASSEMBLY__
104181 /*
104182  * WARNING: The C register and register group struct declarations are provided for
104183  * convenience and illustrative purposes. They should, however, be used with
104184  * caution as the C language standard provides no guarantees about the alignment or
104185  * atomicity of device memory accesses. The recommended practice for writing
104186  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
104187  * alt_write_word() functions.
104188  *
104189  * The struct declaration for register ALT_USB_DEV_DIEPINT15.
104190  */
104191 struct ALT_USB_DEV_DIEPINT15_s
104192 {
104193  uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT15_XFERCOMPL */
104194  uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT15_EPDISBLD */
104195  uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT15_AHBERR */
104196  uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT15_TMO */
104197  uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT15_INTKNTXFEMP */
104198  uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT15_INTKNEPMIS */
104199  uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT15_INEPNAKEFF */
104200  const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT15_TXFEMP */
104201  uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN */
104202  uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT15_BNAINTR */
104203  uint32_t : 1; /* *UNDEFINED* */
104204  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT15_PKTDRPSTS */
104205  uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT15_BBLEERR */
104206  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT15_NAKINTRPT */
104207  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT15_NYETINTRPT */
104208  uint32_t : 17; /* *UNDEFINED* */
104209 };
104210 
104211 /* The typedef declaration for register ALT_USB_DEV_DIEPINT15. */
104212 typedef volatile struct ALT_USB_DEV_DIEPINT15_s ALT_USB_DEV_DIEPINT15_t;
104213 #endif /* __ASSEMBLY__ */
104214 
104215 /* The reset value of the ALT_USB_DEV_DIEPINT15 register. */
104216 #define ALT_USB_DEV_DIEPINT15_RESET 0x00000080
104217 /* The byte offset of the ALT_USB_DEV_DIEPINT15 register from the beginning of the component. */
104218 #define ALT_USB_DEV_DIEPINT15_OFST 0x2e8
104219 /* The address of the ALT_USB_DEV_DIEPINT15 register. */
104220 #define ALT_USB_DEV_DIEPINT15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT15_OFST))
104221 
104222 /*
104223  * Register : dieptsiz15
104224  *
104225  * Device IN Endpoint 15 Transfer Size Register
104226  *
104227  * Register Layout
104228  *
104229  * Bits | Access | Reset | Description
104230  * :--------|:-------|:------|:--------------------------------
104231  * [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ15_XFERSIZE
104232  * [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ15_PKTCNT
104233  * [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ15_MC
104234  * [31] | ??? | 0x0 | *UNDEFINED*
104235  *
104236  */
104237 /*
104238  * Field : xfersize
104239  *
104240  * Transfer Size (XferSize)
104241  *
104242  * Indicates the transfer size in bytes For endpoint 0. The core
104243  *
104244  * interrupts the application only after it has exhausted the transfer
104245  *
104246  * size amount of data. The transfer size can be Set to the
104247  *
104248  * maximum packet size of the endpoint, to be interrupted at the
104249  *
104250  * end of each packet.
104251  *
104252  * The core decrements this field every time a packet from the
104253  *
104254  * external memory is written to the TxFIFO.
104255  *
104256  * Field Access Macros:
104257  *
104258  */
104259 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */
104260 #define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_LSB 0
104261 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */
104262 #define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_MSB 18
104263 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */
104264 #define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_WIDTH 19
104265 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field value. */
104266 #define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_SET_MSK 0x0007ffff
104267 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field value. */
104268 #define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_CLR_MSK 0xfff80000
104269 /* The reset value of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */
104270 #define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_RESET 0x0
104271 /* Extracts the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE field value from a register. */
104272 #define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
104273 /* Produces a ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field value suitable for setting the register. */
104274 #define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
104275 
104276 /*
104277  * Field : pktcnt
104278  *
104279  * Packet Count (PktCnt)
104280  *
104281  * Indicates the total number of USB packets that constitute the
104282  *
104283  * Transfer Size amount of data For endpoint 0.
104284  *
104285  * This field is decremented every time a packet (maximum size or
104286  *
104287  * short packet) is read from the TxFIFO.
104288  *
104289  * Field Access Macros:
104290  *
104291  */
104292 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */
104293 #define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_LSB 19
104294 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */
104295 #define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_MSB 28
104296 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */
104297 #define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_WIDTH 10
104298 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field value. */
104299 #define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_SET_MSK 0x1ff80000
104300 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field value. */
104301 #define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_CLR_MSK 0xe007ffff
104302 /* The reset value of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */
104303 #define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_RESET 0x0
104304 /* Extracts the ALT_USB_DEV_DIEPTSIZ15_PKTCNT field value from a register. */
104305 #define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
104306 /* Produces a ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field value suitable for setting the register. */
104307 #define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
104308 
104309 /*
104310  * Field : mc
104311  *
104312  * Applies to IN endpoints only.
104313  *
104314  * For periodic IN endpoints, this field indicates the number of packets that must
104315  * be transmitted per microframe on the USB. The core uses this field to calculate
104316  * the data PID for isochronous IN endpoints.
104317  *
104318  * 2'b01: 1 packet
104319  *
104320  * 2'b10: 2 packets
104321  *
104322  * 2'b11: 3 packets
104323  *
104324  * For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
104325  * specifies the number of packets the core must fetchfor an IN endpoint before it
104326  * switches to the endpoint pointed to by the Next Endpoint field of the Device
104327  * Endpoint-n Control register (DIEPCTLn.NextEp)
104328  *
104329  * Field Enumeration Values:
104330  *
104331  * Enum | Value | Description
104332  * :-------------------------------------|:------|:------------
104333  * ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTONE | 0x1 | 1 packet
104334  * ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTWO | 0x2 | 2 packets
104335  * ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTHREE | 0x3 | 3 packets
104336  *
104337  * Field Access Macros:
104338  *
104339  */
104340 /*
104341  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ15_MC
104342  *
104343  * 1 packet
104344  */
104345 #define ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTONE 0x1
104346 /*
104347  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ15_MC
104348  *
104349  * 2 packets
104350  */
104351 #define ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTWO 0x2
104352 /*
104353  * Enumerated value for register field ALT_USB_DEV_DIEPTSIZ15_MC
104354  *
104355  * 3 packets
104356  */
104357 #define ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTHREE 0x3
104358 
104359 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */
104360 #define ALT_USB_DEV_DIEPTSIZ15_MC_LSB 29
104361 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */
104362 #define ALT_USB_DEV_DIEPTSIZ15_MC_MSB 30
104363 /* The width in bits of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */
104364 #define ALT_USB_DEV_DIEPTSIZ15_MC_WIDTH 2
104365 /* The mask used to set the ALT_USB_DEV_DIEPTSIZ15_MC register field value. */
104366 #define ALT_USB_DEV_DIEPTSIZ15_MC_SET_MSK 0x60000000
104367 /* The mask used to clear the ALT_USB_DEV_DIEPTSIZ15_MC register field value. */
104368 #define ALT_USB_DEV_DIEPTSIZ15_MC_CLR_MSK 0x9fffffff
104369 /* The reset value of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */
104370 #define ALT_USB_DEV_DIEPTSIZ15_MC_RESET 0x0
104371 /* Extracts the ALT_USB_DEV_DIEPTSIZ15_MC field value from a register. */
104372 #define ALT_USB_DEV_DIEPTSIZ15_MC_GET(value) (((value) & 0x60000000) >> 29)
104373 /* Produces a ALT_USB_DEV_DIEPTSIZ15_MC register field value suitable for setting the register. */
104374 #define ALT_USB_DEV_DIEPTSIZ15_MC_SET(value) (((value) << 29) & 0x60000000)
104375 
104376 #ifndef __ASSEMBLY__
104377 /*
104378  * WARNING: The C register and register group struct declarations are provided for
104379  * convenience and illustrative purposes. They should, however, be used with
104380  * caution as the C language standard provides no guarantees about the alignment or
104381  * atomicity of device memory accesses. The recommended practice for writing
104382  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
104383  * alt_write_word() functions.
104384  *
104385  * The struct declaration for register ALT_USB_DEV_DIEPTSIZ15.
104386  */
104387 struct ALT_USB_DEV_DIEPTSIZ15_s
104388 {
104389  uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ15_XFERSIZE */
104390  uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ15_PKTCNT */
104391  uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ15_MC */
104392  uint32_t : 1; /* *UNDEFINED* */
104393 };
104394 
104395 /* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ15. */
104396 typedef volatile struct ALT_USB_DEV_DIEPTSIZ15_s ALT_USB_DEV_DIEPTSIZ15_t;
104397 #endif /* __ASSEMBLY__ */
104398 
104399 /* The reset value of the ALT_USB_DEV_DIEPTSIZ15 register. */
104400 #define ALT_USB_DEV_DIEPTSIZ15_RESET 0x00000000
104401 /* The byte offset of the ALT_USB_DEV_DIEPTSIZ15 register from the beginning of the component. */
104402 #define ALT_USB_DEV_DIEPTSIZ15_OFST 0x2f0
104403 /* The address of the ALT_USB_DEV_DIEPTSIZ15 register. */
104404 #define ALT_USB_DEV_DIEPTSIZ15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ15_OFST))
104405 
104406 /*
104407  * Register : diepdma15
104408  *
104409  * Device IN Endpoint 15 DMA Address Register
104410  *
104411  * Register Layout
104412  *
104413  * Bits | Access | Reset | Description
104414  * :-------|:-------|:--------|:--------------------------------
104415  * [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA15_DIEPDMA15
104416  *
104417  */
104418 /*
104419  * Field : diepdma15
104420  *
104421  * Holds the start address of the external memory for storing or fetching endpoint
104422  *
104423  * data.
104424  *
104425  * Note: For control endpoints, this field stores control OUT data packets as well
104426  * as
104427  *
104428  * SETUP transaction data packets. When more than three SETUP packets are
104429  *
104430  * received back-to-back, the SETUP data packet in the memory is overwritten.
104431  *
104432  * This register is incremented on every AHB transaction. The application can give
104433  *
104434  * only a DWORD-aligned address.
104435  *
104436  * When Scatter/Gather DMA mode is not enabled, the application programs the
104437  *
104438  * start address value in this field.
104439  *
104440  * When Scatter/Gather DMA mode is enabled, this field indicates the base
104441  *
104442  * pointer for the descriptor list.
104443  *
104444  * Field Access Macros:
104445  *
104446  */
104447 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field. */
104448 #define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_LSB 0
104449 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field. */
104450 #define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_MSB 31
104451 /* The width in bits of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field. */
104452 #define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_WIDTH 32
104453 /* The mask used to set the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field value. */
104454 #define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_SET_MSK 0xffffffff
104455 /* The mask used to clear the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field value. */
104456 #define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_CLR_MSK 0x00000000
104457 /* The reset value of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field is UNKNOWN. */
104458 #define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_RESET 0x0
104459 /* Extracts the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 field value from a register. */
104460 #define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_GET(value) (((value) & 0xffffffff) >> 0)
104461 /* Produces a ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field value suitable for setting the register. */
104462 #define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_SET(value) (((value) << 0) & 0xffffffff)
104463 
104464 #ifndef __ASSEMBLY__
104465 /*
104466  * WARNING: The C register and register group struct declarations are provided for
104467  * convenience and illustrative purposes. They should, however, be used with
104468  * caution as the C language standard provides no guarantees about the alignment or
104469  * atomicity of device memory accesses. The recommended practice for writing
104470  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
104471  * alt_write_word() functions.
104472  *
104473  * The struct declaration for register ALT_USB_DEV_DIEPDMA15.
104474  */
104475 struct ALT_USB_DEV_DIEPDMA15_s
104476 {
104477  uint32_t diepdma15 : 32; /* ALT_USB_DEV_DIEPDMA15_DIEPDMA15 */
104478 };
104479 
104480 /* The typedef declaration for register ALT_USB_DEV_DIEPDMA15. */
104481 typedef volatile struct ALT_USB_DEV_DIEPDMA15_s ALT_USB_DEV_DIEPDMA15_t;
104482 #endif /* __ASSEMBLY__ */
104483 
104484 /* The reset value of the ALT_USB_DEV_DIEPDMA15 register. */
104485 #define ALT_USB_DEV_DIEPDMA15_RESET 0x00000000
104486 /* The byte offset of the ALT_USB_DEV_DIEPDMA15 register from the beginning of the component. */
104487 #define ALT_USB_DEV_DIEPDMA15_OFST 0x2f4
104488 /* The address of the ALT_USB_DEV_DIEPDMA15 register. */
104489 #define ALT_USB_DEV_DIEPDMA15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA15_OFST))
104490 
104491 /*
104492  * Register : dtxfsts15
104493  *
104494  * Device IN Endpoint Transmit FIFO Status Register 15
104495  *
104496  * Register Layout
104497  *
104498  * Bits | Access | Reset | Description
104499  * :--------|:-------|:-------|:--------------------------------------
104500  * [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL
104501  * [31:16] | ??? | 0x0 | *UNDEFINED*
104502  *
104503  */
104504 /*
104505  * Field : ineptxfspcavail
104506  *
104507  * IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
104508  *
104509  * Indicates the amount of free space available in the Endpoint
104510  *
104511  * TxFIFO.
104512  *
104513  * Values are in terms of 32-bit words.
104514  *
104515  * 16'h0: Endpoint TxFIFO is full
104516  *
104517  * 16'h1: 1 word available
104518  *
104519  * 16'h2: 2 words available
104520  *
104521  * 16'hn: n words available (where 0 n 32,768)
104522  *
104523  * 16'h8000: 32,768 words available
104524  *
104525  * Others: Reserved
104526  *
104527  * Field Access Macros:
104528  *
104529  */
104530 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */
104531 #define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_LSB 0
104532 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */
104533 #define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_MSB 15
104534 /* The width in bits of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */
104535 #define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_WIDTH 16
104536 /* The mask used to set the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field value. */
104537 #define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
104538 /* The mask used to clear the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field value. */
104539 #define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
104540 /* The reset value of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */
104541 #define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_RESET 0x2000
104542 /* Extracts the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL field value from a register. */
104543 #define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
104544 /* Produces a ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field value suitable for setting the register. */
104545 #define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
104546 
104547 #ifndef __ASSEMBLY__
104548 /*
104549  * WARNING: The C register and register group struct declarations are provided for
104550  * convenience and illustrative purposes. They should, however, be used with
104551  * caution as the C language standard provides no guarantees about the alignment or
104552  * atomicity of device memory accesses. The recommended practice for writing
104553  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
104554  * alt_write_word() functions.
104555  *
104556  * The struct declaration for register ALT_USB_DEV_DTXFSTS15.
104557  */
104558 struct ALT_USB_DEV_DTXFSTS15_s
104559 {
104560  const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL */
104561  uint32_t : 16; /* *UNDEFINED* */
104562 };
104563 
104564 /* The typedef declaration for register ALT_USB_DEV_DTXFSTS15. */
104565 typedef volatile struct ALT_USB_DEV_DTXFSTS15_s ALT_USB_DEV_DTXFSTS15_t;
104566 #endif /* __ASSEMBLY__ */
104567 
104568 /* The reset value of the ALT_USB_DEV_DTXFSTS15 register. */
104569 #define ALT_USB_DEV_DTXFSTS15_RESET 0x00002000
104570 /* The byte offset of the ALT_USB_DEV_DTXFSTS15 register from the beginning of the component. */
104571 #define ALT_USB_DEV_DTXFSTS15_OFST 0x2f8
104572 /* The address of the ALT_USB_DEV_DTXFSTS15 register. */
104573 #define ALT_USB_DEV_DTXFSTS15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS15_OFST))
104574 
104575 /*
104576  * Register : diepdmab15
104577  *
104578  * Device IN Endpoint 15 Buffer Address Register
104579  *
104580  * Register Layout
104581  *
104582  * Bits | Access | Reset | Description
104583  * :-------|:-------|:--------|:----------------------------------
104584  * [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15
104585  *
104586  */
104587 /*
104588  * Field : diepdmab15
104589  *
104590  * Holds the current buffer address.This register is updated as and when the data
104591  *
104592  * transfer for the corresponding end point is in progress.
104593  *
104594  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
104595  * is
104596  *
104597  * reserved.
104598  *
104599  * Field Access Macros:
104600  *
104601  */
104602 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field. */
104603 #define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_LSB 0
104604 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field. */
104605 #define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_MSB 31
104606 /* The width in bits of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field. */
104607 #define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_WIDTH 32
104608 /* The mask used to set the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field value. */
104609 #define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_SET_MSK 0xffffffff
104610 /* The mask used to clear the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field value. */
104611 #define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_CLR_MSK 0x00000000
104612 /* The reset value of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field is UNKNOWN. */
104613 #define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_RESET 0x0
104614 /* Extracts the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 field value from a register. */
104615 #define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_GET(value) (((value) & 0xffffffff) >> 0)
104616 /* Produces a ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field value suitable for setting the register. */
104617 #define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_SET(value) (((value) << 0) & 0xffffffff)
104618 
104619 #ifndef __ASSEMBLY__
104620 /*
104621  * WARNING: The C register and register group struct declarations are provided for
104622  * convenience and illustrative purposes. They should, however, be used with
104623  * caution as the C language standard provides no guarantees about the alignment or
104624  * atomicity of device memory accesses. The recommended practice for writing
104625  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
104626  * alt_write_word() functions.
104627  *
104628  * The struct declaration for register ALT_USB_DEV_DIEPDMAB15.
104629  */
104630 struct ALT_USB_DEV_DIEPDMAB15_s
104631 {
104632  const uint32_t diepdmab15 : 32; /* ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 */
104633 };
104634 
104635 /* The typedef declaration for register ALT_USB_DEV_DIEPDMAB15. */
104636 typedef volatile struct ALT_USB_DEV_DIEPDMAB15_s ALT_USB_DEV_DIEPDMAB15_t;
104637 #endif /* __ASSEMBLY__ */
104638 
104639 /* The reset value of the ALT_USB_DEV_DIEPDMAB15 register. */
104640 #define ALT_USB_DEV_DIEPDMAB15_RESET 0x00000000
104641 /* The byte offset of the ALT_USB_DEV_DIEPDMAB15 register from the beginning of the component. */
104642 #define ALT_USB_DEV_DIEPDMAB15_OFST 0x2fc
104643 /* The address of the ALT_USB_DEV_DIEPDMAB15 register. */
104644 #define ALT_USB_DEV_DIEPDMAB15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB15_OFST))
104645 
104646 /*
104647  * Register : doepctl0
104648  *
104649  * Device Control OUT Endpoint 0 Control Register
104650  *
104651  * Register Layout
104652  *
104653  * Bits | Access | Reset | Description
104654  * :--------|:---------|:------|:------------------------------
104655  * [1:0] | R | 0x0 | ALT_USB_DEV_DOEPCTL0_MPS
104656  * [14:2] | ??? | 0x0 | *UNDEFINED*
104657  * [15] | R | 0x1 | ALT_USB_DEV_DOEPCTL0_USBACTEP
104658  * [16] | ??? | 0x0 | *UNDEFINED*
104659  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL0_NAKSTS
104660  * [19:18] | R | 0x0 | ALT_USB_DEV_DOEPCTL0_EPTYPE
104661  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL0_SNP
104662  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL0_STALL
104663  * [25:22] | ??? | 0x0 | *UNDEFINED*
104664  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL0_CNAK
104665  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL0_SNAK
104666  * [29:28] | ??? | 0x0 | *UNDEFINED*
104667  * [30] | R | 0x0 | ALT_USB_DEV_DOEPCTL0_EPDIS
104668  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL0_EPENA
104669  *
104670  */
104671 /*
104672  * Field : mps
104673  *
104674  * Maximum Packet Size (MPS)
104675  *
104676  * The maximum packet size For control OUT endpoint 0 is the
104677  *
104678  * same as what is programmed in control IN Endpoint 0.
104679  *
104680  * 2'b00: 64 bytes
104681  *
104682  * 2'b01: 32 bytes
104683  *
104684  * 2'b10: 16 bytes
104685  *
104686  * 2'b11: 8 bytes
104687  *
104688  * Field Enumeration Values:
104689  *
104690  * Enum | Value | Description
104691  * :----------------------------------|:------|:------------
104692  * ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE64 | 0x0 | 64 bytes
104693  * ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE32 | 0x1 | 32 bytes
104694  * ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE16 | 0x2 | 16 bytes
104695  * ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE8 | 0x3 | 8 bytes
104696  *
104697  * Field Access Macros:
104698  *
104699  */
104700 /*
104701  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS
104702  *
104703  * 64 bytes
104704  */
104705 #define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE64 0x0
104706 /*
104707  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS
104708  *
104709  * 32 bytes
104710  */
104711 #define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE32 0x1
104712 /*
104713  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS
104714  *
104715  * 16 bytes
104716  */
104717 #define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE16 0x2
104718 /*
104719  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS
104720  *
104721  * 8 bytes
104722  */
104723 #define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE8 0x3
104724 
104725 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_MPS register field. */
104726 #define ALT_USB_DEV_DOEPCTL0_MPS_LSB 0
104727 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_MPS register field. */
104728 #define ALT_USB_DEV_DOEPCTL0_MPS_MSB 1
104729 /* The width in bits of the ALT_USB_DEV_DOEPCTL0_MPS register field. */
104730 #define ALT_USB_DEV_DOEPCTL0_MPS_WIDTH 2
104731 /* The mask used to set the ALT_USB_DEV_DOEPCTL0_MPS register field value. */
104732 #define ALT_USB_DEV_DOEPCTL0_MPS_SET_MSK 0x00000003
104733 /* The mask used to clear the ALT_USB_DEV_DOEPCTL0_MPS register field value. */
104734 #define ALT_USB_DEV_DOEPCTL0_MPS_CLR_MSK 0xfffffffc
104735 /* The reset value of the ALT_USB_DEV_DOEPCTL0_MPS register field. */
104736 #define ALT_USB_DEV_DOEPCTL0_MPS_RESET 0x0
104737 /* Extracts the ALT_USB_DEV_DOEPCTL0_MPS field value from a register. */
104738 #define ALT_USB_DEV_DOEPCTL0_MPS_GET(value) (((value) & 0x00000003) >> 0)
104739 /* Produces a ALT_USB_DEV_DOEPCTL0_MPS register field value suitable for setting the register. */
104740 #define ALT_USB_DEV_DOEPCTL0_MPS_SET(value) (((value) << 0) & 0x00000003)
104741 
104742 /*
104743  * Field : usbactep
104744  *
104745  * USB Active Endpoint (USBActEP)
104746  *
104747  * This bit is always Set to 1, indicating that a control endpoint 0 is
104748  *
104749  * always active in all configurations and interfaces.
104750  *
104751  * Field Enumeration Values:
104752  *
104753  * Enum | Value | Description
104754  * :------------------------------------|:------|:----------------------
104755  * ALT_USB_DEV_DOEPCTL0_USBACTEP_E_ACT | 0x1 | USB Active Endpoint 0
104756  *
104757  * Field Access Macros:
104758  *
104759  */
104760 /*
104761  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_USBACTEP
104762  *
104763  * USB Active Endpoint 0
104764  */
104765 #define ALT_USB_DEV_DOEPCTL0_USBACTEP_E_ACT 0x1
104766 
104767 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */
104768 #define ALT_USB_DEV_DOEPCTL0_USBACTEP_LSB 15
104769 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */
104770 #define ALT_USB_DEV_DOEPCTL0_USBACTEP_MSB 15
104771 /* The width in bits of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */
104772 #define ALT_USB_DEV_DOEPCTL0_USBACTEP_WIDTH 1
104773 /* The mask used to set the ALT_USB_DEV_DOEPCTL0_USBACTEP register field value. */
104774 #define ALT_USB_DEV_DOEPCTL0_USBACTEP_SET_MSK 0x00008000
104775 /* The mask used to clear the ALT_USB_DEV_DOEPCTL0_USBACTEP register field value. */
104776 #define ALT_USB_DEV_DOEPCTL0_USBACTEP_CLR_MSK 0xffff7fff
104777 /* The reset value of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */
104778 #define ALT_USB_DEV_DOEPCTL0_USBACTEP_RESET 0x1
104779 /* Extracts the ALT_USB_DEV_DOEPCTL0_USBACTEP field value from a register. */
104780 #define ALT_USB_DEV_DOEPCTL0_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
104781 /* Produces a ALT_USB_DEV_DOEPCTL0_USBACTEP register field value suitable for setting the register. */
104782 #define ALT_USB_DEV_DOEPCTL0_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
104783 
104784 /*
104785  * Field : naksts
104786  *
104787  * NAK Status (NAKSts)
104788  *
104789  * Indicates the following:
104790  *
104791  * 1'b0: The core is transmitting non-NAK handshakes based
104792  *
104793  * on the FIFO status.
104794  *
104795  * 1'b1: The core is transmitting NAK handshakes on this
104796  *
104797  * endpoint.
104798  *
104799  * When either the application or the core sets this bit, the core
104800  *
104801  * stops receiving data, even If there is space in the RxFIFO to
104802  *
104803  * accommodate the incoming packet. Irrespective of this bit's
104804  *
104805  * setting, the core always responds to SETUP data packets with
104806  *
104807  * an ACK handshake.
104808  *
104809  * Field Enumeration Values:
104810  *
104811  * Enum | Value | Description
104812  * :------------------------------------|:------|:------------------------------------------------
104813  * ALT_USB_DEV_DOEPCTL0_NAKSTS_E_INACT | 0x0 | The core is transmitting non-NAK handshakes
104814  * : | | based on the FIFO status
104815  * ALT_USB_DEV_DOEPCTL0_NAKSTS_E_ACT | 0x1 | The core is transmitting NAK handshakes on this
104816  * : | | endpoint
104817  *
104818  * Field Access Macros:
104819  *
104820  */
104821 /*
104822  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_NAKSTS
104823  *
104824  * The core is transmitting non-NAK handshakes based on the FIFO status
104825  */
104826 #define ALT_USB_DEV_DOEPCTL0_NAKSTS_E_INACT 0x0
104827 /*
104828  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_NAKSTS
104829  *
104830  * The core is transmitting NAK handshakes on this endpoint
104831  */
104832 #define ALT_USB_DEV_DOEPCTL0_NAKSTS_E_ACT 0x1
104833 
104834 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */
104835 #define ALT_USB_DEV_DOEPCTL0_NAKSTS_LSB 17
104836 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */
104837 #define ALT_USB_DEV_DOEPCTL0_NAKSTS_MSB 17
104838 /* The width in bits of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */
104839 #define ALT_USB_DEV_DOEPCTL0_NAKSTS_WIDTH 1
104840 /* The mask used to set the ALT_USB_DEV_DOEPCTL0_NAKSTS register field value. */
104841 #define ALT_USB_DEV_DOEPCTL0_NAKSTS_SET_MSK 0x00020000
104842 /* The mask used to clear the ALT_USB_DEV_DOEPCTL0_NAKSTS register field value. */
104843 #define ALT_USB_DEV_DOEPCTL0_NAKSTS_CLR_MSK 0xfffdffff
104844 /* The reset value of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */
104845 #define ALT_USB_DEV_DOEPCTL0_NAKSTS_RESET 0x0
104846 /* Extracts the ALT_USB_DEV_DOEPCTL0_NAKSTS field value from a register. */
104847 #define ALT_USB_DEV_DOEPCTL0_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
104848 /* Produces a ALT_USB_DEV_DOEPCTL0_NAKSTS register field value suitable for setting the register. */
104849 #define ALT_USB_DEV_DOEPCTL0_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
104850 
104851 /*
104852  * Field : eptype
104853  *
104854  * Endpoint Type (EPType)
104855  *
104856  * Hardcoded to 2'b00 For control.
104857  *
104858  * Field Enumeration Values:
104859  *
104860  * Enum | Value | Description
104861  * :----------------------------------|:------|:-------------------
104862  * ALT_USB_DEV_DOEPCTL0_EPTYPE_E_ACT | 0x0 | Endpoint Control 0
104863  *
104864  * Field Access Macros:
104865  *
104866  */
104867 /*
104868  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPTYPE
104869  *
104870  * Endpoint Control 0
104871  */
104872 #define ALT_USB_DEV_DOEPCTL0_EPTYPE_E_ACT 0x0
104873 
104874 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */
104875 #define ALT_USB_DEV_DOEPCTL0_EPTYPE_LSB 18
104876 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */
104877 #define ALT_USB_DEV_DOEPCTL0_EPTYPE_MSB 19
104878 /* The width in bits of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */
104879 #define ALT_USB_DEV_DOEPCTL0_EPTYPE_WIDTH 2
104880 /* The mask used to set the ALT_USB_DEV_DOEPCTL0_EPTYPE register field value. */
104881 #define ALT_USB_DEV_DOEPCTL0_EPTYPE_SET_MSK 0x000c0000
104882 /* The mask used to clear the ALT_USB_DEV_DOEPCTL0_EPTYPE register field value. */
104883 #define ALT_USB_DEV_DOEPCTL0_EPTYPE_CLR_MSK 0xfff3ffff
104884 /* The reset value of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */
104885 #define ALT_USB_DEV_DOEPCTL0_EPTYPE_RESET 0x0
104886 /* Extracts the ALT_USB_DEV_DOEPCTL0_EPTYPE field value from a register. */
104887 #define ALT_USB_DEV_DOEPCTL0_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
104888 /* Produces a ALT_USB_DEV_DOEPCTL0_EPTYPE register field value suitable for setting the register. */
104889 #define ALT_USB_DEV_DOEPCTL0_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
104890 
104891 /*
104892  * Field : snp
104893  *
104894  * Snoop Mode (Snp)
104895  *
104896  * This bit configures the endpoint to Snoop mode. In Snoop mode,
104897  *
104898  * the core does not check the correctness of OUT packets before
104899  *
104900  * transferring them to application memory.
104901  *
104902  * Field Enumeration Values:
104903  *
104904  * Enum | Value | Description
104905  * :--------------------------------|:------|:--------------------
104906  * ALT_USB_DEV_DOEPCTL0_SNP_E_DISD | 0x0 | Snoop Mode disabled
104907  * ALT_USB_DEV_DOEPCTL0_SNP_E_END | 0x1 | Snoop Mode enabled
104908  *
104909  * Field Access Macros:
104910  *
104911  */
104912 /*
104913  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNP
104914  *
104915  * Snoop Mode disabled
104916  */
104917 #define ALT_USB_DEV_DOEPCTL0_SNP_E_DISD 0x0
104918 /*
104919  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNP
104920  *
104921  * Snoop Mode enabled
104922  */
104923 #define ALT_USB_DEV_DOEPCTL0_SNP_E_END 0x1
104924 
104925 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_SNP register field. */
104926 #define ALT_USB_DEV_DOEPCTL0_SNP_LSB 20
104927 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_SNP register field. */
104928 #define ALT_USB_DEV_DOEPCTL0_SNP_MSB 20
104929 /* The width in bits of the ALT_USB_DEV_DOEPCTL0_SNP register field. */
104930 #define ALT_USB_DEV_DOEPCTL0_SNP_WIDTH 1
104931 /* The mask used to set the ALT_USB_DEV_DOEPCTL0_SNP register field value. */
104932 #define ALT_USB_DEV_DOEPCTL0_SNP_SET_MSK 0x00100000
104933 /* The mask used to clear the ALT_USB_DEV_DOEPCTL0_SNP register field value. */
104934 #define ALT_USB_DEV_DOEPCTL0_SNP_CLR_MSK 0xffefffff
104935 /* The reset value of the ALT_USB_DEV_DOEPCTL0_SNP register field. */
104936 #define ALT_USB_DEV_DOEPCTL0_SNP_RESET 0x0
104937 /* Extracts the ALT_USB_DEV_DOEPCTL0_SNP field value from a register. */
104938 #define ALT_USB_DEV_DOEPCTL0_SNP_GET(value) (((value) & 0x00100000) >> 20)
104939 /* Produces a ALT_USB_DEV_DOEPCTL0_SNP register field value suitable for setting the register. */
104940 #define ALT_USB_DEV_DOEPCTL0_SNP_SET(value) (((value) << 20) & 0x00100000)
104941 
104942 /*
104943  * Field : stall
104944  *
104945  * STALL Handshake (Stall)
104946  *
104947  * The application can only Set this bit, and the core clears it, when
104948  *
104949  * a SETUP token is received For this endpoint. If a NAK bit or
104950  *
104951  * Global OUT NAK is Set along with this bit, the STALL bit takes
104952  *
104953  * priority. Irrespective of this bit's setting, the core always
104954  *
104955  * responds to SETUP data packets with an ACK handshake.
104956  *
104957  * Field Enumeration Values:
104958  *
104959  * Enum | Value | Description
104960  * :-----------------------------------|:------|:----------------
104961  * ALT_USB_DEV_DOEPCTL0_STALL_E_INACT | 0x0 | No Stall
104962  * ALT_USB_DEV_DOEPCTL0_STALL_E_ACT | 0x1 | Stall Handshake
104963  *
104964  * Field Access Macros:
104965  *
104966  */
104967 /*
104968  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_STALL
104969  *
104970  * No Stall
104971  */
104972 #define ALT_USB_DEV_DOEPCTL0_STALL_E_INACT 0x0
104973 /*
104974  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_STALL
104975  *
104976  * Stall Handshake
104977  */
104978 #define ALT_USB_DEV_DOEPCTL0_STALL_E_ACT 0x1
104979 
104980 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_STALL register field. */
104981 #define ALT_USB_DEV_DOEPCTL0_STALL_LSB 21
104982 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_STALL register field. */
104983 #define ALT_USB_DEV_DOEPCTL0_STALL_MSB 21
104984 /* The width in bits of the ALT_USB_DEV_DOEPCTL0_STALL register field. */
104985 #define ALT_USB_DEV_DOEPCTL0_STALL_WIDTH 1
104986 /* The mask used to set the ALT_USB_DEV_DOEPCTL0_STALL register field value. */
104987 #define ALT_USB_DEV_DOEPCTL0_STALL_SET_MSK 0x00200000
104988 /* The mask used to clear the ALT_USB_DEV_DOEPCTL0_STALL register field value. */
104989 #define ALT_USB_DEV_DOEPCTL0_STALL_CLR_MSK 0xffdfffff
104990 /* The reset value of the ALT_USB_DEV_DOEPCTL0_STALL register field. */
104991 #define ALT_USB_DEV_DOEPCTL0_STALL_RESET 0x0
104992 /* Extracts the ALT_USB_DEV_DOEPCTL0_STALL field value from a register. */
104993 #define ALT_USB_DEV_DOEPCTL0_STALL_GET(value) (((value) & 0x00200000) >> 21)
104994 /* Produces a ALT_USB_DEV_DOEPCTL0_STALL register field value suitable for setting the register. */
104995 #define ALT_USB_DEV_DOEPCTL0_STALL_SET(value) (((value) << 21) & 0x00200000)
104996 
104997 /*
104998  * Field : cnak
104999  *
105000  * Clear NAK (CNAK)
105001  *
105002  * A write to this bit clears the NAK bit For the endpoint.
105003  *
105004  * Field Enumeration Values:
105005  *
105006  * Enum | Value | Description
105007  * :----------------------------------|:------|:------------
105008  * ALT_USB_DEV_DOEPCTL0_CNAK_E_NOCLR | 0x0 | No action
105009  * ALT_USB_DEV_DOEPCTL0_CNAK_E_CLR | 0x1 | Clear NAK
105010  *
105011  * Field Access Macros:
105012  *
105013  */
105014 /*
105015  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_CNAK
105016  *
105017  * No action
105018  */
105019 #define ALT_USB_DEV_DOEPCTL0_CNAK_E_NOCLR 0x0
105020 /*
105021  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_CNAK
105022  *
105023  * Clear NAK
105024  */
105025 #define ALT_USB_DEV_DOEPCTL0_CNAK_E_CLR 0x1
105026 
105027 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */
105028 #define ALT_USB_DEV_DOEPCTL0_CNAK_LSB 26
105029 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */
105030 #define ALT_USB_DEV_DOEPCTL0_CNAK_MSB 26
105031 /* The width in bits of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */
105032 #define ALT_USB_DEV_DOEPCTL0_CNAK_WIDTH 1
105033 /* The mask used to set the ALT_USB_DEV_DOEPCTL0_CNAK register field value. */
105034 #define ALT_USB_DEV_DOEPCTL0_CNAK_SET_MSK 0x04000000
105035 /* The mask used to clear the ALT_USB_DEV_DOEPCTL0_CNAK register field value. */
105036 #define ALT_USB_DEV_DOEPCTL0_CNAK_CLR_MSK 0xfbffffff
105037 /* The reset value of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */
105038 #define ALT_USB_DEV_DOEPCTL0_CNAK_RESET 0x0
105039 /* Extracts the ALT_USB_DEV_DOEPCTL0_CNAK field value from a register. */
105040 #define ALT_USB_DEV_DOEPCTL0_CNAK_GET(value) (((value) & 0x04000000) >> 26)
105041 /* Produces a ALT_USB_DEV_DOEPCTL0_CNAK register field value suitable for setting the register. */
105042 #define ALT_USB_DEV_DOEPCTL0_CNAK_SET(value) (((value) << 26) & 0x04000000)
105043 
105044 /*
105045  * Field : snak
105046  *
105047  * Set NAK (SNAK)
105048  *
105049  * A write to this bit sets the NAK bit For the endpoint.
105050  *
105051  * Using this bit, the application can control the transmission of
105052  *
105053  * NAK handshakes on an endpoint. The core can also Set bit on a
105054  *
105055  * Transfer Completed interrupt, or after a SETUP is received on
105056  *
105057  * the endpoint.
105058  *
105059  * Field Enumeration Values:
105060  *
105061  * Enum | Value | Description
105062  * :----------------------------------|:------|:------------
105063  * ALT_USB_DEV_DOEPCTL0_SNAK_E_NOSET | 0x0 | No action
105064  * ALT_USB_DEV_DOEPCTL0_SNAK_E_SET | 0x1 | Set NAK
105065  *
105066  * Field Access Macros:
105067  *
105068  */
105069 /*
105070  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNAK
105071  *
105072  * No action
105073  */
105074 #define ALT_USB_DEV_DOEPCTL0_SNAK_E_NOSET 0x0
105075 /*
105076  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNAK
105077  *
105078  * Set NAK
105079  */
105080 #define ALT_USB_DEV_DOEPCTL0_SNAK_E_SET 0x1
105081 
105082 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */
105083 #define ALT_USB_DEV_DOEPCTL0_SNAK_LSB 27
105084 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */
105085 #define ALT_USB_DEV_DOEPCTL0_SNAK_MSB 27
105086 /* The width in bits of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */
105087 #define ALT_USB_DEV_DOEPCTL0_SNAK_WIDTH 1
105088 /* The mask used to set the ALT_USB_DEV_DOEPCTL0_SNAK register field value. */
105089 #define ALT_USB_DEV_DOEPCTL0_SNAK_SET_MSK 0x08000000
105090 /* The mask used to clear the ALT_USB_DEV_DOEPCTL0_SNAK register field value. */
105091 #define ALT_USB_DEV_DOEPCTL0_SNAK_CLR_MSK 0xf7ffffff
105092 /* The reset value of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */
105093 #define ALT_USB_DEV_DOEPCTL0_SNAK_RESET 0x0
105094 /* Extracts the ALT_USB_DEV_DOEPCTL0_SNAK field value from a register. */
105095 #define ALT_USB_DEV_DOEPCTL0_SNAK_GET(value) (((value) & 0x08000000) >> 27)
105096 /* Produces a ALT_USB_DEV_DOEPCTL0_SNAK register field value suitable for setting the register. */
105097 #define ALT_USB_DEV_DOEPCTL0_SNAK_SET(value) (((value) << 27) & 0x08000000)
105098 
105099 /*
105100  * Field : epdis
105101  *
105102  * Endpoint Disable (EPDis)
105103  *
105104  * The application cannot disable control OUT endpoint 0.
105105  *
105106  * Field Enumeration Values:
105107  *
105108  * Enum | Value | Description
105109  * :-----------------------------------|:------|:--------------------
105110  * ALT_USB_DEV_DOEPCTL0_EPDIS_E_INACT | 0x0 | No Endpoint disable
105111  *
105112  * Field Access Macros:
105113  *
105114  */
105115 /*
105116  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPDIS
105117  *
105118  * No Endpoint disable
105119  */
105120 #define ALT_USB_DEV_DOEPCTL0_EPDIS_E_INACT 0x0
105121 
105122 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */
105123 #define ALT_USB_DEV_DOEPCTL0_EPDIS_LSB 30
105124 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */
105125 #define ALT_USB_DEV_DOEPCTL0_EPDIS_MSB 30
105126 /* The width in bits of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */
105127 #define ALT_USB_DEV_DOEPCTL0_EPDIS_WIDTH 1
105128 /* The mask used to set the ALT_USB_DEV_DOEPCTL0_EPDIS register field value. */
105129 #define ALT_USB_DEV_DOEPCTL0_EPDIS_SET_MSK 0x40000000
105130 /* The mask used to clear the ALT_USB_DEV_DOEPCTL0_EPDIS register field value. */
105131 #define ALT_USB_DEV_DOEPCTL0_EPDIS_CLR_MSK 0xbfffffff
105132 /* The reset value of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */
105133 #define ALT_USB_DEV_DOEPCTL0_EPDIS_RESET 0x0
105134 /* Extracts the ALT_USB_DEV_DOEPCTL0_EPDIS field value from a register. */
105135 #define ALT_USB_DEV_DOEPCTL0_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
105136 /* Produces a ALT_USB_DEV_DOEPCTL0_EPDIS register field value suitable for setting the register. */
105137 #define ALT_USB_DEV_DOEPCTL0_EPDIS_SET(value) (((value) << 30) & 0x40000000)
105138 
105139 /*
105140  * Field : epena
105141  *
105142  * Endpoint Enable (EPEna)
105143  *
105144  * When Scatter/Gather DMA mode is enabled, For OUT
105145  *
105146  * endpoints this bit indicates that the descriptor structure and
105147  *
105148  * data buffer to receive data is setup.
105149  *
105150  * When Scatter/Gather DMA mode is disabled(such as For
105151  *
105152  * buffer-pointer based DMA mode)this bit indicates that the
105153  *
105154  * application has allocated the memory to start receiving data
105155  *
105156  * from the USB.
105157  *
105158  * The core clears this bit before setting any of the following
105159  *
105160  * interrupts on this endpoint:
105161  *
105162  * SETUP Phase Done
105163  *
105164  * Endpoint Disabled
105165  *
105166  * Transfer Completed
105167  *
105168  * Note: In DMA mode, this bit must be Set For the core to transfer
105169  *
105170  * SETUP data packets into memory.
105171  *
105172  * Field Enumeration Values:
105173  *
105174  * Enum | Value | Description
105175  * :-----------------------------------|:------|:-----------------
105176  * ALT_USB_DEV_DOEPCTL0_EPENA_E_INACT | 0x0 | No action
105177  * ALT_USB_DEV_DOEPCTL0_EPENA_E_ACT | 0x1 | Endpoint Enabled
105178  *
105179  * Field Access Macros:
105180  *
105181  */
105182 /*
105183  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPENA
105184  *
105185  * No action
105186  */
105187 #define ALT_USB_DEV_DOEPCTL0_EPENA_E_INACT 0x0
105188 /*
105189  * Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPENA
105190  *
105191  * Endpoint Enabled
105192  */
105193 #define ALT_USB_DEV_DOEPCTL0_EPENA_E_ACT 0x1
105194 
105195 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */
105196 #define ALT_USB_DEV_DOEPCTL0_EPENA_LSB 31
105197 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */
105198 #define ALT_USB_DEV_DOEPCTL0_EPENA_MSB 31
105199 /* The width in bits of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */
105200 #define ALT_USB_DEV_DOEPCTL0_EPENA_WIDTH 1
105201 /* The mask used to set the ALT_USB_DEV_DOEPCTL0_EPENA register field value. */
105202 #define ALT_USB_DEV_DOEPCTL0_EPENA_SET_MSK 0x80000000
105203 /* The mask used to clear the ALT_USB_DEV_DOEPCTL0_EPENA register field value. */
105204 #define ALT_USB_DEV_DOEPCTL0_EPENA_CLR_MSK 0x7fffffff
105205 /* The reset value of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */
105206 #define ALT_USB_DEV_DOEPCTL0_EPENA_RESET 0x0
105207 /* Extracts the ALT_USB_DEV_DOEPCTL0_EPENA field value from a register. */
105208 #define ALT_USB_DEV_DOEPCTL0_EPENA_GET(value) (((value) & 0x80000000) >> 31)
105209 /* Produces a ALT_USB_DEV_DOEPCTL0_EPENA register field value suitable for setting the register. */
105210 #define ALT_USB_DEV_DOEPCTL0_EPENA_SET(value) (((value) << 31) & 0x80000000)
105211 
105212 #ifndef __ASSEMBLY__
105213 /*
105214  * WARNING: The C register and register group struct declarations are provided for
105215  * convenience and illustrative purposes. They should, however, be used with
105216  * caution as the C language standard provides no guarantees about the alignment or
105217  * atomicity of device memory accesses. The recommended practice for writing
105218  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
105219  * alt_write_word() functions.
105220  *
105221  * The struct declaration for register ALT_USB_DEV_DOEPCTL0.
105222  */
105223 struct ALT_USB_DEV_DOEPCTL0_s
105224 {
105225  const uint32_t mps : 2; /* ALT_USB_DEV_DOEPCTL0_MPS */
105226  uint32_t : 13; /* *UNDEFINED* */
105227  const uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL0_USBACTEP */
105228  uint32_t : 1; /* *UNDEFINED* */
105229  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL0_NAKSTS */
105230  const uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL0_EPTYPE */
105231  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL0_SNP */
105232  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL0_STALL */
105233  uint32_t : 4; /* *UNDEFINED* */
105234  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL0_CNAK */
105235  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL0_SNAK */
105236  uint32_t : 2; /* *UNDEFINED* */
105237  const uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL0_EPDIS */
105238  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL0_EPENA */
105239 };
105240 
105241 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL0. */
105242 typedef volatile struct ALT_USB_DEV_DOEPCTL0_s ALT_USB_DEV_DOEPCTL0_t;
105243 #endif /* __ASSEMBLY__ */
105244 
105245 /* The reset value of the ALT_USB_DEV_DOEPCTL0 register. */
105246 #define ALT_USB_DEV_DOEPCTL0_RESET 0x00008000
105247 /* The byte offset of the ALT_USB_DEV_DOEPCTL0 register from the beginning of the component. */
105248 #define ALT_USB_DEV_DOEPCTL0_OFST 0x300
105249 /* The address of the ALT_USB_DEV_DOEPCTL0 register. */
105250 #define ALT_USB_DEV_DOEPCTL0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL0_OFST))
105251 
105252 /*
105253  * Register : doepint0
105254  *
105255  * Device OUT Endpoint 0 Interrupt Register
105256  *
105257  * Register Layout
105258  *
105259  * Bits | Access | Reset | Description
105260  * :--------|:-------|:------|:------------------------------------
105261  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_XFERCOMPL
105262  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_EPDISBLD
105263  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_AHBERR
105264  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_SETUP
105265  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS
105266  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_STSPHSERCVD
105267  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP
105268  * [7] | ??? | 0x0 | *UNDEFINED*
105269  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_OUTPKTERR
105270  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_BNAINTR
105271  * [10] | ??? | 0x0 | *UNDEFINED*
105272  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_PKTDRPSTS
105273  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_BBLEERR
105274  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_NAKINTRPT
105275  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_NYETINTRPT
105276  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_STUPPKTRCVD
105277  * [31:16] | ??? | 0x0 | *UNDEFINED*
105278  *
105279  */
105280 /*
105281  * Field : xfercompl
105282  *
105283  * Transfer Completed Interrupt (XferCompl)
105284  *
105285  * Applies to IN and OUT endpoints.
105286  *
105287  * When Scatter/Gather DMA mode is enabled
105288  *
105289  * * For IN endpoint this field indicates that the requested data
105290  *
105291  * from the descriptor is moved from external system memory
105292  *
105293  * to internal FIFO.
105294  *
105295  * * For OUT endpoint this field indicates that the requested
105296  *
105297  * data from the internal FIFO is moved to external system
105298  *
105299  * memory. This interrupt is generated only when the
105300  *
105301  * corresponding endpoint descriptor is closed, and the IOC
105302  *
105303  * bit For the corresponding descriptor is Set.
105304  *
105305  * When Scatter/Gather DMA mode is disabled, this field
105306  *
105307  * indicates that the programmed transfer is complete on the
105308  *
105309  * AHB as well as on the USB, For this endpoint.
105310  *
105311  * Field Enumeration Values:
105312  *
105313  * Enum | Value | Description
105314  * :---------------------------------------|:------|:-----------------------------
105315  * ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_INACT | 0x0 | No Interrupt
105316  * ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
105317  *
105318  * Field Access Macros:
105319  *
105320  */
105321 /*
105322  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_XFERCOMPL
105323  *
105324  * No Interrupt
105325  */
105326 #define ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_INACT 0x0
105327 /*
105328  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_XFERCOMPL
105329  *
105330  * Transfer Completed Interrupt
105331  */
105332 #define ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_ACT 0x1
105333 
105334 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */
105335 #define ALT_USB_DEV_DOEPINT0_XFERCOMPL_LSB 0
105336 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */
105337 #define ALT_USB_DEV_DOEPINT0_XFERCOMPL_MSB 0
105338 /* The width in bits of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */
105339 #define ALT_USB_DEV_DOEPINT0_XFERCOMPL_WIDTH 1
105340 /* The mask used to set the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field value. */
105341 #define ALT_USB_DEV_DOEPINT0_XFERCOMPL_SET_MSK 0x00000001
105342 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field value. */
105343 #define ALT_USB_DEV_DOEPINT0_XFERCOMPL_CLR_MSK 0xfffffffe
105344 /* The reset value of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */
105345 #define ALT_USB_DEV_DOEPINT0_XFERCOMPL_RESET 0x0
105346 /* Extracts the ALT_USB_DEV_DOEPINT0_XFERCOMPL field value from a register. */
105347 #define ALT_USB_DEV_DOEPINT0_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
105348 /* Produces a ALT_USB_DEV_DOEPINT0_XFERCOMPL register field value suitable for setting the register. */
105349 #define ALT_USB_DEV_DOEPINT0_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
105350 
105351 /*
105352  * Field : epdisbld
105353  *
105354  * Endpoint Disabled Interrupt (EPDisbld)
105355  *
105356  * Applies to IN and OUT endpoints.
105357  *
105358  * This bit indicates that the endpoint is disabled per the
105359  *
105360  * application's request.
105361  *
105362  * Field Enumeration Values:
105363  *
105364  * Enum | Value | Description
105365  * :--------------------------------------|:------|:----------------------------
105366  * ALT_USB_DEV_DOEPINT0_EPDISBLD_E_INACT | 0x0 | No Interrupt
105367  * ALT_USB_DEV_DOEPINT0_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
105368  *
105369  * Field Access Macros:
105370  *
105371  */
105372 /*
105373  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_EPDISBLD
105374  *
105375  * No Interrupt
105376  */
105377 #define ALT_USB_DEV_DOEPINT0_EPDISBLD_E_INACT 0x0
105378 /*
105379  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_EPDISBLD
105380  *
105381  * Endpoint Disabled Interrupt
105382  */
105383 #define ALT_USB_DEV_DOEPINT0_EPDISBLD_E_ACT 0x1
105384 
105385 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */
105386 #define ALT_USB_DEV_DOEPINT0_EPDISBLD_LSB 1
105387 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */
105388 #define ALT_USB_DEV_DOEPINT0_EPDISBLD_MSB 1
105389 /* The width in bits of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */
105390 #define ALT_USB_DEV_DOEPINT0_EPDISBLD_WIDTH 1
105391 /* The mask used to set the ALT_USB_DEV_DOEPINT0_EPDISBLD register field value. */
105392 #define ALT_USB_DEV_DOEPINT0_EPDISBLD_SET_MSK 0x00000002
105393 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_EPDISBLD register field value. */
105394 #define ALT_USB_DEV_DOEPINT0_EPDISBLD_CLR_MSK 0xfffffffd
105395 /* The reset value of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */
105396 #define ALT_USB_DEV_DOEPINT0_EPDISBLD_RESET 0x0
105397 /* Extracts the ALT_USB_DEV_DOEPINT0_EPDISBLD field value from a register. */
105398 #define ALT_USB_DEV_DOEPINT0_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
105399 /* Produces a ALT_USB_DEV_DOEPINT0_EPDISBLD register field value suitable for setting the register. */
105400 #define ALT_USB_DEV_DOEPINT0_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
105401 
105402 /*
105403  * Field : ahberr
105404  *
105405  * AHB Error (AHBErr)
105406  *
105407  * Applies to IN and OUT endpoints.
105408  *
105409  * This is generated only in Internal DMA mode when there is an
105410  *
105411  * AHB error during an AHB read/write. The application can read
105412  *
105413  * the corresponding endpoint DMA address register to get the
105414  *
105415  * error address.
105416  *
105417  * Field Enumeration Values:
105418  *
105419  * Enum | Value | Description
105420  * :------------------------------------|:------|:--------------------
105421  * ALT_USB_DEV_DOEPINT0_AHBERR_E_INACT | 0x0 | No Interrupt
105422  * ALT_USB_DEV_DOEPINT0_AHBERR_E_ACT | 0x1 | AHB Error interrupt
105423  *
105424  * Field Access Macros:
105425  *
105426  */
105427 /*
105428  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_AHBERR
105429  *
105430  * No Interrupt
105431  */
105432 #define ALT_USB_DEV_DOEPINT0_AHBERR_E_INACT 0x0
105433 /*
105434  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_AHBERR
105435  *
105436  * AHB Error interrupt
105437  */
105438 #define ALT_USB_DEV_DOEPINT0_AHBERR_E_ACT 0x1
105439 
105440 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */
105441 #define ALT_USB_DEV_DOEPINT0_AHBERR_LSB 2
105442 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */
105443 #define ALT_USB_DEV_DOEPINT0_AHBERR_MSB 2
105444 /* The width in bits of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */
105445 #define ALT_USB_DEV_DOEPINT0_AHBERR_WIDTH 1
105446 /* The mask used to set the ALT_USB_DEV_DOEPINT0_AHBERR register field value. */
105447 #define ALT_USB_DEV_DOEPINT0_AHBERR_SET_MSK 0x00000004
105448 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_AHBERR register field value. */
105449 #define ALT_USB_DEV_DOEPINT0_AHBERR_CLR_MSK 0xfffffffb
105450 /* The reset value of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */
105451 #define ALT_USB_DEV_DOEPINT0_AHBERR_RESET 0x0
105452 /* Extracts the ALT_USB_DEV_DOEPINT0_AHBERR field value from a register. */
105453 #define ALT_USB_DEV_DOEPINT0_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
105454 /* Produces a ALT_USB_DEV_DOEPINT0_AHBERR register field value suitable for setting the register. */
105455 #define ALT_USB_DEV_DOEPINT0_AHBERR_SET(value) (((value) << 2) & 0x00000004)
105456 
105457 /*
105458  * Field : setup
105459  *
105460  * SETUP Phase Done (SetUp)
105461  *
105462  * Applies to control OUT endpoints only.
105463  *
105464  * Indicates that the SETUP phase For the control endpoint is
105465  *
105466  * complete and no more back-to-back SETUP packets were
105467  *
105468  * received For the current control transfer. On this interrupt, the
105469  *
105470  * application can decode the received SETUP data packet.
105471  *
105472  * Field Enumeration Values:
105473  *
105474  * Enum | Value | Description
105475  * :-----------------------------------|:------|:--------------------
105476  * ALT_USB_DEV_DOEPINT0_SETUP_E_INACT | 0x0 | No SETUP Phase Done
105477  * ALT_USB_DEV_DOEPINT0_SETUP_E_ACT | 0x1 | SETUP Phase Done
105478  *
105479  * Field Access Macros:
105480  *
105481  */
105482 /*
105483  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_SETUP
105484  *
105485  * No SETUP Phase Done
105486  */
105487 #define ALT_USB_DEV_DOEPINT0_SETUP_E_INACT 0x0
105488 /*
105489  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_SETUP
105490  *
105491  * SETUP Phase Done
105492  */
105493 #define ALT_USB_DEV_DOEPINT0_SETUP_E_ACT 0x1
105494 
105495 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_SETUP register field. */
105496 #define ALT_USB_DEV_DOEPINT0_SETUP_LSB 3
105497 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_SETUP register field. */
105498 #define ALT_USB_DEV_DOEPINT0_SETUP_MSB 3
105499 /* The width in bits of the ALT_USB_DEV_DOEPINT0_SETUP register field. */
105500 #define ALT_USB_DEV_DOEPINT0_SETUP_WIDTH 1
105501 /* The mask used to set the ALT_USB_DEV_DOEPINT0_SETUP register field value. */
105502 #define ALT_USB_DEV_DOEPINT0_SETUP_SET_MSK 0x00000008
105503 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_SETUP register field value. */
105504 #define ALT_USB_DEV_DOEPINT0_SETUP_CLR_MSK 0xfffffff7
105505 /* The reset value of the ALT_USB_DEV_DOEPINT0_SETUP register field. */
105506 #define ALT_USB_DEV_DOEPINT0_SETUP_RESET 0x0
105507 /* Extracts the ALT_USB_DEV_DOEPINT0_SETUP field value from a register. */
105508 #define ALT_USB_DEV_DOEPINT0_SETUP_GET(value) (((value) & 0x00000008) >> 3)
105509 /* Produces a ALT_USB_DEV_DOEPINT0_SETUP register field value suitable for setting the register. */
105510 #define ALT_USB_DEV_DOEPINT0_SETUP_SET(value) (((value) << 3) & 0x00000008)
105511 
105512 /*
105513  * Field : outtknepdis
105514  *
105515  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
105516  *
105517  * Applies only to control OUT endpoints.
105518  *
105519  * Indicates that an OUT token was received when the endpoint
105520  *
105521  * was not yet enabled. This interrupt is asserted on the endpoint
105522  *
105523  * For which the OUT token was received.
105524  *
105525  * Field Enumeration Values:
105526  *
105527  * Enum | Value | Description
105528  * :-----------------------------------------|:------|:---------------------------------------------
105529  * ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
105530  * ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
105531  *
105532  * Field Access Macros:
105533  *
105534  */
105535 /*
105536  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS
105537  *
105538  * No OUT Token Received When Endpoint Disabled
105539  */
105540 #define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_INACT 0x0
105541 /*
105542  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS
105543  *
105544  * OUT Token Received When Endpoint Disabled
105545  */
105546 #define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_ACT 0x1
105547 
105548 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */
105549 #define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_LSB 4
105550 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */
105551 #define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_MSB 4
105552 /* The width in bits of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */
105553 #define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_WIDTH 1
105554 /* The mask used to set the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field value. */
105555 #define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_SET_MSK 0x00000010
105556 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field value. */
105557 #define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_CLR_MSK 0xffffffef
105558 /* The reset value of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */
105559 #define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_RESET 0x0
105560 /* Extracts the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS field value from a register. */
105561 #define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
105562 /* Produces a ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field value suitable for setting the register. */
105563 #define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
105564 
105565 /*
105566  * Field : stsphsercvd
105567  *
105568  * Status Phase Received For Control Write (StsPhseRcvd)
105569  *
105570  * This interrupt is valid only For Control OUT endpoints and only in
105571  *
105572  * Scatter Gather DMA mode.
105573  *
105574  * This interrupt is generated only after the core has transferred all
105575  *
105576  * the data that the host has sent during the data phase of a control
105577  *
105578  * write transfer, to the system memory buffer.
105579  *
105580  * The interrupt indicates to the application that the host has
105581  *
105582  * switched from data phase to the status phase of a Control Write
105583  *
105584  * transfer. The application can use this interrupt to ACK or STALL
105585  *
105586  * the Status phase, after it has decoded the data phase. This is
105587  *
105588  * applicable only in Case of Scatter Gather DMA mode.
105589  *
105590  * Field Enumeration Values:
105591  *
105592  * Enum | Value | Description
105593  * :-----------------------------------------|:------|:-------------------------------------------
105594  * ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
105595  * ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
105596  *
105597  * Field Access Macros:
105598  *
105599  */
105600 /*
105601  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_STSPHSERCVD
105602  *
105603  * No Status Phase Received for Control Write
105604  */
105605 #define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_INACT 0x0
105606 /*
105607  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_STSPHSERCVD
105608  *
105609  * Status Phase Received for Control Write
105610  */
105611 #define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_ACT 0x1
105612 
105613 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */
105614 #define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_LSB 5
105615 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */
105616 #define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_MSB 5
105617 /* The width in bits of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */
105618 #define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_WIDTH 1
105619 /* The mask used to set the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field value. */
105620 #define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_SET_MSK 0x00000020
105621 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field value. */
105622 #define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_CLR_MSK 0xffffffdf
105623 /* The reset value of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */
105624 #define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_RESET 0x0
105625 /* Extracts the ALT_USB_DEV_DOEPINT0_STSPHSERCVD field value from a register. */
105626 #define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
105627 /* Produces a ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field value suitable for setting the register. */
105628 #define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
105629 
105630 /*
105631  * Field : back2backsetup
105632  *
105633  * Back-to-Back SETUP Packets Received (Back2BackSETup)
105634  *
105635  * Applies to Control OUT endpoints only.
105636  *
105637  * This bit indicates that the core has received more than three
105638  *
105639  * back-to-back SETUP packets For this particular endpoint. For
105640  *
105641  * information about handling this interrupt,
105642  *
105643  * Field Enumeration Values:
105644  *
105645  * Enum | Value | Description
105646  * :--------------------------------------------|:------|:---------------------------------------
105647  * ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
105648  * ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
105649  *
105650  * Field Access Macros:
105651  *
105652  */
105653 /*
105654  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP
105655  *
105656  * No Back-to-Back SETUP Packets Received
105657  */
105658 #define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_INACT 0x0
105659 /*
105660  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP
105661  *
105662  * Back-to-Back SETUP Packets Received
105663  */
105664 #define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_ACT 0x1
105665 
105666 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */
105667 #define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_LSB 6
105668 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */
105669 #define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_MSB 6
105670 /* The width in bits of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */
105671 #define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_WIDTH 1
105672 /* The mask used to set the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field value. */
105673 #define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_SET_MSK 0x00000040
105674 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field value. */
105675 #define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_CLR_MSK 0xffffffbf
105676 /* The reset value of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */
105677 #define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_RESET 0x0
105678 /* Extracts the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP field value from a register. */
105679 #define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
105680 /* Produces a ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field value suitable for setting the register. */
105681 #define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
105682 
105683 /*
105684  * Field : outpkterr
105685  *
105686  * OUT Packet Error (OutPktErr)
105687  *
105688  * Applies to OUT endpoints Only
105689  *
105690  * This interrupt is valid only when thresholding is enabled.
105691  *
105692  * This interrupt is asserted when the core detects an overflow
105693  *
105694  * or a CRC error For non-Isochronous OUT packet.
105695  *
105696  * Field Enumeration Values:
105697  *
105698  * Enum | Value | Description
105699  * :---------------------------------------|:------|:--------------------
105700  * ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
105701  * ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
105702  *
105703  * Field Access Macros:
105704  *
105705  */
105706 /*
105707  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTPKTERR
105708  *
105709  * No OUT Packet Error
105710  */
105711 #define ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_INACT 0x0
105712 /*
105713  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTPKTERR
105714  *
105715  * OUT Packet Error
105716  */
105717 #define ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_ACT 0x1
105718 
105719 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */
105720 #define ALT_USB_DEV_DOEPINT0_OUTPKTERR_LSB 8
105721 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */
105722 #define ALT_USB_DEV_DOEPINT0_OUTPKTERR_MSB 8
105723 /* The width in bits of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */
105724 #define ALT_USB_DEV_DOEPINT0_OUTPKTERR_WIDTH 1
105725 /* The mask used to set the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field value. */
105726 #define ALT_USB_DEV_DOEPINT0_OUTPKTERR_SET_MSK 0x00000100
105727 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field value. */
105728 #define ALT_USB_DEV_DOEPINT0_OUTPKTERR_CLR_MSK 0xfffffeff
105729 /* The reset value of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */
105730 #define ALT_USB_DEV_DOEPINT0_OUTPKTERR_RESET 0x0
105731 /* Extracts the ALT_USB_DEV_DOEPINT0_OUTPKTERR field value from a register. */
105732 #define ALT_USB_DEV_DOEPINT0_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
105733 /* Produces a ALT_USB_DEV_DOEPINT0_OUTPKTERR register field value suitable for setting the register. */
105734 #define ALT_USB_DEV_DOEPINT0_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
105735 
105736 /*
105737  * Field : bnaintr
105738  *
105739  * BNA (Buffer Not Available) Interrupt (BNAIntr)
105740  *
105741  * This bit is valid only when Scatter/Gather DMA mode is enabled.
105742  *
105743  * The core generates this interrupt when the descriptor accessed
105744  *
105745  * is not ready For the Core to process, such as Host busy or DMA
105746  *
105747  * done
105748  *
105749  * Field Enumeration Values:
105750  *
105751  * Enum | Value | Description
105752  * :-------------------------------------|:------|:--------------
105753  * ALT_USB_DEV_DOEPINT0_BNAINTR_E_INACT | 0x0 | No interrupt
105754  * ALT_USB_DEV_DOEPINT0_BNAINTR_E_ACT | 0x1 | BNA interrupt
105755  *
105756  * Field Access Macros:
105757  *
105758  */
105759 /*
105760  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BNAINTR
105761  *
105762  * No interrupt
105763  */
105764 #define ALT_USB_DEV_DOEPINT0_BNAINTR_E_INACT 0x0
105765 /*
105766  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BNAINTR
105767  *
105768  * BNA interrupt
105769  */
105770 #define ALT_USB_DEV_DOEPINT0_BNAINTR_E_ACT 0x1
105771 
105772 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */
105773 #define ALT_USB_DEV_DOEPINT0_BNAINTR_LSB 9
105774 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */
105775 #define ALT_USB_DEV_DOEPINT0_BNAINTR_MSB 9
105776 /* The width in bits of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */
105777 #define ALT_USB_DEV_DOEPINT0_BNAINTR_WIDTH 1
105778 /* The mask used to set the ALT_USB_DEV_DOEPINT0_BNAINTR register field value. */
105779 #define ALT_USB_DEV_DOEPINT0_BNAINTR_SET_MSK 0x00000200
105780 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_BNAINTR register field value. */
105781 #define ALT_USB_DEV_DOEPINT0_BNAINTR_CLR_MSK 0xfffffdff
105782 /* The reset value of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */
105783 #define ALT_USB_DEV_DOEPINT0_BNAINTR_RESET 0x0
105784 /* Extracts the ALT_USB_DEV_DOEPINT0_BNAINTR field value from a register. */
105785 #define ALT_USB_DEV_DOEPINT0_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
105786 /* Produces a ALT_USB_DEV_DOEPINT0_BNAINTR register field value suitable for setting the register. */
105787 #define ALT_USB_DEV_DOEPINT0_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
105788 
105789 /*
105790  * Field : pktdrpsts
105791  *
105792  * Packet Drop Status (PktDrpSts)
105793  *
105794  * This bit indicates to the application that an ISOC OUT packet has been dropped.
105795  * This
105796  *
105797  * bit does not have an associated mask bit and does not generate an interrupt.
105798  *
105799  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
105800  * transfer
105801  *
105802  * interrupt feature is selected.
105803  *
105804  * Field Enumeration Values:
105805  *
105806  * Enum | Value | Description
105807  * :---------------------------------------|:------|:-----------------------------
105808  * ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_INACT | 0x0 | No interrupt
105809  * ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
105810  *
105811  * Field Access Macros:
105812  *
105813  */
105814 /*
105815  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_PKTDRPSTS
105816  *
105817  * No interrupt
105818  */
105819 #define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_INACT 0x0
105820 /*
105821  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_PKTDRPSTS
105822  *
105823  * Packet Drop Status interrupt
105824  */
105825 #define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_ACT 0x1
105826 
105827 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */
105828 #define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_LSB 11
105829 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */
105830 #define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_MSB 11
105831 /* The width in bits of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */
105832 #define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_WIDTH 1
105833 /* The mask used to set the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field value. */
105834 #define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_SET_MSK 0x00000800
105835 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field value. */
105836 #define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_CLR_MSK 0xfffff7ff
105837 /* The reset value of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */
105838 #define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_RESET 0x0
105839 /* Extracts the ALT_USB_DEV_DOEPINT0_PKTDRPSTS field value from a register. */
105840 #define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
105841 /* Produces a ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field value suitable for setting the register. */
105842 #define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
105843 
105844 /*
105845  * Field : bbleerr
105846  *
105847  * NAK Interrupt (BbleErr)
105848  *
105849  * The core generates this interrupt when babble is received for the endpoint.
105850  *
105851  * Field Enumeration Values:
105852  *
105853  * Enum | Value | Description
105854  * :-------------------------------------|:------|:------------------
105855  * ALT_USB_DEV_DOEPINT0_BBLEERR_E_INACT | 0x0 | No interrupt
105856  * ALT_USB_DEV_DOEPINT0_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
105857  *
105858  * Field Access Macros:
105859  *
105860  */
105861 /*
105862  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BBLEERR
105863  *
105864  * No interrupt
105865  */
105866 #define ALT_USB_DEV_DOEPINT0_BBLEERR_E_INACT 0x0
105867 /*
105868  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_BBLEERR
105869  *
105870  * BbleErr interrupt
105871  */
105872 #define ALT_USB_DEV_DOEPINT0_BBLEERR_E_ACT 0x1
105873 
105874 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */
105875 #define ALT_USB_DEV_DOEPINT0_BBLEERR_LSB 12
105876 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */
105877 #define ALT_USB_DEV_DOEPINT0_BBLEERR_MSB 12
105878 /* The width in bits of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */
105879 #define ALT_USB_DEV_DOEPINT0_BBLEERR_WIDTH 1
105880 /* The mask used to set the ALT_USB_DEV_DOEPINT0_BBLEERR register field value. */
105881 #define ALT_USB_DEV_DOEPINT0_BBLEERR_SET_MSK 0x00001000
105882 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_BBLEERR register field value. */
105883 #define ALT_USB_DEV_DOEPINT0_BBLEERR_CLR_MSK 0xffffefff
105884 /* The reset value of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */
105885 #define ALT_USB_DEV_DOEPINT0_BBLEERR_RESET 0x0
105886 /* Extracts the ALT_USB_DEV_DOEPINT0_BBLEERR field value from a register. */
105887 #define ALT_USB_DEV_DOEPINT0_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
105888 /* Produces a ALT_USB_DEV_DOEPINT0_BBLEERR register field value suitable for setting the register. */
105889 #define ALT_USB_DEV_DOEPINT0_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
105890 
105891 /*
105892  * Field : nakintrpt
105893  *
105894  * NAK Interrupt (NAKInterrupt)
105895  *
105896  * The core generates this interrupt when a NAK is transmitted or received by the
105897  * device.
105898  *
105899  * In case of isochronous IN endpoints the interrupt gets generated when a zero
105900  * length
105901  *
105902  * packet is transmitted due to un-availability of data in the TXFifo.
105903  *
105904  * Field Enumeration Values:
105905  *
105906  * Enum | Value | Description
105907  * :---------------------------------------|:------|:--------------
105908  * ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_INACT | 0x0 | No interrupt
105909  * ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
105910  *
105911  * Field Access Macros:
105912  *
105913  */
105914 /*
105915  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_NAKINTRPT
105916  *
105917  * No interrupt
105918  */
105919 #define ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_INACT 0x0
105920 /*
105921  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_NAKINTRPT
105922  *
105923  * NAK Interrupt
105924  */
105925 #define ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_ACT 0x1
105926 
105927 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */
105928 #define ALT_USB_DEV_DOEPINT0_NAKINTRPT_LSB 13
105929 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */
105930 #define ALT_USB_DEV_DOEPINT0_NAKINTRPT_MSB 13
105931 /* The width in bits of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */
105932 #define ALT_USB_DEV_DOEPINT0_NAKINTRPT_WIDTH 1
105933 /* The mask used to set the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field value. */
105934 #define ALT_USB_DEV_DOEPINT0_NAKINTRPT_SET_MSK 0x00002000
105935 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field value. */
105936 #define ALT_USB_DEV_DOEPINT0_NAKINTRPT_CLR_MSK 0xffffdfff
105937 /* The reset value of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */
105938 #define ALT_USB_DEV_DOEPINT0_NAKINTRPT_RESET 0x0
105939 /* Extracts the ALT_USB_DEV_DOEPINT0_NAKINTRPT field value from a register. */
105940 #define ALT_USB_DEV_DOEPINT0_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
105941 /* Produces a ALT_USB_DEV_DOEPINT0_NAKINTRPT register field value suitable for setting the register. */
105942 #define ALT_USB_DEV_DOEPINT0_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
105943 
105944 /*
105945  * Field : nyetintrpt
105946  *
105947  * NYET Interrupt (NYETIntrpt)
105948  *
105949  * The core generates this interrupt when a NYET response is transmitted for a non
105950  * isochronous OUT endpoint.
105951  *
105952  * Field Enumeration Values:
105953  *
105954  * Enum | Value | Description
105955  * :----------------------------------------|:------|:---------------
105956  * ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_INACT | 0x0 | No interrupt
105957  * ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
105958  *
105959  * Field Access Macros:
105960  *
105961  */
105962 /*
105963  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_NYETINTRPT
105964  *
105965  * No interrupt
105966  */
105967 #define ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_INACT 0x0
105968 /*
105969  * Enumerated value for register field ALT_USB_DEV_DOEPINT0_NYETINTRPT
105970  *
105971  * NYET Interrupt
105972  */
105973 #define ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_ACT 0x1
105974 
105975 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */
105976 #define ALT_USB_DEV_DOEPINT0_NYETINTRPT_LSB 14
105977 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */
105978 #define ALT_USB_DEV_DOEPINT0_NYETINTRPT_MSB 14
105979 /* The width in bits of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */
105980 #define ALT_USB_DEV_DOEPINT0_NYETINTRPT_WIDTH 1
105981 /* The mask used to set the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field value. */
105982 #define ALT_USB_DEV_DOEPINT0_NYETINTRPT_SET_MSK 0x00004000
105983 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field value. */
105984 #define ALT_USB_DEV_DOEPINT0_NYETINTRPT_CLR_MSK 0xffffbfff
105985 /* The reset value of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */
105986 #define ALT_USB_DEV_DOEPINT0_NYETINTRPT_RESET 0x0
105987 /* Extracts the ALT_USB_DEV_DOEPINT0_NYETINTRPT field value from a register. */
105988 #define ALT_USB_DEV_DOEPINT0_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
105989 /* Produces a ALT_USB_DEV_DOEPINT0_NYETINTRPT register field value suitable for setting the register. */
105990 #define ALT_USB_DEV_DOEPINT0_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
105991 
105992 /*
105993  * Field : stuppktrcvd
105994  *
105995  * Setup Packet Received
105996  *
105997  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
105998  *
105999  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
106000  *
106001  * setup data. There is only one Setup packet per buffer. On receiving a
106002  *
106003  * Setup packet, the DWC_otg core closes the buffer and disables the
106004  *
106005  * corresponding endpoint. The application has to re-enable the endpoint to
106006  *
106007  * receive any OUT data for the Control Transfer and reprogram the buffer
106008  *
106009  * start address.
106010  *
106011  * Note: Because of the above behavior, the DWC_otg core can receive any
106012  *
106013  * number of back to back setup packets and one buffer for every setup
106014  *
106015  * packet is used.
106016  *
106017  * 1'b0: No Setup packet received
106018  *
106019  * 1'b1: Setup packet received
106020  *
106021  * Reset: 1'b0
106022  *
106023  * Field Access Macros:
106024  *
106025  */
106026 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field. */
106027 #define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_LSB 15
106028 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field. */
106029 #define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_MSB 15
106030 /* The width in bits of the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field. */
106031 #define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_WIDTH 1
106032 /* The mask used to set the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field value. */
106033 #define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_SET_MSK 0x00008000
106034 /* The mask used to clear the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field value. */
106035 #define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_CLR_MSK 0xffff7fff
106036 /* The reset value of the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field. */
106037 #define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_RESET 0x0
106038 /* Extracts the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD field value from a register. */
106039 #define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
106040 /* Produces a ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field value suitable for setting the register. */
106041 #define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
106042 
106043 #ifndef __ASSEMBLY__
106044 /*
106045  * WARNING: The C register and register group struct declarations are provided for
106046  * convenience and illustrative purposes. They should, however, be used with
106047  * caution as the C language standard provides no guarantees about the alignment or
106048  * atomicity of device memory accesses. The recommended practice for writing
106049  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
106050  * alt_write_word() functions.
106051  *
106052  * The struct declaration for register ALT_USB_DEV_DOEPINT0.
106053  */
106054 struct ALT_USB_DEV_DOEPINT0_s
106055 {
106056  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT0_XFERCOMPL */
106057  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT0_EPDISBLD */
106058  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT0_AHBERR */
106059  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT0_SETUP */
106060  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS */
106061  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT0_STSPHSERCVD */
106062  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP */
106063  uint32_t : 1; /* *UNDEFINED* */
106064  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT0_OUTPKTERR */
106065  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT0_BNAINTR */
106066  uint32_t : 1; /* *UNDEFINED* */
106067  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT0_PKTDRPSTS */
106068  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT0_BBLEERR */
106069  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT0_NAKINTRPT */
106070  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT0_NYETINTRPT */
106071  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT0_STUPPKTRCVD */
106072  uint32_t : 16; /* *UNDEFINED* */
106073 };
106074 
106075 /* The typedef declaration for register ALT_USB_DEV_DOEPINT0. */
106076 typedef volatile struct ALT_USB_DEV_DOEPINT0_s ALT_USB_DEV_DOEPINT0_t;
106077 #endif /* __ASSEMBLY__ */
106078 
106079 /* The reset value of the ALT_USB_DEV_DOEPINT0 register. */
106080 #define ALT_USB_DEV_DOEPINT0_RESET 0x00000000
106081 /* The byte offset of the ALT_USB_DEV_DOEPINT0 register from the beginning of the component. */
106082 #define ALT_USB_DEV_DOEPINT0_OFST 0x308
106083 /* The address of the ALT_USB_DEV_DOEPINT0 register. */
106084 #define ALT_USB_DEV_DOEPINT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT0_OFST))
106085 
106086 /*
106087  * Register : doeptsiz0
106088  *
106089  * Device OUT Endpoint 0 Transfer Size Register
106090  *
106091  * Register Layout
106092  *
106093  * Bits | Access | Reset | Description
106094  * :--------|:-------|:------|:-------------------------------
106095  * [6:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ0_XFERSIZE
106096  * [18:7] | ??? | 0x0 | *UNDEFINED*
106097  * [19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ0_PKTCNT
106098  * [28:20] | ??? | 0x0 | *UNDEFINED*
106099  * [30:29] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ0_SUPCNT
106100  * [31] | ??? | 0x0 | *UNDEFINED*
106101  *
106102  */
106103 /*
106104  * Field : xfersize
106105  *
106106  * Transfer Size (XferSize)
106107  *
106108  * Indicates the transfer size in bytes For endpoint 0. The core
106109  *
106110  * interrupts the application only after it has exhausted the transfer
106111  *
106112  * size amount of data. The transfer size can be Set to the
106113  *
106114  * maximum packet size of the endpoint, to be interrupted at the
106115  *
106116  * end of each packet.
106117  *
106118  * The core decrements this field every time a packet is read from
106119  *
106120  * the RxFIFO and written to the external memory.
106121  *
106122  * Field Access Macros:
106123  *
106124  */
106125 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */
106126 #define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_LSB 0
106127 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */
106128 #define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_MSB 6
106129 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */
106130 #define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_WIDTH 7
106131 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field value. */
106132 #define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_SET_MSK 0x0000007f
106133 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field value. */
106134 #define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_CLR_MSK 0xffffff80
106135 /* The reset value of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */
106136 #define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_RESET 0x0
106137 /* Extracts the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE field value from a register. */
106138 #define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_GET(value) (((value) & 0x0000007f) >> 0)
106139 /* Produces a ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field value suitable for setting the register. */
106140 #define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_SET(value) (((value) << 0) & 0x0000007f)
106141 
106142 /*
106143  * Field : pktcnt
106144  *
106145  * Packet Count (PktCnt)
106146  *
106147  * This field is decremented to zero after a packet is written into the
106148  *
106149  * RxFIFO.
106150  *
106151  * Field Access Macros:
106152  *
106153  */
106154 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */
106155 #define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_LSB 19
106156 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */
106157 #define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_MSB 19
106158 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */
106159 #define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_WIDTH 1
106160 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field value. */
106161 #define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_SET_MSK 0x00080000
106162 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field value. */
106163 #define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_CLR_MSK 0xfff7ffff
106164 /* The reset value of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */
106165 #define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_RESET 0x0
106166 /* Extracts the ALT_USB_DEV_DOEPTSIZ0_PKTCNT field value from a register. */
106167 #define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_GET(value) (((value) & 0x00080000) >> 19)
106168 /* Produces a ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field value suitable for setting the register. */
106169 #define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_SET(value) (((value) << 19) & 0x00080000)
106170 
106171 /*
106172  * Field : supcnt
106173  *
106174  * SETUP Packet Count (SUPCnt)
106175  *
106176  * This field specifies the number of back-to-back SETUP data
106177  *
106178  * packets the endpoint can receive.
106179  *
106180  * 2'b01: 1 packet
106181  *
106182  * 2'b10: 2 packets
106183  *
106184  * 2'b11: 3 packets
106185  *
106186  * Field Enumeration Values:
106187  *
106188  * Enum | Value | Description
106189  * :----------------------------------------|:------|:------------
106190  * ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_ONEPKT | 0x1 | 1 packet
106191  * ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_TWOPKT | 0x2 | 2 packets
106192  * ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_THREEPKT | 0x3 | 3 packets
106193  *
106194  * Field Access Macros:
106195  *
106196  */
106197 /*
106198  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ0_SUPCNT
106199  *
106200  * 1 packet
106201  */
106202 #define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_ONEPKT 0x1
106203 /*
106204  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ0_SUPCNT
106205  *
106206  * 2 packets
106207  */
106208 #define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_TWOPKT 0x2
106209 /*
106210  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ0_SUPCNT
106211  *
106212  * 3 packets
106213  */
106214 #define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_THREEPKT 0x3
106215 
106216 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */
106217 #define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_LSB 29
106218 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */
106219 #define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_MSB 30
106220 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */
106221 #define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_WIDTH 2
106222 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field value. */
106223 #define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_SET_MSK 0x60000000
106224 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field value. */
106225 #define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_CLR_MSK 0x9fffffff
106226 /* The reset value of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */
106227 #define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_RESET 0x0
106228 /* Extracts the ALT_USB_DEV_DOEPTSIZ0_SUPCNT field value from a register. */
106229 #define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_GET(value) (((value) & 0x60000000) >> 29)
106230 /* Produces a ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field value suitable for setting the register. */
106231 #define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_SET(value) (((value) << 29) & 0x60000000)
106232 
106233 #ifndef __ASSEMBLY__
106234 /*
106235  * WARNING: The C register and register group struct declarations are provided for
106236  * convenience and illustrative purposes. They should, however, be used with
106237  * caution as the C language standard provides no guarantees about the alignment or
106238  * atomicity of device memory accesses. The recommended practice for writing
106239  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
106240  * alt_write_word() functions.
106241  *
106242  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ0.
106243  */
106244 struct ALT_USB_DEV_DOEPTSIZ0_s
106245 {
106246  uint32_t xfersize : 7; /* ALT_USB_DEV_DOEPTSIZ0_XFERSIZE */
106247  uint32_t : 12; /* *UNDEFINED* */
106248  uint32_t pktcnt : 1; /* ALT_USB_DEV_DOEPTSIZ0_PKTCNT */
106249  uint32_t : 9; /* *UNDEFINED* */
106250  uint32_t supcnt : 2; /* ALT_USB_DEV_DOEPTSIZ0_SUPCNT */
106251  uint32_t : 1; /* *UNDEFINED* */
106252 };
106253 
106254 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ0. */
106255 typedef volatile struct ALT_USB_DEV_DOEPTSIZ0_s ALT_USB_DEV_DOEPTSIZ0_t;
106256 #endif /* __ASSEMBLY__ */
106257 
106258 /* The reset value of the ALT_USB_DEV_DOEPTSIZ0 register. */
106259 #define ALT_USB_DEV_DOEPTSIZ0_RESET 0x00000000
106260 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ0 register from the beginning of the component. */
106261 #define ALT_USB_DEV_DOEPTSIZ0_OFST 0x310
106262 /* The address of the ALT_USB_DEV_DOEPTSIZ0 register. */
106263 #define ALT_USB_DEV_DOEPTSIZ0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ0_OFST))
106264 
106265 /*
106266  * Register : doepdma0
106267  *
106268  * Device OUT Endpoint 0 DMA Address Register
106269  *
106270  * Register Layout
106271  *
106272  * Bits | Access | Reset | Description
106273  * :-------|:-------|:--------|:------------------------------
106274  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA0_DOEPDMA0
106275  *
106276  */
106277 /*
106278  * Field : doepdma0
106279  *
106280  * Holds the start address of the external memory for storing or fetching endpoint
106281  *
106282  * data.
106283  *
106284  * Note: For control endpoints, this field stores control OUT data packets as well
106285  * as
106286  *
106287  * SETUP transaction data packets. When more than three SETUP packets are
106288  *
106289  * received back-to-back, the SETUP data packet in the memory is overwritten.
106290  *
106291  * This register is incremented on every AHB transaction. The application can give
106292  *
106293  * only a DWORD-aligned address.
106294  *
106295  * When Scatter/Gather DMA mode is not enabled, the application programs the
106296  *
106297  * start address value in this field.
106298  *
106299  * When Scatter/Gather DMA mode is enabled, this field indicates the base
106300  *
106301  * pointer for the descriptor list.
106302  *
106303  * Field Access Macros:
106304  *
106305  */
106306 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field. */
106307 #define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_LSB 0
106308 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field. */
106309 #define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_MSB 31
106310 /* The width in bits of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field. */
106311 #define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_WIDTH 32
106312 /* The mask used to set the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field value. */
106313 #define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_SET_MSK 0xffffffff
106314 /* The mask used to clear the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field value. */
106315 #define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_CLR_MSK 0x00000000
106316 /* The reset value of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field is UNKNOWN. */
106317 #define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_RESET 0x0
106318 /* Extracts the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 field value from a register. */
106319 #define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_GET(value) (((value) & 0xffffffff) >> 0)
106320 /* Produces a ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field value suitable for setting the register. */
106321 #define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_SET(value) (((value) << 0) & 0xffffffff)
106322 
106323 #ifndef __ASSEMBLY__
106324 /*
106325  * WARNING: The C register and register group struct declarations are provided for
106326  * convenience and illustrative purposes. They should, however, be used with
106327  * caution as the C language standard provides no guarantees about the alignment or
106328  * atomicity of device memory accesses. The recommended practice for writing
106329  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
106330  * alt_write_word() functions.
106331  *
106332  * The struct declaration for register ALT_USB_DEV_DOEPDMA0.
106333  */
106334 struct ALT_USB_DEV_DOEPDMA0_s
106335 {
106336  uint32_t doepdma0 : 32; /* ALT_USB_DEV_DOEPDMA0_DOEPDMA0 */
106337 };
106338 
106339 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA0. */
106340 typedef volatile struct ALT_USB_DEV_DOEPDMA0_s ALT_USB_DEV_DOEPDMA0_t;
106341 #endif /* __ASSEMBLY__ */
106342 
106343 /* The reset value of the ALT_USB_DEV_DOEPDMA0 register. */
106344 #define ALT_USB_DEV_DOEPDMA0_RESET 0x00000000
106345 /* The byte offset of the ALT_USB_DEV_DOEPDMA0 register from the beginning of the component. */
106346 #define ALT_USB_DEV_DOEPDMA0_OFST 0x314
106347 /* The address of the ALT_USB_DEV_DOEPDMA0 register. */
106348 #define ALT_USB_DEV_DOEPDMA0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA0_OFST))
106349 
106350 /*
106351  * Register : doepdmab0
106352  *
106353  * Device OUT Endpoint 16 Buffer Address Register
106354  *
106355  * Register Layout
106356  *
106357  * Bits | Access | Reset | Description
106358  * :-------|:-------|:--------|:--------------------------------
106359  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0
106360  *
106361  */
106362 /*
106363  * Field : doepdmab0
106364  *
106365  * Holds the current buffer address.This register is updated as and when the data
106366  *
106367  * transfer for the corresponding end point is in progress.
106368  *
106369  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
106370  * is
106371  *
106372  * reserved.
106373  *
106374  * Field Access Macros:
106375  *
106376  */
106377 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field. */
106378 #define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_LSB 0
106379 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field. */
106380 #define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_MSB 31
106381 /* The width in bits of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field. */
106382 #define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_WIDTH 32
106383 /* The mask used to set the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field value. */
106384 #define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_SET_MSK 0xffffffff
106385 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field value. */
106386 #define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_CLR_MSK 0x00000000
106387 /* The reset value of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field is UNKNOWN. */
106388 #define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_RESET 0x0
106389 /* Extracts the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 field value from a register. */
106390 #define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_GET(value) (((value) & 0xffffffff) >> 0)
106391 /* Produces a ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field value suitable for setting the register. */
106392 #define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_SET(value) (((value) << 0) & 0xffffffff)
106393 
106394 #ifndef __ASSEMBLY__
106395 /*
106396  * WARNING: The C register and register group struct declarations are provided for
106397  * convenience and illustrative purposes. They should, however, be used with
106398  * caution as the C language standard provides no guarantees about the alignment or
106399  * atomicity of device memory accesses. The recommended practice for writing
106400  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
106401  * alt_write_word() functions.
106402  *
106403  * The struct declaration for register ALT_USB_DEV_DOEPDMAB0.
106404  */
106405 struct ALT_USB_DEV_DOEPDMAB0_s
106406 {
106407  const uint32_t doepdmab0 : 32; /* ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 */
106408 };
106409 
106410 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB0. */
106411 typedef volatile struct ALT_USB_DEV_DOEPDMAB0_s ALT_USB_DEV_DOEPDMAB0_t;
106412 #endif /* __ASSEMBLY__ */
106413 
106414 /* The reset value of the ALT_USB_DEV_DOEPDMAB0 register. */
106415 #define ALT_USB_DEV_DOEPDMAB0_RESET 0x00000000
106416 /* The byte offset of the ALT_USB_DEV_DOEPDMAB0 register from the beginning of the component. */
106417 #define ALT_USB_DEV_DOEPDMAB0_OFST 0x31c
106418 /* The address of the ALT_USB_DEV_DOEPDMAB0 register. */
106419 #define ALT_USB_DEV_DOEPDMAB0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB0_OFST))
106420 
106421 /*
106422  * Register : doepctl1
106423  *
106424  * Device Control OUT Endpoint 1 Control Register
106425  *
106426  * Register Layout
106427  *
106428  * Bits | Access | Reset | Description
106429  * :--------|:---------|:------|:------------------------------
106430  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL1_MPS
106431  * [14:11] | ??? | 0x0 | *UNDEFINED*
106432  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL1_USBACTEP
106433  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL1_DPID
106434  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL1_NAKSTS
106435  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL1_EPTYPE
106436  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL1_SNP
106437  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL1_STALL
106438  * [25:22] | ??? | 0x0 | *UNDEFINED*
106439  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL1_CNAK
106440  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL1_SNAK
106441  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL1_SETD0PID
106442  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL1_SETD1PID
106443  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL1_EPDIS
106444  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL1_EPENA
106445  *
106446  */
106447 /*
106448  * Field : mps
106449  *
106450  * Maximum Packet Size (MPS)
106451  *
106452  * The application must program this field with the maximum packet size for the
106453  * current
106454  *
106455  * logical endpoint. This value is in bytes.
106456  *
106457  * Field Access Macros:
106458  *
106459  */
106460 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_MPS register field. */
106461 #define ALT_USB_DEV_DOEPCTL1_MPS_LSB 0
106462 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_MPS register field. */
106463 #define ALT_USB_DEV_DOEPCTL1_MPS_MSB 10
106464 /* The width in bits of the ALT_USB_DEV_DOEPCTL1_MPS register field. */
106465 #define ALT_USB_DEV_DOEPCTL1_MPS_WIDTH 11
106466 /* The mask used to set the ALT_USB_DEV_DOEPCTL1_MPS register field value. */
106467 #define ALT_USB_DEV_DOEPCTL1_MPS_SET_MSK 0x000007ff
106468 /* The mask used to clear the ALT_USB_DEV_DOEPCTL1_MPS register field value. */
106469 #define ALT_USB_DEV_DOEPCTL1_MPS_CLR_MSK 0xfffff800
106470 /* The reset value of the ALT_USB_DEV_DOEPCTL1_MPS register field. */
106471 #define ALT_USB_DEV_DOEPCTL1_MPS_RESET 0x0
106472 /* Extracts the ALT_USB_DEV_DOEPCTL1_MPS field value from a register. */
106473 #define ALT_USB_DEV_DOEPCTL1_MPS_GET(value) (((value) & 0x000007ff) >> 0)
106474 /* Produces a ALT_USB_DEV_DOEPCTL1_MPS register field value suitable for setting the register. */
106475 #define ALT_USB_DEV_DOEPCTL1_MPS_SET(value) (((value) << 0) & 0x000007ff)
106476 
106477 /*
106478  * Field : usbactep
106479  *
106480  * USB Active Endpoint (USBActEP)
106481  *
106482  * Indicates whether this endpoint is active in the current configuration and
106483  * interface. The
106484  *
106485  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
106486  * reset. After
106487  *
106488  * receiving the SetConfiguration and SetInterface commands, the application must
106489  *
106490  * program endpoint registers accordingly and set this bit.
106491  *
106492  * Field Enumeration Values:
106493  *
106494  * Enum | Value | Description
106495  * :-------------------------------------|:------|:--------------------
106496  * ALT_USB_DEV_DOEPCTL1_USBACTEP_E_DISD | 0x0 | Not Active
106497  * ALT_USB_DEV_DOEPCTL1_USBACTEP_E_END | 0x1 | USB Active Endpoint
106498  *
106499  * Field Access Macros:
106500  *
106501  */
106502 /*
106503  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_USBACTEP
106504  *
106505  * Not Active
106506  */
106507 #define ALT_USB_DEV_DOEPCTL1_USBACTEP_E_DISD 0x0
106508 /*
106509  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_USBACTEP
106510  *
106511  * USB Active Endpoint
106512  */
106513 #define ALT_USB_DEV_DOEPCTL1_USBACTEP_E_END 0x1
106514 
106515 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */
106516 #define ALT_USB_DEV_DOEPCTL1_USBACTEP_LSB 15
106517 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */
106518 #define ALT_USB_DEV_DOEPCTL1_USBACTEP_MSB 15
106519 /* The width in bits of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */
106520 #define ALT_USB_DEV_DOEPCTL1_USBACTEP_WIDTH 1
106521 /* The mask used to set the ALT_USB_DEV_DOEPCTL1_USBACTEP register field value. */
106522 #define ALT_USB_DEV_DOEPCTL1_USBACTEP_SET_MSK 0x00008000
106523 /* The mask used to clear the ALT_USB_DEV_DOEPCTL1_USBACTEP register field value. */
106524 #define ALT_USB_DEV_DOEPCTL1_USBACTEP_CLR_MSK 0xffff7fff
106525 /* The reset value of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */
106526 #define ALT_USB_DEV_DOEPCTL1_USBACTEP_RESET 0x0
106527 /* Extracts the ALT_USB_DEV_DOEPCTL1_USBACTEP field value from a register. */
106528 #define ALT_USB_DEV_DOEPCTL1_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
106529 /* Produces a ALT_USB_DEV_DOEPCTL1_USBACTEP register field value suitable for setting the register. */
106530 #define ALT_USB_DEV_DOEPCTL1_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
106531 
106532 /*
106533  * Field : dpid
106534  *
106535  * Endpoint Data PID (DPID)
106536  *
106537  * Applies to interrupt/bulk IN and OUT endpoints only.
106538  *
106539  * Contains the PID of the packet to be received or transmitted on this endpoint.
106540  * The
106541  *
106542  * application must program the PID of the first packet to be received or
106543  * transmitted on
106544  *
106545  * this endpoint, after the endpoint is activated. The applications use the
106546  * SetD1PID and
106547  *
106548  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
106549  *
106550  * 1'b0: DATA0
106551  *
106552  * 1'b1: DATA1
106553  *
106554  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
106555  *
106556  * DMA mode.
106557  *
106558  * 1'b0 RO
106559  *
106560  * Even/Odd (Micro)Frame (EO_FrNum)
106561  *
106562  * In non-Scatter/Gather DMA mode:
106563  *
106564  * Applies to isochronous IN and OUT endpoints only.
106565  *
106566  * Indicates the (micro)frame number in which the core transmits/receives
106567  * isochronous
106568  *
106569  * data for this endpoint. The application must program the even/odd (micro) frame
106570  *
106571  * number in which it intends to transmit/receive isochronous data for this
106572  * endpoint using
106573  *
106574  * the SetEvnFr and SetOddFr fields in this register.
106575  *
106576  * 1'b0: Even (micro)frame
106577  *
106578  * 1'b1: Odd (micro)frame
106579  *
106580  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
106581  * number
106582  *
106583  * in which to send data is provided in the transmit descriptor structure. The
106584  * frame in
106585  *
106586  * which data is received is updated in receive descriptor structure.
106587  *
106588  * Field Enumeration Values:
106589  *
106590  * Enum | Value | Description
106591  * :----------------------------------|:------|:-----------------------------
106592  * ALT_USB_DEV_DOEPCTL1_DPID_E_INACT | 0x0 | Endpoint Data PID not active
106593  * ALT_USB_DEV_DOEPCTL1_DPID_E_ACT | 0x1 | Endpoint Data PID active
106594  *
106595  * Field Access Macros:
106596  *
106597  */
106598 /*
106599  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_DPID
106600  *
106601  * Endpoint Data PID not active
106602  */
106603 #define ALT_USB_DEV_DOEPCTL1_DPID_E_INACT 0x0
106604 /*
106605  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_DPID
106606  *
106607  * Endpoint Data PID active
106608  */
106609 #define ALT_USB_DEV_DOEPCTL1_DPID_E_ACT 0x1
106610 
106611 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_DPID register field. */
106612 #define ALT_USB_DEV_DOEPCTL1_DPID_LSB 16
106613 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_DPID register field. */
106614 #define ALT_USB_DEV_DOEPCTL1_DPID_MSB 16
106615 /* The width in bits of the ALT_USB_DEV_DOEPCTL1_DPID register field. */
106616 #define ALT_USB_DEV_DOEPCTL1_DPID_WIDTH 1
106617 /* The mask used to set the ALT_USB_DEV_DOEPCTL1_DPID register field value. */
106618 #define ALT_USB_DEV_DOEPCTL1_DPID_SET_MSK 0x00010000
106619 /* The mask used to clear the ALT_USB_DEV_DOEPCTL1_DPID register field value. */
106620 #define ALT_USB_DEV_DOEPCTL1_DPID_CLR_MSK 0xfffeffff
106621 /* The reset value of the ALT_USB_DEV_DOEPCTL1_DPID register field. */
106622 #define ALT_USB_DEV_DOEPCTL1_DPID_RESET 0x0
106623 /* Extracts the ALT_USB_DEV_DOEPCTL1_DPID field value from a register. */
106624 #define ALT_USB_DEV_DOEPCTL1_DPID_GET(value) (((value) & 0x00010000) >> 16)
106625 /* Produces a ALT_USB_DEV_DOEPCTL1_DPID register field value suitable for setting the register. */
106626 #define ALT_USB_DEV_DOEPCTL1_DPID_SET(value) (((value) << 16) & 0x00010000)
106627 
106628 /*
106629  * Field : naksts
106630  *
106631  * NAK Status (NAKSts)
106632  *
106633  * Indicates the following:
106634  *
106635  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
106636  *
106637  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
106638  *
106639  * When either the application or the core sets this bit:
106640  *
106641  * The core stops receiving any data on an OUT endpoint, even if there is space in
106642  *
106643  * the RxFIFO to accommodate the incoming packet.
106644  *
106645  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
106646  *
106647  * endpoint, even if there data is available in the TxFIFO.
106648  *
106649  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
106650  *
106651  * if there data is available in the TxFIFO.
106652  *
106653  * Irrespective of this bit's setting, the core always responds to SETUP data
106654  * packets with
106655  *
106656  * an ACK handshake.
106657  *
106658  * Field Enumeration Values:
106659  *
106660  * Enum | Value | Description
106661  * :-------------------------------------|:------|:------------------------------------------------
106662  * ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
106663  * : | | based on the FIFO status
106664  * ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
106665  * : | | endpoint
106666  *
106667  * Field Access Macros:
106668  *
106669  */
106670 /*
106671  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_NAKSTS
106672  *
106673  * The core is transmitting non-NAK handshakes based on the FIFO status
106674  */
106675 #define ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NONNAK 0x0
106676 /*
106677  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_NAKSTS
106678  *
106679  * The core is transmitting NAK handshakes on this endpoint
106680  */
106681 #define ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NAK 0x1
106682 
106683 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */
106684 #define ALT_USB_DEV_DOEPCTL1_NAKSTS_LSB 17
106685 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */
106686 #define ALT_USB_DEV_DOEPCTL1_NAKSTS_MSB 17
106687 /* The width in bits of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */
106688 #define ALT_USB_DEV_DOEPCTL1_NAKSTS_WIDTH 1
106689 /* The mask used to set the ALT_USB_DEV_DOEPCTL1_NAKSTS register field value. */
106690 #define ALT_USB_DEV_DOEPCTL1_NAKSTS_SET_MSK 0x00020000
106691 /* The mask used to clear the ALT_USB_DEV_DOEPCTL1_NAKSTS register field value. */
106692 #define ALT_USB_DEV_DOEPCTL1_NAKSTS_CLR_MSK 0xfffdffff
106693 /* The reset value of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */
106694 #define ALT_USB_DEV_DOEPCTL1_NAKSTS_RESET 0x0
106695 /* Extracts the ALT_USB_DEV_DOEPCTL1_NAKSTS field value from a register. */
106696 #define ALT_USB_DEV_DOEPCTL1_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
106697 /* Produces a ALT_USB_DEV_DOEPCTL1_NAKSTS register field value suitable for setting the register. */
106698 #define ALT_USB_DEV_DOEPCTL1_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
106699 
106700 /*
106701  * Field : eptype
106702  *
106703  * Endpoint Type (EPType)
106704  *
106705  * This is the transfer type supported by this logical endpoint.
106706  *
106707  * 2'b00: Control
106708  *
106709  * 2'b01: Isochronous
106710  *
106711  * 2'b10: Bulk
106712  *
106713  * 2'b11: Interrupt
106714  *
106715  * Field Enumeration Values:
106716  *
106717  * Enum | Value | Description
106718  * :------------------------------------------|:------|:------------
106719  * ALT_USB_DEV_DOEPCTL1_EPTYPE_E_CTL | 0x0 | Control
106720  * ALT_USB_DEV_DOEPCTL1_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
106721  * ALT_USB_DEV_DOEPCTL1_EPTYPE_E_BULK | 0x2 | Bulk
106722  * ALT_USB_DEV_DOEPCTL1_EPTYPE_E_INTERRUP | 0x3 | Interrupt
106723  *
106724  * Field Access Macros:
106725  *
106726  */
106727 /*
106728  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE
106729  *
106730  * Control
106731  */
106732 #define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_CTL 0x0
106733 /*
106734  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE
106735  *
106736  * Isochronous
106737  */
106738 #define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_ISOCHRONOUS 0x1
106739 /*
106740  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE
106741  *
106742  * Bulk
106743  */
106744 #define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_BULK 0x2
106745 /*
106746  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE
106747  *
106748  * Interrupt
106749  */
106750 #define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_INTERRUP 0x3
106751 
106752 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */
106753 #define ALT_USB_DEV_DOEPCTL1_EPTYPE_LSB 18
106754 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */
106755 #define ALT_USB_DEV_DOEPCTL1_EPTYPE_MSB 19
106756 /* The width in bits of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */
106757 #define ALT_USB_DEV_DOEPCTL1_EPTYPE_WIDTH 2
106758 /* The mask used to set the ALT_USB_DEV_DOEPCTL1_EPTYPE register field value. */
106759 #define ALT_USB_DEV_DOEPCTL1_EPTYPE_SET_MSK 0x000c0000
106760 /* The mask used to clear the ALT_USB_DEV_DOEPCTL1_EPTYPE register field value. */
106761 #define ALT_USB_DEV_DOEPCTL1_EPTYPE_CLR_MSK 0xfff3ffff
106762 /* The reset value of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */
106763 #define ALT_USB_DEV_DOEPCTL1_EPTYPE_RESET 0x0
106764 /* Extracts the ALT_USB_DEV_DOEPCTL1_EPTYPE field value from a register. */
106765 #define ALT_USB_DEV_DOEPCTL1_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
106766 /* Produces a ALT_USB_DEV_DOEPCTL1_EPTYPE register field value suitable for setting the register. */
106767 #define ALT_USB_DEV_DOEPCTL1_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
106768 
106769 /*
106770  * Field : snp
106771  *
106772  * Snoop Mode (Snp)
106773  *
106774  * Applies to OUT endpoints only.
106775  *
106776  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
106777  *
106778  * check the correctness of OUT packets before transferring them to application
106779  * memory.
106780  *
106781  * Field Enumeration Values:
106782  *
106783  * Enum | Value | Description
106784  * :-------------------------------|:------|:-------------------
106785  * ALT_USB_DEV_DOEPCTL1_SNP_E_DIS | 0x0 | Disable Snoop Mode
106786  * ALT_USB_DEV_DOEPCTL1_SNP_E_EN | 0x1 | Enable Snoop Mode
106787  *
106788  * Field Access Macros:
106789  *
106790  */
106791 /*
106792  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNP
106793  *
106794  * Disable Snoop Mode
106795  */
106796 #define ALT_USB_DEV_DOEPCTL1_SNP_E_DIS 0x0
106797 /*
106798  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNP
106799  *
106800  * Enable Snoop Mode
106801  */
106802 #define ALT_USB_DEV_DOEPCTL1_SNP_E_EN 0x1
106803 
106804 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SNP register field. */
106805 #define ALT_USB_DEV_DOEPCTL1_SNP_LSB 20
106806 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SNP register field. */
106807 #define ALT_USB_DEV_DOEPCTL1_SNP_MSB 20
106808 /* The width in bits of the ALT_USB_DEV_DOEPCTL1_SNP register field. */
106809 #define ALT_USB_DEV_DOEPCTL1_SNP_WIDTH 1
106810 /* The mask used to set the ALT_USB_DEV_DOEPCTL1_SNP register field value. */
106811 #define ALT_USB_DEV_DOEPCTL1_SNP_SET_MSK 0x00100000
106812 /* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SNP register field value. */
106813 #define ALT_USB_DEV_DOEPCTL1_SNP_CLR_MSK 0xffefffff
106814 /* The reset value of the ALT_USB_DEV_DOEPCTL1_SNP register field. */
106815 #define ALT_USB_DEV_DOEPCTL1_SNP_RESET 0x0
106816 /* Extracts the ALT_USB_DEV_DOEPCTL1_SNP field value from a register. */
106817 #define ALT_USB_DEV_DOEPCTL1_SNP_GET(value) (((value) & 0x00100000) >> 20)
106818 /* Produces a ALT_USB_DEV_DOEPCTL1_SNP register field value suitable for setting the register. */
106819 #define ALT_USB_DEV_DOEPCTL1_SNP_SET(value) (((value) << 20) & 0x00100000)
106820 
106821 /*
106822  * Field : stall
106823  *
106824  * STALL Handshake (Stall)
106825  *
106826  * Applies to non-control, non-isochronous IN and OUT endpoints only.
106827  *
106828  * The application sets this bit to stall all tokens from the USB host to this
106829  * endpoint. If a
106830  *
106831  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
106832  * bit, the
106833  *
106834  * STALL bit takes priority. Only the application can clear this bit, never the
106835  * core.
106836  *
106837  * 1'b0 R_W
106838  *
106839  * Applies to control endpoints only.
106840  *
106841  * The application can only set this bit, and the core clears it, when a SETUP
106842  * token is
106843  *
106844  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
106845  * OUT
106846  *
106847  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
106848  * this bit's
106849  *
106850  * setting, the core always responds to SETUP data packets with an ACK handshake.
106851  *
106852  * Field Enumeration Values:
106853  *
106854  * Enum | Value | Description
106855  * :-----------------------------------|:------|:----------------------------
106856  * ALT_USB_DEV_DOEPCTL1_STALL_E_INACT | 0x0 | STALL All Tokens not active
106857  * ALT_USB_DEV_DOEPCTL1_STALL_E_ACT | 0x1 | STALL All Tokens active
106858  *
106859  * Field Access Macros:
106860  *
106861  */
106862 /*
106863  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_STALL
106864  *
106865  * STALL All Tokens not active
106866  */
106867 #define ALT_USB_DEV_DOEPCTL1_STALL_E_INACT 0x0
106868 /*
106869  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_STALL
106870  *
106871  * STALL All Tokens active
106872  */
106873 #define ALT_USB_DEV_DOEPCTL1_STALL_E_ACT 0x1
106874 
106875 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_STALL register field. */
106876 #define ALT_USB_DEV_DOEPCTL1_STALL_LSB 21
106877 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_STALL register field. */
106878 #define ALT_USB_DEV_DOEPCTL1_STALL_MSB 21
106879 /* The width in bits of the ALT_USB_DEV_DOEPCTL1_STALL register field. */
106880 #define ALT_USB_DEV_DOEPCTL1_STALL_WIDTH 1
106881 /* The mask used to set the ALT_USB_DEV_DOEPCTL1_STALL register field value. */
106882 #define ALT_USB_DEV_DOEPCTL1_STALL_SET_MSK 0x00200000
106883 /* The mask used to clear the ALT_USB_DEV_DOEPCTL1_STALL register field value. */
106884 #define ALT_USB_DEV_DOEPCTL1_STALL_CLR_MSK 0xffdfffff
106885 /* The reset value of the ALT_USB_DEV_DOEPCTL1_STALL register field. */
106886 #define ALT_USB_DEV_DOEPCTL1_STALL_RESET 0x0
106887 /* Extracts the ALT_USB_DEV_DOEPCTL1_STALL field value from a register. */
106888 #define ALT_USB_DEV_DOEPCTL1_STALL_GET(value) (((value) & 0x00200000) >> 21)
106889 /* Produces a ALT_USB_DEV_DOEPCTL1_STALL register field value suitable for setting the register. */
106890 #define ALT_USB_DEV_DOEPCTL1_STALL_SET(value) (((value) << 21) & 0x00200000)
106891 
106892 /*
106893  * Field : cnak
106894  *
106895  * Clear NAK (CNAK)
106896  *
106897  * A write to this bit clears the NAK bit For the endpoint.
106898  *
106899  * Field Enumeration Values:
106900  *
106901  * Enum | Value | Description
106902  * :----------------------------------|:------|:-------------
106903  * ALT_USB_DEV_DOEPCTL1_CNAK_E_INACT | 0x0 | No Clear NAK
106904  * ALT_USB_DEV_DOEPCTL1_CNAK_E_ACT | 0x1 | Clear NAK
106905  *
106906  * Field Access Macros:
106907  *
106908  */
106909 /*
106910  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_CNAK
106911  *
106912  * No Clear NAK
106913  */
106914 #define ALT_USB_DEV_DOEPCTL1_CNAK_E_INACT 0x0
106915 /*
106916  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_CNAK
106917  *
106918  * Clear NAK
106919  */
106920 #define ALT_USB_DEV_DOEPCTL1_CNAK_E_ACT 0x1
106921 
106922 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */
106923 #define ALT_USB_DEV_DOEPCTL1_CNAK_LSB 26
106924 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */
106925 #define ALT_USB_DEV_DOEPCTL1_CNAK_MSB 26
106926 /* The width in bits of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */
106927 #define ALT_USB_DEV_DOEPCTL1_CNAK_WIDTH 1
106928 /* The mask used to set the ALT_USB_DEV_DOEPCTL1_CNAK register field value. */
106929 #define ALT_USB_DEV_DOEPCTL1_CNAK_SET_MSK 0x04000000
106930 /* The mask used to clear the ALT_USB_DEV_DOEPCTL1_CNAK register field value. */
106931 #define ALT_USB_DEV_DOEPCTL1_CNAK_CLR_MSK 0xfbffffff
106932 /* The reset value of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */
106933 #define ALT_USB_DEV_DOEPCTL1_CNAK_RESET 0x0
106934 /* Extracts the ALT_USB_DEV_DOEPCTL1_CNAK field value from a register. */
106935 #define ALT_USB_DEV_DOEPCTL1_CNAK_GET(value) (((value) & 0x04000000) >> 26)
106936 /* Produces a ALT_USB_DEV_DOEPCTL1_CNAK register field value suitable for setting the register. */
106937 #define ALT_USB_DEV_DOEPCTL1_CNAK_SET(value) (((value) << 26) & 0x04000000)
106938 
106939 /*
106940  * Field : snak
106941  *
106942  * Set NAK (SNAK)
106943  *
106944  * A write to this bit sets the NAK bit For the endpoint.
106945  *
106946  * Using this bit, the application can control the transmission of NAK
106947  *
106948  * handshakes on an endpoint. The core can also Set this bit For an
106949  *
106950  * endpoint after a SETUP packet is received on that endpoint.
106951  *
106952  * Field Enumeration Values:
106953  *
106954  * Enum | Value | Description
106955  * :----------------------------------|:------|:------------
106956  * ALT_USB_DEV_DOEPCTL1_SNAK_E_INACT | 0x0 | No Set NAK
106957  * ALT_USB_DEV_DOEPCTL1_SNAK_E_ACT | 0x1 | Set NAK
106958  *
106959  * Field Access Macros:
106960  *
106961  */
106962 /*
106963  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNAK
106964  *
106965  * No Set NAK
106966  */
106967 #define ALT_USB_DEV_DOEPCTL1_SNAK_E_INACT 0x0
106968 /*
106969  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNAK
106970  *
106971  * Set NAK
106972  */
106973 #define ALT_USB_DEV_DOEPCTL1_SNAK_E_ACT 0x1
106974 
106975 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */
106976 #define ALT_USB_DEV_DOEPCTL1_SNAK_LSB 27
106977 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */
106978 #define ALT_USB_DEV_DOEPCTL1_SNAK_MSB 27
106979 /* The width in bits of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */
106980 #define ALT_USB_DEV_DOEPCTL1_SNAK_WIDTH 1
106981 /* The mask used to set the ALT_USB_DEV_DOEPCTL1_SNAK register field value. */
106982 #define ALT_USB_DEV_DOEPCTL1_SNAK_SET_MSK 0x08000000
106983 /* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SNAK register field value. */
106984 #define ALT_USB_DEV_DOEPCTL1_SNAK_CLR_MSK 0xf7ffffff
106985 /* The reset value of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */
106986 #define ALT_USB_DEV_DOEPCTL1_SNAK_RESET 0x0
106987 /* Extracts the ALT_USB_DEV_DOEPCTL1_SNAK field value from a register. */
106988 #define ALT_USB_DEV_DOEPCTL1_SNAK_GET(value) (((value) & 0x08000000) >> 27)
106989 /* Produces a ALT_USB_DEV_DOEPCTL1_SNAK register field value suitable for setting the register. */
106990 #define ALT_USB_DEV_DOEPCTL1_SNAK_SET(value) (((value) << 27) & 0x08000000)
106991 
106992 /*
106993  * Field : setd0pid
106994  *
106995  * Set DATA0 PID (SetD0PID)
106996  *
106997  * Applies to interrupt/bulk IN and OUT endpoints only.
106998  *
106999  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
107000  * to DATA0.
107001  *
107002  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
107003  *
107004  * DMA mode.
107005  *
107006  * 1'b0 WO
107007  *
107008  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
107009  *
107010  * Applies to isochronous IN and OUT endpoints only.
107011  *
107012  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
107013  * (micro)
107014  *
107015  * frame.
107016  *
107017  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
107018  * number
107019  *
107020  * in which to send data is in the transmit descriptor structure. The frame in
107021  * which to
107022  *
107023  * receive data is updated in receive descriptor structure.
107024  *
107025  * Field Enumeration Values:
107026  *
107027  * Enum | Value | Description
107028  * :-------------------------------------|:------|:------------------------------------
107029  * ALT_USB_DEV_DOEPCTL1_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
107030  * ALT_USB_DEV_DOEPCTL1_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
107031  *
107032  * Field Access Macros:
107033  *
107034  */
107035 /*
107036  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD0PID
107037  *
107038  * Disables Set DATA0 PID
107039  */
107040 #define ALT_USB_DEV_DOEPCTL1_SETD0PID_E_DISD 0x0
107041 /*
107042  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD0PID
107043  *
107044  * Enables Endpoint Data PID to DATA0)
107045  */
107046 #define ALT_USB_DEV_DOEPCTL1_SETD0PID_E_END 0x1
107047 
107048 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */
107049 #define ALT_USB_DEV_DOEPCTL1_SETD0PID_LSB 28
107050 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */
107051 #define ALT_USB_DEV_DOEPCTL1_SETD0PID_MSB 28
107052 /* The width in bits of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */
107053 #define ALT_USB_DEV_DOEPCTL1_SETD0PID_WIDTH 1
107054 /* The mask used to set the ALT_USB_DEV_DOEPCTL1_SETD0PID register field value. */
107055 #define ALT_USB_DEV_DOEPCTL1_SETD0PID_SET_MSK 0x10000000
107056 /* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SETD0PID register field value. */
107057 #define ALT_USB_DEV_DOEPCTL1_SETD0PID_CLR_MSK 0xefffffff
107058 /* The reset value of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */
107059 #define ALT_USB_DEV_DOEPCTL1_SETD0PID_RESET 0x0
107060 /* Extracts the ALT_USB_DEV_DOEPCTL1_SETD0PID field value from a register. */
107061 #define ALT_USB_DEV_DOEPCTL1_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
107062 /* Produces a ALT_USB_DEV_DOEPCTL1_SETD0PID register field value suitable for setting the register. */
107063 #define ALT_USB_DEV_DOEPCTL1_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
107064 
107065 /*
107066  * Field : setd1pid
107067  *
107068  * Set DATA1 PID (SetD1PID)
107069  *
107070  * Applies to interrupt/bulk IN and OUT endpoints only.
107071  *
107072  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
107073  * to DATA1.
107074  *
107075  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
107076  *
107077  * DMA mode.
107078  *
107079  * Set Odd (micro)frame (SetOddFr)
107080  *
107081  * Applies to isochronous IN and OUT endpoints only.
107082  *
107083  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
107084  *
107085  * (micro)frame.
107086  *
107087  * This field is not applicable for Scatter/Gather DMA mode.
107088  *
107089  * Field Enumeration Values:
107090  *
107091  * Enum | Value | Description
107092  * :-------------------------------------|:------|:-----------------------
107093  * ALT_USB_DEV_DOEPCTL1_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
107094  * ALT_USB_DEV_DOEPCTL1_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
107095  *
107096  * Field Access Macros:
107097  *
107098  */
107099 /*
107100  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD1PID
107101  *
107102  * Disables Set DATA1 PID
107103  */
107104 #define ALT_USB_DEV_DOEPCTL1_SETD1PID_E_DISD 0x0
107105 /*
107106  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD1PID
107107  *
107108  * Enables Set DATA1 PID
107109  */
107110 #define ALT_USB_DEV_DOEPCTL1_SETD1PID_E_END 0x1
107111 
107112 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */
107113 #define ALT_USB_DEV_DOEPCTL1_SETD1PID_LSB 29
107114 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */
107115 #define ALT_USB_DEV_DOEPCTL1_SETD1PID_MSB 29
107116 /* The width in bits of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */
107117 #define ALT_USB_DEV_DOEPCTL1_SETD1PID_WIDTH 1
107118 /* The mask used to set the ALT_USB_DEV_DOEPCTL1_SETD1PID register field value. */
107119 #define ALT_USB_DEV_DOEPCTL1_SETD1PID_SET_MSK 0x20000000
107120 /* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SETD1PID register field value. */
107121 #define ALT_USB_DEV_DOEPCTL1_SETD1PID_CLR_MSK 0xdfffffff
107122 /* The reset value of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */
107123 #define ALT_USB_DEV_DOEPCTL1_SETD1PID_RESET 0x0
107124 /* Extracts the ALT_USB_DEV_DOEPCTL1_SETD1PID field value from a register. */
107125 #define ALT_USB_DEV_DOEPCTL1_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
107126 /* Produces a ALT_USB_DEV_DOEPCTL1_SETD1PID register field value suitable for setting the register. */
107127 #define ALT_USB_DEV_DOEPCTL1_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
107128 
107129 /*
107130  * Field : epdis
107131  *
107132  * Endpoint Disable (EPDis)
107133  *
107134  * Applies to IN and OUT endpoints.
107135  *
107136  * The application sets this bit to stop transmitting/receiving data on an
107137  * endpoint, even
107138  *
107139  * before the transfer for that endpoint is complete. The application must wait for
107140  * the
107141  *
107142  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
107143  * clears
107144  *
107145  * this bit before setting the Endpoint Disabled interrupt. The application must
107146  * set this bit
107147  *
107148  * only if Endpoint Enable is already set for this endpoint.
107149  *
107150  * Field Enumeration Values:
107151  *
107152  * Enum | Value | Description
107153  * :-----------------------------------|:------|:--------------------
107154  * ALT_USB_DEV_DOEPCTL1_EPDIS_E_INACT | 0x0 | No Endpoint Disable
107155  * ALT_USB_DEV_DOEPCTL1_EPDIS_E_ACT | 0x1 | Endpoint Disable
107156  *
107157  * Field Access Macros:
107158  *
107159  */
107160 /*
107161  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPDIS
107162  *
107163  * No Endpoint Disable
107164  */
107165 #define ALT_USB_DEV_DOEPCTL1_EPDIS_E_INACT 0x0
107166 /*
107167  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPDIS
107168  *
107169  * Endpoint Disable
107170  */
107171 #define ALT_USB_DEV_DOEPCTL1_EPDIS_E_ACT 0x1
107172 
107173 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */
107174 #define ALT_USB_DEV_DOEPCTL1_EPDIS_LSB 30
107175 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */
107176 #define ALT_USB_DEV_DOEPCTL1_EPDIS_MSB 30
107177 /* The width in bits of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */
107178 #define ALT_USB_DEV_DOEPCTL1_EPDIS_WIDTH 1
107179 /* The mask used to set the ALT_USB_DEV_DOEPCTL1_EPDIS register field value. */
107180 #define ALT_USB_DEV_DOEPCTL1_EPDIS_SET_MSK 0x40000000
107181 /* The mask used to clear the ALT_USB_DEV_DOEPCTL1_EPDIS register field value. */
107182 #define ALT_USB_DEV_DOEPCTL1_EPDIS_CLR_MSK 0xbfffffff
107183 /* The reset value of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */
107184 #define ALT_USB_DEV_DOEPCTL1_EPDIS_RESET 0x0
107185 /* Extracts the ALT_USB_DEV_DOEPCTL1_EPDIS field value from a register. */
107186 #define ALT_USB_DEV_DOEPCTL1_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
107187 /* Produces a ALT_USB_DEV_DOEPCTL1_EPDIS register field value suitable for setting the register. */
107188 #define ALT_USB_DEV_DOEPCTL1_EPDIS_SET(value) (((value) << 30) & 0x40000000)
107189 
107190 /*
107191  * Field : epena
107192  *
107193  * Endpoint Enable (EPEna)
107194  *
107195  * Applies to IN and OUT endpoints.
107196  *
107197  * When Scatter/Gather DMA mode is enabled,
107198  *
107199  * For IN endpoints this bit indicates that the descriptor structure and data
107200  * buffer with
107201  *
107202  * data ready to transmit is setup.
107203  *
107204  * For OUT endpoint it indicates that the descriptor structure and data buffer to
107205  *
107206  * receive data is setup.
107207  *
107208  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
107209  *
107210  * DMA mode:
107211  *
107212  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
107213  * the
107214  *
107215  * endpoint.
107216  *
107217  * * For OUT endpoints, this bit indicates that the application has allocated the
107218  *
107219  * memory to start receiving data from the USB.
107220  *
107221  * * The core clears this bit before setting any of the following interrupts on
107222  * this
107223  *
107224  * endpoint:
107225  *
107226  * SETUP Phase Done
107227  *
107228  * Endpoint Disabled
107229  *
107230  * Transfer Completed
107231  *
107232  * Note: For control endpoints in DMA mode, this bit must be set to be able to
107233  * transfer
107234  *
107235  * SETUP data packets in memory.
107236  *
107237  * Field Enumeration Values:
107238  *
107239  * Enum | Value | Description
107240  * :-----------------------------------|:------|:-------------------------
107241  * ALT_USB_DEV_DOEPCTL1_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
107242  * ALT_USB_DEV_DOEPCTL1_EPENA_E_ACT | 0x1 | Endpoint Enable active
107243  *
107244  * Field Access Macros:
107245  *
107246  */
107247 /*
107248  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPENA
107249  *
107250  * Endpoint Enable inactive
107251  */
107252 #define ALT_USB_DEV_DOEPCTL1_EPENA_E_INACT 0x0
107253 /*
107254  * Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPENA
107255  *
107256  * Endpoint Enable active
107257  */
107258 #define ALT_USB_DEV_DOEPCTL1_EPENA_E_ACT 0x1
107259 
107260 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */
107261 #define ALT_USB_DEV_DOEPCTL1_EPENA_LSB 31
107262 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */
107263 #define ALT_USB_DEV_DOEPCTL1_EPENA_MSB 31
107264 /* The width in bits of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */
107265 #define ALT_USB_DEV_DOEPCTL1_EPENA_WIDTH 1
107266 /* The mask used to set the ALT_USB_DEV_DOEPCTL1_EPENA register field value. */
107267 #define ALT_USB_DEV_DOEPCTL1_EPENA_SET_MSK 0x80000000
107268 /* The mask used to clear the ALT_USB_DEV_DOEPCTL1_EPENA register field value. */
107269 #define ALT_USB_DEV_DOEPCTL1_EPENA_CLR_MSK 0x7fffffff
107270 /* The reset value of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */
107271 #define ALT_USB_DEV_DOEPCTL1_EPENA_RESET 0x0
107272 /* Extracts the ALT_USB_DEV_DOEPCTL1_EPENA field value from a register. */
107273 #define ALT_USB_DEV_DOEPCTL1_EPENA_GET(value) (((value) & 0x80000000) >> 31)
107274 /* Produces a ALT_USB_DEV_DOEPCTL1_EPENA register field value suitable for setting the register. */
107275 #define ALT_USB_DEV_DOEPCTL1_EPENA_SET(value) (((value) << 31) & 0x80000000)
107276 
107277 #ifndef __ASSEMBLY__
107278 /*
107279  * WARNING: The C register and register group struct declarations are provided for
107280  * convenience and illustrative purposes. They should, however, be used with
107281  * caution as the C language standard provides no guarantees about the alignment or
107282  * atomicity of device memory accesses. The recommended practice for writing
107283  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
107284  * alt_write_word() functions.
107285  *
107286  * The struct declaration for register ALT_USB_DEV_DOEPCTL1.
107287  */
107288 struct ALT_USB_DEV_DOEPCTL1_s
107289 {
107290  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL1_MPS */
107291  uint32_t : 4; /* *UNDEFINED* */
107292  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL1_USBACTEP */
107293  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL1_DPID */
107294  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL1_NAKSTS */
107295  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL1_EPTYPE */
107296  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL1_SNP */
107297  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL1_STALL */
107298  uint32_t : 4; /* *UNDEFINED* */
107299  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL1_CNAK */
107300  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL1_SNAK */
107301  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL1_SETD0PID */
107302  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL1_SETD1PID */
107303  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL1_EPDIS */
107304  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL1_EPENA */
107305 };
107306 
107307 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL1. */
107308 typedef volatile struct ALT_USB_DEV_DOEPCTL1_s ALT_USB_DEV_DOEPCTL1_t;
107309 #endif /* __ASSEMBLY__ */
107310 
107311 /* The reset value of the ALT_USB_DEV_DOEPCTL1 register. */
107312 #define ALT_USB_DEV_DOEPCTL1_RESET 0x00000000
107313 /* The byte offset of the ALT_USB_DEV_DOEPCTL1 register from the beginning of the component. */
107314 #define ALT_USB_DEV_DOEPCTL1_OFST 0x320
107315 /* The address of the ALT_USB_DEV_DOEPCTL1 register. */
107316 #define ALT_USB_DEV_DOEPCTL1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL1_OFST))
107317 
107318 /*
107319  * Register : doepint1
107320  *
107321  * Device OUT Endpoint 1 Interrupt Register
107322  *
107323  * Register Layout
107324  *
107325  * Bits | Access | Reset | Description
107326  * :--------|:-------|:------|:------------------------------------
107327  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_XFERCOMPL
107328  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_EPDISBLD
107329  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_AHBERR
107330  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_SETUP
107331  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS
107332  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_STSPHSERCVD
107333  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP
107334  * [7] | ??? | 0x0 | *UNDEFINED*
107335  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_OUTPKTERR
107336  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_BNAINTR
107337  * [10] | ??? | 0x0 | *UNDEFINED*
107338  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_PKTDRPSTS
107339  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_BBLEERR
107340  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_NAKINTRPT
107341  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_NYETINTRPT
107342  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_STUPPKTRCVD
107343  * [31:16] | ??? | 0x0 | *UNDEFINED*
107344  *
107345  */
107346 /*
107347  * Field : xfercompl
107348  *
107349  * Transfer Completed Interrupt (XferCompl)
107350  *
107351  * Applies to IN and OUT endpoints.
107352  *
107353  * When Scatter/Gather DMA mode is enabled
107354  *
107355  * * For IN endpoint this field indicates that the requested data
107356  *
107357  * from the descriptor is moved from external system memory
107358  *
107359  * to internal FIFO.
107360  *
107361  * * For OUT endpoint this field indicates that the requested
107362  *
107363  * data from the internal FIFO is moved to external system
107364  *
107365  * memory. This interrupt is generated only when the
107366  *
107367  * corresponding endpoint descriptor is closed, and the IOC
107368  *
107369  * bit For the corresponding descriptor is Set.
107370  *
107371  * When Scatter/Gather DMA mode is disabled, this field
107372  *
107373  * indicates that the programmed transfer is complete on the
107374  *
107375  * AHB as well as on the USB, For this endpoint.
107376  *
107377  * Field Enumeration Values:
107378  *
107379  * Enum | Value | Description
107380  * :---------------------------------------|:------|:-----------------------------
107381  * ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_INACT | 0x0 | No Interrupt
107382  * ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
107383  *
107384  * Field Access Macros:
107385  *
107386  */
107387 /*
107388  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_XFERCOMPL
107389  *
107390  * No Interrupt
107391  */
107392 #define ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_INACT 0x0
107393 /*
107394  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_XFERCOMPL
107395  *
107396  * Transfer Completed Interrupt
107397  */
107398 #define ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_ACT 0x1
107399 
107400 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */
107401 #define ALT_USB_DEV_DOEPINT1_XFERCOMPL_LSB 0
107402 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */
107403 #define ALT_USB_DEV_DOEPINT1_XFERCOMPL_MSB 0
107404 /* The width in bits of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */
107405 #define ALT_USB_DEV_DOEPINT1_XFERCOMPL_WIDTH 1
107406 /* The mask used to set the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field value. */
107407 #define ALT_USB_DEV_DOEPINT1_XFERCOMPL_SET_MSK 0x00000001
107408 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field value. */
107409 #define ALT_USB_DEV_DOEPINT1_XFERCOMPL_CLR_MSK 0xfffffffe
107410 /* The reset value of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */
107411 #define ALT_USB_DEV_DOEPINT1_XFERCOMPL_RESET 0x0
107412 /* Extracts the ALT_USB_DEV_DOEPINT1_XFERCOMPL field value from a register. */
107413 #define ALT_USB_DEV_DOEPINT1_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
107414 /* Produces a ALT_USB_DEV_DOEPINT1_XFERCOMPL register field value suitable for setting the register. */
107415 #define ALT_USB_DEV_DOEPINT1_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
107416 
107417 /*
107418  * Field : epdisbld
107419  *
107420  * Endpoint Disabled Interrupt (EPDisbld)
107421  *
107422  * Applies to IN and OUT endpoints.
107423  *
107424  * This bit indicates that the endpoint is disabled per the
107425  *
107426  * application's request.
107427  *
107428  * Field Enumeration Values:
107429  *
107430  * Enum | Value | Description
107431  * :--------------------------------------|:------|:----------------------------
107432  * ALT_USB_DEV_DOEPINT1_EPDISBLD_E_INACT | 0x0 | No Interrupt
107433  * ALT_USB_DEV_DOEPINT1_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
107434  *
107435  * Field Access Macros:
107436  *
107437  */
107438 /*
107439  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_EPDISBLD
107440  *
107441  * No Interrupt
107442  */
107443 #define ALT_USB_DEV_DOEPINT1_EPDISBLD_E_INACT 0x0
107444 /*
107445  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_EPDISBLD
107446  *
107447  * Endpoint Disabled Interrupt
107448  */
107449 #define ALT_USB_DEV_DOEPINT1_EPDISBLD_E_ACT 0x1
107450 
107451 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */
107452 #define ALT_USB_DEV_DOEPINT1_EPDISBLD_LSB 1
107453 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */
107454 #define ALT_USB_DEV_DOEPINT1_EPDISBLD_MSB 1
107455 /* The width in bits of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */
107456 #define ALT_USB_DEV_DOEPINT1_EPDISBLD_WIDTH 1
107457 /* The mask used to set the ALT_USB_DEV_DOEPINT1_EPDISBLD register field value. */
107458 #define ALT_USB_DEV_DOEPINT1_EPDISBLD_SET_MSK 0x00000002
107459 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_EPDISBLD register field value. */
107460 #define ALT_USB_DEV_DOEPINT1_EPDISBLD_CLR_MSK 0xfffffffd
107461 /* The reset value of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */
107462 #define ALT_USB_DEV_DOEPINT1_EPDISBLD_RESET 0x0
107463 /* Extracts the ALT_USB_DEV_DOEPINT1_EPDISBLD field value from a register. */
107464 #define ALT_USB_DEV_DOEPINT1_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
107465 /* Produces a ALT_USB_DEV_DOEPINT1_EPDISBLD register field value suitable for setting the register. */
107466 #define ALT_USB_DEV_DOEPINT1_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
107467 
107468 /*
107469  * Field : ahberr
107470  *
107471  * AHB Error (AHBErr)
107472  *
107473  * Applies to IN and OUT endpoints.
107474  *
107475  * This is generated only in Internal DMA mode when there is an
107476  *
107477  * AHB error during an AHB read/write. The application can read
107478  *
107479  * the corresponding endpoint DMA address register to get the
107480  *
107481  * error address.
107482  *
107483  * Field Enumeration Values:
107484  *
107485  * Enum | Value | Description
107486  * :------------------------------------|:------|:--------------------
107487  * ALT_USB_DEV_DOEPINT1_AHBERR_E_INACT | 0x0 | No Interrupt
107488  * ALT_USB_DEV_DOEPINT1_AHBERR_E_ACT | 0x1 | AHB Error interrupt
107489  *
107490  * Field Access Macros:
107491  *
107492  */
107493 /*
107494  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_AHBERR
107495  *
107496  * No Interrupt
107497  */
107498 #define ALT_USB_DEV_DOEPINT1_AHBERR_E_INACT 0x0
107499 /*
107500  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_AHBERR
107501  *
107502  * AHB Error interrupt
107503  */
107504 #define ALT_USB_DEV_DOEPINT1_AHBERR_E_ACT 0x1
107505 
107506 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */
107507 #define ALT_USB_DEV_DOEPINT1_AHBERR_LSB 2
107508 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */
107509 #define ALT_USB_DEV_DOEPINT1_AHBERR_MSB 2
107510 /* The width in bits of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */
107511 #define ALT_USB_DEV_DOEPINT1_AHBERR_WIDTH 1
107512 /* The mask used to set the ALT_USB_DEV_DOEPINT1_AHBERR register field value. */
107513 #define ALT_USB_DEV_DOEPINT1_AHBERR_SET_MSK 0x00000004
107514 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_AHBERR register field value. */
107515 #define ALT_USB_DEV_DOEPINT1_AHBERR_CLR_MSK 0xfffffffb
107516 /* The reset value of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */
107517 #define ALT_USB_DEV_DOEPINT1_AHBERR_RESET 0x0
107518 /* Extracts the ALT_USB_DEV_DOEPINT1_AHBERR field value from a register. */
107519 #define ALT_USB_DEV_DOEPINT1_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
107520 /* Produces a ALT_USB_DEV_DOEPINT1_AHBERR register field value suitable for setting the register. */
107521 #define ALT_USB_DEV_DOEPINT1_AHBERR_SET(value) (((value) << 2) & 0x00000004)
107522 
107523 /*
107524  * Field : setup
107525  *
107526  * SETUP Phase Done (SetUp)
107527  *
107528  * Applies to control OUT endpoints only.
107529  *
107530  * Indicates that the SETUP phase For the control endpoint is
107531  *
107532  * complete and no more back-to-back SETUP packets were
107533  *
107534  * received For the current control transfer. On this interrupt, the
107535  *
107536  * application can decode the received SETUP data packet.
107537  *
107538  * Field Enumeration Values:
107539  *
107540  * Enum | Value | Description
107541  * :-----------------------------------|:------|:--------------------
107542  * ALT_USB_DEV_DOEPINT1_SETUP_E_INACT | 0x0 | No SETUP Phase Done
107543  * ALT_USB_DEV_DOEPINT1_SETUP_E_ACT | 0x1 | SETUP Phase Done
107544  *
107545  * Field Access Macros:
107546  *
107547  */
107548 /*
107549  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_SETUP
107550  *
107551  * No SETUP Phase Done
107552  */
107553 #define ALT_USB_DEV_DOEPINT1_SETUP_E_INACT 0x0
107554 /*
107555  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_SETUP
107556  *
107557  * SETUP Phase Done
107558  */
107559 #define ALT_USB_DEV_DOEPINT1_SETUP_E_ACT 0x1
107560 
107561 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_SETUP register field. */
107562 #define ALT_USB_DEV_DOEPINT1_SETUP_LSB 3
107563 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_SETUP register field. */
107564 #define ALT_USB_DEV_DOEPINT1_SETUP_MSB 3
107565 /* The width in bits of the ALT_USB_DEV_DOEPINT1_SETUP register field. */
107566 #define ALT_USB_DEV_DOEPINT1_SETUP_WIDTH 1
107567 /* The mask used to set the ALT_USB_DEV_DOEPINT1_SETUP register field value. */
107568 #define ALT_USB_DEV_DOEPINT1_SETUP_SET_MSK 0x00000008
107569 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_SETUP register field value. */
107570 #define ALT_USB_DEV_DOEPINT1_SETUP_CLR_MSK 0xfffffff7
107571 /* The reset value of the ALT_USB_DEV_DOEPINT1_SETUP register field. */
107572 #define ALT_USB_DEV_DOEPINT1_SETUP_RESET 0x0
107573 /* Extracts the ALT_USB_DEV_DOEPINT1_SETUP field value from a register. */
107574 #define ALT_USB_DEV_DOEPINT1_SETUP_GET(value) (((value) & 0x00000008) >> 3)
107575 /* Produces a ALT_USB_DEV_DOEPINT1_SETUP register field value suitable for setting the register. */
107576 #define ALT_USB_DEV_DOEPINT1_SETUP_SET(value) (((value) << 3) & 0x00000008)
107577 
107578 /*
107579  * Field : outtknepdis
107580  *
107581  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
107582  *
107583  * Applies only to control OUT endpoints.
107584  *
107585  * Indicates that an OUT token was received when the endpoint
107586  *
107587  * was not yet enabled. This interrupt is asserted on the endpoint
107588  *
107589  * For which the OUT token was received.
107590  *
107591  * Field Enumeration Values:
107592  *
107593  * Enum | Value | Description
107594  * :-----------------------------------------|:------|:---------------------------------------------
107595  * ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
107596  * ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
107597  *
107598  * Field Access Macros:
107599  *
107600  */
107601 /*
107602  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS
107603  *
107604  * No OUT Token Received When Endpoint Disabled
107605  */
107606 #define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_INACT 0x0
107607 /*
107608  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS
107609  *
107610  * OUT Token Received When Endpoint Disabled
107611  */
107612 #define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_ACT 0x1
107613 
107614 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */
107615 #define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_LSB 4
107616 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */
107617 #define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_MSB 4
107618 /* The width in bits of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */
107619 #define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_WIDTH 1
107620 /* The mask used to set the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field value. */
107621 #define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_SET_MSK 0x00000010
107622 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field value. */
107623 #define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_CLR_MSK 0xffffffef
107624 /* The reset value of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */
107625 #define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_RESET 0x0
107626 /* Extracts the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS field value from a register. */
107627 #define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
107628 /* Produces a ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field value suitable for setting the register. */
107629 #define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
107630 
107631 /*
107632  * Field : stsphsercvd
107633  *
107634  * Status Phase Received For Control Write (StsPhseRcvd)
107635  *
107636  * This interrupt is valid only For Control OUT endpoints and only in
107637  *
107638  * Scatter Gather DMA mode.
107639  *
107640  * This interrupt is generated only after the core has transferred all
107641  *
107642  * the data that the host has sent during the data phase of a control
107643  *
107644  * write transfer, to the system memory buffer.
107645  *
107646  * The interrupt indicates to the application that the host has
107647  *
107648  * switched from data phase to the status phase of a Control Write
107649  *
107650  * transfer. The application can use this interrupt to ACK or STALL
107651  *
107652  * the Status phase, after it has decoded the data phase. This is
107653  *
107654  * applicable only in Case of Scatter Gather DMA mode.
107655  *
107656  * Field Enumeration Values:
107657  *
107658  * Enum | Value | Description
107659  * :-----------------------------------------|:------|:-------------------------------------------
107660  * ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
107661  * ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
107662  *
107663  * Field Access Macros:
107664  *
107665  */
107666 /*
107667  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_STSPHSERCVD
107668  *
107669  * No Status Phase Received for Control Write
107670  */
107671 #define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_INACT 0x0
107672 /*
107673  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_STSPHSERCVD
107674  *
107675  * Status Phase Received for Control Write
107676  */
107677 #define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_ACT 0x1
107678 
107679 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */
107680 #define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_LSB 5
107681 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */
107682 #define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_MSB 5
107683 /* The width in bits of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */
107684 #define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_WIDTH 1
107685 /* The mask used to set the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field value. */
107686 #define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_SET_MSK 0x00000020
107687 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field value. */
107688 #define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_CLR_MSK 0xffffffdf
107689 /* The reset value of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */
107690 #define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_RESET 0x0
107691 /* Extracts the ALT_USB_DEV_DOEPINT1_STSPHSERCVD field value from a register. */
107692 #define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
107693 /* Produces a ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field value suitable for setting the register. */
107694 #define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
107695 
107696 /*
107697  * Field : back2backsetup
107698  *
107699  * Back-to-Back SETUP Packets Received (Back2BackSETup)
107700  *
107701  * Applies to Control OUT endpoints only.
107702  *
107703  * This bit indicates that the core has received more than three
107704  *
107705  * back-to-back SETUP packets For this particular endpoint. For
107706  *
107707  * information about handling this interrupt,
107708  *
107709  * Field Enumeration Values:
107710  *
107711  * Enum | Value | Description
107712  * :--------------------------------------------|:------|:---------------------------------------
107713  * ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
107714  * ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
107715  *
107716  * Field Access Macros:
107717  *
107718  */
107719 /*
107720  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP
107721  *
107722  * No Back-to-Back SETUP Packets Received
107723  */
107724 #define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_INACT 0x0
107725 /*
107726  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP
107727  *
107728  * Back-to-Back SETUP Packets Received
107729  */
107730 #define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_ACT 0x1
107731 
107732 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */
107733 #define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_LSB 6
107734 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */
107735 #define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_MSB 6
107736 /* The width in bits of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */
107737 #define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_WIDTH 1
107738 /* The mask used to set the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field value. */
107739 #define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_SET_MSK 0x00000040
107740 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field value. */
107741 #define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_CLR_MSK 0xffffffbf
107742 /* The reset value of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */
107743 #define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_RESET 0x0
107744 /* Extracts the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP field value from a register. */
107745 #define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
107746 /* Produces a ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field value suitable for setting the register. */
107747 #define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
107748 
107749 /*
107750  * Field : outpkterr
107751  *
107752  * OUT Packet Error (OutPktErr)
107753  *
107754  * Applies to OUT endpoints Only
107755  *
107756  * This interrupt is valid only when thresholding is enabled. This interrupt is
107757  * asserted when the
107758  *
107759  * core detects an overflow or a CRC error For non-Isochronous
107760  *
107761  * OUT packet.
107762  *
107763  * Field Enumeration Values:
107764  *
107765  * Enum | Value | Description
107766  * :---------------------------------------|:------|:--------------------
107767  * ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
107768  * ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
107769  *
107770  * Field Access Macros:
107771  *
107772  */
107773 /*
107774  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTPKTERR
107775  *
107776  * No OUT Packet Error
107777  */
107778 #define ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_INACT 0x0
107779 /*
107780  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTPKTERR
107781  *
107782  * OUT Packet Error
107783  */
107784 #define ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_ACT 0x1
107785 
107786 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */
107787 #define ALT_USB_DEV_DOEPINT1_OUTPKTERR_LSB 8
107788 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */
107789 #define ALT_USB_DEV_DOEPINT1_OUTPKTERR_MSB 8
107790 /* The width in bits of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */
107791 #define ALT_USB_DEV_DOEPINT1_OUTPKTERR_WIDTH 1
107792 /* The mask used to set the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field value. */
107793 #define ALT_USB_DEV_DOEPINT1_OUTPKTERR_SET_MSK 0x00000100
107794 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field value. */
107795 #define ALT_USB_DEV_DOEPINT1_OUTPKTERR_CLR_MSK 0xfffffeff
107796 /* The reset value of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */
107797 #define ALT_USB_DEV_DOEPINT1_OUTPKTERR_RESET 0x0
107798 /* Extracts the ALT_USB_DEV_DOEPINT1_OUTPKTERR field value from a register. */
107799 #define ALT_USB_DEV_DOEPINT1_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
107800 /* Produces a ALT_USB_DEV_DOEPINT1_OUTPKTERR register field value suitable for setting the register. */
107801 #define ALT_USB_DEV_DOEPINT1_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
107802 
107803 /*
107804  * Field : bnaintr
107805  *
107806  * BNA (Buffer Not Available) Interrupt (BNAIntr)
107807  *
107808  * This bit is valid only when Scatter/Gather DMA mode is enabled.
107809  *
107810  * The core generates this interrupt when the descriptor accessed
107811  *
107812  * is not ready For the Core to process, such as Host busy or DMA
107813  *
107814  * done
107815  *
107816  * Field Enumeration Values:
107817  *
107818  * Enum | Value | Description
107819  * :-------------------------------------|:------|:--------------
107820  * ALT_USB_DEV_DOEPINT1_BNAINTR_E_INACT | 0x0 | No interrupt
107821  * ALT_USB_DEV_DOEPINT1_BNAINTR_E_ACT | 0x1 | BNA interrupt
107822  *
107823  * Field Access Macros:
107824  *
107825  */
107826 /*
107827  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BNAINTR
107828  *
107829  * No interrupt
107830  */
107831 #define ALT_USB_DEV_DOEPINT1_BNAINTR_E_INACT 0x0
107832 /*
107833  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BNAINTR
107834  *
107835  * BNA interrupt
107836  */
107837 #define ALT_USB_DEV_DOEPINT1_BNAINTR_E_ACT 0x1
107838 
107839 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */
107840 #define ALT_USB_DEV_DOEPINT1_BNAINTR_LSB 9
107841 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */
107842 #define ALT_USB_DEV_DOEPINT1_BNAINTR_MSB 9
107843 /* The width in bits of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */
107844 #define ALT_USB_DEV_DOEPINT1_BNAINTR_WIDTH 1
107845 /* The mask used to set the ALT_USB_DEV_DOEPINT1_BNAINTR register field value. */
107846 #define ALT_USB_DEV_DOEPINT1_BNAINTR_SET_MSK 0x00000200
107847 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_BNAINTR register field value. */
107848 #define ALT_USB_DEV_DOEPINT1_BNAINTR_CLR_MSK 0xfffffdff
107849 /* The reset value of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */
107850 #define ALT_USB_DEV_DOEPINT1_BNAINTR_RESET 0x0
107851 /* Extracts the ALT_USB_DEV_DOEPINT1_BNAINTR field value from a register. */
107852 #define ALT_USB_DEV_DOEPINT1_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
107853 /* Produces a ALT_USB_DEV_DOEPINT1_BNAINTR register field value suitable for setting the register. */
107854 #define ALT_USB_DEV_DOEPINT1_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
107855 
107856 /*
107857  * Field : pktdrpsts
107858  *
107859  * Packet Drop Status (PktDrpSts)
107860  *
107861  * This bit indicates to the application that an ISOC OUT packet has been dropped.
107862  * This
107863  *
107864  * bit does not have an associated mask bit and does not generate an interrupt.
107865  *
107866  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
107867  * transfer
107868  *
107869  * interrupt feature is selected.
107870  *
107871  * Field Enumeration Values:
107872  *
107873  * Enum | Value | Description
107874  * :---------------------------------------|:------|:-----------------------------
107875  * ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_INACT | 0x0 | No interrupt
107876  * ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
107877  *
107878  * Field Access Macros:
107879  *
107880  */
107881 /*
107882  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_PKTDRPSTS
107883  *
107884  * No interrupt
107885  */
107886 #define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_INACT 0x0
107887 /*
107888  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_PKTDRPSTS
107889  *
107890  * Packet Drop Status interrupt
107891  */
107892 #define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_ACT 0x1
107893 
107894 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */
107895 #define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_LSB 11
107896 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */
107897 #define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_MSB 11
107898 /* The width in bits of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */
107899 #define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_WIDTH 1
107900 /* The mask used to set the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field value. */
107901 #define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_SET_MSK 0x00000800
107902 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field value. */
107903 #define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_CLR_MSK 0xfffff7ff
107904 /* The reset value of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */
107905 #define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_RESET 0x0
107906 /* Extracts the ALT_USB_DEV_DOEPINT1_PKTDRPSTS field value from a register. */
107907 #define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
107908 /* Produces a ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field value suitable for setting the register. */
107909 #define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
107910 
107911 /*
107912  * Field : bbleerr
107913  *
107914  * NAK Interrupt (BbleErr)
107915  *
107916  * The core generates this interrupt when babble is received for the endpoint.
107917  *
107918  * Field Enumeration Values:
107919  *
107920  * Enum | Value | Description
107921  * :-------------------------------------|:------|:------------------
107922  * ALT_USB_DEV_DOEPINT1_BBLEERR_E_INACT | 0x0 | No interrupt
107923  * ALT_USB_DEV_DOEPINT1_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
107924  *
107925  * Field Access Macros:
107926  *
107927  */
107928 /*
107929  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BBLEERR
107930  *
107931  * No interrupt
107932  */
107933 #define ALT_USB_DEV_DOEPINT1_BBLEERR_E_INACT 0x0
107934 /*
107935  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_BBLEERR
107936  *
107937  * BbleErr interrupt
107938  */
107939 #define ALT_USB_DEV_DOEPINT1_BBLEERR_E_ACT 0x1
107940 
107941 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */
107942 #define ALT_USB_DEV_DOEPINT1_BBLEERR_LSB 12
107943 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */
107944 #define ALT_USB_DEV_DOEPINT1_BBLEERR_MSB 12
107945 /* The width in bits of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */
107946 #define ALT_USB_DEV_DOEPINT1_BBLEERR_WIDTH 1
107947 /* The mask used to set the ALT_USB_DEV_DOEPINT1_BBLEERR register field value. */
107948 #define ALT_USB_DEV_DOEPINT1_BBLEERR_SET_MSK 0x00001000
107949 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_BBLEERR register field value. */
107950 #define ALT_USB_DEV_DOEPINT1_BBLEERR_CLR_MSK 0xffffefff
107951 /* The reset value of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */
107952 #define ALT_USB_DEV_DOEPINT1_BBLEERR_RESET 0x0
107953 /* Extracts the ALT_USB_DEV_DOEPINT1_BBLEERR field value from a register. */
107954 #define ALT_USB_DEV_DOEPINT1_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
107955 /* Produces a ALT_USB_DEV_DOEPINT1_BBLEERR register field value suitable for setting the register. */
107956 #define ALT_USB_DEV_DOEPINT1_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
107957 
107958 /*
107959  * Field : nakintrpt
107960  *
107961  * NAK Interrupt (NAKInterrupt)
107962  *
107963  * The core generates this interrupt when a NAK is transmitted or received by the
107964  * device.
107965  *
107966  * In case of isochronous IN endpoints the interrupt gets generated when a zero
107967  * length
107968  *
107969  * packet is transmitted due to un-availability of data in the TXFifo.
107970  *
107971  * Field Enumeration Values:
107972  *
107973  * Enum | Value | Description
107974  * :---------------------------------------|:------|:--------------
107975  * ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_INACT | 0x0 | No interrupt
107976  * ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
107977  *
107978  * Field Access Macros:
107979  *
107980  */
107981 /*
107982  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_NAKINTRPT
107983  *
107984  * No interrupt
107985  */
107986 #define ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_INACT 0x0
107987 /*
107988  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_NAKINTRPT
107989  *
107990  * NAK Interrupt
107991  */
107992 #define ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_ACT 0x1
107993 
107994 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */
107995 #define ALT_USB_DEV_DOEPINT1_NAKINTRPT_LSB 13
107996 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */
107997 #define ALT_USB_DEV_DOEPINT1_NAKINTRPT_MSB 13
107998 /* The width in bits of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */
107999 #define ALT_USB_DEV_DOEPINT1_NAKINTRPT_WIDTH 1
108000 /* The mask used to set the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field value. */
108001 #define ALT_USB_DEV_DOEPINT1_NAKINTRPT_SET_MSK 0x00002000
108002 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field value. */
108003 #define ALT_USB_DEV_DOEPINT1_NAKINTRPT_CLR_MSK 0xffffdfff
108004 /* The reset value of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */
108005 #define ALT_USB_DEV_DOEPINT1_NAKINTRPT_RESET 0x0
108006 /* Extracts the ALT_USB_DEV_DOEPINT1_NAKINTRPT field value from a register. */
108007 #define ALT_USB_DEV_DOEPINT1_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
108008 /* Produces a ALT_USB_DEV_DOEPINT1_NAKINTRPT register field value suitable for setting the register. */
108009 #define ALT_USB_DEV_DOEPINT1_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
108010 
108011 /*
108012  * Field : nyetintrpt
108013  *
108014  * NYET Interrupt (NYETIntrpt)
108015  *
108016  * The core generates this interrupt when a NYET response is transmitted for a non
108017  * isochronous OUT endpoint.
108018  *
108019  * Field Enumeration Values:
108020  *
108021  * Enum | Value | Description
108022  * :----------------------------------------|:------|:---------------
108023  * ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_INACT | 0x0 | No interrupt
108024  * ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
108025  *
108026  * Field Access Macros:
108027  *
108028  */
108029 /*
108030  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_NYETINTRPT
108031  *
108032  * No interrupt
108033  */
108034 #define ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_INACT 0x0
108035 /*
108036  * Enumerated value for register field ALT_USB_DEV_DOEPINT1_NYETINTRPT
108037  *
108038  * NYET Interrupt
108039  */
108040 #define ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_ACT 0x1
108041 
108042 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */
108043 #define ALT_USB_DEV_DOEPINT1_NYETINTRPT_LSB 14
108044 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */
108045 #define ALT_USB_DEV_DOEPINT1_NYETINTRPT_MSB 14
108046 /* The width in bits of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */
108047 #define ALT_USB_DEV_DOEPINT1_NYETINTRPT_WIDTH 1
108048 /* The mask used to set the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field value. */
108049 #define ALT_USB_DEV_DOEPINT1_NYETINTRPT_SET_MSK 0x00004000
108050 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field value. */
108051 #define ALT_USB_DEV_DOEPINT1_NYETINTRPT_CLR_MSK 0xffffbfff
108052 /* The reset value of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */
108053 #define ALT_USB_DEV_DOEPINT1_NYETINTRPT_RESET 0x0
108054 /* Extracts the ALT_USB_DEV_DOEPINT1_NYETINTRPT field value from a register. */
108055 #define ALT_USB_DEV_DOEPINT1_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
108056 /* Produces a ALT_USB_DEV_DOEPINT1_NYETINTRPT register field value suitable for setting the register. */
108057 #define ALT_USB_DEV_DOEPINT1_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
108058 
108059 /*
108060  * Field : stuppktrcvd
108061  *
108062  * Setup Packet Received
108063  *
108064  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
108065  *
108066  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
108067  *
108068  * setup data. There is only one Setup packet per buffer. On receiving a
108069  *
108070  * Setup packet, the DWC_otg core closes the buffer and disables the
108071  *
108072  * corresponding endpoint. The application has to re-enable the endpoint to
108073  *
108074  * receive any OUT data for the Control Transfer and reprogram the buffer
108075  *
108076  * start address.
108077  *
108078  * Note: Because of the above behavior, the DWC_otg core can receive any
108079  *
108080  * number of back to back setup packets and one buffer for every setup
108081  *
108082  * packet is used.
108083  *
108084  * 1'b0: No Setup packet received
108085  *
108086  * 1'b1: Setup packet received
108087  *
108088  * Reset: 1'b0
108089  *
108090  * Field Access Macros:
108091  *
108092  */
108093 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field. */
108094 #define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_LSB 15
108095 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field. */
108096 #define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_MSB 15
108097 /* The width in bits of the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field. */
108098 #define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_WIDTH 1
108099 /* The mask used to set the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field value. */
108100 #define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_SET_MSK 0x00008000
108101 /* The mask used to clear the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field value. */
108102 #define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_CLR_MSK 0xffff7fff
108103 /* The reset value of the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field. */
108104 #define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_RESET 0x0
108105 /* Extracts the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD field value from a register. */
108106 #define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
108107 /* Produces a ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field value suitable for setting the register. */
108108 #define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
108109 
108110 #ifndef __ASSEMBLY__
108111 /*
108112  * WARNING: The C register and register group struct declarations are provided for
108113  * convenience and illustrative purposes. They should, however, be used with
108114  * caution as the C language standard provides no guarantees about the alignment or
108115  * atomicity of device memory accesses. The recommended practice for writing
108116  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
108117  * alt_write_word() functions.
108118  *
108119  * The struct declaration for register ALT_USB_DEV_DOEPINT1.
108120  */
108121 struct ALT_USB_DEV_DOEPINT1_s
108122 {
108123  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT1_XFERCOMPL */
108124  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT1_EPDISBLD */
108125  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT1_AHBERR */
108126  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT1_SETUP */
108127  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS */
108128  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT1_STSPHSERCVD */
108129  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP */
108130  uint32_t : 1; /* *UNDEFINED* */
108131  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT1_OUTPKTERR */
108132  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT1_BNAINTR */
108133  uint32_t : 1; /* *UNDEFINED* */
108134  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT1_PKTDRPSTS */
108135  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT1_BBLEERR */
108136  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT1_NAKINTRPT */
108137  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT1_NYETINTRPT */
108138  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT1_STUPPKTRCVD */
108139  uint32_t : 16; /* *UNDEFINED* */
108140 };
108141 
108142 /* The typedef declaration for register ALT_USB_DEV_DOEPINT1. */
108143 typedef volatile struct ALT_USB_DEV_DOEPINT1_s ALT_USB_DEV_DOEPINT1_t;
108144 #endif /* __ASSEMBLY__ */
108145 
108146 /* The reset value of the ALT_USB_DEV_DOEPINT1 register. */
108147 #define ALT_USB_DEV_DOEPINT1_RESET 0x00000000
108148 /* The byte offset of the ALT_USB_DEV_DOEPINT1 register from the beginning of the component. */
108149 #define ALT_USB_DEV_DOEPINT1_OFST 0x328
108150 /* The address of the ALT_USB_DEV_DOEPINT1 register. */
108151 #define ALT_USB_DEV_DOEPINT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT1_OFST))
108152 
108153 /*
108154  * Register : doeptsiz1
108155  *
108156  * Device OUT Endpoint 1 Transfer Size Register
108157  *
108158  * Register Layout
108159  *
108160  * Bits | Access | Reset | Description
108161  * :--------|:-------|:------|:-------------------------------
108162  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ1_XFERSIZE
108163  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ1_PKTCNT
108164  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ1_RXDPID
108165  * [31] | ??? | 0x0 | *UNDEFINED*
108166  *
108167  */
108168 /*
108169  * Field : xfersize
108170  *
108171  * Transfer Size (XferSize)
108172  *
108173  * Indicates the transfer size in bytes For endpoint 0. The core
108174  *
108175  * interrupts the application only after it has exhausted the transfer
108176  *
108177  * size amount of data. The transfer size can be Set to the
108178  *
108179  * maximum packet size of the endpoint, to be interrupted at the
108180  *
108181  * end of each packet.
108182  *
108183  * The core decrements this field every time a packet is read from
108184  *
108185  * the RxFIFO and written to the external memory.
108186  *
108187  * Field Access Macros:
108188  *
108189  */
108190 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */
108191 #define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_LSB 0
108192 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */
108193 #define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_MSB 18
108194 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */
108195 #define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_WIDTH 19
108196 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field value. */
108197 #define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_SET_MSK 0x0007ffff
108198 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field value. */
108199 #define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_CLR_MSK 0xfff80000
108200 /* The reset value of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */
108201 #define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_RESET 0x0
108202 /* Extracts the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE field value from a register. */
108203 #define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
108204 /* Produces a ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field value suitable for setting the register. */
108205 #define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
108206 
108207 /*
108208  * Field : pktcnt
108209  *
108210  * Packet Count (PktCnt)
108211  *
108212  * This field is decremented to zero after a packet is written into the
108213  *
108214  * RxFIFO.
108215  *
108216  * Field Access Macros:
108217  *
108218  */
108219 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */
108220 #define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_LSB 19
108221 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */
108222 #define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_MSB 28
108223 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */
108224 #define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_WIDTH 10
108225 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field value. */
108226 #define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_SET_MSK 0x1ff80000
108227 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field value. */
108228 #define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_CLR_MSK 0xe007ffff
108229 /* The reset value of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */
108230 #define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_RESET 0x0
108231 /* Extracts the ALT_USB_DEV_DOEPTSIZ1_PKTCNT field value from a register. */
108232 #define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
108233 /* Produces a ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field value suitable for setting the register. */
108234 #define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
108235 
108236 /*
108237  * Field : rxdpid
108238  *
108239  * Applies to isochronous OUT endpoints only.
108240  *
108241  * This is the data PID received in the last packet for this endpoint.
108242  *
108243  * 2'b00: DATA0
108244  *
108245  * 2'b01: DATA2
108246  *
108247  * 2'b10: DATA1
108248  *
108249  * 2'b11: MDATA
108250  *
108251  * SETUP Packet Count (SUPCnt)
108252  *
108253  * Applies to control OUT Endpoints only.
108254  *
108255  * This field specifies the number of back-to-back SETUP data
108256  *
108257  * packets the endpoint can receive.
108258  *
108259  * 2'b01: 1 packet
108260  *
108261  * 2'b10: 2 packets
108262  *
108263  * 2'b11: 3 packets
108264  *
108265  * Field Enumeration Values:
108266  *
108267  * Enum | Value | Description
108268  * :-----------------------------------------|:------|:-------------------
108269  * ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA0 | 0x0 | DATA0
108270  * ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
108271  * ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
108272  * ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
108273  *
108274  * Field Access Macros:
108275  *
108276  */
108277 /*
108278  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID
108279  *
108280  * DATA0
108281  */
108282 #define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA0 0x0
108283 /*
108284  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID
108285  *
108286  * DATA2 or 1 packet
108287  */
108288 #define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA2PKT1 0x1
108289 /*
108290  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID
108291  *
108292  * DATA1 or 2 packets
108293  */
108294 #define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA1PKT2 0x2
108295 /*
108296  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID
108297  *
108298  * MDATA or 3 packets
108299  */
108300 #define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_MDATAPKT3 0x3
108301 
108302 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */
108303 #define ALT_USB_DEV_DOEPTSIZ1_RXDPID_LSB 29
108304 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */
108305 #define ALT_USB_DEV_DOEPTSIZ1_RXDPID_MSB 30
108306 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */
108307 #define ALT_USB_DEV_DOEPTSIZ1_RXDPID_WIDTH 2
108308 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field value. */
108309 #define ALT_USB_DEV_DOEPTSIZ1_RXDPID_SET_MSK 0x60000000
108310 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field value. */
108311 #define ALT_USB_DEV_DOEPTSIZ1_RXDPID_CLR_MSK 0x9fffffff
108312 /* The reset value of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */
108313 #define ALT_USB_DEV_DOEPTSIZ1_RXDPID_RESET 0x0
108314 /* Extracts the ALT_USB_DEV_DOEPTSIZ1_RXDPID field value from a register. */
108315 #define ALT_USB_DEV_DOEPTSIZ1_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
108316 /* Produces a ALT_USB_DEV_DOEPTSIZ1_RXDPID register field value suitable for setting the register. */
108317 #define ALT_USB_DEV_DOEPTSIZ1_RXDPID_SET(value) (((value) << 29) & 0x60000000)
108318 
108319 #ifndef __ASSEMBLY__
108320 /*
108321  * WARNING: The C register and register group struct declarations are provided for
108322  * convenience and illustrative purposes. They should, however, be used with
108323  * caution as the C language standard provides no guarantees about the alignment or
108324  * atomicity of device memory accesses. The recommended practice for writing
108325  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
108326  * alt_write_word() functions.
108327  *
108328  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ1.
108329  */
108330 struct ALT_USB_DEV_DOEPTSIZ1_s
108331 {
108332  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ1_XFERSIZE */
108333  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ1_PKTCNT */
108334  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ1_RXDPID */
108335  uint32_t : 1; /* *UNDEFINED* */
108336 };
108337 
108338 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ1. */
108339 typedef volatile struct ALT_USB_DEV_DOEPTSIZ1_s ALT_USB_DEV_DOEPTSIZ1_t;
108340 #endif /* __ASSEMBLY__ */
108341 
108342 /* The reset value of the ALT_USB_DEV_DOEPTSIZ1 register. */
108343 #define ALT_USB_DEV_DOEPTSIZ1_RESET 0x00000000
108344 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ1 register from the beginning of the component. */
108345 #define ALT_USB_DEV_DOEPTSIZ1_OFST 0x330
108346 /* The address of the ALT_USB_DEV_DOEPTSIZ1 register. */
108347 #define ALT_USB_DEV_DOEPTSIZ1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ1_OFST))
108348 
108349 /*
108350  * Register : doepdma1
108351  *
108352  * Device OUT Endpoint 1 DMA Address Register
108353  *
108354  * Register Layout
108355  *
108356  * Bits | Access | Reset | Description
108357  * :-------|:-------|:--------|:------------------------------
108358  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA1_DOEPDMA1
108359  *
108360  */
108361 /*
108362  * Field : doepdma1
108363  *
108364  * Holds the start address of the external memory for storing or fetching endpoint
108365  *
108366  * data.
108367  *
108368  * Note: For control endpoints, this field stores control OUT data packets as well
108369  * as
108370  *
108371  * SETUP transaction data packets. When more than three SETUP packets are
108372  *
108373  * received back-to-back, the SETUP data packet in the memory is overwritten.
108374  *
108375  * This register is incremented on every AHB transaction. The application can give
108376  *
108377  * only a DWORD-aligned address.
108378  *
108379  * When Scatter/Gather DMA mode is not enabled, the application programs the
108380  *
108381  * start address value in this field.
108382  *
108383  * When Scatter/Gather DMA mode is enabled, this field indicates the base
108384  *
108385  * pointer for the descriptor list.
108386  *
108387  * Field Access Macros:
108388  *
108389  */
108390 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field. */
108391 #define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_LSB 0
108392 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field. */
108393 #define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_MSB 31
108394 /* The width in bits of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field. */
108395 #define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_WIDTH 32
108396 /* The mask used to set the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field value. */
108397 #define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_SET_MSK 0xffffffff
108398 /* The mask used to clear the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field value. */
108399 #define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_CLR_MSK 0x00000000
108400 /* The reset value of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field is UNKNOWN. */
108401 #define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_RESET 0x0
108402 /* Extracts the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 field value from a register. */
108403 #define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_GET(value) (((value) & 0xffffffff) >> 0)
108404 /* Produces a ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field value suitable for setting the register. */
108405 #define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_SET(value) (((value) << 0) & 0xffffffff)
108406 
108407 #ifndef __ASSEMBLY__
108408 /*
108409  * WARNING: The C register and register group struct declarations are provided for
108410  * convenience and illustrative purposes. They should, however, be used with
108411  * caution as the C language standard provides no guarantees about the alignment or
108412  * atomicity of device memory accesses. The recommended practice for writing
108413  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
108414  * alt_write_word() functions.
108415  *
108416  * The struct declaration for register ALT_USB_DEV_DOEPDMA1.
108417  */
108418 struct ALT_USB_DEV_DOEPDMA1_s
108419 {
108420  uint32_t doepdma1 : 32; /* ALT_USB_DEV_DOEPDMA1_DOEPDMA1 */
108421 };
108422 
108423 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA1. */
108424 typedef volatile struct ALT_USB_DEV_DOEPDMA1_s ALT_USB_DEV_DOEPDMA1_t;
108425 #endif /* __ASSEMBLY__ */
108426 
108427 /* The reset value of the ALT_USB_DEV_DOEPDMA1 register. */
108428 #define ALT_USB_DEV_DOEPDMA1_RESET 0x00000000
108429 /* The byte offset of the ALT_USB_DEV_DOEPDMA1 register from the beginning of the component. */
108430 #define ALT_USB_DEV_DOEPDMA1_OFST 0x334
108431 /* The address of the ALT_USB_DEV_DOEPDMA1 register. */
108432 #define ALT_USB_DEV_DOEPDMA1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA1_OFST))
108433 
108434 /*
108435  * Register : doepdmab1
108436  *
108437  * Device OUT Endpoint 1 Buffer Address Register
108438  *
108439  * Register Layout
108440  *
108441  * Bits | Access | Reset | Description
108442  * :-------|:-------|:--------|:--------------------------------
108443  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1
108444  *
108445  */
108446 /*
108447  * Field : doepdmab1
108448  *
108449  * Holds the current buffer address.This register is updated as and when the data
108450  *
108451  * transfer for the corresponding end point is in progress.
108452  *
108453  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
108454  * is
108455  *
108456  * reserved.
108457  *
108458  * Field Access Macros:
108459  *
108460  */
108461 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field. */
108462 #define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_LSB 0
108463 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field. */
108464 #define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_MSB 31
108465 /* The width in bits of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field. */
108466 #define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_WIDTH 32
108467 /* The mask used to set the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field value. */
108468 #define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_SET_MSK 0xffffffff
108469 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field value. */
108470 #define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_CLR_MSK 0x00000000
108471 /* The reset value of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field is UNKNOWN. */
108472 #define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_RESET 0x0
108473 /* Extracts the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 field value from a register. */
108474 #define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_GET(value) (((value) & 0xffffffff) >> 0)
108475 /* Produces a ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field value suitable for setting the register. */
108476 #define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_SET(value) (((value) << 0) & 0xffffffff)
108477 
108478 #ifndef __ASSEMBLY__
108479 /*
108480  * WARNING: The C register and register group struct declarations are provided for
108481  * convenience and illustrative purposes. They should, however, be used with
108482  * caution as the C language standard provides no guarantees about the alignment or
108483  * atomicity of device memory accesses. The recommended practice for writing
108484  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
108485  * alt_write_word() functions.
108486  *
108487  * The struct declaration for register ALT_USB_DEV_DOEPDMAB1.
108488  */
108489 struct ALT_USB_DEV_DOEPDMAB1_s
108490 {
108491  const uint32_t doepdmab1 : 32; /* ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 */
108492 };
108493 
108494 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB1. */
108495 typedef volatile struct ALT_USB_DEV_DOEPDMAB1_s ALT_USB_DEV_DOEPDMAB1_t;
108496 #endif /* __ASSEMBLY__ */
108497 
108498 /* The reset value of the ALT_USB_DEV_DOEPDMAB1 register. */
108499 #define ALT_USB_DEV_DOEPDMAB1_RESET 0x00000000
108500 /* The byte offset of the ALT_USB_DEV_DOEPDMAB1 register from the beginning of the component. */
108501 #define ALT_USB_DEV_DOEPDMAB1_OFST 0x33c
108502 /* The address of the ALT_USB_DEV_DOEPDMAB1 register. */
108503 #define ALT_USB_DEV_DOEPDMAB1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB1_OFST))
108504 
108505 /*
108506  * Register : doepctl2
108507  *
108508  * Device Control OUT Endpoint 2 Control Register
108509  *
108510  * Register Layout
108511  *
108512  * Bits | Access | Reset | Description
108513  * :--------|:---------|:------|:------------------------------
108514  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL2_MPS
108515  * [14:11] | ??? | 0x0 | *UNDEFINED*
108516  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL2_USBACTEP
108517  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL2_DPID
108518  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL2_NAKSTS
108519  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL2_EPTYPE
108520  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL2_SNP
108521  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL2_STALL
108522  * [25:22] | ??? | 0x0 | *UNDEFINED*
108523  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL2_CNAK
108524  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL2_SNAK
108525  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL2_SETD0PID
108526  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL2_SETD1PID
108527  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL2_EPDIS
108528  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL2_EPENA
108529  *
108530  */
108531 /*
108532  * Field : mps
108533  *
108534  * Maximum Packet Size (MPS)
108535  *
108536  * The application must program this field with the maximum packet size for the
108537  * current
108538  *
108539  * logical endpoint. This value is in bytes.
108540  *
108541  * Field Access Macros:
108542  *
108543  */
108544 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_MPS register field. */
108545 #define ALT_USB_DEV_DOEPCTL2_MPS_LSB 0
108546 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_MPS register field. */
108547 #define ALT_USB_DEV_DOEPCTL2_MPS_MSB 10
108548 /* The width in bits of the ALT_USB_DEV_DOEPCTL2_MPS register field. */
108549 #define ALT_USB_DEV_DOEPCTL2_MPS_WIDTH 11
108550 /* The mask used to set the ALT_USB_DEV_DOEPCTL2_MPS register field value. */
108551 #define ALT_USB_DEV_DOEPCTL2_MPS_SET_MSK 0x000007ff
108552 /* The mask used to clear the ALT_USB_DEV_DOEPCTL2_MPS register field value. */
108553 #define ALT_USB_DEV_DOEPCTL2_MPS_CLR_MSK 0xfffff800
108554 /* The reset value of the ALT_USB_DEV_DOEPCTL2_MPS register field. */
108555 #define ALT_USB_DEV_DOEPCTL2_MPS_RESET 0x0
108556 /* Extracts the ALT_USB_DEV_DOEPCTL2_MPS field value from a register. */
108557 #define ALT_USB_DEV_DOEPCTL2_MPS_GET(value) (((value) & 0x000007ff) >> 0)
108558 /* Produces a ALT_USB_DEV_DOEPCTL2_MPS register field value suitable for setting the register. */
108559 #define ALT_USB_DEV_DOEPCTL2_MPS_SET(value) (((value) << 0) & 0x000007ff)
108560 
108561 /*
108562  * Field : usbactep
108563  *
108564  * USB Active Endpoint (USBActEP)
108565  *
108566  * Indicates whether this endpoint is active in the current configuration and
108567  * interface. The
108568  *
108569  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
108570  * reset. After
108571  *
108572  * receiving the SetConfiguration and SetInterface commands, the application must
108573  *
108574  * program endpoint registers accordingly and set this bit.
108575  *
108576  * Field Enumeration Values:
108577  *
108578  * Enum | Value | Description
108579  * :-------------------------------------|:------|:--------------------
108580  * ALT_USB_DEV_DOEPCTL2_USBACTEP_E_DISD | 0x0 | Not Active
108581  * ALT_USB_DEV_DOEPCTL2_USBACTEP_E_END | 0x1 | USB Active Endpoint
108582  *
108583  * Field Access Macros:
108584  *
108585  */
108586 /*
108587  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_USBACTEP
108588  *
108589  * Not Active
108590  */
108591 #define ALT_USB_DEV_DOEPCTL2_USBACTEP_E_DISD 0x0
108592 /*
108593  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_USBACTEP
108594  *
108595  * USB Active Endpoint
108596  */
108597 #define ALT_USB_DEV_DOEPCTL2_USBACTEP_E_END 0x1
108598 
108599 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */
108600 #define ALT_USB_DEV_DOEPCTL2_USBACTEP_LSB 15
108601 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */
108602 #define ALT_USB_DEV_DOEPCTL2_USBACTEP_MSB 15
108603 /* The width in bits of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */
108604 #define ALT_USB_DEV_DOEPCTL2_USBACTEP_WIDTH 1
108605 /* The mask used to set the ALT_USB_DEV_DOEPCTL2_USBACTEP register field value. */
108606 #define ALT_USB_DEV_DOEPCTL2_USBACTEP_SET_MSK 0x00008000
108607 /* The mask used to clear the ALT_USB_DEV_DOEPCTL2_USBACTEP register field value. */
108608 #define ALT_USB_DEV_DOEPCTL2_USBACTEP_CLR_MSK 0xffff7fff
108609 /* The reset value of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */
108610 #define ALT_USB_DEV_DOEPCTL2_USBACTEP_RESET 0x0
108611 /* Extracts the ALT_USB_DEV_DOEPCTL2_USBACTEP field value from a register. */
108612 #define ALT_USB_DEV_DOEPCTL2_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
108613 /* Produces a ALT_USB_DEV_DOEPCTL2_USBACTEP register field value suitable for setting the register. */
108614 #define ALT_USB_DEV_DOEPCTL2_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
108615 
108616 /*
108617  * Field : dpid
108618  *
108619  * Endpoint Data PID (DPID)
108620  *
108621  * Applies to interrupt/bulk IN and OUT endpoints only.
108622  *
108623  * Contains the PID of the packet to be received or transmitted on this endpoint.
108624  * The
108625  *
108626  * application must program the PID of the first packet to be received or
108627  * transmitted on
108628  *
108629  * this endpoint, after the endpoint is activated. The applications use the
108630  * SetD1PID and
108631  *
108632  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
108633  *
108634  * 1'b0: DATA0
108635  *
108636  * 1'b1: DATA1
108637  *
108638  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
108639  *
108640  * DMA mode.
108641  *
108642  * 1'b0 RO
108643  *
108644  * Even/Odd (Micro)Frame (EO_FrNum)
108645  *
108646  * In non-Scatter/Gather DMA mode:
108647  *
108648  * Applies to isochronous IN and OUT endpoints only.
108649  *
108650  * Indicates the (micro)frame number in which the core transmits/receives
108651  * isochronous
108652  *
108653  * data for this endpoint. The application must program the even/odd (micro) frame
108654  *
108655  * number in which it intends to transmit/receive isochronous data for this
108656  * endpoint using
108657  *
108658  * the SetEvnFr and SetOddFr fields in this register.
108659  *
108660  * 1'b0: Even (micro)frame
108661  *
108662  * 1'b1: Odd (micro)frame
108663  *
108664  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
108665  * number
108666  *
108667  * in which to send data is provided in the transmit descriptor structure. The
108668  * frame in
108669  *
108670  * which data is received is updated in receive descriptor structure.
108671  *
108672  * Field Enumeration Values:
108673  *
108674  * Enum | Value | Description
108675  * :----------------------------------|:------|:-----------------------------
108676  * ALT_USB_DEV_DOEPCTL2_DPID_E_INACT | 0x0 | Endpoint Data PID not active
108677  * ALT_USB_DEV_DOEPCTL2_DPID_E_ACT | 0x1 | Endpoint Data PID active
108678  *
108679  * Field Access Macros:
108680  *
108681  */
108682 /*
108683  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_DPID
108684  *
108685  * Endpoint Data PID not active
108686  */
108687 #define ALT_USB_DEV_DOEPCTL2_DPID_E_INACT 0x0
108688 /*
108689  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_DPID
108690  *
108691  * Endpoint Data PID active
108692  */
108693 #define ALT_USB_DEV_DOEPCTL2_DPID_E_ACT 0x1
108694 
108695 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_DPID register field. */
108696 #define ALT_USB_DEV_DOEPCTL2_DPID_LSB 16
108697 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_DPID register field. */
108698 #define ALT_USB_DEV_DOEPCTL2_DPID_MSB 16
108699 /* The width in bits of the ALT_USB_DEV_DOEPCTL2_DPID register field. */
108700 #define ALT_USB_DEV_DOEPCTL2_DPID_WIDTH 1
108701 /* The mask used to set the ALT_USB_DEV_DOEPCTL2_DPID register field value. */
108702 #define ALT_USB_DEV_DOEPCTL2_DPID_SET_MSK 0x00010000
108703 /* The mask used to clear the ALT_USB_DEV_DOEPCTL2_DPID register field value. */
108704 #define ALT_USB_DEV_DOEPCTL2_DPID_CLR_MSK 0xfffeffff
108705 /* The reset value of the ALT_USB_DEV_DOEPCTL2_DPID register field. */
108706 #define ALT_USB_DEV_DOEPCTL2_DPID_RESET 0x0
108707 /* Extracts the ALT_USB_DEV_DOEPCTL2_DPID field value from a register. */
108708 #define ALT_USB_DEV_DOEPCTL2_DPID_GET(value) (((value) & 0x00010000) >> 16)
108709 /* Produces a ALT_USB_DEV_DOEPCTL2_DPID register field value suitable for setting the register. */
108710 #define ALT_USB_DEV_DOEPCTL2_DPID_SET(value) (((value) << 16) & 0x00010000)
108711 
108712 /*
108713  * Field : naksts
108714  *
108715  * NAK Status (NAKSts)
108716  *
108717  * Indicates the following:
108718  *
108719  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
108720  *
108721  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
108722  *
108723  * When either the application or the core sets this bit:
108724  *
108725  * The core stops receiving any data on an OUT endpoint, even if there is space in
108726  *
108727  * the RxFIFO to accommodate the incoming packet.
108728  *
108729  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
108730  *
108731  * endpoint, even if there data is available in the TxFIFO.
108732  *
108733  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
108734  *
108735  * if there data is available in the TxFIFO.
108736  *
108737  * Irrespective of this bit's setting, the core always responds to SETUP data
108738  * packets with
108739  *
108740  * an ACK handshake.
108741  *
108742  * Field Enumeration Values:
108743  *
108744  * Enum | Value | Description
108745  * :-------------------------------------|:------|:------------------------------------------------
108746  * ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
108747  * : | | based on the FIFO status
108748  * ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
108749  * : | | endpoint
108750  *
108751  * Field Access Macros:
108752  *
108753  */
108754 /*
108755  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_NAKSTS
108756  *
108757  * The core is transmitting non-NAK handshakes based on the FIFO status
108758  */
108759 #define ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NONNAK 0x0
108760 /*
108761  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_NAKSTS
108762  *
108763  * The core is transmitting NAK handshakes on this endpoint
108764  */
108765 #define ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NAK 0x1
108766 
108767 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */
108768 #define ALT_USB_DEV_DOEPCTL2_NAKSTS_LSB 17
108769 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */
108770 #define ALT_USB_DEV_DOEPCTL2_NAKSTS_MSB 17
108771 /* The width in bits of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */
108772 #define ALT_USB_DEV_DOEPCTL2_NAKSTS_WIDTH 1
108773 /* The mask used to set the ALT_USB_DEV_DOEPCTL2_NAKSTS register field value. */
108774 #define ALT_USB_DEV_DOEPCTL2_NAKSTS_SET_MSK 0x00020000
108775 /* The mask used to clear the ALT_USB_DEV_DOEPCTL2_NAKSTS register field value. */
108776 #define ALT_USB_DEV_DOEPCTL2_NAKSTS_CLR_MSK 0xfffdffff
108777 /* The reset value of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */
108778 #define ALT_USB_DEV_DOEPCTL2_NAKSTS_RESET 0x0
108779 /* Extracts the ALT_USB_DEV_DOEPCTL2_NAKSTS field value from a register. */
108780 #define ALT_USB_DEV_DOEPCTL2_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
108781 /* Produces a ALT_USB_DEV_DOEPCTL2_NAKSTS register field value suitable for setting the register. */
108782 #define ALT_USB_DEV_DOEPCTL2_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
108783 
108784 /*
108785  * Field : eptype
108786  *
108787  * Endpoint Type (EPType)
108788  *
108789  * This is the transfer type supported by this logical endpoint.
108790  *
108791  * 2'b00: Control
108792  *
108793  * 2'b01: Isochronous
108794  *
108795  * 2'b10: Bulk
108796  *
108797  * 2'b11: Interrupt
108798  *
108799  * Field Enumeration Values:
108800  *
108801  * Enum | Value | Description
108802  * :------------------------------------------|:------|:------------
108803  * ALT_USB_DEV_DOEPCTL2_EPTYPE_E_CTL | 0x0 | Control
108804  * ALT_USB_DEV_DOEPCTL2_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
108805  * ALT_USB_DEV_DOEPCTL2_EPTYPE_E_BULK | 0x2 | Bulk
108806  * ALT_USB_DEV_DOEPCTL2_EPTYPE_E_INTERRUP | 0x3 | Interrupt
108807  *
108808  * Field Access Macros:
108809  *
108810  */
108811 /*
108812  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE
108813  *
108814  * Control
108815  */
108816 #define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_CTL 0x0
108817 /*
108818  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE
108819  *
108820  * Isochronous
108821  */
108822 #define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_ISOCHRONOUS 0x1
108823 /*
108824  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE
108825  *
108826  * Bulk
108827  */
108828 #define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_BULK 0x2
108829 /*
108830  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE
108831  *
108832  * Interrupt
108833  */
108834 #define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_INTERRUP 0x3
108835 
108836 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */
108837 #define ALT_USB_DEV_DOEPCTL2_EPTYPE_LSB 18
108838 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */
108839 #define ALT_USB_DEV_DOEPCTL2_EPTYPE_MSB 19
108840 /* The width in bits of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */
108841 #define ALT_USB_DEV_DOEPCTL2_EPTYPE_WIDTH 2
108842 /* The mask used to set the ALT_USB_DEV_DOEPCTL2_EPTYPE register field value. */
108843 #define ALT_USB_DEV_DOEPCTL2_EPTYPE_SET_MSK 0x000c0000
108844 /* The mask used to clear the ALT_USB_DEV_DOEPCTL2_EPTYPE register field value. */
108845 #define ALT_USB_DEV_DOEPCTL2_EPTYPE_CLR_MSK 0xfff3ffff
108846 /* The reset value of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */
108847 #define ALT_USB_DEV_DOEPCTL2_EPTYPE_RESET 0x0
108848 /* Extracts the ALT_USB_DEV_DOEPCTL2_EPTYPE field value from a register. */
108849 #define ALT_USB_DEV_DOEPCTL2_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
108850 /* Produces a ALT_USB_DEV_DOEPCTL2_EPTYPE register field value suitable for setting the register. */
108851 #define ALT_USB_DEV_DOEPCTL2_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
108852 
108853 /*
108854  * Field : snp
108855  *
108856  * Snoop Mode (Snp)
108857  *
108858  * Applies to OUT endpoints only.
108859  *
108860  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
108861  *
108862  * check the correctness of OUT packets before transferring them to application
108863  * memory.
108864  *
108865  * Field Enumeration Values:
108866  *
108867  * Enum | Value | Description
108868  * :-------------------------------|:------|:-------------------
108869  * ALT_USB_DEV_DOEPCTL2_SNP_E_DIS | 0x0 | Disable Snoop Mode
108870  * ALT_USB_DEV_DOEPCTL2_SNP_E_EN | 0x1 | Enable Snoop Mode
108871  *
108872  * Field Access Macros:
108873  *
108874  */
108875 /*
108876  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNP
108877  *
108878  * Disable Snoop Mode
108879  */
108880 #define ALT_USB_DEV_DOEPCTL2_SNP_E_DIS 0x0
108881 /*
108882  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNP
108883  *
108884  * Enable Snoop Mode
108885  */
108886 #define ALT_USB_DEV_DOEPCTL2_SNP_E_EN 0x1
108887 
108888 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SNP register field. */
108889 #define ALT_USB_DEV_DOEPCTL2_SNP_LSB 20
108890 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SNP register field. */
108891 #define ALT_USB_DEV_DOEPCTL2_SNP_MSB 20
108892 /* The width in bits of the ALT_USB_DEV_DOEPCTL2_SNP register field. */
108893 #define ALT_USB_DEV_DOEPCTL2_SNP_WIDTH 1
108894 /* The mask used to set the ALT_USB_DEV_DOEPCTL2_SNP register field value. */
108895 #define ALT_USB_DEV_DOEPCTL2_SNP_SET_MSK 0x00100000
108896 /* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SNP register field value. */
108897 #define ALT_USB_DEV_DOEPCTL2_SNP_CLR_MSK 0xffefffff
108898 /* The reset value of the ALT_USB_DEV_DOEPCTL2_SNP register field. */
108899 #define ALT_USB_DEV_DOEPCTL2_SNP_RESET 0x0
108900 /* Extracts the ALT_USB_DEV_DOEPCTL2_SNP field value from a register. */
108901 #define ALT_USB_DEV_DOEPCTL2_SNP_GET(value) (((value) & 0x00100000) >> 20)
108902 /* Produces a ALT_USB_DEV_DOEPCTL2_SNP register field value suitable for setting the register. */
108903 #define ALT_USB_DEV_DOEPCTL2_SNP_SET(value) (((value) << 20) & 0x00100000)
108904 
108905 /*
108906  * Field : stall
108907  *
108908  * STALL Handshake (Stall)
108909  *
108910  * Applies to non-control, non-isochronous IN and OUT endpoints only.
108911  *
108912  * The application sets this bit to stall all tokens from the USB host to this
108913  * endpoint. If a
108914  *
108915  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
108916  * bit, the
108917  *
108918  * STALL bit takes priority. Only the application can clear this bit, never the
108919  * core.
108920  *
108921  * 1'b0 R_W
108922  *
108923  * Applies to control endpoints only.
108924  *
108925  * The application can only set this bit, and the core clears it, when a SETUP
108926  * token is
108927  *
108928  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
108929  * OUT
108930  *
108931  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
108932  * this bit's
108933  *
108934  * setting, the core always responds to SETUP data packets with an ACK handshake.
108935  *
108936  * Field Enumeration Values:
108937  *
108938  * Enum | Value | Description
108939  * :-----------------------------------|:------|:----------------------------
108940  * ALT_USB_DEV_DOEPCTL2_STALL_E_INACT | 0x0 | STALL All Tokens not active
108941  * ALT_USB_DEV_DOEPCTL2_STALL_E_ACT | 0x1 | STALL All Tokens active
108942  *
108943  * Field Access Macros:
108944  *
108945  */
108946 /*
108947  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_STALL
108948  *
108949  * STALL All Tokens not active
108950  */
108951 #define ALT_USB_DEV_DOEPCTL2_STALL_E_INACT 0x0
108952 /*
108953  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_STALL
108954  *
108955  * STALL All Tokens active
108956  */
108957 #define ALT_USB_DEV_DOEPCTL2_STALL_E_ACT 0x1
108958 
108959 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_STALL register field. */
108960 #define ALT_USB_DEV_DOEPCTL2_STALL_LSB 21
108961 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_STALL register field. */
108962 #define ALT_USB_DEV_DOEPCTL2_STALL_MSB 21
108963 /* The width in bits of the ALT_USB_DEV_DOEPCTL2_STALL register field. */
108964 #define ALT_USB_DEV_DOEPCTL2_STALL_WIDTH 1
108965 /* The mask used to set the ALT_USB_DEV_DOEPCTL2_STALL register field value. */
108966 #define ALT_USB_DEV_DOEPCTL2_STALL_SET_MSK 0x00200000
108967 /* The mask used to clear the ALT_USB_DEV_DOEPCTL2_STALL register field value. */
108968 #define ALT_USB_DEV_DOEPCTL2_STALL_CLR_MSK 0xffdfffff
108969 /* The reset value of the ALT_USB_DEV_DOEPCTL2_STALL register field. */
108970 #define ALT_USB_DEV_DOEPCTL2_STALL_RESET 0x0
108971 /* Extracts the ALT_USB_DEV_DOEPCTL2_STALL field value from a register. */
108972 #define ALT_USB_DEV_DOEPCTL2_STALL_GET(value) (((value) & 0x00200000) >> 21)
108973 /* Produces a ALT_USB_DEV_DOEPCTL2_STALL register field value suitable for setting the register. */
108974 #define ALT_USB_DEV_DOEPCTL2_STALL_SET(value) (((value) << 21) & 0x00200000)
108975 
108976 /*
108977  * Field : cnak
108978  *
108979  * Clear NAK (CNAK)
108980  *
108981  * A write to this bit clears the NAK bit For the endpoint.
108982  *
108983  * Field Enumeration Values:
108984  *
108985  * Enum | Value | Description
108986  * :----------------------------------|:------|:-------------
108987  * ALT_USB_DEV_DOEPCTL2_CNAK_E_INACT | 0x0 | No Clear NAK
108988  * ALT_USB_DEV_DOEPCTL2_CNAK_E_ACT | 0x1 | Clear NAK
108989  *
108990  * Field Access Macros:
108991  *
108992  */
108993 /*
108994  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_CNAK
108995  *
108996  * No Clear NAK
108997  */
108998 #define ALT_USB_DEV_DOEPCTL2_CNAK_E_INACT 0x0
108999 /*
109000  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_CNAK
109001  *
109002  * Clear NAK
109003  */
109004 #define ALT_USB_DEV_DOEPCTL2_CNAK_E_ACT 0x1
109005 
109006 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */
109007 #define ALT_USB_DEV_DOEPCTL2_CNAK_LSB 26
109008 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */
109009 #define ALT_USB_DEV_DOEPCTL2_CNAK_MSB 26
109010 /* The width in bits of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */
109011 #define ALT_USB_DEV_DOEPCTL2_CNAK_WIDTH 1
109012 /* The mask used to set the ALT_USB_DEV_DOEPCTL2_CNAK register field value. */
109013 #define ALT_USB_DEV_DOEPCTL2_CNAK_SET_MSK 0x04000000
109014 /* The mask used to clear the ALT_USB_DEV_DOEPCTL2_CNAK register field value. */
109015 #define ALT_USB_DEV_DOEPCTL2_CNAK_CLR_MSK 0xfbffffff
109016 /* The reset value of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */
109017 #define ALT_USB_DEV_DOEPCTL2_CNAK_RESET 0x0
109018 /* Extracts the ALT_USB_DEV_DOEPCTL2_CNAK field value from a register. */
109019 #define ALT_USB_DEV_DOEPCTL2_CNAK_GET(value) (((value) & 0x04000000) >> 26)
109020 /* Produces a ALT_USB_DEV_DOEPCTL2_CNAK register field value suitable for setting the register. */
109021 #define ALT_USB_DEV_DOEPCTL2_CNAK_SET(value) (((value) << 26) & 0x04000000)
109022 
109023 /*
109024  * Field : snak
109025  *
109026  * Set NAK (SNAK)
109027  *
109028  * A write to this bit sets the NAK bit For the endpoint.
109029  *
109030  * Using this bit, the application can control the transmission of NAK
109031  *
109032  * handshakes on an endpoint. The core can also Set this bit For an
109033  *
109034  * endpoint after a SETUP packet is received on that endpoint.
109035  *
109036  * Field Enumeration Values:
109037  *
109038  * Enum | Value | Description
109039  * :----------------------------------|:------|:------------
109040  * ALT_USB_DEV_DOEPCTL2_SNAK_E_INACT | 0x0 | No Set NAK
109041  * ALT_USB_DEV_DOEPCTL2_SNAK_E_ACT | 0x1 | Set NAK
109042  *
109043  * Field Access Macros:
109044  *
109045  */
109046 /*
109047  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNAK
109048  *
109049  * No Set NAK
109050  */
109051 #define ALT_USB_DEV_DOEPCTL2_SNAK_E_INACT 0x0
109052 /*
109053  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNAK
109054  *
109055  * Set NAK
109056  */
109057 #define ALT_USB_DEV_DOEPCTL2_SNAK_E_ACT 0x1
109058 
109059 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */
109060 #define ALT_USB_DEV_DOEPCTL2_SNAK_LSB 27
109061 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */
109062 #define ALT_USB_DEV_DOEPCTL2_SNAK_MSB 27
109063 /* The width in bits of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */
109064 #define ALT_USB_DEV_DOEPCTL2_SNAK_WIDTH 1
109065 /* The mask used to set the ALT_USB_DEV_DOEPCTL2_SNAK register field value. */
109066 #define ALT_USB_DEV_DOEPCTL2_SNAK_SET_MSK 0x08000000
109067 /* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SNAK register field value. */
109068 #define ALT_USB_DEV_DOEPCTL2_SNAK_CLR_MSK 0xf7ffffff
109069 /* The reset value of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */
109070 #define ALT_USB_DEV_DOEPCTL2_SNAK_RESET 0x0
109071 /* Extracts the ALT_USB_DEV_DOEPCTL2_SNAK field value from a register. */
109072 #define ALT_USB_DEV_DOEPCTL2_SNAK_GET(value) (((value) & 0x08000000) >> 27)
109073 /* Produces a ALT_USB_DEV_DOEPCTL2_SNAK register field value suitable for setting the register. */
109074 #define ALT_USB_DEV_DOEPCTL2_SNAK_SET(value) (((value) << 27) & 0x08000000)
109075 
109076 /*
109077  * Field : setd0pid
109078  *
109079  * Set DATA0 PID (SetD0PID)
109080  *
109081  * Applies to interrupt/bulk IN and OUT endpoints only.
109082  *
109083  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
109084  * to DATA0.
109085  *
109086  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
109087  *
109088  * DMA mode.
109089  *
109090  * 1'b0 WO
109091  *
109092  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
109093  *
109094  * Applies to isochronous IN and OUT endpoints only.
109095  *
109096  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
109097  * (micro)
109098  *
109099  * frame.
109100  *
109101  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
109102  * number
109103  *
109104  * in which to send data is in the transmit descriptor structure. The frame in
109105  * which to
109106  *
109107  * receive data is updated in receive descriptor structure.
109108  *
109109  * Field Enumeration Values:
109110  *
109111  * Enum | Value | Description
109112  * :-------------------------------------|:------|:------------------------------------
109113  * ALT_USB_DEV_DOEPCTL2_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
109114  * ALT_USB_DEV_DOEPCTL2_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
109115  *
109116  * Field Access Macros:
109117  *
109118  */
109119 /*
109120  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD0PID
109121  *
109122  * Disables Set DATA0 PID
109123  */
109124 #define ALT_USB_DEV_DOEPCTL2_SETD0PID_E_DISD 0x0
109125 /*
109126  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD0PID
109127  *
109128  * Enables Endpoint Data PID to DATA0)
109129  */
109130 #define ALT_USB_DEV_DOEPCTL2_SETD0PID_E_END 0x1
109131 
109132 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */
109133 #define ALT_USB_DEV_DOEPCTL2_SETD0PID_LSB 28
109134 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */
109135 #define ALT_USB_DEV_DOEPCTL2_SETD0PID_MSB 28
109136 /* The width in bits of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */
109137 #define ALT_USB_DEV_DOEPCTL2_SETD0PID_WIDTH 1
109138 /* The mask used to set the ALT_USB_DEV_DOEPCTL2_SETD0PID register field value. */
109139 #define ALT_USB_DEV_DOEPCTL2_SETD0PID_SET_MSK 0x10000000
109140 /* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SETD0PID register field value. */
109141 #define ALT_USB_DEV_DOEPCTL2_SETD0PID_CLR_MSK 0xefffffff
109142 /* The reset value of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */
109143 #define ALT_USB_DEV_DOEPCTL2_SETD0PID_RESET 0x0
109144 /* Extracts the ALT_USB_DEV_DOEPCTL2_SETD0PID field value from a register. */
109145 #define ALT_USB_DEV_DOEPCTL2_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
109146 /* Produces a ALT_USB_DEV_DOEPCTL2_SETD0PID register field value suitable for setting the register. */
109147 #define ALT_USB_DEV_DOEPCTL2_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
109148 
109149 /*
109150  * Field : setd1pid
109151  *
109152  * Set DATA1 PID (SetD1PID)
109153  *
109154  * Applies to interrupt/bulk IN and OUT endpoints only.
109155  *
109156  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
109157  * to DATA1.
109158  *
109159  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
109160  *
109161  * DMA mode.
109162  *
109163  * Set Odd (micro)frame (SetOddFr)
109164  *
109165  * Applies to isochronous IN and OUT endpoints only.
109166  *
109167  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
109168  *
109169  * (micro)frame.
109170  *
109171  * This field is not applicable for Scatter/Gather DMA mode.
109172  *
109173  * Field Enumeration Values:
109174  *
109175  * Enum | Value | Description
109176  * :-------------------------------------|:------|:-----------------------
109177  * ALT_USB_DEV_DOEPCTL2_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
109178  * ALT_USB_DEV_DOEPCTL2_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
109179  *
109180  * Field Access Macros:
109181  *
109182  */
109183 /*
109184  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD1PID
109185  *
109186  * Disables Set DATA1 PID
109187  */
109188 #define ALT_USB_DEV_DOEPCTL2_SETD1PID_E_DISD 0x0
109189 /*
109190  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD1PID
109191  *
109192  * Enables Set DATA1 PID
109193  */
109194 #define ALT_USB_DEV_DOEPCTL2_SETD1PID_E_END 0x1
109195 
109196 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */
109197 #define ALT_USB_DEV_DOEPCTL2_SETD1PID_LSB 29
109198 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */
109199 #define ALT_USB_DEV_DOEPCTL2_SETD1PID_MSB 29
109200 /* The width in bits of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */
109201 #define ALT_USB_DEV_DOEPCTL2_SETD1PID_WIDTH 1
109202 /* The mask used to set the ALT_USB_DEV_DOEPCTL2_SETD1PID register field value. */
109203 #define ALT_USB_DEV_DOEPCTL2_SETD1PID_SET_MSK 0x20000000
109204 /* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SETD1PID register field value. */
109205 #define ALT_USB_DEV_DOEPCTL2_SETD1PID_CLR_MSK 0xdfffffff
109206 /* The reset value of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */
109207 #define ALT_USB_DEV_DOEPCTL2_SETD1PID_RESET 0x0
109208 /* Extracts the ALT_USB_DEV_DOEPCTL2_SETD1PID field value from a register. */
109209 #define ALT_USB_DEV_DOEPCTL2_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
109210 /* Produces a ALT_USB_DEV_DOEPCTL2_SETD1PID register field value suitable for setting the register. */
109211 #define ALT_USB_DEV_DOEPCTL2_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
109212 
109213 /*
109214  * Field : epdis
109215  *
109216  * Endpoint Disable (EPDis)
109217  *
109218  * Applies to IN and OUT endpoints.
109219  *
109220  * The application sets this bit to stop transmitting/receiving data on an
109221  * endpoint, even
109222  *
109223  * before the transfer for that endpoint is complete. The application must wait for
109224  * the
109225  *
109226  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
109227  * clears
109228  *
109229  * this bit before setting the Endpoint Disabled interrupt. The application must
109230  * set this bit
109231  *
109232  * only if Endpoint Enable is already set for this endpoint.
109233  *
109234  * Field Enumeration Values:
109235  *
109236  * Enum | Value | Description
109237  * :-----------------------------------|:------|:--------------------
109238  * ALT_USB_DEV_DOEPCTL2_EPDIS_E_INACT | 0x0 | No Endpoint Disable
109239  * ALT_USB_DEV_DOEPCTL2_EPDIS_E_ACT | 0x1 | Endpoint Disable
109240  *
109241  * Field Access Macros:
109242  *
109243  */
109244 /*
109245  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPDIS
109246  *
109247  * No Endpoint Disable
109248  */
109249 #define ALT_USB_DEV_DOEPCTL2_EPDIS_E_INACT 0x0
109250 /*
109251  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPDIS
109252  *
109253  * Endpoint Disable
109254  */
109255 #define ALT_USB_DEV_DOEPCTL2_EPDIS_E_ACT 0x1
109256 
109257 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */
109258 #define ALT_USB_DEV_DOEPCTL2_EPDIS_LSB 30
109259 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */
109260 #define ALT_USB_DEV_DOEPCTL2_EPDIS_MSB 30
109261 /* The width in bits of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */
109262 #define ALT_USB_DEV_DOEPCTL2_EPDIS_WIDTH 1
109263 /* The mask used to set the ALT_USB_DEV_DOEPCTL2_EPDIS register field value. */
109264 #define ALT_USB_DEV_DOEPCTL2_EPDIS_SET_MSK 0x40000000
109265 /* The mask used to clear the ALT_USB_DEV_DOEPCTL2_EPDIS register field value. */
109266 #define ALT_USB_DEV_DOEPCTL2_EPDIS_CLR_MSK 0xbfffffff
109267 /* The reset value of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */
109268 #define ALT_USB_DEV_DOEPCTL2_EPDIS_RESET 0x0
109269 /* Extracts the ALT_USB_DEV_DOEPCTL2_EPDIS field value from a register. */
109270 #define ALT_USB_DEV_DOEPCTL2_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
109271 /* Produces a ALT_USB_DEV_DOEPCTL2_EPDIS register field value suitable for setting the register. */
109272 #define ALT_USB_DEV_DOEPCTL2_EPDIS_SET(value) (((value) << 30) & 0x40000000)
109273 
109274 /*
109275  * Field : epena
109276  *
109277  * Endpoint Enable (EPEna)
109278  *
109279  * Applies to IN and OUT endpoints.
109280  *
109281  * When Scatter/Gather DMA mode is enabled,
109282  *
109283  * For IN endpoints this bit indicates that the descriptor structure and data
109284  * buffer with
109285  *
109286  * data ready to transmit is setup.
109287  *
109288  * For OUT endpoint it indicates that the descriptor structure and data buffer to
109289  *
109290  * receive data is setup.
109291  *
109292  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
109293  *
109294  * DMA mode:
109295  *
109296  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
109297  * the
109298  *
109299  * endpoint.
109300  *
109301  * * For OUT endpoints, this bit indicates that the application has allocated the
109302  *
109303  * memory to start receiving data from the USB.
109304  *
109305  * * The core clears this bit before setting any of the following interrupts on
109306  * this
109307  *
109308  * endpoint:
109309  *
109310  * SETUP Phase Done
109311  *
109312  * Endpoint Disabled
109313  *
109314  * Transfer Completed
109315  *
109316  * Note: For control endpoints in DMA mode, this bit must be set to be able to
109317  * transfer
109318  *
109319  * SETUP data packets in memory.
109320  *
109321  * Field Enumeration Values:
109322  *
109323  * Enum | Value | Description
109324  * :-----------------------------------|:------|:-------------------------
109325  * ALT_USB_DEV_DOEPCTL2_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
109326  * ALT_USB_DEV_DOEPCTL2_EPENA_E_ACT | 0x1 | Endpoint Enable active
109327  *
109328  * Field Access Macros:
109329  *
109330  */
109331 /*
109332  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPENA
109333  *
109334  * Endpoint Enable inactive
109335  */
109336 #define ALT_USB_DEV_DOEPCTL2_EPENA_E_INACT 0x0
109337 /*
109338  * Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPENA
109339  *
109340  * Endpoint Enable active
109341  */
109342 #define ALT_USB_DEV_DOEPCTL2_EPENA_E_ACT 0x1
109343 
109344 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */
109345 #define ALT_USB_DEV_DOEPCTL2_EPENA_LSB 31
109346 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */
109347 #define ALT_USB_DEV_DOEPCTL2_EPENA_MSB 31
109348 /* The width in bits of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */
109349 #define ALT_USB_DEV_DOEPCTL2_EPENA_WIDTH 1
109350 /* The mask used to set the ALT_USB_DEV_DOEPCTL2_EPENA register field value. */
109351 #define ALT_USB_DEV_DOEPCTL2_EPENA_SET_MSK 0x80000000
109352 /* The mask used to clear the ALT_USB_DEV_DOEPCTL2_EPENA register field value. */
109353 #define ALT_USB_DEV_DOEPCTL2_EPENA_CLR_MSK 0x7fffffff
109354 /* The reset value of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */
109355 #define ALT_USB_DEV_DOEPCTL2_EPENA_RESET 0x0
109356 /* Extracts the ALT_USB_DEV_DOEPCTL2_EPENA field value from a register. */
109357 #define ALT_USB_DEV_DOEPCTL2_EPENA_GET(value) (((value) & 0x80000000) >> 31)
109358 /* Produces a ALT_USB_DEV_DOEPCTL2_EPENA register field value suitable for setting the register. */
109359 #define ALT_USB_DEV_DOEPCTL2_EPENA_SET(value) (((value) << 31) & 0x80000000)
109360 
109361 #ifndef __ASSEMBLY__
109362 /*
109363  * WARNING: The C register and register group struct declarations are provided for
109364  * convenience and illustrative purposes. They should, however, be used with
109365  * caution as the C language standard provides no guarantees about the alignment or
109366  * atomicity of device memory accesses. The recommended practice for writing
109367  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
109368  * alt_write_word() functions.
109369  *
109370  * The struct declaration for register ALT_USB_DEV_DOEPCTL2.
109371  */
109372 struct ALT_USB_DEV_DOEPCTL2_s
109373 {
109374  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL2_MPS */
109375  uint32_t : 4; /* *UNDEFINED* */
109376  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL2_USBACTEP */
109377  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL2_DPID */
109378  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL2_NAKSTS */
109379  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL2_EPTYPE */
109380  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL2_SNP */
109381  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL2_STALL */
109382  uint32_t : 4; /* *UNDEFINED* */
109383  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL2_CNAK */
109384  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL2_SNAK */
109385  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL2_SETD0PID */
109386  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL2_SETD1PID */
109387  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL2_EPDIS */
109388  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL2_EPENA */
109389 };
109390 
109391 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL2. */
109392 typedef volatile struct ALT_USB_DEV_DOEPCTL2_s ALT_USB_DEV_DOEPCTL2_t;
109393 #endif /* __ASSEMBLY__ */
109394 
109395 /* The reset value of the ALT_USB_DEV_DOEPCTL2 register. */
109396 #define ALT_USB_DEV_DOEPCTL2_RESET 0x00000000
109397 /* The byte offset of the ALT_USB_DEV_DOEPCTL2 register from the beginning of the component. */
109398 #define ALT_USB_DEV_DOEPCTL2_OFST 0x340
109399 /* The address of the ALT_USB_DEV_DOEPCTL2 register. */
109400 #define ALT_USB_DEV_DOEPCTL2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL2_OFST))
109401 
109402 /*
109403  * Register : doepint2
109404  *
109405  * Device OUT Endpoint 2 Interrupt Register
109406  *
109407  * Register Layout
109408  *
109409  * Bits | Access | Reset | Description
109410  * :--------|:-------|:------|:------------------------------------
109411  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_XFERCOMPL
109412  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_EPDISBLD
109413  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_AHBERR
109414  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_SETUP
109415  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS
109416  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_STSPHSERCVD
109417  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP
109418  * [7] | ??? | 0x0 | *UNDEFINED*
109419  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_OUTPKTERR
109420  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_BNAINTR
109421  * [10] | ??? | 0x0 | *UNDEFINED*
109422  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_PKTDRPSTS
109423  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_BBLEERR
109424  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_NAKINTRPT
109425  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_NYETINTRPT
109426  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_STUPPKTRCVD
109427  * [31:16] | ??? | 0x0 | *UNDEFINED*
109428  *
109429  */
109430 /*
109431  * Field : xfercompl
109432  *
109433  * Transfer Completed Interrupt (XferCompl)
109434  *
109435  * Applies to IN and OUT endpoints.
109436  *
109437  * When Scatter/Gather DMA mode is enabled
109438  *
109439  * * For IN endpoint this field indicates that the requested data
109440  *
109441  * from the descriptor is moved from external system memory
109442  *
109443  * to internal FIFO.
109444  *
109445  * * For OUT endpoint this field indicates that the requested
109446  *
109447  * data from the internal FIFO is moved to external system
109448  *
109449  * memory. This interrupt is generated only when the
109450  *
109451  * corresponding endpoint descriptor is closed, and the IOC
109452  *
109453  * bit For the corresponding descriptor is Set.
109454  *
109455  * When Scatter/Gather DMA mode is disabled, this field
109456  *
109457  * indicates that the programmed transfer is complete on the
109458  *
109459  * AHB as well as on the USB, For this endpoint.
109460  *
109461  * Field Enumeration Values:
109462  *
109463  * Enum | Value | Description
109464  * :---------------------------------------|:------|:-----------------------------
109465  * ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_INACT | 0x0 | No Interrupt
109466  * ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
109467  *
109468  * Field Access Macros:
109469  *
109470  */
109471 /*
109472  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_XFERCOMPL
109473  *
109474  * No Interrupt
109475  */
109476 #define ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_INACT 0x0
109477 /*
109478  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_XFERCOMPL
109479  *
109480  * Transfer Completed Interrupt
109481  */
109482 #define ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_ACT 0x1
109483 
109484 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */
109485 #define ALT_USB_DEV_DOEPINT2_XFERCOMPL_LSB 0
109486 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */
109487 #define ALT_USB_DEV_DOEPINT2_XFERCOMPL_MSB 0
109488 /* The width in bits of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */
109489 #define ALT_USB_DEV_DOEPINT2_XFERCOMPL_WIDTH 1
109490 /* The mask used to set the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field value. */
109491 #define ALT_USB_DEV_DOEPINT2_XFERCOMPL_SET_MSK 0x00000001
109492 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field value. */
109493 #define ALT_USB_DEV_DOEPINT2_XFERCOMPL_CLR_MSK 0xfffffffe
109494 /* The reset value of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */
109495 #define ALT_USB_DEV_DOEPINT2_XFERCOMPL_RESET 0x0
109496 /* Extracts the ALT_USB_DEV_DOEPINT2_XFERCOMPL field value from a register. */
109497 #define ALT_USB_DEV_DOEPINT2_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
109498 /* Produces a ALT_USB_DEV_DOEPINT2_XFERCOMPL register field value suitable for setting the register. */
109499 #define ALT_USB_DEV_DOEPINT2_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
109500 
109501 /*
109502  * Field : epdisbld
109503  *
109504  * Endpoint Disabled Interrupt (EPDisbld)
109505  *
109506  * Applies to IN and OUT endpoints.
109507  *
109508  * This bit indicates that the endpoint is disabled per the
109509  *
109510  * application's request.
109511  *
109512  * Field Enumeration Values:
109513  *
109514  * Enum | Value | Description
109515  * :--------------------------------------|:------|:----------------------------
109516  * ALT_USB_DEV_DOEPINT2_EPDISBLD_E_INACT | 0x0 | No Interrupt
109517  * ALT_USB_DEV_DOEPINT2_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
109518  *
109519  * Field Access Macros:
109520  *
109521  */
109522 /*
109523  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_EPDISBLD
109524  *
109525  * No Interrupt
109526  */
109527 #define ALT_USB_DEV_DOEPINT2_EPDISBLD_E_INACT 0x0
109528 /*
109529  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_EPDISBLD
109530  *
109531  * Endpoint Disabled Interrupt
109532  */
109533 #define ALT_USB_DEV_DOEPINT2_EPDISBLD_E_ACT 0x1
109534 
109535 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */
109536 #define ALT_USB_DEV_DOEPINT2_EPDISBLD_LSB 1
109537 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */
109538 #define ALT_USB_DEV_DOEPINT2_EPDISBLD_MSB 1
109539 /* The width in bits of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */
109540 #define ALT_USB_DEV_DOEPINT2_EPDISBLD_WIDTH 1
109541 /* The mask used to set the ALT_USB_DEV_DOEPINT2_EPDISBLD register field value. */
109542 #define ALT_USB_DEV_DOEPINT2_EPDISBLD_SET_MSK 0x00000002
109543 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_EPDISBLD register field value. */
109544 #define ALT_USB_DEV_DOEPINT2_EPDISBLD_CLR_MSK 0xfffffffd
109545 /* The reset value of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */
109546 #define ALT_USB_DEV_DOEPINT2_EPDISBLD_RESET 0x0
109547 /* Extracts the ALT_USB_DEV_DOEPINT2_EPDISBLD field value from a register. */
109548 #define ALT_USB_DEV_DOEPINT2_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
109549 /* Produces a ALT_USB_DEV_DOEPINT2_EPDISBLD register field value suitable for setting the register. */
109550 #define ALT_USB_DEV_DOEPINT2_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
109551 
109552 /*
109553  * Field : ahberr
109554  *
109555  * AHB Error (AHBErr)
109556  *
109557  * Applies to IN and OUT endpoints.
109558  *
109559  * This is generated only in Internal DMA mode when there is an
109560  *
109561  * AHB error during an AHB read/write. The application can read
109562  *
109563  * the corresponding endpoint DMA address register to get the
109564  *
109565  * error address.
109566  *
109567  * Field Enumeration Values:
109568  *
109569  * Enum | Value | Description
109570  * :------------------------------------|:------|:--------------------
109571  * ALT_USB_DEV_DOEPINT2_AHBERR_E_INACT | 0x0 | No Interrupt
109572  * ALT_USB_DEV_DOEPINT2_AHBERR_E_ACT | 0x1 | AHB Error interrupt
109573  *
109574  * Field Access Macros:
109575  *
109576  */
109577 /*
109578  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_AHBERR
109579  *
109580  * No Interrupt
109581  */
109582 #define ALT_USB_DEV_DOEPINT2_AHBERR_E_INACT 0x0
109583 /*
109584  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_AHBERR
109585  *
109586  * AHB Error interrupt
109587  */
109588 #define ALT_USB_DEV_DOEPINT2_AHBERR_E_ACT 0x1
109589 
109590 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */
109591 #define ALT_USB_DEV_DOEPINT2_AHBERR_LSB 2
109592 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */
109593 #define ALT_USB_DEV_DOEPINT2_AHBERR_MSB 2
109594 /* The width in bits of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */
109595 #define ALT_USB_DEV_DOEPINT2_AHBERR_WIDTH 1
109596 /* The mask used to set the ALT_USB_DEV_DOEPINT2_AHBERR register field value. */
109597 #define ALT_USB_DEV_DOEPINT2_AHBERR_SET_MSK 0x00000004
109598 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_AHBERR register field value. */
109599 #define ALT_USB_DEV_DOEPINT2_AHBERR_CLR_MSK 0xfffffffb
109600 /* The reset value of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */
109601 #define ALT_USB_DEV_DOEPINT2_AHBERR_RESET 0x0
109602 /* Extracts the ALT_USB_DEV_DOEPINT2_AHBERR field value from a register. */
109603 #define ALT_USB_DEV_DOEPINT2_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
109604 /* Produces a ALT_USB_DEV_DOEPINT2_AHBERR register field value suitable for setting the register. */
109605 #define ALT_USB_DEV_DOEPINT2_AHBERR_SET(value) (((value) << 2) & 0x00000004)
109606 
109607 /*
109608  * Field : setup
109609  *
109610  * SETUP Phase Done (SetUp)
109611  *
109612  * Applies to control OUT endpoints only.
109613  *
109614  * Indicates that the SETUP phase For the control endpoint is
109615  *
109616  * complete and no more back-to-back SETUP packets were
109617  *
109618  * received For the current control transfer. On this interrupt, the
109619  *
109620  * application can decode the received SETUP data packet.
109621  *
109622  * Field Enumeration Values:
109623  *
109624  * Enum | Value | Description
109625  * :-----------------------------------|:------|:--------------------
109626  * ALT_USB_DEV_DOEPINT2_SETUP_E_INACT | 0x0 | No SETUP Phase Done
109627  * ALT_USB_DEV_DOEPINT2_SETUP_E_ACT | 0x1 | SETUP Phase Done
109628  *
109629  * Field Access Macros:
109630  *
109631  */
109632 /*
109633  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_SETUP
109634  *
109635  * No SETUP Phase Done
109636  */
109637 #define ALT_USB_DEV_DOEPINT2_SETUP_E_INACT 0x0
109638 /*
109639  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_SETUP
109640  *
109641  * SETUP Phase Done
109642  */
109643 #define ALT_USB_DEV_DOEPINT2_SETUP_E_ACT 0x1
109644 
109645 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_SETUP register field. */
109646 #define ALT_USB_DEV_DOEPINT2_SETUP_LSB 3
109647 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_SETUP register field. */
109648 #define ALT_USB_DEV_DOEPINT2_SETUP_MSB 3
109649 /* The width in bits of the ALT_USB_DEV_DOEPINT2_SETUP register field. */
109650 #define ALT_USB_DEV_DOEPINT2_SETUP_WIDTH 1
109651 /* The mask used to set the ALT_USB_DEV_DOEPINT2_SETUP register field value. */
109652 #define ALT_USB_DEV_DOEPINT2_SETUP_SET_MSK 0x00000008
109653 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_SETUP register field value. */
109654 #define ALT_USB_DEV_DOEPINT2_SETUP_CLR_MSK 0xfffffff7
109655 /* The reset value of the ALT_USB_DEV_DOEPINT2_SETUP register field. */
109656 #define ALT_USB_DEV_DOEPINT2_SETUP_RESET 0x0
109657 /* Extracts the ALT_USB_DEV_DOEPINT2_SETUP field value from a register. */
109658 #define ALT_USB_DEV_DOEPINT2_SETUP_GET(value) (((value) & 0x00000008) >> 3)
109659 /* Produces a ALT_USB_DEV_DOEPINT2_SETUP register field value suitable for setting the register. */
109660 #define ALT_USB_DEV_DOEPINT2_SETUP_SET(value) (((value) << 3) & 0x00000008)
109661 
109662 /*
109663  * Field : outtknepdis
109664  *
109665  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
109666  *
109667  * Applies only to control OUT endpoints.
109668  *
109669  * Indicates that an OUT token was received when the endpoint
109670  *
109671  * was not yet enabled. This interrupt is asserted on the endpoint
109672  *
109673  * For which the OUT token was received.
109674  *
109675  * Field Enumeration Values:
109676  *
109677  * Enum | Value | Description
109678  * :-----------------------------------------|:------|:---------------------------------------------
109679  * ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
109680  * ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
109681  *
109682  * Field Access Macros:
109683  *
109684  */
109685 /*
109686  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS
109687  *
109688  * No OUT Token Received When Endpoint Disabled
109689  */
109690 #define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_INACT 0x0
109691 /*
109692  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS
109693  *
109694  * OUT Token Received When Endpoint Disabled
109695  */
109696 #define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_ACT 0x1
109697 
109698 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */
109699 #define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_LSB 4
109700 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */
109701 #define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_MSB 4
109702 /* The width in bits of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */
109703 #define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_WIDTH 1
109704 /* The mask used to set the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field value. */
109705 #define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_SET_MSK 0x00000010
109706 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field value. */
109707 #define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_CLR_MSK 0xffffffef
109708 /* The reset value of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */
109709 #define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_RESET 0x0
109710 /* Extracts the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS field value from a register. */
109711 #define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
109712 /* Produces a ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field value suitable for setting the register. */
109713 #define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
109714 
109715 /*
109716  * Field : stsphsercvd
109717  *
109718  * Status Phase Received For Control Write (StsPhseRcvd)
109719  *
109720  * This interrupt is valid only For Control OUT endpoints and only in
109721  *
109722  * Scatter Gather DMA mode.
109723  *
109724  * This interrupt is generated only after the core has transferred all
109725  *
109726  * the data that the host has sent during the data phase of a control
109727  *
109728  * write transfer, to the system memory buffer.
109729  *
109730  * The interrupt indicates to the application that the host has
109731  *
109732  * switched from data phase to the status phase of a Control Write
109733  *
109734  * transfer. The application can use this interrupt to ACK or STALL
109735  *
109736  * the Status phase, after it has decoded the data phase. This is
109737  *
109738  * applicable only in Case of Scatter Gather DMA mode.
109739  *
109740  * Field Enumeration Values:
109741  *
109742  * Enum | Value | Description
109743  * :-----------------------------------------|:------|:-------------------------------------------
109744  * ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
109745  * ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
109746  *
109747  * Field Access Macros:
109748  *
109749  */
109750 /*
109751  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_STSPHSERCVD
109752  *
109753  * No Status Phase Received for Control Write
109754  */
109755 #define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_INACT 0x0
109756 /*
109757  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_STSPHSERCVD
109758  *
109759  * Status Phase Received for Control Write
109760  */
109761 #define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_ACT 0x1
109762 
109763 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */
109764 #define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_LSB 5
109765 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */
109766 #define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_MSB 5
109767 /* The width in bits of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */
109768 #define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_WIDTH 1
109769 /* The mask used to set the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field value. */
109770 #define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_SET_MSK 0x00000020
109771 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field value. */
109772 #define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_CLR_MSK 0xffffffdf
109773 /* The reset value of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */
109774 #define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_RESET 0x0
109775 /* Extracts the ALT_USB_DEV_DOEPINT2_STSPHSERCVD field value from a register. */
109776 #define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
109777 /* Produces a ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field value suitable for setting the register. */
109778 #define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
109779 
109780 /*
109781  * Field : back2backsetup
109782  *
109783  * Back-to-Back SETUP Packets Received (Back2BackSETup)
109784  *
109785  * Applies to Control OUT endpoints only.
109786  *
109787  * This bit indicates that the core has received more than three
109788  *
109789  * back-to-back SETUP packets For this particular endpoint. For
109790  *
109791  * information about handling this interrupt,
109792  *
109793  * Field Enumeration Values:
109794  *
109795  * Enum | Value | Description
109796  * :--------------------------------------------|:------|:---------------------------------------
109797  * ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
109798  * ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
109799  *
109800  * Field Access Macros:
109801  *
109802  */
109803 /*
109804  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP
109805  *
109806  * No Back-to-Back SETUP Packets Received
109807  */
109808 #define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_INACT 0x0
109809 /*
109810  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP
109811  *
109812  * Back-to-Back SETUP Packets Received
109813  */
109814 #define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_ACT 0x1
109815 
109816 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */
109817 #define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_LSB 6
109818 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */
109819 #define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_MSB 6
109820 /* The width in bits of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */
109821 #define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_WIDTH 1
109822 /* The mask used to set the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field value. */
109823 #define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_SET_MSK 0x00000040
109824 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field value. */
109825 #define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_CLR_MSK 0xffffffbf
109826 /* The reset value of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */
109827 #define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_RESET 0x0
109828 /* Extracts the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP field value from a register. */
109829 #define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
109830 /* Produces a ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field value suitable for setting the register. */
109831 #define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
109832 
109833 /*
109834  * Field : outpkterr
109835  *
109836  * OUT Packet Error (OutPktErr)
109837  *
109838  * Applies to OUT endpoints Only
109839  *
109840  * This interrupt is valid only when thresholding is enabled. This interrupt is
109841  * asserted when the
109842  *
109843  * core detects an overflow or a CRC error For non-Isochronous
109844  *
109845  * OUT packet.
109846  *
109847  * Field Enumeration Values:
109848  *
109849  * Enum | Value | Description
109850  * :---------------------------------------|:------|:--------------------
109851  * ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
109852  * ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
109853  *
109854  * Field Access Macros:
109855  *
109856  */
109857 /*
109858  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTPKTERR
109859  *
109860  * No OUT Packet Error
109861  */
109862 #define ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_INACT 0x0
109863 /*
109864  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTPKTERR
109865  *
109866  * OUT Packet Error
109867  */
109868 #define ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_ACT 0x1
109869 
109870 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */
109871 #define ALT_USB_DEV_DOEPINT2_OUTPKTERR_LSB 8
109872 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */
109873 #define ALT_USB_DEV_DOEPINT2_OUTPKTERR_MSB 8
109874 /* The width in bits of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */
109875 #define ALT_USB_DEV_DOEPINT2_OUTPKTERR_WIDTH 1
109876 /* The mask used to set the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field value. */
109877 #define ALT_USB_DEV_DOEPINT2_OUTPKTERR_SET_MSK 0x00000100
109878 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field value. */
109879 #define ALT_USB_DEV_DOEPINT2_OUTPKTERR_CLR_MSK 0xfffffeff
109880 /* The reset value of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */
109881 #define ALT_USB_DEV_DOEPINT2_OUTPKTERR_RESET 0x0
109882 /* Extracts the ALT_USB_DEV_DOEPINT2_OUTPKTERR field value from a register. */
109883 #define ALT_USB_DEV_DOEPINT2_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
109884 /* Produces a ALT_USB_DEV_DOEPINT2_OUTPKTERR register field value suitable for setting the register. */
109885 #define ALT_USB_DEV_DOEPINT2_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
109886 
109887 /*
109888  * Field : bnaintr
109889  *
109890  * BNA (Buffer Not Available) Interrupt (BNAIntr)
109891  *
109892  * This bit is valid only when Scatter/Gather DMA mode is enabled.
109893  *
109894  * The core generates this interrupt when the descriptor accessed
109895  *
109896  * is not ready For the Core to process, such as Host busy or DMA
109897  *
109898  * done
109899  *
109900  * Field Enumeration Values:
109901  *
109902  * Enum | Value | Description
109903  * :-------------------------------------|:------|:--------------
109904  * ALT_USB_DEV_DOEPINT2_BNAINTR_E_INACT | 0x0 | No interrupt
109905  * ALT_USB_DEV_DOEPINT2_BNAINTR_E_ACT | 0x1 | BNA interrupt
109906  *
109907  * Field Access Macros:
109908  *
109909  */
109910 /*
109911  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BNAINTR
109912  *
109913  * No interrupt
109914  */
109915 #define ALT_USB_DEV_DOEPINT2_BNAINTR_E_INACT 0x0
109916 /*
109917  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BNAINTR
109918  *
109919  * BNA interrupt
109920  */
109921 #define ALT_USB_DEV_DOEPINT2_BNAINTR_E_ACT 0x1
109922 
109923 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */
109924 #define ALT_USB_DEV_DOEPINT2_BNAINTR_LSB 9
109925 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */
109926 #define ALT_USB_DEV_DOEPINT2_BNAINTR_MSB 9
109927 /* The width in bits of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */
109928 #define ALT_USB_DEV_DOEPINT2_BNAINTR_WIDTH 1
109929 /* The mask used to set the ALT_USB_DEV_DOEPINT2_BNAINTR register field value. */
109930 #define ALT_USB_DEV_DOEPINT2_BNAINTR_SET_MSK 0x00000200
109931 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_BNAINTR register field value. */
109932 #define ALT_USB_DEV_DOEPINT2_BNAINTR_CLR_MSK 0xfffffdff
109933 /* The reset value of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */
109934 #define ALT_USB_DEV_DOEPINT2_BNAINTR_RESET 0x0
109935 /* Extracts the ALT_USB_DEV_DOEPINT2_BNAINTR field value from a register. */
109936 #define ALT_USB_DEV_DOEPINT2_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
109937 /* Produces a ALT_USB_DEV_DOEPINT2_BNAINTR register field value suitable for setting the register. */
109938 #define ALT_USB_DEV_DOEPINT2_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
109939 
109940 /*
109941  * Field : pktdrpsts
109942  *
109943  * Packet Drop Status (PktDrpSts)
109944  *
109945  * This bit indicates to the application that an ISOC OUT packet has been dropped.
109946  * This
109947  *
109948  * bit does not have an associated mask bit and does not generate an interrupt.
109949  *
109950  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
109951  * transfer
109952  *
109953  * interrupt feature is selected.
109954  *
109955  * Field Enumeration Values:
109956  *
109957  * Enum | Value | Description
109958  * :---------------------------------------|:------|:-----------------------------
109959  * ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_INACT | 0x0 | No interrupt
109960  * ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
109961  *
109962  * Field Access Macros:
109963  *
109964  */
109965 /*
109966  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_PKTDRPSTS
109967  *
109968  * No interrupt
109969  */
109970 #define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_INACT 0x0
109971 /*
109972  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_PKTDRPSTS
109973  *
109974  * Packet Drop Status interrupt
109975  */
109976 #define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_ACT 0x1
109977 
109978 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */
109979 #define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_LSB 11
109980 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */
109981 #define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_MSB 11
109982 /* The width in bits of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */
109983 #define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_WIDTH 1
109984 /* The mask used to set the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field value. */
109985 #define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_SET_MSK 0x00000800
109986 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field value. */
109987 #define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_CLR_MSK 0xfffff7ff
109988 /* The reset value of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */
109989 #define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_RESET 0x0
109990 /* Extracts the ALT_USB_DEV_DOEPINT2_PKTDRPSTS field value from a register. */
109991 #define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
109992 /* Produces a ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field value suitable for setting the register. */
109993 #define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
109994 
109995 /*
109996  * Field : bbleerr
109997  *
109998  * NAK Interrupt (BbleErr)
109999  *
110000  * The core generates this interrupt when babble is received for the endpoint.
110001  *
110002  * Field Enumeration Values:
110003  *
110004  * Enum | Value | Description
110005  * :-------------------------------------|:------|:------------------
110006  * ALT_USB_DEV_DOEPINT2_BBLEERR_E_INACT | 0x0 | No interrupt
110007  * ALT_USB_DEV_DOEPINT2_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
110008  *
110009  * Field Access Macros:
110010  *
110011  */
110012 /*
110013  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BBLEERR
110014  *
110015  * No interrupt
110016  */
110017 #define ALT_USB_DEV_DOEPINT2_BBLEERR_E_INACT 0x0
110018 /*
110019  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_BBLEERR
110020  *
110021  * BbleErr interrupt
110022  */
110023 #define ALT_USB_DEV_DOEPINT2_BBLEERR_E_ACT 0x1
110024 
110025 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */
110026 #define ALT_USB_DEV_DOEPINT2_BBLEERR_LSB 12
110027 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */
110028 #define ALT_USB_DEV_DOEPINT2_BBLEERR_MSB 12
110029 /* The width in bits of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */
110030 #define ALT_USB_DEV_DOEPINT2_BBLEERR_WIDTH 1
110031 /* The mask used to set the ALT_USB_DEV_DOEPINT2_BBLEERR register field value. */
110032 #define ALT_USB_DEV_DOEPINT2_BBLEERR_SET_MSK 0x00001000
110033 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_BBLEERR register field value. */
110034 #define ALT_USB_DEV_DOEPINT2_BBLEERR_CLR_MSK 0xffffefff
110035 /* The reset value of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */
110036 #define ALT_USB_DEV_DOEPINT2_BBLEERR_RESET 0x0
110037 /* Extracts the ALT_USB_DEV_DOEPINT2_BBLEERR field value from a register. */
110038 #define ALT_USB_DEV_DOEPINT2_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
110039 /* Produces a ALT_USB_DEV_DOEPINT2_BBLEERR register field value suitable for setting the register. */
110040 #define ALT_USB_DEV_DOEPINT2_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
110041 
110042 /*
110043  * Field : nakintrpt
110044  *
110045  * NAK Interrupt (NAKInterrupt)
110046  *
110047  * The core generates this interrupt when a NAK is transmitted or received by the
110048  * device.
110049  *
110050  * In case of isochronous IN endpoints the interrupt gets generated when a zero
110051  * length
110052  *
110053  * packet is transmitted due to un-availability of data in the TXFifo.
110054  *
110055  * Field Enumeration Values:
110056  *
110057  * Enum | Value | Description
110058  * :---------------------------------------|:------|:--------------
110059  * ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_INACT | 0x0 | No interrupt
110060  * ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
110061  *
110062  * Field Access Macros:
110063  *
110064  */
110065 /*
110066  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_NAKINTRPT
110067  *
110068  * No interrupt
110069  */
110070 #define ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_INACT 0x0
110071 /*
110072  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_NAKINTRPT
110073  *
110074  * NAK Interrupt
110075  */
110076 #define ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_ACT 0x1
110077 
110078 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */
110079 #define ALT_USB_DEV_DOEPINT2_NAKINTRPT_LSB 13
110080 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */
110081 #define ALT_USB_DEV_DOEPINT2_NAKINTRPT_MSB 13
110082 /* The width in bits of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */
110083 #define ALT_USB_DEV_DOEPINT2_NAKINTRPT_WIDTH 1
110084 /* The mask used to set the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field value. */
110085 #define ALT_USB_DEV_DOEPINT2_NAKINTRPT_SET_MSK 0x00002000
110086 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field value. */
110087 #define ALT_USB_DEV_DOEPINT2_NAKINTRPT_CLR_MSK 0xffffdfff
110088 /* The reset value of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */
110089 #define ALT_USB_DEV_DOEPINT2_NAKINTRPT_RESET 0x0
110090 /* Extracts the ALT_USB_DEV_DOEPINT2_NAKINTRPT field value from a register. */
110091 #define ALT_USB_DEV_DOEPINT2_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
110092 /* Produces a ALT_USB_DEV_DOEPINT2_NAKINTRPT register field value suitable for setting the register. */
110093 #define ALT_USB_DEV_DOEPINT2_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
110094 
110095 /*
110096  * Field : nyetintrpt
110097  *
110098  * NYET Interrupt (NYETIntrpt)
110099  *
110100  * The core generates this interrupt when a NYET response is transmitted for a non
110101  * isochronous OUT endpoint.
110102  *
110103  * Field Enumeration Values:
110104  *
110105  * Enum | Value | Description
110106  * :----------------------------------------|:------|:---------------
110107  * ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_INACT | 0x0 | No interrupt
110108  * ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
110109  *
110110  * Field Access Macros:
110111  *
110112  */
110113 /*
110114  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_NYETINTRPT
110115  *
110116  * No interrupt
110117  */
110118 #define ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_INACT 0x0
110119 /*
110120  * Enumerated value for register field ALT_USB_DEV_DOEPINT2_NYETINTRPT
110121  *
110122  * NYET Interrupt
110123  */
110124 #define ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_ACT 0x1
110125 
110126 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */
110127 #define ALT_USB_DEV_DOEPINT2_NYETINTRPT_LSB 14
110128 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */
110129 #define ALT_USB_DEV_DOEPINT2_NYETINTRPT_MSB 14
110130 /* The width in bits of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */
110131 #define ALT_USB_DEV_DOEPINT2_NYETINTRPT_WIDTH 1
110132 /* The mask used to set the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field value. */
110133 #define ALT_USB_DEV_DOEPINT2_NYETINTRPT_SET_MSK 0x00004000
110134 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field value. */
110135 #define ALT_USB_DEV_DOEPINT2_NYETINTRPT_CLR_MSK 0xffffbfff
110136 /* The reset value of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */
110137 #define ALT_USB_DEV_DOEPINT2_NYETINTRPT_RESET 0x0
110138 /* Extracts the ALT_USB_DEV_DOEPINT2_NYETINTRPT field value from a register. */
110139 #define ALT_USB_DEV_DOEPINT2_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
110140 /* Produces a ALT_USB_DEV_DOEPINT2_NYETINTRPT register field value suitable for setting the register. */
110141 #define ALT_USB_DEV_DOEPINT2_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
110142 
110143 /*
110144  * Field : stuppktrcvd
110145  *
110146  * Setup Packet Received
110147  *
110148  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
110149  *
110150  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
110151  *
110152  * setup data. There is only one Setup packet per buffer. On receiving a
110153  *
110154  * Setup packet, the DWC_otg core closes the buffer and disables the
110155  *
110156  * corresponding endpoint. The application has to re-enable the endpoint to
110157  *
110158  * receive any OUT data for the Control Transfer and reprogram the buffer
110159  *
110160  * start address.
110161  *
110162  * Note: Because of the above behavior, the DWC_otg core can receive any
110163  *
110164  * number of back to back setup packets and one buffer for every setup
110165  *
110166  * packet is used.
110167  *
110168  * 1'b0: No Setup packet received
110169  *
110170  * 1'b1: Setup packet received
110171  *
110172  * Reset: 1'b0
110173  *
110174  * Field Access Macros:
110175  *
110176  */
110177 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field. */
110178 #define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_LSB 15
110179 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field. */
110180 #define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_MSB 15
110181 /* The width in bits of the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field. */
110182 #define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_WIDTH 1
110183 /* The mask used to set the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field value. */
110184 #define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_SET_MSK 0x00008000
110185 /* The mask used to clear the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field value. */
110186 #define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_CLR_MSK 0xffff7fff
110187 /* The reset value of the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field. */
110188 #define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_RESET 0x0
110189 /* Extracts the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD field value from a register. */
110190 #define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
110191 /* Produces a ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field value suitable for setting the register. */
110192 #define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
110193 
110194 #ifndef __ASSEMBLY__
110195 /*
110196  * WARNING: The C register and register group struct declarations are provided for
110197  * convenience and illustrative purposes. They should, however, be used with
110198  * caution as the C language standard provides no guarantees about the alignment or
110199  * atomicity of device memory accesses. The recommended practice for writing
110200  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
110201  * alt_write_word() functions.
110202  *
110203  * The struct declaration for register ALT_USB_DEV_DOEPINT2.
110204  */
110205 struct ALT_USB_DEV_DOEPINT2_s
110206 {
110207  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT2_XFERCOMPL */
110208  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT2_EPDISBLD */
110209  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT2_AHBERR */
110210  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT2_SETUP */
110211  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS */
110212  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT2_STSPHSERCVD */
110213  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP */
110214  uint32_t : 1; /* *UNDEFINED* */
110215  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT2_OUTPKTERR */
110216  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT2_BNAINTR */
110217  uint32_t : 1; /* *UNDEFINED* */
110218  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT2_PKTDRPSTS */
110219  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT2_BBLEERR */
110220  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT2_NAKINTRPT */
110221  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT2_NYETINTRPT */
110222  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT2_STUPPKTRCVD */
110223  uint32_t : 16; /* *UNDEFINED* */
110224 };
110225 
110226 /* The typedef declaration for register ALT_USB_DEV_DOEPINT2. */
110227 typedef volatile struct ALT_USB_DEV_DOEPINT2_s ALT_USB_DEV_DOEPINT2_t;
110228 #endif /* __ASSEMBLY__ */
110229 
110230 /* The reset value of the ALT_USB_DEV_DOEPINT2 register. */
110231 #define ALT_USB_DEV_DOEPINT2_RESET 0x00000000
110232 /* The byte offset of the ALT_USB_DEV_DOEPINT2 register from the beginning of the component. */
110233 #define ALT_USB_DEV_DOEPINT2_OFST 0x348
110234 /* The address of the ALT_USB_DEV_DOEPINT2 register. */
110235 #define ALT_USB_DEV_DOEPINT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT2_OFST))
110236 
110237 /*
110238  * Register : doeptsiz2
110239  *
110240  * Device OUT Endpoint 2 Transfer Size Register
110241  *
110242  * Register Layout
110243  *
110244  * Bits | Access | Reset | Description
110245  * :--------|:-------|:------|:-------------------------------
110246  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ2_XFERSIZE
110247  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ2_PKTCNT
110248  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ2_RXDPID
110249  * [31] | ??? | 0x0 | *UNDEFINED*
110250  *
110251  */
110252 /*
110253  * Field : xfersize
110254  *
110255  * Transfer Size (XferSize)
110256  *
110257  * Indicates the transfer size in bytes For endpoint 0. The core
110258  *
110259  * interrupts the application only after it has exhausted the transfer
110260  *
110261  * size amount of data. The transfer size can be Set to the
110262  *
110263  * maximum packet size of the endpoint, to be interrupted at the
110264  *
110265  * end of each packet.
110266  *
110267  * The core decrements this field every time a packet is read from
110268  *
110269  * the RxFIFO and written to the external memory.
110270  *
110271  * Field Access Macros:
110272  *
110273  */
110274 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */
110275 #define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_LSB 0
110276 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */
110277 #define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_MSB 18
110278 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */
110279 #define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_WIDTH 19
110280 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field value. */
110281 #define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_SET_MSK 0x0007ffff
110282 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field value. */
110283 #define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_CLR_MSK 0xfff80000
110284 /* The reset value of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */
110285 #define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_RESET 0x0
110286 /* Extracts the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE field value from a register. */
110287 #define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
110288 /* Produces a ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field value suitable for setting the register. */
110289 #define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
110290 
110291 /*
110292  * Field : pktcnt
110293  *
110294  * Packet Count (PktCnt)
110295  *
110296  * This field is decremented to zero after a packet is written into the
110297  *
110298  * RxFIFO.
110299  *
110300  * Field Access Macros:
110301  *
110302  */
110303 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */
110304 #define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_LSB 19
110305 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */
110306 #define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_MSB 28
110307 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */
110308 #define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_WIDTH 10
110309 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field value. */
110310 #define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_SET_MSK 0x1ff80000
110311 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field value. */
110312 #define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_CLR_MSK 0xe007ffff
110313 /* The reset value of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */
110314 #define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_RESET 0x0
110315 /* Extracts the ALT_USB_DEV_DOEPTSIZ2_PKTCNT field value from a register. */
110316 #define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
110317 /* Produces a ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field value suitable for setting the register. */
110318 #define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
110319 
110320 /*
110321  * Field : rxdpid
110322  *
110323  * Applies to isochronous OUT endpoints only.
110324  *
110325  * This is the data PID received in the last packet for this endpoint.
110326  *
110327  * 2'b00: DATA0
110328  *
110329  * 2'b01: DATA2
110330  *
110331  * 2'b10: DATA1
110332  *
110333  * 2'b11: MDATA
110334  *
110335  * SETUP Packet Count (SUPCnt)
110336  *
110337  * Applies to control OUT Endpoints only.
110338  *
110339  * This field specifies the number of back-to-back SETUP data
110340  *
110341  * packets the endpoint can receive.
110342  *
110343  * 2'b01: 1 packet
110344  *
110345  * 2'b10: 2 packets
110346  *
110347  * 2'b11: 3 packets
110348  *
110349  * Field Enumeration Values:
110350  *
110351  * Enum | Value | Description
110352  * :-----------------------------------------|:------|:-------------------
110353  * ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA0 | 0x0 | DATA0
110354  * ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
110355  * ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
110356  * ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
110357  *
110358  * Field Access Macros:
110359  *
110360  */
110361 /*
110362  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID
110363  *
110364  * DATA0
110365  */
110366 #define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA0 0x0
110367 /*
110368  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID
110369  *
110370  * DATA2 or 1 packet
110371  */
110372 #define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA2PKT1 0x1
110373 /*
110374  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID
110375  *
110376  * DATA1 or 2 packets
110377  */
110378 #define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA1PKT2 0x2
110379 /*
110380  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID
110381  *
110382  * MDATA or 3 packets
110383  */
110384 #define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_MDATAPKT3 0x3
110385 
110386 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */
110387 #define ALT_USB_DEV_DOEPTSIZ2_RXDPID_LSB 29
110388 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */
110389 #define ALT_USB_DEV_DOEPTSIZ2_RXDPID_MSB 30
110390 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */
110391 #define ALT_USB_DEV_DOEPTSIZ2_RXDPID_WIDTH 2
110392 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field value. */
110393 #define ALT_USB_DEV_DOEPTSIZ2_RXDPID_SET_MSK 0x60000000
110394 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field value. */
110395 #define ALT_USB_DEV_DOEPTSIZ2_RXDPID_CLR_MSK 0x9fffffff
110396 /* The reset value of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */
110397 #define ALT_USB_DEV_DOEPTSIZ2_RXDPID_RESET 0x0
110398 /* Extracts the ALT_USB_DEV_DOEPTSIZ2_RXDPID field value from a register. */
110399 #define ALT_USB_DEV_DOEPTSIZ2_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
110400 /* Produces a ALT_USB_DEV_DOEPTSIZ2_RXDPID register field value suitable for setting the register. */
110401 #define ALT_USB_DEV_DOEPTSIZ2_RXDPID_SET(value) (((value) << 29) & 0x60000000)
110402 
110403 #ifndef __ASSEMBLY__
110404 /*
110405  * WARNING: The C register and register group struct declarations are provided for
110406  * convenience and illustrative purposes. They should, however, be used with
110407  * caution as the C language standard provides no guarantees about the alignment or
110408  * atomicity of device memory accesses. The recommended practice for writing
110409  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
110410  * alt_write_word() functions.
110411  *
110412  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ2.
110413  */
110414 struct ALT_USB_DEV_DOEPTSIZ2_s
110415 {
110416  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ2_XFERSIZE */
110417  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ2_PKTCNT */
110418  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ2_RXDPID */
110419  uint32_t : 1; /* *UNDEFINED* */
110420 };
110421 
110422 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ2. */
110423 typedef volatile struct ALT_USB_DEV_DOEPTSIZ2_s ALT_USB_DEV_DOEPTSIZ2_t;
110424 #endif /* __ASSEMBLY__ */
110425 
110426 /* The reset value of the ALT_USB_DEV_DOEPTSIZ2 register. */
110427 #define ALT_USB_DEV_DOEPTSIZ2_RESET 0x00000000
110428 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ2 register from the beginning of the component. */
110429 #define ALT_USB_DEV_DOEPTSIZ2_OFST 0x350
110430 /* The address of the ALT_USB_DEV_DOEPTSIZ2 register. */
110431 #define ALT_USB_DEV_DOEPTSIZ2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ2_OFST))
110432 
110433 /*
110434  * Register : doepdma2
110435  *
110436  * Device OUT Endpoint 2 DMA Address Register
110437  *
110438  * Register Layout
110439  *
110440  * Bits | Access | Reset | Description
110441  * :-------|:-------|:--------|:------------------------------
110442  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA2_DOEPDMA2
110443  *
110444  */
110445 /*
110446  * Field : doepdma2
110447  *
110448  * Holds the start address of the external memory for storing or fetching endpoint
110449  *
110450  * data.
110451  *
110452  * Note: For control endpoints, this field stores control OUT data packets as well
110453  * as
110454  *
110455  * SETUP transaction data packets. When more than three SETUP packets are
110456  *
110457  * received back-to-back, the SETUP data packet in the memory is overwritten.
110458  *
110459  * This register is incremented on every AHB transaction. The application can give
110460  *
110461  * only a DWORD-aligned address.
110462  *
110463  * When Scatter/Gather DMA mode is not enabled, the application programs the
110464  *
110465  * start address value in this field.
110466  *
110467  * When Scatter/Gather DMA mode is enabled, this field indicates the base
110468  *
110469  * pointer for the descriptor list.
110470  *
110471  * Field Access Macros:
110472  *
110473  */
110474 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field. */
110475 #define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_LSB 0
110476 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field. */
110477 #define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_MSB 31
110478 /* The width in bits of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field. */
110479 #define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_WIDTH 32
110480 /* The mask used to set the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field value. */
110481 #define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_SET_MSK 0xffffffff
110482 /* The mask used to clear the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field value. */
110483 #define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_CLR_MSK 0x00000000
110484 /* The reset value of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field is UNKNOWN. */
110485 #define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_RESET 0x0
110486 /* Extracts the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 field value from a register. */
110487 #define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_GET(value) (((value) & 0xffffffff) >> 0)
110488 /* Produces a ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field value suitable for setting the register. */
110489 #define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_SET(value) (((value) << 0) & 0xffffffff)
110490 
110491 #ifndef __ASSEMBLY__
110492 /*
110493  * WARNING: The C register and register group struct declarations are provided for
110494  * convenience and illustrative purposes. They should, however, be used with
110495  * caution as the C language standard provides no guarantees about the alignment or
110496  * atomicity of device memory accesses. The recommended practice for writing
110497  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
110498  * alt_write_word() functions.
110499  *
110500  * The struct declaration for register ALT_USB_DEV_DOEPDMA2.
110501  */
110502 struct ALT_USB_DEV_DOEPDMA2_s
110503 {
110504  uint32_t doepdma2 : 32; /* ALT_USB_DEV_DOEPDMA2_DOEPDMA2 */
110505 };
110506 
110507 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA2. */
110508 typedef volatile struct ALT_USB_DEV_DOEPDMA2_s ALT_USB_DEV_DOEPDMA2_t;
110509 #endif /* __ASSEMBLY__ */
110510 
110511 /* The reset value of the ALT_USB_DEV_DOEPDMA2 register. */
110512 #define ALT_USB_DEV_DOEPDMA2_RESET 0x00000000
110513 /* The byte offset of the ALT_USB_DEV_DOEPDMA2 register from the beginning of the component. */
110514 #define ALT_USB_DEV_DOEPDMA2_OFST 0x354
110515 /* The address of the ALT_USB_DEV_DOEPDMA2 register. */
110516 #define ALT_USB_DEV_DOEPDMA2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA2_OFST))
110517 
110518 /*
110519  * Register : doepdmab2
110520  *
110521  * Device OUT Endpoint 2 Buffer Address Register
110522  *
110523  * Register Layout
110524  *
110525  * Bits | Access | Reset | Description
110526  * :-------|:-------|:--------|:--------------------------------
110527  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2
110528  *
110529  */
110530 /*
110531  * Field : doepdmab2
110532  *
110533  * Holds the current buffer address.This register is updated as and when the data
110534  *
110535  * transfer for the corresponding end point is in progress.
110536  *
110537  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
110538  * is
110539  *
110540  * reserved.
110541  *
110542  * Field Access Macros:
110543  *
110544  */
110545 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field. */
110546 #define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_LSB 0
110547 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field. */
110548 #define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_MSB 31
110549 /* The width in bits of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field. */
110550 #define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_WIDTH 32
110551 /* The mask used to set the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field value. */
110552 #define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_SET_MSK 0xffffffff
110553 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field value. */
110554 #define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_CLR_MSK 0x00000000
110555 /* The reset value of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field is UNKNOWN. */
110556 #define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_RESET 0x0
110557 /* Extracts the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 field value from a register. */
110558 #define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_GET(value) (((value) & 0xffffffff) >> 0)
110559 /* Produces a ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field value suitable for setting the register. */
110560 #define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_SET(value) (((value) << 0) & 0xffffffff)
110561 
110562 #ifndef __ASSEMBLY__
110563 /*
110564  * WARNING: The C register and register group struct declarations are provided for
110565  * convenience and illustrative purposes. They should, however, be used with
110566  * caution as the C language standard provides no guarantees about the alignment or
110567  * atomicity of device memory accesses. The recommended practice for writing
110568  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
110569  * alt_write_word() functions.
110570  *
110571  * The struct declaration for register ALT_USB_DEV_DOEPDMAB2.
110572  */
110573 struct ALT_USB_DEV_DOEPDMAB2_s
110574 {
110575  const uint32_t doepdmab2 : 32; /* ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 */
110576 };
110577 
110578 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB2. */
110579 typedef volatile struct ALT_USB_DEV_DOEPDMAB2_s ALT_USB_DEV_DOEPDMAB2_t;
110580 #endif /* __ASSEMBLY__ */
110581 
110582 /* The reset value of the ALT_USB_DEV_DOEPDMAB2 register. */
110583 #define ALT_USB_DEV_DOEPDMAB2_RESET 0x00000000
110584 /* The byte offset of the ALT_USB_DEV_DOEPDMAB2 register from the beginning of the component. */
110585 #define ALT_USB_DEV_DOEPDMAB2_OFST 0x35c
110586 /* The address of the ALT_USB_DEV_DOEPDMAB2 register. */
110587 #define ALT_USB_DEV_DOEPDMAB2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB2_OFST))
110588 
110589 /*
110590  * Register : doepctl3
110591  *
110592  * Device Control OUT Endpoint 3 Control Register
110593  *
110594  * Register Layout
110595  *
110596  * Bits | Access | Reset | Description
110597  * :--------|:---------|:------|:------------------------------
110598  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL3_MPS
110599  * [14:11] | ??? | 0x0 | *UNDEFINED*
110600  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL3_USBACTEP
110601  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL3_DPID
110602  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL3_NAKSTS
110603  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL3_EPTYPE
110604  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL3_SNP
110605  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL3_STALL
110606  * [25:22] | ??? | 0x0 | *UNDEFINED*
110607  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL3_CNAK
110608  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL3_SNAK
110609  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL3_SETD0PID
110610  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL3_SETD1PID
110611  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL3_EPDIS
110612  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL3_EPENA
110613  *
110614  */
110615 /*
110616  * Field : mps
110617  *
110618  * Maximum Packet Size (MPS)
110619  *
110620  * The application must program this field with the maximum packet size for the
110621  * current
110622  *
110623  * logical endpoint. This value is in bytes.
110624  *
110625  * Field Access Macros:
110626  *
110627  */
110628 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_MPS register field. */
110629 #define ALT_USB_DEV_DOEPCTL3_MPS_LSB 0
110630 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_MPS register field. */
110631 #define ALT_USB_DEV_DOEPCTL3_MPS_MSB 10
110632 /* The width in bits of the ALT_USB_DEV_DOEPCTL3_MPS register field. */
110633 #define ALT_USB_DEV_DOEPCTL3_MPS_WIDTH 11
110634 /* The mask used to set the ALT_USB_DEV_DOEPCTL3_MPS register field value. */
110635 #define ALT_USB_DEV_DOEPCTL3_MPS_SET_MSK 0x000007ff
110636 /* The mask used to clear the ALT_USB_DEV_DOEPCTL3_MPS register field value. */
110637 #define ALT_USB_DEV_DOEPCTL3_MPS_CLR_MSK 0xfffff800
110638 /* The reset value of the ALT_USB_DEV_DOEPCTL3_MPS register field. */
110639 #define ALT_USB_DEV_DOEPCTL3_MPS_RESET 0x0
110640 /* Extracts the ALT_USB_DEV_DOEPCTL3_MPS field value from a register. */
110641 #define ALT_USB_DEV_DOEPCTL3_MPS_GET(value) (((value) & 0x000007ff) >> 0)
110642 /* Produces a ALT_USB_DEV_DOEPCTL3_MPS register field value suitable for setting the register. */
110643 #define ALT_USB_DEV_DOEPCTL3_MPS_SET(value) (((value) << 0) & 0x000007ff)
110644 
110645 /*
110646  * Field : usbactep
110647  *
110648  * USB Active Endpoint (USBActEP)
110649  *
110650  * Indicates whether this endpoint is active in the current configuration and
110651  * interface. The
110652  *
110653  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
110654  * reset. After
110655  *
110656  * receiving the SetConfiguration and SetInterface commands, the application must
110657  *
110658  * program endpoint registers accordingly and set this bit.
110659  *
110660  * Field Enumeration Values:
110661  *
110662  * Enum | Value | Description
110663  * :-------------------------------------|:------|:--------------------
110664  * ALT_USB_DEV_DOEPCTL3_USBACTEP_E_DISD | 0x0 | Not Active
110665  * ALT_USB_DEV_DOEPCTL3_USBACTEP_E_END | 0x1 | USB Active Endpoint
110666  *
110667  * Field Access Macros:
110668  *
110669  */
110670 /*
110671  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_USBACTEP
110672  *
110673  * Not Active
110674  */
110675 #define ALT_USB_DEV_DOEPCTL3_USBACTEP_E_DISD 0x0
110676 /*
110677  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_USBACTEP
110678  *
110679  * USB Active Endpoint
110680  */
110681 #define ALT_USB_DEV_DOEPCTL3_USBACTEP_E_END 0x1
110682 
110683 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */
110684 #define ALT_USB_DEV_DOEPCTL3_USBACTEP_LSB 15
110685 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */
110686 #define ALT_USB_DEV_DOEPCTL3_USBACTEP_MSB 15
110687 /* The width in bits of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */
110688 #define ALT_USB_DEV_DOEPCTL3_USBACTEP_WIDTH 1
110689 /* The mask used to set the ALT_USB_DEV_DOEPCTL3_USBACTEP register field value. */
110690 #define ALT_USB_DEV_DOEPCTL3_USBACTEP_SET_MSK 0x00008000
110691 /* The mask used to clear the ALT_USB_DEV_DOEPCTL3_USBACTEP register field value. */
110692 #define ALT_USB_DEV_DOEPCTL3_USBACTEP_CLR_MSK 0xffff7fff
110693 /* The reset value of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */
110694 #define ALT_USB_DEV_DOEPCTL3_USBACTEP_RESET 0x0
110695 /* Extracts the ALT_USB_DEV_DOEPCTL3_USBACTEP field value from a register. */
110696 #define ALT_USB_DEV_DOEPCTL3_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
110697 /* Produces a ALT_USB_DEV_DOEPCTL3_USBACTEP register field value suitable for setting the register. */
110698 #define ALT_USB_DEV_DOEPCTL3_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
110699 
110700 /*
110701  * Field : dpid
110702  *
110703  * Endpoint Data PID (DPID)
110704  *
110705  * Applies to interrupt/bulk IN and OUT endpoints only.
110706  *
110707  * Contains the PID of the packet to be received or transmitted on this endpoint.
110708  * The
110709  *
110710  * application must program the PID of the first packet to be received or
110711  * transmitted on
110712  *
110713  * this endpoint, after the endpoint is activated. The applications use the
110714  * SetD1PID and
110715  *
110716  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
110717  *
110718  * 1'b0: DATA0
110719  *
110720  * 1'b1: DATA1
110721  *
110722  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
110723  *
110724  * DMA mode.
110725  *
110726  * 1'b0 RO
110727  *
110728  * Even/Odd (Micro)Frame (EO_FrNum)
110729  *
110730  * In non-Scatter/Gather DMA mode:
110731  *
110732  * Applies to isochronous IN and OUT endpoints only.
110733  *
110734  * Indicates the (micro)frame number in which the core transmits/receives
110735  * isochronous
110736  *
110737  * data for this endpoint. The application must program the even/odd (micro) frame
110738  *
110739  * number in which it intends to transmit/receive isochronous data for this
110740  * endpoint using
110741  *
110742  * the SetEvnFr and SetOddFr fields in this register.
110743  *
110744  * 1'b0: Even (micro)frame
110745  *
110746  * 1'b1: Odd (micro)frame
110747  *
110748  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
110749  * number
110750  *
110751  * in which to send data is provided in the transmit descriptor structure. The
110752  * frame in
110753  *
110754  * which data is received is updated in receive descriptor structure.
110755  *
110756  * Field Enumeration Values:
110757  *
110758  * Enum | Value | Description
110759  * :----------------------------------|:------|:-----------------------------
110760  * ALT_USB_DEV_DOEPCTL3_DPID_E_INACT | 0x0 | Endpoint Data PID not active
110761  * ALT_USB_DEV_DOEPCTL3_DPID_E_ACT | 0x1 | Endpoint Data PID active
110762  *
110763  * Field Access Macros:
110764  *
110765  */
110766 /*
110767  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_DPID
110768  *
110769  * Endpoint Data PID not active
110770  */
110771 #define ALT_USB_DEV_DOEPCTL3_DPID_E_INACT 0x0
110772 /*
110773  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_DPID
110774  *
110775  * Endpoint Data PID active
110776  */
110777 #define ALT_USB_DEV_DOEPCTL3_DPID_E_ACT 0x1
110778 
110779 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_DPID register field. */
110780 #define ALT_USB_DEV_DOEPCTL3_DPID_LSB 16
110781 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_DPID register field. */
110782 #define ALT_USB_DEV_DOEPCTL3_DPID_MSB 16
110783 /* The width in bits of the ALT_USB_DEV_DOEPCTL3_DPID register field. */
110784 #define ALT_USB_DEV_DOEPCTL3_DPID_WIDTH 1
110785 /* The mask used to set the ALT_USB_DEV_DOEPCTL3_DPID register field value. */
110786 #define ALT_USB_DEV_DOEPCTL3_DPID_SET_MSK 0x00010000
110787 /* The mask used to clear the ALT_USB_DEV_DOEPCTL3_DPID register field value. */
110788 #define ALT_USB_DEV_DOEPCTL3_DPID_CLR_MSK 0xfffeffff
110789 /* The reset value of the ALT_USB_DEV_DOEPCTL3_DPID register field. */
110790 #define ALT_USB_DEV_DOEPCTL3_DPID_RESET 0x0
110791 /* Extracts the ALT_USB_DEV_DOEPCTL3_DPID field value from a register. */
110792 #define ALT_USB_DEV_DOEPCTL3_DPID_GET(value) (((value) & 0x00010000) >> 16)
110793 /* Produces a ALT_USB_DEV_DOEPCTL3_DPID register field value suitable for setting the register. */
110794 #define ALT_USB_DEV_DOEPCTL3_DPID_SET(value) (((value) << 16) & 0x00010000)
110795 
110796 /*
110797  * Field : naksts
110798  *
110799  * NAK Status (NAKSts)
110800  *
110801  * Indicates the following:
110802  *
110803  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
110804  *
110805  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
110806  *
110807  * When either the application or the core sets this bit:
110808  *
110809  * The core stops receiving any data on an OUT endpoint, even if there is space in
110810  *
110811  * the RxFIFO to accommodate the incoming packet.
110812  *
110813  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
110814  *
110815  * endpoint, even if there data is available in the TxFIFO.
110816  *
110817  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
110818  *
110819  * if there data is available in the TxFIFO.
110820  *
110821  * Irrespective of this bit's setting, the core always responds to SETUP data
110822  * packets with
110823  *
110824  * an ACK handshake.
110825  *
110826  * Field Enumeration Values:
110827  *
110828  * Enum | Value | Description
110829  * :-------------------------------------|:------|:------------------------------------------------
110830  * ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
110831  * : | | based on the FIFO status
110832  * ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
110833  * : | | endpoint
110834  *
110835  * Field Access Macros:
110836  *
110837  */
110838 /*
110839  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_NAKSTS
110840  *
110841  * The core is transmitting non-NAK handshakes based on the FIFO status
110842  */
110843 #define ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NONNAK 0x0
110844 /*
110845  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_NAKSTS
110846  *
110847  * The core is transmitting NAK handshakes on this endpoint
110848  */
110849 #define ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NAK 0x1
110850 
110851 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */
110852 #define ALT_USB_DEV_DOEPCTL3_NAKSTS_LSB 17
110853 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */
110854 #define ALT_USB_DEV_DOEPCTL3_NAKSTS_MSB 17
110855 /* The width in bits of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */
110856 #define ALT_USB_DEV_DOEPCTL3_NAKSTS_WIDTH 1
110857 /* The mask used to set the ALT_USB_DEV_DOEPCTL3_NAKSTS register field value. */
110858 #define ALT_USB_DEV_DOEPCTL3_NAKSTS_SET_MSK 0x00020000
110859 /* The mask used to clear the ALT_USB_DEV_DOEPCTL3_NAKSTS register field value. */
110860 #define ALT_USB_DEV_DOEPCTL3_NAKSTS_CLR_MSK 0xfffdffff
110861 /* The reset value of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */
110862 #define ALT_USB_DEV_DOEPCTL3_NAKSTS_RESET 0x0
110863 /* Extracts the ALT_USB_DEV_DOEPCTL3_NAKSTS field value from a register. */
110864 #define ALT_USB_DEV_DOEPCTL3_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
110865 /* Produces a ALT_USB_DEV_DOEPCTL3_NAKSTS register field value suitable for setting the register. */
110866 #define ALT_USB_DEV_DOEPCTL3_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
110867 
110868 /*
110869  * Field : eptype
110870  *
110871  * Endpoint Type (EPType)
110872  *
110873  * This is the transfer type supported by this logical endpoint.
110874  *
110875  * 2'b00: Control
110876  *
110877  * 2'b01: Isochronous
110878  *
110879  * 2'b10: Bulk
110880  *
110881  * 2'b11: Interrupt
110882  *
110883  * Field Enumeration Values:
110884  *
110885  * Enum | Value | Description
110886  * :------------------------------------------|:------|:------------
110887  * ALT_USB_DEV_DOEPCTL3_EPTYPE_E_CTL | 0x0 | Control
110888  * ALT_USB_DEV_DOEPCTL3_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
110889  * ALT_USB_DEV_DOEPCTL3_EPTYPE_E_BULK | 0x2 | Bulk
110890  * ALT_USB_DEV_DOEPCTL3_EPTYPE_E_INTERRUP | 0x3 | Interrupt
110891  *
110892  * Field Access Macros:
110893  *
110894  */
110895 /*
110896  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE
110897  *
110898  * Control
110899  */
110900 #define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_CTL 0x0
110901 /*
110902  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE
110903  *
110904  * Isochronous
110905  */
110906 #define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_ISOCHRONOUS 0x1
110907 /*
110908  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE
110909  *
110910  * Bulk
110911  */
110912 #define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_BULK 0x2
110913 /*
110914  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE
110915  *
110916  * Interrupt
110917  */
110918 #define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_INTERRUP 0x3
110919 
110920 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */
110921 #define ALT_USB_DEV_DOEPCTL3_EPTYPE_LSB 18
110922 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */
110923 #define ALT_USB_DEV_DOEPCTL3_EPTYPE_MSB 19
110924 /* The width in bits of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */
110925 #define ALT_USB_DEV_DOEPCTL3_EPTYPE_WIDTH 2
110926 /* The mask used to set the ALT_USB_DEV_DOEPCTL3_EPTYPE register field value. */
110927 #define ALT_USB_DEV_DOEPCTL3_EPTYPE_SET_MSK 0x000c0000
110928 /* The mask used to clear the ALT_USB_DEV_DOEPCTL3_EPTYPE register field value. */
110929 #define ALT_USB_DEV_DOEPCTL3_EPTYPE_CLR_MSK 0xfff3ffff
110930 /* The reset value of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */
110931 #define ALT_USB_DEV_DOEPCTL3_EPTYPE_RESET 0x0
110932 /* Extracts the ALT_USB_DEV_DOEPCTL3_EPTYPE field value from a register. */
110933 #define ALT_USB_DEV_DOEPCTL3_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
110934 /* Produces a ALT_USB_DEV_DOEPCTL3_EPTYPE register field value suitable for setting the register. */
110935 #define ALT_USB_DEV_DOEPCTL3_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
110936 
110937 /*
110938  * Field : snp
110939  *
110940  * Snoop Mode (Snp)
110941  *
110942  * Applies to OUT endpoints only.
110943  *
110944  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
110945  *
110946  * check the correctness of OUT packets before transferring them to application
110947  * memory.
110948  *
110949  * Field Enumeration Values:
110950  *
110951  * Enum | Value | Description
110952  * :-------------------------------|:------|:-------------------
110953  * ALT_USB_DEV_DOEPCTL3_SNP_E_DIS | 0x0 | Disable Snoop Mode
110954  * ALT_USB_DEV_DOEPCTL3_SNP_E_EN | 0x1 | Enable Snoop Mode
110955  *
110956  * Field Access Macros:
110957  *
110958  */
110959 /*
110960  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNP
110961  *
110962  * Disable Snoop Mode
110963  */
110964 #define ALT_USB_DEV_DOEPCTL3_SNP_E_DIS 0x0
110965 /*
110966  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNP
110967  *
110968  * Enable Snoop Mode
110969  */
110970 #define ALT_USB_DEV_DOEPCTL3_SNP_E_EN 0x1
110971 
110972 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SNP register field. */
110973 #define ALT_USB_DEV_DOEPCTL3_SNP_LSB 20
110974 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SNP register field. */
110975 #define ALT_USB_DEV_DOEPCTL3_SNP_MSB 20
110976 /* The width in bits of the ALT_USB_DEV_DOEPCTL3_SNP register field. */
110977 #define ALT_USB_DEV_DOEPCTL3_SNP_WIDTH 1
110978 /* The mask used to set the ALT_USB_DEV_DOEPCTL3_SNP register field value. */
110979 #define ALT_USB_DEV_DOEPCTL3_SNP_SET_MSK 0x00100000
110980 /* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SNP register field value. */
110981 #define ALT_USB_DEV_DOEPCTL3_SNP_CLR_MSK 0xffefffff
110982 /* The reset value of the ALT_USB_DEV_DOEPCTL3_SNP register field. */
110983 #define ALT_USB_DEV_DOEPCTL3_SNP_RESET 0x0
110984 /* Extracts the ALT_USB_DEV_DOEPCTL3_SNP field value from a register. */
110985 #define ALT_USB_DEV_DOEPCTL3_SNP_GET(value) (((value) & 0x00100000) >> 20)
110986 /* Produces a ALT_USB_DEV_DOEPCTL3_SNP register field value suitable for setting the register. */
110987 #define ALT_USB_DEV_DOEPCTL3_SNP_SET(value) (((value) << 20) & 0x00100000)
110988 
110989 /*
110990  * Field : stall
110991  *
110992  * STALL Handshake (Stall)
110993  *
110994  * Applies to non-control, non-isochronous IN and OUT endpoints only.
110995  *
110996  * The application sets this bit to stall all tokens from the USB host to this
110997  * endpoint. If a
110998  *
110999  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
111000  * bit, the
111001  *
111002  * STALL bit takes priority. Only the application can clear this bit, never the
111003  * core.
111004  *
111005  * 1'b0 R_W
111006  *
111007  * Applies to control endpoints only.
111008  *
111009  * The application can only set this bit, and the core clears it, when a SETUP
111010  * token is
111011  *
111012  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
111013  * OUT
111014  *
111015  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
111016  * this bit's
111017  *
111018  * setting, the core always responds to SETUP data packets with an ACK handshake.
111019  *
111020  * Field Enumeration Values:
111021  *
111022  * Enum | Value | Description
111023  * :-----------------------------------|:------|:----------------------------
111024  * ALT_USB_DEV_DOEPCTL3_STALL_E_INACT | 0x0 | STALL All Tokens not active
111025  * ALT_USB_DEV_DOEPCTL3_STALL_E_ACT | 0x1 | STALL All Tokens active
111026  *
111027  * Field Access Macros:
111028  *
111029  */
111030 /*
111031  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_STALL
111032  *
111033  * STALL All Tokens not active
111034  */
111035 #define ALT_USB_DEV_DOEPCTL3_STALL_E_INACT 0x0
111036 /*
111037  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_STALL
111038  *
111039  * STALL All Tokens active
111040  */
111041 #define ALT_USB_DEV_DOEPCTL3_STALL_E_ACT 0x1
111042 
111043 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_STALL register field. */
111044 #define ALT_USB_DEV_DOEPCTL3_STALL_LSB 21
111045 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_STALL register field. */
111046 #define ALT_USB_DEV_DOEPCTL3_STALL_MSB 21
111047 /* The width in bits of the ALT_USB_DEV_DOEPCTL3_STALL register field. */
111048 #define ALT_USB_DEV_DOEPCTL3_STALL_WIDTH 1
111049 /* The mask used to set the ALT_USB_DEV_DOEPCTL3_STALL register field value. */
111050 #define ALT_USB_DEV_DOEPCTL3_STALL_SET_MSK 0x00200000
111051 /* The mask used to clear the ALT_USB_DEV_DOEPCTL3_STALL register field value. */
111052 #define ALT_USB_DEV_DOEPCTL3_STALL_CLR_MSK 0xffdfffff
111053 /* The reset value of the ALT_USB_DEV_DOEPCTL3_STALL register field. */
111054 #define ALT_USB_DEV_DOEPCTL3_STALL_RESET 0x0
111055 /* Extracts the ALT_USB_DEV_DOEPCTL3_STALL field value from a register. */
111056 #define ALT_USB_DEV_DOEPCTL3_STALL_GET(value) (((value) & 0x00200000) >> 21)
111057 /* Produces a ALT_USB_DEV_DOEPCTL3_STALL register field value suitable for setting the register. */
111058 #define ALT_USB_DEV_DOEPCTL3_STALL_SET(value) (((value) << 21) & 0x00200000)
111059 
111060 /*
111061  * Field : cnak
111062  *
111063  * Clear NAK (CNAK)
111064  *
111065  * A write to this bit clears the NAK bit For the endpoint.
111066  *
111067  * Field Enumeration Values:
111068  *
111069  * Enum | Value | Description
111070  * :----------------------------------|:------|:-------------
111071  * ALT_USB_DEV_DOEPCTL3_CNAK_E_INACT | 0x0 | No Clear NAK
111072  * ALT_USB_DEV_DOEPCTL3_CNAK_E_ACT | 0x1 | Clear NAK
111073  *
111074  * Field Access Macros:
111075  *
111076  */
111077 /*
111078  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_CNAK
111079  *
111080  * No Clear NAK
111081  */
111082 #define ALT_USB_DEV_DOEPCTL3_CNAK_E_INACT 0x0
111083 /*
111084  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_CNAK
111085  *
111086  * Clear NAK
111087  */
111088 #define ALT_USB_DEV_DOEPCTL3_CNAK_E_ACT 0x1
111089 
111090 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */
111091 #define ALT_USB_DEV_DOEPCTL3_CNAK_LSB 26
111092 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */
111093 #define ALT_USB_DEV_DOEPCTL3_CNAK_MSB 26
111094 /* The width in bits of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */
111095 #define ALT_USB_DEV_DOEPCTL3_CNAK_WIDTH 1
111096 /* The mask used to set the ALT_USB_DEV_DOEPCTL3_CNAK register field value. */
111097 #define ALT_USB_DEV_DOEPCTL3_CNAK_SET_MSK 0x04000000
111098 /* The mask used to clear the ALT_USB_DEV_DOEPCTL3_CNAK register field value. */
111099 #define ALT_USB_DEV_DOEPCTL3_CNAK_CLR_MSK 0xfbffffff
111100 /* The reset value of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */
111101 #define ALT_USB_DEV_DOEPCTL3_CNAK_RESET 0x0
111102 /* Extracts the ALT_USB_DEV_DOEPCTL3_CNAK field value from a register. */
111103 #define ALT_USB_DEV_DOEPCTL3_CNAK_GET(value) (((value) & 0x04000000) >> 26)
111104 /* Produces a ALT_USB_DEV_DOEPCTL3_CNAK register field value suitable for setting the register. */
111105 #define ALT_USB_DEV_DOEPCTL3_CNAK_SET(value) (((value) << 26) & 0x04000000)
111106 
111107 /*
111108  * Field : snak
111109  *
111110  * Set NAK (SNAK)
111111  *
111112  * A write to this bit sets the NAK bit For the endpoint.
111113  *
111114  * Using this bit, the application can control the transmission of NAK
111115  *
111116  * handshakes on an endpoint. The core can also Set this bit For an
111117  *
111118  * endpoint after a SETUP packet is received on that endpoint.
111119  *
111120  * Field Enumeration Values:
111121  *
111122  * Enum | Value | Description
111123  * :----------------------------------|:------|:------------
111124  * ALT_USB_DEV_DOEPCTL3_SNAK_E_INACT | 0x0 | No Set NAK
111125  * ALT_USB_DEV_DOEPCTL3_SNAK_E_ACT | 0x1 | Set NAK
111126  *
111127  * Field Access Macros:
111128  *
111129  */
111130 /*
111131  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNAK
111132  *
111133  * No Set NAK
111134  */
111135 #define ALT_USB_DEV_DOEPCTL3_SNAK_E_INACT 0x0
111136 /*
111137  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNAK
111138  *
111139  * Set NAK
111140  */
111141 #define ALT_USB_DEV_DOEPCTL3_SNAK_E_ACT 0x1
111142 
111143 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */
111144 #define ALT_USB_DEV_DOEPCTL3_SNAK_LSB 27
111145 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */
111146 #define ALT_USB_DEV_DOEPCTL3_SNAK_MSB 27
111147 /* The width in bits of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */
111148 #define ALT_USB_DEV_DOEPCTL3_SNAK_WIDTH 1
111149 /* The mask used to set the ALT_USB_DEV_DOEPCTL3_SNAK register field value. */
111150 #define ALT_USB_DEV_DOEPCTL3_SNAK_SET_MSK 0x08000000
111151 /* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SNAK register field value. */
111152 #define ALT_USB_DEV_DOEPCTL3_SNAK_CLR_MSK 0xf7ffffff
111153 /* The reset value of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */
111154 #define ALT_USB_DEV_DOEPCTL3_SNAK_RESET 0x0
111155 /* Extracts the ALT_USB_DEV_DOEPCTL3_SNAK field value from a register. */
111156 #define ALT_USB_DEV_DOEPCTL3_SNAK_GET(value) (((value) & 0x08000000) >> 27)
111157 /* Produces a ALT_USB_DEV_DOEPCTL3_SNAK register field value suitable for setting the register. */
111158 #define ALT_USB_DEV_DOEPCTL3_SNAK_SET(value) (((value) << 27) & 0x08000000)
111159 
111160 /*
111161  * Field : setd0pid
111162  *
111163  * Set DATA0 PID (SetD0PID)
111164  *
111165  * Applies to interrupt/bulk IN and OUT endpoints only.
111166  *
111167  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
111168  * to DATA0.
111169  *
111170  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
111171  *
111172  * DMA mode.
111173  *
111174  * 1'b0 WO
111175  *
111176  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
111177  *
111178  * Applies to isochronous IN and OUT endpoints only.
111179  *
111180  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
111181  * (micro)
111182  *
111183  * frame.
111184  *
111185  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
111186  * number
111187  *
111188  * in which to send data is in the transmit descriptor structure. The frame in
111189  * which to
111190  *
111191  * receive data is updated in receive descriptor structure.
111192  *
111193  * Field Enumeration Values:
111194  *
111195  * Enum | Value | Description
111196  * :-------------------------------------|:------|:------------------------------------
111197  * ALT_USB_DEV_DOEPCTL3_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
111198  * ALT_USB_DEV_DOEPCTL3_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
111199  *
111200  * Field Access Macros:
111201  *
111202  */
111203 /*
111204  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD0PID
111205  *
111206  * Disables Set DATA0 PID
111207  */
111208 #define ALT_USB_DEV_DOEPCTL3_SETD0PID_E_DISD 0x0
111209 /*
111210  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD0PID
111211  *
111212  * Enables Endpoint Data PID to DATA0)
111213  */
111214 #define ALT_USB_DEV_DOEPCTL3_SETD0PID_E_END 0x1
111215 
111216 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */
111217 #define ALT_USB_DEV_DOEPCTL3_SETD0PID_LSB 28
111218 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */
111219 #define ALT_USB_DEV_DOEPCTL3_SETD0PID_MSB 28
111220 /* The width in bits of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */
111221 #define ALT_USB_DEV_DOEPCTL3_SETD0PID_WIDTH 1
111222 /* The mask used to set the ALT_USB_DEV_DOEPCTL3_SETD0PID register field value. */
111223 #define ALT_USB_DEV_DOEPCTL3_SETD0PID_SET_MSK 0x10000000
111224 /* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SETD0PID register field value. */
111225 #define ALT_USB_DEV_DOEPCTL3_SETD0PID_CLR_MSK 0xefffffff
111226 /* The reset value of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */
111227 #define ALT_USB_DEV_DOEPCTL3_SETD0PID_RESET 0x0
111228 /* Extracts the ALT_USB_DEV_DOEPCTL3_SETD0PID field value from a register. */
111229 #define ALT_USB_DEV_DOEPCTL3_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
111230 /* Produces a ALT_USB_DEV_DOEPCTL3_SETD0PID register field value suitable for setting the register. */
111231 #define ALT_USB_DEV_DOEPCTL3_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
111232 
111233 /*
111234  * Field : setd1pid
111235  *
111236  * Set DATA1 PID (SetD1PID)
111237  *
111238  * Applies to interrupt/bulk IN and OUT endpoints only.
111239  *
111240  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
111241  * to DATA1.
111242  *
111243  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
111244  *
111245  * DMA mode.
111246  *
111247  * Set Odd (micro)frame (SetOddFr)
111248  *
111249  * Applies to isochronous IN and OUT endpoints only.
111250  *
111251  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
111252  *
111253  * (micro)frame.
111254  *
111255  * This field is not applicable for Scatter/Gather DMA mode.
111256  *
111257  * Field Enumeration Values:
111258  *
111259  * Enum | Value | Description
111260  * :-------------------------------------|:------|:-----------------------
111261  * ALT_USB_DEV_DOEPCTL3_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
111262  * ALT_USB_DEV_DOEPCTL3_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
111263  *
111264  * Field Access Macros:
111265  *
111266  */
111267 /*
111268  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD1PID
111269  *
111270  * Disables Set DATA1 PID
111271  */
111272 #define ALT_USB_DEV_DOEPCTL3_SETD1PID_E_DISD 0x0
111273 /*
111274  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD1PID
111275  *
111276  * Enables Set DATA1 PID
111277  */
111278 #define ALT_USB_DEV_DOEPCTL3_SETD1PID_E_END 0x1
111279 
111280 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */
111281 #define ALT_USB_DEV_DOEPCTL3_SETD1PID_LSB 29
111282 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */
111283 #define ALT_USB_DEV_DOEPCTL3_SETD1PID_MSB 29
111284 /* The width in bits of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */
111285 #define ALT_USB_DEV_DOEPCTL3_SETD1PID_WIDTH 1
111286 /* The mask used to set the ALT_USB_DEV_DOEPCTL3_SETD1PID register field value. */
111287 #define ALT_USB_DEV_DOEPCTL3_SETD1PID_SET_MSK 0x20000000
111288 /* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SETD1PID register field value. */
111289 #define ALT_USB_DEV_DOEPCTL3_SETD1PID_CLR_MSK 0xdfffffff
111290 /* The reset value of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */
111291 #define ALT_USB_DEV_DOEPCTL3_SETD1PID_RESET 0x0
111292 /* Extracts the ALT_USB_DEV_DOEPCTL3_SETD1PID field value from a register. */
111293 #define ALT_USB_DEV_DOEPCTL3_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
111294 /* Produces a ALT_USB_DEV_DOEPCTL3_SETD1PID register field value suitable for setting the register. */
111295 #define ALT_USB_DEV_DOEPCTL3_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
111296 
111297 /*
111298  * Field : epdis
111299  *
111300  * Endpoint Disable (EPDis)
111301  *
111302  * Applies to IN and OUT endpoints.
111303  *
111304  * The application sets this bit to stop transmitting/receiving data on an
111305  * endpoint, even
111306  *
111307  * before the transfer for that endpoint is complete. The application must wait for
111308  * the
111309  *
111310  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
111311  * clears
111312  *
111313  * this bit before setting the Endpoint Disabled interrupt. The application must
111314  * set this bit
111315  *
111316  * only if Endpoint Enable is already set for this endpoint.
111317  *
111318  * Field Enumeration Values:
111319  *
111320  * Enum | Value | Description
111321  * :-----------------------------------|:------|:--------------------
111322  * ALT_USB_DEV_DOEPCTL3_EPDIS_E_INACT | 0x0 | No Endpoint Disable
111323  * ALT_USB_DEV_DOEPCTL3_EPDIS_E_ACT | 0x1 | Endpoint Disable
111324  *
111325  * Field Access Macros:
111326  *
111327  */
111328 /*
111329  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPDIS
111330  *
111331  * No Endpoint Disable
111332  */
111333 #define ALT_USB_DEV_DOEPCTL3_EPDIS_E_INACT 0x0
111334 /*
111335  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPDIS
111336  *
111337  * Endpoint Disable
111338  */
111339 #define ALT_USB_DEV_DOEPCTL3_EPDIS_E_ACT 0x1
111340 
111341 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */
111342 #define ALT_USB_DEV_DOEPCTL3_EPDIS_LSB 30
111343 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */
111344 #define ALT_USB_DEV_DOEPCTL3_EPDIS_MSB 30
111345 /* The width in bits of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */
111346 #define ALT_USB_DEV_DOEPCTL3_EPDIS_WIDTH 1
111347 /* The mask used to set the ALT_USB_DEV_DOEPCTL3_EPDIS register field value. */
111348 #define ALT_USB_DEV_DOEPCTL3_EPDIS_SET_MSK 0x40000000
111349 /* The mask used to clear the ALT_USB_DEV_DOEPCTL3_EPDIS register field value. */
111350 #define ALT_USB_DEV_DOEPCTL3_EPDIS_CLR_MSK 0xbfffffff
111351 /* The reset value of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */
111352 #define ALT_USB_DEV_DOEPCTL3_EPDIS_RESET 0x0
111353 /* Extracts the ALT_USB_DEV_DOEPCTL3_EPDIS field value from a register. */
111354 #define ALT_USB_DEV_DOEPCTL3_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
111355 /* Produces a ALT_USB_DEV_DOEPCTL3_EPDIS register field value suitable for setting the register. */
111356 #define ALT_USB_DEV_DOEPCTL3_EPDIS_SET(value) (((value) << 30) & 0x40000000)
111357 
111358 /*
111359  * Field : epena
111360  *
111361  * Endpoint Enable (EPEna)
111362  *
111363  * Applies to IN and OUT endpoints.
111364  *
111365  * When Scatter/Gather DMA mode is enabled,
111366  *
111367  * For IN endpoints this bit indicates that the descriptor structure and data
111368  * buffer with
111369  *
111370  * data ready to transmit is setup.
111371  *
111372  * For OUT endpoint it indicates that the descriptor structure and data buffer to
111373  *
111374  * receive data is setup.
111375  *
111376  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
111377  *
111378  * DMA mode:
111379  *
111380  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
111381  * the
111382  *
111383  * endpoint.
111384  *
111385  * * For OUT endpoints, this bit indicates that the application has allocated the
111386  *
111387  * memory to start receiving data from the USB.
111388  *
111389  * * The core clears this bit before setting any of the following interrupts on
111390  * this
111391  *
111392  * endpoint:
111393  *
111394  * SETUP Phase Done
111395  *
111396  * Endpoint Disabled
111397  *
111398  * Transfer Completed
111399  *
111400  * Note: For control endpoints in DMA mode, this bit must be set to be able to
111401  * transfer
111402  *
111403  * SETUP data packets in memory.
111404  *
111405  * Field Enumeration Values:
111406  *
111407  * Enum | Value | Description
111408  * :-----------------------------------|:------|:-------------------------
111409  * ALT_USB_DEV_DOEPCTL3_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
111410  * ALT_USB_DEV_DOEPCTL3_EPENA_E_ACT | 0x1 | Endpoint Enable active
111411  *
111412  * Field Access Macros:
111413  *
111414  */
111415 /*
111416  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPENA
111417  *
111418  * Endpoint Enable inactive
111419  */
111420 #define ALT_USB_DEV_DOEPCTL3_EPENA_E_INACT 0x0
111421 /*
111422  * Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPENA
111423  *
111424  * Endpoint Enable active
111425  */
111426 #define ALT_USB_DEV_DOEPCTL3_EPENA_E_ACT 0x1
111427 
111428 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */
111429 #define ALT_USB_DEV_DOEPCTL3_EPENA_LSB 31
111430 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */
111431 #define ALT_USB_DEV_DOEPCTL3_EPENA_MSB 31
111432 /* The width in bits of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */
111433 #define ALT_USB_DEV_DOEPCTL3_EPENA_WIDTH 1
111434 /* The mask used to set the ALT_USB_DEV_DOEPCTL3_EPENA register field value. */
111435 #define ALT_USB_DEV_DOEPCTL3_EPENA_SET_MSK 0x80000000
111436 /* The mask used to clear the ALT_USB_DEV_DOEPCTL3_EPENA register field value. */
111437 #define ALT_USB_DEV_DOEPCTL3_EPENA_CLR_MSK 0x7fffffff
111438 /* The reset value of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */
111439 #define ALT_USB_DEV_DOEPCTL3_EPENA_RESET 0x0
111440 /* Extracts the ALT_USB_DEV_DOEPCTL3_EPENA field value from a register. */
111441 #define ALT_USB_DEV_DOEPCTL3_EPENA_GET(value) (((value) & 0x80000000) >> 31)
111442 /* Produces a ALT_USB_DEV_DOEPCTL3_EPENA register field value suitable for setting the register. */
111443 #define ALT_USB_DEV_DOEPCTL3_EPENA_SET(value) (((value) << 31) & 0x80000000)
111444 
111445 #ifndef __ASSEMBLY__
111446 /*
111447  * WARNING: The C register and register group struct declarations are provided for
111448  * convenience and illustrative purposes. They should, however, be used with
111449  * caution as the C language standard provides no guarantees about the alignment or
111450  * atomicity of device memory accesses. The recommended practice for writing
111451  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
111452  * alt_write_word() functions.
111453  *
111454  * The struct declaration for register ALT_USB_DEV_DOEPCTL3.
111455  */
111456 struct ALT_USB_DEV_DOEPCTL3_s
111457 {
111458  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL3_MPS */
111459  uint32_t : 4; /* *UNDEFINED* */
111460  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL3_USBACTEP */
111461  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL3_DPID */
111462  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL3_NAKSTS */
111463  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL3_EPTYPE */
111464  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL3_SNP */
111465  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL3_STALL */
111466  uint32_t : 4; /* *UNDEFINED* */
111467  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL3_CNAK */
111468  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL3_SNAK */
111469  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL3_SETD0PID */
111470  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL3_SETD1PID */
111471  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL3_EPDIS */
111472  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL3_EPENA */
111473 };
111474 
111475 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL3. */
111476 typedef volatile struct ALT_USB_DEV_DOEPCTL3_s ALT_USB_DEV_DOEPCTL3_t;
111477 #endif /* __ASSEMBLY__ */
111478 
111479 /* The reset value of the ALT_USB_DEV_DOEPCTL3 register. */
111480 #define ALT_USB_DEV_DOEPCTL3_RESET 0x00000000
111481 /* The byte offset of the ALT_USB_DEV_DOEPCTL3 register from the beginning of the component. */
111482 #define ALT_USB_DEV_DOEPCTL3_OFST 0x360
111483 /* The address of the ALT_USB_DEV_DOEPCTL3 register. */
111484 #define ALT_USB_DEV_DOEPCTL3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL3_OFST))
111485 
111486 /*
111487  * Register : doepint3
111488  *
111489  * Device OUT Endpoint 3 Interrupt Register
111490  *
111491  * Register Layout
111492  *
111493  * Bits | Access | Reset | Description
111494  * :--------|:-------|:------|:------------------------------------
111495  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_XFERCOMPL
111496  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_EPDISBLD
111497  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_AHBERR
111498  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_SETUP
111499  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS
111500  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_STSPHSERCVD
111501  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP
111502  * [7] | ??? | 0x0 | *UNDEFINED*
111503  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_OUTPKTERR
111504  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_BNAINTR
111505  * [10] | ??? | 0x0 | *UNDEFINED*
111506  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_PKTDRPSTS
111507  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_BBLEERR
111508  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_NAKINTRPT
111509  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_NYETINTRPT
111510  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_STUPPKTRCVD
111511  * [31:16] | ??? | 0x0 | *UNDEFINED*
111512  *
111513  */
111514 /*
111515  * Field : xfercompl
111516  *
111517  * Transfer Completed Interrupt (XferCompl)
111518  *
111519  * Applies to IN and OUT endpoints.
111520  *
111521  * When Scatter/Gather DMA mode is enabled
111522  *
111523  * * For IN endpoint this field indicates that the requested data
111524  *
111525  * from the descriptor is moved from external system memory
111526  *
111527  * to internal FIFO.
111528  *
111529  * * For OUT endpoint this field indicates that the requested
111530  *
111531  * data from the internal FIFO is moved to external system
111532  *
111533  * memory. This interrupt is generated only when the
111534  *
111535  * corresponding endpoint descriptor is closed, and the IOC
111536  *
111537  * bit For the corresponding descriptor is Set.
111538  *
111539  * When Scatter/Gather DMA mode is disabled, this field
111540  *
111541  * indicates that the programmed transfer is complete on the
111542  *
111543  * AHB as well as on the USB, For this endpoint.
111544  *
111545  * Field Enumeration Values:
111546  *
111547  * Enum | Value | Description
111548  * :---------------------------------------|:------|:-----------------------------
111549  * ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_INACT | 0x0 | No Interrupt
111550  * ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
111551  *
111552  * Field Access Macros:
111553  *
111554  */
111555 /*
111556  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_XFERCOMPL
111557  *
111558  * No Interrupt
111559  */
111560 #define ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_INACT 0x0
111561 /*
111562  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_XFERCOMPL
111563  *
111564  * Transfer Completed Interrupt
111565  */
111566 #define ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_ACT 0x1
111567 
111568 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */
111569 #define ALT_USB_DEV_DOEPINT3_XFERCOMPL_LSB 0
111570 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */
111571 #define ALT_USB_DEV_DOEPINT3_XFERCOMPL_MSB 0
111572 /* The width in bits of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */
111573 #define ALT_USB_DEV_DOEPINT3_XFERCOMPL_WIDTH 1
111574 /* The mask used to set the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field value. */
111575 #define ALT_USB_DEV_DOEPINT3_XFERCOMPL_SET_MSK 0x00000001
111576 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field value. */
111577 #define ALT_USB_DEV_DOEPINT3_XFERCOMPL_CLR_MSK 0xfffffffe
111578 /* The reset value of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */
111579 #define ALT_USB_DEV_DOEPINT3_XFERCOMPL_RESET 0x0
111580 /* Extracts the ALT_USB_DEV_DOEPINT3_XFERCOMPL field value from a register. */
111581 #define ALT_USB_DEV_DOEPINT3_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
111582 /* Produces a ALT_USB_DEV_DOEPINT3_XFERCOMPL register field value suitable for setting the register. */
111583 #define ALT_USB_DEV_DOEPINT3_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
111584 
111585 /*
111586  * Field : epdisbld
111587  *
111588  * Endpoint Disabled Interrupt (EPDisbld)
111589  *
111590  * Applies to IN and OUT endpoints.
111591  *
111592  * This bit indicates that the endpoint is disabled per the
111593  *
111594  * application's request.
111595  *
111596  * Field Enumeration Values:
111597  *
111598  * Enum | Value | Description
111599  * :--------------------------------------|:------|:----------------------------
111600  * ALT_USB_DEV_DOEPINT3_EPDISBLD_E_INACT | 0x0 | No Interrupt
111601  * ALT_USB_DEV_DOEPINT3_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
111602  *
111603  * Field Access Macros:
111604  *
111605  */
111606 /*
111607  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_EPDISBLD
111608  *
111609  * No Interrupt
111610  */
111611 #define ALT_USB_DEV_DOEPINT3_EPDISBLD_E_INACT 0x0
111612 /*
111613  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_EPDISBLD
111614  *
111615  * Endpoint Disabled Interrupt
111616  */
111617 #define ALT_USB_DEV_DOEPINT3_EPDISBLD_E_ACT 0x1
111618 
111619 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */
111620 #define ALT_USB_DEV_DOEPINT3_EPDISBLD_LSB 1
111621 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */
111622 #define ALT_USB_DEV_DOEPINT3_EPDISBLD_MSB 1
111623 /* The width in bits of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */
111624 #define ALT_USB_DEV_DOEPINT3_EPDISBLD_WIDTH 1
111625 /* The mask used to set the ALT_USB_DEV_DOEPINT3_EPDISBLD register field value. */
111626 #define ALT_USB_DEV_DOEPINT3_EPDISBLD_SET_MSK 0x00000002
111627 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_EPDISBLD register field value. */
111628 #define ALT_USB_DEV_DOEPINT3_EPDISBLD_CLR_MSK 0xfffffffd
111629 /* The reset value of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */
111630 #define ALT_USB_DEV_DOEPINT3_EPDISBLD_RESET 0x0
111631 /* Extracts the ALT_USB_DEV_DOEPINT3_EPDISBLD field value from a register. */
111632 #define ALT_USB_DEV_DOEPINT3_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
111633 /* Produces a ALT_USB_DEV_DOEPINT3_EPDISBLD register field value suitable for setting the register. */
111634 #define ALT_USB_DEV_DOEPINT3_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
111635 
111636 /*
111637  * Field : ahberr
111638  *
111639  * AHB Error (AHBErr)
111640  *
111641  * Applies to IN and OUT endpoints.
111642  *
111643  * This is generated only in Internal DMA mode when there is an
111644  *
111645  * AHB error during an AHB read/write. The application can read
111646  *
111647  * the corresponding endpoint DMA address register to get the
111648  *
111649  * error address.
111650  *
111651  * Field Enumeration Values:
111652  *
111653  * Enum | Value | Description
111654  * :------------------------------------|:------|:--------------------
111655  * ALT_USB_DEV_DOEPINT3_AHBERR_E_INACT | 0x0 | No Interrupt
111656  * ALT_USB_DEV_DOEPINT3_AHBERR_E_ACT | 0x1 | AHB Error interrupt
111657  *
111658  * Field Access Macros:
111659  *
111660  */
111661 /*
111662  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_AHBERR
111663  *
111664  * No Interrupt
111665  */
111666 #define ALT_USB_DEV_DOEPINT3_AHBERR_E_INACT 0x0
111667 /*
111668  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_AHBERR
111669  *
111670  * AHB Error interrupt
111671  */
111672 #define ALT_USB_DEV_DOEPINT3_AHBERR_E_ACT 0x1
111673 
111674 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */
111675 #define ALT_USB_DEV_DOEPINT3_AHBERR_LSB 2
111676 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */
111677 #define ALT_USB_DEV_DOEPINT3_AHBERR_MSB 2
111678 /* The width in bits of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */
111679 #define ALT_USB_DEV_DOEPINT3_AHBERR_WIDTH 1
111680 /* The mask used to set the ALT_USB_DEV_DOEPINT3_AHBERR register field value. */
111681 #define ALT_USB_DEV_DOEPINT3_AHBERR_SET_MSK 0x00000004
111682 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_AHBERR register field value. */
111683 #define ALT_USB_DEV_DOEPINT3_AHBERR_CLR_MSK 0xfffffffb
111684 /* The reset value of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */
111685 #define ALT_USB_DEV_DOEPINT3_AHBERR_RESET 0x0
111686 /* Extracts the ALT_USB_DEV_DOEPINT3_AHBERR field value from a register. */
111687 #define ALT_USB_DEV_DOEPINT3_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
111688 /* Produces a ALT_USB_DEV_DOEPINT3_AHBERR register field value suitable for setting the register. */
111689 #define ALT_USB_DEV_DOEPINT3_AHBERR_SET(value) (((value) << 2) & 0x00000004)
111690 
111691 /*
111692  * Field : setup
111693  *
111694  * SETUP Phase Done (SetUp)
111695  *
111696  * Applies to control OUT endpoints only.
111697  *
111698  * Indicates that the SETUP phase For the control endpoint is
111699  *
111700  * complete and no more back-to-back SETUP packets were
111701  *
111702  * received For the current control transfer. On this interrupt, the
111703  *
111704  * application can decode the received SETUP data packet.
111705  *
111706  * Field Enumeration Values:
111707  *
111708  * Enum | Value | Description
111709  * :-----------------------------------|:------|:--------------------
111710  * ALT_USB_DEV_DOEPINT3_SETUP_E_INACT | 0x0 | No SETUP Phase Done
111711  * ALT_USB_DEV_DOEPINT3_SETUP_E_ACT | 0x1 | SETUP Phase Done
111712  *
111713  * Field Access Macros:
111714  *
111715  */
111716 /*
111717  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_SETUP
111718  *
111719  * No SETUP Phase Done
111720  */
111721 #define ALT_USB_DEV_DOEPINT3_SETUP_E_INACT 0x0
111722 /*
111723  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_SETUP
111724  *
111725  * SETUP Phase Done
111726  */
111727 #define ALT_USB_DEV_DOEPINT3_SETUP_E_ACT 0x1
111728 
111729 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_SETUP register field. */
111730 #define ALT_USB_DEV_DOEPINT3_SETUP_LSB 3
111731 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_SETUP register field. */
111732 #define ALT_USB_DEV_DOEPINT3_SETUP_MSB 3
111733 /* The width in bits of the ALT_USB_DEV_DOEPINT3_SETUP register field. */
111734 #define ALT_USB_DEV_DOEPINT3_SETUP_WIDTH 1
111735 /* The mask used to set the ALT_USB_DEV_DOEPINT3_SETUP register field value. */
111736 #define ALT_USB_DEV_DOEPINT3_SETUP_SET_MSK 0x00000008
111737 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_SETUP register field value. */
111738 #define ALT_USB_DEV_DOEPINT3_SETUP_CLR_MSK 0xfffffff7
111739 /* The reset value of the ALT_USB_DEV_DOEPINT3_SETUP register field. */
111740 #define ALT_USB_DEV_DOEPINT3_SETUP_RESET 0x0
111741 /* Extracts the ALT_USB_DEV_DOEPINT3_SETUP field value from a register. */
111742 #define ALT_USB_DEV_DOEPINT3_SETUP_GET(value) (((value) & 0x00000008) >> 3)
111743 /* Produces a ALT_USB_DEV_DOEPINT3_SETUP register field value suitable for setting the register. */
111744 #define ALT_USB_DEV_DOEPINT3_SETUP_SET(value) (((value) << 3) & 0x00000008)
111745 
111746 /*
111747  * Field : outtknepdis
111748  *
111749  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
111750  *
111751  * Applies only to control OUT endpoints.
111752  *
111753  * Indicates that an OUT token was received when the endpoint
111754  *
111755  * was not yet enabled. This interrupt is asserted on the endpoint
111756  *
111757  * For which the OUT token was received.
111758  *
111759  * Field Enumeration Values:
111760  *
111761  * Enum | Value | Description
111762  * :-----------------------------------------|:------|:---------------------------------------------
111763  * ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
111764  * ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
111765  *
111766  * Field Access Macros:
111767  *
111768  */
111769 /*
111770  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS
111771  *
111772  * No OUT Token Received When Endpoint Disabled
111773  */
111774 #define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_INACT 0x0
111775 /*
111776  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS
111777  *
111778  * OUT Token Received When Endpoint Disabled
111779  */
111780 #define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_ACT 0x1
111781 
111782 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */
111783 #define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_LSB 4
111784 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */
111785 #define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_MSB 4
111786 /* The width in bits of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */
111787 #define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_WIDTH 1
111788 /* The mask used to set the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field value. */
111789 #define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_SET_MSK 0x00000010
111790 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field value. */
111791 #define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_CLR_MSK 0xffffffef
111792 /* The reset value of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */
111793 #define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_RESET 0x0
111794 /* Extracts the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS field value from a register. */
111795 #define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
111796 /* Produces a ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field value suitable for setting the register. */
111797 #define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
111798 
111799 /*
111800  * Field : stsphsercvd
111801  *
111802  * Status Phase Received For Control Write (StsPhseRcvd)
111803  *
111804  * This interrupt is valid only For Control OUT endpoints and only in
111805  *
111806  * Scatter Gather DMA mode.
111807  *
111808  * This interrupt is generated only after the core has transferred all
111809  *
111810  * the data that the host has sent during the data phase of a control
111811  *
111812  * write transfer, to the system memory buffer.
111813  *
111814  * The interrupt indicates to the application that the host has
111815  *
111816  * switched from data phase to the status phase of a Control Write
111817  *
111818  * transfer. The application can use this interrupt to ACK or STALL
111819  *
111820  * the Status phase, after it has decoded the data phase. This is
111821  *
111822  * applicable only in Case of Scatter Gather DMA mode.
111823  *
111824  * Field Enumeration Values:
111825  *
111826  * Enum | Value | Description
111827  * :-----------------------------------------|:------|:-------------------------------------------
111828  * ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
111829  * ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
111830  *
111831  * Field Access Macros:
111832  *
111833  */
111834 /*
111835  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_STSPHSERCVD
111836  *
111837  * No Status Phase Received for Control Write
111838  */
111839 #define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_INACT 0x0
111840 /*
111841  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_STSPHSERCVD
111842  *
111843  * Status Phase Received for Control Write
111844  */
111845 #define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_ACT 0x1
111846 
111847 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */
111848 #define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_LSB 5
111849 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */
111850 #define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_MSB 5
111851 /* The width in bits of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */
111852 #define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_WIDTH 1
111853 /* The mask used to set the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field value. */
111854 #define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_SET_MSK 0x00000020
111855 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field value. */
111856 #define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_CLR_MSK 0xffffffdf
111857 /* The reset value of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */
111858 #define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_RESET 0x0
111859 /* Extracts the ALT_USB_DEV_DOEPINT3_STSPHSERCVD field value from a register. */
111860 #define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
111861 /* Produces a ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field value suitable for setting the register. */
111862 #define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
111863 
111864 /*
111865  * Field : back2backsetup
111866  *
111867  * Back-to-Back SETUP Packets Received (Back2BackSETup)
111868  *
111869  * Applies to Control OUT endpoints only.
111870  *
111871  * This bit indicates that the core has received more than three
111872  *
111873  * back-to-back SETUP packets For this particular endpoint. For
111874  *
111875  * information about handling this interrupt,
111876  *
111877  * Field Enumeration Values:
111878  *
111879  * Enum | Value | Description
111880  * :--------------------------------------------|:------|:---------------------------------------
111881  * ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
111882  * ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
111883  *
111884  * Field Access Macros:
111885  *
111886  */
111887 /*
111888  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP
111889  *
111890  * No Back-to-Back SETUP Packets Received
111891  */
111892 #define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_INACT 0x0
111893 /*
111894  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP
111895  *
111896  * Back-to-Back SETUP Packets Received
111897  */
111898 #define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_ACT 0x1
111899 
111900 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */
111901 #define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_LSB 6
111902 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */
111903 #define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_MSB 6
111904 /* The width in bits of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */
111905 #define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_WIDTH 1
111906 /* The mask used to set the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field value. */
111907 #define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_SET_MSK 0x00000040
111908 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field value. */
111909 #define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_CLR_MSK 0xffffffbf
111910 /* The reset value of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */
111911 #define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_RESET 0x0
111912 /* Extracts the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP field value from a register. */
111913 #define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
111914 /* Produces a ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field value suitable for setting the register. */
111915 #define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
111916 
111917 /*
111918  * Field : outpkterr
111919  *
111920  * OUT Packet Error (OutPktErr)
111921  *
111922  * Applies to OUT endpoints Only
111923  *
111924  * This interrupt is valid only when thresholding is enabled. This interrupt is
111925  * asserted when the
111926  *
111927  * core detects an overflow or a CRC error For non-Isochronous
111928  *
111929  * OUT packet.
111930  *
111931  * Field Enumeration Values:
111932  *
111933  * Enum | Value | Description
111934  * :---------------------------------------|:------|:--------------------
111935  * ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
111936  * ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
111937  *
111938  * Field Access Macros:
111939  *
111940  */
111941 /*
111942  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTPKTERR
111943  *
111944  * No OUT Packet Error
111945  */
111946 #define ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_INACT 0x0
111947 /*
111948  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTPKTERR
111949  *
111950  * OUT Packet Error
111951  */
111952 #define ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_ACT 0x1
111953 
111954 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */
111955 #define ALT_USB_DEV_DOEPINT3_OUTPKTERR_LSB 8
111956 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */
111957 #define ALT_USB_DEV_DOEPINT3_OUTPKTERR_MSB 8
111958 /* The width in bits of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */
111959 #define ALT_USB_DEV_DOEPINT3_OUTPKTERR_WIDTH 1
111960 /* The mask used to set the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field value. */
111961 #define ALT_USB_DEV_DOEPINT3_OUTPKTERR_SET_MSK 0x00000100
111962 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field value. */
111963 #define ALT_USB_DEV_DOEPINT3_OUTPKTERR_CLR_MSK 0xfffffeff
111964 /* The reset value of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */
111965 #define ALT_USB_DEV_DOEPINT3_OUTPKTERR_RESET 0x0
111966 /* Extracts the ALT_USB_DEV_DOEPINT3_OUTPKTERR field value from a register. */
111967 #define ALT_USB_DEV_DOEPINT3_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
111968 /* Produces a ALT_USB_DEV_DOEPINT3_OUTPKTERR register field value suitable for setting the register. */
111969 #define ALT_USB_DEV_DOEPINT3_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
111970 
111971 /*
111972  * Field : bnaintr
111973  *
111974  * BNA (Buffer Not Available) Interrupt (BNAIntr)
111975  *
111976  * This bit is valid only when Scatter/Gather DMA mode is enabled.
111977  *
111978  * The core generates this interrupt when the descriptor accessed
111979  *
111980  * is not ready For the Core to process, such as Host busy or DMA
111981  *
111982  * done
111983  *
111984  * Field Enumeration Values:
111985  *
111986  * Enum | Value | Description
111987  * :-------------------------------------|:------|:--------------
111988  * ALT_USB_DEV_DOEPINT3_BNAINTR_E_INACT | 0x0 | No interrupt
111989  * ALT_USB_DEV_DOEPINT3_BNAINTR_E_ACT | 0x1 | BNA interrupt
111990  *
111991  * Field Access Macros:
111992  *
111993  */
111994 /*
111995  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BNAINTR
111996  *
111997  * No interrupt
111998  */
111999 #define ALT_USB_DEV_DOEPINT3_BNAINTR_E_INACT 0x0
112000 /*
112001  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BNAINTR
112002  *
112003  * BNA interrupt
112004  */
112005 #define ALT_USB_DEV_DOEPINT3_BNAINTR_E_ACT 0x1
112006 
112007 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */
112008 #define ALT_USB_DEV_DOEPINT3_BNAINTR_LSB 9
112009 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */
112010 #define ALT_USB_DEV_DOEPINT3_BNAINTR_MSB 9
112011 /* The width in bits of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */
112012 #define ALT_USB_DEV_DOEPINT3_BNAINTR_WIDTH 1
112013 /* The mask used to set the ALT_USB_DEV_DOEPINT3_BNAINTR register field value. */
112014 #define ALT_USB_DEV_DOEPINT3_BNAINTR_SET_MSK 0x00000200
112015 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_BNAINTR register field value. */
112016 #define ALT_USB_DEV_DOEPINT3_BNAINTR_CLR_MSK 0xfffffdff
112017 /* The reset value of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */
112018 #define ALT_USB_DEV_DOEPINT3_BNAINTR_RESET 0x0
112019 /* Extracts the ALT_USB_DEV_DOEPINT3_BNAINTR field value from a register. */
112020 #define ALT_USB_DEV_DOEPINT3_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
112021 /* Produces a ALT_USB_DEV_DOEPINT3_BNAINTR register field value suitable for setting the register. */
112022 #define ALT_USB_DEV_DOEPINT3_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
112023 
112024 /*
112025  * Field : pktdrpsts
112026  *
112027  * Packet Drop Status (PktDrpSts)
112028  *
112029  * This bit indicates to the application that an ISOC OUT packet has been dropped.
112030  * This
112031  *
112032  * bit does not have an associated mask bit and does not generate an interrupt.
112033  *
112034  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
112035  * transfer
112036  *
112037  * interrupt feature is selected.
112038  *
112039  * Field Enumeration Values:
112040  *
112041  * Enum | Value | Description
112042  * :---------------------------------------|:------|:-----------------------------
112043  * ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_INACT | 0x0 | No interrupt
112044  * ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
112045  *
112046  * Field Access Macros:
112047  *
112048  */
112049 /*
112050  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_PKTDRPSTS
112051  *
112052  * No interrupt
112053  */
112054 #define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_INACT 0x0
112055 /*
112056  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_PKTDRPSTS
112057  *
112058  * Packet Drop Status interrupt
112059  */
112060 #define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_ACT 0x1
112061 
112062 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */
112063 #define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_LSB 11
112064 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */
112065 #define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_MSB 11
112066 /* The width in bits of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */
112067 #define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_WIDTH 1
112068 /* The mask used to set the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field value. */
112069 #define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_SET_MSK 0x00000800
112070 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field value. */
112071 #define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_CLR_MSK 0xfffff7ff
112072 /* The reset value of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */
112073 #define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_RESET 0x0
112074 /* Extracts the ALT_USB_DEV_DOEPINT3_PKTDRPSTS field value from a register. */
112075 #define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
112076 /* Produces a ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field value suitable for setting the register. */
112077 #define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
112078 
112079 /*
112080  * Field : bbleerr
112081  *
112082  * NAK Interrupt (BbleErr)
112083  *
112084  * The core generates this interrupt when babble is received for the endpoint.
112085  *
112086  * Field Enumeration Values:
112087  *
112088  * Enum | Value | Description
112089  * :-------------------------------------|:------|:------------------
112090  * ALT_USB_DEV_DOEPINT3_BBLEERR_E_INACT | 0x0 | No interrupt
112091  * ALT_USB_DEV_DOEPINT3_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
112092  *
112093  * Field Access Macros:
112094  *
112095  */
112096 /*
112097  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BBLEERR
112098  *
112099  * No interrupt
112100  */
112101 #define ALT_USB_DEV_DOEPINT3_BBLEERR_E_INACT 0x0
112102 /*
112103  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_BBLEERR
112104  *
112105  * BbleErr interrupt
112106  */
112107 #define ALT_USB_DEV_DOEPINT3_BBLEERR_E_ACT 0x1
112108 
112109 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */
112110 #define ALT_USB_DEV_DOEPINT3_BBLEERR_LSB 12
112111 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */
112112 #define ALT_USB_DEV_DOEPINT3_BBLEERR_MSB 12
112113 /* The width in bits of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */
112114 #define ALT_USB_DEV_DOEPINT3_BBLEERR_WIDTH 1
112115 /* The mask used to set the ALT_USB_DEV_DOEPINT3_BBLEERR register field value. */
112116 #define ALT_USB_DEV_DOEPINT3_BBLEERR_SET_MSK 0x00001000
112117 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_BBLEERR register field value. */
112118 #define ALT_USB_DEV_DOEPINT3_BBLEERR_CLR_MSK 0xffffefff
112119 /* The reset value of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */
112120 #define ALT_USB_DEV_DOEPINT3_BBLEERR_RESET 0x0
112121 /* Extracts the ALT_USB_DEV_DOEPINT3_BBLEERR field value from a register. */
112122 #define ALT_USB_DEV_DOEPINT3_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
112123 /* Produces a ALT_USB_DEV_DOEPINT3_BBLEERR register field value suitable for setting the register. */
112124 #define ALT_USB_DEV_DOEPINT3_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
112125 
112126 /*
112127  * Field : nakintrpt
112128  *
112129  * NAK Interrupt (NAKInterrupt)
112130  *
112131  * The core generates this interrupt when a NAK is transmitted or received by the
112132  * device.
112133  *
112134  * In case of isochronous IN endpoints the interrupt gets generated when a zero
112135  * length
112136  *
112137  * packet is transmitted due to un-availability of data in the TXFifo.
112138  *
112139  * Field Enumeration Values:
112140  *
112141  * Enum | Value | Description
112142  * :---------------------------------------|:------|:--------------
112143  * ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_INACT | 0x0 | No interrupt
112144  * ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
112145  *
112146  * Field Access Macros:
112147  *
112148  */
112149 /*
112150  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_NAKINTRPT
112151  *
112152  * No interrupt
112153  */
112154 #define ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_INACT 0x0
112155 /*
112156  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_NAKINTRPT
112157  *
112158  * NAK Interrupt
112159  */
112160 #define ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_ACT 0x1
112161 
112162 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */
112163 #define ALT_USB_DEV_DOEPINT3_NAKINTRPT_LSB 13
112164 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */
112165 #define ALT_USB_DEV_DOEPINT3_NAKINTRPT_MSB 13
112166 /* The width in bits of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */
112167 #define ALT_USB_DEV_DOEPINT3_NAKINTRPT_WIDTH 1
112168 /* The mask used to set the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field value. */
112169 #define ALT_USB_DEV_DOEPINT3_NAKINTRPT_SET_MSK 0x00002000
112170 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field value. */
112171 #define ALT_USB_DEV_DOEPINT3_NAKINTRPT_CLR_MSK 0xffffdfff
112172 /* The reset value of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */
112173 #define ALT_USB_DEV_DOEPINT3_NAKINTRPT_RESET 0x0
112174 /* Extracts the ALT_USB_DEV_DOEPINT3_NAKINTRPT field value from a register. */
112175 #define ALT_USB_DEV_DOEPINT3_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
112176 /* Produces a ALT_USB_DEV_DOEPINT3_NAKINTRPT register field value suitable for setting the register. */
112177 #define ALT_USB_DEV_DOEPINT3_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
112178 
112179 /*
112180  * Field : nyetintrpt
112181  *
112182  * NYET Interrupt (NYETIntrpt)
112183  *
112184  * The core generates this interrupt when a NYET response is transmitted for a non
112185  * isochronous OUT endpoint.
112186  *
112187  * Field Enumeration Values:
112188  *
112189  * Enum | Value | Description
112190  * :----------------------------------------|:------|:---------------
112191  * ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_INACT | 0x0 | No interrupt
112192  * ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
112193  *
112194  * Field Access Macros:
112195  *
112196  */
112197 /*
112198  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_NYETINTRPT
112199  *
112200  * No interrupt
112201  */
112202 #define ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_INACT 0x0
112203 /*
112204  * Enumerated value for register field ALT_USB_DEV_DOEPINT3_NYETINTRPT
112205  *
112206  * NYET Interrupt
112207  */
112208 #define ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_ACT 0x1
112209 
112210 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */
112211 #define ALT_USB_DEV_DOEPINT3_NYETINTRPT_LSB 14
112212 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */
112213 #define ALT_USB_DEV_DOEPINT3_NYETINTRPT_MSB 14
112214 /* The width in bits of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */
112215 #define ALT_USB_DEV_DOEPINT3_NYETINTRPT_WIDTH 1
112216 /* The mask used to set the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field value. */
112217 #define ALT_USB_DEV_DOEPINT3_NYETINTRPT_SET_MSK 0x00004000
112218 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field value. */
112219 #define ALT_USB_DEV_DOEPINT3_NYETINTRPT_CLR_MSK 0xffffbfff
112220 /* The reset value of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */
112221 #define ALT_USB_DEV_DOEPINT3_NYETINTRPT_RESET 0x0
112222 /* Extracts the ALT_USB_DEV_DOEPINT3_NYETINTRPT field value from a register. */
112223 #define ALT_USB_DEV_DOEPINT3_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
112224 /* Produces a ALT_USB_DEV_DOEPINT3_NYETINTRPT register field value suitable for setting the register. */
112225 #define ALT_USB_DEV_DOEPINT3_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
112226 
112227 /*
112228  * Field : stuppktrcvd
112229  *
112230  * Setup Packet Received
112231  *
112232  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
112233  *
112234  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
112235  *
112236  * setup data. There is only one Setup packet per buffer. On receiving a
112237  *
112238  * Setup packet, the DWC_otg core closes the buffer and disables the
112239  *
112240  * corresponding endpoint. The application has to re-enable the endpoint to
112241  *
112242  * receive any OUT data for the Control Transfer and reprogram the buffer
112243  *
112244  * start address.
112245  *
112246  * Note: Because of the above behavior, the DWC_otg core can receive any
112247  *
112248  * number of back to back setup packets and one buffer for every setup
112249  *
112250  * packet is used.
112251  *
112252  * 1'b0: No Setup packet received
112253  *
112254  * 1'b1: Setup packet received
112255  *
112256  * Reset: 1'b0
112257  *
112258  * Field Access Macros:
112259  *
112260  */
112261 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field. */
112262 #define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_LSB 15
112263 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field. */
112264 #define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_MSB 15
112265 /* The width in bits of the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field. */
112266 #define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_WIDTH 1
112267 /* The mask used to set the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field value. */
112268 #define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_SET_MSK 0x00008000
112269 /* The mask used to clear the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field value. */
112270 #define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_CLR_MSK 0xffff7fff
112271 /* The reset value of the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field. */
112272 #define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_RESET 0x0
112273 /* Extracts the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD field value from a register. */
112274 #define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
112275 /* Produces a ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field value suitable for setting the register. */
112276 #define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
112277 
112278 #ifndef __ASSEMBLY__
112279 /*
112280  * WARNING: The C register and register group struct declarations are provided for
112281  * convenience and illustrative purposes. They should, however, be used with
112282  * caution as the C language standard provides no guarantees about the alignment or
112283  * atomicity of device memory accesses. The recommended practice for writing
112284  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
112285  * alt_write_word() functions.
112286  *
112287  * The struct declaration for register ALT_USB_DEV_DOEPINT3.
112288  */
112289 struct ALT_USB_DEV_DOEPINT3_s
112290 {
112291  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT3_XFERCOMPL */
112292  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT3_EPDISBLD */
112293  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT3_AHBERR */
112294  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT3_SETUP */
112295  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS */
112296  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT3_STSPHSERCVD */
112297  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP */
112298  uint32_t : 1; /* *UNDEFINED* */
112299  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT3_OUTPKTERR */
112300  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT3_BNAINTR */
112301  uint32_t : 1; /* *UNDEFINED* */
112302  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT3_PKTDRPSTS */
112303  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT3_BBLEERR */
112304  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT3_NAKINTRPT */
112305  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT3_NYETINTRPT */
112306  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT3_STUPPKTRCVD */
112307  uint32_t : 16; /* *UNDEFINED* */
112308 };
112309 
112310 /* The typedef declaration for register ALT_USB_DEV_DOEPINT3. */
112311 typedef volatile struct ALT_USB_DEV_DOEPINT3_s ALT_USB_DEV_DOEPINT3_t;
112312 #endif /* __ASSEMBLY__ */
112313 
112314 /* The reset value of the ALT_USB_DEV_DOEPINT3 register. */
112315 #define ALT_USB_DEV_DOEPINT3_RESET 0x00000000
112316 /* The byte offset of the ALT_USB_DEV_DOEPINT3 register from the beginning of the component. */
112317 #define ALT_USB_DEV_DOEPINT3_OFST 0x368
112318 /* The address of the ALT_USB_DEV_DOEPINT3 register. */
112319 #define ALT_USB_DEV_DOEPINT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT3_OFST))
112320 
112321 /*
112322  * Register : doeptsiz3
112323  *
112324  * Device OUT Endpoint 3 Transfer Size Register
112325  *
112326  * Register Layout
112327  *
112328  * Bits | Access | Reset | Description
112329  * :--------|:-------|:------|:-------------------------------
112330  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ3_XFERSIZE
112331  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ3_PKTCNT
112332  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ3_RXDPID
112333  * [31] | ??? | 0x0 | *UNDEFINED*
112334  *
112335  */
112336 /*
112337  * Field : xfersize
112338  *
112339  * Transfer Size (XferSize)
112340  *
112341  * Indicates the transfer size in bytes For endpoint 0. The core
112342  *
112343  * interrupts the application only after it has exhausted the transfer
112344  *
112345  * size amount of data. The transfer size can be Set to the
112346  *
112347  * maximum packet size of the endpoint, to be interrupted at the
112348  *
112349  * end of each packet.
112350  *
112351  * The core decrements this field every time a packet is read from
112352  *
112353  * the RxFIFO and written to the external memory.
112354  *
112355  * Field Access Macros:
112356  *
112357  */
112358 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */
112359 #define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_LSB 0
112360 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */
112361 #define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_MSB 18
112362 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */
112363 #define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_WIDTH 19
112364 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field value. */
112365 #define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_SET_MSK 0x0007ffff
112366 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field value. */
112367 #define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_CLR_MSK 0xfff80000
112368 /* The reset value of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */
112369 #define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_RESET 0x0
112370 /* Extracts the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE field value from a register. */
112371 #define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
112372 /* Produces a ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field value suitable for setting the register. */
112373 #define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
112374 
112375 /*
112376  * Field : pktcnt
112377  *
112378  * Packet Count (PktCnt)
112379  *
112380  * This field is decremented to zero after a packet is written into the
112381  *
112382  * RxFIFO.
112383  *
112384  * Field Access Macros:
112385  *
112386  */
112387 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */
112388 #define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_LSB 19
112389 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */
112390 #define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_MSB 28
112391 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */
112392 #define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_WIDTH 10
112393 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field value. */
112394 #define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_SET_MSK 0x1ff80000
112395 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field value. */
112396 #define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_CLR_MSK 0xe007ffff
112397 /* The reset value of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */
112398 #define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_RESET 0x0
112399 /* Extracts the ALT_USB_DEV_DOEPTSIZ3_PKTCNT field value from a register. */
112400 #define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
112401 /* Produces a ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field value suitable for setting the register. */
112402 #define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
112403 
112404 /*
112405  * Field : rxdpid
112406  *
112407  * Applies to isochronous OUT endpoints only.
112408  *
112409  * This is the data PID received in the last packet for this endpoint.
112410  *
112411  * 2'b00: DATA0
112412  *
112413  * 2'b01: DATA2
112414  *
112415  * 2'b10: DATA1
112416  *
112417  * 2'b11: MDATA
112418  *
112419  * SETUP Packet Count (SUPCnt)
112420  *
112421  * Applies to control OUT Endpoints only.
112422  *
112423  * This field specifies the number of back-to-back SETUP data
112424  *
112425  * packets the endpoint can receive.
112426  *
112427  * 2'b01: 1 packet
112428  *
112429  * 2'b10: 2 packets
112430  *
112431  * 2'b11: 3 packets
112432  *
112433  * Field Enumeration Values:
112434  *
112435  * Enum | Value | Description
112436  * :-----------------------------------------|:------|:-------------------
112437  * ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA0 | 0x0 | DATA0
112438  * ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
112439  * ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
112440  * ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
112441  *
112442  * Field Access Macros:
112443  *
112444  */
112445 /*
112446  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID
112447  *
112448  * DATA0
112449  */
112450 #define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA0 0x0
112451 /*
112452  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID
112453  *
112454  * DATA2 or 1 packet
112455  */
112456 #define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA2PKT1 0x1
112457 /*
112458  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID
112459  *
112460  * DATA1 or 2 packets
112461  */
112462 #define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA1PKT2 0x2
112463 /*
112464  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID
112465  *
112466  * MDATA or 3 packets
112467  */
112468 #define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_MDATAPKT3 0x3
112469 
112470 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */
112471 #define ALT_USB_DEV_DOEPTSIZ3_RXDPID_LSB 29
112472 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */
112473 #define ALT_USB_DEV_DOEPTSIZ3_RXDPID_MSB 30
112474 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */
112475 #define ALT_USB_DEV_DOEPTSIZ3_RXDPID_WIDTH 2
112476 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field value. */
112477 #define ALT_USB_DEV_DOEPTSIZ3_RXDPID_SET_MSK 0x60000000
112478 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field value. */
112479 #define ALT_USB_DEV_DOEPTSIZ3_RXDPID_CLR_MSK 0x9fffffff
112480 /* The reset value of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */
112481 #define ALT_USB_DEV_DOEPTSIZ3_RXDPID_RESET 0x0
112482 /* Extracts the ALT_USB_DEV_DOEPTSIZ3_RXDPID field value from a register. */
112483 #define ALT_USB_DEV_DOEPTSIZ3_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
112484 /* Produces a ALT_USB_DEV_DOEPTSIZ3_RXDPID register field value suitable for setting the register. */
112485 #define ALT_USB_DEV_DOEPTSIZ3_RXDPID_SET(value) (((value) << 29) & 0x60000000)
112486 
112487 #ifndef __ASSEMBLY__
112488 /*
112489  * WARNING: The C register and register group struct declarations are provided for
112490  * convenience and illustrative purposes. They should, however, be used with
112491  * caution as the C language standard provides no guarantees about the alignment or
112492  * atomicity of device memory accesses. The recommended practice for writing
112493  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
112494  * alt_write_word() functions.
112495  *
112496  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ3.
112497  */
112498 struct ALT_USB_DEV_DOEPTSIZ3_s
112499 {
112500  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ3_XFERSIZE */
112501  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ3_PKTCNT */
112502  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ3_RXDPID */
112503  uint32_t : 1; /* *UNDEFINED* */
112504 };
112505 
112506 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ3. */
112507 typedef volatile struct ALT_USB_DEV_DOEPTSIZ3_s ALT_USB_DEV_DOEPTSIZ3_t;
112508 #endif /* __ASSEMBLY__ */
112509 
112510 /* The reset value of the ALT_USB_DEV_DOEPTSIZ3 register. */
112511 #define ALT_USB_DEV_DOEPTSIZ3_RESET 0x00000000
112512 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ3 register from the beginning of the component. */
112513 #define ALT_USB_DEV_DOEPTSIZ3_OFST 0x370
112514 /* The address of the ALT_USB_DEV_DOEPTSIZ3 register. */
112515 #define ALT_USB_DEV_DOEPTSIZ3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ3_OFST))
112516 
112517 /*
112518  * Register : doepdma3
112519  *
112520  * Device OUT Endpoint 3 DMA Address Register
112521  *
112522  * Register Layout
112523  *
112524  * Bits | Access | Reset | Description
112525  * :-------|:-------|:--------|:------------------------------
112526  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA3_DOEPDMA3
112527  *
112528  */
112529 /*
112530  * Field : doepdma3
112531  *
112532  * Holds the start address of the external memory for storing or fetching endpoint
112533  *
112534  * data.
112535  *
112536  * Note: For control endpoints, this field stores control OUT data packets as well
112537  * as
112538  *
112539  * SETUP transaction data packets. When more than three SETUP packets are
112540  *
112541  * received back-to-back, the SETUP data packet in the memory is overwritten.
112542  *
112543  * This register is incremented on every AHB transaction. The application can give
112544  *
112545  * only a DWORD-aligned address.
112546  *
112547  * When Scatter/Gather DMA mode is not enabled, the application programs the
112548  *
112549  * start address value in this field.
112550  *
112551  * When Scatter/Gather DMA mode is enabled, this field indicates the base
112552  *
112553  * pointer for the descriptor list.
112554  *
112555  * Field Access Macros:
112556  *
112557  */
112558 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field. */
112559 #define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_LSB 0
112560 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field. */
112561 #define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_MSB 31
112562 /* The width in bits of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field. */
112563 #define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_WIDTH 32
112564 /* The mask used to set the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field value. */
112565 #define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_SET_MSK 0xffffffff
112566 /* The mask used to clear the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field value. */
112567 #define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_CLR_MSK 0x00000000
112568 /* The reset value of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field is UNKNOWN. */
112569 #define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_RESET 0x0
112570 /* Extracts the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 field value from a register. */
112571 #define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_GET(value) (((value) & 0xffffffff) >> 0)
112572 /* Produces a ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field value suitable for setting the register. */
112573 #define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_SET(value) (((value) << 0) & 0xffffffff)
112574 
112575 #ifndef __ASSEMBLY__
112576 /*
112577  * WARNING: The C register and register group struct declarations are provided for
112578  * convenience and illustrative purposes. They should, however, be used with
112579  * caution as the C language standard provides no guarantees about the alignment or
112580  * atomicity of device memory accesses. The recommended practice for writing
112581  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
112582  * alt_write_word() functions.
112583  *
112584  * The struct declaration for register ALT_USB_DEV_DOEPDMA3.
112585  */
112586 struct ALT_USB_DEV_DOEPDMA3_s
112587 {
112588  uint32_t doepdma3 : 32; /* ALT_USB_DEV_DOEPDMA3_DOEPDMA3 */
112589 };
112590 
112591 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA3. */
112592 typedef volatile struct ALT_USB_DEV_DOEPDMA3_s ALT_USB_DEV_DOEPDMA3_t;
112593 #endif /* __ASSEMBLY__ */
112594 
112595 /* The reset value of the ALT_USB_DEV_DOEPDMA3 register. */
112596 #define ALT_USB_DEV_DOEPDMA3_RESET 0x00000000
112597 /* The byte offset of the ALT_USB_DEV_DOEPDMA3 register from the beginning of the component. */
112598 #define ALT_USB_DEV_DOEPDMA3_OFST 0x374
112599 /* The address of the ALT_USB_DEV_DOEPDMA3 register. */
112600 #define ALT_USB_DEV_DOEPDMA3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA3_OFST))
112601 
112602 /*
112603  * Register : doepdmab3
112604  *
112605  * Device OUT Endpoint 3 Buffer Address Register
112606  *
112607  * Register Layout
112608  *
112609  * Bits | Access | Reset | Description
112610  * :-------|:-------|:--------|:--------------------------------
112611  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3
112612  *
112613  */
112614 /*
112615  * Field : doepdmab3
112616  *
112617  * Holds the current buffer address.This register is updated as and when the data
112618  *
112619  * transfer for the corresponding end point is in progress.
112620  *
112621  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
112622  * is
112623  *
112624  * reserved.
112625  *
112626  * Field Access Macros:
112627  *
112628  */
112629 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field. */
112630 #define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_LSB 0
112631 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field. */
112632 #define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_MSB 31
112633 /* The width in bits of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field. */
112634 #define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_WIDTH 32
112635 /* The mask used to set the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field value. */
112636 #define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_SET_MSK 0xffffffff
112637 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field value. */
112638 #define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_CLR_MSK 0x00000000
112639 /* The reset value of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field is UNKNOWN. */
112640 #define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_RESET 0x0
112641 /* Extracts the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 field value from a register. */
112642 #define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_GET(value) (((value) & 0xffffffff) >> 0)
112643 /* Produces a ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field value suitable for setting the register. */
112644 #define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_SET(value) (((value) << 0) & 0xffffffff)
112645 
112646 #ifndef __ASSEMBLY__
112647 /*
112648  * WARNING: The C register and register group struct declarations are provided for
112649  * convenience and illustrative purposes. They should, however, be used with
112650  * caution as the C language standard provides no guarantees about the alignment or
112651  * atomicity of device memory accesses. The recommended practice for writing
112652  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
112653  * alt_write_word() functions.
112654  *
112655  * The struct declaration for register ALT_USB_DEV_DOEPDMAB3.
112656  */
112657 struct ALT_USB_DEV_DOEPDMAB3_s
112658 {
112659  const uint32_t doepdmab3 : 32; /* ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 */
112660 };
112661 
112662 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB3. */
112663 typedef volatile struct ALT_USB_DEV_DOEPDMAB3_s ALT_USB_DEV_DOEPDMAB3_t;
112664 #endif /* __ASSEMBLY__ */
112665 
112666 /* The reset value of the ALT_USB_DEV_DOEPDMAB3 register. */
112667 #define ALT_USB_DEV_DOEPDMAB3_RESET 0x00000000
112668 /* The byte offset of the ALT_USB_DEV_DOEPDMAB3 register from the beginning of the component. */
112669 #define ALT_USB_DEV_DOEPDMAB3_OFST 0x37c
112670 /* The address of the ALT_USB_DEV_DOEPDMAB3 register. */
112671 #define ALT_USB_DEV_DOEPDMAB3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB3_OFST))
112672 
112673 /*
112674  * Register : doepctl4
112675  *
112676  * Device Control OUT Endpoint 4 Control Register
112677  *
112678  * Register Layout
112679  *
112680  * Bits | Access | Reset | Description
112681  * :--------|:---------|:------|:------------------------------
112682  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL4_MPS
112683  * [14:11] | ??? | 0x0 | *UNDEFINED*
112684  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL4_USBACTEP
112685  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL4_DPID
112686  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL4_NAKSTS
112687  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL4_EPTYPE
112688  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL4_SNP
112689  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL4_STALL
112690  * [25:22] | ??? | 0x0 | *UNDEFINED*
112691  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL4_CNAK
112692  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL4_SNAK
112693  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL4_SETD0PID
112694  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL4_SETD1PID
112695  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL4_EPDIS
112696  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL4_EPENA
112697  *
112698  */
112699 /*
112700  * Field : mps
112701  *
112702  * Maximum Packet Size (MPS)
112703  *
112704  * The application must program this field with the maximum packet size for the
112705  * current
112706  *
112707  * logical endpoint. This value is in bytes.
112708  *
112709  * Field Access Macros:
112710  *
112711  */
112712 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_MPS register field. */
112713 #define ALT_USB_DEV_DOEPCTL4_MPS_LSB 0
112714 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_MPS register field. */
112715 #define ALT_USB_DEV_DOEPCTL4_MPS_MSB 10
112716 /* The width in bits of the ALT_USB_DEV_DOEPCTL4_MPS register field. */
112717 #define ALT_USB_DEV_DOEPCTL4_MPS_WIDTH 11
112718 /* The mask used to set the ALT_USB_DEV_DOEPCTL4_MPS register field value. */
112719 #define ALT_USB_DEV_DOEPCTL4_MPS_SET_MSK 0x000007ff
112720 /* The mask used to clear the ALT_USB_DEV_DOEPCTL4_MPS register field value. */
112721 #define ALT_USB_DEV_DOEPCTL4_MPS_CLR_MSK 0xfffff800
112722 /* The reset value of the ALT_USB_DEV_DOEPCTL4_MPS register field. */
112723 #define ALT_USB_DEV_DOEPCTL4_MPS_RESET 0x0
112724 /* Extracts the ALT_USB_DEV_DOEPCTL4_MPS field value from a register. */
112725 #define ALT_USB_DEV_DOEPCTL4_MPS_GET(value) (((value) & 0x000007ff) >> 0)
112726 /* Produces a ALT_USB_DEV_DOEPCTL4_MPS register field value suitable for setting the register. */
112727 #define ALT_USB_DEV_DOEPCTL4_MPS_SET(value) (((value) << 0) & 0x000007ff)
112728 
112729 /*
112730  * Field : usbactep
112731  *
112732  * USB Active Endpoint (USBActEP)
112733  *
112734  * Indicates whether this endpoint is active in the current configuration and
112735  * interface. The
112736  *
112737  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
112738  * reset. After
112739  *
112740  * receiving the SetConfiguration and SetInterface commands, the application must
112741  *
112742  * program endpoint registers accordingly and set this bit.
112743  *
112744  * Field Enumeration Values:
112745  *
112746  * Enum | Value | Description
112747  * :-------------------------------------|:------|:--------------------
112748  * ALT_USB_DEV_DOEPCTL4_USBACTEP_E_DISD | 0x0 | Not Active
112749  * ALT_USB_DEV_DOEPCTL4_USBACTEP_E_END | 0x1 | USB Active Endpoint
112750  *
112751  * Field Access Macros:
112752  *
112753  */
112754 /*
112755  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_USBACTEP
112756  *
112757  * Not Active
112758  */
112759 #define ALT_USB_DEV_DOEPCTL4_USBACTEP_E_DISD 0x0
112760 /*
112761  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_USBACTEP
112762  *
112763  * USB Active Endpoint
112764  */
112765 #define ALT_USB_DEV_DOEPCTL4_USBACTEP_E_END 0x1
112766 
112767 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */
112768 #define ALT_USB_DEV_DOEPCTL4_USBACTEP_LSB 15
112769 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */
112770 #define ALT_USB_DEV_DOEPCTL4_USBACTEP_MSB 15
112771 /* The width in bits of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */
112772 #define ALT_USB_DEV_DOEPCTL4_USBACTEP_WIDTH 1
112773 /* The mask used to set the ALT_USB_DEV_DOEPCTL4_USBACTEP register field value. */
112774 #define ALT_USB_DEV_DOEPCTL4_USBACTEP_SET_MSK 0x00008000
112775 /* The mask used to clear the ALT_USB_DEV_DOEPCTL4_USBACTEP register field value. */
112776 #define ALT_USB_DEV_DOEPCTL4_USBACTEP_CLR_MSK 0xffff7fff
112777 /* The reset value of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */
112778 #define ALT_USB_DEV_DOEPCTL4_USBACTEP_RESET 0x0
112779 /* Extracts the ALT_USB_DEV_DOEPCTL4_USBACTEP field value from a register. */
112780 #define ALT_USB_DEV_DOEPCTL4_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
112781 /* Produces a ALT_USB_DEV_DOEPCTL4_USBACTEP register field value suitable for setting the register. */
112782 #define ALT_USB_DEV_DOEPCTL4_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
112783 
112784 /*
112785  * Field : dpid
112786  *
112787  * Endpoint Data PID (DPID)
112788  *
112789  * Applies to interrupt/bulk IN and OUT endpoints only.
112790  *
112791  * Contains the PID of the packet to be received or transmitted on this endpoint.
112792  * The
112793  *
112794  * application must program the PID of the first packet to be received or
112795  * transmitted on
112796  *
112797  * this endpoint, after the endpoint is activated. The applications use the
112798  * SetD1PID and
112799  *
112800  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
112801  *
112802  * 1'b0: DATA0
112803  *
112804  * 1'b1: DATA1
112805  *
112806  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
112807  *
112808  * DMA mode.
112809  *
112810  * 1'b0 RO
112811  *
112812  * Even/Odd (Micro)Frame (EO_FrNum)
112813  *
112814  * In non-Scatter/Gather DMA mode:
112815  *
112816  * Applies to isochronous IN and OUT endpoints only.
112817  *
112818  * Indicates the (micro)frame number in which the core transmits/receives
112819  * isochronous
112820  *
112821  * data for this endpoint. The application must program the even/odd (micro) frame
112822  *
112823  * number in which it intends to transmit/receive isochronous data for this
112824  * endpoint using
112825  *
112826  * the SetEvnFr and SetOddFr fields in this register.
112827  *
112828  * 1'b0: Even (micro)frame
112829  *
112830  * 1'b1: Odd (micro)frame
112831  *
112832  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
112833  * number
112834  *
112835  * in which to send data is provided in the transmit descriptor structure. The
112836  * frame in
112837  *
112838  * which data is received is updated in receive descriptor structure.
112839  *
112840  * Field Enumeration Values:
112841  *
112842  * Enum | Value | Description
112843  * :----------------------------------|:------|:-----------------------------
112844  * ALT_USB_DEV_DOEPCTL4_DPID_E_INACT | 0x0 | Endpoint Data PID not active
112845  * ALT_USB_DEV_DOEPCTL4_DPID_E_ACT | 0x1 | Endpoint Data PID active
112846  *
112847  * Field Access Macros:
112848  *
112849  */
112850 /*
112851  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_DPID
112852  *
112853  * Endpoint Data PID not active
112854  */
112855 #define ALT_USB_DEV_DOEPCTL4_DPID_E_INACT 0x0
112856 /*
112857  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_DPID
112858  *
112859  * Endpoint Data PID active
112860  */
112861 #define ALT_USB_DEV_DOEPCTL4_DPID_E_ACT 0x1
112862 
112863 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_DPID register field. */
112864 #define ALT_USB_DEV_DOEPCTL4_DPID_LSB 16
112865 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_DPID register field. */
112866 #define ALT_USB_DEV_DOEPCTL4_DPID_MSB 16
112867 /* The width in bits of the ALT_USB_DEV_DOEPCTL4_DPID register field. */
112868 #define ALT_USB_DEV_DOEPCTL4_DPID_WIDTH 1
112869 /* The mask used to set the ALT_USB_DEV_DOEPCTL4_DPID register field value. */
112870 #define ALT_USB_DEV_DOEPCTL4_DPID_SET_MSK 0x00010000
112871 /* The mask used to clear the ALT_USB_DEV_DOEPCTL4_DPID register field value. */
112872 #define ALT_USB_DEV_DOEPCTL4_DPID_CLR_MSK 0xfffeffff
112873 /* The reset value of the ALT_USB_DEV_DOEPCTL4_DPID register field. */
112874 #define ALT_USB_DEV_DOEPCTL4_DPID_RESET 0x0
112875 /* Extracts the ALT_USB_DEV_DOEPCTL4_DPID field value from a register. */
112876 #define ALT_USB_DEV_DOEPCTL4_DPID_GET(value) (((value) & 0x00010000) >> 16)
112877 /* Produces a ALT_USB_DEV_DOEPCTL4_DPID register field value suitable for setting the register. */
112878 #define ALT_USB_DEV_DOEPCTL4_DPID_SET(value) (((value) << 16) & 0x00010000)
112879 
112880 /*
112881  * Field : naksts
112882  *
112883  * NAK Status (NAKSts)
112884  *
112885  * Indicates the following:
112886  *
112887  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
112888  *
112889  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
112890  *
112891  * When either the application or the core sets this bit:
112892  *
112893  * The core stops receiving any data on an OUT endpoint, even if there is space in
112894  *
112895  * the RxFIFO to accommodate the incoming packet.
112896  *
112897  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
112898  *
112899  * endpoint, even if there data is available in the TxFIFO.
112900  *
112901  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
112902  *
112903  * if there data is available in the TxFIFO.
112904  *
112905  * Irrespective of this bit's setting, the core always responds to SETUP data
112906  * packets with
112907  *
112908  * an ACK handshake.
112909  *
112910  * Field Enumeration Values:
112911  *
112912  * Enum | Value | Description
112913  * :-------------------------------------|:------|:------------------------------------------------
112914  * ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
112915  * : | | based on the FIFO status
112916  * ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
112917  * : | | endpoint
112918  *
112919  * Field Access Macros:
112920  *
112921  */
112922 /*
112923  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_NAKSTS
112924  *
112925  * The core is transmitting non-NAK handshakes based on the FIFO status
112926  */
112927 #define ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NONNAK 0x0
112928 /*
112929  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_NAKSTS
112930  *
112931  * The core is transmitting NAK handshakes on this endpoint
112932  */
112933 #define ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NAK 0x1
112934 
112935 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */
112936 #define ALT_USB_DEV_DOEPCTL4_NAKSTS_LSB 17
112937 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */
112938 #define ALT_USB_DEV_DOEPCTL4_NAKSTS_MSB 17
112939 /* The width in bits of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */
112940 #define ALT_USB_DEV_DOEPCTL4_NAKSTS_WIDTH 1
112941 /* The mask used to set the ALT_USB_DEV_DOEPCTL4_NAKSTS register field value. */
112942 #define ALT_USB_DEV_DOEPCTL4_NAKSTS_SET_MSK 0x00020000
112943 /* The mask used to clear the ALT_USB_DEV_DOEPCTL4_NAKSTS register field value. */
112944 #define ALT_USB_DEV_DOEPCTL4_NAKSTS_CLR_MSK 0xfffdffff
112945 /* The reset value of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */
112946 #define ALT_USB_DEV_DOEPCTL4_NAKSTS_RESET 0x0
112947 /* Extracts the ALT_USB_DEV_DOEPCTL4_NAKSTS field value from a register. */
112948 #define ALT_USB_DEV_DOEPCTL4_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
112949 /* Produces a ALT_USB_DEV_DOEPCTL4_NAKSTS register field value suitable for setting the register. */
112950 #define ALT_USB_DEV_DOEPCTL4_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
112951 
112952 /*
112953  * Field : eptype
112954  *
112955  * Endpoint Type (EPType)
112956  *
112957  * This is the transfer type supported by this logical endpoint.
112958  *
112959  * 2'b00: Control
112960  *
112961  * 2'b01: Isochronous
112962  *
112963  * 2'b10: Bulk
112964  *
112965  * 2'b11: Interrupt
112966  *
112967  * Field Enumeration Values:
112968  *
112969  * Enum | Value | Description
112970  * :------------------------------------------|:------|:------------
112971  * ALT_USB_DEV_DOEPCTL4_EPTYPE_E_CTL | 0x0 | Control
112972  * ALT_USB_DEV_DOEPCTL4_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
112973  * ALT_USB_DEV_DOEPCTL4_EPTYPE_E_BULK | 0x2 | Bulk
112974  * ALT_USB_DEV_DOEPCTL4_EPTYPE_E_INTERRUP | 0x3 | Interrupt
112975  *
112976  * Field Access Macros:
112977  *
112978  */
112979 /*
112980  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE
112981  *
112982  * Control
112983  */
112984 #define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_CTL 0x0
112985 /*
112986  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE
112987  *
112988  * Isochronous
112989  */
112990 #define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_ISOCHRONOUS 0x1
112991 /*
112992  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE
112993  *
112994  * Bulk
112995  */
112996 #define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_BULK 0x2
112997 /*
112998  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE
112999  *
113000  * Interrupt
113001  */
113002 #define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_INTERRUP 0x3
113003 
113004 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */
113005 #define ALT_USB_DEV_DOEPCTL4_EPTYPE_LSB 18
113006 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */
113007 #define ALT_USB_DEV_DOEPCTL4_EPTYPE_MSB 19
113008 /* The width in bits of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */
113009 #define ALT_USB_DEV_DOEPCTL4_EPTYPE_WIDTH 2
113010 /* The mask used to set the ALT_USB_DEV_DOEPCTL4_EPTYPE register field value. */
113011 #define ALT_USB_DEV_DOEPCTL4_EPTYPE_SET_MSK 0x000c0000
113012 /* The mask used to clear the ALT_USB_DEV_DOEPCTL4_EPTYPE register field value. */
113013 #define ALT_USB_DEV_DOEPCTL4_EPTYPE_CLR_MSK 0xfff3ffff
113014 /* The reset value of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */
113015 #define ALT_USB_DEV_DOEPCTL4_EPTYPE_RESET 0x0
113016 /* Extracts the ALT_USB_DEV_DOEPCTL4_EPTYPE field value from a register. */
113017 #define ALT_USB_DEV_DOEPCTL4_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
113018 /* Produces a ALT_USB_DEV_DOEPCTL4_EPTYPE register field value suitable for setting the register. */
113019 #define ALT_USB_DEV_DOEPCTL4_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
113020 
113021 /*
113022  * Field : snp
113023  *
113024  * Snoop Mode (Snp)
113025  *
113026  * Applies to OUT endpoints only.
113027  *
113028  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
113029  *
113030  * check the correctness of OUT packets before transferring them to application
113031  * memory.
113032  *
113033  * Field Enumeration Values:
113034  *
113035  * Enum | Value | Description
113036  * :-------------------------------|:------|:-------------------
113037  * ALT_USB_DEV_DOEPCTL4_SNP_E_DIS | 0x0 | Disable Snoop Mode
113038  * ALT_USB_DEV_DOEPCTL4_SNP_E_EN | 0x1 | Enable Snoop Mode
113039  *
113040  * Field Access Macros:
113041  *
113042  */
113043 /*
113044  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNP
113045  *
113046  * Disable Snoop Mode
113047  */
113048 #define ALT_USB_DEV_DOEPCTL4_SNP_E_DIS 0x0
113049 /*
113050  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNP
113051  *
113052  * Enable Snoop Mode
113053  */
113054 #define ALT_USB_DEV_DOEPCTL4_SNP_E_EN 0x1
113055 
113056 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SNP register field. */
113057 #define ALT_USB_DEV_DOEPCTL4_SNP_LSB 20
113058 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SNP register field. */
113059 #define ALT_USB_DEV_DOEPCTL4_SNP_MSB 20
113060 /* The width in bits of the ALT_USB_DEV_DOEPCTL4_SNP register field. */
113061 #define ALT_USB_DEV_DOEPCTL4_SNP_WIDTH 1
113062 /* The mask used to set the ALT_USB_DEV_DOEPCTL4_SNP register field value. */
113063 #define ALT_USB_DEV_DOEPCTL4_SNP_SET_MSK 0x00100000
113064 /* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SNP register field value. */
113065 #define ALT_USB_DEV_DOEPCTL4_SNP_CLR_MSK 0xffefffff
113066 /* The reset value of the ALT_USB_DEV_DOEPCTL4_SNP register field. */
113067 #define ALT_USB_DEV_DOEPCTL4_SNP_RESET 0x0
113068 /* Extracts the ALT_USB_DEV_DOEPCTL4_SNP field value from a register. */
113069 #define ALT_USB_DEV_DOEPCTL4_SNP_GET(value) (((value) & 0x00100000) >> 20)
113070 /* Produces a ALT_USB_DEV_DOEPCTL4_SNP register field value suitable for setting the register. */
113071 #define ALT_USB_DEV_DOEPCTL4_SNP_SET(value) (((value) << 20) & 0x00100000)
113072 
113073 /*
113074  * Field : stall
113075  *
113076  * STALL Handshake (Stall)
113077  *
113078  * Applies to non-control, non-isochronous IN and OUT endpoints only.
113079  *
113080  * The application sets this bit to stall all tokens from the USB host to this
113081  * endpoint. If a
113082  *
113083  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
113084  * bit, the
113085  *
113086  * STALL bit takes priority. Only the application can clear this bit, never the
113087  * core.
113088  *
113089  * 1'b0 R_W
113090  *
113091  * Applies to control endpoints only.
113092  *
113093  * The application can only set this bit, and the core clears it, when a SETUP
113094  * token is
113095  *
113096  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
113097  * OUT
113098  *
113099  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
113100  * this bit's
113101  *
113102  * setting, the core always responds to SETUP data packets with an ACK handshake.
113103  *
113104  * Field Enumeration Values:
113105  *
113106  * Enum | Value | Description
113107  * :-----------------------------------|:------|:----------------------------
113108  * ALT_USB_DEV_DOEPCTL4_STALL_E_INACT | 0x0 | STALL All Tokens not active
113109  * ALT_USB_DEV_DOEPCTL4_STALL_E_ACT | 0x1 | STALL All Tokens active
113110  *
113111  * Field Access Macros:
113112  *
113113  */
113114 /*
113115  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_STALL
113116  *
113117  * STALL All Tokens not active
113118  */
113119 #define ALT_USB_DEV_DOEPCTL4_STALL_E_INACT 0x0
113120 /*
113121  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_STALL
113122  *
113123  * STALL All Tokens active
113124  */
113125 #define ALT_USB_DEV_DOEPCTL4_STALL_E_ACT 0x1
113126 
113127 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_STALL register field. */
113128 #define ALT_USB_DEV_DOEPCTL4_STALL_LSB 21
113129 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_STALL register field. */
113130 #define ALT_USB_DEV_DOEPCTL4_STALL_MSB 21
113131 /* The width in bits of the ALT_USB_DEV_DOEPCTL4_STALL register field. */
113132 #define ALT_USB_DEV_DOEPCTL4_STALL_WIDTH 1
113133 /* The mask used to set the ALT_USB_DEV_DOEPCTL4_STALL register field value. */
113134 #define ALT_USB_DEV_DOEPCTL4_STALL_SET_MSK 0x00200000
113135 /* The mask used to clear the ALT_USB_DEV_DOEPCTL4_STALL register field value. */
113136 #define ALT_USB_DEV_DOEPCTL4_STALL_CLR_MSK 0xffdfffff
113137 /* The reset value of the ALT_USB_DEV_DOEPCTL4_STALL register field. */
113138 #define ALT_USB_DEV_DOEPCTL4_STALL_RESET 0x0
113139 /* Extracts the ALT_USB_DEV_DOEPCTL4_STALL field value from a register. */
113140 #define ALT_USB_DEV_DOEPCTL4_STALL_GET(value) (((value) & 0x00200000) >> 21)
113141 /* Produces a ALT_USB_DEV_DOEPCTL4_STALL register field value suitable for setting the register. */
113142 #define ALT_USB_DEV_DOEPCTL4_STALL_SET(value) (((value) << 21) & 0x00200000)
113143 
113144 /*
113145  * Field : cnak
113146  *
113147  * Clear NAK (CNAK)
113148  *
113149  * A write to this bit clears the NAK bit For the endpoint.
113150  *
113151  * Field Enumeration Values:
113152  *
113153  * Enum | Value | Description
113154  * :----------------------------------|:------|:-------------
113155  * ALT_USB_DEV_DOEPCTL4_CNAK_E_INACT | 0x0 | No Clear NAK
113156  * ALT_USB_DEV_DOEPCTL4_CNAK_E_ACT | 0x1 | Clear NAK
113157  *
113158  * Field Access Macros:
113159  *
113160  */
113161 /*
113162  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_CNAK
113163  *
113164  * No Clear NAK
113165  */
113166 #define ALT_USB_DEV_DOEPCTL4_CNAK_E_INACT 0x0
113167 /*
113168  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_CNAK
113169  *
113170  * Clear NAK
113171  */
113172 #define ALT_USB_DEV_DOEPCTL4_CNAK_E_ACT 0x1
113173 
113174 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */
113175 #define ALT_USB_DEV_DOEPCTL4_CNAK_LSB 26
113176 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */
113177 #define ALT_USB_DEV_DOEPCTL4_CNAK_MSB 26
113178 /* The width in bits of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */
113179 #define ALT_USB_DEV_DOEPCTL4_CNAK_WIDTH 1
113180 /* The mask used to set the ALT_USB_DEV_DOEPCTL4_CNAK register field value. */
113181 #define ALT_USB_DEV_DOEPCTL4_CNAK_SET_MSK 0x04000000
113182 /* The mask used to clear the ALT_USB_DEV_DOEPCTL4_CNAK register field value. */
113183 #define ALT_USB_DEV_DOEPCTL4_CNAK_CLR_MSK 0xfbffffff
113184 /* The reset value of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */
113185 #define ALT_USB_DEV_DOEPCTL4_CNAK_RESET 0x0
113186 /* Extracts the ALT_USB_DEV_DOEPCTL4_CNAK field value from a register. */
113187 #define ALT_USB_DEV_DOEPCTL4_CNAK_GET(value) (((value) & 0x04000000) >> 26)
113188 /* Produces a ALT_USB_DEV_DOEPCTL4_CNAK register field value suitable for setting the register. */
113189 #define ALT_USB_DEV_DOEPCTL4_CNAK_SET(value) (((value) << 26) & 0x04000000)
113190 
113191 /*
113192  * Field : snak
113193  *
113194  * Set NAK (SNAK)
113195  *
113196  * A write to this bit sets the NAK bit For the endpoint.
113197  *
113198  * Using this bit, the application can control the transmission of NAK
113199  *
113200  * handshakes on an endpoint. The core can also Set this bit For an
113201  *
113202  * endpoint after a SETUP packet is received on that endpoint.
113203  *
113204  * Field Enumeration Values:
113205  *
113206  * Enum | Value | Description
113207  * :----------------------------------|:------|:------------
113208  * ALT_USB_DEV_DOEPCTL4_SNAK_E_INACT | 0x0 | No Set NAK
113209  * ALT_USB_DEV_DOEPCTL4_SNAK_E_ACT | 0x1 | Set NAK
113210  *
113211  * Field Access Macros:
113212  *
113213  */
113214 /*
113215  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNAK
113216  *
113217  * No Set NAK
113218  */
113219 #define ALT_USB_DEV_DOEPCTL4_SNAK_E_INACT 0x0
113220 /*
113221  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNAK
113222  *
113223  * Set NAK
113224  */
113225 #define ALT_USB_DEV_DOEPCTL4_SNAK_E_ACT 0x1
113226 
113227 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */
113228 #define ALT_USB_DEV_DOEPCTL4_SNAK_LSB 27
113229 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */
113230 #define ALT_USB_DEV_DOEPCTL4_SNAK_MSB 27
113231 /* The width in bits of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */
113232 #define ALT_USB_DEV_DOEPCTL4_SNAK_WIDTH 1
113233 /* The mask used to set the ALT_USB_DEV_DOEPCTL4_SNAK register field value. */
113234 #define ALT_USB_DEV_DOEPCTL4_SNAK_SET_MSK 0x08000000
113235 /* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SNAK register field value. */
113236 #define ALT_USB_DEV_DOEPCTL4_SNAK_CLR_MSK 0xf7ffffff
113237 /* The reset value of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */
113238 #define ALT_USB_DEV_DOEPCTL4_SNAK_RESET 0x0
113239 /* Extracts the ALT_USB_DEV_DOEPCTL4_SNAK field value from a register. */
113240 #define ALT_USB_DEV_DOEPCTL4_SNAK_GET(value) (((value) & 0x08000000) >> 27)
113241 /* Produces a ALT_USB_DEV_DOEPCTL4_SNAK register field value suitable for setting the register. */
113242 #define ALT_USB_DEV_DOEPCTL4_SNAK_SET(value) (((value) << 27) & 0x08000000)
113243 
113244 /*
113245  * Field : setd0pid
113246  *
113247  * Set DATA0 PID (SetD0PID)
113248  *
113249  * Applies to interrupt/bulk IN and OUT endpoints only.
113250  *
113251  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
113252  * to DATA0.
113253  *
113254  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
113255  *
113256  * DMA mode.
113257  *
113258  * 1'b0 WO
113259  *
113260  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
113261  *
113262  * Applies to isochronous IN and OUT endpoints only.
113263  *
113264  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
113265  * (micro)
113266  *
113267  * frame.
113268  *
113269  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
113270  * number
113271  *
113272  * in which to send data is in the transmit descriptor structure. The frame in
113273  * which to
113274  *
113275  * receive data is updated in receive descriptor structure.
113276  *
113277  * Field Enumeration Values:
113278  *
113279  * Enum | Value | Description
113280  * :-------------------------------------|:------|:------------------------------------
113281  * ALT_USB_DEV_DOEPCTL4_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
113282  * ALT_USB_DEV_DOEPCTL4_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
113283  *
113284  * Field Access Macros:
113285  *
113286  */
113287 /*
113288  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD0PID
113289  *
113290  * Disables Set DATA0 PID
113291  */
113292 #define ALT_USB_DEV_DOEPCTL4_SETD0PID_E_DISD 0x0
113293 /*
113294  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD0PID
113295  *
113296  * Enables Endpoint Data PID to DATA0)
113297  */
113298 #define ALT_USB_DEV_DOEPCTL4_SETD0PID_E_END 0x1
113299 
113300 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */
113301 #define ALT_USB_DEV_DOEPCTL4_SETD0PID_LSB 28
113302 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */
113303 #define ALT_USB_DEV_DOEPCTL4_SETD0PID_MSB 28
113304 /* The width in bits of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */
113305 #define ALT_USB_DEV_DOEPCTL4_SETD0PID_WIDTH 1
113306 /* The mask used to set the ALT_USB_DEV_DOEPCTL4_SETD0PID register field value. */
113307 #define ALT_USB_DEV_DOEPCTL4_SETD0PID_SET_MSK 0x10000000
113308 /* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SETD0PID register field value. */
113309 #define ALT_USB_DEV_DOEPCTL4_SETD0PID_CLR_MSK 0xefffffff
113310 /* The reset value of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */
113311 #define ALT_USB_DEV_DOEPCTL4_SETD0PID_RESET 0x0
113312 /* Extracts the ALT_USB_DEV_DOEPCTL4_SETD0PID field value from a register. */
113313 #define ALT_USB_DEV_DOEPCTL4_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
113314 /* Produces a ALT_USB_DEV_DOEPCTL4_SETD0PID register field value suitable for setting the register. */
113315 #define ALT_USB_DEV_DOEPCTL4_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
113316 
113317 /*
113318  * Field : setd1pid
113319  *
113320  * Set DATA1 PID (SetD1PID)
113321  *
113322  * Applies to interrupt/bulk IN and OUT endpoints only.
113323  *
113324  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
113325  * to DATA1.
113326  *
113327  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
113328  *
113329  * DMA mode.
113330  *
113331  * Set Odd (micro)frame (SetOddFr)
113332  *
113333  * Applies to isochronous IN and OUT endpoints only.
113334  *
113335  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
113336  *
113337  * (micro)frame.
113338  *
113339  * This field is not applicable for Scatter/Gather DMA mode.
113340  *
113341  * Field Enumeration Values:
113342  *
113343  * Enum | Value | Description
113344  * :-------------------------------------|:------|:-----------------------
113345  * ALT_USB_DEV_DOEPCTL4_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
113346  * ALT_USB_DEV_DOEPCTL4_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
113347  *
113348  * Field Access Macros:
113349  *
113350  */
113351 /*
113352  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD1PID
113353  *
113354  * Disables Set DATA1 PID
113355  */
113356 #define ALT_USB_DEV_DOEPCTL4_SETD1PID_E_DISD 0x0
113357 /*
113358  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD1PID
113359  *
113360  * Enables Set DATA1 PID
113361  */
113362 #define ALT_USB_DEV_DOEPCTL4_SETD1PID_E_END 0x1
113363 
113364 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */
113365 #define ALT_USB_DEV_DOEPCTL4_SETD1PID_LSB 29
113366 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */
113367 #define ALT_USB_DEV_DOEPCTL4_SETD1PID_MSB 29
113368 /* The width in bits of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */
113369 #define ALT_USB_DEV_DOEPCTL4_SETD1PID_WIDTH 1
113370 /* The mask used to set the ALT_USB_DEV_DOEPCTL4_SETD1PID register field value. */
113371 #define ALT_USB_DEV_DOEPCTL4_SETD1PID_SET_MSK 0x20000000
113372 /* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SETD1PID register field value. */
113373 #define ALT_USB_DEV_DOEPCTL4_SETD1PID_CLR_MSK 0xdfffffff
113374 /* The reset value of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */
113375 #define ALT_USB_DEV_DOEPCTL4_SETD1PID_RESET 0x0
113376 /* Extracts the ALT_USB_DEV_DOEPCTL4_SETD1PID field value from a register. */
113377 #define ALT_USB_DEV_DOEPCTL4_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
113378 /* Produces a ALT_USB_DEV_DOEPCTL4_SETD1PID register field value suitable for setting the register. */
113379 #define ALT_USB_DEV_DOEPCTL4_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
113380 
113381 /*
113382  * Field : epdis
113383  *
113384  * Endpoint Disable (EPDis)
113385  *
113386  * Applies to IN and OUT endpoints.
113387  *
113388  * The application sets this bit to stop transmitting/receiving data on an
113389  * endpoint, even
113390  *
113391  * before the transfer for that endpoint is complete. The application must wait for
113392  * the
113393  *
113394  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
113395  * clears
113396  *
113397  * this bit before setting the Endpoint Disabled interrupt. The application must
113398  * set this bit
113399  *
113400  * only if Endpoint Enable is already set for this endpoint.
113401  *
113402  * Field Enumeration Values:
113403  *
113404  * Enum | Value | Description
113405  * :-----------------------------------|:------|:--------------------
113406  * ALT_USB_DEV_DOEPCTL4_EPDIS_E_INACT | 0x0 | No Endpoint Disable
113407  * ALT_USB_DEV_DOEPCTL4_EPDIS_E_ACT | 0x1 | Endpoint Disable
113408  *
113409  * Field Access Macros:
113410  *
113411  */
113412 /*
113413  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPDIS
113414  *
113415  * No Endpoint Disable
113416  */
113417 #define ALT_USB_DEV_DOEPCTL4_EPDIS_E_INACT 0x0
113418 /*
113419  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPDIS
113420  *
113421  * Endpoint Disable
113422  */
113423 #define ALT_USB_DEV_DOEPCTL4_EPDIS_E_ACT 0x1
113424 
113425 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */
113426 #define ALT_USB_DEV_DOEPCTL4_EPDIS_LSB 30
113427 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */
113428 #define ALT_USB_DEV_DOEPCTL4_EPDIS_MSB 30
113429 /* The width in bits of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */
113430 #define ALT_USB_DEV_DOEPCTL4_EPDIS_WIDTH 1
113431 /* The mask used to set the ALT_USB_DEV_DOEPCTL4_EPDIS register field value. */
113432 #define ALT_USB_DEV_DOEPCTL4_EPDIS_SET_MSK 0x40000000
113433 /* The mask used to clear the ALT_USB_DEV_DOEPCTL4_EPDIS register field value. */
113434 #define ALT_USB_DEV_DOEPCTL4_EPDIS_CLR_MSK 0xbfffffff
113435 /* The reset value of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */
113436 #define ALT_USB_DEV_DOEPCTL4_EPDIS_RESET 0x0
113437 /* Extracts the ALT_USB_DEV_DOEPCTL4_EPDIS field value from a register. */
113438 #define ALT_USB_DEV_DOEPCTL4_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
113439 /* Produces a ALT_USB_DEV_DOEPCTL4_EPDIS register field value suitable for setting the register. */
113440 #define ALT_USB_DEV_DOEPCTL4_EPDIS_SET(value) (((value) << 30) & 0x40000000)
113441 
113442 /*
113443  * Field : epena
113444  *
113445  * Endpoint Enable (EPEna)
113446  *
113447  * Applies to IN and OUT endpoints.
113448  *
113449  * When Scatter/Gather DMA mode is enabled,
113450  *
113451  * For IN endpoints this bit indicates that the descriptor structure and data
113452  * buffer with
113453  *
113454  * data ready to transmit is setup.
113455  *
113456  * For OUT endpoint it indicates that the descriptor structure and data buffer to
113457  *
113458  * receive data is setup.
113459  *
113460  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
113461  *
113462  * DMA mode:
113463  *
113464  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
113465  * the
113466  *
113467  * endpoint.
113468  *
113469  * * For OUT endpoints, this bit indicates that the application has allocated the
113470  *
113471  * memory to start receiving data from the USB.
113472  *
113473  * * The core clears this bit before setting any of the following interrupts on
113474  * this
113475  *
113476  * endpoint:
113477  *
113478  * SETUP Phase Done
113479  *
113480  * Endpoint Disabled
113481  *
113482  * Transfer Completed
113483  *
113484  * Note: For control endpoints in DMA mode, this bit must be set to be able to
113485  * transfer
113486  *
113487  * SETUP data packets in memory.
113488  *
113489  * Field Enumeration Values:
113490  *
113491  * Enum | Value | Description
113492  * :-----------------------------------|:------|:-------------------------
113493  * ALT_USB_DEV_DOEPCTL4_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
113494  * ALT_USB_DEV_DOEPCTL4_EPENA_E_ACT | 0x1 | Endpoint Enable active
113495  *
113496  * Field Access Macros:
113497  *
113498  */
113499 /*
113500  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPENA
113501  *
113502  * Endpoint Enable inactive
113503  */
113504 #define ALT_USB_DEV_DOEPCTL4_EPENA_E_INACT 0x0
113505 /*
113506  * Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPENA
113507  *
113508  * Endpoint Enable active
113509  */
113510 #define ALT_USB_DEV_DOEPCTL4_EPENA_E_ACT 0x1
113511 
113512 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */
113513 #define ALT_USB_DEV_DOEPCTL4_EPENA_LSB 31
113514 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */
113515 #define ALT_USB_DEV_DOEPCTL4_EPENA_MSB 31
113516 /* The width in bits of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */
113517 #define ALT_USB_DEV_DOEPCTL4_EPENA_WIDTH 1
113518 /* The mask used to set the ALT_USB_DEV_DOEPCTL4_EPENA register field value. */
113519 #define ALT_USB_DEV_DOEPCTL4_EPENA_SET_MSK 0x80000000
113520 /* The mask used to clear the ALT_USB_DEV_DOEPCTL4_EPENA register field value. */
113521 #define ALT_USB_DEV_DOEPCTL4_EPENA_CLR_MSK 0x7fffffff
113522 /* The reset value of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */
113523 #define ALT_USB_DEV_DOEPCTL4_EPENA_RESET 0x0
113524 /* Extracts the ALT_USB_DEV_DOEPCTL4_EPENA field value from a register. */
113525 #define ALT_USB_DEV_DOEPCTL4_EPENA_GET(value) (((value) & 0x80000000) >> 31)
113526 /* Produces a ALT_USB_DEV_DOEPCTL4_EPENA register field value suitable for setting the register. */
113527 #define ALT_USB_DEV_DOEPCTL4_EPENA_SET(value) (((value) << 31) & 0x80000000)
113528 
113529 #ifndef __ASSEMBLY__
113530 /*
113531  * WARNING: The C register and register group struct declarations are provided for
113532  * convenience and illustrative purposes. They should, however, be used with
113533  * caution as the C language standard provides no guarantees about the alignment or
113534  * atomicity of device memory accesses. The recommended practice for writing
113535  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
113536  * alt_write_word() functions.
113537  *
113538  * The struct declaration for register ALT_USB_DEV_DOEPCTL4.
113539  */
113540 struct ALT_USB_DEV_DOEPCTL4_s
113541 {
113542  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL4_MPS */
113543  uint32_t : 4; /* *UNDEFINED* */
113544  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL4_USBACTEP */
113545  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL4_DPID */
113546  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL4_NAKSTS */
113547  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL4_EPTYPE */
113548  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL4_SNP */
113549  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL4_STALL */
113550  uint32_t : 4; /* *UNDEFINED* */
113551  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL4_CNAK */
113552  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL4_SNAK */
113553  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL4_SETD0PID */
113554  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL4_SETD1PID */
113555  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL4_EPDIS */
113556  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL4_EPENA */
113557 };
113558 
113559 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL4. */
113560 typedef volatile struct ALT_USB_DEV_DOEPCTL4_s ALT_USB_DEV_DOEPCTL4_t;
113561 #endif /* __ASSEMBLY__ */
113562 
113563 /* The reset value of the ALT_USB_DEV_DOEPCTL4 register. */
113564 #define ALT_USB_DEV_DOEPCTL4_RESET 0x00000000
113565 /* The byte offset of the ALT_USB_DEV_DOEPCTL4 register from the beginning of the component. */
113566 #define ALT_USB_DEV_DOEPCTL4_OFST 0x380
113567 /* The address of the ALT_USB_DEV_DOEPCTL4 register. */
113568 #define ALT_USB_DEV_DOEPCTL4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL4_OFST))
113569 
113570 /*
113571  * Register : doepint4
113572  *
113573  * Device OUT Endpoint 4 Interrupt Register
113574  *
113575  * Register Layout
113576  *
113577  * Bits | Access | Reset | Description
113578  * :--------|:-------|:------|:------------------------------------
113579  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_XFERCOMPL
113580  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_EPDISBLD
113581  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_AHBERR
113582  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_SETUP
113583  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS
113584  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_STSPHSERCVD
113585  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP
113586  * [7] | ??? | 0x0 | *UNDEFINED*
113587  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_OUTPKTERR
113588  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_BNAINTR
113589  * [10] | ??? | 0x0 | *UNDEFINED*
113590  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_PKTDRPSTS
113591  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_BBLEERR
113592  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_NAKINTRPT
113593  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_NYETINTRPT
113594  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_STUPPKTRCVD
113595  * [31:16] | ??? | 0x0 | *UNDEFINED*
113596  *
113597  */
113598 /*
113599  * Field : xfercompl
113600  *
113601  * Transfer Completed Interrupt (XferCompl)
113602  *
113603  * Applies to IN and OUT endpoints.
113604  *
113605  * When Scatter/Gather DMA mode is enabled
113606  *
113607  * * For IN endpoint this field indicates that the requested data
113608  *
113609  * from the descriptor is moved from external system memory
113610  *
113611  * to internal FIFO.
113612  *
113613  * * For OUT endpoint this field indicates that the requested
113614  *
113615  * data from the internal FIFO is moved to external system
113616  *
113617  * memory. This interrupt is generated only when the
113618  *
113619  * corresponding endpoint descriptor is closed, and the IOC
113620  *
113621  * bit For the corresponding descriptor is Set.
113622  *
113623  * When Scatter/Gather DMA mode is disabled, this field
113624  *
113625  * indicates that the programmed transfer is complete on the
113626  *
113627  * AHB as well as on the USB, For this endpoint.
113628  *
113629  * Field Enumeration Values:
113630  *
113631  * Enum | Value | Description
113632  * :---------------------------------------|:------|:-----------------------------
113633  * ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_INACT | 0x0 | No Interrupt
113634  * ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
113635  *
113636  * Field Access Macros:
113637  *
113638  */
113639 /*
113640  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_XFERCOMPL
113641  *
113642  * No Interrupt
113643  */
113644 #define ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_INACT 0x0
113645 /*
113646  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_XFERCOMPL
113647  *
113648  * Transfer Completed Interrupt
113649  */
113650 #define ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_ACT 0x1
113651 
113652 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */
113653 #define ALT_USB_DEV_DOEPINT4_XFERCOMPL_LSB 0
113654 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */
113655 #define ALT_USB_DEV_DOEPINT4_XFERCOMPL_MSB 0
113656 /* The width in bits of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */
113657 #define ALT_USB_DEV_DOEPINT4_XFERCOMPL_WIDTH 1
113658 /* The mask used to set the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field value. */
113659 #define ALT_USB_DEV_DOEPINT4_XFERCOMPL_SET_MSK 0x00000001
113660 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field value. */
113661 #define ALT_USB_DEV_DOEPINT4_XFERCOMPL_CLR_MSK 0xfffffffe
113662 /* The reset value of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */
113663 #define ALT_USB_DEV_DOEPINT4_XFERCOMPL_RESET 0x0
113664 /* Extracts the ALT_USB_DEV_DOEPINT4_XFERCOMPL field value from a register. */
113665 #define ALT_USB_DEV_DOEPINT4_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
113666 /* Produces a ALT_USB_DEV_DOEPINT4_XFERCOMPL register field value suitable for setting the register. */
113667 #define ALT_USB_DEV_DOEPINT4_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
113668 
113669 /*
113670  * Field : epdisbld
113671  *
113672  * Endpoint Disabled Interrupt (EPDisbld)
113673  *
113674  * Applies to IN and OUT endpoints.
113675  *
113676  * This bit indicates that the endpoint is disabled per the
113677  *
113678  * application's request.
113679  *
113680  * Field Enumeration Values:
113681  *
113682  * Enum | Value | Description
113683  * :--------------------------------------|:------|:----------------------------
113684  * ALT_USB_DEV_DOEPINT4_EPDISBLD_E_INACT | 0x0 | No Interrupt
113685  * ALT_USB_DEV_DOEPINT4_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
113686  *
113687  * Field Access Macros:
113688  *
113689  */
113690 /*
113691  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_EPDISBLD
113692  *
113693  * No Interrupt
113694  */
113695 #define ALT_USB_DEV_DOEPINT4_EPDISBLD_E_INACT 0x0
113696 /*
113697  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_EPDISBLD
113698  *
113699  * Endpoint Disabled Interrupt
113700  */
113701 #define ALT_USB_DEV_DOEPINT4_EPDISBLD_E_ACT 0x1
113702 
113703 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */
113704 #define ALT_USB_DEV_DOEPINT4_EPDISBLD_LSB 1
113705 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */
113706 #define ALT_USB_DEV_DOEPINT4_EPDISBLD_MSB 1
113707 /* The width in bits of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */
113708 #define ALT_USB_DEV_DOEPINT4_EPDISBLD_WIDTH 1
113709 /* The mask used to set the ALT_USB_DEV_DOEPINT4_EPDISBLD register field value. */
113710 #define ALT_USB_DEV_DOEPINT4_EPDISBLD_SET_MSK 0x00000002
113711 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_EPDISBLD register field value. */
113712 #define ALT_USB_DEV_DOEPINT4_EPDISBLD_CLR_MSK 0xfffffffd
113713 /* The reset value of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */
113714 #define ALT_USB_DEV_DOEPINT4_EPDISBLD_RESET 0x0
113715 /* Extracts the ALT_USB_DEV_DOEPINT4_EPDISBLD field value from a register. */
113716 #define ALT_USB_DEV_DOEPINT4_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
113717 /* Produces a ALT_USB_DEV_DOEPINT4_EPDISBLD register field value suitable for setting the register. */
113718 #define ALT_USB_DEV_DOEPINT4_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
113719 
113720 /*
113721  * Field : ahberr
113722  *
113723  * AHB Error (AHBErr)
113724  *
113725  * Applies to IN and OUT endpoints.
113726  *
113727  * This is generated only in Internal DMA mode when there is an
113728  *
113729  * AHB error during an AHB read/write. The application can read
113730  *
113731  * the corresponding endpoint DMA address register to get the
113732  *
113733  * error address.
113734  *
113735  * Field Enumeration Values:
113736  *
113737  * Enum | Value | Description
113738  * :------------------------------------|:------|:--------------------
113739  * ALT_USB_DEV_DOEPINT4_AHBERR_E_INACT | 0x0 | No Interrupt
113740  * ALT_USB_DEV_DOEPINT4_AHBERR_E_ACT | 0x1 | AHB Error interrupt
113741  *
113742  * Field Access Macros:
113743  *
113744  */
113745 /*
113746  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_AHBERR
113747  *
113748  * No Interrupt
113749  */
113750 #define ALT_USB_DEV_DOEPINT4_AHBERR_E_INACT 0x0
113751 /*
113752  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_AHBERR
113753  *
113754  * AHB Error interrupt
113755  */
113756 #define ALT_USB_DEV_DOEPINT4_AHBERR_E_ACT 0x1
113757 
113758 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */
113759 #define ALT_USB_DEV_DOEPINT4_AHBERR_LSB 2
113760 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */
113761 #define ALT_USB_DEV_DOEPINT4_AHBERR_MSB 2
113762 /* The width in bits of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */
113763 #define ALT_USB_DEV_DOEPINT4_AHBERR_WIDTH 1
113764 /* The mask used to set the ALT_USB_DEV_DOEPINT4_AHBERR register field value. */
113765 #define ALT_USB_DEV_DOEPINT4_AHBERR_SET_MSK 0x00000004
113766 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_AHBERR register field value. */
113767 #define ALT_USB_DEV_DOEPINT4_AHBERR_CLR_MSK 0xfffffffb
113768 /* The reset value of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */
113769 #define ALT_USB_DEV_DOEPINT4_AHBERR_RESET 0x0
113770 /* Extracts the ALT_USB_DEV_DOEPINT4_AHBERR field value from a register. */
113771 #define ALT_USB_DEV_DOEPINT4_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
113772 /* Produces a ALT_USB_DEV_DOEPINT4_AHBERR register field value suitable for setting the register. */
113773 #define ALT_USB_DEV_DOEPINT4_AHBERR_SET(value) (((value) << 2) & 0x00000004)
113774 
113775 /*
113776  * Field : setup
113777  *
113778  * SETUP Phase Done (SetUp)
113779  *
113780  * Applies to control OUT endpoints only.
113781  *
113782  * Indicates that the SETUP phase For the control endpoint is
113783  *
113784  * complete and no more back-to-back SETUP packets were
113785  *
113786  * received For the current control transfer. On this interrupt, the
113787  *
113788  * application can decode the received SETUP data packet.
113789  *
113790  * Field Enumeration Values:
113791  *
113792  * Enum | Value | Description
113793  * :-----------------------------------|:------|:--------------------
113794  * ALT_USB_DEV_DOEPINT4_SETUP_E_INACT | 0x0 | No SETUP Phase Done
113795  * ALT_USB_DEV_DOEPINT4_SETUP_E_ACT | 0x1 | SETUP Phase Done
113796  *
113797  * Field Access Macros:
113798  *
113799  */
113800 /*
113801  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_SETUP
113802  *
113803  * No SETUP Phase Done
113804  */
113805 #define ALT_USB_DEV_DOEPINT4_SETUP_E_INACT 0x0
113806 /*
113807  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_SETUP
113808  *
113809  * SETUP Phase Done
113810  */
113811 #define ALT_USB_DEV_DOEPINT4_SETUP_E_ACT 0x1
113812 
113813 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_SETUP register field. */
113814 #define ALT_USB_DEV_DOEPINT4_SETUP_LSB 3
113815 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_SETUP register field. */
113816 #define ALT_USB_DEV_DOEPINT4_SETUP_MSB 3
113817 /* The width in bits of the ALT_USB_DEV_DOEPINT4_SETUP register field. */
113818 #define ALT_USB_DEV_DOEPINT4_SETUP_WIDTH 1
113819 /* The mask used to set the ALT_USB_DEV_DOEPINT4_SETUP register field value. */
113820 #define ALT_USB_DEV_DOEPINT4_SETUP_SET_MSK 0x00000008
113821 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_SETUP register field value. */
113822 #define ALT_USB_DEV_DOEPINT4_SETUP_CLR_MSK 0xfffffff7
113823 /* The reset value of the ALT_USB_DEV_DOEPINT4_SETUP register field. */
113824 #define ALT_USB_DEV_DOEPINT4_SETUP_RESET 0x0
113825 /* Extracts the ALT_USB_DEV_DOEPINT4_SETUP field value from a register. */
113826 #define ALT_USB_DEV_DOEPINT4_SETUP_GET(value) (((value) & 0x00000008) >> 3)
113827 /* Produces a ALT_USB_DEV_DOEPINT4_SETUP register field value suitable for setting the register. */
113828 #define ALT_USB_DEV_DOEPINT4_SETUP_SET(value) (((value) << 3) & 0x00000008)
113829 
113830 /*
113831  * Field : outtknepdis
113832  *
113833  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
113834  *
113835  * Applies only to control OUT endpoints.
113836  *
113837  * Indicates that an OUT token was received when the endpoint
113838  *
113839  * was not yet enabled. This interrupt is asserted on the endpoint
113840  *
113841  * For which the OUT token was received.
113842  *
113843  * Field Enumeration Values:
113844  *
113845  * Enum | Value | Description
113846  * :-----------------------------------------|:------|:---------------------------------------------
113847  * ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
113848  * ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
113849  *
113850  * Field Access Macros:
113851  *
113852  */
113853 /*
113854  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS
113855  *
113856  * No OUT Token Received When Endpoint Disabled
113857  */
113858 #define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_INACT 0x0
113859 /*
113860  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS
113861  *
113862  * OUT Token Received When Endpoint Disabled
113863  */
113864 #define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_ACT 0x1
113865 
113866 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */
113867 #define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_LSB 4
113868 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */
113869 #define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_MSB 4
113870 /* The width in bits of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */
113871 #define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_WIDTH 1
113872 /* The mask used to set the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field value. */
113873 #define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_SET_MSK 0x00000010
113874 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field value. */
113875 #define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_CLR_MSK 0xffffffef
113876 /* The reset value of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */
113877 #define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_RESET 0x0
113878 /* Extracts the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS field value from a register. */
113879 #define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
113880 /* Produces a ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field value suitable for setting the register. */
113881 #define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
113882 
113883 /*
113884  * Field : stsphsercvd
113885  *
113886  * Status Phase Received For Control Write (StsPhseRcvd)
113887  *
113888  * This interrupt is valid only For Control OUT endpoints and only in
113889  *
113890  * Scatter Gather DMA mode.
113891  *
113892  * This interrupt is generated only after the core has transferred all
113893  *
113894  * the data that the host has sent during the data phase of a control
113895  *
113896  * write transfer, to the system memory buffer.
113897  *
113898  * The interrupt indicates to the application that the host has
113899  *
113900  * switched from data phase to the status phase of a Control Write
113901  *
113902  * transfer. The application can use this interrupt to ACK or STALL
113903  *
113904  * the Status phase, after it has decoded the data phase. This is
113905  *
113906  * applicable only in Case of Scatter Gather DMA mode.
113907  *
113908  * Field Enumeration Values:
113909  *
113910  * Enum | Value | Description
113911  * :-----------------------------------------|:------|:-------------------------------------------
113912  * ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
113913  * ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
113914  *
113915  * Field Access Macros:
113916  *
113917  */
113918 /*
113919  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_STSPHSERCVD
113920  *
113921  * No Status Phase Received for Control Write
113922  */
113923 #define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_INACT 0x0
113924 /*
113925  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_STSPHSERCVD
113926  *
113927  * Status Phase Received for Control Write
113928  */
113929 #define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_ACT 0x1
113930 
113931 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */
113932 #define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_LSB 5
113933 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */
113934 #define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_MSB 5
113935 /* The width in bits of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */
113936 #define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_WIDTH 1
113937 /* The mask used to set the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field value. */
113938 #define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_SET_MSK 0x00000020
113939 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field value. */
113940 #define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_CLR_MSK 0xffffffdf
113941 /* The reset value of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */
113942 #define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_RESET 0x0
113943 /* Extracts the ALT_USB_DEV_DOEPINT4_STSPHSERCVD field value from a register. */
113944 #define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
113945 /* Produces a ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field value suitable for setting the register. */
113946 #define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
113947 
113948 /*
113949  * Field : back2backsetup
113950  *
113951  * Back-to-Back SETUP Packets Received (Back2BackSETup)
113952  *
113953  * Applies to Control OUT endpoints only.
113954  *
113955  * This bit indicates that the core has received more than three
113956  *
113957  * back-to-back SETUP packets For this particular endpoint. For
113958  *
113959  * information about handling this interrupt,
113960  *
113961  * Field Enumeration Values:
113962  *
113963  * Enum | Value | Description
113964  * :--------------------------------------------|:------|:---------------------------------------
113965  * ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
113966  * ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
113967  *
113968  * Field Access Macros:
113969  *
113970  */
113971 /*
113972  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP
113973  *
113974  * No Back-to-Back SETUP Packets Received
113975  */
113976 #define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_INACT 0x0
113977 /*
113978  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP
113979  *
113980  * Back-to-Back SETUP Packets Received
113981  */
113982 #define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_ACT 0x1
113983 
113984 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */
113985 #define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_LSB 6
113986 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */
113987 #define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_MSB 6
113988 /* The width in bits of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */
113989 #define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_WIDTH 1
113990 /* The mask used to set the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field value. */
113991 #define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_SET_MSK 0x00000040
113992 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field value. */
113993 #define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_CLR_MSK 0xffffffbf
113994 /* The reset value of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */
113995 #define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_RESET 0x0
113996 /* Extracts the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP field value from a register. */
113997 #define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
113998 /* Produces a ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field value suitable for setting the register. */
113999 #define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
114000 
114001 /*
114002  * Field : outpkterr
114003  *
114004  * OUT Packet Error (OutPktErr)
114005  *
114006  * Applies to OUT endpoints Only
114007  *
114008  * This interrupt is valid only when thresholding is enabled. This interrupt is
114009  * asserted when the
114010  *
114011  * core detects an overflow or a CRC error For non-Isochronous
114012  *
114013  * OUT packet.
114014  *
114015  * Field Enumeration Values:
114016  *
114017  * Enum | Value | Description
114018  * :---------------------------------------|:------|:--------------------
114019  * ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
114020  * ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
114021  *
114022  * Field Access Macros:
114023  *
114024  */
114025 /*
114026  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTPKTERR
114027  *
114028  * No OUT Packet Error
114029  */
114030 #define ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_INACT 0x0
114031 /*
114032  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTPKTERR
114033  *
114034  * OUT Packet Error
114035  */
114036 #define ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_ACT 0x1
114037 
114038 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */
114039 #define ALT_USB_DEV_DOEPINT4_OUTPKTERR_LSB 8
114040 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */
114041 #define ALT_USB_DEV_DOEPINT4_OUTPKTERR_MSB 8
114042 /* The width in bits of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */
114043 #define ALT_USB_DEV_DOEPINT4_OUTPKTERR_WIDTH 1
114044 /* The mask used to set the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field value. */
114045 #define ALT_USB_DEV_DOEPINT4_OUTPKTERR_SET_MSK 0x00000100
114046 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field value. */
114047 #define ALT_USB_DEV_DOEPINT4_OUTPKTERR_CLR_MSK 0xfffffeff
114048 /* The reset value of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */
114049 #define ALT_USB_DEV_DOEPINT4_OUTPKTERR_RESET 0x0
114050 /* Extracts the ALT_USB_DEV_DOEPINT4_OUTPKTERR field value from a register. */
114051 #define ALT_USB_DEV_DOEPINT4_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
114052 /* Produces a ALT_USB_DEV_DOEPINT4_OUTPKTERR register field value suitable for setting the register. */
114053 #define ALT_USB_DEV_DOEPINT4_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
114054 
114055 /*
114056  * Field : bnaintr
114057  *
114058  * BNA (Buffer Not Available) Interrupt (BNAIntr)
114059  *
114060  * This bit is valid only when Scatter/Gather DMA mode is enabled.
114061  *
114062  * The core generates this interrupt when the descriptor accessed
114063  *
114064  * is not ready For the Core to process, such as Host busy or DMA
114065  *
114066  * done
114067  *
114068  * Field Enumeration Values:
114069  *
114070  * Enum | Value | Description
114071  * :-------------------------------------|:------|:--------------
114072  * ALT_USB_DEV_DOEPINT4_BNAINTR_E_INACT | 0x0 | No interrupt
114073  * ALT_USB_DEV_DOEPINT4_BNAINTR_E_ACT | 0x1 | BNA interrupt
114074  *
114075  * Field Access Macros:
114076  *
114077  */
114078 /*
114079  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BNAINTR
114080  *
114081  * No interrupt
114082  */
114083 #define ALT_USB_DEV_DOEPINT4_BNAINTR_E_INACT 0x0
114084 /*
114085  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BNAINTR
114086  *
114087  * BNA interrupt
114088  */
114089 #define ALT_USB_DEV_DOEPINT4_BNAINTR_E_ACT 0x1
114090 
114091 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */
114092 #define ALT_USB_DEV_DOEPINT4_BNAINTR_LSB 9
114093 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */
114094 #define ALT_USB_DEV_DOEPINT4_BNAINTR_MSB 9
114095 /* The width in bits of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */
114096 #define ALT_USB_DEV_DOEPINT4_BNAINTR_WIDTH 1
114097 /* The mask used to set the ALT_USB_DEV_DOEPINT4_BNAINTR register field value. */
114098 #define ALT_USB_DEV_DOEPINT4_BNAINTR_SET_MSK 0x00000200
114099 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_BNAINTR register field value. */
114100 #define ALT_USB_DEV_DOEPINT4_BNAINTR_CLR_MSK 0xfffffdff
114101 /* The reset value of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */
114102 #define ALT_USB_DEV_DOEPINT4_BNAINTR_RESET 0x0
114103 /* Extracts the ALT_USB_DEV_DOEPINT4_BNAINTR field value from a register. */
114104 #define ALT_USB_DEV_DOEPINT4_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
114105 /* Produces a ALT_USB_DEV_DOEPINT4_BNAINTR register field value suitable for setting the register. */
114106 #define ALT_USB_DEV_DOEPINT4_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
114107 
114108 /*
114109  * Field : pktdrpsts
114110  *
114111  * Packet Drop Status (PktDrpSts)
114112  *
114113  * This bit indicates to the application that an ISOC OUT packet has been dropped.
114114  * This
114115  *
114116  * bit does not have an associated mask bit and does not generate an interrupt.
114117  *
114118  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
114119  * transfer
114120  *
114121  * interrupt feature is selected.
114122  *
114123  * Field Enumeration Values:
114124  *
114125  * Enum | Value | Description
114126  * :---------------------------------------|:------|:-----------------------------
114127  * ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_INACT | 0x0 | No interrupt
114128  * ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
114129  *
114130  * Field Access Macros:
114131  *
114132  */
114133 /*
114134  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_PKTDRPSTS
114135  *
114136  * No interrupt
114137  */
114138 #define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_INACT 0x0
114139 /*
114140  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_PKTDRPSTS
114141  *
114142  * Packet Drop Status interrupt
114143  */
114144 #define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_ACT 0x1
114145 
114146 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */
114147 #define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_LSB 11
114148 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */
114149 #define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_MSB 11
114150 /* The width in bits of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */
114151 #define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_WIDTH 1
114152 /* The mask used to set the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field value. */
114153 #define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_SET_MSK 0x00000800
114154 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field value. */
114155 #define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_CLR_MSK 0xfffff7ff
114156 /* The reset value of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */
114157 #define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_RESET 0x0
114158 /* Extracts the ALT_USB_DEV_DOEPINT4_PKTDRPSTS field value from a register. */
114159 #define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
114160 /* Produces a ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field value suitable for setting the register. */
114161 #define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
114162 
114163 /*
114164  * Field : bbleerr
114165  *
114166  * NAK Interrupt (BbleErr)
114167  *
114168  * The core generates this interrupt when babble is received for the endpoint.
114169  *
114170  * Field Enumeration Values:
114171  *
114172  * Enum | Value | Description
114173  * :-------------------------------------|:------|:------------------
114174  * ALT_USB_DEV_DOEPINT4_BBLEERR_E_INACT | 0x0 | No interrupt
114175  * ALT_USB_DEV_DOEPINT4_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
114176  *
114177  * Field Access Macros:
114178  *
114179  */
114180 /*
114181  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BBLEERR
114182  *
114183  * No interrupt
114184  */
114185 #define ALT_USB_DEV_DOEPINT4_BBLEERR_E_INACT 0x0
114186 /*
114187  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_BBLEERR
114188  *
114189  * BbleErr interrupt
114190  */
114191 #define ALT_USB_DEV_DOEPINT4_BBLEERR_E_ACT 0x1
114192 
114193 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */
114194 #define ALT_USB_DEV_DOEPINT4_BBLEERR_LSB 12
114195 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */
114196 #define ALT_USB_DEV_DOEPINT4_BBLEERR_MSB 12
114197 /* The width in bits of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */
114198 #define ALT_USB_DEV_DOEPINT4_BBLEERR_WIDTH 1
114199 /* The mask used to set the ALT_USB_DEV_DOEPINT4_BBLEERR register field value. */
114200 #define ALT_USB_DEV_DOEPINT4_BBLEERR_SET_MSK 0x00001000
114201 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_BBLEERR register field value. */
114202 #define ALT_USB_DEV_DOEPINT4_BBLEERR_CLR_MSK 0xffffefff
114203 /* The reset value of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */
114204 #define ALT_USB_DEV_DOEPINT4_BBLEERR_RESET 0x0
114205 /* Extracts the ALT_USB_DEV_DOEPINT4_BBLEERR field value from a register. */
114206 #define ALT_USB_DEV_DOEPINT4_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
114207 /* Produces a ALT_USB_DEV_DOEPINT4_BBLEERR register field value suitable for setting the register. */
114208 #define ALT_USB_DEV_DOEPINT4_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
114209 
114210 /*
114211  * Field : nakintrpt
114212  *
114213  * NAK Interrupt (NAKInterrupt)
114214  *
114215  * The core generates this interrupt when a NAK is transmitted or received by the
114216  * device.
114217  *
114218  * In case of isochronous IN endpoints the interrupt gets generated when a zero
114219  * length
114220  *
114221  * packet is transmitted due to un-availability of data in the TXFifo.
114222  *
114223  * Field Enumeration Values:
114224  *
114225  * Enum | Value | Description
114226  * :---------------------------------------|:------|:--------------
114227  * ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_INACT | 0x0 | No interrupt
114228  * ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
114229  *
114230  * Field Access Macros:
114231  *
114232  */
114233 /*
114234  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_NAKINTRPT
114235  *
114236  * No interrupt
114237  */
114238 #define ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_INACT 0x0
114239 /*
114240  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_NAKINTRPT
114241  *
114242  * NAK Interrupt
114243  */
114244 #define ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_ACT 0x1
114245 
114246 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */
114247 #define ALT_USB_DEV_DOEPINT4_NAKINTRPT_LSB 13
114248 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */
114249 #define ALT_USB_DEV_DOEPINT4_NAKINTRPT_MSB 13
114250 /* The width in bits of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */
114251 #define ALT_USB_DEV_DOEPINT4_NAKINTRPT_WIDTH 1
114252 /* The mask used to set the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field value. */
114253 #define ALT_USB_DEV_DOEPINT4_NAKINTRPT_SET_MSK 0x00002000
114254 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field value. */
114255 #define ALT_USB_DEV_DOEPINT4_NAKINTRPT_CLR_MSK 0xffffdfff
114256 /* The reset value of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */
114257 #define ALT_USB_DEV_DOEPINT4_NAKINTRPT_RESET 0x0
114258 /* Extracts the ALT_USB_DEV_DOEPINT4_NAKINTRPT field value from a register. */
114259 #define ALT_USB_DEV_DOEPINT4_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
114260 /* Produces a ALT_USB_DEV_DOEPINT4_NAKINTRPT register field value suitable for setting the register. */
114261 #define ALT_USB_DEV_DOEPINT4_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
114262 
114263 /*
114264  * Field : nyetintrpt
114265  *
114266  * NYET Interrupt (NYETIntrpt)
114267  *
114268  * The core generates this interrupt when a NYET response is transmitted for a non
114269  * isochronous OUT endpoint.
114270  *
114271  * Field Enumeration Values:
114272  *
114273  * Enum | Value | Description
114274  * :----------------------------------------|:------|:---------------
114275  * ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_INACT | 0x0 | No interrupt
114276  * ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
114277  *
114278  * Field Access Macros:
114279  *
114280  */
114281 /*
114282  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_NYETINTRPT
114283  *
114284  * No interrupt
114285  */
114286 #define ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_INACT 0x0
114287 /*
114288  * Enumerated value for register field ALT_USB_DEV_DOEPINT4_NYETINTRPT
114289  *
114290  * NYET Interrupt
114291  */
114292 #define ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_ACT 0x1
114293 
114294 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */
114295 #define ALT_USB_DEV_DOEPINT4_NYETINTRPT_LSB 14
114296 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */
114297 #define ALT_USB_DEV_DOEPINT4_NYETINTRPT_MSB 14
114298 /* The width in bits of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */
114299 #define ALT_USB_DEV_DOEPINT4_NYETINTRPT_WIDTH 1
114300 /* The mask used to set the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field value. */
114301 #define ALT_USB_DEV_DOEPINT4_NYETINTRPT_SET_MSK 0x00004000
114302 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field value. */
114303 #define ALT_USB_DEV_DOEPINT4_NYETINTRPT_CLR_MSK 0xffffbfff
114304 /* The reset value of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */
114305 #define ALT_USB_DEV_DOEPINT4_NYETINTRPT_RESET 0x0
114306 /* Extracts the ALT_USB_DEV_DOEPINT4_NYETINTRPT field value from a register. */
114307 #define ALT_USB_DEV_DOEPINT4_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
114308 /* Produces a ALT_USB_DEV_DOEPINT4_NYETINTRPT register field value suitable for setting the register. */
114309 #define ALT_USB_DEV_DOEPINT4_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
114310 
114311 /*
114312  * Field : stuppktrcvd
114313  *
114314  * Setup Packet Received
114315  *
114316  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
114317  *
114318  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
114319  *
114320  * setup data. There is only one Setup packet per buffer. On receiving a
114321  *
114322  * Setup packet, the DWC_otg core closes the buffer and disables the
114323  *
114324  * corresponding endpoint. The application has to re-enable the endpoint to
114325  *
114326  * receive any OUT data for the Control Transfer and reprogram the buffer
114327  *
114328  * start address.
114329  *
114330  * Note: Because of the above behavior, the DWC_otg core can receive any
114331  *
114332  * number of back to back setup packets and one buffer for every setup
114333  *
114334  * packet is used.
114335  *
114336  * 1'b0: No Setup packet received
114337  *
114338  * 1'b1: Setup packet received
114339  *
114340  * Reset: 1'b0
114341  *
114342  * Field Access Macros:
114343  *
114344  */
114345 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field. */
114346 #define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_LSB 15
114347 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field. */
114348 #define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_MSB 15
114349 /* The width in bits of the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field. */
114350 #define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_WIDTH 1
114351 /* The mask used to set the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field value. */
114352 #define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_SET_MSK 0x00008000
114353 /* The mask used to clear the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field value. */
114354 #define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_CLR_MSK 0xffff7fff
114355 /* The reset value of the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field. */
114356 #define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_RESET 0x0
114357 /* Extracts the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD field value from a register. */
114358 #define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
114359 /* Produces a ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field value suitable for setting the register. */
114360 #define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
114361 
114362 #ifndef __ASSEMBLY__
114363 /*
114364  * WARNING: The C register and register group struct declarations are provided for
114365  * convenience and illustrative purposes. They should, however, be used with
114366  * caution as the C language standard provides no guarantees about the alignment or
114367  * atomicity of device memory accesses. The recommended practice for writing
114368  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
114369  * alt_write_word() functions.
114370  *
114371  * The struct declaration for register ALT_USB_DEV_DOEPINT4.
114372  */
114373 struct ALT_USB_DEV_DOEPINT4_s
114374 {
114375  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT4_XFERCOMPL */
114376  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT4_EPDISBLD */
114377  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT4_AHBERR */
114378  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT4_SETUP */
114379  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS */
114380  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT4_STSPHSERCVD */
114381  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP */
114382  uint32_t : 1; /* *UNDEFINED* */
114383  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT4_OUTPKTERR */
114384  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT4_BNAINTR */
114385  uint32_t : 1; /* *UNDEFINED* */
114386  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT4_PKTDRPSTS */
114387  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT4_BBLEERR */
114388  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT4_NAKINTRPT */
114389  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT4_NYETINTRPT */
114390  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT4_STUPPKTRCVD */
114391  uint32_t : 16; /* *UNDEFINED* */
114392 };
114393 
114394 /* The typedef declaration for register ALT_USB_DEV_DOEPINT4. */
114395 typedef volatile struct ALT_USB_DEV_DOEPINT4_s ALT_USB_DEV_DOEPINT4_t;
114396 #endif /* __ASSEMBLY__ */
114397 
114398 /* The reset value of the ALT_USB_DEV_DOEPINT4 register. */
114399 #define ALT_USB_DEV_DOEPINT4_RESET 0x00000000
114400 /* The byte offset of the ALT_USB_DEV_DOEPINT4 register from the beginning of the component. */
114401 #define ALT_USB_DEV_DOEPINT4_OFST 0x388
114402 /* The address of the ALT_USB_DEV_DOEPINT4 register. */
114403 #define ALT_USB_DEV_DOEPINT4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT4_OFST))
114404 
114405 /*
114406  * Register : doeptsiz4
114407  *
114408  * Device OUT Endpoint 4 Transfer Size Register
114409  *
114410  * Register Layout
114411  *
114412  * Bits | Access | Reset | Description
114413  * :--------|:-------|:------|:-------------------------------
114414  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ4_XFERSIZE
114415  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ4_PKTCNT
114416  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ4_RXDPID
114417  * [31] | ??? | 0x0 | *UNDEFINED*
114418  *
114419  */
114420 /*
114421  * Field : xfersize
114422  *
114423  * Transfer Size (XferSize)
114424  *
114425  * Indicates the transfer size in bytes For endpoint 0. The core
114426  *
114427  * interrupts the application only after it has exhausted the transfer
114428  *
114429  * size amount of data. The transfer size can be Set to the
114430  *
114431  * maximum packet size of the endpoint, to be interrupted at the
114432  *
114433  * end of each packet.
114434  *
114435  * The core decrements this field every time a packet is read from
114436  *
114437  * the RxFIFO and written to the external memory.
114438  *
114439  * Field Access Macros:
114440  *
114441  */
114442 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */
114443 #define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_LSB 0
114444 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */
114445 #define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_MSB 18
114446 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */
114447 #define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_WIDTH 19
114448 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field value. */
114449 #define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_SET_MSK 0x0007ffff
114450 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field value. */
114451 #define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_CLR_MSK 0xfff80000
114452 /* The reset value of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */
114453 #define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_RESET 0x0
114454 /* Extracts the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE field value from a register. */
114455 #define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
114456 /* Produces a ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field value suitable for setting the register. */
114457 #define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
114458 
114459 /*
114460  * Field : pktcnt
114461  *
114462  * Packet Count (PktCnt)
114463  *
114464  * This field is decremented to zero after a packet is written into the
114465  *
114466  * RxFIFO.
114467  *
114468  * Field Access Macros:
114469  *
114470  */
114471 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */
114472 #define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_LSB 19
114473 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */
114474 #define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_MSB 28
114475 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */
114476 #define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_WIDTH 10
114477 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field value. */
114478 #define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_SET_MSK 0x1ff80000
114479 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field value. */
114480 #define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_CLR_MSK 0xe007ffff
114481 /* The reset value of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */
114482 #define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_RESET 0x0
114483 /* Extracts the ALT_USB_DEV_DOEPTSIZ4_PKTCNT field value from a register. */
114484 #define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
114485 /* Produces a ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field value suitable for setting the register. */
114486 #define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
114487 
114488 /*
114489  * Field : rxdpid
114490  *
114491  * Applies to isochronous OUT endpoints only.
114492  *
114493  * This is the data PID received in the last packet for this endpoint.
114494  *
114495  * 2'b00: DATA0
114496  *
114497  * 2'b01: DATA2
114498  *
114499  * 2'b10: DATA1
114500  *
114501  * 2'b11: MDATA
114502  *
114503  * SETUP Packet Count (SUPCnt)
114504  *
114505  * Applies to control OUT Endpoints only.
114506  *
114507  * This field specifies the number of back-to-back SETUP data
114508  *
114509  * packets the endpoint can receive.
114510  *
114511  * 2'b01: 1 packet
114512  *
114513  * 2'b10: 2 packets
114514  *
114515  * 2'b11: 3 packets
114516  *
114517  * Field Enumeration Values:
114518  *
114519  * Enum | Value | Description
114520  * :-----------------------------------------|:------|:-------------------
114521  * ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA0 | 0x0 | DATA0
114522  * ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
114523  * ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
114524  * ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
114525  *
114526  * Field Access Macros:
114527  *
114528  */
114529 /*
114530  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID
114531  *
114532  * DATA0
114533  */
114534 #define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA0 0x0
114535 /*
114536  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID
114537  *
114538  * DATA2 or 1 packet
114539  */
114540 #define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA2PKT1 0x1
114541 /*
114542  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID
114543  *
114544  * DATA1 or 2 packets
114545  */
114546 #define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA1PKT2 0x2
114547 /*
114548  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID
114549  *
114550  * MDATA or 3 packets
114551  */
114552 #define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_MDATAPKT3 0x3
114553 
114554 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */
114555 #define ALT_USB_DEV_DOEPTSIZ4_RXDPID_LSB 29
114556 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */
114557 #define ALT_USB_DEV_DOEPTSIZ4_RXDPID_MSB 30
114558 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */
114559 #define ALT_USB_DEV_DOEPTSIZ4_RXDPID_WIDTH 2
114560 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field value. */
114561 #define ALT_USB_DEV_DOEPTSIZ4_RXDPID_SET_MSK 0x60000000
114562 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field value. */
114563 #define ALT_USB_DEV_DOEPTSIZ4_RXDPID_CLR_MSK 0x9fffffff
114564 /* The reset value of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */
114565 #define ALT_USB_DEV_DOEPTSIZ4_RXDPID_RESET 0x0
114566 /* Extracts the ALT_USB_DEV_DOEPTSIZ4_RXDPID field value from a register. */
114567 #define ALT_USB_DEV_DOEPTSIZ4_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
114568 /* Produces a ALT_USB_DEV_DOEPTSIZ4_RXDPID register field value suitable for setting the register. */
114569 #define ALT_USB_DEV_DOEPTSIZ4_RXDPID_SET(value) (((value) << 29) & 0x60000000)
114570 
114571 #ifndef __ASSEMBLY__
114572 /*
114573  * WARNING: The C register and register group struct declarations are provided for
114574  * convenience and illustrative purposes. They should, however, be used with
114575  * caution as the C language standard provides no guarantees about the alignment or
114576  * atomicity of device memory accesses. The recommended practice for writing
114577  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
114578  * alt_write_word() functions.
114579  *
114580  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ4.
114581  */
114582 struct ALT_USB_DEV_DOEPTSIZ4_s
114583 {
114584  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ4_XFERSIZE */
114585  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ4_PKTCNT */
114586  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ4_RXDPID */
114587  uint32_t : 1; /* *UNDEFINED* */
114588 };
114589 
114590 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ4. */
114591 typedef volatile struct ALT_USB_DEV_DOEPTSIZ4_s ALT_USB_DEV_DOEPTSIZ4_t;
114592 #endif /* __ASSEMBLY__ */
114593 
114594 /* The reset value of the ALT_USB_DEV_DOEPTSIZ4 register. */
114595 #define ALT_USB_DEV_DOEPTSIZ4_RESET 0x00000000
114596 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ4 register from the beginning of the component. */
114597 #define ALT_USB_DEV_DOEPTSIZ4_OFST 0x390
114598 /* The address of the ALT_USB_DEV_DOEPTSIZ4 register. */
114599 #define ALT_USB_DEV_DOEPTSIZ4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ4_OFST))
114600 
114601 /*
114602  * Register : doepdma4
114603  *
114604  * Device OUT Endpoint 4 DMA Address Register
114605  *
114606  * Register Layout
114607  *
114608  * Bits | Access | Reset | Description
114609  * :-------|:-------|:--------|:------------------------------
114610  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA4_DOEPDMA4
114611  *
114612  */
114613 /*
114614  * Field : doepdma4
114615  *
114616  * Holds the start address of the external memory for storing or fetching endpoint
114617  *
114618  * data.
114619  *
114620  * Note: For control endpoints, this field stores control OUT data packets as well
114621  * as
114622  *
114623  * SETUP transaction data packets. When more than three SETUP packets are
114624  *
114625  * received back-to-back, the SETUP data packet in the memory is overwritten.
114626  *
114627  * This register is incremented on every AHB transaction. The application can give
114628  *
114629  * only a DWORD-aligned address.
114630  *
114631  * When Scatter/Gather DMA mode is not enabled, the application programs the
114632  *
114633  * start address value in this field.
114634  *
114635  * When Scatter/Gather DMA mode is enabled, this field indicates the base
114636  *
114637  * pointer for the descriptor list.
114638  *
114639  * Field Access Macros:
114640  *
114641  */
114642 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field. */
114643 #define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_LSB 0
114644 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field. */
114645 #define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_MSB 31
114646 /* The width in bits of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field. */
114647 #define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_WIDTH 32
114648 /* The mask used to set the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field value. */
114649 #define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_SET_MSK 0xffffffff
114650 /* The mask used to clear the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field value. */
114651 #define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_CLR_MSK 0x00000000
114652 /* The reset value of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field is UNKNOWN. */
114653 #define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_RESET 0x0
114654 /* Extracts the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 field value from a register. */
114655 #define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_GET(value) (((value) & 0xffffffff) >> 0)
114656 /* Produces a ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field value suitable for setting the register. */
114657 #define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_SET(value) (((value) << 0) & 0xffffffff)
114658 
114659 #ifndef __ASSEMBLY__
114660 /*
114661  * WARNING: The C register and register group struct declarations are provided for
114662  * convenience and illustrative purposes. They should, however, be used with
114663  * caution as the C language standard provides no guarantees about the alignment or
114664  * atomicity of device memory accesses. The recommended practice for writing
114665  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
114666  * alt_write_word() functions.
114667  *
114668  * The struct declaration for register ALT_USB_DEV_DOEPDMA4.
114669  */
114670 struct ALT_USB_DEV_DOEPDMA4_s
114671 {
114672  uint32_t doepdma4 : 32; /* ALT_USB_DEV_DOEPDMA4_DOEPDMA4 */
114673 };
114674 
114675 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA4. */
114676 typedef volatile struct ALT_USB_DEV_DOEPDMA4_s ALT_USB_DEV_DOEPDMA4_t;
114677 #endif /* __ASSEMBLY__ */
114678 
114679 /* The reset value of the ALT_USB_DEV_DOEPDMA4 register. */
114680 #define ALT_USB_DEV_DOEPDMA4_RESET 0x00000000
114681 /* The byte offset of the ALT_USB_DEV_DOEPDMA4 register from the beginning of the component. */
114682 #define ALT_USB_DEV_DOEPDMA4_OFST 0x394
114683 /* The address of the ALT_USB_DEV_DOEPDMA4 register. */
114684 #define ALT_USB_DEV_DOEPDMA4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA4_OFST))
114685 
114686 /*
114687  * Register : doepdmab4
114688  *
114689  * Device OUT Endpoint 4 Buffer Address Register
114690  *
114691  * Register Layout
114692  *
114693  * Bits | Access | Reset | Description
114694  * :-------|:-------|:--------|:--------------------------------
114695  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4
114696  *
114697  */
114698 /*
114699  * Field : doepdmab4
114700  *
114701  * Holds the current buffer address.This register is updated as and when the data
114702  *
114703  * transfer for the corresponding end point is in progress.
114704  *
114705  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
114706  * is
114707  *
114708  * reserved.
114709  *
114710  * Field Access Macros:
114711  *
114712  */
114713 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field. */
114714 #define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_LSB 0
114715 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field. */
114716 #define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_MSB 31
114717 /* The width in bits of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field. */
114718 #define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_WIDTH 32
114719 /* The mask used to set the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field value. */
114720 #define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_SET_MSK 0xffffffff
114721 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field value. */
114722 #define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_CLR_MSK 0x00000000
114723 /* The reset value of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field is UNKNOWN. */
114724 #define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_RESET 0x0
114725 /* Extracts the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 field value from a register. */
114726 #define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_GET(value) (((value) & 0xffffffff) >> 0)
114727 /* Produces a ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field value suitable for setting the register. */
114728 #define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_SET(value) (((value) << 0) & 0xffffffff)
114729 
114730 #ifndef __ASSEMBLY__
114731 /*
114732  * WARNING: The C register and register group struct declarations are provided for
114733  * convenience and illustrative purposes. They should, however, be used with
114734  * caution as the C language standard provides no guarantees about the alignment or
114735  * atomicity of device memory accesses. The recommended practice for writing
114736  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
114737  * alt_write_word() functions.
114738  *
114739  * The struct declaration for register ALT_USB_DEV_DOEPDMAB4.
114740  */
114741 struct ALT_USB_DEV_DOEPDMAB4_s
114742 {
114743  const uint32_t doepdmab4 : 32; /* ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 */
114744 };
114745 
114746 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB4. */
114747 typedef volatile struct ALT_USB_DEV_DOEPDMAB4_s ALT_USB_DEV_DOEPDMAB4_t;
114748 #endif /* __ASSEMBLY__ */
114749 
114750 /* The reset value of the ALT_USB_DEV_DOEPDMAB4 register. */
114751 #define ALT_USB_DEV_DOEPDMAB4_RESET 0x00000000
114752 /* The byte offset of the ALT_USB_DEV_DOEPDMAB4 register from the beginning of the component. */
114753 #define ALT_USB_DEV_DOEPDMAB4_OFST 0x39c
114754 /* The address of the ALT_USB_DEV_DOEPDMAB4 register. */
114755 #define ALT_USB_DEV_DOEPDMAB4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB4_OFST))
114756 
114757 /*
114758  * Register : doepctl5
114759  *
114760  * Device Control OUT Endpoint 5 Control Register
114761  *
114762  * Register Layout
114763  *
114764  * Bits | Access | Reset | Description
114765  * :--------|:---------|:------|:------------------------------
114766  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL5_MPS
114767  * [14:11] | ??? | 0x0 | *UNDEFINED*
114768  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL5_USBACTEP
114769  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL5_DPID
114770  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL5_NAKSTS
114771  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL5_EPTYPE
114772  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL5_SNP
114773  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL5_STALL
114774  * [25:22] | ??? | 0x0 | *UNDEFINED*
114775  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL5_CNAK
114776  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL5_SNAK
114777  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL5_SETD0PID
114778  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL5_SETD1PID
114779  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL5_EPDIS
114780  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL5_EPENA
114781  *
114782  */
114783 /*
114784  * Field : mps
114785  *
114786  * Maximum Packet Size (MPS)
114787  *
114788  * The application must program this field with the maximum packet size for the
114789  * current
114790  *
114791  * logical endpoint. This value is in bytes.
114792  *
114793  * Field Access Macros:
114794  *
114795  */
114796 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_MPS register field. */
114797 #define ALT_USB_DEV_DOEPCTL5_MPS_LSB 0
114798 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_MPS register field. */
114799 #define ALT_USB_DEV_DOEPCTL5_MPS_MSB 10
114800 /* The width in bits of the ALT_USB_DEV_DOEPCTL5_MPS register field. */
114801 #define ALT_USB_DEV_DOEPCTL5_MPS_WIDTH 11
114802 /* The mask used to set the ALT_USB_DEV_DOEPCTL5_MPS register field value. */
114803 #define ALT_USB_DEV_DOEPCTL5_MPS_SET_MSK 0x000007ff
114804 /* The mask used to clear the ALT_USB_DEV_DOEPCTL5_MPS register field value. */
114805 #define ALT_USB_DEV_DOEPCTL5_MPS_CLR_MSK 0xfffff800
114806 /* The reset value of the ALT_USB_DEV_DOEPCTL5_MPS register field. */
114807 #define ALT_USB_DEV_DOEPCTL5_MPS_RESET 0x0
114808 /* Extracts the ALT_USB_DEV_DOEPCTL5_MPS field value from a register. */
114809 #define ALT_USB_DEV_DOEPCTL5_MPS_GET(value) (((value) & 0x000007ff) >> 0)
114810 /* Produces a ALT_USB_DEV_DOEPCTL5_MPS register field value suitable for setting the register. */
114811 #define ALT_USB_DEV_DOEPCTL5_MPS_SET(value) (((value) << 0) & 0x000007ff)
114812 
114813 /*
114814  * Field : usbactep
114815  *
114816  * USB Active Endpoint (USBActEP)
114817  *
114818  * Indicates whether this endpoint is active in the current configuration and
114819  * interface. The
114820  *
114821  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
114822  * reset. After
114823  *
114824  * receiving the SetConfiguration and SetInterface commands, the application must
114825  *
114826  * program endpoint registers accordingly and set this bit.
114827  *
114828  * Field Enumeration Values:
114829  *
114830  * Enum | Value | Description
114831  * :-------------------------------------|:------|:--------------------
114832  * ALT_USB_DEV_DOEPCTL5_USBACTEP_E_DISD | 0x0 | Not Active
114833  * ALT_USB_DEV_DOEPCTL5_USBACTEP_E_END | 0x1 | USB Active Endpoint
114834  *
114835  * Field Access Macros:
114836  *
114837  */
114838 /*
114839  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_USBACTEP
114840  *
114841  * Not Active
114842  */
114843 #define ALT_USB_DEV_DOEPCTL5_USBACTEP_E_DISD 0x0
114844 /*
114845  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_USBACTEP
114846  *
114847  * USB Active Endpoint
114848  */
114849 #define ALT_USB_DEV_DOEPCTL5_USBACTEP_E_END 0x1
114850 
114851 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */
114852 #define ALT_USB_DEV_DOEPCTL5_USBACTEP_LSB 15
114853 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */
114854 #define ALT_USB_DEV_DOEPCTL5_USBACTEP_MSB 15
114855 /* The width in bits of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */
114856 #define ALT_USB_DEV_DOEPCTL5_USBACTEP_WIDTH 1
114857 /* The mask used to set the ALT_USB_DEV_DOEPCTL5_USBACTEP register field value. */
114858 #define ALT_USB_DEV_DOEPCTL5_USBACTEP_SET_MSK 0x00008000
114859 /* The mask used to clear the ALT_USB_DEV_DOEPCTL5_USBACTEP register field value. */
114860 #define ALT_USB_DEV_DOEPCTL5_USBACTEP_CLR_MSK 0xffff7fff
114861 /* The reset value of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */
114862 #define ALT_USB_DEV_DOEPCTL5_USBACTEP_RESET 0x0
114863 /* Extracts the ALT_USB_DEV_DOEPCTL5_USBACTEP field value from a register. */
114864 #define ALT_USB_DEV_DOEPCTL5_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
114865 /* Produces a ALT_USB_DEV_DOEPCTL5_USBACTEP register field value suitable for setting the register. */
114866 #define ALT_USB_DEV_DOEPCTL5_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
114867 
114868 /*
114869  * Field : dpid
114870  *
114871  * Endpoint Data PID (DPID)
114872  *
114873  * Applies to interrupt/bulk IN and OUT endpoints only.
114874  *
114875  * Contains the PID of the packet to be received or transmitted on this endpoint.
114876  * The
114877  *
114878  * application must program the PID of the first packet to be received or
114879  * transmitted on
114880  *
114881  * this endpoint, after the endpoint is activated. The applications use the
114882  * SetD1PID and
114883  *
114884  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
114885  *
114886  * 1'b0: DATA0
114887  *
114888  * 1'b1: DATA1
114889  *
114890  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
114891  *
114892  * DMA mode.
114893  *
114894  * 1'b0 RO
114895  *
114896  * Even/Odd (Micro)Frame (EO_FrNum)
114897  *
114898  * In non-Scatter/Gather DMA mode:
114899  *
114900  * Applies to isochronous IN and OUT endpoints only.
114901  *
114902  * Indicates the (micro)frame number in which the core transmits/receives
114903  * isochronous
114904  *
114905  * data for this endpoint. The application must program the even/odd (micro) frame
114906  *
114907  * number in which it intends to transmit/receive isochronous data for this
114908  * endpoint using
114909  *
114910  * the SetEvnFr and SetOddFr fields in this register.
114911  *
114912  * 1'b0: Even (micro)frame
114913  *
114914  * 1'b1: Odd (micro)frame
114915  *
114916  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
114917  * number
114918  *
114919  * in which to send data is provided in the transmit descriptor structure. The
114920  * frame in
114921  *
114922  * which data is received is updated in receive descriptor structure.
114923  *
114924  * Field Enumeration Values:
114925  *
114926  * Enum | Value | Description
114927  * :----------------------------------|:------|:-----------------------------
114928  * ALT_USB_DEV_DOEPCTL5_DPID_E_INACT | 0x0 | Endpoint Data PID not active
114929  * ALT_USB_DEV_DOEPCTL5_DPID_E_ACT | 0x1 | Endpoint Data PID active
114930  *
114931  * Field Access Macros:
114932  *
114933  */
114934 /*
114935  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_DPID
114936  *
114937  * Endpoint Data PID not active
114938  */
114939 #define ALT_USB_DEV_DOEPCTL5_DPID_E_INACT 0x0
114940 /*
114941  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_DPID
114942  *
114943  * Endpoint Data PID active
114944  */
114945 #define ALT_USB_DEV_DOEPCTL5_DPID_E_ACT 0x1
114946 
114947 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_DPID register field. */
114948 #define ALT_USB_DEV_DOEPCTL5_DPID_LSB 16
114949 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_DPID register field. */
114950 #define ALT_USB_DEV_DOEPCTL5_DPID_MSB 16
114951 /* The width in bits of the ALT_USB_DEV_DOEPCTL5_DPID register field. */
114952 #define ALT_USB_DEV_DOEPCTL5_DPID_WIDTH 1
114953 /* The mask used to set the ALT_USB_DEV_DOEPCTL5_DPID register field value. */
114954 #define ALT_USB_DEV_DOEPCTL5_DPID_SET_MSK 0x00010000
114955 /* The mask used to clear the ALT_USB_DEV_DOEPCTL5_DPID register field value. */
114956 #define ALT_USB_DEV_DOEPCTL5_DPID_CLR_MSK 0xfffeffff
114957 /* The reset value of the ALT_USB_DEV_DOEPCTL5_DPID register field. */
114958 #define ALT_USB_DEV_DOEPCTL5_DPID_RESET 0x0
114959 /* Extracts the ALT_USB_DEV_DOEPCTL5_DPID field value from a register. */
114960 #define ALT_USB_DEV_DOEPCTL5_DPID_GET(value) (((value) & 0x00010000) >> 16)
114961 /* Produces a ALT_USB_DEV_DOEPCTL5_DPID register field value suitable for setting the register. */
114962 #define ALT_USB_DEV_DOEPCTL5_DPID_SET(value) (((value) << 16) & 0x00010000)
114963 
114964 /*
114965  * Field : naksts
114966  *
114967  * NAK Status (NAKSts)
114968  *
114969  * Indicates the following:
114970  *
114971  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
114972  *
114973  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
114974  *
114975  * When either the application or the core sets this bit:
114976  *
114977  * The core stops receiving any data on an OUT endpoint, even if there is space in
114978  *
114979  * the RxFIFO to accommodate the incoming packet.
114980  *
114981  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
114982  *
114983  * endpoint, even if there data is available in the TxFIFO.
114984  *
114985  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
114986  *
114987  * if there data is available in the TxFIFO.
114988  *
114989  * Irrespective of this bit's setting, the core always responds to SETUP data
114990  * packets with
114991  *
114992  * an ACK handshake.
114993  *
114994  * Field Enumeration Values:
114995  *
114996  * Enum | Value | Description
114997  * :-------------------------------------|:------|:------------------------------------------------
114998  * ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
114999  * : | | based on the FIFO status
115000  * ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
115001  * : | | endpoint
115002  *
115003  * Field Access Macros:
115004  *
115005  */
115006 /*
115007  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_NAKSTS
115008  *
115009  * The core is transmitting non-NAK handshakes based on the FIFO status
115010  */
115011 #define ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NONNAK 0x0
115012 /*
115013  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_NAKSTS
115014  *
115015  * The core is transmitting NAK handshakes on this endpoint
115016  */
115017 #define ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NAK 0x1
115018 
115019 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */
115020 #define ALT_USB_DEV_DOEPCTL5_NAKSTS_LSB 17
115021 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */
115022 #define ALT_USB_DEV_DOEPCTL5_NAKSTS_MSB 17
115023 /* The width in bits of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */
115024 #define ALT_USB_DEV_DOEPCTL5_NAKSTS_WIDTH 1
115025 /* The mask used to set the ALT_USB_DEV_DOEPCTL5_NAKSTS register field value. */
115026 #define ALT_USB_DEV_DOEPCTL5_NAKSTS_SET_MSK 0x00020000
115027 /* The mask used to clear the ALT_USB_DEV_DOEPCTL5_NAKSTS register field value. */
115028 #define ALT_USB_DEV_DOEPCTL5_NAKSTS_CLR_MSK 0xfffdffff
115029 /* The reset value of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */
115030 #define ALT_USB_DEV_DOEPCTL5_NAKSTS_RESET 0x0
115031 /* Extracts the ALT_USB_DEV_DOEPCTL5_NAKSTS field value from a register. */
115032 #define ALT_USB_DEV_DOEPCTL5_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
115033 /* Produces a ALT_USB_DEV_DOEPCTL5_NAKSTS register field value suitable for setting the register. */
115034 #define ALT_USB_DEV_DOEPCTL5_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
115035 
115036 /*
115037  * Field : eptype
115038  *
115039  * Endpoint Type (EPType)
115040  *
115041  * This is the transfer type supported by this logical endpoint.
115042  *
115043  * 2'b00: Control
115044  *
115045  * 2'b01: Isochronous
115046  *
115047  * 2'b10: Bulk
115048  *
115049  * 2'b11: Interrupt
115050  *
115051  * Field Enumeration Values:
115052  *
115053  * Enum | Value | Description
115054  * :------------------------------------------|:------|:------------
115055  * ALT_USB_DEV_DOEPCTL5_EPTYPE_E_CTL | 0x0 | Control
115056  * ALT_USB_DEV_DOEPCTL5_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
115057  * ALT_USB_DEV_DOEPCTL5_EPTYPE_E_BULK | 0x2 | Bulk
115058  * ALT_USB_DEV_DOEPCTL5_EPTYPE_E_INTERRUP | 0x3 | Interrupt
115059  *
115060  * Field Access Macros:
115061  *
115062  */
115063 /*
115064  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE
115065  *
115066  * Control
115067  */
115068 #define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_CTL 0x0
115069 /*
115070  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE
115071  *
115072  * Isochronous
115073  */
115074 #define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_ISOCHRONOUS 0x1
115075 /*
115076  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE
115077  *
115078  * Bulk
115079  */
115080 #define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_BULK 0x2
115081 /*
115082  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE
115083  *
115084  * Interrupt
115085  */
115086 #define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_INTERRUP 0x3
115087 
115088 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */
115089 #define ALT_USB_DEV_DOEPCTL5_EPTYPE_LSB 18
115090 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */
115091 #define ALT_USB_DEV_DOEPCTL5_EPTYPE_MSB 19
115092 /* The width in bits of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */
115093 #define ALT_USB_DEV_DOEPCTL5_EPTYPE_WIDTH 2
115094 /* The mask used to set the ALT_USB_DEV_DOEPCTL5_EPTYPE register field value. */
115095 #define ALT_USB_DEV_DOEPCTL5_EPTYPE_SET_MSK 0x000c0000
115096 /* The mask used to clear the ALT_USB_DEV_DOEPCTL5_EPTYPE register field value. */
115097 #define ALT_USB_DEV_DOEPCTL5_EPTYPE_CLR_MSK 0xfff3ffff
115098 /* The reset value of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */
115099 #define ALT_USB_DEV_DOEPCTL5_EPTYPE_RESET 0x0
115100 /* Extracts the ALT_USB_DEV_DOEPCTL5_EPTYPE field value from a register. */
115101 #define ALT_USB_DEV_DOEPCTL5_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
115102 /* Produces a ALT_USB_DEV_DOEPCTL5_EPTYPE register field value suitable for setting the register. */
115103 #define ALT_USB_DEV_DOEPCTL5_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
115104 
115105 /*
115106  * Field : snp
115107  *
115108  * Snoop Mode (Snp)
115109  *
115110  * Applies to OUT endpoints only.
115111  *
115112  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
115113  *
115114  * check the correctness of OUT packets before transferring them to application
115115  * memory.
115116  *
115117  * Field Enumeration Values:
115118  *
115119  * Enum | Value | Description
115120  * :-------------------------------|:------|:-------------------
115121  * ALT_USB_DEV_DOEPCTL5_SNP_E_DIS | 0x0 | Disable Snoop Mode
115122  * ALT_USB_DEV_DOEPCTL5_SNP_E_EN | 0x1 | Enable Snoop Mode
115123  *
115124  * Field Access Macros:
115125  *
115126  */
115127 /*
115128  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNP
115129  *
115130  * Disable Snoop Mode
115131  */
115132 #define ALT_USB_DEV_DOEPCTL5_SNP_E_DIS 0x0
115133 /*
115134  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNP
115135  *
115136  * Enable Snoop Mode
115137  */
115138 #define ALT_USB_DEV_DOEPCTL5_SNP_E_EN 0x1
115139 
115140 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SNP register field. */
115141 #define ALT_USB_DEV_DOEPCTL5_SNP_LSB 20
115142 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SNP register field. */
115143 #define ALT_USB_DEV_DOEPCTL5_SNP_MSB 20
115144 /* The width in bits of the ALT_USB_DEV_DOEPCTL5_SNP register field. */
115145 #define ALT_USB_DEV_DOEPCTL5_SNP_WIDTH 1
115146 /* The mask used to set the ALT_USB_DEV_DOEPCTL5_SNP register field value. */
115147 #define ALT_USB_DEV_DOEPCTL5_SNP_SET_MSK 0x00100000
115148 /* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SNP register field value. */
115149 #define ALT_USB_DEV_DOEPCTL5_SNP_CLR_MSK 0xffefffff
115150 /* The reset value of the ALT_USB_DEV_DOEPCTL5_SNP register field. */
115151 #define ALT_USB_DEV_DOEPCTL5_SNP_RESET 0x0
115152 /* Extracts the ALT_USB_DEV_DOEPCTL5_SNP field value from a register. */
115153 #define ALT_USB_DEV_DOEPCTL5_SNP_GET(value) (((value) & 0x00100000) >> 20)
115154 /* Produces a ALT_USB_DEV_DOEPCTL5_SNP register field value suitable for setting the register. */
115155 #define ALT_USB_DEV_DOEPCTL5_SNP_SET(value) (((value) << 20) & 0x00100000)
115156 
115157 /*
115158  * Field : stall
115159  *
115160  * STALL Handshake (Stall)
115161  *
115162  * Applies to non-control, non-isochronous IN and OUT endpoints only.
115163  *
115164  * The application sets this bit to stall all tokens from the USB host to this
115165  * endpoint. If a
115166  *
115167  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
115168  * bit, the
115169  *
115170  * STALL bit takes priority. Only the application can clear this bit, never the
115171  * core.
115172  *
115173  * 1'b0 R_W
115174  *
115175  * Applies to control endpoints only.
115176  *
115177  * The application can only set this bit, and the core clears it, when a SETUP
115178  * token is
115179  *
115180  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
115181  * OUT
115182  *
115183  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
115184  * this bit's
115185  *
115186  * setting, the core always responds to SETUP data packets with an ACK handshake.
115187  *
115188  * Field Enumeration Values:
115189  *
115190  * Enum | Value | Description
115191  * :-----------------------------------|:------|:----------------------------
115192  * ALT_USB_DEV_DOEPCTL5_STALL_E_INACT | 0x0 | STALL All Tokens not active
115193  * ALT_USB_DEV_DOEPCTL5_STALL_E_ACT | 0x1 | STALL All Tokens active
115194  *
115195  * Field Access Macros:
115196  *
115197  */
115198 /*
115199  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_STALL
115200  *
115201  * STALL All Tokens not active
115202  */
115203 #define ALT_USB_DEV_DOEPCTL5_STALL_E_INACT 0x0
115204 /*
115205  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_STALL
115206  *
115207  * STALL All Tokens active
115208  */
115209 #define ALT_USB_DEV_DOEPCTL5_STALL_E_ACT 0x1
115210 
115211 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_STALL register field. */
115212 #define ALT_USB_DEV_DOEPCTL5_STALL_LSB 21
115213 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_STALL register field. */
115214 #define ALT_USB_DEV_DOEPCTL5_STALL_MSB 21
115215 /* The width in bits of the ALT_USB_DEV_DOEPCTL5_STALL register field. */
115216 #define ALT_USB_DEV_DOEPCTL5_STALL_WIDTH 1
115217 /* The mask used to set the ALT_USB_DEV_DOEPCTL5_STALL register field value. */
115218 #define ALT_USB_DEV_DOEPCTL5_STALL_SET_MSK 0x00200000
115219 /* The mask used to clear the ALT_USB_DEV_DOEPCTL5_STALL register field value. */
115220 #define ALT_USB_DEV_DOEPCTL5_STALL_CLR_MSK 0xffdfffff
115221 /* The reset value of the ALT_USB_DEV_DOEPCTL5_STALL register field. */
115222 #define ALT_USB_DEV_DOEPCTL5_STALL_RESET 0x0
115223 /* Extracts the ALT_USB_DEV_DOEPCTL5_STALL field value from a register. */
115224 #define ALT_USB_DEV_DOEPCTL5_STALL_GET(value) (((value) & 0x00200000) >> 21)
115225 /* Produces a ALT_USB_DEV_DOEPCTL5_STALL register field value suitable for setting the register. */
115226 #define ALT_USB_DEV_DOEPCTL5_STALL_SET(value) (((value) << 21) & 0x00200000)
115227 
115228 /*
115229  * Field : cnak
115230  *
115231  * Clear NAK (CNAK)
115232  *
115233  * A write to this bit clears the NAK bit For the endpoint.
115234  *
115235  * Field Enumeration Values:
115236  *
115237  * Enum | Value | Description
115238  * :----------------------------------|:------|:-------------
115239  * ALT_USB_DEV_DOEPCTL5_CNAK_E_INACT | 0x0 | No Clear NAK
115240  * ALT_USB_DEV_DOEPCTL5_CNAK_E_ACT | 0x1 | Clear NAK
115241  *
115242  * Field Access Macros:
115243  *
115244  */
115245 /*
115246  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_CNAK
115247  *
115248  * No Clear NAK
115249  */
115250 #define ALT_USB_DEV_DOEPCTL5_CNAK_E_INACT 0x0
115251 /*
115252  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_CNAK
115253  *
115254  * Clear NAK
115255  */
115256 #define ALT_USB_DEV_DOEPCTL5_CNAK_E_ACT 0x1
115257 
115258 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */
115259 #define ALT_USB_DEV_DOEPCTL5_CNAK_LSB 26
115260 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */
115261 #define ALT_USB_DEV_DOEPCTL5_CNAK_MSB 26
115262 /* The width in bits of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */
115263 #define ALT_USB_DEV_DOEPCTL5_CNAK_WIDTH 1
115264 /* The mask used to set the ALT_USB_DEV_DOEPCTL5_CNAK register field value. */
115265 #define ALT_USB_DEV_DOEPCTL5_CNAK_SET_MSK 0x04000000
115266 /* The mask used to clear the ALT_USB_DEV_DOEPCTL5_CNAK register field value. */
115267 #define ALT_USB_DEV_DOEPCTL5_CNAK_CLR_MSK 0xfbffffff
115268 /* The reset value of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */
115269 #define ALT_USB_DEV_DOEPCTL5_CNAK_RESET 0x0
115270 /* Extracts the ALT_USB_DEV_DOEPCTL5_CNAK field value from a register. */
115271 #define ALT_USB_DEV_DOEPCTL5_CNAK_GET(value) (((value) & 0x04000000) >> 26)
115272 /* Produces a ALT_USB_DEV_DOEPCTL5_CNAK register field value suitable for setting the register. */
115273 #define ALT_USB_DEV_DOEPCTL5_CNAK_SET(value) (((value) << 26) & 0x04000000)
115274 
115275 /*
115276  * Field : snak
115277  *
115278  * Set NAK (SNAK)
115279  *
115280  * A write to this bit sets the NAK bit For the endpoint.
115281  *
115282  * Using this bit, the application can control the transmission of NAK
115283  *
115284  * handshakes on an endpoint. The core can also Set this bit For an
115285  *
115286  * endpoint after a SETUP packet is received on that endpoint.
115287  *
115288  * Field Enumeration Values:
115289  *
115290  * Enum | Value | Description
115291  * :----------------------------------|:------|:------------
115292  * ALT_USB_DEV_DOEPCTL5_SNAK_E_INACT | 0x0 | No Set NAK
115293  * ALT_USB_DEV_DOEPCTL5_SNAK_E_ACT | 0x1 | Set NAK
115294  *
115295  * Field Access Macros:
115296  *
115297  */
115298 /*
115299  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNAK
115300  *
115301  * No Set NAK
115302  */
115303 #define ALT_USB_DEV_DOEPCTL5_SNAK_E_INACT 0x0
115304 /*
115305  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNAK
115306  *
115307  * Set NAK
115308  */
115309 #define ALT_USB_DEV_DOEPCTL5_SNAK_E_ACT 0x1
115310 
115311 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */
115312 #define ALT_USB_DEV_DOEPCTL5_SNAK_LSB 27
115313 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */
115314 #define ALT_USB_DEV_DOEPCTL5_SNAK_MSB 27
115315 /* The width in bits of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */
115316 #define ALT_USB_DEV_DOEPCTL5_SNAK_WIDTH 1
115317 /* The mask used to set the ALT_USB_DEV_DOEPCTL5_SNAK register field value. */
115318 #define ALT_USB_DEV_DOEPCTL5_SNAK_SET_MSK 0x08000000
115319 /* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SNAK register field value. */
115320 #define ALT_USB_DEV_DOEPCTL5_SNAK_CLR_MSK 0xf7ffffff
115321 /* The reset value of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */
115322 #define ALT_USB_DEV_DOEPCTL5_SNAK_RESET 0x0
115323 /* Extracts the ALT_USB_DEV_DOEPCTL5_SNAK field value from a register. */
115324 #define ALT_USB_DEV_DOEPCTL5_SNAK_GET(value) (((value) & 0x08000000) >> 27)
115325 /* Produces a ALT_USB_DEV_DOEPCTL5_SNAK register field value suitable for setting the register. */
115326 #define ALT_USB_DEV_DOEPCTL5_SNAK_SET(value) (((value) << 27) & 0x08000000)
115327 
115328 /*
115329  * Field : setd0pid
115330  *
115331  * Set DATA0 PID (SetD0PID)
115332  *
115333  * Applies to interrupt/bulk IN and OUT endpoints only.
115334  *
115335  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
115336  * to DATA0.
115337  *
115338  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
115339  *
115340  * DMA mode.
115341  *
115342  * 1'b0 WO
115343  *
115344  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
115345  *
115346  * Applies to isochronous IN and OUT endpoints only.
115347  *
115348  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
115349  * (micro)
115350  *
115351  * frame.
115352  *
115353  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
115354  * number
115355  *
115356  * in which to send data is in the transmit descriptor structure. The frame in
115357  * which to
115358  *
115359  * receive data is updated in receive descriptor structure.
115360  *
115361  * Field Enumeration Values:
115362  *
115363  * Enum | Value | Description
115364  * :-------------------------------------|:------|:------------------------------------
115365  * ALT_USB_DEV_DOEPCTL5_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
115366  * ALT_USB_DEV_DOEPCTL5_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
115367  *
115368  * Field Access Macros:
115369  *
115370  */
115371 /*
115372  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD0PID
115373  *
115374  * Disables Set DATA0 PID
115375  */
115376 #define ALT_USB_DEV_DOEPCTL5_SETD0PID_E_DISD 0x0
115377 /*
115378  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD0PID
115379  *
115380  * Enables Endpoint Data PID to DATA0)
115381  */
115382 #define ALT_USB_DEV_DOEPCTL5_SETD0PID_E_END 0x1
115383 
115384 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */
115385 #define ALT_USB_DEV_DOEPCTL5_SETD0PID_LSB 28
115386 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */
115387 #define ALT_USB_DEV_DOEPCTL5_SETD0PID_MSB 28
115388 /* The width in bits of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */
115389 #define ALT_USB_DEV_DOEPCTL5_SETD0PID_WIDTH 1
115390 /* The mask used to set the ALT_USB_DEV_DOEPCTL5_SETD0PID register field value. */
115391 #define ALT_USB_DEV_DOEPCTL5_SETD0PID_SET_MSK 0x10000000
115392 /* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SETD0PID register field value. */
115393 #define ALT_USB_DEV_DOEPCTL5_SETD0PID_CLR_MSK 0xefffffff
115394 /* The reset value of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */
115395 #define ALT_USB_DEV_DOEPCTL5_SETD0PID_RESET 0x0
115396 /* Extracts the ALT_USB_DEV_DOEPCTL5_SETD0PID field value from a register. */
115397 #define ALT_USB_DEV_DOEPCTL5_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
115398 /* Produces a ALT_USB_DEV_DOEPCTL5_SETD0PID register field value suitable for setting the register. */
115399 #define ALT_USB_DEV_DOEPCTL5_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
115400 
115401 /*
115402  * Field : setd1pid
115403  *
115404  * Set DATA1 PID (SetD1PID)
115405  *
115406  * Applies to interrupt/bulk IN and OUT endpoints only.
115407  *
115408  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
115409  * to DATA1.
115410  *
115411  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
115412  *
115413  * DMA mode.
115414  *
115415  * Set Odd (micro)frame (SetOddFr)
115416  *
115417  * Applies to isochronous IN and OUT endpoints only.
115418  *
115419  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
115420  *
115421  * (micro)frame.
115422  *
115423  * This field is not applicable for Scatter/Gather DMA mode.
115424  *
115425  * Field Enumeration Values:
115426  *
115427  * Enum | Value | Description
115428  * :-------------------------------------|:------|:-----------------------
115429  * ALT_USB_DEV_DOEPCTL5_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
115430  * ALT_USB_DEV_DOEPCTL5_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
115431  *
115432  * Field Access Macros:
115433  *
115434  */
115435 /*
115436  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD1PID
115437  *
115438  * Disables Set DATA1 PID
115439  */
115440 #define ALT_USB_DEV_DOEPCTL5_SETD1PID_E_DISD 0x0
115441 /*
115442  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD1PID
115443  *
115444  * Enables Set DATA1 PID
115445  */
115446 #define ALT_USB_DEV_DOEPCTL5_SETD1PID_E_END 0x1
115447 
115448 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */
115449 #define ALT_USB_DEV_DOEPCTL5_SETD1PID_LSB 29
115450 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */
115451 #define ALT_USB_DEV_DOEPCTL5_SETD1PID_MSB 29
115452 /* The width in bits of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */
115453 #define ALT_USB_DEV_DOEPCTL5_SETD1PID_WIDTH 1
115454 /* The mask used to set the ALT_USB_DEV_DOEPCTL5_SETD1PID register field value. */
115455 #define ALT_USB_DEV_DOEPCTL5_SETD1PID_SET_MSK 0x20000000
115456 /* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SETD1PID register field value. */
115457 #define ALT_USB_DEV_DOEPCTL5_SETD1PID_CLR_MSK 0xdfffffff
115458 /* The reset value of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */
115459 #define ALT_USB_DEV_DOEPCTL5_SETD1PID_RESET 0x0
115460 /* Extracts the ALT_USB_DEV_DOEPCTL5_SETD1PID field value from a register. */
115461 #define ALT_USB_DEV_DOEPCTL5_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
115462 /* Produces a ALT_USB_DEV_DOEPCTL5_SETD1PID register field value suitable for setting the register. */
115463 #define ALT_USB_DEV_DOEPCTL5_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
115464 
115465 /*
115466  * Field : epdis
115467  *
115468  * Endpoint Disable (EPDis)
115469  *
115470  * Applies to IN and OUT endpoints.
115471  *
115472  * The application sets this bit to stop transmitting/receiving data on an
115473  * endpoint, even
115474  *
115475  * before the transfer for that endpoint is complete. The application must wait for
115476  * the
115477  *
115478  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
115479  * clears
115480  *
115481  * this bit before setting the Endpoint Disabled interrupt. The application must
115482  * set this bit
115483  *
115484  * only if Endpoint Enable is already set for this endpoint.
115485  *
115486  * Field Enumeration Values:
115487  *
115488  * Enum | Value | Description
115489  * :-----------------------------------|:------|:--------------------
115490  * ALT_USB_DEV_DOEPCTL5_EPDIS_E_INACT | 0x0 | No Endpoint Disable
115491  * ALT_USB_DEV_DOEPCTL5_EPDIS_E_ACT | 0x1 | Endpoint Disable
115492  *
115493  * Field Access Macros:
115494  *
115495  */
115496 /*
115497  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPDIS
115498  *
115499  * No Endpoint Disable
115500  */
115501 #define ALT_USB_DEV_DOEPCTL5_EPDIS_E_INACT 0x0
115502 /*
115503  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPDIS
115504  *
115505  * Endpoint Disable
115506  */
115507 #define ALT_USB_DEV_DOEPCTL5_EPDIS_E_ACT 0x1
115508 
115509 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */
115510 #define ALT_USB_DEV_DOEPCTL5_EPDIS_LSB 30
115511 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */
115512 #define ALT_USB_DEV_DOEPCTL5_EPDIS_MSB 30
115513 /* The width in bits of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */
115514 #define ALT_USB_DEV_DOEPCTL5_EPDIS_WIDTH 1
115515 /* The mask used to set the ALT_USB_DEV_DOEPCTL5_EPDIS register field value. */
115516 #define ALT_USB_DEV_DOEPCTL5_EPDIS_SET_MSK 0x40000000
115517 /* The mask used to clear the ALT_USB_DEV_DOEPCTL5_EPDIS register field value. */
115518 #define ALT_USB_DEV_DOEPCTL5_EPDIS_CLR_MSK 0xbfffffff
115519 /* The reset value of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */
115520 #define ALT_USB_DEV_DOEPCTL5_EPDIS_RESET 0x0
115521 /* Extracts the ALT_USB_DEV_DOEPCTL5_EPDIS field value from a register. */
115522 #define ALT_USB_DEV_DOEPCTL5_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
115523 /* Produces a ALT_USB_DEV_DOEPCTL5_EPDIS register field value suitable for setting the register. */
115524 #define ALT_USB_DEV_DOEPCTL5_EPDIS_SET(value) (((value) << 30) & 0x40000000)
115525 
115526 /*
115527  * Field : epena
115528  *
115529  * Endpoint Enable (EPEna)
115530  *
115531  * Applies to IN and OUT endpoints.
115532  *
115533  * When Scatter/Gather DMA mode is enabled,
115534  *
115535  * For IN endpoints this bit indicates that the descriptor structure and data
115536  * buffer with
115537  *
115538  * data ready to transmit is setup.
115539  *
115540  * For OUT endpoint it indicates that the descriptor structure and data buffer to
115541  *
115542  * receive data is setup.
115543  *
115544  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
115545  *
115546  * DMA mode:
115547  *
115548  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
115549  * the
115550  *
115551  * endpoint.
115552  *
115553  * * For OUT endpoints, this bit indicates that the application has allocated the
115554  *
115555  * memory to start receiving data from the USB.
115556  *
115557  * * The core clears this bit before setting any of the following interrupts on
115558  * this
115559  *
115560  * endpoint:
115561  *
115562  * SETUP Phase Done
115563  *
115564  * Endpoint Disabled
115565  *
115566  * Transfer Completed
115567  *
115568  * Note: For control endpoints in DMA mode, this bit must be set to be able to
115569  * transfer
115570  *
115571  * SETUP data packets in memory.
115572  *
115573  * Field Enumeration Values:
115574  *
115575  * Enum | Value | Description
115576  * :-----------------------------------|:------|:-------------------------
115577  * ALT_USB_DEV_DOEPCTL5_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
115578  * ALT_USB_DEV_DOEPCTL5_EPENA_E_ACT | 0x1 | Endpoint Enable active
115579  *
115580  * Field Access Macros:
115581  *
115582  */
115583 /*
115584  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPENA
115585  *
115586  * Endpoint Enable inactive
115587  */
115588 #define ALT_USB_DEV_DOEPCTL5_EPENA_E_INACT 0x0
115589 /*
115590  * Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPENA
115591  *
115592  * Endpoint Enable active
115593  */
115594 #define ALT_USB_DEV_DOEPCTL5_EPENA_E_ACT 0x1
115595 
115596 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */
115597 #define ALT_USB_DEV_DOEPCTL5_EPENA_LSB 31
115598 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */
115599 #define ALT_USB_DEV_DOEPCTL5_EPENA_MSB 31
115600 /* The width in bits of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */
115601 #define ALT_USB_DEV_DOEPCTL5_EPENA_WIDTH 1
115602 /* The mask used to set the ALT_USB_DEV_DOEPCTL5_EPENA register field value. */
115603 #define ALT_USB_DEV_DOEPCTL5_EPENA_SET_MSK 0x80000000
115604 /* The mask used to clear the ALT_USB_DEV_DOEPCTL5_EPENA register field value. */
115605 #define ALT_USB_DEV_DOEPCTL5_EPENA_CLR_MSK 0x7fffffff
115606 /* The reset value of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */
115607 #define ALT_USB_DEV_DOEPCTL5_EPENA_RESET 0x0
115608 /* Extracts the ALT_USB_DEV_DOEPCTL5_EPENA field value from a register. */
115609 #define ALT_USB_DEV_DOEPCTL5_EPENA_GET(value) (((value) & 0x80000000) >> 31)
115610 /* Produces a ALT_USB_DEV_DOEPCTL5_EPENA register field value suitable for setting the register. */
115611 #define ALT_USB_DEV_DOEPCTL5_EPENA_SET(value) (((value) << 31) & 0x80000000)
115612 
115613 #ifndef __ASSEMBLY__
115614 /*
115615  * WARNING: The C register and register group struct declarations are provided for
115616  * convenience and illustrative purposes. They should, however, be used with
115617  * caution as the C language standard provides no guarantees about the alignment or
115618  * atomicity of device memory accesses. The recommended practice for writing
115619  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
115620  * alt_write_word() functions.
115621  *
115622  * The struct declaration for register ALT_USB_DEV_DOEPCTL5.
115623  */
115624 struct ALT_USB_DEV_DOEPCTL5_s
115625 {
115626  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL5_MPS */
115627  uint32_t : 4; /* *UNDEFINED* */
115628  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL5_USBACTEP */
115629  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL5_DPID */
115630  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL5_NAKSTS */
115631  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL5_EPTYPE */
115632  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL5_SNP */
115633  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL5_STALL */
115634  uint32_t : 4; /* *UNDEFINED* */
115635  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL5_CNAK */
115636  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL5_SNAK */
115637  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL5_SETD0PID */
115638  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL5_SETD1PID */
115639  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL5_EPDIS */
115640  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL5_EPENA */
115641 };
115642 
115643 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL5. */
115644 typedef volatile struct ALT_USB_DEV_DOEPCTL5_s ALT_USB_DEV_DOEPCTL5_t;
115645 #endif /* __ASSEMBLY__ */
115646 
115647 /* The reset value of the ALT_USB_DEV_DOEPCTL5 register. */
115648 #define ALT_USB_DEV_DOEPCTL5_RESET 0x00000000
115649 /* The byte offset of the ALT_USB_DEV_DOEPCTL5 register from the beginning of the component. */
115650 #define ALT_USB_DEV_DOEPCTL5_OFST 0x3a0
115651 /* The address of the ALT_USB_DEV_DOEPCTL5 register. */
115652 #define ALT_USB_DEV_DOEPCTL5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL5_OFST))
115653 
115654 /*
115655  * Register : doepint5
115656  *
115657  * Device OUT Endpoint 5 Interrupt Register
115658  *
115659  * Register Layout
115660  *
115661  * Bits | Access | Reset | Description
115662  * :--------|:-------|:------|:------------------------------------
115663  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_XFERCOMPL
115664  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_EPDISBLD
115665  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_AHBERR
115666  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_SETUP
115667  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS
115668  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_STSPHSERCVD
115669  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP
115670  * [7] | ??? | 0x0 | *UNDEFINED*
115671  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_OUTPKTERR
115672  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_BNAINTR
115673  * [10] | ??? | 0x0 | *UNDEFINED*
115674  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_PKTDRPSTS
115675  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_BBLEERR
115676  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_NAKINTRPT
115677  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_NYETINTRPT
115678  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_STUPPKTRCVD
115679  * [31:16] | ??? | 0x0 | *UNDEFINED*
115680  *
115681  */
115682 /*
115683  * Field : xfercompl
115684  *
115685  * Transfer Completed Interrupt (XferCompl)
115686  *
115687  * Applies to IN and OUT endpoints.
115688  *
115689  * When Scatter/Gather DMA mode is enabled
115690  *
115691  * * For IN endpoint this field indicates that the requested data
115692  *
115693  * from the descriptor is moved from external system memory
115694  *
115695  * to internal FIFO.
115696  *
115697  * * For OUT endpoint this field indicates that the requested
115698  *
115699  * data from the internal FIFO is moved to external system
115700  *
115701  * memory. This interrupt is generated only when the
115702  *
115703  * corresponding endpoint descriptor is closed, and the IOC
115704  *
115705  * bit For the corresponding descriptor is Set.
115706  *
115707  * When Scatter/Gather DMA mode is disabled, this field
115708  *
115709  * indicates that the programmed transfer is complete on the
115710  *
115711  * AHB as well as on the USB, For this endpoint.
115712  *
115713  * Field Enumeration Values:
115714  *
115715  * Enum | Value | Description
115716  * :---------------------------------------|:------|:-----------------------------
115717  * ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_INACT | 0x0 | No Interrupt
115718  * ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
115719  *
115720  * Field Access Macros:
115721  *
115722  */
115723 /*
115724  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_XFERCOMPL
115725  *
115726  * No Interrupt
115727  */
115728 #define ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_INACT 0x0
115729 /*
115730  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_XFERCOMPL
115731  *
115732  * Transfer Completed Interrupt
115733  */
115734 #define ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_ACT 0x1
115735 
115736 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */
115737 #define ALT_USB_DEV_DOEPINT5_XFERCOMPL_LSB 0
115738 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */
115739 #define ALT_USB_DEV_DOEPINT5_XFERCOMPL_MSB 0
115740 /* The width in bits of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */
115741 #define ALT_USB_DEV_DOEPINT5_XFERCOMPL_WIDTH 1
115742 /* The mask used to set the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field value. */
115743 #define ALT_USB_DEV_DOEPINT5_XFERCOMPL_SET_MSK 0x00000001
115744 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field value. */
115745 #define ALT_USB_DEV_DOEPINT5_XFERCOMPL_CLR_MSK 0xfffffffe
115746 /* The reset value of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */
115747 #define ALT_USB_DEV_DOEPINT5_XFERCOMPL_RESET 0x0
115748 /* Extracts the ALT_USB_DEV_DOEPINT5_XFERCOMPL field value from a register. */
115749 #define ALT_USB_DEV_DOEPINT5_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
115750 /* Produces a ALT_USB_DEV_DOEPINT5_XFERCOMPL register field value suitable for setting the register. */
115751 #define ALT_USB_DEV_DOEPINT5_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
115752 
115753 /*
115754  * Field : epdisbld
115755  *
115756  * Endpoint Disabled Interrupt (EPDisbld)
115757  *
115758  * Applies to IN and OUT endpoints.
115759  *
115760  * This bit indicates that the endpoint is disabled per the
115761  *
115762  * application's request.
115763  *
115764  * Field Enumeration Values:
115765  *
115766  * Enum | Value | Description
115767  * :--------------------------------------|:------|:----------------------------
115768  * ALT_USB_DEV_DOEPINT5_EPDISBLD_E_INACT | 0x0 | No Interrupt
115769  * ALT_USB_DEV_DOEPINT5_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
115770  *
115771  * Field Access Macros:
115772  *
115773  */
115774 /*
115775  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_EPDISBLD
115776  *
115777  * No Interrupt
115778  */
115779 #define ALT_USB_DEV_DOEPINT5_EPDISBLD_E_INACT 0x0
115780 /*
115781  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_EPDISBLD
115782  *
115783  * Endpoint Disabled Interrupt
115784  */
115785 #define ALT_USB_DEV_DOEPINT5_EPDISBLD_E_ACT 0x1
115786 
115787 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */
115788 #define ALT_USB_DEV_DOEPINT5_EPDISBLD_LSB 1
115789 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */
115790 #define ALT_USB_DEV_DOEPINT5_EPDISBLD_MSB 1
115791 /* The width in bits of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */
115792 #define ALT_USB_DEV_DOEPINT5_EPDISBLD_WIDTH 1
115793 /* The mask used to set the ALT_USB_DEV_DOEPINT5_EPDISBLD register field value. */
115794 #define ALT_USB_DEV_DOEPINT5_EPDISBLD_SET_MSK 0x00000002
115795 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_EPDISBLD register field value. */
115796 #define ALT_USB_DEV_DOEPINT5_EPDISBLD_CLR_MSK 0xfffffffd
115797 /* The reset value of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */
115798 #define ALT_USB_DEV_DOEPINT5_EPDISBLD_RESET 0x0
115799 /* Extracts the ALT_USB_DEV_DOEPINT5_EPDISBLD field value from a register. */
115800 #define ALT_USB_DEV_DOEPINT5_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
115801 /* Produces a ALT_USB_DEV_DOEPINT5_EPDISBLD register field value suitable for setting the register. */
115802 #define ALT_USB_DEV_DOEPINT5_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
115803 
115804 /*
115805  * Field : ahberr
115806  *
115807  * AHB Error (AHBErr)
115808  *
115809  * Applies to IN and OUT endpoints.
115810  *
115811  * This is generated only in Internal DMA mode when there is an
115812  *
115813  * AHB error during an AHB read/write. The application can read
115814  *
115815  * the corresponding endpoint DMA address register to get the
115816  *
115817  * error address.
115818  *
115819  * Field Enumeration Values:
115820  *
115821  * Enum | Value | Description
115822  * :------------------------------------|:------|:--------------------
115823  * ALT_USB_DEV_DOEPINT5_AHBERR_E_INACT | 0x0 | No Interrupt
115824  * ALT_USB_DEV_DOEPINT5_AHBERR_E_ACT | 0x1 | AHB Error interrupt
115825  *
115826  * Field Access Macros:
115827  *
115828  */
115829 /*
115830  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_AHBERR
115831  *
115832  * No Interrupt
115833  */
115834 #define ALT_USB_DEV_DOEPINT5_AHBERR_E_INACT 0x0
115835 /*
115836  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_AHBERR
115837  *
115838  * AHB Error interrupt
115839  */
115840 #define ALT_USB_DEV_DOEPINT5_AHBERR_E_ACT 0x1
115841 
115842 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */
115843 #define ALT_USB_DEV_DOEPINT5_AHBERR_LSB 2
115844 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */
115845 #define ALT_USB_DEV_DOEPINT5_AHBERR_MSB 2
115846 /* The width in bits of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */
115847 #define ALT_USB_DEV_DOEPINT5_AHBERR_WIDTH 1
115848 /* The mask used to set the ALT_USB_DEV_DOEPINT5_AHBERR register field value. */
115849 #define ALT_USB_DEV_DOEPINT5_AHBERR_SET_MSK 0x00000004
115850 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_AHBERR register field value. */
115851 #define ALT_USB_DEV_DOEPINT5_AHBERR_CLR_MSK 0xfffffffb
115852 /* The reset value of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */
115853 #define ALT_USB_DEV_DOEPINT5_AHBERR_RESET 0x0
115854 /* Extracts the ALT_USB_DEV_DOEPINT5_AHBERR field value from a register. */
115855 #define ALT_USB_DEV_DOEPINT5_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
115856 /* Produces a ALT_USB_DEV_DOEPINT5_AHBERR register field value suitable for setting the register. */
115857 #define ALT_USB_DEV_DOEPINT5_AHBERR_SET(value) (((value) << 2) & 0x00000004)
115858 
115859 /*
115860  * Field : setup
115861  *
115862  * SETUP Phase Done (SetUp)
115863  *
115864  * Applies to control OUT endpoints only.
115865  *
115866  * Indicates that the SETUP phase For the control endpoint is
115867  *
115868  * complete and no more back-to-back SETUP packets were
115869  *
115870  * received For the current control transfer. On this interrupt, the
115871  *
115872  * application can decode the received SETUP data packet.
115873  *
115874  * Field Enumeration Values:
115875  *
115876  * Enum | Value | Description
115877  * :-----------------------------------|:------|:--------------------
115878  * ALT_USB_DEV_DOEPINT5_SETUP_E_INACT | 0x0 | No SETUP Phase Done
115879  * ALT_USB_DEV_DOEPINT5_SETUP_E_ACT | 0x1 | SETUP Phase Done
115880  *
115881  * Field Access Macros:
115882  *
115883  */
115884 /*
115885  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_SETUP
115886  *
115887  * No SETUP Phase Done
115888  */
115889 #define ALT_USB_DEV_DOEPINT5_SETUP_E_INACT 0x0
115890 /*
115891  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_SETUP
115892  *
115893  * SETUP Phase Done
115894  */
115895 #define ALT_USB_DEV_DOEPINT5_SETUP_E_ACT 0x1
115896 
115897 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_SETUP register field. */
115898 #define ALT_USB_DEV_DOEPINT5_SETUP_LSB 3
115899 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_SETUP register field. */
115900 #define ALT_USB_DEV_DOEPINT5_SETUP_MSB 3
115901 /* The width in bits of the ALT_USB_DEV_DOEPINT5_SETUP register field. */
115902 #define ALT_USB_DEV_DOEPINT5_SETUP_WIDTH 1
115903 /* The mask used to set the ALT_USB_DEV_DOEPINT5_SETUP register field value. */
115904 #define ALT_USB_DEV_DOEPINT5_SETUP_SET_MSK 0x00000008
115905 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_SETUP register field value. */
115906 #define ALT_USB_DEV_DOEPINT5_SETUP_CLR_MSK 0xfffffff7
115907 /* The reset value of the ALT_USB_DEV_DOEPINT5_SETUP register field. */
115908 #define ALT_USB_DEV_DOEPINT5_SETUP_RESET 0x0
115909 /* Extracts the ALT_USB_DEV_DOEPINT5_SETUP field value from a register. */
115910 #define ALT_USB_DEV_DOEPINT5_SETUP_GET(value) (((value) & 0x00000008) >> 3)
115911 /* Produces a ALT_USB_DEV_DOEPINT5_SETUP register field value suitable for setting the register. */
115912 #define ALT_USB_DEV_DOEPINT5_SETUP_SET(value) (((value) << 3) & 0x00000008)
115913 
115914 /*
115915  * Field : outtknepdis
115916  *
115917  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
115918  *
115919  * Applies only to control OUT endpoints.
115920  *
115921  * Indicates that an OUT token was received when the endpoint
115922  *
115923  * was not yet enabled. This interrupt is asserted on the endpoint
115924  *
115925  * For which the OUT token was received.
115926  *
115927  * Field Enumeration Values:
115928  *
115929  * Enum | Value | Description
115930  * :-----------------------------------------|:------|:---------------------------------------------
115931  * ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
115932  * ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
115933  *
115934  * Field Access Macros:
115935  *
115936  */
115937 /*
115938  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS
115939  *
115940  * No OUT Token Received When Endpoint Disabled
115941  */
115942 #define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_INACT 0x0
115943 /*
115944  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS
115945  *
115946  * OUT Token Received When Endpoint Disabled
115947  */
115948 #define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_ACT 0x1
115949 
115950 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */
115951 #define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_LSB 4
115952 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */
115953 #define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_MSB 4
115954 /* The width in bits of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */
115955 #define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_WIDTH 1
115956 /* The mask used to set the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field value. */
115957 #define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_SET_MSK 0x00000010
115958 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field value. */
115959 #define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_CLR_MSK 0xffffffef
115960 /* The reset value of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */
115961 #define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_RESET 0x0
115962 /* Extracts the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS field value from a register. */
115963 #define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
115964 /* Produces a ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field value suitable for setting the register. */
115965 #define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
115966 
115967 /*
115968  * Field : stsphsercvd
115969  *
115970  * Status Phase Received For Control Write (StsPhseRcvd)
115971  *
115972  * This interrupt is valid only For Control OUT endpoints and only in
115973  *
115974  * Scatter Gather DMA mode.
115975  *
115976  * This interrupt is generated only after the core has transferred all
115977  *
115978  * the data that the host has sent during the data phase of a control
115979  *
115980  * write transfer, to the system memory buffer.
115981  *
115982  * The interrupt indicates to the application that the host has
115983  *
115984  * switched from data phase to the status phase of a Control Write
115985  *
115986  * transfer. The application can use this interrupt to ACK or STALL
115987  *
115988  * the Status phase, after it has decoded the data phase. This is
115989  *
115990  * applicable only in Case of Scatter Gather DMA mode.
115991  *
115992  * Field Enumeration Values:
115993  *
115994  * Enum | Value | Description
115995  * :-----------------------------------------|:------|:-------------------------------------------
115996  * ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
115997  * ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
115998  *
115999  * Field Access Macros:
116000  *
116001  */
116002 /*
116003  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_STSPHSERCVD
116004  *
116005  * No Status Phase Received for Control Write
116006  */
116007 #define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_INACT 0x0
116008 /*
116009  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_STSPHSERCVD
116010  *
116011  * Status Phase Received for Control Write
116012  */
116013 #define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_ACT 0x1
116014 
116015 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */
116016 #define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_LSB 5
116017 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */
116018 #define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_MSB 5
116019 /* The width in bits of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */
116020 #define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_WIDTH 1
116021 /* The mask used to set the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field value. */
116022 #define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_SET_MSK 0x00000020
116023 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field value. */
116024 #define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_CLR_MSK 0xffffffdf
116025 /* The reset value of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */
116026 #define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_RESET 0x0
116027 /* Extracts the ALT_USB_DEV_DOEPINT5_STSPHSERCVD field value from a register. */
116028 #define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
116029 /* Produces a ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field value suitable for setting the register. */
116030 #define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
116031 
116032 /*
116033  * Field : back2backsetup
116034  *
116035  * Back-to-Back SETUP Packets Received (Back2BackSETup)
116036  *
116037  * Applies to Control OUT endpoints only.
116038  *
116039  * This bit indicates that the core has received more than three
116040  *
116041  * back-to-back SETUP packets For this particular endpoint. For
116042  *
116043  * information about handling this interrupt,
116044  *
116045  * Field Enumeration Values:
116046  *
116047  * Enum | Value | Description
116048  * :--------------------------------------------|:------|:---------------------------------------
116049  * ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
116050  * ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
116051  *
116052  * Field Access Macros:
116053  *
116054  */
116055 /*
116056  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP
116057  *
116058  * No Back-to-Back SETUP Packets Received
116059  */
116060 #define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_INACT 0x0
116061 /*
116062  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP
116063  *
116064  * Back-to-Back SETUP Packets Received
116065  */
116066 #define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_ACT 0x1
116067 
116068 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */
116069 #define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_LSB 6
116070 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */
116071 #define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_MSB 6
116072 /* The width in bits of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */
116073 #define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_WIDTH 1
116074 /* The mask used to set the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field value. */
116075 #define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_SET_MSK 0x00000040
116076 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field value. */
116077 #define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_CLR_MSK 0xffffffbf
116078 /* The reset value of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */
116079 #define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_RESET 0x0
116080 /* Extracts the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP field value from a register. */
116081 #define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
116082 /* Produces a ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field value suitable for setting the register. */
116083 #define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
116084 
116085 /*
116086  * Field : outpkterr
116087  *
116088  * OUT Packet Error (OutPktErr)
116089  *
116090  * Applies to OUT endpoints Only
116091  *
116092  * This interrupt is valid only when thresholding is enabled. This interrupt is
116093  * asserted when the
116094  *
116095  * core detects an overflow or a CRC error For non-Isochronous
116096  *
116097  * OUT packet.
116098  *
116099  * Field Enumeration Values:
116100  *
116101  * Enum | Value | Description
116102  * :---------------------------------------|:------|:--------------------
116103  * ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
116104  * ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
116105  *
116106  * Field Access Macros:
116107  *
116108  */
116109 /*
116110  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTPKTERR
116111  *
116112  * No OUT Packet Error
116113  */
116114 #define ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_INACT 0x0
116115 /*
116116  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTPKTERR
116117  *
116118  * OUT Packet Error
116119  */
116120 #define ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_ACT 0x1
116121 
116122 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */
116123 #define ALT_USB_DEV_DOEPINT5_OUTPKTERR_LSB 8
116124 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */
116125 #define ALT_USB_DEV_DOEPINT5_OUTPKTERR_MSB 8
116126 /* The width in bits of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */
116127 #define ALT_USB_DEV_DOEPINT5_OUTPKTERR_WIDTH 1
116128 /* The mask used to set the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field value. */
116129 #define ALT_USB_DEV_DOEPINT5_OUTPKTERR_SET_MSK 0x00000100
116130 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field value. */
116131 #define ALT_USB_DEV_DOEPINT5_OUTPKTERR_CLR_MSK 0xfffffeff
116132 /* The reset value of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */
116133 #define ALT_USB_DEV_DOEPINT5_OUTPKTERR_RESET 0x0
116134 /* Extracts the ALT_USB_DEV_DOEPINT5_OUTPKTERR field value from a register. */
116135 #define ALT_USB_DEV_DOEPINT5_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
116136 /* Produces a ALT_USB_DEV_DOEPINT5_OUTPKTERR register field value suitable for setting the register. */
116137 #define ALT_USB_DEV_DOEPINT5_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
116138 
116139 /*
116140  * Field : bnaintr
116141  *
116142  * BNA (Buffer Not Available) Interrupt (BNAIntr)
116143  *
116144  * This bit is valid only when Scatter/Gather DMA mode is enabled.
116145  *
116146  * The core generates this interrupt when the descriptor accessed
116147  *
116148  * is not ready For the Core to process, such as Host busy or DMA
116149  *
116150  * done
116151  *
116152  * Field Enumeration Values:
116153  *
116154  * Enum | Value | Description
116155  * :-------------------------------------|:------|:--------------
116156  * ALT_USB_DEV_DOEPINT5_BNAINTR_E_INACT | 0x0 | No interrupt
116157  * ALT_USB_DEV_DOEPINT5_BNAINTR_E_ACT | 0x1 | BNA interrupt
116158  *
116159  * Field Access Macros:
116160  *
116161  */
116162 /*
116163  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BNAINTR
116164  *
116165  * No interrupt
116166  */
116167 #define ALT_USB_DEV_DOEPINT5_BNAINTR_E_INACT 0x0
116168 /*
116169  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BNAINTR
116170  *
116171  * BNA interrupt
116172  */
116173 #define ALT_USB_DEV_DOEPINT5_BNAINTR_E_ACT 0x1
116174 
116175 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */
116176 #define ALT_USB_DEV_DOEPINT5_BNAINTR_LSB 9
116177 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */
116178 #define ALT_USB_DEV_DOEPINT5_BNAINTR_MSB 9
116179 /* The width in bits of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */
116180 #define ALT_USB_DEV_DOEPINT5_BNAINTR_WIDTH 1
116181 /* The mask used to set the ALT_USB_DEV_DOEPINT5_BNAINTR register field value. */
116182 #define ALT_USB_DEV_DOEPINT5_BNAINTR_SET_MSK 0x00000200
116183 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_BNAINTR register field value. */
116184 #define ALT_USB_DEV_DOEPINT5_BNAINTR_CLR_MSK 0xfffffdff
116185 /* The reset value of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */
116186 #define ALT_USB_DEV_DOEPINT5_BNAINTR_RESET 0x0
116187 /* Extracts the ALT_USB_DEV_DOEPINT5_BNAINTR field value from a register. */
116188 #define ALT_USB_DEV_DOEPINT5_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
116189 /* Produces a ALT_USB_DEV_DOEPINT5_BNAINTR register field value suitable for setting the register. */
116190 #define ALT_USB_DEV_DOEPINT5_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
116191 
116192 /*
116193  * Field : pktdrpsts
116194  *
116195  * Packet Drop Status (PktDrpSts)
116196  *
116197  * This bit indicates to the application that an ISOC OUT packet has been dropped.
116198  * This
116199  *
116200  * bit does not have an associated mask bit and does not generate an interrupt.
116201  *
116202  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
116203  * transfer
116204  *
116205  * interrupt feature is selected.
116206  *
116207  * Field Enumeration Values:
116208  *
116209  * Enum | Value | Description
116210  * :---------------------------------------|:------|:-----------------------------
116211  * ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_INACT | 0x0 | No interrupt
116212  * ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
116213  *
116214  * Field Access Macros:
116215  *
116216  */
116217 /*
116218  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_PKTDRPSTS
116219  *
116220  * No interrupt
116221  */
116222 #define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_INACT 0x0
116223 /*
116224  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_PKTDRPSTS
116225  *
116226  * Packet Drop Status interrupt
116227  */
116228 #define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_ACT 0x1
116229 
116230 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */
116231 #define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_LSB 11
116232 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */
116233 #define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_MSB 11
116234 /* The width in bits of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */
116235 #define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_WIDTH 1
116236 /* The mask used to set the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field value. */
116237 #define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_SET_MSK 0x00000800
116238 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field value. */
116239 #define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_CLR_MSK 0xfffff7ff
116240 /* The reset value of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */
116241 #define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_RESET 0x0
116242 /* Extracts the ALT_USB_DEV_DOEPINT5_PKTDRPSTS field value from a register. */
116243 #define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
116244 /* Produces a ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field value suitable for setting the register. */
116245 #define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
116246 
116247 /*
116248  * Field : bbleerr
116249  *
116250  * NAK Interrupt (BbleErr)
116251  *
116252  * The core generates this interrupt when babble is received for the endpoint.
116253  *
116254  * Field Enumeration Values:
116255  *
116256  * Enum | Value | Description
116257  * :-------------------------------------|:------|:------------------
116258  * ALT_USB_DEV_DOEPINT5_BBLEERR_E_INACT | 0x0 | No interrupt
116259  * ALT_USB_DEV_DOEPINT5_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
116260  *
116261  * Field Access Macros:
116262  *
116263  */
116264 /*
116265  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BBLEERR
116266  *
116267  * No interrupt
116268  */
116269 #define ALT_USB_DEV_DOEPINT5_BBLEERR_E_INACT 0x0
116270 /*
116271  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_BBLEERR
116272  *
116273  * BbleErr interrupt
116274  */
116275 #define ALT_USB_DEV_DOEPINT5_BBLEERR_E_ACT 0x1
116276 
116277 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */
116278 #define ALT_USB_DEV_DOEPINT5_BBLEERR_LSB 12
116279 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */
116280 #define ALT_USB_DEV_DOEPINT5_BBLEERR_MSB 12
116281 /* The width in bits of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */
116282 #define ALT_USB_DEV_DOEPINT5_BBLEERR_WIDTH 1
116283 /* The mask used to set the ALT_USB_DEV_DOEPINT5_BBLEERR register field value. */
116284 #define ALT_USB_DEV_DOEPINT5_BBLEERR_SET_MSK 0x00001000
116285 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_BBLEERR register field value. */
116286 #define ALT_USB_DEV_DOEPINT5_BBLEERR_CLR_MSK 0xffffefff
116287 /* The reset value of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */
116288 #define ALT_USB_DEV_DOEPINT5_BBLEERR_RESET 0x0
116289 /* Extracts the ALT_USB_DEV_DOEPINT5_BBLEERR field value from a register. */
116290 #define ALT_USB_DEV_DOEPINT5_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
116291 /* Produces a ALT_USB_DEV_DOEPINT5_BBLEERR register field value suitable for setting the register. */
116292 #define ALT_USB_DEV_DOEPINT5_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
116293 
116294 /*
116295  * Field : nakintrpt
116296  *
116297  * NAK Interrupt (NAKInterrupt)
116298  *
116299  * The core generates this interrupt when a NAK is transmitted or received by the
116300  * device.
116301  *
116302  * In case of isochronous IN endpoints the interrupt gets generated when a zero
116303  * length
116304  *
116305  * packet is transmitted due to un-availability of data in the TXFifo.
116306  *
116307  * Field Enumeration Values:
116308  *
116309  * Enum | Value | Description
116310  * :---------------------------------------|:------|:--------------
116311  * ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_INACT | 0x0 | No interrupt
116312  * ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
116313  *
116314  * Field Access Macros:
116315  *
116316  */
116317 /*
116318  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_NAKINTRPT
116319  *
116320  * No interrupt
116321  */
116322 #define ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_INACT 0x0
116323 /*
116324  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_NAKINTRPT
116325  *
116326  * NAK Interrupt
116327  */
116328 #define ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_ACT 0x1
116329 
116330 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */
116331 #define ALT_USB_DEV_DOEPINT5_NAKINTRPT_LSB 13
116332 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */
116333 #define ALT_USB_DEV_DOEPINT5_NAKINTRPT_MSB 13
116334 /* The width in bits of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */
116335 #define ALT_USB_DEV_DOEPINT5_NAKINTRPT_WIDTH 1
116336 /* The mask used to set the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field value. */
116337 #define ALT_USB_DEV_DOEPINT5_NAKINTRPT_SET_MSK 0x00002000
116338 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field value. */
116339 #define ALT_USB_DEV_DOEPINT5_NAKINTRPT_CLR_MSK 0xffffdfff
116340 /* The reset value of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */
116341 #define ALT_USB_DEV_DOEPINT5_NAKINTRPT_RESET 0x0
116342 /* Extracts the ALT_USB_DEV_DOEPINT5_NAKINTRPT field value from a register. */
116343 #define ALT_USB_DEV_DOEPINT5_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
116344 /* Produces a ALT_USB_DEV_DOEPINT5_NAKINTRPT register field value suitable for setting the register. */
116345 #define ALT_USB_DEV_DOEPINT5_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
116346 
116347 /*
116348  * Field : nyetintrpt
116349  *
116350  * NYET Interrupt (NYETIntrpt)
116351  *
116352  * The core generates this interrupt when a NYET response is transmitted for a non
116353  * isochronous OUT endpoint.
116354  *
116355  * Field Enumeration Values:
116356  *
116357  * Enum | Value | Description
116358  * :----------------------------------------|:------|:---------------
116359  * ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_INACT | 0x0 | No interrupt
116360  * ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
116361  *
116362  * Field Access Macros:
116363  *
116364  */
116365 /*
116366  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_NYETINTRPT
116367  *
116368  * No interrupt
116369  */
116370 #define ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_INACT 0x0
116371 /*
116372  * Enumerated value for register field ALT_USB_DEV_DOEPINT5_NYETINTRPT
116373  *
116374  * NYET Interrupt
116375  */
116376 #define ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_ACT 0x1
116377 
116378 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */
116379 #define ALT_USB_DEV_DOEPINT5_NYETINTRPT_LSB 14
116380 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */
116381 #define ALT_USB_DEV_DOEPINT5_NYETINTRPT_MSB 14
116382 /* The width in bits of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */
116383 #define ALT_USB_DEV_DOEPINT5_NYETINTRPT_WIDTH 1
116384 /* The mask used to set the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field value. */
116385 #define ALT_USB_DEV_DOEPINT5_NYETINTRPT_SET_MSK 0x00004000
116386 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field value. */
116387 #define ALT_USB_DEV_DOEPINT5_NYETINTRPT_CLR_MSK 0xffffbfff
116388 /* The reset value of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */
116389 #define ALT_USB_DEV_DOEPINT5_NYETINTRPT_RESET 0x0
116390 /* Extracts the ALT_USB_DEV_DOEPINT5_NYETINTRPT field value from a register. */
116391 #define ALT_USB_DEV_DOEPINT5_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
116392 /* Produces a ALT_USB_DEV_DOEPINT5_NYETINTRPT register field value suitable for setting the register. */
116393 #define ALT_USB_DEV_DOEPINT5_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
116394 
116395 /*
116396  * Field : stuppktrcvd
116397  *
116398  * Setup Packet Received
116399  *
116400  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
116401  *
116402  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
116403  *
116404  * setup data. There is only one Setup packet per buffer. On receiving a
116405  *
116406  * Setup packet, the DWC_otg core closes the buffer and disables the
116407  *
116408  * corresponding endpoint. The application has to re-enable the endpoint to
116409  *
116410  * receive any OUT data for the Control Transfer and reprogram the buffer
116411  *
116412  * start address.
116413  *
116414  * Note: Because of the above behavior, the DWC_otg core can receive any
116415  *
116416  * number of back to back setup packets and one buffer for every setup
116417  *
116418  * packet is used.
116419  *
116420  * 1'b0: No Setup packet received
116421  *
116422  * 1'b1: Setup packet received
116423  *
116424  * Reset: 1'b0
116425  *
116426  * Field Access Macros:
116427  *
116428  */
116429 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field. */
116430 #define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_LSB 15
116431 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field. */
116432 #define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_MSB 15
116433 /* The width in bits of the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field. */
116434 #define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_WIDTH 1
116435 /* The mask used to set the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field value. */
116436 #define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_SET_MSK 0x00008000
116437 /* The mask used to clear the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field value. */
116438 #define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_CLR_MSK 0xffff7fff
116439 /* The reset value of the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field. */
116440 #define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_RESET 0x0
116441 /* Extracts the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD field value from a register. */
116442 #define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
116443 /* Produces a ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field value suitable for setting the register. */
116444 #define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
116445 
116446 #ifndef __ASSEMBLY__
116447 /*
116448  * WARNING: The C register and register group struct declarations are provided for
116449  * convenience and illustrative purposes. They should, however, be used with
116450  * caution as the C language standard provides no guarantees about the alignment or
116451  * atomicity of device memory accesses. The recommended practice for writing
116452  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
116453  * alt_write_word() functions.
116454  *
116455  * The struct declaration for register ALT_USB_DEV_DOEPINT5.
116456  */
116457 struct ALT_USB_DEV_DOEPINT5_s
116458 {
116459  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT5_XFERCOMPL */
116460  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT5_EPDISBLD */
116461  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT5_AHBERR */
116462  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT5_SETUP */
116463  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS */
116464  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT5_STSPHSERCVD */
116465  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP */
116466  uint32_t : 1; /* *UNDEFINED* */
116467  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT5_OUTPKTERR */
116468  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT5_BNAINTR */
116469  uint32_t : 1; /* *UNDEFINED* */
116470  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT5_PKTDRPSTS */
116471  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT5_BBLEERR */
116472  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT5_NAKINTRPT */
116473  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT5_NYETINTRPT */
116474  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT5_STUPPKTRCVD */
116475  uint32_t : 16; /* *UNDEFINED* */
116476 };
116477 
116478 /* The typedef declaration for register ALT_USB_DEV_DOEPINT5. */
116479 typedef volatile struct ALT_USB_DEV_DOEPINT5_s ALT_USB_DEV_DOEPINT5_t;
116480 #endif /* __ASSEMBLY__ */
116481 
116482 /* The reset value of the ALT_USB_DEV_DOEPINT5 register. */
116483 #define ALT_USB_DEV_DOEPINT5_RESET 0x00000000
116484 /* The byte offset of the ALT_USB_DEV_DOEPINT5 register from the beginning of the component. */
116485 #define ALT_USB_DEV_DOEPINT5_OFST 0x3a8
116486 /* The address of the ALT_USB_DEV_DOEPINT5 register. */
116487 #define ALT_USB_DEV_DOEPINT5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT5_OFST))
116488 
116489 /*
116490  * Register : doeptsiz5
116491  *
116492  * Device OUT Endpoint 5 Transfer Size Register
116493  *
116494  * Register Layout
116495  *
116496  * Bits | Access | Reset | Description
116497  * :--------|:-------|:------|:-------------------------------
116498  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ5_XFERSIZE
116499  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ5_PKTCNT
116500  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ5_RXDPID
116501  * [31] | ??? | 0x0 | *UNDEFINED*
116502  *
116503  */
116504 /*
116505  * Field : xfersize
116506  *
116507  * Transfer Size (XferSize)
116508  *
116509  * Indicates the transfer size in bytes For endpoint 0. The core
116510  *
116511  * interrupts the application only after it has exhausted the transfer
116512  *
116513  * size amount of data. The transfer size can be Set to the
116514  *
116515  * maximum packet size of the endpoint, to be interrupted at the
116516  *
116517  * end of each packet.
116518  *
116519  * The core decrements this field every time a packet is read from
116520  *
116521  * the RxFIFO and written to the external memory.
116522  *
116523  * Field Access Macros:
116524  *
116525  */
116526 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */
116527 #define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_LSB 0
116528 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */
116529 #define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_MSB 18
116530 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */
116531 #define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_WIDTH 19
116532 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field value. */
116533 #define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_SET_MSK 0x0007ffff
116534 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field value. */
116535 #define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_CLR_MSK 0xfff80000
116536 /* The reset value of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */
116537 #define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_RESET 0x0
116538 /* Extracts the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE field value from a register. */
116539 #define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
116540 /* Produces a ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field value suitable for setting the register. */
116541 #define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
116542 
116543 /*
116544  * Field : pktcnt
116545  *
116546  * Packet Count (PktCnt)
116547  *
116548  * This field is decremented to zero after a packet is written into the
116549  *
116550  * RxFIFO.
116551  *
116552  * Field Access Macros:
116553  *
116554  */
116555 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */
116556 #define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_LSB 19
116557 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */
116558 #define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_MSB 28
116559 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */
116560 #define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_WIDTH 10
116561 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field value. */
116562 #define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_SET_MSK 0x1ff80000
116563 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field value. */
116564 #define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_CLR_MSK 0xe007ffff
116565 /* The reset value of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */
116566 #define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_RESET 0x0
116567 /* Extracts the ALT_USB_DEV_DOEPTSIZ5_PKTCNT field value from a register. */
116568 #define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
116569 /* Produces a ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field value suitable for setting the register. */
116570 #define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
116571 
116572 /*
116573  * Field : rxdpid
116574  *
116575  * Applies to isochronous OUT endpoints only.
116576  *
116577  * This is the data PID received in the last packet for this endpoint.
116578  *
116579  * 2'b00: DATA0
116580  *
116581  * 2'b01: DATA2
116582  *
116583  * 2'b10: DATA1
116584  *
116585  * 2'b11: MDATA
116586  *
116587  * SETUP Packet Count (SUPCnt)
116588  *
116589  * Applies to control OUT Endpoints only.
116590  *
116591  * This field specifies the number of back-to-back SETUP data
116592  *
116593  * packets the endpoint can receive.
116594  *
116595  * 2'b01: 1 packet
116596  *
116597  * 2'b10: 2 packets
116598  *
116599  * 2'b11: 3 packets
116600  *
116601  * Field Enumeration Values:
116602  *
116603  * Enum | Value | Description
116604  * :-----------------------------------------|:------|:-------------------
116605  * ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA0 | 0x0 | DATA0
116606  * ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
116607  * ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
116608  * ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
116609  *
116610  * Field Access Macros:
116611  *
116612  */
116613 /*
116614  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID
116615  *
116616  * DATA0
116617  */
116618 #define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA0 0x0
116619 /*
116620  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID
116621  *
116622  * DATA2 or 1 packet
116623  */
116624 #define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA2PKT1 0x1
116625 /*
116626  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID
116627  *
116628  * DATA1 or 2 packets
116629  */
116630 #define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA1PKT2 0x2
116631 /*
116632  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID
116633  *
116634  * MDATA or 3 packets
116635  */
116636 #define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_MDATAPKT3 0x3
116637 
116638 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */
116639 #define ALT_USB_DEV_DOEPTSIZ5_RXDPID_LSB 29
116640 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */
116641 #define ALT_USB_DEV_DOEPTSIZ5_RXDPID_MSB 30
116642 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */
116643 #define ALT_USB_DEV_DOEPTSIZ5_RXDPID_WIDTH 2
116644 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field value. */
116645 #define ALT_USB_DEV_DOEPTSIZ5_RXDPID_SET_MSK 0x60000000
116646 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field value. */
116647 #define ALT_USB_DEV_DOEPTSIZ5_RXDPID_CLR_MSK 0x9fffffff
116648 /* The reset value of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */
116649 #define ALT_USB_DEV_DOEPTSIZ5_RXDPID_RESET 0x0
116650 /* Extracts the ALT_USB_DEV_DOEPTSIZ5_RXDPID field value from a register. */
116651 #define ALT_USB_DEV_DOEPTSIZ5_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
116652 /* Produces a ALT_USB_DEV_DOEPTSIZ5_RXDPID register field value suitable for setting the register. */
116653 #define ALT_USB_DEV_DOEPTSIZ5_RXDPID_SET(value) (((value) << 29) & 0x60000000)
116654 
116655 #ifndef __ASSEMBLY__
116656 /*
116657  * WARNING: The C register and register group struct declarations are provided for
116658  * convenience and illustrative purposes. They should, however, be used with
116659  * caution as the C language standard provides no guarantees about the alignment or
116660  * atomicity of device memory accesses. The recommended practice for writing
116661  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
116662  * alt_write_word() functions.
116663  *
116664  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ5.
116665  */
116666 struct ALT_USB_DEV_DOEPTSIZ5_s
116667 {
116668  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ5_XFERSIZE */
116669  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ5_PKTCNT */
116670  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ5_RXDPID */
116671  uint32_t : 1; /* *UNDEFINED* */
116672 };
116673 
116674 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ5. */
116675 typedef volatile struct ALT_USB_DEV_DOEPTSIZ5_s ALT_USB_DEV_DOEPTSIZ5_t;
116676 #endif /* __ASSEMBLY__ */
116677 
116678 /* The reset value of the ALT_USB_DEV_DOEPTSIZ5 register. */
116679 #define ALT_USB_DEV_DOEPTSIZ5_RESET 0x00000000
116680 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ5 register from the beginning of the component. */
116681 #define ALT_USB_DEV_DOEPTSIZ5_OFST 0x3b0
116682 /* The address of the ALT_USB_DEV_DOEPTSIZ5 register. */
116683 #define ALT_USB_DEV_DOEPTSIZ5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ5_OFST))
116684 
116685 /*
116686  * Register : doepdma5
116687  *
116688  * Device OUT Endpoint 5 DMA Address Register
116689  *
116690  * Register Layout
116691  *
116692  * Bits | Access | Reset | Description
116693  * :-------|:-------|:--------|:------------------------------
116694  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA5_DOEPDMA5
116695  *
116696  */
116697 /*
116698  * Field : doepdma5
116699  *
116700  * Holds the start address of the external memory for storing or fetching endpoint
116701  *
116702  * data.
116703  *
116704  * Note: For control endpoints, this field stores control OUT data packets as well
116705  * as
116706  *
116707  * SETUP transaction data packets. When more than three SETUP packets are
116708  *
116709  * received back-to-back, the SETUP data packet in the memory is overwritten.
116710  *
116711  * This register is incremented on every AHB transaction. The application can give
116712  *
116713  * only a DWORD-aligned address.
116714  *
116715  * When Scatter/Gather DMA mode is not enabled, the application programs the
116716  *
116717  * start address value in this field.
116718  *
116719  * When Scatter/Gather DMA mode is enabled, this field indicates the base
116720  *
116721  * pointer for the descriptor list.
116722  *
116723  * Field Access Macros:
116724  *
116725  */
116726 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field. */
116727 #define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_LSB 0
116728 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field. */
116729 #define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_MSB 31
116730 /* The width in bits of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field. */
116731 #define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_WIDTH 32
116732 /* The mask used to set the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field value. */
116733 #define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_SET_MSK 0xffffffff
116734 /* The mask used to clear the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field value. */
116735 #define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_CLR_MSK 0x00000000
116736 /* The reset value of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field is UNKNOWN. */
116737 #define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_RESET 0x0
116738 /* Extracts the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 field value from a register. */
116739 #define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_GET(value) (((value) & 0xffffffff) >> 0)
116740 /* Produces a ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field value suitable for setting the register. */
116741 #define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_SET(value) (((value) << 0) & 0xffffffff)
116742 
116743 #ifndef __ASSEMBLY__
116744 /*
116745  * WARNING: The C register and register group struct declarations are provided for
116746  * convenience and illustrative purposes. They should, however, be used with
116747  * caution as the C language standard provides no guarantees about the alignment or
116748  * atomicity of device memory accesses. The recommended practice for writing
116749  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
116750  * alt_write_word() functions.
116751  *
116752  * The struct declaration for register ALT_USB_DEV_DOEPDMA5.
116753  */
116754 struct ALT_USB_DEV_DOEPDMA5_s
116755 {
116756  uint32_t doepdma5 : 32; /* ALT_USB_DEV_DOEPDMA5_DOEPDMA5 */
116757 };
116758 
116759 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA5. */
116760 typedef volatile struct ALT_USB_DEV_DOEPDMA5_s ALT_USB_DEV_DOEPDMA5_t;
116761 #endif /* __ASSEMBLY__ */
116762 
116763 /* The reset value of the ALT_USB_DEV_DOEPDMA5 register. */
116764 #define ALT_USB_DEV_DOEPDMA5_RESET 0x00000000
116765 /* The byte offset of the ALT_USB_DEV_DOEPDMA5 register from the beginning of the component. */
116766 #define ALT_USB_DEV_DOEPDMA5_OFST 0x3b4
116767 /* The address of the ALT_USB_DEV_DOEPDMA5 register. */
116768 #define ALT_USB_DEV_DOEPDMA5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA5_OFST))
116769 
116770 /*
116771  * Register : doepdmab5
116772  *
116773  * Device OUT Endpoint 5 Buffer Address Register
116774  *
116775  * Register Layout
116776  *
116777  * Bits | Access | Reset | Description
116778  * :-------|:-------|:--------|:--------------------------------
116779  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5
116780  *
116781  */
116782 /*
116783  * Field : doepdmab5
116784  *
116785  * Holds the current buffer address.This register is updated as and when the data
116786  *
116787  * transfer for the corresponding end point is in progress.
116788  *
116789  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
116790  * is
116791  *
116792  * reserved.
116793  *
116794  * Field Access Macros:
116795  *
116796  */
116797 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field. */
116798 #define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_LSB 0
116799 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field. */
116800 #define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_MSB 31
116801 /* The width in bits of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field. */
116802 #define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_WIDTH 32
116803 /* The mask used to set the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field value. */
116804 #define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_SET_MSK 0xffffffff
116805 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field value. */
116806 #define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_CLR_MSK 0x00000000
116807 /* The reset value of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field is UNKNOWN. */
116808 #define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_RESET 0x0
116809 /* Extracts the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 field value from a register. */
116810 #define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_GET(value) (((value) & 0xffffffff) >> 0)
116811 /* Produces a ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field value suitable for setting the register. */
116812 #define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_SET(value) (((value) << 0) & 0xffffffff)
116813 
116814 #ifndef __ASSEMBLY__
116815 /*
116816  * WARNING: The C register and register group struct declarations are provided for
116817  * convenience and illustrative purposes. They should, however, be used with
116818  * caution as the C language standard provides no guarantees about the alignment or
116819  * atomicity of device memory accesses. The recommended practice for writing
116820  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
116821  * alt_write_word() functions.
116822  *
116823  * The struct declaration for register ALT_USB_DEV_DOEPDMAB5.
116824  */
116825 struct ALT_USB_DEV_DOEPDMAB5_s
116826 {
116827  const uint32_t doepdmab5 : 32; /* ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 */
116828 };
116829 
116830 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB5. */
116831 typedef volatile struct ALT_USB_DEV_DOEPDMAB5_s ALT_USB_DEV_DOEPDMAB5_t;
116832 #endif /* __ASSEMBLY__ */
116833 
116834 /* The reset value of the ALT_USB_DEV_DOEPDMAB5 register. */
116835 #define ALT_USB_DEV_DOEPDMAB5_RESET 0x00000000
116836 /* The byte offset of the ALT_USB_DEV_DOEPDMAB5 register from the beginning of the component. */
116837 #define ALT_USB_DEV_DOEPDMAB5_OFST 0x3bc
116838 /* The address of the ALT_USB_DEV_DOEPDMAB5 register. */
116839 #define ALT_USB_DEV_DOEPDMAB5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB5_OFST))
116840 
116841 /*
116842  * Register : doepctl6
116843  *
116844  * Device Control OUT Endpoint 6 Control Register
116845  *
116846  * Register Layout
116847  *
116848  * Bits | Access | Reset | Description
116849  * :--------|:---------|:------|:------------------------------
116850  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL6_MPS
116851  * [14:11] | ??? | 0x0 | *UNDEFINED*
116852  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL6_USBACTEP
116853  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL6_DPID
116854  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL6_NAKSTS
116855  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL6_EPTYPE
116856  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL6_SNP
116857  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL6_STALL
116858  * [25:22] | ??? | 0x0 | *UNDEFINED*
116859  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL6_CNAK
116860  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL6_SNAK
116861  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL6_SETD0PID
116862  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL6_SETD1PID
116863  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL6_EPDIS
116864  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL6_EPENA
116865  *
116866  */
116867 /*
116868  * Field : mps
116869  *
116870  * Maximum Packet Size (MPS)
116871  *
116872  * The application must program this field with the maximum packet size for the
116873  * current
116874  *
116875  * logical endpoint. This value is in bytes.
116876  *
116877  * Field Access Macros:
116878  *
116879  */
116880 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_MPS register field. */
116881 #define ALT_USB_DEV_DOEPCTL6_MPS_LSB 0
116882 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_MPS register field. */
116883 #define ALT_USB_DEV_DOEPCTL6_MPS_MSB 10
116884 /* The width in bits of the ALT_USB_DEV_DOEPCTL6_MPS register field. */
116885 #define ALT_USB_DEV_DOEPCTL6_MPS_WIDTH 11
116886 /* The mask used to set the ALT_USB_DEV_DOEPCTL6_MPS register field value. */
116887 #define ALT_USB_DEV_DOEPCTL6_MPS_SET_MSK 0x000007ff
116888 /* The mask used to clear the ALT_USB_DEV_DOEPCTL6_MPS register field value. */
116889 #define ALT_USB_DEV_DOEPCTL6_MPS_CLR_MSK 0xfffff800
116890 /* The reset value of the ALT_USB_DEV_DOEPCTL6_MPS register field. */
116891 #define ALT_USB_DEV_DOEPCTL6_MPS_RESET 0x0
116892 /* Extracts the ALT_USB_DEV_DOEPCTL6_MPS field value from a register. */
116893 #define ALT_USB_DEV_DOEPCTL6_MPS_GET(value) (((value) & 0x000007ff) >> 0)
116894 /* Produces a ALT_USB_DEV_DOEPCTL6_MPS register field value suitable for setting the register. */
116895 #define ALT_USB_DEV_DOEPCTL6_MPS_SET(value) (((value) << 0) & 0x000007ff)
116896 
116897 /*
116898  * Field : usbactep
116899  *
116900  * USB Active Endpoint (USBActEP)
116901  *
116902  * Indicates whether this endpoint is active in the current configuration and
116903  * interface. The
116904  *
116905  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
116906  * reset. After
116907  *
116908  * receiving the SetConfiguration and SetInterface commands, the application must
116909  *
116910  * program endpoint registers accordingly and set this bit.
116911  *
116912  * Field Enumeration Values:
116913  *
116914  * Enum | Value | Description
116915  * :-------------------------------------|:------|:--------------------
116916  * ALT_USB_DEV_DOEPCTL6_USBACTEP_E_DISD | 0x0 | Not Active
116917  * ALT_USB_DEV_DOEPCTL6_USBACTEP_E_END | 0x1 | USB Active Endpoint
116918  *
116919  * Field Access Macros:
116920  *
116921  */
116922 /*
116923  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_USBACTEP
116924  *
116925  * Not Active
116926  */
116927 #define ALT_USB_DEV_DOEPCTL6_USBACTEP_E_DISD 0x0
116928 /*
116929  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_USBACTEP
116930  *
116931  * USB Active Endpoint
116932  */
116933 #define ALT_USB_DEV_DOEPCTL6_USBACTEP_E_END 0x1
116934 
116935 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */
116936 #define ALT_USB_DEV_DOEPCTL6_USBACTEP_LSB 15
116937 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */
116938 #define ALT_USB_DEV_DOEPCTL6_USBACTEP_MSB 15
116939 /* The width in bits of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */
116940 #define ALT_USB_DEV_DOEPCTL6_USBACTEP_WIDTH 1
116941 /* The mask used to set the ALT_USB_DEV_DOEPCTL6_USBACTEP register field value. */
116942 #define ALT_USB_DEV_DOEPCTL6_USBACTEP_SET_MSK 0x00008000
116943 /* The mask used to clear the ALT_USB_DEV_DOEPCTL6_USBACTEP register field value. */
116944 #define ALT_USB_DEV_DOEPCTL6_USBACTEP_CLR_MSK 0xffff7fff
116945 /* The reset value of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */
116946 #define ALT_USB_DEV_DOEPCTL6_USBACTEP_RESET 0x0
116947 /* Extracts the ALT_USB_DEV_DOEPCTL6_USBACTEP field value from a register. */
116948 #define ALT_USB_DEV_DOEPCTL6_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
116949 /* Produces a ALT_USB_DEV_DOEPCTL6_USBACTEP register field value suitable for setting the register. */
116950 #define ALT_USB_DEV_DOEPCTL6_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
116951 
116952 /*
116953  * Field : dpid
116954  *
116955  * Endpoint Data PID (DPID)
116956  *
116957  * Applies to interrupt/bulk IN and OUT endpoints only.
116958  *
116959  * Contains the PID of the packet to be received or transmitted on this endpoint.
116960  * The
116961  *
116962  * application must program the PID of the first packet to be received or
116963  * transmitted on
116964  *
116965  * this endpoint, after the endpoint is activated. The applications use the
116966  * SetD1PID and
116967  *
116968  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
116969  *
116970  * 1'b0: DATA0
116971  *
116972  * 1'b1: DATA1
116973  *
116974  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
116975  *
116976  * DMA mode.
116977  *
116978  * 1'b0 RO
116979  *
116980  * Even/Odd (Micro)Frame (EO_FrNum)
116981  *
116982  * In non-Scatter/Gather DMA mode:
116983  *
116984  * Applies to isochronous IN and OUT endpoints only.
116985  *
116986  * Indicates the (micro)frame number in which the core transmits/receives
116987  * isochronous
116988  *
116989  * data for this endpoint. The application must program the even/odd (micro) frame
116990  *
116991  * number in which it intends to transmit/receive isochronous data for this
116992  * endpoint using
116993  *
116994  * the SetEvnFr and SetOddFr fields in this register.
116995  *
116996  * 1'b0: Even (micro)frame
116997  *
116998  * 1'b1: Odd (micro)frame
116999  *
117000  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
117001  * number
117002  *
117003  * in which to send data is provided in the transmit descriptor structure. The
117004  * frame in
117005  *
117006  * which data is received is updated in receive descriptor structure.
117007  *
117008  * Field Enumeration Values:
117009  *
117010  * Enum | Value | Description
117011  * :----------------------------------|:------|:-----------------------------
117012  * ALT_USB_DEV_DOEPCTL6_DPID_E_INACT | 0x0 | Endpoint Data PID not active
117013  * ALT_USB_DEV_DOEPCTL6_DPID_E_ACT | 0x1 | Endpoint Data PID active
117014  *
117015  * Field Access Macros:
117016  *
117017  */
117018 /*
117019  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_DPID
117020  *
117021  * Endpoint Data PID not active
117022  */
117023 #define ALT_USB_DEV_DOEPCTL6_DPID_E_INACT 0x0
117024 /*
117025  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_DPID
117026  *
117027  * Endpoint Data PID active
117028  */
117029 #define ALT_USB_DEV_DOEPCTL6_DPID_E_ACT 0x1
117030 
117031 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_DPID register field. */
117032 #define ALT_USB_DEV_DOEPCTL6_DPID_LSB 16
117033 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_DPID register field. */
117034 #define ALT_USB_DEV_DOEPCTL6_DPID_MSB 16
117035 /* The width in bits of the ALT_USB_DEV_DOEPCTL6_DPID register field. */
117036 #define ALT_USB_DEV_DOEPCTL6_DPID_WIDTH 1
117037 /* The mask used to set the ALT_USB_DEV_DOEPCTL6_DPID register field value. */
117038 #define ALT_USB_DEV_DOEPCTL6_DPID_SET_MSK 0x00010000
117039 /* The mask used to clear the ALT_USB_DEV_DOEPCTL6_DPID register field value. */
117040 #define ALT_USB_DEV_DOEPCTL6_DPID_CLR_MSK 0xfffeffff
117041 /* The reset value of the ALT_USB_DEV_DOEPCTL6_DPID register field. */
117042 #define ALT_USB_DEV_DOEPCTL6_DPID_RESET 0x0
117043 /* Extracts the ALT_USB_DEV_DOEPCTL6_DPID field value from a register. */
117044 #define ALT_USB_DEV_DOEPCTL6_DPID_GET(value) (((value) & 0x00010000) >> 16)
117045 /* Produces a ALT_USB_DEV_DOEPCTL6_DPID register field value suitable for setting the register. */
117046 #define ALT_USB_DEV_DOEPCTL6_DPID_SET(value) (((value) << 16) & 0x00010000)
117047 
117048 /*
117049  * Field : naksts
117050  *
117051  * NAK Status (NAKSts)
117052  *
117053  * Indicates the following:
117054  *
117055  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
117056  *
117057  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
117058  *
117059  * When either the application or the core sets this bit:
117060  *
117061  * The core stops receiving any data on an OUT endpoint, even if there is space in
117062  *
117063  * the RxFIFO to accommodate the incoming packet.
117064  *
117065  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
117066  *
117067  * endpoint, even if there data is available in the TxFIFO.
117068  *
117069  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
117070  *
117071  * if there data is available in the TxFIFO.
117072  *
117073  * Irrespective of this bit's setting, the core always responds to SETUP data
117074  * packets with
117075  *
117076  * an ACK handshake.
117077  *
117078  * Field Enumeration Values:
117079  *
117080  * Enum | Value | Description
117081  * :-------------------------------------|:------|:------------------------------------------------
117082  * ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
117083  * : | | based on the FIFO status
117084  * ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
117085  * : | | endpoint
117086  *
117087  * Field Access Macros:
117088  *
117089  */
117090 /*
117091  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_NAKSTS
117092  *
117093  * The core is transmitting non-NAK handshakes based on the FIFO status
117094  */
117095 #define ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NONNAK 0x0
117096 /*
117097  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_NAKSTS
117098  *
117099  * The core is transmitting NAK handshakes on this endpoint
117100  */
117101 #define ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NAK 0x1
117102 
117103 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */
117104 #define ALT_USB_DEV_DOEPCTL6_NAKSTS_LSB 17
117105 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */
117106 #define ALT_USB_DEV_DOEPCTL6_NAKSTS_MSB 17
117107 /* The width in bits of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */
117108 #define ALT_USB_DEV_DOEPCTL6_NAKSTS_WIDTH 1
117109 /* The mask used to set the ALT_USB_DEV_DOEPCTL6_NAKSTS register field value. */
117110 #define ALT_USB_DEV_DOEPCTL6_NAKSTS_SET_MSK 0x00020000
117111 /* The mask used to clear the ALT_USB_DEV_DOEPCTL6_NAKSTS register field value. */
117112 #define ALT_USB_DEV_DOEPCTL6_NAKSTS_CLR_MSK 0xfffdffff
117113 /* The reset value of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */
117114 #define ALT_USB_DEV_DOEPCTL6_NAKSTS_RESET 0x0
117115 /* Extracts the ALT_USB_DEV_DOEPCTL6_NAKSTS field value from a register. */
117116 #define ALT_USB_DEV_DOEPCTL6_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
117117 /* Produces a ALT_USB_DEV_DOEPCTL6_NAKSTS register field value suitable for setting the register. */
117118 #define ALT_USB_DEV_DOEPCTL6_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
117119 
117120 /*
117121  * Field : eptype
117122  *
117123  * Endpoint Type (EPType)
117124  *
117125  * This is the transfer type supported by this logical endpoint.
117126  *
117127  * 2'b00: Control
117128  *
117129  * 2'b01: Isochronous
117130  *
117131  * 2'b10: Bulk
117132  *
117133  * 2'b11: Interrupt
117134  *
117135  * Field Enumeration Values:
117136  *
117137  * Enum | Value | Description
117138  * :------------------------------------------|:------|:------------
117139  * ALT_USB_DEV_DOEPCTL6_EPTYPE_E_CTL | 0x0 | Control
117140  * ALT_USB_DEV_DOEPCTL6_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
117141  * ALT_USB_DEV_DOEPCTL6_EPTYPE_E_BULK | 0x2 | Bulk
117142  * ALT_USB_DEV_DOEPCTL6_EPTYPE_E_INTERRUP | 0x3 | Interrupt
117143  *
117144  * Field Access Macros:
117145  *
117146  */
117147 /*
117148  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE
117149  *
117150  * Control
117151  */
117152 #define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_CTL 0x0
117153 /*
117154  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE
117155  *
117156  * Isochronous
117157  */
117158 #define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_ISOCHRONOUS 0x1
117159 /*
117160  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE
117161  *
117162  * Bulk
117163  */
117164 #define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_BULK 0x2
117165 /*
117166  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE
117167  *
117168  * Interrupt
117169  */
117170 #define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_INTERRUP 0x3
117171 
117172 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */
117173 #define ALT_USB_DEV_DOEPCTL6_EPTYPE_LSB 18
117174 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */
117175 #define ALT_USB_DEV_DOEPCTL6_EPTYPE_MSB 19
117176 /* The width in bits of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */
117177 #define ALT_USB_DEV_DOEPCTL6_EPTYPE_WIDTH 2
117178 /* The mask used to set the ALT_USB_DEV_DOEPCTL6_EPTYPE register field value. */
117179 #define ALT_USB_DEV_DOEPCTL6_EPTYPE_SET_MSK 0x000c0000
117180 /* The mask used to clear the ALT_USB_DEV_DOEPCTL6_EPTYPE register field value. */
117181 #define ALT_USB_DEV_DOEPCTL6_EPTYPE_CLR_MSK 0xfff3ffff
117182 /* The reset value of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */
117183 #define ALT_USB_DEV_DOEPCTL6_EPTYPE_RESET 0x0
117184 /* Extracts the ALT_USB_DEV_DOEPCTL6_EPTYPE field value from a register. */
117185 #define ALT_USB_DEV_DOEPCTL6_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
117186 /* Produces a ALT_USB_DEV_DOEPCTL6_EPTYPE register field value suitable for setting the register. */
117187 #define ALT_USB_DEV_DOEPCTL6_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
117188 
117189 /*
117190  * Field : snp
117191  *
117192  * Snoop Mode (Snp)
117193  *
117194  * Applies to OUT endpoints only.
117195  *
117196  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
117197  *
117198  * check the correctness of OUT packets before transferring them to application
117199  * memory.
117200  *
117201  * Field Enumeration Values:
117202  *
117203  * Enum | Value | Description
117204  * :-------------------------------|:------|:-------------------
117205  * ALT_USB_DEV_DOEPCTL6_SNP_E_DIS | 0x0 | Disable Snoop Mode
117206  * ALT_USB_DEV_DOEPCTL6_SNP_E_EN | 0x1 | Enable Snoop Mode
117207  *
117208  * Field Access Macros:
117209  *
117210  */
117211 /*
117212  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNP
117213  *
117214  * Disable Snoop Mode
117215  */
117216 #define ALT_USB_DEV_DOEPCTL6_SNP_E_DIS 0x0
117217 /*
117218  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNP
117219  *
117220  * Enable Snoop Mode
117221  */
117222 #define ALT_USB_DEV_DOEPCTL6_SNP_E_EN 0x1
117223 
117224 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SNP register field. */
117225 #define ALT_USB_DEV_DOEPCTL6_SNP_LSB 20
117226 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SNP register field. */
117227 #define ALT_USB_DEV_DOEPCTL6_SNP_MSB 20
117228 /* The width in bits of the ALT_USB_DEV_DOEPCTL6_SNP register field. */
117229 #define ALT_USB_DEV_DOEPCTL6_SNP_WIDTH 1
117230 /* The mask used to set the ALT_USB_DEV_DOEPCTL6_SNP register field value. */
117231 #define ALT_USB_DEV_DOEPCTL6_SNP_SET_MSK 0x00100000
117232 /* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SNP register field value. */
117233 #define ALT_USB_DEV_DOEPCTL6_SNP_CLR_MSK 0xffefffff
117234 /* The reset value of the ALT_USB_DEV_DOEPCTL6_SNP register field. */
117235 #define ALT_USB_DEV_DOEPCTL6_SNP_RESET 0x0
117236 /* Extracts the ALT_USB_DEV_DOEPCTL6_SNP field value from a register. */
117237 #define ALT_USB_DEV_DOEPCTL6_SNP_GET(value) (((value) & 0x00100000) >> 20)
117238 /* Produces a ALT_USB_DEV_DOEPCTL6_SNP register field value suitable for setting the register. */
117239 #define ALT_USB_DEV_DOEPCTL6_SNP_SET(value) (((value) << 20) & 0x00100000)
117240 
117241 /*
117242  * Field : stall
117243  *
117244  * STALL Handshake (Stall)
117245  *
117246  * Applies to non-control, non-isochronous IN and OUT endpoints only.
117247  *
117248  * The application sets this bit to stall all tokens from the USB host to this
117249  * endpoint. If a
117250  *
117251  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
117252  * bit, the
117253  *
117254  * STALL bit takes priority. Only the application can clear this bit, never the
117255  * core.
117256  *
117257  * 1'b0 R_W
117258  *
117259  * Applies to control endpoints only.
117260  *
117261  * The application can only set this bit, and the core clears it, when a SETUP
117262  * token is
117263  *
117264  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
117265  * OUT
117266  *
117267  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
117268  * this bit's
117269  *
117270  * setting, the core always responds to SETUP data packets with an ACK handshake.
117271  *
117272  * Field Enumeration Values:
117273  *
117274  * Enum | Value | Description
117275  * :-----------------------------------|:------|:----------------------------
117276  * ALT_USB_DEV_DOEPCTL6_STALL_E_INACT | 0x0 | STALL All Tokens not active
117277  * ALT_USB_DEV_DOEPCTL6_STALL_E_ACT | 0x1 | STALL All Tokens active
117278  *
117279  * Field Access Macros:
117280  *
117281  */
117282 /*
117283  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_STALL
117284  *
117285  * STALL All Tokens not active
117286  */
117287 #define ALT_USB_DEV_DOEPCTL6_STALL_E_INACT 0x0
117288 /*
117289  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_STALL
117290  *
117291  * STALL All Tokens active
117292  */
117293 #define ALT_USB_DEV_DOEPCTL6_STALL_E_ACT 0x1
117294 
117295 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_STALL register field. */
117296 #define ALT_USB_DEV_DOEPCTL6_STALL_LSB 21
117297 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_STALL register field. */
117298 #define ALT_USB_DEV_DOEPCTL6_STALL_MSB 21
117299 /* The width in bits of the ALT_USB_DEV_DOEPCTL6_STALL register field. */
117300 #define ALT_USB_DEV_DOEPCTL6_STALL_WIDTH 1
117301 /* The mask used to set the ALT_USB_DEV_DOEPCTL6_STALL register field value. */
117302 #define ALT_USB_DEV_DOEPCTL6_STALL_SET_MSK 0x00200000
117303 /* The mask used to clear the ALT_USB_DEV_DOEPCTL6_STALL register field value. */
117304 #define ALT_USB_DEV_DOEPCTL6_STALL_CLR_MSK 0xffdfffff
117305 /* The reset value of the ALT_USB_DEV_DOEPCTL6_STALL register field. */
117306 #define ALT_USB_DEV_DOEPCTL6_STALL_RESET 0x0
117307 /* Extracts the ALT_USB_DEV_DOEPCTL6_STALL field value from a register. */
117308 #define ALT_USB_DEV_DOEPCTL6_STALL_GET(value) (((value) & 0x00200000) >> 21)
117309 /* Produces a ALT_USB_DEV_DOEPCTL6_STALL register field value suitable for setting the register. */
117310 #define ALT_USB_DEV_DOEPCTL6_STALL_SET(value) (((value) << 21) & 0x00200000)
117311 
117312 /*
117313  * Field : cnak
117314  *
117315  * Clear NAK (CNAK)
117316  *
117317  * A write to this bit clears the NAK bit For the endpoint.
117318  *
117319  * Field Enumeration Values:
117320  *
117321  * Enum | Value | Description
117322  * :----------------------------------|:------|:-------------
117323  * ALT_USB_DEV_DOEPCTL6_CNAK_E_INACT | 0x0 | No Clear NAK
117324  * ALT_USB_DEV_DOEPCTL6_CNAK_E_ACT | 0x1 | Clear NAK
117325  *
117326  * Field Access Macros:
117327  *
117328  */
117329 /*
117330  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_CNAK
117331  *
117332  * No Clear NAK
117333  */
117334 #define ALT_USB_DEV_DOEPCTL6_CNAK_E_INACT 0x0
117335 /*
117336  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_CNAK
117337  *
117338  * Clear NAK
117339  */
117340 #define ALT_USB_DEV_DOEPCTL6_CNAK_E_ACT 0x1
117341 
117342 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */
117343 #define ALT_USB_DEV_DOEPCTL6_CNAK_LSB 26
117344 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */
117345 #define ALT_USB_DEV_DOEPCTL6_CNAK_MSB 26
117346 /* The width in bits of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */
117347 #define ALT_USB_DEV_DOEPCTL6_CNAK_WIDTH 1
117348 /* The mask used to set the ALT_USB_DEV_DOEPCTL6_CNAK register field value. */
117349 #define ALT_USB_DEV_DOEPCTL6_CNAK_SET_MSK 0x04000000
117350 /* The mask used to clear the ALT_USB_DEV_DOEPCTL6_CNAK register field value. */
117351 #define ALT_USB_DEV_DOEPCTL6_CNAK_CLR_MSK 0xfbffffff
117352 /* The reset value of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */
117353 #define ALT_USB_DEV_DOEPCTL6_CNAK_RESET 0x0
117354 /* Extracts the ALT_USB_DEV_DOEPCTL6_CNAK field value from a register. */
117355 #define ALT_USB_DEV_DOEPCTL6_CNAK_GET(value) (((value) & 0x04000000) >> 26)
117356 /* Produces a ALT_USB_DEV_DOEPCTL6_CNAK register field value suitable for setting the register. */
117357 #define ALT_USB_DEV_DOEPCTL6_CNAK_SET(value) (((value) << 26) & 0x04000000)
117358 
117359 /*
117360  * Field : snak
117361  *
117362  * Set NAK (SNAK)
117363  *
117364  * A write to this bit sets the NAK bit For the endpoint.
117365  *
117366  * Using this bit, the application can control the transmission of NAK
117367  *
117368  * handshakes on an endpoint. The core can also Set this bit For an
117369  *
117370  * endpoint after a SETUP packet is received on that endpoint.
117371  *
117372  * Field Enumeration Values:
117373  *
117374  * Enum | Value | Description
117375  * :----------------------------------|:------|:------------
117376  * ALT_USB_DEV_DOEPCTL6_SNAK_E_INACT | 0x0 | No Set NAK
117377  * ALT_USB_DEV_DOEPCTL6_SNAK_E_ACT | 0x1 | Set NAK
117378  *
117379  * Field Access Macros:
117380  *
117381  */
117382 /*
117383  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNAK
117384  *
117385  * No Set NAK
117386  */
117387 #define ALT_USB_DEV_DOEPCTL6_SNAK_E_INACT 0x0
117388 /*
117389  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNAK
117390  *
117391  * Set NAK
117392  */
117393 #define ALT_USB_DEV_DOEPCTL6_SNAK_E_ACT 0x1
117394 
117395 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */
117396 #define ALT_USB_DEV_DOEPCTL6_SNAK_LSB 27
117397 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */
117398 #define ALT_USB_DEV_DOEPCTL6_SNAK_MSB 27
117399 /* The width in bits of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */
117400 #define ALT_USB_DEV_DOEPCTL6_SNAK_WIDTH 1
117401 /* The mask used to set the ALT_USB_DEV_DOEPCTL6_SNAK register field value. */
117402 #define ALT_USB_DEV_DOEPCTL6_SNAK_SET_MSK 0x08000000
117403 /* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SNAK register field value. */
117404 #define ALT_USB_DEV_DOEPCTL6_SNAK_CLR_MSK 0xf7ffffff
117405 /* The reset value of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */
117406 #define ALT_USB_DEV_DOEPCTL6_SNAK_RESET 0x0
117407 /* Extracts the ALT_USB_DEV_DOEPCTL6_SNAK field value from a register. */
117408 #define ALT_USB_DEV_DOEPCTL6_SNAK_GET(value) (((value) & 0x08000000) >> 27)
117409 /* Produces a ALT_USB_DEV_DOEPCTL6_SNAK register field value suitable for setting the register. */
117410 #define ALT_USB_DEV_DOEPCTL6_SNAK_SET(value) (((value) << 27) & 0x08000000)
117411 
117412 /*
117413  * Field : setd0pid
117414  *
117415  * Set DATA0 PID (SetD0PID)
117416  *
117417  * Applies to interrupt/bulk IN and OUT endpoints only.
117418  *
117419  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
117420  * to DATA0.
117421  *
117422  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
117423  *
117424  * DMA mode.
117425  *
117426  * 1'b0 WO
117427  *
117428  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
117429  *
117430  * Applies to isochronous IN and OUT endpoints only.
117431  *
117432  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
117433  * (micro)
117434  *
117435  * frame.
117436  *
117437  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
117438  * number
117439  *
117440  * in which to send data is in the transmit descriptor structure. The frame in
117441  * which to
117442  *
117443  * receive data is updated in receive descriptor structure.
117444  *
117445  * Field Enumeration Values:
117446  *
117447  * Enum | Value | Description
117448  * :-------------------------------------|:------|:------------------------------------
117449  * ALT_USB_DEV_DOEPCTL6_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
117450  * ALT_USB_DEV_DOEPCTL6_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
117451  *
117452  * Field Access Macros:
117453  *
117454  */
117455 /*
117456  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD0PID
117457  *
117458  * Disables Set DATA0 PID
117459  */
117460 #define ALT_USB_DEV_DOEPCTL6_SETD0PID_E_DISD 0x0
117461 /*
117462  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD0PID
117463  *
117464  * Enables Endpoint Data PID to DATA0)
117465  */
117466 #define ALT_USB_DEV_DOEPCTL6_SETD0PID_E_END 0x1
117467 
117468 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */
117469 #define ALT_USB_DEV_DOEPCTL6_SETD0PID_LSB 28
117470 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */
117471 #define ALT_USB_DEV_DOEPCTL6_SETD0PID_MSB 28
117472 /* The width in bits of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */
117473 #define ALT_USB_DEV_DOEPCTL6_SETD0PID_WIDTH 1
117474 /* The mask used to set the ALT_USB_DEV_DOEPCTL6_SETD0PID register field value. */
117475 #define ALT_USB_DEV_DOEPCTL6_SETD0PID_SET_MSK 0x10000000
117476 /* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SETD0PID register field value. */
117477 #define ALT_USB_DEV_DOEPCTL6_SETD0PID_CLR_MSK 0xefffffff
117478 /* The reset value of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */
117479 #define ALT_USB_DEV_DOEPCTL6_SETD0PID_RESET 0x0
117480 /* Extracts the ALT_USB_DEV_DOEPCTL6_SETD0PID field value from a register. */
117481 #define ALT_USB_DEV_DOEPCTL6_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
117482 /* Produces a ALT_USB_DEV_DOEPCTL6_SETD0PID register field value suitable for setting the register. */
117483 #define ALT_USB_DEV_DOEPCTL6_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
117484 
117485 /*
117486  * Field : setd1pid
117487  *
117488  * Set DATA1 PID (SetD1PID)
117489  *
117490  * Applies to interrupt/bulk IN and OUT endpoints only.
117491  *
117492  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
117493  * to DATA1.
117494  *
117495  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
117496  *
117497  * DMA mode.
117498  *
117499  * Set Odd (micro)frame (SetOddFr)
117500  *
117501  * Applies to isochronous IN and OUT endpoints only.
117502  *
117503  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
117504  *
117505  * (micro)frame.
117506  *
117507  * This field is not applicable for Scatter/Gather DMA mode.
117508  *
117509  * Field Enumeration Values:
117510  *
117511  * Enum | Value | Description
117512  * :-------------------------------------|:------|:-----------------------
117513  * ALT_USB_DEV_DOEPCTL6_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
117514  * ALT_USB_DEV_DOEPCTL6_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
117515  *
117516  * Field Access Macros:
117517  *
117518  */
117519 /*
117520  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD1PID
117521  *
117522  * Disables Set DATA1 PID
117523  */
117524 #define ALT_USB_DEV_DOEPCTL6_SETD1PID_E_DISD 0x0
117525 /*
117526  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD1PID
117527  *
117528  * Enables Set DATA1 PID
117529  */
117530 #define ALT_USB_DEV_DOEPCTL6_SETD1PID_E_END 0x1
117531 
117532 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */
117533 #define ALT_USB_DEV_DOEPCTL6_SETD1PID_LSB 29
117534 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */
117535 #define ALT_USB_DEV_DOEPCTL6_SETD1PID_MSB 29
117536 /* The width in bits of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */
117537 #define ALT_USB_DEV_DOEPCTL6_SETD1PID_WIDTH 1
117538 /* The mask used to set the ALT_USB_DEV_DOEPCTL6_SETD1PID register field value. */
117539 #define ALT_USB_DEV_DOEPCTL6_SETD1PID_SET_MSK 0x20000000
117540 /* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SETD1PID register field value. */
117541 #define ALT_USB_DEV_DOEPCTL6_SETD1PID_CLR_MSK 0xdfffffff
117542 /* The reset value of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */
117543 #define ALT_USB_DEV_DOEPCTL6_SETD1PID_RESET 0x0
117544 /* Extracts the ALT_USB_DEV_DOEPCTL6_SETD1PID field value from a register. */
117545 #define ALT_USB_DEV_DOEPCTL6_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
117546 /* Produces a ALT_USB_DEV_DOEPCTL6_SETD1PID register field value suitable for setting the register. */
117547 #define ALT_USB_DEV_DOEPCTL6_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
117548 
117549 /*
117550  * Field : epdis
117551  *
117552  * Endpoint Disable (EPDis)
117553  *
117554  * Applies to IN and OUT endpoints.
117555  *
117556  * The application sets this bit to stop transmitting/receiving data on an
117557  * endpoint, even
117558  *
117559  * before the transfer for that endpoint is complete. The application must wait for
117560  * the
117561  *
117562  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
117563  * clears
117564  *
117565  * this bit before setting the Endpoint Disabled interrupt. The application must
117566  * set this bit
117567  *
117568  * only if Endpoint Enable is already set for this endpoint.
117569  *
117570  * Field Enumeration Values:
117571  *
117572  * Enum | Value | Description
117573  * :-----------------------------------|:------|:--------------------
117574  * ALT_USB_DEV_DOEPCTL6_EPDIS_E_INACT | 0x0 | No Endpoint Disable
117575  * ALT_USB_DEV_DOEPCTL6_EPDIS_E_ACT | 0x1 | Endpoint Disable
117576  *
117577  * Field Access Macros:
117578  *
117579  */
117580 /*
117581  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPDIS
117582  *
117583  * No Endpoint Disable
117584  */
117585 #define ALT_USB_DEV_DOEPCTL6_EPDIS_E_INACT 0x0
117586 /*
117587  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPDIS
117588  *
117589  * Endpoint Disable
117590  */
117591 #define ALT_USB_DEV_DOEPCTL6_EPDIS_E_ACT 0x1
117592 
117593 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */
117594 #define ALT_USB_DEV_DOEPCTL6_EPDIS_LSB 30
117595 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */
117596 #define ALT_USB_DEV_DOEPCTL6_EPDIS_MSB 30
117597 /* The width in bits of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */
117598 #define ALT_USB_DEV_DOEPCTL6_EPDIS_WIDTH 1
117599 /* The mask used to set the ALT_USB_DEV_DOEPCTL6_EPDIS register field value. */
117600 #define ALT_USB_DEV_DOEPCTL6_EPDIS_SET_MSK 0x40000000
117601 /* The mask used to clear the ALT_USB_DEV_DOEPCTL6_EPDIS register field value. */
117602 #define ALT_USB_DEV_DOEPCTL6_EPDIS_CLR_MSK 0xbfffffff
117603 /* The reset value of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */
117604 #define ALT_USB_DEV_DOEPCTL6_EPDIS_RESET 0x0
117605 /* Extracts the ALT_USB_DEV_DOEPCTL6_EPDIS field value from a register. */
117606 #define ALT_USB_DEV_DOEPCTL6_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
117607 /* Produces a ALT_USB_DEV_DOEPCTL6_EPDIS register field value suitable for setting the register. */
117608 #define ALT_USB_DEV_DOEPCTL6_EPDIS_SET(value) (((value) << 30) & 0x40000000)
117609 
117610 /*
117611  * Field : epena
117612  *
117613  * Endpoint Enable (EPEna)
117614  *
117615  * Applies to IN and OUT endpoints.
117616  *
117617  * When Scatter/Gather DMA mode is enabled,
117618  *
117619  * For IN endpoints this bit indicates that the descriptor structure and data
117620  * buffer with
117621  *
117622  * data ready to transmit is setup.
117623  *
117624  * For OUT endpoint it indicates that the descriptor structure and data buffer to
117625  *
117626  * receive data is setup.
117627  *
117628  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
117629  *
117630  * DMA mode:
117631  *
117632  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
117633  * the
117634  *
117635  * endpoint.
117636  *
117637  * * For OUT endpoints, this bit indicates that the application has allocated the
117638  *
117639  * memory to start receiving data from the USB.
117640  *
117641  * * The core clears this bit before setting any of the following interrupts on
117642  * this
117643  *
117644  * endpoint:
117645  *
117646  * SETUP Phase Done
117647  *
117648  * Endpoint Disabled
117649  *
117650  * Transfer Completed
117651  *
117652  * Note: For control endpoints in DMA mode, this bit must be set to be able to
117653  * transfer
117654  *
117655  * SETUP data packets in memory.
117656  *
117657  * Field Enumeration Values:
117658  *
117659  * Enum | Value | Description
117660  * :-----------------------------------|:------|:-------------------------
117661  * ALT_USB_DEV_DOEPCTL6_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
117662  * ALT_USB_DEV_DOEPCTL6_EPENA_E_ACT | 0x1 | Endpoint Enable active
117663  *
117664  * Field Access Macros:
117665  *
117666  */
117667 /*
117668  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPENA
117669  *
117670  * Endpoint Enable inactive
117671  */
117672 #define ALT_USB_DEV_DOEPCTL6_EPENA_E_INACT 0x0
117673 /*
117674  * Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPENA
117675  *
117676  * Endpoint Enable active
117677  */
117678 #define ALT_USB_DEV_DOEPCTL6_EPENA_E_ACT 0x1
117679 
117680 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */
117681 #define ALT_USB_DEV_DOEPCTL6_EPENA_LSB 31
117682 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */
117683 #define ALT_USB_DEV_DOEPCTL6_EPENA_MSB 31
117684 /* The width in bits of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */
117685 #define ALT_USB_DEV_DOEPCTL6_EPENA_WIDTH 1
117686 /* The mask used to set the ALT_USB_DEV_DOEPCTL6_EPENA register field value. */
117687 #define ALT_USB_DEV_DOEPCTL6_EPENA_SET_MSK 0x80000000
117688 /* The mask used to clear the ALT_USB_DEV_DOEPCTL6_EPENA register field value. */
117689 #define ALT_USB_DEV_DOEPCTL6_EPENA_CLR_MSK 0x7fffffff
117690 /* The reset value of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */
117691 #define ALT_USB_DEV_DOEPCTL6_EPENA_RESET 0x0
117692 /* Extracts the ALT_USB_DEV_DOEPCTL6_EPENA field value from a register. */
117693 #define ALT_USB_DEV_DOEPCTL6_EPENA_GET(value) (((value) & 0x80000000) >> 31)
117694 /* Produces a ALT_USB_DEV_DOEPCTL6_EPENA register field value suitable for setting the register. */
117695 #define ALT_USB_DEV_DOEPCTL6_EPENA_SET(value) (((value) << 31) & 0x80000000)
117696 
117697 #ifndef __ASSEMBLY__
117698 /*
117699  * WARNING: The C register and register group struct declarations are provided for
117700  * convenience and illustrative purposes. They should, however, be used with
117701  * caution as the C language standard provides no guarantees about the alignment or
117702  * atomicity of device memory accesses. The recommended practice for writing
117703  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
117704  * alt_write_word() functions.
117705  *
117706  * The struct declaration for register ALT_USB_DEV_DOEPCTL6.
117707  */
117708 struct ALT_USB_DEV_DOEPCTL6_s
117709 {
117710  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL6_MPS */
117711  uint32_t : 4; /* *UNDEFINED* */
117712  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL6_USBACTEP */
117713  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL6_DPID */
117714  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL6_NAKSTS */
117715  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL6_EPTYPE */
117716  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL6_SNP */
117717  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL6_STALL */
117718  uint32_t : 4; /* *UNDEFINED* */
117719  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL6_CNAK */
117720  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL6_SNAK */
117721  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL6_SETD0PID */
117722  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL6_SETD1PID */
117723  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL6_EPDIS */
117724  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL6_EPENA */
117725 };
117726 
117727 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL6. */
117728 typedef volatile struct ALT_USB_DEV_DOEPCTL6_s ALT_USB_DEV_DOEPCTL6_t;
117729 #endif /* __ASSEMBLY__ */
117730 
117731 /* The reset value of the ALT_USB_DEV_DOEPCTL6 register. */
117732 #define ALT_USB_DEV_DOEPCTL6_RESET 0x00000000
117733 /* The byte offset of the ALT_USB_DEV_DOEPCTL6 register from the beginning of the component. */
117734 #define ALT_USB_DEV_DOEPCTL6_OFST 0x3c0
117735 /* The address of the ALT_USB_DEV_DOEPCTL6 register. */
117736 #define ALT_USB_DEV_DOEPCTL6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL6_OFST))
117737 
117738 /*
117739  * Register : doepint6
117740  *
117741  * Device OUT Endpoint 6 Interrupt Register
117742  *
117743  * Register Layout
117744  *
117745  * Bits | Access | Reset | Description
117746  * :--------|:-------|:------|:------------------------------------
117747  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_XFERCOMPL
117748  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_EPDISBLD
117749  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_AHBERR
117750  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_SETUP
117751  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS
117752  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_STSPHSERCVD
117753  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP
117754  * [7] | ??? | 0x0 | *UNDEFINED*
117755  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_OUTPKTERR
117756  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_BNAINTR
117757  * [10] | ??? | 0x0 | *UNDEFINED*
117758  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_PKTDRPSTS
117759  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_BBLEERR
117760  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_NAKINTRPT
117761  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_NYETINTRPT
117762  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_STUPPKTRCVD
117763  * [31:16] | ??? | 0x0 | *UNDEFINED*
117764  *
117765  */
117766 /*
117767  * Field : xfercompl
117768  *
117769  * Transfer Completed Interrupt (XferCompl)
117770  *
117771  * Applies to IN and OUT endpoints.
117772  *
117773  * When Scatter/Gather DMA mode is enabled
117774  *
117775  * * For IN endpoint this field indicates that the requested data
117776  *
117777  * from the descriptor is moved from external system memory
117778  *
117779  * to internal FIFO.
117780  *
117781  * * For OUT endpoint this field indicates that the requested
117782  *
117783  * data from the internal FIFO is moved to external system
117784  *
117785  * memory. This interrupt is generated only when the
117786  *
117787  * corresponding endpoint descriptor is closed, and the IOC
117788  *
117789  * bit For the corresponding descriptor is Set.
117790  *
117791  * When Scatter/Gather DMA mode is disabled, this field
117792  *
117793  * indicates that the programmed transfer is complete on the
117794  *
117795  * AHB as well as on the USB, For this endpoint.
117796  *
117797  * Field Enumeration Values:
117798  *
117799  * Enum | Value | Description
117800  * :---------------------------------------|:------|:-----------------------------
117801  * ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_INACT | 0x0 | No Interrupt
117802  * ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
117803  *
117804  * Field Access Macros:
117805  *
117806  */
117807 /*
117808  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_XFERCOMPL
117809  *
117810  * No Interrupt
117811  */
117812 #define ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_INACT 0x0
117813 /*
117814  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_XFERCOMPL
117815  *
117816  * Transfer Completed Interrupt
117817  */
117818 #define ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_ACT 0x1
117819 
117820 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */
117821 #define ALT_USB_DEV_DOEPINT6_XFERCOMPL_LSB 0
117822 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */
117823 #define ALT_USB_DEV_DOEPINT6_XFERCOMPL_MSB 0
117824 /* The width in bits of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */
117825 #define ALT_USB_DEV_DOEPINT6_XFERCOMPL_WIDTH 1
117826 /* The mask used to set the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field value. */
117827 #define ALT_USB_DEV_DOEPINT6_XFERCOMPL_SET_MSK 0x00000001
117828 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field value. */
117829 #define ALT_USB_DEV_DOEPINT6_XFERCOMPL_CLR_MSK 0xfffffffe
117830 /* The reset value of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */
117831 #define ALT_USB_DEV_DOEPINT6_XFERCOMPL_RESET 0x0
117832 /* Extracts the ALT_USB_DEV_DOEPINT6_XFERCOMPL field value from a register. */
117833 #define ALT_USB_DEV_DOEPINT6_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
117834 /* Produces a ALT_USB_DEV_DOEPINT6_XFERCOMPL register field value suitable for setting the register. */
117835 #define ALT_USB_DEV_DOEPINT6_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
117836 
117837 /*
117838  * Field : epdisbld
117839  *
117840  * Endpoint Disabled Interrupt (EPDisbld)
117841  *
117842  * Applies to IN and OUT endpoints.
117843  *
117844  * This bit indicates that the endpoint is disabled per the
117845  *
117846  * application's request.
117847  *
117848  * Field Enumeration Values:
117849  *
117850  * Enum | Value | Description
117851  * :--------------------------------------|:------|:----------------------------
117852  * ALT_USB_DEV_DOEPINT6_EPDISBLD_E_INACT | 0x0 | No Interrupt
117853  * ALT_USB_DEV_DOEPINT6_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
117854  *
117855  * Field Access Macros:
117856  *
117857  */
117858 /*
117859  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_EPDISBLD
117860  *
117861  * No Interrupt
117862  */
117863 #define ALT_USB_DEV_DOEPINT6_EPDISBLD_E_INACT 0x0
117864 /*
117865  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_EPDISBLD
117866  *
117867  * Endpoint Disabled Interrupt
117868  */
117869 #define ALT_USB_DEV_DOEPINT6_EPDISBLD_E_ACT 0x1
117870 
117871 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */
117872 #define ALT_USB_DEV_DOEPINT6_EPDISBLD_LSB 1
117873 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */
117874 #define ALT_USB_DEV_DOEPINT6_EPDISBLD_MSB 1
117875 /* The width in bits of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */
117876 #define ALT_USB_DEV_DOEPINT6_EPDISBLD_WIDTH 1
117877 /* The mask used to set the ALT_USB_DEV_DOEPINT6_EPDISBLD register field value. */
117878 #define ALT_USB_DEV_DOEPINT6_EPDISBLD_SET_MSK 0x00000002
117879 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_EPDISBLD register field value. */
117880 #define ALT_USB_DEV_DOEPINT6_EPDISBLD_CLR_MSK 0xfffffffd
117881 /* The reset value of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */
117882 #define ALT_USB_DEV_DOEPINT6_EPDISBLD_RESET 0x0
117883 /* Extracts the ALT_USB_DEV_DOEPINT6_EPDISBLD field value from a register. */
117884 #define ALT_USB_DEV_DOEPINT6_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
117885 /* Produces a ALT_USB_DEV_DOEPINT6_EPDISBLD register field value suitable for setting the register. */
117886 #define ALT_USB_DEV_DOEPINT6_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
117887 
117888 /*
117889  * Field : ahberr
117890  *
117891  * AHB Error (AHBErr)
117892  *
117893  * Applies to IN and OUT endpoints.
117894  *
117895  * This is generated only in Internal DMA mode when there is an
117896  *
117897  * AHB error during an AHB read/write. The application can read
117898  *
117899  * the corresponding endpoint DMA address register to get the
117900  *
117901  * error address.
117902  *
117903  * Field Enumeration Values:
117904  *
117905  * Enum | Value | Description
117906  * :------------------------------------|:------|:--------------------
117907  * ALT_USB_DEV_DOEPINT6_AHBERR_E_INACT | 0x0 | No Interrupt
117908  * ALT_USB_DEV_DOEPINT6_AHBERR_E_ACT | 0x1 | AHB Error interrupt
117909  *
117910  * Field Access Macros:
117911  *
117912  */
117913 /*
117914  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_AHBERR
117915  *
117916  * No Interrupt
117917  */
117918 #define ALT_USB_DEV_DOEPINT6_AHBERR_E_INACT 0x0
117919 /*
117920  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_AHBERR
117921  *
117922  * AHB Error interrupt
117923  */
117924 #define ALT_USB_DEV_DOEPINT6_AHBERR_E_ACT 0x1
117925 
117926 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */
117927 #define ALT_USB_DEV_DOEPINT6_AHBERR_LSB 2
117928 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */
117929 #define ALT_USB_DEV_DOEPINT6_AHBERR_MSB 2
117930 /* The width in bits of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */
117931 #define ALT_USB_DEV_DOEPINT6_AHBERR_WIDTH 1
117932 /* The mask used to set the ALT_USB_DEV_DOEPINT6_AHBERR register field value. */
117933 #define ALT_USB_DEV_DOEPINT6_AHBERR_SET_MSK 0x00000004
117934 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_AHBERR register field value. */
117935 #define ALT_USB_DEV_DOEPINT6_AHBERR_CLR_MSK 0xfffffffb
117936 /* The reset value of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */
117937 #define ALT_USB_DEV_DOEPINT6_AHBERR_RESET 0x0
117938 /* Extracts the ALT_USB_DEV_DOEPINT6_AHBERR field value from a register. */
117939 #define ALT_USB_DEV_DOEPINT6_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
117940 /* Produces a ALT_USB_DEV_DOEPINT6_AHBERR register field value suitable for setting the register. */
117941 #define ALT_USB_DEV_DOEPINT6_AHBERR_SET(value) (((value) << 2) & 0x00000004)
117942 
117943 /*
117944  * Field : setup
117945  *
117946  * SETUP Phase Done (SetUp)
117947  *
117948  * Applies to control OUT endpoints only.
117949  *
117950  * Indicates that the SETUP phase For the control endpoint is
117951  *
117952  * complete and no more back-to-back SETUP packets were
117953  *
117954  * received For the current control transfer. On this interrupt, the
117955  *
117956  * application can decode the received SETUP data packet.
117957  *
117958  * Field Enumeration Values:
117959  *
117960  * Enum | Value | Description
117961  * :-----------------------------------|:------|:--------------------
117962  * ALT_USB_DEV_DOEPINT6_SETUP_E_INACT | 0x0 | No SETUP Phase Done
117963  * ALT_USB_DEV_DOEPINT6_SETUP_E_ACT | 0x1 | SETUP Phase Done
117964  *
117965  * Field Access Macros:
117966  *
117967  */
117968 /*
117969  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_SETUP
117970  *
117971  * No SETUP Phase Done
117972  */
117973 #define ALT_USB_DEV_DOEPINT6_SETUP_E_INACT 0x0
117974 /*
117975  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_SETUP
117976  *
117977  * SETUP Phase Done
117978  */
117979 #define ALT_USB_DEV_DOEPINT6_SETUP_E_ACT 0x1
117980 
117981 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_SETUP register field. */
117982 #define ALT_USB_DEV_DOEPINT6_SETUP_LSB 3
117983 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_SETUP register field. */
117984 #define ALT_USB_DEV_DOEPINT6_SETUP_MSB 3
117985 /* The width in bits of the ALT_USB_DEV_DOEPINT6_SETUP register field. */
117986 #define ALT_USB_DEV_DOEPINT6_SETUP_WIDTH 1
117987 /* The mask used to set the ALT_USB_DEV_DOEPINT6_SETUP register field value. */
117988 #define ALT_USB_DEV_DOEPINT6_SETUP_SET_MSK 0x00000008
117989 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_SETUP register field value. */
117990 #define ALT_USB_DEV_DOEPINT6_SETUP_CLR_MSK 0xfffffff7
117991 /* The reset value of the ALT_USB_DEV_DOEPINT6_SETUP register field. */
117992 #define ALT_USB_DEV_DOEPINT6_SETUP_RESET 0x0
117993 /* Extracts the ALT_USB_DEV_DOEPINT6_SETUP field value from a register. */
117994 #define ALT_USB_DEV_DOEPINT6_SETUP_GET(value) (((value) & 0x00000008) >> 3)
117995 /* Produces a ALT_USB_DEV_DOEPINT6_SETUP register field value suitable for setting the register. */
117996 #define ALT_USB_DEV_DOEPINT6_SETUP_SET(value) (((value) << 3) & 0x00000008)
117997 
117998 /*
117999  * Field : outtknepdis
118000  *
118001  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
118002  *
118003  * Applies only to control OUT endpoints.
118004  *
118005  * Indicates that an OUT token was received when the endpoint
118006  *
118007  * was not yet enabled. This interrupt is asserted on the endpoint
118008  *
118009  * For which the OUT token was received.
118010  *
118011  * Field Enumeration Values:
118012  *
118013  * Enum | Value | Description
118014  * :-----------------------------------------|:------|:---------------------------------------------
118015  * ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
118016  * ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
118017  *
118018  * Field Access Macros:
118019  *
118020  */
118021 /*
118022  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS
118023  *
118024  * No OUT Token Received When Endpoint Disabled
118025  */
118026 #define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_INACT 0x0
118027 /*
118028  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS
118029  *
118030  * OUT Token Received When Endpoint Disabled
118031  */
118032 #define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_ACT 0x1
118033 
118034 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */
118035 #define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_LSB 4
118036 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */
118037 #define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_MSB 4
118038 /* The width in bits of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */
118039 #define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_WIDTH 1
118040 /* The mask used to set the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field value. */
118041 #define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_SET_MSK 0x00000010
118042 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field value. */
118043 #define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_CLR_MSK 0xffffffef
118044 /* The reset value of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */
118045 #define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_RESET 0x0
118046 /* Extracts the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS field value from a register. */
118047 #define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
118048 /* Produces a ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field value suitable for setting the register. */
118049 #define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
118050 
118051 /*
118052  * Field : stsphsercvd
118053  *
118054  * Status Phase Received For Control Write (StsPhseRcvd)
118055  *
118056  * This interrupt is valid only For Control OUT endpoints and only in
118057  *
118058  * Scatter Gather DMA mode.
118059  *
118060  * This interrupt is generated only after the core has transferred all
118061  *
118062  * the data that the host has sent during the data phase of a control
118063  *
118064  * write transfer, to the system memory buffer.
118065  *
118066  * The interrupt indicates to the application that the host has
118067  *
118068  * switched from data phase to the status phase of a Control Write
118069  *
118070  * transfer. The application can use this interrupt to ACK or STALL
118071  *
118072  * the Status phase, after it has decoded the data phase. This is
118073  *
118074  * applicable only in Case of Scatter Gather DMA mode.
118075  *
118076  * Field Enumeration Values:
118077  *
118078  * Enum | Value | Description
118079  * :-----------------------------------------|:------|:-------------------------------------------
118080  * ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
118081  * ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
118082  *
118083  * Field Access Macros:
118084  *
118085  */
118086 /*
118087  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_STSPHSERCVD
118088  *
118089  * No Status Phase Received for Control Write
118090  */
118091 #define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_INACT 0x0
118092 /*
118093  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_STSPHSERCVD
118094  *
118095  * Status Phase Received for Control Write
118096  */
118097 #define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_ACT 0x1
118098 
118099 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */
118100 #define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_LSB 5
118101 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */
118102 #define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_MSB 5
118103 /* The width in bits of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */
118104 #define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_WIDTH 1
118105 /* The mask used to set the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field value. */
118106 #define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_SET_MSK 0x00000020
118107 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field value. */
118108 #define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_CLR_MSK 0xffffffdf
118109 /* The reset value of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */
118110 #define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_RESET 0x0
118111 /* Extracts the ALT_USB_DEV_DOEPINT6_STSPHSERCVD field value from a register. */
118112 #define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
118113 /* Produces a ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field value suitable for setting the register. */
118114 #define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
118115 
118116 /*
118117  * Field : back2backsetup
118118  *
118119  * Back-to-Back SETUP Packets Received (Back2BackSETup)
118120  *
118121  * Applies to Control OUT endpoints only.
118122  *
118123  * This bit indicates that the core has received more than three
118124  *
118125  * back-to-back SETUP packets For this particular endpoint. For
118126  *
118127  * information about handling this interrupt,
118128  *
118129  * Field Enumeration Values:
118130  *
118131  * Enum | Value | Description
118132  * :--------------------------------------------|:------|:---------------------------------------
118133  * ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
118134  * ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
118135  *
118136  * Field Access Macros:
118137  *
118138  */
118139 /*
118140  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP
118141  *
118142  * No Back-to-Back SETUP Packets Received
118143  */
118144 #define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_INACT 0x0
118145 /*
118146  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP
118147  *
118148  * Back-to-Back SETUP Packets Received
118149  */
118150 #define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_ACT 0x1
118151 
118152 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */
118153 #define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_LSB 6
118154 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */
118155 #define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_MSB 6
118156 /* The width in bits of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */
118157 #define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_WIDTH 1
118158 /* The mask used to set the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field value. */
118159 #define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_SET_MSK 0x00000040
118160 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field value. */
118161 #define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_CLR_MSK 0xffffffbf
118162 /* The reset value of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */
118163 #define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_RESET 0x0
118164 /* Extracts the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP field value from a register. */
118165 #define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
118166 /* Produces a ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field value suitable for setting the register. */
118167 #define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
118168 
118169 /*
118170  * Field : outpkterr
118171  *
118172  * OUT Packet Error (OutPktErr)
118173  *
118174  * Applies to OUT endpoints Only
118175  *
118176  * This interrupt is valid only when thresholding is enabled. This interrupt is
118177  * asserted when the
118178  *
118179  * core detects an overflow or a CRC error For non-Isochronous
118180  *
118181  * OUT packet.
118182  *
118183  * Field Enumeration Values:
118184  *
118185  * Enum | Value | Description
118186  * :---------------------------------------|:------|:--------------------
118187  * ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
118188  * ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
118189  *
118190  * Field Access Macros:
118191  *
118192  */
118193 /*
118194  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTPKTERR
118195  *
118196  * No OUT Packet Error
118197  */
118198 #define ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_INACT 0x0
118199 /*
118200  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTPKTERR
118201  *
118202  * OUT Packet Error
118203  */
118204 #define ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_ACT 0x1
118205 
118206 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */
118207 #define ALT_USB_DEV_DOEPINT6_OUTPKTERR_LSB 8
118208 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */
118209 #define ALT_USB_DEV_DOEPINT6_OUTPKTERR_MSB 8
118210 /* The width in bits of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */
118211 #define ALT_USB_DEV_DOEPINT6_OUTPKTERR_WIDTH 1
118212 /* The mask used to set the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field value. */
118213 #define ALT_USB_DEV_DOEPINT6_OUTPKTERR_SET_MSK 0x00000100
118214 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field value. */
118215 #define ALT_USB_DEV_DOEPINT6_OUTPKTERR_CLR_MSK 0xfffffeff
118216 /* The reset value of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */
118217 #define ALT_USB_DEV_DOEPINT6_OUTPKTERR_RESET 0x0
118218 /* Extracts the ALT_USB_DEV_DOEPINT6_OUTPKTERR field value from a register. */
118219 #define ALT_USB_DEV_DOEPINT6_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
118220 /* Produces a ALT_USB_DEV_DOEPINT6_OUTPKTERR register field value suitable for setting the register. */
118221 #define ALT_USB_DEV_DOEPINT6_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
118222 
118223 /*
118224  * Field : bnaintr
118225  *
118226  * BNA (Buffer Not Available) Interrupt (BNAIntr)
118227  *
118228  * This bit is valid only when Scatter/Gather DMA mode is enabled.
118229  *
118230  * The core generates this interrupt when the descriptor accessed
118231  *
118232  * is not ready For the Core to process, such as Host busy or DMA
118233  *
118234  * done
118235  *
118236  * Field Enumeration Values:
118237  *
118238  * Enum | Value | Description
118239  * :-------------------------------------|:------|:--------------
118240  * ALT_USB_DEV_DOEPINT6_BNAINTR_E_INACT | 0x0 | No interrupt
118241  * ALT_USB_DEV_DOEPINT6_BNAINTR_E_ACT | 0x1 | BNA interrupt
118242  *
118243  * Field Access Macros:
118244  *
118245  */
118246 /*
118247  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BNAINTR
118248  *
118249  * No interrupt
118250  */
118251 #define ALT_USB_DEV_DOEPINT6_BNAINTR_E_INACT 0x0
118252 /*
118253  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BNAINTR
118254  *
118255  * BNA interrupt
118256  */
118257 #define ALT_USB_DEV_DOEPINT6_BNAINTR_E_ACT 0x1
118258 
118259 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */
118260 #define ALT_USB_DEV_DOEPINT6_BNAINTR_LSB 9
118261 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */
118262 #define ALT_USB_DEV_DOEPINT6_BNAINTR_MSB 9
118263 /* The width in bits of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */
118264 #define ALT_USB_DEV_DOEPINT6_BNAINTR_WIDTH 1
118265 /* The mask used to set the ALT_USB_DEV_DOEPINT6_BNAINTR register field value. */
118266 #define ALT_USB_DEV_DOEPINT6_BNAINTR_SET_MSK 0x00000200
118267 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_BNAINTR register field value. */
118268 #define ALT_USB_DEV_DOEPINT6_BNAINTR_CLR_MSK 0xfffffdff
118269 /* The reset value of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */
118270 #define ALT_USB_DEV_DOEPINT6_BNAINTR_RESET 0x0
118271 /* Extracts the ALT_USB_DEV_DOEPINT6_BNAINTR field value from a register. */
118272 #define ALT_USB_DEV_DOEPINT6_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
118273 /* Produces a ALT_USB_DEV_DOEPINT6_BNAINTR register field value suitable for setting the register. */
118274 #define ALT_USB_DEV_DOEPINT6_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
118275 
118276 /*
118277  * Field : pktdrpsts
118278  *
118279  * Packet Drop Status (PktDrpSts)
118280  *
118281  * This bit indicates to the application that an ISOC OUT packet has been dropped.
118282  * This
118283  *
118284  * bit does not have an associated mask bit and does not generate an interrupt.
118285  *
118286  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
118287  * transfer
118288  *
118289  * interrupt feature is selected.
118290  *
118291  * Field Enumeration Values:
118292  *
118293  * Enum | Value | Description
118294  * :---------------------------------------|:------|:-----------------------------
118295  * ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_INACT | 0x0 | No interrupt
118296  * ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
118297  *
118298  * Field Access Macros:
118299  *
118300  */
118301 /*
118302  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_PKTDRPSTS
118303  *
118304  * No interrupt
118305  */
118306 #define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_INACT 0x0
118307 /*
118308  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_PKTDRPSTS
118309  *
118310  * Packet Drop Status interrupt
118311  */
118312 #define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_ACT 0x1
118313 
118314 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */
118315 #define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_LSB 11
118316 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */
118317 #define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_MSB 11
118318 /* The width in bits of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */
118319 #define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_WIDTH 1
118320 /* The mask used to set the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field value. */
118321 #define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_SET_MSK 0x00000800
118322 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field value. */
118323 #define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_CLR_MSK 0xfffff7ff
118324 /* The reset value of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */
118325 #define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_RESET 0x0
118326 /* Extracts the ALT_USB_DEV_DOEPINT6_PKTDRPSTS field value from a register. */
118327 #define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
118328 /* Produces a ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field value suitable for setting the register. */
118329 #define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
118330 
118331 /*
118332  * Field : bbleerr
118333  *
118334  * NAK Interrupt (BbleErr)
118335  *
118336  * The core generates this interrupt when babble is received for the endpoint.
118337  *
118338  * Field Enumeration Values:
118339  *
118340  * Enum | Value | Description
118341  * :-------------------------------------|:------|:------------------
118342  * ALT_USB_DEV_DOEPINT6_BBLEERR_E_INACT | 0x0 | No interrupt
118343  * ALT_USB_DEV_DOEPINT6_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
118344  *
118345  * Field Access Macros:
118346  *
118347  */
118348 /*
118349  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BBLEERR
118350  *
118351  * No interrupt
118352  */
118353 #define ALT_USB_DEV_DOEPINT6_BBLEERR_E_INACT 0x0
118354 /*
118355  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_BBLEERR
118356  *
118357  * BbleErr interrupt
118358  */
118359 #define ALT_USB_DEV_DOEPINT6_BBLEERR_E_ACT 0x1
118360 
118361 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */
118362 #define ALT_USB_DEV_DOEPINT6_BBLEERR_LSB 12
118363 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */
118364 #define ALT_USB_DEV_DOEPINT6_BBLEERR_MSB 12
118365 /* The width in bits of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */
118366 #define ALT_USB_DEV_DOEPINT6_BBLEERR_WIDTH 1
118367 /* The mask used to set the ALT_USB_DEV_DOEPINT6_BBLEERR register field value. */
118368 #define ALT_USB_DEV_DOEPINT6_BBLEERR_SET_MSK 0x00001000
118369 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_BBLEERR register field value. */
118370 #define ALT_USB_DEV_DOEPINT6_BBLEERR_CLR_MSK 0xffffefff
118371 /* The reset value of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */
118372 #define ALT_USB_DEV_DOEPINT6_BBLEERR_RESET 0x0
118373 /* Extracts the ALT_USB_DEV_DOEPINT6_BBLEERR field value from a register. */
118374 #define ALT_USB_DEV_DOEPINT6_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
118375 /* Produces a ALT_USB_DEV_DOEPINT6_BBLEERR register field value suitable for setting the register. */
118376 #define ALT_USB_DEV_DOEPINT6_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
118377 
118378 /*
118379  * Field : nakintrpt
118380  *
118381  * NAK Interrupt (NAKInterrupt)
118382  *
118383  * The core generates this interrupt when a NAK is transmitted or received by the
118384  * device.
118385  *
118386  * In case of isochronous IN endpoints the interrupt gets generated when a zero
118387  * length
118388  *
118389  * packet is transmitted due to un-availability of data in the TXFifo.
118390  *
118391  * Field Enumeration Values:
118392  *
118393  * Enum | Value | Description
118394  * :---------------------------------------|:------|:--------------
118395  * ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_INACT | 0x0 | No interrupt
118396  * ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
118397  *
118398  * Field Access Macros:
118399  *
118400  */
118401 /*
118402  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_NAKINTRPT
118403  *
118404  * No interrupt
118405  */
118406 #define ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_INACT 0x0
118407 /*
118408  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_NAKINTRPT
118409  *
118410  * NAK Interrupt
118411  */
118412 #define ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_ACT 0x1
118413 
118414 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */
118415 #define ALT_USB_DEV_DOEPINT6_NAKINTRPT_LSB 13
118416 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */
118417 #define ALT_USB_DEV_DOEPINT6_NAKINTRPT_MSB 13
118418 /* The width in bits of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */
118419 #define ALT_USB_DEV_DOEPINT6_NAKINTRPT_WIDTH 1
118420 /* The mask used to set the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field value. */
118421 #define ALT_USB_DEV_DOEPINT6_NAKINTRPT_SET_MSK 0x00002000
118422 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field value. */
118423 #define ALT_USB_DEV_DOEPINT6_NAKINTRPT_CLR_MSK 0xffffdfff
118424 /* The reset value of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */
118425 #define ALT_USB_DEV_DOEPINT6_NAKINTRPT_RESET 0x0
118426 /* Extracts the ALT_USB_DEV_DOEPINT6_NAKINTRPT field value from a register. */
118427 #define ALT_USB_DEV_DOEPINT6_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
118428 /* Produces a ALT_USB_DEV_DOEPINT6_NAKINTRPT register field value suitable for setting the register. */
118429 #define ALT_USB_DEV_DOEPINT6_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
118430 
118431 /*
118432  * Field : nyetintrpt
118433  *
118434  * NYET Interrupt (NYETIntrpt)
118435  *
118436  * The core generates this interrupt when a NYET response is transmitted for a non
118437  * isochronous OUT endpoint.
118438  *
118439  * Field Enumeration Values:
118440  *
118441  * Enum | Value | Description
118442  * :----------------------------------------|:------|:---------------
118443  * ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_INACT | 0x0 | No interrupt
118444  * ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
118445  *
118446  * Field Access Macros:
118447  *
118448  */
118449 /*
118450  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_NYETINTRPT
118451  *
118452  * No interrupt
118453  */
118454 #define ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_INACT 0x0
118455 /*
118456  * Enumerated value for register field ALT_USB_DEV_DOEPINT6_NYETINTRPT
118457  *
118458  * NYET Interrupt
118459  */
118460 #define ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_ACT 0x1
118461 
118462 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */
118463 #define ALT_USB_DEV_DOEPINT6_NYETINTRPT_LSB 14
118464 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */
118465 #define ALT_USB_DEV_DOEPINT6_NYETINTRPT_MSB 14
118466 /* The width in bits of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */
118467 #define ALT_USB_DEV_DOEPINT6_NYETINTRPT_WIDTH 1
118468 /* The mask used to set the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field value. */
118469 #define ALT_USB_DEV_DOEPINT6_NYETINTRPT_SET_MSK 0x00004000
118470 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field value. */
118471 #define ALT_USB_DEV_DOEPINT6_NYETINTRPT_CLR_MSK 0xffffbfff
118472 /* The reset value of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */
118473 #define ALT_USB_DEV_DOEPINT6_NYETINTRPT_RESET 0x0
118474 /* Extracts the ALT_USB_DEV_DOEPINT6_NYETINTRPT field value from a register. */
118475 #define ALT_USB_DEV_DOEPINT6_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
118476 /* Produces a ALT_USB_DEV_DOEPINT6_NYETINTRPT register field value suitable for setting the register. */
118477 #define ALT_USB_DEV_DOEPINT6_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
118478 
118479 /*
118480  * Field : stuppktrcvd
118481  *
118482  * Setup Packet Received
118483  *
118484  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
118485  *
118486  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
118487  *
118488  * setup data. There is only one Setup packet per buffer. On receiving a
118489  *
118490  * Setup packet, the DWC_otg core closes the buffer and disables the
118491  *
118492  * corresponding endpoint. The application has to re-enable the endpoint to
118493  *
118494  * receive any OUT data for the Control Transfer and reprogram the buffer
118495  *
118496  * start address.
118497  *
118498  * Note: Because of the above behavior, the DWC_otg core can receive any
118499  *
118500  * number of back to back setup packets and one buffer for every setup
118501  *
118502  * packet is used.
118503  *
118504  * 1'b0: No Setup packet received
118505  *
118506  * 1'b1: Setup packet received
118507  *
118508  * Reset: 1'b0
118509  *
118510  * Field Access Macros:
118511  *
118512  */
118513 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field. */
118514 #define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_LSB 15
118515 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field. */
118516 #define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_MSB 15
118517 /* The width in bits of the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field. */
118518 #define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_WIDTH 1
118519 /* The mask used to set the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field value. */
118520 #define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_SET_MSK 0x00008000
118521 /* The mask used to clear the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field value. */
118522 #define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_CLR_MSK 0xffff7fff
118523 /* The reset value of the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field. */
118524 #define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_RESET 0x0
118525 /* Extracts the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD field value from a register. */
118526 #define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
118527 /* Produces a ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field value suitable for setting the register. */
118528 #define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
118529 
118530 #ifndef __ASSEMBLY__
118531 /*
118532  * WARNING: The C register and register group struct declarations are provided for
118533  * convenience and illustrative purposes. They should, however, be used with
118534  * caution as the C language standard provides no guarantees about the alignment or
118535  * atomicity of device memory accesses. The recommended practice for writing
118536  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
118537  * alt_write_word() functions.
118538  *
118539  * The struct declaration for register ALT_USB_DEV_DOEPINT6.
118540  */
118541 struct ALT_USB_DEV_DOEPINT6_s
118542 {
118543  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT6_XFERCOMPL */
118544  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT6_EPDISBLD */
118545  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT6_AHBERR */
118546  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT6_SETUP */
118547  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS */
118548  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT6_STSPHSERCVD */
118549  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP */
118550  uint32_t : 1; /* *UNDEFINED* */
118551  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT6_OUTPKTERR */
118552  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT6_BNAINTR */
118553  uint32_t : 1; /* *UNDEFINED* */
118554  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT6_PKTDRPSTS */
118555  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT6_BBLEERR */
118556  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT6_NAKINTRPT */
118557  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT6_NYETINTRPT */
118558  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT6_STUPPKTRCVD */
118559  uint32_t : 16; /* *UNDEFINED* */
118560 };
118561 
118562 /* The typedef declaration for register ALT_USB_DEV_DOEPINT6. */
118563 typedef volatile struct ALT_USB_DEV_DOEPINT6_s ALT_USB_DEV_DOEPINT6_t;
118564 #endif /* __ASSEMBLY__ */
118565 
118566 /* The reset value of the ALT_USB_DEV_DOEPINT6 register. */
118567 #define ALT_USB_DEV_DOEPINT6_RESET 0x00000000
118568 /* The byte offset of the ALT_USB_DEV_DOEPINT6 register from the beginning of the component. */
118569 #define ALT_USB_DEV_DOEPINT6_OFST 0x3c8
118570 /* The address of the ALT_USB_DEV_DOEPINT6 register. */
118571 #define ALT_USB_DEV_DOEPINT6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT6_OFST))
118572 
118573 /*
118574  * Register : doeptsiz6
118575  *
118576  * Device OUT Endpoint 6 Transfer Size Register
118577  *
118578  * Register Layout
118579  *
118580  * Bits | Access | Reset | Description
118581  * :--------|:-------|:------|:-------------------------------
118582  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ6_XFERSIZE
118583  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ6_PKTCNT
118584  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ6_RXDPID
118585  * [31] | ??? | 0x0 | *UNDEFINED*
118586  *
118587  */
118588 /*
118589  * Field : xfersize
118590  *
118591  * Transfer Size (XferSize)
118592  *
118593  * Indicates the transfer size in bytes For endpoint 0. The core
118594  *
118595  * interrupts the application only after it has exhausted the transfer
118596  *
118597  * size amount of data. The transfer size can be Set to the
118598  *
118599  * maximum packet size of the endpoint, to be interrupted at the
118600  *
118601  * end of each packet.
118602  *
118603  * The core decrements this field every time a packet is read from
118604  *
118605  * the RxFIFO and written to the external memory.
118606  *
118607  * Field Access Macros:
118608  *
118609  */
118610 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */
118611 #define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_LSB 0
118612 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */
118613 #define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_MSB 18
118614 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */
118615 #define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_WIDTH 19
118616 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field value. */
118617 #define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_SET_MSK 0x0007ffff
118618 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field value. */
118619 #define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_CLR_MSK 0xfff80000
118620 /* The reset value of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */
118621 #define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_RESET 0x0
118622 /* Extracts the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE field value from a register. */
118623 #define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
118624 /* Produces a ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field value suitable for setting the register. */
118625 #define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
118626 
118627 /*
118628  * Field : pktcnt
118629  *
118630  * Packet Count (PktCnt)
118631  *
118632  * This field is decremented to zero after a packet is written into the
118633  *
118634  * RxFIFO.
118635  *
118636  * Field Access Macros:
118637  *
118638  */
118639 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */
118640 #define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_LSB 19
118641 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */
118642 #define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_MSB 28
118643 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */
118644 #define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_WIDTH 10
118645 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field value. */
118646 #define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_SET_MSK 0x1ff80000
118647 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field value. */
118648 #define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_CLR_MSK 0xe007ffff
118649 /* The reset value of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */
118650 #define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_RESET 0x0
118651 /* Extracts the ALT_USB_DEV_DOEPTSIZ6_PKTCNT field value from a register. */
118652 #define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
118653 /* Produces a ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field value suitable for setting the register. */
118654 #define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
118655 
118656 /*
118657  * Field : rxdpid
118658  *
118659  * Applies to isochronous OUT endpoints only.
118660  *
118661  * This is the data PID received in the last packet for this endpoint.
118662  *
118663  * 2'b00: DATA0
118664  *
118665  * 2'b01: DATA2
118666  *
118667  * 2'b10: DATA1
118668  *
118669  * 2'b11: MDATA
118670  *
118671  * SETUP Packet Count (SUPCnt)
118672  *
118673  * Applies to control OUT Endpoints only.
118674  *
118675  * This field specifies the number of back-to-back SETUP data
118676  *
118677  * packets the endpoint can receive.
118678  *
118679  * 2'b01: 1 packet
118680  *
118681  * 2'b10: 2 packets
118682  *
118683  * 2'b11: 3 packets
118684  *
118685  * Field Enumeration Values:
118686  *
118687  * Enum | Value | Description
118688  * :-----------------------------------------|:------|:-------------------
118689  * ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA0 | 0x0 | DATA0
118690  * ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
118691  * ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
118692  * ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
118693  *
118694  * Field Access Macros:
118695  *
118696  */
118697 /*
118698  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID
118699  *
118700  * DATA0
118701  */
118702 #define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA0 0x0
118703 /*
118704  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID
118705  *
118706  * DATA2 or 1 packet
118707  */
118708 #define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA2PKT1 0x1
118709 /*
118710  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID
118711  *
118712  * DATA1 or 2 packets
118713  */
118714 #define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA1PKT2 0x2
118715 /*
118716  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID
118717  *
118718  * MDATA or 3 packets
118719  */
118720 #define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_MDATAPKT3 0x3
118721 
118722 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */
118723 #define ALT_USB_DEV_DOEPTSIZ6_RXDPID_LSB 29
118724 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */
118725 #define ALT_USB_DEV_DOEPTSIZ6_RXDPID_MSB 30
118726 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */
118727 #define ALT_USB_DEV_DOEPTSIZ6_RXDPID_WIDTH 2
118728 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field value. */
118729 #define ALT_USB_DEV_DOEPTSIZ6_RXDPID_SET_MSK 0x60000000
118730 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field value. */
118731 #define ALT_USB_DEV_DOEPTSIZ6_RXDPID_CLR_MSK 0x9fffffff
118732 /* The reset value of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */
118733 #define ALT_USB_DEV_DOEPTSIZ6_RXDPID_RESET 0x0
118734 /* Extracts the ALT_USB_DEV_DOEPTSIZ6_RXDPID field value from a register. */
118735 #define ALT_USB_DEV_DOEPTSIZ6_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
118736 /* Produces a ALT_USB_DEV_DOEPTSIZ6_RXDPID register field value suitable for setting the register. */
118737 #define ALT_USB_DEV_DOEPTSIZ6_RXDPID_SET(value) (((value) << 29) & 0x60000000)
118738 
118739 #ifndef __ASSEMBLY__
118740 /*
118741  * WARNING: The C register and register group struct declarations are provided for
118742  * convenience and illustrative purposes. They should, however, be used with
118743  * caution as the C language standard provides no guarantees about the alignment or
118744  * atomicity of device memory accesses. The recommended practice for writing
118745  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
118746  * alt_write_word() functions.
118747  *
118748  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ6.
118749  */
118750 struct ALT_USB_DEV_DOEPTSIZ6_s
118751 {
118752  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ6_XFERSIZE */
118753  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ6_PKTCNT */
118754  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ6_RXDPID */
118755  uint32_t : 1; /* *UNDEFINED* */
118756 };
118757 
118758 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ6. */
118759 typedef volatile struct ALT_USB_DEV_DOEPTSIZ6_s ALT_USB_DEV_DOEPTSIZ6_t;
118760 #endif /* __ASSEMBLY__ */
118761 
118762 /* The reset value of the ALT_USB_DEV_DOEPTSIZ6 register. */
118763 #define ALT_USB_DEV_DOEPTSIZ6_RESET 0x00000000
118764 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ6 register from the beginning of the component. */
118765 #define ALT_USB_DEV_DOEPTSIZ6_OFST 0x3d0
118766 /* The address of the ALT_USB_DEV_DOEPTSIZ6 register. */
118767 #define ALT_USB_DEV_DOEPTSIZ6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ6_OFST))
118768 
118769 /*
118770  * Register : doepdma6
118771  *
118772  * Device OUT Endpoint 6 DMA Address Register
118773  *
118774  * Register Layout
118775  *
118776  * Bits | Access | Reset | Description
118777  * :-------|:-------|:--------|:------------------------------
118778  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA6_DOEPDMA6
118779  *
118780  */
118781 /*
118782  * Field : doepdma6
118783  *
118784  * Holds the start address of the external memory for storing or fetching endpoint
118785  *
118786  * data.
118787  *
118788  * Note: For control endpoints, this field stores control OUT data packets as well
118789  * as
118790  *
118791  * SETUP transaction data packets. When more than three SETUP packets are
118792  *
118793  * received back-to-back, the SETUP data packet in the memory is overwritten.
118794  *
118795  * This register is incremented on every AHB transaction. The application can give
118796  *
118797  * only a DWORD-aligned address.
118798  *
118799  * When Scatter/Gather DMA mode is not enabled, the application programs the
118800  *
118801  * start address value in this field.
118802  *
118803  * When Scatter/Gather DMA mode is enabled, this field indicates the base
118804  *
118805  * pointer for the descriptor list.
118806  *
118807  * Field Access Macros:
118808  *
118809  */
118810 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field. */
118811 #define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_LSB 0
118812 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field. */
118813 #define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_MSB 31
118814 /* The width in bits of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field. */
118815 #define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_WIDTH 32
118816 /* The mask used to set the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field value. */
118817 #define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_SET_MSK 0xffffffff
118818 /* The mask used to clear the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field value. */
118819 #define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_CLR_MSK 0x00000000
118820 /* The reset value of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field is UNKNOWN. */
118821 #define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_RESET 0x0
118822 /* Extracts the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 field value from a register. */
118823 #define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_GET(value) (((value) & 0xffffffff) >> 0)
118824 /* Produces a ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field value suitable for setting the register. */
118825 #define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_SET(value) (((value) << 0) & 0xffffffff)
118826 
118827 #ifndef __ASSEMBLY__
118828 /*
118829  * WARNING: The C register and register group struct declarations are provided for
118830  * convenience and illustrative purposes. They should, however, be used with
118831  * caution as the C language standard provides no guarantees about the alignment or
118832  * atomicity of device memory accesses. The recommended practice for writing
118833  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
118834  * alt_write_word() functions.
118835  *
118836  * The struct declaration for register ALT_USB_DEV_DOEPDMA6.
118837  */
118838 struct ALT_USB_DEV_DOEPDMA6_s
118839 {
118840  uint32_t doepdma6 : 32; /* ALT_USB_DEV_DOEPDMA6_DOEPDMA6 */
118841 };
118842 
118843 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA6. */
118844 typedef volatile struct ALT_USB_DEV_DOEPDMA6_s ALT_USB_DEV_DOEPDMA6_t;
118845 #endif /* __ASSEMBLY__ */
118846 
118847 /* The reset value of the ALT_USB_DEV_DOEPDMA6 register. */
118848 #define ALT_USB_DEV_DOEPDMA6_RESET 0x00000000
118849 /* The byte offset of the ALT_USB_DEV_DOEPDMA6 register from the beginning of the component. */
118850 #define ALT_USB_DEV_DOEPDMA6_OFST 0x3d4
118851 /* The address of the ALT_USB_DEV_DOEPDMA6 register. */
118852 #define ALT_USB_DEV_DOEPDMA6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA6_OFST))
118853 
118854 /*
118855  * Register : doepdmab6
118856  *
118857  * Device OUT Endpoint 6 Buffer Address Register
118858  *
118859  * Register Layout
118860  *
118861  * Bits | Access | Reset | Description
118862  * :-------|:-------|:--------|:--------------------------------
118863  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6
118864  *
118865  */
118866 /*
118867  * Field : doepdmab6
118868  *
118869  * Holds the current buffer address.This register is updated as and when the data
118870  *
118871  * transfer for the corresponding end point is in progress.
118872  *
118873  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
118874  * is
118875  *
118876  * reserved.
118877  *
118878  * Field Access Macros:
118879  *
118880  */
118881 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field. */
118882 #define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_LSB 0
118883 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field. */
118884 #define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_MSB 31
118885 /* The width in bits of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field. */
118886 #define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_WIDTH 32
118887 /* The mask used to set the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field value. */
118888 #define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_SET_MSK 0xffffffff
118889 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field value. */
118890 #define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_CLR_MSK 0x00000000
118891 /* The reset value of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field is UNKNOWN. */
118892 #define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_RESET 0x0
118893 /* Extracts the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 field value from a register. */
118894 #define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_GET(value) (((value) & 0xffffffff) >> 0)
118895 /* Produces a ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field value suitable for setting the register. */
118896 #define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_SET(value) (((value) << 0) & 0xffffffff)
118897 
118898 #ifndef __ASSEMBLY__
118899 /*
118900  * WARNING: The C register and register group struct declarations are provided for
118901  * convenience and illustrative purposes. They should, however, be used with
118902  * caution as the C language standard provides no guarantees about the alignment or
118903  * atomicity of device memory accesses. The recommended practice for writing
118904  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
118905  * alt_write_word() functions.
118906  *
118907  * The struct declaration for register ALT_USB_DEV_DOEPDMAB6.
118908  */
118909 struct ALT_USB_DEV_DOEPDMAB6_s
118910 {
118911  const uint32_t doepdmab6 : 32; /* ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 */
118912 };
118913 
118914 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB6. */
118915 typedef volatile struct ALT_USB_DEV_DOEPDMAB6_s ALT_USB_DEV_DOEPDMAB6_t;
118916 #endif /* __ASSEMBLY__ */
118917 
118918 /* The reset value of the ALT_USB_DEV_DOEPDMAB6 register. */
118919 #define ALT_USB_DEV_DOEPDMAB6_RESET 0x00000000
118920 /* The byte offset of the ALT_USB_DEV_DOEPDMAB6 register from the beginning of the component. */
118921 #define ALT_USB_DEV_DOEPDMAB6_OFST 0x3dc
118922 /* The address of the ALT_USB_DEV_DOEPDMAB6 register. */
118923 #define ALT_USB_DEV_DOEPDMAB6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB6_OFST))
118924 
118925 /*
118926  * Register : doepctl7
118927  *
118928  * Device Control OUT Endpoint 7 Control Register
118929  *
118930  * Register Layout
118931  *
118932  * Bits | Access | Reset | Description
118933  * :--------|:---------|:------|:------------------------------
118934  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL7_MPS
118935  * [14:11] | ??? | 0x0 | *UNDEFINED*
118936  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL7_USBACTEP
118937  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL7_DPID
118938  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL7_NAKSTS
118939  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL7_EPTYPE
118940  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL7_SNP
118941  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL7_STALL
118942  * [25:22] | ??? | 0x0 | *UNDEFINED*
118943  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL7_CNAK
118944  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL7_SNAK
118945  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL7_SETD0PID
118946  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL7_SETD1PID
118947  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL7_EPDIS
118948  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL7_EPENA
118949  *
118950  */
118951 /*
118952  * Field : mps
118953  *
118954  * Maximum Packet Size (MPS)
118955  *
118956  * The application must program this field with the maximum packet size for the
118957  * current
118958  *
118959  * logical endpoint. This value is in bytes.
118960  *
118961  * Field Access Macros:
118962  *
118963  */
118964 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_MPS register field. */
118965 #define ALT_USB_DEV_DOEPCTL7_MPS_LSB 0
118966 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_MPS register field. */
118967 #define ALT_USB_DEV_DOEPCTL7_MPS_MSB 10
118968 /* The width in bits of the ALT_USB_DEV_DOEPCTL7_MPS register field. */
118969 #define ALT_USB_DEV_DOEPCTL7_MPS_WIDTH 11
118970 /* The mask used to set the ALT_USB_DEV_DOEPCTL7_MPS register field value. */
118971 #define ALT_USB_DEV_DOEPCTL7_MPS_SET_MSK 0x000007ff
118972 /* The mask used to clear the ALT_USB_DEV_DOEPCTL7_MPS register field value. */
118973 #define ALT_USB_DEV_DOEPCTL7_MPS_CLR_MSK 0xfffff800
118974 /* The reset value of the ALT_USB_DEV_DOEPCTL7_MPS register field. */
118975 #define ALT_USB_DEV_DOEPCTL7_MPS_RESET 0x0
118976 /* Extracts the ALT_USB_DEV_DOEPCTL7_MPS field value from a register. */
118977 #define ALT_USB_DEV_DOEPCTL7_MPS_GET(value) (((value) & 0x000007ff) >> 0)
118978 /* Produces a ALT_USB_DEV_DOEPCTL7_MPS register field value suitable for setting the register. */
118979 #define ALT_USB_DEV_DOEPCTL7_MPS_SET(value) (((value) << 0) & 0x000007ff)
118980 
118981 /*
118982  * Field : usbactep
118983  *
118984  * USB Active Endpoint (USBActEP)
118985  *
118986  * Indicates whether this endpoint is active in the current configuration and
118987  * interface. The
118988  *
118989  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
118990  * reset. After
118991  *
118992  * receiving the SetConfiguration and SetInterface commands, the application must
118993  *
118994  * program endpoint registers accordingly and set this bit.
118995  *
118996  * Field Enumeration Values:
118997  *
118998  * Enum | Value | Description
118999  * :-------------------------------------|:------|:--------------------
119000  * ALT_USB_DEV_DOEPCTL7_USBACTEP_E_DISD | 0x0 | Not Active
119001  * ALT_USB_DEV_DOEPCTL7_USBACTEP_E_END | 0x1 | USB Active Endpoint
119002  *
119003  * Field Access Macros:
119004  *
119005  */
119006 /*
119007  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_USBACTEP
119008  *
119009  * Not Active
119010  */
119011 #define ALT_USB_DEV_DOEPCTL7_USBACTEP_E_DISD 0x0
119012 /*
119013  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_USBACTEP
119014  *
119015  * USB Active Endpoint
119016  */
119017 #define ALT_USB_DEV_DOEPCTL7_USBACTEP_E_END 0x1
119018 
119019 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */
119020 #define ALT_USB_DEV_DOEPCTL7_USBACTEP_LSB 15
119021 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */
119022 #define ALT_USB_DEV_DOEPCTL7_USBACTEP_MSB 15
119023 /* The width in bits of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */
119024 #define ALT_USB_DEV_DOEPCTL7_USBACTEP_WIDTH 1
119025 /* The mask used to set the ALT_USB_DEV_DOEPCTL7_USBACTEP register field value. */
119026 #define ALT_USB_DEV_DOEPCTL7_USBACTEP_SET_MSK 0x00008000
119027 /* The mask used to clear the ALT_USB_DEV_DOEPCTL7_USBACTEP register field value. */
119028 #define ALT_USB_DEV_DOEPCTL7_USBACTEP_CLR_MSK 0xffff7fff
119029 /* The reset value of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */
119030 #define ALT_USB_DEV_DOEPCTL7_USBACTEP_RESET 0x0
119031 /* Extracts the ALT_USB_DEV_DOEPCTL7_USBACTEP field value from a register. */
119032 #define ALT_USB_DEV_DOEPCTL7_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
119033 /* Produces a ALT_USB_DEV_DOEPCTL7_USBACTEP register field value suitable for setting the register. */
119034 #define ALT_USB_DEV_DOEPCTL7_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
119035 
119036 /*
119037  * Field : dpid
119038  *
119039  * Endpoint Data PID (DPID)
119040  *
119041  * Applies to interrupt/bulk IN and OUT endpoints only.
119042  *
119043  * Contains the PID of the packet to be received or transmitted on this endpoint.
119044  * The
119045  *
119046  * application must program the PID of the first packet to be received or
119047  * transmitted on
119048  *
119049  * this endpoint, after the endpoint is activated. The applications use the
119050  * SetD1PID and
119051  *
119052  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
119053  *
119054  * 1'b0: DATA0
119055  *
119056  * 1'b1: DATA1
119057  *
119058  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
119059  *
119060  * DMA mode.
119061  *
119062  * 1'b0 RO
119063  *
119064  * Even/Odd (Micro)Frame (EO_FrNum)
119065  *
119066  * In non-Scatter/Gather DMA mode:
119067  *
119068  * Applies to isochronous IN and OUT endpoints only.
119069  *
119070  * Indicates the (micro)frame number in which the core transmits/receives
119071  * isochronous
119072  *
119073  * data for this endpoint. The application must program the even/odd (micro) frame
119074  *
119075  * number in which it intends to transmit/receive isochronous data for this
119076  * endpoint using
119077  *
119078  * the SetEvnFr and SetOddFr fields in this register.
119079  *
119080  * 1'b0: Even (micro)frame
119081  *
119082  * 1'b1: Odd (micro)frame
119083  *
119084  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
119085  * number
119086  *
119087  * in which to send data is provided in the transmit descriptor structure. The
119088  * frame in
119089  *
119090  * which data is received is updated in receive descriptor structure.
119091  *
119092  * Field Enumeration Values:
119093  *
119094  * Enum | Value | Description
119095  * :----------------------------------|:------|:-----------------------------
119096  * ALT_USB_DEV_DOEPCTL7_DPID_E_INACT | 0x0 | Endpoint Data PID not active
119097  * ALT_USB_DEV_DOEPCTL7_DPID_E_ACT | 0x1 | Endpoint Data PID active
119098  *
119099  * Field Access Macros:
119100  *
119101  */
119102 /*
119103  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_DPID
119104  *
119105  * Endpoint Data PID not active
119106  */
119107 #define ALT_USB_DEV_DOEPCTL7_DPID_E_INACT 0x0
119108 /*
119109  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_DPID
119110  *
119111  * Endpoint Data PID active
119112  */
119113 #define ALT_USB_DEV_DOEPCTL7_DPID_E_ACT 0x1
119114 
119115 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_DPID register field. */
119116 #define ALT_USB_DEV_DOEPCTL7_DPID_LSB 16
119117 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_DPID register field. */
119118 #define ALT_USB_DEV_DOEPCTL7_DPID_MSB 16
119119 /* The width in bits of the ALT_USB_DEV_DOEPCTL7_DPID register field. */
119120 #define ALT_USB_DEV_DOEPCTL7_DPID_WIDTH 1
119121 /* The mask used to set the ALT_USB_DEV_DOEPCTL7_DPID register field value. */
119122 #define ALT_USB_DEV_DOEPCTL7_DPID_SET_MSK 0x00010000
119123 /* The mask used to clear the ALT_USB_DEV_DOEPCTL7_DPID register field value. */
119124 #define ALT_USB_DEV_DOEPCTL7_DPID_CLR_MSK 0xfffeffff
119125 /* The reset value of the ALT_USB_DEV_DOEPCTL7_DPID register field. */
119126 #define ALT_USB_DEV_DOEPCTL7_DPID_RESET 0x0
119127 /* Extracts the ALT_USB_DEV_DOEPCTL7_DPID field value from a register. */
119128 #define ALT_USB_DEV_DOEPCTL7_DPID_GET(value) (((value) & 0x00010000) >> 16)
119129 /* Produces a ALT_USB_DEV_DOEPCTL7_DPID register field value suitable for setting the register. */
119130 #define ALT_USB_DEV_DOEPCTL7_DPID_SET(value) (((value) << 16) & 0x00010000)
119131 
119132 /*
119133  * Field : naksts
119134  *
119135  * NAK Status (NAKSts)
119136  *
119137  * Indicates the following:
119138  *
119139  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
119140  *
119141  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
119142  *
119143  * When either the application or the core sets this bit:
119144  *
119145  * The core stops receiving any data on an OUT endpoint, even if there is space in
119146  *
119147  * the RxFIFO to accommodate the incoming packet.
119148  *
119149  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
119150  *
119151  * endpoint, even if there data is available in the TxFIFO.
119152  *
119153  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
119154  *
119155  * if there data is available in the TxFIFO.
119156  *
119157  * Irrespective of this bit's setting, the core always responds to SETUP data
119158  * packets with
119159  *
119160  * an ACK handshake.
119161  *
119162  * Field Enumeration Values:
119163  *
119164  * Enum | Value | Description
119165  * :-------------------------------------|:------|:------------------------------------------------
119166  * ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
119167  * : | | based on the FIFO status
119168  * ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
119169  * : | | endpoint
119170  *
119171  * Field Access Macros:
119172  *
119173  */
119174 /*
119175  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_NAKSTS
119176  *
119177  * The core is transmitting non-NAK handshakes based on the FIFO status
119178  */
119179 #define ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NONNAK 0x0
119180 /*
119181  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_NAKSTS
119182  *
119183  * The core is transmitting NAK handshakes on this endpoint
119184  */
119185 #define ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NAK 0x1
119186 
119187 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */
119188 #define ALT_USB_DEV_DOEPCTL7_NAKSTS_LSB 17
119189 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */
119190 #define ALT_USB_DEV_DOEPCTL7_NAKSTS_MSB 17
119191 /* The width in bits of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */
119192 #define ALT_USB_DEV_DOEPCTL7_NAKSTS_WIDTH 1
119193 /* The mask used to set the ALT_USB_DEV_DOEPCTL7_NAKSTS register field value. */
119194 #define ALT_USB_DEV_DOEPCTL7_NAKSTS_SET_MSK 0x00020000
119195 /* The mask used to clear the ALT_USB_DEV_DOEPCTL7_NAKSTS register field value. */
119196 #define ALT_USB_DEV_DOEPCTL7_NAKSTS_CLR_MSK 0xfffdffff
119197 /* The reset value of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */
119198 #define ALT_USB_DEV_DOEPCTL7_NAKSTS_RESET 0x0
119199 /* Extracts the ALT_USB_DEV_DOEPCTL7_NAKSTS field value from a register. */
119200 #define ALT_USB_DEV_DOEPCTL7_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
119201 /* Produces a ALT_USB_DEV_DOEPCTL7_NAKSTS register field value suitable for setting the register. */
119202 #define ALT_USB_DEV_DOEPCTL7_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
119203 
119204 /*
119205  * Field : eptype
119206  *
119207  * Endpoint Type (EPType)
119208  *
119209  * This is the transfer type supported by this logical endpoint.
119210  *
119211  * 2'b00: Control
119212  *
119213  * 2'b01: Isochronous
119214  *
119215  * 2'b10: Bulk
119216  *
119217  * 2'b11: Interrupt
119218  *
119219  * Field Enumeration Values:
119220  *
119221  * Enum | Value | Description
119222  * :------------------------------------------|:------|:------------
119223  * ALT_USB_DEV_DOEPCTL7_EPTYPE_E_CTL | 0x0 | Control
119224  * ALT_USB_DEV_DOEPCTL7_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
119225  * ALT_USB_DEV_DOEPCTL7_EPTYPE_E_BULK | 0x2 | Bulk
119226  * ALT_USB_DEV_DOEPCTL7_EPTYPE_E_INTERRUP | 0x3 | Interrupt
119227  *
119228  * Field Access Macros:
119229  *
119230  */
119231 /*
119232  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE
119233  *
119234  * Control
119235  */
119236 #define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_CTL 0x0
119237 /*
119238  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE
119239  *
119240  * Isochronous
119241  */
119242 #define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_ISOCHRONOUS 0x1
119243 /*
119244  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE
119245  *
119246  * Bulk
119247  */
119248 #define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_BULK 0x2
119249 /*
119250  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE
119251  *
119252  * Interrupt
119253  */
119254 #define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_INTERRUP 0x3
119255 
119256 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */
119257 #define ALT_USB_DEV_DOEPCTL7_EPTYPE_LSB 18
119258 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */
119259 #define ALT_USB_DEV_DOEPCTL7_EPTYPE_MSB 19
119260 /* The width in bits of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */
119261 #define ALT_USB_DEV_DOEPCTL7_EPTYPE_WIDTH 2
119262 /* The mask used to set the ALT_USB_DEV_DOEPCTL7_EPTYPE register field value. */
119263 #define ALT_USB_DEV_DOEPCTL7_EPTYPE_SET_MSK 0x000c0000
119264 /* The mask used to clear the ALT_USB_DEV_DOEPCTL7_EPTYPE register field value. */
119265 #define ALT_USB_DEV_DOEPCTL7_EPTYPE_CLR_MSK 0xfff3ffff
119266 /* The reset value of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */
119267 #define ALT_USB_DEV_DOEPCTL7_EPTYPE_RESET 0x0
119268 /* Extracts the ALT_USB_DEV_DOEPCTL7_EPTYPE field value from a register. */
119269 #define ALT_USB_DEV_DOEPCTL7_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
119270 /* Produces a ALT_USB_DEV_DOEPCTL7_EPTYPE register field value suitable for setting the register. */
119271 #define ALT_USB_DEV_DOEPCTL7_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
119272 
119273 /*
119274  * Field : snp
119275  *
119276  * Snoop Mode (Snp)
119277  *
119278  * Applies to OUT endpoints only.
119279  *
119280  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
119281  *
119282  * check the correctness of OUT packets before transferring them to application
119283  * memory.
119284  *
119285  * Field Access Macros:
119286  *
119287  */
119288 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SNP register field. */
119289 #define ALT_USB_DEV_DOEPCTL7_SNP_LSB 20
119290 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SNP register field. */
119291 #define ALT_USB_DEV_DOEPCTL7_SNP_MSB 20
119292 /* The width in bits of the ALT_USB_DEV_DOEPCTL7_SNP register field. */
119293 #define ALT_USB_DEV_DOEPCTL7_SNP_WIDTH 1
119294 /* The mask used to set the ALT_USB_DEV_DOEPCTL7_SNP register field value. */
119295 #define ALT_USB_DEV_DOEPCTL7_SNP_SET_MSK 0x00100000
119296 /* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SNP register field value. */
119297 #define ALT_USB_DEV_DOEPCTL7_SNP_CLR_MSK 0xffefffff
119298 /* The reset value of the ALT_USB_DEV_DOEPCTL7_SNP register field. */
119299 #define ALT_USB_DEV_DOEPCTL7_SNP_RESET 0x0
119300 /* Extracts the ALT_USB_DEV_DOEPCTL7_SNP field value from a register. */
119301 #define ALT_USB_DEV_DOEPCTL7_SNP_GET(value) (((value) & 0x00100000) >> 20)
119302 /* Produces a ALT_USB_DEV_DOEPCTL7_SNP register field value suitable for setting the register. */
119303 #define ALT_USB_DEV_DOEPCTL7_SNP_SET(value) (((value) << 20) & 0x00100000)
119304 
119305 /*
119306  * Field : stall
119307  *
119308  * STALL Handshake (Stall)
119309  *
119310  * Applies to non-control, non-isochronous IN and OUT endpoints only.
119311  *
119312  * The application sets this bit to stall all tokens from the USB host to this
119313  * endpoint. If a
119314  *
119315  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
119316  * bit, the
119317  *
119318  * STALL bit takes priority. Only the application can clear this bit, never the
119319  * core.
119320  *
119321  * 1'b0 R_W
119322  *
119323  * Applies to control endpoints only.
119324  *
119325  * The application can only set this bit, and the core clears it, when a SETUP
119326  * token is
119327  *
119328  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
119329  * OUT
119330  *
119331  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
119332  * this bit's
119333  *
119334  * setting, the core always responds to SETUP data packets with an ACK handshake.
119335  *
119336  * Field Enumeration Values:
119337  *
119338  * Enum | Value | Description
119339  * :-----------------------------------|:------|:----------------------------
119340  * ALT_USB_DEV_DOEPCTL7_STALL_E_INACT | 0x0 | STALL All Tokens not active
119341  * ALT_USB_DEV_DOEPCTL7_STALL_E_ACT | 0x1 | STALL All Tokens active
119342  *
119343  * Field Access Macros:
119344  *
119345  */
119346 /*
119347  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_STALL
119348  *
119349  * STALL All Tokens not active
119350  */
119351 #define ALT_USB_DEV_DOEPCTL7_STALL_E_INACT 0x0
119352 /*
119353  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_STALL
119354  *
119355  * STALL All Tokens active
119356  */
119357 #define ALT_USB_DEV_DOEPCTL7_STALL_E_ACT 0x1
119358 
119359 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_STALL register field. */
119360 #define ALT_USB_DEV_DOEPCTL7_STALL_LSB 21
119361 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_STALL register field. */
119362 #define ALT_USB_DEV_DOEPCTL7_STALL_MSB 21
119363 /* The width in bits of the ALT_USB_DEV_DOEPCTL7_STALL register field. */
119364 #define ALT_USB_DEV_DOEPCTL7_STALL_WIDTH 1
119365 /* The mask used to set the ALT_USB_DEV_DOEPCTL7_STALL register field value. */
119366 #define ALT_USB_DEV_DOEPCTL7_STALL_SET_MSK 0x00200000
119367 /* The mask used to clear the ALT_USB_DEV_DOEPCTL7_STALL register field value. */
119368 #define ALT_USB_DEV_DOEPCTL7_STALL_CLR_MSK 0xffdfffff
119369 /* The reset value of the ALT_USB_DEV_DOEPCTL7_STALL register field. */
119370 #define ALT_USB_DEV_DOEPCTL7_STALL_RESET 0x0
119371 /* Extracts the ALT_USB_DEV_DOEPCTL7_STALL field value from a register. */
119372 #define ALT_USB_DEV_DOEPCTL7_STALL_GET(value) (((value) & 0x00200000) >> 21)
119373 /* Produces a ALT_USB_DEV_DOEPCTL7_STALL register field value suitable for setting the register. */
119374 #define ALT_USB_DEV_DOEPCTL7_STALL_SET(value) (((value) << 21) & 0x00200000)
119375 
119376 /*
119377  * Field : cnak
119378  *
119379  * Clear NAK (CNAK)
119380  *
119381  * A write to this bit clears the NAK bit For the endpoint.
119382  *
119383  * Field Enumeration Values:
119384  *
119385  * Enum | Value | Description
119386  * :----------------------------------|:------|:-------------
119387  * ALT_USB_DEV_DOEPCTL7_CNAK_E_INACT | 0x0 | No Clear NAK
119388  * ALT_USB_DEV_DOEPCTL7_CNAK_E_ACT | 0x1 | Clear NAK
119389  *
119390  * Field Access Macros:
119391  *
119392  */
119393 /*
119394  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_CNAK
119395  *
119396  * No Clear NAK
119397  */
119398 #define ALT_USB_DEV_DOEPCTL7_CNAK_E_INACT 0x0
119399 /*
119400  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_CNAK
119401  *
119402  * Clear NAK
119403  */
119404 #define ALT_USB_DEV_DOEPCTL7_CNAK_E_ACT 0x1
119405 
119406 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */
119407 #define ALT_USB_DEV_DOEPCTL7_CNAK_LSB 26
119408 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */
119409 #define ALT_USB_DEV_DOEPCTL7_CNAK_MSB 26
119410 /* The width in bits of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */
119411 #define ALT_USB_DEV_DOEPCTL7_CNAK_WIDTH 1
119412 /* The mask used to set the ALT_USB_DEV_DOEPCTL7_CNAK register field value. */
119413 #define ALT_USB_DEV_DOEPCTL7_CNAK_SET_MSK 0x04000000
119414 /* The mask used to clear the ALT_USB_DEV_DOEPCTL7_CNAK register field value. */
119415 #define ALT_USB_DEV_DOEPCTL7_CNAK_CLR_MSK 0xfbffffff
119416 /* The reset value of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */
119417 #define ALT_USB_DEV_DOEPCTL7_CNAK_RESET 0x0
119418 /* Extracts the ALT_USB_DEV_DOEPCTL7_CNAK field value from a register. */
119419 #define ALT_USB_DEV_DOEPCTL7_CNAK_GET(value) (((value) & 0x04000000) >> 26)
119420 /* Produces a ALT_USB_DEV_DOEPCTL7_CNAK register field value suitable for setting the register. */
119421 #define ALT_USB_DEV_DOEPCTL7_CNAK_SET(value) (((value) << 26) & 0x04000000)
119422 
119423 /*
119424  * Field : snak
119425  *
119426  * Set NAK (SNAK)
119427  *
119428  * A write to this bit sets the NAK bit For the endpoint.
119429  *
119430  * Using this bit, the application can control the transmission of NAK
119431  *
119432  * handshakes on an endpoint. The core can also Set this bit For an
119433  *
119434  * endpoint after a SETUP packet is received on that endpoint.
119435  *
119436  * Field Enumeration Values:
119437  *
119438  * Enum | Value | Description
119439  * :----------------------------------|:------|:------------
119440  * ALT_USB_DEV_DOEPCTL7_SNAK_E_INACT | 0x0 | No Set NAK
119441  * ALT_USB_DEV_DOEPCTL7_SNAK_E_ACT | 0x1 | Set NAK
119442  *
119443  * Field Access Macros:
119444  *
119445  */
119446 /*
119447  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SNAK
119448  *
119449  * No Set NAK
119450  */
119451 #define ALT_USB_DEV_DOEPCTL7_SNAK_E_INACT 0x0
119452 /*
119453  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SNAK
119454  *
119455  * Set NAK
119456  */
119457 #define ALT_USB_DEV_DOEPCTL7_SNAK_E_ACT 0x1
119458 
119459 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */
119460 #define ALT_USB_DEV_DOEPCTL7_SNAK_LSB 27
119461 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */
119462 #define ALT_USB_DEV_DOEPCTL7_SNAK_MSB 27
119463 /* The width in bits of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */
119464 #define ALT_USB_DEV_DOEPCTL7_SNAK_WIDTH 1
119465 /* The mask used to set the ALT_USB_DEV_DOEPCTL7_SNAK register field value. */
119466 #define ALT_USB_DEV_DOEPCTL7_SNAK_SET_MSK 0x08000000
119467 /* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SNAK register field value. */
119468 #define ALT_USB_DEV_DOEPCTL7_SNAK_CLR_MSK 0xf7ffffff
119469 /* The reset value of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */
119470 #define ALT_USB_DEV_DOEPCTL7_SNAK_RESET 0x0
119471 /* Extracts the ALT_USB_DEV_DOEPCTL7_SNAK field value from a register. */
119472 #define ALT_USB_DEV_DOEPCTL7_SNAK_GET(value) (((value) & 0x08000000) >> 27)
119473 /* Produces a ALT_USB_DEV_DOEPCTL7_SNAK register field value suitable for setting the register. */
119474 #define ALT_USB_DEV_DOEPCTL7_SNAK_SET(value) (((value) << 27) & 0x08000000)
119475 
119476 /*
119477  * Field : setd0pid
119478  *
119479  * Set DATA0 PID (SetD0PID)
119480  *
119481  * Applies to interrupt/bulk IN and OUT endpoints only.
119482  *
119483  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
119484  * to DATA0.
119485  *
119486  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
119487  *
119488  * DMA mode.
119489  *
119490  * 1'b0 WO
119491  *
119492  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
119493  *
119494  * Applies to isochronous IN and OUT endpoints only.
119495  *
119496  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
119497  * (micro)
119498  *
119499  * frame.
119500  *
119501  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
119502  * number
119503  *
119504  * in which to send data is in the transmit descriptor structure. The frame in
119505  * which to
119506  *
119507  * receive data is updated in receive descriptor structure.
119508  *
119509  * Field Enumeration Values:
119510  *
119511  * Enum | Value | Description
119512  * :-------------------------------------|:------|:----------------------------
119513  * ALT_USB_DEV_DOEPCTL7_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
119514  * ALT_USB_DEV_DOEPCTL7_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
119515  *
119516  * Field Access Macros:
119517  *
119518  */
119519 /*
119520  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD0PID
119521  *
119522  * Disables Set DATA0 PID
119523  */
119524 #define ALT_USB_DEV_DOEPCTL7_SETD0PID_E_DISD 0x0
119525 /*
119526  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD0PID
119527  *
119528  * Endpoint Data PID to DATA0)
119529  */
119530 #define ALT_USB_DEV_DOEPCTL7_SETD0PID_E_END 0x1
119531 
119532 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */
119533 #define ALT_USB_DEV_DOEPCTL7_SETD0PID_LSB 28
119534 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */
119535 #define ALT_USB_DEV_DOEPCTL7_SETD0PID_MSB 28
119536 /* The width in bits of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */
119537 #define ALT_USB_DEV_DOEPCTL7_SETD0PID_WIDTH 1
119538 /* The mask used to set the ALT_USB_DEV_DOEPCTL7_SETD0PID register field value. */
119539 #define ALT_USB_DEV_DOEPCTL7_SETD0PID_SET_MSK 0x10000000
119540 /* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SETD0PID register field value. */
119541 #define ALT_USB_DEV_DOEPCTL7_SETD0PID_CLR_MSK 0xefffffff
119542 /* The reset value of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */
119543 #define ALT_USB_DEV_DOEPCTL7_SETD0PID_RESET 0x0
119544 /* Extracts the ALT_USB_DEV_DOEPCTL7_SETD0PID field value from a register. */
119545 #define ALT_USB_DEV_DOEPCTL7_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
119546 /* Produces a ALT_USB_DEV_DOEPCTL7_SETD0PID register field value suitable for setting the register. */
119547 #define ALT_USB_DEV_DOEPCTL7_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
119548 
119549 /*
119550  * Field : setd1pid
119551  *
119552  * Set DATA1 PID (SetD1PID)
119553  *
119554  * Applies to interrupt/bulk IN and OUT endpoints only.
119555  *
119556  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
119557  * to DATA1.
119558  *
119559  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
119560  *
119561  * DMA mode.
119562  *
119563  * Set Odd (micro)frame (SetOddFr)
119564  *
119565  * Applies to isochronous IN and OUT endpoints only.
119566  *
119567  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
119568  *
119569  * (micro)frame.
119570  *
119571  * This field is not applicable for Scatter/Gather DMA mode.
119572  *
119573  * Field Enumeration Values:
119574  *
119575  * Enum | Value | Description
119576  * :-------------------------------------|:------|:-----------------------
119577  * ALT_USB_DEV_DOEPCTL7_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
119578  * ALT_USB_DEV_DOEPCTL7_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
119579  *
119580  * Field Access Macros:
119581  *
119582  */
119583 /*
119584  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD1PID
119585  *
119586  * Disables Set DATA1 PID
119587  */
119588 #define ALT_USB_DEV_DOEPCTL7_SETD1PID_E_DISD 0x0
119589 /*
119590  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD1PID
119591  *
119592  * Enables Set DATA1 PID
119593  */
119594 #define ALT_USB_DEV_DOEPCTL7_SETD1PID_E_END 0x1
119595 
119596 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */
119597 #define ALT_USB_DEV_DOEPCTL7_SETD1PID_LSB 29
119598 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */
119599 #define ALT_USB_DEV_DOEPCTL7_SETD1PID_MSB 29
119600 /* The width in bits of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */
119601 #define ALT_USB_DEV_DOEPCTL7_SETD1PID_WIDTH 1
119602 /* The mask used to set the ALT_USB_DEV_DOEPCTL7_SETD1PID register field value. */
119603 #define ALT_USB_DEV_DOEPCTL7_SETD1PID_SET_MSK 0x20000000
119604 /* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SETD1PID register field value. */
119605 #define ALT_USB_DEV_DOEPCTL7_SETD1PID_CLR_MSK 0xdfffffff
119606 /* The reset value of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */
119607 #define ALT_USB_DEV_DOEPCTL7_SETD1PID_RESET 0x0
119608 /* Extracts the ALT_USB_DEV_DOEPCTL7_SETD1PID field value from a register. */
119609 #define ALT_USB_DEV_DOEPCTL7_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
119610 /* Produces a ALT_USB_DEV_DOEPCTL7_SETD1PID register field value suitable for setting the register. */
119611 #define ALT_USB_DEV_DOEPCTL7_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
119612 
119613 /*
119614  * Field : epdis
119615  *
119616  * Endpoint Disable (EPDis)
119617  *
119618  * Applies to IN and OUT endpoints.
119619  *
119620  * The application sets this bit to stop transmitting/receiving data on an
119621  * endpoint, even
119622  *
119623  * before the transfer for that endpoint is complete. The application must wait for
119624  * the
119625  *
119626  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
119627  * clears
119628  *
119629  * this bit before setting the Endpoint Disabled interrupt. The application must
119630  * set this bit
119631  *
119632  * only if Endpoint Enable is already set for this endpoint.
119633  *
119634  * Field Enumeration Values:
119635  *
119636  * Enum | Value | Description
119637  * :-----------------------------------|:------|:--------------------
119638  * ALT_USB_DEV_DOEPCTL7_EPDIS_E_INACT | 0x0 | No Endpoint Disable
119639  * ALT_USB_DEV_DOEPCTL7_EPDIS_E_ACT | 0x1 | Endpoint Disable
119640  *
119641  * Field Access Macros:
119642  *
119643  */
119644 /*
119645  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPDIS
119646  *
119647  * No Endpoint Disable
119648  */
119649 #define ALT_USB_DEV_DOEPCTL7_EPDIS_E_INACT 0x0
119650 /*
119651  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPDIS
119652  *
119653  * Endpoint Disable
119654  */
119655 #define ALT_USB_DEV_DOEPCTL7_EPDIS_E_ACT 0x1
119656 
119657 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */
119658 #define ALT_USB_DEV_DOEPCTL7_EPDIS_LSB 30
119659 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */
119660 #define ALT_USB_DEV_DOEPCTL7_EPDIS_MSB 30
119661 /* The width in bits of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */
119662 #define ALT_USB_DEV_DOEPCTL7_EPDIS_WIDTH 1
119663 /* The mask used to set the ALT_USB_DEV_DOEPCTL7_EPDIS register field value. */
119664 #define ALT_USB_DEV_DOEPCTL7_EPDIS_SET_MSK 0x40000000
119665 /* The mask used to clear the ALT_USB_DEV_DOEPCTL7_EPDIS register field value. */
119666 #define ALT_USB_DEV_DOEPCTL7_EPDIS_CLR_MSK 0xbfffffff
119667 /* The reset value of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */
119668 #define ALT_USB_DEV_DOEPCTL7_EPDIS_RESET 0x0
119669 /* Extracts the ALT_USB_DEV_DOEPCTL7_EPDIS field value from a register. */
119670 #define ALT_USB_DEV_DOEPCTL7_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
119671 /* Produces a ALT_USB_DEV_DOEPCTL7_EPDIS register field value suitable for setting the register. */
119672 #define ALT_USB_DEV_DOEPCTL7_EPDIS_SET(value) (((value) << 30) & 0x40000000)
119673 
119674 /*
119675  * Field : epena
119676  *
119677  * Endpoint Enable (EPEna)
119678  *
119679  * Applies to IN and OUT endpoints.
119680  *
119681  * When Scatter/Gather DMA mode is enabled,
119682  *
119683  * For IN endpoints this bit indicates that the descriptor structure and data
119684  * buffer with
119685  *
119686  * data ready to transmit is setup.
119687  *
119688  * For OUT endpoint it indicates that the descriptor structure and data buffer to
119689  *
119690  * receive data is setup.
119691  *
119692  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
119693  *
119694  * DMA mode:
119695  *
119696  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
119697  * the
119698  *
119699  * endpoint.
119700  *
119701  * * For OUT endpoints, this bit indicates that the application has allocated the
119702  *
119703  * memory to start receiving data from the USB.
119704  *
119705  * * The core clears this bit before setting any of the following interrupts on
119706  * this
119707  *
119708  * endpoint:
119709  *
119710  * SETUP Phase Done
119711  *
119712  * Endpoint Disabled
119713  *
119714  * Transfer Completed
119715  *
119716  * Note: For control endpoints in DMA mode, this bit must be set to be able to
119717  * transfer
119718  *
119719  * SETUP data packets in memory.
119720  *
119721  * Field Enumeration Values:
119722  *
119723  * Enum | Value | Description
119724  * :-----------------------------------|:------|:-------------------------
119725  * ALT_USB_DEV_DOEPCTL7_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
119726  * ALT_USB_DEV_DOEPCTL7_EPENA_E_ACT | 0x1 | Endpoint Enable active
119727  *
119728  * Field Access Macros:
119729  *
119730  */
119731 /*
119732  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPENA
119733  *
119734  * Endpoint Enable inactive
119735  */
119736 #define ALT_USB_DEV_DOEPCTL7_EPENA_E_INACT 0x0
119737 /*
119738  * Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPENA
119739  *
119740  * Endpoint Enable active
119741  */
119742 #define ALT_USB_DEV_DOEPCTL7_EPENA_E_ACT 0x1
119743 
119744 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */
119745 #define ALT_USB_DEV_DOEPCTL7_EPENA_LSB 31
119746 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */
119747 #define ALT_USB_DEV_DOEPCTL7_EPENA_MSB 31
119748 /* The width in bits of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */
119749 #define ALT_USB_DEV_DOEPCTL7_EPENA_WIDTH 1
119750 /* The mask used to set the ALT_USB_DEV_DOEPCTL7_EPENA register field value. */
119751 #define ALT_USB_DEV_DOEPCTL7_EPENA_SET_MSK 0x80000000
119752 /* The mask used to clear the ALT_USB_DEV_DOEPCTL7_EPENA register field value. */
119753 #define ALT_USB_DEV_DOEPCTL7_EPENA_CLR_MSK 0x7fffffff
119754 /* The reset value of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */
119755 #define ALT_USB_DEV_DOEPCTL7_EPENA_RESET 0x0
119756 /* Extracts the ALT_USB_DEV_DOEPCTL7_EPENA field value from a register. */
119757 #define ALT_USB_DEV_DOEPCTL7_EPENA_GET(value) (((value) & 0x80000000) >> 31)
119758 /* Produces a ALT_USB_DEV_DOEPCTL7_EPENA register field value suitable for setting the register. */
119759 #define ALT_USB_DEV_DOEPCTL7_EPENA_SET(value) (((value) << 31) & 0x80000000)
119760 
119761 #ifndef __ASSEMBLY__
119762 /*
119763  * WARNING: The C register and register group struct declarations are provided for
119764  * convenience and illustrative purposes. They should, however, be used with
119765  * caution as the C language standard provides no guarantees about the alignment or
119766  * atomicity of device memory accesses. The recommended practice for writing
119767  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
119768  * alt_write_word() functions.
119769  *
119770  * The struct declaration for register ALT_USB_DEV_DOEPCTL7.
119771  */
119772 struct ALT_USB_DEV_DOEPCTL7_s
119773 {
119774  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL7_MPS */
119775  uint32_t : 4; /* *UNDEFINED* */
119776  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL7_USBACTEP */
119777  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL7_DPID */
119778  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL7_NAKSTS */
119779  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL7_EPTYPE */
119780  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL7_SNP */
119781  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL7_STALL */
119782  uint32_t : 4; /* *UNDEFINED* */
119783  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL7_CNAK */
119784  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL7_SNAK */
119785  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL7_SETD0PID */
119786  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL7_SETD1PID */
119787  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL7_EPDIS */
119788  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL7_EPENA */
119789 };
119790 
119791 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL7. */
119792 typedef volatile struct ALT_USB_DEV_DOEPCTL7_s ALT_USB_DEV_DOEPCTL7_t;
119793 #endif /* __ASSEMBLY__ */
119794 
119795 /* The reset value of the ALT_USB_DEV_DOEPCTL7 register. */
119796 #define ALT_USB_DEV_DOEPCTL7_RESET 0x00000000
119797 /* The byte offset of the ALT_USB_DEV_DOEPCTL7 register from the beginning of the component. */
119798 #define ALT_USB_DEV_DOEPCTL7_OFST 0x3e0
119799 /* The address of the ALT_USB_DEV_DOEPCTL7 register. */
119800 #define ALT_USB_DEV_DOEPCTL7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL7_OFST))
119801 
119802 /*
119803  * Register : doepint7
119804  *
119805  * Device OUT Endpoint 7 Interrupt Register
119806  *
119807  * Register Layout
119808  *
119809  * Bits | Access | Reset | Description
119810  * :--------|:-------|:------|:------------------------------------
119811  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_XFERCOMPL
119812  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_EPDISBLD
119813  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_AHBERR
119814  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_SETUP
119815  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS
119816  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_STSPHSERCVD
119817  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP
119818  * [7] | ??? | 0x0 | *UNDEFINED*
119819  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_OUTPKTERR
119820  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_BNAINTR
119821  * [10] | ??? | 0x0 | *UNDEFINED*
119822  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_PKTDRPSTS
119823  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_BBLEERR
119824  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_NAKINTRPT
119825  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_NYETINTRPT
119826  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_STUPPKTRCVD
119827  * [31:16] | ??? | 0x0 | *UNDEFINED*
119828  *
119829  */
119830 /*
119831  * Field : xfercompl
119832  *
119833  * Transfer Completed Interrupt (XferCompl)
119834  *
119835  * Applies to IN and OUT endpoints.
119836  *
119837  * When Scatter/Gather DMA mode is enabled
119838  *
119839  * * For IN endpoint this field indicates that the requested data
119840  *
119841  * from the descriptor is moved from external system memory
119842  *
119843  * to internal FIFO.
119844  *
119845  * * For OUT endpoint this field indicates that the requested
119846  *
119847  * data from the internal FIFO is moved to external system
119848  *
119849  * memory. This interrupt is generated only when the
119850  *
119851  * corresponding endpoint descriptor is closed, and the IOC
119852  *
119853  * bit For the corresponding descriptor is Set.
119854  *
119855  * When Scatter/Gather DMA mode is disabled, this field
119856  *
119857  * indicates that the programmed transfer is complete on the
119858  *
119859  * AHB as well as on the USB, For this endpoint.
119860  *
119861  * Field Enumeration Values:
119862  *
119863  * Enum | Value | Description
119864  * :---------------------------------------|:------|:-----------------------------
119865  * ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_INACT | 0x0 | No Interrupt
119866  * ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
119867  *
119868  * Field Access Macros:
119869  *
119870  */
119871 /*
119872  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_XFERCOMPL
119873  *
119874  * No Interrupt
119875  */
119876 #define ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_INACT 0x0
119877 /*
119878  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_XFERCOMPL
119879  *
119880  * Transfer Completed Interrupt
119881  */
119882 #define ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_ACT 0x1
119883 
119884 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */
119885 #define ALT_USB_DEV_DOEPINT7_XFERCOMPL_LSB 0
119886 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */
119887 #define ALT_USB_DEV_DOEPINT7_XFERCOMPL_MSB 0
119888 /* The width in bits of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */
119889 #define ALT_USB_DEV_DOEPINT7_XFERCOMPL_WIDTH 1
119890 /* The mask used to set the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field value. */
119891 #define ALT_USB_DEV_DOEPINT7_XFERCOMPL_SET_MSK 0x00000001
119892 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field value. */
119893 #define ALT_USB_DEV_DOEPINT7_XFERCOMPL_CLR_MSK 0xfffffffe
119894 /* The reset value of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */
119895 #define ALT_USB_DEV_DOEPINT7_XFERCOMPL_RESET 0x0
119896 /* Extracts the ALT_USB_DEV_DOEPINT7_XFERCOMPL field value from a register. */
119897 #define ALT_USB_DEV_DOEPINT7_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
119898 /* Produces a ALT_USB_DEV_DOEPINT7_XFERCOMPL register field value suitable for setting the register. */
119899 #define ALT_USB_DEV_DOEPINT7_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
119900 
119901 /*
119902  * Field : epdisbld
119903  *
119904  * Endpoint Disabled Interrupt (EPDisbld)
119905  *
119906  * Applies to IN and OUT endpoints.
119907  *
119908  * This bit indicates that the endpoint is disabled per the
119909  *
119910  * application's request.
119911  *
119912  * Field Enumeration Values:
119913  *
119914  * Enum | Value | Description
119915  * :--------------------------------------|:------|:----------------------------
119916  * ALT_USB_DEV_DOEPINT7_EPDISBLD_E_INACT | 0x0 | No Interrupt
119917  * ALT_USB_DEV_DOEPINT7_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
119918  *
119919  * Field Access Macros:
119920  *
119921  */
119922 /*
119923  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_EPDISBLD
119924  *
119925  * No Interrupt
119926  */
119927 #define ALT_USB_DEV_DOEPINT7_EPDISBLD_E_INACT 0x0
119928 /*
119929  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_EPDISBLD
119930  *
119931  * Endpoint Disabled Interrupt
119932  */
119933 #define ALT_USB_DEV_DOEPINT7_EPDISBLD_E_ACT 0x1
119934 
119935 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */
119936 #define ALT_USB_DEV_DOEPINT7_EPDISBLD_LSB 1
119937 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */
119938 #define ALT_USB_DEV_DOEPINT7_EPDISBLD_MSB 1
119939 /* The width in bits of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */
119940 #define ALT_USB_DEV_DOEPINT7_EPDISBLD_WIDTH 1
119941 /* The mask used to set the ALT_USB_DEV_DOEPINT7_EPDISBLD register field value. */
119942 #define ALT_USB_DEV_DOEPINT7_EPDISBLD_SET_MSK 0x00000002
119943 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_EPDISBLD register field value. */
119944 #define ALT_USB_DEV_DOEPINT7_EPDISBLD_CLR_MSK 0xfffffffd
119945 /* The reset value of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */
119946 #define ALT_USB_DEV_DOEPINT7_EPDISBLD_RESET 0x0
119947 /* Extracts the ALT_USB_DEV_DOEPINT7_EPDISBLD field value from a register. */
119948 #define ALT_USB_DEV_DOEPINT7_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
119949 /* Produces a ALT_USB_DEV_DOEPINT7_EPDISBLD register field value suitable for setting the register. */
119950 #define ALT_USB_DEV_DOEPINT7_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
119951 
119952 /*
119953  * Field : ahberr
119954  *
119955  * AHB Error (AHBErr)
119956  *
119957  * Applies to IN and OUT endpoints.
119958  *
119959  * This is generated only in Internal DMA mode when there is an
119960  *
119961  * AHB error during an AHB read/write. The application can read
119962  *
119963  * the corresponding endpoint DMA address register to get the
119964  *
119965  * error address.
119966  *
119967  * Field Enumeration Values:
119968  *
119969  * Enum | Value | Description
119970  * :------------------------------------|:------|:--------------------
119971  * ALT_USB_DEV_DOEPINT7_AHBERR_E_INACT | 0x0 | No Interrupt
119972  * ALT_USB_DEV_DOEPINT7_AHBERR_E_ACT | 0x1 | AHB Error interrupt
119973  *
119974  * Field Access Macros:
119975  *
119976  */
119977 /*
119978  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_AHBERR
119979  *
119980  * No Interrupt
119981  */
119982 #define ALT_USB_DEV_DOEPINT7_AHBERR_E_INACT 0x0
119983 /*
119984  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_AHBERR
119985  *
119986  * AHB Error interrupt
119987  */
119988 #define ALT_USB_DEV_DOEPINT7_AHBERR_E_ACT 0x1
119989 
119990 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */
119991 #define ALT_USB_DEV_DOEPINT7_AHBERR_LSB 2
119992 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */
119993 #define ALT_USB_DEV_DOEPINT7_AHBERR_MSB 2
119994 /* The width in bits of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */
119995 #define ALT_USB_DEV_DOEPINT7_AHBERR_WIDTH 1
119996 /* The mask used to set the ALT_USB_DEV_DOEPINT7_AHBERR register field value. */
119997 #define ALT_USB_DEV_DOEPINT7_AHBERR_SET_MSK 0x00000004
119998 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_AHBERR register field value. */
119999 #define ALT_USB_DEV_DOEPINT7_AHBERR_CLR_MSK 0xfffffffb
120000 /* The reset value of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */
120001 #define ALT_USB_DEV_DOEPINT7_AHBERR_RESET 0x0
120002 /* Extracts the ALT_USB_DEV_DOEPINT7_AHBERR field value from a register. */
120003 #define ALT_USB_DEV_DOEPINT7_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
120004 /* Produces a ALT_USB_DEV_DOEPINT7_AHBERR register field value suitable for setting the register. */
120005 #define ALT_USB_DEV_DOEPINT7_AHBERR_SET(value) (((value) << 2) & 0x00000004)
120006 
120007 /*
120008  * Field : setup
120009  *
120010  * SETUP Phase Done (SetUp)
120011  *
120012  * Applies to control OUT endpoints only.
120013  *
120014  * Indicates that the SETUP phase For the control endpoint is
120015  *
120016  * complete and no more back-to-back SETUP packets were
120017  *
120018  * received For the current control transfer. On this interrupt, the
120019  *
120020  * application can decode the received SETUP data packet.
120021  *
120022  * Field Enumeration Values:
120023  *
120024  * Enum | Value | Description
120025  * :-----------------------------------|:------|:--------------------
120026  * ALT_USB_DEV_DOEPINT7_SETUP_E_INACT | 0x0 | No SETUP Phase Done
120027  * ALT_USB_DEV_DOEPINT7_SETUP_E_ACT | 0x1 | SETUP Phase Done
120028  *
120029  * Field Access Macros:
120030  *
120031  */
120032 /*
120033  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_SETUP
120034  *
120035  * No SETUP Phase Done
120036  */
120037 #define ALT_USB_DEV_DOEPINT7_SETUP_E_INACT 0x0
120038 /*
120039  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_SETUP
120040  *
120041  * SETUP Phase Done
120042  */
120043 #define ALT_USB_DEV_DOEPINT7_SETUP_E_ACT 0x1
120044 
120045 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_SETUP register field. */
120046 #define ALT_USB_DEV_DOEPINT7_SETUP_LSB 3
120047 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_SETUP register field. */
120048 #define ALT_USB_DEV_DOEPINT7_SETUP_MSB 3
120049 /* The width in bits of the ALT_USB_DEV_DOEPINT7_SETUP register field. */
120050 #define ALT_USB_DEV_DOEPINT7_SETUP_WIDTH 1
120051 /* The mask used to set the ALT_USB_DEV_DOEPINT7_SETUP register field value. */
120052 #define ALT_USB_DEV_DOEPINT7_SETUP_SET_MSK 0x00000008
120053 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_SETUP register field value. */
120054 #define ALT_USB_DEV_DOEPINT7_SETUP_CLR_MSK 0xfffffff7
120055 /* The reset value of the ALT_USB_DEV_DOEPINT7_SETUP register field. */
120056 #define ALT_USB_DEV_DOEPINT7_SETUP_RESET 0x0
120057 /* Extracts the ALT_USB_DEV_DOEPINT7_SETUP field value from a register. */
120058 #define ALT_USB_DEV_DOEPINT7_SETUP_GET(value) (((value) & 0x00000008) >> 3)
120059 /* Produces a ALT_USB_DEV_DOEPINT7_SETUP register field value suitable for setting the register. */
120060 #define ALT_USB_DEV_DOEPINT7_SETUP_SET(value) (((value) << 3) & 0x00000008)
120061 
120062 /*
120063  * Field : outtknepdis
120064  *
120065  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
120066  *
120067  * Applies only to control OUT endpoints.
120068  *
120069  * Indicates that an OUT token was received when the endpoint
120070  *
120071  * was not yet enabled. This interrupt is asserted on the endpoint
120072  *
120073  * For which the OUT token was received.
120074  *
120075  * Field Enumeration Values:
120076  *
120077  * Enum | Value | Description
120078  * :-----------------------------------------|:------|:---------------------------------------------
120079  * ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
120080  * ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
120081  *
120082  * Field Access Macros:
120083  *
120084  */
120085 /*
120086  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS
120087  *
120088  * No OUT Token Received When Endpoint Disabled
120089  */
120090 #define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_INACT 0x0
120091 /*
120092  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS
120093  *
120094  * OUT Token Received When Endpoint Disabled
120095  */
120096 #define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_ACT 0x1
120097 
120098 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */
120099 #define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_LSB 4
120100 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */
120101 #define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_MSB 4
120102 /* The width in bits of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */
120103 #define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_WIDTH 1
120104 /* The mask used to set the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field value. */
120105 #define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_SET_MSK 0x00000010
120106 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field value. */
120107 #define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_CLR_MSK 0xffffffef
120108 /* The reset value of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */
120109 #define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_RESET 0x0
120110 /* Extracts the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS field value from a register. */
120111 #define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
120112 /* Produces a ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field value suitable for setting the register. */
120113 #define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
120114 
120115 /*
120116  * Field : stsphsercvd
120117  *
120118  * Status Phase Received For Control Write (StsPhseRcvd)
120119  *
120120  * This interrupt is valid only For Control OUT endpoints and only in
120121  *
120122  * Scatter Gather DMA mode.
120123  *
120124  * This interrupt is generated only after the core has transferred all
120125  *
120126  * the data that the host has sent during the data phase of a control
120127  *
120128  * write transfer, to the system memory buffer.
120129  *
120130  * The interrupt indicates to the application that the host has
120131  *
120132  * switched from data phase to the status phase of a Control Write
120133  *
120134  * transfer. The application can use this interrupt to ACK or STALL
120135  *
120136  * the Status phase, after it has decoded the data phase. This is
120137  *
120138  * applicable only in Case of Scatter Gather DMA mode.
120139  *
120140  * Field Enumeration Values:
120141  *
120142  * Enum | Value | Description
120143  * :-----------------------------------------|:------|:-------------------------------------------
120144  * ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
120145  * ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
120146  *
120147  * Field Access Macros:
120148  *
120149  */
120150 /*
120151  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_STSPHSERCVD
120152  *
120153  * No Status Phase Received for Control Write
120154  */
120155 #define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_INACT 0x0
120156 /*
120157  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_STSPHSERCVD
120158  *
120159  * Status Phase Received for Control Write
120160  */
120161 #define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_ACT 0x1
120162 
120163 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */
120164 #define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_LSB 5
120165 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */
120166 #define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_MSB 5
120167 /* The width in bits of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */
120168 #define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_WIDTH 1
120169 /* The mask used to set the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field value. */
120170 #define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_SET_MSK 0x00000020
120171 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field value. */
120172 #define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_CLR_MSK 0xffffffdf
120173 /* The reset value of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */
120174 #define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_RESET 0x0
120175 /* Extracts the ALT_USB_DEV_DOEPINT7_STSPHSERCVD field value from a register. */
120176 #define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
120177 /* Produces a ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field value suitable for setting the register. */
120178 #define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
120179 
120180 /*
120181  * Field : back2backsetup
120182  *
120183  * Back-to-Back SETUP Packets Received (Back2BackSETup)
120184  *
120185  * Applies to Control OUT endpoints only.
120186  *
120187  * This bit indicates that the core has received more than three
120188  *
120189  * back-to-back SETUP packets For this particular endpoint. For
120190  *
120191  * information about handling this interrupt,
120192  *
120193  * Field Enumeration Values:
120194  *
120195  * Enum | Value | Description
120196  * :--------------------------------------------|:------|:---------------------------------------
120197  * ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
120198  * ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
120199  *
120200  * Field Access Macros:
120201  *
120202  */
120203 /*
120204  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP
120205  *
120206  * No Back-to-Back SETUP Packets Received
120207  */
120208 #define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_INACT 0x0
120209 /*
120210  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP
120211  *
120212  * Back-to-Back SETUP Packets Received
120213  */
120214 #define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_ACT 0x1
120215 
120216 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */
120217 #define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_LSB 6
120218 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */
120219 #define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_MSB 6
120220 /* The width in bits of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */
120221 #define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_WIDTH 1
120222 /* The mask used to set the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field value. */
120223 #define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_SET_MSK 0x00000040
120224 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field value. */
120225 #define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_CLR_MSK 0xffffffbf
120226 /* The reset value of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */
120227 #define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_RESET 0x0
120228 /* Extracts the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP field value from a register. */
120229 #define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
120230 /* Produces a ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field value suitable for setting the register. */
120231 #define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
120232 
120233 /*
120234  * Field : outpkterr
120235  *
120236  * OUT Packet Error (OutPktErr)
120237  *
120238  * Applies to OUT endpoints Only
120239  *
120240  * This interrupt is valid only when thresholding is enabled. This interrupt is
120241  * asserted when the
120242  *
120243  * core detects an overflow or a CRC error For non-Isochronous
120244  *
120245  * OUT packet.
120246  *
120247  * Field Enumeration Values:
120248  *
120249  * Enum | Value | Description
120250  * :---------------------------------------|:------|:--------------------
120251  * ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
120252  * ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
120253  *
120254  * Field Access Macros:
120255  *
120256  */
120257 /*
120258  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTPKTERR
120259  *
120260  * No OUT Packet Error
120261  */
120262 #define ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_INACT 0x0
120263 /*
120264  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTPKTERR
120265  *
120266  * OUT Packet Error
120267  */
120268 #define ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_ACT 0x1
120269 
120270 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */
120271 #define ALT_USB_DEV_DOEPINT7_OUTPKTERR_LSB 8
120272 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */
120273 #define ALT_USB_DEV_DOEPINT7_OUTPKTERR_MSB 8
120274 /* The width in bits of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */
120275 #define ALT_USB_DEV_DOEPINT7_OUTPKTERR_WIDTH 1
120276 /* The mask used to set the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field value. */
120277 #define ALT_USB_DEV_DOEPINT7_OUTPKTERR_SET_MSK 0x00000100
120278 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field value. */
120279 #define ALT_USB_DEV_DOEPINT7_OUTPKTERR_CLR_MSK 0xfffffeff
120280 /* The reset value of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */
120281 #define ALT_USB_DEV_DOEPINT7_OUTPKTERR_RESET 0x0
120282 /* Extracts the ALT_USB_DEV_DOEPINT7_OUTPKTERR field value from a register. */
120283 #define ALT_USB_DEV_DOEPINT7_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
120284 /* Produces a ALT_USB_DEV_DOEPINT7_OUTPKTERR register field value suitable for setting the register. */
120285 #define ALT_USB_DEV_DOEPINT7_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
120286 
120287 /*
120288  * Field : bnaintr
120289  *
120290  * BNA (Buffer Not Available) Interrupt (BNAIntr)
120291  *
120292  * This bit is valid only when Scatter/Gather DMA mode is enabled.
120293  *
120294  * The core generates this interrupt when the descriptor accessed
120295  *
120296  * is not ready For the Core to process, such as Host busy or DMA
120297  *
120298  * done
120299  *
120300  * Field Enumeration Values:
120301  *
120302  * Enum | Value | Description
120303  * :-------------------------------------|:------|:--------------
120304  * ALT_USB_DEV_DOEPINT7_BNAINTR_E_INACT | 0x0 | No interrupt
120305  * ALT_USB_DEV_DOEPINT7_BNAINTR_E_ACT | 0x1 | BNA interrupt
120306  *
120307  * Field Access Macros:
120308  *
120309  */
120310 /*
120311  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BNAINTR
120312  *
120313  * No interrupt
120314  */
120315 #define ALT_USB_DEV_DOEPINT7_BNAINTR_E_INACT 0x0
120316 /*
120317  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BNAINTR
120318  *
120319  * BNA interrupt
120320  */
120321 #define ALT_USB_DEV_DOEPINT7_BNAINTR_E_ACT 0x1
120322 
120323 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */
120324 #define ALT_USB_DEV_DOEPINT7_BNAINTR_LSB 9
120325 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */
120326 #define ALT_USB_DEV_DOEPINT7_BNAINTR_MSB 9
120327 /* The width in bits of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */
120328 #define ALT_USB_DEV_DOEPINT7_BNAINTR_WIDTH 1
120329 /* The mask used to set the ALT_USB_DEV_DOEPINT7_BNAINTR register field value. */
120330 #define ALT_USB_DEV_DOEPINT7_BNAINTR_SET_MSK 0x00000200
120331 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_BNAINTR register field value. */
120332 #define ALT_USB_DEV_DOEPINT7_BNAINTR_CLR_MSK 0xfffffdff
120333 /* The reset value of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */
120334 #define ALT_USB_DEV_DOEPINT7_BNAINTR_RESET 0x0
120335 /* Extracts the ALT_USB_DEV_DOEPINT7_BNAINTR field value from a register. */
120336 #define ALT_USB_DEV_DOEPINT7_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
120337 /* Produces a ALT_USB_DEV_DOEPINT7_BNAINTR register field value suitable for setting the register. */
120338 #define ALT_USB_DEV_DOEPINT7_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
120339 
120340 /*
120341  * Field : pktdrpsts
120342  *
120343  * Packet Drop Status (PktDrpSts)
120344  *
120345  * This bit indicates to the application that an ISOC OUT packet has been dropped.
120346  * This
120347  *
120348  * bit does not have an associated mask bit and does not generate an interrupt.
120349  *
120350  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
120351  * transfer
120352  *
120353  * interrupt feature is selected.
120354  *
120355  * Field Enumeration Values:
120356  *
120357  * Enum | Value | Description
120358  * :---------------------------------------|:------|:-----------------------------
120359  * ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_INACT | 0x0 | No interrupt
120360  * ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
120361  *
120362  * Field Access Macros:
120363  *
120364  */
120365 /*
120366  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_PKTDRPSTS
120367  *
120368  * No interrupt
120369  */
120370 #define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_INACT 0x0
120371 /*
120372  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_PKTDRPSTS
120373  *
120374  * Packet Drop Status interrupt
120375  */
120376 #define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_ACT 0x1
120377 
120378 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */
120379 #define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_LSB 11
120380 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */
120381 #define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_MSB 11
120382 /* The width in bits of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */
120383 #define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_WIDTH 1
120384 /* The mask used to set the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field value. */
120385 #define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_SET_MSK 0x00000800
120386 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field value. */
120387 #define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_CLR_MSK 0xfffff7ff
120388 /* The reset value of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */
120389 #define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_RESET 0x0
120390 /* Extracts the ALT_USB_DEV_DOEPINT7_PKTDRPSTS field value from a register. */
120391 #define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
120392 /* Produces a ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field value suitable for setting the register. */
120393 #define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
120394 
120395 /*
120396  * Field : bbleerr
120397  *
120398  * NAK Interrupt (BbleErr)
120399  *
120400  * The core generates this interrupt when babble is received for the endpoint.
120401  *
120402  * Field Enumeration Values:
120403  *
120404  * Enum | Value | Description
120405  * :-------------------------------------|:------|:------------------
120406  * ALT_USB_DEV_DOEPINT7_BBLEERR_E_INACT | 0x0 | No interrupt
120407  * ALT_USB_DEV_DOEPINT7_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
120408  *
120409  * Field Access Macros:
120410  *
120411  */
120412 /*
120413  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BBLEERR
120414  *
120415  * No interrupt
120416  */
120417 #define ALT_USB_DEV_DOEPINT7_BBLEERR_E_INACT 0x0
120418 /*
120419  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_BBLEERR
120420  *
120421  * BbleErr interrupt
120422  */
120423 #define ALT_USB_DEV_DOEPINT7_BBLEERR_E_ACT 0x1
120424 
120425 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */
120426 #define ALT_USB_DEV_DOEPINT7_BBLEERR_LSB 12
120427 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */
120428 #define ALT_USB_DEV_DOEPINT7_BBLEERR_MSB 12
120429 /* The width in bits of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */
120430 #define ALT_USB_DEV_DOEPINT7_BBLEERR_WIDTH 1
120431 /* The mask used to set the ALT_USB_DEV_DOEPINT7_BBLEERR register field value. */
120432 #define ALT_USB_DEV_DOEPINT7_BBLEERR_SET_MSK 0x00001000
120433 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_BBLEERR register field value. */
120434 #define ALT_USB_DEV_DOEPINT7_BBLEERR_CLR_MSK 0xffffefff
120435 /* The reset value of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */
120436 #define ALT_USB_DEV_DOEPINT7_BBLEERR_RESET 0x0
120437 /* Extracts the ALT_USB_DEV_DOEPINT7_BBLEERR field value from a register. */
120438 #define ALT_USB_DEV_DOEPINT7_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
120439 /* Produces a ALT_USB_DEV_DOEPINT7_BBLEERR register field value suitable for setting the register. */
120440 #define ALT_USB_DEV_DOEPINT7_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
120441 
120442 /*
120443  * Field : nakintrpt
120444  *
120445  * NAK Interrupt (NAKInterrupt)
120446  *
120447  * The core generates this interrupt when a NAK is transmitted or received by the
120448  * device.
120449  *
120450  * In case of isochronous IN endpoints the interrupt gets generated when a zero
120451  * length
120452  *
120453  * packet is transmitted due to un-availability of data in the TXFifo.
120454  *
120455  * Field Enumeration Values:
120456  *
120457  * Enum | Value | Description
120458  * :---------------------------------------|:------|:--------------
120459  * ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_INACT | 0x0 | No interrupt
120460  * ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
120461  *
120462  * Field Access Macros:
120463  *
120464  */
120465 /*
120466  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_NAKINTRPT
120467  *
120468  * No interrupt
120469  */
120470 #define ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_INACT 0x0
120471 /*
120472  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_NAKINTRPT
120473  *
120474  * NAK Interrupt
120475  */
120476 #define ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_ACT 0x1
120477 
120478 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */
120479 #define ALT_USB_DEV_DOEPINT7_NAKINTRPT_LSB 13
120480 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */
120481 #define ALT_USB_DEV_DOEPINT7_NAKINTRPT_MSB 13
120482 /* The width in bits of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */
120483 #define ALT_USB_DEV_DOEPINT7_NAKINTRPT_WIDTH 1
120484 /* The mask used to set the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field value. */
120485 #define ALT_USB_DEV_DOEPINT7_NAKINTRPT_SET_MSK 0x00002000
120486 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field value. */
120487 #define ALT_USB_DEV_DOEPINT7_NAKINTRPT_CLR_MSK 0xffffdfff
120488 /* The reset value of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */
120489 #define ALT_USB_DEV_DOEPINT7_NAKINTRPT_RESET 0x0
120490 /* Extracts the ALT_USB_DEV_DOEPINT7_NAKINTRPT field value from a register. */
120491 #define ALT_USB_DEV_DOEPINT7_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
120492 /* Produces a ALT_USB_DEV_DOEPINT7_NAKINTRPT register field value suitable for setting the register. */
120493 #define ALT_USB_DEV_DOEPINT7_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
120494 
120495 /*
120496  * Field : nyetintrpt
120497  *
120498  * NYET Interrupt (NYETIntrpt)
120499  *
120500  * The core generates this interrupt when a NYET response is transmitted for a non
120501  * isochronous OUT endpoint.
120502  *
120503  * Field Enumeration Values:
120504  *
120505  * Enum | Value | Description
120506  * :----------------------------------------|:------|:---------------
120507  * ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_INACT | 0x0 | No interrupt
120508  * ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
120509  *
120510  * Field Access Macros:
120511  *
120512  */
120513 /*
120514  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_NYETINTRPT
120515  *
120516  * No interrupt
120517  */
120518 #define ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_INACT 0x0
120519 /*
120520  * Enumerated value for register field ALT_USB_DEV_DOEPINT7_NYETINTRPT
120521  *
120522  * NYET Interrupt
120523  */
120524 #define ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_ACT 0x1
120525 
120526 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */
120527 #define ALT_USB_DEV_DOEPINT7_NYETINTRPT_LSB 14
120528 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */
120529 #define ALT_USB_DEV_DOEPINT7_NYETINTRPT_MSB 14
120530 /* The width in bits of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */
120531 #define ALT_USB_DEV_DOEPINT7_NYETINTRPT_WIDTH 1
120532 /* The mask used to set the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field value. */
120533 #define ALT_USB_DEV_DOEPINT7_NYETINTRPT_SET_MSK 0x00004000
120534 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field value. */
120535 #define ALT_USB_DEV_DOEPINT7_NYETINTRPT_CLR_MSK 0xffffbfff
120536 /* The reset value of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */
120537 #define ALT_USB_DEV_DOEPINT7_NYETINTRPT_RESET 0x0
120538 /* Extracts the ALT_USB_DEV_DOEPINT7_NYETINTRPT field value from a register. */
120539 #define ALT_USB_DEV_DOEPINT7_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
120540 /* Produces a ALT_USB_DEV_DOEPINT7_NYETINTRPT register field value suitable for setting the register. */
120541 #define ALT_USB_DEV_DOEPINT7_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
120542 
120543 /*
120544  * Field : stuppktrcvd
120545  *
120546  * Setup Packet Received
120547  *
120548  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
120549  *
120550  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
120551  *
120552  * setup data. There is only one Setup packet per buffer. On receiving a
120553  *
120554  * Setup packet, the DWC_otg core closes the buffer and disables the
120555  *
120556  * corresponding endpoint. The application has to re-enable the endpoint to
120557  *
120558  * receive any OUT data for the Control Transfer and reprogram the buffer
120559  *
120560  * start address.
120561  *
120562  * Note: Because of the above behavior, the DWC_otg core can receive any
120563  *
120564  * number of back to back setup packets and one buffer for every setup
120565  *
120566  * packet is used.
120567  *
120568  * 1'b0: No Setup packet received
120569  *
120570  * 1'b1: Setup packet received
120571  *
120572  * Reset: 1'b0
120573  *
120574  * Field Access Macros:
120575  *
120576  */
120577 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field. */
120578 #define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_LSB 15
120579 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field. */
120580 #define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_MSB 15
120581 /* The width in bits of the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field. */
120582 #define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_WIDTH 1
120583 /* The mask used to set the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field value. */
120584 #define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_SET_MSK 0x00008000
120585 /* The mask used to clear the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field value. */
120586 #define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_CLR_MSK 0xffff7fff
120587 /* The reset value of the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field. */
120588 #define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_RESET 0x0
120589 /* Extracts the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD field value from a register. */
120590 #define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
120591 /* Produces a ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field value suitable for setting the register. */
120592 #define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
120593 
120594 #ifndef __ASSEMBLY__
120595 /*
120596  * WARNING: The C register and register group struct declarations are provided for
120597  * convenience and illustrative purposes. They should, however, be used with
120598  * caution as the C language standard provides no guarantees about the alignment or
120599  * atomicity of device memory accesses. The recommended practice for writing
120600  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
120601  * alt_write_word() functions.
120602  *
120603  * The struct declaration for register ALT_USB_DEV_DOEPINT7.
120604  */
120605 struct ALT_USB_DEV_DOEPINT7_s
120606 {
120607  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT7_XFERCOMPL */
120608  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT7_EPDISBLD */
120609  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT7_AHBERR */
120610  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT7_SETUP */
120611  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS */
120612  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT7_STSPHSERCVD */
120613  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP */
120614  uint32_t : 1; /* *UNDEFINED* */
120615  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT7_OUTPKTERR */
120616  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT7_BNAINTR */
120617  uint32_t : 1; /* *UNDEFINED* */
120618  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT7_PKTDRPSTS */
120619  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT7_BBLEERR */
120620  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT7_NAKINTRPT */
120621  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT7_NYETINTRPT */
120622  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT7_STUPPKTRCVD */
120623  uint32_t : 16; /* *UNDEFINED* */
120624 };
120625 
120626 /* The typedef declaration for register ALT_USB_DEV_DOEPINT7. */
120627 typedef volatile struct ALT_USB_DEV_DOEPINT7_s ALT_USB_DEV_DOEPINT7_t;
120628 #endif /* __ASSEMBLY__ */
120629 
120630 /* The reset value of the ALT_USB_DEV_DOEPINT7 register. */
120631 #define ALT_USB_DEV_DOEPINT7_RESET 0x00000000
120632 /* The byte offset of the ALT_USB_DEV_DOEPINT7 register from the beginning of the component. */
120633 #define ALT_USB_DEV_DOEPINT7_OFST 0x3e8
120634 /* The address of the ALT_USB_DEV_DOEPINT7 register. */
120635 #define ALT_USB_DEV_DOEPINT7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT7_OFST))
120636 
120637 /*
120638  * Register : doeptsiz7
120639  *
120640  * Device OUT Endpoint 7 Transfer Size Register
120641  *
120642  * Register Layout
120643  *
120644  * Bits | Access | Reset | Description
120645  * :--------|:-------|:------|:-------------------------------
120646  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ7_XFERSIZE
120647  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ7_PKTCNT
120648  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ7_RXDPID
120649  * [31] | ??? | 0x0 | *UNDEFINED*
120650  *
120651  */
120652 /*
120653  * Field : xfersize
120654  *
120655  * Transfer Size (XferSize)
120656  *
120657  * Indicates the transfer size in bytes For endpoint 0. The core
120658  *
120659  * interrupts the application only after it has exhausted the transfer
120660  *
120661  * size amount of data. The transfer size can be Set to the
120662  *
120663  * maximum packet size of the endpoint, to be interrupted at the
120664  *
120665  * end of each packet.
120666  *
120667  * The core decrements this field every time a packet is read from
120668  *
120669  * the RxFIFO and written to the external memory.
120670  *
120671  * Field Access Macros:
120672  *
120673  */
120674 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */
120675 #define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_LSB 0
120676 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */
120677 #define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_MSB 18
120678 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */
120679 #define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_WIDTH 19
120680 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field value. */
120681 #define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_SET_MSK 0x0007ffff
120682 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field value. */
120683 #define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_CLR_MSK 0xfff80000
120684 /* The reset value of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */
120685 #define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_RESET 0x0
120686 /* Extracts the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE field value from a register. */
120687 #define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
120688 /* Produces a ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field value suitable for setting the register. */
120689 #define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
120690 
120691 /*
120692  * Field : pktcnt
120693  *
120694  * Packet Count (PktCnt)
120695  *
120696  * This field is decremented to zero after a packet is written into the
120697  *
120698  * RxFIFO.
120699  *
120700  * Field Access Macros:
120701  *
120702  */
120703 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */
120704 #define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_LSB 19
120705 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */
120706 #define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_MSB 28
120707 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */
120708 #define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_WIDTH 10
120709 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field value. */
120710 #define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_SET_MSK 0x1ff80000
120711 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field value. */
120712 #define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_CLR_MSK 0xe007ffff
120713 /* The reset value of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */
120714 #define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_RESET 0x0
120715 /* Extracts the ALT_USB_DEV_DOEPTSIZ7_PKTCNT field value from a register. */
120716 #define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
120717 /* Produces a ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field value suitable for setting the register. */
120718 #define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
120719 
120720 /*
120721  * Field : rxdpid
120722  *
120723  * Applies to isochronous OUT endpoints only.
120724  *
120725  * This is the data PID received in the last packet for this endpoint.
120726  *
120727  * 2'b00: DATA0
120728  *
120729  * 2'b01: DATA2
120730  *
120731  * 2'b10: DATA1
120732  *
120733  * 2'b11: MDATA
120734  *
120735  * SETUP Packet Count (SUPCnt)
120736  *
120737  * Applies to control OUT Endpoints only.
120738  *
120739  * This field specifies the number of back-to-back SETUP data
120740  *
120741  * packets the endpoint can receive.
120742  *
120743  * 2'b01: 1 packet
120744  *
120745  * 2'b10: 2 packets
120746  *
120747  * 2'b11: 3 packets
120748  *
120749  * Field Enumeration Values:
120750  *
120751  * Enum | Value | Description
120752  * :-----------------------------------------|:------|:-------------------
120753  * ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA0 | 0x0 | DATA0
120754  * ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
120755  * ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
120756  * ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
120757  *
120758  * Field Access Macros:
120759  *
120760  */
120761 /*
120762  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID
120763  *
120764  * DATA0
120765  */
120766 #define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA0 0x0
120767 /*
120768  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID
120769  *
120770  * DATA2 or 1 packet
120771  */
120772 #define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA2PKT1 0x1
120773 /*
120774  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID
120775  *
120776  * DATA1 or 2 packets
120777  */
120778 #define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA1PKT2 0x2
120779 /*
120780  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID
120781  *
120782  * MDATA or 3 packets
120783  */
120784 #define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_MDATAPKT3 0x3
120785 
120786 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */
120787 #define ALT_USB_DEV_DOEPTSIZ7_RXDPID_LSB 29
120788 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */
120789 #define ALT_USB_DEV_DOEPTSIZ7_RXDPID_MSB 30
120790 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */
120791 #define ALT_USB_DEV_DOEPTSIZ7_RXDPID_WIDTH 2
120792 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field value. */
120793 #define ALT_USB_DEV_DOEPTSIZ7_RXDPID_SET_MSK 0x60000000
120794 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field value. */
120795 #define ALT_USB_DEV_DOEPTSIZ7_RXDPID_CLR_MSK 0x9fffffff
120796 /* The reset value of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */
120797 #define ALT_USB_DEV_DOEPTSIZ7_RXDPID_RESET 0x0
120798 /* Extracts the ALT_USB_DEV_DOEPTSIZ7_RXDPID field value from a register. */
120799 #define ALT_USB_DEV_DOEPTSIZ7_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
120800 /* Produces a ALT_USB_DEV_DOEPTSIZ7_RXDPID register field value suitable for setting the register. */
120801 #define ALT_USB_DEV_DOEPTSIZ7_RXDPID_SET(value) (((value) << 29) & 0x60000000)
120802 
120803 #ifndef __ASSEMBLY__
120804 /*
120805  * WARNING: The C register and register group struct declarations are provided for
120806  * convenience and illustrative purposes. They should, however, be used with
120807  * caution as the C language standard provides no guarantees about the alignment or
120808  * atomicity of device memory accesses. The recommended practice for writing
120809  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
120810  * alt_write_word() functions.
120811  *
120812  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ7.
120813  */
120814 struct ALT_USB_DEV_DOEPTSIZ7_s
120815 {
120816  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ7_XFERSIZE */
120817  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ7_PKTCNT */
120818  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ7_RXDPID */
120819  uint32_t : 1; /* *UNDEFINED* */
120820 };
120821 
120822 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ7. */
120823 typedef volatile struct ALT_USB_DEV_DOEPTSIZ7_s ALT_USB_DEV_DOEPTSIZ7_t;
120824 #endif /* __ASSEMBLY__ */
120825 
120826 /* The reset value of the ALT_USB_DEV_DOEPTSIZ7 register. */
120827 #define ALT_USB_DEV_DOEPTSIZ7_RESET 0x00000000
120828 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ7 register from the beginning of the component. */
120829 #define ALT_USB_DEV_DOEPTSIZ7_OFST 0x3f0
120830 /* The address of the ALT_USB_DEV_DOEPTSIZ7 register. */
120831 #define ALT_USB_DEV_DOEPTSIZ7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ7_OFST))
120832 
120833 /*
120834  * Register : doepdma7
120835  *
120836  * Device OUT Endpoint 7 DMA Address Register
120837  *
120838  * Register Layout
120839  *
120840  * Bits | Access | Reset | Description
120841  * :-------|:-------|:--------|:------------------------------
120842  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA7_DOEPDMA7
120843  *
120844  */
120845 /*
120846  * Field : doepdma7
120847  *
120848  * Holds the start address of the external memory for storing or fetching endpoint
120849  *
120850  * data.
120851  *
120852  * Note: For control endpoints, this field stores control OUT data packets as well
120853  * as
120854  *
120855  * SETUP transaction data packets. When more than three SETUP packets are
120856  *
120857  * received back-to-back, the SETUP data packet in the memory is overwritten.
120858  *
120859  * This register is incremented on every AHB transaction. The application can give
120860  *
120861  * only a DWORD-aligned address.
120862  *
120863  * When Scatter/Gather DMA mode is not enabled, the application programs the
120864  *
120865  * start address value in this field.
120866  *
120867  * When Scatter/Gather DMA mode is enabled, this field indicates the base
120868  *
120869  * pointer for the descriptor list.
120870  *
120871  * Field Access Macros:
120872  *
120873  */
120874 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field. */
120875 #define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_LSB 0
120876 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field. */
120877 #define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_MSB 31
120878 /* The width in bits of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field. */
120879 #define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_WIDTH 32
120880 /* The mask used to set the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field value. */
120881 #define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_SET_MSK 0xffffffff
120882 /* The mask used to clear the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field value. */
120883 #define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_CLR_MSK 0x00000000
120884 /* The reset value of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field is UNKNOWN. */
120885 #define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_RESET 0x0
120886 /* Extracts the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 field value from a register. */
120887 #define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_GET(value) (((value) & 0xffffffff) >> 0)
120888 /* Produces a ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field value suitable for setting the register. */
120889 #define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_SET(value) (((value) << 0) & 0xffffffff)
120890 
120891 #ifndef __ASSEMBLY__
120892 /*
120893  * WARNING: The C register and register group struct declarations are provided for
120894  * convenience and illustrative purposes. They should, however, be used with
120895  * caution as the C language standard provides no guarantees about the alignment or
120896  * atomicity of device memory accesses. The recommended practice for writing
120897  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
120898  * alt_write_word() functions.
120899  *
120900  * The struct declaration for register ALT_USB_DEV_DOEPDMA7.
120901  */
120902 struct ALT_USB_DEV_DOEPDMA7_s
120903 {
120904  uint32_t doepdma7 : 32; /* ALT_USB_DEV_DOEPDMA7_DOEPDMA7 */
120905 };
120906 
120907 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA7. */
120908 typedef volatile struct ALT_USB_DEV_DOEPDMA7_s ALT_USB_DEV_DOEPDMA7_t;
120909 #endif /* __ASSEMBLY__ */
120910 
120911 /* The reset value of the ALT_USB_DEV_DOEPDMA7 register. */
120912 #define ALT_USB_DEV_DOEPDMA7_RESET 0x00000000
120913 /* The byte offset of the ALT_USB_DEV_DOEPDMA7 register from the beginning of the component. */
120914 #define ALT_USB_DEV_DOEPDMA7_OFST 0x3f4
120915 /* The address of the ALT_USB_DEV_DOEPDMA7 register. */
120916 #define ALT_USB_DEV_DOEPDMA7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA7_OFST))
120917 
120918 /*
120919  * Register : doepdmab7
120920  *
120921  * Device OUT Endpoint 7 Buffer Address Register
120922  *
120923  * Register Layout
120924  *
120925  * Bits | Access | Reset | Description
120926  * :-------|:-------|:--------|:--------------------------------
120927  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7
120928  *
120929  */
120930 /*
120931  * Field : doepdmab7
120932  *
120933  * Holds the current buffer address.This register is updated as and when the data
120934  *
120935  * transfer for the corresponding end point is in progress.
120936  *
120937  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
120938  * is
120939  *
120940  * reserved.
120941  *
120942  * Field Access Macros:
120943  *
120944  */
120945 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field. */
120946 #define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_LSB 0
120947 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field. */
120948 #define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_MSB 31
120949 /* The width in bits of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field. */
120950 #define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_WIDTH 32
120951 /* The mask used to set the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field value. */
120952 #define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_SET_MSK 0xffffffff
120953 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field value. */
120954 #define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_CLR_MSK 0x00000000
120955 /* The reset value of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field is UNKNOWN. */
120956 #define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_RESET 0x0
120957 /* Extracts the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 field value from a register. */
120958 #define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_GET(value) (((value) & 0xffffffff) >> 0)
120959 /* Produces a ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field value suitable for setting the register. */
120960 #define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_SET(value) (((value) << 0) & 0xffffffff)
120961 
120962 #ifndef __ASSEMBLY__
120963 /*
120964  * WARNING: The C register and register group struct declarations are provided for
120965  * convenience and illustrative purposes. They should, however, be used with
120966  * caution as the C language standard provides no guarantees about the alignment or
120967  * atomicity of device memory accesses. The recommended practice for writing
120968  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
120969  * alt_write_word() functions.
120970  *
120971  * The struct declaration for register ALT_USB_DEV_DOEPDMAB7.
120972  */
120973 struct ALT_USB_DEV_DOEPDMAB7_s
120974 {
120975  const uint32_t doepdmab7 : 32; /* ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 */
120976 };
120977 
120978 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB7. */
120979 typedef volatile struct ALT_USB_DEV_DOEPDMAB7_s ALT_USB_DEV_DOEPDMAB7_t;
120980 #endif /* __ASSEMBLY__ */
120981 
120982 /* The reset value of the ALT_USB_DEV_DOEPDMAB7 register. */
120983 #define ALT_USB_DEV_DOEPDMAB7_RESET 0x00000000
120984 /* The byte offset of the ALT_USB_DEV_DOEPDMAB7 register from the beginning of the component. */
120985 #define ALT_USB_DEV_DOEPDMAB7_OFST 0x3fc
120986 /* The address of the ALT_USB_DEV_DOEPDMAB7 register. */
120987 #define ALT_USB_DEV_DOEPDMAB7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB7_OFST))
120988 
120989 /*
120990  * Register : doepctl8
120991  *
120992  * Device Control OUT Endpoint 8 Control Register
120993  *
120994  * Register Layout
120995  *
120996  * Bits | Access | Reset | Description
120997  * :--------|:---------|:------|:------------------------------
120998  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL8_MPS
120999  * [14:11] | ??? | 0x0 | *UNDEFINED*
121000  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL8_USBACTEP
121001  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL8_DPID
121002  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL8_NAKSTS
121003  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL8_EPTYPE
121004  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL8_SNP
121005  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL8_STALL
121006  * [25:22] | ??? | 0x0 | *UNDEFINED*
121007  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL8_CNAK
121008  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL8_SNAK
121009  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL8_SETD0PID
121010  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL8_SETD1PID
121011  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL8_EPDIS
121012  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL8_EPENA
121013  *
121014  */
121015 /*
121016  * Field : mps
121017  *
121018  * Maximum Packet Size (MPS)
121019  *
121020  * The application must program this field with the maximum packet size for the
121021  * current
121022  *
121023  * logical endpoint. This value is in bytes.
121024  *
121025  * Field Access Macros:
121026  *
121027  */
121028 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_MPS register field. */
121029 #define ALT_USB_DEV_DOEPCTL8_MPS_LSB 0
121030 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_MPS register field. */
121031 #define ALT_USB_DEV_DOEPCTL8_MPS_MSB 10
121032 /* The width in bits of the ALT_USB_DEV_DOEPCTL8_MPS register field. */
121033 #define ALT_USB_DEV_DOEPCTL8_MPS_WIDTH 11
121034 /* The mask used to set the ALT_USB_DEV_DOEPCTL8_MPS register field value. */
121035 #define ALT_USB_DEV_DOEPCTL8_MPS_SET_MSK 0x000007ff
121036 /* The mask used to clear the ALT_USB_DEV_DOEPCTL8_MPS register field value. */
121037 #define ALT_USB_DEV_DOEPCTL8_MPS_CLR_MSK 0xfffff800
121038 /* The reset value of the ALT_USB_DEV_DOEPCTL8_MPS register field. */
121039 #define ALT_USB_DEV_DOEPCTL8_MPS_RESET 0x0
121040 /* Extracts the ALT_USB_DEV_DOEPCTL8_MPS field value from a register. */
121041 #define ALT_USB_DEV_DOEPCTL8_MPS_GET(value) (((value) & 0x000007ff) >> 0)
121042 /* Produces a ALT_USB_DEV_DOEPCTL8_MPS register field value suitable for setting the register. */
121043 #define ALT_USB_DEV_DOEPCTL8_MPS_SET(value) (((value) << 0) & 0x000007ff)
121044 
121045 /*
121046  * Field : usbactep
121047  *
121048  * USB Active Endpoint (USBActEP)
121049  *
121050  * Indicates whether this endpoint is active in the current configuration and
121051  * interface. The
121052  *
121053  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
121054  * reset. After
121055  *
121056  * receiving the SetConfiguration and SetInterface commands, the application must
121057  *
121058  * program endpoint registers accordingly and set this bit.
121059  *
121060  * Field Enumeration Values:
121061  *
121062  * Enum | Value | Description
121063  * :-------------------------------------|:------|:--------------------
121064  * ALT_USB_DEV_DOEPCTL8_USBACTEP_E_DISD | 0x0 | Not Active
121065  * ALT_USB_DEV_DOEPCTL8_USBACTEP_E_END | 0x1 | USB Active Endpoint
121066  *
121067  * Field Access Macros:
121068  *
121069  */
121070 /*
121071  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_USBACTEP
121072  *
121073  * Not Active
121074  */
121075 #define ALT_USB_DEV_DOEPCTL8_USBACTEP_E_DISD 0x0
121076 /*
121077  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_USBACTEP
121078  *
121079  * USB Active Endpoint
121080  */
121081 #define ALT_USB_DEV_DOEPCTL8_USBACTEP_E_END 0x1
121082 
121083 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */
121084 #define ALT_USB_DEV_DOEPCTL8_USBACTEP_LSB 15
121085 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */
121086 #define ALT_USB_DEV_DOEPCTL8_USBACTEP_MSB 15
121087 /* The width in bits of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */
121088 #define ALT_USB_DEV_DOEPCTL8_USBACTEP_WIDTH 1
121089 /* The mask used to set the ALT_USB_DEV_DOEPCTL8_USBACTEP register field value. */
121090 #define ALT_USB_DEV_DOEPCTL8_USBACTEP_SET_MSK 0x00008000
121091 /* The mask used to clear the ALT_USB_DEV_DOEPCTL8_USBACTEP register field value. */
121092 #define ALT_USB_DEV_DOEPCTL8_USBACTEP_CLR_MSK 0xffff7fff
121093 /* The reset value of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */
121094 #define ALT_USB_DEV_DOEPCTL8_USBACTEP_RESET 0x0
121095 /* Extracts the ALT_USB_DEV_DOEPCTL8_USBACTEP field value from a register. */
121096 #define ALT_USB_DEV_DOEPCTL8_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
121097 /* Produces a ALT_USB_DEV_DOEPCTL8_USBACTEP register field value suitable for setting the register. */
121098 #define ALT_USB_DEV_DOEPCTL8_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
121099 
121100 /*
121101  * Field : dpid
121102  *
121103  * Endpoint Data PID (DPID)
121104  *
121105  * Applies to interrupt/bulk IN and OUT endpoints only.
121106  *
121107  * Contains the PID of the packet to be received or transmitted on this endpoint.
121108  * The
121109  *
121110  * application must program the PID of the first packet to be received or
121111  * transmitted on
121112  *
121113  * this endpoint, after the endpoint is activated. The applications use the
121114  * SetD1PID and
121115  *
121116  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
121117  *
121118  * 1'b0: DATA0
121119  *
121120  * 1'b1: DATA1
121121  *
121122  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
121123  *
121124  * DMA mode.
121125  *
121126  * 1'b0 RO
121127  *
121128  * Even/Odd (Micro)Frame (EO_FrNum)
121129  *
121130  * In non-Scatter/Gather DMA mode:
121131  *
121132  * Applies to isochronous IN and OUT endpoints only.
121133  *
121134  * Indicates the (micro)frame number in which the core transmits/receives
121135  * isochronous
121136  *
121137  * data for this endpoint. The application must program the even/odd (micro) frame
121138  *
121139  * number in which it intends to transmit/receive isochronous data for this
121140  * endpoint using
121141  *
121142  * the SetEvnFr and SetOddFr fields in this register.
121143  *
121144  * 1'b0: Even (micro)frame
121145  *
121146  * 1'b1: Odd (micro)frame
121147  *
121148  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
121149  * number
121150  *
121151  * in which to send data is provided in the transmit descriptor structure. The
121152  * frame in
121153  *
121154  * which data is received is updated in receive descriptor structure.
121155  *
121156  * Field Enumeration Values:
121157  *
121158  * Enum | Value | Description
121159  * :----------------------------------|:------|:-----------------------------
121160  * ALT_USB_DEV_DOEPCTL8_DPID_E_INACT | 0x0 | Endpoint Data PID not active
121161  * ALT_USB_DEV_DOEPCTL8_DPID_E_ACT | 0x1 | Endpoint Data PID active
121162  *
121163  * Field Access Macros:
121164  *
121165  */
121166 /*
121167  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_DPID
121168  *
121169  * Endpoint Data PID not active
121170  */
121171 #define ALT_USB_DEV_DOEPCTL8_DPID_E_INACT 0x0
121172 /*
121173  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_DPID
121174  *
121175  * Endpoint Data PID active
121176  */
121177 #define ALT_USB_DEV_DOEPCTL8_DPID_E_ACT 0x1
121178 
121179 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_DPID register field. */
121180 #define ALT_USB_DEV_DOEPCTL8_DPID_LSB 16
121181 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_DPID register field. */
121182 #define ALT_USB_DEV_DOEPCTL8_DPID_MSB 16
121183 /* The width in bits of the ALT_USB_DEV_DOEPCTL8_DPID register field. */
121184 #define ALT_USB_DEV_DOEPCTL8_DPID_WIDTH 1
121185 /* The mask used to set the ALT_USB_DEV_DOEPCTL8_DPID register field value. */
121186 #define ALT_USB_DEV_DOEPCTL8_DPID_SET_MSK 0x00010000
121187 /* The mask used to clear the ALT_USB_DEV_DOEPCTL8_DPID register field value. */
121188 #define ALT_USB_DEV_DOEPCTL8_DPID_CLR_MSK 0xfffeffff
121189 /* The reset value of the ALT_USB_DEV_DOEPCTL8_DPID register field. */
121190 #define ALT_USB_DEV_DOEPCTL8_DPID_RESET 0x0
121191 /* Extracts the ALT_USB_DEV_DOEPCTL8_DPID field value from a register. */
121192 #define ALT_USB_DEV_DOEPCTL8_DPID_GET(value) (((value) & 0x00010000) >> 16)
121193 /* Produces a ALT_USB_DEV_DOEPCTL8_DPID register field value suitable for setting the register. */
121194 #define ALT_USB_DEV_DOEPCTL8_DPID_SET(value) (((value) << 16) & 0x00010000)
121195 
121196 /*
121197  * Field : naksts
121198  *
121199  * NAK Status (NAKSts)
121200  *
121201  * Indicates the following:
121202  *
121203  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
121204  *
121205  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
121206  *
121207  * When either the application or the core sets this bit:
121208  *
121209  * The core stops receiving any data on an OUT endpoint, even if there is space in
121210  *
121211  * the RxFIFO to accommodate the incoming packet.
121212  *
121213  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
121214  *
121215  * endpoint, even if there data is available in the TxFIFO.
121216  *
121217  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
121218  *
121219  * if there data is available in the TxFIFO.
121220  *
121221  * Irrespective of this bit's setting, the core always responds to SETUP data
121222  * packets with
121223  *
121224  * an ACK handshake.
121225  *
121226  * Field Enumeration Values:
121227  *
121228  * Enum | Value | Description
121229  * :-------------------------------------|:------|:------------------------------------------------
121230  * ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
121231  * : | | based on the FIFO status
121232  * ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
121233  * : | | endpoint
121234  *
121235  * Field Access Macros:
121236  *
121237  */
121238 /*
121239  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_NAKSTS
121240  *
121241  * The core is transmitting non-NAK handshakes based on the FIFO status
121242  */
121243 #define ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NONNAK 0x0
121244 /*
121245  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_NAKSTS
121246  *
121247  * The core is transmitting NAK handshakes on this endpoint
121248  */
121249 #define ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NAK 0x1
121250 
121251 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */
121252 #define ALT_USB_DEV_DOEPCTL8_NAKSTS_LSB 17
121253 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */
121254 #define ALT_USB_DEV_DOEPCTL8_NAKSTS_MSB 17
121255 /* The width in bits of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */
121256 #define ALT_USB_DEV_DOEPCTL8_NAKSTS_WIDTH 1
121257 /* The mask used to set the ALT_USB_DEV_DOEPCTL8_NAKSTS register field value. */
121258 #define ALT_USB_DEV_DOEPCTL8_NAKSTS_SET_MSK 0x00020000
121259 /* The mask used to clear the ALT_USB_DEV_DOEPCTL8_NAKSTS register field value. */
121260 #define ALT_USB_DEV_DOEPCTL8_NAKSTS_CLR_MSK 0xfffdffff
121261 /* The reset value of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */
121262 #define ALT_USB_DEV_DOEPCTL8_NAKSTS_RESET 0x0
121263 /* Extracts the ALT_USB_DEV_DOEPCTL8_NAKSTS field value from a register. */
121264 #define ALT_USB_DEV_DOEPCTL8_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
121265 /* Produces a ALT_USB_DEV_DOEPCTL8_NAKSTS register field value suitable for setting the register. */
121266 #define ALT_USB_DEV_DOEPCTL8_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
121267 
121268 /*
121269  * Field : eptype
121270  *
121271  * Endpoint Type (EPType)
121272  *
121273  * This is the transfer type supported by this logical endpoint.
121274  *
121275  * 2'b00: Control
121276  *
121277  * 2'b01: Isochronous
121278  *
121279  * 2'b10: Bulk
121280  *
121281  * 2'b11: Interrupt
121282  *
121283  * Field Enumeration Values:
121284  *
121285  * Enum | Value | Description
121286  * :------------------------------------------|:------|:------------
121287  * ALT_USB_DEV_DOEPCTL8_EPTYPE_E_CTL | 0x0 | Control
121288  * ALT_USB_DEV_DOEPCTL8_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
121289  * ALT_USB_DEV_DOEPCTL8_EPTYPE_E_BULK | 0x2 | Bulk
121290  * ALT_USB_DEV_DOEPCTL8_EPTYPE_E_INTERRUP | 0x3 | Interrupt
121291  *
121292  * Field Access Macros:
121293  *
121294  */
121295 /*
121296  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE
121297  *
121298  * Control
121299  */
121300 #define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_CTL 0x0
121301 /*
121302  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE
121303  *
121304  * Isochronous
121305  */
121306 #define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_ISOCHRONOUS 0x1
121307 /*
121308  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE
121309  *
121310  * Bulk
121311  */
121312 #define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_BULK 0x2
121313 /*
121314  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE
121315  *
121316  * Interrupt
121317  */
121318 #define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_INTERRUP 0x3
121319 
121320 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */
121321 #define ALT_USB_DEV_DOEPCTL8_EPTYPE_LSB 18
121322 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */
121323 #define ALT_USB_DEV_DOEPCTL8_EPTYPE_MSB 19
121324 /* The width in bits of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */
121325 #define ALT_USB_DEV_DOEPCTL8_EPTYPE_WIDTH 2
121326 /* The mask used to set the ALT_USB_DEV_DOEPCTL8_EPTYPE register field value. */
121327 #define ALT_USB_DEV_DOEPCTL8_EPTYPE_SET_MSK 0x000c0000
121328 /* The mask used to clear the ALT_USB_DEV_DOEPCTL8_EPTYPE register field value. */
121329 #define ALT_USB_DEV_DOEPCTL8_EPTYPE_CLR_MSK 0xfff3ffff
121330 /* The reset value of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */
121331 #define ALT_USB_DEV_DOEPCTL8_EPTYPE_RESET 0x0
121332 /* Extracts the ALT_USB_DEV_DOEPCTL8_EPTYPE field value from a register. */
121333 #define ALT_USB_DEV_DOEPCTL8_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
121334 /* Produces a ALT_USB_DEV_DOEPCTL8_EPTYPE register field value suitable for setting the register. */
121335 #define ALT_USB_DEV_DOEPCTL8_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
121336 
121337 /*
121338  * Field : snp
121339  *
121340  * Snoop Mode (Snp)
121341  *
121342  * Applies to OUT endpoints only.
121343  *
121344  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
121345  *
121346  * check the correctness of OUT packets before transferring them to application
121347  * memory.
121348  *
121349  * Field Enumeration Values:
121350  *
121351  * Enum | Value | Description
121352  * :-------------------------------|:------|:-------------------
121353  * ALT_USB_DEV_DOEPCTL8_SNP_E_DIS | 0x0 | Disable Snoop Mode
121354  * ALT_USB_DEV_DOEPCTL8_SNP_E_EN | 0x1 | Enable Snoop Mode
121355  *
121356  * Field Access Macros:
121357  *
121358  */
121359 /*
121360  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNP
121361  *
121362  * Disable Snoop Mode
121363  */
121364 #define ALT_USB_DEV_DOEPCTL8_SNP_E_DIS 0x0
121365 /*
121366  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNP
121367  *
121368  * Enable Snoop Mode
121369  */
121370 #define ALT_USB_DEV_DOEPCTL8_SNP_E_EN 0x1
121371 
121372 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SNP register field. */
121373 #define ALT_USB_DEV_DOEPCTL8_SNP_LSB 20
121374 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SNP register field. */
121375 #define ALT_USB_DEV_DOEPCTL8_SNP_MSB 20
121376 /* The width in bits of the ALT_USB_DEV_DOEPCTL8_SNP register field. */
121377 #define ALT_USB_DEV_DOEPCTL8_SNP_WIDTH 1
121378 /* The mask used to set the ALT_USB_DEV_DOEPCTL8_SNP register field value. */
121379 #define ALT_USB_DEV_DOEPCTL8_SNP_SET_MSK 0x00100000
121380 /* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SNP register field value. */
121381 #define ALT_USB_DEV_DOEPCTL8_SNP_CLR_MSK 0xffefffff
121382 /* The reset value of the ALT_USB_DEV_DOEPCTL8_SNP register field. */
121383 #define ALT_USB_DEV_DOEPCTL8_SNP_RESET 0x0
121384 /* Extracts the ALT_USB_DEV_DOEPCTL8_SNP field value from a register. */
121385 #define ALT_USB_DEV_DOEPCTL8_SNP_GET(value) (((value) & 0x00100000) >> 20)
121386 /* Produces a ALT_USB_DEV_DOEPCTL8_SNP register field value suitable for setting the register. */
121387 #define ALT_USB_DEV_DOEPCTL8_SNP_SET(value) (((value) << 20) & 0x00100000)
121388 
121389 /*
121390  * Field : stall
121391  *
121392  * STALL Handshake (Stall)
121393  *
121394  * Applies to non-control, non-isochronous IN and OUT endpoints only.
121395  *
121396  * The application sets this bit to stall all tokens from the USB host to this
121397  * endpoint. If a
121398  *
121399  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
121400  * bit, the
121401  *
121402  * STALL bit takes priority. Only the application can clear this bit, never the
121403  * core.
121404  *
121405  * 1'b0 R_W
121406  *
121407  * Applies to control endpoints only.
121408  *
121409  * The application can only set this bit, and the core clears it, when a SETUP
121410  * token is
121411  *
121412  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
121413  * OUT
121414  *
121415  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
121416  * this bit's
121417  *
121418  * setting, the core always responds to SETUP data packets with an ACK handshake.
121419  *
121420  * Field Enumeration Values:
121421  *
121422  * Enum | Value | Description
121423  * :-----------------------------------|:------|:----------------------------
121424  * ALT_USB_DEV_DOEPCTL8_STALL_E_INACT | 0x0 | STALL All Tokens not active
121425  * ALT_USB_DEV_DOEPCTL8_STALL_E_ACT | 0x1 | STALL All Tokens active
121426  *
121427  * Field Access Macros:
121428  *
121429  */
121430 /*
121431  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_STALL
121432  *
121433  * STALL All Tokens not active
121434  */
121435 #define ALT_USB_DEV_DOEPCTL8_STALL_E_INACT 0x0
121436 /*
121437  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_STALL
121438  *
121439  * STALL All Tokens active
121440  */
121441 #define ALT_USB_DEV_DOEPCTL8_STALL_E_ACT 0x1
121442 
121443 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_STALL register field. */
121444 #define ALT_USB_DEV_DOEPCTL8_STALL_LSB 21
121445 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_STALL register field. */
121446 #define ALT_USB_DEV_DOEPCTL8_STALL_MSB 21
121447 /* The width in bits of the ALT_USB_DEV_DOEPCTL8_STALL register field. */
121448 #define ALT_USB_DEV_DOEPCTL8_STALL_WIDTH 1
121449 /* The mask used to set the ALT_USB_DEV_DOEPCTL8_STALL register field value. */
121450 #define ALT_USB_DEV_DOEPCTL8_STALL_SET_MSK 0x00200000
121451 /* The mask used to clear the ALT_USB_DEV_DOEPCTL8_STALL register field value. */
121452 #define ALT_USB_DEV_DOEPCTL8_STALL_CLR_MSK 0xffdfffff
121453 /* The reset value of the ALT_USB_DEV_DOEPCTL8_STALL register field. */
121454 #define ALT_USB_DEV_DOEPCTL8_STALL_RESET 0x0
121455 /* Extracts the ALT_USB_DEV_DOEPCTL8_STALL field value from a register. */
121456 #define ALT_USB_DEV_DOEPCTL8_STALL_GET(value) (((value) & 0x00200000) >> 21)
121457 /* Produces a ALT_USB_DEV_DOEPCTL8_STALL register field value suitable for setting the register. */
121458 #define ALT_USB_DEV_DOEPCTL8_STALL_SET(value) (((value) << 21) & 0x00200000)
121459 
121460 /*
121461  * Field : cnak
121462  *
121463  * Clear NAK (CNAK)
121464  *
121465  * A write to this bit clears the NAK bit For the endpoint.
121466  *
121467  * Field Enumeration Values:
121468  *
121469  * Enum | Value | Description
121470  * :----------------------------------|:------|:-------------
121471  * ALT_USB_DEV_DOEPCTL8_CNAK_E_INACT | 0x0 | No Clear NAK
121472  * ALT_USB_DEV_DOEPCTL8_CNAK_E_ACT | 0x1 | Clear NAK
121473  *
121474  * Field Access Macros:
121475  *
121476  */
121477 /*
121478  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_CNAK
121479  *
121480  * No Clear NAK
121481  */
121482 #define ALT_USB_DEV_DOEPCTL8_CNAK_E_INACT 0x0
121483 /*
121484  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_CNAK
121485  *
121486  * Clear NAK
121487  */
121488 #define ALT_USB_DEV_DOEPCTL8_CNAK_E_ACT 0x1
121489 
121490 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */
121491 #define ALT_USB_DEV_DOEPCTL8_CNAK_LSB 26
121492 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */
121493 #define ALT_USB_DEV_DOEPCTL8_CNAK_MSB 26
121494 /* The width in bits of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */
121495 #define ALT_USB_DEV_DOEPCTL8_CNAK_WIDTH 1
121496 /* The mask used to set the ALT_USB_DEV_DOEPCTL8_CNAK register field value. */
121497 #define ALT_USB_DEV_DOEPCTL8_CNAK_SET_MSK 0x04000000
121498 /* The mask used to clear the ALT_USB_DEV_DOEPCTL8_CNAK register field value. */
121499 #define ALT_USB_DEV_DOEPCTL8_CNAK_CLR_MSK 0xfbffffff
121500 /* The reset value of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */
121501 #define ALT_USB_DEV_DOEPCTL8_CNAK_RESET 0x0
121502 /* Extracts the ALT_USB_DEV_DOEPCTL8_CNAK field value from a register. */
121503 #define ALT_USB_DEV_DOEPCTL8_CNAK_GET(value) (((value) & 0x04000000) >> 26)
121504 /* Produces a ALT_USB_DEV_DOEPCTL8_CNAK register field value suitable for setting the register. */
121505 #define ALT_USB_DEV_DOEPCTL8_CNAK_SET(value) (((value) << 26) & 0x04000000)
121506 
121507 /*
121508  * Field : snak
121509  *
121510  * Set NAK (SNAK)
121511  *
121512  * A write to this bit sets the NAK bit For the endpoint.
121513  *
121514  * Using this bit, the application can control the transmission of NAK
121515  *
121516  * handshakes on an endpoint. The core can also Set this bit For an
121517  *
121518  * endpoint after a SETUP packet is received on that endpoint.
121519  *
121520  * Field Enumeration Values:
121521  *
121522  * Enum | Value | Description
121523  * :----------------------------------|:------|:------------
121524  * ALT_USB_DEV_DOEPCTL8_SNAK_E_INACT | 0x0 | No Set NAK
121525  * ALT_USB_DEV_DOEPCTL8_SNAK_E_ACT | 0x1 | Set NAK
121526  *
121527  * Field Access Macros:
121528  *
121529  */
121530 /*
121531  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNAK
121532  *
121533  * No Set NAK
121534  */
121535 #define ALT_USB_DEV_DOEPCTL8_SNAK_E_INACT 0x0
121536 /*
121537  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNAK
121538  *
121539  * Set NAK
121540  */
121541 #define ALT_USB_DEV_DOEPCTL8_SNAK_E_ACT 0x1
121542 
121543 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */
121544 #define ALT_USB_DEV_DOEPCTL8_SNAK_LSB 27
121545 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */
121546 #define ALT_USB_DEV_DOEPCTL8_SNAK_MSB 27
121547 /* The width in bits of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */
121548 #define ALT_USB_DEV_DOEPCTL8_SNAK_WIDTH 1
121549 /* The mask used to set the ALT_USB_DEV_DOEPCTL8_SNAK register field value. */
121550 #define ALT_USB_DEV_DOEPCTL8_SNAK_SET_MSK 0x08000000
121551 /* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SNAK register field value. */
121552 #define ALT_USB_DEV_DOEPCTL8_SNAK_CLR_MSK 0xf7ffffff
121553 /* The reset value of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */
121554 #define ALT_USB_DEV_DOEPCTL8_SNAK_RESET 0x0
121555 /* Extracts the ALT_USB_DEV_DOEPCTL8_SNAK field value from a register. */
121556 #define ALT_USB_DEV_DOEPCTL8_SNAK_GET(value) (((value) & 0x08000000) >> 27)
121557 /* Produces a ALT_USB_DEV_DOEPCTL8_SNAK register field value suitable for setting the register. */
121558 #define ALT_USB_DEV_DOEPCTL8_SNAK_SET(value) (((value) << 27) & 0x08000000)
121559 
121560 /*
121561  * Field : setd0pid
121562  *
121563  * Set DATA0 PID (SetD0PID)
121564  *
121565  * Applies to interrupt/bulk IN and OUT endpoints only.
121566  *
121567  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
121568  * to DATA0.
121569  *
121570  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
121571  *
121572  * DMA mode.
121573  *
121574  * 1'b0 WO
121575  *
121576  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
121577  *
121578  * Applies to isochronous IN and OUT endpoints only.
121579  *
121580  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
121581  * (micro)
121582  *
121583  * frame.
121584  *
121585  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
121586  * number
121587  *
121588  * in which to send data is in the transmit descriptor structure. The frame in
121589  * which to
121590  *
121591  * receive data is updated in receive descriptor structure.
121592  *
121593  * Field Enumeration Values:
121594  *
121595  * Enum | Value | Description
121596  * :-------------------------------------|:------|:------------------------------------
121597  * ALT_USB_DEV_DOEPCTL8_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
121598  * ALT_USB_DEV_DOEPCTL8_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
121599  *
121600  * Field Access Macros:
121601  *
121602  */
121603 /*
121604  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD0PID
121605  *
121606  * Disables Set DATA0 PID
121607  */
121608 #define ALT_USB_DEV_DOEPCTL8_SETD0PID_E_DISD 0x0
121609 /*
121610  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD0PID
121611  *
121612  * Enables Endpoint Data PID to DATA0)
121613  */
121614 #define ALT_USB_DEV_DOEPCTL8_SETD0PID_E_END 0x1
121615 
121616 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */
121617 #define ALT_USB_DEV_DOEPCTL8_SETD0PID_LSB 28
121618 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */
121619 #define ALT_USB_DEV_DOEPCTL8_SETD0PID_MSB 28
121620 /* The width in bits of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */
121621 #define ALT_USB_DEV_DOEPCTL8_SETD0PID_WIDTH 1
121622 /* The mask used to set the ALT_USB_DEV_DOEPCTL8_SETD0PID register field value. */
121623 #define ALT_USB_DEV_DOEPCTL8_SETD0PID_SET_MSK 0x10000000
121624 /* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SETD0PID register field value. */
121625 #define ALT_USB_DEV_DOEPCTL8_SETD0PID_CLR_MSK 0xefffffff
121626 /* The reset value of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */
121627 #define ALT_USB_DEV_DOEPCTL8_SETD0PID_RESET 0x0
121628 /* Extracts the ALT_USB_DEV_DOEPCTL8_SETD0PID field value from a register. */
121629 #define ALT_USB_DEV_DOEPCTL8_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
121630 /* Produces a ALT_USB_DEV_DOEPCTL8_SETD0PID register field value suitable for setting the register. */
121631 #define ALT_USB_DEV_DOEPCTL8_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
121632 
121633 /*
121634  * Field : setd1pid
121635  *
121636  * Set DATA1 PID (SetD1PID)
121637  *
121638  * Applies to interrupt/bulk IN and OUT endpoints only.
121639  *
121640  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
121641  * to DATA1.
121642  *
121643  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
121644  *
121645  * DMA mode.
121646  *
121647  * Set Odd (micro)frame (SetOddFr)
121648  *
121649  * Applies to isochronous IN and OUT endpoints only.
121650  *
121651  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
121652  *
121653  * (micro)frame.
121654  *
121655  * This field is not applicable for Scatter/Gather DMA mode.
121656  *
121657  * Field Enumeration Values:
121658  *
121659  * Enum | Value | Description
121660  * :-------------------------------------|:------|:-----------------------
121661  * ALT_USB_DEV_DOEPCTL8_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
121662  * ALT_USB_DEV_DOEPCTL8_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
121663  *
121664  * Field Access Macros:
121665  *
121666  */
121667 /*
121668  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD1PID
121669  *
121670  * Disables Set DATA1 PID
121671  */
121672 #define ALT_USB_DEV_DOEPCTL8_SETD1PID_E_DISD 0x0
121673 /*
121674  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD1PID
121675  *
121676  * Enables Set DATA1 PID
121677  */
121678 #define ALT_USB_DEV_DOEPCTL8_SETD1PID_E_END 0x1
121679 
121680 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */
121681 #define ALT_USB_DEV_DOEPCTL8_SETD1PID_LSB 29
121682 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */
121683 #define ALT_USB_DEV_DOEPCTL8_SETD1PID_MSB 29
121684 /* The width in bits of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */
121685 #define ALT_USB_DEV_DOEPCTL8_SETD1PID_WIDTH 1
121686 /* The mask used to set the ALT_USB_DEV_DOEPCTL8_SETD1PID register field value. */
121687 #define ALT_USB_DEV_DOEPCTL8_SETD1PID_SET_MSK 0x20000000
121688 /* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SETD1PID register field value. */
121689 #define ALT_USB_DEV_DOEPCTL8_SETD1PID_CLR_MSK 0xdfffffff
121690 /* The reset value of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */
121691 #define ALT_USB_DEV_DOEPCTL8_SETD1PID_RESET 0x0
121692 /* Extracts the ALT_USB_DEV_DOEPCTL8_SETD1PID field value from a register. */
121693 #define ALT_USB_DEV_DOEPCTL8_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
121694 /* Produces a ALT_USB_DEV_DOEPCTL8_SETD1PID register field value suitable for setting the register. */
121695 #define ALT_USB_DEV_DOEPCTL8_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
121696 
121697 /*
121698  * Field : epdis
121699  *
121700  * Endpoint Disable (EPDis)
121701  *
121702  * Applies to IN and OUT endpoints.
121703  *
121704  * The application sets this bit to stop transmitting/receiving data on an
121705  * endpoint, even
121706  *
121707  * before the transfer for that endpoint is complete. The application must wait for
121708  * the
121709  *
121710  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
121711  * clears
121712  *
121713  * this bit before setting the Endpoint Disabled interrupt. The application must
121714  * set this bit
121715  *
121716  * only if Endpoint Enable is already set for this endpoint.
121717  *
121718  * Field Enumeration Values:
121719  *
121720  * Enum | Value | Description
121721  * :-----------------------------------|:------|:--------------------
121722  * ALT_USB_DEV_DOEPCTL8_EPDIS_E_INACT | 0x0 | No Endpoint Disable
121723  * ALT_USB_DEV_DOEPCTL8_EPDIS_E_ACT | 0x1 | Endpoint Disable
121724  *
121725  * Field Access Macros:
121726  *
121727  */
121728 /*
121729  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPDIS
121730  *
121731  * No Endpoint Disable
121732  */
121733 #define ALT_USB_DEV_DOEPCTL8_EPDIS_E_INACT 0x0
121734 /*
121735  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPDIS
121736  *
121737  * Endpoint Disable
121738  */
121739 #define ALT_USB_DEV_DOEPCTL8_EPDIS_E_ACT 0x1
121740 
121741 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */
121742 #define ALT_USB_DEV_DOEPCTL8_EPDIS_LSB 30
121743 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */
121744 #define ALT_USB_DEV_DOEPCTL8_EPDIS_MSB 30
121745 /* The width in bits of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */
121746 #define ALT_USB_DEV_DOEPCTL8_EPDIS_WIDTH 1
121747 /* The mask used to set the ALT_USB_DEV_DOEPCTL8_EPDIS register field value. */
121748 #define ALT_USB_DEV_DOEPCTL8_EPDIS_SET_MSK 0x40000000
121749 /* The mask used to clear the ALT_USB_DEV_DOEPCTL8_EPDIS register field value. */
121750 #define ALT_USB_DEV_DOEPCTL8_EPDIS_CLR_MSK 0xbfffffff
121751 /* The reset value of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */
121752 #define ALT_USB_DEV_DOEPCTL8_EPDIS_RESET 0x0
121753 /* Extracts the ALT_USB_DEV_DOEPCTL8_EPDIS field value from a register. */
121754 #define ALT_USB_DEV_DOEPCTL8_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
121755 /* Produces a ALT_USB_DEV_DOEPCTL8_EPDIS register field value suitable for setting the register. */
121756 #define ALT_USB_DEV_DOEPCTL8_EPDIS_SET(value) (((value) << 30) & 0x40000000)
121757 
121758 /*
121759  * Field : epena
121760  *
121761  * Endpoint Enable (EPEna)
121762  *
121763  * Applies to IN and OUT endpoints.
121764  *
121765  * When Scatter/Gather DMA mode is enabled,
121766  *
121767  * For IN endpoints this bit indicates that the descriptor structure and data
121768  * buffer with
121769  *
121770  * data ready to transmit is setup.
121771  *
121772  * For OUT endpoint it indicates that the descriptor structure and data buffer to
121773  *
121774  * receive data is setup.
121775  *
121776  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
121777  *
121778  * DMA mode:
121779  *
121780  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
121781  * the
121782  *
121783  * endpoint.
121784  *
121785  * * For OUT endpoints, this bit indicates that the application has allocated the
121786  *
121787  * memory to start receiving data from the USB.
121788  *
121789  * * The core clears this bit before setting any of the following interrupts on
121790  * this
121791  *
121792  * endpoint:
121793  *
121794  * SETUP Phase Done
121795  *
121796  * Endpoint Disabled
121797  *
121798  * Transfer Completed
121799  *
121800  * Note: For control endpoints in DMA mode, this bit must be set to be able to
121801  * transfer
121802  *
121803  * SETUP data packets in memory.
121804  *
121805  * Field Enumeration Values:
121806  *
121807  * Enum | Value | Description
121808  * :-----------------------------------|:------|:-------------------------
121809  * ALT_USB_DEV_DOEPCTL8_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
121810  * ALT_USB_DEV_DOEPCTL8_EPENA_E_ACT | 0x1 | Endpoint Enable active
121811  *
121812  * Field Access Macros:
121813  *
121814  */
121815 /*
121816  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPENA
121817  *
121818  * Endpoint Enable inactive
121819  */
121820 #define ALT_USB_DEV_DOEPCTL8_EPENA_E_INACT 0x0
121821 /*
121822  * Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPENA
121823  *
121824  * Endpoint Enable active
121825  */
121826 #define ALT_USB_DEV_DOEPCTL8_EPENA_E_ACT 0x1
121827 
121828 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */
121829 #define ALT_USB_DEV_DOEPCTL8_EPENA_LSB 31
121830 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */
121831 #define ALT_USB_DEV_DOEPCTL8_EPENA_MSB 31
121832 /* The width in bits of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */
121833 #define ALT_USB_DEV_DOEPCTL8_EPENA_WIDTH 1
121834 /* The mask used to set the ALT_USB_DEV_DOEPCTL8_EPENA register field value. */
121835 #define ALT_USB_DEV_DOEPCTL8_EPENA_SET_MSK 0x80000000
121836 /* The mask used to clear the ALT_USB_DEV_DOEPCTL8_EPENA register field value. */
121837 #define ALT_USB_DEV_DOEPCTL8_EPENA_CLR_MSK 0x7fffffff
121838 /* The reset value of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */
121839 #define ALT_USB_DEV_DOEPCTL8_EPENA_RESET 0x0
121840 /* Extracts the ALT_USB_DEV_DOEPCTL8_EPENA field value from a register. */
121841 #define ALT_USB_DEV_DOEPCTL8_EPENA_GET(value) (((value) & 0x80000000) >> 31)
121842 /* Produces a ALT_USB_DEV_DOEPCTL8_EPENA register field value suitable for setting the register. */
121843 #define ALT_USB_DEV_DOEPCTL8_EPENA_SET(value) (((value) << 31) & 0x80000000)
121844 
121845 #ifndef __ASSEMBLY__
121846 /*
121847  * WARNING: The C register and register group struct declarations are provided for
121848  * convenience and illustrative purposes. They should, however, be used with
121849  * caution as the C language standard provides no guarantees about the alignment or
121850  * atomicity of device memory accesses. The recommended practice for writing
121851  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
121852  * alt_write_word() functions.
121853  *
121854  * The struct declaration for register ALT_USB_DEV_DOEPCTL8.
121855  */
121856 struct ALT_USB_DEV_DOEPCTL8_s
121857 {
121858  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL8_MPS */
121859  uint32_t : 4; /* *UNDEFINED* */
121860  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL8_USBACTEP */
121861  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL8_DPID */
121862  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL8_NAKSTS */
121863  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL8_EPTYPE */
121864  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL8_SNP */
121865  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL8_STALL */
121866  uint32_t : 4; /* *UNDEFINED* */
121867  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL8_CNAK */
121868  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL8_SNAK */
121869  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL8_SETD0PID */
121870  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL8_SETD1PID */
121871  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL8_EPDIS */
121872  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL8_EPENA */
121873 };
121874 
121875 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL8. */
121876 typedef volatile struct ALT_USB_DEV_DOEPCTL8_s ALT_USB_DEV_DOEPCTL8_t;
121877 #endif /* __ASSEMBLY__ */
121878 
121879 /* The reset value of the ALT_USB_DEV_DOEPCTL8 register. */
121880 #define ALT_USB_DEV_DOEPCTL8_RESET 0x00000000
121881 /* The byte offset of the ALT_USB_DEV_DOEPCTL8 register from the beginning of the component. */
121882 #define ALT_USB_DEV_DOEPCTL8_OFST 0x400
121883 /* The address of the ALT_USB_DEV_DOEPCTL8 register. */
121884 #define ALT_USB_DEV_DOEPCTL8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL8_OFST))
121885 
121886 /*
121887  * Register : doepint8
121888  *
121889  * Device OUT Endpoint 8 Interrupt Register
121890  *
121891  * Register Layout
121892  *
121893  * Bits | Access | Reset | Description
121894  * :--------|:-------|:------|:------------------------------------
121895  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_XFERCOMPL
121896  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_EPDISBLD
121897  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_AHBERR
121898  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_SETUP
121899  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS
121900  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_STSPHSERCVD
121901  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP
121902  * [7] | ??? | 0x0 | *UNDEFINED*
121903  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_OUTPKTERR
121904  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_BNAINTR
121905  * [10] | ??? | 0x0 | *UNDEFINED*
121906  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_PKTDRPSTS
121907  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_BBLEERR
121908  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_NAKINTRPT
121909  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_NYETINTRPT
121910  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_STUPPKTRCVD
121911  * [31:16] | ??? | 0x0 | *UNDEFINED*
121912  *
121913  */
121914 /*
121915  * Field : xfercompl
121916  *
121917  * Transfer Completed Interrupt (XferCompl)
121918  *
121919  * Applies to IN and OUT endpoints.
121920  *
121921  * When Scatter/Gather DMA mode is enabled
121922  *
121923  * * For IN endpoint this field indicates that the requested data
121924  *
121925  * from the descriptor is moved from external system memory
121926  *
121927  * to internal FIFO.
121928  *
121929  * * For OUT endpoint this field indicates that the requested
121930  *
121931  * data from the internal FIFO is moved to external system
121932  *
121933  * memory. This interrupt is generated only when the
121934  *
121935  * corresponding endpoint descriptor is closed, and the IOC
121936  *
121937  * bit For the corresponding descriptor is Set.
121938  *
121939  * When Scatter/Gather DMA mode is disabled, this field
121940  *
121941  * indicates that the programmed transfer is complete on the
121942  *
121943  * AHB as well as on the USB, For this endpoint.
121944  *
121945  * Field Enumeration Values:
121946  *
121947  * Enum | Value | Description
121948  * :---------------------------------------|:------|:-----------------------------
121949  * ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_INACT | 0x0 | No Interrupt
121950  * ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
121951  *
121952  * Field Access Macros:
121953  *
121954  */
121955 /*
121956  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_XFERCOMPL
121957  *
121958  * No Interrupt
121959  */
121960 #define ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_INACT 0x0
121961 /*
121962  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_XFERCOMPL
121963  *
121964  * Transfer Completed Interrupt
121965  */
121966 #define ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_ACT 0x1
121967 
121968 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */
121969 #define ALT_USB_DEV_DOEPINT8_XFERCOMPL_LSB 0
121970 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */
121971 #define ALT_USB_DEV_DOEPINT8_XFERCOMPL_MSB 0
121972 /* The width in bits of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */
121973 #define ALT_USB_DEV_DOEPINT8_XFERCOMPL_WIDTH 1
121974 /* The mask used to set the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field value. */
121975 #define ALT_USB_DEV_DOEPINT8_XFERCOMPL_SET_MSK 0x00000001
121976 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field value. */
121977 #define ALT_USB_DEV_DOEPINT8_XFERCOMPL_CLR_MSK 0xfffffffe
121978 /* The reset value of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */
121979 #define ALT_USB_DEV_DOEPINT8_XFERCOMPL_RESET 0x0
121980 /* Extracts the ALT_USB_DEV_DOEPINT8_XFERCOMPL field value from a register. */
121981 #define ALT_USB_DEV_DOEPINT8_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
121982 /* Produces a ALT_USB_DEV_DOEPINT8_XFERCOMPL register field value suitable for setting the register. */
121983 #define ALT_USB_DEV_DOEPINT8_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
121984 
121985 /*
121986  * Field : epdisbld
121987  *
121988  * Endpoint Disabled Interrupt (EPDisbld)
121989  *
121990  * Applies to IN and OUT endpoints.
121991  *
121992  * This bit indicates that the endpoint is disabled per the
121993  *
121994  * application's request.
121995  *
121996  * Field Enumeration Values:
121997  *
121998  * Enum | Value | Description
121999  * :--------------------------------------|:------|:----------------------------
122000  * ALT_USB_DEV_DOEPINT8_EPDISBLD_E_INACT | 0x0 | No Interrupt
122001  * ALT_USB_DEV_DOEPINT8_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
122002  *
122003  * Field Access Macros:
122004  *
122005  */
122006 /*
122007  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_EPDISBLD
122008  *
122009  * No Interrupt
122010  */
122011 #define ALT_USB_DEV_DOEPINT8_EPDISBLD_E_INACT 0x0
122012 /*
122013  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_EPDISBLD
122014  *
122015  * Endpoint Disabled Interrupt
122016  */
122017 #define ALT_USB_DEV_DOEPINT8_EPDISBLD_E_ACT 0x1
122018 
122019 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */
122020 #define ALT_USB_DEV_DOEPINT8_EPDISBLD_LSB 1
122021 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */
122022 #define ALT_USB_DEV_DOEPINT8_EPDISBLD_MSB 1
122023 /* The width in bits of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */
122024 #define ALT_USB_DEV_DOEPINT8_EPDISBLD_WIDTH 1
122025 /* The mask used to set the ALT_USB_DEV_DOEPINT8_EPDISBLD register field value. */
122026 #define ALT_USB_DEV_DOEPINT8_EPDISBLD_SET_MSK 0x00000002
122027 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_EPDISBLD register field value. */
122028 #define ALT_USB_DEV_DOEPINT8_EPDISBLD_CLR_MSK 0xfffffffd
122029 /* The reset value of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */
122030 #define ALT_USB_DEV_DOEPINT8_EPDISBLD_RESET 0x0
122031 /* Extracts the ALT_USB_DEV_DOEPINT8_EPDISBLD field value from a register. */
122032 #define ALT_USB_DEV_DOEPINT8_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
122033 /* Produces a ALT_USB_DEV_DOEPINT8_EPDISBLD register field value suitable for setting the register. */
122034 #define ALT_USB_DEV_DOEPINT8_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
122035 
122036 /*
122037  * Field : ahberr
122038  *
122039  * AHB Error (AHBErr)
122040  *
122041  * Applies to IN and OUT endpoints.
122042  *
122043  * This is generated only in Internal DMA mode when there is an
122044  *
122045  * AHB error during an AHB read/write. The application can read
122046  *
122047  * the corresponding endpoint DMA address register to get the
122048  *
122049  * error address.
122050  *
122051  * Field Enumeration Values:
122052  *
122053  * Enum | Value | Description
122054  * :------------------------------------|:------|:--------------------
122055  * ALT_USB_DEV_DOEPINT8_AHBERR_E_INACT | 0x0 | No Interrupt
122056  * ALT_USB_DEV_DOEPINT8_AHBERR_E_ACT | 0x1 | AHB Error interrupt
122057  *
122058  * Field Access Macros:
122059  *
122060  */
122061 /*
122062  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_AHBERR
122063  *
122064  * No Interrupt
122065  */
122066 #define ALT_USB_DEV_DOEPINT8_AHBERR_E_INACT 0x0
122067 /*
122068  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_AHBERR
122069  *
122070  * AHB Error interrupt
122071  */
122072 #define ALT_USB_DEV_DOEPINT8_AHBERR_E_ACT 0x1
122073 
122074 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */
122075 #define ALT_USB_DEV_DOEPINT8_AHBERR_LSB 2
122076 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */
122077 #define ALT_USB_DEV_DOEPINT8_AHBERR_MSB 2
122078 /* The width in bits of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */
122079 #define ALT_USB_DEV_DOEPINT8_AHBERR_WIDTH 1
122080 /* The mask used to set the ALT_USB_DEV_DOEPINT8_AHBERR register field value. */
122081 #define ALT_USB_DEV_DOEPINT8_AHBERR_SET_MSK 0x00000004
122082 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_AHBERR register field value. */
122083 #define ALT_USB_DEV_DOEPINT8_AHBERR_CLR_MSK 0xfffffffb
122084 /* The reset value of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */
122085 #define ALT_USB_DEV_DOEPINT8_AHBERR_RESET 0x0
122086 /* Extracts the ALT_USB_DEV_DOEPINT8_AHBERR field value from a register. */
122087 #define ALT_USB_DEV_DOEPINT8_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
122088 /* Produces a ALT_USB_DEV_DOEPINT8_AHBERR register field value suitable for setting the register. */
122089 #define ALT_USB_DEV_DOEPINT8_AHBERR_SET(value) (((value) << 2) & 0x00000004)
122090 
122091 /*
122092  * Field : setup
122093  *
122094  * SETUP Phase Done (SetUp)
122095  *
122096  * Applies to control OUT endpoints only.
122097  *
122098  * Indicates that the SETUP phase For the control endpoint is
122099  *
122100  * complete and no more back-to-back SETUP packets were
122101  *
122102  * received For the current control transfer. On this interrupt, the
122103  *
122104  * application can decode the received SETUP data packet.
122105  *
122106  * Field Enumeration Values:
122107  *
122108  * Enum | Value | Description
122109  * :-----------------------------------|:------|:--------------------
122110  * ALT_USB_DEV_DOEPINT8_SETUP_E_INACT | 0x0 | No SETUP Phase Done
122111  * ALT_USB_DEV_DOEPINT8_SETUP_E_ACT | 0x1 | SETUP Phase Done
122112  *
122113  * Field Access Macros:
122114  *
122115  */
122116 /*
122117  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_SETUP
122118  *
122119  * No SETUP Phase Done
122120  */
122121 #define ALT_USB_DEV_DOEPINT8_SETUP_E_INACT 0x0
122122 /*
122123  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_SETUP
122124  *
122125  * SETUP Phase Done
122126  */
122127 #define ALT_USB_DEV_DOEPINT8_SETUP_E_ACT 0x1
122128 
122129 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_SETUP register field. */
122130 #define ALT_USB_DEV_DOEPINT8_SETUP_LSB 3
122131 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_SETUP register field. */
122132 #define ALT_USB_DEV_DOEPINT8_SETUP_MSB 3
122133 /* The width in bits of the ALT_USB_DEV_DOEPINT8_SETUP register field. */
122134 #define ALT_USB_DEV_DOEPINT8_SETUP_WIDTH 1
122135 /* The mask used to set the ALT_USB_DEV_DOEPINT8_SETUP register field value. */
122136 #define ALT_USB_DEV_DOEPINT8_SETUP_SET_MSK 0x00000008
122137 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_SETUP register field value. */
122138 #define ALT_USB_DEV_DOEPINT8_SETUP_CLR_MSK 0xfffffff7
122139 /* The reset value of the ALT_USB_DEV_DOEPINT8_SETUP register field. */
122140 #define ALT_USB_DEV_DOEPINT8_SETUP_RESET 0x0
122141 /* Extracts the ALT_USB_DEV_DOEPINT8_SETUP field value from a register. */
122142 #define ALT_USB_DEV_DOEPINT8_SETUP_GET(value) (((value) & 0x00000008) >> 3)
122143 /* Produces a ALT_USB_DEV_DOEPINT8_SETUP register field value suitable for setting the register. */
122144 #define ALT_USB_DEV_DOEPINT8_SETUP_SET(value) (((value) << 3) & 0x00000008)
122145 
122146 /*
122147  * Field : outtknepdis
122148  *
122149  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
122150  *
122151  * Applies only to control OUT endpoints.
122152  *
122153  * Indicates that an OUT token was received when the endpoint
122154  *
122155  * was not yet enabled. This interrupt is asserted on the endpoint
122156  *
122157  * For which the OUT token was received.
122158  *
122159  * Field Enumeration Values:
122160  *
122161  * Enum | Value | Description
122162  * :-----------------------------------------|:------|:---------------------------------------------
122163  * ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
122164  * ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
122165  *
122166  * Field Access Macros:
122167  *
122168  */
122169 /*
122170  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS
122171  *
122172  * No OUT Token Received When Endpoint Disabled
122173  */
122174 #define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_INACT 0x0
122175 /*
122176  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS
122177  *
122178  * OUT Token Received When Endpoint Disabled
122179  */
122180 #define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_ACT 0x1
122181 
122182 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */
122183 #define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_LSB 4
122184 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */
122185 #define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_MSB 4
122186 /* The width in bits of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */
122187 #define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_WIDTH 1
122188 /* The mask used to set the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field value. */
122189 #define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_SET_MSK 0x00000010
122190 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field value. */
122191 #define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_CLR_MSK 0xffffffef
122192 /* The reset value of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */
122193 #define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_RESET 0x0
122194 /* Extracts the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS field value from a register. */
122195 #define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
122196 /* Produces a ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field value suitable for setting the register. */
122197 #define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
122198 
122199 /*
122200  * Field : stsphsercvd
122201  *
122202  * Status Phase Received For Control Write (StsPhseRcvd)
122203  *
122204  * This interrupt is valid only For Control OUT endpoints and only in
122205  *
122206  * Scatter Gather DMA mode.
122207  *
122208  * This interrupt is generated only after the core has transferred all
122209  *
122210  * the data that the host has sent during the data phase of a control
122211  *
122212  * write transfer, to the system memory buffer.
122213  *
122214  * The interrupt indicates to the application that the host has
122215  *
122216  * switched from data phase to the status phase of a Control Write
122217  *
122218  * transfer. The application can use this interrupt to ACK or STALL
122219  *
122220  * the Status phase, after it has decoded the data phase. This is
122221  *
122222  * applicable only in Case of Scatter Gather DMA mode.
122223  *
122224  * Field Enumeration Values:
122225  *
122226  * Enum | Value | Description
122227  * :-----------------------------------------|:------|:-------------------------------------------
122228  * ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
122229  * ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
122230  *
122231  * Field Access Macros:
122232  *
122233  */
122234 /*
122235  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_STSPHSERCVD
122236  *
122237  * No Status Phase Received for Control Write
122238  */
122239 #define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_INACT 0x0
122240 /*
122241  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_STSPHSERCVD
122242  *
122243  * Status Phase Received for Control Write
122244  */
122245 #define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_ACT 0x1
122246 
122247 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */
122248 #define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_LSB 5
122249 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */
122250 #define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_MSB 5
122251 /* The width in bits of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */
122252 #define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_WIDTH 1
122253 /* The mask used to set the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field value. */
122254 #define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_SET_MSK 0x00000020
122255 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field value. */
122256 #define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_CLR_MSK 0xffffffdf
122257 /* The reset value of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */
122258 #define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_RESET 0x0
122259 /* Extracts the ALT_USB_DEV_DOEPINT8_STSPHSERCVD field value from a register. */
122260 #define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
122261 /* Produces a ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field value suitable for setting the register. */
122262 #define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
122263 
122264 /*
122265  * Field : back2backsetup
122266  *
122267  * Back-to-Back SETUP Packets Received (Back2BackSETup)
122268  *
122269  * Applies to Control OUT endpoints only.
122270  *
122271  * This bit indicates that the core has received more than three
122272  *
122273  * back-to-back SETUP packets For this particular endpoint. For
122274  *
122275  * information about handling this interrupt,
122276  *
122277  * Field Enumeration Values:
122278  *
122279  * Enum | Value | Description
122280  * :--------------------------------------------|:------|:---------------------------------------
122281  * ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
122282  * ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
122283  *
122284  * Field Access Macros:
122285  *
122286  */
122287 /*
122288  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP
122289  *
122290  * No Back-to-Back SETUP Packets Received
122291  */
122292 #define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_INACT 0x0
122293 /*
122294  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP
122295  *
122296  * Back-to-Back SETUP Packets Received
122297  */
122298 #define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_ACT 0x1
122299 
122300 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */
122301 #define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_LSB 6
122302 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */
122303 #define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_MSB 6
122304 /* The width in bits of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */
122305 #define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_WIDTH 1
122306 /* The mask used to set the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field value. */
122307 #define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_SET_MSK 0x00000040
122308 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field value. */
122309 #define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_CLR_MSK 0xffffffbf
122310 /* The reset value of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */
122311 #define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_RESET 0x0
122312 /* Extracts the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP field value from a register. */
122313 #define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
122314 /* Produces a ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field value suitable for setting the register. */
122315 #define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
122316 
122317 /*
122318  * Field : outpkterr
122319  *
122320  * OUT Packet Error (OutPktErr)
122321  *
122322  * Applies to OUT endpoints Only
122323  *
122324  * This interrupt is valid only when thresholding is enabled. This interrupt is
122325  * asserted when the
122326  *
122327  * core detects an overflow or a CRC error For non-Isochronous
122328  *
122329  * OUT packet.
122330  *
122331  * Field Enumeration Values:
122332  *
122333  * Enum | Value | Description
122334  * :---------------------------------------|:------|:--------------------
122335  * ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
122336  * ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
122337  *
122338  * Field Access Macros:
122339  *
122340  */
122341 /*
122342  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTPKTERR
122343  *
122344  * No OUT Packet Error
122345  */
122346 #define ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_INACT 0x0
122347 /*
122348  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTPKTERR
122349  *
122350  * OUT Packet Error
122351  */
122352 #define ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_ACT 0x1
122353 
122354 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */
122355 #define ALT_USB_DEV_DOEPINT8_OUTPKTERR_LSB 8
122356 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */
122357 #define ALT_USB_DEV_DOEPINT8_OUTPKTERR_MSB 8
122358 /* The width in bits of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */
122359 #define ALT_USB_DEV_DOEPINT8_OUTPKTERR_WIDTH 1
122360 /* The mask used to set the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field value. */
122361 #define ALT_USB_DEV_DOEPINT8_OUTPKTERR_SET_MSK 0x00000100
122362 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field value. */
122363 #define ALT_USB_DEV_DOEPINT8_OUTPKTERR_CLR_MSK 0xfffffeff
122364 /* The reset value of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */
122365 #define ALT_USB_DEV_DOEPINT8_OUTPKTERR_RESET 0x0
122366 /* Extracts the ALT_USB_DEV_DOEPINT8_OUTPKTERR field value from a register. */
122367 #define ALT_USB_DEV_DOEPINT8_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
122368 /* Produces a ALT_USB_DEV_DOEPINT8_OUTPKTERR register field value suitable for setting the register. */
122369 #define ALT_USB_DEV_DOEPINT8_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
122370 
122371 /*
122372  * Field : bnaintr
122373  *
122374  * BNA (Buffer Not Available) Interrupt (BNAIntr)
122375  *
122376  * This bit is valid only when Scatter/Gather DMA mode is enabled.
122377  *
122378  * The core generates this interrupt when the descriptor accessed
122379  *
122380  * is not ready For the Core to process, such as Host busy or DMA
122381  *
122382  * done
122383  *
122384  * Field Enumeration Values:
122385  *
122386  * Enum | Value | Description
122387  * :-------------------------------------|:------|:--------------
122388  * ALT_USB_DEV_DOEPINT8_BNAINTR_E_INACT | 0x0 | No interrupt
122389  * ALT_USB_DEV_DOEPINT8_BNAINTR_E_ACT | 0x1 | BNA interrupt
122390  *
122391  * Field Access Macros:
122392  *
122393  */
122394 /*
122395  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BNAINTR
122396  *
122397  * No interrupt
122398  */
122399 #define ALT_USB_DEV_DOEPINT8_BNAINTR_E_INACT 0x0
122400 /*
122401  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BNAINTR
122402  *
122403  * BNA interrupt
122404  */
122405 #define ALT_USB_DEV_DOEPINT8_BNAINTR_E_ACT 0x1
122406 
122407 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */
122408 #define ALT_USB_DEV_DOEPINT8_BNAINTR_LSB 9
122409 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */
122410 #define ALT_USB_DEV_DOEPINT8_BNAINTR_MSB 9
122411 /* The width in bits of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */
122412 #define ALT_USB_DEV_DOEPINT8_BNAINTR_WIDTH 1
122413 /* The mask used to set the ALT_USB_DEV_DOEPINT8_BNAINTR register field value. */
122414 #define ALT_USB_DEV_DOEPINT8_BNAINTR_SET_MSK 0x00000200
122415 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_BNAINTR register field value. */
122416 #define ALT_USB_DEV_DOEPINT8_BNAINTR_CLR_MSK 0xfffffdff
122417 /* The reset value of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */
122418 #define ALT_USB_DEV_DOEPINT8_BNAINTR_RESET 0x0
122419 /* Extracts the ALT_USB_DEV_DOEPINT8_BNAINTR field value from a register. */
122420 #define ALT_USB_DEV_DOEPINT8_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
122421 /* Produces a ALT_USB_DEV_DOEPINT8_BNAINTR register field value suitable for setting the register. */
122422 #define ALT_USB_DEV_DOEPINT8_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
122423 
122424 /*
122425  * Field : pktdrpsts
122426  *
122427  * Packet Drop Status (PktDrpSts)
122428  *
122429  * This bit indicates to the application that an ISOC OUT packet has been dropped.
122430  * This
122431  *
122432  * bit does not have an associated mask bit and does not generate an interrupt.
122433  *
122434  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
122435  * transfer
122436  *
122437  * interrupt feature is selected.
122438  *
122439  * Field Enumeration Values:
122440  *
122441  * Enum | Value | Description
122442  * :---------------------------------------|:------|:-----------------------------
122443  * ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_INACT | 0x0 | No interrupt
122444  * ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
122445  *
122446  * Field Access Macros:
122447  *
122448  */
122449 /*
122450  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_PKTDRPSTS
122451  *
122452  * No interrupt
122453  */
122454 #define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_INACT 0x0
122455 /*
122456  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_PKTDRPSTS
122457  *
122458  * Packet Drop Status interrupt
122459  */
122460 #define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_ACT 0x1
122461 
122462 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */
122463 #define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_LSB 11
122464 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */
122465 #define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_MSB 11
122466 /* The width in bits of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */
122467 #define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_WIDTH 1
122468 /* The mask used to set the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field value. */
122469 #define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_SET_MSK 0x00000800
122470 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field value. */
122471 #define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_CLR_MSK 0xfffff7ff
122472 /* The reset value of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */
122473 #define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_RESET 0x0
122474 /* Extracts the ALT_USB_DEV_DOEPINT8_PKTDRPSTS field value from a register. */
122475 #define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
122476 /* Produces a ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field value suitable for setting the register. */
122477 #define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
122478 
122479 /*
122480  * Field : bbleerr
122481  *
122482  * NAK Interrupt (BbleErr)
122483  *
122484  * The core generates this interrupt when babble is received for the endpoint.
122485  *
122486  * Field Enumeration Values:
122487  *
122488  * Enum | Value | Description
122489  * :-------------------------------------|:------|:------------------
122490  * ALT_USB_DEV_DOEPINT8_BBLEERR_E_INACT | 0x0 | No interrupt
122491  * ALT_USB_DEV_DOEPINT8_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
122492  *
122493  * Field Access Macros:
122494  *
122495  */
122496 /*
122497  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BBLEERR
122498  *
122499  * No interrupt
122500  */
122501 #define ALT_USB_DEV_DOEPINT8_BBLEERR_E_INACT 0x0
122502 /*
122503  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_BBLEERR
122504  *
122505  * BbleErr interrupt
122506  */
122507 #define ALT_USB_DEV_DOEPINT8_BBLEERR_E_ACT 0x1
122508 
122509 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */
122510 #define ALT_USB_DEV_DOEPINT8_BBLEERR_LSB 12
122511 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */
122512 #define ALT_USB_DEV_DOEPINT8_BBLEERR_MSB 12
122513 /* The width in bits of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */
122514 #define ALT_USB_DEV_DOEPINT8_BBLEERR_WIDTH 1
122515 /* The mask used to set the ALT_USB_DEV_DOEPINT8_BBLEERR register field value. */
122516 #define ALT_USB_DEV_DOEPINT8_BBLEERR_SET_MSK 0x00001000
122517 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_BBLEERR register field value. */
122518 #define ALT_USB_DEV_DOEPINT8_BBLEERR_CLR_MSK 0xffffefff
122519 /* The reset value of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */
122520 #define ALT_USB_DEV_DOEPINT8_BBLEERR_RESET 0x0
122521 /* Extracts the ALT_USB_DEV_DOEPINT8_BBLEERR field value from a register. */
122522 #define ALT_USB_DEV_DOEPINT8_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
122523 /* Produces a ALT_USB_DEV_DOEPINT8_BBLEERR register field value suitable for setting the register. */
122524 #define ALT_USB_DEV_DOEPINT8_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
122525 
122526 /*
122527  * Field : nakintrpt
122528  *
122529  * NAK Interrupt (NAKInterrupt)
122530  *
122531  * The core generates this interrupt when a NAK is transmitted or received by the
122532  * device.
122533  *
122534  * In case of isochronous IN endpoints the interrupt gets generated when a zero
122535  * length
122536  *
122537  * packet is transmitted due to un-availability of data in the TXFifo.
122538  *
122539  * Field Enumeration Values:
122540  *
122541  * Enum | Value | Description
122542  * :---------------------------------------|:------|:--------------
122543  * ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_INACT | 0x0 | No interrupt
122544  * ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
122545  *
122546  * Field Access Macros:
122547  *
122548  */
122549 /*
122550  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_NAKINTRPT
122551  *
122552  * No interrupt
122553  */
122554 #define ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_INACT 0x0
122555 /*
122556  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_NAKINTRPT
122557  *
122558  * NAK Interrupt
122559  */
122560 #define ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_ACT 0x1
122561 
122562 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */
122563 #define ALT_USB_DEV_DOEPINT8_NAKINTRPT_LSB 13
122564 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */
122565 #define ALT_USB_DEV_DOEPINT8_NAKINTRPT_MSB 13
122566 /* The width in bits of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */
122567 #define ALT_USB_DEV_DOEPINT8_NAKINTRPT_WIDTH 1
122568 /* The mask used to set the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field value. */
122569 #define ALT_USB_DEV_DOEPINT8_NAKINTRPT_SET_MSK 0x00002000
122570 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field value. */
122571 #define ALT_USB_DEV_DOEPINT8_NAKINTRPT_CLR_MSK 0xffffdfff
122572 /* The reset value of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */
122573 #define ALT_USB_DEV_DOEPINT8_NAKINTRPT_RESET 0x0
122574 /* Extracts the ALT_USB_DEV_DOEPINT8_NAKINTRPT field value from a register. */
122575 #define ALT_USB_DEV_DOEPINT8_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
122576 /* Produces a ALT_USB_DEV_DOEPINT8_NAKINTRPT register field value suitable for setting the register. */
122577 #define ALT_USB_DEV_DOEPINT8_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
122578 
122579 /*
122580  * Field : nyetintrpt
122581  *
122582  * NYET Interrupt (NYETIntrpt)
122583  *
122584  * The core generates this interrupt when a NYET response is transmitted for a non
122585  * isochronous OUT endpoint.
122586  *
122587  * Field Enumeration Values:
122588  *
122589  * Enum | Value | Description
122590  * :----------------------------------------|:------|:---------------
122591  * ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_INACT | 0x0 | No interrupt
122592  * ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
122593  *
122594  * Field Access Macros:
122595  *
122596  */
122597 /*
122598  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_NYETINTRPT
122599  *
122600  * No interrupt
122601  */
122602 #define ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_INACT 0x0
122603 /*
122604  * Enumerated value for register field ALT_USB_DEV_DOEPINT8_NYETINTRPT
122605  *
122606  * NYET Interrupt
122607  */
122608 #define ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_ACT 0x1
122609 
122610 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */
122611 #define ALT_USB_DEV_DOEPINT8_NYETINTRPT_LSB 14
122612 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */
122613 #define ALT_USB_DEV_DOEPINT8_NYETINTRPT_MSB 14
122614 /* The width in bits of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */
122615 #define ALT_USB_DEV_DOEPINT8_NYETINTRPT_WIDTH 1
122616 /* The mask used to set the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field value. */
122617 #define ALT_USB_DEV_DOEPINT8_NYETINTRPT_SET_MSK 0x00004000
122618 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field value. */
122619 #define ALT_USB_DEV_DOEPINT8_NYETINTRPT_CLR_MSK 0xffffbfff
122620 /* The reset value of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */
122621 #define ALT_USB_DEV_DOEPINT8_NYETINTRPT_RESET 0x0
122622 /* Extracts the ALT_USB_DEV_DOEPINT8_NYETINTRPT field value from a register. */
122623 #define ALT_USB_DEV_DOEPINT8_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
122624 /* Produces a ALT_USB_DEV_DOEPINT8_NYETINTRPT register field value suitable for setting the register. */
122625 #define ALT_USB_DEV_DOEPINT8_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
122626 
122627 /*
122628  * Field : stuppktrcvd
122629  *
122630  * Setup Packet Received
122631  *
122632  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
122633  *
122634  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
122635  *
122636  * setup data. There is only one Setup packet per buffer. On receiving a
122637  *
122638  * Setup packet, the DWC_otg core closes the buffer and disables the
122639  *
122640  * corresponding endpoint. The application has to re-enable the endpoint to
122641  *
122642  * receive any OUT data for the Control Transfer and reprogram the buffer
122643  *
122644  * start address.
122645  *
122646  * Note: Because of the above behavior, the DWC_otg core can receive any
122647  *
122648  * number of back to back setup packets and one buffer for every setup
122649  *
122650  * packet is used.
122651  *
122652  * 1'b0: No Setup packet received
122653  *
122654  * 1'b1: Setup packet received
122655  *
122656  * Reset: 1'b0
122657  *
122658  * Field Access Macros:
122659  *
122660  */
122661 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field. */
122662 #define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_LSB 15
122663 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field. */
122664 #define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_MSB 15
122665 /* The width in bits of the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field. */
122666 #define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_WIDTH 1
122667 /* The mask used to set the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field value. */
122668 #define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_SET_MSK 0x00008000
122669 /* The mask used to clear the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field value. */
122670 #define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_CLR_MSK 0xffff7fff
122671 /* The reset value of the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field. */
122672 #define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_RESET 0x0
122673 /* Extracts the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD field value from a register. */
122674 #define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
122675 /* Produces a ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field value suitable for setting the register. */
122676 #define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
122677 
122678 #ifndef __ASSEMBLY__
122679 /*
122680  * WARNING: The C register and register group struct declarations are provided for
122681  * convenience and illustrative purposes. They should, however, be used with
122682  * caution as the C language standard provides no guarantees about the alignment or
122683  * atomicity of device memory accesses. The recommended practice for writing
122684  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
122685  * alt_write_word() functions.
122686  *
122687  * The struct declaration for register ALT_USB_DEV_DOEPINT8.
122688  */
122689 struct ALT_USB_DEV_DOEPINT8_s
122690 {
122691  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT8_XFERCOMPL */
122692  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT8_EPDISBLD */
122693  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT8_AHBERR */
122694  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT8_SETUP */
122695  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS */
122696  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT8_STSPHSERCVD */
122697  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP */
122698  uint32_t : 1; /* *UNDEFINED* */
122699  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT8_OUTPKTERR */
122700  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT8_BNAINTR */
122701  uint32_t : 1; /* *UNDEFINED* */
122702  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT8_PKTDRPSTS */
122703  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT8_BBLEERR */
122704  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT8_NAKINTRPT */
122705  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT8_NYETINTRPT */
122706  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT8_STUPPKTRCVD */
122707  uint32_t : 16; /* *UNDEFINED* */
122708 };
122709 
122710 /* The typedef declaration for register ALT_USB_DEV_DOEPINT8. */
122711 typedef volatile struct ALT_USB_DEV_DOEPINT8_s ALT_USB_DEV_DOEPINT8_t;
122712 #endif /* __ASSEMBLY__ */
122713 
122714 /* The reset value of the ALT_USB_DEV_DOEPINT8 register. */
122715 #define ALT_USB_DEV_DOEPINT8_RESET 0x00000000
122716 /* The byte offset of the ALT_USB_DEV_DOEPINT8 register from the beginning of the component. */
122717 #define ALT_USB_DEV_DOEPINT8_OFST 0x408
122718 /* The address of the ALT_USB_DEV_DOEPINT8 register. */
122719 #define ALT_USB_DEV_DOEPINT8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT8_OFST))
122720 
122721 /*
122722  * Register : doeptsiz8
122723  *
122724  * Device OUT Endpoint 8 Transfer Size Register
122725  *
122726  * Register Layout
122727  *
122728  * Bits | Access | Reset | Description
122729  * :--------|:-------|:------|:-------------------------------
122730  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ8_XFERSIZE
122731  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ8_PKTCNT
122732  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ8_RXDPID
122733  * [31] | ??? | 0x0 | *UNDEFINED*
122734  *
122735  */
122736 /*
122737  * Field : xfersize
122738  *
122739  * Transfer Size (XferSize)
122740  *
122741  * Indicates the transfer size in bytes For endpoint 0. The core
122742  *
122743  * interrupts the application only after it has exhausted the transfer
122744  *
122745  * size amount of data. The transfer size can be Set to the
122746  *
122747  * maximum packet size of the endpoint, to be interrupted at the
122748  *
122749  * end of each packet.
122750  *
122751  * The core decrements this field every time a packet is read from
122752  *
122753  * the RxFIFO and written to the external memory.
122754  *
122755  * Field Access Macros:
122756  *
122757  */
122758 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */
122759 #define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_LSB 0
122760 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */
122761 #define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_MSB 18
122762 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */
122763 #define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_WIDTH 19
122764 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field value. */
122765 #define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_SET_MSK 0x0007ffff
122766 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field value. */
122767 #define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_CLR_MSK 0xfff80000
122768 /* The reset value of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */
122769 #define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_RESET 0x0
122770 /* Extracts the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE field value from a register. */
122771 #define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
122772 /* Produces a ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field value suitable for setting the register. */
122773 #define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
122774 
122775 /*
122776  * Field : pktcnt
122777  *
122778  * Packet Count (PktCnt)
122779  *
122780  * This field is decremented to zero after a packet is written into the
122781  *
122782  * RxFIFO.
122783  *
122784  * Field Access Macros:
122785  *
122786  */
122787 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */
122788 #define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_LSB 19
122789 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */
122790 #define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_MSB 28
122791 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */
122792 #define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_WIDTH 10
122793 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field value. */
122794 #define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_SET_MSK 0x1ff80000
122795 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field value. */
122796 #define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_CLR_MSK 0xe007ffff
122797 /* The reset value of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */
122798 #define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_RESET 0x0
122799 /* Extracts the ALT_USB_DEV_DOEPTSIZ8_PKTCNT field value from a register. */
122800 #define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
122801 /* Produces a ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field value suitable for setting the register. */
122802 #define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
122803 
122804 /*
122805  * Field : rxdpid
122806  *
122807  * Applies to isochronous OUT endpoints only.
122808  *
122809  * This is the data PID received in the last packet for this endpoint.
122810  *
122811  * 2'b00: DATA0
122812  *
122813  * 2'b01: DATA2
122814  *
122815  * 2'b10: DATA1
122816  *
122817  * 2'b11: MDATA
122818  *
122819  * SETUP Packet Count (SUPCnt)
122820  *
122821  * Applies to control OUT Endpoints only.
122822  *
122823  * This field specifies the number of back-to-back SETUP data
122824  *
122825  * packets the endpoint can receive.
122826  *
122827  * 2'b01: 1 packet
122828  *
122829  * 2'b10: 2 packets
122830  *
122831  * 2'b11: 3 packets
122832  *
122833  * Field Enumeration Values:
122834  *
122835  * Enum | Value | Description
122836  * :-----------------------------------------|:------|:-------------------
122837  * ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA0 | 0x0 | DATA0
122838  * ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
122839  * ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
122840  * ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
122841  *
122842  * Field Access Macros:
122843  *
122844  */
122845 /*
122846  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID
122847  *
122848  * DATA0
122849  */
122850 #define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA0 0x0
122851 /*
122852  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID
122853  *
122854  * DATA2 or 1 packet
122855  */
122856 #define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA2PKT1 0x1
122857 /*
122858  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID
122859  *
122860  * DATA1 or 2 packets
122861  */
122862 #define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA1PKT2 0x2
122863 /*
122864  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID
122865  *
122866  * MDATA or 3 packets
122867  */
122868 #define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_MDATAPKT3 0x3
122869 
122870 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */
122871 #define ALT_USB_DEV_DOEPTSIZ8_RXDPID_LSB 29
122872 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */
122873 #define ALT_USB_DEV_DOEPTSIZ8_RXDPID_MSB 30
122874 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */
122875 #define ALT_USB_DEV_DOEPTSIZ8_RXDPID_WIDTH 2
122876 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field value. */
122877 #define ALT_USB_DEV_DOEPTSIZ8_RXDPID_SET_MSK 0x60000000
122878 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field value. */
122879 #define ALT_USB_DEV_DOEPTSIZ8_RXDPID_CLR_MSK 0x9fffffff
122880 /* The reset value of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */
122881 #define ALT_USB_DEV_DOEPTSIZ8_RXDPID_RESET 0x0
122882 /* Extracts the ALT_USB_DEV_DOEPTSIZ8_RXDPID field value from a register. */
122883 #define ALT_USB_DEV_DOEPTSIZ8_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
122884 /* Produces a ALT_USB_DEV_DOEPTSIZ8_RXDPID register field value suitable for setting the register. */
122885 #define ALT_USB_DEV_DOEPTSIZ8_RXDPID_SET(value) (((value) << 29) & 0x60000000)
122886 
122887 #ifndef __ASSEMBLY__
122888 /*
122889  * WARNING: The C register and register group struct declarations are provided for
122890  * convenience and illustrative purposes. They should, however, be used with
122891  * caution as the C language standard provides no guarantees about the alignment or
122892  * atomicity of device memory accesses. The recommended practice for writing
122893  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
122894  * alt_write_word() functions.
122895  *
122896  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ8.
122897  */
122898 struct ALT_USB_DEV_DOEPTSIZ8_s
122899 {
122900  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ8_XFERSIZE */
122901  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ8_PKTCNT */
122902  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ8_RXDPID */
122903  uint32_t : 1; /* *UNDEFINED* */
122904 };
122905 
122906 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ8. */
122907 typedef volatile struct ALT_USB_DEV_DOEPTSIZ8_s ALT_USB_DEV_DOEPTSIZ8_t;
122908 #endif /* __ASSEMBLY__ */
122909 
122910 /* The reset value of the ALT_USB_DEV_DOEPTSIZ8 register. */
122911 #define ALT_USB_DEV_DOEPTSIZ8_RESET 0x00000000
122912 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ8 register from the beginning of the component. */
122913 #define ALT_USB_DEV_DOEPTSIZ8_OFST 0x410
122914 /* The address of the ALT_USB_DEV_DOEPTSIZ8 register. */
122915 #define ALT_USB_DEV_DOEPTSIZ8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ8_OFST))
122916 
122917 /*
122918  * Register : doepdma8
122919  *
122920  * Device OUT Endpoint 8 DMA Address Register
122921  *
122922  * Register Layout
122923  *
122924  * Bits | Access | Reset | Description
122925  * :-------|:-------|:--------|:------------------------------
122926  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA8_DOEPDMA8
122927  *
122928  */
122929 /*
122930  * Field : doepdma8
122931  *
122932  * Holds the start address of the external memory for storing or fetching endpoint
122933  *
122934  * data.
122935  *
122936  * Note: For control endpoints, this field stores control OUT data packets as well
122937  * as
122938  *
122939  * SETUP transaction data packets. When more than three SETUP packets are
122940  *
122941  * received back-to-back, the SETUP data packet in the memory is overwritten.
122942  *
122943  * This register is incremented on every AHB transaction. The application can give
122944  *
122945  * only a DWORD-aligned address.
122946  *
122947  * When Scatter/Gather DMA mode is not enabled, the application programs the
122948  *
122949  * start address value in this field.
122950  *
122951  * When Scatter/Gather DMA mode is enabled, this field indicates the base
122952  *
122953  * pointer for the descriptor list.
122954  *
122955  * Field Access Macros:
122956  *
122957  */
122958 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field. */
122959 #define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_LSB 0
122960 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field. */
122961 #define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_MSB 31
122962 /* The width in bits of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field. */
122963 #define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_WIDTH 32
122964 /* The mask used to set the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field value. */
122965 #define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_SET_MSK 0xffffffff
122966 /* The mask used to clear the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field value. */
122967 #define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_CLR_MSK 0x00000000
122968 /* The reset value of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field is UNKNOWN. */
122969 #define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_RESET 0x0
122970 /* Extracts the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 field value from a register. */
122971 #define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_GET(value) (((value) & 0xffffffff) >> 0)
122972 /* Produces a ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field value suitable for setting the register. */
122973 #define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_SET(value) (((value) << 0) & 0xffffffff)
122974 
122975 #ifndef __ASSEMBLY__
122976 /*
122977  * WARNING: The C register and register group struct declarations are provided for
122978  * convenience and illustrative purposes. They should, however, be used with
122979  * caution as the C language standard provides no guarantees about the alignment or
122980  * atomicity of device memory accesses. The recommended practice for writing
122981  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
122982  * alt_write_word() functions.
122983  *
122984  * The struct declaration for register ALT_USB_DEV_DOEPDMA8.
122985  */
122986 struct ALT_USB_DEV_DOEPDMA8_s
122987 {
122988  uint32_t doepdma8 : 32; /* ALT_USB_DEV_DOEPDMA8_DOEPDMA8 */
122989 };
122990 
122991 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA8. */
122992 typedef volatile struct ALT_USB_DEV_DOEPDMA8_s ALT_USB_DEV_DOEPDMA8_t;
122993 #endif /* __ASSEMBLY__ */
122994 
122995 /* The reset value of the ALT_USB_DEV_DOEPDMA8 register. */
122996 #define ALT_USB_DEV_DOEPDMA8_RESET 0x00000000
122997 /* The byte offset of the ALT_USB_DEV_DOEPDMA8 register from the beginning of the component. */
122998 #define ALT_USB_DEV_DOEPDMA8_OFST 0x414
122999 /* The address of the ALT_USB_DEV_DOEPDMA8 register. */
123000 #define ALT_USB_DEV_DOEPDMA8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA8_OFST))
123001 
123002 /*
123003  * Register : doepdmab8
123004  *
123005  * Device OUT Endpoint 8 Buffer Address Register
123006  *
123007  * Register Layout
123008  *
123009  * Bits | Access | Reset | Description
123010  * :-------|:-------|:--------|:--------------------------------
123011  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8
123012  *
123013  */
123014 /*
123015  * Field : doepdmab8
123016  *
123017  * Holds the current buffer address.This register is updated as and when the data
123018  *
123019  * transfer for the corresponding end point is in progress.
123020  *
123021  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
123022  * is
123023  *
123024  * reserved.
123025  *
123026  * Field Access Macros:
123027  *
123028  */
123029 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field. */
123030 #define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_LSB 0
123031 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field. */
123032 #define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_MSB 31
123033 /* The width in bits of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field. */
123034 #define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_WIDTH 32
123035 /* The mask used to set the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field value. */
123036 #define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_SET_MSK 0xffffffff
123037 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field value. */
123038 #define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_CLR_MSK 0x00000000
123039 /* The reset value of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field is UNKNOWN. */
123040 #define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_RESET 0x0
123041 /* Extracts the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 field value from a register. */
123042 #define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_GET(value) (((value) & 0xffffffff) >> 0)
123043 /* Produces a ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field value suitable for setting the register. */
123044 #define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_SET(value) (((value) << 0) & 0xffffffff)
123045 
123046 #ifndef __ASSEMBLY__
123047 /*
123048  * WARNING: The C register and register group struct declarations are provided for
123049  * convenience and illustrative purposes. They should, however, be used with
123050  * caution as the C language standard provides no guarantees about the alignment or
123051  * atomicity of device memory accesses. The recommended practice for writing
123052  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
123053  * alt_write_word() functions.
123054  *
123055  * The struct declaration for register ALT_USB_DEV_DOEPDMAB8.
123056  */
123057 struct ALT_USB_DEV_DOEPDMAB8_s
123058 {
123059  const uint32_t doepdmab8 : 32; /* ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 */
123060 };
123061 
123062 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB8. */
123063 typedef volatile struct ALT_USB_DEV_DOEPDMAB8_s ALT_USB_DEV_DOEPDMAB8_t;
123064 #endif /* __ASSEMBLY__ */
123065 
123066 /* The reset value of the ALT_USB_DEV_DOEPDMAB8 register. */
123067 #define ALT_USB_DEV_DOEPDMAB8_RESET 0x00000000
123068 /* The byte offset of the ALT_USB_DEV_DOEPDMAB8 register from the beginning of the component. */
123069 #define ALT_USB_DEV_DOEPDMAB8_OFST 0x41c
123070 /* The address of the ALT_USB_DEV_DOEPDMAB8 register. */
123071 #define ALT_USB_DEV_DOEPDMAB8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB8_OFST))
123072 
123073 /*
123074  * Register : doepctl9
123075  *
123076  * Device Control OUT Endpoint 9 Control Register
123077  *
123078  * Register Layout
123079  *
123080  * Bits | Access | Reset | Description
123081  * :--------|:---------|:------|:------------------------------
123082  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL9_MPS
123083  * [14:11] | ??? | 0x0 | *UNDEFINED*
123084  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL9_USBACTEP
123085  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL9_DPID
123086  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL9_NAKSTS
123087  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL9_EPTYPE
123088  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL9_SNP
123089  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL9_STALL
123090  * [25:22] | ??? | 0x0 | *UNDEFINED*
123091  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL9_CNAK
123092  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL9_SNAK
123093  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL9_SETD0PID
123094  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL9_SETD1PID
123095  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL9_EPDIS
123096  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL9_EPENA
123097  *
123098  */
123099 /*
123100  * Field : mps
123101  *
123102  * Maximum Packet Size (MPS)
123103  *
123104  * The application must program this field with the maximum packet size for the
123105  * current
123106  *
123107  * logical endpoint. This value is in bytes.
123108  *
123109  * Field Access Macros:
123110  *
123111  */
123112 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_MPS register field. */
123113 #define ALT_USB_DEV_DOEPCTL9_MPS_LSB 0
123114 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_MPS register field. */
123115 #define ALT_USB_DEV_DOEPCTL9_MPS_MSB 10
123116 /* The width in bits of the ALT_USB_DEV_DOEPCTL9_MPS register field. */
123117 #define ALT_USB_DEV_DOEPCTL9_MPS_WIDTH 11
123118 /* The mask used to set the ALT_USB_DEV_DOEPCTL9_MPS register field value. */
123119 #define ALT_USB_DEV_DOEPCTL9_MPS_SET_MSK 0x000007ff
123120 /* The mask used to clear the ALT_USB_DEV_DOEPCTL9_MPS register field value. */
123121 #define ALT_USB_DEV_DOEPCTL9_MPS_CLR_MSK 0xfffff800
123122 /* The reset value of the ALT_USB_DEV_DOEPCTL9_MPS register field. */
123123 #define ALT_USB_DEV_DOEPCTL9_MPS_RESET 0x0
123124 /* Extracts the ALT_USB_DEV_DOEPCTL9_MPS field value from a register. */
123125 #define ALT_USB_DEV_DOEPCTL9_MPS_GET(value) (((value) & 0x000007ff) >> 0)
123126 /* Produces a ALT_USB_DEV_DOEPCTL9_MPS register field value suitable for setting the register. */
123127 #define ALT_USB_DEV_DOEPCTL9_MPS_SET(value) (((value) << 0) & 0x000007ff)
123128 
123129 /*
123130  * Field : usbactep
123131  *
123132  * USB Active Endpoint (USBActEP)
123133  *
123134  * Indicates whether this endpoint is active in the current configuration and
123135  * interface. The
123136  *
123137  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
123138  * reset. After
123139  *
123140  * receiving the SetConfiguration and SetInterface commands, the application must
123141  *
123142  * program endpoint registers accordingly and set this bit.
123143  *
123144  * Field Enumeration Values:
123145  *
123146  * Enum | Value | Description
123147  * :-------------------------------------|:------|:--------------------
123148  * ALT_USB_DEV_DOEPCTL9_USBACTEP_E_DISD | 0x0 | Not Active
123149  * ALT_USB_DEV_DOEPCTL9_USBACTEP_E_END | 0x1 | USB Active Endpoint
123150  *
123151  * Field Access Macros:
123152  *
123153  */
123154 /*
123155  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_USBACTEP
123156  *
123157  * Not Active
123158  */
123159 #define ALT_USB_DEV_DOEPCTL9_USBACTEP_E_DISD 0x0
123160 /*
123161  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_USBACTEP
123162  *
123163  * USB Active Endpoint
123164  */
123165 #define ALT_USB_DEV_DOEPCTL9_USBACTEP_E_END 0x1
123166 
123167 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */
123168 #define ALT_USB_DEV_DOEPCTL9_USBACTEP_LSB 15
123169 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */
123170 #define ALT_USB_DEV_DOEPCTL9_USBACTEP_MSB 15
123171 /* The width in bits of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */
123172 #define ALT_USB_DEV_DOEPCTL9_USBACTEP_WIDTH 1
123173 /* The mask used to set the ALT_USB_DEV_DOEPCTL9_USBACTEP register field value. */
123174 #define ALT_USB_DEV_DOEPCTL9_USBACTEP_SET_MSK 0x00008000
123175 /* The mask used to clear the ALT_USB_DEV_DOEPCTL9_USBACTEP register field value. */
123176 #define ALT_USB_DEV_DOEPCTL9_USBACTEP_CLR_MSK 0xffff7fff
123177 /* The reset value of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */
123178 #define ALT_USB_DEV_DOEPCTL9_USBACTEP_RESET 0x0
123179 /* Extracts the ALT_USB_DEV_DOEPCTL9_USBACTEP field value from a register. */
123180 #define ALT_USB_DEV_DOEPCTL9_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
123181 /* Produces a ALT_USB_DEV_DOEPCTL9_USBACTEP register field value suitable for setting the register. */
123182 #define ALT_USB_DEV_DOEPCTL9_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
123183 
123184 /*
123185  * Field : dpid
123186  *
123187  * Endpoint Data PID (DPID)
123188  *
123189  * Applies to interrupt/bulk IN and OUT endpoints only.
123190  *
123191  * Contains the PID of the packet to be received or transmitted on this endpoint.
123192  * The
123193  *
123194  * application must program the PID of the first packet to be received or
123195  * transmitted on
123196  *
123197  * this endpoint, after the endpoint is activated. The applications use the
123198  * SetD1PID and
123199  *
123200  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
123201  *
123202  * 1'b0: DATA0
123203  *
123204  * 1'b1: DATA1
123205  *
123206  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
123207  *
123208  * DMA mode.
123209  *
123210  * 1'b0 RO
123211  *
123212  * Even/Odd (Micro)Frame (EO_FrNum)
123213  *
123214  * In non-Scatter/Gather DMA mode:
123215  *
123216  * Applies to isochronous IN and OUT endpoints only.
123217  *
123218  * Indicates the (micro)frame number in which the core transmits/receives
123219  * isochronous
123220  *
123221  * data for this endpoint. The application must program the even/odd (micro) frame
123222  *
123223  * number in which it intends to transmit/receive isochronous data for this
123224  * endpoint using
123225  *
123226  * the SetEvnFr and SetOddFr fields in this register.
123227  *
123228  * 1'b0: Even (micro)frame
123229  *
123230  * 1'b1: Odd (micro)frame
123231  *
123232  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
123233  * number
123234  *
123235  * in which to send data is provided in the transmit descriptor structure. The
123236  * frame in
123237  *
123238  * which data is received is updated in receive descriptor structure.
123239  *
123240  * Field Enumeration Values:
123241  *
123242  * Enum | Value | Description
123243  * :----------------------------------|:------|:-----------------------------
123244  * ALT_USB_DEV_DOEPCTL9_DPID_E_INACT | 0x0 | Endpoint Data PID not active
123245  * ALT_USB_DEV_DOEPCTL9_DPID_E_ACT | 0x1 | Endpoint Data PID active
123246  *
123247  * Field Access Macros:
123248  *
123249  */
123250 /*
123251  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_DPID
123252  *
123253  * Endpoint Data PID not active
123254  */
123255 #define ALT_USB_DEV_DOEPCTL9_DPID_E_INACT 0x0
123256 /*
123257  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_DPID
123258  *
123259  * Endpoint Data PID active
123260  */
123261 #define ALT_USB_DEV_DOEPCTL9_DPID_E_ACT 0x1
123262 
123263 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_DPID register field. */
123264 #define ALT_USB_DEV_DOEPCTL9_DPID_LSB 16
123265 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_DPID register field. */
123266 #define ALT_USB_DEV_DOEPCTL9_DPID_MSB 16
123267 /* The width in bits of the ALT_USB_DEV_DOEPCTL9_DPID register field. */
123268 #define ALT_USB_DEV_DOEPCTL9_DPID_WIDTH 1
123269 /* The mask used to set the ALT_USB_DEV_DOEPCTL9_DPID register field value. */
123270 #define ALT_USB_DEV_DOEPCTL9_DPID_SET_MSK 0x00010000
123271 /* The mask used to clear the ALT_USB_DEV_DOEPCTL9_DPID register field value. */
123272 #define ALT_USB_DEV_DOEPCTL9_DPID_CLR_MSK 0xfffeffff
123273 /* The reset value of the ALT_USB_DEV_DOEPCTL9_DPID register field. */
123274 #define ALT_USB_DEV_DOEPCTL9_DPID_RESET 0x0
123275 /* Extracts the ALT_USB_DEV_DOEPCTL9_DPID field value from a register. */
123276 #define ALT_USB_DEV_DOEPCTL9_DPID_GET(value) (((value) & 0x00010000) >> 16)
123277 /* Produces a ALT_USB_DEV_DOEPCTL9_DPID register field value suitable for setting the register. */
123278 #define ALT_USB_DEV_DOEPCTL9_DPID_SET(value) (((value) << 16) & 0x00010000)
123279 
123280 /*
123281  * Field : naksts
123282  *
123283  * NAK Status (NAKSts)
123284  *
123285  * Indicates the following:
123286  *
123287  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
123288  *
123289  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
123290  *
123291  * When either the application or the core sets this bit:
123292  *
123293  * The core stops receiving any data on an OUT endpoint, even if there is space in
123294  *
123295  * the RxFIFO to accommodate the incoming packet.
123296  *
123297  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
123298  *
123299  * endpoint, even if there data is available in the TxFIFO.
123300  *
123301  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
123302  *
123303  * if there data is available in the TxFIFO.
123304  *
123305  * Irrespective of this bit's setting, the core always responds to SETUP data
123306  * packets with
123307  *
123308  * an ACK handshake.
123309  *
123310  * Field Enumeration Values:
123311  *
123312  * Enum | Value | Description
123313  * :-------------------------------------|:------|:------------------------------------------------
123314  * ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
123315  * : | | based on the FIFO status
123316  * ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
123317  * : | | endpoint
123318  *
123319  * Field Access Macros:
123320  *
123321  */
123322 /*
123323  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_NAKSTS
123324  *
123325  * The core is transmitting non-NAK handshakes based on the FIFO status
123326  */
123327 #define ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NONNAK 0x0
123328 /*
123329  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_NAKSTS
123330  *
123331  * The core is transmitting NAK handshakes on this endpoint
123332  */
123333 #define ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NAK 0x1
123334 
123335 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */
123336 #define ALT_USB_DEV_DOEPCTL9_NAKSTS_LSB 17
123337 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */
123338 #define ALT_USB_DEV_DOEPCTL9_NAKSTS_MSB 17
123339 /* The width in bits of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */
123340 #define ALT_USB_DEV_DOEPCTL9_NAKSTS_WIDTH 1
123341 /* The mask used to set the ALT_USB_DEV_DOEPCTL9_NAKSTS register field value. */
123342 #define ALT_USB_DEV_DOEPCTL9_NAKSTS_SET_MSK 0x00020000
123343 /* The mask used to clear the ALT_USB_DEV_DOEPCTL9_NAKSTS register field value. */
123344 #define ALT_USB_DEV_DOEPCTL9_NAKSTS_CLR_MSK 0xfffdffff
123345 /* The reset value of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */
123346 #define ALT_USB_DEV_DOEPCTL9_NAKSTS_RESET 0x0
123347 /* Extracts the ALT_USB_DEV_DOEPCTL9_NAKSTS field value from a register. */
123348 #define ALT_USB_DEV_DOEPCTL9_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
123349 /* Produces a ALT_USB_DEV_DOEPCTL9_NAKSTS register field value suitable for setting the register. */
123350 #define ALT_USB_DEV_DOEPCTL9_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
123351 
123352 /*
123353  * Field : eptype
123354  *
123355  * Endpoint Type (EPType)
123356  *
123357  * This is the transfer type supported by this logical endpoint.
123358  *
123359  * 2'b00: Control
123360  *
123361  * 2'b01: Isochronous
123362  *
123363  * 2'b10: Bulk
123364  *
123365  * 2'b11: Interrupt
123366  *
123367  * Field Enumeration Values:
123368  *
123369  * Enum | Value | Description
123370  * :------------------------------------------|:------|:------------
123371  * ALT_USB_DEV_DOEPCTL9_EPTYPE_E_CTL | 0x0 | Control
123372  * ALT_USB_DEV_DOEPCTL9_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
123373  * ALT_USB_DEV_DOEPCTL9_EPTYPE_E_BULK | 0x2 | Bulk
123374  * ALT_USB_DEV_DOEPCTL9_EPTYPE_E_INTERRUP | 0x3 | Interrupt
123375  *
123376  * Field Access Macros:
123377  *
123378  */
123379 /*
123380  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE
123381  *
123382  * Control
123383  */
123384 #define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_CTL 0x0
123385 /*
123386  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE
123387  *
123388  * Isochronous
123389  */
123390 #define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_ISOCHRONOUS 0x1
123391 /*
123392  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE
123393  *
123394  * Bulk
123395  */
123396 #define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_BULK 0x2
123397 /*
123398  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE
123399  *
123400  * Interrupt
123401  */
123402 #define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_INTERRUP 0x3
123403 
123404 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */
123405 #define ALT_USB_DEV_DOEPCTL9_EPTYPE_LSB 18
123406 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */
123407 #define ALT_USB_DEV_DOEPCTL9_EPTYPE_MSB 19
123408 /* The width in bits of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */
123409 #define ALT_USB_DEV_DOEPCTL9_EPTYPE_WIDTH 2
123410 /* The mask used to set the ALT_USB_DEV_DOEPCTL9_EPTYPE register field value. */
123411 #define ALT_USB_DEV_DOEPCTL9_EPTYPE_SET_MSK 0x000c0000
123412 /* The mask used to clear the ALT_USB_DEV_DOEPCTL9_EPTYPE register field value. */
123413 #define ALT_USB_DEV_DOEPCTL9_EPTYPE_CLR_MSK 0xfff3ffff
123414 /* The reset value of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */
123415 #define ALT_USB_DEV_DOEPCTL9_EPTYPE_RESET 0x0
123416 /* Extracts the ALT_USB_DEV_DOEPCTL9_EPTYPE field value from a register. */
123417 #define ALT_USB_DEV_DOEPCTL9_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
123418 /* Produces a ALT_USB_DEV_DOEPCTL9_EPTYPE register field value suitable for setting the register. */
123419 #define ALT_USB_DEV_DOEPCTL9_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
123420 
123421 /*
123422  * Field : snp
123423  *
123424  * Snoop Mode (Snp)
123425  *
123426  * Applies to OUT endpoints only.
123427  *
123428  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
123429  *
123430  * check the correctness of OUT packets before transferring them to application
123431  * memory.
123432  *
123433  * Field Enumeration Values:
123434  *
123435  * Enum | Value | Description
123436  * :-------------------------------|:------|:-------------------
123437  * ALT_USB_DEV_DOEPCTL9_SNP_E_DIS | 0x0 | Disable Snoop Mode
123438  * ALT_USB_DEV_DOEPCTL9_SNP_E_EN | 0x1 | Enable Snoop Mode
123439  *
123440  * Field Access Macros:
123441  *
123442  */
123443 /*
123444  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNP
123445  *
123446  * Disable Snoop Mode
123447  */
123448 #define ALT_USB_DEV_DOEPCTL9_SNP_E_DIS 0x0
123449 /*
123450  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNP
123451  *
123452  * Enable Snoop Mode
123453  */
123454 #define ALT_USB_DEV_DOEPCTL9_SNP_E_EN 0x1
123455 
123456 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SNP register field. */
123457 #define ALT_USB_DEV_DOEPCTL9_SNP_LSB 20
123458 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SNP register field. */
123459 #define ALT_USB_DEV_DOEPCTL9_SNP_MSB 20
123460 /* The width in bits of the ALT_USB_DEV_DOEPCTL9_SNP register field. */
123461 #define ALT_USB_DEV_DOEPCTL9_SNP_WIDTH 1
123462 /* The mask used to set the ALT_USB_DEV_DOEPCTL9_SNP register field value. */
123463 #define ALT_USB_DEV_DOEPCTL9_SNP_SET_MSK 0x00100000
123464 /* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SNP register field value. */
123465 #define ALT_USB_DEV_DOEPCTL9_SNP_CLR_MSK 0xffefffff
123466 /* The reset value of the ALT_USB_DEV_DOEPCTL9_SNP register field. */
123467 #define ALT_USB_DEV_DOEPCTL9_SNP_RESET 0x0
123468 /* Extracts the ALT_USB_DEV_DOEPCTL9_SNP field value from a register. */
123469 #define ALT_USB_DEV_DOEPCTL9_SNP_GET(value) (((value) & 0x00100000) >> 20)
123470 /* Produces a ALT_USB_DEV_DOEPCTL9_SNP register field value suitable for setting the register. */
123471 #define ALT_USB_DEV_DOEPCTL9_SNP_SET(value) (((value) << 20) & 0x00100000)
123472 
123473 /*
123474  * Field : stall
123475  *
123476  * STALL Handshake (Stall)
123477  *
123478  * Applies to non-control, non-isochronous IN and OUT endpoints only.
123479  *
123480  * The application sets this bit to stall all tokens from the USB host to this
123481  * endpoint. If a
123482  *
123483  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
123484  * bit, the
123485  *
123486  * STALL bit takes priority. Only the application can clear this bit, never the
123487  * core.
123488  *
123489  * 1'b0 R_W
123490  *
123491  * Applies to control endpoints only.
123492  *
123493  * The application can only set this bit, and the core clears it, when a SETUP
123494  * token is
123495  *
123496  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
123497  * OUT
123498  *
123499  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
123500  * this bit's
123501  *
123502  * setting, the core always responds to SETUP data packets with an ACK handshake.
123503  *
123504  * Field Enumeration Values:
123505  *
123506  * Enum | Value | Description
123507  * :-----------------------------------|:------|:----------------------------
123508  * ALT_USB_DEV_DOEPCTL9_STALL_E_INACT | 0x0 | STALL All Tokens not active
123509  * ALT_USB_DEV_DOEPCTL9_STALL_E_ACT | 0x1 | STALL All Tokens active
123510  *
123511  * Field Access Macros:
123512  *
123513  */
123514 /*
123515  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_STALL
123516  *
123517  * STALL All Tokens not active
123518  */
123519 #define ALT_USB_DEV_DOEPCTL9_STALL_E_INACT 0x0
123520 /*
123521  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_STALL
123522  *
123523  * STALL All Tokens active
123524  */
123525 #define ALT_USB_DEV_DOEPCTL9_STALL_E_ACT 0x1
123526 
123527 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_STALL register field. */
123528 #define ALT_USB_DEV_DOEPCTL9_STALL_LSB 21
123529 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_STALL register field. */
123530 #define ALT_USB_DEV_DOEPCTL9_STALL_MSB 21
123531 /* The width in bits of the ALT_USB_DEV_DOEPCTL9_STALL register field. */
123532 #define ALT_USB_DEV_DOEPCTL9_STALL_WIDTH 1
123533 /* The mask used to set the ALT_USB_DEV_DOEPCTL9_STALL register field value. */
123534 #define ALT_USB_DEV_DOEPCTL9_STALL_SET_MSK 0x00200000
123535 /* The mask used to clear the ALT_USB_DEV_DOEPCTL9_STALL register field value. */
123536 #define ALT_USB_DEV_DOEPCTL9_STALL_CLR_MSK 0xffdfffff
123537 /* The reset value of the ALT_USB_DEV_DOEPCTL9_STALL register field. */
123538 #define ALT_USB_DEV_DOEPCTL9_STALL_RESET 0x0
123539 /* Extracts the ALT_USB_DEV_DOEPCTL9_STALL field value from a register. */
123540 #define ALT_USB_DEV_DOEPCTL9_STALL_GET(value) (((value) & 0x00200000) >> 21)
123541 /* Produces a ALT_USB_DEV_DOEPCTL9_STALL register field value suitable for setting the register. */
123542 #define ALT_USB_DEV_DOEPCTL9_STALL_SET(value) (((value) << 21) & 0x00200000)
123543 
123544 /*
123545  * Field : cnak
123546  *
123547  * Clear NAK (CNAK)
123548  *
123549  * A write to this bit clears the NAK bit For the endpoint.
123550  *
123551  * Field Enumeration Values:
123552  *
123553  * Enum | Value | Description
123554  * :----------------------------------|:------|:-------------
123555  * ALT_USB_DEV_DOEPCTL9_CNAK_E_INACT | 0x0 | No Clear NAK
123556  * ALT_USB_DEV_DOEPCTL9_CNAK_E_ACT | 0x1 | Clear NAK
123557  *
123558  * Field Access Macros:
123559  *
123560  */
123561 /*
123562  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_CNAK
123563  *
123564  * No Clear NAK
123565  */
123566 #define ALT_USB_DEV_DOEPCTL9_CNAK_E_INACT 0x0
123567 /*
123568  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_CNAK
123569  *
123570  * Clear NAK
123571  */
123572 #define ALT_USB_DEV_DOEPCTL9_CNAK_E_ACT 0x1
123573 
123574 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */
123575 #define ALT_USB_DEV_DOEPCTL9_CNAK_LSB 26
123576 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */
123577 #define ALT_USB_DEV_DOEPCTL9_CNAK_MSB 26
123578 /* The width in bits of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */
123579 #define ALT_USB_DEV_DOEPCTL9_CNAK_WIDTH 1
123580 /* The mask used to set the ALT_USB_DEV_DOEPCTL9_CNAK register field value. */
123581 #define ALT_USB_DEV_DOEPCTL9_CNAK_SET_MSK 0x04000000
123582 /* The mask used to clear the ALT_USB_DEV_DOEPCTL9_CNAK register field value. */
123583 #define ALT_USB_DEV_DOEPCTL9_CNAK_CLR_MSK 0xfbffffff
123584 /* The reset value of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */
123585 #define ALT_USB_DEV_DOEPCTL9_CNAK_RESET 0x0
123586 /* Extracts the ALT_USB_DEV_DOEPCTL9_CNAK field value from a register. */
123587 #define ALT_USB_DEV_DOEPCTL9_CNAK_GET(value) (((value) & 0x04000000) >> 26)
123588 /* Produces a ALT_USB_DEV_DOEPCTL9_CNAK register field value suitable for setting the register. */
123589 #define ALT_USB_DEV_DOEPCTL9_CNAK_SET(value) (((value) << 26) & 0x04000000)
123590 
123591 /*
123592  * Field : snak
123593  *
123594  * Set NAK (SNAK)
123595  *
123596  * A write to this bit sets the NAK bit For the endpoint.
123597  *
123598  * Using this bit, the application can control the transmission of NAK
123599  *
123600  * handshakes on an endpoint. The core can also Set this bit For an
123601  *
123602  * endpoint after a SETUP packet is received on that endpoint.
123603  *
123604  * Field Enumeration Values:
123605  *
123606  * Enum | Value | Description
123607  * :----------------------------------|:------|:------------
123608  * ALT_USB_DEV_DOEPCTL9_SNAK_E_INACT | 0x0 | No Set NAK
123609  * ALT_USB_DEV_DOEPCTL9_SNAK_E_ACT | 0x1 | Set NAK
123610  *
123611  * Field Access Macros:
123612  *
123613  */
123614 /*
123615  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNAK
123616  *
123617  * No Set NAK
123618  */
123619 #define ALT_USB_DEV_DOEPCTL9_SNAK_E_INACT 0x0
123620 /*
123621  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNAK
123622  *
123623  * Set NAK
123624  */
123625 #define ALT_USB_DEV_DOEPCTL9_SNAK_E_ACT 0x1
123626 
123627 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */
123628 #define ALT_USB_DEV_DOEPCTL9_SNAK_LSB 27
123629 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */
123630 #define ALT_USB_DEV_DOEPCTL9_SNAK_MSB 27
123631 /* The width in bits of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */
123632 #define ALT_USB_DEV_DOEPCTL9_SNAK_WIDTH 1
123633 /* The mask used to set the ALT_USB_DEV_DOEPCTL9_SNAK register field value. */
123634 #define ALT_USB_DEV_DOEPCTL9_SNAK_SET_MSK 0x08000000
123635 /* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SNAK register field value. */
123636 #define ALT_USB_DEV_DOEPCTL9_SNAK_CLR_MSK 0xf7ffffff
123637 /* The reset value of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */
123638 #define ALT_USB_DEV_DOEPCTL9_SNAK_RESET 0x0
123639 /* Extracts the ALT_USB_DEV_DOEPCTL9_SNAK field value from a register. */
123640 #define ALT_USB_DEV_DOEPCTL9_SNAK_GET(value) (((value) & 0x08000000) >> 27)
123641 /* Produces a ALT_USB_DEV_DOEPCTL9_SNAK register field value suitable for setting the register. */
123642 #define ALT_USB_DEV_DOEPCTL9_SNAK_SET(value) (((value) << 27) & 0x08000000)
123643 
123644 /*
123645  * Field : setd0pid
123646  *
123647  * Set DATA0 PID (SetD0PID)
123648  *
123649  * Applies to interrupt/bulk IN and OUT endpoints only.
123650  *
123651  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
123652  * to DATA0.
123653  *
123654  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
123655  *
123656  * DMA mode.
123657  *
123658  * 1'b0 WO
123659  *
123660  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
123661  *
123662  * Applies to isochronous IN and OUT endpoints only.
123663  *
123664  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
123665  * (micro)
123666  *
123667  * frame.
123668  *
123669  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
123670  * number
123671  *
123672  * in which to send data is in the transmit descriptor structure. The frame in
123673  * which to
123674  *
123675  * receive data is updated in receive descriptor structure.
123676  *
123677  * Field Enumeration Values:
123678  *
123679  * Enum | Value | Description
123680  * :-------------------------------------|:------|:------------------------------------
123681  * ALT_USB_DEV_DOEPCTL9_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
123682  * ALT_USB_DEV_DOEPCTL9_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
123683  *
123684  * Field Access Macros:
123685  *
123686  */
123687 /*
123688  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD0PID
123689  *
123690  * Disables Set DATA0 PID
123691  */
123692 #define ALT_USB_DEV_DOEPCTL9_SETD0PID_E_DISD 0x0
123693 /*
123694  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD0PID
123695  *
123696  * Enables Endpoint Data PID to DATA0)
123697  */
123698 #define ALT_USB_DEV_DOEPCTL9_SETD0PID_E_END 0x1
123699 
123700 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */
123701 #define ALT_USB_DEV_DOEPCTL9_SETD0PID_LSB 28
123702 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */
123703 #define ALT_USB_DEV_DOEPCTL9_SETD0PID_MSB 28
123704 /* The width in bits of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */
123705 #define ALT_USB_DEV_DOEPCTL9_SETD0PID_WIDTH 1
123706 /* The mask used to set the ALT_USB_DEV_DOEPCTL9_SETD0PID register field value. */
123707 #define ALT_USB_DEV_DOEPCTL9_SETD0PID_SET_MSK 0x10000000
123708 /* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SETD0PID register field value. */
123709 #define ALT_USB_DEV_DOEPCTL9_SETD0PID_CLR_MSK 0xefffffff
123710 /* The reset value of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */
123711 #define ALT_USB_DEV_DOEPCTL9_SETD0PID_RESET 0x0
123712 /* Extracts the ALT_USB_DEV_DOEPCTL9_SETD0PID field value from a register. */
123713 #define ALT_USB_DEV_DOEPCTL9_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
123714 /* Produces a ALT_USB_DEV_DOEPCTL9_SETD0PID register field value suitable for setting the register. */
123715 #define ALT_USB_DEV_DOEPCTL9_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
123716 
123717 /*
123718  * Field : setd1pid
123719  *
123720  * Set DATA1 PID (SetD1PID)
123721  *
123722  * Applies to interrupt/bulk IN and OUT endpoints only.
123723  *
123724  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
123725  * to DATA1.
123726  *
123727  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
123728  *
123729  * DMA mode.
123730  *
123731  * Set Odd (micro)frame (SetOddFr)
123732  *
123733  * Applies to isochronous IN and OUT endpoints only.
123734  *
123735  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
123736  *
123737  * (micro)frame.
123738  *
123739  * This field is not applicable for Scatter/Gather DMA mode.
123740  *
123741  * Field Enumeration Values:
123742  *
123743  * Enum | Value | Description
123744  * :-------------------------------------|:------|:-----------------------
123745  * ALT_USB_DEV_DOEPCTL9_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
123746  * ALT_USB_DEV_DOEPCTL9_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
123747  *
123748  * Field Access Macros:
123749  *
123750  */
123751 /*
123752  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD1PID
123753  *
123754  * Disables Set DATA1 PID
123755  */
123756 #define ALT_USB_DEV_DOEPCTL9_SETD1PID_E_DISD 0x0
123757 /*
123758  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD1PID
123759  *
123760  * Enables Set DATA1 PID
123761  */
123762 #define ALT_USB_DEV_DOEPCTL9_SETD1PID_E_END 0x1
123763 
123764 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */
123765 #define ALT_USB_DEV_DOEPCTL9_SETD1PID_LSB 29
123766 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */
123767 #define ALT_USB_DEV_DOEPCTL9_SETD1PID_MSB 29
123768 /* The width in bits of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */
123769 #define ALT_USB_DEV_DOEPCTL9_SETD1PID_WIDTH 1
123770 /* The mask used to set the ALT_USB_DEV_DOEPCTL9_SETD1PID register field value. */
123771 #define ALT_USB_DEV_DOEPCTL9_SETD1PID_SET_MSK 0x20000000
123772 /* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SETD1PID register field value. */
123773 #define ALT_USB_DEV_DOEPCTL9_SETD1PID_CLR_MSK 0xdfffffff
123774 /* The reset value of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */
123775 #define ALT_USB_DEV_DOEPCTL9_SETD1PID_RESET 0x0
123776 /* Extracts the ALT_USB_DEV_DOEPCTL9_SETD1PID field value from a register. */
123777 #define ALT_USB_DEV_DOEPCTL9_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
123778 /* Produces a ALT_USB_DEV_DOEPCTL9_SETD1PID register field value suitable for setting the register. */
123779 #define ALT_USB_DEV_DOEPCTL9_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
123780 
123781 /*
123782  * Field : epdis
123783  *
123784  * Endpoint Disable (EPDis)
123785  *
123786  * Applies to IN and OUT endpoints.
123787  *
123788  * The application sets this bit to stop transmitting/receiving data on an
123789  * endpoint, even
123790  *
123791  * before the transfer for that endpoint is complete. The application must wait for
123792  * the
123793  *
123794  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
123795  * clears
123796  *
123797  * this bit before setting the Endpoint Disabled interrupt. The application must
123798  * set this bit
123799  *
123800  * only if Endpoint Enable is already set for this endpoint.
123801  *
123802  * Field Enumeration Values:
123803  *
123804  * Enum | Value | Description
123805  * :-----------------------------------|:------|:--------------------
123806  * ALT_USB_DEV_DOEPCTL9_EPDIS_E_INACT | 0x0 | No Endpoint Disable
123807  * ALT_USB_DEV_DOEPCTL9_EPDIS_E_ACT | 0x1 | Endpoint Disable
123808  *
123809  * Field Access Macros:
123810  *
123811  */
123812 /*
123813  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPDIS
123814  *
123815  * No Endpoint Disable
123816  */
123817 #define ALT_USB_DEV_DOEPCTL9_EPDIS_E_INACT 0x0
123818 /*
123819  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPDIS
123820  *
123821  * Endpoint Disable
123822  */
123823 #define ALT_USB_DEV_DOEPCTL9_EPDIS_E_ACT 0x1
123824 
123825 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */
123826 #define ALT_USB_DEV_DOEPCTL9_EPDIS_LSB 30
123827 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */
123828 #define ALT_USB_DEV_DOEPCTL9_EPDIS_MSB 30
123829 /* The width in bits of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */
123830 #define ALT_USB_DEV_DOEPCTL9_EPDIS_WIDTH 1
123831 /* The mask used to set the ALT_USB_DEV_DOEPCTL9_EPDIS register field value. */
123832 #define ALT_USB_DEV_DOEPCTL9_EPDIS_SET_MSK 0x40000000
123833 /* The mask used to clear the ALT_USB_DEV_DOEPCTL9_EPDIS register field value. */
123834 #define ALT_USB_DEV_DOEPCTL9_EPDIS_CLR_MSK 0xbfffffff
123835 /* The reset value of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */
123836 #define ALT_USB_DEV_DOEPCTL9_EPDIS_RESET 0x0
123837 /* Extracts the ALT_USB_DEV_DOEPCTL9_EPDIS field value from a register. */
123838 #define ALT_USB_DEV_DOEPCTL9_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
123839 /* Produces a ALT_USB_DEV_DOEPCTL9_EPDIS register field value suitable for setting the register. */
123840 #define ALT_USB_DEV_DOEPCTL9_EPDIS_SET(value) (((value) << 30) & 0x40000000)
123841 
123842 /*
123843  * Field : epena
123844  *
123845  * Endpoint Enable (EPEna)
123846  *
123847  * Applies to IN and OUT endpoints.
123848  *
123849  * When Scatter/Gather DMA mode is enabled,
123850  *
123851  * For IN endpoints this bit indicates that the descriptor structure and data
123852  * buffer with
123853  *
123854  * data ready to transmit is setup.
123855  *
123856  * For OUT endpoint it indicates that the descriptor structure and data buffer to
123857  *
123858  * receive data is setup.
123859  *
123860  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
123861  *
123862  * DMA mode:
123863  *
123864  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
123865  * the
123866  *
123867  * endpoint.
123868  *
123869  * * For OUT endpoints, this bit indicates that the application has allocated the
123870  *
123871  * memory to start receiving data from the USB.
123872  *
123873  * * The core clears this bit before setting any of the following interrupts on
123874  * this
123875  *
123876  * endpoint:
123877  *
123878  * SETUP Phase Done
123879  *
123880  * Endpoint Disabled
123881  *
123882  * Transfer Completed
123883  *
123884  * Note: For control endpoints in DMA mode, this bit must be set to be able to
123885  * transfer
123886  *
123887  * SETUP data packets in memory.
123888  *
123889  * Field Enumeration Values:
123890  *
123891  * Enum | Value | Description
123892  * :-----------------------------------|:------|:-------------------------
123893  * ALT_USB_DEV_DOEPCTL9_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
123894  * ALT_USB_DEV_DOEPCTL9_EPENA_E_ACT | 0x1 | Endpoint Enable active
123895  *
123896  * Field Access Macros:
123897  *
123898  */
123899 /*
123900  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPENA
123901  *
123902  * Endpoint Enable inactive
123903  */
123904 #define ALT_USB_DEV_DOEPCTL9_EPENA_E_INACT 0x0
123905 /*
123906  * Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPENA
123907  *
123908  * Endpoint Enable active
123909  */
123910 #define ALT_USB_DEV_DOEPCTL9_EPENA_E_ACT 0x1
123911 
123912 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */
123913 #define ALT_USB_DEV_DOEPCTL9_EPENA_LSB 31
123914 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */
123915 #define ALT_USB_DEV_DOEPCTL9_EPENA_MSB 31
123916 /* The width in bits of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */
123917 #define ALT_USB_DEV_DOEPCTL9_EPENA_WIDTH 1
123918 /* The mask used to set the ALT_USB_DEV_DOEPCTL9_EPENA register field value. */
123919 #define ALT_USB_DEV_DOEPCTL9_EPENA_SET_MSK 0x80000000
123920 /* The mask used to clear the ALT_USB_DEV_DOEPCTL9_EPENA register field value. */
123921 #define ALT_USB_DEV_DOEPCTL9_EPENA_CLR_MSK 0x7fffffff
123922 /* The reset value of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */
123923 #define ALT_USB_DEV_DOEPCTL9_EPENA_RESET 0x0
123924 /* Extracts the ALT_USB_DEV_DOEPCTL9_EPENA field value from a register. */
123925 #define ALT_USB_DEV_DOEPCTL9_EPENA_GET(value) (((value) & 0x80000000) >> 31)
123926 /* Produces a ALT_USB_DEV_DOEPCTL9_EPENA register field value suitable for setting the register. */
123927 #define ALT_USB_DEV_DOEPCTL9_EPENA_SET(value) (((value) << 31) & 0x80000000)
123928 
123929 #ifndef __ASSEMBLY__
123930 /*
123931  * WARNING: The C register and register group struct declarations are provided for
123932  * convenience and illustrative purposes. They should, however, be used with
123933  * caution as the C language standard provides no guarantees about the alignment or
123934  * atomicity of device memory accesses. The recommended practice for writing
123935  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
123936  * alt_write_word() functions.
123937  *
123938  * The struct declaration for register ALT_USB_DEV_DOEPCTL9.
123939  */
123940 struct ALT_USB_DEV_DOEPCTL9_s
123941 {
123942  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL9_MPS */
123943  uint32_t : 4; /* *UNDEFINED* */
123944  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL9_USBACTEP */
123945  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL9_DPID */
123946  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL9_NAKSTS */
123947  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL9_EPTYPE */
123948  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL9_SNP */
123949  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL9_STALL */
123950  uint32_t : 4; /* *UNDEFINED* */
123951  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL9_CNAK */
123952  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL9_SNAK */
123953  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL9_SETD0PID */
123954  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL9_SETD1PID */
123955  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL9_EPDIS */
123956  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL9_EPENA */
123957 };
123958 
123959 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL9. */
123960 typedef volatile struct ALT_USB_DEV_DOEPCTL9_s ALT_USB_DEV_DOEPCTL9_t;
123961 #endif /* __ASSEMBLY__ */
123962 
123963 /* The reset value of the ALT_USB_DEV_DOEPCTL9 register. */
123964 #define ALT_USB_DEV_DOEPCTL9_RESET 0x00000000
123965 /* The byte offset of the ALT_USB_DEV_DOEPCTL9 register from the beginning of the component. */
123966 #define ALT_USB_DEV_DOEPCTL9_OFST 0x420
123967 /* The address of the ALT_USB_DEV_DOEPCTL9 register. */
123968 #define ALT_USB_DEV_DOEPCTL9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL9_OFST))
123969 
123970 /*
123971  * Register : doepint9
123972  *
123973  * Device OUT Endpoint 9 Interrupt Register
123974  *
123975  * Register Layout
123976  *
123977  * Bits | Access | Reset | Description
123978  * :--------|:-------|:------|:------------------------------------
123979  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_XFERCOMPL
123980  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_EPDISBLD
123981  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_AHBERR
123982  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_SETUP
123983  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS
123984  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_STSPHSERCVD
123985  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP
123986  * [7] | ??? | 0x0 | *UNDEFINED*
123987  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_OUTPKTERR
123988  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_BNAINTR
123989  * [10] | ??? | 0x0 | *UNDEFINED*
123990  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_PKTDRPSTS
123991  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_BBLEERR
123992  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_NAKINTRPT
123993  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_NYETINTRPT
123994  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_STUPPKTRCVD
123995  * [31:16] | ??? | 0x0 | *UNDEFINED*
123996  *
123997  */
123998 /*
123999  * Field : xfercompl
124000  *
124001  * Transfer Completed Interrupt (XferCompl)
124002  *
124003  * Applies to IN and OUT endpoints.
124004  *
124005  * When Scatter/Gather DMA mode is enabled
124006  *
124007  * * For IN endpoint this field indicates that the requested data
124008  *
124009  * from the descriptor is moved from external system memory
124010  *
124011  * to internal FIFO.
124012  *
124013  * * For OUT endpoint this field indicates that the requested
124014  *
124015  * data from the internal FIFO is moved to external system
124016  *
124017  * memory. This interrupt is generated only when the
124018  *
124019  * corresponding endpoint descriptor is closed, and the IOC
124020  *
124021  * bit For the corresponding descriptor is Set.
124022  *
124023  * When Scatter/Gather DMA mode is disabled, this field
124024  *
124025  * indicates that the programmed transfer is complete on the
124026  *
124027  * AHB as well as on the USB, For this endpoint.
124028  *
124029  * Field Enumeration Values:
124030  *
124031  * Enum | Value | Description
124032  * :---------------------------------------|:------|:-----------------------------
124033  * ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_INACT | 0x0 | No Interrupt
124034  * ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
124035  *
124036  * Field Access Macros:
124037  *
124038  */
124039 /*
124040  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_XFERCOMPL
124041  *
124042  * No Interrupt
124043  */
124044 #define ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_INACT 0x0
124045 /*
124046  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_XFERCOMPL
124047  *
124048  * Transfer Completed Interrupt
124049  */
124050 #define ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_ACT 0x1
124051 
124052 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */
124053 #define ALT_USB_DEV_DOEPINT9_XFERCOMPL_LSB 0
124054 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */
124055 #define ALT_USB_DEV_DOEPINT9_XFERCOMPL_MSB 0
124056 /* The width in bits of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */
124057 #define ALT_USB_DEV_DOEPINT9_XFERCOMPL_WIDTH 1
124058 /* The mask used to set the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field value. */
124059 #define ALT_USB_DEV_DOEPINT9_XFERCOMPL_SET_MSK 0x00000001
124060 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field value. */
124061 #define ALT_USB_DEV_DOEPINT9_XFERCOMPL_CLR_MSK 0xfffffffe
124062 /* The reset value of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */
124063 #define ALT_USB_DEV_DOEPINT9_XFERCOMPL_RESET 0x0
124064 /* Extracts the ALT_USB_DEV_DOEPINT9_XFERCOMPL field value from a register. */
124065 #define ALT_USB_DEV_DOEPINT9_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
124066 /* Produces a ALT_USB_DEV_DOEPINT9_XFERCOMPL register field value suitable for setting the register. */
124067 #define ALT_USB_DEV_DOEPINT9_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
124068 
124069 /*
124070  * Field : epdisbld
124071  *
124072  * Endpoint Disabled Interrupt (EPDisbld)
124073  *
124074  * Applies to IN and OUT endpoints.
124075  *
124076  * This bit indicates that the endpoint is disabled per the
124077  *
124078  * application's request.
124079  *
124080  * Field Enumeration Values:
124081  *
124082  * Enum | Value | Description
124083  * :--------------------------------------|:------|:----------------------------
124084  * ALT_USB_DEV_DOEPINT9_EPDISBLD_E_INACT | 0x0 | No Interrupt
124085  * ALT_USB_DEV_DOEPINT9_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
124086  *
124087  * Field Access Macros:
124088  *
124089  */
124090 /*
124091  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_EPDISBLD
124092  *
124093  * No Interrupt
124094  */
124095 #define ALT_USB_DEV_DOEPINT9_EPDISBLD_E_INACT 0x0
124096 /*
124097  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_EPDISBLD
124098  *
124099  * Endpoint Disabled Interrupt
124100  */
124101 #define ALT_USB_DEV_DOEPINT9_EPDISBLD_E_ACT 0x1
124102 
124103 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */
124104 #define ALT_USB_DEV_DOEPINT9_EPDISBLD_LSB 1
124105 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */
124106 #define ALT_USB_DEV_DOEPINT9_EPDISBLD_MSB 1
124107 /* The width in bits of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */
124108 #define ALT_USB_DEV_DOEPINT9_EPDISBLD_WIDTH 1
124109 /* The mask used to set the ALT_USB_DEV_DOEPINT9_EPDISBLD register field value. */
124110 #define ALT_USB_DEV_DOEPINT9_EPDISBLD_SET_MSK 0x00000002
124111 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_EPDISBLD register field value. */
124112 #define ALT_USB_DEV_DOEPINT9_EPDISBLD_CLR_MSK 0xfffffffd
124113 /* The reset value of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */
124114 #define ALT_USB_DEV_DOEPINT9_EPDISBLD_RESET 0x0
124115 /* Extracts the ALT_USB_DEV_DOEPINT9_EPDISBLD field value from a register. */
124116 #define ALT_USB_DEV_DOEPINT9_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
124117 /* Produces a ALT_USB_DEV_DOEPINT9_EPDISBLD register field value suitable for setting the register. */
124118 #define ALT_USB_DEV_DOEPINT9_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
124119 
124120 /*
124121  * Field : ahberr
124122  *
124123  * AHB Error (AHBErr)
124124  *
124125  * Applies to IN and OUT endpoints.
124126  *
124127  * This is generated only in Internal DMA mode when there is an
124128  *
124129  * AHB error during an AHB read/write. The application can read
124130  *
124131  * the corresponding endpoint DMA address register to get the
124132  *
124133  * error address.
124134  *
124135  * Field Enumeration Values:
124136  *
124137  * Enum | Value | Description
124138  * :------------------------------------|:------|:--------------------
124139  * ALT_USB_DEV_DOEPINT9_AHBERR_E_INACT | 0x0 | No Interrupt
124140  * ALT_USB_DEV_DOEPINT9_AHBERR_E_ACT | 0x1 | AHB Error interrupt
124141  *
124142  * Field Access Macros:
124143  *
124144  */
124145 /*
124146  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_AHBERR
124147  *
124148  * No Interrupt
124149  */
124150 #define ALT_USB_DEV_DOEPINT9_AHBERR_E_INACT 0x0
124151 /*
124152  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_AHBERR
124153  *
124154  * AHB Error interrupt
124155  */
124156 #define ALT_USB_DEV_DOEPINT9_AHBERR_E_ACT 0x1
124157 
124158 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */
124159 #define ALT_USB_DEV_DOEPINT9_AHBERR_LSB 2
124160 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */
124161 #define ALT_USB_DEV_DOEPINT9_AHBERR_MSB 2
124162 /* The width in bits of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */
124163 #define ALT_USB_DEV_DOEPINT9_AHBERR_WIDTH 1
124164 /* The mask used to set the ALT_USB_DEV_DOEPINT9_AHBERR register field value. */
124165 #define ALT_USB_DEV_DOEPINT9_AHBERR_SET_MSK 0x00000004
124166 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_AHBERR register field value. */
124167 #define ALT_USB_DEV_DOEPINT9_AHBERR_CLR_MSK 0xfffffffb
124168 /* The reset value of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */
124169 #define ALT_USB_DEV_DOEPINT9_AHBERR_RESET 0x0
124170 /* Extracts the ALT_USB_DEV_DOEPINT9_AHBERR field value from a register. */
124171 #define ALT_USB_DEV_DOEPINT9_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
124172 /* Produces a ALT_USB_DEV_DOEPINT9_AHBERR register field value suitable for setting the register. */
124173 #define ALT_USB_DEV_DOEPINT9_AHBERR_SET(value) (((value) << 2) & 0x00000004)
124174 
124175 /*
124176  * Field : setup
124177  *
124178  * SETUP Phase Done (SetUp)
124179  *
124180  * Applies to control OUT endpoints only.
124181  *
124182  * Indicates that the SETUP phase For the control endpoint is
124183  *
124184  * complete and no more back-to-back SETUP packets were
124185  *
124186  * received For the current control transfer. On this interrupt, the
124187  *
124188  * application can decode the received SETUP data packet.
124189  *
124190  * Field Enumeration Values:
124191  *
124192  * Enum | Value | Description
124193  * :-----------------------------------|:------|:--------------------
124194  * ALT_USB_DEV_DOEPINT9_SETUP_E_INACT | 0x0 | No SETUP Phase Done
124195  * ALT_USB_DEV_DOEPINT9_SETUP_E_ACT | 0x1 | SETUP Phase Done
124196  *
124197  * Field Access Macros:
124198  *
124199  */
124200 /*
124201  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_SETUP
124202  *
124203  * No SETUP Phase Done
124204  */
124205 #define ALT_USB_DEV_DOEPINT9_SETUP_E_INACT 0x0
124206 /*
124207  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_SETUP
124208  *
124209  * SETUP Phase Done
124210  */
124211 #define ALT_USB_DEV_DOEPINT9_SETUP_E_ACT 0x1
124212 
124213 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_SETUP register field. */
124214 #define ALT_USB_DEV_DOEPINT9_SETUP_LSB 3
124215 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_SETUP register field. */
124216 #define ALT_USB_DEV_DOEPINT9_SETUP_MSB 3
124217 /* The width in bits of the ALT_USB_DEV_DOEPINT9_SETUP register field. */
124218 #define ALT_USB_DEV_DOEPINT9_SETUP_WIDTH 1
124219 /* The mask used to set the ALT_USB_DEV_DOEPINT9_SETUP register field value. */
124220 #define ALT_USB_DEV_DOEPINT9_SETUP_SET_MSK 0x00000008
124221 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_SETUP register field value. */
124222 #define ALT_USB_DEV_DOEPINT9_SETUP_CLR_MSK 0xfffffff7
124223 /* The reset value of the ALT_USB_DEV_DOEPINT9_SETUP register field. */
124224 #define ALT_USB_DEV_DOEPINT9_SETUP_RESET 0x0
124225 /* Extracts the ALT_USB_DEV_DOEPINT9_SETUP field value from a register. */
124226 #define ALT_USB_DEV_DOEPINT9_SETUP_GET(value) (((value) & 0x00000008) >> 3)
124227 /* Produces a ALT_USB_DEV_DOEPINT9_SETUP register field value suitable for setting the register. */
124228 #define ALT_USB_DEV_DOEPINT9_SETUP_SET(value) (((value) << 3) & 0x00000008)
124229 
124230 /*
124231  * Field : outtknepdis
124232  *
124233  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
124234  *
124235  * Applies only to control OUT endpoints.
124236  *
124237  * Indicates that an OUT token was received when the endpoint
124238  *
124239  * was not yet enabled. This interrupt is asserted on the endpoint
124240  *
124241  * For which the OUT token was received.
124242  *
124243  * Field Enumeration Values:
124244  *
124245  * Enum | Value | Description
124246  * :-----------------------------------------|:------|:---------------------------------------------
124247  * ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
124248  * ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
124249  *
124250  * Field Access Macros:
124251  *
124252  */
124253 /*
124254  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS
124255  *
124256  * No OUT Token Received When Endpoint Disabled
124257  */
124258 #define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_INACT 0x0
124259 /*
124260  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS
124261  *
124262  * OUT Token Received When Endpoint Disabled
124263  */
124264 #define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_ACT 0x1
124265 
124266 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */
124267 #define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_LSB 4
124268 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */
124269 #define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_MSB 4
124270 /* The width in bits of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */
124271 #define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_WIDTH 1
124272 /* The mask used to set the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field value. */
124273 #define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_SET_MSK 0x00000010
124274 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field value. */
124275 #define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_CLR_MSK 0xffffffef
124276 /* The reset value of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */
124277 #define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_RESET 0x0
124278 /* Extracts the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS field value from a register. */
124279 #define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
124280 /* Produces a ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field value suitable for setting the register. */
124281 #define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
124282 
124283 /*
124284  * Field : stsphsercvd
124285  *
124286  * Status Phase Received For Control Write (StsPhseRcvd)
124287  *
124288  * This interrupt is valid only For Control OUT endpoints and only in
124289  *
124290  * Scatter Gather DMA mode.
124291  *
124292  * This interrupt is generated only after the core has transferred all
124293  *
124294  * the data that the host has sent during the data phase of a control
124295  *
124296  * write transfer, to the system memory buffer.
124297  *
124298  * The interrupt indicates to the application that the host has
124299  *
124300  * switched from data phase to the status phase of a Control Write
124301  *
124302  * transfer. The application can use this interrupt to ACK or STALL
124303  *
124304  * the Status phase, after it has decoded the data phase. This is
124305  *
124306  * applicable only in Case of Scatter Gather DMA mode.
124307  *
124308  * Field Enumeration Values:
124309  *
124310  * Enum | Value | Description
124311  * :-----------------------------------------|:------|:-------------------------------------------
124312  * ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
124313  * ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
124314  *
124315  * Field Access Macros:
124316  *
124317  */
124318 /*
124319  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_STSPHSERCVD
124320  *
124321  * No Status Phase Received for Control Write
124322  */
124323 #define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_INACT 0x0
124324 /*
124325  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_STSPHSERCVD
124326  *
124327  * Status Phase Received for Control Write
124328  */
124329 #define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_ACT 0x1
124330 
124331 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */
124332 #define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_LSB 5
124333 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */
124334 #define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_MSB 5
124335 /* The width in bits of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */
124336 #define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_WIDTH 1
124337 /* The mask used to set the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field value. */
124338 #define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_SET_MSK 0x00000020
124339 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field value. */
124340 #define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_CLR_MSK 0xffffffdf
124341 /* The reset value of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */
124342 #define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_RESET 0x0
124343 /* Extracts the ALT_USB_DEV_DOEPINT9_STSPHSERCVD field value from a register. */
124344 #define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
124345 /* Produces a ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field value suitable for setting the register. */
124346 #define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
124347 
124348 /*
124349  * Field : back2backsetup
124350  *
124351  * Back-to-Back SETUP Packets Received (Back2BackSETup)
124352  *
124353  * Applies to Control OUT endpoints only.
124354  *
124355  * This bit indicates that the core has received more than three
124356  *
124357  * back-to-back SETUP packets For this particular endpoint. For
124358  *
124359  * information about handling this interrupt,
124360  *
124361  * Field Enumeration Values:
124362  *
124363  * Enum | Value | Description
124364  * :--------------------------------------------|:------|:---------------------------------------
124365  * ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
124366  * ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
124367  *
124368  * Field Access Macros:
124369  *
124370  */
124371 /*
124372  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP
124373  *
124374  * No Back-to-Back SETUP Packets Received
124375  */
124376 #define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_INACT 0x0
124377 /*
124378  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP
124379  *
124380  * Back-to-Back SETUP Packets Received
124381  */
124382 #define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_ACT 0x1
124383 
124384 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */
124385 #define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_LSB 6
124386 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */
124387 #define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_MSB 6
124388 /* The width in bits of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */
124389 #define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_WIDTH 1
124390 /* The mask used to set the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field value. */
124391 #define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_SET_MSK 0x00000040
124392 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field value. */
124393 #define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_CLR_MSK 0xffffffbf
124394 /* The reset value of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */
124395 #define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_RESET 0x0
124396 /* Extracts the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP field value from a register. */
124397 #define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
124398 /* Produces a ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field value suitable for setting the register. */
124399 #define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
124400 
124401 /*
124402  * Field : outpkterr
124403  *
124404  * OUT Packet Error (OutPktErr)
124405  *
124406  * Applies to OUT endpoints Only
124407  *
124408  * This interrupt is valid only when thresholding is enabled. This interrupt is
124409  * asserted when the
124410  *
124411  * core detects an overflow or a CRC error For non-Isochronous
124412  *
124413  * OUT packet.
124414  *
124415  * Field Enumeration Values:
124416  *
124417  * Enum | Value | Description
124418  * :---------------------------------------|:------|:--------------------
124419  * ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
124420  * ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
124421  *
124422  * Field Access Macros:
124423  *
124424  */
124425 /*
124426  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTPKTERR
124427  *
124428  * No OUT Packet Error
124429  */
124430 #define ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_INACT 0x0
124431 /*
124432  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTPKTERR
124433  *
124434  * OUT Packet Error
124435  */
124436 #define ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_ACT 0x1
124437 
124438 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */
124439 #define ALT_USB_DEV_DOEPINT9_OUTPKTERR_LSB 8
124440 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */
124441 #define ALT_USB_DEV_DOEPINT9_OUTPKTERR_MSB 8
124442 /* The width in bits of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */
124443 #define ALT_USB_DEV_DOEPINT9_OUTPKTERR_WIDTH 1
124444 /* The mask used to set the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field value. */
124445 #define ALT_USB_DEV_DOEPINT9_OUTPKTERR_SET_MSK 0x00000100
124446 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field value. */
124447 #define ALT_USB_DEV_DOEPINT9_OUTPKTERR_CLR_MSK 0xfffffeff
124448 /* The reset value of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */
124449 #define ALT_USB_DEV_DOEPINT9_OUTPKTERR_RESET 0x0
124450 /* Extracts the ALT_USB_DEV_DOEPINT9_OUTPKTERR field value from a register. */
124451 #define ALT_USB_DEV_DOEPINT9_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
124452 /* Produces a ALT_USB_DEV_DOEPINT9_OUTPKTERR register field value suitable for setting the register. */
124453 #define ALT_USB_DEV_DOEPINT9_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
124454 
124455 /*
124456  * Field : bnaintr
124457  *
124458  * BNA (Buffer Not Available) Interrupt (BNAIntr)
124459  *
124460  * This bit is valid only when Scatter/Gather DMA mode is enabled.
124461  *
124462  * The core generates this interrupt when the descriptor accessed
124463  *
124464  * is not ready For the Core to process, such as Host busy or DMA
124465  *
124466  * done
124467  *
124468  * Field Enumeration Values:
124469  *
124470  * Enum | Value | Description
124471  * :-------------------------------------|:------|:--------------
124472  * ALT_USB_DEV_DOEPINT9_BNAINTR_E_INACT | 0x0 | No interrupt
124473  * ALT_USB_DEV_DOEPINT9_BNAINTR_E_ACT | 0x1 | BNA interrupt
124474  *
124475  * Field Access Macros:
124476  *
124477  */
124478 /*
124479  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BNAINTR
124480  *
124481  * No interrupt
124482  */
124483 #define ALT_USB_DEV_DOEPINT9_BNAINTR_E_INACT 0x0
124484 /*
124485  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BNAINTR
124486  *
124487  * BNA interrupt
124488  */
124489 #define ALT_USB_DEV_DOEPINT9_BNAINTR_E_ACT 0x1
124490 
124491 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */
124492 #define ALT_USB_DEV_DOEPINT9_BNAINTR_LSB 9
124493 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */
124494 #define ALT_USB_DEV_DOEPINT9_BNAINTR_MSB 9
124495 /* The width in bits of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */
124496 #define ALT_USB_DEV_DOEPINT9_BNAINTR_WIDTH 1
124497 /* The mask used to set the ALT_USB_DEV_DOEPINT9_BNAINTR register field value. */
124498 #define ALT_USB_DEV_DOEPINT9_BNAINTR_SET_MSK 0x00000200
124499 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_BNAINTR register field value. */
124500 #define ALT_USB_DEV_DOEPINT9_BNAINTR_CLR_MSK 0xfffffdff
124501 /* The reset value of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */
124502 #define ALT_USB_DEV_DOEPINT9_BNAINTR_RESET 0x0
124503 /* Extracts the ALT_USB_DEV_DOEPINT9_BNAINTR field value from a register. */
124504 #define ALT_USB_DEV_DOEPINT9_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
124505 /* Produces a ALT_USB_DEV_DOEPINT9_BNAINTR register field value suitable for setting the register. */
124506 #define ALT_USB_DEV_DOEPINT9_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
124507 
124508 /*
124509  * Field : pktdrpsts
124510  *
124511  * Packet Drop Status (PktDrpSts)
124512  *
124513  * This bit indicates to the application that an ISOC OUT packet has been dropped.
124514  * This
124515  *
124516  * bit does not have an associated mask bit and does not generate an interrupt.
124517  *
124518  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
124519  * transfer
124520  *
124521  * interrupt feature is selected.
124522  *
124523  * Field Enumeration Values:
124524  *
124525  * Enum | Value | Description
124526  * :---------------------------------------|:------|:-----------------------------
124527  * ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_INACT | 0x0 | No interrupt
124528  * ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
124529  *
124530  * Field Access Macros:
124531  *
124532  */
124533 /*
124534  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_PKTDRPSTS
124535  *
124536  * No interrupt
124537  */
124538 #define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_INACT 0x0
124539 /*
124540  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_PKTDRPSTS
124541  *
124542  * Packet Drop Status interrupt
124543  */
124544 #define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_ACT 0x1
124545 
124546 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */
124547 #define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_LSB 11
124548 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */
124549 #define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_MSB 11
124550 /* The width in bits of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */
124551 #define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_WIDTH 1
124552 /* The mask used to set the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field value. */
124553 #define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_SET_MSK 0x00000800
124554 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field value. */
124555 #define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_CLR_MSK 0xfffff7ff
124556 /* The reset value of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */
124557 #define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_RESET 0x0
124558 /* Extracts the ALT_USB_DEV_DOEPINT9_PKTDRPSTS field value from a register. */
124559 #define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
124560 /* Produces a ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field value suitable for setting the register. */
124561 #define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
124562 
124563 /*
124564  * Field : bbleerr
124565  *
124566  * NAK Interrupt (BbleErr)
124567  *
124568  * The core generates this interrupt when babble is received for the endpoint.
124569  *
124570  * Field Enumeration Values:
124571  *
124572  * Enum | Value | Description
124573  * :-------------------------------------|:------|:------------------
124574  * ALT_USB_DEV_DOEPINT9_BBLEERR_E_INACT | 0x0 | No interrupt
124575  * ALT_USB_DEV_DOEPINT9_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
124576  *
124577  * Field Access Macros:
124578  *
124579  */
124580 /*
124581  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BBLEERR
124582  *
124583  * No interrupt
124584  */
124585 #define ALT_USB_DEV_DOEPINT9_BBLEERR_E_INACT 0x0
124586 /*
124587  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_BBLEERR
124588  *
124589  * BbleErr interrupt
124590  */
124591 #define ALT_USB_DEV_DOEPINT9_BBLEERR_E_ACT 0x1
124592 
124593 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */
124594 #define ALT_USB_DEV_DOEPINT9_BBLEERR_LSB 12
124595 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */
124596 #define ALT_USB_DEV_DOEPINT9_BBLEERR_MSB 12
124597 /* The width in bits of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */
124598 #define ALT_USB_DEV_DOEPINT9_BBLEERR_WIDTH 1
124599 /* The mask used to set the ALT_USB_DEV_DOEPINT9_BBLEERR register field value. */
124600 #define ALT_USB_DEV_DOEPINT9_BBLEERR_SET_MSK 0x00001000
124601 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_BBLEERR register field value. */
124602 #define ALT_USB_DEV_DOEPINT9_BBLEERR_CLR_MSK 0xffffefff
124603 /* The reset value of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */
124604 #define ALT_USB_DEV_DOEPINT9_BBLEERR_RESET 0x0
124605 /* Extracts the ALT_USB_DEV_DOEPINT9_BBLEERR field value from a register. */
124606 #define ALT_USB_DEV_DOEPINT9_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
124607 /* Produces a ALT_USB_DEV_DOEPINT9_BBLEERR register field value suitable for setting the register. */
124608 #define ALT_USB_DEV_DOEPINT9_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
124609 
124610 /*
124611  * Field : nakintrpt
124612  *
124613  * NAK Interrupt (NAKInterrupt)
124614  *
124615  * The core generates this interrupt when a NAK is transmitted or received by the
124616  * device.
124617  *
124618  * In case of isochronous IN endpoints the interrupt gets generated when a zero
124619  * length
124620  *
124621  * packet is transmitted due to un-availability of data in the TXFifo.
124622  *
124623  * Field Enumeration Values:
124624  *
124625  * Enum | Value | Description
124626  * :---------------------------------------|:------|:--------------
124627  * ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_INACT | 0x0 | No interrupt
124628  * ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
124629  *
124630  * Field Access Macros:
124631  *
124632  */
124633 /*
124634  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_NAKINTRPT
124635  *
124636  * No interrupt
124637  */
124638 #define ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_INACT 0x0
124639 /*
124640  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_NAKINTRPT
124641  *
124642  * NAK Interrupt
124643  */
124644 #define ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_ACT 0x1
124645 
124646 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */
124647 #define ALT_USB_DEV_DOEPINT9_NAKINTRPT_LSB 13
124648 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */
124649 #define ALT_USB_DEV_DOEPINT9_NAKINTRPT_MSB 13
124650 /* The width in bits of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */
124651 #define ALT_USB_DEV_DOEPINT9_NAKINTRPT_WIDTH 1
124652 /* The mask used to set the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field value. */
124653 #define ALT_USB_DEV_DOEPINT9_NAKINTRPT_SET_MSK 0x00002000
124654 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field value. */
124655 #define ALT_USB_DEV_DOEPINT9_NAKINTRPT_CLR_MSK 0xffffdfff
124656 /* The reset value of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */
124657 #define ALT_USB_DEV_DOEPINT9_NAKINTRPT_RESET 0x0
124658 /* Extracts the ALT_USB_DEV_DOEPINT9_NAKINTRPT field value from a register. */
124659 #define ALT_USB_DEV_DOEPINT9_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
124660 /* Produces a ALT_USB_DEV_DOEPINT9_NAKINTRPT register field value suitable for setting the register. */
124661 #define ALT_USB_DEV_DOEPINT9_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
124662 
124663 /*
124664  * Field : nyetintrpt
124665  *
124666  * NYET Interrupt (NYETIntrpt)
124667  *
124668  * The core generates this interrupt when a NYET response is transmitted for a non
124669  * isochronous OUT endpoint.
124670  *
124671  * Field Enumeration Values:
124672  *
124673  * Enum | Value | Description
124674  * :----------------------------------------|:------|:---------------
124675  * ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_INACT | 0x0 | No interrupt
124676  * ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
124677  *
124678  * Field Access Macros:
124679  *
124680  */
124681 /*
124682  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_NYETINTRPT
124683  *
124684  * No interrupt
124685  */
124686 #define ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_INACT 0x0
124687 /*
124688  * Enumerated value for register field ALT_USB_DEV_DOEPINT9_NYETINTRPT
124689  *
124690  * NYET Interrupt
124691  */
124692 #define ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_ACT 0x1
124693 
124694 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */
124695 #define ALT_USB_DEV_DOEPINT9_NYETINTRPT_LSB 14
124696 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */
124697 #define ALT_USB_DEV_DOEPINT9_NYETINTRPT_MSB 14
124698 /* The width in bits of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */
124699 #define ALT_USB_DEV_DOEPINT9_NYETINTRPT_WIDTH 1
124700 /* The mask used to set the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field value. */
124701 #define ALT_USB_DEV_DOEPINT9_NYETINTRPT_SET_MSK 0x00004000
124702 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field value. */
124703 #define ALT_USB_DEV_DOEPINT9_NYETINTRPT_CLR_MSK 0xffffbfff
124704 /* The reset value of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */
124705 #define ALT_USB_DEV_DOEPINT9_NYETINTRPT_RESET 0x0
124706 /* Extracts the ALT_USB_DEV_DOEPINT9_NYETINTRPT field value from a register. */
124707 #define ALT_USB_DEV_DOEPINT9_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
124708 /* Produces a ALT_USB_DEV_DOEPINT9_NYETINTRPT register field value suitable for setting the register. */
124709 #define ALT_USB_DEV_DOEPINT9_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
124710 
124711 /*
124712  * Field : stuppktrcvd
124713  *
124714  * Setup Packet Received
124715  *
124716  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
124717  *
124718  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
124719  *
124720  * setup data. There is only one Setup packet per buffer. On receiving a
124721  *
124722  * Setup packet, the DWC_otg core closes the buffer and disables the
124723  *
124724  * corresponding endpoint. The application has to re-enable the endpoint to
124725  *
124726  * receive any OUT data for the Control Transfer and reprogram the buffer
124727  *
124728  * start address.
124729  *
124730  * Note: Because of the above behavior, the DWC_otg core can receive any
124731  *
124732  * number of back to back setup packets and one buffer for every setup
124733  *
124734  * packet is used.
124735  *
124736  * 1'b0: No Setup packet received
124737  *
124738  * 1'b1: Setup packet received
124739  *
124740  * Reset: 1'b0
124741  *
124742  * Field Access Macros:
124743  *
124744  */
124745 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field. */
124746 #define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_LSB 15
124747 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field. */
124748 #define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_MSB 15
124749 /* The width in bits of the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field. */
124750 #define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_WIDTH 1
124751 /* The mask used to set the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field value. */
124752 #define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_SET_MSK 0x00008000
124753 /* The mask used to clear the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field value. */
124754 #define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_CLR_MSK 0xffff7fff
124755 /* The reset value of the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field. */
124756 #define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_RESET 0x0
124757 /* Extracts the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD field value from a register. */
124758 #define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
124759 /* Produces a ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field value suitable for setting the register. */
124760 #define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
124761 
124762 #ifndef __ASSEMBLY__
124763 /*
124764  * WARNING: The C register and register group struct declarations are provided for
124765  * convenience and illustrative purposes. They should, however, be used with
124766  * caution as the C language standard provides no guarantees about the alignment or
124767  * atomicity of device memory accesses. The recommended practice for writing
124768  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
124769  * alt_write_word() functions.
124770  *
124771  * The struct declaration for register ALT_USB_DEV_DOEPINT9.
124772  */
124773 struct ALT_USB_DEV_DOEPINT9_s
124774 {
124775  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT9_XFERCOMPL */
124776  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT9_EPDISBLD */
124777  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT9_AHBERR */
124778  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT9_SETUP */
124779  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS */
124780  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT9_STSPHSERCVD */
124781  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP */
124782  uint32_t : 1; /* *UNDEFINED* */
124783  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT9_OUTPKTERR */
124784  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT9_BNAINTR */
124785  uint32_t : 1; /* *UNDEFINED* */
124786  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT9_PKTDRPSTS */
124787  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT9_BBLEERR */
124788  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT9_NAKINTRPT */
124789  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT9_NYETINTRPT */
124790  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT9_STUPPKTRCVD */
124791  uint32_t : 16; /* *UNDEFINED* */
124792 };
124793 
124794 /* The typedef declaration for register ALT_USB_DEV_DOEPINT9. */
124795 typedef volatile struct ALT_USB_DEV_DOEPINT9_s ALT_USB_DEV_DOEPINT9_t;
124796 #endif /* __ASSEMBLY__ */
124797 
124798 /* The reset value of the ALT_USB_DEV_DOEPINT9 register. */
124799 #define ALT_USB_DEV_DOEPINT9_RESET 0x00000000
124800 /* The byte offset of the ALT_USB_DEV_DOEPINT9 register from the beginning of the component. */
124801 #define ALT_USB_DEV_DOEPINT9_OFST 0x428
124802 /* The address of the ALT_USB_DEV_DOEPINT9 register. */
124803 #define ALT_USB_DEV_DOEPINT9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT9_OFST))
124804 
124805 /*
124806  * Register : doeptsiz9
124807  *
124808  * Device OUT Endpoint 9 Transfer Size Register
124809  *
124810  * Register Layout
124811  *
124812  * Bits | Access | Reset | Description
124813  * :--------|:-------|:------|:-------------------------------
124814  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ9_XFERSIZE
124815  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ9_PKTCNT
124816  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ9_RXDPID
124817  * [31] | ??? | 0x0 | *UNDEFINED*
124818  *
124819  */
124820 /*
124821  * Field : xfersize
124822  *
124823  * Transfer Size (XferSize)
124824  *
124825  * Indicates the transfer size in bytes For endpoint 0. The core
124826  *
124827  * interrupts the application only after it has exhausted the transfer
124828  *
124829  * size amount of data. The transfer size can be Set to the
124830  *
124831  * maximum packet size of the endpoint, to be interrupted at the
124832  *
124833  * end of each packet.
124834  *
124835  * The core decrements this field every time a packet is read from
124836  *
124837  * the RxFIFO and written to the external memory.
124838  *
124839  * Field Access Macros:
124840  *
124841  */
124842 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */
124843 #define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_LSB 0
124844 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */
124845 #define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_MSB 18
124846 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */
124847 #define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_WIDTH 19
124848 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field value. */
124849 #define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_SET_MSK 0x0007ffff
124850 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field value. */
124851 #define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_CLR_MSK 0xfff80000
124852 /* The reset value of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */
124853 #define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_RESET 0x0
124854 /* Extracts the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE field value from a register. */
124855 #define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
124856 /* Produces a ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field value suitable for setting the register. */
124857 #define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
124858 
124859 /*
124860  * Field : pktcnt
124861  *
124862  * Packet Count (PktCnt)
124863  *
124864  * This field is decremented to zero after a packet is written into the
124865  *
124866  * RxFIFO.
124867  *
124868  * Field Access Macros:
124869  *
124870  */
124871 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */
124872 #define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_LSB 19
124873 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */
124874 #define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_MSB 28
124875 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */
124876 #define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_WIDTH 10
124877 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field value. */
124878 #define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_SET_MSK 0x1ff80000
124879 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field value. */
124880 #define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_CLR_MSK 0xe007ffff
124881 /* The reset value of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */
124882 #define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_RESET 0x0
124883 /* Extracts the ALT_USB_DEV_DOEPTSIZ9_PKTCNT field value from a register. */
124884 #define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
124885 /* Produces a ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field value suitable for setting the register. */
124886 #define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
124887 
124888 /*
124889  * Field : rxdpid
124890  *
124891  * Applies to isochronous OUT endpoints only.
124892  *
124893  * This is the data PID received in the last packet for this endpoint.
124894  *
124895  * 2'b00: DATA0
124896  *
124897  * 2'b01: DATA2
124898  *
124899  * 2'b10: DATA1
124900  *
124901  * 2'b11: MDATA
124902  *
124903  * SETUP Packet Count (SUPCnt)
124904  *
124905  * Applies to control OUT Endpoints only.
124906  *
124907  * This field specifies the number of back-to-back SETUP data
124908  *
124909  * packets the endpoint can receive.
124910  *
124911  * 2'b01: 1 packet
124912  *
124913  * 2'b10: 2 packets
124914  *
124915  * 2'b11: 3 packets
124916  *
124917  * Field Enumeration Values:
124918  *
124919  * Enum | Value | Description
124920  * :-----------------------------------------|:------|:-------------------
124921  * ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA0 | 0x0 | DATA0
124922  * ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
124923  * ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
124924  * ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
124925  *
124926  * Field Access Macros:
124927  *
124928  */
124929 /*
124930  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID
124931  *
124932  * DATA0
124933  */
124934 #define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA0 0x0
124935 /*
124936  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID
124937  *
124938  * DATA2 or 1 packet
124939  */
124940 #define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA2PKT1 0x1
124941 /*
124942  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID
124943  *
124944  * DATA1 or 2 packets
124945  */
124946 #define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA1PKT2 0x2
124947 /*
124948  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID
124949  *
124950  * MDATA or 3 packets
124951  */
124952 #define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_MDATAPKT3 0x3
124953 
124954 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */
124955 #define ALT_USB_DEV_DOEPTSIZ9_RXDPID_LSB 29
124956 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */
124957 #define ALT_USB_DEV_DOEPTSIZ9_RXDPID_MSB 30
124958 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */
124959 #define ALT_USB_DEV_DOEPTSIZ9_RXDPID_WIDTH 2
124960 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field value. */
124961 #define ALT_USB_DEV_DOEPTSIZ9_RXDPID_SET_MSK 0x60000000
124962 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field value. */
124963 #define ALT_USB_DEV_DOEPTSIZ9_RXDPID_CLR_MSK 0x9fffffff
124964 /* The reset value of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */
124965 #define ALT_USB_DEV_DOEPTSIZ9_RXDPID_RESET 0x0
124966 /* Extracts the ALT_USB_DEV_DOEPTSIZ9_RXDPID field value from a register. */
124967 #define ALT_USB_DEV_DOEPTSIZ9_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
124968 /* Produces a ALT_USB_DEV_DOEPTSIZ9_RXDPID register field value suitable for setting the register. */
124969 #define ALT_USB_DEV_DOEPTSIZ9_RXDPID_SET(value) (((value) << 29) & 0x60000000)
124970 
124971 #ifndef __ASSEMBLY__
124972 /*
124973  * WARNING: The C register and register group struct declarations are provided for
124974  * convenience and illustrative purposes. They should, however, be used with
124975  * caution as the C language standard provides no guarantees about the alignment or
124976  * atomicity of device memory accesses. The recommended practice for writing
124977  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
124978  * alt_write_word() functions.
124979  *
124980  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ9.
124981  */
124982 struct ALT_USB_DEV_DOEPTSIZ9_s
124983 {
124984  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ9_XFERSIZE */
124985  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ9_PKTCNT */
124986  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ9_RXDPID */
124987  uint32_t : 1; /* *UNDEFINED* */
124988 };
124989 
124990 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ9. */
124991 typedef volatile struct ALT_USB_DEV_DOEPTSIZ9_s ALT_USB_DEV_DOEPTSIZ9_t;
124992 #endif /* __ASSEMBLY__ */
124993 
124994 /* The reset value of the ALT_USB_DEV_DOEPTSIZ9 register. */
124995 #define ALT_USB_DEV_DOEPTSIZ9_RESET 0x00000000
124996 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ9 register from the beginning of the component. */
124997 #define ALT_USB_DEV_DOEPTSIZ9_OFST 0x430
124998 /* The address of the ALT_USB_DEV_DOEPTSIZ9 register. */
124999 #define ALT_USB_DEV_DOEPTSIZ9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ9_OFST))
125000 
125001 /*
125002  * Register : doepdma9
125003  *
125004  * Device OUT Endpoint 9 DMA Address Register
125005  *
125006  * Register Layout
125007  *
125008  * Bits | Access | Reset | Description
125009  * :-------|:-------|:--------|:------------------------------
125010  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA9_DOEPDMA9
125011  *
125012  */
125013 /*
125014  * Field : doepdma9
125015  *
125016  * Holds the start address of the external memory for storing or fetching endpoint
125017  *
125018  * data.
125019  *
125020  * Note: For control endpoints, this field stores control OUT data packets as well
125021  * as
125022  *
125023  * SETUP transaction data packets. When more than three SETUP packets are
125024  *
125025  * received back-to-back, the SETUP data packet in the memory is overwritten.
125026  *
125027  * This register is incremented on every AHB transaction. The application can give
125028  *
125029  * only a DWORD-aligned address.
125030  *
125031  * When Scatter/Gather DMA mode is not enabled, the application programs the
125032  *
125033  * start address value in this field.
125034  *
125035  * When Scatter/Gather DMA mode is enabled, this field indicates the base
125036  *
125037  * pointer for the descriptor list.
125038  *
125039  * Field Access Macros:
125040  *
125041  */
125042 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field. */
125043 #define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_LSB 0
125044 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field. */
125045 #define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_MSB 31
125046 /* The width in bits of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field. */
125047 #define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_WIDTH 32
125048 /* The mask used to set the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field value. */
125049 #define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_SET_MSK 0xffffffff
125050 /* The mask used to clear the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field value. */
125051 #define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_CLR_MSK 0x00000000
125052 /* The reset value of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field is UNKNOWN. */
125053 #define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_RESET 0x0
125054 /* Extracts the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 field value from a register. */
125055 #define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_GET(value) (((value) & 0xffffffff) >> 0)
125056 /* Produces a ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field value suitable for setting the register. */
125057 #define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_SET(value) (((value) << 0) & 0xffffffff)
125058 
125059 #ifndef __ASSEMBLY__
125060 /*
125061  * WARNING: The C register and register group struct declarations are provided for
125062  * convenience and illustrative purposes. They should, however, be used with
125063  * caution as the C language standard provides no guarantees about the alignment or
125064  * atomicity of device memory accesses. The recommended practice for writing
125065  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
125066  * alt_write_word() functions.
125067  *
125068  * The struct declaration for register ALT_USB_DEV_DOEPDMA9.
125069  */
125070 struct ALT_USB_DEV_DOEPDMA9_s
125071 {
125072  uint32_t doepdma9 : 32; /* ALT_USB_DEV_DOEPDMA9_DOEPDMA9 */
125073 };
125074 
125075 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA9. */
125076 typedef volatile struct ALT_USB_DEV_DOEPDMA9_s ALT_USB_DEV_DOEPDMA9_t;
125077 #endif /* __ASSEMBLY__ */
125078 
125079 /* The reset value of the ALT_USB_DEV_DOEPDMA9 register. */
125080 #define ALT_USB_DEV_DOEPDMA9_RESET 0x00000000
125081 /* The byte offset of the ALT_USB_DEV_DOEPDMA9 register from the beginning of the component. */
125082 #define ALT_USB_DEV_DOEPDMA9_OFST 0x434
125083 /* The address of the ALT_USB_DEV_DOEPDMA9 register. */
125084 #define ALT_USB_DEV_DOEPDMA9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA9_OFST))
125085 
125086 /*
125087  * Register : doepdmab9
125088  *
125089  * Device OUT Endpoint 9 Buffer Address Register
125090  *
125091  * Register Layout
125092  *
125093  * Bits | Access | Reset | Description
125094  * :-------|:-------|:--------|:--------------------------------
125095  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9
125096  *
125097  */
125098 /*
125099  * Field : doepdmab9
125100  *
125101  * Holds the current buffer address.This register is updated as and when the data
125102  *
125103  * transfer for the corresponding end point is in progress.
125104  *
125105  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
125106  * is
125107  *
125108  * reserved.
125109  *
125110  * Field Access Macros:
125111  *
125112  */
125113 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field. */
125114 #define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_LSB 0
125115 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field. */
125116 #define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_MSB 31
125117 /* The width in bits of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field. */
125118 #define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_WIDTH 32
125119 /* The mask used to set the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field value. */
125120 #define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_SET_MSK 0xffffffff
125121 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field value. */
125122 #define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_CLR_MSK 0x00000000
125123 /* The reset value of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field is UNKNOWN. */
125124 #define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_RESET 0x0
125125 /* Extracts the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 field value from a register. */
125126 #define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_GET(value) (((value) & 0xffffffff) >> 0)
125127 /* Produces a ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field value suitable for setting the register. */
125128 #define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_SET(value) (((value) << 0) & 0xffffffff)
125129 
125130 #ifndef __ASSEMBLY__
125131 /*
125132  * WARNING: The C register and register group struct declarations are provided for
125133  * convenience and illustrative purposes. They should, however, be used with
125134  * caution as the C language standard provides no guarantees about the alignment or
125135  * atomicity of device memory accesses. The recommended practice for writing
125136  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
125137  * alt_write_word() functions.
125138  *
125139  * The struct declaration for register ALT_USB_DEV_DOEPDMAB9.
125140  */
125141 struct ALT_USB_DEV_DOEPDMAB9_s
125142 {
125143  const uint32_t doepdmab9 : 32; /* ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 */
125144 };
125145 
125146 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB9. */
125147 typedef volatile struct ALT_USB_DEV_DOEPDMAB9_s ALT_USB_DEV_DOEPDMAB9_t;
125148 #endif /* __ASSEMBLY__ */
125149 
125150 /* The reset value of the ALT_USB_DEV_DOEPDMAB9 register. */
125151 #define ALT_USB_DEV_DOEPDMAB9_RESET 0x00000000
125152 /* The byte offset of the ALT_USB_DEV_DOEPDMAB9 register from the beginning of the component. */
125153 #define ALT_USB_DEV_DOEPDMAB9_OFST 0x43c
125154 /* The address of the ALT_USB_DEV_DOEPDMAB9 register. */
125155 #define ALT_USB_DEV_DOEPDMAB9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB9_OFST))
125156 
125157 /*
125158  * Register : doepctl10
125159  *
125160  * Device Control OUT Endpoint 10 Control Register
125161  *
125162  * Register Layout
125163  *
125164  * Bits | Access | Reset | Description
125165  * :--------|:---------|:------|:-------------------------------
125166  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL10_MPS
125167  * [14:11] | ??? | 0x0 | *UNDEFINED*
125168  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL10_USBACTEP
125169  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL10_DPID
125170  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL10_NAKSTS
125171  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL10_EPTYPE
125172  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL10_SNP
125173  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL10_STALL
125174  * [25:22] | ??? | 0x0 | *UNDEFINED*
125175  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL10_CNAK
125176  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL10_SNAK
125177  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL10_SETD0PID
125178  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL10_SETD1PID
125179  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL10_EPDIS
125180  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL10_EPENA
125181  *
125182  */
125183 /*
125184  * Field : mps
125185  *
125186  * Maximum Packet Size (MPS)
125187  *
125188  * The application must program this field with the maximum packet size for the
125189  * current
125190  *
125191  * logical endpoint. This value is in bytes.
125192  *
125193  * Field Access Macros:
125194  *
125195  */
125196 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_MPS register field. */
125197 #define ALT_USB_DEV_DOEPCTL10_MPS_LSB 0
125198 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_MPS register field. */
125199 #define ALT_USB_DEV_DOEPCTL10_MPS_MSB 10
125200 /* The width in bits of the ALT_USB_DEV_DOEPCTL10_MPS register field. */
125201 #define ALT_USB_DEV_DOEPCTL10_MPS_WIDTH 11
125202 /* The mask used to set the ALT_USB_DEV_DOEPCTL10_MPS register field value. */
125203 #define ALT_USB_DEV_DOEPCTL10_MPS_SET_MSK 0x000007ff
125204 /* The mask used to clear the ALT_USB_DEV_DOEPCTL10_MPS register field value. */
125205 #define ALT_USB_DEV_DOEPCTL10_MPS_CLR_MSK 0xfffff800
125206 /* The reset value of the ALT_USB_DEV_DOEPCTL10_MPS register field. */
125207 #define ALT_USB_DEV_DOEPCTL10_MPS_RESET 0x0
125208 /* Extracts the ALT_USB_DEV_DOEPCTL10_MPS field value from a register. */
125209 #define ALT_USB_DEV_DOEPCTL10_MPS_GET(value) (((value) & 0x000007ff) >> 0)
125210 /* Produces a ALT_USB_DEV_DOEPCTL10_MPS register field value suitable for setting the register. */
125211 #define ALT_USB_DEV_DOEPCTL10_MPS_SET(value) (((value) << 0) & 0x000007ff)
125212 
125213 /*
125214  * Field : usbactep
125215  *
125216  * USB Active Endpoint (USBActEP)
125217  *
125218  * Indicates whether this endpoint is active in the current configuration and
125219  * interface. The
125220  *
125221  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
125222  * reset. After
125223  *
125224  * receiving the SetConfiguration and SetInterface commands, the application must
125225  *
125226  * program endpoint registers accordingly and set this bit.
125227  *
125228  * Field Enumeration Values:
125229  *
125230  * Enum | Value | Description
125231  * :--------------------------------------|:------|:--------------------
125232  * ALT_USB_DEV_DOEPCTL10_USBACTEP_E_DISD | 0x0 | Not Active
125233  * ALT_USB_DEV_DOEPCTL10_USBACTEP_E_END | 0x1 | USB Active Endpoint
125234  *
125235  * Field Access Macros:
125236  *
125237  */
125238 /*
125239  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_USBACTEP
125240  *
125241  * Not Active
125242  */
125243 #define ALT_USB_DEV_DOEPCTL10_USBACTEP_E_DISD 0x0
125244 /*
125245  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_USBACTEP
125246  *
125247  * USB Active Endpoint
125248  */
125249 #define ALT_USB_DEV_DOEPCTL10_USBACTEP_E_END 0x1
125250 
125251 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */
125252 #define ALT_USB_DEV_DOEPCTL10_USBACTEP_LSB 15
125253 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */
125254 #define ALT_USB_DEV_DOEPCTL10_USBACTEP_MSB 15
125255 /* The width in bits of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */
125256 #define ALT_USB_DEV_DOEPCTL10_USBACTEP_WIDTH 1
125257 /* The mask used to set the ALT_USB_DEV_DOEPCTL10_USBACTEP register field value. */
125258 #define ALT_USB_DEV_DOEPCTL10_USBACTEP_SET_MSK 0x00008000
125259 /* The mask used to clear the ALT_USB_DEV_DOEPCTL10_USBACTEP register field value. */
125260 #define ALT_USB_DEV_DOEPCTL10_USBACTEP_CLR_MSK 0xffff7fff
125261 /* The reset value of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */
125262 #define ALT_USB_DEV_DOEPCTL10_USBACTEP_RESET 0x0
125263 /* Extracts the ALT_USB_DEV_DOEPCTL10_USBACTEP field value from a register. */
125264 #define ALT_USB_DEV_DOEPCTL10_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
125265 /* Produces a ALT_USB_DEV_DOEPCTL10_USBACTEP register field value suitable for setting the register. */
125266 #define ALT_USB_DEV_DOEPCTL10_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
125267 
125268 /*
125269  * Field : dpid
125270  *
125271  * Endpoint Data PID (DPID)
125272  *
125273  * Applies to interrupt/bulk IN and OUT endpoints only.
125274  *
125275  * Contains the PID of the packet to be received or transmitted on this endpoint.
125276  * The
125277  *
125278  * application must program the PID of the first packet to be received or
125279  * transmitted on
125280  *
125281  * this endpoint, after the endpoint is activated. The applications use the
125282  * SetD1PID and
125283  *
125284  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
125285  *
125286  * 1'b0: DATA0
125287  *
125288  * 1'b1: DATA1
125289  *
125290  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
125291  *
125292  * DMA mode.
125293  *
125294  * 1'b0 RO
125295  *
125296  * Even/Odd (Micro)Frame (EO_FrNum)
125297  *
125298  * In non-Scatter/Gather DMA mode:
125299  *
125300  * Applies to isochronous IN and OUT endpoints only.
125301  *
125302  * Indicates the (micro)frame number in which the core transmits/receives
125303  * isochronous
125304  *
125305  * data for this endpoint. The application must program the even/odd (micro) frame
125306  *
125307  * number in which it intends to transmit/receive isochronous data for this
125308  * endpoint using
125309  *
125310  * the SetEvnFr and SetOddFr fields in this register.
125311  *
125312  * 1'b0: Even (micro)frame
125313  *
125314  * 1'b1: Odd (micro)frame
125315  *
125316  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
125317  * number
125318  *
125319  * in which to send data is provided in the transmit descriptor structure. The
125320  * frame in
125321  *
125322  * which data is received is updated in receive descriptor structure.
125323  *
125324  * Field Enumeration Values:
125325  *
125326  * Enum | Value | Description
125327  * :-----------------------------------|:------|:-----------------------------
125328  * ALT_USB_DEV_DOEPCTL10_DPID_E_INACT | 0x0 | Endpoint Data PID not active
125329  * ALT_USB_DEV_DOEPCTL10_DPID_E_ACT | 0x1 | Endpoint Data PID active
125330  *
125331  * Field Access Macros:
125332  *
125333  */
125334 /*
125335  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_DPID
125336  *
125337  * Endpoint Data PID not active
125338  */
125339 #define ALT_USB_DEV_DOEPCTL10_DPID_E_INACT 0x0
125340 /*
125341  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_DPID
125342  *
125343  * Endpoint Data PID active
125344  */
125345 #define ALT_USB_DEV_DOEPCTL10_DPID_E_ACT 0x1
125346 
125347 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_DPID register field. */
125348 #define ALT_USB_DEV_DOEPCTL10_DPID_LSB 16
125349 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_DPID register field. */
125350 #define ALT_USB_DEV_DOEPCTL10_DPID_MSB 16
125351 /* The width in bits of the ALT_USB_DEV_DOEPCTL10_DPID register field. */
125352 #define ALT_USB_DEV_DOEPCTL10_DPID_WIDTH 1
125353 /* The mask used to set the ALT_USB_DEV_DOEPCTL10_DPID register field value. */
125354 #define ALT_USB_DEV_DOEPCTL10_DPID_SET_MSK 0x00010000
125355 /* The mask used to clear the ALT_USB_DEV_DOEPCTL10_DPID register field value. */
125356 #define ALT_USB_DEV_DOEPCTL10_DPID_CLR_MSK 0xfffeffff
125357 /* The reset value of the ALT_USB_DEV_DOEPCTL10_DPID register field. */
125358 #define ALT_USB_DEV_DOEPCTL10_DPID_RESET 0x0
125359 /* Extracts the ALT_USB_DEV_DOEPCTL10_DPID field value from a register. */
125360 #define ALT_USB_DEV_DOEPCTL10_DPID_GET(value) (((value) & 0x00010000) >> 16)
125361 /* Produces a ALT_USB_DEV_DOEPCTL10_DPID register field value suitable for setting the register. */
125362 #define ALT_USB_DEV_DOEPCTL10_DPID_SET(value) (((value) << 16) & 0x00010000)
125363 
125364 /*
125365  * Field : naksts
125366  *
125367  * NAK Status (NAKSts)
125368  *
125369  * Indicates the following:
125370  *
125371  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
125372  *
125373  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
125374  *
125375  * When either the application or the core sets this bit:
125376  *
125377  * The core stops receiving any data on an OUT endpoint, even if there is space in
125378  *
125379  * the RxFIFO to accommodate the incoming packet.
125380  *
125381  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
125382  *
125383  * endpoint, even if there data is available in the TxFIFO.
125384  *
125385  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
125386  *
125387  * if there data is available in the TxFIFO.
125388  *
125389  * Irrespective of this bit's setting, the core always responds to SETUP data
125390  * packets with
125391  *
125392  * an ACK handshake.
125393  *
125394  * Field Enumeration Values:
125395  *
125396  * Enum | Value | Description
125397  * :--------------------------------------|:------|:------------------------------------------------
125398  * ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
125399  * : | | based on the FIFO status
125400  * ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
125401  * : | | endpoint
125402  *
125403  * Field Access Macros:
125404  *
125405  */
125406 /*
125407  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_NAKSTS
125408  *
125409  * The core is transmitting non-NAK handshakes based on the FIFO status
125410  */
125411 #define ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NONNAK 0x0
125412 /*
125413  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_NAKSTS
125414  *
125415  * The core is transmitting NAK handshakes on this endpoint
125416  */
125417 #define ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NAK 0x1
125418 
125419 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */
125420 #define ALT_USB_DEV_DOEPCTL10_NAKSTS_LSB 17
125421 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */
125422 #define ALT_USB_DEV_DOEPCTL10_NAKSTS_MSB 17
125423 /* The width in bits of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */
125424 #define ALT_USB_DEV_DOEPCTL10_NAKSTS_WIDTH 1
125425 /* The mask used to set the ALT_USB_DEV_DOEPCTL10_NAKSTS register field value. */
125426 #define ALT_USB_DEV_DOEPCTL10_NAKSTS_SET_MSK 0x00020000
125427 /* The mask used to clear the ALT_USB_DEV_DOEPCTL10_NAKSTS register field value. */
125428 #define ALT_USB_DEV_DOEPCTL10_NAKSTS_CLR_MSK 0xfffdffff
125429 /* The reset value of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */
125430 #define ALT_USB_DEV_DOEPCTL10_NAKSTS_RESET 0x0
125431 /* Extracts the ALT_USB_DEV_DOEPCTL10_NAKSTS field value from a register. */
125432 #define ALT_USB_DEV_DOEPCTL10_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
125433 /* Produces a ALT_USB_DEV_DOEPCTL10_NAKSTS register field value suitable for setting the register. */
125434 #define ALT_USB_DEV_DOEPCTL10_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
125435 
125436 /*
125437  * Field : eptype
125438  *
125439  * Endpoint Type (EPType)
125440  *
125441  * This is the transfer type supported by this logical endpoint.
125442  *
125443  * 2'b00: Control
125444  *
125445  * 2'b01: Isochronous
125446  *
125447  * 2'b10: Bulk
125448  *
125449  * 2'b11: Interrupt
125450  *
125451  * Field Enumeration Values:
125452  *
125453  * Enum | Value | Description
125454  * :-------------------------------------------|:------|:------------
125455  * ALT_USB_DEV_DOEPCTL10_EPTYPE_E_CTL | 0x0 | Control
125456  * ALT_USB_DEV_DOEPCTL10_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
125457  * ALT_USB_DEV_DOEPCTL10_EPTYPE_E_BULK | 0x2 | Bulk
125458  * ALT_USB_DEV_DOEPCTL10_EPTYPE_E_INTERRUP | 0x3 | Interrupt
125459  *
125460  * Field Access Macros:
125461  *
125462  */
125463 /*
125464  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE
125465  *
125466  * Control
125467  */
125468 #define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_CTL 0x0
125469 /*
125470  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE
125471  *
125472  * Isochronous
125473  */
125474 #define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_ISOCHRONOUS 0x1
125475 /*
125476  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE
125477  *
125478  * Bulk
125479  */
125480 #define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_BULK 0x2
125481 /*
125482  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE
125483  *
125484  * Interrupt
125485  */
125486 #define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_INTERRUP 0x3
125487 
125488 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */
125489 #define ALT_USB_DEV_DOEPCTL10_EPTYPE_LSB 18
125490 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */
125491 #define ALT_USB_DEV_DOEPCTL10_EPTYPE_MSB 19
125492 /* The width in bits of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */
125493 #define ALT_USB_DEV_DOEPCTL10_EPTYPE_WIDTH 2
125494 /* The mask used to set the ALT_USB_DEV_DOEPCTL10_EPTYPE register field value. */
125495 #define ALT_USB_DEV_DOEPCTL10_EPTYPE_SET_MSK 0x000c0000
125496 /* The mask used to clear the ALT_USB_DEV_DOEPCTL10_EPTYPE register field value. */
125497 #define ALT_USB_DEV_DOEPCTL10_EPTYPE_CLR_MSK 0xfff3ffff
125498 /* The reset value of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */
125499 #define ALT_USB_DEV_DOEPCTL10_EPTYPE_RESET 0x0
125500 /* Extracts the ALT_USB_DEV_DOEPCTL10_EPTYPE field value from a register. */
125501 #define ALT_USB_DEV_DOEPCTL10_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
125502 /* Produces a ALT_USB_DEV_DOEPCTL10_EPTYPE register field value suitable for setting the register. */
125503 #define ALT_USB_DEV_DOEPCTL10_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
125504 
125505 /*
125506  * Field : snp
125507  *
125508  * Snoop Mode (Snp)
125509  *
125510  * Applies to OUT endpoints only.
125511  *
125512  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
125513  *
125514  * check the correctness of OUT packets before transferring them to application
125515  * memory.
125516  *
125517  * Field Enumeration Values:
125518  *
125519  * Enum | Value | Description
125520  * :--------------------------------|:------|:-------------------
125521  * ALT_USB_DEV_DOEPCTL10_SNP_E_DIS | 0x0 | Disable Snoop Mode
125522  * ALT_USB_DEV_DOEPCTL10_SNP_E_EN | 0x1 | Enable Snoop Mode
125523  *
125524  * Field Access Macros:
125525  *
125526  */
125527 /*
125528  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNP
125529  *
125530  * Disable Snoop Mode
125531  */
125532 #define ALT_USB_DEV_DOEPCTL10_SNP_E_DIS 0x0
125533 /*
125534  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNP
125535  *
125536  * Enable Snoop Mode
125537  */
125538 #define ALT_USB_DEV_DOEPCTL10_SNP_E_EN 0x1
125539 
125540 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SNP register field. */
125541 #define ALT_USB_DEV_DOEPCTL10_SNP_LSB 20
125542 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SNP register field. */
125543 #define ALT_USB_DEV_DOEPCTL10_SNP_MSB 20
125544 /* The width in bits of the ALT_USB_DEV_DOEPCTL10_SNP register field. */
125545 #define ALT_USB_DEV_DOEPCTL10_SNP_WIDTH 1
125546 /* The mask used to set the ALT_USB_DEV_DOEPCTL10_SNP register field value. */
125547 #define ALT_USB_DEV_DOEPCTL10_SNP_SET_MSK 0x00100000
125548 /* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SNP register field value. */
125549 #define ALT_USB_DEV_DOEPCTL10_SNP_CLR_MSK 0xffefffff
125550 /* The reset value of the ALT_USB_DEV_DOEPCTL10_SNP register field. */
125551 #define ALT_USB_DEV_DOEPCTL10_SNP_RESET 0x0
125552 /* Extracts the ALT_USB_DEV_DOEPCTL10_SNP field value from a register. */
125553 #define ALT_USB_DEV_DOEPCTL10_SNP_GET(value) (((value) & 0x00100000) >> 20)
125554 /* Produces a ALT_USB_DEV_DOEPCTL10_SNP register field value suitable for setting the register. */
125555 #define ALT_USB_DEV_DOEPCTL10_SNP_SET(value) (((value) << 20) & 0x00100000)
125556 
125557 /*
125558  * Field : stall
125559  *
125560  * STALL Handshake (Stall)
125561  *
125562  * Applies to non-control, non-isochronous IN and OUT endpoints only.
125563  *
125564  * The application sets this bit to stall all tokens from the USB host to this
125565  * endpoint. If a
125566  *
125567  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
125568  * bit, the
125569  *
125570  * STALL bit takes priority. Only the application can clear this bit, never the
125571  * core.
125572  *
125573  * 1'b0 R_W
125574  *
125575  * Applies to control endpoints only.
125576  *
125577  * The application can only set this bit, and the core clears it, when a SETUP
125578  * token is
125579  *
125580  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
125581  * OUT
125582  *
125583  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
125584  * this bit's
125585  *
125586  * setting, the core always responds to SETUP data packets with an ACK handshake.
125587  *
125588  * Field Enumeration Values:
125589  *
125590  * Enum | Value | Description
125591  * :------------------------------------|:------|:----------------------------
125592  * ALT_USB_DEV_DOEPCTL10_STALL_E_INACT | 0x0 | STALL All Tokens not active
125593  * ALT_USB_DEV_DOEPCTL10_STALL_E_ACT | 0x1 | STALL All Tokens active
125594  *
125595  * Field Access Macros:
125596  *
125597  */
125598 /*
125599  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_STALL
125600  *
125601  * STALL All Tokens not active
125602  */
125603 #define ALT_USB_DEV_DOEPCTL10_STALL_E_INACT 0x0
125604 /*
125605  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_STALL
125606  *
125607  * STALL All Tokens active
125608  */
125609 #define ALT_USB_DEV_DOEPCTL10_STALL_E_ACT 0x1
125610 
125611 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_STALL register field. */
125612 #define ALT_USB_DEV_DOEPCTL10_STALL_LSB 21
125613 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_STALL register field. */
125614 #define ALT_USB_DEV_DOEPCTL10_STALL_MSB 21
125615 /* The width in bits of the ALT_USB_DEV_DOEPCTL10_STALL register field. */
125616 #define ALT_USB_DEV_DOEPCTL10_STALL_WIDTH 1
125617 /* The mask used to set the ALT_USB_DEV_DOEPCTL10_STALL register field value. */
125618 #define ALT_USB_DEV_DOEPCTL10_STALL_SET_MSK 0x00200000
125619 /* The mask used to clear the ALT_USB_DEV_DOEPCTL10_STALL register field value. */
125620 #define ALT_USB_DEV_DOEPCTL10_STALL_CLR_MSK 0xffdfffff
125621 /* The reset value of the ALT_USB_DEV_DOEPCTL10_STALL register field. */
125622 #define ALT_USB_DEV_DOEPCTL10_STALL_RESET 0x0
125623 /* Extracts the ALT_USB_DEV_DOEPCTL10_STALL field value from a register. */
125624 #define ALT_USB_DEV_DOEPCTL10_STALL_GET(value) (((value) & 0x00200000) >> 21)
125625 /* Produces a ALT_USB_DEV_DOEPCTL10_STALL register field value suitable for setting the register. */
125626 #define ALT_USB_DEV_DOEPCTL10_STALL_SET(value) (((value) << 21) & 0x00200000)
125627 
125628 /*
125629  * Field : cnak
125630  *
125631  * Clear NAK (CNAK)
125632  *
125633  * A write to this bit clears the NAK bit For the endpoint.
125634  *
125635  * Field Enumeration Values:
125636  *
125637  * Enum | Value | Description
125638  * :-----------------------------------|:------|:-------------
125639  * ALT_USB_DEV_DOEPCTL10_CNAK_E_INACT | 0x0 | No Clear NAK
125640  * ALT_USB_DEV_DOEPCTL10_CNAK_E_ACT | 0x1 | Clear NAK
125641  *
125642  * Field Access Macros:
125643  *
125644  */
125645 /*
125646  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_CNAK
125647  *
125648  * No Clear NAK
125649  */
125650 #define ALT_USB_DEV_DOEPCTL10_CNAK_E_INACT 0x0
125651 /*
125652  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_CNAK
125653  *
125654  * Clear NAK
125655  */
125656 #define ALT_USB_DEV_DOEPCTL10_CNAK_E_ACT 0x1
125657 
125658 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */
125659 #define ALT_USB_DEV_DOEPCTL10_CNAK_LSB 26
125660 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */
125661 #define ALT_USB_DEV_DOEPCTL10_CNAK_MSB 26
125662 /* The width in bits of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */
125663 #define ALT_USB_DEV_DOEPCTL10_CNAK_WIDTH 1
125664 /* The mask used to set the ALT_USB_DEV_DOEPCTL10_CNAK register field value. */
125665 #define ALT_USB_DEV_DOEPCTL10_CNAK_SET_MSK 0x04000000
125666 /* The mask used to clear the ALT_USB_DEV_DOEPCTL10_CNAK register field value. */
125667 #define ALT_USB_DEV_DOEPCTL10_CNAK_CLR_MSK 0xfbffffff
125668 /* The reset value of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */
125669 #define ALT_USB_DEV_DOEPCTL10_CNAK_RESET 0x0
125670 /* Extracts the ALT_USB_DEV_DOEPCTL10_CNAK field value from a register. */
125671 #define ALT_USB_DEV_DOEPCTL10_CNAK_GET(value) (((value) & 0x04000000) >> 26)
125672 /* Produces a ALT_USB_DEV_DOEPCTL10_CNAK register field value suitable for setting the register. */
125673 #define ALT_USB_DEV_DOEPCTL10_CNAK_SET(value) (((value) << 26) & 0x04000000)
125674 
125675 /*
125676  * Field : snak
125677  *
125678  * Set NAK (SNAK)
125679  *
125680  * A write to this bit sets the NAK bit For the endpoint.
125681  *
125682  * Using this bit, the application can control the transmission of NAK
125683  *
125684  * handshakes on an endpoint. The core can also Set this bit For an
125685  *
125686  * endpoint after a SETUP packet is received on that endpoint.
125687  *
125688  * Field Enumeration Values:
125689  *
125690  * Enum | Value | Description
125691  * :-----------------------------------|:------|:------------
125692  * ALT_USB_DEV_DOEPCTL10_SNAK_E_INACT | 0x0 | No Set NAK
125693  * ALT_USB_DEV_DOEPCTL10_SNAK_E_ACT | 0x1 | Set NAK
125694  *
125695  * Field Access Macros:
125696  *
125697  */
125698 /*
125699  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNAK
125700  *
125701  * No Set NAK
125702  */
125703 #define ALT_USB_DEV_DOEPCTL10_SNAK_E_INACT 0x0
125704 /*
125705  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNAK
125706  *
125707  * Set NAK
125708  */
125709 #define ALT_USB_DEV_DOEPCTL10_SNAK_E_ACT 0x1
125710 
125711 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */
125712 #define ALT_USB_DEV_DOEPCTL10_SNAK_LSB 27
125713 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */
125714 #define ALT_USB_DEV_DOEPCTL10_SNAK_MSB 27
125715 /* The width in bits of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */
125716 #define ALT_USB_DEV_DOEPCTL10_SNAK_WIDTH 1
125717 /* The mask used to set the ALT_USB_DEV_DOEPCTL10_SNAK register field value. */
125718 #define ALT_USB_DEV_DOEPCTL10_SNAK_SET_MSK 0x08000000
125719 /* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SNAK register field value. */
125720 #define ALT_USB_DEV_DOEPCTL10_SNAK_CLR_MSK 0xf7ffffff
125721 /* The reset value of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */
125722 #define ALT_USB_DEV_DOEPCTL10_SNAK_RESET 0x0
125723 /* Extracts the ALT_USB_DEV_DOEPCTL10_SNAK field value from a register. */
125724 #define ALT_USB_DEV_DOEPCTL10_SNAK_GET(value) (((value) & 0x08000000) >> 27)
125725 /* Produces a ALT_USB_DEV_DOEPCTL10_SNAK register field value suitable for setting the register. */
125726 #define ALT_USB_DEV_DOEPCTL10_SNAK_SET(value) (((value) << 27) & 0x08000000)
125727 
125728 /*
125729  * Field : setd0pid
125730  *
125731  * Set DATA0 PID (SetD0PID)
125732  *
125733  * Applies to interrupt/bulk IN and OUT endpoints only.
125734  *
125735  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
125736  * to DATA0.
125737  *
125738  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
125739  *
125740  * DMA mode.
125741  *
125742  * 1'b0 WO
125743  *
125744  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
125745  *
125746  * Applies to isochronous IN and OUT endpoints only.
125747  *
125748  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
125749  * (micro)
125750  *
125751  * frame.
125752  *
125753  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
125754  * number
125755  *
125756  * in which to send data is in the transmit descriptor structure. The frame in
125757  * which to
125758  *
125759  * receive data is updated in receive descriptor structure.
125760  *
125761  * Field Enumeration Values:
125762  *
125763  * Enum | Value | Description
125764  * :--------------------------------------|:------|:------------------------------------
125765  * ALT_USB_DEV_DOEPCTL10_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
125766  * ALT_USB_DEV_DOEPCTL10_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
125767  *
125768  * Field Access Macros:
125769  *
125770  */
125771 /*
125772  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD0PID
125773  *
125774  * Disables Set DATA0 PID
125775  */
125776 #define ALT_USB_DEV_DOEPCTL10_SETD0PID_E_DISD 0x0
125777 /*
125778  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD0PID
125779  *
125780  * Enables Endpoint Data PID to DATA0)
125781  */
125782 #define ALT_USB_DEV_DOEPCTL10_SETD0PID_E_END 0x1
125783 
125784 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */
125785 #define ALT_USB_DEV_DOEPCTL10_SETD0PID_LSB 28
125786 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */
125787 #define ALT_USB_DEV_DOEPCTL10_SETD0PID_MSB 28
125788 /* The width in bits of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */
125789 #define ALT_USB_DEV_DOEPCTL10_SETD0PID_WIDTH 1
125790 /* The mask used to set the ALT_USB_DEV_DOEPCTL10_SETD0PID register field value. */
125791 #define ALT_USB_DEV_DOEPCTL10_SETD0PID_SET_MSK 0x10000000
125792 /* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SETD0PID register field value. */
125793 #define ALT_USB_DEV_DOEPCTL10_SETD0PID_CLR_MSK 0xefffffff
125794 /* The reset value of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */
125795 #define ALT_USB_DEV_DOEPCTL10_SETD0PID_RESET 0x0
125796 /* Extracts the ALT_USB_DEV_DOEPCTL10_SETD0PID field value from a register. */
125797 #define ALT_USB_DEV_DOEPCTL10_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
125798 /* Produces a ALT_USB_DEV_DOEPCTL10_SETD0PID register field value suitable for setting the register. */
125799 #define ALT_USB_DEV_DOEPCTL10_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
125800 
125801 /*
125802  * Field : setd1pid
125803  *
125804  * Set DATA1 PID (SetD1PID)
125805  *
125806  * Applies to interrupt/bulk IN and OUT endpoints only.
125807  *
125808  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
125809  * to DATA1.
125810  *
125811  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
125812  *
125813  * DMA mode.
125814  *
125815  * Set Odd (micro)frame (SetOddFr)
125816  *
125817  * Applies to isochronous IN and OUT endpoints only.
125818  *
125819  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
125820  *
125821  * (micro)frame.
125822  *
125823  * This field is not applicable for Scatter/Gather DMA mode.
125824  *
125825  * Field Enumeration Values:
125826  *
125827  * Enum | Value | Description
125828  * :--------------------------------------|:------|:-----------------------
125829  * ALT_USB_DEV_DOEPCTL10_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
125830  * ALT_USB_DEV_DOEPCTL10_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
125831  *
125832  * Field Access Macros:
125833  *
125834  */
125835 /*
125836  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD1PID
125837  *
125838  * Disables Set DATA1 PID
125839  */
125840 #define ALT_USB_DEV_DOEPCTL10_SETD1PID_E_DISD 0x0
125841 /*
125842  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD1PID
125843  *
125844  * Enables Set DATA1 PID
125845  */
125846 #define ALT_USB_DEV_DOEPCTL10_SETD1PID_E_END 0x1
125847 
125848 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */
125849 #define ALT_USB_DEV_DOEPCTL10_SETD1PID_LSB 29
125850 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */
125851 #define ALT_USB_DEV_DOEPCTL10_SETD1PID_MSB 29
125852 /* The width in bits of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */
125853 #define ALT_USB_DEV_DOEPCTL10_SETD1PID_WIDTH 1
125854 /* The mask used to set the ALT_USB_DEV_DOEPCTL10_SETD1PID register field value. */
125855 #define ALT_USB_DEV_DOEPCTL10_SETD1PID_SET_MSK 0x20000000
125856 /* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SETD1PID register field value. */
125857 #define ALT_USB_DEV_DOEPCTL10_SETD1PID_CLR_MSK 0xdfffffff
125858 /* The reset value of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */
125859 #define ALT_USB_DEV_DOEPCTL10_SETD1PID_RESET 0x0
125860 /* Extracts the ALT_USB_DEV_DOEPCTL10_SETD1PID field value from a register. */
125861 #define ALT_USB_DEV_DOEPCTL10_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
125862 /* Produces a ALT_USB_DEV_DOEPCTL10_SETD1PID register field value suitable for setting the register. */
125863 #define ALT_USB_DEV_DOEPCTL10_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
125864 
125865 /*
125866  * Field : epdis
125867  *
125868  * Endpoint Disable (EPDis)
125869  *
125870  * Applies to IN and OUT endpoints.
125871  *
125872  * The application sets this bit to stop transmitting/receiving data on an
125873  * endpoint, even
125874  *
125875  * before the transfer for that endpoint is complete. The application must wait for
125876  * the
125877  *
125878  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
125879  * clears
125880  *
125881  * this bit before setting the Endpoint Disabled interrupt. The application must
125882  * set this bit
125883  *
125884  * only if Endpoint Enable is already set for this endpoint.
125885  *
125886  * Field Enumeration Values:
125887  *
125888  * Enum | Value | Description
125889  * :------------------------------------|:------|:--------------------
125890  * ALT_USB_DEV_DOEPCTL10_EPDIS_E_INACT | 0x0 | No Endpoint Disable
125891  * ALT_USB_DEV_DOEPCTL10_EPDIS_E_ACT | 0x1 | Endpoint Disable
125892  *
125893  * Field Access Macros:
125894  *
125895  */
125896 /*
125897  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPDIS
125898  *
125899  * No Endpoint Disable
125900  */
125901 #define ALT_USB_DEV_DOEPCTL10_EPDIS_E_INACT 0x0
125902 /*
125903  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPDIS
125904  *
125905  * Endpoint Disable
125906  */
125907 #define ALT_USB_DEV_DOEPCTL10_EPDIS_E_ACT 0x1
125908 
125909 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */
125910 #define ALT_USB_DEV_DOEPCTL10_EPDIS_LSB 30
125911 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */
125912 #define ALT_USB_DEV_DOEPCTL10_EPDIS_MSB 30
125913 /* The width in bits of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */
125914 #define ALT_USB_DEV_DOEPCTL10_EPDIS_WIDTH 1
125915 /* The mask used to set the ALT_USB_DEV_DOEPCTL10_EPDIS register field value. */
125916 #define ALT_USB_DEV_DOEPCTL10_EPDIS_SET_MSK 0x40000000
125917 /* The mask used to clear the ALT_USB_DEV_DOEPCTL10_EPDIS register field value. */
125918 #define ALT_USB_DEV_DOEPCTL10_EPDIS_CLR_MSK 0xbfffffff
125919 /* The reset value of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */
125920 #define ALT_USB_DEV_DOEPCTL10_EPDIS_RESET 0x0
125921 /* Extracts the ALT_USB_DEV_DOEPCTL10_EPDIS field value from a register. */
125922 #define ALT_USB_DEV_DOEPCTL10_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
125923 /* Produces a ALT_USB_DEV_DOEPCTL10_EPDIS register field value suitable for setting the register. */
125924 #define ALT_USB_DEV_DOEPCTL10_EPDIS_SET(value) (((value) << 30) & 0x40000000)
125925 
125926 /*
125927  * Field : epena
125928  *
125929  * Endpoint Enable (EPEna)
125930  *
125931  * Applies to IN and OUT endpoints.
125932  *
125933  * When Scatter/Gather DMA mode is enabled,
125934  *
125935  * For IN endpoints this bit indicates that the descriptor structure and data
125936  * buffer with
125937  *
125938  * data ready to transmit is setup.
125939  *
125940  * For OUT endpoint it indicates that the descriptor structure and data buffer to
125941  *
125942  * receive data is setup.
125943  *
125944  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
125945  *
125946  * DMA mode:
125947  *
125948  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
125949  * the
125950  *
125951  * endpoint.
125952  *
125953  * * For OUT endpoints, this bit indicates that the application has allocated the
125954  *
125955  * memory to start receiving data from the USB.
125956  *
125957  * * The core clears this bit before setting any of the following interrupts on
125958  * this
125959  *
125960  * endpoint:
125961  *
125962  * SETUP Phase Done
125963  *
125964  * Endpoint Disabled
125965  *
125966  * Transfer Completed
125967  *
125968  * Note: For control endpoints in DMA mode, this bit must be set to be able to
125969  * transfer
125970  *
125971  * SETUP data packets in memory.
125972  *
125973  * Field Enumeration Values:
125974  *
125975  * Enum | Value | Description
125976  * :------------------------------------|:------|:-------------------------
125977  * ALT_USB_DEV_DOEPCTL10_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
125978  * ALT_USB_DEV_DOEPCTL10_EPENA_E_ACT | 0x1 | Endpoint Enable active
125979  *
125980  * Field Access Macros:
125981  *
125982  */
125983 /*
125984  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPENA
125985  *
125986  * Endpoint Enable inactive
125987  */
125988 #define ALT_USB_DEV_DOEPCTL10_EPENA_E_INACT 0x0
125989 /*
125990  * Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPENA
125991  *
125992  * Endpoint Enable active
125993  */
125994 #define ALT_USB_DEV_DOEPCTL10_EPENA_E_ACT 0x1
125995 
125996 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */
125997 #define ALT_USB_DEV_DOEPCTL10_EPENA_LSB 31
125998 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */
125999 #define ALT_USB_DEV_DOEPCTL10_EPENA_MSB 31
126000 /* The width in bits of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */
126001 #define ALT_USB_DEV_DOEPCTL10_EPENA_WIDTH 1
126002 /* The mask used to set the ALT_USB_DEV_DOEPCTL10_EPENA register field value. */
126003 #define ALT_USB_DEV_DOEPCTL10_EPENA_SET_MSK 0x80000000
126004 /* The mask used to clear the ALT_USB_DEV_DOEPCTL10_EPENA register field value. */
126005 #define ALT_USB_DEV_DOEPCTL10_EPENA_CLR_MSK 0x7fffffff
126006 /* The reset value of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */
126007 #define ALT_USB_DEV_DOEPCTL10_EPENA_RESET 0x0
126008 /* Extracts the ALT_USB_DEV_DOEPCTL10_EPENA field value from a register. */
126009 #define ALT_USB_DEV_DOEPCTL10_EPENA_GET(value) (((value) & 0x80000000) >> 31)
126010 /* Produces a ALT_USB_DEV_DOEPCTL10_EPENA register field value suitable for setting the register. */
126011 #define ALT_USB_DEV_DOEPCTL10_EPENA_SET(value) (((value) << 31) & 0x80000000)
126012 
126013 #ifndef __ASSEMBLY__
126014 /*
126015  * WARNING: The C register and register group struct declarations are provided for
126016  * convenience and illustrative purposes. They should, however, be used with
126017  * caution as the C language standard provides no guarantees about the alignment or
126018  * atomicity of device memory accesses. The recommended practice for writing
126019  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
126020  * alt_write_word() functions.
126021  *
126022  * The struct declaration for register ALT_USB_DEV_DOEPCTL10.
126023  */
126024 struct ALT_USB_DEV_DOEPCTL10_s
126025 {
126026  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL10_MPS */
126027  uint32_t : 4; /* *UNDEFINED* */
126028  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL10_USBACTEP */
126029  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL10_DPID */
126030  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL10_NAKSTS */
126031  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL10_EPTYPE */
126032  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL10_SNP */
126033  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL10_STALL */
126034  uint32_t : 4; /* *UNDEFINED* */
126035  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL10_CNAK */
126036  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL10_SNAK */
126037  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL10_SETD0PID */
126038  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL10_SETD1PID */
126039  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL10_EPDIS */
126040  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL10_EPENA */
126041 };
126042 
126043 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL10. */
126044 typedef volatile struct ALT_USB_DEV_DOEPCTL10_s ALT_USB_DEV_DOEPCTL10_t;
126045 #endif /* __ASSEMBLY__ */
126046 
126047 /* The reset value of the ALT_USB_DEV_DOEPCTL10 register. */
126048 #define ALT_USB_DEV_DOEPCTL10_RESET 0x00000000
126049 /* The byte offset of the ALT_USB_DEV_DOEPCTL10 register from the beginning of the component. */
126050 #define ALT_USB_DEV_DOEPCTL10_OFST 0x440
126051 /* The address of the ALT_USB_DEV_DOEPCTL10 register. */
126052 #define ALT_USB_DEV_DOEPCTL10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL10_OFST))
126053 
126054 /*
126055  * Register : doepint10
126056  *
126057  * Device OUT Endpoint 10 Interrupt Register
126058  *
126059  * Register Layout
126060  *
126061  * Bits | Access | Reset | Description
126062  * :--------|:-------|:------|:-------------------------------------
126063  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_XFERCOMPL
126064  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_EPDISBLD
126065  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_AHBERR
126066  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_SETUP
126067  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS
126068  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_STSPHSERCVD
126069  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP
126070  * [7] | ??? | 0x0 | *UNDEFINED*
126071  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_OUTPKTERR
126072  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_BNAINTR
126073  * [10] | ??? | 0x0 | *UNDEFINED*
126074  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_PKTDRPSTS
126075  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_BBLEERR
126076  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_NAKINTRPT
126077  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_NYETINTRPT
126078  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_STUPPKTRCVD
126079  * [31:16] | ??? | 0x0 | *UNDEFINED*
126080  *
126081  */
126082 /*
126083  * Field : xfercompl
126084  *
126085  * Transfer Completed Interrupt (XferCompl)
126086  *
126087  * Applies to IN and OUT endpoints.
126088  *
126089  * When Scatter/Gather DMA mode is enabled
126090  *
126091  * * For IN endpoint this field indicates that the requested data
126092  *
126093  * from the descriptor is moved from external system memory
126094  *
126095  * to internal FIFO.
126096  *
126097  * * For OUT endpoint this field indicates that the requested
126098  *
126099  * data from the internal FIFO is moved to external system
126100  *
126101  * memory. This interrupt is generated only when the
126102  *
126103  * corresponding endpoint descriptor is closed, and the IOC
126104  *
126105  * bit For the corresponding descriptor is Set.
126106  *
126107  * When Scatter/Gather DMA mode is disabled, this field
126108  *
126109  * indicates that the programmed transfer is complete on the
126110  *
126111  * AHB as well as on the USB, For this endpoint.
126112  *
126113  * Field Enumeration Values:
126114  *
126115  * Enum | Value | Description
126116  * :----------------------------------------|:------|:-----------------------------
126117  * ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_INACT | 0x0 | No Interrupt
126118  * ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
126119  *
126120  * Field Access Macros:
126121  *
126122  */
126123 /*
126124  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_XFERCOMPL
126125  *
126126  * No Interrupt
126127  */
126128 #define ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_INACT 0x0
126129 /*
126130  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_XFERCOMPL
126131  *
126132  * Transfer Completed Interrupt
126133  */
126134 #define ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_ACT 0x1
126135 
126136 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */
126137 #define ALT_USB_DEV_DOEPINT10_XFERCOMPL_LSB 0
126138 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */
126139 #define ALT_USB_DEV_DOEPINT10_XFERCOMPL_MSB 0
126140 /* The width in bits of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */
126141 #define ALT_USB_DEV_DOEPINT10_XFERCOMPL_WIDTH 1
126142 /* The mask used to set the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field value. */
126143 #define ALT_USB_DEV_DOEPINT10_XFERCOMPL_SET_MSK 0x00000001
126144 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field value. */
126145 #define ALT_USB_DEV_DOEPINT10_XFERCOMPL_CLR_MSK 0xfffffffe
126146 /* The reset value of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */
126147 #define ALT_USB_DEV_DOEPINT10_XFERCOMPL_RESET 0x0
126148 /* Extracts the ALT_USB_DEV_DOEPINT10_XFERCOMPL field value from a register. */
126149 #define ALT_USB_DEV_DOEPINT10_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
126150 /* Produces a ALT_USB_DEV_DOEPINT10_XFERCOMPL register field value suitable for setting the register. */
126151 #define ALT_USB_DEV_DOEPINT10_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
126152 
126153 /*
126154  * Field : epdisbld
126155  *
126156  * Endpoint Disabled Interrupt (EPDisbld)
126157  *
126158  * Applies to IN and OUT endpoints.
126159  *
126160  * This bit indicates that the endpoint is disabled per the
126161  *
126162  * application's request.
126163  *
126164  * Field Enumeration Values:
126165  *
126166  * Enum | Value | Description
126167  * :---------------------------------------|:------|:----------------------------
126168  * ALT_USB_DEV_DOEPINT10_EPDISBLD_E_INACT | 0x0 | No Interrupt
126169  * ALT_USB_DEV_DOEPINT10_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
126170  *
126171  * Field Access Macros:
126172  *
126173  */
126174 /*
126175  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_EPDISBLD
126176  *
126177  * No Interrupt
126178  */
126179 #define ALT_USB_DEV_DOEPINT10_EPDISBLD_E_INACT 0x0
126180 /*
126181  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_EPDISBLD
126182  *
126183  * Endpoint Disabled Interrupt
126184  */
126185 #define ALT_USB_DEV_DOEPINT10_EPDISBLD_E_ACT 0x1
126186 
126187 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */
126188 #define ALT_USB_DEV_DOEPINT10_EPDISBLD_LSB 1
126189 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */
126190 #define ALT_USB_DEV_DOEPINT10_EPDISBLD_MSB 1
126191 /* The width in bits of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */
126192 #define ALT_USB_DEV_DOEPINT10_EPDISBLD_WIDTH 1
126193 /* The mask used to set the ALT_USB_DEV_DOEPINT10_EPDISBLD register field value. */
126194 #define ALT_USB_DEV_DOEPINT10_EPDISBLD_SET_MSK 0x00000002
126195 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_EPDISBLD register field value. */
126196 #define ALT_USB_DEV_DOEPINT10_EPDISBLD_CLR_MSK 0xfffffffd
126197 /* The reset value of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */
126198 #define ALT_USB_DEV_DOEPINT10_EPDISBLD_RESET 0x0
126199 /* Extracts the ALT_USB_DEV_DOEPINT10_EPDISBLD field value from a register. */
126200 #define ALT_USB_DEV_DOEPINT10_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
126201 /* Produces a ALT_USB_DEV_DOEPINT10_EPDISBLD register field value suitable for setting the register. */
126202 #define ALT_USB_DEV_DOEPINT10_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
126203 
126204 /*
126205  * Field : ahberr
126206  *
126207  * AHB Error (AHBErr)
126208  *
126209  * Applies to IN and OUT endpoints.
126210  *
126211  * This is generated only in Internal DMA mode when there is an
126212  *
126213  * AHB error during an AHB read/write. The application can read
126214  *
126215  * the corresponding endpoint DMA address register to get the
126216  *
126217  * error address.
126218  *
126219  * Field Enumeration Values:
126220  *
126221  * Enum | Value | Description
126222  * :-------------------------------------|:------|:--------------------
126223  * ALT_USB_DEV_DOEPINT10_AHBERR_E_INACT | 0x0 | No Interrupt
126224  * ALT_USB_DEV_DOEPINT10_AHBERR_E_ACT | 0x1 | AHB Error interrupt
126225  *
126226  * Field Access Macros:
126227  *
126228  */
126229 /*
126230  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_AHBERR
126231  *
126232  * No Interrupt
126233  */
126234 #define ALT_USB_DEV_DOEPINT10_AHBERR_E_INACT 0x0
126235 /*
126236  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_AHBERR
126237  *
126238  * AHB Error interrupt
126239  */
126240 #define ALT_USB_DEV_DOEPINT10_AHBERR_E_ACT 0x1
126241 
126242 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */
126243 #define ALT_USB_DEV_DOEPINT10_AHBERR_LSB 2
126244 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */
126245 #define ALT_USB_DEV_DOEPINT10_AHBERR_MSB 2
126246 /* The width in bits of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */
126247 #define ALT_USB_DEV_DOEPINT10_AHBERR_WIDTH 1
126248 /* The mask used to set the ALT_USB_DEV_DOEPINT10_AHBERR register field value. */
126249 #define ALT_USB_DEV_DOEPINT10_AHBERR_SET_MSK 0x00000004
126250 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_AHBERR register field value. */
126251 #define ALT_USB_DEV_DOEPINT10_AHBERR_CLR_MSK 0xfffffffb
126252 /* The reset value of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */
126253 #define ALT_USB_DEV_DOEPINT10_AHBERR_RESET 0x0
126254 /* Extracts the ALT_USB_DEV_DOEPINT10_AHBERR field value from a register. */
126255 #define ALT_USB_DEV_DOEPINT10_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
126256 /* Produces a ALT_USB_DEV_DOEPINT10_AHBERR register field value suitable for setting the register. */
126257 #define ALT_USB_DEV_DOEPINT10_AHBERR_SET(value) (((value) << 2) & 0x00000004)
126258 
126259 /*
126260  * Field : setup
126261  *
126262  * SETUP Phase Done (SetUp)
126263  *
126264  * Applies to control OUT endpoints only.
126265  *
126266  * Indicates that the SETUP phase For the control endpoint is
126267  *
126268  * complete and no more back-to-back SETUP packets were
126269  *
126270  * received For the current control transfer. On this interrupt, the
126271  *
126272  * application can decode the received SETUP data packet.
126273  *
126274  * Field Enumeration Values:
126275  *
126276  * Enum | Value | Description
126277  * :------------------------------------|:------|:--------------------
126278  * ALT_USB_DEV_DOEPINT10_SETUP_E_INACT | 0x0 | No SETUP Phase Done
126279  * ALT_USB_DEV_DOEPINT10_SETUP_E_ACT | 0x1 | SETUP Phase Done
126280  *
126281  * Field Access Macros:
126282  *
126283  */
126284 /*
126285  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_SETUP
126286  *
126287  * No SETUP Phase Done
126288  */
126289 #define ALT_USB_DEV_DOEPINT10_SETUP_E_INACT 0x0
126290 /*
126291  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_SETUP
126292  *
126293  * SETUP Phase Done
126294  */
126295 #define ALT_USB_DEV_DOEPINT10_SETUP_E_ACT 0x1
126296 
126297 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_SETUP register field. */
126298 #define ALT_USB_DEV_DOEPINT10_SETUP_LSB 3
126299 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_SETUP register field. */
126300 #define ALT_USB_DEV_DOEPINT10_SETUP_MSB 3
126301 /* The width in bits of the ALT_USB_DEV_DOEPINT10_SETUP register field. */
126302 #define ALT_USB_DEV_DOEPINT10_SETUP_WIDTH 1
126303 /* The mask used to set the ALT_USB_DEV_DOEPINT10_SETUP register field value. */
126304 #define ALT_USB_DEV_DOEPINT10_SETUP_SET_MSK 0x00000008
126305 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_SETUP register field value. */
126306 #define ALT_USB_DEV_DOEPINT10_SETUP_CLR_MSK 0xfffffff7
126307 /* The reset value of the ALT_USB_DEV_DOEPINT10_SETUP register field. */
126308 #define ALT_USB_DEV_DOEPINT10_SETUP_RESET 0x0
126309 /* Extracts the ALT_USB_DEV_DOEPINT10_SETUP field value from a register. */
126310 #define ALT_USB_DEV_DOEPINT10_SETUP_GET(value) (((value) & 0x00000008) >> 3)
126311 /* Produces a ALT_USB_DEV_DOEPINT10_SETUP register field value suitable for setting the register. */
126312 #define ALT_USB_DEV_DOEPINT10_SETUP_SET(value) (((value) << 3) & 0x00000008)
126313 
126314 /*
126315  * Field : outtknepdis
126316  *
126317  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
126318  *
126319  * Applies only to control OUT endpoints.
126320  *
126321  * Indicates that an OUT token was received when the endpoint
126322  *
126323  * was not yet enabled. This interrupt is asserted on the endpoint
126324  *
126325  * For which the OUT token was received.
126326  *
126327  * Field Enumeration Values:
126328  *
126329  * Enum | Value | Description
126330  * :------------------------------------------|:------|:---------------------------------------------
126331  * ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
126332  * ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
126333  *
126334  * Field Access Macros:
126335  *
126336  */
126337 /*
126338  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS
126339  *
126340  * No OUT Token Received When Endpoint Disabled
126341  */
126342 #define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_INACT 0x0
126343 /*
126344  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS
126345  *
126346  * OUT Token Received When Endpoint Disabled
126347  */
126348 #define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_ACT 0x1
126349 
126350 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */
126351 #define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_LSB 4
126352 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */
126353 #define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_MSB 4
126354 /* The width in bits of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */
126355 #define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_WIDTH 1
126356 /* The mask used to set the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field value. */
126357 #define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_SET_MSK 0x00000010
126358 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field value. */
126359 #define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_CLR_MSK 0xffffffef
126360 /* The reset value of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */
126361 #define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_RESET 0x0
126362 /* Extracts the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS field value from a register. */
126363 #define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
126364 /* Produces a ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field value suitable for setting the register. */
126365 #define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
126366 
126367 /*
126368  * Field : stsphsercvd
126369  *
126370  * Status Phase Received For Control Write (StsPhseRcvd)
126371  *
126372  * This interrupt is valid only For Control OUT endpoints and only in
126373  *
126374  * Scatter Gather DMA mode.
126375  *
126376  * This interrupt is generated only after the core has transferred all
126377  *
126378  * the data that the host has sent during the data phase of a control
126379  *
126380  * write transfer, to the system memory buffer.
126381  *
126382  * The interrupt indicates to the application that the host has
126383  *
126384  * switched from data phase to the status phase of a Control Write
126385  *
126386  * transfer. The application can use this interrupt to ACK or STALL
126387  *
126388  * the Status phase, after it has decoded the data phase. This is
126389  *
126390  * applicable only in Case of Scatter Gather DMA mode.
126391  *
126392  * Field Enumeration Values:
126393  *
126394  * Enum | Value | Description
126395  * :------------------------------------------|:------|:-------------------------------------------
126396  * ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
126397  * ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
126398  *
126399  * Field Access Macros:
126400  *
126401  */
126402 /*
126403  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_STSPHSERCVD
126404  *
126405  * No Status Phase Received for Control Write
126406  */
126407 #define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_INACT 0x0
126408 /*
126409  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_STSPHSERCVD
126410  *
126411  * Status Phase Received for Control Write
126412  */
126413 #define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_ACT 0x1
126414 
126415 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */
126416 #define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_LSB 5
126417 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */
126418 #define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_MSB 5
126419 /* The width in bits of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */
126420 #define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_WIDTH 1
126421 /* The mask used to set the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field value. */
126422 #define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_SET_MSK 0x00000020
126423 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field value. */
126424 #define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_CLR_MSK 0xffffffdf
126425 /* The reset value of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */
126426 #define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_RESET 0x0
126427 /* Extracts the ALT_USB_DEV_DOEPINT10_STSPHSERCVD field value from a register. */
126428 #define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
126429 /* Produces a ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field value suitable for setting the register. */
126430 #define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
126431 
126432 /*
126433  * Field : back2backsetup
126434  *
126435  * Back-to-Back SETUP Packets Received (Back2BackSETup)
126436  *
126437  * Applies to Control OUT endpoints only.
126438  *
126439  * This bit indicates that the core has received more than three
126440  *
126441  * back-to-back SETUP packets For this particular endpoint. For
126442  *
126443  * information about handling this interrupt,
126444  *
126445  * Field Enumeration Values:
126446  *
126447  * Enum | Value | Description
126448  * :---------------------------------------------|:------|:---------------------------------------
126449  * ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
126450  * ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
126451  *
126452  * Field Access Macros:
126453  *
126454  */
126455 /*
126456  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP
126457  *
126458  * No Back-to-Back SETUP Packets Received
126459  */
126460 #define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_INACT 0x0
126461 /*
126462  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP
126463  *
126464  * Back-to-Back SETUP Packets Received
126465  */
126466 #define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_ACT 0x1
126467 
126468 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */
126469 #define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_LSB 6
126470 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */
126471 #define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_MSB 6
126472 /* The width in bits of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */
126473 #define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_WIDTH 1
126474 /* The mask used to set the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field value. */
126475 #define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_SET_MSK 0x00000040
126476 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field value. */
126477 #define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_CLR_MSK 0xffffffbf
126478 /* The reset value of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */
126479 #define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_RESET 0x0
126480 /* Extracts the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP field value from a register. */
126481 #define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
126482 /* Produces a ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field value suitable for setting the register. */
126483 #define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
126484 
126485 /*
126486  * Field : outpkterr
126487  *
126488  * OUT Packet Error (OutPktErr)
126489  *
126490  * Applies to OUT endpoints Only
126491  *
126492  * This interrupt is valid only when thresholding is enabled. This interrupt is
126493  * asserted when the
126494  *
126495  * core detects an overflow or a CRC error For non-Isochronous
126496  *
126497  * OUT packet.
126498  *
126499  * Field Enumeration Values:
126500  *
126501  * Enum | Value | Description
126502  * :----------------------------------------|:------|:--------------------
126503  * ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
126504  * ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
126505  *
126506  * Field Access Macros:
126507  *
126508  */
126509 /*
126510  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTPKTERR
126511  *
126512  * No OUT Packet Error
126513  */
126514 #define ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_INACT 0x0
126515 /*
126516  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTPKTERR
126517  *
126518  * OUT Packet Error
126519  */
126520 #define ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_ACT 0x1
126521 
126522 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */
126523 #define ALT_USB_DEV_DOEPINT10_OUTPKTERR_LSB 8
126524 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */
126525 #define ALT_USB_DEV_DOEPINT10_OUTPKTERR_MSB 8
126526 /* The width in bits of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */
126527 #define ALT_USB_DEV_DOEPINT10_OUTPKTERR_WIDTH 1
126528 /* The mask used to set the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field value. */
126529 #define ALT_USB_DEV_DOEPINT10_OUTPKTERR_SET_MSK 0x00000100
126530 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field value. */
126531 #define ALT_USB_DEV_DOEPINT10_OUTPKTERR_CLR_MSK 0xfffffeff
126532 /* The reset value of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */
126533 #define ALT_USB_DEV_DOEPINT10_OUTPKTERR_RESET 0x0
126534 /* Extracts the ALT_USB_DEV_DOEPINT10_OUTPKTERR field value from a register. */
126535 #define ALT_USB_DEV_DOEPINT10_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
126536 /* Produces a ALT_USB_DEV_DOEPINT10_OUTPKTERR register field value suitable for setting the register. */
126537 #define ALT_USB_DEV_DOEPINT10_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
126538 
126539 /*
126540  * Field : bnaintr
126541  *
126542  * BNA (Buffer Not Available) Interrupt (BNAIntr)
126543  *
126544  * This bit is valid only when Scatter/Gather DMA mode is enabled.
126545  *
126546  * The core generates this interrupt when the descriptor accessed
126547  *
126548  * is not ready For the Core to process, such as Host busy or DMA
126549  *
126550  * done
126551  *
126552  * Field Enumeration Values:
126553  *
126554  * Enum | Value | Description
126555  * :--------------------------------------|:------|:--------------
126556  * ALT_USB_DEV_DOEPINT10_BNAINTR_E_INACT | 0x0 | No interrupt
126557  * ALT_USB_DEV_DOEPINT10_BNAINTR_E_ACT | 0x1 | BNA interrupt
126558  *
126559  * Field Access Macros:
126560  *
126561  */
126562 /*
126563  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BNAINTR
126564  *
126565  * No interrupt
126566  */
126567 #define ALT_USB_DEV_DOEPINT10_BNAINTR_E_INACT 0x0
126568 /*
126569  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BNAINTR
126570  *
126571  * BNA interrupt
126572  */
126573 #define ALT_USB_DEV_DOEPINT10_BNAINTR_E_ACT 0x1
126574 
126575 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */
126576 #define ALT_USB_DEV_DOEPINT10_BNAINTR_LSB 9
126577 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */
126578 #define ALT_USB_DEV_DOEPINT10_BNAINTR_MSB 9
126579 /* The width in bits of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */
126580 #define ALT_USB_DEV_DOEPINT10_BNAINTR_WIDTH 1
126581 /* The mask used to set the ALT_USB_DEV_DOEPINT10_BNAINTR register field value. */
126582 #define ALT_USB_DEV_DOEPINT10_BNAINTR_SET_MSK 0x00000200
126583 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_BNAINTR register field value. */
126584 #define ALT_USB_DEV_DOEPINT10_BNAINTR_CLR_MSK 0xfffffdff
126585 /* The reset value of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */
126586 #define ALT_USB_DEV_DOEPINT10_BNAINTR_RESET 0x0
126587 /* Extracts the ALT_USB_DEV_DOEPINT10_BNAINTR field value from a register. */
126588 #define ALT_USB_DEV_DOEPINT10_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
126589 /* Produces a ALT_USB_DEV_DOEPINT10_BNAINTR register field value suitable for setting the register. */
126590 #define ALT_USB_DEV_DOEPINT10_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
126591 
126592 /*
126593  * Field : pktdrpsts
126594  *
126595  * Packet Drop Status (PktDrpSts)
126596  *
126597  * This bit indicates to the application that an ISOC OUT packet has been dropped.
126598  * This
126599  *
126600  * bit does not have an associated mask bit and does not generate an interrupt.
126601  *
126602  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
126603  * transfer
126604  *
126605  * interrupt feature is selected.
126606  *
126607  * Field Enumeration Values:
126608  *
126609  * Enum | Value | Description
126610  * :----------------------------------------|:------|:-----------------------------
126611  * ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_INACT | 0x0 | No interrupt
126612  * ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
126613  *
126614  * Field Access Macros:
126615  *
126616  */
126617 /*
126618  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_PKTDRPSTS
126619  *
126620  * No interrupt
126621  */
126622 #define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_INACT 0x0
126623 /*
126624  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_PKTDRPSTS
126625  *
126626  * Packet Drop Status interrupt
126627  */
126628 #define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_ACT 0x1
126629 
126630 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */
126631 #define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_LSB 11
126632 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */
126633 #define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_MSB 11
126634 /* The width in bits of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */
126635 #define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_WIDTH 1
126636 /* The mask used to set the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field value. */
126637 #define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_SET_MSK 0x00000800
126638 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field value. */
126639 #define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_CLR_MSK 0xfffff7ff
126640 /* The reset value of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */
126641 #define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_RESET 0x0
126642 /* Extracts the ALT_USB_DEV_DOEPINT10_PKTDRPSTS field value from a register. */
126643 #define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
126644 /* Produces a ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field value suitable for setting the register. */
126645 #define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
126646 
126647 /*
126648  * Field : bbleerr
126649  *
126650  * NAK Interrupt (BbleErr)
126651  *
126652  * The core generates this interrupt when babble is received for the endpoint.
126653  *
126654  * Field Enumeration Values:
126655  *
126656  * Enum | Value | Description
126657  * :--------------------------------------|:------|:------------------
126658  * ALT_USB_DEV_DOEPINT10_BBLEERR_E_INACT | 0x0 | No interrupt
126659  * ALT_USB_DEV_DOEPINT10_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
126660  *
126661  * Field Access Macros:
126662  *
126663  */
126664 /*
126665  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BBLEERR
126666  *
126667  * No interrupt
126668  */
126669 #define ALT_USB_DEV_DOEPINT10_BBLEERR_E_INACT 0x0
126670 /*
126671  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_BBLEERR
126672  *
126673  * BbleErr interrupt
126674  */
126675 #define ALT_USB_DEV_DOEPINT10_BBLEERR_E_ACT 0x1
126676 
126677 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */
126678 #define ALT_USB_DEV_DOEPINT10_BBLEERR_LSB 12
126679 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */
126680 #define ALT_USB_DEV_DOEPINT10_BBLEERR_MSB 12
126681 /* The width in bits of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */
126682 #define ALT_USB_DEV_DOEPINT10_BBLEERR_WIDTH 1
126683 /* The mask used to set the ALT_USB_DEV_DOEPINT10_BBLEERR register field value. */
126684 #define ALT_USB_DEV_DOEPINT10_BBLEERR_SET_MSK 0x00001000
126685 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_BBLEERR register field value. */
126686 #define ALT_USB_DEV_DOEPINT10_BBLEERR_CLR_MSK 0xffffefff
126687 /* The reset value of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */
126688 #define ALT_USB_DEV_DOEPINT10_BBLEERR_RESET 0x0
126689 /* Extracts the ALT_USB_DEV_DOEPINT10_BBLEERR field value from a register. */
126690 #define ALT_USB_DEV_DOEPINT10_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
126691 /* Produces a ALT_USB_DEV_DOEPINT10_BBLEERR register field value suitable for setting the register. */
126692 #define ALT_USB_DEV_DOEPINT10_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
126693 
126694 /*
126695  * Field : nakintrpt
126696  *
126697  * NAK Interrupt (NAKInterrupt)
126698  *
126699  * The core generates this interrupt when a NAK is transmitted or received by the
126700  * device.
126701  *
126702  * In case of isochronous IN endpoints the interrupt gets generated when a zero
126703  * length
126704  *
126705  * packet is transmitted due to un-availability of data in the TXFifo.
126706  *
126707  * Field Enumeration Values:
126708  *
126709  * Enum | Value | Description
126710  * :----------------------------------------|:------|:--------------
126711  * ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_INACT | 0x0 | No interrupt
126712  * ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
126713  *
126714  * Field Access Macros:
126715  *
126716  */
126717 /*
126718  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_NAKINTRPT
126719  *
126720  * No interrupt
126721  */
126722 #define ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_INACT 0x0
126723 /*
126724  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_NAKINTRPT
126725  *
126726  * NAK Interrupt
126727  */
126728 #define ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_ACT 0x1
126729 
126730 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */
126731 #define ALT_USB_DEV_DOEPINT10_NAKINTRPT_LSB 13
126732 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */
126733 #define ALT_USB_DEV_DOEPINT10_NAKINTRPT_MSB 13
126734 /* The width in bits of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */
126735 #define ALT_USB_DEV_DOEPINT10_NAKINTRPT_WIDTH 1
126736 /* The mask used to set the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field value. */
126737 #define ALT_USB_DEV_DOEPINT10_NAKINTRPT_SET_MSK 0x00002000
126738 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field value. */
126739 #define ALT_USB_DEV_DOEPINT10_NAKINTRPT_CLR_MSK 0xffffdfff
126740 /* The reset value of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */
126741 #define ALT_USB_DEV_DOEPINT10_NAKINTRPT_RESET 0x0
126742 /* Extracts the ALT_USB_DEV_DOEPINT10_NAKINTRPT field value from a register. */
126743 #define ALT_USB_DEV_DOEPINT10_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
126744 /* Produces a ALT_USB_DEV_DOEPINT10_NAKINTRPT register field value suitable for setting the register. */
126745 #define ALT_USB_DEV_DOEPINT10_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
126746 
126747 /*
126748  * Field : nyetintrpt
126749  *
126750  * NYET Interrupt (NYETIntrpt)
126751  *
126752  * The core generates this interrupt when a NYET response is transmitted for a non
126753  * isochronous OUT endpoint.
126754  *
126755  * Field Enumeration Values:
126756  *
126757  * Enum | Value | Description
126758  * :-----------------------------------------|:------|:---------------
126759  * ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_INACT | 0x0 | No interrupt
126760  * ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
126761  *
126762  * Field Access Macros:
126763  *
126764  */
126765 /*
126766  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_NYETINTRPT
126767  *
126768  * No interrupt
126769  */
126770 #define ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_INACT 0x0
126771 /*
126772  * Enumerated value for register field ALT_USB_DEV_DOEPINT10_NYETINTRPT
126773  *
126774  * NYET Interrupt
126775  */
126776 #define ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_ACT 0x1
126777 
126778 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */
126779 #define ALT_USB_DEV_DOEPINT10_NYETINTRPT_LSB 14
126780 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */
126781 #define ALT_USB_DEV_DOEPINT10_NYETINTRPT_MSB 14
126782 /* The width in bits of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */
126783 #define ALT_USB_DEV_DOEPINT10_NYETINTRPT_WIDTH 1
126784 /* The mask used to set the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field value. */
126785 #define ALT_USB_DEV_DOEPINT10_NYETINTRPT_SET_MSK 0x00004000
126786 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field value. */
126787 #define ALT_USB_DEV_DOEPINT10_NYETINTRPT_CLR_MSK 0xffffbfff
126788 /* The reset value of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */
126789 #define ALT_USB_DEV_DOEPINT10_NYETINTRPT_RESET 0x0
126790 /* Extracts the ALT_USB_DEV_DOEPINT10_NYETINTRPT field value from a register. */
126791 #define ALT_USB_DEV_DOEPINT10_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
126792 /* Produces a ALT_USB_DEV_DOEPINT10_NYETINTRPT register field value suitable for setting the register. */
126793 #define ALT_USB_DEV_DOEPINT10_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
126794 
126795 /*
126796  * Field : stuppktrcvd
126797  *
126798  * Setup Packet Received
126799  *
126800  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
126801  *
126802  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
126803  *
126804  * setup data. There is only one Setup packet per buffer. On receiving a
126805  *
126806  * Setup packet, the DWC_otg core closes the buffer and disables the
126807  *
126808  * corresponding endpoint. The application has to re-enable the endpoint to
126809  *
126810  * receive any OUT data for the Control Transfer and reprogram the buffer
126811  *
126812  * start address.
126813  *
126814  * Note: Because of the above behavior, the DWC_otg core can receive any
126815  *
126816  * number of back to back setup packets and one buffer for every setup
126817  *
126818  * packet is used.
126819  *
126820  * 1'b0: No Setup packet received
126821  *
126822  * 1'b1: Setup packet received
126823  *
126824  * Reset: 1'b0
126825  *
126826  * Field Access Macros:
126827  *
126828  */
126829 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field. */
126830 #define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_LSB 15
126831 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field. */
126832 #define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_MSB 15
126833 /* The width in bits of the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field. */
126834 #define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_WIDTH 1
126835 /* The mask used to set the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field value. */
126836 #define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_SET_MSK 0x00008000
126837 /* The mask used to clear the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field value. */
126838 #define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_CLR_MSK 0xffff7fff
126839 /* The reset value of the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field. */
126840 #define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_RESET 0x0
126841 /* Extracts the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD field value from a register. */
126842 #define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
126843 /* Produces a ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field value suitable for setting the register. */
126844 #define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
126845 
126846 #ifndef __ASSEMBLY__
126847 /*
126848  * WARNING: The C register and register group struct declarations are provided for
126849  * convenience and illustrative purposes. They should, however, be used with
126850  * caution as the C language standard provides no guarantees about the alignment or
126851  * atomicity of device memory accesses. The recommended practice for writing
126852  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
126853  * alt_write_word() functions.
126854  *
126855  * The struct declaration for register ALT_USB_DEV_DOEPINT10.
126856  */
126857 struct ALT_USB_DEV_DOEPINT10_s
126858 {
126859  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT10_XFERCOMPL */
126860  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT10_EPDISBLD */
126861  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT10_AHBERR */
126862  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT10_SETUP */
126863  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS */
126864  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT10_STSPHSERCVD */
126865  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP */
126866  uint32_t : 1; /* *UNDEFINED* */
126867  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT10_OUTPKTERR */
126868  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT10_BNAINTR */
126869  uint32_t : 1; /* *UNDEFINED* */
126870  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT10_PKTDRPSTS */
126871  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT10_BBLEERR */
126872  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT10_NAKINTRPT */
126873  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT10_NYETINTRPT */
126874  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT10_STUPPKTRCVD */
126875  uint32_t : 16; /* *UNDEFINED* */
126876 };
126877 
126878 /* The typedef declaration for register ALT_USB_DEV_DOEPINT10. */
126879 typedef volatile struct ALT_USB_DEV_DOEPINT10_s ALT_USB_DEV_DOEPINT10_t;
126880 #endif /* __ASSEMBLY__ */
126881 
126882 /* The reset value of the ALT_USB_DEV_DOEPINT10 register. */
126883 #define ALT_USB_DEV_DOEPINT10_RESET 0x00000000
126884 /* The byte offset of the ALT_USB_DEV_DOEPINT10 register from the beginning of the component. */
126885 #define ALT_USB_DEV_DOEPINT10_OFST 0x448
126886 /* The address of the ALT_USB_DEV_DOEPINT10 register. */
126887 #define ALT_USB_DEV_DOEPINT10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT10_OFST))
126888 
126889 /*
126890  * Register : doeptsiz10
126891  *
126892  * Device OUT Endpoint 10 Transfer Size Register
126893  *
126894  * Register Layout
126895  *
126896  * Bits | Access | Reset | Description
126897  * :--------|:-------|:------|:--------------------------------
126898  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ10_XFERSIZE
126899  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ10_PKTCNT
126900  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ10_RXDPID
126901  * [31] | ??? | 0x0 | *UNDEFINED*
126902  *
126903  */
126904 /*
126905  * Field : xfersize
126906  *
126907  * Transfer Size (XferSize)
126908  *
126909  * Indicates the transfer size in bytes For endpoint 0. The core
126910  *
126911  * interrupts the application only after it has exhausted the transfer
126912  *
126913  * size amount of data. The transfer size can be Set to the
126914  *
126915  * maximum packet size of the endpoint, to be interrupted at the
126916  *
126917  * end of each packet.
126918  *
126919  * The core decrements this field every time a packet is read from
126920  *
126921  * the RxFIFO and written to the external memory.
126922  *
126923  * Field Access Macros:
126924  *
126925  */
126926 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */
126927 #define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_LSB 0
126928 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */
126929 #define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_MSB 18
126930 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */
126931 #define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_WIDTH 19
126932 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field value. */
126933 #define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_SET_MSK 0x0007ffff
126934 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field value. */
126935 #define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_CLR_MSK 0xfff80000
126936 /* The reset value of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */
126937 #define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_RESET 0x0
126938 /* Extracts the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE field value from a register. */
126939 #define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
126940 /* Produces a ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field value suitable for setting the register. */
126941 #define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
126942 
126943 /*
126944  * Field : pktcnt
126945  *
126946  * Packet Count (PktCnt)
126947  *
126948  * This field is decremented to zero after a packet is written into the
126949  *
126950  * RxFIFO.
126951  *
126952  * Field Access Macros:
126953  *
126954  */
126955 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */
126956 #define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_LSB 19
126957 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */
126958 #define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_MSB 28
126959 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */
126960 #define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_WIDTH 10
126961 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field value. */
126962 #define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_SET_MSK 0x1ff80000
126963 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field value. */
126964 #define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_CLR_MSK 0xe007ffff
126965 /* The reset value of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */
126966 #define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_RESET 0x0
126967 /* Extracts the ALT_USB_DEV_DOEPTSIZ10_PKTCNT field value from a register. */
126968 #define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
126969 /* Produces a ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field value suitable for setting the register. */
126970 #define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
126971 
126972 /*
126973  * Field : rxdpid
126974  *
126975  * Applies to isochronous OUT endpoints only.
126976  *
126977  * This is the data PID received in the last packet for this endpoint.
126978  *
126979  * 2'b00: DATA0
126980  *
126981  * 2'b01: DATA2
126982  *
126983  * 2'b10: DATA1
126984  *
126985  * 2'b11: MDATA
126986  *
126987  * SETUP Packet Count (SUPCnt)
126988  *
126989  * Applies to control OUT Endpoints only.
126990  *
126991  * This field specifies the number of back-to-back SETUP data
126992  *
126993  * packets the endpoint can receive.
126994  *
126995  * 2'b01: 1 packet
126996  *
126997  * 2'b10: 2 packets
126998  *
126999  * 2'b11: 3 packets
127000  *
127001  * Field Enumeration Values:
127002  *
127003  * Enum | Value | Description
127004  * :------------------------------------------|:------|:-------------------
127005  * ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA0 | 0x0 | DATA0
127006  * ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
127007  * ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
127008  * ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
127009  *
127010  * Field Access Macros:
127011  *
127012  */
127013 /*
127014  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID
127015  *
127016  * DATA0
127017  */
127018 #define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA0 0x0
127019 /*
127020  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID
127021  *
127022  * DATA2 or 1 packet
127023  */
127024 #define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA2PKT1 0x1
127025 /*
127026  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID
127027  *
127028  * DATA1 or 2 packets
127029  */
127030 #define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA1PKT2 0x2
127031 /*
127032  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID
127033  *
127034  * MDATA or 3 packets
127035  */
127036 #define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_MDATAPKT3 0x3
127037 
127038 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */
127039 #define ALT_USB_DEV_DOEPTSIZ10_RXDPID_LSB 29
127040 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */
127041 #define ALT_USB_DEV_DOEPTSIZ10_RXDPID_MSB 30
127042 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */
127043 #define ALT_USB_DEV_DOEPTSIZ10_RXDPID_WIDTH 2
127044 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field value. */
127045 #define ALT_USB_DEV_DOEPTSIZ10_RXDPID_SET_MSK 0x60000000
127046 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field value. */
127047 #define ALT_USB_DEV_DOEPTSIZ10_RXDPID_CLR_MSK 0x9fffffff
127048 /* The reset value of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */
127049 #define ALT_USB_DEV_DOEPTSIZ10_RXDPID_RESET 0x0
127050 /* Extracts the ALT_USB_DEV_DOEPTSIZ10_RXDPID field value from a register. */
127051 #define ALT_USB_DEV_DOEPTSIZ10_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
127052 /* Produces a ALT_USB_DEV_DOEPTSIZ10_RXDPID register field value suitable for setting the register. */
127053 #define ALT_USB_DEV_DOEPTSIZ10_RXDPID_SET(value) (((value) << 29) & 0x60000000)
127054 
127055 #ifndef __ASSEMBLY__
127056 /*
127057  * WARNING: The C register and register group struct declarations are provided for
127058  * convenience and illustrative purposes. They should, however, be used with
127059  * caution as the C language standard provides no guarantees about the alignment or
127060  * atomicity of device memory accesses. The recommended practice for writing
127061  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
127062  * alt_write_word() functions.
127063  *
127064  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ10.
127065  */
127066 struct ALT_USB_DEV_DOEPTSIZ10_s
127067 {
127068  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ10_XFERSIZE */
127069  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ10_PKTCNT */
127070  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ10_RXDPID */
127071  uint32_t : 1; /* *UNDEFINED* */
127072 };
127073 
127074 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ10. */
127075 typedef volatile struct ALT_USB_DEV_DOEPTSIZ10_s ALT_USB_DEV_DOEPTSIZ10_t;
127076 #endif /* __ASSEMBLY__ */
127077 
127078 /* The reset value of the ALT_USB_DEV_DOEPTSIZ10 register. */
127079 #define ALT_USB_DEV_DOEPTSIZ10_RESET 0x00000000
127080 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ10 register from the beginning of the component. */
127081 #define ALT_USB_DEV_DOEPTSIZ10_OFST 0x450
127082 /* The address of the ALT_USB_DEV_DOEPTSIZ10 register. */
127083 #define ALT_USB_DEV_DOEPTSIZ10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ10_OFST))
127084 
127085 /*
127086  * Register : doepdma10
127087  *
127088  * Device OUT Endpoint 10 DMA Address Register
127089  *
127090  * Register Layout
127091  *
127092  * Bits | Access | Reset | Description
127093  * :-------|:-------|:--------|:--------------------------------
127094  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA10_DOEPDMA10
127095  *
127096  */
127097 /*
127098  * Field : doepdma10
127099  *
127100  * Holds the start address of the external memory for storing or fetching endpoint
127101  *
127102  * data.
127103  *
127104  * Note: For control endpoints, this field stores control OUT data packets as well
127105  * as
127106  *
127107  * SETUP transaction data packets. When more than three SETUP packets are
127108  *
127109  * received back-to-back, the SETUP data packet in the memory is overwritten.
127110  *
127111  * This register is incremented on every AHB transaction. The application can give
127112  *
127113  * only a DWORD-aligned address.
127114  *
127115  * When Scatter/Gather DMA mode is not enabled, the application programs the
127116  *
127117  * start address value in this field.
127118  *
127119  * When Scatter/Gather DMA mode is enabled, this field indicates the base
127120  *
127121  * pointer for the descriptor list.
127122  *
127123  * Field Access Macros:
127124  *
127125  */
127126 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field. */
127127 #define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_LSB 0
127128 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field. */
127129 #define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_MSB 31
127130 /* The width in bits of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field. */
127131 #define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_WIDTH 32
127132 /* The mask used to set the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field value. */
127133 #define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_SET_MSK 0xffffffff
127134 /* The mask used to clear the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field value. */
127135 #define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_CLR_MSK 0x00000000
127136 /* The reset value of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field is UNKNOWN. */
127137 #define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_RESET 0x0
127138 /* Extracts the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 field value from a register. */
127139 #define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_GET(value) (((value) & 0xffffffff) >> 0)
127140 /* Produces a ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field value suitable for setting the register. */
127141 #define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_SET(value) (((value) << 0) & 0xffffffff)
127142 
127143 #ifndef __ASSEMBLY__
127144 /*
127145  * WARNING: The C register and register group struct declarations are provided for
127146  * convenience and illustrative purposes. They should, however, be used with
127147  * caution as the C language standard provides no guarantees about the alignment or
127148  * atomicity of device memory accesses. The recommended practice for writing
127149  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
127150  * alt_write_word() functions.
127151  *
127152  * The struct declaration for register ALT_USB_DEV_DOEPDMA10.
127153  */
127154 struct ALT_USB_DEV_DOEPDMA10_s
127155 {
127156  uint32_t doepdma10 : 32; /* ALT_USB_DEV_DOEPDMA10_DOEPDMA10 */
127157 };
127158 
127159 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA10. */
127160 typedef volatile struct ALT_USB_DEV_DOEPDMA10_s ALT_USB_DEV_DOEPDMA10_t;
127161 #endif /* __ASSEMBLY__ */
127162 
127163 /* The reset value of the ALT_USB_DEV_DOEPDMA10 register. */
127164 #define ALT_USB_DEV_DOEPDMA10_RESET 0x00000000
127165 /* The byte offset of the ALT_USB_DEV_DOEPDMA10 register from the beginning of the component. */
127166 #define ALT_USB_DEV_DOEPDMA10_OFST 0x454
127167 /* The address of the ALT_USB_DEV_DOEPDMA10 register. */
127168 #define ALT_USB_DEV_DOEPDMA10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA10_OFST))
127169 
127170 /*
127171  * Register : doepdmab10
127172  *
127173  * Device OUT Endpoint 10 Buffer Address Register
127174  *
127175  * Register Layout
127176  *
127177  * Bits | Access | Reset | Description
127178  * :-------|:-------|:--------|:----------------------------------
127179  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10
127180  *
127181  */
127182 /*
127183  * Field : doepdmab10
127184  *
127185  * Holds the current buffer address.This register is updated as and when the data
127186  *
127187  * transfer for the corresponding end point is in progress.
127188  *
127189  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
127190  * is
127191  *
127192  * reserved.
127193  *
127194  * Field Access Macros:
127195  *
127196  */
127197 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field. */
127198 #define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_LSB 0
127199 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field. */
127200 #define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_MSB 31
127201 /* The width in bits of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field. */
127202 #define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_WIDTH 32
127203 /* The mask used to set the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field value. */
127204 #define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_SET_MSK 0xffffffff
127205 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field value. */
127206 #define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_CLR_MSK 0x00000000
127207 /* The reset value of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field is UNKNOWN. */
127208 #define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_RESET 0x0
127209 /* Extracts the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 field value from a register. */
127210 #define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_GET(value) (((value) & 0xffffffff) >> 0)
127211 /* Produces a ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field value suitable for setting the register. */
127212 #define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_SET(value) (((value) << 0) & 0xffffffff)
127213 
127214 #ifndef __ASSEMBLY__
127215 /*
127216  * WARNING: The C register and register group struct declarations are provided for
127217  * convenience and illustrative purposes. They should, however, be used with
127218  * caution as the C language standard provides no guarantees about the alignment or
127219  * atomicity of device memory accesses. The recommended practice for writing
127220  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
127221  * alt_write_word() functions.
127222  *
127223  * The struct declaration for register ALT_USB_DEV_DOEPDMAB10.
127224  */
127225 struct ALT_USB_DEV_DOEPDMAB10_s
127226 {
127227  const uint32_t doepdmab10 : 32; /* ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 */
127228 };
127229 
127230 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB10. */
127231 typedef volatile struct ALT_USB_DEV_DOEPDMAB10_s ALT_USB_DEV_DOEPDMAB10_t;
127232 #endif /* __ASSEMBLY__ */
127233 
127234 /* The reset value of the ALT_USB_DEV_DOEPDMAB10 register. */
127235 #define ALT_USB_DEV_DOEPDMAB10_RESET 0x00000000
127236 /* The byte offset of the ALT_USB_DEV_DOEPDMAB10 register from the beginning of the component. */
127237 #define ALT_USB_DEV_DOEPDMAB10_OFST 0x45c
127238 /* The address of the ALT_USB_DEV_DOEPDMAB10 register. */
127239 #define ALT_USB_DEV_DOEPDMAB10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB10_OFST))
127240 
127241 /*
127242  * Register : doepctl11
127243  *
127244  * Device Control OUT Endpoint 11 Control Register
127245  *
127246  * Register Layout
127247  *
127248  * Bits | Access | Reset | Description
127249  * :--------|:---------|:------|:-------------------------------
127250  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL11_MPS
127251  * [14:11] | ??? | 0x0 | *UNDEFINED*
127252  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL11_USBACTEP
127253  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL11_DPID
127254  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL11_NAKSTS
127255  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL11_EPTYPE
127256  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL11_SNP
127257  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL11_STALL
127258  * [25:22] | ??? | 0x0 | *UNDEFINED*
127259  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL11_CNAK
127260  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL11_SNAK
127261  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL11_SETD0PID
127262  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL11_SETD1PID
127263  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL11_EPDIS
127264  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL11_EPENA
127265  *
127266  */
127267 /*
127268  * Field : mps
127269  *
127270  * Maximum Packet Size (MPS)
127271  *
127272  * The application must program this field with the maximum packet size for the
127273  * current
127274  *
127275  * logical endpoint. This value is in bytes.
127276  *
127277  * Field Access Macros:
127278  *
127279  */
127280 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_MPS register field. */
127281 #define ALT_USB_DEV_DOEPCTL11_MPS_LSB 0
127282 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_MPS register field. */
127283 #define ALT_USB_DEV_DOEPCTL11_MPS_MSB 10
127284 /* The width in bits of the ALT_USB_DEV_DOEPCTL11_MPS register field. */
127285 #define ALT_USB_DEV_DOEPCTL11_MPS_WIDTH 11
127286 /* The mask used to set the ALT_USB_DEV_DOEPCTL11_MPS register field value. */
127287 #define ALT_USB_DEV_DOEPCTL11_MPS_SET_MSK 0x000007ff
127288 /* The mask used to clear the ALT_USB_DEV_DOEPCTL11_MPS register field value. */
127289 #define ALT_USB_DEV_DOEPCTL11_MPS_CLR_MSK 0xfffff800
127290 /* The reset value of the ALT_USB_DEV_DOEPCTL11_MPS register field. */
127291 #define ALT_USB_DEV_DOEPCTL11_MPS_RESET 0x0
127292 /* Extracts the ALT_USB_DEV_DOEPCTL11_MPS field value from a register. */
127293 #define ALT_USB_DEV_DOEPCTL11_MPS_GET(value) (((value) & 0x000007ff) >> 0)
127294 /* Produces a ALT_USB_DEV_DOEPCTL11_MPS register field value suitable for setting the register. */
127295 #define ALT_USB_DEV_DOEPCTL11_MPS_SET(value) (((value) << 0) & 0x000007ff)
127296 
127297 /*
127298  * Field : usbactep
127299  *
127300  * USB Active Endpoint (USBActEP)
127301  *
127302  * Indicates whether this endpoint is active in the current configuration and
127303  * interface. The
127304  *
127305  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
127306  * reset. After
127307  *
127308  * receiving the SetConfiguration and SetInterface commands, the application must
127309  *
127310  * program endpoint registers accordingly and set this bit.
127311  *
127312  * Field Enumeration Values:
127313  *
127314  * Enum | Value | Description
127315  * :--------------------------------------|:------|:--------------------
127316  * ALT_USB_DEV_DOEPCTL11_USBACTEP_E_DISD | 0x0 | Not Active
127317  * ALT_USB_DEV_DOEPCTL11_USBACTEP_E_END | 0x1 | USB Active Endpoint
127318  *
127319  * Field Access Macros:
127320  *
127321  */
127322 /*
127323  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_USBACTEP
127324  *
127325  * Not Active
127326  */
127327 #define ALT_USB_DEV_DOEPCTL11_USBACTEP_E_DISD 0x0
127328 /*
127329  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_USBACTEP
127330  *
127331  * USB Active Endpoint
127332  */
127333 #define ALT_USB_DEV_DOEPCTL11_USBACTEP_E_END 0x1
127334 
127335 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */
127336 #define ALT_USB_DEV_DOEPCTL11_USBACTEP_LSB 15
127337 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */
127338 #define ALT_USB_DEV_DOEPCTL11_USBACTEP_MSB 15
127339 /* The width in bits of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */
127340 #define ALT_USB_DEV_DOEPCTL11_USBACTEP_WIDTH 1
127341 /* The mask used to set the ALT_USB_DEV_DOEPCTL11_USBACTEP register field value. */
127342 #define ALT_USB_DEV_DOEPCTL11_USBACTEP_SET_MSK 0x00008000
127343 /* The mask used to clear the ALT_USB_DEV_DOEPCTL11_USBACTEP register field value. */
127344 #define ALT_USB_DEV_DOEPCTL11_USBACTEP_CLR_MSK 0xffff7fff
127345 /* The reset value of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */
127346 #define ALT_USB_DEV_DOEPCTL11_USBACTEP_RESET 0x0
127347 /* Extracts the ALT_USB_DEV_DOEPCTL11_USBACTEP field value from a register. */
127348 #define ALT_USB_DEV_DOEPCTL11_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
127349 /* Produces a ALT_USB_DEV_DOEPCTL11_USBACTEP register field value suitable for setting the register. */
127350 #define ALT_USB_DEV_DOEPCTL11_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
127351 
127352 /*
127353  * Field : dpid
127354  *
127355  * Endpoint Data PID (DPID)
127356  *
127357  * Applies to interrupt/bulk IN and OUT endpoints only.
127358  *
127359  * Contains the PID of the packet to be received or transmitted on this endpoint.
127360  * The
127361  *
127362  * application must program the PID of the first packet to be received or
127363  * transmitted on
127364  *
127365  * this endpoint, after the endpoint is activated. The applications use the
127366  * SetD1PID and
127367  *
127368  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
127369  *
127370  * 1'b0: DATA0
127371  *
127372  * 1'b1: DATA1
127373  *
127374  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
127375  *
127376  * DMA mode.
127377  *
127378  * 1'b0 RO
127379  *
127380  * Even/Odd (Micro)Frame (EO_FrNum)
127381  *
127382  * In non-Scatter/Gather DMA mode:
127383  *
127384  * Applies to isochronous IN and OUT endpoints only.
127385  *
127386  * Indicates the (micro)frame number in which the core transmits/receives
127387  * isochronous
127388  *
127389  * data for this endpoint. The application must program the even/odd (micro) frame
127390  *
127391  * number in which it intends to transmit/receive isochronous data for this
127392  * endpoint using
127393  *
127394  * the SetEvnFr and SetOddFr fields in this register.
127395  *
127396  * 1'b0: Even (micro)frame
127397  *
127398  * 1'b1: Odd (micro)frame
127399  *
127400  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
127401  * number
127402  *
127403  * in which to send data is provided in the transmit descriptor structure. The
127404  * frame in
127405  *
127406  * which data is received is updated in receive descriptor structure.
127407  *
127408  * Field Enumeration Values:
127409  *
127410  * Enum | Value | Description
127411  * :-----------------------------------|:------|:-----------------------------
127412  * ALT_USB_DEV_DOEPCTL11_DPID_E_INACT | 0x0 | Endpoint Data PID not active
127413  * ALT_USB_DEV_DOEPCTL11_DPID_E_ACT | 0x1 | Endpoint Data PID active
127414  *
127415  * Field Access Macros:
127416  *
127417  */
127418 /*
127419  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_DPID
127420  *
127421  * Endpoint Data PID not active
127422  */
127423 #define ALT_USB_DEV_DOEPCTL11_DPID_E_INACT 0x0
127424 /*
127425  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_DPID
127426  *
127427  * Endpoint Data PID active
127428  */
127429 #define ALT_USB_DEV_DOEPCTL11_DPID_E_ACT 0x1
127430 
127431 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_DPID register field. */
127432 #define ALT_USB_DEV_DOEPCTL11_DPID_LSB 16
127433 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_DPID register field. */
127434 #define ALT_USB_DEV_DOEPCTL11_DPID_MSB 16
127435 /* The width in bits of the ALT_USB_DEV_DOEPCTL11_DPID register field. */
127436 #define ALT_USB_DEV_DOEPCTL11_DPID_WIDTH 1
127437 /* The mask used to set the ALT_USB_DEV_DOEPCTL11_DPID register field value. */
127438 #define ALT_USB_DEV_DOEPCTL11_DPID_SET_MSK 0x00010000
127439 /* The mask used to clear the ALT_USB_DEV_DOEPCTL11_DPID register field value. */
127440 #define ALT_USB_DEV_DOEPCTL11_DPID_CLR_MSK 0xfffeffff
127441 /* The reset value of the ALT_USB_DEV_DOEPCTL11_DPID register field. */
127442 #define ALT_USB_DEV_DOEPCTL11_DPID_RESET 0x0
127443 /* Extracts the ALT_USB_DEV_DOEPCTL11_DPID field value from a register. */
127444 #define ALT_USB_DEV_DOEPCTL11_DPID_GET(value) (((value) & 0x00010000) >> 16)
127445 /* Produces a ALT_USB_DEV_DOEPCTL11_DPID register field value suitable for setting the register. */
127446 #define ALT_USB_DEV_DOEPCTL11_DPID_SET(value) (((value) << 16) & 0x00010000)
127447 
127448 /*
127449  * Field : naksts
127450  *
127451  * NAK Status (NAKSts)
127452  *
127453  * Indicates the following:
127454  *
127455  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
127456  *
127457  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
127458  *
127459  * When either the application or the core sets this bit:
127460  *
127461  * The core stops receiving any data on an OUT endpoint, even if there is space in
127462  *
127463  * the RxFIFO to accommodate the incoming packet.
127464  *
127465  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
127466  *
127467  * endpoint, even if there data is available in the TxFIFO.
127468  *
127469  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
127470  *
127471  * if there data is available in the TxFIFO.
127472  *
127473  * Irrespective of this bit's setting, the core always responds to SETUP data
127474  * packets with
127475  *
127476  * an ACK handshake.
127477  *
127478  * Field Enumeration Values:
127479  *
127480  * Enum | Value | Description
127481  * :--------------------------------------|:------|:------------------------------------------------
127482  * ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
127483  * : | | based on the FIFO status
127484  * ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
127485  * : | | endpoint
127486  *
127487  * Field Access Macros:
127488  *
127489  */
127490 /*
127491  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_NAKSTS
127492  *
127493  * The core is transmitting non-NAK handshakes based on the FIFO status
127494  */
127495 #define ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NONNAK 0x0
127496 /*
127497  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_NAKSTS
127498  *
127499  * The core is transmitting NAK handshakes on this endpoint
127500  */
127501 #define ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NAK 0x1
127502 
127503 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */
127504 #define ALT_USB_DEV_DOEPCTL11_NAKSTS_LSB 17
127505 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */
127506 #define ALT_USB_DEV_DOEPCTL11_NAKSTS_MSB 17
127507 /* The width in bits of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */
127508 #define ALT_USB_DEV_DOEPCTL11_NAKSTS_WIDTH 1
127509 /* The mask used to set the ALT_USB_DEV_DOEPCTL11_NAKSTS register field value. */
127510 #define ALT_USB_DEV_DOEPCTL11_NAKSTS_SET_MSK 0x00020000
127511 /* The mask used to clear the ALT_USB_DEV_DOEPCTL11_NAKSTS register field value. */
127512 #define ALT_USB_DEV_DOEPCTL11_NAKSTS_CLR_MSK 0xfffdffff
127513 /* The reset value of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */
127514 #define ALT_USB_DEV_DOEPCTL11_NAKSTS_RESET 0x0
127515 /* Extracts the ALT_USB_DEV_DOEPCTL11_NAKSTS field value from a register. */
127516 #define ALT_USB_DEV_DOEPCTL11_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
127517 /* Produces a ALT_USB_DEV_DOEPCTL11_NAKSTS register field value suitable for setting the register. */
127518 #define ALT_USB_DEV_DOEPCTL11_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
127519 
127520 /*
127521  * Field : eptype
127522  *
127523  * Endpoint Type (EPType)
127524  *
127525  * This is the transfer type supported by this logical endpoint.
127526  *
127527  * 2'b00: Control
127528  *
127529  * 2'b01: Isochronous
127530  *
127531  * 2'b10: Bulk
127532  *
127533  * 2'b11: Interrupt
127534  *
127535  * Field Enumeration Values:
127536  *
127537  * Enum | Value | Description
127538  * :-------------------------------------------|:------|:------------
127539  * ALT_USB_DEV_DOEPCTL11_EPTYPE_E_CTL | 0x0 | Control
127540  * ALT_USB_DEV_DOEPCTL11_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
127541  * ALT_USB_DEV_DOEPCTL11_EPTYPE_E_BULK | 0x2 | Bulk
127542  * ALT_USB_DEV_DOEPCTL11_EPTYPE_E_INTERRUP | 0x3 | Interrupt
127543  *
127544  * Field Access Macros:
127545  *
127546  */
127547 /*
127548  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE
127549  *
127550  * Control
127551  */
127552 #define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_CTL 0x0
127553 /*
127554  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE
127555  *
127556  * Isochronous
127557  */
127558 #define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_ISOCHRONOUS 0x1
127559 /*
127560  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE
127561  *
127562  * Bulk
127563  */
127564 #define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_BULK 0x2
127565 /*
127566  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE
127567  *
127568  * Interrupt
127569  */
127570 #define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_INTERRUP 0x3
127571 
127572 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */
127573 #define ALT_USB_DEV_DOEPCTL11_EPTYPE_LSB 18
127574 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */
127575 #define ALT_USB_DEV_DOEPCTL11_EPTYPE_MSB 19
127576 /* The width in bits of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */
127577 #define ALT_USB_DEV_DOEPCTL11_EPTYPE_WIDTH 2
127578 /* The mask used to set the ALT_USB_DEV_DOEPCTL11_EPTYPE register field value. */
127579 #define ALT_USB_DEV_DOEPCTL11_EPTYPE_SET_MSK 0x000c0000
127580 /* The mask used to clear the ALT_USB_DEV_DOEPCTL11_EPTYPE register field value. */
127581 #define ALT_USB_DEV_DOEPCTL11_EPTYPE_CLR_MSK 0xfff3ffff
127582 /* The reset value of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */
127583 #define ALT_USB_DEV_DOEPCTL11_EPTYPE_RESET 0x0
127584 /* Extracts the ALT_USB_DEV_DOEPCTL11_EPTYPE field value from a register. */
127585 #define ALT_USB_DEV_DOEPCTL11_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
127586 /* Produces a ALT_USB_DEV_DOEPCTL11_EPTYPE register field value suitable for setting the register. */
127587 #define ALT_USB_DEV_DOEPCTL11_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
127588 
127589 /*
127590  * Field : snp
127591  *
127592  * Snoop Mode (Snp)
127593  *
127594  * Applies to OUT endpoints only.
127595  *
127596  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
127597  *
127598  * check the correctness of OUT packets before transferring them to application
127599  * memory.
127600  *
127601  * Field Enumeration Values:
127602  *
127603  * Enum | Value | Description
127604  * :--------------------------------|:------|:-------------------
127605  * ALT_USB_DEV_DOEPCTL11_SNP_E_DIS | 0x0 | Disable Snoop Mode
127606  * ALT_USB_DEV_DOEPCTL11_SNP_E_EN | 0x1 | Enable Snoop Mode
127607  *
127608  * Field Access Macros:
127609  *
127610  */
127611 /*
127612  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNP
127613  *
127614  * Disable Snoop Mode
127615  */
127616 #define ALT_USB_DEV_DOEPCTL11_SNP_E_DIS 0x0
127617 /*
127618  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNP
127619  *
127620  * Enable Snoop Mode
127621  */
127622 #define ALT_USB_DEV_DOEPCTL11_SNP_E_EN 0x1
127623 
127624 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SNP register field. */
127625 #define ALT_USB_DEV_DOEPCTL11_SNP_LSB 20
127626 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SNP register field. */
127627 #define ALT_USB_DEV_DOEPCTL11_SNP_MSB 20
127628 /* The width in bits of the ALT_USB_DEV_DOEPCTL11_SNP register field. */
127629 #define ALT_USB_DEV_DOEPCTL11_SNP_WIDTH 1
127630 /* The mask used to set the ALT_USB_DEV_DOEPCTL11_SNP register field value. */
127631 #define ALT_USB_DEV_DOEPCTL11_SNP_SET_MSK 0x00100000
127632 /* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SNP register field value. */
127633 #define ALT_USB_DEV_DOEPCTL11_SNP_CLR_MSK 0xffefffff
127634 /* The reset value of the ALT_USB_DEV_DOEPCTL11_SNP register field. */
127635 #define ALT_USB_DEV_DOEPCTL11_SNP_RESET 0x0
127636 /* Extracts the ALT_USB_DEV_DOEPCTL11_SNP field value from a register. */
127637 #define ALT_USB_DEV_DOEPCTL11_SNP_GET(value) (((value) & 0x00100000) >> 20)
127638 /* Produces a ALT_USB_DEV_DOEPCTL11_SNP register field value suitable for setting the register. */
127639 #define ALT_USB_DEV_DOEPCTL11_SNP_SET(value) (((value) << 20) & 0x00100000)
127640 
127641 /*
127642  * Field : stall
127643  *
127644  * STALL Handshake (Stall)
127645  *
127646  * Applies to non-control, non-isochronous IN and OUT endpoints only.
127647  *
127648  * The application sets this bit to stall all tokens from the USB host to this
127649  * endpoint. If a
127650  *
127651  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
127652  * bit, the
127653  *
127654  * STALL bit takes priority. Only the application can clear this bit, never the
127655  * core.
127656  *
127657  * 1'b0 R_W
127658  *
127659  * Applies to control endpoints only.
127660  *
127661  * The application can only set this bit, and the core clears it, when a SETUP
127662  * token is
127663  *
127664  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
127665  * OUT
127666  *
127667  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
127668  * this bit's
127669  *
127670  * setting, the core always responds to SETUP data packets with an ACK handshake.
127671  *
127672  * Field Enumeration Values:
127673  *
127674  * Enum | Value | Description
127675  * :------------------------------------|:------|:----------------------------
127676  * ALT_USB_DEV_DOEPCTL11_STALL_E_INACT | 0x0 | STALL All Tokens not active
127677  * ALT_USB_DEV_DOEPCTL11_STALL_E_ACT | 0x1 | STALL All Tokens active
127678  *
127679  * Field Access Macros:
127680  *
127681  */
127682 /*
127683  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_STALL
127684  *
127685  * STALL All Tokens not active
127686  */
127687 #define ALT_USB_DEV_DOEPCTL11_STALL_E_INACT 0x0
127688 /*
127689  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_STALL
127690  *
127691  * STALL All Tokens active
127692  */
127693 #define ALT_USB_DEV_DOEPCTL11_STALL_E_ACT 0x1
127694 
127695 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_STALL register field. */
127696 #define ALT_USB_DEV_DOEPCTL11_STALL_LSB 21
127697 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_STALL register field. */
127698 #define ALT_USB_DEV_DOEPCTL11_STALL_MSB 21
127699 /* The width in bits of the ALT_USB_DEV_DOEPCTL11_STALL register field. */
127700 #define ALT_USB_DEV_DOEPCTL11_STALL_WIDTH 1
127701 /* The mask used to set the ALT_USB_DEV_DOEPCTL11_STALL register field value. */
127702 #define ALT_USB_DEV_DOEPCTL11_STALL_SET_MSK 0x00200000
127703 /* The mask used to clear the ALT_USB_DEV_DOEPCTL11_STALL register field value. */
127704 #define ALT_USB_DEV_DOEPCTL11_STALL_CLR_MSK 0xffdfffff
127705 /* The reset value of the ALT_USB_DEV_DOEPCTL11_STALL register field. */
127706 #define ALT_USB_DEV_DOEPCTL11_STALL_RESET 0x0
127707 /* Extracts the ALT_USB_DEV_DOEPCTL11_STALL field value from a register. */
127708 #define ALT_USB_DEV_DOEPCTL11_STALL_GET(value) (((value) & 0x00200000) >> 21)
127709 /* Produces a ALT_USB_DEV_DOEPCTL11_STALL register field value suitable for setting the register. */
127710 #define ALT_USB_DEV_DOEPCTL11_STALL_SET(value) (((value) << 21) & 0x00200000)
127711 
127712 /*
127713  * Field : cnak
127714  *
127715  * Clear NAK (CNAK)
127716  *
127717  * A write to this bit clears the NAK bit For the endpoint.
127718  *
127719  * Field Enumeration Values:
127720  *
127721  * Enum | Value | Description
127722  * :-----------------------------------|:------|:-------------
127723  * ALT_USB_DEV_DOEPCTL11_CNAK_E_INACT | 0x0 | No Clear NAK
127724  * ALT_USB_DEV_DOEPCTL11_CNAK_E_ACT | 0x1 | Clear NAK
127725  *
127726  * Field Access Macros:
127727  *
127728  */
127729 /*
127730  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_CNAK
127731  *
127732  * No Clear NAK
127733  */
127734 #define ALT_USB_DEV_DOEPCTL11_CNAK_E_INACT 0x0
127735 /*
127736  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_CNAK
127737  *
127738  * Clear NAK
127739  */
127740 #define ALT_USB_DEV_DOEPCTL11_CNAK_E_ACT 0x1
127741 
127742 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */
127743 #define ALT_USB_DEV_DOEPCTL11_CNAK_LSB 26
127744 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */
127745 #define ALT_USB_DEV_DOEPCTL11_CNAK_MSB 26
127746 /* The width in bits of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */
127747 #define ALT_USB_DEV_DOEPCTL11_CNAK_WIDTH 1
127748 /* The mask used to set the ALT_USB_DEV_DOEPCTL11_CNAK register field value. */
127749 #define ALT_USB_DEV_DOEPCTL11_CNAK_SET_MSK 0x04000000
127750 /* The mask used to clear the ALT_USB_DEV_DOEPCTL11_CNAK register field value. */
127751 #define ALT_USB_DEV_DOEPCTL11_CNAK_CLR_MSK 0xfbffffff
127752 /* The reset value of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */
127753 #define ALT_USB_DEV_DOEPCTL11_CNAK_RESET 0x0
127754 /* Extracts the ALT_USB_DEV_DOEPCTL11_CNAK field value from a register. */
127755 #define ALT_USB_DEV_DOEPCTL11_CNAK_GET(value) (((value) & 0x04000000) >> 26)
127756 /* Produces a ALT_USB_DEV_DOEPCTL11_CNAK register field value suitable for setting the register. */
127757 #define ALT_USB_DEV_DOEPCTL11_CNAK_SET(value) (((value) << 26) & 0x04000000)
127758 
127759 /*
127760  * Field : snak
127761  *
127762  * Set NAK (SNAK)
127763  *
127764  * A write to this bit sets the NAK bit For the endpoint.
127765  *
127766  * Using this bit, the application can control the transmission of NAK
127767  *
127768  * handshakes on an endpoint. The core can also Set this bit For an
127769  *
127770  * endpoint after a SETUP packet is received on that endpoint.
127771  *
127772  * Field Enumeration Values:
127773  *
127774  * Enum | Value | Description
127775  * :-----------------------------------|:------|:------------
127776  * ALT_USB_DEV_DOEPCTL11_SNAK_E_INACT | 0x0 | No Set NAK
127777  * ALT_USB_DEV_DOEPCTL11_SNAK_E_ACT | 0x1 | Set NAK
127778  *
127779  * Field Access Macros:
127780  *
127781  */
127782 /*
127783  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNAK
127784  *
127785  * No Set NAK
127786  */
127787 #define ALT_USB_DEV_DOEPCTL11_SNAK_E_INACT 0x0
127788 /*
127789  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNAK
127790  *
127791  * Set NAK
127792  */
127793 #define ALT_USB_DEV_DOEPCTL11_SNAK_E_ACT 0x1
127794 
127795 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */
127796 #define ALT_USB_DEV_DOEPCTL11_SNAK_LSB 27
127797 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */
127798 #define ALT_USB_DEV_DOEPCTL11_SNAK_MSB 27
127799 /* The width in bits of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */
127800 #define ALT_USB_DEV_DOEPCTL11_SNAK_WIDTH 1
127801 /* The mask used to set the ALT_USB_DEV_DOEPCTL11_SNAK register field value. */
127802 #define ALT_USB_DEV_DOEPCTL11_SNAK_SET_MSK 0x08000000
127803 /* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SNAK register field value. */
127804 #define ALT_USB_DEV_DOEPCTL11_SNAK_CLR_MSK 0xf7ffffff
127805 /* The reset value of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */
127806 #define ALT_USB_DEV_DOEPCTL11_SNAK_RESET 0x0
127807 /* Extracts the ALT_USB_DEV_DOEPCTL11_SNAK field value from a register. */
127808 #define ALT_USB_DEV_DOEPCTL11_SNAK_GET(value) (((value) & 0x08000000) >> 27)
127809 /* Produces a ALT_USB_DEV_DOEPCTL11_SNAK register field value suitable for setting the register. */
127810 #define ALT_USB_DEV_DOEPCTL11_SNAK_SET(value) (((value) << 27) & 0x08000000)
127811 
127812 /*
127813  * Field : setd0pid
127814  *
127815  * Set DATA0 PID (SetD0PID)
127816  *
127817  * Applies to interrupt/bulk IN and OUT endpoints only.
127818  *
127819  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
127820  * to DATA0.
127821  *
127822  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
127823  *
127824  * DMA mode.
127825  *
127826  * 1'b0 WO
127827  *
127828  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
127829  *
127830  * Applies to isochronous IN and OUT endpoints only.
127831  *
127832  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
127833  * (micro)
127834  *
127835  * frame.
127836  *
127837  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
127838  * number
127839  *
127840  * in which to send data is in the transmit descriptor structure. The frame in
127841  * which to
127842  *
127843  * receive data is updated in receive descriptor structure.
127844  *
127845  * Field Enumeration Values:
127846  *
127847  * Enum | Value | Description
127848  * :--------------------------------------|:------|:------------------------------------
127849  * ALT_USB_DEV_DOEPCTL11_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
127850  * ALT_USB_DEV_DOEPCTL11_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
127851  *
127852  * Field Access Macros:
127853  *
127854  */
127855 /*
127856  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD0PID
127857  *
127858  * Disables Set DATA0 PID
127859  */
127860 #define ALT_USB_DEV_DOEPCTL11_SETD0PID_E_DISD 0x0
127861 /*
127862  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD0PID
127863  *
127864  * Enables Endpoint Data PID to DATA0)
127865  */
127866 #define ALT_USB_DEV_DOEPCTL11_SETD0PID_E_END 0x1
127867 
127868 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */
127869 #define ALT_USB_DEV_DOEPCTL11_SETD0PID_LSB 28
127870 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */
127871 #define ALT_USB_DEV_DOEPCTL11_SETD0PID_MSB 28
127872 /* The width in bits of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */
127873 #define ALT_USB_DEV_DOEPCTL11_SETD0PID_WIDTH 1
127874 /* The mask used to set the ALT_USB_DEV_DOEPCTL11_SETD0PID register field value. */
127875 #define ALT_USB_DEV_DOEPCTL11_SETD0PID_SET_MSK 0x10000000
127876 /* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SETD0PID register field value. */
127877 #define ALT_USB_DEV_DOEPCTL11_SETD0PID_CLR_MSK 0xefffffff
127878 /* The reset value of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */
127879 #define ALT_USB_DEV_DOEPCTL11_SETD0PID_RESET 0x0
127880 /* Extracts the ALT_USB_DEV_DOEPCTL11_SETD0PID field value from a register. */
127881 #define ALT_USB_DEV_DOEPCTL11_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
127882 /* Produces a ALT_USB_DEV_DOEPCTL11_SETD0PID register field value suitable for setting the register. */
127883 #define ALT_USB_DEV_DOEPCTL11_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
127884 
127885 /*
127886  * Field : setd1pid
127887  *
127888  * Set DATA1 PID (SetD1PID)
127889  *
127890  * Applies to interrupt/bulk IN and OUT endpoints only.
127891  *
127892  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
127893  * to DATA1.
127894  *
127895  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
127896  *
127897  * DMA mode.
127898  *
127899  * Set Odd (micro)frame (SetOddFr)
127900  *
127901  * Applies to isochronous IN and OUT endpoints only.
127902  *
127903  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
127904  *
127905  * (micro)frame.
127906  *
127907  * This field is not applicable for Scatter/Gather DMA mode.
127908  *
127909  * Field Enumeration Values:
127910  *
127911  * Enum | Value | Description
127912  * :--------------------------------------|:------|:-----------------------
127913  * ALT_USB_DEV_DOEPCTL11_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
127914  * ALT_USB_DEV_DOEPCTL11_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
127915  *
127916  * Field Access Macros:
127917  *
127918  */
127919 /*
127920  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD1PID
127921  *
127922  * Disables Set DATA1 PID
127923  */
127924 #define ALT_USB_DEV_DOEPCTL11_SETD1PID_E_DISD 0x0
127925 /*
127926  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD1PID
127927  *
127928  * Enables Set DATA1 PID
127929  */
127930 #define ALT_USB_DEV_DOEPCTL11_SETD1PID_E_END 0x1
127931 
127932 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */
127933 #define ALT_USB_DEV_DOEPCTL11_SETD1PID_LSB 29
127934 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */
127935 #define ALT_USB_DEV_DOEPCTL11_SETD1PID_MSB 29
127936 /* The width in bits of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */
127937 #define ALT_USB_DEV_DOEPCTL11_SETD1PID_WIDTH 1
127938 /* The mask used to set the ALT_USB_DEV_DOEPCTL11_SETD1PID register field value. */
127939 #define ALT_USB_DEV_DOEPCTL11_SETD1PID_SET_MSK 0x20000000
127940 /* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SETD1PID register field value. */
127941 #define ALT_USB_DEV_DOEPCTL11_SETD1PID_CLR_MSK 0xdfffffff
127942 /* The reset value of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */
127943 #define ALT_USB_DEV_DOEPCTL11_SETD1PID_RESET 0x0
127944 /* Extracts the ALT_USB_DEV_DOEPCTL11_SETD1PID field value from a register. */
127945 #define ALT_USB_DEV_DOEPCTL11_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
127946 /* Produces a ALT_USB_DEV_DOEPCTL11_SETD1PID register field value suitable for setting the register. */
127947 #define ALT_USB_DEV_DOEPCTL11_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
127948 
127949 /*
127950  * Field : epdis
127951  *
127952  * Endpoint Disable (EPDis)
127953  *
127954  * Applies to IN and OUT endpoints.
127955  *
127956  * The application sets this bit to stop transmitting/receiving data on an
127957  * endpoint, even
127958  *
127959  * before the transfer for that endpoint is complete. The application must wait for
127960  * the
127961  *
127962  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
127963  * clears
127964  *
127965  * this bit before setting the Endpoint Disabled interrupt. The application must
127966  * set this bit
127967  *
127968  * only if Endpoint Enable is already set for this endpoint.
127969  *
127970  * Field Enumeration Values:
127971  *
127972  * Enum | Value | Description
127973  * :------------------------------------|:------|:--------------------
127974  * ALT_USB_DEV_DOEPCTL11_EPDIS_E_INACT | 0x0 | No Endpoint Disable
127975  * ALT_USB_DEV_DOEPCTL11_EPDIS_E_ACT | 0x1 | Endpoint Disable
127976  *
127977  * Field Access Macros:
127978  *
127979  */
127980 /*
127981  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPDIS
127982  *
127983  * No Endpoint Disable
127984  */
127985 #define ALT_USB_DEV_DOEPCTL11_EPDIS_E_INACT 0x0
127986 /*
127987  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPDIS
127988  *
127989  * Endpoint Disable
127990  */
127991 #define ALT_USB_DEV_DOEPCTL11_EPDIS_E_ACT 0x1
127992 
127993 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */
127994 #define ALT_USB_DEV_DOEPCTL11_EPDIS_LSB 30
127995 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */
127996 #define ALT_USB_DEV_DOEPCTL11_EPDIS_MSB 30
127997 /* The width in bits of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */
127998 #define ALT_USB_DEV_DOEPCTL11_EPDIS_WIDTH 1
127999 /* The mask used to set the ALT_USB_DEV_DOEPCTL11_EPDIS register field value. */
128000 #define ALT_USB_DEV_DOEPCTL11_EPDIS_SET_MSK 0x40000000
128001 /* The mask used to clear the ALT_USB_DEV_DOEPCTL11_EPDIS register field value. */
128002 #define ALT_USB_DEV_DOEPCTL11_EPDIS_CLR_MSK 0xbfffffff
128003 /* The reset value of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */
128004 #define ALT_USB_DEV_DOEPCTL11_EPDIS_RESET 0x0
128005 /* Extracts the ALT_USB_DEV_DOEPCTL11_EPDIS field value from a register. */
128006 #define ALT_USB_DEV_DOEPCTL11_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
128007 /* Produces a ALT_USB_DEV_DOEPCTL11_EPDIS register field value suitable for setting the register. */
128008 #define ALT_USB_DEV_DOEPCTL11_EPDIS_SET(value) (((value) << 30) & 0x40000000)
128009 
128010 /*
128011  * Field : epena
128012  *
128013  * Endpoint Enable (EPEna)
128014  *
128015  * Applies to IN and OUT endpoints.
128016  *
128017  * When Scatter/Gather DMA mode is enabled,
128018  *
128019  * For IN endpoints this bit indicates that the descriptor structure and data
128020  * buffer with
128021  *
128022  * data ready to transmit is setup.
128023  *
128024  * For OUT endpoint it indicates that the descriptor structure and data buffer to
128025  *
128026  * receive data is setup.
128027  *
128028  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
128029  *
128030  * DMA mode:
128031  *
128032  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
128033  * the
128034  *
128035  * endpoint.
128036  *
128037  * * For OUT endpoints, this bit indicates that the application has allocated the
128038  *
128039  * memory to start receiving data from the USB.
128040  *
128041  * * The core clears this bit before setting any of the following interrupts on
128042  * this
128043  *
128044  * endpoint:
128045  *
128046  * SETUP Phase Done
128047  *
128048  * Endpoint Disabled
128049  *
128050  * Transfer Completed
128051  *
128052  * Note: For control endpoints in DMA mode, this bit must be set to be able to
128053  * transfer
128054  *
128055  * SETUP data packets in memory.
128056  *
128057  * Field Enumeration Values:
128058  *
128059  * Enum | Value | Description
128060  * :------------------------------------|:------|:-------------------------
128061  * ALT_USB_DEV_DOEPCTL11_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
128062  * ALT_USB_DEV_DOEPCTL11_EPENA_E_ACT | 0x1 | Endpoint Enable active
128063  *
128064  * Field Access Macros:
128065  *
128066  */
128067 /*
128068  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPENA
128069  *
128070  * Endpoint Enable inactive
128071  */
128072 #define ALT_USB_DEV_DOEPCTL11_EPENA_E_INACT 0x0
128073 /*
128074  * Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPENA
128075  *
128076  * Endpoint Enable active
128077  */
128078 #define ALT_USB_DEV_DOEPCTL11_EPENA_E_ACT 0x1
128079 
128080 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */
128081 #define ALT_USB_DEV_DOEPCTL11_EPENA_LSB 31
128082 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */
128083 #define ALT_USB_DEV_DOEPCTL11_EPENA_MSB 31
128084 /* The width in bits of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */
128085 #define ALT_USB_DEV_DOEPCTL11_EPENA_WIDTH 1
128086 /* The mask used to set the ALT_USB_DEV_DOEPCTL11_EPENA register field value. */
128087 #define ALT_USB_DEV_DOEPCTL11_EPENA_SET_MSK 0x80000000
128088 /* The mask used to clear the ALT_USB_DEV_DOEPCTL11_EPENA register field value. */
128089 #define ALT_USB_DEV_DOEPCTL11_EPENA_CLR_MSK 0x7fffffff
128090 /* The reset value of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */
128091 #define ALT_USB_DEV_DOEPCTL11_EPENA_RESET 0x0
128092 /* Extracts the ALT_USB_DEV_DOEPCTL11_EPENA field value from a register. */
128093 #define ALT_USB_DEV_DOEPCTL11_EPENA_GET(value) (((value) & 0x80000000) >> 31)
128094 /* Produces a ALT_USB_DEV_DOEPCTL11_EPENA register field value suitable for setting the register. */
128095 #define ALT_USB_DEV_DOEPCTL11_EPENA_SET(value) (((value) << 31) & 0x80000000)
128096 
128097 #ifndef __ASSEMBLY__
128098 /*
128099  * WARNING: The C register and register group struct declarations are provided for
128100  * convenience and illustrative purposes. They should, however, be used with
128101  * caution as the C language standard provides no guarantees about the alignment or
128102  * atomicity of device memory accesses. The recommended practice for writing
128103  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
128104  * alt_write_word() functions.
128105  *
128106  * The struct declaration for register ALT_USB_DEV_DOEPCTL11.
128107  */
128108 struct ALT_USB_DEV_DOEPCTL11_s
128109 {
128110  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL11_MPS */
128111  uint32_t : 4; /* *UNDEFINED* */
128112  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL11_USBACTEP */
128113  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL11_DPID */
128114  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL11_NAKSTS */
128115  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL11_EPTYPE */
128116  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL11_SNP */
128117  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL11_STALL */
128118  uint32_t : 4; /* *UNDEFINED* */
128119  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL11_CNAK */
128120  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL11_SNAK */
128121  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL11_SETD0PID */
128122  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL11_SETD1PID */
128123  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL11_EPDIS */
128124  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL11_EPENA */
128125 };
128126 
128127 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL11. */
128128 typedef volatile struct ALT_USB_DEV_DOEPCTL11_s ALT_USB_DEV_DOEPCTL11_t;
128129 #endif /* __ASSEMBLY__ */
128130 
128131 /* The reset value of the ALT_USB_DEV_DOEPCTL11 register. */
128132 #define ALT_USB_DEV_DOEPCTL11_RESET 0x00000000
128133 /* The byte offset of the ALT_USB_DEV_DOEPCTL11 register from the beginning of the component. */
128134 #define ALT_USB_DEV_DOEPCTL11_OFST 0x460
128135 /* The address of the ALT_USB_DEV_DOEPCTL11 register. */
128136 #define ALT_USB_DEV_DOEPCTL11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL11_OFST))
128137 
128138 /*
128139  * Register : doepint11
128140  *
128141  * Device OUT Endpoint 11 Interrupt Register
128142  *
128143  * Register Layout
128144  *
128145  * Bits | Access | Reset | Description
128146  * :--------|:-------|:------|:-------------------------------------
128147  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_XFERCOMPL
128148  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_EPDISBLD
128149  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_AHBERR
128150  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_SETUP
128151  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS
128152  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_STSPHSERCVD
128153  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP
128154  * [7] | ??? | 0x0 | *UNDEFINED*
128155  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_OUTPKTERR
128156  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_BNAINTR
128157  * [10] | ??? | 0x0 | *UNDEFINED*
128158  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_PKTDRPSTS
128159  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_BBLEERR
128160  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_NAKINTRPT
128161  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_NYETINTRPT
128162  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_STUPPKTRCVD
128163  * [31:16] | ??? | 0x0 | *UNDEFINED*
128164  *
128165  */
128166 /*
128167  * Field : xfercompl
128168  *
128169  * Transfer Completed Interrupt (XferCompl)
128170  *
128171  * Applies to IN and OUT endpoints.
128172  *
128173  * When Scatter/Gather DMA mode is enabled
128174  *
128175  * * For IN endpoint this field indicates that the requested data
128176  *
128177  * from the descriptor is moved from external system memory
128178  *
128179  * to internal FIFO.
128180  *
128181  * * For OUT endpoint this field indicates that the requested
128182  *
128183  * data from the internal FIFO is moved to external system
128184  *
128185  * memory. This interrupt is generated only when the
128186  *
128187  * corresponding endpoint descriptor is closed, and the IOC
128188  *
128189  * bit For the corresponding descriptor is Set.
128190  *
128191  * When Scatter/Gather DMA mode is disabled, this field
128192  *
128193  * indicates that the programmed transfer is complete on the
128194  *
128195  * AHB as well as on the USB, For this endpoint.
128196  *
128197  * Field Enumeration Values:
128198  *
128199  * Enum | Value | Description
128200  * :----------------------------------------|:------|:-----------------------------
128201  * ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_INACT | 0x0 | No Interrupt
128202  * ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
128203  *
128204  * Field Access Macros:
128205  *
128206  */
128207 /*
128208  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_XFERCOMPL
128209  *
128210  * No Interrupt
128211  */
128212 #define ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_INACT 0x0
128213 /*
128214  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_XFERCOMPL
128215  *
128216  * Transfer Completed Interrupt
128217  */
128218 #define ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_ACT 0x1
128219 
128220 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */
128221 #define ALT_USB_DEV_DOEPINT11_XFERCOMPL_LSB 0
128222 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */
128223 #define ALT_USB_DEV_DOEPINT11_XFERCOMPL_MSB 0
128224 /* The width in bits of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */
128225 #define ALT_USB_DEV_DOEPINT11_XFERCOMPL_WIDTH 1
128226 /* The mask used to set the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field value. */
128227 #define ALT_USB_DEV_DOEPINT11_XFERCOMPL_SET_MSK 0x00000001
128228 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field value. */
128229 #define ALT_USB_DEV_DOEPINT11_XFERCOMPL_CLR_MSK 0xfffffffe
128230 /* The reset value of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */
128231 #define ALT_USB_DEV_DOEPINT11_XFERCOMPL_RESET 0x0
128232 /* Extracts the ALT_USB_DEV_DOEPINT11_XFERCOMPL field value from a register. */
128233 #define ALT_USB_DEV_DOEPINT11_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
128234 /* Produces a ALT_USB_DEV_DOEPINT11_XFERCOMPL register field value suitable for setting the register. */
128235 #define ALT_USB_DEV_DOEPINT11_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
128236 
128237 /*
128238  * Field : epdisbld
128239  *
128240  * Endpoint Disabled Interrupt (EPDisbld)
128241  *
128242  * Applies to IN and OUT endpoints.
128243  *
128244  * This bit indicates that the endpoint is disabled per the
128245  *
128246  * application's request.
128247  *
128248  * Field Enumeration Values:
128249  *
128250  * Enum | Value | Description
128251  * :---------------------------------------|:------|:----------------------------
128252  * ALT_USB_DEV_DOEPINT11_EPDISBLD_E_INACT | 0x0 | No Interrupt
128253  * ALT_USB_DEV_DOEPINT11_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
128254  *
128255  * Field Access Macros:
128256  *
128257  */
128258 /*
128259  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_EPDISBLD
128260  *
128261  * No Interrupt
128262  */
128263 #define ALT_USB_DEV_DOEPINT11_EPDISBLD_E_INACT 0x0
128264 /*
128265  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_EPDISBLD
128266  *
128267  * Endpoint Disabled Interrupt
128268  */
128269 #define ALT_USB_DEV_DOEPINT11_EPDISBLD_E_ACT 0x1
128270 
128271 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */
128272 #define ALT_USB_DEV_DOEPINT11_EPDISBLD_LSB 1
128273 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */
128274 #define ALT_USB_DEV_DOEPINT11_EPDISBLD_MSB 1
128275 /* The width in bits of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */
128276 #define ALT_USB_DEV_DOEPINT11_EPDISBLD_WIDTH 1
128277 /* The mask used to set the ALT_USB_DEV_DOEPINT11_EPDISBLD register field value. */
128278 #define ALT_USB_DEV_DOEPINT11_EPDISBLD_SET_MSK 0x00000002
128279 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_EPDISBLD register field value. */
128280 #define ALT_USB_DEV_DOEPINT11_EPDISBLD_CLR_MSK 0xfffffffd
128281 /* The reset value of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */
128282 #define ALT_USB_DEV_DOEPINT11_EPDISBLD_RESET 0x0
128283 /* Extracts the ALT_USB_DEV_DOEPINT11_EPDISBLD field value from a register. */
128284 #define ALT_USB_DEV_DOEPINT11_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
128285 /* Produces a ALT_USB_DEV_DOEPINT11_EPDISBLD register field value suitable for setting the register. */
128286 #define ALT_USB_DEV_DOEPINT11_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
128287 
128288 /*
128289  * Field : ahberr
128290  *
128291  * AHB Error (AHBErr)
128292  *
128293  * Applies to IN and OUT endpoints.
128294  *
128295  * This is generated only in Internal DMA mode when there is an
128296  *
128297  * AHB error during an AHB read/write. The application can read
128298  *
128299  * the corresponding endpoint DMA address register to get the
128300  *
128301  * error address.
128302  *
128303  * Field Enumeration Values:
128304  *
128305  * Enum | Value | Description
128306  * :-------------------------------------|:------|:--------------------
128307  * ALT_USB_DEV_DOEPINT11_AHBERR_E_INACT | 0x0 | No Interrupt
128308  * ALT_USB_DEV_DOEPINT11_AHBERR_E_ACT | 0x1 | AHB Error interrupt
128309  *
128310  * Field Access Macros:
128311  *
128312  */
128313 /*
128314  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_AHBERR
128315  *
128316  * No Interrupt
128317  */
128318 #define ALT_USB_DEV_DOEPINT11_AHBERR_E_INACT 0x0
128319 /*
128320  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_AHBERR
128321  *
128322  * AHB Error interrupt
128323  */
128324 #define ALT_USB_DEV_DOEPINT11_AHBERR_E_ACT 0x1
128325 
128326 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */
128327 #define ALT_USB_DEV_DOEPINT11_AHBERR_LSB 2
128328 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */
128329 #define ALT_USB_DEV_DOEPINT11_AHBERR_MSB 2
128330 /* The width in bits of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */
128331 #define ALT_USB_DEV_DOEPINT11_AHBERR_WIDTH 1
128332 /* The mask used to set the ALT_USB_DEV_DOEPINT11_AHBERR register field value. */
128333 #define ALT_USB_DEV_DOEPINT11_AHBERR_SET_MSK 0x00000004
128334 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_AHBERR register field value. */
128335 #define ALT_USB_DEV_DOEPINT11_AHBERR_CLR_MSK 0xfffffffb
128336 /* The reset value of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */
128337 #define ALT_USB_DEV_DOEPINT11_AHBERR_RESET 0x0
128338 /* Extracts the ALT_USB_DEV_DOEPINT11_AHBERR field value from a register. */
128339 #define ALT_USB_DEV_DOEPINT11_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
128340 /* Produces a ALT_USB_DEV_DOEPINT11_AHBERR register field value suitable for setting the register. */
128341 #define ALT_USB_DEV_DOEPINT11_AHBERR_SET(value) (((value) << 2) & 0x00000004)
128342 
128343 /*
128344  * Field : setup
128345  *
128346  * SETUP Phase Done (SetUp)
128347  *
128348  * Applies to control OUT endpoints only.
128349  *
128350  * Indicates that the SETUP phase For the control endpoint is
128351  *
128352  * complete and no more back-to-back SETUP packets were
128353  *
128354  * received For the current control transfer. On this interrupt, the
128355  *
128356  * application can decode the received SETUP data packet.
128357  *
128358  * Field Enumeration Values:
128359  *
128360  * Enum | Value | Description
128361  * :------------------------------------|:------|:--------------------
128362  * ALT_USB_DEV_DOEPINT11_SETUP_E_INACT | 0x0 | No SETUP Phase Done
128363  * ALT_USB_DEV_DOEPINT11_SETUP_E_ACT | 0x1 | SETUP Phase Done
128364  *
128365  * Field Access Macros:
128366  *
128367  */
128368 /*
128369  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_SETUP
128370  *
128371  * No SETUP Phase Done
128372  */
128373 #define ALT_USB_DEV_DOEPINT11_SETUP_E_INACT 0x0
128374 /*
128375  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_SETUP
128376  *
128377  * SETUP Phase Done
128378  */
128379 #define ALT_USB_DEV_DOEPINT11_SETUP_E_ACT 0x1
128380 
128381 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_SETUP register field. */
128382 #define ALT_USB_DEV_DOEPINT11_SETUP_LSB 3
128383 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_SETUP register field. */
128384 #define ALT_USB_DEV_DOEPINT11_SETUP_MSB 3
128385 /* The width in bits of the ALT_USB_DEV_DOEPINT11_SETUP register field. */
128386 #define ALT_USB_DEV_DOEPINT11_SETUP_WIDTH 1
128387 /* The mask used to set the ALT_USB_DEV_DOEPINT11_SETUP register field value. */
128388 #define ALT_USB_DEV_DOEPINT11_SETUP_SET_MSK 0x00000008
128389 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_SETUP register field value. */
128390 #define ALT_USB_DEV_DOEPINT11_SETUP_CLR_MSK 0xfffffff7
128391 /* The reset value of the ALT_USB_DEV_DOEPINT11_SETUP register field. */
128392 #define ALT_USB_DEV_DOEPINT11_SETUP_RESET 0x0
128393 /* Extracts the ALT_USB_DEV_DOEPINT11_SETUP field value from a register. */
128394 #define ALT_USB_DEV_DOEPINT11_SETUP_GET(value) (((value) & 0x00000008) >> 3)
128395 /* Produces a ALT_USB_DEV_DOEPINT11_SETUP register field value suitable for setting the register. */
128396 #define ALT_USB_DEV_DOEPINT11_SETUP_SET(value) (((value) << 3) & 0x00000008)
128397 
128398 /*
128399  * Field : outtknepdis
128400  *
128401  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
128402  *
128403  * Applies only to control OUT endpoints.
128404  *
128405  * Indicates that an OUT token was received when the endpoint
128406  *
128407  * was not yet enabled. This interrupt is asserted on the endpoint
128408  *
128409  * For which the OUT token was received.
128410  *
128411  * Field Enumeration Values:
128412  *
128413  * Enum | Value | Description
128414  * :------------------------------------------|:------|:---------------------------------------------
128415  * ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
128416  * ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
128417  *
128418  * Field Access Macros:
128419  *
128420  */
128421 /*
128422  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS
128423  *
128424  * No OUT Token Received When Endpoint Disabled
128425  */
128426 #define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_INACT 0x0
128427 /*
128428  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS
128429  *
128430  * OUT Token Received When Endpoint Disabled
128431  */
128432 #define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_ACT 0x1
128433 
128434 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */
128435 #define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_LSB 4
128436 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */
128437 #define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_MSB 4
128438 /* The width in bits of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */
128439 #define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_WIDTH 1
128440 /* The mask used to set the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field value. */
128441 #define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_SET_MSK 0x00000010
128442 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field value. */
128443 #define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_CLR_MSK 0xffffffef
128444 /* The reset value of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */
128445 #define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_RESET 0x0
128446 /* Extracts the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS field value from a register. */
128447 #define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
128448 /* Produces a ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field value suitable for setting the register. */
128449 #define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
128450 
128451 /*
128452  * Field : stsphsercvd
128453  *
128454  * Status Phase Received For Control Write (StsPhseRcvd)
128455  *
128456  * This interrupt is valid only For Control OUT endpoints and only in
128457  *
128458  * Scatter Gather DMA mode.
128459  *
128460  * This interrupt is generated only after the core has transferred all
128461  *
128462  * the data that the host has sent during the data phase of a control
128463  *
128464  * write transfer, to the system memory buffer.
128465  *
128466  * The interrupt indicates to the application that the host has
128467  *
128468  * switched from data phase to the status phase of a Control Write
128469  *
128470  * transfer. The application can use this interrupt to ACK or STALL
128471  *
128472  * the Status phase, after it has decoded the data phase. This is
128473  *
128474  * applicable only in Case of Scatter Gather DMA mode.
128475  *
128476  * Field Enumeration Values:
128477  *
128478  * Enum | Value | Description
128479  * :------------------------------------------|:------|:-------------------------------------------
128480  * ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
128481  * ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
128482  *
128483  * Field Access Macros:
128484  *
128485  */
128486 /*
128487  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_STSPHSERCVD
128488  *
128489  * No Status Phase Received for Control Write
128490  */
128491 #define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_INACT 0x0
128492 /*
128493  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_STSPHSERCVD
128494  *
128495  * Status Phase Received for Control Write
128496  */
128497 #define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_ACT 0x1
128498 
128499 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */
128500 #define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_LSB 5
128501 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */
128502 #define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_MSB 5
128503 /* The width in bits of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */
128504 #define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_WIDTH 1
128505 /* The mask used to set the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field value. */
128506 #define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_SET_MSK 0x00000020
128507 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field value. */
128508 #define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_CLR_MSK 0xffffffdf
128509 /* The reset value of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */
128510 #define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_RESET 0x0
128511 /* Extracts the ALT_USB_DEV_DOEPINT11_STSPHSERCVD field value from a register. */
128512 #define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
128513 /* Produces a ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field value suitable for setting the register. */
128514 #define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
128515 
128516 /*
128517  * Field : back2backsetup
128518  *
128519  * Back-to-Back SETUP Packets Received (Back2BackSETup)
128520  *
128521  * Applies to Control OUT endpoints only.
128522  *
128523  * This bit indicates that the core has received more than three
128524  *
128525  * back-to-back SETUP packets For this particular endpoint. For
128526  *
128527  * information about handling this interrupt,
128528  *
128529  * Field Enumeration Values:
128530  *
128531  * Enum | Value | Description
128532  * :---------------------------------------------|:------|:---------------------------------------
128533  * ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
128534  * ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
128535  *
128536  * Field Access Macros:
128537  *
128538  */
128539 /*
128540  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP
128541  *
128542  * No Back-to-Back SETUP Packets Received
128543  */
128544 #define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_INACT 0x0
128545 /*
128546  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP
128547  *
128548  * Back-to-Back SETUP Packets Received
128549  */
128550 #define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_ACT 0x1
128551 
128552 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */
128553 #define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_LSB 6
128554 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */
128555 #define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_MSB 6
128556 /* The width in bits of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */
128557 #define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_WIDTH 1
128558 /* The mask used to set the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field value. */
128559 #define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_SET_MSK 0x00000040
128560 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field value. */
128561 #define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_CLR_MSK 0xffffffbf
128562 /* The reset value of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */
128563 #define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_RESET 0x0
128564 /* Extracts the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP field value from a register. */
128565 #define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
128566 /* Produces a ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field value suitable for setting the register. */
128567 #define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
128568 
128569 /*
128570  * Field : outpkterr
128571  *
128572  * OUT Packet Error (OutPktErr)
128573  *
128574  * Applies to OUT endpoints Only
128575  *
128576  * This interrupt is valid only when thresholding is enabled. This interrupt is
128577  * asserted when the
128578  *
128579  * core detects an overflow or a CRC error For non-Isochronous
128580  *
128581  * OUT packet.
128582  *
128583  * Field Enumeration Values:
128584  *
128585  * Enum | Value | Description
128586  * :----------------------------------------|:------|:--------------------
128587  * ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
128588  * ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
128589  *
128590  * Field Access Macros:
128591  *
128592  */
128593 /*
128594  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTPKTERR
128595  *
128596  * No OUT Packet Error
128597  */
128598 #define ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_INACT 0x0
128599 /*
128600  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTPKTERR
128601  *
128602  * OUT Packet Error
128603  */
128604 #define ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_ACT 0x1
128605 
128606 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */
128607 #define ALT_USB_DEV_DOEPINT11_OUTPKTERR_LSB 8
128608 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */
128609 #define ALT_USB_DEV_DOEPINT11_OUTPKTERR_MSB 8
128610 /* The width in bits of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */
128611 #define ALT_USB_DEV_DOEPINT11_OUTPKTERR_WIDTH 1
128612 /* The mask used to set the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field value. */
128613 #define ALT_USB_DEV_DOEPINT11_OUTPKTERR_SET_MSK 0x00000100
128614 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field value. */
128615 #define ALT_USB_DEV_DOEPINT11_OUTPKTERR_CLR_MSK 0xfffffeff
128616 /* The reset value of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */
128617 #define ALT_USB_DEV_DOEPINT11_OUTPKTERR_RESET 0x0
128618 /* Extracts the ALT_USB_DEV_DOEPINT11_OUTPKTERR field value from a register. */
128619 #define ALT_USB_DEV_DOEPINT11_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
128620 /* Produces a ALT_USB_DEV_DOEPINT11_OUTPKTERR register field value suitable for setting the register. */
128621 #define ALT_USB_DEV_DOEPINT11_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
128622 
128623 /*
128624  * Field : bnaintr
128625  *
128626  * BNA (Buffer Not Available) Interrupt (BNAIntr)
128627  *
128628  * This bit is valid only when Scatter/Gather DMA mode is enabled.
128629  *
128630  * The core generates this interrupt when the descriptor accessed
128631  *
128632  * is not ready For the Core to process, such as Host busy or DMA
128633  *
128634  * done
128635  *
128636  * Field Enumeration Values:
128637  *
128638  * Enum | Value | Description
128639  * :--------------------------------------|:------|:--------------
128640  * ALT_USB_DEV_DOEPINT11_BNAINTR_E_INACT | 0x0 | No interrupt
128641  * ALT_USB_DEV_DOEPINT11_BNAINTR_E_ACT | 0x1 | BNA interrupt
128642  *
128643  * Field Access Macros:
128644  *
128645  */
128646 /*
128647  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BNAINTR
128648  *
128649  * No interrupt
128650  */
128651 #define ALT_USB_DEV_DOEPINT11_BNAINTR_E_INACT 0x0
128652 /*
128653  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BNAINTR
128654  *
128655  * BNA interrupt
128656  */
128657 #define ALT_USB_DEV_DOEPINT11_BNAINTR_E_ACT 0x1
128658 
128659 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */
128660 #define ALT_USB_DEV_DOEPINT11_BNAINTR_LSB 9
128661 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */
128662 #define ALT_USB_DEV_DOEPINT11_BNAINTR_MSB 9
128663 /* The width in bits of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */
128664 #define ALT_USB_DEV_DOEPINT11_BNAINTR_WIDTH 1
128665 /* The mask used to set the ALT_USB_DEV_DOEPINT11_BNAINTR register field value. */
128666 #define ALT_USB_DEV_DOEPINT11_BNAINTR_SET_MSK 0x00000200
128667 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_BNAINTR register field value. */
128668 #define ALT_USB_DEV_DOEPINT11_BNAINTR_CLR_MSK 0xfffffdff
128669 /* The reset value of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */
128670 #define ALT_USB_DEV_DOEPINT11_BNAINTR_RESET 0x0
128671 /* Extracts the ALT_USB_DEV_DOEPINT11_BNAINTR field value from a register. */
128672 #define ALT_USB_DEV_DOEPINT11_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
128673 /* Produces a ALT_USB_DEV_DOEPINT11_BNAINTR register field value suitable for setting the register. */
128674 #define ALT_USB_DEV_DOEPINT11_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
128675 
128676 /*
128677  * Field : pktdrpsts
128678  *
128679  * Packet Drop Status (PktDrpSts)
128680  *
128681  * This bit indicates to the application that an ISOC OUT packet has been dropped.
128682  * This
128683  *
128684  * bit does not have an associated mask bit and does not generate an interrupt.
128685  *
128686  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
128687  * transfer
128688  *
128689  * interrupt feature is selected.
128690  *
128691  * Field Enumeration Values:
128692  *
128693  * Enum | Value | Description
128694  * :----------------------------------------|:------|:-----------------------------
128695  * ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_INACT | 0x0 | No interrupt
128696  * ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
128697  *
128698  * Field Access Macros:
128699  *
128700  */
128701 /*
128702  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_PKTDRPSTS
128703  *
128704  * No interrupt
128705  */
128706 #define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_INACT 0x0
128707 /*
128708  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_PKTDRPSTS
128709  *
128710  * Packet Drop Status interrupt
128711  */
128712 #define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_ACT 0x1
128713 
128714 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */
128715 #define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_LSB 11
128716 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */
128717 #define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_MSB 11
128718 /* The width in bits of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */
128719 #define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_WIDTH 1
128720 /* The mask used to set the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field value. */
128721 #define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_SET_MSK 0x00000800
128722 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field value. */
128723 #define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_CLR_MSK 0xfffff7ff
128724 /* The reset value of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */
128725 #define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_RESET 0x0
128726 /* Extracts the ALT_USB_DEV_DOEPINT11_PKTDRPSTS field value from a register. */
128727 #define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
128728 /* Produces a ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field value suitable for setting the register. */
128729 #define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
128730 
128731 /*
128732  * Field : bbleerr
128733  *
128734  * NAK Interrupt (BbleErr)
128735  *
128736  * The core generates this interrupt when babble is received for the endpoint.
128737  *
128738  * Field Enumeration Values:
128739  *
128740  * Enum | Value | Description
128741  * :--------------------------------------|:------|:------------------
128742  * ALT_USB_DEV_DOEPINT11_BBLEERR_E_INACT | 0x0 | No interrupt
128743  * ALT_USB_DEV_DOEPINT11_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
128744  *
128745  * Field Access Macros:
128746  *
128747  */
128748 /*
128749  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BBLEERR
128750  *
128751  * No interrupt
128752  */
128753 #define ALT_USB_DEV_DOEPINT11_BBLEERR_E_INACT 0x0
128754 /*
128755  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_BBLEERR
128756  *
128757  * BbleErr interrupt
128758  */
128759 #define ALT_USB_DEV_DOEPINT11_BBLEERR_E_ACT 0x1
128760 
128761 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */
128762 #define ALT_USB_DEV_DOEPINT11_BBLEERR_LSB 12
128763 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */
128764 #define ALT_USB_DEV_DOEPINT11_BBLEERR_MSB 12
128765 /* The width in bits of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */
128766 #define ALT_USB_DEV_DOEPINT11_BBLEERR_WIDTH 1
128767 /* The mask used to set the ALT_USB_DEV_DOEPINT11_BBLEERR register field value. */
128768 #define ALT_USB_DEV_DOEPINT11_BBLEERR_SET_MSK 0x00001000
128769 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_BBLEERR register field value. */
128770 #define ALT_USB_DEV_DOEPINT11_BBLEERR_CLR_MSK 0xffffefff
128771 /* The reset value of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */
128772 #define ALT_USB_DEV_DOEPINT11_BBLEERR_RESET 0x0
128773 /* Extracts the ALT_USB_DEV_DOEPINT11_BBLEERR field value from a register. */
128774 #define ALT_USB_DEV_DOEPINT11_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
128775 /* Produces a ALT_USB_DEV_DOEPINT11_BBLEERR register field value suitable for setting the register. */
128776 #define ALT_USB_DEV_DOEPINT11_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
128777 
128778 /*
128779  * Field : nakintrpt
128780  *
128781  * NAK Interrupt (NAKInterrupt)
128782  *
128783  * The core generates this interrupt when a NAK is transmitted or received by the
128784  * device.
128785  *
128786  * In case of isochronous IN endpoints the interrupt gets generated when a zero
128787  * length
128788  *
128789  * packet is transmitted due to un-availability of data in the TXFifo.
128790  *
128791  * Field Enumeration Values:
128792  *
128793  * Enum | Value | Description
128794  * :----------------------------------------|:------|:--------------
128795  * ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_INACT | 0x0 | No interrupt
128796  * ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
128797  *
128798  * Field Access Macros:
128799  *
128800  */
128801 /*
128802  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_NAKINTRPT
128803  *
128804  * No interrupt
128805  */
128806 #define ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_INACT 0x0
128807 /*
128808  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_NAKINTRPT
128809  *
128810  * NAK Interrupt
128811  */
128812 #define ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_ACT 0x1
128813 
128814 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */
128815 #define ALT_USB_DEV_DOEPINT11_NAKINTRPT_LSB 13
128816 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */
128817 #define ALT_USB_DEV_DOEPINT11_NAKINTRPT_MSB 13
128818 /* The width in bits of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */
128819 #define ALT_USB_DEV_DOEPINT11_NAKINTRPT_WIDTH 1
128820 /* The mask used to set the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field value. */
128821 #define ALT_USB_DEV_DOEPINT11_NAKINTRPT_SET_MSK 0x00002000
128822 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field value. */
128823 #define ALT_USB_DEV_DOEPINT11_NAKINTRPT_CLR_MSK 0xffffdfff
128824 /* The reset value of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */
128825 #define ALT_USB_DEV_DOEPINT11_NAKINTRPT_RESET 0x0
128826 /* Extracts the ALT_USB_DEV_DOEPINT11_NAKINTRPT field value from a register. */
128827 #define ALT_USB_DEV_DOEPINT11_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
128828 /* Produces a ALT_USB_DEV_DOEPINT11_NAKINTRPT register field value suitable for setting the register. */
128829 #define ALT_USB_DEV_DOEPINT11_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
128830 
128831 /*
128832  * Field : nyetintrpt
128833  *
128834  * NYET Interrupt (NYETIntrpt)
128835  *
128836  * The core generates this interrupt when a NYET response is transmitted for a non
128837  * isochronous OUT endpoint.
128838  *
128839  * Field Enumeration Values:
128840  *
128841  * Enum | Value | Description
128842  * :-----------------------------------------|:------|:---------------
128843  * ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_INACT | 0x0 | No interrupt
128844  * ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
128845  *
128846  * Field Access Macros:
128847  *
128848  */
128849 /*
128850  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_NYETINTRPT
128851  *
128852  * No interrupt
128853  */
128854 #define ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_INACT 0x0
128855 /*
128856  * Enumerated value for register field ALT_USB_DEV_DOEPINT11_NYETINTRPT
128857  *
128858  * NYET Interrupt
128859  */
128860 #define ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_ACT 0x1
128861 
128862 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */
128863 #define ALT_USB_DEV_DOEPINT11_NYETINTRPT_LSB 14
128864 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */
128865 #define ALT_USB_DEV_DOEPINT11_NYETINTRPT_MSB 14
128866 /* The width in bits of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */
128867 #define ALT_USB_DEV_DOEPINT11_NYETINTRPT_WIDTH 1
128868 /* The mask used to set the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field value. */
128869 #define ALT_USB_DEV_DOEPINT11_NYETINTRPT_SET_MSK 0x00004000
128870 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field value. */
128871 #define ALT_USB_DEV_DOEPINT11_NYETINTRPT_CLR_MSK 0xffffbfff
128872 /* The reset value of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */
128873 #define ALT_USB_DEV_DOEPINT11_NYETINTRPT_RESET 0x0
128874 /* Extracts the ALT_USB_DEV_DOEPINT11_NYETINTRPT field value from a register. */
128875 #define ALT_USB_DEV_DOEPINT11_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
128876 /* Produces a ALT_USB_DEV_DOEPINT11_NYETINTRPT register field value suitable for setting the register. */
128877 #define ALT_USB_DEV_DOEPINT11_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
128878 
128879 /*
128880  * Field : stuppktrcvd
128881  *
128882  * Setup Packet Received
128883  *
128884  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
128885  *
128886  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
128887  *
128888  * setup data. There is only one Setup packet per buffer. On receiving a
128889  *
128890  * Setup packet, the DWC_otg core closes the buffer and disables the
128891  *
128892  * corresponding endpoint. The application has to re-enable the endpoint to
128893  *
128894  * receive any OUT data for the Control Transfer and reprogram the buffer
128895  *
128896  * start address.
128897  *
128898  * Note: Because of the above behavior, the DWC_otg core can receive any
128899  *
128900  * number of back to back setup packets and one buffer for every setup
128901  *
128902  * packet is used.
128903  *
128904  * 1'b0: No Setup packet received
128905  *
128906  * 1'b1: Setup packet received
128907  *
128908  * Reset: 1'b0
128909  *
128910  * Field Access Macros:
128911  *
128912  */
128913 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field. */
128914 #define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_LSB 15
128915 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field. */
128916 #define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_MSB 15
128917 /* The width in bits of the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field. */
128918 #define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_WIDTH 1
128919 /* The mask used to set the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field value. */
128920 #define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_SET_MSK 0x00008000
128921 /* The mask used to clear the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field value. */
128922 #define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_CLR_MSK 0xffff7fff
128923 /* The reset value of the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field. */
128924 #define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_RESET 0x0
128925 /* Extracts the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD field value from a register. */
128926 #define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
128927 /* Produces a ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field value suitable for setting the register. */
128928 #define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
128929 
128930 #ifndef __ASSEMBLY__
128931 /*
128932  * WARNING: The C register and register group struct declarations are provided for
128933  * convenience and illustrative purposes. They should, however, be used with
128934  * caution as the C language standard provides no guarantees about the alignment or
128935  * atomicity of device memory accesses. The recommended practice for writing
128936  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
128937  * alt_write_word() functions.
128938  *
128939  * The struct declaration for register ALT_USB_DEV_DOEPINT11.
128940  */
128941 struct ALT_USB_DEV_DOEPINT11_s
128942 {
128943  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT11_XFERCOMPL */
128944  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT11_EPDISBLD */
128945  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT11_AHBERR */
128946  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT11_SETUP */
128947  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS */
128948  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT11_STSPHSERCVD */
128949  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP */
128950  uint32_t : 1; /* *UNDEFINED* */
128951  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT11_OUTPKTERR */
128952  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT11_BNAINTR */
128953  uint32_t : 1; /* *UNDEFINED* */
128954  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT11_PKTDRPSTS */
128955  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT11_BBLEERR */
128956  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT11_NAKINTRPT */
128957  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT11_NYETINTRPT */
128958  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT11_STUPPKTRCVD */
128959  uint32_t : 16; /* *UNDEFINED* */
128960 };
128961 
128962 /* The typedef declaration for register ALT_USB_DEV_DOEPINT11. */
128963 typedef volatile struct ALT_USB_DEV_DOEPINT11_s ALT_USB_DEV_DOEPINT11_t;
128964 #endif /* __ASSEMBLY__ */
128965 
128966 /* The reset value of the ALT_USB_DEV_DOEPINT11 register. */
128967 #define ALT_USB_DEV_DOEPINT11_RESET 0x00000000
128968 /* The byte offset of the ALT_USB_DEV_DOEPINT11 register from the beginning of the component. */
128969 #define ALT_USB_DEV_DOEPINT11_OFST 0x468
128970 /* The address of the ALT_USB_DEV_DOEPINT11 register. */
128971 #define ALT_USB_DEV_DOEPINT11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT11_OFST))
128972 
128973 /*
128974  * Register : doeptsiz11
128975  *
128976  * Device OUT Endpoint 11 Transfer Size Register
128977  *
128978  * Register Layout
128979  *
128980  * Bits | Access | Reset | Description
128981  * :--------|:-------|:------|:--------------------------------
128982  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ11_XFERSIZE
128983  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ11_PKTCNT
128984  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ11_RXDPID
128985  * [31] | ??? | 0x0 | *UNDEFINED*
128986  *
128987  */
128988 /*
128989  * Field : xfersize
128990  *
128991  * Transfer Size (XferSize)
128992  *
128993  * Indicates the transfer size in bytes For endpoint 0. The core
128994  *
128995  * interrupts the application only after it has exhausted the transfer
128996  *
128997  * size amount of data. The transfer size can be Set to the
128998  *
128999  * maximum packet size of the endpoint, to be interrupted at the
129000  *
129001  * end of each packet.
129002  *
129003  * The core decrements this field every time a packet is read from
129004  *
129005  * the RxFIFO and written to the external memory.
129006  *
129007  * Field Access Macros:
129008  *
129009  */
129010 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */
129011 #define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_LSB 0
129012 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */
129013 #define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_MSB 18
129014 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */
129015 #define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_WIDTH 19
129016 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field value. */
129017 #define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_SET_MSK 0x0007ffff
129018 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field value. */
129019 #define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_CLR_MSK 0xfff80000
129020 /* The reset value of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */
129021 #define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_RESET 0x0
129022 /* Extracts the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE field value from a register. */
129023 #define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
129024 /* Produces a ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field value suitable for setting the register. */
129025 #define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
129026 
129027 /*
129028  * Field : pktcnt
129029  *
129030  * Packet Count (PktCnt)
129031  *
129032  * This field is decremented to zero after a packet is written into the
129033  *
129034  * RxFIFO.
129035  *
129036  * Field Access Macros:
129037  *
129038  */
129039 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */
129040 #define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_LSB 19
129041 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */
129042 #define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_MSB 28
129043 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */
129044 #define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_WIDTH 10
129045 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field value. */
129046 #define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_SET_MSK 0x1ff80000
129047 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field value. */
129048 #define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_CLR_MSK 0xe007ffff
129049 /* The reset value of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */
129050 #define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_RESET 0x0
129051 /* Extracts the ALT_USB_DEV_DOEPTSIZ11_PKTCNT field value from a register. */
129052 #define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
129053 /* Produces a ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field value suitable for setting the register. */
129054 #define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
129055 
129056 /*
129057  * Field : rxdpid
129058  *
129059  * Applies to isochronous OUT endpoints only.
129060  *
129061  * This is the data PID received in the last packet for this endpoint.
129062  *
129063  * 2'b00: DATA0
129064  *
129065  * 2'b01: DATA2
129066  *
129067  * 2'b10: DATA1
129068  *
129069  * 2'b11: MDATA
129070  *
129071  * SETUP Packet Count (SUPCnt)
129072  *
129073  * Applies to control OUT Endpoints only.
129074  *
129075  * This field specifies the number of back-to-back SETUP data
129076  *
129077  * packets the endpoint can receive.
129078  *
129079  * 2'b01: 1 packet
129080  *
129081  * 2'b10: 2 packets
129082  *
129083  * 2'b11: 3 packets
129084  *
129085  * Field Enumeration Values:
129086  *
129087  * Enum | Value | Description
129088  * :------------------------------------------|:------|:-------------------
129089  * ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA0 | 0x0 | DATA0
129090  * ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
129091  * ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
129092  * ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
129093  *
129094  * Field Access Macros:
129095  *
129096  */
129097 /*
129098  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID
129099  *
129100  * DATA0
129101  */
129102 #define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA0 0x0
129103 /*
129104  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID
129105  *
129106  * DATA2 or 1 packet
129107  */
129108 #define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA2PKT1 0x1
129109 /*
129110  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID
129111  *
129112  * DATA1 or 2 packets
129113  */
129114 #define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA1PKT2 0x2
129115 /*
129116  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID
129117  *
129118  * MDATA or 3 packets
129119  */
129120 #define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_MDATAPKT3 0x3
129121 
129122 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */
129123 #define ALT_USB_DEV_DOEPTSIZ11_RXDPID_LSB 29
129124 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */
129125 #define ALT_USB_DEV_DOEPTSIZ11_RXDPID_MSB 30
129126 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */
129127 #define ALT_USB_DEV_DOEPTSIZ11_RXDPID_WIDTH 2
129128 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field value. */
129129 #define ALT_USB_DEV_DOEPTSIZ11_RXDPID_SET_MSK 0x60000000
129130 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field value. */
129131 #define ALT_USB_DEV_DOEPTSIZ11_RXDPID_CLR_MSK 0x9fffffff
129132 /* The reset value of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */
129133 #define ALT_USB_DEV_DOEPTSIZ11_RXDPID_RESET 0x0
129134 /* Extracts the ALT_USB_DEV_DOEPTSIZ11_RXDPID field value from a register. */
129135 #define ALT_USB_DEV_DOEPTSIZ11_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
129136 /* Produces a ALT_USB_DEV_DOEPTSIZ11_RXDPID register field value suitable for setting the register. */
129137 #define ALT_USB_DEV_DOEPTSIZ11_RXDPID_SET(value) (((value) << 29) & 0x60000000)
129138 
129139 #ifndef __ASSEMBLY__
129140 /*
129141  * WARNING: The C register and register group struct declarations are provided for
129142  * convenience and illustrative purposes. They should, however, be used with
129143  * caution as the C language standard provides no guarantees about the alignment or
129144  * atomicity of device memory accesses. The recommended practice for writing
129145  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
129146  * alt_write_word() functions.
129147  *
129148  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ11.
129149  */
129150 struct ALT_USB_DEV_DOEPTSIZ11_s
129151 {
129152  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ11_XFERSIZE */
129153  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ11_PKTCNT */
129154  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ11_RXDPID */
129155  uint32_t : 1; /* *UNDEFINED* */
129156 };
129157 
129158 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ11. */
129159 typedef volatile struct ALT_USB_DEV_DOEPTSIZ11_s ALT_USB_DEV_DOEPTSIZ11_t;
129160 #endif /* __ASSEMBLY__ */
129161 
129162 /* The reset value of the ALT_USB_DEV_DOEPTSIZ11 register. */
129163 #define ALT_USB_DEV_DOEPTSIZ11_RESET 0x00000000
129164 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ11 register from the beginning of the component. */
129165 #define ALT_USB_DEV_DOEPTSIZ11_OFST 0x470
129166 /* The address of the ALT_USB_DEV_DOEPTSIZ11 register. */
129167 #define ALT_USB_DEV_DOEPTSIZ11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ11_OFST))
129168 
129169 /*
129170  * Register : doepdma11
129171  *
129172  * Device OUT Endpoint 11 DMA Address Register
129173  *
129174  * Register Layout
129175  *
129176  * Bits | Access | Reset | Description
129177  * :-------|:-------|:--------|:--------------------------------
129178  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA11_DOEPDMA11
129179  *
129180  */
129181 /*
129182  * Field : doepdma11
129183  *
129184  * Holds the start address of the external memory for storing or fetching endpoint
129185  *
129186  * data.
129187  *
129188  * Note: For control endpoints, this field stores control OUT data packets as well
129189  * as
129190  *
129191  * SETUP transaction data packets. When more than three SETUP packets are
129192  *
129193  * received back-to-back, the SETUP data packet in the memory is overwritten.
129194  *
129195  * This register is incremented on every AHB transaction. The application can give
129196  *
129197  * only a DWORD-aligned address.
129198  *
129199  * When Scatter/Gather DMA mode is not enabled, the application programs the
129200  *
129201  * start address value in this field.
129202  *
129203  * When Scatter/Gather DMA mode is enabled, this field indicates the base
129204  *
129205  * pointer for the descriptor list.
129206  *
129207  * Field Access Macros:
129208  *
129209  */
129210 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field. */
129211 #define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_LSB 0
129212 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field. */
129213 #define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_MSB 31
129214 /* The width in bits of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field. */
129215 #define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_WIDTH 32
129216 /* The mask used to set the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field value. */
129217 #define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_SET_MSK 0xffffffff
129218 /* The mask used to clear the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field value. */
129219 #define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_CLR_MSK 0x00000000
129220 /* The reset value of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field is UNKNOWN. */
129221 #define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_RESET 0x0
129222 /* Extracts the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 field value from a register. */
129223 #define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_GET(value) (((value) & 0xffffffff) >> 0)
129224 /* Produces a ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field value suitable for setting the register. */
129225 #define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_SET(value) (((value) << 0) & 0xffffffff)
129226 
129227 #ifndef __ASSEMBLY__
129228 /*
129229  * WARNING: The C register and register group struct declarations are provided for
129230  * convenience and illustrative purposes. They should, however, be used with
129231  * caution as the C language standard provides no guarantees about the alignment or
129232  * atomicity of device memory accesses. The recommended practice for writing
129233  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
129234  * alt_write_word() functions.
129235  *
129236  * The struct declaration for register ALT_USB_DEV_DOEPDMA11.
129237  */
129238 struct ALT_USB_DEV_DOEPDMA11_s
129239 {
129240  uint32_t doepdma11 : 32; /* ALT_USB_DEV_DOEPDMA11_DOEPDMA11 */
129241 };
129242 
129243 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA11. */
129244 typedef volatile struct ALT_USB_DEV_DOEPDMA11_s ALT_USB_DEV_DOEPDMA11_t;
129245 #endif /* __ASSEMBLY__ */
129246 
129247 /* The reset value of the ALT_USB_DEV_DOEPDMA11 register. */
129248 #define ALT_USB_DEV_DOEPDMA11_RESET 0x00000000
129249 /* The byte offset of the ALT_USB_DEV_DOEPDMA11 register from the beginning of the component. */
129250 #define ALT_USB_DEV_DOEPDMA11_OFST 0x474
129251 /* The address of the ALT_USB_DEV_DOEPDMA11 register. */
129252 #define ALT_USB_DEV_DOEPDMA11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA11_OFST))
129253 
129254 /*
129255  * Register : doepdmab11
129256  *
129257  * Device OUT Endpoint 11 Buffer Address Register
129258  *
129259  * Register Layout
129260  *
129261  * Bits | Access | Reset | Description
129262  * :-------|:-------|:--------|:----------------------------------
129263  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11
129264  *
129265  */
129266 /*
129267  * Field : doepdmab11
129268  *
129269  * Holds the current buffer address.This register is updated as and when the data
129270  *
129271  * transfer for the corresponding end point is in progress.
129272  *
129273  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
129274  * is
129275  *
129276  * reserved.
129277  *
129278  * Field Access Macros:
129279  *
129280  */
129281 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field. */
129282 #define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_LSB 0
129283 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field. */
129284 #define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_MSB 31
129285 /* The width in bits of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field. */
129286 #define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_WIDTH 32
129287 /* The mask used to set the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field value. */
129288 #define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_SET_MSK 0xffffffff
129289 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field value. */
129290 #define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_CLR_MSK 0x00000000
129291 /* The reset value of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field is UNKNOWN. */
129292 #define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_RESET 0x0
129293 /* Extracts the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 field value from a register. */
129294 #define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_GET(value) (((value) & 0xffffffff) >> 0)
129295 /* Produces a ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field value suitable for setting the register. */
129296 #define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_SET(value) (((value) << 0) & 0xffffffff)
129297 
129298 #ifndef __ASSEMBLY__
129299 /*
129300  * WARNING: The C register and register group struct declarations are provided for
129301  * convenience and illustrative purposes. They should, however, be used with
129302  * caution as the C language standard provides no guarantees about the alignment or
129303  * atomicity of device memory accesses. The recommended practice for writing
129304  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
129305  * alt_write_word() functions.
129306  *
129307  * The struct declaration for register ALT_USB_DEV_DOEPDMAB11.
129308  */
129309 struct ALT_USB_DEV_DOEPDMAB11_s
129310 {
129311  const uint32_t doepdmab11 : 32; /* ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 */
129312 };
129313 
129314 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB11. */
129315 typedef volatile struct ALT_USB_DEV_DOEPDMAB11_s ALT_USB_DEV_DOEPDMAB11_t;
129316 #endif /* __ASSEMBLY__ */
129317 
129318 /* The reset value of the ALT_USB_DEV_DOEPDMAB11 register. */
129319 #define ALT_USB_DEV_DOEPDMAB11_RESET 0x00000000
129320 /* The byte offset of the ALT_USB_DEV_DOEPDMAB11 register from the beginning of the component. */
129321 #define ALT_USB_DEV_DOEPDMAB11_OFST 0x47c
129322 /* The address of the ALT_USB_DEV_DOEPDMAB11 register. */
129323 #define ALT_USB_DEV_DOEPDMAB11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB11_OFST))
129324 
129325 /*
129326  * Register : doepctl12
129327  *
129328  * Device Control OUT Endpoint 12 Control Register
129329  *
129330  * Register Layout
129331  *
129332  * Bits | Access | Reset | Description
129333  * :--------|:---------|:------|:-------------------------------
129334  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL12_MPS
129335  * [14:11] | ??? | 0x0 | *UNDEFINED*
129336  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL12_USBACTEP
129337  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL12_DPID
129338  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL12_NAKSTS
129339  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL12_EPTYPE
129340  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL12_SNP
129341  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL12_STALL
129342  * [25:22] | ??? | 0x0 | *UNDEFINED*
129343  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL12_CNAK
129344  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL12_SNAK
129345  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL12_SETD0PID
129346  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL12_SETD1PID
129347  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL12_EPDIS
129348  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL12_EPENA
129349  *
129350  */
129351 /*
129352  * Field : mps
129353  *
129354  * Maximum Packet Size (MPS)
129355  *
129356  * The application must program this field with the maximum packet size for the
129357  * current
129358  *
129359  * logical endpoint. This value is in bytes.
129360  *
129361  * Field Access Macros:
129362  *
129363  */
129364 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_MPS register field. */
129365 #define ALT_USB_DEV_DOEPCTL12_MPS_LSB 0
129366 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_MPS register field. */
129367 #define ALT_USB_DEV_DOEPCTL12_MPS_MSB 10
129368 /* The width in bits of the ALT_USB_DEV_DOEPCTL12_MPS register field. */
129369 #define ALT_USB_DEV_DOEPCTL12_MPS_WIDTH 11
129370 /* The mask used to set the ALT_USB_DEV_DOEPCTL12_MPS register field value. */
129371 #define ALT_USB_DEV_DOEPCTL12_MPS_SET_MSK 0x000007ff
129372 /* The mask used to clear the ALT_USB_DEV_DOEPCTL12_MPS register field value. */
129373 #define ALT_USB_DEV_DOEPCTL12_MPS_CLR_MSK 0xfffff800
129374 /* The reset value of the ALT_USB_DEV_DOEPCTL12_MPS register field. */
129375 #define ALT_USB_DEV_DOEPCTL12_MPS_RESET 0x0
129376 /* Extracts the ALT_USB_DEV_DOEPCTL12_MPS field value from a register. */
129377 #define ALT_USB_DEV_DOEPCTL12_MPS_GET(value) (((value) & 0x000007ff) >> 0)
129378 /* Produces a ALT_USB_DEV_DOEPCTL12_MPS register field value suitable for setting the register. */
129379 #define ALT_USB_DEV_DOEPCTL12_MPS_SET(value) (((value) << 0) & 0x000007ff)
129380 
129381 /*
129382  * Field : usbactep
129383  *
129384  * USB Active Endpoint (USBActEP)
129385  *
129386  * Indicates whether this endpoint is active in the current configuration and
129387  * interface. The
129388  *
129389  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
129390  * reset. After
129391  *
129392  * receiving the SetConfiguration and SetInterface commands, the application must
129393  *
129394  * program endpoint registers accordingly and set this bit.
129395  *
129396  * Field Enumeration Values:
129397  *
129398  * Enum | Value | Description
129399  * :--------------------------------------|:------|:--------------------
129400  * ALT_USB_DEV_DOEPCTL12_USBACTEP_E_DISD | 0x0 | Not Active
129401  * ALT_USB_DEV_DOEPCTL12_USBACTEP_E_END | 0x1 | USB Active Endpoint
129402  *
129403  * Field Access Macros:
129404  *
129405  */
129406 /*
129407  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_USBACTEP
129408  *
129409  * Not Active
129410  */
129411 #define ALT_USB_DEV_DOEPCTL12_USBACTEP_E_DISD 0x0
129412 /*
129413  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_USBACTEP
129414  *
129415  * USB Active Endpoint
129416  */
129417 #define ALT_USB_DEV_DOEPCTL12_USBACTEP_E_END 0x1
129418 
129419 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */
129420 #define ALT_USB_DEV_DOEPCTL12_USBACTEP_LSB 15
129421 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */
129422 #define ALT_USB_DEV_DOEPCTL12_USBACTEP_MSB 15
129423 /* The width in bits of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */
129424 #define ALT_USB_DEV_DOEPCTL12_USBACTEP_WIDTH 1
129425 /* The mask used to set the ALT_USB_DEV_DOEPCTL12_USBACTEP register field value. */
129426 #define ALT_USB_DEV_DOEPCTL12_USBACTEP_SET_MSK 0x00008000
129427 /* The mask used to clear the ALT_USB_DEV_DOEPCTL12_USBACTEP register field value. */
129428 #define ALT_USB_DEV_DOEPCTL12_USBACTEP_CLR_MSK 0xffff7fff
129429 /* The reset value of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */
129430 #define ALT_USB_DEV_DOEPCTL12_USBACTEP_RESET 0x0
129431 /* Extracts the ALT_USB_DEV_DOEPCTL12_USBACTEP field value from a register. */
129432 #define ALT_USB_DEV_DOEPCTL12_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
129433 /* Produces a ALT_USB_DEV_DOEPCTL12_USBACTEP register field value suitable for setting the register. */
129434 #define ALT_USB_DEV_DOEPCTL12_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
129435 
129436 /*
129437  * Field : dpid
129438  *
129439  * Endpoint Data PID (DPID)
129440  *
129441  * Applies to interrupt/bulk IN and OUT endpoints only.
129442  *
129443  * Contains the PID of the packet to be received or transmitted on this endpoint.
129444  * The
129445  *
129446  * application must program the PID of the first packet to be received or
129447  * transmitted on
129448  *
129449  * this endpoint, after the endpoint is activated. The applications use the
129450  * SetD1PID and
129451  *
129452  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
129453  *
129454  * 1'b0: DATA0
129455  *
129456  * 1'b1: DATA1
129457  *
129458  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
129459  *
129460  * DMA mode.
129461  *
129462  * 1'b0 RO
129463  *
129464  * Even/Odd (Micro)Frame (EO_FrNum)
129465  *
129466  * In non-Scatter/Gather DMA mode:
129467  *
129468  * Applies to isochronous IN and OUT endpoints only.
129469  *
129470  * Indicates the (micro)frame number in which the core transmits/receives
129471  * isochronous
129472  *
129473  * data for this endpoint. The application must program the even/odd (micro) frame
129474  *
129475  * number in which it intends to transmit/receive isochronous data for this
129476  * endpoint using
129477  *
129478  * the SetEvnFr and SetOddFr fields in this register.
129479  *
129480  * 1'b0: Even (micro)frame
129481  *
129482  * 1'b1: Odd (micro)frame
129483  *
129484  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
129485  * number
129486  *
129487  * in which to send data is provided in the transmit descriptor structure. The
129488  * frame in
129489  *
129490  * which data is received is updated in receive descriptor structure.
129491  *
129492  * Field Enumeration Values:
129493  *
129494  * Enum | Value | Description
129495  * :-----------------------------------|:------|:-----------------------------
129496  * ALT_USB_DEV_DOEPCTL12_DPID_E_INACT | 0x0 | Endpoint Data PID not active
129497  * ALT_USB_DEV_DOEPCTL12_DPID_E_ACT | 0x1 | Endpoint Data PID active
129498  *
129499  * Field Access Macros:
129500  *
129501  */
129502 /*
129503  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_DPID
129504  *
129505  * Endpoint Data PID not active
129506  */
129507 #define ALT_USB_DEV_DOEPCTL12_DPID_E_INACT 0x0
129508 /*
129509  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_DPID
129510  *
129511  * Endpoint Data PID active
129512  */
129513 #define ALT_USB_DEV_DOEPCTL12_DPID_E_ACT 0x1
129514 
129515 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_DPID register field. */
129516 #define ALT_USB_DEV_DOEPCTL12_DPID_LSB 16
129517 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_DPID register field. */
129518 #define ALT_USB_DEV_DOEPCTL12_DPID_MSB 16
129519 /* The width in bits of the ALT_USB_DEV_DOEPCTL12_DPID register field. */
129520 #define ALT_USB_DEV_DOEPCTL12_DPID_WIDTH 1
129521 /* The mask used to set the ALT_USB_DEV_DOEPCTL12_DPID register field value. */
129522 #define ALT_USB_DEV_DOEPCTL12_DPID_SET_MSK 0x00010000
129523 /* The mask used to clear the ALT_USB_DEV_DOEPCTL12_DPID register field value. */
129524 #define ALT_USB_DEV_DOEPCTL12_DPID_CLR_MSK 0xfffeffff
129525 /* The reset value of the ALT_USB_DEV_DOEPCTL12_DPID register field. */
129526 #define ALT_USB_DEV_DOEPCTL12_DPID_RESET 0x0
129527 /* Extracts the ALT_USB_DEV_DOEPCTL12_DPID field value from a register. */
129528 #define ALT_USB_DEV_DOEPCTL12_DPID_GET(value) (((value) & 0x00010000) >> 16)
129529 /* Produces a ALT_USB_DEV_DOEPCTL12_DPID register field value suitable for setting the register. */
129530 #define ALT_USB_DEV_DOEPCTL12_DPID_SET(value) (((value) << 16) & 0x00010000)
129531 
129532 /*
129533  * Field : naksts
129534  *
129535  * NAK Status (NAKSts)
129536  *
129537  * Indicates the following:
129538  *
129539  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
129540  *
129541  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
129542  *
129543  * When either the application or the core sets this bit:
129544  *
129545  * The core stops receiving any data on an OUT endpoint, even if there is space in
129546  *
129547  * the RxFIFO to accommodate the incoming packet.
129548  *
129549  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
129550  *
129551  * endpoint, even if there data is available in the TxFIFO.
129552  *
129553  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
129554  *
129555  * if there data is available in the TxFIFO.
129556  *
129557  * Irrespective of this bit's setting, the core always responds to SETUP data
129558  * packets with
129559  *
129560  * an ACK handshake.
129561  *
129562  * Field Enumeration Values:
129563  *
129564  * Enum | Value | Description
129565  * :--------------------------------------|:------|:------------------------------------------------
129566  * ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
129567  * : | | based on the FIFO status
129568  * ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
129569  * : | | endpoint
129570  *
129571  * Field Access Macros:
129572  *
129573  */
129574 /*
129575  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_NAKSTS
129576  *
129577  * The core is transmitting non-NAK handshakes based on the FIFO status
129578  */
129579 #define ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NONNAK 0x0
129580 /*
129581  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_NAKSTS
129582  *
129583  * The core is transmitting NAK handshakes on this endpoint
129584  */
129585 #define ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NAK 0x1
129586 
129587 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */
129588 #define ALT_USB_DEV_DOEPCTL12_NAKSTS_LSB 17
129589 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */
129590 #define ALT_USB_DEV_DOEPCTL12_NAKSTS_MSB 17
129591 /* The width in bits of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */
129592 #define ALT_USB_DEV_DOEPCTL12_NAKSTS_WIDTH 1
129593 /* The mask used to set the ALT_USB_DEV_DOEPCTL12_NAKSTS register field value. */
129594 #define ALT_USB_DEV_DOEPCTL12_NAKSTS_SET_MSK 0x00020000
129595 /* The mask used to clear the ALT_USB_DEV_DOEPCTL12_NAKSTS register field value. */
129596 #define ALT_USB_DEV_DOEPCTL12_NAKSTS_CLR_MSK 0xfffdffff
129597 /* The reset value of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */
129598 #define ALT_USB_DEV_DOEPCTL12_NAKSTS_RESET 0x0
129599 /* Extracts the ALT_USB_DEV_DOEPCTL12_NAKSTS field value from a register. */
129600 #define ALT_USB_DEV_DOEPCTL12_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
129601 /* Produces a ALT_USB_DEV_DOEPCTL12_NAKSTS register field value suitable for setting the register. */
129602 #define ALT_USB_DEV_DOEPCTL12_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
129603 
129604 /*
129605  * Field : eptype
129606  *
129607  * Endpoint Type (EPType)
129608  *
129609  * This is the transfer type supported by this logical endpoint.
129610  *
129611  * 2'b00: Control
129612  *
129613  * 2'b01: Isochronous
129614  *
129615  * 2'b10: Bulk
129616  *
129617  * 2'b11: Interrupt
129618  *
129619  * Field Enumeration Values:
129620  *
129621  * Enum | Value | Description
129622  * :-------------------------------------------|:------|:------------
129623  * ALT_USB_DEV_DOEPCTL12_EPTYPE_E_CTL | 0x0 | Control
129624  * ALT_USB_DEV_DOEPCTL12_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
129625  * ALT_USB_DEV_DOEPCTL12_EPTYPE_E_BULK | 0x2 | Bulk
129626  * ALT_USB_DEV_DOEPCTL12_EPTYPE_E_INTERRUP | 0x3 | Interrupt
129627  *
129628  * Field Access Macros:
129629  *
129630  */
129631 /*
129632  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE
129633  *
129634  * Control
129635  */
129636 #define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_CTL 0x0
129637 /*
129638  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE
129639  *
129640  * Isochronous
129641  */
129642 #define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_ISOCHRONOUS 0x1
129643 /*
129644  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE
129645  *
129646  * Bulk
129647  */
129648 #define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_BULK 0x2
129649 /*
129650  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE
129651  *
129652  * Interrupt
129653  */
129654 #define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_INTERRUP 0x3
129655 
129656 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */
129657 #define ALT_USB_DEV_DOEPCTL12_EPTYPE_LSB 18
129658 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */
129659 #define ALT_USB_DEV_DOEPCTL12_EPTYPE_MSB 19
129660 /* The width in bits of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */
129661 #define ALT_USB_DEV_DOEPCTL12_EPTYPE_WIDTH 2
129662 /* The mask used to set the ALT_USB_DEV_DOEPCTL12_EPTYPE register field value. */
129663 #define ALT_USB_DEV_DOEPCTL12_EPTYPE_SET_MSK 0x000c0000
129664 /* The mask used to clear the ALT_USB_DEV_DOEPCTL12_EPTYPE register field value. */
129665 #define ALT_USB_DEV_DOEPCTL12_EPTYPE_CLR_MSK 0xfff3ffff
129666 /* The reset value of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */
129667 #define ALT_USB_DEV_DOEPCTL12_EPTYPE_RESET 0x0
129668 /* Extracts the ALT_USB_DEV_DOEPCTL12_EPTYPE field value from a register. */
129669 #define ALT_USB_DEV_DOEPCTL12_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
129670 /* Produces a ALT_USB_DEV_DOEPCTL12_EPTYPE register field value suitable for setting the register. */
129671 #define ALT_USB_DEV_DOEPCTL12_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
129672 
129673 /*
129674  * Field : snp
129675  *
129676  * Snoop Mode (Snp)
129677  *
129678  * Applies to OUT endpoints only.
129679  *
129680  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
129681  *
129682  * check the correctness of OUT packets before transferring them to application
129683  * memory.
129684  *
129685  * Field Enumeration Values:
129686  *
129687  * Enum | Value | Description
129688  * :--------------------------------|:------|:-------------------
129689  * ALT_USB_DEV_DOEPCTL12_SNP_E_DIS | 0x0 | Disable Snoop Mode
129690  * ALT_USB_DEV_DOEPCTL12_SNP_E_EN | 0x1 | Enable Snoop Mode
129691  *
129692  * Field Access Macros:
129693  *
129694  */
129695 /*
129696  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNP
129697  *
129698  * Disable Snoop Mode
129699  */
129700 #define ALT_USB_DEV_DOEPCTL12_SNP_E_DIS 0x0
129701 /*
129702  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNP
129703  *
129704  * Enable Snoop Mode
129705  */
129706 #define ALT_USB_DEV_DOEPCTL12_SNP_E_EN 0x1
129707 
129708 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SNP register field. */
129709 #define ALT_USB_DEV_DOEPCTL12_SNP_LSB 20
129710 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SNP register field. */
129711 #define ALT_USB_DEV_DOEPCTL12_SNP_MSB 20
129712 /* The width in bits of the ALT_USB_DEV_DOEPCTL12_SNP register field. */
129713 #define ALT_USB_DEV_DOEPCTL12_SNP_WIDTH 1
129714 /* The mask used to set the ALT_USB_DEV_DOEPCTL12_SNP register field value. */
129715 #define ALT_USB_DEV_DOEPCTL12_SNP_SET_MSK 0x00100000
129716 /* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SNP register field value. */
129717 #define ALT_USB_DEV_DOEPCTL12_SNP_CLR_MSK 0xffefffff
129718 /* The reset value of the ALT_USB_DEV_DOEPCTL12_SNP register field. */
129719 #define ALT_USB_DEV_DOEPCTL12_SNP_RESET 0x0
129720 /* Extracts the ALT_USB_DEV_DOEPCTL12_SNP field value from a register. */
129721 #define ALT_USB_DEV_DOEPCTL12_SNP_GET(value) (((value) & 0x00100000) >> 20)
129722 /* Produces a ALT_USB_DEV_DOEPCTL12_SNP register field value suitable for setting the register. */
129723 #define ALT_USB_DEV_DOEPCTL12_SNP_SET(value) (((value) << 20) & 0x00100000)
129724 
129725 /*
129726  * Field : stall
129727  *
129728  * STALL Handshake (Stall)
129729  *
129730  * Applies to non-control, non-isochronous IN and OUT endpoints only.
129731  *
129732  * The application sets this bit to stall all tokens from the USB host to this
129733  * endpoint. If a
129734  *
129735  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
129736  * bit, the
129737  *
129738  * STALL bit takes priority. Only the application can clear this bit, never the
129739  * core.
129740  *
129741  * 1'b0 R_W
129742  *
129743  * Applies to control endpoints only.
129744  *
129745  * The application can only set this bit, and the core clears it, when a SETUP
129746  * token is
129747  *
129748  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
129749  * OUT
129750  *
129751  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
129752  * this bit's
129753  *
129754  * setting, the core always responds to SETUP data packets with an ACK handshake.
129755  *
129756  * Field Enumeration Values:
129757  *
129758  * Enum | Value | Description
129759  * :------------------------------------|:------|:----------------------------
129760  * ALT_USB_DEV_DOEPCTL12_STALL_E_INACT | 0x0 | STALL All Tokens not active
129761  * ALT_USB_DEV_DOEPCTL12_STALL_E_ACT | 0x1 | STALL All Tokens active
129762  *
129763  * Field Access Macros:
129764  *
129765  */
129766 /*
129767  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_STALL
129768  *
129769  * STALL All Tokens not active
129770  */
129771 #define ALT_USB_DEV_DOEPCTL12_STALL_E_INACT 0x0
129772 /*
129773  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_STALL
129774  *
129775  * STALL All Tokens active
129776  */
129777 #define ALT_USB_DEV_DOEPCTL12_STALL_E_ACT 0x1
129778 
129779 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_STALL register field. */
129780 #define ALT_USB_DEV_DOEPCTL12_STALL_LSB 21
129781 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_STALL register field. */
129782 #define ALT_USB_DEV_DOEPCTL12_STALL_MSB 21
129783 /* The width in bits of the ALT_USB_DEV_DOEPCTL12_STALL register field. */
129784 #define ALT_USB_DEV_DOEPCTL12_STALL_WIDTH 1
129785 /* The mask used to set the ALT_USB_DEV_DOEPCTL12_STALL register field value. */
129786 #define ALT_USB_DEV_DOEPCTL12_STALL_SET_MSK 0x00200000
129787 /* The mask used to clear the ALT_USB_DEV_DOEPCTL12_STALL register field value. */
129788 #define ALT_USB_DEV_DOEPCTL12_STALL_CLR_MSK 0xffdfffff
129789 /* The reset value of the ALT_USB_DEV_DOEPCTL12_STALL register field. */
129790 #define ALT_USB_DEV_DOEPCTL12_STALL_RESET 0x0
129791 /* Extracts the ALT_USB_DEV_DOEPCTL12_STALL field value from a register. */
129792 #define ALT_USB_DEV_DOEPCTL12_STALL_GET(value) (((value) & 0x00200000) >> 21)
129793 /* Produces a ALT_USB_DEV_DOEPCTL12_STALL register field value suitable for setting the register. */
129794 #define ALT_USB_DEV_DOEPCTL12_STALL_SET(value) (((value) << 21) & 0x00200000)
129795 
129796 /*
129797  * Field : cnak
129798  *
129799  * Clear NAK (CNAK)
129800  *
129801  * A write to this bit clears the NAK bit For the endpoint.
129802  *
129803  * Field Enumeration Values:
129804  *
129805  * Enum | Value | Description
129806  * :-----------------------------------|:------|:-------------
129807  * ALT_USB_DEV_DOEPCTL12_CNAK_E_INACT | 0x0 | No Clear NAK
129808  * ALT_USB_DEV_DOEPCTL12_CNAK_E_ACT | 0x1 | Clear NAK
129809  *
129810  * Field Access Macros:
129811  *
129812  */
129813 /*
129814  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_CNAK
129815  *
129816  * No Clear NAK
129817  */
129818 #define ALT_USB_DEV_DOEPCTL12_CNAK_E_INACT 0x0
129819 /*
129820  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_CNAK
129821  *
129822  * Clear NAK
129823  */
129824 #define ALT_USB_DEV_DOEPCTL12_CNAK_E_ACT 0x1
129825 
129826 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */
129827 #define ALT_USB_DEV_DOEPCTL12_CNAK_LSB 26
129828 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */
129829 #define ALT_USB_DEV_DOEPCTL12_CNAK_MSB 26
129830 /* The width in bits of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */
129831 #define ALT_USB_DEV_DOEPCTL12_CNAK_WIDTH 1
129832 /* The mask used to set the ALT_USB_DEV_DOEPCTL12_CNAK register field value. */
129833 #define ALT_USB_DEV_DOEPCTL12_CNAK_SET_MSK 0x04000000
129834 /* The mask used to clear the ALT_USB_DEV_DOEPCTL12_CNAK register field value. */
129835 #define ALT_USB_DEV_DOEPCTL12_CNAK_CLR_MSK 0xfbffffff
129836 /* The reset value of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */
129837 #define ALT_USB_DEV_DOEPCTL12_CNAK_RESET 0x0
129838 /* Extracts the ALT_USB_DEV_DOEPCTL12_CNAK field value from a register. */
129839 #define ALT_USB_DEV_DOEPCTL12_CNAK_GET(value) (((value) & 0x04000000) >> 26)
129840 /* Produces a ALT_USB_DEV_DOEPCTL12_CNAK register field value suitable for setting the register. */
129841 #define ALT_USB_DEV_DOEPCTL12_CNAK_SET(value) (((value) << 26) & 0x04000000)
129842 
129843 /*
129844  * Field : snak
129845  *
129846  * Set NAK (SNAK)
129847  *
129848  * A write to this bit sets the NAK bit For the endpoint.
129849  *
129850  * Using this bit, the application can control the transmission of NAK
129851  *
129852  * handshakes on an endpoint. The core can also Set this bit For an
129853  *
129854  * endpoint after a SETUP packet is received on that endpoint.
129855  *
129856  * Field Enumeration Values:
129857  *
129858  * Enum | Value | Description
129859  * :-----------------------------------|:------|:------------
129860  * ALT_USB_DEV_DOEPCTL12_SNAK_E_INACT | 0x0 | No Set NAK
129861  * ALT_USB_DEV_DOEPCTL12_SNAK_E_ACT | 0x1 | Set NAK
129862  *
129863  * Field Access Macros:
129864  *
129865  */
129866 /*
129867  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNAK
129868  *
129869  * No Set NAK
129870  */
129871 #define ALT_USB_DEV_DOEPCTL12_SNAK_E_INACT 0x0
129872 /*
129873  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNAK
129874  *
129875  * Set NAK
129876  */
129877 #define ALT_USB_DEV_DOEPCTL12_SNAK_E_ACT 0x1
129878 
129879 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */
129880 #define ALT_USB_DEV_DOEPCTL12_SNAK_LSB 27
129881 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */
129882 #define ALT_USB_DEV_DOEPCTL12_SNAK_MSB 27
129883 /* The width in bits of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */
129884 #define ALT_USB_DEV_DOEPCTL12_SNAK_WIDTH 1
129885 /* The mask used to set the ALT_USB_DEV_DOEPCTL12_SNAK register field value. */
129886 #define ALT_USB_DEV_DOEPCTL12_SNAK_SET_MSK 0x08000000
129887 /* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SNAK register field value. */
129888 #define ALT_USB_DEV_DOEPCTL12_SNAK_CLR_MSK 0xf7ffffff
129889 /* The reset value of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */
129890 #define ALT_USB_DEV_DOEPCTL12_SNAK_RESET 0x0
129891 /* Extracts the ALT_USB_DEV_DOEPCTL12_SNAK field value from a register. */
129892 #define ALT_USB_DEV_DOEPCTL12_SNAK_GET(value) (((value) & 0x08000000) >> 27)
129893 /* Produces a ALT_USB_DEV_DOEPCTL12_SNAK register field value suitable for setting the register. */
129894 #define ALT_USB_DEV_DOEPCTL12_SNAK_SET(value) (((value) << 27) & 0x08000000)
129895 
129896 /*
129897  * Field : setd0pid
129898  *
129899  * Set DATA0 PID (SetD0PID)
129900  *
129901  * Applies to interrupt/bulk IN and OUT endpoints only.
129902  *
129903  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
129904  * to DATA0.
129905  *
129906  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
129907  *
129908  * DMA mode.
129909  *
129910  * 1'b0 WO
129911  *
129912  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
129913  *
129914  * Applies to isochronous IN and OUT endpoints only.
129915  *
129916  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
129917  * (micro)
129918  *
129919  * frame.
129920  *
129921  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
129922  * number
129923  *
129924  * in which to send data is in the transmit descriptor structure. The frame in
129925  * which to
129926  *
129927  * receive data is updated in receive descriptor structure.
129928  *
129929  * Field Enumeration Values:
129930  *
129931  * Enum | Value | Description
129932  * :--------------------------------------|:------|:------------------------------------
129933  * ALT_USB_DEV_DOEPCTL12_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
129934  * ALT_USB_DEV_DOEPCTL12_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
129935  *
129936  * Field Access Macros:
129937  *
129938  */
129939 /*
129940  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD0PID
129941  *
129942  * Disables Set DATA0 PID
129943  */
129944 #define ALT_USB_DEV_DOEPCTL12_SETD0PID_E_DISD 0x0
129945 /*
129946  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD0PID
129947  *
129948  * Enables Endpoint Data PID to DATA0)
129949  */
129950 #define ALT_USB_DEV_DOEPCTL12_SETD0PID_E_END 0x1
129951 
129952 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */
129953 #define ALT_USB_DEV_DOEPCTL12_SETD0PID_LSB 28
129954 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */
129955 #define ALT_USB_DEV_DOEPCTL12_SETD0PID_MSB 28
129956 /* The width in bits of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */
129957 #define ALT_USB_DEV_DOEPCTL12_SETD0PID_WIDTH 1
129958 /* The mask used to set the ALT_USB_DEV_DOEPCTL12_SETD0PID register field value. */
129959 #define ALT_USB_DEV_DOEPCTL12_SETD0PID_SET_MSK 0x10000000
129960 /* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SETD0PID register field value. */
129961 #define ALT_USB_DEV_DOEPCTL12_SETD0PID_CLR_MSK 0xefffffff
129962 /* The reset value of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */
129963 #define ALT_USB_DEV_DOEPCTL12_SETD0PID_RESET 0x0
129964 /* Extracts the ALT_USB_DEV_DOEPCTL12_SETD0PID field value from a register. */
129965 #define ALT_USB_DEV_DOEPCTL12_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
129966 /* Produces a ALT_USB_DEV_DOEPCTL12_SETD0PID register field value suitable for setting the register. */
129967 #define ALT_USB_DEV_DOEPCTL12_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
129968 
129969 /*
129970  * Field : setd1pid
129971  *
129972  * Set DATA1 PID (SetD1PID)
129973  *
129974  * Applies to interrupt/bulk IN and OUT endpoints only.
129975  *
129976  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
129977  * to DATA1.
129978  *
129979  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
129980  *
129981  * DMA mode.
129982  *
129983  * Set Odd (micro)frame (SetOddFr)
129984  *
129985  * Applies to isochronous IN and OUT endpoints only.
129986  *
129987  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
129988  *
129989  * (micro)frame.
129990  *
129991  * This field is not applicable for Scatter/Gather DMA mode.
129992  *
129993  * Field Enumeration Values:
129994  *
129995  * Enum | Value | Description
129996  * :--------------------------------------|:------|:-----------------------
129997  * ALT_USB_DEV_DOEPCTL12_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
129998  * ALT_USB_DEV_DOEPCTL12_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
129999  *
130000  * Field Access Macros:
130001  *
130002  */
130003 /*
130004  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD1PID
130005  *
130006  * Disables Set DATA1 PID
130007  */
130008 #define ALT_USB_DEV_DOEPCTL12_SETD1PID_E_DISD 0x0
130009 /*
130010  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD1PID
130011  *
130012  * Enables Set DATA1 PID
130013  */
130014 #define ALT_USB_DEV_DOEPCTL12_SETD1PID_E_END 0x1
130015 
130016 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */
130017 #define ALT_USB_DEV_DOEPCTL12_SETD1PID_LSB 29
130018 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */
130019 #define ALT_USB_DEV_DOEPCTL12_SETD1PID_MSB 29
130020 /* The width in bits of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */
130021 #define ALT_USB_DEV_DOEPCTL12_SETD1PID_WIDTH 1
130022 /* The mask used to set the ALT_USB_DEV_DOEPCTL12_SETD1PID register field value. */
130023 #define ALT_USB_DEV_DOEPCTL12_SETD1PID_SET_MSK 0x20000000
130024 /* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SETD1PID register field value. */
130025 #define ALT_USB_DEV_DOEPCTL12_SETD1PID_CLR_MSK 0xdfffffff
130026 /* The reset value of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */
130027 #define ALT_USB_DEV_DOEPCTL12_SETD1PID_RESET 0x0
130028 /* Extracts the ALT_USB_DEV_DOEPCTL12_SETD1PID field value from a register. */
130029 #define ALT_USB_DEV_DOEPCTL12_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
130030 /* Produces a ALT_USB_DEV_DOEPCTL12_SETD1PID register field value suitable for setting the register. */
130031 #define ALT_USB_DEV_DOEPCTL12_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
130032 
130033 /*
130034  * Field : epdis
130035  *
130036  * Endpoint Disable (EPDis)
130037  *
130038  * Applies to IN and OUT endpoints.
130039  *
130040  * The application sets this bit to stop transmitting/receiving data on an
130041  * endpoint, even
130042  *
130043  * before the transfer for that endpoint is complete. The application must wait for
130044  * the
130045  *
130046  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
130047  * clears
130048  *
130049  * this bit before setting the Endpoint Disabled interrupt. The application must
130050  * set this bit
130051  *
130052  * only if Endpoint Enable is already set for this endpoint.
130053  *
130054  * Field Enumeration Values:
130055  *
130056  * Enum | Value | Description
130057  * :------------------------------------|:------|:--------------------
130058  * ALT_USB_DEV_DOEPCTL12_EPDIS_E_INACT | 0x0 | No Endpoint Disable
130059  * ALT_USB_DEV_DOEPCTL12_EPDIS_E_ACT | 0x1 | Endpoint Disable
130060  *
130061  * Field Access Macros:
130062  *
130063  */
130064 /*
130065  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPDIS
130066  *
130067  * No Endpoint Disable
130068  */
130069 #define ALT_USB_DEV_DOEPCTL12_EPDIS_E_INACT 0x0
130070 /*
130071  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPDIS
130072  *
130073  * Endpoint Disable
130074  */
130075 #define ALT_USB_DEV_DOEPCTL12_EPDIS_E_ACT 0x1
130076 
130077 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */
130078 #define ALT_USB_DEV_DOEPCTL12_EPDIS_LSB 30
130079 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */
130080 #define ALT_USB_DEV_DOEPCTL12_EPDIS_MSB 30
130081 /* The width in bits of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */
130082 #define ALT_USB_DEV_DOEPCTL12_EPDIS_WIDTH 1
130083 /* The mask used to set the ALT_USB_DEV_DOEPCTL12_EPDIS register field value. */
130084 #define ALT_USB_DEV_DOEPCTL12_EPDIS_SET_MSK 0x40000000
130085 /* The mask used to clear the ALT_USB_DEV_DOEPCTL12_EPDIS register field value. */
130086 #define ALT_USB_DEV_DOEPCTL12_EPDIS_CLR_MSK 0xbfffffff
130087 /* The reset value of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */
130088 #define ALT_USB_DEV_DOEPCTL12_EPDIS_RESET 0x0
130089 /* Extracts the ALT_USB_DEV_DOEPCTL12_EPDIS field value from a register. */
130090 #define ALT_USB_DEV_DOEPCTL12_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
130091 /* Produces a ALT_USB_DEV_DOEPCTL12_EPDIS register field value suitable for setting the register. */
130092 #define ALT_USB_DEV_DOEPCTL12_EPDIS_SET(value) (((value) << 30) & 0x40000000)
130093 
130094 /*
130095  * Field : epena
130096  *
130097  * Endpoint Enable (EPEna)
130098  *
130099  * Applies to IN and OUT endpoints.
130100  *
130101  * When Scatter/Gather DMA mode is enabled,
130102  *
130103  * For IN endpoints this bit indicates that the descriptor structure and data
130104  * buffer with
130105  *
130106  * data ready to transmit is setup.
130107  *
130108  * For OUT endpoint it indicates that the descriptor structure and data buffer to
130109  *
130110  * receive data is setup.
130111  *
130112  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
130113  *
130114  * DMA mode:
130115  *
130116  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
130117  * the
130118  *
130119  * endpoint.
130120  *
130121  * * For OUT endpoints, this bit indicates that the application has allocated the
130122  *
130123  * memory to start receiving data from the USB.
130124  *
130125  * * The core clears this bit before setting any of the following interrupts on
130126  * this
130127  *
130128  * endpoint:
130129  *
130130  * SETUP Phase Done
130131  *
130132  * Endpoint Disabled
130133  *
130134  * Transfer Completed
130135  *
130136  * Note: For control endpoints in DMA mode, this bit must be set to be able to
130137  * transfer
130138  *
130139  * SETUP data packets in memory.
130140  *
130141  * Field Enumeration Values:
130142  *
130143  * Enum | Value | Description
130144  * :------------------------------------|:------|:-------------------------
130145  * ALT_USB_DEV_DOEPCTL12_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
130146  * ALT_USB_DEV_DOEPCTL12_EPENA_E_ACT | 0x1 | Endpoint Enable active
130147  *
130148  * Field Access Macros:
130149  *
130150  */
130151 /*
130152  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPENA
130153  *
130154  * Endpoint Enable inactive
130155  */
130156 #define ALT_USB_DEV_DOEPCTL12_EPENA_E_INACT 0x0
130157 /*
130158  * Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPENA
130159  *
130160  * Endpoint Enable active
130161  */
130162 #define ALT_USB_DEV_DOEPCTL12_EPENA_E_ACT 0x1
130163 
130164 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */
130165 #define ALT_USB_DEV_DOEPCTL12_EPENA_LSB 31
130166 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */
130167 #define ALT_USB_DEV_DOEPCTL12_EPENA_MSB 31
130168 /* The width in bits of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */
130169 #define ALT_USB_DEV_DOEPCTL12_EPENA_WIDTH 1
130170 /* The mask used to set the ALT_USB_DEV_DOEPCTL12_EPENA register field value. */
130171 #define ALT_USB_DEV_DOEPCTL12_EPENA_SET_MSK 0x80000000
130172 /* The mask used to clear the ALT_USB_DEV_DOEPCTL12_EPENA register field value. */
130173 #define ALT_USB_DEV_DOEPCTL12_EPENA_CLR_MSK 0x7fffffff
130174 /* The reset value of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */
130175 #define ALT_USB_DEV_DOEPCTL12_EPENA_RESET 0x0
130176 /* Extracts the ALT_USB_DEV_DOEPCTL12_EPENA field value from a register. */
130177 #define ALT_USB_DEV_DOEPCTL12_EPENA_GET(value) (((value) & 0x80000000) >> 31)
130178 /* Produces a ALT_USB_DEV_DOEPCTL12_EPENA register field value suitable for setting the register. */
130179 #define ALT_USB_DEV_DOEPCTL12_EPENA_SET(value) (((value) << 31) & 0x80000000)
130180 
130181 #ifndef __ASSEMBLY__
130182 /*
130183  * WARNING: The C register and register group struct declarations are provided for
130184  * convenience and illustrative purposes. They should, however, be used with
130185  * caution as the C language standard provides no guarantees about the alignment or
130186  * atomicity of device memory accesses. The recommended practice for writing
130187  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
130188  * alt_write_word() functions.
130189  *
130190  * The struct declaration for register ALT_USB_DEV_DOEPCTL12.
130191  */
130192 struct ALT_USB_DEV_DOEPCTL12_s
130193 {
130194  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL12_MPS */
130195  uint32_t : 4; /* *UNDEFINED* */
130196  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL12_USBACTEP */
130197  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL12_DPID */
130198  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL12_NAKSTS */
130199  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL12_EPTYPE */
130200  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL12_SNP */
130201  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL12_STALL */
130202  uint32_t : 4; /* *UNDEFINED* */
130203  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL12_CNAK */
130204  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL12_SNAK */
130205  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL12_SETD0PID */
130206  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL12_SETD1PID */
130207  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL12_EPDIS */
130208  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL12_EPENA */
130209 };
130210 
130211 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL12. */
130212 typedef volatile struct ALT_USB_DEV_DOEPCTL12_s ALT_USB_DEV_DOEPCTL12_t;
130213 #endif /* __ASSEMBLY__ */
130214 
130215 /* The reset value of the ALT_USB_DEV_DOEPCTL12 register. */
130216 #define ALT_USB_DEV_DOEPCTL12_RESET 0x00000000
130217 /* The byte offset of the ALT_USB_DEV_DOEPCTL12 register from the beginning of the component. */
130218 #define ALT_USB_DEV_DOEPCTL12_OFST 0x480
130219 /* The address of the ALT_USB_DEV_DOEPCTL12 register. */
130220 #define ALT_USB_DEV_DOEPCTL12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL12_OFST))
130221 
130222 /*
130223  * Register : doepint12
130224  *
130225  * Device OUT Endpoint 12 Interrupt Register
130226  *
130227  * Register Layout
130228  *
130229  * Bits | Access | Reset | Description
130230  * :--------|:-------|:------|:-------------------------------------
130231  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_XFERCOMPL
130232  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_EPDISBLD
130233  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_AHBERR
130234  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_SETUP
130235  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS
130236  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_STSPHSERCVD
130237  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP
130238  * [7] | ??? | 0x0 | *UNDEFINED*
130239  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_OUTPKTERR
130240  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_BNAINTR
130241  * [10] | ??? | 0x0 | *UNDEFINED*
130242  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_PKTDRPSTS
130243  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_BBLEERR
130244  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_NAKINTRPT
130245  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_NYETINTRPT
130246  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_STUPPKTRCVD
130247  * [31:16] | ??? | 0x0 | *UNDEFINED*
130248  *
130249  */
130250 /*
130251  * Field : xfercompl
130252  *
130253  * Transfer Completed Interrupt (XferCompl)
130254  *
130255  * Applies to IN and OUT endpoints.
130256  *
130257  * When Scatter/Gather DMA mode is enabled
130258  *
130259  * * For IN endpoint this field indicates that the requested data
130260  *
130261  * from the descriptor is moved from external system memory
130262  *
130263  * to internal FIFO.
130264  *
130265  * * For OUT endpoint this field indicates that the requested
130266  *
130267  * data from the internal FIFO is moved to external system
130268  *
130269  * memory. This interrupt is generated only when the
130270  *
130271  * corresponding endpoint descriptor is closed, and the IOC
130272  *
130273  * bit For the corresponding descriptor is Set.
130274  *
130275  * When Scatter/Gather DMA mode is disabled, this field
130276  *
130277  * indicates that the programmed transfer is complete on the
130278  *
130279  * AHB as well as on the USB, For this endpoint.
130280  *
130281  * Field Enumeration Values:
130282  *
130283  * Enum | Value | Description
130284  * :----------------------------------------|:------|:-----------------------------
130285  * ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_INACT | 0x0 | No Interrupt
130286  * ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
130287  *
130288  * Field Access Macros:
130289  *
130290  */
130291 /*
130292  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_XFERCOMPL
130293  *
130294  * No Interrupt
130295  */
130296 #define ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_INACT 0x0
130297 /*
130298  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_XFERCOMPL
130299  *
130300  * Transfer Completed Interrupt
130301  */
130302 #define ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_ACT 0x1
130303 
130304 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */
130305 #define ALT_USB_DEV_DOEPINT12_XFERCOMPL_LSB 0
130306 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */
130307 #define ALT_USB_DEV_DOEPINT12_XFERCOMPL_MSB 0
130308 /* The width in bits of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */
130309 #define ALT_USB_DEV_DOEPINT12_XFERCOMPL_WIDTH 1
130310 /* The mask used to set the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field value. */
130311 #define ALT_USB_DEV_DOEPINT12_XFERCOMPL_SET_MSK 0x00000001
130312 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field value. */
130313 #define ALT_USB_DEV_DOEPINT12_XFERCOMPL_CLR_MSK 0xfffffffe
130314 /* The reset value of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */
130315 #define ALT_USB_DEV_DOEPINT12_XFERCOMPL_RESET 0x0
130316 /* Extracts the ALT_USB_DEV_DOEPINT12_XFERCOMPL field value from a register. */
130317 #define ALT_USB_DEV_DOEPINT12_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
130318 /* Produces a ALT_USB_DEV_DOEPINT12_XFERCOMPL register field value suitable for setting the register. */
130319 #define ALT_USB_DEV_DOEPINT12_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
130320 
130321 /*
130322  * Field : epdisbld
130323  *
130324  * Endpoint Disabled Interrupt (EPDisbld)
130325  *
130326  * Applies to IN and OUT endpoints.
130327  *
130328  * This bit indicates that the endpoint is disabled per the
130329  *
130330  * application's request.
130331  *
130332  * Field Enumeration Values:
130333  *
130334  * Enum | Value | Description
130335  * :---------------------------------------|:------|:----------------------------
130336  * ALT_USB_DEV_DOEPINT12_EPDISBLD_E_INACT | 0x0 | No Interrupt
130337  * ALT_USB_DEV_DOEPINT12_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
130338  *
130339  * Field Access Macros:
130340  *
130341  */
130342 /*
130343  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_EPDISBLD
130344  *
130345  * No Interrupt
130346  */
130347 #define ALT_USB_DEV_DOEPINT12_EPDISBLD_E_INACT 0x0
130348 /*
130349  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_EPDISBLD
130350  *
130351  * Endpoint Disabled Interrupt
130352  */
130353 #define ALT_USB_DEV_DOEPINT12_EPDISBLD_E_ACT 0x1
130354 
130355 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */
130356 #define ALT_USB_DEV_DOEPINT12_EPDISBLD_LSB 1
130357 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */
130358 #define ALT_USB_DEV_DOEPINT12_EPDISBLD_MSB 1
130359 /* The width in bits of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */
130360 #define ALT_USB_DEV_DOEPINT12_EPDISBLD_WIDTH 1
130361 /* The mask used to set the ALT_USB_DEV_DOEPINT12_EPDISBLD register field value. */
130362 #define ALT_USB_DEV_DOEPINT12_EPDISBLD_SET_MSK 0x00000002
130363 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_EPDISBLD register field value. */
130364 #define ALT_USB_DEV_DOEPINT12_EPDISBLD_CLR_MSK 0xfffffffd
130365 /* The reset value of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */
130366 #define ALT_USB_DEV_DOEPINT12_EPDISBLD_RESET 0x0
130367 /* Extracts the ALT_USB_DEV_DOEPINT12_EPDISBLD field value from a register. */
130368 #define ALT_USB_DEV_DOEPINT12_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
130369 /* Produces a ALT_USB_DEV_DOEPINT12_EPDISBLD register field value suitable for setting the register. */
130370 #define ALT_USB_DEV_DOEPINT12_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
130371 
130372 /*
130373  * Field : ahberr
130374  *
130375  * AHB Error (AHBErr)
130376  *
130377  * Applies to IN and OUT endpoints.
130378  *
130379  * This is generated only in Internal DMA mode when there is an
130380  *
130381  * AHB error during an AHB read/write. The application can read
130382  *
130383  * the corresponding endpoint DMA address register to get the
130384  *
130385  * error address.
130386  *
130387  * Field Enumeration Values:
130388  *
130389  * Enum | Value | Description
130390  * :-------------------------------------|:------|:--------------------
130391  * ALT_USB_DEV_DOEPINT12_AHBERR_E_INACT | 0x0 | No Interrupt
130392  * ALT_USB_DEV_DOEPINT12_AHBERR_E_ACT | 0x1 | AHB Error interrupt
130393  *
130394  * Field Access Macros:
130395  *
130396  */
130397 /*
130398  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_AHBERR
130399  *
130400  * No Interrupt
130401  */
130402 #define ALT_USB_DEV_DOEPINT12_AHBERR_E_INACT 0x0
130403 /*
130404  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_AHBERR
130405  *
130406  * AHB Error interrupt
130407  */
130408 #define ALT_USB_DEV_DOEPINT12_AHBERR_E_ACT 0x1
130409 
130410 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */
130411 #define ALT_USB_DEV_DOEPINT12_AHBERR_LSB 2
130412 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */
130413 #define ALT_USB_DEV_DOEPINT12_AHBERR_MSB 2
130414 /* The width in bits of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */
130415 #define ALT_USB_DEV_DOEPINT12_AHBERR_WIDTH 1
130416 /* The mask used to set the ALT_USB_DEV_DOEPINT12_AHBERR register field value. */
130417 #define ALT_USB_DEV_DOEPINT12_AHBERR_SET_MSK 0x00000004
130418 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_AHBERR register field value. */
130419 #define ALT_USB_DEV_DOEPINT12_AHBERR_CLR_MSK 0xfffffffb
130420 /* The reset value of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */
130421 #define ALT_USB_DEV_DOEPINT12_AHBERR_RESET 0x0
130422 /* Extracts the ALT_USB_DEV_DOEPINT12_AHBERR field value from a register. */
130423 #define ALT_USB_DEV_DOEPINT12_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
130424 /* Produces a ALT_USB_DEV_DOEPINT12_AHBERR register field value suitable for setting the register. */
130425 #define ALT_USB_DEV_DOEPINT12_AHBERR_SET(value) (((value) << 2) & 0x00000004)
130426 
130427 /*
130428  * Field : setup
130429  *
130430  * SETUP Phase Done (SetUp)
130431  *
130432  * Applies to control OUT endpoints only.
130433  *
130434  * Indicates that the SETUP phase For the control endpoint is
130435  *
130436  * complete and no more back-to-back SETUP packets were
130437  *
130438  * received For the current control transfer. On this interrupt, the
130439  *
130440  * application can decode the received SETUP data packet.
130441  *
130442  * Field Enumeration Values:
130443  *
130444  * Enum | Value | Description
130445  * :------------------------------------|:------|:--------------------
130446  * ALT_USB_DEV_DOEPINT12_SETUP_E_INACT | 0x0 | No SETUP Phase Done
130447  * ALT_USB_DEV_DOEPINT12_SETUP_E_ACT | 0x1 | SETUP Phase Done
130448  *
130449  * Field Access Macros:
130450  *
130451  */
130452 /*
130453  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_SETUP
130454  *
130455  * No SETUP Phase Done
130456  */
130457 #define ALT_USB_DEV_DOEPINT12_SETUP_E_INACT 0x0
130458 /*
130459  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_SETUP
130460  *
130461  * SETUP Phase Done
130462  */
130463 #define ALT_USB_DEV_DOEPINT12_SETUP_E_ACT 0x1
130464 
130465 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_SETUP register field. */
130466 #define ALT_USB_DEV_DOEPINT12_SETUP_LSB 3
130467 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_SETUP register field. */
130468 #define ALT_USB_DEV_DOEPINT12_SETUP_MSB 3
130469 /* The width in bits of the ALT_USB_DEV_DOEPINT12_SETUP register field. */
130470 #define ALT_USB_DEV_DOEPINT12_SETUP_WIDTH 1
130471 /* The mask used to set the ALT_USB_DEV_DOEPINT12_SETUP register field value. */
130472 #define ALT_USB_DEV_DOEPINT12_SETUP_SET_MSK 0x00000008
130473 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_SETUP register field value. */
130474 #define ALT_USB_DEV_DOEPINT12_SETUP_CLR_MSK 0xfffffff7
130475 /* The reset value of the ALT_USB_DEV_DOEPINT12_SETUP register field. */
130476 #define ALT_USB_DEV_DOEPINT12_SETUP_RESET 0x0
130477 /* Extracts the ALT_USB_DEV_DOEPINT12_SETUP field value from a register. */
130478 #define ALT_USB_DEV_DOEPINT12_SETUP_GET(value) (((value) & 0x00000008) >> 3)
130479 /* Produces a ALT_USB_DEV_DOEPINT12_SETUP register field value suitable for setting the register. */
130480 #define ALT_USB_DEV_DOEPINT12_SETUP_SET(value) (((value) << 3) & 0x00000008)
130481 
130482 /*
130483  * Field : outtknepdis
130484  *
130485  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
130486  *
130487  * Applies only to control OUT endpoints.
130488  *
130489  * Indicates that an OUT token was received when the endpoint
130490  *
130491  * was not yet enabled. This interrupt is asserted on the endpoint
130492  *
130493  * For which the OUT token was received.
130494  *
130495  * Field Enumeration Values:
130496  *
130497  * Enum | Value | Description
130498  * :------------------------------------------|:------|:---------------------------------------------
130499  * ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
130500  * ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
130501  *
130502  * Field Access Macros:
130503  *
130504  */
130505 /*
130506  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS
130507  *
130508  * No OUT Token Received When Endpoint Disabled
130509  */
130510 #define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_INACT 0x0
130511 /*
130512  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS
130513  *
130514  * OUT Token Received When Endpoint Disabled
130515  */
130516 #define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_ACT 0x1
130517 
130518 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */
130519 #define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_LSB 4
130520 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */
130521 #define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_MSB 4
130522 /* The width in bits of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */
130523 #define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_WIDTH 1
130524 /* The mask used to set the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field value. */
130525 #define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_SET_MSK 0x00000010
130526 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field value. */
130527 #define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_CLR_MSK 0xffffffef
130528 /* The reset value of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */
130529 #define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_RESET 0x0
130530 /* Extracts the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS field value from a register. */
130531 #define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
130532 /* Produces a ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field value suitable for setting the register. */
130533 #define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
130534 
130535 /*
130536  * Field : stsphsercvd
130537  *
130538  * Status Phase Received For Control Write (StsPhseRcvd)
130539  *
130540  * This interrupt is valid only For Control OUT endpoints and only in
130541  *
130542  * Scatter Gather DMA mode.
130543  *
130544  * This interrupt is generated only after the core has transferred all
130545  *
130546  * the data that the host has sent during the data phase of a control
130547  *
130548  * write transfer, to the system memory buffer.
130549  *
130550  * The interrupt indicates to the application that the host has
130551  *
130552  * switched from data phase to the status phase of a Control Write
130553  *
130554  * transfer. The application can use this interrupt to ACK or STALL
130555  *
130556  * the Status phase, after it has decoded the data phase. This is
130557  *
130558  * applicable only in Case of Scatter Gather DMA mode.
130559  *
130560  * Field Enumeration Values:
130561  *
130562  * Enum | Value | Description
130563  * :------------------------------------------|:------|:-------------------------------------------
130564  * ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
130565  * ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
130566  *
130567  * Field Access Macros:
130568  *
130569  */
130570 /*
130571  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_STSPHSERCVD
130572  *
130573  * No Status Phase Received for Control Write
130574  */
130575 #define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_INACT 0x0
130576 /*
130577  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_STSPHSERCVD
130578  *
130579  * Status Phase Received for Control Write
130580  */
130581 #define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_ACT 0x1
130582 
130583 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */
130584 #define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_LSB 5
130585 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */
130586 #define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_MSB 5
130587 /* The width in bits of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */
130588 #define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_WIDTH 1
130589 /* The mask used to set the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field value. */
130590 #define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_SET_MSK 0x00000020
130591 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field value. */
130592 #define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_CLR_MSK 0xffffffdf
130593 /* The reset value of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */
130594 #define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_RESET 0x0
130595 /* Extracts the ALT_USB_DEV_DOEPINT12_STSPHSERCVD field value from a register. */
130596 #define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
130597 /* Produces a ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field value suitable for setting the register. */
130598 #define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
130599 
130600 /*
130601  * Field : back2backsetup
130602  *
130603  * Back-to-Back SETUP Packets Received (Back2BackSETup)
130604  *
130605  * Applies to Control OUT endpoints only.
130606  *
130607  * This bit indicates that the core has received more than three
130608  *
130609  * back-to-back SETUP packets For this particular endpoint. For
130610  *
130611  * information about handling this interrupt,
130612  *
130613  * Field Enumeration Values:
130614  *
130615  * Enum | Value | Description
130616  * :---------------------------------------------|:------|:---------------------------------------
130617  * ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
130618  * ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
130619  *
130620  * Field Access Macros:
130621  *
130622  */
130623 /*
130624  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP
130625  *
130626  * No Back-to-Back SETUP Packets Received
130627  */
130628 #define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_INACT 0x0
130629 /*
130630  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP
130631  *
130632  * Back-to-Back SETUP Packets Received
130633  */
130634 #define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_ACT 0x1
130635 
130636 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */
130637 #define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_LSB 6
130638 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */
130639 #define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_MSB 6
130640 /* The width in bits of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */
130641 #define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_WIDTH 1
130642 /* The mask used to set the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field value. */
130643 #define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_SET_MSK 0x00000040
130644 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field value. */
130645 #define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_CLR_MSK 0xffffffbf
130646 /* The reset value of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */
130647 #define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_RESET 0x0
130648 /* Extracts the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP field value from a register. */
130649 #define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
130650 /* Produces a ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field value suitable for setting the register. */
130651 #define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
130652 
130653 /*
130654  * Field : outpkterr
130655  *
130656  * OUT Packet Error (OutPktErr)
130657  *
130658  * Applies to OUT endpoints Only
130659  *
130660  * This interrupt is valid only when thresholding is enabled. This interrupt is
130661  * asserted when the
130662  *
130663  * core detects an overflow or a CRC error For non-Isochronous
130664  *
130665  * OUT packet.
130666  *
130667  * Field Enumeration Values:
130668  *
130669  * Enum | Value | Description
130670  * :----------------------------------------|:------|:--------------------
130671  * ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
130672  * ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
130673  *
130674  * Field Access Macros:
130675  *
130676  */
130677 /*
130678  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTPKTERR
130679  *
130680  * No OUT Packet Error
130681  */
130682 #define ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_INACT 0x0
130683 /*
130684  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTPKTERR
130685  *
130686  * OUT Packet Error
130687  */
130688 #define ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_ACT 0x1
130689 
130690 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */
130691 #define ALT_USB_DEV_DOEPINT12_OUTPKTERR_LSB 8
130692 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */
130693 #define ALT_USB_DEV_DOEPINT12_OUTPKTERR_MSB 8
130694 /* The width in bits of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */
130695 #define ALT_USB_DEV_DOEPINT12_OUTPKTERR_WIDTH 1
130696 /* The mask used to set the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field value. */
130697 #define ALT_USB_DEV_DOEPINT12_OUTPKTERR_SET_MSK 0x00000100
130698 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field value. */
130699 #define ALT_USB_DEV_DOEPINT12_OUTPKTERR_CLR_MSK 0xfffffeff
130700 /* The reset value of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */
130701 #define ALT_USB_DEV_DOEPINT12_OUTPKTERR_RESET 0x0
130702 /* Extracts the ALT_USB_DEV_DOEPINT12_OUTPKTERR field value from a register. */
130703 #define ALT_USB_DEV_DOEPINT12_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
130704 /* Produces a ALT_USB_DEV_DOEPINT12_OUTPKTERR register field value suitable for setting the register. */
130705 #define ALT_USB_DEV_DOEPINT12_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
130706 
130707 /*
130708  * Field : bnaintr
130709  *
130710  * BNA (Buffer Not Available) Interrupt (BNAIntr)
130711  *
130712  * This bit is valid only when Scatter/Gather DMA mode is enabled.
130713  *
130714  * The core generates this interrupt when the descriptor accessed
130715  *
130716  * is not ready For the Core to process, such as Host busy or DMA
130717  *
130718  * done
130719  *
130720  * Field Enumeration Values:
130721  *
130722  * Enum | Value | Description
130723  * :--------------------------------------|:------|:--------------
130724  * ALT_USB_DEV_DOEPINT12_BNAINTR_E_INACT | 0x0 | No interrupt
130725  * ALT_USB_DEV_DOEPINT12_BNAINTR_E_ACT | 0x1 | BNA interrupt
130726  *
130727  * Field Access Macros:
130728  *
130729  */
130730 /*
130731  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BNAINTR
130732  *
130733  * No interrupt
130734  */
130735 #define ALT_USB_DEV_DOEPINT12_BNAINTR_E_INACT 0x0
130736 /*
130737  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BNAINTR
130738  *
130739  * BNA interrupt
130740  */
130741 #define ALT_USB_DEV_DOEPINT12_BNAINTR_E_ACT 0x1
130742 
130743 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */
130744 #define ALT_USB_DEV_DOEPINT12_BNAINTR_LSB 9
130745 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */
130746 #define ALT_USB_DEV_DOEPINT12_BNAINTR_MSB 9
130747 /* The width in bits of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */
130748 #define ALT_USB_DEV_DOEPINT12_BNAINTR_WIDTH 1
130749 /* The mask used to set the ALT_USB_DEV_DOEPINT12_BNAINTR register field value. */
130750 #define ALT_USB_DEV_DOEPINT12_BNAINTR_SET_MSK 0x00000200
130751 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_BNAINTR register field value. */
130752 #define ALT_USB_DEV_DOEPINT12_BNAINTR_CLR_MSK 0xfffffdff
130753 /* The reset value of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */
130754 #define ALT_USB_DEV_DOEPINT12_BNAINTR_RESET 0x0
130755 /* Extracts the ALT_USB_DEV_DOEPINT12_BNAINTR field value from a register. */
130756 #define ALT_USB_DEV_DOEPINT12_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
130757 /* Produces a ALT_USB_DEV_DOEPINT12_BNAINTR register field value suitable for setting the register. */
130758 #define ALT_USB_DEV_DOEPINT12_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
130759 
130760 /*
130761  * Field : pktdrpsts
130762  *
130763  * Packet Drop Status (PktDrpSts)
130764  *
130765  * This bit indicates to the application that an ISOC OUT packet has been dropped.
130766  * This
130767  *
130768  * bit does not have an associated mask bit and does not generate an interrupt.
130769  *
130770  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
130771  * transfer
130772  *
130773  * interrupt feature is selected.
130774  *
130775  * Field Enumeration Values:
130776  *
130777  * Enum | Value | Description
130778  * :----------------------------------------|:------|:-----------------------------
130779  * ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_INACT | 0x0 | No interrupt
130780  * ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
130781  *
130782  * Field Access Macros:
130783  *
130784  */
130785 /*
130786  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_PKTDRPSTS
130787  *
130788  * No interrupt
130789  */
130790 #define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_INACT 0x0
130791 /*
130792  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_PKTDRPSTS
130793  *
130794  * Packet Drop Status interrupt
130795  */
130796 #define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_ACT 0x1
130797 
130798 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */
130799 #define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_LSB 11
130800 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */
130801 #define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_MSB 11
130802 /* The width in bits of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */
130803 #define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_WIDTH 1
130804 /* The mask used to set the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field value. */
130805 #define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_SET_MSK 0x00000800
130806 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field value. */
130807 #define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_CLR_MSK 0xfffff7ff
130808 /* The reset value of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */
130809 #define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_RESET 0x0
130810 /* Extracts the ALT_USB_DEV_DOEPINT12_PKTDRPSTS field value from a register. */
130811 #define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
130812 /* Produces a ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field value suitable for setting the register. */
130813 #define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
130814 
130815 /*
130816  * Field : bbleerr
130817  *
130818  * NAK Interrupt (BbleErr)
130819  *
130820  * The core generates this interrupt when babble is received for the endpoint.
130821  *
130822  * Field Enumeration Values:
130823  *
130824  * Enum | Value | Description
130825  * :--------------------------------------|:------|:------------------
130826  * ALT_USB_DEV_DOEPINT12_BBLEERR_E_INACT | 0x0 | No interrupt
130827  * ALT_USB_DEV_DOEPINT12_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
130828  *
130829  * Field Access Macros:
130830  *
130831  */
130832 /*
130833  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BBLEERR
130834  *
130835  * No interrupt
130836  */
130837 #define ALT_USB_DEV_DOEPINT12_BBLEERR_E_INACT 0x0
130838 /*
130839  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_BBLEERR
130840  *
130841  * BbleErr interrupt
130842  */
130843 #define ALT_USB_DEV_DOEPINT12_BBLEERR_E_ACT 0x1
130844 
130845 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */
130846 #define ALT_USB_DEV_DOEPINT12_BBLEERR_LSB 12
130847 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */
130848 #define ALT_USB_DEV_DOEPINT12_BBLEERR_MSB 12
130849 /* The width in bits of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */
130850 #define ALT_USB_DEV_DOEPINT12_BBLEERR_WIDTH 1
130851 /* The mask used to set the ALT_USB_DEV_DOEPINT12_BBLEERR register field value. */
130852 #define ALT_USB_DEV_DOEPINT12_BBLEERR_SET_MSK 0x00001000
130853 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_BBLEERR register field value. */
130854 #define ALT_USB_DEV_DOEPINT12_BBLEERR_CLR_MSK 0xffffefff
130855 /* The reset value of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */
130856 #define ALT_USB_DEV_DOEPINT12_BBLEERR_RESET 0x0
130857 /* Extracts the ALT_USB_DEV_DOEPINT12_BBLEERR field value from a register. */
130858 #define ALT_USB_DEV_DOEPINT12_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
130859 /* Produces a ALT_USB_DEV_DOEPINT12_BBLEERR register field value suitable for setting the register. */
130860 #define ALT_USB_DEV_DOEPINT12_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
130861 
130862 /*
130863  * Field : nakintrpt
130864  *
130865  * NAK Interrupt (NAKInterrupt)
130866  *
130867  * The core generates this interrupt when a NAK is transmitted or received by the
130868  * device.
130869  *
130870  * In case of isochronous IN endpoints the interrupt gets generated when a zero
130871  * length
130872  *
130873  * packet is transmitted due to un-availability of data in the TXFifo.
130874  *
130875  * Field Enumeration Values:
130876  *
130877  * Enum | Value | Description
130878  * :----------------------------------------|:------|:--------------
130879  * ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_INACT | 0x0 | No interrupt
130880  * ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
130881  *
130882  * Field Access Macros:
130883  *
130884  */
130885 /*
130886  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_NAKINTRPT
130887  *
130888  * No interrupt
130889  */
130890 #define ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_INACT 0x0
130891 /*
130892  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_NAKINTRPT
130893  *
130894  * NAK Interrupt
130895  */
130896 #define ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_ACT 0x1
130897 
130898 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */
130899 #define ALT_USB_DEV_DOEPINT12_NAKINTRPT_LSB 13
130900 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */
130901 #define ALT_USB_DEV_DOEPINT12_NAKINTRPT_MSB 13
130902 /* The width in bits of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */
130903 #define ALT_USB_DEV_DOEPINT12_NAKINTRPT_WIDTH 1
130904 /* The mask used to set the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field value. */
130905 #define ALT_USB_DEV_DOEPINT12_NAKINTRPT_SET_MSK 0x00002000
130906 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field value. */
130907 #define ALT_USB_DEV_DOEPINT12_NAKINTRPT_CLR_MSK 0xffffdfff
130908 /* The reset value of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */
130909 #define ALT_USB_DEV_DOEPINT12_NAKINTRPT_RESET 0x0
130910 /* Extracts the ALT_USB_DEV_DOEPINT12_NAKINTRPT field value from a register. */
130911 #define ALT_USB_DEV_DOEPINT12_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
130912 /* Produces a ALT_USB_DEV_DOEPINT12_NAKINTRPT register field value suitable for setting the register. */
130913 #define ALT_USB_DEV_DOEPINT12_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
130914 
130915 /*
130916  * Field : nyetintrpt
130917  *
130918  * NYET Interrupt (NYETIntrpt)
130919  *
130920  * The core generates this interrupt when a NYET response is transmitted for a non
130921  * isochronous OUT endpoint.
130922  *
130923  * Field Enumeration Values:
130924  *
130925  * Enum | Value | Description
130926  * :-----------------------------------------|:------|:---------------
130927  * ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_INACT | 0x0 | No interrupt
130928  * ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
130929  *
130930  * Field Access Macros:
130931  *
130932  */
130933 /*
130934  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_NYETINTRPT
130935  *
130936  * No interrupt
130937  */
130938 #define ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_INACT 0x0
130939 /*
130940  * Enumerated value for register field ALT_USB_DEV_DOEPINT12_NYETINTRPT
130941  *
130942  * NYET Interrupt
130943  */
130944 #define ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_ACT 0x1
130945 
130946 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */
130947 #define ALT_USB_DEV_DOEPINT12_NYETINTRPT_LSB 14
130948 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */
130949 #define ALT_USB_DEV_DOEPINT12_NYETINTRPT_MSB 14
130950 /* The width in bits of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */
130951 #define ALT_USB_DEV_DOEPINT12_NYETINTRPT_WIDTH 1
130952 /* The mask used to set the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field value. */
130953 #define ALT_USB_DEV_DOEPINT12_NYETINTRPT_SET_MSK 0x00004000
130954 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field value. */
130955 #define ALT_USB_DEV_DOEPINT12_NYETINTRPT_CLR_MSK 0xffffbfff
130956 /* The reset value of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */
130957 #define ALT_USB_DEV_DOEPINT12_NYETINTRPT_RESET 0x0
130958 /* Extracts the ALT_USB_DEV_DOEPINT12_NYETINTRPT field value from a register. */
130959 #define ALT_USB_DEV_DOEPINT12_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
130960 /* Produces a ALT_USB_DEV_DOEPINT12_NYETINTRPT register field value suitable for setting the register. */
130961 #define ALT_USB_DEV_DOEPINT12_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
130962 
130963 /*
130964  * Field : stuppktrcvd
130965  *
130966  * Setup Packet Received
130967  *
130968  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
130969  *
130970  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
130971  *
130972  * setup data. There is only one Setup packet per buffer. On receiving a
130973  *
130974  * Setup packet, the DWC_otg core closes the buffer and disables the
130975  *
130976  * corresponding endpoint. The application has to re-enable the endpoint to
130977  *
130978  * receive any OUT data for the Control Transfer and reprogram the buffer
130979  *
130980  * start address.
130981  *
130982  * Note: Because of the above behavior, the DWC_otg core can receive any
130983  *
130984  * number of back to back setup packets and one buffer for every setup
130985  *
130986  * packet is used.
130987  *
130988  * 1'b0: No Setup packet received
130989  *
130990  * 1'b1: Setup packet received
130991  *
130992  * Reset: 1'b0
130993  *
130994  * Field Access Macros:
130995  *
130996  */
130997 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field. */
130998 #define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_LSB 15
130999 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field. */
131000 #define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_MSB 15
131001 /* The width in bits of the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field. */
131002 #define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_WIDTH 1
131003 /* The mask used to set the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field value. */
131004 #define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_SET_MSK 0x00008000
131005 /* The mask used to clear the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field value. */
131006 #define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_CLR_MSK 0xffff7fff
131007 /* The reset value of the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field. */
131008 #define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_RESET 0x0
131009 /* Extracts the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD field value from a register. */
131010 #define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
131011 /* Produces a ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field value suitable for setting the register. */
131012 #define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
131013 
131014 #ifndef __ASSEMBLY__
131015 /*
131016  * WARNING: The C register and register group struct declarations are provided for
131017  * convenience and illustrative purposes. They should, however, be used with
131018  * caution as the C language standard provides no guarantees about the alignment or
131019  * atomicity of device memory accesses. The recommended practice for writing
131020  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
131021  * alt_write_word() functions.
131022  *
131023  * The struct declaration for register ALT_USB_DEV_DOEPINT12.
131024  */
131025 struct ALT_USB_DEV_DOEPINT12_s
131026 {
131027  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT12_XFERCOMPL */
131028  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT12_EPDISBLD */
131029  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT12_AHBERR */
131030  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT12_SETUP */
131031  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS */
131032  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT12_STSPHSERCVD */
131033  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP */
131034  uint32_t : 1; /* *UNDEFINED* */
131035  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT12_OUTPKTERR */
131036  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT12_BNAINTR */
131037  uint32_t : 1; /* *UNDEFINED* */
131038  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT12_PKTDRPSTS */
131039  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT12_BBLEERR */
131040  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT12_NAKINTRPT */
131041  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT12_NYETINTRPT */
131042  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT12_STUPPKTRCVD */
131043  uint32_t : 16; /* *UNDEFINED* */
131044 };
131045 
131046 /* The typedef declaration for register ALT_USB_DEV_DOEPINT12. */
131047 typedef volatile struct ALT_USB_DEV_DOEPINT12_s ALT_USB_DEV_DOEPINT12_t;
131048 #endif /* __ASSEMBLY__ */
131049 
131050 /* The reset value of the ALT_USB_DEV_DOEPINT12 register. */
131051 #define ALT_USB_DEV_DOEPINT12_RESET 0x00000000
131052 /* The byte offset of the ALT_USB_DEV_DOEPINT12 register from the beginning of the component. */
131053 #define ALT_USB_DEV_DOEPINT12_OFST 0x488
131054 /* The address of the ALT_USB_DEV_DOEPINT12 register. */
131055 #define ALT_USB_DEV_DOEPINT12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT12_OFST))
131056 
131057 /*
131058  * Register : doeptsiz12
131059  *
131060  * Device OUT Endpoint 12 Transfer Size Register
131061  *
131062  * Register Layout
131063  *
131064  * Bits | Access | Reset | Description
131065  * :--------|:-------|:------|:--------------------------------
131066  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ12_XFERSIZE
131067  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ12_PKTCNT
131068  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ12_RXDPID
131069  * [31] | ??? | 0x0 | *UNDEFINED*
131070  *
131071  */
131072 /*
131073  * Field : xfersize
131074  *
131075  * Transfer Size (XferSize)
131076  *
131077  * Indicates the transfer size in bytes For endpoint 0. The core
131078  *
131079  * interrupts the application only after it has exhausted the transfer
131080  *
131081  * size amount of data. The transfer size can be Set to the
131082  *
131083  * maximum packet size of the endpoint, to be interrupted at the
131084  *
131085  * end of each packet.
131086  *
131087  * The core decrements this field every time a packet is read from
131088  *
131089  * the RxFIFO and written to the external memory.
131090  *
131091  * Field Access Macros:
131092  *
131093  */
131094 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */
131095 #define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_LSB 0
131096 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */
131097 #define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_MSB 18
131098 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */
131099 #define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_WIDTH 19
131100 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field value. */
131101 #define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_SET_MSK 0x0007ffff
131102 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field value. */
131103 #define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_CLR_MSK 0xfff80000
131104 /* The reset value of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */
131105 #define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_RESET 0x0
131106 /* Extracts the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE field value from a register. */
131107 #define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
131108 /* Produces a ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field value suitable for setting the register. */
131109 #define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
131110 
131111 /*
131112  * Field : pktcnt
131113  *
131114  * Packet Count (PktCnt)
131115  *
131116  * This field is decremented to zero after a packet is written into the
131117  *
131118  * RxFIFO.
131119  *
131120  * Field Access Macros:
131121  *
131122  */
131123 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */
131124 #define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_LSB 19
131125 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */
131126 #define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_MSB 28
131127 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */
131128 #define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_WIDTH 10
131129 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field value. */
131130 #define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_SET_MSK 0x1ff80000
131131 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field value. */
131132 #define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_CLR_MSK 0xe007ffff
131133 /* The reset value of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */
131134 #define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_RESET 0x0
131135 /* Extracts the ALT_USB_DEV_DOEPTSIZ12_PKTCNT field value from a register. */
131136 #define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
131137 /* Produces a ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field value suitable for setting the register. */
131138 #define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
131139 
131140 /*
131141  * Field : rxdpid
131142  *
131143  * Applies to isochronous OUT endpoints only.
131144  *
131145  * This is the data PID received in the last packet for this endpoint.
131146  *
131147  * 2'b00: DATA0
131148  *
131149  * 2'b01: DATA2
131150  *
131151  * 2'b10: DATA1
131152  *
131153  * 2'b11: MDATA
131154  *
131155  * SETUP Packet Count (SUPCnt)
131156  *
131157  * Applies to control OUT Endpoints only.
131158  *
131159  * This field specifies the number of back-to-back SETUP data
131160  *
131161  * packets the endpoint can receive.
131162  *
131163  * 2'b01: 1 packet
131164  *
131165  * 2'b10: 2 packets
131166  *
131167  * 2'b11: 3 packets
131168  *
131169  * Field Enumeration Values:
131170  *
131171  * Enum | Value | Description
131172  * :------------------------------------------|:------|:-------------------
131173  * ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA0 | 0x0 | DATA0
131174  * ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
131175  * ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
131176  * ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
131177  *
131178  * Field Access Macros:
131179  *
131180  */
131181 /*
131182  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID
131183  *
131184  * DATA0
131185  */
131186 #define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA0 0x0
131187 /*
131188  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID
131189  *
131190  * DATA2 or 1 packet
131191  */
131192 #define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA2PKT1 0x1
131193 /*
131194  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID
131195  *
131196  * DATA1 or 2 packets
131197  */
131198 #define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA1PKT2 0x2
131199 /*
131200  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID
131201  *
131202  * MDATA or 3 packets
131203  */
131204 #define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_MDATAPKT3 0x3
131205 
131206 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */
131207 #define ALT_USB_DEV_DOEPTSIZ12_RXDPID_LSB 29
131208 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */
131209 #define ALT_USB_DEV_DOEPTSIZ12_RXDPID_MSB 30
131210 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */
131211 #define ALT_USB_DEV_DOEPTSIZ12_RXDPID_WIDTH 2
131212 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field value. */
131213 #define ALT_USB_DEV_DOEPTSIZ12_RXDPID_SET_MSK 0x60000000
131214 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field value. */
131215 #define ALT_USB_DEV_DOEPTSIZ12_RXDPID_CLR_MSK 0x9fffffff
131216 /* The reset value of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */
131217 #define ALT_USB_DEV_DOEPTSIZ12_RXDPID_RESET 0x0
131218 /* Extracts the ALT_USB_DEV_DOEPTSIZ12_RXDPID field value from a register. */
131219 #define ALT_USB_DEV_DOEPTSIZ12_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
131220 /* Produces a ALT_USB_DEV_DOEPTSIZ12_RXDPID register field value suitable for setting the register. */
131221 #define ALT_USB_DEV_DOEPTSIZ12_RXDPID_SET(value) (((value) << 29) & 0x60000000)
131222 
131223 #ifndef __ASSEMBLY__
131224 /*
131225  * WARNING: The C register and register group struct declarations are provided for
131226  * convenience and illustrative purposes. They should, however, be used with
131227  * caution as the C language standard provides no guarantees about the alignment or
131228  * atomicity of device memory accesses. The recommended practice for writing
131229  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
131230  * alt_write_word() functions.
131231  *
131232  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ12.
131233  */
131234 struct ALT_USB_DEV_DOEPTSIZ12_s
131235 {
131236  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ12_XFERSIZE */
131237  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ12_PKTCNT */
131238  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ12_RXDPID */
131239  uint32_t : 1; /* *UNDEFINED* */
131240 };
131241 
131242 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ12. */
131243 typedef volatile struct ALT_USB_DEV_DOEPTSIZ12_s ALT_USB_DEV_DOEPTSIZ12_t;
131244 #endif /* __ASSEMBLY__ */
131245 
131246 /* The reset value of the ALT_USB_DEV_DOEPTSIZ12 register. */
131247 #define ALT_USB_DEV_DOEPTSIZ12_RESET 0x00000000
131248 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ12 register from the beginning of the component. */
131249 #define ALT_USB_DEV_DOEPTSIZ12_OFST 0x490
131250 /* The address of the ALT_USB_DEV_DOEPTSIZ12 register. */
131251 #define ALT_USB_DEV_DOEPTSIZ12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ12_OFST))
131252 
131253 /*
131254  * Register : doepdma12
131255  *
131256  * Device OUT Endpoint 12 DMA Address Register
131257  *
131258  * Register Layout
131259  *
131260  * Bits | Access | Reset | Description
131261  * :-------|:-------|:--------|:--------------------------------
131262  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA12_DOEPDMA12
131263  *
131264  */
131265 /*
131266  * Field : doepdma12
131267  *
131268  * Holds the start address of the external memory for storing or fetching endpoint
131269  *
131270  * data.
131271  *
131272  * Note: For control endpoints, this field stores control OUT data packets as well
131273  * as
131274  *
131275  * SETUP transaction data packets. When more than three SETUP packets are
131276  *
131277  * received back-to-back, the SETUP data packet in the memory is overwritten.
131278  *
131279  * This register is incremented on every AHB transaction. The application can give
131280  *
131281  * only a DWORD-aligned address.
131282  *
131283  * When Scatter/Gather DMA mode is not enabled, the application programs the
131284  *
131285  * start address value in this field.
131286  *
131287  * When Scatter/Gather DMA mode is enabled, this field indicates the base
131288  *
131289  * pointer for the descriptor list.
131290  *
131291  * Field Access Macros:
131292  *
131293  */
131294 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field. */
131295 #define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_LSB 0
131296 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field. */
131297 #define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_MSB 31
131298 /* The width in bits of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field. */
131299 #define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_WIDTH 32
131300 /* The mask used to set the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field value. */
131301 #define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_SET_MSK 0xffffffff
131302 /* The mask used to clear the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field value. */
131303 #define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_CLR_MSK 0x00000000
131304 /* The reset value of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field is UNKNOWN. */
131305 #define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_RESET 0x0
131306 /* Extracts the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 field value from a register. */
131307 #define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_GET(value) (((value) & 0xffffffff) >> 0)
131308 /* Produces a ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field value suitable for setting the register. */
131309 #define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_SET(value) (((value) << 0) & 0xffffffff)
131310 
131311 #ifndef __ASSEMBLY__
131312 /*
131313  * WARNING: The C register and register group struct declarations are provided for
131314  * convenience and illustrative purposes. They should, however, be used with
131315  * caution as the C language standard provides no guarantees about the alignment or
131316  * atomicity of device memory accesses. The recommended practice for writing
131317  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
131318  * alt_write_word() functions.
131319  *
131320  * The struct declaration for register ALT_USB_DEV_DOEPDMA12.
131321  */
131322 struct ALT_USB_DEV_DOEPDMA12_s
131323 {
131324  uint32_t doepdma12 : 32; /* ALT_USB_DEV_DOEPDMA12_DOEPDMA12 */
131325 };
131326 
131327 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA12. */
131328 typedef volatile struct ALT_USB_DEV_DOEPDMA12_s ALT_USB_DEV_DOEPDMA12_t;
131329 #endif /* __ASSEMBLY__ */
131330 
131331 /* The reset value of the ALT_USB_DEV_DOEPDMA12 register. */
131332 #define ALT_USB_DEV_DOEPDMA12_RESET 0x00000000
131333 /* The byte offset of the ALT_USB_DEV_DOEPDMA12 register from the beginning of the component. */
131334 #define ALT_USB_DEV_DOEPDMA12_OFST 0x494
131335 /* The address of the ALT_USB_DEV_DOEPDMA12 register. */
131336 #define ALT_USB_DEV_DOEPDMA12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA12_OFST))
131337 
131338 /*
131339  * Register : doepdmab12
131340  *
131341  * Device OUT Endpoint 12 Buffer Address Register
131342  *
131343  * Register Layout
131344  *
131345  * Bits | Access | Reset | Description
131346  * :-------|:-------|:--------|:----------------------------------
131347  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12
131348  *
131349  */
131350 /*
131351  * Field : doepdmab12
131352  *
131353  * Holds the current buffer address.This register is updated as and when the data
131354  *
131355  * transfer for the corresponding end point is in progress.
131356  *
131357  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
131358  * is
131359  *
131360  * reserved.
131361  *
131362  * Field Access Macros:
131363  *
131364  */
131365 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field. */
131366 #define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_LSB 0
131367 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field. */
131368 #define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_MSB 31
131369 /* The width in bits of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field. */
131370 #define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_WIDTH 32
131371 /* The mask used to set the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field value. */
131372 #define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_SET_MSK 0xffffffff
131373 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field value. */
131374 #define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_CLR_MSK 0x00000000
131375 /* The reset value of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field is UNKNOWN. */
131376 #define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_RESET 0x0
131377 /* Extracts the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 field value from a register. */
131378 #define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_GET(value) (((value) & 0xffffffff) >> 0)
131379 /* Produces a ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field value suitable for setting the register. */
131380 #define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_SET(value) (((value) << 0) & 0xffffffff)
131381 
131382 #ifndef __ASSEMBLY__
131383 /*
131384  * WARNING: The C register and register group struct declarations are provided for
131385  * convenience and illustrative purposes. They should, however, be used with
131386  * caution as the C language standard provides no guarantees about the alignment or
131387  * atomicity of device memory accesses. The recommended practice for writing
131388  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
131389  * alt_write_word() functions.
131390  *
131391  * The struct declaration for register ALT_USB_DEV_DOEPDMAB12.
131392  */
131393 struct ALT_USB_DEV_DOEPDMAB12_s
131394 {
131395  const uint32_t doepdmab12 : 32; /* ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 */
131396 };
131397 
131398 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB12. */
131399 typedef volatile struct ALT_USB_DEV_DOEPDMAB12_s ALT_USB_DEV_DOEPDMAB12_t;
131400 #endif /* __ASSEMBLY__ */
131401 
131402 /* The reset value of the ALT_USB_DEV_DOEPDMAB12 register. */
131403 #define ALT_USB_DEV_DOEPDMAB12_RESET 0x00000000
131404 /* The byte offset of the ALT_USB_DEV_DOEPDMAB12 register from the beginning of the component. */
131405 #define ALT_USB_DEV_DOEPDMAB12_OFST 0x49c
131406 /* The address of the ALT_USB_DEV_DOEPDMAB12 register. */
131407 #define ALT_USB_DEV_DOEPDMAB12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB12_OFST))
131408 
131409 /*
131410  * Register : doepctl13
131411  *
131412  * Device Control OUT Endpoint 13 Control Register
131413  *
131414  * Register Layout
131415  *
131416  * Bits | Access | Reset | Description
131417  * :--------|:---------|:------|:-------------------------------
131418  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL13_MPS
131419  * [14:11] | ??? | 0x0 | *UNDEFINED*
131420  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL13_USBACTEP
131421  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL13_DPID
131422  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL13_NAKSTS
131423  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL13_EPTYPE
131424  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL13_SNP
131425  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL13_STALL
131426  * [25:22] | ??? | 0x0 | *UNDEFINED*
131427  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL13_CNAK
131428  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL13_SNAK
131429  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL13_SETD0PID
131430  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL13_SETD1PID
131431  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL13_EPDIS
131432  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL13_EPENA
131433  *
131434  */
131435 /*
131436  * Field : mps
131437  *
131438  * Maximum Packet Size (MPS)
131439  *
131440  * The application must program this field with the maximum packet size for the
131441  * current
131442  *
131443  * logical endpoint. This value is in bytes.
131444  *
131445  * Field Access Macros:
131446  *
131447  */
131448 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_MPS register field. */
131449 #define ALT_USB_DEV_DOEPCTL13_MPS_LSB 0
131450 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_MPS register field. */
131451 #define ALT_USB_DEV_DOEPCTL13_MPS_MSB 10
131452 /* The width in bits of the ALT_USB_DEV_DOEPCTL13_MPS register field. */
131453 #define ALT_USB_DEV_DOEPCTL13_MPS_WIDTH 11
131454 /* The mask used to set the ALT_USB_DEV_DOEPCTL13_MPS register field value. */
131455 #define ALT_USB_DEV_DOEPCTL13_MPS_SET_MSK 0x000007ff
131456 /* The mask used to clear the ALT_USB_DEV_DOEPCTL13_MPS register field value. */
131457 #define ALT_USB_DEV_DOEPCTL13_MPS_CLR_MSK 0xfffff800
131458 /* The reset value of the ALT_USB_DEV_DOEPCTL13_MPS register field. */
131459 #define ALT_USB_DEV_DOEPCTL13_MPS_RESET 0x0
131460 /* Extracts the ALT_USB_DEV_DOEPCTL13_MPS field value from a register. */
131461 #define ALT_USB_DEV_DOEPCTL13_MPS_GET(value) (((value) & 0x000007ff) >> 0)
131462 /* Produces a ALT_USB_DEV_DOEPCTL13_MPS register field value suitable for setting the register. */
131463 #define ALT_USB_DEV_DOEPCTL13_MPS_SET(value) (((value) << 0) & 0x000007ff)
131464 
131465 /*
131466  * Field : usbactep
131467  *
131468  * USB Active Endpoint (USBActEP)
131469  *
131470  * Indicates whether this endpoint is active in the current configuration and
131471  * interface. The
131472  *
131473  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
131474  * reset. After
131475  *
131476  * receiving the SetConfiguration and SetInterface commands, the application must
131477  *
131478  * program endpoint registers accordingly and set this bit.
131479  *
131480  * Field Enumeration Values:
131481  *
131482  * Enum | Value | Description
131483  * :--------------------------------------|:------|:--------------------
131484  * ALT_USB_DEV_DOEPCTL13_USBACTEP_E_DISD | 0x0 | Not Active
131485  * ALT_USB_DEV_DOEPCTL13_USBACTEP_E_END | 0x1 | USB Active Endpoint
131486  *
131487  * Field Access Macros:
131488  *
131489  */
131490 /*
131491  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_USBACTEP
131492  *
131493  * Not Active
131494  */
131495 #define ALT_USB_DEV_DOEPCTL13_USBACTEP_E_DISD 0x0
131496 /*
131497  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_USBACTEP
131498  *
131499  * USB Active Endpoint
131500  */
131501 #define ALT_USB_DEV_DOEPCTL13_USBACTEP_E_END 0x1
131502 
131503 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */
131504 #define ALT_USB_DEV_DOEPCTL13_USBACTEP_LSB 15
131505 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */
131506 #define ALT_USB_DEV_DOEPCTL13_USBACTEP_MSB 15
131507 /* The width in bits of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */
131508 #define ALT_USB_DEV_DOEPCTL13_USBACTEP_WIDTH 1
131509 /* The mask used to set the ALT_USB_DEV_DOEPCTL13_USBACTEP register field value. */
131510 #define ALT_USB_DEV_DOEPCTL13_USBACTEP_SET_MSK 0x00008000
131511 /* The mask used to clear the ALT_USB_DEV_DOEPCTL13_USBACTEP register field value. */
131512 #define ALT_USB_DEV_DOEPCTL13_USBACTEP_CLR_MSK 0xffff7fff
131513 /* The reset value of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */
131514 #define ALT_USB_DEV_DOEPCTL13_USBACTEP_RESET 0x0
131515 /* Extracts the ALT_USB_DEV_DOEPCTL13_USBACTEP field value from a register. */
131516 #define ALT_USB_DEV_DOEPCTL13_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
131517 /* Produces a ALT_USB_DEV_DOEPCTL13_USBACTEP register field value suitable for setting the register. */
131518 #define ALT_USB_DEV_DOEPCTL13_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
131519 
131520 /*
131521  * Field : dpid
131522  *
131523  * Endpoint Data PID (DPID)
131524  *
131525  * Applies to interrupt/bulk IN and OUT endpoints only.
131526  *
131527  * Contains the PID of the packet to be received or transmitted on this endpoint.
131528  * The
131529  *
131530  * application must program the PID of the first packet to be received or
131531  * transmitted on
131532  *
131533  * this endpoint, after the endpoint is activated. The applications use the
131534  * SetD1PID and
131535  *
131536  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
131537  *
131538  * 1'b0: DATA0
131539  *
131540  * 1'b1: DATA1
131541  *
131542  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
131543  *
131544  * DMA mode.
131545  *
131546  * 1'b0 RO
131547  *
131548  * Even/Odd (Micro)Frame (EO_FrNum)
131549  *
131550  * In non-Scatter/Gather DMA mode:
131551  *
131552  * Applies to isochronous IN and OUT endpoints only.
131553  *
131554  * Indicates the (micro)frame number in which the core transmits/receives
131555  * isochronous
131556  *
131557  * data for this endpoint. The application must program the even/odd (micro) frame
131558  *
131559  * number in which it intends to transmit/receive isochronous data for this
131560  * endpoint using
131561  *
131562  * the SetEvnFr and SetOddFr fields in this register.
131563  *
131564  * 1'b0: Even (micro)frame
131565  *
131566  * 1'b1: Odd (micro)frame
131567  *
131568  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
131569  * number
131570  *
131571  * in which to send data is provided in the transmit descriptor structure. The
131572  * frame in
131573  *
131574  * which data is received is updated in receive descriptor structure.
131575  *
131576  * Field Enumeration Values:
131577  *
131578  * Enum | Value | Description
131579  * :-----------------------------------|:------|:-----------------------------
131580  * ALT_USB_DEV_DOEPCTL13_DPID_E_INACT | 0x0 | Endpoint Data PID not active
131581  * ALT_USB_DEV_DOEPCTL13_DPID_E_ACT | 0x1 | Endpoint Data PID active
131582  *
131583  * Field Access Macros:
131584  *
131585  */
131586 /*
131587  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_DPID
131588  *
131589  * Endpoint Data PID not active
131590  */
131591 #define ALT_USB_DEV_DOEPCTL13_DPID_E_INACT 0x0
131592 /*
131593  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_DPID
131594  *
131595  * Endpoint Data PID active
131596  */
131597 #define ALT_USB_DEV_DOEPCTL13_DPID_E_ACT 0x1
131598 
131599 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_DPID register field. */
131600 #define ALT_USB_DEV_DOEPCTL13_DPID_LSB 16
131601 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_DPID register field. */
131602 #define ALT_USB_DEV_DOEPCTL13_DPID_MSB 16
131603 /* The width in bits of the ALT_USB_DEV_DOEPCTL13_DPID register field. */
131604 #define ALT_USB_DEV_DOEPCTL13_DPID_WIDTH 1
131605 /* The mask used to set the ALT_USB_DEV_DOEPCTL13_DPID register field value. */
131606 #define ALT_USB_DEV_DOEPCTL13_DPID_SET_MSK 0x00010000
131607 /* The mask used to clear the ALT_USB_DEV_DOEPCTL13_DPID register field value. */
131608 #define ALT_USB_DEV_DOEPCTL13_DPID_CLR_MSK 0xfffeffff
131609 /* The reset value of the ALT_USB_DEV_DOEPCTL13_DPID register field. */
131610 #define ALT_USB_DEV_DOEPCTL13_DPID_RESET 0x0
131611 /* Extracts the ALT_USB_DEV_DOEPCTL13_DPID field value from a register. */
131612 #define ALT_USB_DEV_DOEPCTL13_DPID_GET(value) (((value) & 0x00010000) >> 16)
131613 /* Produces a ALT_USB_DEV_DOEPCTL13_DPID register field value suitable for setting the register. */
131614 #define ALT_USB_DEV_DOEPCTL13_DPID_SET(value) (((value) << 16) & 0x00010000)
131615 
131616 /*
131617  * Field : naksts
131618  *
131619  * NAK Status (NAKSts)
131620  *
131621  * Indicates the following:
131622  *
131623  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
131624  *
131625  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
131626  *
131627  * When either the application or the core sets this bit:
131628  *
131629  * The core stops receiving any data on an OUT endpoint, even if there is space in
131630  *
131631  * the RxFIFO to accommodate the incoming packet.
131632  *
131633  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
131634  *
131635  * endpoint, even if there data is available in the TxFIFO.
131636  *
131637  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
131638  *
131639  * if there data is available in the TxFIFO.
131640  *
131641  * Irrespective of this bit's setting, the core always responds to SETUP data
131642  * packets with
131643  *
131644  * an ACK handshake.
131645  *
131646  * Field Enumeration Values:
131647  *
131648  * Enum | Value | Description
131649  * :--------------------------------------|:------|:------------------------------------------------
131650  * ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
131651  * : | | based on the FIFO status
131652  * ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
131653  * : | | endpoint
131654  *
131655  * Field Access Macros:
131656  *
131657  */
131658 /*
131659  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_NAKSTS
131660  *
131661  * The core is transmitting non-NAK handshakes based on the FIFO status
131662  */
131663 #define ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NONNAK 0x0
131664 /*
131665  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_NAKSTS
131666  *
131667  * The core is transmitting NAK handshakes on this endpoint
131668  */
131669 #define ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NAK 0x1
131670 
131671 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */
131672 #define ALT_USB_DEV_DOEPCTL13_NAKSTS_LSB 17
131673 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */
131674 #define ALT_USB_DEV_DOEPCTL13_NAKSTS_MSB 17
131675 /* The width in bits of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */
131676 #define ALT_USB_DEV_DOEPCTL13_NAKSTS_WIDTH 1
131677 /* The mask used to set the ALT_USB_DEV_DOEPCTL13_NAKSTS register field value. */
131678 #define ALT_USB_DEV_DOEPCTL13_NAKSTS_SET_MSK 0x00020000
131679 /* The mask used to clear the ALT_USB_DEV_DOEPCTL13_NAKSTS register field value. */
131680 #define ALT_USB_DEV_DOEPCTL13_NAKSTS_CLR_MSK 0xfffdffff
131681 /* The reset value of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */
131682 #define ALT_USB_DEV_DOEPCTL13_NAKSTS_RESET 0x0
131683 /* Extracts the ALT_USB_DEV_DOEPCTL13_NAKSTS field value from a register. */
131684 #define ALT_USB_DEV_DOEPCTL13_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
131685 /* Produces a ALT_USB_DEV_DOEPCTL13_NAKSTS register field value suitable for setting the register. */
131686 #define ALT_USB_DEV_DOEPCTL13_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
131687 
131688 /*
131689  * Field : eptype
131690  *
131691  * Endpoint Type (EPType)
131692  *
131693  * This is the transfer type supported by this logical endpoint.
131694  *
131695  * 2'b00: Control
131696  *
131697  * 2'b01: Isochronous
131698  *
131699  * 2'b10: Bulk
131700  *
131701  * 2'b11: Interrupt
131702  *
131703  * Field Enumeration Values:
131704  *
131705  * Enum | Value | Description
131706  * :-------------------------------------------|:------|:------------
131707  * ALT_USB_DEV_DOEPCTL13_EPTYPE_E_CTL | 0x0 | Control
131708  * ALT_USB_DEV_DOEPCTL13_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
131709  * ALT_USB_DEV_DOEPCTL13_EPTYPE_E_BULK | 0x2 | Bulk
131710  * ALT_USB_DEV_DOEPCTL13_EPTYPE_E_INTERRUP | 0x3 | Interrupt
131711  *
131712  * Field Access Macros:
131713  *
131714  */
131715 /*
131716  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE
131717  *
131718  * Control
131719  */
131720 #define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_CTL 0x0
131721 /*
131722  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE
131723  *
131724  * Isochronous
131725  */
131726 #define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_ISOCHRONOUS 0x1
131727 /*
131728  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE
131729  *
131730  * Bulk
131731  */
131732 #define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_BULK 0x2
131733 /*
131734  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE
131735  *
131736  * Interrupt
131737  */
131738 #define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_INTERRUP 0x3
131739 
131740 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */
131741 #define ALT_USB_DEV_DOEPCTL13_EPTYPE_LSB 18
131742 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */
131743 #define ALT_USB_DEV_DOEPCTL13_EPTYPE_MSB 19
131744 /* The width in bits of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */
131745 #define ALT_USB_DEV_DOEPCTL13_EPTYPE_WIDTH 2
131746 /* The mask used to set the ALT_USB_DEV_DOEPCTL13_EPTYPE register field value. */
131747 #define ALT_USB_DEV_DOEPCTL13_EPTYPE_SET_MSK 0x000c0000
131748 /* The mask used to clear the ALT_USB_DEV_DOEPCTL13_EPTYPE register field value. */
131749 #define ALT_USB_DEV_DOEPCTL13_EPTYPE_CLR_MSK 0xfff3ffff
131750 /* The reset value of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */
131751 #define ALT_USB_DEV_DOEPCTL13_EPTYPE_RESET 0x0
131752 /* Extracts the ALT_USB_DEV_DOEPCTL13_EPTYPE field value from a register. */
131753 #define ALT_USB_DEV_DOEPCTL13_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
131754 /* Produces a ALT_USB_DEV_DOEPCTL13_EPTYPE register field value suitable for setting the register. */
131755 #define ALT_USB_DEV_DOEPCTL13_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
131756 
131757 /*
131758  * Field : snp
131759  *
131760  * Snoop Mode (Snp)
131761  *
131762  * Applies to OUT endpoints only.
131763  *
131764  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
131765  *
131766  * check the correctness of OUT packets before transferring them to application
131767  * memory.
131768  *
131769  * Field Enumeration Values:
131770  *
131771  * Enum | Value | Description
131772  * :--------------------------------|:------|:-------------------
131773  * ALT_USB_DEV_DOEPCTL13_SNP_E_DIS | 0x0 | Disable Snoop Mode
131774  * ALT_USB_DEV_DOEPCTL13_SNP_E_EN | 0x1 | Enable Snoop Mode
131775  *
131776  * Field Access Macros:
131777  *
131778  */
131779 /*
131780  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNP
131781  *
131782  * Disable Snoop Mode
131783  */
131784 #define ALT_USB_DEV_DOEPCTL13_SNP_E_DIS 0x0
131785 /*
131786  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNP
131787  *
131788  * Enable Snoop Mode
131789  */
131790 #define ALT_USB_DEV_DOEPCTL13_SNP_E_EN 0x1
131791 
131792 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SNP register field. */
131793 #define ALT_USB_DEV_DOEPCTL13_SNP_LSB 20
131794 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SNP register field. */
131795 #define ALT_USB_DEV_DOEPCTL13_SNP_MSB 20
131796 /* The width in bits of the ALT_USB_DEV_DOEPCTL13_SNP register field. */
131797 #define ALT_USB_DEV_DOEPCTL13_SNP_WIDTH 1
131798 /* The mask used to set the ALT_USB_DEV_DOEPCTL13_SNP register field value. */
131799 #define ALT_USB_DEV_DOEPCTL13_SNP_SET_MSK 0x00100000
131800 /* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SNP register field value. */
131801 #define ALT_USB_DEV_DOEPCTL13_SNP_CLR_MSK 0xffefffff
131802 /* The reset value of the ALT_USB_DEV_DOEPCTL13_SNP register field. */
131803 #define ALT_USB_DEV_DOEPCTL13_SNP_RESET 0x0
131804 /* Extracts the ALT_USB_DEV_DOEPCTL13_SNP field value from a register. */
131805 #define ALT_USB_DEV_DOEPCTL13_SNP_GET(value) (((value) & 0x00100000) >> 20)
131806 /* Produces a ALT_USB_DEV_DOEPCTL13_SNP register field value suitable for setting the register. */
131807 #define ALT_USB_DEV_DOEPCTL13_SNP_SET(value) (((value) << 20) & 0x00100000)
131808 
131809 /*
131810  * Field : stall
131811  *
131812  * STALL Handshake (Stall)
131813  *
131814  * Applies to non-control, non-isochronous IN and OUT endpoints only.
131815  *
131816  * The application sets this bit to stall all tokens from the USB host to this
131817  * endpoint. If a
131818  *
131819  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
131820  * bit, the
131821  *
131822  * STALL bit takes priority. Only the application can clear this bit, never the
131823  * core.
131824  *
131825  * 1'b0 R_W
131826  *
131827  * Applies to control endpoints only.
131828  *
131829  * The application can only set this bit, and the core clears it, when a SETUP
131830  * token is
131831  *
131832  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
131833  * OUT
131834  *
131835  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
131836  * this bit's
131837  *
131838  * setting, the core always responds to SETUP data packets with an ACK handshake.
131839  *
131840  * Field Enumeration Values:
131841  *
131842  * Enum | Value | Description
131843  * :------------------------------------|:------|:----------------------------
131844  * ALT_USB_DEV_DOEPCTL13_STALL_E_INACT | 0x0 | STALL All Tokens not active
131845  * ALT_USB_DEV_DOEPCTL13_STALL_E_ACT | 0x1 | STALL All Tokens active
131846  *
131847  * Field Access Macros:
131848  *
131849  */
131850 /*
131851  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_STALL
131852  *
131853  * STALL All Tokens not active
131854  */
131855 #define ALT_USB_DEV_DOEPCTL13_STALL_E_INACT 0x0
131856 /*
131857  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_STALL
131858  *
131859  * STALL All Tokens active
131860  */
131861 #define ALT_USB_DEV_DOEPCTL13_STALL_E_ACT 0x1
131862 
131863 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_STALL register field. */
131864 #define ALT_USB_DEV_DOEPCTL13_STALL_LSB 21
131865 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_STALL register field. */
131866 #define ALT_USB_DEV_DOEPCTL13_STALL_MSB 21
131867 /* The width in bits of the ALT_USB_DEV_DOEPCTL13_STALL register field. */
131868 #define ALT_USB_DEV_DOEPCTL13_STALL_WIDTH 1
131869 /* The mask used to set the ALT_USB_DEV_DOEPCTL13_STALL register field value. */
131870 #define ALT_USB_DEV_DOEPCTL13_STALL_SET_MSK 0x00200000
131871 /* The mask used to clear the ALT_USB_DEV_DOEPCTL13_STALL register field value. */
131872 #define ALT_USB_DEV_DOEPCTL13_STALL_CLR_MSK 0xffdfffff
131873 /* The reset value of the ALT_USB_DEV_DOEPCTL13_STALL register field. */
131874 #define ALT_USB_DEV_DOEPCTL13_STALL_RESET 0x0
131875 /* Extracts the ALT_USB_DEV_DOEPCTL13_STALL field value from a register. */
131876 #define ALT_USB_DEV_DOEPCTL13_STALL_GET(value) (((value) & 0x00200000) >> 21)
131877 /* Produces a ALT_USB_DEV_DOEPCTL13_STALL register field value suitable for setting the register. */
131878 #define ALT_USB_DEV_DOEPCTL13_STALL_SET(value) (((value) << 21) & 0x00200000)
131879 
131880 /*
131881  * Field : cnak
131882  *
131883  * Clear NAK (CNAK)
131884  *
131885  * A write to this bit clears the NAK bit For the endpoint.
131886  *
131887  * Field Enumeration Values:
131888  *
131889  * Enum | Value | Description
131890  * :-----------------------------------|:------|:-------------
131891  * ALT_USB_DEV_DOEPCTL13_CNAK_E_INACT | 0x0 | No Clear NAK
131892  * ALT_USB_DEV_DOEPCTL13_CNAK_E_ACT | 0x1 | Clear NAK
131893  *
131894  * Field Access Macros:
131895  *
131896  */
131897 /*
131898  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_CNAK
131899  *
131900  * No Clear NAK
131901  */
131902 #define ALT_USB_DEV_DOEPCTL13_CNAK_E_INACT 0x0
131903 /*
131904  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_CNAK
131905  *
131906  * Clear NAK
131907  */
131908 #define ALT_USB_DEV_DOEPCTL13_CNAK_E_ACT 0x1
131909 
131910 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */
131911 #define ALT_USB_DEV_DOEPCTL13_CNAK_LSB 26
131912 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */
131913 #define ALT_USB_DEV_DOEPCTL13_CNAK_MSB 26
131914 /* The width in bits of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */
131915 #define ALT_USB_DEV_DOEPCTL13_CNAK_WIDTH 1
131916 /* The mask used to set the ALT_USB_DEV_DOEPCTL13_CNAK register field value. */
131917 #define ALT_USB_DEV_DOEPCTL13_CNAK_SET_MSK 0x04000000
131918 /* The mask used to clear the ALT_USB_DEV_DOEPCTL13_CNAK register field value. */
131919 #define ALT_USB_DEV_DOEPCTL13_CNAK_CLR_MSK 0xfbffffff
131920 /* The reset value of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */
131921 #define ALT_USB_DEV_DOEPCTL13_CNAK_RESET 0x0
131922 /* Extracts the ALT_USB_DEV_DOEPCTL13_CNAK field value from a register. */
131923 #define ALT_USB_DEV_DOEPCTL13_CNAK_GET(value) (((value) & 0x04000000) >> 26)
131924 /* Produces a ALT_USB_DEV_DOEPCTL13_CNAK register field value suitable for setting the register. */
131925 #define ALT_USB_DEV_DOEPCTL13_CNAK_SET(value) (((value) << 26) & 0x04000000)
131926 
131927 /*
131928  * Field : snak
131929  *
131930  * Set NAK (SNAK)
131931  *
131932  * A write to this bit sets the NAK bit For the endpoint.
131933  *
131934  * Using this bit, the application can control the transmission of NAK
131935  *
131936  * handshakes on an endpoint. The core can also Set this bit For an
131937  *
131938  * endpoint after a SETUP packet is received on that endpoint.
131939  *
131940  * Field Enumeration Values:
131941  *
131942  * Enum | Value | Description
131943  * :-----------------------------------|:------|:------------
131944  * ALT_USB_DEV_DOEPCTL13_SNAK_E_INACT | 0x0 | No Set NAK
131945  * ALT_USB_DEV_DOEPCTL13_SNAK_E_ACT | 0x1 | Set NAK
131946  *
131947  * Field Access Macros:
131948  *
131949  */
131950 /*
131951  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNAK
131952  *
131953  * No Set NAK
131954  */
131955 #define ALT_USB_DEV_DOEPCTL13_SNAK_E_INACT 0x0
131956 /*
131957  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNAK
131958  *
131959  * Set NAK
131960  */
131961 #define ALT_USB_DEV_DOEPCTL13_SNAK_E_ACT 0x1
131962 
131963 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */
131964 #define ALT_USB_DEV_DOEPCTL13_SNAK_LSB 27
131965 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */
131966 #define ALT_USB_DEV_DOEPCTL13_SNAK_MSB 27
131967 /* The width in bits of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */
131968 #define ALT_USB_DEV_DOEPCTL13_SNAK_WIDTH 1
131969 /* The mask used to set the ALT_USB_DEV_DOEPCTL13_SNAK register field value. */
131970 #define ALT_USB_DEV_DOEPCTL13_SNAK_SET_MSK 0x08000000
131971 /* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SNAK register field value. */
131972 #define ALT_USB_DEV_DOEPCTL13_SNAK_CLR_MSK 0xf7ffffff
131973 /* The reset value of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */
131974 #define ALT_USB_DEV_DOEPCTL13_SNAK_RESET 0x0
131975 /* Extracts the ALT_USB_DEV_DOEPCTL13_SNAK field value from a register. */
131976 #define ALT_USB_DEV_DOEPCTL13_SNAK_GET(value) (((value) & 0x08000000) >> 27)
131977 /* Produces a ALT_USB_DEV_DOEPCTL13_SNAK register field value suitable for setting the register. */
131978 #define ALT_USB_DEV_DOEPCTL13_SNAK_SET(value) (((value) << 27) & 0x08000000)
131979 
131980 /*
131981  * Field : setd0pid
131982  *
131983  * Set DATA0 PID (SetD0PID)
131984  *
131985  * Applies to interrupt/bulk IN and OUT endpoints only.
131986  *
131987  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
131988  * to DATA0.
131989  *
131990  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
131991  *
131992  * DMA mode.
131993  *
131994  * 1'b0 WO
131995  *
131996  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
131997  *
131998  * Applies to isochronous IN and OUT endpoints only.
131999  *
132000  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
132001  * (micro)
132002  *
132003  * frame.
132004  *
132005  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
132006  * number
132007  *
132008  * in which to send data is in the transmit descriptor structure. The frame in
132009  * which to
132010  *
132011  * receive data is updated in receive descriptor structure.
132012  *
132013  * Field Enumeration Values:
132014  *
132015  * Enum | Value | Description
132016  * :--------------------------------------|:------|:------------------------------------
132017  * ALT_USB_DEV_DOEPCTL13_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
132018  * ALT_USB_DEV_DOEPCTL13_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
132019  *
132020  * Field Access Macros:
132021  *
132022  */
132023 /*
132024  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD0PID
132025  *
132026  * Disables Set DATA0 PID
132027  */
132028 #define ALT_USB_DEV_DOEPCTL13_SETD0PID_E_DISD 0x0
132029 /*
132030  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD0PID
132031  *
132032  * Enables Endpoint Data PID to DATA0)
132033  */
132034 #define ALT_USB_DEV_DOEPCTL13_SETD0PID_E_END 0x1
132035 
132036 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */
132037 #define ALT_USB_DEV_DOEPCTL13_SETD0PID_LSB 28
132038 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */
132039 #define ALT_USB_DEV_DOEPCTL13_SETD0PID_MSB 28
132040 /* The width in bits of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */
132041 #define ALT_USB_DEV_DOEPCTL13_SETD0PID_WIDTH 1
132042 /* The mask used to set the ALT_USB_DEV_DOEPCTL13_SETD0PID register field value. */
132043 #define ALT_USB_DEV_DOEPCTL13_SETD0PID_SET_MSK 0x10000000
132044 /* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SETD0PID register field value. */
132045 #define ALT_USB_DEV_DOEPCTL13_SETD0PID_CLR_MSK 0xefffffff
132046 /* The reset value of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */
132047 #define ALT_USB_DEV_DOEPCTL13_SETD0PID_RESET 0x0
132048 /* Extracts the ALT_USB_DEV_DOEPCTL13_SETD0PID field value from a register. */
132049 #define ALT_USB_DEV_DOEPCTL13_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
132050 /* Produces a ALT_USB_DEV_DOEPCTL13_SETD0PID register field value suitable for setting the register. */
132051 #define ALT_USB_DEV_DOEPCTL13_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
132052 
132053 /*
132054  * Field : setd1pid
132055  *
132056  * Set DATA1 PID (SetD1PID)
132057  *
132058  * Applies to interrupt/bulk IN and OUT endpoints only.
132059  *
132060  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
132061  * to DATA1.
132062  *
132063  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
132064  *
132065  * DMA mode.
132066  *
132067  * Set Odd (micro)frame (SetOddFr)
132068  *
132069  * Applies to isochronous IN and OUT endpoints only.
132070  *
132071  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
132072  *
132073  * (micro)frame.
132074  *
132075  * This field is not applicable for Scatter/Gather DMA mode.
132076  *
132077  * Field Enumeration Values:
132078  *
132079  * Enum | Value | Description
132080  * :--------------------------------------|:------|:-----------------------
132081  * ALT_USB_DEV_DOEPCTL13_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
132082  * ALT_USB_DEV_DOEPCTL13_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
132083  *
132084  * Field Access Macros:
132085  *
132086  */
132087 /*
132088  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD1PID
132089  *
132090  * Disables Set DATA1 PID
132091  */
132092 #define ALT_USB_DEV_DOEPCTL13_SETD1PID_E_DISD 0x0
132093 /*
132094  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD1PID
132095  *
132096  * Enables Set DATA1 PID
132097  */
132098 #define ALT_USB_DEV_DOEPCTL13_SETD1PID_E_END 0x1
132099 
132100 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */
132101 #define ALT_USB_DEV_DOEPCTL13_SETD1PID_LSB 29
132102 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */
132103 #define ALT_USB_DEV_DOEPCTL13_SETD1PID_MSB 29
132104 /* The width in bits of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */
132105 #define ALT_USB_DEV_DOEPCTL13_SETD1PID_WIDTH 1
132106 /* The mask used to set the ALT_USB_DEV_DOEPCTL13_SETD1PID register field value. */
132107 #define ALT_USB_DEV_DOEPCTL13_SETD1PID_SET_MSK 0x20000000
132108 /* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SETD1PID register field value. */
132109 #define ALT_USB_DEV_DOEPCTL13_SETD1PID_CLR_MSK 0xdfffffff
132110 /* The reset value of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */
132111 #define ALT_USB_DEV_DOEPCTL13_SETD1PID_RESET 0x0
132112 /* Extracts the ALT_USB_DEV_DOEPCTL13_SETD1PID field value from a register. */
132113 #define ALT_USB_DEV_DOEPCTL13_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
132114 /* Produces a ALT_USB_DEV_DOEPCTL13_SETD1PID register field value suitable for setting the register. */
132115 #define ALT_USB_DEV_DOEPCTL13_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
132116 
132117 /*
132118  * Field : epdis
132119  *
132120  * Endpoint Disable (EPDis)
132121  *
132122  * Applies to IN and OUT endpoints.
132123  *
132124  * The application sets this bit to stop transmitting/receiving data on an
132125  * endpoint, even
132126  *
132127  * before the transfer for that endpoint is complete. The application must wait for
132128  * the
132129  *
132130  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
132131  * clears
132132  *
132133  * this bit before setting the Endpoint Disabled interrupt. The application must
132134  * set this bit
132135  *
132136  * only if Endpoint Enable is already set for this endpoint.
132137  *
132138  * Field Enumeration Values:
132139  *
132140  * Enum | Value | Description
132141  * :------------------------------------|:------|:--------------------
132142  * ALT_USB_DEV_DOEPCTL13_EPDIS_E_INACT | 0x0 | No Endpoint Disable
132143  * ALT_USB_DEV_DOEPCTL13_EPDIS_E_ACT | 0x1 | Endpoint Disable
132144  *
132145  * Field Access Macros:
132146  *
132147  */
132148 /*
132149  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPDIS
132150  *
132151  * No Endpoint Disable
132152  */
132153 #define ALT_USB_DEV_DOEPCTL13_EPDIS_E_INACT 0x0
132154 /*
132155  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPDIS
132156  *
132157  * Endpoint Disable
132158  */
132159 #define ALT_USB_DEV_DOEPCTL13_EPDIS_E_ACT 0x1
132160 
132161 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */
132162 #define ALT_USB_DEV_DOEPCTL13_EPDIS_LSB 30
132163 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */
132164 #define ALT_USB_DEV_DOEPCTL13_EPDIS_MSB 30
132165 /* The width in bits of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */
132166 #define ALT_USB_DEV_DOEPCTL13_EPDIS_WIDTH 1
132167 /* The mask used to set the ALT_USB_DEV_DOEPCTL13_EPDIS register field value. */
132168 #define ALT_USB_DEV_DOEPCTL13_EPDIS_SET_MSK 0x40000000
132169 /* The mask used to clear the ALT_USB_DEV_DOEPCTL13_EPDIS register field value. */
132170 #define ALT_USB_DEV_DOEPCTL13_EPDIS_CLR_MSK 0xbfffffff
132171 /* The reset value of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */
132172 #define ALT_USB_DEV_DOEPCTL13_EPDIS_RESET 0x0
132173 /* Extracts the ALT_USB_DEV_DOEPCTL13_EPDIS field value from a register. */
132174 #define ALT_USB_DEV_DOEPCTL13_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
132175 /* Produces a ALT_USB_DEV_DOEPCTL13_EPDIS register field value suitable for setting the register. */
132176 #define ALT_USB_DEV_DOEPCTL13_EPDIS_SET(value) (((value) << 30) & 0x40000000)
132177 
132178 /*
132179  * Field : epena
132180  *
132181  * Endpoint Enable (EPEna)
132182  *
132183  * Applies to IN and OUT endpoints.
132184  *
132185  * When Scatter/Gather DMA mode is enabled,
132186  *
132187  * For IN endpoints this bit indicates that the descriptor structure and data
132188  * buffer with
132189  *
132190  * data ready to transmit is setup.
132191  *
132192  * For OUT endpoint it indicates that the descriptor structure and data buffer to
132193  *
132194  * receive data is setup.
132195  *
132196  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
132197  *
132198  * DMA mode:
132199  *
132200  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
132201  * the
132202  *
132203  * endpoint.
132204  *
132205  * * For OUT endpoints, this bit indicates that the application has allocated the
132206  *
132207  * memory to start receiving data from the USB.
132208  *
132209  * * The core clears this bit before setting any of the following interrupts on
132210  * this
132211  *
132212  * endpoint:
132213  *
132214  * SETUP Phase Done
132215  *
132216  * Endpoint Disabled
132217  *
132218  * Transfer Completed
132219  *
132220  * Note: For control endpoints in DMA mode, this bit must be set to be able to
132221  * transfer
132222  *
132223  * SETUP data packets in memory.
132224  *
132225  * Field Enumeration Values:
132226  *
132227  * Enum | Value | Description
132228  * :------------------------------------|:------|:-------------------------
132229  * ALT_USB_DEV_DOEPCTL13_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
132230  * ALT_USB_DEV_DOEPCTL13_EPENA_E_ACT | 0x1 | Endpoint Enable active
132231  *
132232  * Field Access Macros:
132233  *
132234  */
132235 /*
132236  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPENA
132237  *
132238  * Endpoint Enable inactive
132239  */
132240 #define ALT_USB_DEV_DOEPCTL13_EPENA_E_INACT 0x0
132241 /*
132242  * Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPENA
132243  *
132244  * Endpoint Enable active
132245  */
132246 #define ALT_USB_DEV_DOEPCTL13_EPENA_E_ACT 0x1
132247 
132248 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */
132249 #define ALT_USB_DEV_DOEPCTL13_EPENA_LSB 31
132250 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */
132251 #define ALT_USB_DEV_DOEPCTL13_EPENA_MSB 31
132252 /* The width in bits of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */
132253 #define ALT_USB_DEV_DOEPCTL13_EPENA_WIDTH 1
132254 /* The mask used to set the ALT_USB_DEV_DOEPCTL13_EPENA register field value. */
132255 #define ALT_USB_DEV_DOEPCTL13_EPENA_SET_MSK 0x80000000
132256 /* The mask used to clear the ALT_USB_DEV_DOEPCTL13_EPENA register field value. */
132257 #define ALT_USB_DEV_DOEPCTL13_EPENA_CLR_MSK 0x7fffffff
132258 /* The reset value of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */
132259 #define ALT_USB_DEV_DOEPCTL13_EPENA_RESET 0x0
132260 /* Extracts the ALT_USB_DEV_DOEPCTL13_EPENA field value from a register. */
132261 #define ALT_USB_DEV_DOEPCTL13_EPENA_GET(value) (((value) & 0x80000000) >> 31)
132262 /* Produces a ALT_USB_DEV_DOEPCTL13_EPENA register field value suitable for setting the register. */
132263 #define ALT_USB_DEV_DOEPCTL13_EPENA_SET(value) (((value) << 31) & 0x80000000)
132264 
132265 #ifndef __ASSEMBLY__
132266 /*
132267  * WARNING: The C register and register group struct declarations are provided for
132268  * convenience and illustrative purposes. They should, however, be used with
132269  * caution as the C language standard provides no guarantees about the alignment or
132270  * atomicity of device memory accesses. The recommended practice for writing
132271  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
132272  * alt_write_word() functions.
132273  *
132274  * The struct declaration for register ALT_USB_DEV_DOEPCTL13.
132275  */
132276 struct ALT_USB_DEV_DOEPCTL13_s
132277 {
132278  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL13_MPS */
132279  uint32_t : 4; /* *UNDEFINED* */
132280  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL13_USBACTEP */
132281  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL13_DPID */
132282  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL13_NAKSTS */
132283  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL13_EPTYPE */
132284  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL13_SNP */
132285  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL13_STALL */
132286  uint32_t : 4; /* *UNDEFINED* */
132287  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL13_CNAK */
132288  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL13_SNAK */
132289  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL13_SETD0PID */
132290  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL13_SETD1PID */
132291  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL13_EPDIS */
132292  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL13_EPENA */
132293 };
132294 
132295 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL13. */
132296 typedef volatile struct ALT_USB_DEV_DOEPCTL13_s ALT_USB_DEV_DOEPCTL13_t;
132297 #endif /* __ASSEMBLY__ */
132298 
132299 /* The reset value of the ALT_USB_DEV_DOEPCTL13 register. */
132300 #define ALT_USB_DEV_DOEPCTL13_RESET 0x00000000
132301 /* The byte offset of the ALT_USB_DEV_DOEPCTL13 register from the beginning of the component. */
132302 #define ALT_USB_DEV_DOEPCTL13_OFST 0x4a0
132303 /* The address of the ALT_USB_DEV_DOEPCTL13 register. */
132304 #define ALT_USB_DEV_DOEPCTL13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL13_OFST))
132305 
132306 /*
132307  * Register : doepint13
132308  *
132309  * Device OUT Endpoint 13 Interrupt Register
132310  *
132311  * Register Layout
132312  *
132313  * Bits | Access | Reset | Description
132314  * :--------|:-------|:------|:-------------------------------------
132315  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_XFERCOMPL
132316  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_EPDISBLD
132317  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_AHBERR
132318  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_SETUP
132319  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS
132320  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_STSPHSERCVD
132321  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP
132322  * [7] | ??? | 0x0 | *UNDEFINED*
132323  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_OUTPKTERR
132324  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_BNAINTR
132325  * [10] | ??? | 0x0 | *UNDEFINED*
132326  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_PKTDRPSTS
132327  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_BBLEERR
132328  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_NAKINTRPT
132329  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_NYETINTRPT
132330  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_STUPPKTRCVD
132331  * [31:16] | ??? | 0x0 | *UNDEFINED*
132332  *
132333  */
132334 /*
132335  * Field : xfercompl
132336  *
132337  * Transfer Completed Interrupt (XferCompl)
132338  *
132339  * Applies to IN and OUT endpoints.
132340  *
132341  * When Scatter/Gather DMA mode is enabled
132342  *
132343  * * For IN endpoint this field indicates that the requested data
132344  *
132345  * from the descriptor is moved from external system memory
132346  *
132347  * to internal FIFO.
132348  *
132349  * * For OUT endpoint this field indicates that the requested
132350  *
132351  * data from the internal FIFO is moved to external system
132352  *
132353  * memory. This interrupt is generated only when the
132354  *
132355  * corresponding endpoint descriptor is closed, and the IOC
132356  *
132357  * bit For the corresponding descriptor is Set.
132358  *
132359  * When Scatter/Gather DMA mode is disabled, this field
132360  *
132361  * indicates that the programmed transfer is complete on the
132362  *
132363  * AHB as well as on the USB, For this endpoint.
132364  *
132365  * Field Enumeration Values:
132366  *
132367  * Enum | Value | Description
132368  * :----------------------------------------|:------|:-----------------------------
132369  * ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_INACT | 0x0 | No Interrupt
132370  * ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
132371  *
132372  * Field Access Macros:
132373  *
132374  */
132375 /*
132376  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_XFERCOMPL
132377  *
132378  * No Interrupt
132379  */
132380 #define ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_INACT 0x0
132381 /*
132382  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_XFERCOMPL
132383  *
132384  * Transfer Completed Interrupt
132385  */
132386 #define ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_ACT 0x1
132387 
132388 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */
132389 #define ALT_USB_DEV_DOEPINT13_XFERCOMPL_LSB 0
132390 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */
132391 #define ALT_USB_DEV_DOEPINT13_XFERCOMPL_MSB 0
132392 /* The width in bits of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */
132393 #define ALT_USB_DEV_DOEPINT13_XFERCOMPL_WIDTH 1
132394 /* The mask used to set the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field value. */
132395 #define ALT_USB_DEV_DOEPINT13_XFERCOMPL_SET_MSK 0x00000001
132396 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field value. */
132397 #define ALT_USB_DEV_DOEPINT13_XFERCOMPL_CLR_MSK 0xfffffffe
132398 /* The reset value of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */
132399 #define ALT_USB_DEV_DOEPINT13_XFERCOMPL_RESET 0x0
132400 /* Extracts the ALT_USB_DEV_DOEPINT13_XFERCOMPL field value from a register. */
132401 #define ALT_USB_DEV_DOEPINT13_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
132402 /* Produces a ALT_USB_DEV_DOEPINT13_XFERCOMPL register field value suitable for setting the register. */
132403 #define ALT_USB_DEV_DOEPINT13_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
132404 
132405 /*
132406  * Field : epdisbld
132407  *
132408  * Endpoint Disabled Interrupt (EPDisbld)
132409  *
132410  * Applies to IN and OUT endpoints.
132411  *
132412  * This bit indicates that the endpoint is disabled per the
132413  *
132414  * application's request.
132415  *
132416  * Field Enumeration Values:
132417  *
132418  * Enum | Value | Description
132419  * :---------------------------------------|:------|:----------------------------
132420  * ALT_USB_DEV_DOEPINT13_EPDISBLD_E_INACT | 0x0 | No Interrupt
132421  * ALT_USB_DEV_DOEPINT13_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
132422  *
132423  * Field Access Macros:
132424  *
132425  */
132426 /*
132427  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_EPDISBLD
132428  *
132429  * No Interrupt
132430  */
132431 #define ALT_USB_DEV_DOEPINT13_EPDISBLD_E_INACT 0x0
132432 /*
132433  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_EPDISBLD
132434  *
132435  * Endpoint Disabled Interrupt
132436  */
132437 #define ALT_USB_DEV_DOEPINT13_EPDISBLD_E_ACT 0x1
132438 
132439 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */
132440 #define ALT_USB_DEV_DOEPINT13_EPDISBLD_LSB 1
132441 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */
132442 #define ALT_USB_DEV_DOEPINT13_EPDISBLD_MSB 1
132443 /* The width in bits of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */
132444 #define ALT_USB_DEV_DOEPINT13_EPDISBLD_WIDTH 1
132445 /* The mask used to set the ALT_USB_DEV_DOEPINT13_EPDISBLD register field value. */
132446 #define ALT_USB_DEV_DOEPINT13_EPDISBLD_SET_MSK 0x00000002
132447 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_EPDISBLD register field value. */
132448 #define ALT_USB_DEV_DOEPINT13_EPDISBLD_CLR_MSK 0xfffffffd
132449 /* The reset value of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */
132450 #define ALT_USB_DEV_DOEPINT13_EPDISBLD_RESET 0x0
132451 /* Extracts the ALT_USB_DEV_DOEPINT13_EPDISBLD field value from a register. */
132452 #define ALT_USB_DEV_DOEPINT13_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
132453 /* Produces a ALT_USB_DEV_DOEPINT13_EPDISBLD register field value suitable for setting the register. */
132454 #define ALT_USB_DEV_DOEPINT13_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
132455 
132456 /*
132457  * Field : ahberr
132458  *
132459  * AHB Error (AHBErr)
132460  *
132461  * Applies to IN and OUT endpoints.
132462  *
132463  * This is generated only in Internal DMA mode when there is an
132464  *
132465  * AHB error during an AHB read/write. The application can read
132466  *
132467  * the corresponding endpoint DMA address register to get the
132468  *
132469  * error address.
132470  *
132471  * Field Enumeration Values:
132472  *
132473  * Enum | Value | Description
132474  * :-------------------------------------|:------|:--------------------
132475  * ALT_USB_DEV_DOEPINT13_AHBERR_E_INACT | 0x0 | No Interrupt
132476  * ALT_USB_DEV_DOEPINT13_AHBERR_E_ACT | 0x1 | AHB Error interrupt
132477  *
132478  * Field Access Macros:
132479  *
132480  */
132481 /*
132482  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_AHBERR
132483  *
132484  * No Interrupt
132485  */
132486 #define ALT_USB_DEV_DOEPINT13_AHBERR_E_INACT 0x0
132487 /*
132488  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_AHBERR
132489  *
132490  * AHB Error interrupt
132491  */
132492 #define ALT_USB_DEV_DOEPINT13_AHBERR_E_ACT 0x1
132493 
132494 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */
132495 #define ALT_USB_DEV_DOEPINT13_AHBERR_LSB 2
132496 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */
132497 #define ALT_USB_DEV_DOEPINT13_AHBERR_MSB 2
132498 /* The width in bits of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */
132499 #define ALT_USB_DEV_DOEPINT13_AHBERR_WIDTH 1
132500 /* The mask used to set the ALT_USB_DEV_DOEPINT13_AHBERR register field value. */
132501 #define ALT_USB_DEV_DOEPINT13_AHBERR_SET_MSK 0x00000004
132502 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_AHBERR register field value. */
132503 #define ALT_USB_DEV_DOEPINT13_AHBERR_CLR_MSK 0xfffffffb
132504 /* The reset value of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */
132505 #define ALT_USB_DEV_DOEPINT13_AHBERR_RESET 0x0
132506 /* Extracts the ALT_USB_DEV_DOEPINT13_AHBERR field value from a register. */
132507 #define ALT_USB_DEV_DOEPINT13_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
132508 /* Produces a ALT_USB_DEV_DOEPINT13_AHBERR register field value suitable for setting the register. */
132509 #define ALT_USB_DEV_DOEPINT13_AHBERR_SET(value) (((value) << 2) & 0x00000004)
132510 
132511 /*
132512  * Field : setup
132513  *
132514  * SETUP Phase Done (SetUp)
132515  *
132516  * Applies to control OUT endpoints only.
132517  *
132518  * Indicates that the SETUP phase For the control endpoint is
132519  *
132520  * complete and no more back-to-back SETUP packets were
132521  *
132522  * received For the current control transfer. On this interrupt, the
132523  *
132524  * application can decode the received SETUP data packet.
132525  *
132526  * Field Enumeration Values:
132527  *
132528  * Enum | Value | Description
132529  * :------------------------------------|:------|:--------------------
132530  * ALT_USB_DEV_DOEPINT13_SETUP_E_INACT | 0x0 | No SETUP Phase Done
132531  * ALT_USB_DEV_DOEPINT13_SETUP_E_ACT | 0x1 | SETUP Phase Done
132532  *
132533  * Field Access Macros:
132534  *
132535  */
132536 /*
132537  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_SETUP
132538  *
132539  * No SETUP Phase Done
132540  */
132541 #define ALT_USB_DEV_DOEPINT13_SETUP_E_INACT 0x0
132542 /*
132543  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_SETUP
132544  *
132545  * SETUP Phase Done
132546  */
132547 #define ALT_USB_DEV_DOEPINT13_SETUP_E_ACT 0x1
132548 
132549 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_SETUP register field. */
132550 #define ALT_USB_DEV_DOEPINT13_SETUP_LSB 3
132551 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_SETUP register field. */
132552 #define ALT_USB_DEV_DOEPINT13_SETUP_MSB 3
132553 /* The width in bits of the ALT_USB_DEV_DOEPINT13_SETUP register field. */
132554 #define ALT_USB_DEV_DOEPINT13_SETUP_WIDTH 1
132555 /* The mask used to set the ALT_USB_DEV_DOEPINT13_SETUP register field value. */
132556 #define ALT_USB_DEV_DOEPINT13_SETUP_SET_MSK 0x00000008
132557 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_SETUP register field value. */
132558 #define ALT_USB_DEV_DOEPINT13_SETUP_CLR_MSK 0xfffffff7
132559 /* The reset value of the ALT_USB_DEV_DOEPINT13_SETUP register field. */
132560 #define ALT_USB_DEV_DOEPINT13_SETUP_RESET 0x0
132561 /* Extracts the ALT_USB_DEV_DOEPINT13_SETUP field value from a register. */
132562 #define ALT_USB_DEV_DOEPINT13_SETUP_GET(value) (((value) & 0x00000008) >> 3)
132563 /* Produces a ALT_USB_DEV_DOEPINT13_SETUP register field value suitable for setting the register. */
132564 #define ALT_USB_DEV_DOEPINT13_SETUP_SET(value) (((value) << 3) & 0x00000008)
132565 
132566 /*
132567  * Field : outtknepdis
132568  *
132569  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
132570  *
132571  * Applies only to control OUT endpoints.
132572  *
132573  * Indicates that an OUT token was received when the endpoint
132574  *
132575  * was not yet enabled. This interrupt is asserted on the endpoint
132576  *
132577  * For which the OUT token was received.
132578  *
132579  * Field Enumeration Values:
132580  *
132581  * Enum | Value | Description
132582  * :------------------------------------------|:------|:---------------------------------------------
132583  * ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
132584  * ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
132585  *
132586  * Field Access Macros:
132587  *
132588  */
132589 /*
132590  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS
132591  *
132592  * No OUT Token Received When Endpoint Disabled
132593  */
132594 #define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_INACT 0x0
132595 /*
132596  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS
132597  *
132598  * OUT Token Received When Endpoint Disabled
132599  */
132600 #define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_ACT 0x1
132601 
132602 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */
132603 #define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_LSB 4
132604 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */
132605 #define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_MSB 4
132606 /* The width in bits of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */
132607 #define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_WIDTH 1
132608 /* The mask used to set the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field value. */
132609 #define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_SET_MSK 0x00000010
132610 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field value. */
132611 #define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_CLR_MSK 0xffffffef
132612 /* The reset value of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */
132613 #define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_RESET 0x0
132614 /* Extracts the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS field value from a register. */
132615 #define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
132616 /* Produces a ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field value suitable for setting the register. */
132617 #define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
132618 
132619 /*
132620  * Field : stsphsercvd
132621  *
132622  * Status Phase Received For Control Write (StsPhseRcvd)
132623  *
132624  * This interrupt is valid only For Control OUT endpoints and only in
132625  *
132626  * Scatter Gather DMA mode.
132627  *
132628  * This interrupt is generated only after the core has transferred all
132629  *
132630  * the data that the host has sent during the data phase of a control
132631  *
132632  * write transfer, to the system memory buffer.
132633  *
132634  * The interrupt indicates to the application that the host has
132635  *
132636  * switched from data phase to the status phase of a Control Write
132637  *
132638  * transfer. The application can use this interrupt to ACK or STALL
132639  *
132640  * the Status phase, after it has decoded the data phase. This is
132641  *
132642  * applicable only in Case of Scatter Gather DMA mode.
132643  *
132644  * Field Enumeration Values:
132645  *
132646  * Enum | Value | Description
132647  * :------------------------------------------|:------|:-------------------------------------------
132648  * ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
132649  * ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
132650  *
132651  * Field Access Macros:
132652  *
132653  */
132654 /*
132655  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_STSPHSERCVD
132656  *
132657  * No Status Phase Received for Control Write
132658  */
132659 #define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_INACT 0x0
132660 /*
132661  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_STSPHSERCVD
132662  *
132663  * Status Phase Received for Control Write
132664  */
132665 #define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_ACT 0x1
132666 
132667 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */
132668 #define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_LSB 5
132669 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */
132670 #define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_MSB 5
132671 /* The width in bits of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */
132672 #define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_WIDTH 1
132673 /* The mask used to set the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field value. */
132674 #define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_SET_MSK 0x00000020
132675 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field value. */
132676 #define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_CLR_MSK 0xffffffdf
132677 /* The reset value of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */
132678 #define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_RESET 0x0
132679 /* Extracts the ALT_USB_DEV_DOEPINT13_STSPHSERCVD field value from a register. */
132680 #define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
132681 /* Produces a ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field value suitable for setting the register. */
132682 #define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
132683 
132684 /*
132685  * Field : back2backsetup
132686  *
132687  * Back-to-Back SETUP Packets Received (Back2BackSETup)
132688  *
132689  * Applies to Control OUT endpoints only.
132690  *
132691  * This bit indicates that the core has received more than three
132692  *
132693  * back-to-back SETUP packets For this particular endpoint. For
132694  *
132695  * information about handling this interrupt,
132696  *
132697  * Field Enumeration Values:
132698  *
132699  * Enum | Value | Description
132700  * :---------------------------------------------|:------|:---------------------------------------
132701  * ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
132702  * ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
132703  *
132704  * Field Access Macros:
132705  *
132706  */
132707 /*
132708  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP
132709  *
132710  * No Back-to-Back SETUP Packets Received
132711  */
132712 #define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_INACT 0x0
132713 /*
132714  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP
132715  *
132716  * Back-to-Back SETUP Packets Received
132717  */
132718 #define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_ACT 0x1
132719 
132720 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */
132721 #define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_LSB 6
132722 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */
132723 #define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_MSB 6
132724 /* The width in bits of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */
132725 #define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_WIDTH 1
132726 /* The mask used to set the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field value. */
132727 #define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_SET_MSK 0x00000040
132728 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field value. */
132729 #define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_CLR_MSK 0xffffffbf
132730 /* The reset value of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */
132731 #define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_RESET 0x0
132732 /* Extracts the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP field value from a register. */
132733 #define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
132734 /* Produces a ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field value suitable for setting the register. */
132735 #define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
132736 
132737 /*
132738  * Field : outpkterr
132739  *
132740  * OUT Packet Error (OutPktErr)
132741  *
132742  * Applies to OUT endpoints Only
132743  *
132744  * This interrupt is valid only when thresholding is enabled. This interrupt is
132745  * asserted when the
132746  *
132747  * core detects an overflow or a CRC error For non-Isochronous
132748  *
132749  * OUT packet.
132750  *
132751  * Field Enumeration Values:
132752  *
132753  * Enum | Value | Description
132754  * :----------------------------------------|:------|:--------------------
132755  * ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
132756  * ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
132757  *
132758  * Field Access Macros:
132759  *
132760  */
132761 /*
132762  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTPKTERR
132763  *
132764  * No OUT Packet Error
132765  */
132766 #define ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_INACT 0x0
132767 /*
132768  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTPKTERR
132769  *
132770  * OUT Packet Error
132771  */
132772 #define ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_ACT 0x1
132773 
132774 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */
132775 #define ALT_USB_DEV_DOEPINT13_OUTPKTERR_LSB 8
132776 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */
132777 #define ALT_USB_DEV_DOEPINT13_OUTPKTERR_MSB 8
132778 /* The width in bits of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */
132779 #define ALT_USB_DEV_DOEPINT13_OUTPKTERR_WIDTH 1
132780 /* The mask used to set the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field value. */
132781 #define ALT_USB_DEV_DOEPINT13_OUTPKTERR_SET_MSK 0x00000100
132782 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field value. */
132783 #define ALT_USB_DEV_DOEPINT13_OUTPKTERR_CLR_MSK 0xfffffeff
132784 /* The reset value of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */
132785 #define ALT_USB_DEV_DOEPINT13_OUTPKTERR_RESET 0x0
132786 /* Extracts the ALT_USB_DEV_DOEPINT13_OUTPKTERR field value from a register. */
132787 #define ALT_USB_DEV_DOEPINT13_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
132788 /* Produces a ALT_USB_DEV_DOEPINT13_OUTPKTERR register field value suitable for setting the register. */
132789 #define ALT_USB_DEV_DOEPINT13_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
132790 
132791 /*
132792  * Field : bnaintr
132793  *
132794  * BNA (Buffer Not Available) Interrupt (BNAIntr)
132795  *
132796  * This bit is valid only when Scatter/Gather DMA mode is enabled.
132797  *
132798  * The core generates this interrupt when the descriptor accessed
132799  *
132800  * is not ready For the Core to process, such as Host busy or DMA
132801  *
132802  * done
132803  *
132804  * Field Enumeration Values:
132805  *
132806  * Enum | Value | Description
132807  * :--------------------------------------|:------|:--------------
132808  * ALT_USB_DEV_DOEPINT13_BNAINTR_E_INACT | 0x0 | No interrupt
132809  * ALT_USB_DEV_DOEPINT13_BNAINTR_E_ACT | 0x1 | BNA interrupt
132810  *
132811  * Field Access Macros:
132812  *
132813  */
132814 /*
132815  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BNAINTR
132816  *
132817  * No interrupt
132818  */
132819 #define ALT_USB_DEV_DOEPINT13_BNAINTR_E_INACT 0x0
132820 /*
132821  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BNAINTR
132822  *
132823  * BNA interrupt
132824  */
132825 #define ALT_USB_DEV_DOEPINT13_BNAINTR_E_ACT 0x1
132826 
132827 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */
132828 #define ALT_USB_DEV_DOEPINT13_BNAINTR_LSB 9
132829 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */
132830 #define ALT_USB_DEV_DOEPINT13_BNAINTR_MSB 9
132831 /* The width in bits of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */
132832 #define ALT_USB_DEV_DOEPINT13_BNAINTR_WIDTH 1
132833 /* The mask used to set the ALT_USB_DEV_DOEPINT13_BNAINTR register field value. */
132834 #define ALT_USB_DEV_DOEPINT13_BNAINTR_SET_MSK 0x00000200
132835 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_BNAINTR register field value. */
132836 #define ALT_USB_DEV_DOEPINT13_BNAINTR_CLR_MSK 0xfffffdff
132837 /* The reset value of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */
132838 #define ALT_USB_DEV_DOEPINT13_BNAINTR_RESET 0x0
132839 /* Extracts the ALT_USB_DEV_DOEPINT13_BNAINTR field value from a register. */
132840 #define ALT_USB_DEV_DOEPINT13_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
132841 /* Produces a ALT_USB_DEV_DOEPINT13_BNAINTR register field value suitable for setting the register. */
132842 #define ALT_USB_DEV_DOEPINT13_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
132843 
132844 /*
132845  * Field : pktdrpsts
132846  *
132847  * Packet Drop Status (PktDrpSts)
132848  *
132849  * This bit indicates to the application that an ISOC OUT packet has been dropped.
132850  * This
132851  *
132852  * bit does not have an associated mask bit and does not generate an interrupt.
132853  *
132854  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
132855  * transfer
132856  *
132857  * interrupt feature is selected.
132858  *
132859  * Field Enumeration Values:
132860  *
132861  * Enum | Value | Description
132862  * :----------------------------------------|:------|:-----------------------------
132863  * ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_INACT | 0x0 | No interrupt
132864  * ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
132865  *
132866  * Field Access Macros:
132867  *
132868  */
132869 /*
132870  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_PKTDRPSTS
132871  *
132872  * No interrupt
132873  */
132874 #define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_INACT 0x0
132875 /*
132876  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_PKTDRPSTS
132877  *
132878  * Packet Drop Status interrupt
132879  */
132880 #define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_ACT 0x1
132881 
132882 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */
132883 #define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_LSB 11
132884 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */
132885 #define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_MSB 11
132886 /* The width in bits of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */
132887 #define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_WIDTH 1
132888 /* The mask used to set the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field value. */
132889 #define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_SET_MSK 0x00000800
132890 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field value. */
132891 #define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_CLR_MSK 0xfffff7ff
132892 /* The reset value of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */
132893 #define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_RESET 0x0
132894 /* Extracts the ALT_USB_DEV_DOEPINT13_PKTDRPSTS field value from a register. */
132895 #define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
132896 /* Produces a ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field value suitable for setting the register. */
132897 #define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
132898 
132899 /*
132900  * Field : bbleerr
132901  *
132902  * NAK Interrupt (BbleErr)
132903  *
132904  * The core generates this interrupt when babble is received for the endpoint.
132905  *
132906  * Field Enumeration Values:
132907  *
132908  * Enum | Value | Description
132909  * :--------------------------------------|:------|:------------------
132910  * ALT_USB_DEV_DOEPINT13_BBLEERR_E_INACT | 0x0 | No interrupt
132911  * ALT_USB_DEV_DOEPINT13_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
132912  *
132913  * Field Access Macros:
132914  *
132915  */
132916 /*
132917  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BBLEERR
132918  *
132919  * No interrupt
132920  */
132921 #define ALT_USB_DEV_DOEPINT13_BBLEERR_E_INACT 0x0
132922 /*
132923  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_BBLEERR
132924  *
132925  * BbleErr interrupt
132926  */
132927 #define ALT_USB_DEV_DOEPINT13_BBLEERR_E_ACT 0x1
132928 
132929 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */
132930 #define ALT_USB_DEV_DOEPINT13_BBLEERR_LSB 12
132931 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */
132932 #define ALT_USB_DEV_DOEPINT13_BBLEERR_MSB 12
132933 /* The width in bits of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */
132934 #define ALT_USB_DEV_DOEPINT13_BBLEERR_WIDTH 1
132935 /* The mask used to set the ALT_USB_DEV_DOEPINT13_BBLEERR register field value. */
132936 #define ALT_USB_DEV_DOEPINT13_BBLEERR_SET_MSK 0x00001000
132937 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_BBLEERR register field value. */
132938 #define ALT_USB_DEV_DOEPINT13_BBLEERR_CLR_MSK 0xffffefff
132939 /* The reset value of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */
132940 #define ALT_USB_DEV_DOEPINT13_BBLEERR_RESET 0x0
132941 /* Extracts the ALT_USB_DEV_DOEPINT13_BBLEERR field value from a register. */
132942 #define ALT_USB_DEV_DOEPINT13_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
132943 /* Produces a ALT_USB_DEV_DOEPINT13_BBLEERR register field value suitable for setting the register. */
132944 #define ALT_USB_DEV_DOEPINT13_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
132945 
132946 /*
132947  * Field : nakintrpt
132948  *
132949  * NAK Interrupt (NAKInterrupt)
132950  *
132951  * The core generates this interrupt when a NAK is transmitted or received by the
132952  * device.
132953  *
132954  * In case of isochronous IN endpoints the interrupt gets generated when a zero
132955  * length
132956  *
132957  * packet is transmitted due to un-availability of data in the TXFifo.
132958  *
132959  * Field Enumeration Values:
132960  *
132961  * Enum | Value | Description
132962  * :----------------------------------------|:------|:--------------
132963  * ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_INACT | 0x0 | No interrupt
132964  * ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
132965  *
132966  * Field Access Macros:
132967  *
132968  */
132969 /*
132970  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_NAKINTRPT
132971  *
132972  * No interrupt
132973  */
132974 #define ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_INACT 0x0
132975 /*
132976  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_NAKINTRPT
132977  *
132978  * NAK Interrupt
132979  */
132980 #define ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_ACT 0x1
132981 
132982 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */
132983 #define ALT_USB_DEV_DOEPINT13_NAKINTRPT_LSB 13
132984 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */
132985 #define ALT_USB_DEV_DOEPINT13_NAKINTRPT_MSB 13
132986 /* The width in bits of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */
132987 #define ALT_USB_DEV_DOEPINT13_NAKINTRPT_WIDTH 1
132988 /* The mask used to set the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field value. */
132989 #define ALT_USB_DEV_DOEPINT13_NAKINTRPT_SET_MSK 0x00002000
132990 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field value. */
132991 #define ALT_USB_DEV_DOEPINT13_NAKINTRPT_CLR_MSK 0xffffdfff
132992 /* The reset value of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */
132993 #define ALT_USB_DEV_DOEPINT13_NAKINTRPT_RESET 0x0
132994 /* Extracts the ALT_USB_DEV_DOEPINT13_NAKINTRPT field value from a register. */
132995 #define ALT_USB_DEV_DOEPINT13_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
132996 /* Produces a ALT_USB_DEV_DOEPINT13_NAKINTRPT register field value suitable for setting the register. */
132997 #define ALT_USB_DEV_DOEPINT13_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
132998 
132999 /*
133000  * Field : nyetintrpt
133001  *
133002  * NYET Interrupt (NYETIntrpt)
133003  *
133004  * The core generates this interrupt when a NYET response is transmitted for a non
133005  * isochronous OUT endpoint.
133006  *
133007  * Field Enumeration Values:
133008  *
133009  * Enum | Value | Description
133010  * :-----------------------------------------|:------|:---------------
133011  * ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_INACT | 0x0 | No interrupt
133012  * ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
133013  *
133014  * Field Access Macros:
133015  *
133016  */
133017 /*
133018  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_NYETINTRPT
133019  *
133020  * No interrupt
133021  */
133022 #define ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_INACT 0x0
133023 /*
133024  * Enumerated value for register field ALT_USB_DEV_DOEPINT13_NYETINTRPT
133025  *
133026  * NYET Interrupt
133027  */
133028 #define ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_ACT 0x1
133029 
133030 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */
133031 #define ALT_USB_DEV_DOEPINT13_NYETINTRPT_LSB 14
133032 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */
133033 #define ALT_USB_DEV_DOEPINT13_NYETINTRPT_MSB 14
133034 /* The width in bits of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */
133035 #define ALT_USB_DEV_DOEPINT13_NYETINTRPT_WIDTH 1
133036 /* The mask used to set the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field value. */
133037 #define ALT_USB_DEV_DOEPINT13_NYETINTRPT_SET_MSK 0x00004000
133038 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field value. */
133039 #define ALT_USB_DEV_DOEPINT13_NYETINTRPT_CLR_MSK 0xffffbfff
133040 /* The reset value of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */
133041 #define ALT_USB_DEV_DOEPINT13_NYETINTRPT_RESET 0x0
133042 /* Extracts the ALT_USB_DEV_DOEPINT13_NYETINTRPT field value from a register. */
133043 #define ALT_USB_DEV_DOEPINT13_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
133044 /* Produces a ALT_USB_DEV_DOEPINT13_NYETINTRPT register field value suitable for setting the register. */
133045 #define ALT_USB_DEV_DOEPINT13_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
133046 
133047 /*
133048  * Field : stuppktrcvd
133049  *
133050  * Setup Packet Received
133051  *
133052  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
133053  *
133054  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
133055  *
133056  * setup data. There is only one Setup packet per buffer. On receiving a
133057  *
133058  * Setup packet, the DWC_otg core closes the buffer and disables the
133059  *
133060  * corresponding endpoint. The application has to re-enable the endpoint to
133061  *
133062  * receive any OUT data for the Control Transfer and reprogram the buffer
133063  *
133064  * start address.
133065  *
133066  * Note: Because of the above behavior, the DWC_otg core can receive any
133067  *
133068  * number of back to back setup packets and one buffer for every setup
133069  *
133070  * packet is used.
133071  *
133072  * 1'b0: No Setup packet received
133073  *
133074  * 1'b1: Setup packet received
133075  *
133076  * Reset: 1'b0
133077  *
133078  * Field Access Macros:
133079  *
133080  */
133081 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field. */
133082 #define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_LSB 15
133083 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field. */
133084 #define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_MSB 15
133085 /* The width in bits of the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field. */
133086 #define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_WIDTH 1
133087 /* The mask used to set the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field value. */
133088 #define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_SET_MSK 0x00008000
133089 /* The mask used to clear the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field value. */
133090 #define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_CLR_MSK 0xffff7fff
133091 /* The reset value of the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field. */
133092 #define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_RESET 0x0
133093 /* Extracts the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD field value from a register. */
133094 #define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
133095 /* Produces a ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field value suitable for setting the register. */
133096 #define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
133097 
133098 #ifndef __ASSEMBLY__
133099 /*
133100  * WARNING: The C register and register group struct declarations are provided for
133101  * convenience and illustrative purposes. They should, however, be used with
133102  * caution as the C language standard provides no guarantees about the alignment or
133103  * atomicity of device memory accesses. The recommended practice for writing
133104  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
133105  * alt_write_word() functions.
133106  *
133107  * The struct declaration for register ALT_USB_DEV_DOEPINT13.
133108  */
133109 struct ALT_USB_DEV_DOEPINT13_s
133110 {
133111  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT13_XFERCOMPL */
133112  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT13_EPDISBLD */
133113  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT13_AHBERR */
133114  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT13_SETUP */
133115  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS */
133116  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT13_STSPHSERCVD */
133117  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP */
133118  uint32_t : 1; /* *UNDEFINED* */
133119  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT13_OUTPKTERR */
133120  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT13_BNAINTR */
133121  uint32_t : 1; /* *UNDEFINED* */
133122  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT13_PKTDRPSTS */
133123  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT13_BBLEERR */
133124  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT13_NAKINTRPT */
133125  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT13_NYETINTRPT */
133126  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT13_STUPPKTRCVD */
133127  uint32_t : 16; /* *UNDEFINED* */
133128 };
133129 
133130 /* The typedef declaration for register ALT_USB_DEV_DOEPINT13. */
133131 typedef volatile struct ALT_USB_DEV_DOEPINT13_s ALT_USB_DEV_DOEPINT13_t;
133132 #endif /* __ASSEMBLY__ */
133133 
133134 /* The reset value of the ALT_USB_DEV_DOEPINT13 register. */
133135 #define ALT_USB_DEV_DOEPINT13_RESET 0x00000000
133136 /* The byte offset of the ALT_USB_DEV_DOEPINT13 register from the beginning of the component. */
133137 #define ALT_USB_DEV_DOEPINT13_OFST 0x4a8
133138 /* The address of the ALT_USB_DEV_DOEPINT13 register. */
133139 #define ALT_USB_DEV_DOEPINT13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT13_OFST))
133140 
133141 /*
133142  * Register : doeptsiz13
133143  *
133144  * Device OUT Endpoint 13 Transfer Size Register
133145  *
133146  * Register Layout
133147  *
133148  * Bits | Access | Reset | Description
133149  * :--------|:-------|:------|:--------------------------------
133150  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ13_XFERSIZE
133151  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ13_PKTCNT
133152  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ13_RXDPID
133153  * [31] | ??? | 0x0 | *UNDEFINED*
133154  *
133155  */
133156 /*
133157  * Field : xfersize
133158  *
133159  * Transfer Size (XferSize)
133160  *
133161  * Indicates the transfer size in bytes For endpoint 0. The core
133162  *
133163  * interrupts the application only after it has exhausted the transfer
133164  *
133165  * size amount of data. The transfer size can be Set to the
133166  *
133167  * maximum packet size of the endpoint, to be interrupted at the
133168  *
133169  * end of each packet.
133170  *
133171  * The core decrements this field every time a packet is read from
133172  *
133173  * the RxFIFO and written to the external memory.
133174  *
133175  * Field Access Macros:
133176  *
133177  */
133178 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */
133179 #define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_LSB 0
133180 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */
133181 #define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_MSB 18
133182 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */
133183 #define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_WIDTH 19
133184 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field value. */
133185 #define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_SET_MSK 0x0007ffff
133186 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field value. */
133187 #define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_CLR_MSK 0xfff80000
133188 /* The reset value of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */
133189 #define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_RESET 0x0
133190 /* Extracts the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE field value from a register. */
133191 #define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
133192 /* Produces a ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field value suitable for setting the register. */
133193 #define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
133194 
133195 /*
133196  * Field : pktcnt
133197  *
133198  * Packet Count (PktCnt)
133199  *
133200  * This field is decremented to zero after a packet is written into the
133201  *
133202  * RxFIFO.
133203  *
133204  * Field Access Macros:
133205  *
133206  */
133207 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */
133208 #define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_LSB 19
133209 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */
133210 #define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_MSB 28
133211 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */
133212 #define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_WIDTH 10
133213 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field value. */
133214 #define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_SET_MSK 0x1ff80000
133215 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field value. */
133216 #define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_CLR_MSK 0xe007ffff
133217 /* The reset value of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */
133218 #define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_RESET 0x0
133219 /* Extracts the ALT_USB_DEV_DOEPTSIZ13_PKTCNT field value from a register. */
133220 #define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
133221 /* Produces a ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field value suitable for setting the register. */
133222 #define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
133223 
133224 /*
133225  * Field : rxdpid
133226  *
133227  * Applies to isochronous OUT endpoints only.
133228  *
133229  * This is the data PID received in the last packet for this endpoint.
133230  *
133231  * 2'b00: DATA0
133232  *
133233  * 2'b01: DATA2
133234  *
133235  * 2'b10: DATA1
133236  *
133237  * 2'b11: MDATA
133238  *
133239  * SETUP Packet Count (SUPCnt)
133240  *
133241  * Applies to control OUT Endpoints only.
133242  *
133243  * This field specifies the number of back-to-back SETUP data
133244  *
133245  * packets the endpoint can receive.
133246  *
133247  * 2'b01: 1 packet
133248  *
133249  * 2'b10: 2 packets
133250  *
133251  * 2'b11: 3 packets
133252  *
133253  * Field Enumeration Values:
133254  *
133255  * Enum | Value | Description
133256  * :------------------------------------------|:------|:-------------------
133257  * ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA0 | 0x0 | DATA0
133258  * ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
133259  * ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
133260  * ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
133261  *
133262  * Field Access Macros:
133263  *
133264  */
133265 /*
133266  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID
133267  *
133268  * DATA0
133269  */
133270 #define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA0 0x0
133271 /*
133272  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID
133273  *
133274  * DATA2 or 1 packet
133275  */
133276 #define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA2PKT1 0x1
133277 /*
133278  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID
133279  *
133280  * DATA1 or 2 packets
133281  */
133282 #define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA1PKT2 0x2
133283 /*
133284  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID
133285  *
133286  * MDATA or 3 packets
133287  */
133288 #define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_MDATAPKT3 0x3
133289 
133290 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */
133291 #define ALT_USB_DEV_DOEPTSIZ13_RXDPID_LSB 29
133292 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */
133293 #define ALT_USB_DEV_DOEPTSIZ13_RXDPID_MSB 30
133294 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */
133295 #define ALT_USB_DEV_DOEPTSIZ13_RXDPID_WIDTH 2
133296 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field value. */
133297 #define ALT_USB_DEV_DOEPTSIZ13_RXDPID_SET_MSK 0x60000000
133298 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field value. */
133299 #define ALT_USB_DEV_DOEPTSIZ13_RXDPID_CLR_MSK 0x9fffffff
133300 /* The reset value of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */
133301 #define ALT_USB_DEV_DOEPTSIZ13_RXDPID_RESET 0x0
133302 /* Extracts the ALT_USB_DEV_DOEPTSIZ13_RXDPID field value from a register. */
133303 #define ALT_USB_DEV_DOEPTSIZ13_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
133304 /* Produces a ALT_USB_DEV_DOEPTSIZ13_RXDPID register field value suitable for setting the register. */
133305 #define ALT_USB_DEV_DOEPTSIZ13_RXDPID_SET(value) (((value) << 29) & 0x60000000)
133306 
133307 #ifndef __ASSEMBLY__
133308 /*
133309  * WARNING: The C register and register group struct declarations are provided for
133310  * convenience and illustrative purposes. They should, however, be used with
133311  * caution as the C language standard provides no guarantees about the alignment or
133312  * atomicity of device memory accesses. The recommended practice for writing
133313  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
133314  * alt_write_word() functions.
133315  *
133316  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ13.
133317  */
133318 struct ALT_USB_DEV_DOEPTSIZ13_s
133319 {
133320  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ13_XFERSIZE */
133321  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ13_PKTCNT */
133322  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ13_RXDPID */
133323  uint32_t : 1; /* *UNDEFINED* */
133324 };
133325 
133326 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ13. */
133327 typedef volatile struct ALT_USB_DEV_DOEPTSIZ13_s ALT_USB_DEV_DOEPTSIZ13_t;
133328 #endif /* __ASSEMBLY__ */
133329 
133330 /* The reset value of the ALT_USB_DEV_DOEPTSIZ13 register. */
133331 #define ALT_USB_DEV_DOEPTSIZ13_RESET 0x00000000
133332 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ13 register from the beginning of the component. */
133333 #define ALT_USB_DEV_DOEPTSIZ13_OFST 0x4b0
133334 /* The address of the ALT_USB_DEV_DOEPTSIZ13 register. */
133335 #define ALT_USB_DEV_DOEPTSIZ13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ13_OFST))
133336 
133337 /*
133338  * Register : doepdma13
133339  *
133340  * Device OUT Endpoint 13 DMA Address Register
133341  *
133342  * Register Layout
133343  *
133344  * Bits | Access | Reset | Description
133345  * :-------|:-------|:--------|:--------------------------------
133346  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA13_DOEPDMA13
133347  *
133348  */
133349 /*
133350  * Field : doepdma13
133351  *
133352  * Holds the start address of the external memory for storing or fetching endpoint
133353  *
133354  * data.
133355  *
133356  * Note: For control endpoints, this field stores control OUT data packets as well
133357  * as
133358  *
133359  * SETUP transaction data packets. When more than three SETUP packets are
133360  *
133361  * received back-to-back, the SETUP data packet in the memory is overwritten.
133362  *
133363  * This register is incremented on every AHB transaction. The application can give
133364  *
133365  * only a DWORD-aligned address.
133366  *
133367  * When Scatter/Gather DMA mode is not enabled, the application programs the
133368  *
133369  * start address value in this field.
133370  *
133371  * When Scatter/Gather DMA mode is enabled, this field indicates the base
133372  *
133373  * pointer for the descriptor list.
133374  *
133375  * Field Access Macros:
133376  *
133377  */
133378 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field. */
133379 #define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_LSB 0
133380 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field. */
133381 #define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_MSB 31
133382 /* The width in bits of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field. */
133383 #define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_WIDTH 32
133384 /* The mask used to set the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field value. */
133385 #define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_SET_MSK 0xffffffff
133386 /* The mask used to clear the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field value. */
133387 #define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_CLR_MSK 0x00000000
133388 /* The reset value of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field is UNKNOWN. */
133389 #define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_RESET 0x0
133390 /* Extracts the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 field value from a register. */
133391 #define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_GET(value) (((value) & 0xffffffff) >> 0)
133392 /* Produces a ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field value suitable for setting the register. */
133393 #define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_SET(value) (((value) << 0) & 0xffffffff)
133394 
133395 #ifndef __ASSEMBLY__
133396 /*
133397  * WARNING: The C register and register group struct declarations are provided for
133398  * convenience and illustrative purposes. They should, however, be used with
133399  * caution as the C language standard provides no guarantees about the alignment or
133400  * atomicity of device memory accesses. The recommended practice for writing
133401  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
133402  * alt_write_word() functions.
133403  *
133404  * The struct declaration for register ALT_USB_DEV_DOEPDMA13.
133405  */
133406 struct ALT_USB_DEV_DOEPDMA13_s
133407 {
133408  uint32_t doepdma13 : 32; /* ALT_USB_DEV_DOEPDMA13_DOEPDMA13 */
133409 };
133410 
133411 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA13. */
133412 typedef volatile struct ALT_USB_DEV_DOEPDMA13_s ALT_USB_DEV_DOEPDMA13_t;
133413 #endif /* __ASSEMBLY__ */
133414 
133415 /* The reset value of the ALT_USB_DEV_DOEPDMA13 register. */
133416 #define ALT_USB_DEV_DOEPDMA13_RESET 0x00000000
133417 /* The byte offset of the ALT_USB_DEV_DOEPDMA13 register from the beginning of the component. */
133418 #define ALT_USB_DEV_DOEPDMA13_OFST 0x4b4
133419 /* The address of the ALT_USB_DEV_DOEPDMA13 register. */
133420 #define ALT_USB_DEV_DOEPDMA13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA13_OFST))
133421 
133422 /*
133423  * Register : doepdmab13
133424  *
133425  * Device OUT Endpoint 13 Buffer Address Register
133426  *
133427  * Register Layout
133428  *
133429  * Bits | Access | Reset | Description
133430  * :-------|:-------|:--------|:----------------------------------
133431  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13
133432  *
133433  */
133434 /*
133435  * Field : doepdmab13
133436  *
133437  * Holds the current buffer address.This register is updated as and when the data
133438  *
133439  * transfer for the corresponding end point is in progress.
133440  *
133441  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
133442  * is
133443  *
133444  * reserved.
133445  *
133446  * Field Access Macros:
133447  *
133448  */
133449 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field. */
133450 #define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_LSB 0
133451 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field. */
133452 #define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_MSB 31
133453 /* The width in bits of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field. */
133454 #define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_WIDTH 32
133455 /* The mask used to set the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field value. */
133456 #define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_SET_MSK 0xffffffff
133457 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field value. */
133458 #define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_CLR_MSK 0x00000000
133459 /* The reset value of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field is UNKNOWN. */
133460 #define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_RESET 0x0
133461 /* Extracts the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 field value from a register. */
133462 #define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_GET(value) (((value) & 0xffffffff) >> 0)
133463 /* Produces a ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field value suitable for setting the register. */
133464 #define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_SET(value) (((value) << 0) & 0xffffffff)
133465 
133466 #ifndef __ASSEMBLY__
133467 /*
133468  * WARNING: The C register and register group struct declarations are provided for
133469  * convenience and illustrative purposes. They should, however, be used with
133470  * caution as the C language standard provides no guarantees about the alignment or
133471  * atomicity of device memory accesses. The recommended practice for writing
133472  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
133473  * alt_write_word() functions.
133474  *
133475  * The struct declaration for register ALT_USB_DEV_DOEPDMAB13.
133476  */
133477 struct ALT_USB_DEV_DOEPDMAB13_s
133478 {
133479  const uint32_t doepdmab13 : 32; /* ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 */
133480 };
133481 
133482 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB13. */
133483 typedef volatile struct ALT_USB_DEV_DOEPDMAB13_s ALT_USB_DEV_DOEPDMAB13_t;
133484 #endif /* __ASSEMBLY__ */
133485 
133486 /* The reset value of the ALT_USB_DEV_DOEPDMAB13 register. */
133487 #define ALT_USB_DEV_DOEPDMAB13_RESET 0x00000000
133488 /* The byte offset of the ALT_USB_DEV_DOEPDMAB13 register from the beginning of the component. */
133489 #define ALT_USB_DEV_DOEPDMAB13_OFST 0x4bc
133490 /* The address of the ALT_USB_DEV_DOEPDMAB13 register. */
133491 #define ALT_USB_DEV_DOEPDMAB13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB13_OFST))
133492 
133493 /*
133494  * Register : doepctl14
133495  *
133496  * Device Control OUT Endpoint 14 Control Register
133497  *
133498  * Register Layout
133499  *
133500  * Bits | Access | Reset | Description
133501  * :--------|:---------|:------|:-------------------------------
133502  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL14_MPS
133503  * [14:11] | ??? | 0x0 | *UNDEFINED*
133504  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL14_USBACTEP
133505  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL14_DPID
133506  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL14_NAKSTS
133507  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL14_EPTYPE
133508  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL14_SNP
133509  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL14_STALL
133510  * [25:22] | ??? | 0x0 | *UNDEFINED*
133511  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL14_CNAK
133512  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL14_SNAK
133513  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL14_SETD0PID
133514  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL14_SETD1PID
133515  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL14_EPDIS
133516  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL14_EPENA
133517  *
133518  */
133519 /*
133520  * Field : mps
133521  *
133522  * Maximum Packet Size (MPS)
133523  *
133524  * The application must program this field with the maximum packet size for the
133525  * current
133526  *
133527  * logical endpoint. This value is in bytes.
133528  *
133529  * Field Access Macros:
133530  *
133531  */
133532 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_MPS register field. */
133533 #define ALT_USB_DEV_DOEPCTL14_MPS_LSB 0
133534 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_MPS register field. */
133535 #define ALT_USB_DEV_DOEPCTL14_MPS_MSB 10
133536 /* The width in bits of the ALT_USB_DEV_DOEPCTL14_MPS register field. */
133537 #define ALT_USB_DEV_DOEPCTL14_MPS_WIDTH 11
133538 /* The mask used to set the ALT_USB_DEV_DOEPCTL14_MPS register field value. */
133539 #define ALT_USB_DEV_DOEPCTL14_MPS_SET_MSK 0x000007ff
133540 /* The mask used to clear the ALT_USB_DEV_DOEPCTL14_MPS register field value. */
133541 #define ALT_USB_DEV_DOEPCTL14_MPS_CLR_MSK 0xfffff800
133542 /* The reset value of the ALT_USB_DEV_DOEPCTL14_MPS register field. */
133543 #define ALT_USB_DEV_DOEPCTL14_MPS_RESET 0x0
133544 /* Extracts the ALT_USB_DEV_DOEPCTL14_MPS field value from a register. */
133545 #define ALT_USB_DEV_DOEPCTL14_MPS_GET(value) (((value) & 0x000007ff) >> 0)
133546 /* Produces a ALT_USB_DEV_DOEPCTL14_MPS register field value suitable for setting the register. */
133547 #define ALT_USB_DEV_DOEPCTL14_MPS_SET(value) (((value) << 0) & 0x000007ff)
133548 
133549 /*
133550  * Field : usbactep
133551  *
133552  * USB Active Endpoint (USBActEP)
133553  *
133554  * Indicates whether this endpoint is active in the current configuration and
133555  * interface. The
133556  *
133557  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
133558  * reset. After
133559  *
133560  * receiving the SetConfiguration and SetInterface commands, the application must
133561  *
133562  * program endpoint registers accordingly and set this bit.
133563  *
133564  * Field Enumeration Values:
133565  *
133566  * Enum | Value | Description
133567  * :--------------------------------------|:------|:--------------------
133568  * ALT_USB_DEV_DOEPCTL14_USBACTEP_E_DISD | 0x0 | Not Active
133569  * ALT_USB_DEV_DOEPCTL14_USBACTEP_E_END | 0x1 | USB Active Endpoint
133570  *
133571  * Field Access Macros:
133572  *
133573  */
133574 /*
133575  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_USBACTEP
133576  *
133577  * Not Active
133578  */
133579 #define ALT_USB_DEV_DOEPCTL14_USBACTEP_E_DISD 0x0
133580 /*
133581  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_USBACTEP
133582  *
133583  * USB Active Endpoint
133584  */
133585 #define ALT_USB_DEV_DOEPCTL14_USBACTEP_E_END 0x1
133586 
133587 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */
133588 #define ALT_USB_DEV_DOEPCTL14_USBACTEP_LSB 15
133589 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */
133590 #define ALT_USB_DEV_DOEPCTL14_USBACTEP_MSB 15
133591 /* The width in bits of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */
133592 #define ALT_USB_DEV_DOEPCTL14_USBACTEP_WIDTH 1
133593 /* The mask used to set the ALT_USB_DEV_DOEPCTL14_USBACTEP register field value. */
133594 #define ALT_USB_DEV_DOEPCTL14_USBACTEP_SET_MSK 0x00008000
133595 /* The mask used to clear the ALT_USB_DEV_DOEPCTL14_USBACTEP register field value. */
133596 #define ALT_USB_DEV_DOEPCTL14_USBACTEP_CLR_MSK 0xffff7fff
133597 /* The reset value of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */
133598 #define ALT_USB_DEV_DOEPCTL14_USBACTEP_RESET 0x0
133599 /* Extracts the ALT_USB_DEV_DOEPCTL14_USBACTEP field value from a register. */
133600 #define ALT_USB_DEV_DOEPCTL14_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
133601 /* Produces a ALT_USB_DEV_DOEPCTL14_USBACTEP register field value suitable for setting the register. */
133602 #define ALT_USB_DEV_DOEPCTL14_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
133603 
133604 /*
133605  * Field : dpid
133606  *
133607  * Endpoint Data PID (DPID)
133608  *
133609  * Applies to interrupt/bulk IN and OUT endpoints only.
133610  *
133611  * Contains the PID of the packet to be received or transmitted on this endpoint.
133612  * The
133613  *
133614  * application must program the PID of the first packet to be received or
133615  * transmitted on
133616  *
133617  * this endpoint, after the endpoint is activated. The applications use the
133618  * SetD1PID and
133619  *
133620  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
133621  *
133622  * 1'b0: DATA0
133623  *
133624  * 1'b1: DATA1
133625  *
133626  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
133627  *
133628  * DMA mode.
133629  *
133630  * 1'b0 RO
133631  *
133632  * Even/Odd (Micro)Frame (EO_FrNum)
133633  *
133634  * In non-Scatter/Gather DMA mode:
133635  *
133636  * Applies to isochronous IN and OUT endpoints only.
133637  *
133638  * Indicates the (micro)frame number in which the core transmits/receives
133639  * isochronous
133640  *
133641  * data for this endpoint. The application must program the even/odd (micro) frame
133642  *
133643  * number in which it intends to transmit/receive isochronous data for this
133644  * endpoint using
133645  *
133646  * the SetEvnFr and SetOddFr fields in this register.
133647  *
133648  * 1'b0: Even (micro)frame
133649  *
133650  * 1'b1: Odd (micro)frame
133651  *
133652  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
133653  * number
133654  *
133655  * in which to send data is provided in the transmit descriptor structure. The
133656  * frame in
133657  *
133658  * which data is received is updated in receive descriptor structure.
133659  *
133660  * Field Enumeration Values:
133661  *
133662  * Enum | Value | Description
133663  * :-----------------------------------|:------|:-----------------------------
133664  * ALT_USB_DEV_DOEPCTL14_DPID_E_INACT | 0x0 | Endpoint Data PID not active
133665  * ALT_USB_DEV_DOEPCTL14_DPID_E_ACT | 0x1 | Endpoint Data PID active
133666  *
133667  * Field Access Macros:
133668  *
133669  */
133670 /*
133671  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_DPID
133672  *
133673  * Endpoint Data PID not active
133674  */
133675 #define ALT_USB_DEV_DOEPCTL14_DPID_E_INACT 0x0
133676 /*
133677  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_DPID
133678  *
133679  * Endpoint Data PID active
133680  */
133681 #define ALT_USB_DEV_DOEPCTL14_DPID_E_ACT 0x1
133682 
133683 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_DPID register field. */
133684 #define ALT_USB_DEV_DOEPCTL14_DPID_LSB 16
133685 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_DPID register field. */
133686 #define ALT_USB_DEV_DOEPCTL14_DPID_MSB 16
133687 /* The width in bits of the ALT_USB_DEV_DOEPCTL14_DPID register field. */
133688 #define ALT_USB_DEV_DOEPCTL14_DPID_WIDTH 1
133689 /* The mask used to set the ALT_USB_DEV_DOEPCTL14_DPID register field value. */
133690 #define ALT_USB_DEV_DOEPCTL14_DPID_SET_MSK 0x00010000
133691 /* The mask used to clear the ALT_USB_DEV_DOEPCTL14_DPID register field value. */
133692 #define ALT_USB_DEV_DOEPCTL14_DPID_CLR_MSK 0xfffeffff
133693 /* The reset value of the ALT_USB_DEV_DOEPCTL14_DPID register field. */
133694 #define ALT_USB_DEV_DOEPCTL14_DPID_RESET 0x0
133695 /* Extracts the ALT_USB_DEV_DOEPCTL14_DPID field value from a register. */
133696 #define ALT_USB_DEV_DOEPCTL14_DPID_GET(value) (((value) & 0x00010000) >> 16)
133697 /* Produces a ALT_USB_DEV_DOEPCTL14_DPID register field value suitable for setting the register. */
133698 #define ALT_USB_DEV_DOEPCTL14_DPID_SET(value) (((value) << 16) & 0x00010000)
133699 
133700 /*
133701  * Field : naksts
133702  *
133703  * NAK Status (NAKSts)
133704  *
133705  * Indicates the following:
133706  *
133707  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
133708  *
133709  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
133710  *
133711  * When either the application or the core sets this bit:
133712  *
133713  * The core stops receiving any data on an OUT endpoint, even if there is space in
133714  *
133715  * the RxFIFO to accommodate the incoming packet.
133716  *
133717  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
133718  *
133719  * endpoint, even if there data is available in the TxFIFO.
133720  *
133721  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
133722  *
133723  * if there data is available in the TxFIFO.
133724  *
133725  * Irrespective of this bit's setting, the core always responds to SETUP data
133726  * packets with
133727  *
133728  * an ACK handshake.
133729  *
133730  * Field Enumeration Values:
133731  *
133732  * Enum | Value | Description
133733  * :--------------------------------------|:------|:------------------------------------------------
133734  * ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
133735  * : | | based on the FIFO status
133736  * ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
133737  * : | | endpoint
133738  *
133739  * Field Access Macros:
133740  *
133741  */
133742 /*
133743  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_NAKSTS
133744  *
133745  * The core is transmitting non-NAK handshakes based on the FIFO status
133746  */
133747 #define ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NONNAK 0x0
133748 /*
133749  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_NAKSTS
133750  *
133751  * The core is transmitting NAK handshakes on this endpoint
133752  */
133753 #define ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NAK 0x1
133754 
133755 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */
133756 #define ALT_USB_DEV_DOEPCTL14_NAKSTS_LSB 17
133757 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */
133758 #define ALT_USB_DEV_DOEPCTL14_NAKSTS_MSB 17
133759 /* The width in bits of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */
133760 #define ALT_USB_DEV_DOEPCTL14_NAKSTS_WIDTH 1
133761 /* The mask used to set the ALT_USB_DEV_DOEPCTL14_NAKSTS register field value. */
133762 #define ALT_USB_DEV_DOEPCTL14_NAKSTS_SET_MSK 0x00020000
133763 /* The mask used to clear the ALT_USB_DEV_DOEPCTL14_NAKSTS register field value. */
133764 #define ALT_USB_DEV_DOEPCTL14_NAKSTS_CLR_MSK 0xfffdffff
133765 /* The reset value of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */
133766 #define ALT_USB_DEV_DOEPCTL14_NAKSTS_RESET 0x0
133767 /* Extracts the ALT_USB_DEV_DOEPCTL14_NAKSTS field value from a register. */
133768 #define ALT_USB_DEV_DOEPCTL14_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
133769 /* Produces a ALT_USB_DEV_DOEPCTL14_NAKSTS register field value suitable for setting the register. */
133770 #define ALT_USB_DEV_DOEPCTL14_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
133771 
133772 /*
133773  * Field : eptype
133774  *
133775  * Endpoint Type (EPType)
133776  *
133777  * This is the transfer type supported by this logical endpoint.
133778  *
133779  * 2'b00: Control
133780  *
133781  * 2'b01: Isochronous
133782  *
133783  * 2'b10: Bulk
133784  *
133785  * 2'b11: Interrupt
133786  *
133787  * Field Enumeration Values:
133788  *
133789  * Enum | Value | Description
133790  * :-------------------------------------------|:------|:------------
133791  * ALT_USB_DEV_DOEPCTL14_EPTYPE_E_CTL | 0x0 | Control
133792  * ALT_USB_DEV_DOEPCTL14_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
133793  * ALT_USB_DEV_DOEPCTL14_EPTYPE_E_BULK | 0x2 | Bulk
133794  * ALT_USB_DEV_DOEPCTL14_EPTYPE_E_INTERRUP | 0x3 | Interrupt
133795  *
133796  * Field Access Macros:
133797  *
133798  */
133799 /*
133800  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE
133801  *
133802  * Control
133803  */
133804 #define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_CTL 0x0
133805 /*
133806  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE
133807  *
133808  * Isochronous
133809  */
133810 #define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_ISOCHRONOUS 0x1
133811 /*
133812  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE
133813  *
133814  * Bulk
133815  */
133816 #define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_BULK 0x2
133817 /*
133818  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE
133819  *
133820  * Interrupt
133821  */
133822 #define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_INTERRUP 0x3
133823 
133824 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */
133825 #define ALT_USB_DEV_DOEPCTL14_EPTYPE_LSB 18
133826 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */
133827 #define ALT_USB_DEV_DOEPCTL14_EPTYPE_MSB 19
133828 /* The width in bits of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */
133829 #define ALT_USB_DEV_DOEPCTL14_EPTYPE_WIDTH 2
133830 /* The mask used to set the ALT_USB_DEV_DOEPCTL14_EPTYPE register field value. */
133831 #define ALT_USB_DEV_DOEPCTL14_EPTYPE_SET_MSK 0x000c0000
133832 /* The mask used to clear the ALT_USB_DEV_DOEPCTL14_EPTYPE register field value. */
133833 #define ALT_USB_DEV_DOEPCTL14_EPTYPE_CLR_MSK 0xfff3ffff
133834 /* The reset value of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */
133835 #define ALT_USB_DEV_DOEPCTL14_EPTYPE_RESET 0x0
133836 /* Extracts the ALT_USB_DEV_DOEPCTL14_EPTYPE field value from a register. */
133837 #define ALT_USB_DEV_DOEPCTL14_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
133838 /* Produces a ALT_USB_DEV_DOEPCTL14_EPTYPE register field value suitable for setting the register. */
133839 #define ALT_USB_DEV_DOEPCTL14_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
133840 
133841 /*
133842  * Field : snp
133843  *
133844  * Snoop Mode (Snp)
133845  *
133846  * Applies to OUT endpoints only.
133847  *
133848  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
133849  *
133850  * check the correctness of OUT packets before transferring them to application
133851  * memory.
133852  *
133853  * Field Enumeration Values:
133854  *
133855  * Enum | Value | Description
133856  * :--------------------------------|:------|:-------------------
133857  * ALT_USB_DEV_DOEPCTL14_SNP_E_DIS | 0x0 | Disable Snoop Mode
133858  * ALT_USB_DEV_DOEPCTL14_SNP_E_EN | 0x1 | Enable Snoop Mode
133859  *
133860  * Field Access Macros:
133861  *
133862  */
133863 /*
133864  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNP
133865  *
133866  * Disable Snoop Mode
133867  */
133868 #define ALT_USB_DEV_DOEPCTL14_SNP_E_DIS 0x0
133869 /*
133870  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNP
133871  *
133872  * Enable Snoop Mode
133873  */
133874 #define ALT_USB_DEV_DOEPCTL14_SNP_E_EN 0x1
133875 
133876 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SNP register field. */
133877 #define ALT_USB_DEV_DOEPCTL14_SNP_LSB 20
133878 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SNP register field. */
133879 #define ALT_USB_DEV_DOEPCTL14_SNP_MSB 20
133880 /* The width in bits of the ALT_USB_DEV_DOEPCTL14_SNP register field. */
133881 #define ALT_USB_DEV_DOEPCTL14_SNP_WIDTH 1
133882 /* The mask used to set the ALT_USB_DEV_DOEPCTL14_SNP register field value. */
133883 #define ALT_USB_DEV_DOEPCTL14_SNP_SET_MSK 0x00100000
133884 /* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SNP register field value. */
133885 #define ALT_USB_DEV_DOEPCTL14_SNP_CLR_MSK 0xffefffff
133886 /* The reset value of the ALT_USB_DEV_DOEPCTL14_SNP register field. */
133887 #define ALT_USB_DEV_DOEPCTL14_SNP_RESET 0x0
133888 /* Extracts the ALT_USB_DEV_DOEPCTL14_SNP field value from a register. */
133889 #define ALT_USB_DEV_DOEPCTL14_SNP_GET(value) (((value) & 0x00100000) >> 20)
133890 /* Produces a ALT_USB_DEV_DOEPCTL14_SNP register field value suitable for setting the register. */
133891 #define ALT_USB_DEV_DOEPCTL14_SNP_SET(value) (((value) << 20) & 0x00100000)
133892 
133893 /*
133894  * Field : stall
133895  *
133896  * STALL Handshake (Stall)
133897  *
133898  * Applies to non-control, non-isochronous IN and OUT endpoints only.
133899  *
133900  * The application sets this bit to stall all tokens from the USB host to this
133901  * endpoint. If a
133902  *
133903  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
133904  * bit, the
133905  *
133906  * STALL bit takes priority. Only the application can clear this bit, never the
133907  * core.
133908  *
133909  * 1'b0 R_W
133910  *
133911  * Applies to control endpoints only.
133912  *
133913  * The application can only set this bit, and the core clears it, when a SETUP
133914  * token is
133915  *
133916  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
133917  * OUT
133918  *
133919  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
133920  * this bit's
133921  *
133922  * setting, the core always responds to SETUP data packets with an ACK handshake.
133923  *
133924  * Field Enumeration Values:
133925  *
133926  * Enum | Value | Description
133927  * :------------------------------------|:------|:----------------------------
133928  * ALT_USB_DEV_DOEPCTL14_STALL_E_INACT | 0x0 | STALL All Tokens not active
133929  * ALT_USB_DEV_DOEPCTL14_STALL_E_ACT | 0x1 | STALL All Tokens active
133930  *
133931  * Field Access Macros:
133932  *
133933  */
133934 /*
133935  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_STALL
133936  *
133937  * STALL All Tokens not active
133938  */
133939 #define ALT_USB_DEV_DOEPCTL14_STALL_E_INACT 0x0
133940 /*
133941  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_STALL
133942  *
133943  * STALL All Tokens active
133944  */
133945 #define ALT_USB_DEV_DOEPCTL14_STALL_E_ACT 0x1
133946 
133947 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_STALL register field. */
133948 #define ALT_USB_DEV_DOEPCTL14_STALL_LSB 21
133949 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_STALL register field. */
133950 #define ALT_USB_DEV_DOEPCTL14_STALL_MSB 21
133951 /* The width in bits of the ALT_USB_DEV_DOEPCTL14_STALL register field. */
133952 #define ALT_USB_DEV_DOEPCTL14_STALL_WIDTH 1
133953 /* The mask used to set the ALT_USB_DEV_DOEPCTL14_STALL register field value. */
133954 #define ALT_USB_DEV_DOEPCTL14_STALL_SET_MSK 0x00200000
133955 /* The mask used to clear the ALT_USB_DEV_DOEPCTL14_STALL register field value. */
133956 #define ALT_USB_DEV_DOEPCTL14_STALL_CLR_MSK 0xffdfffff
133957 /* The reset value of the ALT_USB_DEV_DOEPCTL14_STALL register field. */
133958 #define ALT_USB_DEV_DOEPCTL14_STALL_RESET 0x0
133959 /* Extracts the ALT_USB_DEV_DOEPCTL14_STALL field value from a register. */
133960 #define ALT_USB_DEV_DOEPCTL14_STALL_GET(value) (((value) & 0x00200000) >> 21)
133961 /* Produces a ALT_USB_DEV_DOEPCTL14_STALL register field value suitable for setting the register. */
133962 #define ALT_USB_DEV_DOEPCTL14_STALL_SET(value) (((value) << 21) & 0x00200000)
133963 
133964 /*
133965  * Field : cnak
133966  *
133967  * Clear NAK (CNAK)
133968  *
133969  * A write to this bit clears the NAK bit For the endpoint.
133970  *
133971  * Field Enumeration Values:
133972  *
133973  * Enum | Value | Description
133974  * :-----------------------------------|:------|:-------------
133975  * ALT_USB_DEV_DOEPCTL14_CNAK_E_INACT | 0x0 | No Clear NAK
133976  * ALT_USB_DEV_DOEPCTL14_CNAK_E_ACT | 0x1 | Clear NAK
133977  *
133978  * Field Access Macros:
133979  *
133980  */
133981 /*
133982  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_CNAK
133983  *
133984  * No Clear NAK
133985  */
133986 #define ALT_USB_DEV_DOEPCTL14_CNAK_E_INACT 0x0
133987 /*
133988  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_CNAK
133989  *
133990  * Clear NAK
133991  */
133992 #define ALT_USB_DEV_DOEPCTL14_CNAK_E_ACT 0x1
133993 
133994 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */
133995 #define ALT_USB_DEV_DOEPCTL14_CNAK_LSB 26
133996 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */
133997 #define ALT_USB_DEV_DOEPCTL14_CNAK_MSB 26
133998 /* The width in bits of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */
133999 #define ALT_USB_DEV_DOEPCTL14_CNAK_WIDTH 1
134000 /* The mask used to set the ALT_USB_DEV_DOEPCTL14_CNAK register field value. */
134001 #define ALT_USB_DEV_DOEPCTL14_CNAK_SET_MSK 0x04000000
134002 /* The mask used to clear the ALT_USB_DEV_DOEPCTL14_CNAK register field value. */
134003 #define ALT_USB_DEV_DOEPCTL14_CNAK_CLR_MSK 0xfbffffff
134004 /* The reset value of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */
134005 #define ALT_USB_DEV_DOEPCTL14_CNAK_RESET 0x0
134006 /* Extracts the ALT_USB_DEV_DOEPCTL14_CNAK field value from a register. */
134007 #define ALT_USB_DEV_DOEPCTL14_CNAK_GET(value) (((value) & 0x04000000) >> 26)
134008 /* Produces a ALT_USB_DEV_DOEPCTL14_CNAK register field value suitable for setting the register. */
134009 #define ALT_USB_DEV_DOEPCTL14_CNAK_SET(value) (((value) << 26) & 0x04000000)
134010 
134011 /*
134012  * Field : snak
134013  *
134014  * Set NAK (SNAK)
134015  *
134016  * A write to this bit sets the NAK bit For the endpoint.
134017  *
134018  * Using this bit, the application can control the transmission of NAK
134019  *
134020  * handshakes on an endpoint. The core can also Set this bit For an
134021  *
134022  * endpoint after a SETUP packet is received on that endpoint.
134023  *
134024  * Field Enumeration Values:
134025  *
134026  * Enum | Value | Description
134027  * :-----------------------------------|:------|:------------
134028  * ALT_USB_DEV_DOEPCTL14_SNAK_E_INACT | 0x0 | No Set NAK
134029  * ALT_USB_DEV_DOEPCTL14_SNAK_E_ACT | 0x1 | Set NAK
134030  *
134031  * Field Access Macros:
134032  *
134033  */
134034 /*
134035  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNAK
134036  *
134037  * No Set NAK
134038  */
134039 #define ALT_USB_DEV_DOEPCTL14_SNAK_E_INACT 0x0
134040 /*
134041  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNAK
134042  *
134043  * Set NAK
134044  */
134045 #define ALT_USB_DEV_DOEPCTL14_SNAK_E_ACT 0x1
134046 
134047 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */
134048 #define ALT_USB_DEV_DOEPCTL14_SNAK_LSB 27
134049 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */
134050 #define ALT_USB_DEV_DOEPCTL14_SNAK_MSB 27
134051 /* The width in bits of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */
134052 #define ALT_USB_DEV_DOEPCTL14_SNAK_WIDTH 1
134053 /* The mask used to set the ALT_USB_DEV_DOEPCTL14_SNAK register field value. */
134054 #define ALT_USB_DEV_DOEPCTL14_SNAK_SET_MSK 0x08000000
134055 /* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SNAK register field value. */
134056 #define ALT_USB_DEV_DOEPCTL14_SNAK_CLR_MSK 0xf7ffffff
134057 /* The reset value of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */
134058 #define ALT_USB_DEV_DOEPCTL14_SNAK_RESET 0x0
134059 /* Extracts the ALT_USB_DEV_DOEPCTL14_SNAK field value from a register. */
134060 #define ALT_USB_DEV_DOEPCTL14_SNAK_GET(value) (((value) & 0x08000000) >> 27)
134061 /* Produces a ALT_USB_DEV_DOEPCTL14_SNAK register field value suitable for setting the register. */
134062 #define ALT_USB_DEV_DOEPCTL14_SNAK_SET(value) (((value) << 27) & 0x08000000)
134063 
134064 /*
134065  * Field : setd0pid
134066  *
134067  * Set DATA0 PID (SetD0PID)
134068  *
134069  * Applies to interrupt/bulk IN and OUT endpoints only.
134070  *
134071  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
134072  * to DATA0.
134073  *
134074  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
134075  *
134076  * DMA mode.
134077  *
134078  * 1'b0 WO
134079  *
134080  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
134081  *
134082  * Applies to isochronous IN and OUT endpoints only.
134083  *
134084  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
134085  * (micro)
134086  *
134087  * frame.
134088  *
134089  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
134090  * number
134091  *
134092  * in which to send data is in the transmit descriptor structure. The frame in
134093  * which to
134094  *
134095  * receive data is updated in receive descriptor structure.
134096  *
134097  * Field Enumeration Values:
134098  *
134099  * Enum | Value | Description
134100  * :--------------------------------------|:------|:------------------------------------
134101  * ALT_USB_DEV_DOEPCTL14_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
134102  * ALT_USB_DEV_DOEPCTL14_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
134103  *
134104  * Field Access Macros:
134105  *
134106  */
134107 /*
134108  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD0PID
134109  *
134110  * Disables Set DATA0 PID
134111  */
134112 #define ALT_USB_DEV_DOEPCTL14_SETD0PID_E_DISD 0x0
134113 /*
134114  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD0PID
134115  *
134116  * Enables Endpoint Data PID to DATA0)
134117  */
134118 #define ALT_USB_DEV_DOEPCTL14_SETD0PID_E_END 0x1
134119 
134120 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */
134121 #define ALT_USB_DEV_DOEPCTL14_SETD0PID_LSB 28
134122 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */
134123 #define ALT_USB_DEV_DOEPCTL14_SETD0PID_MSB 28
134124 /* The width in bits of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */
134125 #define ALT_USB_DEV_DOEPCTL14_SETD0PID_WIDTH 1
134126 /* The mask used to set the ALT_USB_DEV_DOEPCTL14_SETD0PID register field value. */
134127 #define ALT_USB_DEV_DOEPCTL14_SETD0PID_SET_MSK 0x10000000
134128 /* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SETD0PID register field value. */
134129 #define ALT_USB_DEV_DOEPCTL14_SETD0PID_CLR_MSK 0xefffffff
134130 /* The reset value of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */
134131 #define ALT_USB_DEV_DOEPCTL14_SETD0PID_RESET 0x0
134132 /* Extracts the ALT_USB_DEV_DOEPCTL14_SETD0PID field value from a register. */
134133 #define ALT_USB_DEV_DOEPCTL14_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
134134 /* Produces a ALT_USB_DEV_DOEPCTL14_SETD0PID register field value suitable for setting the register. */
134135 #define ALT_USB_DEV_DOEPCTL14_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
134136 
134137 /*
134138  * Field : setd1pid
134139  *
134140  * Set DATA1 PID (SetD1PID)
134141  *
134142  * Applies to interrupt/bulk IN and OUT endpoints only.
134143  *
134144  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
134145  * to DATA1.
134146  *
134147  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
134148  *
134149  * DMA mode.
134150  *
134151  * Set Odd (micro)frame (SetOddFr)
134152  *
134153  * Applies to isochronous IN and OUT endpoints only.
134154  *
134155  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
134156  *
134157  * (micro)frame.
134158  *
134159  * This field is not applicable for Scatter/Gather DMA mode.
134160  *
134161  * Field Enumeration Values:
134162  *
134163  * Enum | Value | Description
134164  * :--------------------------------------|:------|:-----------------------
134165  * ALT_USB_DEV_DOEPCTL14_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
134166  * ALT_USB_DEV_DOEPCTL14_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
134167  *
134168  * Field Access Macros:
134169  *
134170  */
134171 /*
134172  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD1PID
134173  *
134174  * Disables Set DATA1 PID
134175  */
134176 #define ALT_USB_DEV_DOEPCTL14_SETD1PID_E_DISD 0x0
134177 /*
134178  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD1PID
134179  *
134180  * Enables Set DATA1 PID
134181  */
134182 #define ALT_USB_DEV_DOEPCTL14_SETD1PID_E_END 0x1
134183 
134184 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */
134185 #define ALT_USB_DEV_DOEPCTL14_SETD1PID_LSB 29
134186 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */
134187 #define ALT_USB_DEV_DOEPCTL14_SETD1PID_MSB 29
134188 /* The width in bits of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */
134189 #define ALT_USB_DEV_DOEPCTL14_SETD1PID_WIDTH 1
134190 /* The mask used to set the ALT_USB_DEV_DOEPCTL14_SETD1PID register field value. */
134191 #define ALT_USB_DEV_DOEPCTL14_SETD1PID_SET_MSK 0x20000000
134192 /* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SETD1PID register field value. */
134193 #define ALT_USB_DEV_DOEPCTL14_SETD1PID_CLR_MSK 0xdfffffff
134194 /* The reset value of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */
134195 #define ALT_USB_DEV_DOEPCTL14_SETD1PID_RESET 0x0
134196 /* Extracts the ALT_USB_DEV_DOEPCTL14_SETD1PID field value from a register. */
134197 #define ALT_USB_DEV_DOEPCTL14_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
134198 /* Produces a ALT_USB_DEV_DOEPCTL14_SETD1PID register field value suitable for setting the register. */
134199 #define ALT_USB_DEV_DOEPCTL14_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
134200 
134201 /*
134202  * Field : epdis
134203  *
134204  * Endpoint Disable (EPDis)
134205  *
134206  * Applies to IN and OUT endpoints.
134207  *
134208  * The application sets this bit to stop transmitting/receiving data on an
134209  * endpoint, even
134210  *
134211  * before the transfer for that endpoint is complete. The application must wait for
134212  * the
134213  *
134214  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
134215  * clears
134216  *
134217  * this bit before setting the Endpoint Disabled interrupt. The application must
134218  * set this bit
134219  *
134220  * only if Endpoint Enable is already set for this endpoint.
134221  *
134222  * Field Enumeration Values:
134223  *
134224  * Enum | Value | Description
134225  * :------------------------------------|:------|:--------------------
134226  * ALT_USB_DEV_DOEPCTL14_EPDIS_E_INACT | 0x0 | No Endpoint Disable
134227  * ALT_USB_DEV_DOEPCTL14_EPDIS_E_ACT | 0x1 | Endpoint Disable
134228  *
134229  * Field Access Macros:
134230  *
134231  */
134232 /*
134233  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPDIS
134234  *
134235  * No Endpoint Disable
134236  */
134237 #define ALT_USB_DEV_DOEPCTL14_EPDIS_E_INACT 0x0
134238 /*
134239  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPDIS
134240  *
134241  * Endpoint Disable
134242  */
134243 #define ALT_USB_DEV_DOEPCTL14_EPDIS_E_ACT 0x1
134244 
134245 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */
134246 #define ALT_USB_DEV_DOEPCTL14_EPDIS_LSB 30
134247 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */
134248 #define ALT_USB_DEV_DOEPCTL14_EPDIS_MSB 30
134249 /* The width in bits of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */
134250 #define ALT_USB_DEV_DOEPCTL14_EPDIS_WIDTH 1
134251 /* The mask used to set the ALT_USB_DEV_DOEPCTL14_EPDIS register field value. */
134252 #define ALT_USB_DEV_DOEPCTL14_EPDIS_SET_MSK 0x40000000
134253 /* The mask used to clear the ALT_USB_DEV_DOEPCTL14_EPDIS register field value. */
134254 #define ALT_USB_DEV_DOEPCTL14_EPDIS_CLR_MSK 0xbfffffff
134255 /* The reset value of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */
134256 #define ALT_USB_DEV_DOEPCTL14_EPDIS_RESET 0x0
134257 /* Extracts the ALT_USB_DEV_DOEPCTL14_EPDIS field value from a register. */
134258 #define ALT_USB_DEV_DOEPCTL14_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
134259 /* Produces a ALT_USB_DEV_DOEPCTL14_EPDIS register field value suitable for setting the register. */
134260 #define ALT_USB_DEV_DOEPCTL14_EPDIS_SET(value) (((value) << 30) & 0x40000000)
134261 
134262 /*
134263  * Field : epena
134264  *
134265  * Endpoint Enable (EPEna)
134266  *
134267  * Applies to IN and OUT endpoints.
134268  *
134269  * When Scatter/Gather DMA mode is enabled,
134270  *
134271  * For IN endpoints this bit indicates that the descriptor structure and data
134272  * buffer with
134273  *
134274  * data ready to transmit is setup.
134275  *
134276  * For OUT endpoint it indicates that the descriptor structure and data buffer to
134277  *
134278  * receive data is setup.
134279  *
134280  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
134281  *
134282  * DMA mode:
134283  *
134284  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
134285  * the
134286  *
134287  * endpoint.
134288  *
134289  * * For OUT endpoints, this bit indicates that the application has allocated the
134290  *
134291  * memory to start receiving data from the USB.
134292  *
134293  * * The core clears this bit before setting any of the following interrupts on
134294  * this
134295  *
134296  * endpoint:
134297  *
134298  * SETUP Phase Done
134299  *
134300  * Endpoint Disabled
134301  *
134302  * Transfer Completed
134303  *
134304  * Note: For control endpoints in DMA mode, this bit must be set to be able to
134305  * transfer
134306  *
134307  * SETUP data packets in memory.
134308  *
134309  * Field Enumeration Values:
134310  *
134311  * Enum | Value | Description
134312  * :------------------------------------|:------|:-------------------------
134313  * ALT_USB_DEV_DOEPCTL14_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
134314  * ALT_USB_DEV_DOEPCTL14_EPENA_E_ACT | 0x1 | Endpoint Enable active
134315  *
134316  * Field Access Macros:
134317  *
134318  */
134319 /*
134320  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPENA
134321  *
134322  * Endpoint Enable inactive
134323  */
134324 #define ALT_USB_DEV_DOEPCTL14_EPENA_E_INACT 0x0
134325 /*
134326  * Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPENA
134327  *
134328  * Endpoint Enable active
134329  */
134330 #define ALT_USB_DEV_DOEPCTL14_EPENA_E_ACT 0x1
134331 
134332 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */
134333 #define ALT_USB_DEV_DOEPCTL14_EPENA_LSB 31
134334 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */
134335 #define ALT_USB_DEV_DOEPCTL14_EPENA_MSB 31
134336 /* The width in bits of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */
134337 #define ALT_USB_DEV_DOEPCTL14_EPENA_WIDTH 1
134338 /* The mask used to set the ALT_USB_DEV_DOEPCTL14_EPENA register field value. */
134339 #define ALT_USB_DEV_DOEPCTL14_EPENA_SET_MSK 0x80000000
134340 /* The mask used to clear the ALT_USB_DEV_DOEPCTL14_EPENA register field value. */
134341 #define ALT_USB_DEV_DOEPCTL14_EPENA_CLR_MSK 0x7fffffff
134342 /* The reset value of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */
134343 #define ALT_USB_DEV_DOEPCTL14_EPENA_RESET 0x0
134344 /* Extracts the ALT_USB_DEV_DOEPCTL14_EPENA field value from a register. */
134345 #define ALT_USB_DEV_DOEPCTL14_EPENA_GET(value) (((value) & 0x80000000) >> 31)
134346 /* Produces a ALT_USB_DEV_DOEPCTL14_EPENA register field value suitable for setting the register. */
134347 #define ALT_USB_DEV_DOEPCTL14_EPENA_SET(value) (((value) << 31) & 0x80000000)
134348 
134349 #ifndef __ASSEMBLY__
134350 /*
134351  * WARNING: The C register and register group struct declarations are provided for
134352  * convenience and illustrative purposes. They should, however, be used with
134353  * caution as the C language standard provides no guarantees about the alignment or
134354  * atomicity of device memory accesses. The recommended practice for writing
134355  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
134356  * alt_write_word() functions.
134357  *
134358  * The struct declaration for register ALT_USB_DEV_DOEPCTL14.
134359  */
134360 struct ALT_USB_DEV_DOEPCTL14_s
134361 {
134362  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL14_MPS */
134363  uint32_t : 4; /* *UNDEFINED* */
134364  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL14_USBACTEP */
134365  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL14_DPID */
134366  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL14_NAKSTS */
134367  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL14_EPTYPE */
134368  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL14_SNP */
134369  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL14_STALL */
134370  uint32_t : 4; /* *UNDEFINED* */
134371  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL14_CNAK */
134372  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL14_SNAK */
134373  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL14_SETD0PID */
134374  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL14_SETD1PID */
134375  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL14_EPDIS */
134376  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL14_EPENA */
134377 };
134378 
134379 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL14. */
134380 typedef volatile struct ALT_USB_DEV_DOEPCTL14_s ALT_USB_DEV_DOEPCTL14_t;
134381 #endif /* __ASSEMBLY__ */
134382 
134383 /* The reset value of the ALT_USB_DEV_DOEPCTL14 register. */
134384 #define ALT_USB_DEV_DOEPCTL14_RESET 0x00000000
134385 /* The byte offset of the ALT_USB_DEV_DOEPCTL14 register from the beginning of the component. */
134386 #define ALT_USB_DEV_DOEPCTL14_OFST 0x4c0
134387 /* The address of the ALT_USB_DEV_DOEPCTL14 register. */
134388 #define ALT_USB_DEV_DOEPCTL14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL14_OFST))
134389 
134390 /*
134391  * Register : doepint14
134392  *
134393  * Device OUT Endpoint 14 Interrupt Register
134394  *
134395  * Register Layout
134396  *
134397  * Bits | Access | Reset | Description
134398  * :--------|:-------|:------|:-------------------------------------
134399  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_XFERCOMPL
134400  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_EPDISBLD
134401  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_AHBERR
134402  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_SETUP
134403  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS
134404  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_STSPHSERCVD
134405  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP
134406  * [7] | ??? | 0x0 | *UNDEFINED*
134407  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_OUTPKTERR
134408  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_BNAINTR
134409  * [10] | ??? | 0x0 | *UNDEFINED*
134410  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_PKTDRPSTS
134411  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_BBLEERR
134412  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_NAKINTRPT
134413  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_NYETINTRPT
134414  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_STUPPKTRCVD
134415  * [31:16] | ??? | 0x0 | *UNDEFINED*
134416  *
134417  */
134418 /*
134419  * Field : xfercompl
134420  *
134421  * Transfer Completed Interrupt (XferCompl)
134422  *
134423  * Applies to IN and OUT endpoints.
134424  *
134425  * When Scatter/Gather DMA mode is enabled
134426  *
134427  * * For IN endpoint this field indicates that the requested data
134428  *
134429  * from the descriptor is moved from external system memory
134430  *
134431  * to internal FIFO.
134432  *
134433  * * For OUT endpoint this field indicates that the requested
134434  *
134435  * data from the internal FIFO is moved to external system
134436  *
134437  * memory. This interrupt is generated only when the
134438  *
134439  * corresponding endpoint descriptor is closed, and the IOC
134440  *
134441  * bit For the corresponding descriptor is Set.
134442  *
134443  * When Scatter/Gather DMA mode is disabled, this field
134444  *
134445  * indicates that the programmed transfer is complete on the
134446  *
134447  * AHB as well as on the USB, For this endpoint.
134448  *
134449  * Field Enumeration Values:
134450  *
134451  * Enum | Value | Description
134452  * :----------------------------------------|:------|:-----------------------------
134453  * ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_INACT | 0x0 | No Interrupt
134454  * ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
134455  *
134456  * Field Access Macros:
134457  *
134458  */
134459 /*
134460  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_XFERCOMPL
134461  *
134462  * No Interrupt
134463  */
134464 #define ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_INACT 0x0
134465 /*
134466  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_XFERCOMPL
134467  *
134468  * Transfer Completed Interrupt
134469  */
134470 #define ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_ACT 0x1
134471 
134472 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */
134473 #define ALT_USB_DEV_DOEPINT14_XFERCOMPL_LSB 0
134474 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */
134475 #define ALT_USB_DEV_DOEPINT14_XFERCOMPL_MSB 0
134476 /* The width in bits of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */
134477 #define ALT_USB_DEV_DOEPINT14_XFERCOMPL_WIDTH 1
134478 /* The mask used to set the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field value. */
134479 #define ALT_USB_DEV_DOEPINT14_XFERCOMPL_SET_MSK 0x00000001
134480 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field value. */
134481 #define ALT_USB_DEV_DOEPINT14_XFERCOMPL_CLR_MSK 0xfffffffe
134482 /* The reset value of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */
134483 #define ALT_USB_DEV_DOEPINT14_XFERCOMPL_RESET 0x0
134484 /* Extracts the ALT_USB_DEV_DOEPINT14_XFERCOMPL field value from a register. */
134485 #define ALT_USB_DEV_DOEPINT14_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
134486 /* Produces a ALT_USB_DEV_DOEPINT14_XFERCOMPL register field value suitable for setting the register. */
134487 #define ALT_USB_DEV_DOEPINT14_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
134488 
134489 /*
134490  * Field : epdisbld
134491  *
134492  * Endpoint Disabled Interrupt (EPDisbld)
134493  *
134494  * Applies to IN and OUT endpoints.
134495  *
134496  * This bit indicates that the endpoint is disabled per the
134497  *
134498  * application's request.
134499  *
134500  * Field Enumeration Values:
134501  *
134502  * Enum | Value | Description
134503  * :---------------------------------------|:------|:----------------------------
134504  * ALT_USB_DEV_DOEPINT14_EPDISBLD_E_INACT | 0x0 | No Interrupt
134505  * ALT_USB_DEV_DOEPINT14_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
134506  *
134507  * Field Access Macros:
134508  *
134509  */
134510 /*
134511  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_EPDISBLD
134512  *
134513  * No Interrupt
134514  */
134515 #define ALT_USB_DEV_DOEPINT14_EPDISBLD_E_INACT 0x0
134516 /*
134517  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_EPDISBLD
134518  *
134519  * Endpoint Disabled Interrupt
134520  */
134521 #define ALT_USB_DEV_DOEPINT14_EPDISBLD_E_ACT 0x1
134522 
134523 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */
134524 #define ALT_USB_DEV_DOEPINT14_EPDISBLD_LSB 1
134525 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */
134526 #define ALT_USB_DEV_DOEPINT14_EPDISBLD_MSB 1
134527 /* The width in bits of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */
134528 #define ALT_USB_DEV_DOEPINT14_EPDISBLD_WIDTH 1
134529 /* The mask used to set the ALT_USB_DEV_DOEPINT14_EPDISBLD register field value. */
134530 #define ALT_USB_DEV_DOEPINT14_EPDISBLD_SET_MSK 0x00000002
134531 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_EPDISBLD register field value. */
134532 #define ALT_USB_DEV_DOEPINT14_EPDISBLD_CLR_MSK 0xfffffffd
134533 /* The reset value of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */
134534 #define ALT_USB_DEV_DOEPINT14_EPDISBLD_RESET 0x0
134535 /* Extracts the ALT_USB_DEV_DOEPINT14_EPDISBLD field value from a register. */
134536 #define ALT_USB_DEV_DOEPINT14_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
134537 /* Produces a ALT_USB_DEV_DOEPINT14_EPDISBLD register field value suitable for setting the register. */
134538 #define ALT_USB_DEV_DOEPINT14_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
134539 
134540 /*
134541  * Field : ahberr
134542  *
134543  * AHB Error (AHBErr)
134544  *
134545  * Applies to IN and OUT endpoints.
134546  *
134547  * This is generated only in Internal DMA mode when there is an
134548  *
134549  * AHB error during an AHB read/write. The application can read
134550  *
134551  * the corresponding endpoint DMA address register to get the
134552  *
134553  * error address.
134554  *
134555  * Field Enumeration Values:
134556  *
134557  * Enum | Value | Description
134558  * :-------------------------------------|:------|:--------------------
134559  * ALT_USB_DEV_DOEPINT14_AHBERR_E_INACT | 0x0 | No Interrupt
134560  * ALT_USB_DEV_DOEPINT14_AHBERR_E_ACT | 0x1 | AHB Error interrupt
134561  *
134562  * Field Access Macros:
134563  *
134564  */
134565 /*
134566  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_AHBERR
134567  *
134568  * No Interrupt
134569  */
134570 #define ALT_USB_DEV_DOEPINT14_AHBERR_E_INACT 0x0
134571 /*
134572  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_AHBERR
134573  *
134574  * AHB Error interrupt
134575  */
134576 #define ALT_USB_DEV_DOEPINT14_AHBERR_E_ACT 0x1
134577 
134578 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */
134579 #define ALT_USB_DEV_DOEPINT14_AHBERR_LSB 2
134580 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */
134581 #define ALT_USB_DEV_DOEPINT14_AHBERR_MSB 2
134582 /* The width in bits of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */
134583 #define ALT_USB_DEV_DOEPINT14_AHBERR_WIDTH 1
134584 /* The mask used to set the ALT_USB_DEV_DOEPINT14_AHBERR register field value. */
134585 #define ALT_USB_DEV_DOEPINT14_AHBERR_SET_MSK 0x00000004
134586 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_AHBERR register field value. */
134587 #define ALT_USB_DEV_DOEPINT14_AHBERR_CLR_MSK 0xfffffffb
134588 /* The reset value of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */
134589 #define ALT_USB_DEV_DOEPINT14_AHBERR_RESET 0x0
134590 /* Extracts the ALT_USB_DEV_DOEPINT14_AHBERR field value from a register. */
134591 #define ALT_USB_DEV_DOEPINT14_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
134592 /* Produces a ALT_USB_DEV_DOEPINT14_AHBERR register field value suitable for setting the register. */
134593 #define ALT_USB_DEV_DOEPINT14_AHBERR_SET(value) (((value) << 2) & 0x00000004)
134594 
134595 /*
134596  * Field : setup
134597  *
134598  * SETUP Phase Done (SetUp)
134599  *
134600  * Applies to control OUT endpoints only.
134601  *
134602  * Indicates that the SETUP phase For the control endpoint is
134603  *
134604  * complete and no more back-to-back SETUP packets were
134605  *
134606  * received For the current control transfer. On this interrupt, the
134607  *
134608  * application can decode the received SETUP data packet.
134609  *
134610  * Field Enumeration Values:
134611  *
134612  * Enum | Value | Description
134613  * :------------------------------------|:------|:--------------------
134614  * ALT_USB_DEV_DOEPINT14_SETUP_E_INACT | 0x0 | No SETUP Phase Done
134615  * ALT_USB_DEV_DOEPINT14_SETUP_E_ACT | 0x1 | SETUP Phase Done
134616  *
134617  * Field Access Macros:
134618  *
134619  */
134620 /*
134621  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_SETUP
134622  *
134623  * No SETUP Phase Done
134624  */
134625 #define ALT_USB_DEV_DOEPINT14_SETUP_E_INACT 0x0
134626 /*
134627  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_SETUP
134628  *
134629  * SETUP Phase Done
134630  */
134631 #define ALT_USB_DEV_DOEPINT14_SETUP_E_ACT 0x1
134632 
134633 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_SETUP register field. */
134634 #define ALT_USB_DEV_DOEPINT14_SETUP_LSB 3
134635 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_SETUP register field. */
134636 #define ALT_USB_DEV_DOEPINT14_SETUP_MSB 3
134637 /* The width in bits of the ALT_USB_DEV_DOEPINT14_SETUP register field. */
134638 #define ALT_USB_DEV_DOEPINT14_SETUP_WIDTH 1
134639 /* The mask used to set the ALT_USB_DEV_DOEPINT14_SETUP register field value. */
134640 #define ALT_USB_DEV_DOEPINT14_SETUP_SET_MSK 0x00000008
134641 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_SETUP register field value. */
134642 #define ALT_USB_DEV_DOEPINT14_SETUP_CLR_MSK 0xfffffff7
134643 /* The reset value of the ALT_USB_DEV_DOEPINT14_SETUP register field. */
134644 #define ALT_USB_DEV_DOEPINT14_SETUP_RESET 0x0
134645 /* Extracts the ALT_USB_DEV_DOEPINT14_SETUP field value from a register. */
134646 #define ALT_USB_DEV_DOEPINT14_SETUP_GET(value) (((value) & 0x00000008) >> 3)
134647 /* Produces a ALT_USB_DEV_DOEPINT14_SETUP register field value suitable for setting the register. */
134648 #define ALT_USB_DEV_DOEPINT14_SETUP_SET(value) (((value) << 3) & 0x00000008)
134649 
134650 /*
134651  * Field : outtknepdis
134652  *
134653  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
134654  *
134655  * Applies only to control OUT endpoints.
134656  *
134657  * Indicates that an OUT token was received when the endpoint
134658  *
134659  * was not yet enabled. This interrupt is asserted on the endpoint
134660  *
134661  * For which the OUT token was received.
134662  *
134663  * Field Enumeration Values:
134664  *
134665  * Enum | Value | Description
134666  * :------------------------------------------|:------|:---------------------------------------------
134667  * ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
134668  * ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
134669  *
134670  * Field Access Macros:
134671  *
134672  */
134673 /*
134674  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS
134675  *
134676  * No OUT Token Received When Endpoint Disabled
134677  */
134678 #define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_INACT 0x0
134679 /*
134680  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS
134681  *
134682  * OUT Token Received When Endpoint Disabled
134683  */
134684 #define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_ACT 0x1
134685 
134686 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */
134687 #define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_LSB 4
134688 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */
134689 #define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_MSB 4
134690 /* The width in bits of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */
134691 #define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_WIDTH 1
134692 /* The mask used to set the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field value. */
134693 #define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_SET_MSK 0x00000010
134694 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field value. */
134695 #define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_CLR_MSK 0xffffffef
134696 /* The reset value of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */
134697 #define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_RESET 0x0
134698 /* Extracts the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS field value from a register. */
134699 #define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
134700 /* Produces a ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field value suitable for setting the register. */
134701 #define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
134702 
134703 /*
134704  * Field : stsphsercvd
134705  *
134706  * Status Phase Received For Control Write (StsPhseRcvd)
134707  *
134708  * This interrupt is valid only For Control OUT endpoints and only in
134709  *
134710  * Scatter Gather DMA mode.
134711  *
134712  * This interrupt is generated only after the core has transferred all
134713  *
134714  * the data that the host has sent during the data phase of a control
134715  *
134716  * write transfer, to the system memory buffer.
134717  *
134718  * The interrupt indicates to the application that the host has
134719  *
134720  * switched from data phase to the status phase of a Control Write
134721  *
134722  * transfer. The application can use this interrupt to ACK or STALL
134723  *
134724  * the Status phase, after it has decoded the data phase. This is
134725  *
134726  * applicable only in Case of Scatter Gather DMA mode.
134727  *
134728  * Field Enumeration Values:
134729  *
134730  * Enum | Value | Description
134731  * :------------------------------------------|:------|:-------------------------------------------
134732  * ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
134733  * ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
134734  *
134735  * Field Access Macros:
134736  *
134737  */
134738 /*
134739  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_STSPHSERCVD
134740  *
134741  * No Status Phase Received for Control Write
134742  */
134743 #define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_INACT 0x0
134744 /*
134745  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_STSPHSERCVD
134746  *
134747  * Status Phase Received for Control Write
134748  */
134749 #define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_ACT 0x1
134750 
134751 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */
134752 #define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_LSB 5
134753 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */
134754 #define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_MSB 5
134755 /* The width in bits of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */
134756 #define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_WIDTH 1
134757 /* The mask used to set the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field value. */
134758 #define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_SET_MSK 0x00000020
134759 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field value. */
134760 #define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_CLR_MSK 0xffffffdf
134761 /* The reset value of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */
134762 #define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_RESET 0x0
134763 /* Extracts the ALT_USB_DEV_DOEPINT14_STSPHSERCVD field value from a register. */
134764 #define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
134765 /* Produces a ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field value suitable for setting the register. */
134766 #define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
134767 
134768 /*
134769  * Field : back2backsetup
134770  *
134771  * Back-to-Back SETUP Packets Received (Back2BackSETup)
134772  *
134773  * Applies to Control OUT endpoints only.
134774  *
134775  * This bit indicates that the core has received more than three
134776  *
134777  * back-to-back SETUP packets For this particular endpoint. For
134778  *
134779  * information about handling this interrupt,
134780  *
134781  * Field Enumeration Values:
134782  *
134783  * Enum | Value | Description
134784  * :---------------------------------------------|:------|:---------------------------------------
134785  * ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
134786  * ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
134787  *
134788  * Field Access Macros:
134789  *
134790  */
134791 /*
134792  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP
134793  *
134794  * No Back-to-Back SETUP Packets Received
134795  */
134796 #define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_INACT 0x0
134797 /*
134798  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP
134799  *
134800  * Back-to-Back SETUP Packets Received
134801  */
134802 #define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_ACT 0x1
134803 
134804 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */
134805 #define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_LSB 6
134806 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */
134807 #define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_MSB 6
134808 /* The width in bits of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */
134809 #define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_WIDTH 1
134810 /* The mask used to set the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field value. */
134811 #define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_SET_MSK 0x00000040
134812 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field value. */
134813 #define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_CLR_MSK 0xffffffbf
134814 /* The reset value of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */
134815 #define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_RESET 0x0
134816 /* Extracts the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP field value from a register. */
134817 #define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
134818 /* Produces a ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field value suitable for setting the register. */
134819 #define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
134820 
134821 /*
134822  * Field : outpkterr
134823  *
134824  * OUT Packet Error (OutPktErr)
134825  *
134826  * Applies to OUT endpoints Only
134827  *
134828  * This interrupt is valid only when thresholding is enabled. This interrupt is
134829  * asserted when the
134830  *
134831  * core detects an overflow or a CRC error For non-Isochronous
134832  *
134833  * OUT packet.
134834  *
134835  * Field Enumeration Values:
134836  *
134837  * Enum | Value | Description
134838  * :----------------------------------------|:------|:--------------------
134839  * ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
134840  * ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
134841  *
134842  * Field Access Macros:
134843  *
134844  */
134845 /*
134846  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTPKTERR
134847  *
134848  * No OUT Packet Error
134849  */
134850 #define ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_INACT 0x0
134851 /*
134852  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTPKTERR
134853  *
134854  * OUT Packet Error
134855  */
134856 #define ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_ACT 0x1
134857 
134858 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */
134859 #define ALT_USB_DEV_DOEPINT14_OUTPKTERR_LSB 8
134860 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */
134861 #define ALT_USB_DEV_DOEPINT14_OUTPKTERR_MSB 8
134862 /* The width in bits of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */
134863 #define ALT_USB_DEV_DOEPINT14_OUTPKTERR_WIDTH 1
134864 /* The mask used to set the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field value. */
134865 #define ALT_USB_DEV_DOEPINT14_OUTPKTERR_SET_MSK 0x00000100
134866 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field value. */
134867 #define ALT_USB_DEV_DOEPINT14_OUTPKTERR_CLR_MSK 0xfffffeff
134868 /* The reset value of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */
134869 #define ALT_USB_DEV_DOEPINT14_OUTPKTERR_RESET 0x0
134870 /* Extracts the ALT_USB_DEV_DOEPINT14_OUTPKTERR field value from a register. */
134871 #define ALT_USB_DEV_DOEPINT14_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
134872 /* Produces a ALT_USB_DEV_DOEPINT14_OUTPKTERR register field value suitable for setting the register. */
134873 #define ALT_USB_DEV_DOEPINT14_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
134874 
134875 /*
134876  * Field : bnaintr
134877  *
134878  * BNA (Buffer Not Available) Interrupt (BNAIntr)
134879  *
134880  * This bit is valid only when Scatter/Gather DMA mode is enabled.
134881  *
134882  * The core generates this interrupt when the descriptor accessed
134883  *
134884  * is not ready For the Core to process, such as Host busy or DMA
134885  *
134886  * done
134887  *
134888  * Field Enumeration Values:
134889  *
134890  * Enum | Value | Description
134891  * :--------------------------------------|:------|:--------------
134892  * ALT_USB_DEV_DOEPINT14_BNAINTR_E_INACT | 0x0 | No interrupt
134893  * ALT_USB_DEV_DOEPINT14_BNAINTR_E_ACT | 0x1 | BNA interrupt
134894  *
134895  * Field Access Macros:
134896  *
134897  */
134898 /*
134899  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BNAINTR
134900  *
134901  * No interrupt
134902  */
134903 #define ALT_USB_DEV_DOEPINT14_BNAINTR_E_INACT 0x0
134904 /*
134905  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BNAINTR
134906  *
134907  * BNA interrupt
134908  */
134909 #define ALT_USB_DEV_DOEPINT14_BNAINTR_E_ACT 0x1
134910 
134911 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */
134912 #define ALT_USB_DEV_DOEPINT14_BNAINTR_LSB 9
134913 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */
134914 #define ALT_USB_DEV_DOEPINT14_BNAINTR_MSB 9
134915 /* The width in bits of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */
134916 #define ALT_USB_DEV_DOEPINT14_BNAINTR_WIDTH 1
134917 /* The mask used to set the ALT_USB_DEV_DOEPINT14_BNAINTR register field value. */
134918 #define ALT_USB_DEV_DOEPINT14_BNAINTR_SET_MSK 0x00000200
134919 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_BNAINTR register field value. */
134920 #define ALT_USB_DEV_DOEPINT14_BNAINTR_CLR_MSK 0xfffffdff
134921 /* The reset value of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */
134922 #define ALT_USB_DEV_DOEPINT14_BNAINTR_RESET 0x0
134923 /* Extracts the ALT_USB_DEV_DOEPINT14_BNAINTR field value from a register. */
134924 #define ALT_USB_DEV_DOEPINT14_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
134925 /* Produces a ALT_USB_DEV_DOEPINT14_BNAINTR register field value suitable for setting the register. */
134926 #define ALT_USB_DEV_DOEPINT14_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
134927 
134928 /*
134929  * Field : pktdrpsts
134930  *
134931  * Packet Drop Status (PktDrpSts)
134932  *
134933  * This bit indicates to the application that an ISOC OUT packet has been dropped.
134934  * This
134935  *
134936  * bit does not have an associated mask bit and does not generate an interrupt.
134937  *
134938  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
134939  * transfer
134940  *
134941  * interrupt feature is selected.
134942  *
134943  * Field Enumeration Values:
134944  *
134945  * Enum | Value | Description
134946  * :----------------------------------------|:------|:-----------------------------
134947  * ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_INACT | 0x0 | No interrupt
134948  * ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
134949  *
134950  * Field Access Macros:
134951  *
134952  */
134953 /*
134954  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_PKTDRPSTS
134955  *
134956  * No interrupt
134957  */
134958 #define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_INACT 0x0
134959 /*
134960  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_PKTDRPSTS
134961  *
134962  * Packet Drop Status interrupt
134963  */
134964 #define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_ACT 0x1
134965 
134966 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */
134967 #define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_LSB 11
134968 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */
134969 #define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_MSB 11
134970 /* The width in bits of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */
134971 #define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_WIDTH 1
134972 /* The mask used to set the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field value. */
134973 #define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_SET_MSK 0x00000800
134974 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field value. */
134975 #define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_CLR_MSK 0xfffff7ff
134976 /* The reset value of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */
134977 #define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_RESET 0x0
134978 /* Extracts the ALT_USB_DEV_DOEPINT14_PKTDRPSTS field value from a register. */
134979 #define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
134980 /* Produces a ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field value suitable for setting the register. */
134981 #define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
134982 
134983 /*
134984  * Field : bbleerr
134985  *
134986  * NAK Interrupt (BbleErr)
134987  *
134988  * The core generates this interrupt when babble is received for the endpoint.
134989  *
134990  * Field Enumeration Values:
134991  *
134992  * Enum | Value | Description
134993  * :--------------------------------------|:------|:------------------
134994  * ALT_USB_DEV_DOEPINT14_BBLEERR_E_INACT | 0x0 | No interrupt
134995  * ALT_USB_DEV_DOEPINT14_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
134996  *
134997  * Field Access Macros:
134998  *
134999  */
135000 /*
135001  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BBLEERR
135002  *
135003  * No interrupt
135004  */
135005 #define ALT_USB_DEV_DOEPINT14_BBLEERR_E_INACT 0x0
135006 /*
135007  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_BBLEERR
135008  *
135009  * BbleErr interrupt
135010  */
135011 #define ALT_USB_DEV_DOEPINT14_BBLEERR_E_ACT 0x1
135012 
135013 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */
135014 #define ALT_USB_DEV_DOEPINT14_BBLEERR_LSB 12
135015 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */
135016 #define ALT_USB_DEV_DOEPINT14_BBLEERR_MSB 12
135017 /* The width in bits of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */
135018 #define ALT_USB_DEV_DOEPINT14_BBLEERR_WIDTH 1
135019 /* The mask used to set the ALT_USB_DEV_DOEPINT14_BBLEERR register field value. */
135020 #define ALT_USB_DEV_DOEPINT14_BBLEERR_SET_MSK 0x00001000
135021 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_BBLEERR register field value. */
135022 #define ALT_USB_DEV_DOEPINT14_BBLEERR_CLR_MSK 0xffffefff
135023 /* The reset value of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */
135024 #define ALT_USB_DEV_DOEPINT14_BBLEERR_RESET 0x0
135025 /* Extracts the ALT_USB_DEV_DOEPINT14_BBLEERR field value from a register. */
135026 #define ALT_USB_DEV_DOEPINT14_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
135027 /* Produces a ALT_USB_DEV_DOEPINT14_BBLEERR register field value suitable for setting the register. */
135028 #define ALT_USB_DEV_DOEPINT14_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
135029 
135030 /*
135031  * Field : nakintrpt
135032  *
135033  * NAK Interrupt (NAKInterrupt)
135034  *
135035  * The core generates this interrupt when a NAK is transmitted or received by the
135036  * device.
135037  *
135038  * In case of isochronous IN endpoints the interrupt gets generated when a zero
135039  * length
135040  *
135041  * packet is transmitted due to un-availability of data in the TXFifo.
135042  *
135043  * Field Enumeration Values:
135044  *
135045  * Enum | Value | Description
135046  * :----------------------------------------|:------|:--------------
135047  * ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_INACT | 0x0 | No interrupt
135048  * ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
135049  *
135050  * Field Access Macros:
135051  *
135052  */
135053 /*
135054  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_NAKINTRPT
135055  *
135056  * No interrupt
135057  */
135058 #define ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_INACT 0x0
135059 /*
135060  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_NAKINTRPT
135061  *
135062  * NAK Interrupt
135063  */
135064 #define ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_ACT 0x1
135065 
135066 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */
135067 #define ALT_USB_DEV_DOEPINT14_NAKINTRPT_LSB 13
135068 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */
135069 #define ALT_USB_DEV_DOEPINT14_NAKINTRPT_MSB 13
135070 /* The width in bits of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */
135071 #define ALT_USB_DEV_DOEPINT14_NAKINTRPT_WIDTH 1
135072 /* The mask used to set the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field value. */
135073 #define ALT_USB_DEV_DOEPINT14_NAKINTRPT_SET_MSK 0x00002000
135074 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field value. */
135075 #define ALT_USB_DEV_DOEPINT14_NAKINTRPT_CLR_MSK 0xffffdfff
135076 /* The reset value of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */
135077 #define ALT_USB_DEV_DOEPINT14_NAKINTRPT_RESET 0x0
135078 /* Extracts the ALT_USB_DEV_DOEPINT14_NAKINTRPT field value from a register. */
135079 #define ALT_USB_DEV_DOEPINT14_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
135080 /* Produces a ALT_USB_DEV_DOEPINT14_NAKINTRPT register field value suitable for setting the register. */
135081 #define ALT_USB_DEV_DOEPINT14_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
135082 
135083 /*
135084  * Field : nyetintrpt
135085  *
135086  * NYET Interrupt (NYETIntrpt)
135087  *
135088  * The core generates this interrupt when a NYET response is transmitted for a non
135089  * isochronous OUT endpoint.
135090  *
135091  * Field Enumeration Values:
135092  *
135093  * Enum | Value | Description
135094  * :-----------------------------------------|:------|:---------------
135095  * ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_INACT | 0x0 | No interrupt
135096  * ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
135097  *
135098  * Field Access Macros:
135099  *
135100  */
135101 /*
135102  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_NYETINTRPT
135103  *
135104  * No interrupt
135105  */
135106 #define ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_INACT 0x0
135107 /*
135108  * Enumerated value for register field ALT_USB_DEV_DOEPINT14_NYETINTRPT
135109  *
135110  * NYET Interrupt
135111  */
135112 #define ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_ACT 0x1
135113 
135114 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */
135115 #define ALT_USB_DEV_DOEPINT14_NYETINTRPT_LSB 14
135116 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */
135117 #define ALT_USB_DEV_DOEPINT14_NYETINTRPT_MSB 14
135118 /* The width in bits of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */
135119 #define ALT_USB_DEV_DOEPINT14_NYETINTRPT_WIDTH 1
135120 /* The mask used to set the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field value. */
135121 #define ALT_USB_DEV_DOEPINT14_NYETINTRPT_SET_MSK 0x00004000
135122 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field value. */
135123 #define ALT_USB_DEV_DOEPINT14_NYETINTRPT_CLR_MSK 0xffffbfff
135124 /* The reset value of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */
135125 #define ALT_USB_DEV_DOEPINT14_NYETINTRPT_RESET 0x0
135126 /* Extracts the ALT_USB_DEV_DOEPINT14_NYETINTRPT field value from a register. */
135127 #define ALT_USB_DEV_DOEPINT14_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
135128 /* Produces a ALT_USB_DEV_DOEPINT14_NYETINTRPT register field value suitable for setting the register. */
135129 #define ALT_USB_DEV_DOEPINT14_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
135130 
135131 /*
135132  * Field : stuppktrcvd
135133  *
135134  * Setup Packet Received
135135  *
135136  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
135137  *
135138  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
135139  *
135140  * setup data. There is only one Setup packet per buffer. On receiving a
135141  *
135142  * Setup packet, the DWC_otg core closes the buffer and disables the
135143  *
135144  * corresponding endpoint. The application has to re-enable the endpoint to
135145  *
135146  * receive any OUT data for the Control Transfer and reprogram the buffer
135147  *
135148  * start address.
135149  *
135150  * Note: Because of the above behavior, the DWC_otg core can receive any
135151  *
135152  * number of back to back setup packets and one buffer for every setup
135153  *
135154  * packet is used.
135155  *
135156  * 1'b0: No Setup packet received
135157  *
135158  * 1'b1: Setup packet received
135159  *
135160  * Reset: 1'b0
135161  *
135162  * Field Access Macros:
135163  *
135164  */
135165 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field. */
135166 #define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_LSB 15
135167 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field. */
135168 #define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_MSB 15
135169 /* The width in bits of the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field. */
135170 #define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_WIDTH 1
135171 /* The mask used to set the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field value. */
135172 #define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_SET_MSK 0x00008000
135173 /* The mask used to clear the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field value. */
135174 #define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_CLR_MSK 0xffff7fff
135175 /* The reset value of the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field. */
135176 #define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_RESET 0x0
135177 /* Extracts the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD field value from a register. */
135178 #define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
135179 /* Produces a ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field value suitable for setting the register. */
135180 #define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
135181 
135182 #ifndef __ASSEMBLY__
135183 /*
135184  * WARNING: The C register and register group struct declarations are provided for
135185  * convenience and illustrative purposes. They should, however, be used with
135186  * caution as the C language standard provides no guarantees about the alignment or
135187  * atomicity of device memory accesses. The recommended practice for writing
135188  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
135189  * alt_write_word() functions.
135190  *
135191  * The struct declaration for register ALT_USB_DEV_DOEPINT14.
135192  */
135193 struct ALT_USB_DEV_DOEPINT14_s
135194 {
135195  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT14_XFERCOMPL */
135196  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT14_EPDISBLD */
135197  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT14_AHBERR */
135198  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT14_SETUP */
135199  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS */
135200  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT14_STSPHSERCVD */
135201  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP */
135202  uint32_t : 1; /* *UNDEFINED* */
135203  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT14_OUTPKTERR */
135204  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT14_BNAINTR */
135205  uint32_t : 1; /* *UNDEFINED* */
135206  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT14_PKTDRPSTS */
135207  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT14_BBLEERR */
135208  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT14_NAKINTRPT */
135209  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT14_NYETINTRPT */
135210  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT14_STUPPKTRCVD */
135211  uint32_t : 16; /* *UNDEFINED* */
135212 };
135213 
135214 /* The typedef declaration for register ALT_USB_DEV_DOEPINT14. */
135215 typedef volatile struct ALT_USB_DEV_DOEPINT14_s ALT_USB_DEV_DOEPINT14_t;
135216 #endif /* __ASSEMBLY__ */
135217 
135218 /* The reset value of the ALT_USB_DEV_DOEPINT14 register. */
135219 #define ALT_USB_DEV_DOEPINT14_RESET 0x00000000
135220 /* The byte offset of the ALT_USB_DEV_DOEPINT14 register from the beginning of the component. */
135221 #define ALT_USB_DEV_DOEPINT14_OFST 0x4c8
135222 /* The address of the ALT_USB_DEV_DOEPINT14 register. */
135223 #define ALT_USB_DEV_DOEPINT14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT14_OFST))
135224 
135225 /*
135226  * Register : doeptsiz14
135227  *
135228  * Device OUT Endpoint 14 Transfer Size Register
135229  *
135230  * Register Layout
135231  *
135232  * Bits | Access | Reset | Description
135233  * :--------|:-------|:------|:--------------------------------
135234  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ14_XFERSIZE
135235  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ14_PKTCNT
135236  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ14_RXDPID
135237  * [31] | ??? | 0x0 | *UNDEFINED*
135238  *
135239  */
135240 /*
135241  * Field : xfersize
135242  *
135243  * Transfer Size (XferSize)
135244  *
135245  * Indicates the transfer size in bytes For endpoint 0. The core
135246  *
135247  * interrupts the application only after it has exhausted the transfer
135248  *
135249  * size amount of data. The transfer size can be Set to the
135250  *
135251  * maximum packet size of the endpoint, to be interrupted at the
135252  *
135253  * end of each packet.
135254  *
135255  * The core decrements this field every time a packet is read from
135256  *
135257  * the RxFIFO and written to the external memory.
135258  *
135259  * Field Access Macros:
135260  *
135261  */
135262 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */
135263 #define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_LSB 0
135264 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */
135265 #define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_MSB 18
135266 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */
135267 #define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_WIDTH 19
135268 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field value. */
135269 #define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_SET_MSK 0x0007ffff
135270 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field value. */
135271 #define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_CLR_MSK 0xfff80000
135272 /* The reset value of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */
135273 #define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_RESET 0x0
135274 /* Extracts the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE field value from a register. */
135275 #define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
135276 /* Produces a ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field value suitable for setting the register. */
135277 #define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
135278 
135279 /*
135280  * Field : pktcnt
135281  *
135282  * Packet Count (PktCnt)
135283  *
135284  * This field is decremented to zero after a packet is written into the
135285  *
135286  * RxFIFO.
135287  *
135288  * Field Access Macros:
135289  *
135290  */
135291 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */
135292 #define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_LSB 19
135293 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */
135294 #define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_MSB 28
135295 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */
135296 #define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_WIDTH 10
135297 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field value. */
135298 #define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_SET_MSK 0x1ff80000
135299 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field value. */
135300 #define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_CLR_MSK 0xe007ffff
135301 /* The reset value of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */
135302 #define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_RESET 0x0
135303 /* Extracts the ALT_USB_DEV_DOEPTSIZ14_PKTCNT field value from a register. */
135304 #define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
135305 /* Produces a ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field value suitable for setting the register. */
135306 #define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
135307 
135308 /*
135309  * Field : rxdpid
135310  *
135311  * Applies to isochronous OUT endpoints only.
135312  *
135313  * This is the data PID received in the last packet for this endpoint.
135314  *
135315  * 2'b00: DATA0
135316  *
135317  * 2'b01: DATA2
135318  *
135319  * 2'b10: DATA1
135320  *
135321  * 2'b11: MDATA
135322  *
135323  * SETUP Packet Count (SUPCnt)
135324  *
135325  * Applies to control OUT Endpoints only.
135326  *
135327  * This field specifies the number of back-to-back SETUP data
135328  *
135329  * packets the endpoint can receive.
135330  *
135331  * 2'b01: 1 packet
135332  *
135333  * 2'b10: 2 packets
135334  *
135335  * 2'b11: 3 packets
135336  *
135337  * Field Enumeration Values:
135338  *
135339  * Enum | Value | Description
135340  * :------------------------------------------|:------|:-------------------
135341  * ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA0 | 0x0 | DATA0
135342  * ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
135343  * ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
135344  * ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
135345  *
135346  * Field Access Macros:
135347  *
135348  */
135349 /*
135350  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID
135351  *
135352  * DATA0
135353  */
135354 #define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA0 0x0
135355 /*
135356  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID
135357  *
135358  * DATA2 or 1 packet
135359  */
135360 #define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA2PKT1 0x1
135361 /*
135362  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID
135363  *
135364  * DATA1 or 2 packets
135365  */
135366 #define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA1PKT2 0x2
135367 /*
135368  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID
135369  *
135370  * MDATA or 3 packets
135371  */
135372 #define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_MDATAPKT3 0x3
135373 
135374 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */
135375 #define ALT_USB_DEV_DOEPTSIZ14_RXDPID_LSB 29
135376 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */
135377 #define ALT_USB_DEV_DOEPTSIZ14_RXDPID_MSB 30
135378 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */
135379 #define ALT_USB_DEV_DOEPTSIZ14_RXDPID_WIDTH 2
135380 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field value. */
135381 #define ALT_USB_DEV_DOEPTSIZ14_RXDPID_SET_MSK 0x60000000
135382 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field value. */
135383 #define ALT_USB_DEV_DOEPTSIZ14_RXDPID_CLR_MSK 0x9fffffff
135384 /* The reset value of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */
135385 #define ALT_USB_DEV_DOEPTSIZ14_RXDPID_RESET 0x0
135386 /* Extracts the ALT_USB_DEV_DOEPTSIZ14_RXDPID field value from a register. */
135387 #define ALT_USB_DEV_DOEPTSIZ14_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
135388 /* Produces a ALT_USB_DEV_DOEPTSIZ14_RXDPID register field value suitable for setting the register. */
135389 #define ALT_USB_DEV_DOEPTSIZ14_RXDPID_SET(value) (((value) << 29) & 0x60000000)
135390 
135391 #ifndef __ASSEMBLY__
135392 /*
135393  * WARNING: The C register and register group struct declarations are provided for
135394  * convenience and illustrative purposes. They should, however, be used with
135395  * caution as the C language standard provides no guarantees about the alignment or
135396  * atomicity of device memory accesses. The recommended practice for writing
135397  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
135398  * alt_write_word() functions.
135399  *
135400  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ14.
135401  */
135402 struct ALT_USB_DEV_DOEPTSIZ14_s
135403 {
135404  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ14_XFERSIZE */
135405  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ14_PKTCNT */
135406  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ14_RXDPID */
135407  uint32_t : 1; /* *UNDEFINED* */
135408 };
135409 
135410 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ14. */
135411 typedef volatile struct ALT_USB_DEV_DOEPTSIZ14_s ALT_USB_DEV_DOEPTSIZ14_t;
135412 #endif /* __ASSEMBLY__ */
135413 
135414 /* The reset value of the ALT_USB_DEV_DOEPTSIZ14 register. */
135415 #define ALT_USB_DEV_DOEPTSIZ14_RESET 0x00000000
135416 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ14 register from the beginning of the component. */
135417 #define ALT_USB_DEV_DOEPTSIZ14_OFST 0x4d0
135418 /* The address of the ALT_USB_DEV_DOEPTSIZ14 register. */
135419 #define ALT_USB_DEV_DOEPTSIZ14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ14_OFST))
135420 
135421 /*
135422  * Register : doepdma14
135423  *
135424  * Device OUT Endpoint 14 DMA Address Register
135425  *
135426  * Register Layout
135427  *
135428  * Bits | Access | Reset | Description
135429  * :-------|:-------|:--------|:--------------------------------
135430  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA14_DOEPDMA14
135431  *
135432  */
135433 /*
135434  * Field : doepdma14
135435  *
135436  * Holds the start address of the external memory for storing or fetching endpoint
135437  *
135438  * data.
135439  *
135440  * Note: For control endpoints, this field stores control OUT data packets as well
135441  * as
135442  *
135443  * SETUP transaction data packets. When more than three SETUP packets are
135444  *
135445  * received back-to-back, the SETUP data packet in the memory is overwritten.
135446  *
135447  * This register is incremented on every AHB transaction. The application can give
135448  *
135449  * only a DWORD-aligned address.
135450  *
135451  * When Scatter/Gather DMA mode is not enabled, the application programs the
135452  *
135453  * start address value in this field.
135454  *
135455  * When Scatter/Gather DMA mode is enabled, this field indicates the base
135456  *
135457  * pointer for the descriptor list.
135458  *
135459  * Field Access Macros:
135460  *
135461  */
135462 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field. */
135463 #define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_LSB 0
135464 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field. */
135465 #define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_MSB 31
135466 /* The width in bits of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field. */
135467 #define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_WIDTH 32
135468 /* The mask used to set the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field value. */
135469 #define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_SET_MSK 0xffffffff
135470 /* The mask used to clear the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field value. */
135471 #define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_CLR_MSK 0x00000000
135472 /* The reset value of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field is UNKNOWN. */
135473 #define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_RESET 0x0
135474 /* Extracts the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 field value from a register. */
135475 #define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_GET(value) (((value) & 0xffffffff) >> 0)
135476 /* Produces a ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field value suitable for setting the register. */
135477 #define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_SET(value) (((value) << 0) & 0xffffffff)
135478 
135479 #ifndef __ASSEMBLY__
135480 /*
135481  * WARNING: The C register and register group struct declarations are provided for
135482  * convenience and illustrative purposes. They should, however, be used with
135483  * caution as the C language standard provides no guarantees about the alignment or
135484  * atomicity of device memory accesses. The recommended practice for writing
135485  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
135486  * alt_write_word() functions.
135487  *
135488  * The struct declaration for register ALT_USB_DEV_DOEPDMA14.
135489  */
135490 struct ALT_USB_DEV_DOEPDMA14_s
135491 {
135492  uint32_t doepdma14 : 32; /* ALT_USB_DEV_DOEPDMA14_DOEPDMA14 */
135493 };
135494 
135495 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA14. */
135496 typedef volatile struct ALT_USB_DEV_DOEPDMA14_s ALT_USB_DEV_DOEPDMA14_t;
135497 #endif /* __ASSEMBLY__ */
135498 
135499 /* The reset value of the ALT_USB_DEV_DOEPDMA14 register. */
135500 #define ALT_USB_DEV_DOEPDMA14_RESET 0x00000000
135501 /* The byte offset of the ALT_USB_DEV_DOEPDMA14 register from the beginning of the component. */
135502 #define ALT_USB_DEV_DOEPDMA14_OFST 0x4d4
135503 /* The address of the ALT_USB_DEV_DOEPDMA14 register. */
135504 #define ALT_USB_DEV_DOEPDMA14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA14_OFST))
135505 
135506 /*
135507  * Register : doepdmab14
135508  *
135509  * Device OUT Endpoint 14 Buffer Address Register
135510  *
135511  * Register Layout
135512  *
135513  * Bits | Access | Reset | Description
135514  * :-------|:-------|:--------|:----------------------------------
135515  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14
135516  *
135517  */
135518 /*
135519  * Field : doepdmab14
135520  *
135521  * Holds the current buffer address.This register is updated as and when the data
135522  *
135523  * transfer for the corresponding end point is in progress.
135524  *
135525  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
135526  * is
135527  *
135528  * reserved.
135529  *
135530  * Field Access Macros:
135531  *
135532  */
135533 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field. */
135534 #define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_LSB 0
135535 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field. */
135536 #define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_MSB 31
135537 /* The width in bits of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field. */
135538 #define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_WIDTH 32
135539 /* The mask used to set the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field value. */
135540 #define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_SET_MSK 0xffffffff
135541 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field value. */
135542 #define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_CLR_MSK 0x00000000
135543 /* The reset value of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field is UNKNOWN. */
135544 #define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_RESET 0x0
135545 /* Extracts the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 field value from a register. */
135546 #define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_GET(value) (((value) & 0xffffffff) >> 0)
135547 /* Produces a ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field value suitable for setting the register. */
135548 #define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_SET(value) (((value) << 0) & 0xffffffff)
135549 
135550 #ifndef __ASSEMBLY__
135551 /*
135552  * WARNING: The C register and register group struct declarations are provided for
135553  * convenience and illustrative purposes. They should, however, be used with
135554  * caution as the C language standard provides no guarantees about the alignment or
135555  * atomicity of device memory accesses. The recommended practice for writing
135556  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
135557  * alt_write_word() functions.
135558  *
135559  * The struct declaration for register ALT_USB_DEV_DOEPDMAB14.
135560  */
135561 struct ALT_USB_DEV_DOEPDMAB14_s
135562 {
135563  const uint32_t doepdmab14 : 32; /* ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 */
135564 };
135565 
135566 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB14. */
135567 typedef volatile struct ALT_USB_DEV_DOEPDMAB14_s ALT_USB_DEV_DOEPDMAB14_t;
135568 #endif /* __ASSEMBLY__ */
135569 
135570 /* The reset value of the ALT_USB_DEV_DOEPDMAB14 register. */
135571 #define ALT_USB_DEV_DOEPDMAB14_RESET 0x00000000
135572 /* The byte offset of the ALT_USB_DEV_DOEPDMAB14 register from the beginning of the component. */
135573 #define ALT_USB_DEV_DOEPDMAB14_OFST 0x4dc
135574 /* The address of the ALT_USB_DEV_DOEPDMAB14 register. */
135575 #define ALT_USB_DEV_DOEPDMAB14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB14_OFST))
135576 
135577 /*
135578  * Register : doepctl15
135579  *
135580  * Device Control OUT Endpoint 15 Control Register
135581  *
135582  * Register Layout
135583  *
135584  * Bits | Access | Reset | Description
135585  * :--------|:---------|:------|:-------------------------------
135586  * [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL15_MPS
135587  * [14:11] | ??? | 0x0 | *UNDEFINED*
135588  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL15_USBACTEP
135589  * [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL15_DPID
135590  * [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL15_NAKSTS
135591  * [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL15_EPTYPE
135592  * [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL15_SNP
135593  * [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL15_STALL
135594  * [25:22] | ??? | 0x0 | *UNDEFINED*
135595  * [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL15_CNAK
135596  * [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL15_SNAK
135597  * [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL15_SETD0PID
135598  * [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL15_SETD1PID
135599  * [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL15_EPDIS
135600  * [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL15_EPENA
135601  *
135602  */
135603 /*
135604  * Field : mps
135605  *
135606  * Maximum Packet Size (MPS)
135607  *
135608  * The application must program this field with the maximum packet size for the
135609  * current
135610  *
135611  * logical endpoint. This value is in bytes.
135612  *
135613  * Field Access Macros:
135614  *
135615  */
135616 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_MPS register field. */
135617 #define ALT_USB_DEV_DOEPCTL15_MPS_LSB 0
135618 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_MPS register field. */
135619 #define ALT_USB_DEV_DOEPCTL15_MPS_MSB 10
135620 /* The width in bits of the ALT_USB_DEV_DOEPCTL15_MPS register field. */
135621 #define ALT_USB_DEV_DOEPCTL15_MPS_WIDTH 11
135622 /* The mask used to set the ALT_USB_DEV_DOEPCTL15_MPS register field value. */
135623 #define ALT_USB_DEV_DOEPCTL15_MPS_SET_MSK 0x000007ff
135624 /* The mask used to clear the ALT_USB_DEV_DOEPCTL15_MPS register field value. */
135625 #define ALT_USB_DEV_DOEPCTL15_MPS_CLR_MSK 0xfffff800
135626 /* The reset value of the ALT_USB_DEV_DOEPCTL15_MPS register field. */
135627 #define ALT_USB_DEV_DOEPCTL15_MPS_RESET 0x0
135628 /* Extracts the ALT_USB_DEV_DOEPCTL15_MPS field value from a register. */
135629 #define ALT_USB_DEV_DOEPCTL15_MPS_GET(value) (((value) & 0x000007ff) >> 0)
135630 /* Produces a ALT_USB_DEV_DOEPCTL15_MPS register field value suitable for setting the register. */
135631 #define ALT_USB_DEV_DOEPCTL15_MPS_SET(value) (((value) << 0) & 0x000007ff)
135632 
135633 /*
135634  * Field : usbactep
135635  *
135636  * USB Active Endpoint (USBActEP)
135637  *
135638  * Indicates whether this endpoint is active in the current configuration and
135639  * interface. The
135640  *
135641  * core clears this bit for all endpoints (other than EP 0) after detecting a USB
135642  * reset. After
135643  *
135644  * receiving the SetConfiguration and SetInterface commands, the application must
135645  *
135646  * program endpoint registers accordingly and set this bit.
135647  *
135648  * Field Enumeration Values:
135649  *
135650  * Enum | Value | Description
135651  * :--------------------------------------|:------|:--------------------
135652  * ALT_USB_DEV_DOEPCTL15_USBACTEP_E_DISD | 0x0 | Not Active
135653  * ALT_USB_DEV_DOEPCTL15_USBACTEP_E_END | 0x1 | USB Active Endpoint
135654  *
135655  * Field Access Macros:
135656  *
135657  */
135658 /*
135659  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_USBACTEP
135660  *
135661  * Not Active
135662  */
135663 #define ALT_USB_DEV_DOEPCTL15_USBACTEP_E_DISD 0x0
135664 /*
135665  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_USBACTEP
135666  *
135667  * USB Active Endpoint
135668  */
135669 #define ALT_USB_DEV_DOEPCTL15_USBACTEP_E_END 0x1
135670 
135671 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */
135672 #define ALT_USB_DEV_DOEPCTL15_USBACTEP_LSB 15
135673 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */
135674 #define ALT_USB_DEV_DOEPCTL15_USBACTEP_MSB 15
135675 /* The width in bits of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */
135676 #define ALT_USB_DEV_DOEPCTL15_USBACTEP_WIDTH 1
135677 /* The mask used to set the ALT_USB_DEV_DOEPCTL15_USBACTEP register field value. */
135678 #define ALT_USB_DEV_DOEPCTL15_USBACTEP_SET_MSK 0x00008000
135679 /* The mask used to clear the ALT_USB_DEV_DOEPCTL15_USBACTEP register field value. */
135680 #define ALT_USB_DEV_DOEPCTL15_USBACTEP_CLR_MSK 0xffff7fff
135681 /* The reset value of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */
135682 #define ALT_USB_DEV_DOEPCTL15_USBACTEP_RESET 0x0
135683 /* Extracts the ALT_USB_DEV_DOEPCTL15_USBACTEP field value from a register. */
135684 #define ALT_USB_DEV_DOEPCTL15_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
135685 /* Produces a ALT_USB_DEV_DOEPCTL15_USBACTEP register field value suitable for setting the register. */
135686 #define ALT_USB_DEV_DOEPCTL15_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
135687 
135688 /*
135689  * Field : dpid
135690  *
135691  * Endpoint Data PID (DPID)
135692  *
135693  * Applies to interrupt/bulk IN and OUT endpoints only.
135694  *
135695  * Contains the PID of the packet to be received or transmitted on this endpoint.
135696  * The
135697  *
135698  * application must program the PID of the first packet to be received or
135699  * transmitted on
135700  *
135701  * this endpoint, after the endpoint is activated. The applications use the
135702  * SetD1PID and
135703  *
135704  * SetD0PID fields of this register to program either DATA0 or DATA1 PID.
135705  *
135706  * 1'b0: DATA0
135707  *
135708  * 1'b1: DATA1
135709  *
135710  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
135711  *
135712  * DMA mode.
135713  *
135714  * 1'b0 RO
135715  *
135716  * Even/Odd (Micro)Frame (EO_FrNum)
135717  *
135718  * In non-Scatter/Gather DMA mode:
135719  *
135720  * Applies to isochronous IN and OUT endpoints only.
135721  *
135722  * Indicates the (micro)frame number in which the core transmits/receives
135723  * isochronous
135724  *
135725  * data for this endpoint. The application must program the even/odd (micro) frame
135726  *
135727  * number in which it intends to transmit/receive isochronous data for this
135728  * endpoint using
135729  *
135730  * the SetEvnFr and SetOddFr fields in this register.
135731  *
135732  * 1'b0: Even (micro)frame
135733  *
135734  * 1'b1: Odd (micro)frame
135735  *
135736  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
135737  * number
135738  *
135739  * in which to send data is provided in the transmit descriptor structure. The
135740  * frame in
135741  *
135742  * which data is received is updated in receive descriptor structure.
135743  *
135744  * Field Enumeration Values:
135745  *
135746  * Enum | Value | Description
135747  * :-----------------------------------|:------|:-----------------------------
135748  * ALT_USB_DEV_DOEPCTL15_DPID_E_INACT | 0x0 | Endpoint Data PID not active
135749  * ALT_USB_DEV_DOEPCTL15_DPID_E_ACT | 0x1 | Endpoint Data PID active
135750  *
135751  * Field Access Macros:
135752  *
135753  */
135754 /*
135755  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_DPID
135756  *
135757  * Endpoint Data PID not active
135758  */
135759 #define ALT_USB_DEV_DOEPCTL15_DPID_E_INACT 0x0
135760 /*
135761  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_DPID
135762  *
135763  * Endpoint Data PID active
135764  */
135765 #define ALT_USB_DEV_DOEPCTL15_DPID_E_ACT 0x1
135766 
135767 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_DPID register field. */
135768 #define ALT_USB_DEV_DOEPCTL15_DPID_LSB 16
135769 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_DPID register field. */
135770 #define ALT_USB_DEV_DOEPCTL15_DPID_MSB 16
135771 /* The width in bits of the ALT_USB_DEV_DOEPCTL15_DPID register field. */
135772 #define ALT_USB_DEV_DOEPCTL15_DPID_WIDTH 1
135773 /* The mask used to set the ALT_USB_DEV_DOEPCTL15_DPID register field value. */
135774 #define ALT_USB_DEV_DOEPCTL15_DPID_SET_MSK 0x00010000
135775 /* The mask used to clear the ALT_USB_DEV_DOEPCTL15_DPID register field value. */
135776 #define ALT_USB_DEV_DOEPCTL15_DPID_CLR_MSK 0xfffeffff
135777 /* The reset value of the ALT_USB_DEV_DOEPCTL15_DPID register field. */
135778 #define ALT_USB_DEV_DOEPCTL15_DPID_RESET 0x0
135779 /* Extracts the ALT_USB_DEV_DOEPCTL15_DPID field value from a register. */
135780 #define ALT_USB_DEV_DOEPCTL15_DPID_GET(value) (((value) & 0x00010000) >> 16)
135781 /* Produces a ALT_USB_DEV_DOEPCTL15_DPID register field value suitable for setting the register. */
135782 #define ALT_USB_DEV_DOEPCTL15_DPID_SET(value) (((value) << 16) & 0x00010000)
135783 
135784 /*
135785  * Field : naksts
135786  *
135787  * NAK Status (NAKSts)
135788  *
135789  * Indicates the following:
135790  *
135791  * 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
135792  *
135793  * 1'b1: The core is transmitting NAK handshakes on this endpoint.
135794  *
135795  * When either the application or the core sets this bit:
135796  *
135797  * The core stops receiving any data on an OUT endpoint, even if there is space in
135798  *
135799  * the RxFIFO to accommodate the incoming packet.
135800  *
135801  * For non-isochronous IN endpoints: The core stops transmitting any data on an IN
135802  *
135803  * endpoint, even if there data is available in the TxFIFO.
135804  *
135805  * For isochronous IN endpoints: The core sends out a zero-length data packet, even
135806  *
135807  * if there data is available in the TxFIFO.
135808  *
135809  * Irrespective of this bit's setting, the core always responds to SETUP data
135810  * packets with
135811  *
135812  * an ACK handshake.
135813  *
135814  * Field Enumeration Values:
135815  *
135816  * Enum | Value | Description
135817  * :--------------------------------------|:------|:------------------------------------------------
135818  * ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
135819  * : | | based on the FIFO status
135820  * ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
135821  * : | | endpoint
135822  *
135823  * Field Access Macros:
135824  *
135825  */
135826 /*
135827  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_NAKSTS
135828  *
135829  * The core is transmitting non-NAK handshakes based on the FIFO status
135830  */
135831 #define ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NONNAK 0x0
135832 /*
135833  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_NAKSTS
135834  *
135835  * The core is transmitting NAK handshakes on this endpoint
135836  */
135837 #define ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NAK 0x1
135838 
135839 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */
135840 #define ALT_USB_DEV_DOEPCTL15_NAKSTS_LSB 17
135841 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */
135842 #define ALT_USB_DEV_DOEPCTL15_NAKSTS_MSB 17
135843 /* The width in bits of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */
135844 #define ALT_USB_DEV_DOEPCTL15_NAKSTS_WIDTH 1
135845 /* The mask used to set the ALT_USB_DEV_DOEPCTL15_NAKSTS register field value. */
135846 #define ALT_USB_DEV_DOEPCTL15_NAKSTS_SET_MSK 0x00020000
135847 /* The mask used to clear the ALT_USB_DEV_DOEPCTL15_NAKSTS register field value. */
135848 #define ALT_USB_DEV_DOEPCTL15_NAKSTS_CLR_MSK 0xfffdffff
135849 /* The reset value of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */
135850 #define ALT_USB_DEV_DOEPCTL15_NAKSTS_RESET 0x0
135851 /* Extracts the ALT_USB_DEV_DOEPCTL15_NAKSTS field value from a register. */
135852 #define ALT_USB_DEV_DOEPCTL15_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
135853 /* Produces a ALT_USB_DEV_DOEPCTL15_NAKSTS register field value suitable for setting the register. */
135854 #define ALT_USB_DEV_DOEPCTL15_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
135855 
135856 /*
135857  * Field : eptype
135858  *
135859  * Endpoint Type (EPType)
135860  *
135861  * This is the transfer type supported by this logical endpoint.
135862  *
135863  * 2'b00: Control
135864  *
135865  * 2'b01: Isochronous
135866  *
135867  * 2'b10: Bulk
135868  *
135869  * 2'b11: Interrupt
135870  *
135871  * Field Enumeration Values:
135872  *
135873  * Enum | Value | Description
135874  * :-------------------------------------------|:------|:------------
135875  * ALT_USB_DEV_DOEPCTL15_EPTYPE_E_CTL | 0x0 | Control
135876  * ALT_USB_DEV_DOEPCTL15_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
135877  * ALT_USB_DEV_DOEPCTL15_EPTYPE_E_BULK | 0x2 | Bulk
135878  * ALT_USB_DEV_DOEPCTL15_EPTYPE_E_INTERRUP | 0x3 | Interrupt
135879  *
135880  * Field Access Macros:
135881  *
135882  */
135883 /*
135884  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE
135885  *
135886  * Control
135887  */
135888 #define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_CTL 0x0
135889 /*
135890  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE
135891  *
135892  * Isochronous
135893  */
135894 #define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_ISOCHRONOUS 0x1
135895 /*
135896  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE
135897  *
135898  * Bulk
135899  */
135900 #define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_BULK 0x2
135901 /*
135902  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE
135903  *
135904  * Interrupt
135905  */
135906 #define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_INTERRUP 0x3
135907 
135908 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */
135909 #define ALT_USB_DEV_DOEPCTL15_EPTYPE_LSB 18
135910 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */
135911 #define ALT_USB_DEV_DOEPCTL15_EPTYPE_MSB 19
135912 /* The width in bits of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */
135913 #define ALT_USB_DEV_DOEPCTL15_EPTYPE_WIDTH 2
135914 /* The mask used to set the ALT_USB_DEV_DOEPCTL15_EPTYPE register field value. */
135915 #define ALT_USB_DEV_DOEPCTL15_EPTYPE_SET_MSK 0x000c0000
135916 /* The mask used to clear the ALT_USB_DEV_DOEPCTL15_EPTYPE register field value. */
135917 #define ALT_USB_DEV_DOEPCTL15_EPTYPE_CLR_MSK 0xfff3ffff
135918 /* The reset value of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */
135919 #define ALT_USB_DEV_DOEPCTL15_EPTYPE_RESET 0x0
135920 /* Extracts the ALT_USB_DEV_DOEPCTL15_EPTYPE field value from a register. */
135921 #define ALT_USB_DEV_DOEPCTL15_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
135922 /* Produces a ALT_USB_DEV_DOEPCTL15_EPTYPE register field value suitable for setting the register. */
135923 #define ALT_USB_DEV_DOEPCTL15_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
135924 
135925 /*
135926  * Field : snp
135927  *
135928  * Snoop Mode (Snp)
135929  *
135930  * Applies to OUT endpoints only.
135931  *
135932  * This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
135933  *
135934  * check the correctness of OUT packets before transferring them to application
135935  * memory.
135936  *
135937  * Field Enumeration Values:
135938  *
135939  * Enum | Value | Description
135940  * :--------------------------------|:------|:-------------------
135941  * ALT_USB_DEV_DOEPCTL15_SNP_E_DIS | 0x0 | Disable Snoop Mode
135942  * ALT_USB_DEV_DOEPCTL15_SNP_E_EN | 0x1 | Enable Snoop Mode
135943  *
135944  * Field Access Macros:
135945  *
135946  */
135947 /*
135948  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNP
135949  *
135950  * Disable Snoop Mode
135951  */
135952 #define ALT_USB_DEV_DOEPCTL15_SNP_E_DIS 0x0
135953 /*
135954  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNP
135955  *
135956  * Enable Snoop Mode
135957  */
135958 #define ALT_USB_DEV_DOEPCTL15_SNP_E_EN 0x1
135959 
135960 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SNP register field. */
135961 #define ALT_USB_DEV_DOEPCTL15_SNP_LSB 20
135962 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SNP register field. */
135963 #define ALT_USB_DEV_DOEPCTL15_SNP_MSB 20
135964 /* The width in bits of the ALT_USB_DEV_DOEPCTL15_SNP register field. */
135965 #define ALT_USB_DEV_DOEPCTL15_SNP_WIDTH 1
135966 /* The mask used to set the ALT_USB_DEV_DOEPCTL15_SNP register field value. */
135967 #define ALT_USB_DEV_DOEPCTL15_SNP_SET_MSK 0x00100000
135968 /* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SNP register field value. */
135969 #define ALT_USB_DEV_DOEPCTL15_SNP_CLR_MSK 0xffefffff
135970 /* The reset value of the ALT_USB_DEV_DOEPCTL15_SNP register field. */
135971 #define ALT_USB_DEV_DOEPCTL15_SNP_RESET 0x0
135972 /* Extracts the ALT_USB_DEV_DOEPCTL15_SNP field value from a register. */
135973 #define ALT_USB_DEV_DOEPCTL15_SNP_GET(value) (((value) & 0x00100000) >> 20)
135974 /* Produces a ALT_USB_DEV_DOEPCTL15_SNP register field value suitable for setting the register. */
135975 #define ALT_USB_DEV_DOEPCTL15_SNP_SET(value) (((value) << 20) & 0x00100000)
135976 
135977 /*
135978  * Field : stall
135979  *
135980  * STALL Handshake (Stall)
135981  *
135982  * Applies to non-control, non-isochronous IN and OUT endpoints only.
135983  *
135984  * The application sets this bit to stall all tokens from the USB host to this
135985  * endpoint. If a
135986  *
135987  * NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
135988  * bit, the
135989  *
135990  * STALL bit takes priority. Only the application can clear this bit, never the
135991  * core.
135992  *
135993  * 1'b0 R_W
135994  *
135995  * Applies to control endpoints only.
135996  *
135997  * The application can only set this bit, and the core clears it, when a SETUP
135998  * token is
135999  *
136000  * received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
136001  * OUT
136002  *
136003  * NAK is set along with this bit, the STALL bit takes priority. Irrespective of
136004  * this bit's
136005  *
136006  * setting, the core always responds to SETUP data packets with an ACK handshake.
136007  *
136008  * Field Enumeration Values:
136009  *
136010  * Enum | Value | Description
136011  * :------------------------------------|:------|:----------------------------
136012  * ALT_USB_DEV_DOEPCTL15_STALL_E_INACT | 0x0 | STALL All Tokens not active
136013  * ALT_USB_DEV_DOEPCTL15_STALL_E_ACT | 0x1 | STALL All Tokens active
136014  *
136015  * Field Access Macros:
136016  *
136017  */
136018 /*
136019  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_STALL
136020  *
136021  * STALL All Tokens not active
136022  */
136023 #define ALT_USB_DEV_DOEPCTL15_STALL_E_INACT 0x0
136024 /*
136025  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_STALL
136026  *
136027  * STALL All Tokens active
136028  */
136029 #define ALT_USB_DEV_DOEPCTL15_STALL_E_ACT 0x1
136030 
136031 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_STALL register field. */
136032 #define ALT_USB_DEV_DOEPCTL15_STALL_LSB 21
136033 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_STALL register field. */
136034 #define ALT_USB_DEV_DOEPCTL15_STALL_MSB 21
136035 /* The width in bits of the ALT_USB_DEV_DOEPCTL15_STALL register field. */
136036 #define ALT_USB_DEV_DOEPCTL15_STALL_WIDTH 1
136037 /* The mask used to set the ALT_USB_DEV_DOEPCTL15_STALL register field value. */
136038 #define ALT_USB_DEV_DOEPCTL15_STALL_SET_MSK 0x00200000
136039 /* The mask used to clear the ALT_USB_DEV_DOEPCTL15_STALL register field value. */
136040 #define ALT_USB_DEV_DOEPCTL15_STALL_CLR_MSK 0xffdfffff
136041 /* The reset value of the ALT_USB_DEV_DOEPCTL15_STALL register field. */
136042 #define ALT_USB_DEV_DOEPCTL15_STALL_RESET 0x0
136043 /* Extracts the ALT_USB_DEV_DOEPCTL15_STALL field value from a register. */
136044 #define ALT_USB_DEV_DOEPCTL15_STALL_GET(value) (((value) & 0x00200000) >> 21)
136045 /* Produces a ALT_USB_DEV_DOEPCTL15_STALL register field value suitable for setting the register. */
136046 #define ALT_USB_DEV_DOEPCTL15_STALL_SET(value) (((value) << 21) & 0x00200000)
136047 
136048 /*
136049  * Field : cnak
136050  *
136051  * Clear NAK (CNAK)
136052  *
136053  * A write to this bit clears the NAK bit For the endpoint.
136054  *
136055  * Field Enumeration Values:
136056  *
136057  * Enum | Value | Description
136058  * :-----------------------------------|:------|:-------------
136059  * ALT_USB_DEV_DOEPCTL15_CNAK_E_INACT | 0x0 | No Clear NAK
136060  * ALT_USB_DEV_DOEPCTL15_CNAK_E_ACT | 0x1 | Clear NAK
136061  *
136062  * Field Access Macros:
136063  *
136064  */
136065 /*
136066  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_CNAK
136067  *
136068  * No Clear NAK
136069  */
136070 #define ALT_USB_DEV_DOEPCTL15_CNAK_E_INACT 0x0
136071 /*
136072  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_CNAK
136073  *
136074  * Clear NAK
136075  */
136076 #define ALT_USB_DEV_DOEPCTL15_CNAK_E_ACT 0x1
136077 
136078 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */
136079 #define ALT_USB_DEV_DOEPCTL15_CNAK_LSB 26
136080 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */
136081 #define ALT_USB_DEV_DOEPCTL15_CNAK_MSB 26
136082 /* The width in bits of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */
136083 #define ALT_USB_DEV_DOEPCTL15_CNAK_WIDTH 1
136084 /* The mask used to set the ALT_USB_DEV_DOEPCTL15_CNAK register field value. */
136085 #define ALT_USB_DEV_DOEPCTL15_CNAK_SET_MSK 0x04000000
136086 /* The mask used to clear the ALT_USB_DEV_DOEPCTL15_CNAK register field value. */
136087 #define ALT_USB_DEV_DOEPCTL15_CNAK_CLR_MSK 0xfbffffff
136088 /* The reset value of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */
136089 #define ALT_USB_DEV_DOEPCTL15_CNAK_RESET 0x0
136090 /* Extracts the ALT_USB_DEV_DOEPCTL15_CNAK field value from a register. */
136091 #define ALT_USB_DEV_DOEPCTL15_CNAK_GET(value) (((value) & 0x04000000) >> 26)
136092 /* Produces a ALT_USB_DEV_DOEPCTL15_CNAK register field value suitable for setting the register. */
136093 #define ALT_USB_DEV_DOEPCTL15_CNAK_SET(value) (((value) << 26) & 0x04000000)
136094 
136095 /*
136096  * Field : snak
136097  *
136098  * Set NAK (SNAK)
136099  *
136100  * A write to this bit sets the NAK bit For the endpoint.
136101  *
136102  * Using this bit, the application can control the transmission of NAK
136103  *
136104  * handshakes on an endpoint. The core can also Set this bit For an
136105  *
136106  * endpoint after a SETUP packet is received on that endpoint.
136107  *
136108  * Field Enumeration Values:
136109  *
136110  * Enum | Value | Description
136111  * :-----------------------------------|:------|:------------
136112  * ALT_USB_DEV_DOEPCTL15_SNAK_E_INACT | 0x0 | No Set NAK
136113  * ALT_USB_DEV_DOEPCTL15_SNAK_E_ACT | 0x1 | Set NAK
136114  *
136115  * Field Access Macros:
136116  *
136117  */
136118 /*
136119  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNAK
136120  *
136121  * No Set NAK
136122  */
136123 #define ALT_USB_DEV_DOEPCTL15_SNAK_E_INACT 0x0
136124 /*
136125  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNAK
136126  *
136127  * Set NAK
136128  */
136129 #define ALT_USB_DEV_DOEPCTL15_SNAK_E_ACT 0x1
136130 
136131 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */
136132 #define ALT_USB_DEV_DOEPCTL15_SNAK_LSB 27
136133 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */
136134 #define ALT_USB_DEV_DOEPCTL15_SNAK_MSB 27
136135 /* The width in bits of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */
136136 #define ALT_USB_DEV_DOEPCTL15_SNAK_WIDTH 1
136137 /* The mask used to set the ALT_USB_DEV_DOEPCTL15_SNAK register field value. */
136138 #define ALT_USB_DEV_DOEPCTL15_SNAK_SET_MSK 0x08000000
136139 /* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SNAK register field value. */
136140 #define ALT_USB_DEV_DOEPCTL15_SNAK_CLR_MSK 0xf7ffffff
136141 /* The reset value of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */
136142 #define ALT_USB_DEV_DOEPCTL15_SNAK_RESET 0x0
136143 /* Extracts the ALT_USB_DEV_DOEPCTL15_SNAK field value from a register. */
136144 #define ALT_USB_DEV_DOEPCTL15_SNAK_GET(value) (((value) & 0x08000000) >> 27)
136145 /* Produces a ALT_USB_DEV_DOEPCTL15_SNAK register field value suitable for setting the register. */
136146 #define ALT_USB_DEV_DOEPCTL15_SNAK_SET(value) (((value) << 27) & 0x08000000)
136147 
136148 /*
136149  * Field : setd0pid
136150  *
136151  * Set DATA0 PID (SetD0PID)
136152  *
136153  * Applies to interrupt/bulk IN and OUT endpoints only.
136154  *
136155  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
136156  * to DATA0.
136157  *
136158  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
136159  *
136160  * DMA mode.
136161  *
136162  * 1'b0 WO
136163  *
136164  * In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
136165  *
136166  * Applies to isochronous IN and OUT endpoints only.
136167  *
136168  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
136169  * (micro)
136170  *
136171  * frame.
136172  *
136173  * When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
136174  * number
136175  *
136176  * in which to send data is in the transmit descriptor structure. The frame in
136177  * which to
136178  *
136179  * receive data is updated in receive descriptor structure.
136180  *
136181  * Field Enumeration Values:
136182  *
136183  * Enum | Value | Description
136184  * :--------------------------------------|:------|:------------------------------------
136185  * ALT_USB_DEV_DOEPCTL15_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
136186  * ALT_USB_DEV_DOEPCTL15_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
136187  *
136188  * Field Access Macros:
136189  *
136190  */
136191 /*
136192  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD0PID
136193  *
136194  * Disables Set DATA0 PID
136195  */
136196 #define ALT_USB_DEV_DOEPCTL15_SETD0PID_E_DISD 0x0
136197 /*
136198  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD0PID
136199  *
136200  * Enables Endpoint Data PID to DATA0)
136201  */
136202 #define ALT_USB_DEV_DOEPCTL15_SETD0PID_E_END 0x1
136203 
136204 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */
136205 #define ALT_USB_DEV_DOEPCTL15_SETD0PID_LSB 28
136206 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */
136207 #define ALT_USB_DEV_DOEPCTL15_SETD0PID_MSB 28
136208 /* The width in bits of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */
136209 #define ALT_USB_DEV_DOEPCTL15_SETD0PID_WIDTH 1
136210 /* The mask used to set the ALT_USB_DEV_DOEPCTL15_SETD0PID register field value. */
136211 #define ALT_USB_DEV_DOEPCTL15_SETD0PID_SET_MSK 0x10000000
136212 /* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SETD0PID register field value. */
136213 #define ALT_USB_DEV_DOEPCTL15_SETD0PID_CLR_MSK 0xefffffff
136214 /* The reset value of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */
136215 #define ALT_USB_DEV_DOEPCTL15_SETD0PID_RESET 0x0
136216 /* Extracts the ALT_USB_DEV_DOEPCTL15_SETD0PID field value from a register. */
136217 #define ALT_USB_DEV_DOEPCTL15_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
136218 /* Produces a ALT_USB_DEV_DOEPCTL15_SETD0PID register field value suitable for setting the register. */
136219 #define ALT_USB_DEV_DOEPCTL15_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
136220 
136221 /*
136222  * Field : setd1pid
136223  *
136224  * Set DATA1 PID (SetD1PID)
136225  *
136226  * Applies to interrupt/bulk IN and OUT endpoints only.
136227  *
136228  * Writing to this field sets the Endpoint Data PID (DPID) field in this register
136229  * to DATA1.
136230  *
136231  * This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
136232  *
136233  * DMA mode.
136234  *
136235  * Set Odd (micro)frame (SetOddFr)
136236  *
136237  * Applies to isochronous IN and OUT endpoints only.
136238  *
136239  * Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
136240  *
136241  * (micro)frame.
136242  *
136243  * This field is not applicable for Scatter/Gather DMA mode.
136244  *
136245  * Field Enumeration Values:
136246  *
136247  * Enum | Value | Description
136248  * :--------------------------------------|:------|:-----------------------
136249  * ALT_USB_DEV_DOEPCTL15_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
136250  * ALT_USB_DEV_DOEPCTL15_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
136251  *
136252  * Field Access Macros:
136253  *
136254  */
136255 /*
136256  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD1PID
136257  *
136258  * Disables Set DATA1 PID
136259  */
136260 #define ALT_USB_DEV_DOEPCTL15_SETD1PID_E_DISD 0x0
136261 /*
136262  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD1PID
136263  *
136264  * Enables Set DATA1 PID
136265  */
136266 #define ALT_USB_DEV_DOEPCTL15_SETD1PID_E_END 0x1
136267 
136268 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */
136269 #define ALT_USB_DEV_DOEPCTL15_SETD1PID_LSB 29
136270 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */
136271 #define ALT_USB_DEV_DOEPCTL15_SETD1PID_MSB 29
136272 /* The width in bits of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */
136273 #define ALT_USB_DEV_DOEPCTL15_SETD1PID_WIDTH 1
136274 /* The mask used to set the ALT_USB_DEV_DOEPCTL15_SETD1PID register field value. */
136275 #define ALT_USB_DEV_DOEPCTL15_SETD1PID_SET_MSK 0x20000000
136276 /* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SETD1PID register field value. */
136277 #define ALT_USB_DEV_DOEPCTL15_SETD1PID_CLR_MSK 0xdfffffff
136278 /* The reset value of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */
136279 #define ALT_USB_DEV_DOEPCTL15_SETD1PID_RESET 0x0
136280 /* Extracts the ALT_USB_DEV_DOEPCTL15_SETD1PID field value from a register. */
136281 #define ALT_USB_DEV_DOEPCTL15_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
136282 /* Produces a ALT_USB_DEV_DOEPCTL15_SETD1PID register field value suitable for setting the register. */
136283 #define ALT_USB_DEV_DOEPCTL15_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
136284 
136285 /*
136286  * Field : epdis
136287  *
136288  * Endpoint Disable (EPDis)
136289  *
136290  * Applies to IN and OUT endpoints.
136291  *
136292  * The application sets this bit to stop transmitting/receiving data on an
136293  * endpoint, even
136294  *
136295  * before the transfer for that endpoint is complete. The application must wait for
136296  * the
136297  *
136298  * Endpoint Disabled interrupt before treating the endpoint as disabled. The core
136299  * clears
136300  *
136301  * this bit before setting the Endpoint Disabled interrupt. The application must
136302  * set this bit
136303  *
136304  * only if Endpoint Enable is already set for this endpoint.
136305  *
136306  * Field Enumeration Values:
136307  *
136308  * Enum | Value | Description
136309  * :------------------------------------|:------|:--------------------
136310  * ALT_USB_DEV_DOEPCTL15_EPDIS_E_INACT | 0x0 | No Endpoint Disable
136311  * ALT_USB_DEV_DOEPCTL15_EPDIS_E_ACT | 0x1 | Endpoint Disable
136312  *
136313  * Field Access Macros:
136314  *
136315  */
136316 /*
136317  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPDIS
136318  *
136319  * No Endpoint Disable
136320  */
136321 #define ALT_USB_DEV_DOEPCTL15_EPDIS_E_INACT 0x0
136322 /*
136323  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPDIS
136324  *
136325  * Endpoint Disable
136326  */
136327 #define ALT_USB_DEV_DOEPCTL15_EPDIS_E_ACT 0x1
136328 
136329 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */
136330 #define ALT_USB_DEV_DOEPCTL15_EPDIS_LSB 30
136331 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */
136332 #define ALT_USB_DEV_DOEPCTL15_EPDIS_MSB 30
136333 /* The width in bits of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */
136334 #define ALT_USB_DEV_DOEPCTL15_EPDIS_WIDTH 1
136335 /* The mask used to set the ALT_USB_DEV_DOEPCTL15_EPDIS register field value. */
136336 #define ALT_USB_DEV_DOEPCTL15_EPDIS_SET_MSK 0x40000000
136337 /* The mask used to clear the ALT_USB_DEV_DOEPCTL15_EPDIS register field value. */
136338 #define ALT_USB_DEV_DOEPCTL15_EPDIS_CLR_MSK 0xbfffffff
136339 /* The reset value of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */
136340 #define ALT_USB_DEV_DOEPCTL15_EPDIS_RESET 0x0
136341 /* Extracts the ALT_USB_DEV_DOEPCTL15_EPDIS field value from a register. */
136342 #define ALT_USB_DEV_DOEPCTL15_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
136343 /* Produces a ALT_USB_DEV_DOEPCTL15_EPDIS register field value suitable for setting the register. */
136344 #define ALT_USB_DEV_DOEPCTL15_EPDIS_SET(value) (((value) << 30) & 0x40000000)
136345 
136346 /*
136347  * Field : epena
136348  *
136349  * Endpoint Enable (EPEna)
136350  *
136351  * Applies to IN and OUT endpoints.
136352  *
136353  * When Scatter/Gather DMA mode is enabled,
136354  *
136355  * For IN endpoints this bit indicates that the descriptor structure and data
136356  * buffer with
136357  *
136358  * data ready to transmit is setup.
136359  *
136360  * For OUT endpoint it indicates that the descriptor structure and data buffer to
136361  *
136362  * receive data is setup.
136363  *
136364  * When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
136365  *
136366  * DMA mode:
136367  *
136368  * * For IN endpoints, this bit indicates that data is ready to be transmitted on
136369  * the
136370  *
136371  * endpoint.
136372  *
136373  * * For OUT endpoints, this bit indicates that the application has allocated the
136374  *
136375  * memory to start receiving data from the USB.
136376  *
136377  * * The core clears this bit before setting any of the following interrupts on
136378  * this
136379  *
136380  * endpoint:
136381  *
136382  * SETUP Phase Done
136383  *
136384  * Endpoint Disabled
136385  *
136386  * Transfer Completed
136387  *
136388  * Note: For control endpoints in DMA mode, this bit must be set to be able to
136389  * transfer
136390  *
136391  * SETUP data packets in memory.
136392  *
136393  * Field Enumeration Values:
136394  *
136395  * Enum | Value | Description
136396  * :------------------------------------|:------|:-------------------------
136397  * ALT_USB_DEV_DOEPCTL15_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
136398  * ALT_USB_DEV_DOEPCTL15_EPENA_E_ACT | 0x1 | Endpoint Enable active
136399  *
136400  * Field Access Macros:
136401  *
136402  */
136403 /*
136404  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPENA
136405  *
136406  * Endpoint Enable inactive
136407  */
136408 #define ALT_USB_DEV_DOEPCTL15_EPENA_E_INACT 0x0
136409 /*
136410  * Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPENA
136411  *
136412  * Endpoint Enable active
136413  */
136414 #define ALT_USB_DEV_DOEPCTL15_EPENA_E_ACT 0x1
136415 
136416 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */
136417 #define ALT_USB_DEV_DOEPCTL15_EPENA_LSB 31
136418 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */
136419 #define ALT_USB_DEV_DOEPCTL15_EPENA_MSB 31
136420 /* The width in bits of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */
136421 #define ALT_USB_DEV_DOEPCTL15_EPENA_WIDTH 1
136422 /* The mask used to set the ALT_USB_DEV_DOEPCTL15_EPENA register field value. */
136423 #define ALT_USB_DEV_DOEPCTL15_EPENA_SET_MSK 0x80000000
136424 /* The mask used to clear the ALT_USB_DEV_DOEPCTL15_EPENA register field value. */
136425 #define ALT_USB_DEV_DOEPCTL15_EPENA_CLR_MSK 0x7fffffff
136426 /* The reset value of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */
136427 #define ALT_USB_DEV_DOEPCTL15_EPENA_RESET 0x0
136428 /* Extracts the ALT_USB_DEV_DOEPCTL15_EPENA field value from a register. */
136429 #define ALT_USB_DEV_DOEPCTL15_EPENA_GET(value) (((value) & 0x80000000) >> 31)
136430 /* Produces a ALT_USB_DEV_DOEPCTL15_EPENA register field value suitable for setting the register. */
136431 #define ALT_USB_DEV_DOEPCTL15_EPENA_SET(value) (((value) << 31) & 0x80000000)
136432 
136433 #ifndef __ASSEMBLY__
136434 /*
136435  * WARNING: The C register and register group struct declarations are provided for
136436  * convenience and illustrative purposes. They should, however, be used with
136437  * caution as the C language standard provides no guarantees about the alignment or
136438  * atomicity of device memory accesses. The recommended practice for writing
136439  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
136440  * alt_write_word() functions.
136441  *
136442  * The struct declaration for register ALT_USB_DEV_DOEPCTL15.
136443  */
136444 struct ALT_USB_DEV_DOEPCTL15_s
136445 {
136446  uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL15_MPS */
136447  uint32_t : 4; /* *UNDEFINED* */
136448  uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL15_USBACTEP */
136449  const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL15_DPID */
136450  const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL15_NAKSTS */
136451  uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL15_EPTYPE */
136452  uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL15_SNP */
136453  uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL15_STALL */
136454  uint32_t : 4; /* *UNDEFINED* */
136455  uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL15_CNAK */
136456  uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL15_SNAK */
136457  uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL15_SETD0PID */
136458  uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL15_SETD1PID */
136459  uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL15_EPDIS */
136460  uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL15_EPENA */
136461 };
136462 
136463 /* The typedef declaration for register ALT_USB_DEV_DOEPCTL15. */
136464 typedef volatile struct ALT_USB_DEV_DOEPCTL15_s ALT_USB_DEV_DOEPCTL15_t;
136465 #endif /* __ASSEMBLY__ */
136466 
136467 /* The reset value of the ALT_USB_DEV_DOEPCTL15 register. */
136468 #define ALT_USB_DEV_DOEPCTL15_RESET 0x00000000
136469 /* The byte offset of the ALT_USB_DEV_DOEPCTL15 register from the beginning of the component. */
136470 #define ALT_USB_DEV_DOEPCTL15_OFST 0x4e0
136471 /* The address of the ALT_USB_DEV_DOEPCTL15 register. */
136472 #define ALT_USB_DEV_DOEPCTL15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL15_OFST))
136473 
136474 /*
136475  * Register : doepint15
136476  *
136477  * Device OUT Endpoint 15 Interrupt Register
136478  *
136479  * Register Layout
136480  *
136481  * Bits | Access | Reset | Description
136482  * :--------|:-------|:------|:-------------------------------------
136483  * [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_XFERCOMPL
136484  * [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_EPDISBLD
136485  * [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_AHBERR
136486  * [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_SETUP
136487  * [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS
136488  * [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_STSPHSERCVD
136489  * [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP
136490  * [7] | ??? | 0x0 | *UNDEFINED*
136491  * [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_OUTPKTERR
136492  * [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_BNAINTR
136493  * [10] | ??? | 0x0 | *UNDEFINED*
136494  * [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_PKTDRPSTS
136495  * [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_BBLEERR
136496  * [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_NAKINTRPT
136497  * [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_NYETINTRPT
136498  * [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_STUPPKTRCVD
136499  * [31:16] | ??? | 0x0 | *UNDEFINED*
136500  *
136501  */
136502 /*
136503  * Field : xfercompl
136504  *
136505  * Transfer Completed Interrupt (XferCompl)
136506  *
136507  * Applies to IN and OUT endpoints.
136508  *
136509  * When Scatter/Gather DMA mode is enabled
136510  *
136511  * * For IN endpoint this field indicates that the requested data
136512  *
136513  * from the descriptor is moved from external system memory
136514  *
136515  * to internal FIFO.
136516  *
136517  * * For OUT endpoint this field indicates that the requested
136518  *
136519  * data from the internal FIFO is moved to external system
136520  *
136521  * memory. This interrupt is generated only when the
136522  *
136523  * corresponding endpoint descriptor is closed, and the IOC
136524  *
136525  * bit For the corresponding descriptor is Set.
136526  *
136527  * When Scatter/Gather DMA mode is disabled, this field
136528  *
136529  * indicates that the programmed transfer is complete on the
136530  *
136531  * AHB as well as on the USB, For this endpoint.
136532  *
136533  * Field Enumeration Values:
136534  *
136535  * Enum | Value | Description
136536  * :----------------------------------------|:------|:-----------------------------
136537  * ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_INACT | 0x0 | No Interrupt
136538  * ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
136539  *
136540  * Field Access Macros:
136541  *
136542  */
136543 /*
136544  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_XFERCOMPL
136545  *
136546  * No Interrupt
136547  */
136548 #define ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_INACT 0x0
136549 /*
136550  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_XFERCOMPL
136551  *
136552  * Transfer Completed Interrupt
136553  */
136554 #define ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_ACT 0x1
136555 
136556 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */
136557 #define ALT_USB_DEV_DOEPINT15_XFERCOMPL_LSB 0
136558 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */
136559 #define ALT_USB_DEV_DOEPINT15_XFERCOMPL_MSB 0
136560 /* The width in bits of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */
136561 #define ALT_USB_DEV_DOEPINT15_XFERCOMPL_WIDTH 1
136562 /* The mask used to set the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field value. */
136563 #define ALT_USB_DEV_DOEPINT15_XFERCOMPL_SET_MSK 0x00000001
136564 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field value. */
136565 #define ALT_USB_DEV_DOEPINT15_XFERCOMPL_CLR_MSK 0xfffffffe
136566 /* The reset value of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */
136567 #define ALT_USB_DEV_DOEPINT15_XFERCOMPL_RESET 0x0
136568 /* Extracts the ALT_USB_DEV_DOEPINT15_XFERCOMPL field value from a register. */
136569 #define ALT_USB_DEV_DOEPINT15_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
136570 /* Produces a ALT_USB_DEV_DOEPINT15_XFERCOMPL register field value suitable for setting the register. */
136571 #define ALT_USB_DEV_DOEPINT15_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
136572 
136573 /*
136574  * Field : epdisbld
136575  *
136576  * Endpoint Disabled Interrupt (EPDisbld)
136577  *
136578  * Applies to IN and OUT endpoints.
136579  *
136580  * This bit indicates that the endpoint is disabled per the
136581  *
136582  * application's request.
136583  *
136584  * Field Enumeration Values:
136585  *
136586  * Enum | Value | Description
136587  * :---------------------------------------|:------|:----------------------------
136588  * ALT_USB_DEV_DOEPINT15_EPDISBLD_E_INACT | 0x0 | No Interrupt
136589  * ALT_USB_DEV_DOEPINT15_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
136590  *
136591  * Field Access Macros:
136592  *
136593  */
136594 /*
136595  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_EPDISBLD
136596  *
136597  * No Interrupt
136598  */
136599 #define ALT_USB_DEV_DOEPINT15_EPDISBLD_E_INACT 0x0
136600 /*
136601  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_EPDISBLD
136602  *
136603  * Endpoint Disabled Interrupt
136604  */
136605 #define ALT_USB_DEV_DOEPINT15_EPDISBLD_E_ACT 0x1
136606 
136607 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */
136608 #define ALT_USB_DEV_DOEPINT15_EPDISBLD_LSB 1
136609 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */
136610 #define ALT_USB_DEV_DOEPINT15_EPDISBLD_MSB 1
136611 /* The width in bits of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */
136612 #define ALT_USB_DEV_DOEPINT15_EPDISBLD_WIDTH 1
136613 /* The mask used to set the ALT_USB_DEV_DOEPINT15_EPDISBLD register field value. */
136614 #define ALT_USB_DEV_DOEPINT15_EPDISBLD_SET_MSK 0x00000002
136615 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_EPDISBLD register field value. */
136616 #define ALT_USB_DEV_DOEPINT15_EPDISBLD_CLR_MSK 0xfffffffd
136617 /* The reset value of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */
136618 #define ALT_USB_DEV_DOEPINT15_EPDISBLD_RESET 0x0
136619 /* Extracts the ALT_USB_DEV_DOEPINT15_EPDISBLD field value from a register. */
136620 #define ALT_USB_DEV_DOEPINT15_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
136621 /* Produces a ALT_USB_DEV_DOEPINT15_EPDISBLD register field value suitable for setting the register. */
136622 #define ALT_USB_DEV_DOEPINT15_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
136623 
136624 /*
136625  * Field : ahberr
136626  *
136627  * AHB Error (AHBErr)
136628  *
136629  * Applies to IN and OUT endpoints.
136630  *
136631  * This is generated only in Internal DMA mode when there is an
136632  *
136633  * AHB error during an AHB read/write. The application can read
136634  *
136635  * the corresponding endpoint DMA address register to get the
136636  *
136637  * error address.
136638  *
136639  * Field Enumeration Values:
136640  *
136641  * Enum | Value | Description
136642  * :-------------------------------------|:------|:--------------------
136643  * ALT_USB_DEV_DOEPINT15_AHBERR_E_INACT | 0x0 | No Interrupt
136644  * ALT_USB_DEV_DOEPINT15_AHBERR_E_ACT | 0x1 | AHB Error interrupt
136645  *
136646  * Field Access Macros:
136647  *
136648  */
136649 /*
136650  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_AHBERR
136651  *
136652  * No Interrupt
136653  */
136654 #define ALT_USB_DEV_DOEPINT15_AHBERR_E_INACT 0x0
136655 /*
136656  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_AHBERR
136657  *
136658  * AHB Error interrupt
136659  */
136660 #define ALT_USB_DEV_DOEPINT15_AHBERR_E_ACT 0x1
136661 
136662 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */
136663 #define ALT_USB_DEV_DOEPINT15_AHBERR_LSB 2
136664 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */
136665 #define ALT_USB_DEV_DOEPINT15_AHBERR_MSB 2
136666 /* The width in bits of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */
136667 #define ALT_USB_DEV_DOEPINT15_AHBERR_WIDTH 1
136668 /* The mask used to set the ALT_USB_DEV_DOEPINT15_AHBERR register field value. */
136669 #define ALT_USB_DEV_DOEPINT15_AHBERR_SET_MSK 0x00000004
136670 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_AHBERR register field value. */
136671 #define ALT_USB_DEV_DOEPINT15_AHBERR_CLR_MSK 0xfffffffb
136672 /* The reset value of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */
136673 #define ALT_USB_DEV_DOEPINT15_AHBERR_RESET 0x0
136674 /* Extracts the ALT_USB_DEV_DOEPINT15_AHBERR field value from a register. */
136675 #define ALT_USB_DEV_DOEPINT15_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
136676 /* Produces a ALT_USB_DEV_DOEPINT15_AHBERR register field value suitable for setting the register. */
136677 #define ALT_USB_DEV_DOEPINT15_AHBERR_SET(value) (((value) << 2) & 0x00000004)
136678 
136679 /*
136680  * Field : setup
136681  *
136682  * SETUP Phase Done (SetUp)
136683  *
136684  * Applies to control OUT endpoints only.
136685  *
136686  * Indicates that the SETUP phase For the control endpoint is
136687  *
136688  * complete and no more back-to-back SETUP packets were
136689  *
136690  * received For the current control transfer. On this interrupt, the
136691  *
136692  * application can decode the received SETUP data packet.
136693  *
136694  * Field Enumeration Values:
136695  *
136696  * Enum | Value | Description
136697  * :------------------------------------|:------|:--------------------
136698  * ALT_USB_DEV_DOEPINT15_SETUP_E_INACT | 0x0 | No SETUP Phase Done
136699  * ALT_USB_DEV_DOEPINT15_SETUP_E_ACT | 0x1 | SETUP Phase Done
136700  *
136701  * Field Access Macros:
136702  *
136703  */
136704 /*
136705  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_SETUP
136706  *
136707  * No SETUP Phase Done
136708  */
136709 #define ALT_USB_DEV_DOEPINT15_SETUP_E_INACT 0x0
136710 /*
136711  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_SETUP
136712  *
136713  * SETUP Phase Done
136714  */
136715 #define ALT_USB_DEV_DOEPINT15_SETUP_E_ACT 0x1
136716 
136717 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_SETUP register field. */
136718 #define ALT_USB_DEV_DOEPINT15_SETUP_LSB 3
136719 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_SETUP register field. */
136720 #define ALT_USB_DEV_DOEPINT15_SETUP_MSB 3
136721 /* The width in bits of the ALT_USB_DEV_DOEPINT15_SETUP register field. */
136722 #define ALT_USB_DEV_DOEPINT15_SETUP_WIDTH 1
136723 /* The mask used to set the ALT_USB_DEV_DOEPINT15_SETUP register field value. */
136724 #define ALT_USB_DEV_DOEPINT15_SETUP_SET_MSK 0x00000008
136725 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_SETUP register field value. */
136726 #define ALT_USB_DEV_DOEPINT15_SETUP_CLR_MSK 0xfffffff7
136727 /* The reset value of the ALT_USB_DEV_DOEPINT15_SETUP register field. */
136728 #define ALT_USB_DEV_DOEPINT15_SETUP_RESET 0x0
136729 /* Extracts the ALT_USB_DEV_DOEPINT15_SETUP field value from a register. */
136730 #define ALT_USB_DEV_DOEPINT15_SETUP_GET(value) (((value) & 0x00000008) >> 3)
136731 /* Produces a ALT_USB_DEV_DOEPINT15_SETUP register field value suitable for setting the register. */
136732 #define ALT_USB_DEV_DOEPINT15_SETUP_SET(value) (((value) << 3) & 0x00000008)
136733 
136734 /*
136735  * Field : outtknepdis
136736  *
136737  * OUT Token Received When Endpoint Disabled (OUTTknEPdis)
136738  *
136739  * Applies only to control OUT endpoints.
136740  *
136741  * Indicates that an OUT token was received when the endpoint
136742  *
136743  * was not yet enabled. This interrupt is asserted on the endpoint
136744  *
136745  * For which the OUT token was received.
136746  *
136747  * Field Enumeration Values:
136748  *
136749  * Enum | Value | Description
136750  * :------------------------------------------|:------|:---------------------------------------------
136751  * ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
136752  * ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
136753  *
136754  * Field Access Macros:
136755  *
136756  */
136757 /*
136758  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS
136759  *
136760  * No OUT Token Received When Endpoint Disabled
136761  */
136762 #define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_INACT 0x0
136763 /*
136764  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS
136765  *
136766  * OUT Token Received When Endpoint Disabled
136767  */
136768 #define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_ACT 0x1
136769 
136770 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */
136771 #define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_LSB 4
136772 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */
136773 #define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_MSB 4
136774 /* The width in bits of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */
136775 #define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_WIDTH 1
136776 /* The mask used to set the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field value. */
136777 #define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_SET_MSK 0x00000010
136778 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field value. */
136779 #define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_CLR_MSK 0xffffffef
136780 /* The reset value of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */
136781 #define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_RESET 0x0
136782 /* Extracts the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS field value from a register. */
136783 #define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
136784 /* Produces a ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field value suitable for setting the register. */
136785 #define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
136786 
136787 /*
136788  * Field : stsphsercvd
136789  *
136790  * Status Phase Received For Control Write (StsPhseRcvd)
136791  *
136792  * This interrupt is valid only For Control OUT endpoints and only in
136793  *
136794  * Scatter Gather DMA mode.
136795  *
136796  * This interrupt is generated only after the core has transferred all
136797  *
136798  * the data that the host has sent during the data phase of a control
136799  *
136800  * write transfer, to the system memory buffer.
136801  *
136802  * The interrupt indicates to the application that the host has
136803  *
136804  * switched from data phase to the status phase of a Control Write
136805  *
136806  * transfer. The application can use this interrupt to ACK or STALL
136807  *
136808  * the Status phase, after it has decoded the data phase. This is
136809  *
136810  * applicable only in Case of Scatter Gather DMA mode.
136811  *
136812  * Field Enumeration Values:
136813  *
136814  * Enum | Value | Description
136815  * :------------------------------------------|:------|:-------------------------------------------
136816  * ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
136817  * ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
136818  *
136819  * Field Access Macros:
136820  *
136821  */
136822 /*
136823  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_STSPHSERCVD
136824  *
136825  * No Status Phase Received for Control Write
136826  */
136827 #define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_INACT 0x0
136828 /*
136829  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_STSPHSERCVD
136830  *
136831  * Status Phase Received for Control Write
136832  */
136833 #define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_ACT 0x1
136834 
136835 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */
136836 #define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_LSB 5
136837 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */
136838 #define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_MSB 5
136839 /* The width in bits of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */
136840 #define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_WIDTH 1
136841 /* The mask used to set the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field value. */
136842 #define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_SET_MSK 0x00000020
136843 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field value. */
136844 #define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_CLR_MSK 0xffffffdf
136845 /* The reset value of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */
136846 #define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_RESET 0x0
136847 /* Extracts the ALT_USB_DEV_DOEPINT15_STSPHSERCVD field value from a register. */
136848 #define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
136849 /* Produces a ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field value suitable for setting the register. */
136850 #define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
136851 
136852 /*
136853  * Field : back2backsetup
136854  *
136855  * Back-to-Back SETUP Packets Received (Back2BackSETup)
136856  *
136857  * Applies to Control OUT endpoints only.
136858  *
136859  * This bit indicates that the core has received more than three
136860  *
136861  * back-to-back SETUP packets For this particular endpoint. For
136862  *
136863  * information about handling this interrupt,
136864  *
136865  * Field Enumeration Values:
136866  *
136867  * Enum | Value | Description
136868  * :---------------------------------------------|:------|:---------------------------------------
136869  * ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
136870  * ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
136871  *
136872  * Field Access Macros:
136873  *
136874  */
136875 /*
136876  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP
136877  *
136878  * No Back-to-Back SETUP Packets Received
136879  */
136880 #define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_INACT 0x0
136881 /*
136882  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP
136883  *
136884  * Back-to-Back SETUP Packets Received
136885  */
136886 #define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_ACT 0x1
136887 
136888 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */
136889 #define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_LSB 6
136890 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */
136891 #define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_MSB 6
136892 /* The width in bits of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */
136893 #define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_WIDTH 1
136894 /* The mask used to set the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field value. */
136895 #define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_SET_MSK 0x00000040
136896 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field value. */
136897 #define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_CLR_MSK 0xffffffbf
136898 /* The reset value of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */
136899 #define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_RESET 0x0
136900 /* Extracts the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP field value from a register. */
136901 #define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
136902 /* Produces a ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field value suitable for setting the register. */
136903 #define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
136904 
136905 /*
136906  * Field : outpkterr
136907  *
136908  * OUT Packet Error (OutPktErr)
136909  *
136910  * Applies to OUT endpoints Only
136911  *
136912  * This interrupt is valid only when thresholding is enabled. This interrupt is
136913  * asserted when the
136914  *
136915  * core detects an overflow or a CRC error For non-Isochronous
136916  *
136917  * OUT packet.
136918  *
136919  * Field Enumeration Values:
136920  *
136921  * Enum | Value | Description
136922  * :----------------------------------------|:------|:--------------------
136923  * ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
136924  * ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
136925  *
136926  * Field Access Macros:
136927  *
136928  */
136929 /*
136930  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTPKTERR
136931  *
136932  * No OUT Packet Error
136933  */
136934 #define ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_INACT 0x0
136935 /*
136936  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTPKTERR
136937  *
136938  * OUT Packet Error
136939  */
136940 #define ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_ACT 0x1
136941 
136942 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */
136943 #define ALT_USB_DEV_DOEPINT15_OUTPKTERR_LSB 8
136944 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */
136945 #define ALT_USB_DEV_DOEPINT15_OUTPKTERR_MSB 8
136946 /* The width in bits of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */
136947 #define ALT_USB_DEV_DOEPINT15_OUTPKTERR_WIDTH 1
136948 /* The mask used to set the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field value. */
136949 #define ALT_USB_DEV_DOEPINT15_OUTPKTERR_SET_MSK 0x00000100
136950 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field value. */
136951 #define ALT_USB_DEV_DOEPINT15_OUTPKTERR_CLR_MSK 0xfffffeff
136952 /* The reset value of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */
136953 #define ALT_USB_DEV_DOEPINT15_OUTPKTERR_RESET 0x0
136954 /* Extracts the ALT_USB_DEV_DOEPINT15_OUTPKTERR field value from a register. */
136955 #define ALT_USB_DEV_DOEPINT15_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
136956 /* Produces a ALT_USB_DEV_DOEPINT15_OUTPKTERR register field value suitable for setting the register. */
136957 #define ALT_USB_DEV_DOEPINT15_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
136958 
136959 /*
136960  * Field : bnaintr
136961  *
136962  * BNA (Buffer Not Available) Interrupt (BNAIntr)
136963  *
136964  * This bit is valid only when Scatter/Gather DMA mode is enabled.
136965  *
136966  * The core generates this interrupt when the descriptor accessed
136967  *
136968  * is not ready For the Core to process, such as Host busy or DMA
136969  *
136970  * done
136971  *
136972  * Field Enumeration Values:
136973  *
136974  * Enum | Value | Description
136975  * :--------------------------------------|:------|:--------------
136976  * ALT_USB_DEV_DOEPINT15_BNAINTR_E_INACT | 0x0 | No interrupt
136977  * ALT_USB_DEV_DOEPINT15_BNAINTR_E_ACT | 0x1 | BNA interrupt
136978  *
136979  * Field Access Macros:
136980  *
136981  */
136982 /*
136983  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BNAINTR
136984  *
136985  * No interrupt
136986  */
136987 #define ALT_USB_DEV_DOEPINT15_BNAINTR_E_INACT 0x0
136988 /*
136989  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BNAINTR
136990  *
136991  * BNA interrupt
136992  */
136993 #define ALT_USB_DEV_DOEPINT15_BNAINTR_E_ACT 0x1
136994 
136995 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */
136996 #define ALT_USB_DEV_DOEPINT15_BNAINTR_LSB 9
136997 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */
136998 #define ALT_USB_DEV_DOEPINT15_BNAINTR_MSB 9
136999 /* The width in bits of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */
137000 #define ALT_USB_DEV_DOEPINT15_BNAINTR_WIDTH 1
137001 /* The mask used to set the ALT_USB_DEV_DOEPINT15_BNAINTR register field value. */
137002 #define ALT_USB_DEV_DOEPINT15_BNAINTR_SET_MSK 0x00000200
137003 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_BNAINTR register field value. */
137004 #define ALT_USB_DEV_DOEPINT15_BNAINTR_CLR_MSK 0xfffffdff
137005 /* The reset value of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */
137006 #define ALT_USB_DEV_DOEPINT15_BNAINTR_RESET 0x0
137007 /* Extracts the ALT_USB_DEV_DOEPINT15_BNAINTR field value from a register. */
137008 #define ALT_USB_DEV_DOEPINT15_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
137009 /* Produces a ALT_USB_DEV_DOEPINT15_BNAINTR register field value suitable for setting the register. */
137010 #define ALT_USB_DEV_DOEPINT15_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
137011 
137012 /*
137013  * Field : pktdrpsts
137014  *
137015  * Packet Drop Status (PktDrpSts)
137016  *
137017  * This bit indicates to the application that an ISOC OUT packet has been dropped.
137018  * This
137019  *
137020  * bit does not have an associated mask bit and does not generate an interrupt.
137021  *
137022  * Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
137023  * transfer
137024  *
137025  * interrupt feature is selected.
137026  *
137027  * Field Enumeration Values:
137028  *
137029  * Enum | Value | Description
137030  * :----------------------------------------|:------|:-----------------------------
137031  * ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_INACT | 0x0 | No interrupt
137032  * ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
137033  *
137034  * Field Access Macros:
137035  *
137036  */
137037 /*
137038  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_PKTDRPSTS
137039  *
137040  * No interrupt
137041  */
137042 #define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_INACT 0x0
137043 /*
137044  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_PKTDRPSTS
137045  *
137046  * Packet Drop Status interrupt
137047  */
137048 #define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_ACT 0x1
137049 
137050 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */
137051 #define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_LSB 11
137052 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */
137053 #define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_MSB 11
137054 /* The width in bits of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */
137055 #define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_WIDTH 1
137056 /* The mask used to set the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field value. */
137057 #define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_SET_MSK 0x00000800
137058 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field value. */
137059 #define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_CLR_MSK 0xfffff7ff
137060 /* The reset value of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */
137061 #define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_RESET 0x0
137062 /* Extracts the ALT_USB_DEV_DOEPINT15_PKTDRPSTS field value from a register. */
137063 #define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
137064 /* Produces a ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field value suitable for setting the register. */
137065 #define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
137066 
137067 /*
137068  * Field : bbleerr
137069  *
137070  * NAK Interrupt (BbleErr)
137071  *
137072  * The core generates this interrupt when babble is received for the endpoint.
137073  *
137074  * Field Enumeration Values:
137075  *
137076  * Enum | Value | Description
137077  * :--------------------------------------|:------|:------------------
137078  * ALT_USB_DEV_DOEPINT15_BBLEERR_E_INACT | 0x0 | No interrupt
137079  * ALT_USB_DEV_DOEPINT15_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
137080  *
137081  * Field Access Macros:
137082  *
137083  */
137084 /*
137085  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BBLEERR
137086  *
137087  * No interrupt
137088  */
137089 #define ALT_USB_DEV_DOEPINT15_BBLEERR_E_INACT 0x0
137090 /*
137091  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_BBLEERR
137092  *
137093  * BbleErr interrupt
137094  */
137095 #define ALT_USB_DEV_DOEPINT15_BBLEERR_E_ACT 0x1
137096 
137097 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */
137098 #define ALT_USB_DEV_DOEPINT15_BBLEERR_LSB 12
137099 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */
137100 #define ALT_USB_DEV_DOEPINT15_BBLEERR_MSB 12
137101 /* The width in bits of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */
137102 #define ALT_USB_DEV_DOEPINT15_BBLEERR_WIDTH 1
137103 /* The mask used to set the ALT_USB_DEV_DOEPINT15_BBLEERR register field value. */
137104 #define ALT_USB_DEV_DOEPINT15_BBLEERR_SET_MSK 0x00001000
137105 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_BBLEERR register field value. */
137106 #define ALT_USB_DEV_DOEPINT15_BBLEERR_CLR_MSK 0xffffefff
137107 /* The reset value of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */
137108 #define ALT_USB_DEV_DOEPINT15_BBLEERR_RESET 0x0
137109 /* Extracts the ALT_USB_DEV_DOEPINT15_BBLEERR field value from a register. */
137110 #define ALT_USB_DEV_DOEPINT15_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
137111 /* Produces a ALT_USB_DEV_DOEPINT15_BBLEERR register field value suitable for setting the register. */
137112 #define ALT_USB_DEV_DOEPINT15_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
137113 
137114 /*
137115  * Field : nakintrpt
137116  *
137117  * NAK Interrupt (NAKInterrupt)
137118  *
137119  * The core generates this interrupt when a NAK is transmitted or received by the
137120  * device.
137121  *
137122  * In case of isochronous IN endpoints the interrupt gets generated when a zero
137123  * length
137124  *
137125  * packet is transmitted due to un-availability of data in the TXFifo.
137126  *
137127  * Field Enumeration Values:
137128  *
137129  * Enum | Value | Description
137130  * :----------------------------------------|:------|:--------------
137131  * ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_INACT | 0x0 | No interrupt
137132  * ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
137133  *
137134  * Field Access Macros:
137135  *
137136  */
137137 /*
137138  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_NAKINTRPT
137139  *
137140  * No interrupt
137141  */
137142 #define ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_INACT 0x0
137143 /*
137144  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_NAKINTRPT
137145  *
137146  * NAK Interrupt
137147  */
137148 #define ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_ACT 0x1
137149 
137150 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */
137151 #define ALT_USB_DEV_DOEPINT15_NAKINTRPT_LSB 13
137152 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */
137153 #define ALT_USB_DEV_DOEPINT15_NAKINTRPT_MSB 13
137154 /* The width in bits of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */
137155 #define ALT_USB_DEV_DOEPINT15_NAKINTRPT_WIDTH 1
137156 /* The mask used to set the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field value. */
137157 #define ALT_USB_DEV_DOEPINT15_NAKINTRPT_SET_MSK 0x00002000
137158 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field value. */
137159 #define ALT_USB_DEV_DOEPINT15_NAKINTRPT_CLR_MSK 0xffffdfff
137160 /* The reset value of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */
137161 #define ALT_USB_DEV_DOEPINT15_NAKINTRPT_RESET 0x0
137162 /* Extracts the ALT_USB_DEV_DOEPINT15_NAKINTRPT field value from a register. */
137163 #define ALT_USB_DEV_DOEPINT15_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
137164 /* Produces a ALT_USB_DEV_DOEPINT15_NAKINTRPT register field value suitable for setting the register. */
137165 #define ALT_USB_DEV_DOEPINT15_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
137166 
137167 /*
137168  * Field : nyetintrpt
137169  *
137170  * NYET Interrupt (NYETIntrpt)
137171  *
137172  * The core generates this interrupt when a NYET response is transmitted for a non
137173  * isochronous OUT endpoint.
137174  *
137175  * Field Enumeration Values:
137176  *
137177  * Enum | Value | Description
137178  * :-----------------------------------------|:------|:---------------
137179  * ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_INACT | 0x0 | No interrupt
137180  * ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
137181  *
137182  * Field Access Macros:
137183  *
137184  */
137185 /*
137186  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_NYETINTRPT
137187  *
137188  * No interrupt
137189  */
137190 #define ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_INACT 0x0
137191 /*
137192  * Enumerated value for register field ALT_USB_DEV_DOEPINT15_NYETINTRPT
137193  *
137194  * NYET Interrupt
137195  */
137196 #define ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_ACT 0x1
137197 
137198 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */
137199 #define ALT_USB_DEV_DOEPINT15_NYETINTRPT_LSB 14
137200 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */
137201 #define ALT_USB_DEV_DOEPINT15_NYETINTRPT_MSB 14
137202 /* The width in bits of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */
137203 #define ALT_USB_DEV_DOEPINT15_NYETINTRPT_WIDTH 1
137204 /* The mask used to set the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field value. */
137205 #define ALT_USB_DEV_DOEPINT15_NYETINTRPT_SET_MSK 0x00004000
137206 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field value. */
137207 #define ALT_USB_DEV_DOEPINT15_NYETINTRPT_CLR_MSK 0xffffbfff
137208 /* The reset value of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */
137209 #define ALT_USB_DEV_DOEPINT15_NYETINTRPT_RESET 0x0
137210 /* Extracts the ALT_USB_DEV_DOEPINT15_NYETINTRPT field value from a register. */
137211 #define ALT_USB_DEV_DOEPINT15_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
137212 /* Produces a ALT_USB_DEV_DOEPINT15_NYETINTRPT register field value suitable for setting the register. */
137213 #define ALT_USB_DEV_DOEPINT15_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
137214 
137215 /*
137216  * Field : stuppktrcvd
137217  *
137218  * Setup Packet Received
137219  *
137220  * Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
137221  *
137222  * Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
137223  *
137224  * setup data. There is only one Setup packet per buffer. On receiving a
137225  *
137226  * Setup packet, the DWC_otg core closes the buffer and disables the
137227  *
137228  * corresponding endpoint. The application has to re-enable the endpoint to
137229  *
137230  * receive any OUT data for the Control Transfer and reprogram the buffer
137231  *
137232  * start address.
137233  *
137234  * Note: Because of the above behavior, the DWC_otg core can receive any
137235  *
137236  * number of back to back setup packets and one buffer for every setup
137237  *
137238  * packet is used.
137239  *
137240  * 1'b0: No Setup packet received
137241  *
137242  * 1'b1: Setup packet received
137243  *
137244  * Reset: 1'b0
137245  *
137246  * Field Access Macros:
137247  *
137248  */
137249 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field. */
137250 #define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_LSB 15
137251 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field. */
137252 #define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_MSB 15
137253 /* The width in bits of the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field. */
137254 #define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_WIDTH 1
137255 /* The mask used to set the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field value. */
137256 #define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_SET_MSK 0x00008000
137257 /* The mask used to clear the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field value. */
137258 #define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_CLR_MSK 0xffff7fff
137259 /* The reset value of the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field. */
137260 #define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_RESET 0x0
137261 /* Extracts the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD field value from a register. */
137262 #define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
137263 /* Produces a ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field value suitable for setting the register. */
137264 #define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
137265 
137266 #ifndef __ASSEMBLY__
137267 /*
137268  * WARNING: The C register and register group struct declarations are provided for
137269  * convenience and illustrative purposes. They should, however, be used with
137270  * caution as the C language standard provides no guarantees about the alignment or
137271  * atomicity of device memory accesses. The recommended practice for writing
137272  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
137273  * alt_write_word() functions.
137274  *
137275  * The struct declaration for register ALT_USB_DEV_DOEPINT15.
137276  */
137277 struct ALT_USB_DEV_DOEPINT15_s
137278 {
137279  uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT15_XFERCOMPL */
137280  uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT15_EPDISBLD */
137281  uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT15_AHBERR */
137282  uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT15_SETUP */
137283  uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS */
137284  uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT15_STSPHSERCVD */
137285  uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP */
137286  uint32_t : 1; /* *UNDEFINED* */
137287  uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT15_OUTPKTERR */
137288  uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT15_BNAINTR */
137289  uint32_t : 1; /* *UNDEFINED* */
137290  uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT15_PKTDRPSTS */
137291  uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT15_BBLEERR */
137292  uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT15_NAKINTRPT */
137293  uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT15_NYETINTRPT */
137294  uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT15_STUPPKTRCVD */
137295  uint32_t : 16; /* *UNDEFINED* */
137296 };
137297 
137298 /* The typedef declaration for register ALT_USB_DEV_DOEPINT15. */
137299 typedef volatile struct ALT_USB_DEV_DOEPINT15_s ALT_USB_DEV_DOEPINT15_t;
137300 #endif /* __ASSEMBLY__ */
137301 
137302 /* The reset value of the ALT_USB_DEV_DOEPINT15 register. */
137303 #define ALT_USB_DEV_DOEPINT15_RESET 0x00000000
137304 /* The byte offset of the ALT_USB_DEV_DOEPINT15 register from the beginning of the component. */
137305 #define ALT_USB_DEV_DOEPINT15_OFST 0x4e8
137306 /* The address of the ALT_USB_DEV_DOEPINT15 register. */
137307 #define ALT_USB_DEV_DOEPINT15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT15_OFST))
137308 
137309 /*
137310  * Register : doeptsiz15
137311  *
137312  * Device OUT Endpoint 15 Transfer Size Register
137313  *
137314  * Register Layout
137315  *
137316  * Bits | Access | Reset | Description
137317  * :--------|:-------|:------|:--------------------------------
137318  * [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ15_XFERSIZE
137319  * [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ15_PKTCNT
137320  * [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ15_RXDPID
137321  * [31] | ??? | 0x0 | *UNDEFINED*
137322  *
137323  */
137324 /*
137325  * Field : xfersize
137326  *
137327  * Transfer Size (XferSize)
137328  *
137329  * Indicates the transfer size in bytes For endpoint 0. The core
137330  *
137331  * interrupts the application only after it has exhausted the transfer
137332  *
137333  * size amount of data. The transfer size can be Set to the
137334  *
137335  * maximum packet size of the endpoint, to be interrupted at the
137336  *
137337  * end of each packet.
137338  *
137339  * The core decrements this field every time a packet is read from
137340  *
137341  * the RxFIFO and written to the external memory.
137342  *
137343  * Field Access Macros:
137344  *
137345  */
137346 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */
137347 #define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_LSB 0
137348 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */
137349 #define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_MSB 18
137350 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */
137351 #define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_WIDTH 19
137352 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field value. */
137353 #define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_SET_MSK 0x0007ffff
137354 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field value. */
137355 #define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_CLR_MSK 0xfff80000
137356 /* The reset value of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */
137357 #define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_RESET 0x0
137358 /* Extracts the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE field value from a register. */
137359 #define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
137360 /* Produces a ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field value suitable for setting the register. */
137361 #define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
137362 
137363 /*
137364  * Field : pktcnt
137365  *
137366  * Packet Count (PktCnt)
137367  *
137368  * This field is decremented to zero after a packet is written into the
137369  *
137370  * RxFIFO.
137371  *
137372  * Field Access Macros:
137373  *
137374  */
137375 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */
137376 #define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_LSB 19
137377 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */
137378 #define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_MSB 28
137379 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */
137380 #define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_WIDTH 10
137381 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field value. */
137382 #define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_SET_MSK 0x1ff80000
137383 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field value. */
137384 #define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_CLR_MSK 0xe007ffff
137385 /* The reset value of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */
137386 #define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_RESET 0x0
137387 /* Extracts the ALT_USB_DEV_DOEPTSIZ15_PKTCNT field value from a register. */
137388 #define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
137389 /* Produces a ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field value suitable for setting the register. */
137390 #define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
137391 
137392 /*
137393  * Field : rxdpid
137394  *
137395  * Applies to isochronous OUT endpoints only.
137396  *
137397  * This is the data PID received in the last packet for this endpoint.
137398  *
137399  * 2'b00: DATA0
137400  *
137401  * 2'b01: DATA2
137402  *
137403  * 2'b10: DATA1
137404  *
137405  * 2'b11: MDATA
137406  *
137407  * SETUP Packet Count (SUPCnt)
137408  *
137409  * Applies to control OUT Endpoints only.
137410  *
137411  * This field specifies the number of back-to-back SETUP data
137412  *
137413  * packets the endpoint can receive.
137414  *
137415  * 2'b01: 1 packet
137416  *
137417  * 2'b10: 2 packets
137418  *
137419  * 2'b11: 3 packets
137420  *
137421  * Field Enumeration Values:
137422  *
137423  * Enum | Value | Description
137424  * :------------------------------------------|:------|:-------------------
137425  * ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA0 | 0x0 | DATA0
137426  * ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
137427  * ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
137428  * ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
137429  *
137430  * Field Access Macros:
137431  *
137432  */
137433 /*
137434  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID
137435  *
137436  * DATA0
137437  */
137438 #define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA0 0x0
137439 /*
137440  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID
137441  *
137442  * DATA2 or 1 packet
137443  */
137444 #define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA2PKT1 0x1
137445 /*
137446  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID
137447  *
137448  * DATA1 or 2 packets
137449  */
137450 #define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA1PKT2 0x2
137451 /*
137452  * Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID
137453  *
137454  * MDATA or 3 packets
137455  */
137456 #define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_MDATAPKT3 0x3
137457 
137458 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */
137459 #define ALT_USB_DEV_DOEPTSIZ15_RXDPID_LSB 29
137460 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */
137461 #define ALT_USB_DEV_DOEPTSIZ15_RXDPID_MSB 30
137462 /* The width in bits of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */
137463 #define ALT_USB_DEV_DOEPTSIZ15_RXDPID_WIDTH 2
137464 /* The mask used to set the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field value. */
137465 #define ALT_USB_DEV_DOEPTSIZ15_RXDPID_SET_MSK 0x60000000
137466 /* The mask used to clear the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field value. */
137467 #define ALT_USB_DEV_DOEPTSIZ15_RXDPID_CLR_MSK 0x9fffffff
137468 /* The reset value of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */
137469 #define ALT_USB_DEV_DOEPTSIZ15_RXDPID_RESET 0x0
137470 /* Extracts the ALT_USB_DEV_DOEPTSIZ15_RXDPID field value from a register. */
137471 #define ALT_USB_DEV_DOEPTSIZ15_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
137472 /* Produces a ALT_USB_DEV_DOEPTSIZ15_RXDPID register field value suitable for setting the register. */
137473 #define ALT_USB_DEV_DOEPTSIZ15_RXDPID_SET(value) (((value) << 29) & 0x60000000)
137474 
137475 #ifndef __ASSEMBLY__
137476 /*
137477  * WARNING: The C register and register group struct declarations are provided for
137478  * convenience and illustrative purposes. They should, however, be used with
137479  * caution as the C language standard provides no guarantees about the alignment or
137480  * atomicity of device memory accesses. The recommended practice for writing
137481  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
137482  * alt_write_word() functions.
137483  *
137484  * The struct declaration for register ALT_USB_DEV_DOEPTSIZ15.
137485  */
137486 struct ALT_USB_DEV_DOEPTSIZ15_s
137487 {
137488  uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ15_XFERSIZE */
137489  uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ15_PKTCNT */
137490  const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ15_RXDPID */
137491  uint32_t : 1; /* *UNDEFINED* */
137492 };
137493 
137494 /* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ15. */
137495 typedef volatile struct ALT_USB_DEV_DOEPTSIZ15_s ALT_USB_DEV_DOEPTSIZ15_t;
137496 #endif /* __ASSEMBLY__ */
137497 
137498 /* The reset value of the ALT_USB_DEV_DOEPTSIZ15 register. */
137499 #define ALT_USB_DEV_DOEPTSIZ15_RESET 0x00000000
137500 /* The byte offset of the ALT_USB_DEV_DOEPTSIZ15 register from the beginning of the component. */
137501 #define ALT_USB_DEV_DOEPTSIZ15_OFST 0x4f0
137502 /* The address of the ALT_USB_DEV_DOEPTSIZ15 register. */
137503 #define ALT_USB_DEV_DOEPTSIZ15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ15_OFST))
137504 
137505 /*
137506  * Register : doepdma15
137507  *
137508  * Device OUT Endpoint 15 DMA Address Register
137509  *
137510  * Register Layout
137511  *
137512  * Bits | Access | Reset | Description
137513  * :-------|:-------|:--------|:--------------------------------
137514  * [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA15_DOEPDMA15
137515  *
137516  */
137517 /*
137518  * Field : doepdma15
137519  *
137520  * Holds the start address of the external memory for storing or fetching endpoint
137521  *
137522  * data.
137523  *
137524  * Note: For control endpoints, this field stores control OUT data packets as well
137525  * as
137526  *
137527  * SETUP transaction data packets. When more than three SETUP packets are
137528  *
137529  * received back-to-back, the SETUP data packet in the memory is overwritten.
137530  *
137531  * This register is incremented on every AHB transaction. The application can give
137532  *
137533  * only a DWORD-aligned address.
137534  *
137535  * When Scatter/Gather DMA mode is not enabled, the application programs the
137536  *
137537  * start address value in this field.
137538  *
137539  * When Scatter/Gather DMA mode is enabled, this field indicates the base
137540  *
137541  * pointer for the descriptor list.
137542  *
137543  * Field Access Macros:
137544  *
137545  */
137546 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field. */
137547 #define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_LSB 0
137548 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field. */
137549 #define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_MSB 31
137550 /* The width in bits of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field. */
137551 #define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_WIDTH 32
137552 /* The mask used to set the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field value. */
137553 #define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_SET_MSK 0xffffffff
137554 /* The mask used to clear the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field value. */
137555 #define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_CLR_MSK 0x00000000
137556 /* The reset value of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field is UNKNOWN. */
137557 #define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_RESET 0x0
137558 /* Extracts the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 field value from a register. */
137559 #define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_GET(value) (((value) & 0xffffffff) >> 0)
137560 /* Produces a ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field value suitable for setting the register. */
137561 #define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_SET(value) (((value) << 0) & 0xffffffff)
137562 
137563 #ifndef __ASSEMBLY__
137564 /*
137565  * WARNING: The C register and register group struct declarations are provided for
137566  * convenience and illustrative purposes. They should, however, be used with
137567  * caution as the C language standard provides no guarantees about the alignment or
137568  * atomicity of device memory accesses. The recommended practice for writing
137569  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
137570  * alt_write_word() functions.
137571  *
137572  * The struct declaration for register ALT_USB_DEV_DOEPDMA15.
137573  */
137574 struct ALT_USB_DEV_DOEPDMA15_s
137575 {
137576  uint32_t doepdma15 : 32; /* ALT_USB_DEV_DOEPDMA15_DOEPDMA15 */
137577 };
137578 
137579 /* The typedef declaration for register ALT_USB_DEV_DOEPDMA15. */
137580 typedef volatile struct ALT_USB_DEV_DOEPDMA15_s ALT_USB_DEV_DOEPDMA15_t;
137581 #endif /* __ASSEMBLY__ */
137582 
137583 /* The reset value of the ALT_USB_DEV_DOEPDMA15 register. */
137584 #define ALT_USB_DEV_DOEPDMA15_RESET 0x00000000
137585 /* The byte offset of the ALT_USB_DEV_DOEPDMA15 register from the beginning of the component. */
137586 #define ALT_USB_DEV_DOEPDMA15_OFST 0x4f4
137587 /* The address of the ALT_USB_DEV_DOEPDMA15 register. */
137588 #define ALT_USB_DEV_DOEPDMA15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA15_OFST))
137589 
137590 /*
137591  * Register : doepdmab15
137592  *
137593  * Device OUT Endpoint 15 Buffer Address Register
137594  *
137595  * Register Layout
137596  *
137597  * Bits | Access | Reset | Description
137598  * :-------|:-------|:--------|:----------------------------------
137599  * [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15
137600  *
137601  */
137602 /*
137603  * Field : doepdmab15
137604  *
137605  * Holds the current buffer address.This register is updated as and when the data
137606  *
137607  * transfer for the corresponding end point is in progress.
137608  *
137609  * This register is present only in Scatter/Gather DMA mode. Otherwise this field
137610  * is
137611  *
137612  * reserved.
137613  *
137614  * Field Access Macros:
137615  *
137616  */
137617 /* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field. */
137618 #define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_LSB 0
137619 /* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field. */
137620 #define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_MSB 31
137621 /* The width in bits of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field. */
137622 #define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_WIDTH 32
137623 /* The mask used to set the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field value. */
137624 #define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_SET_MSK 0xffffffff
137625 /* The mask used to clear the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field value. */
137626 #define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_CLR_MSK 0x00000000
137627 /* The reset value of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field is UNKNOWN. */
137628 #define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_RESET 0x0
137629 /* Extracts the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 field value from a register. */
137630 #define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_GET(value) (((value) & 0xffffffff) >> 0)
137631 /* Produces a ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field value suitable for setting the register. */
137632 #define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_SET(value) (((value) << 0) & 0xffffffff)
137633 
137634 #ifndef __ASSEMBLY__
137635 /*
137636  * WARNING: The C register and register group struct declarations are provided for
137637  * convenience and illustrative purposes. They should, however, be used with
137638  * caution as the C language standard provides no guarantees about the alignment or
137639  * atomicity of device memory accesses. The recommended practice for writing
137640  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
137641  * alt_write_word() functions.
137642  *
137643  * The struct declaration for register ALT_USB_DEV_DOEPDMAB15.
137644  */
137645 struct ALT_USB_DEV_DOEPDMAB15_s
137646 {
137647  const uint32_t doepdmab15 : 32; /* ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 */
137648 };
137649 
137650 /* The typedef declaration for register ALT_USB_DEV_DOEPDMAB15. */
137651 typedef volatile struct ALT_USB_DEV_DOEPDMAB15_s ALT_USB_DEV_DOEPDMAB15_t;
137652 #endif /* __ASSEMBLY__ */
137653 
137654 /* The reset value of the ALT_USB_DEV_DOEPDMAB15 register. */
137655 #define ALT_USB_DEV_DOEPDMAB15_RESET 0x00000000
137656 /* The byte offset of the ALT_USB_DEV_DOEPDMAB15 register from the beginning of the component. */
137657 #define ALT_USB_DEV_DOEPDMAB15_OFST 0x4fc
137658 /* The address of the ALT_USB_DEV_DOEPDMAB15 register. */
137659 #define ALT_USB_DEV_DOEPDMAB15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB15_OFST))
137660 
137661 #ifndef __ASSEMBLY__
137662 /*
137663  * WARNING: The C register and register group struct declarations are provided for
137664  * convenience and illustrative purposes. They should, however, be used with
137665  * caution as the C language standard provides no guarantees about the alignment or
137666  * atomicity of device memory accesses. The recommended practice for writing
137667  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
137668  * alt_write_word() functions.
137669  *
137670  * The struct declaration for register group ALT_USB_DEV.
137671  */
137672 struct ALT_USB_DEV_s
137673 {
137674  ALT_USB_DEV_DCFG_t dcfg; /* ALT_USB_DEV_DCFG */
137675  ALT_USB_DEV_DCTL_t dctl; /* ALT_USB_DEV_DCTL */
137676  ALT_USB_DEV_DSTS_t dsts; /* ALT_USB_DEV_DSTS */
137677  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
137678  ALT_USB_DEV_DIEPMSK_t diepmsk; /* ALT_USB_DEV_DIEPMSK */
137679  ALT_USB_DEV_DOEPMSK_t doepmsk; /* ALT_USB_DEV_DOEPMSK */
137680  ALT_USB_DEV_DAINT_t daint; /* ALT_USB_DEV_DAINT */
137681  ALT_USB_DEV_DAINTMSK_t daintmsk; /* ALT_USB_DEV_DAINTMSK */
137682  volatile uint32_t _pad_0x20_0x27[2]; /* *UNDEFINED* */
137683  ALT_USB_DEV_DVBUSDIS_t dvbusdis; /* ALT_USB_DEV_DVBUSDIS */
137684  ALT_USB_DEV_DVBUSPULSE_t dvbuspulse; /* ALT_USB_DEV_DVBUSPULSE */
137685  ALT_USB_DEV_DTHRCTL_t dthrctl; /* ALT_USB_DEV_DTHRCTL */
137686  ALT_USB_DEV_DIEPEMPMSK_t diepempmsk; /* ALT_USB_DEV_DIEPEMPMSK */
137687  volatile uint32_t _pad_0x38_0xff[50]; /* *UNDEFINED* */
137688  ALT_USB_DEV_DIEPCTL0_t diepctl0; /* ALT_USB_DEV_DIEPCTL0 */
137689  volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */
137690  ALT_USB_DEV_DIEPINT0_t diepint0; /* ALT_USB_DEV_DIEPINT0 */
137691  volatile uint32_t _pad_0x10c_0x10f; /* *UNDEFINED* */
137692  ALT_USB_DEV_DIEPTSIZ0_t dieptsiz0; /* ALT_USB_DEV_DIEPTSIZ0 */
137693  ALT_USB_DEV_DIEPDMA0_t diepdma0; /* ALT_USB_DEV_DIEPDMA0 */
137694  ALT_USB_DEV_DTXFSTS0_t dtxfsts0; /* ALT_USB_DEV_DTXFSTS0 */
137695  ALT_USB_DEV_DIEPDMAB0_t diepdmab0; /* ALT_USB_DEV_DIEPDMAB0 */
137696  ALT_USB_DEV_DIEPCTL1_t diepctl1; /* ALT_USB_DEV_DIEPCTL1 */
137697  volatile uint32_t _pad_0x124_0x127; /* *UNDEFINED* */
137698  ALT_USB_DEV_DIEPINT1_t diepint1; /* ALT_USB_DEV_DIEPINT1 */
137699  volatile uint32_t _pad_0x12c_0x12f; /* *UNDEFINED* */
137700  ALT_USB_DEV_DIEPTSIZ1_t dieptsiz1; /* ALT_USB_DEV_DIEPTSIZ1 */
137701  ALT_USB_DEV_DIEPDMA1_t diepdma1; /* ALT_USB_DEV_DIEPDMA1 */
137702  ALT_USB_DEV_DTXFSTS1_t dtxfsts1; /* ALT_USB_DEV_DTXFSTS1 */
137703  ALT_USB_DEV_DIEPDMAB1_t diepdmab1; /* ALT_USB_DEV_DIEPDMAB1 */
137704  ALT_USB_DEV_DIEPCTL2_t diepctl2; /* ALT_USB_DEV_DIEPCTL2 */
137705  volatile uint32_t _pad_0x144_0x147; /* *UNDEFINED* */
137706  ALT_USB_DEV_DIEPINT2_t diepint2; /* ALT_USB_DEV_DIEPINT2 */
137707  volatile uint32_t _pad_0x14c_0x14f; /* *UNDEFINED* */
137708  ALT_USB_DEV_DIEPTSIZ2_t dieptsiz2; /* ALT_USB_DEV_DIEPTSIZ2 */
137709  ALT_USB_DEV_DIEPDMA2_t diepdma2; /* ALT_USB_DEV_DIEPDMA2 */
137710  ALT_USB_DEV_DTXFSTS2_t dtxfsts2; /* ALT_USB_DEV_DTXFSTS2 */
137711  ALT_USB_DEV_DIEPDMAB2_t diepdmab2; /* ALT_USB_DEV_DIEPDMAB2 */
137712  ALT_USB_DEV_DIEPCTL3_t diepctl3; /* ALT_USB_DEV_DIEPCTL3 */
137713  volatile uint32_t _pad_0x164_0x167; /* *UNDEFINED* */
137714  ALT_USB_DEV_DIEPINT3_t diepint3; /* ALT_USB_DEV_DIEPINT3 */
137715  volatile uint32_t _pad_0x16c_0x16f; /* *UNDEFINED* */
137716  ALT_USB_DEV_DIEPTSIZ3_t dieptsiz3; /* ALT_USB_DEV_DIEPTSIZ3 */
137717  ALT_USB_DEV_DIEPDMA3_t diepdma3; /* ALT_USB_DEV_DIEPDMA3 */
137718  ALT_USB_DEV_DTXFSTS3_t dtxfsts3; /* ALT_USB_DEV_DTXFSTS3 */
137719  ALT_USB_DEV_DIEPDMAB3_t diepdmab3; /* ALT_USB_DEV_DIEPDMAB3 */
137720  ALT_USB_DEV_DIEPCTL4_t diepctl4; /* ALT_USB_DEV_DIEPCTL4 */
137721  volatile uint32_t _pad_0x184_0x187; /* *UNDEFINED* */
137722  ALT_USB_DEV_DIEPINT4_t diepint4; /* ALT_USB_DEV_DIEPINT4 */
137723  volatile uint32_t _pad_0x18c_0x18f; /* *UNDEFINED* */
137724  ALT_USB_DEV_DIEPTSIZ4_t dieptsiz4; /* ALT_USB_DEV_DIEPTSIZ4 */
137725  ALT_USB_DEV_DIEPDMA4_t diepdma4; /* ALT_USB_DEV_DIEPDMA4 */
137726  ALT_USB_DEV_DTXFSTS4_t dtxfsts4; /* ALT_USB_DEV_DTXFSTS4 */
137727  ALT_USB_DEV_DIEPDMAB4_t diepdmab4; /* ALT_USB_DEV_DIEPDMAB4 */
137728  ALT_USB_DEV_DIEPCTL5_t diepctl5; /* ALT_USB_DEV_DIEPCTL5 */
137729  volatile uint32_t _pad_0x1a4_0x1a7; /* *UNDEFINED* */
137730  ALT_USB_DEV_DIEPINT5_t diepint5; /* ALT_USB_DEV_DIEPINT5 */
137731  volatile uint32_t _pad_0x1ac_0x1af; /* *UNDEFINED* */
137732  ALT_USB_DEV_DIEPTSIZ5_t dieptsiz5; /* ALT_USB_DEV_DIEPTSIZ5 */
137733  ALT_USB_DEV_DIEPDMA5_t diepdma5; /* ALT_USB_DEV_DIEPDMA5 */
137734  ALT_USB_DEV_DTXFSTS5_t dtxfsts5; /* ALT_USB_DEV_DTXFSTS5 */
137735  ALT_USB_DEV_DIEPDMAB5_t diepdmab5; /* ALT_USB_DEV_DIEPDMAB5 */
137736  ALT_USB_DEV_DIEPCTL6_t diepctl6; /* ALT_USB_DEV_DIEPCTL6 */
137737  volatile uint32_t _pad_0x1c4_0x1c7; /* *UNDEFINED* */
137738  ALT_USB_DEV_DIEPINT6_t diepint6; /* ALT_USB_DEV_DIEPINT6 */
137739  volatile uint32_t _pad_0x1cc_0x1cf; /* *UNDEFINED* */
137740  ALT_USB_DEV_DIEPTSIZ6_t dieptsiz6; /* ALT_USB_DEV_DIEPTSIZ6 */
137741  ALT_USB_DEV_DIEPDMA6_t diepdma6; /* ALT_USB_DEV_DIEPDMA6 */
137742  ALT_USB_DEV_DTXFSTS6_t dtxfsts6; /* ALT_USB_DEV_DTXFSTS6 */
137743  ALT_USB_DEV_DIEPDMAB6_t diepdmab6; /* ALT_USB_DEV_DIEPDMAB6 */
137744  ALT_USB_DEV_DIEPCTL7_t diepctl7; /* ALT_USB_DEV_DIEPCTL7 */
137745  volatile uint32_t _pad_0x1e4_0x1e7; /* *UNDEFINED* */
137746  ALT_USB_DEV_DIEPINT7_t diepint7; /* ALT_USB_DEV_DIEPINT7 */
137747  volatile uint32_t _pad_0x1ec_0x1ef; /* *UNDEFINED* */
137748  ALT_USB_DEV_DIEPTSIZ7_t dieptsiz7; /* ALT_USB_DEV_DIEPTSIZ7 */
137749  ALT_USB_DEV_DIEPDMA7_t diepdma7; /* ALT_USB_DEV_DIEPDMA7 */
137750  ALT_USB_DEV_DTXFSTS7_t dtxfsts7; /* ALT_USB_DEV_DTXFSTS7 */
137751  ALT_USB_DEV_DIEPDMAB7_t diepdmab7; /* ALT_USB_DEV_DIEPDMAB7 */
137752  ALT_USB_DEV_DIEPCTL8_t diepctl8; /* ALT_USB_DEV_DIEPCTL8 */
137753  volatile uint32_t _pad_0x204_0x207; /* *UNDEFINED* */
137754  ALT_USB_DEV_DIEPINT8_t diepint8; /* ALT_USB_DEV_DIEPINT8 */
137755  volatile uint32_t _pad_0x20c_0x20f; /* *UNDEFINED* */
137756  ALT_USB_DEV_DIEPTSIZ8_t dieptsiz8; /* ALT_USB_DEV_DIEPTSIZ8 */
137757  ALT_USB_DEV_DIEPDMA8_t diepdma8; /* ALT_USB_DEV_DIEPDMA8 */
137758  ALT_USB_DEV_DTXFSTS8_t dtxfsts8; /* ALT_USB_DEV_DTXFSTS8 */
137759  ALT_USB_DEV_DIEPDMAB8_t diepdmab8; /* ALT_USB_DEV_DIEPDMAB8 */
137760  ALT_USB_DEV_DIEPCTL9_t diepctl9; /* ALT_USB_DEV_DIEPCTL9 */
137761  volatile uint32_t _pad_0x224_0x227; /* *UNDEFINED* */
137762  ALT_USB_DEV_DIEPINT9_t diepint9; /* ALT_USB_DEV_DIEPINT9 */
137763  volatile uint32_t _pad_0x22c_0x22f; /* *UNDEFINED* */
137764  ALT_USB_DEV_DIEPTSIZ9_t dieptsiz9; /* ALT_USB_DEV_DIEPTSIZ9 */
137765  ALT_USB_DEV_DIEPDMA9_t diepdma9; /* ALT_USB_DEV_DIEPDMA9 */
137766  ALT_USB_DEV_DTXFSTS9_t dtxfsts9; /* ALT_USB_DEV_DTXFSTS9 */
137767  ALT_USB_DEV_DIEPDMAB9_t diepdmab9; /* ALT_USB_DEV_DIEPDMAB9 */
137768  ALT_USB_DEV_DIEPCTL10_t diepctl10; /* ALT_USB_DEV_DIEPCTL10 */
137769  volatile uint32_t _pad_0x244_0x247; /* *UNDEFINED* */
137770  ALT_USB_DEV_DIEPINT10_t diepint10; /* ALT_USB_DEV_DIEPINT10 */
137771  volatile uint32_t _pad_0x24c_0x24f; /* *UNDEFINED* */
137772  ALT_USB_DEV_DIEPTSIZ10_t dieptsiz10; /* ALT_USB_DEV_DIEPTSIZ10 */
137773  ALT_USB_DEV_DIEPDMA10_t diepdma10; /* ALT_USB_DEV_DIEPDMA10 */
137774  ALT_USB_DEV_DTXFSTS10_t dtxfsts10; /* ALT_USB_DEV_DTXFSTS10 */
137775  ALT_USB_DEV_DIEPDMAB10_t diepdmab10; /* ALT_USB_DEV_DIEPDMAB10 */
137776  ALT_USB_DEV_DIEPCTL11_t diepctl11; /* ALT_USB_DEV_DIEPCTL11 */
137777  volatile uint32_t _pad_0x264_0x267; /* *UNDEFINED* */
137778  ALT_USB_DEV_DIEPINT11_t diepint11; /* ALT_USB_DEV_DIEPINT11 */
137779  volatile uint32_t _pad_0x26c_0x26f; /* *UNDEFINED* */
137780  ALT_USB_DEV_DIEPTSIZ11_t dieptsiz11; /* ALT_USB_DEV_DIEPTSIZ11 */
137781  ALT_USB_DEV_DIEPDMA11_t diepdma11; /* ALT_USB_DEV_DIEPDMA11 */
137782  ALT_USB_DEV_DTXFSTS11_t dtxfsts11; /* ALT_USB_DEV_DTXFSTS11 */
137783  ALT_USB_DEV_DIEPDMAB11_t diepdmab11; /* ALT_USB_DEV_DIEPDMAB11 */
137784  ALT_USB_DEV_DIEPCTL12_t diepctl12; /* ALT_USB_DEV_DIEPCTL12 */
137785  volatile uint32_t _pad_0x284_0x287; /* *UNDEFINED* */
137786  ALT_USB_DEV_DIEPINT12_t diepint12; /* ALT_USB_DEV_DIEPINT12 */
137787  volatile uint32_t _pad_0x28c_0x28f; /* *UNDEFINED* */
137788  ALT_USB_DEV_DIEPTSIZ12_t dieptsiz12; /* ALT_USB_DEV_DIEPTSIZ12 */
137789  ALT_USB_DEV_DIEPDMA12_t diepdma12; /* ALT_USB_DEV_DIEPDMA12 */
137790  ALT_USB_DEV_DTXFSTS12_t dtxfsts12; /* ALT_USB_DEV_DTXFSTS12 */
137791  ALT_USB_DEV_DIEPDMAB12_t diepdmab12; /* ALT_USB_DEV_DIEPDMAB12 */
137792  ALT_USB_DEV_DIEPCTL13_t diepctl13; /* ALT_USB_DEV_DIEPCTL13 */
137793  volatile uint32_t _pad_0x2a4_0x2a7; /* *UNDEFINED* */
137794  ALT_USB_DEV_DIEPINT13_t diepint13; /* ALT_USB_DEV_DIEPINT13 */
137795  volatile uint32_t _pad_0x2ac_0x2af; /* *UNDEFINED* */
137796  ALT_USB_DEV_DIEPTSIZ13_t dieptsiz13; /* ALT_USB_DEV_DIEPTSIZ13 */
137797  ALT_USB_DEV_DIEPDMA13_t diepdma13; /* ALT_USB_DEV_DIEPDMA13 */
137798  ALT_USB_DEV_DTXFSTS13_t dtxfsts13; /* ALT_USB_DEV_DTXFSTS13 */
137799  ALT_USB_DEV_DIEPDMAB13_t diepdmab13; /* ALT_USB_DEV_DIEPDMAB13 */
137800  ALT_USB_DEV_DIEPCTL14_t diepctl14; /* ALT_USB_DEV_DIEPCTL14 */
137801  volatile uint32_t _pad_0x2c4_0x2c7; /* *UNDEFINED* */
137802  ALT_USB_DEV_DIEPINT14_t diepint14; /* ALT_USB_DEV_DIEPINT14 */
137803  volatile uint32_t _pad_0x2cc_0x2cf; /* *UNDEFINED* */
137804  ALT_USB_DEV_DIEPTSIZ14_t dieptsiz14; /* ALT_USB_DEV_DIEPTSIZ14 */
137805  ALT_USB_DEV_DIEPDMA14_t diepdma14; /* ALT_USB_DEV_DIEPDMA14 */
137806  ALT_USB_DEV_DTXFSTS14_t dtxfsts14; /* ALT_USB_DEV_DTXFSTS14 */
137807  ALT_USB_DEV_DIEPDMAB14_t diepdmab14; /* ALT_USB_DEV_DIEPDMAB14 */
137808  ALT_USB_DEV_DIEPCTL15_t diepctl15; /* ALT_USB_DEV_DIEPCTL15 */
137809  volatile uint32_t _pad_0x2e4_0x2e7; /* *UNDEFINED* */
137810  ALT_USB_DEV_DIEPINT15_t diepint15; /* ALT_USB_DEV_DIEPINT15 */
137811  volatile uint32_t _pad_0x2ec_0x2ef; /* *UNDEFINED* */
137812  ALT_USB_DEV_DIEPTSIZ15_t dieptsiz15; /* ALT_USB_DEV_DIEPTSIZ15 */
137813  ALT_USB_DEV_DIEPDMA15_t diepdma15; /* ALT_USB_DEV_DIEPDMA15 */
137814  ALT_USB_DEV_DTXFSTS15_t dtxfsts15; /* ALT_USB_DEV_DTXFSTS15 */
137815  ALT_USB_DEV_DIEPDMAB15_t diepdmab15; /* ALT_USB_DEV_DIEPDMAB15 */
137816  ALT_USB_DEV_DOEPCTL0_t doepctl0; /* ALT_USB_DEV_DOEPCTL0 */
137817  volatile uint32_t _pad_0x304_0x307; /* *UNDEFINED* */
137818  ALT_USB_DEV_DOEPINT0_t doepint0; /* ALT_USB_DEV_DOEPINT0 */
137819  volatile uint32_t _pad_0x30c_0x30f; /* *UNDEFINED* */
137820  ALT_USB_DEV_DOEPTSIZ0_t doeptsiz0; /* ALT_USB_DEV_DOEPTSIZ0 */
137821  ALT_USB_DEV_DOEPDMA0_t doepdma0; /* ALT_USB_DEV_DOEPDMA0 */
137822  volatile uint32_t _pad_0x318_0x31b; /* *UNDEFINED* */
137823  ALT_USB_DEV_DOEPDMAB0_t doepdmab0; /* ALT_USB_DEV_DOEPDMAB0 */
137824  ALT_USB_DEV_DOEPCTL1_t doepctl1; /* ALT_USB_DEV_DOEPCTL1 */
137825  volatile uint32_t _pad_0x324_0x327; /* *UNDEFINED* */
137826  ALT_USB_DEV_DOEPINT1_t doepint1; /* ALT_USB_DEV_DOEPINT1 */
137827  volatile uint32_t _pad_0x32c_0x32f; /* *UNDEFINED* */
137828  ALT_USB_DEV_DOEPTSIZ1_t doeptsiz1; /* ALT_USB_DEV_DOEPTSIZ1 */
137829  ALT_USB_DEV_DOEPDMA1_t doepdma1; /* ALT_USB_DEV_DOEPDMA1 */
137830  volatile uint32_t _pad_0x338_0x33b; /* *UNDEFINED* */
137831  ALT_USB_DEV_DOEPDMAB1_t doepdmab1; /* ALT_USB_DEV_DOEPDMAB1 */
137832  ALT_USB_DEV_DOEPCTL2_t doepctl2; /* ALT_USB_DEV_DOEPCTL2 */
137833  volatile uint32_t _pad_0x344_0x347; /* *UNDEFINED* */
137834  ALT_USB_DEV_DOEPINT2_t doepint2; /* ALT_USB_DEV_DOEPINT2 */
137835  volatile uint32_t _pad_0x34c_0x34f; /* *UNDEFINED* */
137836  ALT_USB_DEV_DOEPTSIZ2_t doeptsiz2; /* ALT_USB_DEV_DOEPTSIZ2 */
137837  ALT_USB_DEV_DOEPDMA2_t doepdma2; /* ALT_USB_DEV_DOEPDMA2 */
137838  volatile uint32_t _pad_0x358_0x35b; /* *UNDEFINED* */
137839  ALT_USB_DEV_DOEPDMAB2_t doepdmab2; /* ALT_USB_DEV_DOEPDMAB2 */
137840  ALT_USB_DEV_DOEPCTL3_t doepctl3; /* ALT_USB_DEV_DOEPCTL3 */
137841  volatile uint32_t _pad_0x364_0x367; /* *UNDEFINED* */
137842  ALT_USB_DEV_DOEPINT3_t doepint3; /* ALT_USB_DEV_DOEPINT3 */
137843  volatile uint32_t _pad_0x36c_0x36f; /* *UNDEFINED* */
137844  ALT_USB_DEV_DOEPTSIZ3_t doeptsiz3; /* ALT_USB_DEV_DOEPTSIZ3 */
137845  ALT_USB_DEV_DOEPDMA3_t doepdma3; /* ALT_USB_DEV_DOEPDMA3 */
137846  volatile uint32_t _pad_0x378_0x37b; /* *UNDEFINED* */
137847  ALT_USB_DEV_DOEPDMAB3_t doepdmab3; /* ALT_USB_DEV_DOEPDMAB3 */
137848  ALT_USB_DEV_DOEPCTL4_t doepctl4; /* ALT_USB_DEV_DOEPCTL4 */
137849  volatile uint32_t _pad_0x384_0x387; /* *UNDEFINED* */
137850  ALT_USB_DEV_DOEPINT4_t doepint4; /* ALT_USB_DEV_DOEPINT4 */
137851  volatile uint32_t _pad_0x38c_0x38f; /* *UNDEFINED* */
137852  ALT_USB_DEV_DOEPTSIZ4_t doeptsiz4; /* ALT_USB_DEV_DOEPTSIZ4 */
137853  ALT_USB_DEV_DOEPDMA4_t doepdma4; /* ALT_USB_DEV_DOEPDMA4 */
137854  volatile uint32_t _pad_0x398_0x39b; /* *UNDEFINED* */
137855  ALT_USB_DEV_DOEPDMAB4_t doepdmab4; /* ALT_USB_DEV_DOEPDMAB4 */
137856  ALT_USB_DEV_DOEPCTL5_t doepctl5; /* ALT_USB_DEV_DOEPCTL5 */
137857  volatile uint32_t _pad_0x3a4_0x3a7; /* *UNDEFINED* */
137858  ALT_USB_DEV_DOEPINT5_t doepint5; /* ALT_USB_DEV_DOEPINT5 */
137859  volatile uint32_t _pad_0x3ac_0x3af; /* *UNDEFINED* */
137860  ALT_USB_DEV_DOEPTSIZ5_t doeptsiz5; /* ALT_USB_DEV_DOEPTSIZ5 */
137861  ALT_USB_DEV_DOEPDMA5_t doepdma5; /* ALT_USB_DEV_DOEPDMA5 */
137862  volatile uint32_t _pad_0x3b8_0x3bb; /* *UNDEFINED* */
137863  ALT_USB_DEV_DOEPDMAB5_t doepdmab5; /* ALT_USB_DEV_DOEPDMAB5 */
137864  ALT_USB_DEV_DOEPCTL6_t doepctl6; /* ALT_USB_DEV_DOEPCTL6 */
137865  volatile uint32_t _pad_0x3c4_0x3c7; /* *UNDEFINED* */
137866  ALT_USB_DEV_DOEPINT6_t doepint6; /* ALT_USB_DEV_DOEPINT6 */
137867  volatile uint32_t _pad_0x3cc_0x3cf; /* *UNDEFINED* */
137868  ALT_USB_DEV_DOEPTSIZ6_t doeptsiz6; /* ALT_USB_DEV_DOEPTSIZ6 */
137869  ALT_USB_DEV_DOEPDMA6_t doepdma6; /* ALT_USB_DEV_DOEPDMA6 */
137870  volatile uint32_t _pad_0x3d8_0x3db; /* *UNDEFINED* */
137871  ALT_USB_DEV_DOEPDMAB6_t doepdmab6; /* ALT_USB_DEV_DOEPDMAB6 */
137872  ALT_USB_DEV_DOEPCTL7_t doepctl7; /* ALT_USB_DEV_DOEPCTL7 */
137873  volatile uint32_t _pad_0x3e4_0x3e7; /* *UNDEFINED* */
137874  ALT_USB_DEV_DOEPINT7_t doepint7; /* ALT_USB_DEV_DOEPINT7 */
137875  volatile uint32_t _pad_0x3ec_0x3ef; /* *UNDEFINED* */
137876  ALT_USB_DEV_DOEPTSIZ7_t doeptsiz7; /* ALT_USB_DEV_DOEPTSIZ7 */
137877  ALT_USB_DEV_DOEPDMA7_t doepdma7; /* ALT_USB_DEV_DOEPDMA7 */
137878  volatile uint32_t _pad_0x3f8_0x3fb; /* *UNDEFINED* */
137879  ALT_USB_DEV_DOEPDMAB7_t doepdmab7; /* ALT_USB_DEV_DOEPDMAB7 */
137880  ALT_USB_DEV_DOEPCTL8_t doepctl8; /* ALT_USB_DEV_DOEPCTL8 */
137881  volatile uint32_t _pad_0x404_0x407; /* *UNDEFINED* */
137882  ALT_USB_DEV_DOEPINT8_t doepint8; /* ALT_USB_DEV_DOEPINT8 */
137883  volatile uint32_t _pad_0x40c_0x40f; /* *UNDEFINED* */
137884  ALT_USB_DEV_DOEPTSIZ8_t doeptsiz8; /* ALT_USB_DEV_DOEPTSIZ8 */
137885  ALT_USB_DEV_DOEPDMA8_t doepdma8; /* ALT_USB_DEV_DOEPDMA8 */
137886  volatile uint32_t _pad_0x418_0x41b; /* *UNDEFINED* */
137887  ALT_USB_DEV_DOEPDMAB8_t doepdmab8; /* ALT_USB_DEV_DOEPDMAB8 */
137888  ALT_USB_DEV_DOEPCTL9_t doepctl9; /* ALT_USB_DEV_DOEPCTL9 */
137889  volatile uint32_t _pad_0x424_0x427; /* *UNDEFINED* */
137890  ALT_USB_DEV_DOEPINT9_t doepint9; /* ALT_USB_DEV_DOEPINT9 */
137891  volatile uint32_t _pad_0x42c_0x42f; /* *UNDEFINED* */
137892  ALT_USB_DEV_DOEPTSIZ9_t doeptsiz9; /* ALT_USB_DEV_DOEPTSIZ9 */
137893  ALT_USB_DEV_DOEPDMA9_t doepdma9; /* ALT_USB_DEV_DOEPDMA9 */
137894  volatile uint32_t _pad_0x438_0x43b; /* *UNDEFINED* */
137895  ALT_USB_DEV_DOEPDMAB9_t doepdmab9; /* ALT_USB_DEV_DOEPDMAB9 */
137896  ALT_USB_DEV_DOEPCTL10_t doepctl10; /* ALT_USB_DEV_DOEPCTL10 */
137897  volatile uint32_t _pad_0x444_0x447; /* *UNDEFINED* */
137898  ALT_USB_DEV_DOEPINT10_t doepint10; /* ALT_USB_DEV_DOEPINT10 */
137899  volatile uint32_t _pad_0x44c_0x44f; /* *UNDEFINED* */
137900  ALT_USB_DEV_DOEPTSIZ10_t doeptsiz10; /* ALT_USB_DEV_DOEPTSIZ10 */
137901  ALT_USB_DEV_DOEPDMA10_t doepdma10; /* ALT_USB_DEV_DOEPDMA10 */
137902  volatile uint32_t _pad_0x458_0x45b; /* *UNDEFINED* */
137903  ALT_USB_DEV_DOEPDMAB10_t doepdmab10; /* ALT_USB_DEV_DOEPDMAB10 */
137904  ALT_USB_DEV_DOEPCTL11_t doepctl11; /* ALT_USB_DEV_DOEPCTL11 */
137905  volatile uint32_t _pad_0x464_0x467; /* *UNDEFINED* */
137906  ALT_USB_DEV_DOEPINT11_t doepint11; /* ALT_USB_DEV_DOEPINT11 */
137907  volatile uint32_t _pad_0x46c_0x46f; /* *UNDEFINED* */
137908  ALT_USB_DEV_DOEPTSIZ11_t doeptsiz11; /* ALT_USB_DEV_DOEPTSIZ11 */
137909  ALT_USB_DEV_DOEPDMA11_t doepdma11; /* ALT_USB_DEV_DOEPDMA11 */
137910  volatile uint32_t _pad_0x478_0x47b; /* *UNDEFINED* */
137911  ALT_USB_DEV_DOEPDMAB11_t doepdmab11; /* ALT_USB_DEV_DOEPDMAB11 */
137912  ALT_USB_DEV_DOEPCTL12_t doepctl12; /* ALT_USB_DEV_DOEPCTL12 */
137913  volatile uint32_t _pad_0x484_0x487; /* *UNDEFINED* */
137914  ALT_USB_DEV_DOEPINT12_t doepint12; /* ALT_USB_DEV_DOEPINT12 */
137915  volatile uint32_t _pad_0x48c_0x48f; /* *UNDEFINED* */
137916  ALT_USB_DEV_DOEPTSIZ12_t doeptsiz12; /* ALT_USB_DEV_DOEPTSIZ12 */
137917  ALT_USB_DEV_DOEPDMA12_t doepdma12; /* ALT_USB_DEV_DOEPDMA12 */
137918  volatile uint32_t _pad_0x498_0x49b; /* *UNDEFINED* */
137919  ALT_USB_DEV_DOEPDMAB12_t doepdmab12; /* ALT_USB_DEV_DOEPDMAB12 */
137920  ALT_USB_DEV_DOEPCTL13_t doepctl13; /* ALT_USB_DEV_DOEPCTL13 */
137921  volatile uint32_t _pad_0x4a4_0x4a7; /* *UNDEFINED* */
137922  ALT_USB_DEV_DOEPINT13_t doepint13; /* ALT_USB_DEV_DOEPINT13 */
137923  volatile uint32_t _pad_0x4ac_0x4af; /* *UNDEFINED* */
137924  ALT_USB_DEV_DOEPTSIZ13_t doeptsiz13; /* ALT_USB_DEV_DOEPTSIZ13 */
137925  ALT_USB_DEV_DOEPDMA13_t doepdma13; /* ALT_USB_DEV_DOEPDMA13 */
137926  volatile uint32_t _pad_0x4b8_0x4bb; /* *UNDEFINED* */
137927  ALT_USB_DEV_DOEPDMAB13_t doepdmab13; /* ALT_USB_DEV_DOEPDMAB13 */
137928  ALT_USB_DEV_DOEPCTL14_t doepctl14; /* ALT_USB_DEV_DOEPCTL14 */
137929  volatile uint32_t _pad_0x4c4_0x4c7; /* *UNDEFINED* */
137930  ALT_USB_DEV_DOEPINT14_t doepint14; /* ALT_USB_DEV_DOEPINT14 */
137931  volatile uint32_t _pad_0x4cc_0x4cf; /* *UNDEFINED* */
137932  ALT_USB_DEV_DOEPTSIZ14_t doeptsiz14; /* ALT_USB_DEV_DOEPTSIZ14 */
137933  ALT_USB_DEV_DOEPDMA14_t doepdma14; /* ALT_USB_DEV_DOEPDMA14 */
137934  volatile uint32_t _pad_0x4d8_0x4db; /* *UNDEFINED* */
137935  ALT_USB_DEV_DOEPDMAB14_t doepdmab14; /* ALT_USB_DEV_DOEPDMAB14 */
137936  ALT_USB_DEV_DOEPCTL15_t doepctl15; /* ALT_USB_DEV_DOEPCTL15 */
137937  volatile uint32_t _pad_0x4e4_0x4e7; /* *UNDEFINED* */
137938  ALT_USB_DEV_DOEPINT15_t doepint15; /* ALT_USB_DEV_DOEPINT15 */
137939  volatile uint32_t _pad_0x4ec_0x4ef; /* *UNDEFINED* */
137940  ALT_USB_DEV_DOEPTSIZ15_t doeptsiz15; /* ALT_USB_DEV_DOEPTSIZ15 */
137941  ALT_USB_DEV_DOEPDMA15_t doepdma15; /* ALT_USB_DEV_DOEPDMA15 */
137942  volatile uint32_t _pad_0x4f8_0x4fb; /* *UNDEFINED* */
137943  ALT_USB_DEV_DOEPDMAB15_t doepdmab15; /* ALT_USB_DEV_DOEPDMAB15 */
137944 };
137945 
137946 /* The typedef declaration for register group ALT_USB_DEV. */
137947 typedef volatile struct ALT_USB_DEV_s ALT_USB_DEV_t;
137948 /* The struct declaration for the raw register contents of register group ALT_USB_DEV. */
137949 struct ALT_USB_DEV_raw_s
137950 {
137951  volatile uint32_t dcfg; /* ALT_USB_DEV_DCFG */
137952  volatile uint32_t dctl; /* ALT_USB_DEV_DCTL */
137953  volatile uint32_t dsts; /* ALT_USB_DEV_DSTS */
137954  uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
137955  volatile uint32_t diepmsk; /* ALT_USB_DEV_DIEPMSK */
137956  volatile uint32_t doepmsk; /* ALT_USB_DEV_DOEPMSK */
137957  volatile uint32_t daint; /* ALT_USB_DEV_DAINT */
137958  volatile uint32_t daintmsk; /* ALT_USB_DEV_DAINTMSK */
137959  uint32_t _pad_0x20_0x27[2]; /* *UNDEFINED* */
137960  volatile uint32_t dvbusdis; /* ALT_USB_DEV_DVBUSDIS */
137961  volatile uint32_t dvbuspulse; /* ALT_USB_DEV_DVBUSPULSE */
137962  volatile uint32_t dthrctl; /* ALT_USB_DEV_DTHRCTL */
137963  volatile uint32_t diepempmsk; /* ALT_USB_DEV_DIEPEMPMSK */
137964  uint32_t _pad_0x38_0xff[50]; /* *UNDEFINED* */
137965  volatile uint32_t diepctl0; /* ALT_USB_DEV_DIEPCTL0 */
137966  uint32_t _pad_0x104_0x107; /* *UNDEFINED* */
137967  volatile uint32_t diepint0; /* ALT_USB_DEV_DIEPINT0 */
137968  uint32_t _pad_0x10c_0x10f; /* *UNDEFINED* */
137969  volatile uint32_t dieptsiz0; /* ALT_USB_DEV_DIEPTSIZ0 */
137970  volatile uint32_t diepdma0; /* ALT_USB_DEV_DIEPDMA0 */
137971  volatile uint32_t dtxfsts0; /* ALT_USB_DEV_DTXFSTS0 */
137972  volatile uint32_t diepdmab0; /* ALT_USB_DEV_DIEPDMAB0 */
137973  volatile uint32_t diepctl1; /* ALT_USB_DEV_DIEPCTL1 */
137974  uint32_t _pad_0x124_0x127; /* *UNDEFINED* */
137975  volatile uint32_t diepint1; /* ALT_USB_DEV_DIEPINT1 */
137976  uint32_t _pad_0x12c_0x12f; /* *UNDEFINED* */
137977  volatile uint32_t dieptsiz1; /* ALT_USB_DEV_DIEPTSIZ1 */
137978  volatile uint32_t diepdma1; /* ALT_USB_DEV_DIEPDMA1 */
137979  volatile uint32_t dtxfsts1; /* ALT_USB_DEV_DTXFSTS1 */
137980  volatile uint32_t diepdmab1; /* ALT_USB_DEV_DIEPDMAB1 */
137981  volatile uint32_t diepctl2; /* ALT_USB_DEV_DIEPCTL2 */
137982  uint32_t _pad_0x144_0x147; /* *UNDEFINED* */
137983  volatile uint32_t diepint2; /* ALT_USB_DEV_DIEPINT2 */
137984  uint32_t _pad_0x14c_0x14f; /* *UNDEFINED* */
137985  volatile uint32_t dieptsiz2; /* ALT_USB_DEV_DIEPTSIZ2 */
137986  volatile uint32_t diepdma2; /* ALT_USB_DEV_DIEPDMA2 */
137987  volatile uint32_t dtxfsts2; /* ALT_USB_DEV_DTXFSTS2 */
137988  volatile uint32_t diepdmab2; /* ALT_USB_DEV_DIEPDMAB2 */
137989  volatile uint32_t diepctl3; /* ALT_USB_DEV_DIEPCTL3 */
137990  uint32_t _pad_0x164_0x167; /* *UNDEFINED* */
137991  volatile uint32_t diepint3; /* ALT_USB_DEV_DIEPINT3 */
137992  uint32_t _pad_0x16c_0x16f; /* *UNDEFINED* */
137993  volatile uint32_t dieptsiz3; /* ALT_USB_DEV_DIEPTSIZ3 */
137994  volatile uint32_t diepdma3; /* ALT_USB_DEV_DIEPDMA3 */
137995  volatile uint32_t dtxfsts3; /* ALT_USB_DEV_DTXFSTS3 */
137996  volatile uint32_t diepdmab3; /* ALT_USB_DEV_DIEPDMAB3 */
137997  volatile uint32_t diepctl4; /* ALT_USB_DEV_DIEPCTL4 */
137998  uint32_t _pad_0x184_0x187; /* *UNDEFINED* */
137999  volatile uint32_t diepint4; /* ALT_USB_DEV_DIEPINT4 */
138000  uint32_t _pad_0x18c_0x18f; /* *UNDEFINED* */
138001  volatile uint32_t dieptsiz4; /* ALT_USB_DEV_DIEPTSIZ4 */
138002  volatile uint32_t diepdma4; /* ALT_USB_DEV_DIEPDMA4 */
138003  volatile uint32_t dtxfsts4; /* ALT_USB_DEV_DTXFSTS4 */
138004  volatile uint32_t diepdmab4; /* ALT_USB_DEV_DIEPDMAB4 */
138005  volatile uint32_t diepctl5; /* ALT_USB_DEV_DIEPCTL5 */
138006  uint32_t _pad_0x1a4_0x1a7; /* *UNDEFINED* */
138007  volatile uint32_t diepint5; /* ALT_USB_DEV_DIEPINT5 */
138008  uint32_t _pad_0x1ac_0x1af; /* *UNDEFINED* */
138009  volatile uint32_t dieptsiz5; /* ALT_USB_DEV_DIEPTSIZ5 */
138010  volatile uint32_t diepdma5; /* ALT_USB_DEV_DIEPDMA5 */
138011  volatile uint32_t dtxfsts5; /* ALT_USB_DEV_DTXFSTS5 */
138012  volatile uint32_t diepdmab5; /* ALT_USB_DEV_DIEPDMAB5 */
138013  volatile uint32_t diepctl6; /* ALT_USB_DEV_DIEPCTL6 */
138014  uint32_t _pad_0x1c4_0x1c7; /* *UNDEFINED* */
138015  volatile uint32_t diepint6; /* ALT_USB_DEV_DIEPINT6 */
138016  uint32_t _pad_0x1cc_0x1cf; /* *UNDEFINED* */
138017  volatile uint32_t dieptsiz6; /* ALT_USB_DEV_DIEPTSIZ6 */
138018  volatile uint32_t diepdma6; /* ALT_USB_DEV_DIEPDMA6 */
138019  volatile uint32_t dtxfsts6; /* ALT_USB_DEV_DTXFSTS6 */
138020  volatile uint32_t diepdmab6; /* ALT_USB_DEV_DIEPDMAB6 */
138021  volatile uint32_t diepctl7; /* ALT_USB_DEV_DIEPCTL7 */
138022  uint32_t _pad_0x1e4_0x1e7; /* *UNDEFINED* */
138023  volatile uint32_t diepint7; /* ALT_USB_DEV_DIEPINT7 */
138024  uint32_t _pad_0x1ec_0x1ef; /* *UNDEFINED* */
138025  volatile uint32_t dieptsiz7; /* ALT_USB_DEV_DIEPTSIZ7 */
138026  volatile uint32_t diepdma7; /* ALT_USB_DEV_DIEPDMA7 */
138027  volatile uint32_t dtxfsts7; /* ALT_USB_DEV_DTXFSTS7 */
138028  volatile uint32_t diepdmab7; /* ALT_USB_DEV_DIEPDMAB7 */
138029  volatile uint32_t diepctl8; /* ALT_USB_DEV_DIEPCTL8 */
138030  uint32_t _pad_0x204_0x207; /* *UNDEFINED* */
138031  volatile uint32_t diepint8; /* ALT_USB_DEV_DIEPINT8 */
138032  uint32_t _pad_0x20c_0x20f; /* *UNDEFINED* */
138033  volatile uint32_t dieptsiz8; /* ALT_USB_DEV_DIEPTSIZ8 */
138034  volatile uint32_t diepdma8; /* ALT_USB_DEV_DIEPDMA8 */
138035  volatile uint32_t dtxfsts8; /* ALT_USB_DEV_DTXFSTS8 */
138036  volatile uint32_t diepdmab8; /* ALT_USB_DEV_DIEPDMAB8 */
138037  volatile uint32_t diepctl9; /* ALT_USB_DEV_DIEPCTL9 */
138038  uint32_t _pad_0x224_0x227; /* *UNDEFINED* */
138039  volatile uint32_t diepint9; /* ALT_USB_DEV_DIEPINT9 */
138040  uint32_t _pad_0x22c_0x22f; /* *UNDEFINED* */
138041  volatile uint32_t dieptsiz9; /* ALT_USB_DEV_DIEPTSIZ9 */
138042  volatile uint32_t diepdma9; /* ALT_USB_DEV_DIEPDMA9 */
138043  volatile uint32_t dtxfsts9; /* ALT_USB_DEV_DTXFSTS9 */
138044  volatile uint32_t diepdmab9; /* ALT_USB_DEV_DIEPDMAB9 */
138045  volatile uint32_t diepctl10; /* ALT_USB_DEV_DIEPCTL10 */
138046  uint32_t _pad_0x244_0x247; /* *UNDEFINED* */
138047  volatile uint32_t diepint10; /* ALT_USB_DEV_DIEPINT10 */
138048  uint32_t _pad_0x24c_0x24f; /* *UNDEFINED* */
138049  volatile uint32_t dieptsiz10; /* ALT_USB_DEV_DIEPTSIZ10 */
138050  volatile uint32_t diepdma10; /* ALT_USB_DEV_DIEPDMA10 */
138051  volatile uint32_t dtxfsts10; /* ALT_USB_DEV_DTXFSTS10 */
138052  volatile uint32_t diepdmab10; /* ALT_USB_DEV_DIEPDMAB10 */
138053  volatile uint32_t diepctl11; /* ALT_USB_DEV_DIEPCTL11 */
138054  uint32_t _pad_0x264_0x267; /* *UNDEFINED* */
138055  volatile uint32_t diepint11; /* ALT_USB_DEV_DIEPINT11 */
138056  uint32_t _pad_0x26c_0x26f; /* *UNDEFINED* */
138057  volatile uint32_t dieptsiz11; /* ALT_USB_DEV_DIEPTSIZ11 */
138058  volatile uint32_t diepdma11; /* ALT_USB_DEV_DIEPDMA11 */
138059  volatile uint32_t dtxfsts11; /* ALT_USB_DEV_DTXFSTS11 */
138060  volatile uint32_t diepdmab11; /* ALT_USB_DEV_DIEPDMAB11 */
138061  volatile uint32_t diepctl12; /* ALT_USB_DEV_DIEPCTL12 */
138062  uint32_t _pad_0x284_0x287; /* *UNDEFINED* */
138063  volatile uint32_t diepint12; /* ALT_USB_DEV_DIEPINT12 */
138064  uint32_t _pad_0x28c_0x28f; /* *UNDEFINED* */
138065  volatile uint32_t dieptsiz12; /* ALT_USB_DEV_DIEPTSIZ12 */
138066  volatile uint32_t diepdma12; /* ALT_USB_DEV_DIEPDMA12 */
138067  volatile uint32_t dtxfsts12; /* ALT_USB_DEV_DTXFSTS12 */
138068  volatile uint32_t diepdmab12; /* ALT_USB_DEV_DIEPDMAB12 */
138069  volatile uint32_t diepctl13; /* ALT_USB_DEV_DIEPCTL13 */
138070  uint32_t _pad_0x2a4_0x2a7; /* *UNDEFINED* */
138071  volatile uint32_t diepint13; /* ALT_USB_DEV_DIEPINT13 */
138072  uint32_t _pad_0x2ac_0x2af; /* *UNDEFINED* */
138073  volatile uint32_t dieptsiz13; /* ALT_USB_DEV_DIEPTSIZ13 */
138074  volatile uint32_t diepdma13; /* ALT_USB_DEV_DIEPDMA13 */
138075  volatile uint32_t dtxfsts13; /* ALT_USB_DEV_DTXFSTS13 */
138076  volatile uint32_t diepdmab13; /* ALT_USB_DEV_DIEPDMAB13 */
138077  volatile uint32_t diepctl14; /* ALT_USB_DEV_DIEPCTL14 */
138078  uint32_t _pad_0x2c4_0x2c7; /* *UNDEFINED* */
138079  volatile uint32_t diepint14; /* ALT_USB_DEV_DIEPINT14 */
138080  uint32_t _pad_0x2cc_0x2cf; /* *UNDEFINED* */
138081  volatile uint32_t dieptsiz14; /* ALT_USB_DEV_DIEPTSIZ14 */
138082  volatile uint32_t diepdma14; /* ALT_USB_DEV_DIEPDMA14 */
138083  volatile uint32_t dtxfsts14; /* ALT_USB_DEV_DTXFSTS14 */
138084  volatile uint32_t diepdmab14; /* ALT_USB_DEV_DIEPDMAB14 */
138085  volatile uint32_t diepctl15; /* ALT_USB_DEV_DIEPCTL15 */
138086  uint32_t _pad_0x2e4_0x2e7; /* *UNDEFINED* */
138087  volatile uint32_t diepint15; /* ALT_USB_DEV_DIEPINT15 */
138088  uint32_t _pad_0x2ec_0x2ef; /* *UNDEFINED* */
138089  volatile uint32_t dieptsiz15; /* ALT_USB_DEV_DIEPTSIZ15 */
138090  volatile uint32_t diepdma15; /* ALT_USB_DEV_DIEPDMA15 */
138091  volatile uint32_t dtxfsts15; /* ALT_USB_DEV_DTXFSTS15 */
138092  volatile uint32_t diepdmab15; /* ALT_USB_DEV_DIEPDMAB15 */
138093  volatile uint32_t doepctl0; /* ALT_USB_DEV_DOEPCTL0 */
138094  uint32_t _pad_0x304_0x307; /* *UNDEFINED* */
138095  volatile uint32_t doepint0; /* ALT_USB_DEV_DOEPINT0 */
138096  uint32_t _pad_0x30c_0x30f; /* *UNDEFINED* */
138097  volatile uint32_t doeptsiz0; /* ALT_USB_DEV_DOEPTSIZ0 */
138098  volatile uint32_t doepdma0; /* ALT_USB_DEV_DOEPDMA0 */
138099  uint32_t _pad_0x318_0x31b; /* *UNDEFINED* */
138100  volatile uint32_t doepdmab0; /* ALT_USB_DEV_DOEPDMAB0 */
138101  volatile uint32_t doepctl1; /* ALT_USB_DEV_DOEPCTL1 */
138102  uint32_t _pad_0x324_0x327; /* *UNDEFINED* */
138103  volatile uint32_t doepint1; /* ALT_USB_DEV_DOEPINT1 */
138104  uint32_t _pad_0x32c_0x32f; /* *UNDEFINED* */
138105  volatile uint32_t doeptsiz1; /* ALT_USB_DEV_DOEPTSIZ1 */
138106  volatile uint32_t doepdma1; /* ALT_USB_DEV_DOEPDMA1 */
138107  uint32_t _pad_0x338_0x33b; /* *UNDEFINED* */
138108  volatile uint32_t doepdmab1; /* ALT_USB_DEV_DOEPDMAB1 */
138109  volatile uint32_t doepctl2; /* ALT_USB_DEV_DOEPCTL2 */
138110  uint32_t _pad_0x344_0x347; /* *UNDEFINED* */
138111  volatile uint32_t doepint2; /* ALT_USB_DEV_DOEPINT2 */
138112  uint32_t _pad_0x34c_0x34f; /* *UNDEFINED* */
138113  volatile uint32_t doeptsiz2; /* ALT_USB_DEV_DOEPTSIZ2 */
138114  volatile uint32_t doepdma2; /* ALT_USB_DEV_DOEPDMA2 */
138115  uint32_t _pad_0x358_0x35b; /* *UNDEFINED* */
138116  volatile uint32_t doepdmab2; /* ALT_USB_DEV_DOEPDMAB2 */
138117  volatile uint32_t doepctl3; /* ALT_USB_DEV_DOEPCTL3 */
138118  uint32_t _pad_0x364_0x367; /* *UNDEFINED* */
138119  volatile uint32_t doepint3; /* ALT_USB_DEV_DOEPINT3 */
138120  uint32_t _pad_0x36c_0x36f; /* *UNDEFINED* */
138121  volatile uint32_t doeptsiz3; /* ALT_USB_DEV_DOEPTSIZ3 */
138122  volatile uint32_t doepdma3; /* ALT_USB_DEV_DOEPDMA3 */
138123  uint32_t _pad_0x378_0x37b; /* *UNDEFINED* */
138124  volatile uint32_t doepdmab3; /* ALT_USB_DEV_DOEPDMAB3 */
138125  volatile uint32_t doepctl4; /* ALT_USB_DEV_DOEPCTL4 */
138126  uint32_t _pad_0x384_0x387; /* *UNDEFINED* */
138127  volatile uint32_t doepint4; /* ALT_USB_DEV_DOEPINT4 */
138128  uint32_t _pad_0x38c_0x38f; /* *UNDEFINED* */
138129  volatile uint32_t doeptsiz4; /* ALT_USB_DEV_DOEPTSIZ4 */
138130  volatile uint32_t doepdma4; /* ALT_USB_DEV_DOEPDMA4 */
138131  uint32_t _pad_0x398_0x39b; /* *UNDEFINED* */
138132  volatile uint32_t doepdmab4; /* ALT_USB_DEV_DOEPDMAB4 */
138133  volatile uint32_t doepctl5; /* ALT_USB_DEV_DOEPCTL5 */
138134  uint32_t _pad_0x3a4_0x3a7; /* *UNDEFINED* */
138135  volatile uint32_t doepint5; /* ALT_USB_DEV_DOEPINT5 */
138136  uint32_t _pad_0x3ac_0x3af; /* *UNDEFINED* */
138137  volatile uint32_t doeptsiz5; /* ALT_USB_DEV_DOEPTSIZ5 */
138138  volatile uint32_t doepdma5; /* ALT_USB_DEV_DOEPDMA5 */
138139  uint32_t _pad_0x3b8_0x3bb; /* *UNDEFINED* */
138140  volatile uint32_t doepdmab5; /* ALT_USB_DEV_DOEPDMAB5 */
138141  volatile uint32_t doepctl6; /* ALT_USB_DEV_DOEPCTL6 */
138142  uint32_t _pad_0x3c4_0x3c7; /* *UNDEFINED* */
138143  volatile uint32_t doepint6; /* ALT_USB_DEV_DOEPINT6 */
138144  uint32_t _pad_0x3cc_0x3cf; /* *UNDEFINED* */
138145  volatile uint32_t doeptsiz6; /* ALT_USB_DEV_DOEPTSIZ6 */
138146  volatile uint32_t doepdma6; /* ALT_USB_DEV_DOEPDMA6 */
138147  uint32_t _pad_0x3d8_0x3db; /* *UNDEFINED* */
138148  volatile uint32_t doepdmab6; /* ALT_USB_DEV_DOEPDMAB6 */
138149  volatile uint32_t doepctl7; /* ALT_USB_DEV_DOEPCTL7 */
138150  uint32_t _pad_0x3e4_0x3e7; /* *UNDEFINED* */
138151  volatile uint32_t doepint7; /* ALT_USB_DEV_DOEPINT7 */
138152  uint32_t _pad_0x3ec_0x3ef; /* *UNDEFINED* */
138153  volatile uint32_t doeptsiz7; /* ALT_USB_DEV_DOEPTSIZ7 */
138154  volatile uint32_t doepdma7; /* ALT_USB_DEV_DOEPDMA7 */
138155  uint32_t _pad_0x3f8_0x3fb; /* *UNDEFINED* */
138156  volatile uint32_t doepdmab7; /* ALT_USB_DEV_DOEPDMAB7 */
138157  volatile uint32_t doepctl8; /* ALT_USB_DEV_DOEPCTL8 */
138158  uint32_t _pad_0x404_0x407; /* *UNDEFINED* */
138159  volatile uint32_t doepint8; /* ALT_USB_DEV_DOEPINT8 */
138160  uint32_t _pad_0x40c_0x40f; /* *UNDEFINED* */
138161  volatile uint32_t doeptsiz8; /* ALT_USB_DEV_DOEPTSIZ8 */
138162  volatile uint32_t doepdma8; /* ALT_USB_DEV_DOEPDMA8 */
138163  uint32_t _pad_0x418_0x41b; /* *UNDEFINED* */
138164  volatile uint32_t doepdmab8; /* ALT_USB_DEV_DOEPDMAB8 */
138165  volatile uint32_t doepctl9; /* ALT_USB_DEV_DOEPCTL9 */
138166  uint32_t _pad_0x424_0x427; /* *UNDEFINED* */
138167  volatile uint32_t doepint9; /* ALT_USB_DEV_DOEPINT9 */
138168  uint32_t _pad_0x42c_0x42f; /* *UNDEFINED* */
138169  volatile uint32_t doeptsiz9; /* ALT_USB_DEV_DOEPTSIZ9 */
138170  volatile uint32_t doepdma9; /* ALT_USB_DEV_DOEPDMA9 */
138171  uint32_t _pad_0x438_0x43b; /* *UNDEFINED* */
138172  volatile uint32_t doepdmab9; /* ALT_USB_DEV_DOEPDMAB9 */
138173  volatile uint32_t doepctl10; /* ALT_USB_DEV_DOEPCTL10 */
138174  uint32_t _pad_0x444_0x447; /* *UNDEFINED* */
138175  volatile uint32_t doepint10; /* ALT_USB_DEV_DOEPINT10 */
138176  uint32_t _pad_0x44c_0x44f; /* *UNDEFINED* */
138177  volatile uint32_t doeptsiz10; /* ALT_USB_DEV_DOEPTSIZ10 */
138178  volatile uint32_t doepdma10; /* ALT_USB_DEV_DOEPDMA10 */
138179  uint32_t _pad_0x458_0x45b; /* *UNDEFINED* */
138180  volatile uint32_t doepdmab10; /* ALT_USB_DEV_DOEPDMAB10 */
138181  volatile uint32_t doepctl11; /* ALT_USB_DEV_DOEPCTL11 */
138182  uint32_t _pad_0x464_0x467; /* *UNDEFINED* */
138183  volatile uint32_t doepint11; /* ALT_USB_DEV_DOEPINT11 */
138184  uint32_t _pad_0x46c_0x46f; /* *UNDEFINED* */
138185  volatile uint32_t doeptsiz11; /* ALT_USB_DEV_DOEPTSIZ11 */
138186  volatile uint32_t doepdma11; /* ALT_USB_DEV_DOEPDMA11 */
138187  uint32_t _pad_0x478_0x47b; /* *UNDEFINED* */
138188  volatile uint32_t doepdmab11; /* ALT_USB_DEV_DOEPDMAB11 */
138189  volatile uint32_t doepctl12; /* ALT_USB_DEV_DOEPCTL12 */
138190  uint32_t _pad_0x484_0x487; /* *UNDEFINED* */
138191  volatile uint32_t doepint12; /* ALT_USB_DEV_DOEPINT12 */
138192  uint32_t _pad_0x48c_0x48f; /* *UNDEFINED* */
138193  volatile uint32_t doeptsiz12; /* ALT_USB_DEV_DOEPTSIZ12 */
138194  volatile uint32_t doepdma12; /* ALT_USB_DEV_DOEPDMA12 */
138195  uint32_t _pad_0x498_0x49b; /* *UNDEFINED* */
138196  volatile uint32_t doepdmab12; /* ALT_USB_DEV_DOEPDMAB12 */
138197  volatile uint32_t doepctl13; /* ALT_USB_DEV_DOEPCTL13 */
138198  uint32_t _pad_0x4a4_0x4a7; /* *UNDEFINED* */
138199  volatile uint32_t doepint13; /* ALT_USB_DEV_DOEPINT13 */
138200  uint32_t _pad_0x4ac_0x4af; /* *UNDEFINED* */
138201  volatile uint32_t doeptsiz13; /* ALT_USB_DEV_DOEPTSIZ13 */
138202  volatile uint32_t doepdma13; /* ALT_USB_DEV_DOEPDMA13 */
138203  uint32_t _pad_0x4b8_0x4bb; /* *UNDEFINED* */
138204  volatile uint32_t doepdmab13; /* ALT_USB_DEV_DOEPDMAB13 */
138205  volatile uint32_t doepctl14; /* ALT_USB_DEV_DOEPCTL14 */
138206  uint32_t _pad_0x4c4_0x4c7; /* *UNDEFINED* */
138207  volatile uint32_t doepint14; /* ALT_USB_DEV_DOEPINT14 */
138208  uint32_t _pad_0x4cc_0x4cf; /* *UNDEFINED* */
138209  volatile uint32_t doeptsiz14; /* ALT_USB_DEV_DOEPTSIZ14 */
138210  volatile uint32_t doepdma14; /* ALT_USB_DEV_DOEPDMA14 */
138211  uint32_t _pad_0x4d8_0x4db; /* *UNDEFINED* */
138212  volatile uint32_t doepdmab14; /* ALT_USB_DEV_DOEPDMAB14 */
138213  volatile uint32_t doepctl15; /* ALT_USB_DEV_DOEPCTL15 */
138214  uint32_t _pad_0x4e4_0x4e7; /* *UNDEFINED* */
138215  volatile uint32_t doepint15; /* ALT_USB_DEV_DOEPINT15 */
138216  uint32_t _pad_0x4ec_0x4ef; /* *UNDEFINED* */
138217  volatile uint32_t doeptsiz15; /* ALT_USB_DEV_DOEPTSIZ15 */
138218  volatile uint32_t doepdma15; /* ALT_USB_DEV_DOEPDMA15 */
138219  uint32_t _pad_0x4f8_0x4fb; /* *UNDEFINED* */
138220  volatile uint32_t doepdmab15; /* ALT_USB_DEV_DOEPDMAB15 */
138221 };
138222 
138223 /* The typedef declaration for the raw register contents of register group ALT_USB_DEV. */
138224 typedef volatile struct ALT_USB_DEV_raw_s ALT_USB_DEV_raw_t;
138225 #endif /* __ASSEMBLY__ */
138226 
138227 
138228 /*
138229  * Component : ALT_USB_PWRCLK
138230  *
138231  */
138232 /*
138233  * Register : pcgcctl
138234  *
138235  * Power and Clock Gating Control Register
138236  *
138237  * Register Layout
138238  *
138239  * Bits | Access | Reset | Description
138240  * :-------|:-------|:------|:-------------------------------------
138241  * [0] | RW | 0x0 | ALT_USB_PWRCLK_PCGCCTL_STOPPCLK
138242  * [2:1] | ??? | 0x0 | *UNDEFINED*
138243  * [3] | RW | 0x0 | ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE
138244  * [5:4] | ??? | 0x0 | *UNDEFINED*
138245  * [6] | R | 0x0 | ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP
138246  * [7] | R | 0x0 | ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED
138247  * [31:8] | ??? | 0x0 | *UNDEFINED*
138248  *
138249  */
138250 /*
138251  * Field : stoppclk
138252  *
138253  * Stop Pclk (StopPclk)
138254  *
138255  * The application sets this bit to stop the PHY clock (phy_clk)
138256  *
138257  * when the USB is suspended, the session is not valid, or the
138258  *
138259  * device is disconnected. The application clears this bit when the
138260  *
138261  * USB is resumed or a new session starts.
138262  *
138263  * Field Enumeration Values:
138264  *
138265  * Enum | Value | Description
138266  * :---------------------------------------|:------|:------------------
138267  * ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_DISD | 0x0 | Disable Stop Pclk
138268  * ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_END | 0x1 | Enable Stop Pclk
138269  *
138270  * Field Access Macros:
138271  *
138272  */
138273 /*
138274  * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_STOPPCLK
138275  *
138276  * Disable Stop Pclk
138277  */
138278 #define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_DISD 0x0
138279 /*
138280  * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_STOPPCLK
138281  *
138282  * Enable Stop Pclk
138283  */
138284 #define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_END 0x1
138285 
138286 /* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */
138287 #define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_LSB 0
138288 /* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */
138289 #define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_MSB 0
138290 /* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */
138291 #define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_WIDTH 1
138292 /* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value. */
138293 #define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_SET_MSK 0x00000001
138294 /* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value. */
138295 #define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_CLR_MSK 0xfffffffe
138296 /* The reset value of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */
138297 #define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_RESET 0x0
138298 /* Extracts the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK field value from a register. */
138299 #define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_GET(value) (((value) & 0x00000001) >> 0)
138300 /* Produces a ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value suitable for setting the register. */
138301 #define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_SET(value) (((value) << 0) & 0x00000001)
138302 
138303 /*
138304  * Field : rstpdwnmodule
138305  *
138306  * Reset Power-Down Modules (RstPdwnModule)
138307  *
138308  * This bit is valid only in Partial Power-Down mode. The
138309  *
138310  * application sets this bit when the power is turned off. The
138311  *
138312  * application clears this bit after the power is turned on and the
138313  *
138314  * PHY clock is up.Note: The R/W of all core registers are possible only when this
138315  * bit is
138316  *
138317  * set to 1b0.
138318  *
138319  * Field Enumeration Values:
138320  *
138321  * Enum | Value | Description
138322  * :-------------------------------------------|:------|:--------------------
138323  * ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_ON | 0x0 | Power is turned on
138324  * ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_OFF | 0x1 | Power is turned off
138325  *
138326  * Field Access Macros:
138327  *
138328  */
138329 /*
138330  * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE
138331  *
138332  * Power is turned on
138333  */
138334 #define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_ON 0x0
138335 /*
138336  * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE
138337  *
138338  * Power is turned off
138339  */
138340 #define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_OFF 0x1
138341 
138342 /* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */
138343 #define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_LSB 3
138344 /* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */
138345 #define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_MSB 3
138346 /* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */
138347 #define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_WIDTH 1
138348 /* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value. */
138349 #define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_SET_MSK 0x00000008
138350 /* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value. */
138351 #define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_CLR_MSK 0xfffffff7
138352 /* The reset value of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */
138353 #define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_RESET 0x0
138354 /* Extracts the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE field value from a register. */
138355 #define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_GET(value) (((value) & 0x00000008) >> 3)
138356 /* Produces a ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value suitable for setting the register. */
138357 #define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_SET(value) (((value) << 3) & 0x00000008)
138358 
138359 /*
138360  * Field : physleep
138361  *
138362  * PHY In Sleep
138363  *
138364  * Indicates that the PHY is in Sleep State.
138365  *
138366  * Field Enumeration Values:
138367  *
138368  * Enum | Value | Description
138369  * :----------------------------------------|:------|:----------------
138370  * ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_INACT | 0x0 | Phy non-sleep
138371  * ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_ACT | 0x1 | Phy sleep state
138372  *
138373  * Field Access Macros:
138374  *
138375  */
138376 /*
138377  * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP
138378  *
138379  * Phy non-sleep
138380  */
138381 #define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_INACT 0x0
138382 /*
138383  * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP
138384  *
138385  * Phy sleep state
138386  */
138387 #define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_ACT 0x1
138388 
138389 /* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */
138390 #define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_LSB 6
138391 /* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */
138392 #define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_MSB 6
138393 /* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */
138394 #define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_WIDTH 1
138395 /* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value. */
138396 #define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_SET_MSK 0x00000040
138397 /* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value. */
138398 #define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_CLR_MSK 0xffffffbf
138399 /* The reset value of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */
138400 #define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_RESET 0x0
138401 /* Extracts the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP field value from a register. */
138402 #define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_GET(value) (((value) & 0x00000040) >> 6)
138403 /* Produces a ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value suitable for setting the register. */
138404 #define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_SET(value) (((value) << 6) & 0x00000040)
138405 
138406 /*
138407  * Field : l1suspended
138408  *
138409  * L1 Deep Sleep
138410  *
138411  * Indicates that the PHY is in deep sleep when in L1 state.
138412  *
138413  * Field Enumeration Values:
138414  *
138415  * Enum | Value | Description
138416  * :-------------------------------------------|:------|:------------------
138417  * ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_INACT | 0x0 | Non Deep Sleep
138418  * ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_ACT | 0x1 | Deep Sleep active
138419  *
138420  * Field Access Macros:
138421  *
138422  */
138423 /*
138424  * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED
138425  *
138426  * Non Deep Sleep
138427  */
138428 #define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_INACT 0x0
138429 /*
138430  * Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED
138431  *
138432  * Deep Sleep active
138433  */
138434 #define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_ACT 0x1
138435 
138436 /* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */
138437 #define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_LSB 7
138438 /* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */
138439 #define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_MSB 7
138440 /* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */
138441 #define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_WIDTH 1
138442 /* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value. */
138443 #define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_SET_MSK 0x00000080
138444 /* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value. */
138445 #define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_CLR_MSK 0xffffff7f
138446 /* The reset value of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */
138447 #define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_RESET 0x0
138448 /* Extracts the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED field value from a register. */
138449 #define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_GET(value) (((value) & 0x00000080) >> 7)
138450 /* Produces a ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value suitable for setting the register. */
138451 #define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_SET(value) (((value) << 7) & 0x00000080)
138452 
138453 #ifndef __ASSEMBLY__
138454 /*
138455  * WARNING: The C register and register group struct declarations are provided for
138456  * convenience and illustrative purposes. They should, however, be used with
138457  * caution as the C language standard provides no guarantees about the alignment or
138458  * atomicity of device memory accesses. The recommended practice for writing
138459  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
138460  * alt_write_word() functions.
138461  *
138462  * The struct declaration for register ALT_USB_PWRCLK_PCGCCTL.
138463  */
138464 struct ALT_USB_PWRCLK_PCGCCTL_s
138465 {
138466  uint32_t stoppclk : 1; /* ALT_USB_PWRCLK_PCGCCTL_STOPPCLK */
138467  uint32_t : 2; /* *UNDEFINED* */
138468  uint32_t rstpdwnmodule : 1; /* ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE */
138469  uint32_t : 2; /* *UNDEFINED* */
138470  const uint32_t physleep : 1; /* ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP */
138471  const uint32_t l1suspended : 1; /* ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED */
138472  uint32_t : 24; /* *UNDEFINED* */
138473 };
138474 
138475 /* The typedef declaration for register ALT_USB_PWRCLK_PCGCCTL. */
138476 typedef volatile struct ALT_USB_PWRCLK_PCGCCTL_s ALT_USB_PWRCLK_PCGCCTL_t;
138477 #endif /* __ASSEMBLY__ */
138478 
138479 /* The reset value of the ALT_USB_PWRCLK_PCGCCTL register. */
138480 #define ALT_USB_PWRCLK_PCGCCTL_RESET 0x00000000
138481 /* The byte offset of the ALT_USB_PWRCLK_PCGCCTL register from the beginning of the component. */
138482 #define ALT_USB_PWRCLK_PCGCCTL_OFST 0x0
138483 /* The address of the ALT_USB_PWRCLK_PCGCCTL register. */
138484 #define ALT_USB_PWRCLK_PCGCCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_PWRCLK_PCGCCTL_OFST))
138485 
138486 #ifndef __ASSEMBLY__
138487 /*
138488  * WARNING: The C register and register group struct declarations are provided for
138489  * convenience and illustrative purposes. They should, however, be used with
138490  * caution as the C language standard provides no guarantees about the alignment or
138491  * atomicity of device memory accesses. The recommended practice for writing
138492  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
138493  * alt_write_word() functions.
138494  *
138495  * The struct declaration for register group ALT_USB_PWRCLK.
138496  */
138497 struct ALT_USB_PWRCLK_s
138498 {
138499  ALT_USB_PWRCLK_PCGCCTL_t pcgcctl; /* ALT_USB_PWRCLK_PCGCCTL */
138500 };
138501 
138502 /* The typedef declaration for register group ALT_USB_PWRCLK. */
138503 typedef volatile struct ALT_USB_PWRCLK_s ALT_USB_PWRCLK_t;
138504 /* The struct declaration for the raw register contents of register group ALT_USB_PWRCLK. */
138505 struct ALT_USB_PWRCLK_raw_s
138506 {
138507  volatile uint32_t pcgcctl; /* ALT_USB_PWRCLK_PCGCCTL */
138508 };
138509 
138510 /* The typedef declaration for the raw register contents of register group ALT_USB_PWRCLK. */
138511 typedef volatile struct ALT_USB_PWRCLK_raw_s ALT_USB_PWRCLK_raw_t;
138512 #endif /* __ASSEMBLY__ */
138513 
138514 
138515 #ifdef __cplusplus
138516 }
138517 #endif /* __cplusplus */
138518 #endif /* __ALT_SOCAL_USB_H__ */
138519