35 #ifndef __ALT_SOCAL_MPFE_H__
36 #define __ALT_SOCAL_MPFE_H__
72 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_LSB 0
74 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_MSB 7
76 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_WIDTH 8
78 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
80 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
82 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_RESET 0x6
84 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
86 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
97 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_LSB 8
99 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_MSB 31
101 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_WIDTH 24
103 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
105 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
107 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_RESET 0x298113
109 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
111 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
125 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_s
127 const volatile uint32_t CORETYPEID : 8;
128 const volatile uint32_t CORECHECKSUM : 24;
132 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_t;
136 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_RESET 0x29811306
138 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_OFST 0x0
160 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_LSB 0
162 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_MSB 7
164 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_WIDTH 8
166 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_SET_MSK 0x000000ff
168 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
170 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_RESET 0x0
172 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
174 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
186 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_LSB 8
188 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_MSB 31
190 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_WIDTH 24
192 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
194 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
196 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_RESET 0x148
198 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
200 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
214 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_s
216 const volatile uint32_t USERID : 8;
217 const volatile uint32_t FLEXNOCID : 24;
221 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_t;
225 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_RESET 0x00014800
227 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_OFST 0x4
261 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_LSB 0
263 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_MSB 0
265 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_WIDTH 1
267 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_SET_MSK 0x00000001
269 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_CLR_MSK 0xfffffffe
271 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_RESET 0x0
273 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_GET(value) (((value) & 0x00000001) >> 0)
275 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ERREN_SET(value) (((value) << 0) & 0x00000001)
287 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_LSB 1
289 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_MSB 1
291 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_WIDTH 1
293 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_SET_MSK 0x00000002
295 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_CLR_MSK 0xfffffffd
297 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_RESET 0x0
299 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_GET(value) (((value) & 0x00000002) >> 1)
301 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_TRACEEN_SET(value) (((value) << 1) & 0x00000002)
313 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_LSB 2
315 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_MSB 2
317 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_WIDTH 1
319 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_SET_MSK 0x00000004
321 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_CLR_MSK 0xfffffffb
323 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_RESET 0x0
325 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_GET(value) (((value) & 0x00000004) >> 2)
327 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_PAYLOADEN_SET(value) (((value) << 2) & 0x00000004)
341 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_LSB 3
343 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_MSB 3
345 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_WIDTH 1
347 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_SET_MSK 0x00000008
349 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_CLR_MSK 0xfffffff7
351 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_RESET 0x0
353 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_GET(value) (((value) & 0x00000008) >> 3)
355 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATEN_SET(value) (((value) << 3) & 0x00000008)
368 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_LSB 4
370 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_MSB 4
372 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_WIDTH 1
374 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_SET_MSK 0x00000010
376 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_CLR_MSK 0xffffffef
378 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_RESET 0x0
380 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_GET(value) (((value) & 0x00000010) >> 4)
382 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_ALARMEN_SET(value) (((value) << 4) & 0x00000010)
397 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_LSB 5
399 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_MSB 5
401 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_WIDTH 1
403 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_SET_MSK 0x00000020
405 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_CLR_MSK 0xffffffdf
407 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_RESET 0x0
409 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_GET(value) (((value) & 0x00000020) >> 5)
411 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_STATCONDDUMP_SET(value) (((value) << 5) & 0x00000020)
424 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_LSB 6
426 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MSB 6
428 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_WIDTH 1
430 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SET_MSK 0x00000040
432 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_CLR_MSK 0xffffffbf
434 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_RESET 0x0
436 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_GET(value) (((value) & 0x00000040) >> 6)
438 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SET(value) (((value) << 6) & 0x00000040)
453 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_LSB 7
455 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MSB 7
457 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_WIDTH 1
459 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET_MSK 0x00000080
461 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_CLR_MSK 0xffffff7f
463 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_RESET 0x0
465 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_GET(value) (((value) & 0x00000080) >> 7)
467 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET(value) (((value) << 7) & 0x00000080)
481 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_s
483 volatile uint32_t ERREN : 1;
484 volatile uint32_t TRACEEN : 1;
485 volatile uint32_t PAYLOADEN : 1;
486 volatile uint32_t STATEN : 1;
487 volatile uint32_t ALARMEN : 1;
488 volatile uint32_t STATCONDDUMP : 1;
489 const volatile uint32_t INTRUSIVEMODE : 1;
490 volatile uint32_t FILTBYTEALWAYSCHAINABLEEN : 1;
495 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_t;
499 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_RESET 0x00000000
501 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_OFST 0x8
522 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_LSB 0
524 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_MSB 0
526 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_WIDTH 1
528 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_SET_MSK 0x00000001
530 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_CLR_MSK 0xfffffffe
532 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_RESET 0x0
534 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_GET(value) (((value) & 0x00000001) >> 0)
536 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_GLOBALEN_SET(value) (((value) << 0) & 0x00000001)
545 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_LSB 1
547 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_MSB 1
549 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_WIDTH 1
551 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_SET_MSK 0x00000002
553 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_CLR_MSK 0xfffffffd
555 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_RESET 0x0
557 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_GET(value) (((value) & 0x00000002) >> 1)
559 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_ACTIVE_SET(value) (((value) << 1) & 0x00000002)
573 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_s
575 volatile uint32_t GLOBALEN : 1;
576 const volatile uint32_t ACTIVE : 1;
581 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_t;
585 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_RESET 0x00000000
587 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_OFST 0xc
613 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_LSB 0
615 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_MSB 15
617 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_WIDTH 16
619 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_SET_MSK 0x0000ffff
621 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_CLR_MSK 0xffff0000
623 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_RESET 0x0
625 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_GET(value) (((value) & 0x0000ffff) >> 0)
627 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_FILTERLUT_SET(value) (((value) << 0) & 0x0000ffff)
641 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_s
643 volatile uint32_t FILTERLUT : 16;
648 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_t;
652 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_RESET 0x00000000
654 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_OFST 0x14
681 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_LSB 0
683 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_MSB 4
685 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_WIDTH 5
687 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_SET_MSK 0x0000001f
689 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_CLR_MSK 0xffffffe0
691 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_RESET 0x0
693 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_GET(value) (((value) & 0x0000001f) >> 0)
695 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_SET(value) (((value) << 0) & 0x0000001f)
709 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_s
711 volatile uint32_t TRACEALARMEN : 5;
716 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_t;
720 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_RESET 0x00000000
722 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_OFST 0x18
748 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_LSB 0
750 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_MSB 4
752 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_WIDTH 5
754 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_SET_MSK 0x0000001f
756 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_CLR_MSK 0xffffffe0
758 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_RESET 0x0
760 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_GET(value) (((value) & 0x0000001f) >> 0)
762 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_SET(value) (((value) << 0) & 0x0000001f)
776 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_s
778 const volatile uint32_t TRACEALARMSTATUS : 5;
783 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_t;
787 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_RESET 0x00000000
789 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_OFST 0x1c
814 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_LSB 0
816 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_MSB 4
818 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_WIDTH 5
820 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x0000001f
822 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xffffffe0
824 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0
826 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_GET(value) (((value) & 0x0000001f) >> 0)
828 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_SET(value) (((value) << 0) & 0x0000001f)
842 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_s
844 volatile uint32_t TRACEALARMCLR : 5;
849 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_t;
853 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_RESET 0x00000000
855 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_OFST 0x20
884 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_LSB 0
886 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_MSB 4
888 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_WIDTH 5
890 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_SET_MSK 0x0000001f
892 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_CLR_MSK 0xffffffe0
894 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_RESET 0x0
896 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
898 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_STATPERIOD_SET(value) (((value) << 0) & 0x0000001f)
912 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_s
914 volatile uint32_t STATPERIOD : 5;
919 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_t;
923 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_RESET 0x00000000
925 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_OFST 0x24
950 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_LSB 0
952 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_MSB 0
954 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_WIDTH 1
956 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_SET_MSK 0x00000001
958 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_CLR_MSK 0xfffffffe
960 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_RESET 0x0
962 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_GET(value) (((value) & 0x00000001) >> 0)
964 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_STATGO_SET(value) (((value) << 0) & 0x00000001)
978 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_s
980 volatile uint32_t STATGO : 1;
985 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_t;
989 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_RESET 0x00000000
991 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_OFST 0x28
1015 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_LSB 0
1017 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_MSB 31
1019 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_WIDTH 32
1021 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_SET_MSK 0xffffffff
1023 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_CLR_MSK 0x00000000
1025 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_RESET 0x0
1027 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_GET(value) (((value) & 0xffffffff) >> 0)
1029 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_STATALARMMIN_SET(value) (((value) << 0) & 0xffffffff)
1031 #ifndef __ASSEMBLY__
1043 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_s
1045 volatile uint32_t STATALARMMIN : 32;
1049 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_t;
1053 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_RESET 0x00000000
1055 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_OFST 0x2c
1079 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_LSB 0
1081 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_MSB 31
1083 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_WIDTH 32
1085 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_SET_MSK 0xffffffff
1087 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_CLR_MSK 0x00000000
1089 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_RESET 0x0
1091 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_GET(value) (((value) & 0xffffffff) >> 0)
1093 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_STATALARMMAX_SET(value) (((value) << 0) & 0xffffffff)
1095 #ifndef __ASSEMBLY__
1107 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_s
1109 volatile uint32_t STATALARMMAX : 32;
1113 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_t;
1117 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_RESET 0x00000000
1119 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_OFST 0x30
1145 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_LSB 0
1147 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_MSB 0
1149 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_WIDTH 1
1151 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_SET_MSK 0x00000001
1153 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_CLR_MSK 0xfffffffe
1155 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_RESET 0x0
1157 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_GET(value) (((value) & 0x00000001) >> 0)
1159 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_STATALARMSTATUS_SET(value) (((value) << 0) & 0x00000001)
1161 #ifndef __ASSEMBLY__
1173 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_s
1175 const volatile uint32_t STATALARMSTATUS : 1;
1180 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_t;
1184 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_RESET 0x00000000
1186 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_OFST 0x34
1211 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_LSB 0
1213 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_MSB 0
1215 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_WIDTH 1
1217 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_SET_MSK 0x00000001
1219 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_CLR_MSK 0xfffffffe
1221 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_RESET 0x0
1223 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_GET(value) (((value) & 0x00000001) >> 0)
1225 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_STATALARMCLR_SET(value) (((value) << 0) & 0x00000001)
1227 #ifndef __ASSEMBLY__
1239 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_s
1241 volatile uint32_t STATALARMCLR : 1;
1246 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_t;
1250 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_RESET 0x00000000
1252 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_OFST 0x38
1275 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_LSB 0
1277 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_MSB 0
1279 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_WIDTH 1
1281 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_SET_MSK 0x00000001
1283 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_CLR_MSK 0xfffffffe
1285 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_RESET 0x1
1287 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_GET(value) (((value) & 0x00000001) >> 0)
1289 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_STATALARMEN_SET(value) (((value) << 0) & 0x00000001)
1291 #ifndef __ASSEMBLY__
1303 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_s
1305 volatile uint32_t STATALARMEN : 1;
1310 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_t;
1314 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_RESET 0x00000001
1316 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_OFST 0x3c
1339 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_LSB 0
1341 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_MSB 13
1343 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_WIDTH 14
1345 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_SET_MSK 0x00003fff
1347 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_CLR_MSK 0xffffc000
1349 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_RESET 0x0
1351 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_GET(value) (((value) & 0x00003fff) >> 0)
1353 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_0_ROUTEIDBASE_SET(value) (((value) << 0) & 0x00003fff)
1355 #ifndef __ASSEMBLY__
1367 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_s
1369 volatile uint32_t FILTERS_0_ROUTEIDBASE : 14;
1374 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_t;
1378 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_RESET 0x00000000
1380 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_OFST 0x44
1404 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_LSB 0
1406 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_MSB 13
1408 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_WIDTH 14
1410 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_SET_MSK 0x00003fff
1412 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_CLR_MSK 0xffffc000
1414 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_RESET 0x0
1416 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_GET(value) (((value) & 0x00003fff) >> 0)
1418 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_0_ROUTEIDMASK_SET(value) (((value) << 0) & 0x00003fff)
1420 #ifndef __ASSEMBLY__
1432 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_s
1434 volatile uint32_t FILTERS_0_ROUTEIDMASK : 14;
1439 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_t;
1443 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_RESET 0x00000000
1445 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_OFST 0x48
1466 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_LSB 0
1468 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_MSB 31
1470 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_WIDTH 32
1472 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_SET_MSK 0xffffffff
1474 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_CLR_MSK 0x00000000
1476 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_RESET 0x0
1478 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
1480 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_0_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
1482 #ifndef __ASSEMBLY__
1494 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_s
1496 volatile uint32_t FILTERS_0_ADDRBASE_LOW : 32;
1500 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_t;
1504 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_RESET 0x00000000
1506 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_OFST 0x4c
1528 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_LSB 0
1530 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_MSB 4
1532 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_WIDTH 5
1534 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_SET_MSK 0x0000001f
1536 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_CLR_MSK 0xffffffe0
1538 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_RESET 0x0
1540 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_GET(value) (((value) & 0x0000001f) >> 0)
1542 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_0_ADDRBASE_HIGH_SET(value) (((value) << 0) & 0x0000001f)
1544 #ifndef __ASSEMBLY__
1556 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_s
1558 volatile uint32_t FILTERS_0_ADDRBASE_HIGH : 5;
1563 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_t;
1567 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_RESET 0x00000000
1569 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_OFST 0x50
1595 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_LSB 0
1597 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_MSB 5
1599 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_WIDTH 6
1601 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_SET_MSK 0x0000003f
1603 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_CLR_MSK 0xffffffc0
1605 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_RESET 0x0
1607 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
1609 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_0_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
1611 #ifndef __ASSEMBLY__
1623 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_s
1625 volatile uint32_t FILTERS_0_WINDOWSIZE : 6;
1630 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_t;
1634 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_RESET 0x00000000
1636 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_OFST 0x54
1658 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_LSB 0
1660 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_MSB 1
1662 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_WIDTH 2
1664 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_SET_MSK 0x00000003
1666 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_CLR_MSK 0xfffffffc
1668 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_RESET 0x0
1670 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_GET(value) (((value) & 0x00000003) >> 0)
1672 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_0_SECURITYBASE_SET(value) (((value) << 0) & 0x00000003)
1674 #ifndef __ASSEMBLY__
1686 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_s
1688 volatile uint32_t FILTERS_0_SECURITYBASE : 2;
1693 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_t;
1697 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_RESET 0x00000000
1699 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_OFST 0x58
1723 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_LSB 0
1725 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_MSB 1
1727 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_WIDTH 2
1729 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_SET_MSK 0x00000003
1731 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_CLR_MSK 0xfffffffc
1733 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_RESET 0x0
1735 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_GET(value) (((value) & 0x00000003) >> 0)
1737 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_SET(value) (((value) << 0) & 0x00000003)
1739 #ifndef __ASSEMBLY__
1751 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_s
1753 volatile uint32_t FILTERS_0_SECURITYMASK : 2;
1758 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_t;
1762 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_RESET 0x00000000
1764 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_OFST 0x5c
1792 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_LSB 0
1794 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_MSB 0
1796 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_WIDTH 1
1798 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_SET_MSK 0x00000001
1800 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_CLR_MSK 0xfffffffe
1802 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_RESET 0x0
1804 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
1806 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
1817 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_LSB 1
1819 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_MSB 1
1821 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_WIDTH 1
1823 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_SET_MSK 0x00000002
1825 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_CLR_MSK 0xfffffffd
1827 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_RESET 0x0
1829 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
1831 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
1842 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_LSB 2
1844 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_MSB 2
1846 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_WIDTH 1
1848 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_SET_MSK 0x00000004
1850 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
1852 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_RESET 0x0
1854 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
1856 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
1867 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_LSB 3
1869 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_MSB 3
1871 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_WIDTH 1
1873 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_SET_MSK 0x00000008
1875 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_CLR_MSK 0xfffffff7
1877 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_RESET 0x0
1879 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
1881 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
1883 #ifndef __ASSEMBLY__
1895 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_s
1897 volatile uint32_t RDEN : 1;
1898 volatile uint32_t WREN : 1;
1899 volatile uint32_t LOCKEN : 1;
1900 volatile uint32_t URGEN : 1;
1905 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_t;
1909 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_RESET 0x00000000
1911 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_OFST 0x60
1937 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_LSB 0
1939 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_MSB 0
1941 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_WIDTH 1
1943 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_SET_MSK 0x00000001
1945 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_CLR_MSK 0xfffffffe
1947 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_RESET 0x0
1949 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_GET(value) (((value) & 0x00000001) >> 0)
1951 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_REQEN_SET(value) (((value) << 0) & 0x00000001)
1962 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_LSB 1
1964 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_MSB 1
1966 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_WIDTH 1
1968 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_SET_MSK 0x00000002
1970 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_CLR_MSK 0xfffffffd
1972 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_RESET 0x0
1974 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
1976 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_SET(value) (((value) << 1) & 0x00000002)
1978 #ifndef __ASSEMBLY__
1990 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_s
1992 volatile uint32_t REQEN : 1;
1993 volatile uint32_t RSPEN : 1;
1998 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_t;
2002 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_RESET 0x00000000
2004 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_OFST 0x64
2027 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_LSB 0
2029 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_MSB 3
2031 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_WIDTH 4
2033 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_SET_MSK 0x0000000f
2035 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_CLR_MSK 0xfffffff0
2037 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_RESET 0x0
2039 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_GET(value) (((value) & 0x0000000f) >> 0)
2041 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_SET(value) (((value) << 0) & 0x0000000f)
2043 #ifndef __ASSEMBLY__
2055 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_s
2057 volatile uint32_t FILTERS_0_LENGTH : 4;
2062 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_t;
2066 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_RESET 0x00000000
2068 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_OFST 0x68
2092 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_LSB 0
2094 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_MSB 1
2096 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_WIDTH 2
2098 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_SET_MSK 0x00000003
2100 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_CLR_MSK 0xfffffffc
2102 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_RESET 0x0
2104 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2106 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2108 #ifndef __ASSEMBLY__
2120 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_s
2122 volatile uint32_t FILTERS_0_URGENCY : 2;
2127 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_t;
2131 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_RESET 0x00000000
2133 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_OFST 0x6c
2156 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_LSB 0
2158 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_MSB 13
2160 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_WIDTH 14
2162 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_SET_MSK 0x00003fff
2164 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_CLR_MSK 0xffffc000
2166 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_RESET 0x0
2168 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_GET(value) (((value) & 0x00003fff) >> 0)
2170 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_1_ROUTEIDBASE_SET(value) (((value) << 0) & 0x00003fff)
2172 #ifndef __ASSEMBLY__
2184 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_s
2186 volatile uint32_t FILTERS_1_ROUTEIDBASE : 14;
2191 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_t;
2195 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_RESET 0x00000000
2197 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_OFST 0x80
2221 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_LSB 0
2223 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_MSB 13
2225 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_WIDTH 14
2227 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_SET_MSK 0x00003fff
2229 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_CLR_MSK 0xffffc000
2231 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_RESET 0x0
2233 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_GET(value) (((value) & 0x00003fff) >> 0)
2235 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_1_ROUTEIDMASK_SET(value) (((value) << 0) & 0x00003fff)
2237 #ifndef __ASSEMBLY__
2249 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_s
2251 volatile uint32_t FILTERS_1_ROUTEIDMASK : 14;
2256 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_t;
2260 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_RESET 0x00000000
2262 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_OFST 0x84
2283 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_LSB 0
2285 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_MSB 31
2287 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_WIDTH 32
2289 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_SET_MSK 0xffffffff
2291 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_CLR_MSK 0x00000000
2293 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_RESET 0x0
2295 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
2297 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_1_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
2299 #ifndef __ASSEMBLY__
2311 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_s
2313 volatile uint32_t FILTERS_1_ADDRBASE_LOW : 32;
2317 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_t;
2321 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_RESET 0x00000000
2323 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_OFST 0x88
2345 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_LSB 0
2347 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_MSB 4
2349 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_WIDTH 5
2351 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_SET_MSK 0x0000001f
2353 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_CLR_MSK 0xffffffe0
2355 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_RESET 0x0
2357 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_GET(value) (((value) & 0x0000001f) >> 0)
2359 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_1_ADDRBASE_HIGH_SET(value) (((value) << 0) & 0x0000001f)
2361 #ifndef __ASSEMBLY__
2373 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_s
2375 volatile uint32_t FILTERS_1_ADDRBASE_HIGH : 5;
2380 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_t;
2384 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_RESET 0x00000000
2386 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_OFST 0x8c
2412 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_LSB 0
2414 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_MSB 5
2416 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_WIDTH 6
2418 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_SET_MSK 0x0000003f
2420 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_CLR_MSK 0xffffffc0
2422 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_RESET 0x0
2424 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
2426 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_1_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
2428 #ifndef __ASSEMBLY__
2440 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_s
2442 volatile uint32_t FILTERS_1_WINDOWSIZE : 6;
2447 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_t;
2451 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_RESET 0x00000000
2453 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_OFST 0x90
2475 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_LSB 0
2477 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_MSB 1
2479 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_WIDTH 2
2481 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_SET_MSK 0x00000003
2483 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_CLR_MSK 0xfffffffc
2485 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_RESET 0x0
2487 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_GET(value) (((value) & 0x00000003) >> 0)
2489 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_1_SECURITYBASE_SET(value) (((value) << 0) & 0x00000003)
2491 #ifndef __ASSEMBLY__
2503 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_s
2505 volatile uint32_t FILTERS_1_SECURITYBASE : 2;
2510 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_t;
2514 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_RESET 0x00000000
2516 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_OFST 0x94
2540 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_LSB 0
2542 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_MSB 1
2544 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_WIDTH 2
2546 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_SET_MSK 0x00000003
2548 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_CLR_MSK 0xfffffffc
2550 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_RESET 0x0
2552 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_GET(value) (((value) & 0x00000003) >> 0)
2554 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_SET(value) (((value) << 0) & 0x00000003)
2556 #ifndef __ASSEMBLY__
2568 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_s
2570 volatile uint32_t FILTERS_1_SECURITYMASK : 2;
2575 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_t;
2579 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_RESET 0x00000000
2581 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_OFST 0x98
2609 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_LSB 0
2611 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_MSB 0
2613 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_WIDTH 1
2615 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_SET_MSK 0x00000001
2617 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_CLR_MSK 0xfffffffe
2619 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_RESET 0x0
2621 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
2623 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
2634 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_LSB 1
2636 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_MSB 1
2638 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_WIDTH 1
2640 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_SET_MSK 0x00000002
2642 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_CLR_MSK 0xfffffffd
2644 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_RESET 0x0
2646 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
2648 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
2659 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_LSB 2
2661 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_MSB 2
2663 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_WIDTH 1
2665 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_SET_MSK 0x00000004
2667 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
2669 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_RESET 0x0
2671 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
2673 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
2684 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_LSB 3
2686 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_MSB 3
2688 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_WIDTH 1
2690 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_SET_MSK 0x00000008
2692 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_CLR_MSK 0xfffffff7
2694 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_RESET 0x0
2696 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
2698 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
2700 #ifndef __ASSEMBLY__
2712 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_s
2714 volatile uint32_t RDEN : 1;
2715 volatile uint32_t WREN : 1;
2716 volatile uint32_t LOCKEN : 1;
2717 volatile uint32_t URGEN : 1;
2722 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_t;
2726 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_RESET 0x00000000
2728 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_OFST 0x9c
2754 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_LSB 0
2756 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_MSB 0
2758 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_WIDTH 1
2760 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_SET_MSK 0x00000001
2762 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_CLR_MSK 0xfffffffe
2764 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_RESET 0x0
2766 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_GET(value) (((value) & 0x00000001) >> 0)
2768 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_REQEN_SET(value) (((value) << 0) & 0x00000001)
2779 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_LSB 1
2781 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_MSB 1
2783 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_WIDTH 1
2785 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_SET_MSK 0x00000002
2787 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_CLR_MSK 0xfffffffd
2789 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_RESET 0x0
2791 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
2793 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_SET(value) (((value) << 1) & 0x00000002)
2795 #ifndef __ASSEMBLY__
2807 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_s
2809 volatile uint32_t REQEN : 1;
2810 volatile uint32_t RSPEN : 1;
2815 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_t;
2819 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_RESET 0x00000000
2821 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_OFST 0xa0
2844 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_LSB 0
2846 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_MSB 3
2848 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_WIDTH 4
2850 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_SET_MSK 0x0000000f
2852 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_CLR_MSK 0xfffffff0
2854 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_RESET 0x0
2856 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_GET(value) (((value) & 0x0000000f) >> 0)
2858 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_SET(value) (((value) << 0) & 0x0000000f)
2860 #ifndef __ASSEMBLY__
2872 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_s
2874 volatile uint32_t FILTERS_1_LENGTH : 4;
2879 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_t;
2883 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_RESET 0x00000000
2885 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_OFST 0xa4
2909 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_LSB 0
2911 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_MSB 1
2913 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_WIDTH 2
2915 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_SET_MSK 0x00000003
2917 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_CLR_MSK 0xfffffffc
2919 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_RESET 0x0
2921 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2923 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2925 #ifndef __ASSEMBLY__
2937 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_s
2939 volatile uint32_t FILTERS_1_URGENCY : 2;
2944 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_t;
2948 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_RESET 0x00000000
2950 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_OFST 0xa8
2973 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_LSB 0
2975 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_MSB 13
2977 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_WIDTH 14
2979 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_SET_MSK 0x00003fff
2981 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_CLR_MSK 0xffffc000
2983 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_RESET 0x0
2985 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_GET(value) (((value) & 0x00003fff) >> 0)
2987 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_FILTERS_2_ROUTEIDBASE_SET(value) (((value) << 0) & 0x00003fff)
2989 #ifndef __ASSEMBLY__
3001 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_s
3003 volatile uint32_t FILTERS_2_ROUTEIDBASE : 14;
3008 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_t;
3012 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_RESET 0x00000000
3014 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_OFST 0xbc
3038 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_LSB 0
3040 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_MSB 13
3042 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_WIDTH 14
3044 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_SET_MSK 0x00003fff
3046 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_CLR_MSK 0xffffc000
3048 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_RESET 0x0
3050 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_GET(value) (((value) & 0x00003fff) >> 0)
3052 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_FILTERS_2_ROUTEIDMASK_SET(value) (((value) << 0) & 0x00003fff)
3054 #ifndef __ASSEMBLY__
3066 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_s
3068 volatile uint32_t FILTERS_2_ROUTEIDMASK : 14;
3073 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_t;
3077 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_RESET 0x00000000
3079 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_OFST 0xc0
3100 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_LSB 0
3102 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_MSB 31
3104 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_WIDTH 32
3106 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_SET_MSK 0xffffffff
3108 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_CLR_MSK 0x00000000
3110 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_RESET 0x0
3112 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
3114 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_FILTERS_2_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
3116 #ifndef __ASSEMBLY__
3128 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_s
3130 volatile uint32_t FILTERS_2_ADDRBASE_LOW : 32;
3134 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_t;
3138 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_RESET 0x00000000
3140 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_OFST 0xc4
3162 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_LSB 0
3164 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_MSB 4
3166 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_WIDTH 5
3168 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_SET_MSK 0x0000001f
3170 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_CLR_MSK 0xffffffe0
3172 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_RESET 0x0
3174 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_GET(value) (((value) & 0x0000001f) >> 0)
3176 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_FILTERS_2_ADDRBASE_HIGH_SET(value) (((value) << 0) & 0x0000001f)
3178 #ifndef __ASSEMBLY__
3190 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_s
3192 volatile uint32_t FILTERS_2_ADDRBASE_HIGH : 5;
3197 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_t;
3201 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_RESET 0x00000000
3203 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_OFST 0xc8
3229 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_LSB 0
3231 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_MSB 5
3233 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_WIDTH 6
3235 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_SET_MSK 0x0000003f
3237 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_CLR_MSK 0xffffffc0
3239 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_RESET 0x0
3241 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
3243 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_FILTERS_2_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
3245 #ifndef __ASSEMBLY__
3257 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_s
3259 volatile uint32_t FILTERS_2_WINDOWSIZE : 6;
3264 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_t;
3268 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_RESET 0x00000000
3270 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_OFST 0xcc
3292 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_LSB 0
3294 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_MSB 1
3296 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_WIDTH 2
3298 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_SET_MSK 0x00000003
3300 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_CLR_MSK 0xfffffffc
3302 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_RESET 0x0
3304 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_GET(value) (((value) & 0x00000003) >> 0)
3306 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_FILTERS_2_SECURITYBASE_SET(value) (((value) << 0) & 0x00000003)
3308 #ifndef __ASSEMBLY__
3320 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_s
3322 volatile uint32_t FILTERS_2_SECURITYBASE : 2;
3327 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_t;
3331 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_RESET 0x00000000
3333 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_OFST 0xd0
3357 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_LSB 0
3359 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_MSB 1
3361 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_WIDTH 2
3363 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_SET_MSK 0x00000003
3365 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_CLR_MSK 0xfffffffc
3367 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_RESET 0x0
3369 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_GET(value) (((value) & 0x00000003) >> 0)
3371 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_FILTERS_2_SECURITYMASK_SET(value) (((value) << 0) & 0x00000003)
3373 #ifndef __ASSEMBLY__
3385 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_s
3387 volatile uint32_t FILTERS_2_SECURITYMASK : 2;
3392 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_t;
3396 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_RESET 0x00000000
3398 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_OFST 0xd4
3426 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_LSB 0
3428 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_MSB 0
3430 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_WIDTH 1
3432 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_SET_MSK 0x00000001
3434 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_CLR_MSK 0xfffffffe
3436 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_RESET 0x0
3438 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
3440 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
3451 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_LSB 1
3453 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_MSB 1
3455 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_WIDTH 1
3457 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_SET_MSK 0x00000002
3459 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_CLR_MSK 0xfffffffd
3461 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_RESET 0x0
3463 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
3465 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
3476 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_LSB 2
3478 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_MSB 2
3480 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_WIDTH 1
3482 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_SET_MSK 0x00000004
3484 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
3486 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_RESET 0x0
3488 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
3490 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
3501 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_LSB 3
3503 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_MSB 3
3505 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_WIDTH 1
3507 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_SET_MSK 0x00000008
3509 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_CLR_MSK 0xfffffff7
3511 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_RESET 0x0
3513 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
3515 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
3517 #ifndef __ASSEMBLY__
3529 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_s
3531 volatile uint32_t RDEN : 1;
3532 volatile uint32_t WREN : 1;
3533 volatile uint32_t LOCKEN : 1;
3534 volatile uint32_t URGEN : 1;
3539 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_t;
3543 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_RESET 0x00000000
3545 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_OFST 0xd8
3571 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_LSB 0
3573 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_MSB 0
3575 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_WIDTH 1
3577 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_SET_MSK 0x00000001
3579 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_CLR_MSK 0xfffffffe
3581 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_RESET 0x0
3583 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_GET(value) (((value) & 0x00000001) >> 0)
3585 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_REQEN_SET(value) (((value) << 0) & 0x00000001)
3596 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_LSB 1
3598 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_MSB 1
3600 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_WIDTH 1
3602 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_SET_MSK 0x00000002
3604 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_CLR_MSK 0xfffffffd
3606 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_RESET 0x0
3608 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
3610 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RSPEN_SET(value) (((value) << 1) & 0x00000002)
3612 #ifndef __ASSEMBLY__
3624 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_s
3626 volatile uint32_t REQEN : 1;
3627 volatile uint32_t RSPEN : 1;
3632 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_t;
3636 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_RESET 0x00000000
3638 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_OFST 0xdc
3661 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_LSB 0
3663 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_MSB 3
3665 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_WIDTH 4
3667 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_SET_MSK 0x0000000f
3669 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_CLR_MSK 0xfffffff0
3671 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_RESET 0x0
3673 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_GET(value) (((value) & 0x0000000f) >> 0)
3675 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_FILTERS_2_LENGTH_SET(value) (((value) << 0) & 0x0000000f)
3677 #ifndef __ASSEMBLY__
3689 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_s
3691 volatile uint32_t FILTERS_2_LENGTH : 4;
3696 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_t;
3700 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_RESET 0x00000000
3702 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_OFST 0xe0
3726 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_LSB 0
3728 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_MSB 1
3730 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_WIDTH 2
3732 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_SET_MSK 0x00000003
3734 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_CLR_MSK 0xfffffffc
3736 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_RESET 0x0
3738 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
3740 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_FILTERS_2_URGENCY_SET(value) (((value) << 0) & 0x00000003)
3742 #ifndef __ASSEMBLY__
3754 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_s
3756 volatile uint32_t FILTERS_2_URGENCY : 2;
3761 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_t;
3765 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_RESET 0x00000000
3767 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_OFST 0xe4
3790 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_LSB 0
3792 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_MSB 13
3794 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_WIDTH 14
3796 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_SET_MSK 0x00003fff
3798 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_CLR_MSK 0xffffc000
3800 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_RESET 0x0
3802 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_GET(value) (((value) & 0x00003fff) >> 0)
3804 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_FILTERS_3_ROUTEIDBASE_SET(value) (((value) << 0) & 0x00003fff)
3806 #ifndef __ASSEMBLY__
3818 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_s
3820 volatile uint32_t FILTERS_3_ROUTEIDBASE : 14;
3825 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_t;
3829 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_RESET 0x00000000
3831 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_OFST 0xf8
3855 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_LSB 0
3857 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_MSB 13
3859 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_WIDTH 14
3861 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_SET_MSK 0x00003fff
3863 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_CLR_MSK 0xffffc000
3865 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_RESET 0x0
3867 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_GET(value) (((value) & 0x00003fff) >> 0)
3869 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_FILTERS_3_ROUTEIDMASK_SET(value) (((value) << 0) & 0x00003fff)
3871 #ifndef __ASSEMBLY__
3883 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_s
3885 volatile uint32_t FILTERS_3_ROUTEIDMASK : 14;
3890 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_t;
3894 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_RESET 0x00000000
3896 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_OFST 0xfc
3917 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_LSB 0
3919 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_MSB 31
3921 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_WIDTH 32
3923 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_SET_MSK 0xffffffff
3925 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_CLR_MSK 0x00000000
3927 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_RESET 0x0
3929 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
3931 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_FILTERS_3_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
3933 #ifndef __ASSEMBLY__
3945 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_s
3947 volatile uint32_t FILTERS_3_ADDRBASE_LOW : 32;
3951 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_t;
3955 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_RESET 0x00000000
3957 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_OFST 0x100
3979 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_LSB 0
3981 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_MSB 4
3983 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_WIDTH 5
3985 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_SET_MSK 0x0000001f
3987 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_CLR_MSK 0xffffffe0
3989 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_RESET 0x0
3991 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_GET(value) (((value) & 0x0000001f) >> 0)
3993 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_FILTERS_3_ADDRBASE_HIGH_SET(value) (((value) << 0) & 0x0000001f)
3995 #ifndef __ASSEMBLY__
4007 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_s
4009 volatile uint32_t FILTERS_3_ADDRBASE_HIGH : 5;
4014 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_t;
4018 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_RESET 0x00000000
4020 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_OFST 0x104
4046 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_LSB 0
4048 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_MSB 5
4050 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_WIDTH 6
4052 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_SET_MSK 0x0000003f
4054 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_CLR_MSK 0xffffffc0
4056 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_RESET 0x0
4058 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
4060 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_FILTERS_3_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
4062 #ifndef __ASSEMBLY__
4074 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_s
4076 volatile uint32_t FILTERS_3_WINDOWSIZE : 6;
4081 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_t;
4085 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_RESET 0x00000000
4087 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_OFST 0x108
4109 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_LSB 0
4111 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_MSB 1
4113 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_WIDTH 2
4115 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_SET_MSK 0x00000003
4117 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_CLR_MSK 0xfffffffc
4119 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_RESET 0x0
4121 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_GET(value) (((value) & 0x00000003) >> 0)
4123 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_FILTERS_3_SECURITYBASE_SET(value) (((value) << 0) & 0x00000003)
4125 #ifndef __ASSEMBLY__
4137 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_s
4139 volatile uint32_t FILTERS_3_SECURITYBASE : 2;
4144 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_t;
4148 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_RESET 0x00000000
4150 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_OFST 0x10c
4174 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_LSB 0
4176 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_MSB 1
4178 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_WIDTH 2
4180 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_SET_MSK 0x00000003
4182 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_CLR_MSK 0xfffffffc
4184 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_RESET 0x0
4186 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_GET(value) (((value) & 0x00000003) >> 0)
4188 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_FILTERS_3_SECURITYMASK_SET(value) (((value) << 0) & 0x00000003)
4190 #ifndef __ASSEMBLY__
4202 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_s
4204 volatile uint32_t FILTERS_3_SECURITYMASK : 2;
4209 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_t;
4213 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_RESET 0x00000000
4215 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_OFST 0x110
4243 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_LSB 0
4245 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_MSB 0
4247 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_WIDTH 1
4249 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_SET_MSK 0x00000001
4251 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_CLR_MSK 0xfffffffe
4253 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_RESET 0x0
4255 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
4257 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
4268 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_LSB 1
4270 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_MSB 1
4272 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_WIDTH 1
4274 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_SET_MSK 0x00000002
4276 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_CLR_MSK 0xfffffffd
4278 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_RESET 0x0
4280 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
4282 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
4293 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_LSB 2
4295 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_MSB 2
4297 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_WIDTH 1
4299 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_SET_MSK 0x00000004
4301 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
4303 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_RESET 0x0
4305 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
4307 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
4318 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_LSB 3
4320 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_MSB 3
4322 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_WIDTH 1
4324 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_SET_MSK 0x00000008
4326 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_CLR_MSK 0xfffffff7
4328 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_RESET 0x0
4330 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
4332 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
4334 #ifndef __ASSEMBLY__
4346 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_s
4348 volatile uint32_t RDEN : 1;
4349 volatile uint32_t WREN : 1;
4350 volatile uint32_t LOCKEN : 1;
4351 volatile uint32_t URGEN : 1;
4356 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_t;
4360 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_RESET 0x00000000
4362 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_OFST 0x114
4388 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_LSB 0
4390 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_MSB 0
4392 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_WIDTH 1
4394 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_SET_MSK 0x00000001
4396 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_CLR_MSK 0xfffffffe
4398 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_RESET 0x0
4400 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_GET(value) (((value) & 0x00000001) >> 0)
4402 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_REQEN_SET(value) (((value) << 0) & 0x00000001)
4413 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_LSB 1
4415 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_MSB 1
4417 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_WIDTH 1
4419 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_SET_MSK 0x00000002
4421 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_CLR_MSK 0xfffffffd
4423 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_RESET 0x0
4425 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
4427 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RSPEN_SET(value) (((value) << 1) & 0x00000002)
4429 #ifndef __ASSEMBLY__
4441 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_s
4443 volatile uint32_t REQEN : 1;
4444 volatile uint32_t RSPEN : 1;
4449 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_t;
4453 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_RESET 0x00000000
4455 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_OFST 0x118
4478 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_LSB 0
4480 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_MSB 3
4482 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_WIDTH 4
4484 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_SET_MSK 0x0000000f
4486 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_CLR_MSK 0xfffffff0
4488 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_RESET 0x0
4490 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_GET(value) (((value) & 0x0000000f) >> 0)
4492 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_FILTERS_3_LENGTH_SET(value) (((value) << 0) & 0x0000000f)
4494 #ifndef __ASSEMBLY__
4506 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_s
4508 volatile uint32_t FILTERS_3_LENGTH : 4;
4513 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_t;
4517 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_RESET 0x00000000
4519 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_OFST 0x11c
4543 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_LSB 0
4545 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_MSB 1
4547 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_WIDTH 2
4549 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_SET_MSK 0x00000003
4551 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_CLR_MSK 0xfffffffc
4553 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_RESET 0x0
4555 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
4557 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_FILTERS_3_URGENCY_SET(value) (((value) << 0) & 0x00000003)
4559 #ifndef __ASSEMBLY__
4571 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_s
4573 volatile uint32_t FILTERS_3_URGENCY : 2;
4578 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_t;
4582 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_RESET 0x00000000
4584 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_OFST 0x120
4610 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_LSB 0
4612 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_MSB 4
4614 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_WIDTH 5
4616 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_SET_MSK 0x0000001f
4618 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_CLR_MSK 0xffffffe0
4620 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_RESET 0x0
4622 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
4624 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
4626 #ifndef __ASSEMBLY__
4638 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_s
4640 volatile uint32_t INTEVENT : 5;
4645 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_t;
4649 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_RESET 0x00000000
4651 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_OFST 0x138
4675 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_LSB 0
4677 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_MSB 1
4679 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_WIDTH 2
4681 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_SET_MSK 0x00000003
4683 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_CLR_MSK 0xfffffffc
4685 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_RESET 0x0
4687 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_GET(value) (((value) & 0x00000003) >> 0)
4689 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_COUNTERS_0_ALARMMODE_SET(value) (((value) << 0) & 0x00000003)
4691 #ifndef __ASSEMBLY__
4703 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_s
4705 volatile uint32_t COUNTERS_0_ALARMMODE : 2;
4710 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_t;
4714 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_RESET 0x00000000
4716 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_OFST 0x13c
4740 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_LSB 0
4742 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_MSB 15
4744 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_WIDTH 16
4746 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_SET_MSK 0x0000ffff
4748 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_CLR_MSK 0xffff0000
4750 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_RESET 0x0
4752 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
4754 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_SET(value) (((value) << 0) & 0x0000ffff)
4756 #ifndef __ASSEMBLY__
4768 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_s
4770 const volatile uint32_t COUNTERS_0_VAL : 16;
4775 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_t;
4779 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_RESET 0x00000000
4781 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_OFST 0x140
4807 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_LSB 0
4809 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_MSB 4
4811 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_WIDTH 5
4813 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_SET_MSK 0x0000001f
4815 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_CLR_MSK 0xffffffe0
4817 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_RESET 0x0
4819 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
4821 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
4823 #ifndef __ASSEMBLY__
4835 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_s
4837 volatile uint32_t INTEVENT : 5;
4842 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_t;
4846 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_RESET 0x00000000
4848 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_OFST 0x14c
4872 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_LSB 0
4874 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_MSB 1
4876 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_WIDTH 2
4878 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_SET_MSK 0x00000003
4880 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_CLR_MSK 0xfffffffc
4882 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_RESET 0x0
4884 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_GET(value) (((value) & 0x00000003) >> 0)
4886 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_COUNTERS_1_ALARMMODE_SET(value) (((value) << 0) & 0x00000003)
4888 #ifndef __ASSEMBLY__
4900 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_s
4902 volatile uint32_t COUNTERS_1_ALARMMODE : 2;
4907 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_t;
4911 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_RESET 0x00000000
4913 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_OFST 0x150
4937 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_LSB 0
4939 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_MSB 15
4941 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_WIDTH 16
4943 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_SET_MSK 0x0000ffff
4945 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_CLR_MSK 0xffff0000
4947 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_RESET 0x0
4949 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
4951 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_SET(value) (((value) << 0) & 0x0000ffff)
4953 #ifndef __ASSEMBLY__
4965 struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_s
4967 const volatile uint32_t COUNTERS_1_VAL : 16;
4972 typedef struct ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_s ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_t;
4976 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_RESET 0x00000000
4978 #define ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_OFST 0x154
4980 #ifndef __ASSEMBLY__
4992 struct ALT_MPFE_DDR_MAIN_PRB_s
4994 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_COREID_t ddr_T_main_Probe_Id_CoreId;
4995 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_ID_REVISIONID_t ddr_T_main_Probe_Id_RevisionId;
4996 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_MAINCTL_t ddr_T_main_Probe_MainCtl;
4997 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_CFGCTL_t ddr_T_main_Probe_CfgCtl;
4998 volatile uint32_t _pad_0x10_0x13;
4999 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERLUT_t ddr_T_main_Probe_FilterLut;
5000 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMEN_t ddr_T_main_Probe_TraceAlarmEn;
5001 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMSTATUS_t ddr_T_main_Probe_TraceAlarmStatus;
5002 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_TRACEALARMCLR_t ddr_T_main_Probe_TraceAlarmClr;
5003 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATPERIOD_t ddr_T_main_Probe_StatPeriod;
5004 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATGO_t ddr_T_main_Probe_StatGo;
5005 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMIN_t ddr_T_main_Probe_StatAlarmMin;
5006 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMMAX_t ddr_T_main_Probe_StatAlarmMax;
5007 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMSTATUS_t ddr_T_main_Probe_StatAlarmStatus;
5008 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMCLR_t ddr_T_main_Probe_StatAlarmClr;
5009 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_STATALARMEN_t ddr_T_main_Probe_StatAlarmEn;
5010 volatile uint32_t _pad_0x40_0x43;
5011 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_t ddr_T_main_Probe_Filters_0_RouteIdBase;
5012 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_t ddr_T_main_Probe_Filters_0_RouteIdMask;
5013 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_0_AddrBase_Low;
5014 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_t ddr_T_main_Probe_Filters_0_AddrBase_High;
5015 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_WINDOWSIZE_t ddr_T_main_Probe_Filters_0_WindowSize;
5016 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYBASE_t ddr_T_main_Probe_Filters_0_SecurityBase;
5017 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_SECURITYMASK_t ddr_T_main_Probe_Filters_0_SecurityMask;
5018 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_OPCODE_t ddr_T_main_Probe_Filters_0_Opcode;
5019 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_STATUS_t ddr_T_main_Probe_Filters_0_Status;
5020 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_LENGTH_t ddr_T_main_Probe_Filters_0_Length;
5021 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_0_URGENCY_t ddr_T_main_Probe_Filters_0_Urgency;
5022 volatile uint32_t _pad_0x70_0x7f[4];
5023 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_t ddr_T_main_Probe_Filters_1_RouteIdBase;
5024 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_t ddr_T_main_Probe_Filters_1_RouteIdMask;
5025 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_1_AddrBase_Low;
5026 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_t ddr_T_main_Probe_Filters_1_AddrBase_High;
5027 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_WINDOWSIZE_t ddr_T_main_Probe_Filters_1_WindowSize;
5028 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYBASE_t ddr_T_main_Probe_Filters_1_SecurityBase;
5029 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_SECURITYMASK_t ddr_T_main_Probe_Filters_1_SecurityMask;
5030 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_OPCODE_t ddr_T_main_Probe_Filters_1_Opcode;
5031 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_STATUS_t ddr_T_main_Probe_Filters_1_Status;
5032 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_LENGTH_t ddr_T_main_Probe_Filters_1_Length;
5033 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_1_URGENCY_t ddr_T_main_Probe_Filters_1_Urgency;
5034 volatile uint32_t _pad_0xac_0xbb[4];
5035 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDBASE_t ddr_T_main_Probe_Filters_2_RouteIdBase;
5036 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ROUTEIDMASK_t ddr_T_main_Probe_Filters_2_RouteIdMask;
5037 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_2_AddrBase_Low;
5038 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_ADDRBASE_HIGH_t ddr_T_main_Probe_Filters_2_AddrBase_High;
5039 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_WINDOWSIZE_t ddr_T_main_Probe_Filters_2_WindowSize;
5040 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYBASE_t ddr_T_main_Probe_Filters_2_SecurityBase;
5041 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_SECURITYMASK_t ddr_T_main_Probe_Filters_2_SecurityMask;
5042 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_OPCODE_t ddr_T_main_Probe_Filters_2_Opcode;
5043 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_STATUS_t ddr_T_main_Probe_Filters_2_Status;
5044 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_LENGTH_t ddr_T_main_Probe_Filters_2_Length;
5045 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_2_URGENCY_t ddr_T_main_Probe_Filters_2_Urgency;
5046 volatile uint32_t _pad_0xe8_0xf7[4];
5047 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDBASE_t ddr_T_main_Probe_Filters_3_RouteIdBase;
5048 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ROUTEIDMASK_t ddr_T_main_Probe_Filters_3_RouteIdMask;
5049 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_3_AddrBase_Low;
5050 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_ADDRBASE_HIGH_t ddr_T_main_Probe_Filters_3_AddrBase_High;
5051 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_WINDOWSIZE_t ddr_T_main_Probe_Filters_3_WindowSize;
5052 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYBASE_t ddr_T_main_Probe_Filters_3_SecurityBase;
5053 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_SECURITYMASK_t ddr_T_main_Probe_Filters_3_SecurityMask;
5054 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_OPCODE_t ddr_T_main_Probe_Filters_3_Opcode;
5055 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_STATUS_t ddr_T_main_Probe_Filters_3_Status;
5056 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_LENGTH_t ddr_T_main_Probe_Filters_3_Length;
5057 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_FILTERS_3_URGENCY_t ddr_T_main_Probe_Filters_3_Urgency;
5058 volatile uint32_t _pad_0x124_0x137[5];
5059 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_SRC_t ddr_T_main_Probe_Counters_0_Src;
5060 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_ALARMMODE_t ddr_T_main_Probe_Counters_0_AlarmMode;
5061 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_0_VAL_t ddr_T_main_Probe_Counters_0_Val;
5062 volatile uint32_t _pad_0x144_0x14b[2];
5063 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_SRC_t ddr_T_main_Probe_Counters_1_Src;
5064 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_ALARMMODE_t ddr_T_main_Probe_Counters_1_AlarmMode;
5065 volatile ALT_MPFE_DDR_MAIN_PRB_DDR_T_MAIN_PROBE_COUNTERS_1_VAL_t ddr_T_main_Probe_Counters_1_Val;
5066 volatile uint32_t _pad_0x158_0x400[170];
5070 typedef struct ALT_MPFE_DDR_MAIN_PRB_s ALT_MPFE_DDR_MAIN_PRB_t;
5072 struct ALT_MPFE_DDR_MAIN_PRB_raw_s
5074 volatile uint32_t ddr_T_main_Probe_Id_CoreId;
5075 volatile uint32_t ddr_T_main_Probe_Id_RevisionId;
5076 volatile uint32_t ddr_T_main_Probe_MainCtl;
5077 volatile uint32_t ddr_T_main_Probe_CfgCtl;
5078 volatile uint32_t _pad_0x10_0x13;
5079 volatile uint32_t ddr_T_main_Probe_FilterLut;
5080 volatile uint32_t ddr_T_main_Probe_TraceAlarmEn;
5081 volatile uint32_t ddr_T_main_Probe_TraceAlarmStatus;
5082 volatile uint32_t ddr_T_main_Probe_TraceAlarmClr;
5083 volatile uint32_t ddr_T_main_Probe_StatPeriod;
5084 volatile uint32_t ddr_T_main_Probe_StatGo;
5085 volatile uint32_t ddr_T_main_Probe_StatAlarmMin;
5086 volatile uint32_t ddr_T_main_Probe_StatAlarmMax;
5087 volatile uint32_t ddr_T_main_Probe_StatAlarmStatus;
5088 volatile uint32_t ddr_T_main_Probe_StatAlarmClr;
5089 volatile uint32_t ddr_T_main_Probe_StatAlarmEn;
5090 volatile uint32_t _pad_0x40_0x43;
5091 volatile uint32_t ddr_T_main_Probe_Filters_0_RouteIdBase;
5092 volatile uint32_t ddr_T_main_Probe_Filters_0_RouteIdMask;
5093 volatile uint32_t ddr_T_main_Probe_Filters_0_AddrBase_Low;
5094 volatile uint32_t ddr_T_main_Probe_Filters_0_AddrBase_High;
5095 volatile uint32_t ddr_T_main_Probe_Filters_0_WindowSize;
5096 volatile uint32_t ddr_T_main_Probe_Filters_0_SecurityBase;
5097 volatile uint32_t ddr_T_main_Probe_Filters_0_SecurityMask;
5098 volatile uint32_t ddr_T_main_Probe_Filters_0_Opcode;
5099 volatile uint32_t ddr_T_main_Probe_Filters_0_Status;
5100 volatile uint32_t ddr_T_main_Probe_Filters_0_Length;
5101 volatile uint32_t ddr_T_main_Probe_Filters_0_Urgency;
5102 volatile uint32_t _pad_0x70_0x7f[4];
5103 volatile uint32_t ddr_T_main_Probe_Filters_1_RouteIdBase;
5104 volatile uint32_t ddr_T_main_Probe_Filters_1_RouteIdMask;
5105 volatile uint32_t ddr_T_main_Probe_Filters_1_AddrBase_Low;
5106 volatile uint32_t ddr_T_main_Probe_Filters_1_AddrBase_High;
5107 volatile uint32_t ddr_T_main_Probe_Filters_1_WindowSize;
5108 volatile uint32_t ddr_T_main_Probe_Filters_1_SecurityBase;
5109 volatile uint32_t ddr_T_main_Probe_Filters_1_SecurityMask;
5110 volatile uint32_t ddr_T_main_Probe_Filters_1_Opcode;
5111 volatile uint32_t ddr_T_main_Probe_Filters_1_Status;
5112 volatile uint32_t ddr_T_main_Probe_Filters_1_Length;
5113 volatile uint32_t ddr_T_main_Probe_Filters_1_Urgency;
5114 volatile uint32_t _pad_0xac_0xbb[4];
5115 volatile uint32_t ddr_T_main_Probe_Filters_2_RouteIdBase;
5116 volatile uint32_t ddr_T_main_Probe_Filters_2_RouteIdMask;
5117 volatile uint32_t ddr_T_main_Probe_Filters_2_AddrBase_Low;
5118 volatile uint32_t ddr_T_main_Probe_Filters_2_AddrBase_High;
5119 volatile uint32_t ddr_T_main_Probe_Filters_2_WindowSize;
5120 volatile uint32_t ddr_T_main_Probe_Filters_2_SecurityBase;
5121 volatile uint32_t ddr_T_main_Probe_Filters_2_SecurityMask;
5122 volatile uint32_t ddr_T_main_Probe_Filters_2_Opcode;
5123 volatile uint32_t ddr_T_main_Probe_Filters_2_Status;
5124 volatile uint32_t ddr_T_main_Probe_Filters_2_Length;
5125 volatile uint32_t ddr_T_main_Probe_Filters_2_Urgency;
5126 volatile uint32_t _pad_0xe8_0xf7[4];
5127 volatile uint32_t ddr_T_main_Probe_Filters_3_RouteIdBase;
5128 volatile uint32_t ddr_T_main_Probe_Filters_3_RouteIdMask;
5129 volatile uint32_t ddr_T_main_Probe_Filters_3_AddrBase_Low;
5130 volatile uint32_t ddr_T_main_Probe_Filters_3_AddrBase_High;
5131 volatile uint32_t ddr_T_main_Probe_Filters_3_WindowSize;
5132 volatile uint32_t ddr_T_main_Probe_Filters_3_SecurityBase;
5133 volatile uint32_t ddr_T_main_Probe_Filters_3_SecurityMask;
5134 volatile uint32_t ddr_T_main_Probe_Filters_3_Opcode;
5135 volatile uint32_t ddr_T_main_Probe_Filters_3_Status;
5136 volatile uint32_t ddr_T_main_Probe_Filters_3_Length;
5137 volatile uint32_t ddr_T_main_Probe_Filters_3_Urgency;
5138 volatile uint32_t _pad_0x124_0x137[5];
5139 volatile uint32_t ddr_T_main_Probe_Counters_0_Src;
5140 volatile uint32_t ddr_T_main_Probe_Counters_0_AlarmMode;
5141 volatile uint32_t ddr_T_main_Probe_Counters_0_Val;
5142 volatile uint32_t _pad_0x144_0x14b[2];
5143 volatile uint32_t ddr_T_main_Probe_Counters_1_Src;
5144 volatile uint32_t ddr_T_main_Probe_Counters_1_AlarmMode;
5145 volatile uint32_t ddr_T_main_Probe_Counters_1_Val;
5146 volatile uint32_t _pad_0x158_0x400[170];
5150 typedef struct ALT_MPFE_DDR_MAIN_PRB_raw_s ALT_MPFE_DDR_MAIN_PRB_raw_t;
5178 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_LSB 0
5180 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_MSB 7
5182 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_WIDTH 8
5184 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
5186 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
5188 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_RESET 0x2
5190 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
5192 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
5203 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_LSB 8
5205 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_MSB 31
5207 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_WIDTH 24
5209 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
5211 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
5213 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_RESET 0x6471be
5215 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
5217 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
5219 #ifndef __ASSEMBLY__
5231 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_s
5233 const volatile uint32_t CORETYPEID : 8;
5234 const volatile uint32_t CORECHECKSUM : 24;
5238 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_t;
5242 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_RESET 0x6471be02
5244 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_OFST 0x0
5266 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_LSB 0
5268 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_MSB 7
5270 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_WIDTH 8
5272 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_SET_MSK 0x000000ff
5274 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
5276 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_RESET 0x0
5278 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
5280 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
5292 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_LSB 8
5294 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_MSB 31
5296 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_WIDTH 24
5298 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
5300 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
5302 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_RESET 0x148
5304 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
5306 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
5308 #ifndef __ASSEMBLY__
5320 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_s
5322 const volatile uint32_t USERID : 8;
5323 const volatile uint32_t FLEXNOCID : 24;
5327 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_t;
5331 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_RESET 0x00014800
5333 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_OFST 0x4
5386 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R12_B3_C10 0x00
5392 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R13_B3_C9 0x01
5398 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R13_B3_C10 0x02
5404 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R14_B3_C9 0x03
5410 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R14_B3_C10 0x04
5416 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R15_B3_C10 0x05
5422 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R14_B3_C11 0x06
5428 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R15_B3_C11 0x07
5434 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R16_B3_C10 0x08
5440 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R16_B3_C11 0x09
5446 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_R15_B3_C12 0x0A
5452 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B3_R14_C10 0x0B
5458 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B4_R14_C10 0x0C
5464 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B3_R15_C10 0x0D
5470 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B4_R15_C10 0x0E
5476 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B3_R16_C10 0x0F
5482 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B4_R16_C10 0x10
5488 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B3_R17_C10 0x11
5494 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_E_B4_R17_C10 0x12
5497 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_LSB 0
5499 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_MSB 4
5501 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_WIDTH 5
5503 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_SET_MSK 0x0000001f
5505 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_CLR_MSK 0xffffffe0
5507 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_RESET 0x0
5509 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_GET(value) (((value) & 0x0000001f) >> 0)
5511 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_DDRCONF_SET(value) (((value) << 0) & 0x0000001f)
5513 #ifndef __ASSEMBLY__
5525 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_s
5527 volatile uint32_t DDRCONF : 5;
5532 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_t;
5536 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_RESET 0x00000000
5538 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_OFST 0x8
5569 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_LSB 0
5571 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_MSB 5
5573 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_WIDTH 6
5575 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_SET_MSK 0x0000003f
5577 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_CLR_MSK 0xffffffc0
5579 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_RESET 0x1f
5581 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_GET(value) (((value) & 0x0000003f) >> 0)
5583 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_ACTTOACT_SET(value) (((value) << 0) & 0x0000003f)
5596 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_LSB 6
5598 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_MSB 11
5600 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_WIDTH 6
5602 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_SET_MSK 0x00000fc0
5604 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_CLR_MSK 0xfffff03f
5606 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_RESET 0x15
5608 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_GET(value) (((value) & 0x00000fc0) >> 6)
5610 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOMISS_SET(value) (((value) << 6) & 0x00000fc0)
5623 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_LSB 12
5625 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_MSB 17
5627 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_WIDTH 6
5629 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_SET_MSK 0x0003f000
5631 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_CLR_MSK 0xfffc0fff
5633 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_RESET 0x25
5635 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_GET(value) (((value) & 0x0003f000) >> 12)
5637 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTOMISS_SET(value) (((value) << 12) & 0x0003f000)
5650 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_LSB 18
5652 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_MSB 20
5654 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_WIDTH 3
5656 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_SET_MSK 0x001c0000
5658 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_CLR_MSK 0xffe3ffff
5660 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_RESET 0x3
5662 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_GET(value) (((value) & 0x001c0000) >> 18)
5664 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BURSTLEN_SET(value) (((value) << 18) & 0x001c0000)
5677 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_LSB 21
5679 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_MSB 25
5681 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_WIDTH 5
5683 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_SET_MSK 0x03e00000
5685 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_CLR_MSK 0xfc1fffff
5687 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_RESET 0x2
5689 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_GET(value) (((value) & 0x03e00000) >> 21)
5691 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RDTOWR_SET(value) (((value) << 21) & 0x03e00000)
5703 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_LSB 26
5705 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_MSB 30
5707 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_WIDTH 5
5709 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_SET_MSK 0x7c000000
5711 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_CLR_MSK 0x83ffffff
5713 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_RESET 0xc
5715 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_GET(value) (((value) & 0x7c000000) >> 26)
5717 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_WRTORD_SET(value) (((value) << 26) & 0x7c000000)
5731 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_LSB 31
5733 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_MSB 31
5735 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_WIDTH 1
5737 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_SET_MSK 0x80000000
5739 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_CLR_MSK 0x7fffffff
5741 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_RESET 0x1
5743 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_GET(value) (((value) & 0x80000000) >> 31)
5745 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_BWRATIO_SET(value) (((value) << 31) & 0x80000000)
5747 #ifndef __ASSEMBLY__
5759 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_s
5761 volatile uint32_t ACTTOACT : 6;
5762 volatile uint32_t RDTOMISS : 6;
5763 volatile uint32_t WRTOMISS : 6;
5764 volatile uint32_t BURSTLEN : 3;
5765 volatile uint32_t RDTOWR : 5;
5766 volatile uint32_t WRTORD : 5;
5767 volatile uint32_t BWRATIO : 1;
5771 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_t;
5775 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_RESET 0xb04e555f
5777 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_OFST 0xc
5803 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_LSB 0
5805 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_MSB 0
5807 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_WIDTH 1
5809 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_SET_MSK 0x00000001
5811 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_CLR_MSK 0xfffffffe
5813 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_RESET 0x0
5815 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_GET(value) (((value) & 0x00000001) >> 0)
5817 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_AUTOPRECHARGE_SET(value) (((value) << 0) & 0x00000001)
5828 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_LSB 1
5830 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_MSB 1
5832 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_WIDTH 1
5834 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_SET_MSK 0x00000002
5836 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_CLR_MSK 0xfffffffd
5838 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_RESET 0x0
5840 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_GET(value) (((value) & 0x00000002) >> 1)
5842 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_BWRATIOEXTENDED_SET(value) (((value) << 1) & 0x00000002)
5844 #ifndef __ASSEMBLY__
5856 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_s
5858 volatile uint32_t AUTOPRECHARGE : 1;
5859 volatile uint32_t BWRATIOEXTENDED : 1;
5864 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_t;
5868 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_RESET 0x00000000
5870 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_OFST 0x10
5894 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_LSB 0
5896 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_MSB 7
5898 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_WIDTH 8
5900 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_SET_MSK 0x000000ff
5902 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_CLR_MSK 0xffffff00
5904 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_RESET 0x3d
5906 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_GET(value) (((value) & 0x000000ff) >> 0)
5908 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_READLATENCY_SET(value) (((value) << 0) & 0x000000ff)
5910 #ifndef __ASSEMBLY__
5922 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_s
5924 volatile uint32_t READLATENCY : 8;
5929 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_t;
5933 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_RESET 0x0000003d
5935 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_OFST 0x14
5962 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_LSB 0
5964 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_MSB 3
5966 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_WIDTH 4
5968 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_SET_MSK 0x0000000f
5970 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_CLR_MSK 0xfffffff0
5972 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_RESET 0x3
5974 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_GET(value) (((value) & 0x0000000f) >> 0)
5976 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RRD_SET(value) (((value) << 0) & 0x0000000f)
5987 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_LSB 4
5989 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_MSB 9
5991 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_WIDTH 6
5993 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_SET_MSK 0x000003f0
5995 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_CLR_MSK 0xfffffc0f
5997 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_RESET 0xf
5999 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_GET(value) (((value) & 0x000003f0) >> 4)
6001 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAW_SET(value) (((value) << 4) & 0x000003f0)
6014 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_LSB 10
6016 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_MSB 10
6018 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_WIDTH 1
6020 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_SET_MSK 0x00000400
6022 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_CLR_MSK 0xfffffbff
6024 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_RESET 0x1
6026 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_GET(value) (((value) & 0x00000400) >> 10)
6028 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_FAWBANK_SET(value) (((value) << 10) & 0x00000400)
6030 #ifndef __ASSEMBLY__
6042 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_s
6044 volatile uint32_t RRD : 4;
6045 volatile uint32_t FAW : 6;
6046 volatile uint32_t FAWBANK : 1;
6051 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_t;
6055 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_RESET 0x000004f3
6057 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_OFST 0x38
6086 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_LSB 0
6088 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_MSB 1
6090 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_WIDTH 2
6092 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_SET_MSK 0x00000003
6094 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_CLR_MSK 0xfffffffc
6096 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_RESET 0x1
6098 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_GET(value) (((value) & 0x00000003) >> 0)
6100 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTORD_SET(value) (((value) << 0) & 0x00000003)
6113 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_LSB 2
6115 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_MSB 3
6117 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_WIDTH 2
6119 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_SET_MSK 0x0000000c
6121 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_CLR_MSK 0xfffffff3
6123 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_RESET 0x2
6125 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_GET(value) (((value) & 0x0000000c) >> 2)
6127 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSRDTOWR_SET(value) (((value) << 2) & 0x0000000c)
6140 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_LSB 4
6142 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_MSB 5
6144 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_WIDTH 2
6146 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_SET_MSK 0x00000030
6148 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_CLR_MSK 0xffffffcf
6150 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_RESET 0x2
6152 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_GET(value) (((value) & 0x00000030) >> 4)
6154 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_BUSWRTORD_SET(value) (((value) << 4) & 0x00000030)
6156 #ifndef __ASSEMBLY__
6168 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_s
6170 volatile uint32_t BUSRDTORD : 2;
6171 volatile uint32_t BUSRDTOWR : 2;
6172 volatile uint32_t BUSWRTORD : 2;
6177 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_t;
6181 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_RESET 0x00000029
6183 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_OFST 0x3c
6225 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_LSB 0
6227 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_MSB 2
6229 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_WIDTH 3
6231 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_SET_MSK 0x00000007
6233 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_CLR_MSK 0xfffffff8
6235 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_RESET 0x7
6237 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_GET(value) (((value) & 0x00000007) >> 0)
6239 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_CCDL_SET(value) (((value) << 0) & 0x00000007)
6266 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_LSB 3
6268 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_MSB 7
6270 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_WIDTH 5
6272 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_SET_MSK 0x000000f8
6274 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_CLR_MSK 0xffffff07
6276 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_RESET 0xc
6278 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_GET(value) (((value) & 0x000000f8) >> 3)
6280 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_WRTORDL_SET(value) (((value) << 3) & 0x000000f8)
6307 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_LSB 8
6309 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_MSB 11
6311 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_WIDTH 4
6313 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_SET_MSK 0x00000f00
6315 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_CLR_MSK 0xfffff0ff
6317 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_RESET 0x3
6319 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_GET(value) (((value) & 0x00000f00) >> 8)
6321 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RRDL_SET(value) (((value) << 8) & 0x00000f00)
6323 #ifndef __ASSEMBLY__
6335 struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_s
6337 volatile uint32_t CCDL : 3;
6338 volatile uint32_t WRTORDL : 5;
6339 volatile uint32_t RRDL : 4;
6344 typedef struct ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_s ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_t;
6348 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_RESET 0x00000367
6350 #define ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_OFST 0x40
6352 #ifndef __ASSEMBLY__
6364 struct ALT_MPFE_DDR_MAIN_SCHED_s
6366 volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_COREID_t ddr_T_main_Scheduler_Id_CoreId;
6367 volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ID_REVISIONID_t ddr_T_main_Scheduler_Id_RevisionId;
6368 volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRCONF_t ddr_T_main_Scheduler_DdrConf;
6369 volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRTIMING_t ddr_T_main_Scheduler_DdrTiming;
6370 volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDRMODE_t ddr_T_main_Scheduler_DdrMode;
6371 volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_READLATENCY_t ddr_T_main_Scheduler_ReadLatency;
6372 volatile uint32_t _pad_0x18_0x37[8];
6373 volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_ACTIVATE_t ddr_T_main_Scheduler_Activate;
6374 volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DEVTODEV_t ddr_T_main_Scheduler_DevToDev;
6375 volatile ALT_MPFE_DDR_MAIN_SCHED_DDR_T_MAIN_SCHEDULER_DDR4TIMING_t ddr_T_main_Scheduler_Ddr4Timing;
6376 volatile uint32_t _pad_0x44_0x80[15];
6380 typedef struct ALT_MPFE_DDR_MAIN_SCHED_s ALT_MPFE_DDR_MAIN_SCHED_t;
6382 struct ALT_MPFE_DDR_MAIN_SCHED_raw_s
6384 volatile uint32_t ddr_T_main_Scheduler_Id_CoreId;
6385 volatile uint32_t ddr_T_main_Scheduler_Id_RevisionId;
6386 volatile uint32_t ddr_T_main_Scheduler_DdrConf;
6387 volatile uint32_t ddr_T_main_Scheduler_DdrTiming;
6388 volatile uint32_t ddr_T_main_Scheduler_DdrMode;
6389 volatile uint32_t ddr_T_main_Scheduler_ReadLatency;
6390 volatile uint32_t _pad_0x18_0x37[8];
6391 volatile uint32_t ddr_T_main_Scheduler_Activate;
6392 volatile uint32_t ddr_T_main_Scheduler_DevToDev;
6393 volatile uint32_t ddr_T_main_Scheduler_Ddr4Timing;
6394 volatile uint32_t _pad_0x44_0x80[15];
6398 typedef struct ALT_MPFE_DDR_MAIN_SCHED_raw_s ALT_MPFE_DDR_MAIN_SCHED_raw_t;
6436 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_LSB 0
6438 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_MSB 0
6440 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_WIDTH 1
6442 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET_MSK 0x00000001
6444 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_CLR_MSK 0xfffffffe
6446 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_RESET 0x0
6448 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_GET(value) (((value) & 0x00000001) >> 0)
6450 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET(value) (((value) << 0) & 0x00000001)
6466 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_LSB 1
6468 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_MSB 1
6470 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_WIDTH 1
6472 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_SET_MSK 0x00000002
6474 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_CLR_MSK 0xfffffffd
6476 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_RESET 0x0
6478 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_GET(value) (((value) & 0x00000002) >> 1)
6480 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_PRBS_CTRL_SEL_SET(value) (((value) << 1) & 0x00000002)
6496 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_LSB 2
6498 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_MSB 2
6500 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_WIDTH 1
6502 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_SET_MSK 0x00000004
6504 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_CLR_MSK 0xfffffffb
6506 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_RESET 0x0
6508 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_GET(value) (((value) & 0x00000004) >> 2)
6510 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CB_SEQ_EN_FIX_EN_N_SET(value) (((value) << 2) & 0x00000004)
6526 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_LSB 3
6528 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_MSB 3
6530 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_WIDTH 1
6532 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_SET_MSK 0x00000008
6534 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_CLR_MSK 0xfffffff7
6536 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_RESET 0x0
6538 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_GET(value) (((value) & 0x00000008) >> 3)
6540 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_LOOPBACK_EN_SET(value) (((value) << 3) & 0x00000008)
6556 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_LSB 4
6558 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_MSB 4
6560 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_WIDTH 1
6562 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_SET_MSK 0x00000010
6564 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_CLR_MSK 0xffffffef
6566 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_RESET 0x0
6568 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_GET(value) (((value) & 0x00000010) >> 4)
6570 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_CMD_DRIVER_SEL_SET(value) (((value) << 4) & 0x00000010)
6585 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_LSB 5
6587 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_MSB 8
6589 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_WIDTH 4
6591 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_SET_MSK 0x000001e0
6593 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_CLR_MSK 0xfffffe1f
6595 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_RESET 0x0
6597 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_GET(value) (((value) & 0x000001e0) >> 5)
6599 #define ALT_MPFE_IOHMC_REG_DBGCFG0_CFG_DBG_MODE_SET(value) (((value) << 5) & 0x000001e0)
6601 #ifndef __ASSEMBLY__
6613 struct ALT_MPFE_IOHMC_REG_DBGCFG0_s
6615 volatile uint32_t cfg_wdata_driver_sel : 1;
6616 volatile uint32_t cfg_prbs_ctrl_sel : 1;
6617 volatile uint32_t cfg_cb_seq_en_fix_en_n : 1;
6618 volatile uint32_t cfg_loopback_en : 1;
6619 volatile uint32_t cfg_cmd_driver_sel : 1;
6620 volatile uint32_t cfg_dbg_mode : 4;
6625 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG0_s ALT_MPFE_IOHMC_REG_DBGCFG0_t;
6629 #define ALT_MPFE_IOHMC_REG_DBGCFG0_RESET 0x00000000
6631 #define ALT_MPFE_IOHMC_REG_DBGCFG0_OFST 0x0
6656 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_LSB 0
6658 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_MSB 31
6660 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_WIDTH 32
6662 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_SET_MSK 0xffffffff
6664 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_CLR_MSK 0x00000000
6666 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_RESET 0x0
6668 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_GET(value) (((value) & 0xffffffff) >> 0)
6670 #define ALT_MPFE_IOHMC_REG_DBGCFG1_CFG_DBG_CTRL_SET(value) (((value) << 0) & 0xffffffff)
6672 #ifndef __ASSEMBLY__
6684 struct ALT_MPFE_IOHMC_REG_DBGCFG1_s
6686 volatile uint32_t cfg_dbg_ctrl : 32;
6690 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG1_s ALT_MPFE_IOHMC_REG_DBGCFG1_t;
6694 #define ALT_MPFE_IOHMC_REG_DBGCFG1_RESET 0x00000000
6696 #define ALT_MPFE_IOHMC_REG_DBGCFG1_OFST 0x4
6721 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_LSB 0
6723 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_MSB 31
6725 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_WIDTH 32
6727 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_SET_MSK 0xffffffff
6729 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_CLR_MSK 0x00000000
6731 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_RESET 0x0
6733 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_GET(value) (((value) & 0xffffffff) >> 0)
6735 #define ALT_MPFE_IOHMC_REG_DBGCFG2_CFG_BIST_CMD0_U_SET(value) (((value) << 0) & 0xffffffff)
6737 #ifndef __ASSEMBLY__
6749 struct ALT_MPFE_IOHMC_REG_DBGCFG2_s
6751 volatile uint32_t cfg_bist_cmd0_u : 32;
6755 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG2_s ALT_MPFE_IOHMC_REG_DBGCFG2_t;
6759 #define ALT_MPFE_IOHMC_REG_DBGCFG2_RESET 0x00000000
6761 #define ALT_MPFE_IOHMC_REG_DBGCFG2_OFST 0x8
6786 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_LSB 0
6788 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_MSB 31
6790 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_WIDTH 32
6792 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_SET_MSK 0xffffffff
6794 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_CLR_MSK 0x00000000
6796 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_RESET 0x0
6798 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_GET(value) (((value) & 0xffffffff) >> 0)
6800 #define ALT_MPFE_IOHMC_REG_DBGCFG3_CFG_BIST_CMD0_L_SET(value) (((value) << 0) & 0xffffffff)
6802 #ifndef __ASSEMBLY__
6814 struct ALT_MPFE_IOHMC_REG_DBGCFG3_s
6816 volatile uint32_t cfg_bist_cmd0_l : 32;
6820 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG3_s ALT_MPFE_IOHMC_REG_DBGCFG3_t;
6824 #define ALT_MPFE_IOHMC_REG_DBGCFG3_RESET 0x00000000
6826 #define ALT_MPFE_IOHMC_REG_DBGCFG3_OFST 0xc
6851 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_LSB 0
6853 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_MSB 31
6855 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_WIDTH 32
6857 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_SET_MSK 0xffffffff
6859 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_CLR_MSK 0x00000000
6861 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_RESET 0x0
6863 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_GET(value) (((value) & 0xffffffff) >> 0)
6865 #define ALT_MPFE_IOHMC_REG_DBGCFG4_CFG_BIST_CMD1_U_SET(value) (((value) << 0) & 0xffffffff)
6867 #ifndef __ASSEMBLY__
6879 struct ALT_MPFE_IOHMC_REG_DBGCFG4_s
6881 volatile uint32_t cfg_bist_cmd1_u : 32;
6885 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG4_s ALT_MPFE_IOHMC_REG_DBGCFG4_t;
6889 #define ALT_MPFE_IOHMC_REG_DBGCFG4_RESET 0x00000000
6891 #define ALT_MPFE_IOHMC_REG_DBGCFG4_OFST 0x10
6916 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_LSB 0
6918 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_MSB 31
6920 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_WIDTH 32
6922 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_SET_MSK 0xffffffff
6924 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_CLR_MSK 0x00000000
6926 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_RESET 0x0
6928 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_GET(value) (((value) & 0xffffffff) >> 0)
6930 #define ALT_MPFE_IOHMC_REG_DBGCFG5_CFG_BIST_CMD1_L_SET(value) (((value) << 0) & 0xffffffff)
6932 #ifndef __ASSEMBLY__
6944 struct ALT_MPFE_IOHMC_REG_DBGCFG5_s
6946 volatile uint32_t cfg_bist_cmd1_l : 32;
6950 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG5_s ALT_MPFE_IOHMC_REG_DBGCFG5_t;
6954 #define ALT_MPFE_IOHMC_REG_DBGCFG5_RESET 0x00000000
6956 #define ALT_MPFE_IOHMC_REG_DBGCFG5_OFST 0x14
6982 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_LSB 0
6984 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_MSB 15
6986 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_WIDTH 16
6988 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_SET_MSK 0x0000ffff
6990 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_CLR_MSK 0xffff0000
6992 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_RESET 0x0
6994 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_GET(value) (((value) & 0x0000ffff) >> 0)
6996 #define ALT_MPFE_IOHMC_REG_DBGCFG6_CFG_DBG_OUT_SEL_SET(value) (((value) << 0) & 0x0000ffff)
6998 #ifndef __ASSEMBLY__
7010 struct ALT_MPFE_IOHMC_REG_DBGCFG6_s
7012 volatile uint32_t cfg_dbg_out_sel : 16;
7017 typedef struct ALT_MPFE_IOHMC_REG_DBGCFG6_s ALT_MPFE_IOHMC_REG_DBGCFG6_t;
7021 #define ALT_MPFE_IOHMC_REG_DBGCFG6_RESET 0x00000000
7023 #define ALT_MPFE_IOHMC_REG_DBGCFG6_OFST 0x18
7049 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_LSB 0
7051 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_MSB 15
7053 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_WIDTH 16
7055 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_SET_MSK 0x0000ffff
7057 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_CLR_MSK 0xffff0000
7059 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_RESET 0x0
7061 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_GET(value) (((value) & 0x0000ffff) >> 0)
7063 #define ALT_MPFE_IOHMC_REG_RESERVE0_CFG_RESERVE0_SET(value) (((value) << 0) & 0x0000ffff)
7065 #ifndef __ASSEMBLY__
7077 struct ALT_MPFE_IOHMC_REG_RESERVE0_s
7079 volatile uint32_t cfg_reserve0 : 16;
7084 typedef struct ALT_MPFE_IOHMC_REG_RESERVE0_s ALT_MPFE_IOHMC_REG_RESERVE0_t;
7088 #define ALT_MPFE_IOHMC_REG_RESERVE0_RESET 0x00000000
7090 #define ALT_MPFE_IOHMC_REG_RESERVE0_OFST 0x1c
7116 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_LSB 0
7118 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_MSB 15
7120 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_WIDTH 16
7122 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_SET_MSK 0x0000ffff
7124 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_CLR_MSK 0xffff0000
7126 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_RESET 0x0
7128 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_GET(value) (((value) & 0x0000ffff) >> 0)
7130 #define ALT_MPFE_IOHMC_REG_RESERVE1_CFG_RESERVE1_SET(value) (((value) << 0) & 0x0000ffff)
7132 #ifndef __ASSEMBLY__
7144 struct ALT_MPFE_IOHMC_REG_RESERVE1_s
7146 volatile uint32_t cfg_reserve1 : 16;
7151 typedef struct ALT_MPFE_IOHMC_REG_RESERVE1_s ALT_MPFE_IOHMC_REG_RESERVE1_t;
7155 #define ALT_MPFE_IOHMC_REG_RESERVE1_RESET 0x00000000
7157 #define ALT_MPFE_IOHMC_REG_RESERVE1_OFST 0x20
7183 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_LSB 0
7185 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_MSB 15
7187 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_WIDTH 16
7189 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_SET_MSK 0x0000ffff
7191 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_CLR_MSK 0xffff0000
7193 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_RESET 0x0
7195 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_GET(value) (((value) & 0x0000ffff) >> 0)
7197 #define ALT_MPFE_IOHMC_REG_RESERVE2_CFG_RESERVE2_SET(value) (((value) << 0) & 0x0000ffff)
7199 #ifndef __ASSEMBLY__
7211 struct ALT_MPFE_IOHMC_REG_RESERVE2_s
7213 volatile uint32_t cfg_reserve2 : 16;
7218 typedef struct ALT_MPFE_IOHMC_REG_RESERVE2_s ALT_MPFE_IOHMC_REG_RESERVE2_t;
7222 #define ALT_MPFE_IOHMC_REG_RESERVE2_RESET 0x00000000
7224 #define ALT_MPFE_IOHMC_REG_RESERVE2_OFST 0x24
7258 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_LSB 0
7260 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_MSB 3
7262 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_WIDTH 4
7264 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_SET_MSK 0x0000000f
7266 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_CLR_MSK 0xfffffff0
7268 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_RESET 0x0
7270 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_GET(value) (((value) & 0x0000000f) >> 0)
7272 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE_SET(value) (((value) << 0) & 0x0000000f)
7290 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_LSB 4
7292 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_MSB 6
7294 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_WIDTH 3
7296 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_SET_MSK 0x00000070
7298 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_CLR_MSK 0xffffff8f
7300 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_RESET 0x0
7302 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_GET(value) (((value) & 0x00000070) >> 4)
7304 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DIMM_TYPE_SET(value) (((value) << 4) & 0x00000070)
7321 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_LSB 7
7323 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_MSB 8
7325 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_WIDTH 2
7327 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_SET_MSK 0x00000180
7329 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_CLR_MSK 0xfffffe7f
7331 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_RESET 0x0
7333 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_GET(value) (((value) & 0x00000180) >> 7)
7335 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_AC_POS_SET(value) (((value) << 7) & 0x00000180)
7352 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_LSB 9
7354 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_MSB 13
7356 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_WIDTH 5
7358 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_SET_MSK 0x00003e00
7360 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_CLR_MSK 0xffffc1ff
7362 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_RESET 0x0
7364 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_GET(value) (((value) & 0x00003e00) >> 9)
7366 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_CTRL_BURST_LENGTH_SET(value) (((value) << 9) & 0x00003e00)
7383 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_LSB 14
7385 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_MSB 18
7387 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_WIDTH 5
7389 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_SET_MSK 0x0007c000
7391 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_CLR_MSK 0xfff83fff
7393 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_RESET 0x0
7395 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_GET(value) (((value) & 0x0007c000) >> 14)
7397 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC0_BURST_LENGTH_SET(value) (((value) << 14) & 0x0007c000)
7414 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_LSB 19
7416 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_MSB 23
7418 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_WIDTH 5
7420 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_SET_MSK 0x00f80000
7422 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_CLR_MSK 0xff07ffff
7424 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_RESET 0x0
7426 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_GET(value) (((value) & 0x00f80000) >> 19)
7428 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC1_BURST_LENGTH_SET(value) (((value) << 19) & 0x00f80000)
7445 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_LSB 24
7447 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_MSB 28
7449 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_WIDTH 5
7451 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_SET_MSK 0x1f000000
7453 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_CLR_MSK 0xe0ffffff
7455 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_RESET 0x0
7457 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_GET(value) (((value) & 0x1f000000) >> 24)
7459 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_CFG_DBC2_BURST_LENGTH_SET(value) (((value) << 24) & 0x1f000000)
7461 #ifndef __ASSEMBLY__
7473 struct ALT_MPFE_IOHMC_REG_CTRLCFG0_s
7475 volatile uint32_t cfg_mem_type : 4;
7476 volatile uint32_t cfg_dimm_type : 3;
7477 volatile uint32_t cfg_ac_pos : 2;
7478 volatile uint32_t cfg_ctrl_burst_length : 5;
7479 volatile uint32_t cfg_dbc0_burst_length : 5;
7480 volatile uint32_t cfg_dbc1_burst_length : 5;
7481 volatile uint32_t cfg_dbc2_burst_length : 5;
7486 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG0_s ALT_MPFE_IOHMC_REG_CTRLCFG0_t;
7490 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_RESET 0x00000000
7492 #define ALT_MPFE_IOHMC_REG_CTRLCFG0_OFST 0x28
7540 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_LSB 0
7542 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_MSB 4
7544 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_WIDTH 5
7546 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_SET_MSK 0x0000001f
7548 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_CLR_MSK 0xffffffe0
7550 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_RESET 0x0
7552 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_GET(value) (((value) & 0x0000001f) >> 0)
7554 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_BURST_LENGTH_SET(value) (((value) << 0) & 0x0000001f)
7573 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_LSB 5
7575 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_MSB 6
7577 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_WIDTH 2
7579 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_SET_MSK 0x00000060
7581 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_CLR_MSK 0xffffff9f
7583 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_RESET 0x0
7585 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_GET(value) (((value) & 0x00000060) >> 5)
7587 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_ADDR_ORDER_SET(value) (((value) << 5) & 0x00000060)
7602 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_LSB 7
7604 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_MSB 7
7606 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_WIDTH 1
7608 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_SET_MSK 0x00000080
7610 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_CLR_MSK 0xffffff7f
7612 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_RESET 0x0
7614 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_GET(value) (((value) & 0x00000080) >> 7)
7616 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_ECC_SET(value) (((value) << 7) & 0x00000080)
7631 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_LSB 8
7633 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_MSB 8
7635 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_WIDTH 1
7637 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_SET_MSK 0x00000100
7639 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_CLR_MSK 0xfffffeff
7641 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_RESET 0x0
7643 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_GET(value) (((value) & 0x00000100) >> 8)
7645 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_ECC_SET(value) (((value) << 8) & 0x00000100)
7660 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_LSB 9
7662 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_MSB 9
7664 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_WIDTH 1
7666 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_SET_MSK 0x00000200
7668 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_CLR_MSK 0xfffffdff
7670 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_RESET 0x0
7672 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_GET(value) (((value) & 0x00000200) >> 9)
7674 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_ECC_SET(value) (((value) << 9) & 0x00000200)
7689 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_LSB 10
7691 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_MSB 10
7693 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_WIDTH 1
7695 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_SET_MSK 0x00000400
7697 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_CLR_MSK 0xfffffbff
7699 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_RESET 0x0
7701 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_GET(value) (((value) & 0x00000400) >> 10)
7703 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_ECC_SET(value) (((value) << 10) & 0x00000400)
7718 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_LSB 11
7720 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_MSB 11
7722 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_WIDTH 1
7724 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_SET_MSK 0x00000800
7726 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_CLR_MSK 0xfffff7ff
7728 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_RESET 0x0
7730 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_GET(value) (((value) & 0x00000800) >> 11)
7732 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_ECC_SET(value) (((value) << 11) & 0x00000800)
7748 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_LSB 12
7750 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_MSB 12
7752 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_WIDTH 1
7754 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_SET_MSK 0x00001000
7756 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_CLR_MSK 0xffffefff
7758 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_RESET 0x0
7760 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_GET(value) (((value) & 0x00001000) >> 12)
7762 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_DATA_SET(value) (((value) << 12) & 0x00001000)
7778 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_LSB 13
7780 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_MSB 13
7782 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_WIDTH 1
7784 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_SET_MSK 0x00002000
7786 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_CLR_MSK 0xffffdfff
7788 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_RESET 0x0
7790 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_GET(value) (((value) & 0x00002000) >> 13)
7792 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_REORDER_RDATA_SET(value) (((value) << 13) & 0x00002000)
7808 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_LSB 14
7810 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_MSB 14
7812 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_WIDTH 1
7814 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_SET_MSK 0x00004000
7816 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_CLR_MSK 0xffffbfff
7818 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_RESET 0x0
7820 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_GET(value) (((value) & 0x00004000) >> 14)
7822 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_REORDER_RDATA_SET(value) (((value) << 14) & 0x00004000)
7838 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_LSB 15
7840 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_MSB 15
7842 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_WIDTH 1
7844 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_SET_MSK 0x00008000
7846 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_CLR_MSK 0xffff7fff
7848 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_RESET 0x0
7850 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_GET(value) (((value) & 0x00008000) >> 15)
7852 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_REORDER_RDATA_SET(value) (((value) << 15) & 0x00008000)
7868 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_LSB 16
7870 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_MSB 16
7872 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_WIDTH 1
7874 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_SET_MSK 0x00010000
7876 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_CLR_MSK 0xfffeffff
7878 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_RESET 0x0
7880 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_GET(value) (((value) & 0x00010000) >> 16)
7882 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_REORDER_RDATA_SET(value) (((value) << 16) & 0x00010000)
7898 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_LSB 17
7900 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_MSB 17
7902 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_WIDTH 1
7904 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_SET_MSK 0x00020000
7906 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_CLR_MSK 0xfffdffff
7908 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_RESET 0x0
7910 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_GET(value) (((value) & 0x00020000) >> 17)
7912 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_REORDER_RDATA_SET(value) (((value) << 17) & 0x00020000)
7928 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_LSB 18
7930 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_MSB 18
7932 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_WIDTH 1
7934 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_SET_MSK 0x00040000
7936 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_CLR_MSK 0xfffbffff
7938 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_RESET 0x0
7940 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_GET(value) (((value) & 0x00040000) >> 18)
7942 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_REORDER_READ_SET(value) (((value) << 18) & 0x00040000)
7959 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_LSB 19
7961 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_MSB 24
7963 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_WIDTH 6
7965 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_SET_MSK 0x01f80000
7967 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_CLR_MSK 0xfe07ffff
7969 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_RESET 0x0
7971 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_GET(value) (((value) & 0x01f80000) >> 19)
7973 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_STARVE_LIMIT_SET(value) (((value) << 19) & 0x01f80000)
7996 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_LSB 25
7998 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_MSB 25
8000 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_WIDTH 1
8002 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_SET_MSK 0x02000000
8004 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_CLR_MSK 0xfdffffff
8006 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_RESET 0x0
8008 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_GET(value) (((value) & 0x02000000) >> 25)
8010 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DQSTRK_EN_SET(value) (((value) << 25) & 0x02000000)
8025 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_LSB 26
8027 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_MSB 26
8029 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_WIDTH 1
8031 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_SET_MSK 0x04000000
8033 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_CLR_MSK 0xfbffffff
8035 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_RESET 0x0
8037 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_GET(value) (((value) & 0x04000000) >> 26)
8039 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_CTRL_ENABLE_DM_SET(value) (((value) << 26) & 0x04000000)
8054 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_LSB 27
8056 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_MSB 27
8058 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_WIDTH 1
8060 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_SET_MSK 0x08000000
8062 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_CLR_MSK 0xf7ffffff
8064 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_RESET 0x0
8066 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_GET(value) (((value) & 0x08000000) >> 27)
8068 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC0_ENABLE_DM_SET(value) (((value) << 27) & 0x08000000)
8083 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_LSB 28
8085 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_MSB 28
8087 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_WIDTH 1
8089 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_SET_MSK 0x10000000
8091 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_CLR_MSK 0xefffffff
8093 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_RESET 0x0
8095 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_GET(value) (((value) & 0x10000000) >> 28)
8097 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC1_ENABLE_DM_SET(value) (((value) << 28) & 0x10000000)
8112 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_LSB 29
8114 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_MSB 29
8116 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_WIDTH 1
8118 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_SET_MSK 0x20000000
8120 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_CLR_MSK 0xdfffffff
8122 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_RESET 0x0
8124 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_GET(value) (((value) & 0x20000000) >> 29)
8126 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC2_ENABLE_DM_SET(value) (((value) << 29) & 0x20000000)
8141 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_LSB 30
8143 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_MSB 30
8145 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_WIDTH 1
8147 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_SET_MSK 0x40000000
8149 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_CLR_MSK 0xbfffffff
8151 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_RESET 0x0
8153 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_GET(value) (((value) & 0x40000000) >> 30)
8155 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_CFG_DBC3_ENABLE_DM_SET(value) (((value) << 30) & 0x40000000)
8157 #ifndef __ASSEMBLY__
8169 struct ALT_MPFE_IOHMC_REG_CTRLCFG1_s
8171 volatile uint32_t cfg_dbc3_burst_length : 5;
8172 volatile uint32_t cfg_addr_order : 2;
8173 volatile uint32_t cfg_ctrl_enable_ecc : 1;
8174 volatile uint32_t cfg_dbc0_enable_ecc : 1;
8175 volatile uint32_t cfg_dbc1_enable_ecc : 1;
8176 volatile uint32_t cfg_dbc2_enable_ecc : 1;
8177 volatile uint32_t cfg_dbc3_enable_ecc : 1;
8178 volatile uint32_t cfg_reorder_data : 1;
8179 volatile uint32_t cfg_ctrl_reorder_rdata : 1;
8180 volatile uint32_t cfg_dbc0_reorder_rdata : 1;
8181 volatile uint32_t cfg_dbc1_reorder_rdata : 1;
8182 volatile uint32_t cfg_dbc2_reorder_rdata : 1;
8183 volatile uint32_t cfg_dbc3_reorder_rdata : 1;
8184 volatile uint32_t cfg_reorder_read : 1;
8185 volatile uint32_t cfg_starve_limit : 6;
8186 volatile uint32_t cfg_dqstrk_en : 1;
8187 volatile uint32_t cfg_ctrl_enable_dm : 1;
8188 volatile uint32_t cfg_dbc0_enable_dm : 1;
8189 volatile uint32_t cfg_dbc1_enable_dm : 1;
8190 volatile uint32_t cfg_dbc2_enable_dm : 1;
8191 volatile uint32_t cfg_dbc3_enable_dm : 1;
8196 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG1_s ALT_MPFE_IOHMC_REG_CTRLCFG1_t;
8200 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_RESET 0x00000000
8202 #define ALT_MPFE_IOHMC_REG_CTRLCFG1_OFST 0x2c
8243 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_LSB 0
8245 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_MSB 0
8247 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_WIDTH 1
8249 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_SET_MSK 0x00000001
8251 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_CLR_MSK 0xfffffffe
8253 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_RESET 0x0
8255 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_GET(value) (((value) & 0x00000001) >> 0)
8257 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL_OUTPUT_REGD_SET(value) (((value) << 0) & 0x00000001)
8272 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_LSB 1
8274 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_MSB 1
8276 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_WIDTH 1
8278 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_SET_MSK 0x00000002
8280 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_CLR_MSK 0xfffffffd
8282 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_RESET 0x0
8284 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_GET(value) (((value) & 0x00000002) >> 1)
8286 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_OUTPUT_REGD_SET(value) (((value) << 1) & 0x00000002)
8301 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_LSB 2
8303 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_MSB 2
8305 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_WIDTH 1
8307 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_SET_MSK 0x00000004
8309 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_CLR_MSK 0xfffffffb
8311 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_RESET 0x0
8313 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_GET(value) (((value) & 0x00000004) >> 2)
8315 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_OUTPUT_REGD_SET(value) (((value) << 2) & 0x00000004)
8330 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_LSB 3
8332 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_MSB 3
8334 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_WIDTH 1
8336 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_SET_MSK 0x00000008
8338 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_CLR_MSK 0xfffffff7
8340 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_RESET 0x0
8342 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_GET(value) (((value) & 0x00000008) >> 3)
8344 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_OUTPUT_REGD_SET(value) (((value) << 3) & 0x00000008)
8359 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_LSB 4
8361 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_MSB 4
8363 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_WIDTH 1
8365 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_SET_MSK 0x00000010
8367 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_CLR_MSK 0xffffffef
8369 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_RESET 0x0
8371 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_GET(value) (((value) & 0x00000010) >> 4)
8373 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_OUTPUT_REGD_SET(value) (((value) << 4) & 0x00000010)
8390 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_LSB 5
8392 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_MSB 6
8394 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_WIDTH 2
8396 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_SET_MSK 0x00000060
8398 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_CLR_MSK 0xffffff9f
8400 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_RESET 0x0
8402 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_GET(value) (((value) & 0x00000060) >> 5)
8404 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH0_SET(value) (((value) << 5) & 0x00000060)
8421 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_LSB 7
8423 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_MSB 8
8425 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_WIDTH 2
8427 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_SET_MSK 0x00000180
8429 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_CLR_MSK 0xfffffe7f
8431 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_RESET 0x0
8433 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_GET(value) (((value) & 0x00000180) >> 7)
8435 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_CTRL2DBC_SWITCH1_SET(value) (((value) << 7) & 0x00000180)
8451 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_LSB 9
8453 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_MSB 9
8455 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_WIDTH 1
8457 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_SET_MSK 0x00000200
8459 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_CLR_MSK 0xfffffdff
8461 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_RESET 0x0
8463 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_GET(value) (((value) & 0x00000200) >> 9)
8465 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_CTRL_SEL_SET(value) (((value) << 9) & 0x00000200)
8481 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_LSB 10
8483 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_MSB 10
8485 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_WIDTH 1
8487 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_SET_MSK 0x00000400
8489 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_CLR_MSK 0xfffffbff
8491 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_RESET 0x0
8493 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_GET(value) (((value) & 0x00000400) >> 10)
8495 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_CTRL_SEL_SET(value) (((value) << 10) & 0x00000400)
8511 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_LSB 11
8513 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_MSB 11
8515 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_WIDTH 1
8517 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_SET_MSK 0x00000800
8519 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_CLR_MSK 0xfffff7ff
8521 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_RESET 0x0
8523 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_GET(value) (((value) & 0x00000800) >> 11)
8525 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_CTRL_SEL_SET(value) (((value) << 11) & 0x00000800)
8541 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_LSB 12
8543 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_MSB 12
8545 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_WIDTH 1
8547 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_SET_MSK 0x00001000
8549 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_CLR_MSK 0xffffefff
8551 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_RESET 0x0
8553 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_GET(value) (((value) & 0x00001000) >> 12)
8555 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_CTRL_SEL_SET(value) (((value) << 12) & 0x00001000)
8571 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_LSB 13
8573 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_MSB 14
8575 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_WIDTH 2
8577 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_SET_MSK 0x00006000
8579 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_CLR_MSK 0xffff9fff
8581 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_RESET 0x0
8583 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_GET(value) (((value) & 0x00006000) >> 13)
8585 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2CTRL_SEL_SET(value) (((value) << 13) & 0x00006000)
8601 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_LSB 15
8603 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_MSB 17
8605 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_WIDTH 3
8607 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_SET_MSK 0x00038000
8609 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_CLR_MSK 0xfffc7fff
8611 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_RESET 0x0
8613 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_GET(value) (((value) & 0x00038000) >> 15)
8615 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC0_PIPE_LAT_SET(value) (((value) << 15) & 0x00038000)
8631 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_LSB 18
8633 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_MSB 20
8635 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_WIDTH 3
8637 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_SET_MSK 0x001c0000
8639 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_CLR_MSK 0xffe3ffff
8641 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_RESET 0x0
8643 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_GET(value) (((value) & 0x001c0000) >> 18)
8645 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC1_PIPE_LAT_SET(value) (((value) << 18) & 0x001c0000)
8661 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_LSB 21
8663 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_MSB 23
8665 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_WIDTH 3
8667 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_SET_MSK 0x00e00000
8669 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_CLR_MSK 0xff1fffff
8671 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_RESET 0x0
8673 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_GET(value) (((value) & 0x00e00000) >> 21)
8675 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC2_PIPE_LAT_SET(value) (((value) << 21) & 0x00e00000)
8691 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_LSB 24
8693 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_MSB 26
8695 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_WIDTH 3
8697 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_SET_MSK 0x07000000
8699 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_CLR_MSK 0xf8ffffff
8701 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_RESET 0x0
8703 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_GET(value) (((value) & 0x07000000) >> 24)
8705 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_CFG_DBC3_PIPE_LAT_SET(value) (((value) << 24) & 0x07000000)
8707 #ifndef __ASSEMBLY__
8719 struct ALT_MPFE_IOHMC_REG_CTRLCFG2_s
8721 volatile uint32_t cfg_ctrl_output_regd : 1;
8722 volatile uint32_t cfg_dbc0_output_regd : 1;
8723 volatile uint32_t cfg_dbc1_output_regd : 1;
8724 volatile uint32_t cfg_dbc2_output_regd : 1;
8725 volatile uint32_t cfg_dbc3_output_regd : 1;
8726 volatile uint32_t cfg_ctrl2dbc_switch0 : 2;
8727 volatile uint32_t cfg_ctrl2dbc_switch1 : 2;
8728 volatile uint32_t cfg_dbc0_ctrl_sel : 1;
8729 volatile uint32_t cfg_dbc1_ctrl_sel : 1;
8730 volatile uint32_t cfg_dbc2_ctrl_sel : 1;
8731 volatile uint32_t cfg_dbc3_ctrl_sel : 1;
8732 volatile uint32_t cfg_dbc2ctrl_sel : 2;
8733 volatile uint32_t cfg_dbc0_pipe_lat : 3;
8734 volatile uint32_t cfg_dbc1_pipe_lat : 3;
8735 volatile uint32_t cfg_dbc2_pipe_lat : 3;
8736 volatile uint32_t cfg_dbc3_pipe_lat : 3;
8741 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG2_s ALT_MPFE_IOHMC_REG_CTRLCFG2_t;
8745 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_RESET 0x00000000
8747 #define ALT_MPFE_IOHMC_REG_CTRLCFG2_OFST 0x30
8794 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_LSB 0
8796 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_MSB 2
8798 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_WIDTH 3
8800 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_SET_MSK 0x00000007
8802 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_CLR_MSK 0xfffffff8
8804 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_RESET 0x0
8806 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_GET(value) (((value) & 0x00000007) >> 0)
8808 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_CMD_RATE_SET(value) (((value) << 0) & 0x00000007)
8824 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_LSB 3
8826 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_MSB 5
8828 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_WIDTH 3
8830 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_SET_MSK 0x00000038
8832 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_CLR_MSK 0xffffffc7
8834 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_RESET 0x0
8836 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_GET(value) (((value) & 0x00000038) >> 3)
8838 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_CMD_RATE_SET(value) (((value) << 3) & 0x00000038)
8854 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_LSB 6
8856 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_MSB 8
8858 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_WIDTH 3
8860 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_SET_MSK 0x000001c0
8862 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_CLR_MSK 0xfffffe3f
8864 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_RESET 0x0
8866 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_GET(value) (((value) & 0x000001c0) >> 6)
8868 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_CMD_RATE_SET(value) (((value) << 6) & 0x000001c0)
8884 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_LSB 9
8886 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_MSB 11
8888 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_WIDTH 3
8890 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_SET_MSK 0x00000e00
8892 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_CLR_MSK 0xfffff1ff
8894 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_RESET 0x0
8896 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_GET(value) (((value) & 0x00000e00) >> 9)
8898 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_CMD_RATE_SET(value) (((value) << 9) & 0x00000e00)
8914 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_LSB 12
8916 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_MSB 14
8918 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_WIDTH 3
8920 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_SET_MSK 0x00007000
8922 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_CLR_MSK 0xffff8fff
8924 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_RESET 0x0
8926 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_GET(value) (((value) & 0x00007000) >> 12)
8928 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_CMD_RATE_SET(value) (((value) << 12) & 0x00007000)
8943 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_LSB 15
8945 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_MSB 15
8947 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_WIDTH 1
8949 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_SET_MSK 0x00008000
8951 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_CLR_MSK 0xffff7fff
8953 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_RESET 0x0
8955 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_GET(value) (((value) & 0x00008000) >> 15)
8957 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_IN_PROTOCOL_SET(value) (((value) << 15) & 0x00008000)
8972 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_LSB 16
8974 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_MSB 16
8976 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_WIDTH 1
8978 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_SET_MSK 0x00010000
8980 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_CLR_MSK 0xfffeffff
8982 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_RESET 0x0
8984 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_GET(value) (((value) & 0x00010000) >> 16)
8986 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_IN_PROTOCOL_SET(value) (((value) << 16) & 0x00010000)
9001 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_LSB 17
9003 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_MSB 17
9005 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_WIDTH 1
9007 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_SET_MSK 0x00020000
9009 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_CLR_MSK 0xfffdffff
9011 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_RESET 0x0
9013 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_GET(value) (((value) & 0x00020000) >> 17)
9015 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_IN_PROTOCOL_SET(value) (((value) << 17) & 0x00020000)
9030 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_LSB 18
9032 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_MSB 18
9034 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_WIDTH 1
9036 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_SET_MSK 0x00040000
9038 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_CLR_MSK 0xfffbffff
9040 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_RESET 0x0
9042 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_GET(value) (((value) & 0x00040000) >> 18)
9044 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_IN_PROTOCOL_SET(value) (((value) << 18) & 0x00040000)
9059 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_LSB 19
9061 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_MSB 19
9063 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_WIDTH 1
9065 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_SET_MSK 0x00080000
9067 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_CLR_MSK 0xfff7ffff
9069 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_RESET 0x0
9071 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_GET(value) (((value) & 0x00080000) >> 19)
9073 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_IN_PROTOCOL_SET(value) (((value) << 19) & 0x00080000)
9088 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_LSB 20
9090 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_MSB 20
9092 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_WIDTH 1
9094 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_SET_MSK 0x00100000
9096 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_CLR_MSK 0xffefffff
9098 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_RESET 0x0
9100 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_GET(value) (((value) & 0x00100000) >> 20)
9102 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CTRL_DUALPORT_EN_SET(value) (((value) << 20) & 0x00100000)
9117 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_LSB 21
9119 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_MSB 21
9121 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_WIDTH 1
9123 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_SET_MSK 0x00200000
9125 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_CLR_MSK 0xffdfffff
9127 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_RESET 0x0
9129 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_GET(value) (((value) & 0x00200000) >> 21)
9131 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC0_DUALPORT_EN_SET(value) (((value) << 21) & 0x00200000)
9146 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_LSB 22
9148 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_MSB 22
9150 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_WIDTH 1
9152 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_SET_MSK 0x00400000
9154 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_CLR_MSK 0xffbfffff
9156 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_RESET 0x0
9158 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_GET(value) (((value) & 0x00400000) >> 22)
9160 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC1_DUALPORT_EN_SET(value) (((value) << 22) & 0x00400000)
9175 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_LSB 23
9177 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_MSB 23
9179 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_WIDTH 1
9181 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_SET_MSK 0x00800000
9183 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_CLR_MSK 0xff7fffff
9185 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_RESET 0x0
9187 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_GET(value) (((value) & 0x00800000) >> 23)
9189 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC2_DUALPORT_EN_SET(value) (((value) << 23) & 0x00800000)
9204 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_LSB 24
9206 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_MSB 24
9208 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_WIDTH 1
9210 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_SET_MSK 0x01000000
9212 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_CLR_MSK 0xfeffffff
9214 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_RESET 0x0
9216 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_GET(value) (((value) & 0x01000000) >> 24)
9218 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_DBC3_DUALPORT_EN_SET(value) (((value) << 24) & 0x01000000)
9237 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_LSB 25
9239 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_MSB 25
9241 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_WIDTH 1
9243 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_SET_MSK 0x02000000
9245 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_CLR_MSK 0xfdffffff
9247 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_RESET 0x0
9249 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_GET(value) (((value) & 0x02000000) >> 25)
9251 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_ARBITER_TYPE_SET(value) (((value) << 25) & 0x02000000)
9268 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_LSB 26
9270 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_MSB 26
9272 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_WIDTH 1
9274 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_SET_MSK 0x04000000
9276 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_CLR_MSK 0xfbffffff
9278 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_RESET 0x0
9280 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_GET(value) (((value) & 0x04000000) >> 26)
9282 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_OPEN_PAGE_EN_SET(value) (((value) << 26) & 0x04000000)
9297 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_LSB 27
9299 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_MSB 27
9301 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_WIDTH 1
9303 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_SET_MSK 0x08000000
9305 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_CLR_MSK 0xf7ffffff
9307 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_RESET 0x0
9309 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_GET(value) (((value) & 0x08000000) >> 27)
9311 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_GEARDN_EN_SET(value) (((value) << 27) & 0x08000000)
9330 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_LSB 28
9332 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_MSB 28
9334 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_WIDTH 1
9336 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_SET_MSK 0x10000000
9338 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_CLR_MSK 0xefffffff
9340 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_RESET 0x0
9342 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_GET(value) (((value) & 0x10000000) >> 28)
9344 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_3DSREF_ACK_ON_DONE_SET(value) (((value) << 28) & 0x10000000)
9363 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_LSB 30
9365 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_MSB 30
9367 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_WIDTH 1
9369 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_SET_MSK 0x40000000
9371 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_CLR_MSK 0xbfffffff
9373 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_RESET 0x0
9375 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_GET(value) (((value) & 0x40000000) >> 30)
9377 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_CFG_CB_MEMCLK_GATE_DEFAULT_SET(value) (((value) << 30) & 0x40000000)
9379 #ifndef __ASSEMBLY__
9391 struct ALT_MPFE_IOHMC_REG_CTRLCFG3_s
9393 volatile uint32_t cfg_ctrl_cmd_rate : 3;
9394 volatile uint32_t cfg_dbc0_cmd_rate : 3;
9395 volatile uint32_t cfg_dbc1_cmd_rate : 3;
9396 volatile uint32_t cfg_dbc2_cmd_rate : 3;
9397 volatile uint32_t cfg_dbc3_cmd_rate : 3;
9398 volatile uint32_t cfg_ctrl_in_protocol : 1;
9399 volatile uint32_t cfg_dbc0_in_protocol : 1;
9400 volatile uint32_t cfg_dbc1_in_protocol : 1;
9401 volatile uint32_t cfg_dbc2_in_protocol : 1;
9402 volatile uint32_t cfg_dbc3_in_protocol : 1;
9403 volatile uint32_t cfg_ctrl_dualport_en : 1;
9404 volatile uint32_t cfg_dbc0_dualport_en : 1;
9405 volatile uint32_t cfg_dbc1_dualport_en : 1;
9406 volatile uint32_t cfg_dbc2_dualport_en : 1;
9407 volatile uint32_t cfg_dbc3_dualport_en : 1;
9408 volatile uint32_t cfg_arbiter_type : 1;
9409 volatile uint32_t cfg_open_page_en : 1;
9410 volatile uint32_t cfg_geardn_en : 1;
9411 volatile uint32_t cfg_3dsref_ack_on_done : 1;
9413 volatile uint32_t cfg_cb_memclk_gate_default : 1;
9418 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG3_s ALT_MPFE_IOHMC_REG_CTRLCFG3_t;
9422 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_RESET 0x00000000
9424 #define ALT_MPFE_IOHMC_REG_CTRLCFG3_OFST 0x34
9460 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_LSB 0
9462 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_MSB 4
9464 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_WIDTH 5
9466 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_SET_MSK 0x0000001f
9468 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_CLR_MSK 0xffffffe0
9470 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_RESET 0x0
9472 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_GET(value) (((value) & 0x0000001f) >> 0)
9474 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_TILE_ID_SET(value) (((value) << 0) & 0x0000001f)
9490 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_LSB 5
9492 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_MSB 6
9494 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_WIDTH 2
9496 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_SET_MSK 0x00000060
9498 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_CLR_MSK 0xffffff9f
9500 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_RESET 0x0
9502 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_GET(value) (((value) & 0x00000060) >> 5)
9504 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_PINGPONG_MODE_SET(value) (((value) << 5) & 0x00000060)
9523 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_LSB 7
9525 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_MSB 9
9527 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_WIDTH 3
9529 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_SET_MSK 0x00000380
9531 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_CLR_MSK 0xfffffc7f
9533 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_RESET 0x0
9535 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_GET(value) (((value) & 0x00000380) >> 7)
9537 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_ROTATE_EN_SET(value) (((value) << 7) & 0x00000380)
9556 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_LSB 10
9558 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_MSB 12
9560 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_WIDTH 3
9562 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET_MSK 0x00001c00
9564 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_CLR_MSK 0xffffe3ff
9566 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_RESET 0x0
9568 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_GET(value) (((value) & 0x00001c00) >> 10)
9570 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET(value) (((value) << 10) & 0x00001c00)
9589 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_LSB 13
9591 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_MSB 15
9593 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_WIDTH 3
9595 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET_MSK 0x0000e000
9597 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_CLR_MSK 0xffff1fff
9599 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_RESET 0x0
9601 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_GET(value) (((value) & 0x0000e000) >> 13)
9603 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET(value) (((value) << 13) & 0x0000e000)
9622 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_LSB 16
9624 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_MSB 18
9626 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_WIDTH 3
9628 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET_MSK 0x00070000
9630 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_CLR_MSK 0xfff8ffff
9632 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_RESET 0x0
9634 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_GET(value) (((value) & 0x00070000) >> 16)
9636 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET(value) (((value) << 16) & 0x00070000)
9655 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_LSB 19
9657 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_MSB 21
9659 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_WIDTH 3
9661 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET_MSK 0x00380000
9663 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_CLR_MSK 0xffc7ffff
9665 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_RESET 0x0
9667 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_GET(value) (((value) & 0x00380000) >> 19)
9669 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET(value) (((value) << 19) & 0x00380000)
9697 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_LSB 22
9699 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_MSB 23
9701 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_WIDTH 2
9703 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_SET_MSK 0x00c00000
9705 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_CLR_MSK 0xff3fffff
9707 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_RESET 0x0
9709 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_GET(value) (((value) & 0x00c00000) >> 22)
9711 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_CTRL_SLOT_OFFSET_SET(value) (((value) << 22) & 0x00c00000)
9739 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_LSB 24
9741 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_MSB 25
9743 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_WIDTH 2
9745 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_SET_MSK 0x03000000
9747 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_CLR_MSK 0xfcffffff
9749 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_RESET 0x0
9751 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_GET(value) (((value) & 0x03000000) >> 24)
9753 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC0_SLOT_OFFSET_SET(value) (((value) << 24) & 0x03000000)
9781 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_LSB 26
9783 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_MSB 27
9785 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_WIDTH 2
9787 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_SET_MSK 0x0c000000
9789 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_CLR_MSK 0xf3ffffff
9791 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_RESET 0x0
9793 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_GET(value) (((value) & 0x0c000000) >> 26)
9795 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC1_SLOT_OFFSET_SET(value) (((value) << 26) & 0x0c000000)
9823 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_LSB 28
9825 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_MSB 29
9827 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_WIDTH 2
9829 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_SET_MSK 0x30000000
9831 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_CLR_MSK 0xcfffffff
9833 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_RESET 0x0
9835 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_GET(value) (((value) & 0x30000000) >> 28)
9837 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC2_SLOT_OFFSET_SET(value) (((value) << 28) & 0x30000000)
9865 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_LSB 30
9867 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_MSB 31
9869 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_WIDTH 2
9871 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_SET_MSK 0xc0000000
9873 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_CLR_MSK 0x3fffffff
9875 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_RESET 0x0
9877 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_GET(value) (((value) & 0xc0000000) >> 30)
9879 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_CFG_DBC3_SLOT_OFFSET_SET(value) (((value) << 30) & 0xc0000000)
9881 #ifndef __ASSEMBLY__
9893 struct ALT_MPFE_IOHMC_REG_CTRLCFG4_s
9895 volatile uint32_t cfg_tile_id : 5;
9896 volatile uint32_t cfg_pingpong_mode : 2;
9897 volatile uint32_t cfg_ctrl_slot_rotate_en : 3;
9898 volatile uint32_t cfg_dbc0_slot_rotate_en : 3;
9899 volatile uint32_t cfg_dbc1_slot_rotate_en : 3;
9900 volatile uint32_t cfg_dbc2_slot_rotate_en : 3;
9901 volatile uint32_t cfg_dbc3_slot_rotate_en : 3;
9902 volatile uint32_t cfg_ctrl_slot_offset : 2;
9903 volatile uint32_t cfg_dbc0_slot_offset : 2;
9904 volatile uint32_t cfg_dbc1_slot_offset : 2;
9905 volatile uint32_t cfg_dbc2_slot_offset : 2;
9906 volatile uint32_t cfg_dbc3_slot_offset : 2;
9910 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG4_s ALT_MPFE_IOHMC_REG_CTRLCFG4_t;
9914 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_RESET 0x00000000
9916 #define ALT_MPFE_IOHMC_REG_CTRLCFG4_OFST 0x38
9948 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_LSB 0
9950 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_MSB 3
9952 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_WIDTH 4
9954 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_SET_MSK 0x0000000f
9956 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_CLR_MSK 0xfffffff0
9958 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_RESET 0x0
9960 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_GET(value) (((value) & 0x0000000f) >> 0)
9962 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_COL_CMD_SLOT_SET(value) (((value) << 0) & 0x0000000f)
9977 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_LSB 4
9979 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_MSB 7
9981 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_WIDTH 4
9983 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_SET_MSK 0x000000f0
9985 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_CLR_MSK 0xffffff0f
9987 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_RESET 0x0
9989 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_GET(value) (((value) & 0x000000f0) >> 4)
9991 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_ROW_CMD_SLOT_SET(value) (((value) << 4) & 0x000000f0)
10007 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_LSB 8
10009 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_MSB 8
10011 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_WIDTH 1
10013 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_SET_MSK 0x00000100
10015 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_CLR_MSK 0xfffffeff
10017 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_RESET 0x0
10019 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_GET(value) (((value) & 0x00000100) >> 8)
10021 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_CTRL_RC_EN_SET(value) (((value) << 8) & 0x00000100)
10037 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_LSB 9
10039 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_MSB 9
10041 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_WIDTH 1
10043 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_SET_MSK 0x00000200
10045 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_CLR_MSK 0xfffffdff
10047 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_RESET 0x0
10049 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_GET(value) (((value) & 0x00000200) >> 9)
10051 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC0_RC_EN_SET(value) (((value) << 9) & 0x00000200)
10067 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_LSB 10
10069 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_MSB 10
10071 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_WIDTH 1
10073 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_SET_MSK 0x00000400
10075 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_CLR_MSK 0xfffffbff
10077 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_RESET 0x0
10079 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_GET(value) (((value) & 0x00000400) >> 10)
10081 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC1_RC_EN_SET(value) (((value) << 10) & 0x00000400)
10097 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_LSB 11
10099 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_MSB 11
10101 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_WIDTH 1
10103 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_SET_MSK 0x00000800
10105 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_CLR_MSK 0xfffff7ff
10107 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_RESET 0x0
10109 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_GET(value) (((value) & 0x00000800) >> 11)
10111 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC2_RC_EN_SET(value) (((value) << 11) & 0x00000800)
10127 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_LSB 12
10129 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_MSB 12
10131 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_WIDTH 1
10133 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_SET_MSK 0x00001000
10135 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_CLR_MSK 0xffffefff
10137 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_RESET 0x0
10139 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_GET(value) (((value) & 0x00001000) >> 12)
10141 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_CFG_DBC3_RC_EN_SET(value) (((value) << 12) & 0x00001000)
10143 #ifndef __ASSEMBLY__
10155 struct ALT_MPFE_IOHMC_REG_CTRLCFG5_s
10157 volatile uint32_t cfg_col_cmd_slot : 4;
10158 volatile uint32_t cfg_row_cmd_slot : 4;
10159 volatile uint32_t cfg_ctrl_rc_en : 1;
10160 volatile uint32_t cfg_dbc0_rc_en : 1;
10161 volatile uint32_t cfg_dbc1_rc_en : 1;
10162 volatile uint32_t cfg_dbc2_rc_en : 1;
10163 volatile uint32_t cfg_dbc3_rc_en : 1;
10168 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG5_s ALT_MPFE_IOHMC_REG_CTRLCFG5_t;
10172 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_RESET 0x00000000
10174 #define ALT_MPFE_IOHMC_REG_CTRLCFG5_OFST 0x3c
10212 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_LSB 0
10214 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_MSB 15
10216 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_WIDTH 16
10218 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_SET_MSK 0x0000ffff
10220 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_CLR_MSK 0xffff0000
10222 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_RESET 0x0
10224 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_GET(value) (((value) & 0x0000ffff) >> 0)
10226 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_CFG_CS_CHIP_SET(value) (((value) << 0) & 0x0000ffff)
10228 #ifndef __ASSEMBLY__
10240 struct ALT_MPFE_IOHMC_REG_CTRLCFG6_s
10242 volatile uint32_t cfg_cs_chip : 16;
10247 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG6_s ALT_MPFE_IOHMC_REG_CTRLCFG6_t;
10251 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_RESET 0x00000000
10253 #define ALT_MPFE_IOHMC_REG_CTRLCFG6_OFST 0x40
10282 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_LSB 1
10284 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_MSB 7
10286 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_WIDTH 7
10288 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_SET_MSK 0x000000fe
10290 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_CLR_MSK 0xffffff01
10292 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_RESET 0x0
10294 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_GET(value) (((value) & 0x000000fe) >> 1)
10296 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_RB_BACKUP_ENTRY_SET(value) (((value) << 1) & 0x000000fe)
10312 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_LSB 8
10314 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_MSB 14
10316 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_WIDTH 7
10318 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_SET_MSK 0x00007f00
10320 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_CLR_MSK 0xffff80ff
10322 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_RESET 0x0
10324 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_GET(value) (((value) & 0x00007f00) >> 8)
10326 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_CFG_WB_BACKUP_ENTRY_SET(value) (((value) << 8) & 0x00007f00)
10328 #ifndef __ASSEMBLY__
10340 struct ALT_MPFE_IOHMC_REG_CTRLCFG7_s
10343 volatile uint32_t cfg_rb_backup_entry : 7;
10344 volatile uint32_t cfg_wb_backup_entry : 7;
10349 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG7_s ALT_MPFE_IOHMC_REG_CTRLCFG7_t;
10353 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_RESET 0x00000000
10355 #define ALT_MPFE_IOHMC_REG_CTRLCFG7_OFST 0x44
10384 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_LSB 0
10386 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_MSB 0
10388 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_WIDTH 1
10390 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_SET_MSK 0x00000001
10392 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_CLR_MSK 0xfffffffe
10394 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_RESET 0x0
10396 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_GET(value) (((value) & 0x00000001) >> 0)
10398 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_3DS_EN_SET(value) (((value) << 0) & 0x00000001)
10415 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_LSB 1
10417 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_MSB 1
10419 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_WIDTH 1
10421 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_SET_MSK 0x00000002
10423 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_CLR_MSK 0xfffffffd
10425 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_RESET 0x0
10427 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_GET(value) (((value) & 0x00000002) >> 1)
10429 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_CFG_CK_INV_SET(value) (((value) << 1) & 0x00000002)
10431 #ifndef __ASSEMBLY__
10443 struct ALT_MPFE_IOHMC_REG_CTRLCFG8_s
10445 volatile uint32_t cfg_3ds_en : 1;
10446 volatile uint32_t cfg_ck_inv : 1;
10451 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG8_s ALT_MPFE_IOHMC_REG_CTRLCFG8_t;
10455 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_RESET 0x00000000
10457 #define ALT_MPFE_IOHMC_REG_CTRLCFG8_OFST 0x48
10485 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_LSB 0
10487 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_MSB 0
10489 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_WIDTH 1
10491 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_SET_MSK 0x00000001
10493 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_CLR_MSK 0xfffffffe
10495 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_RESET 0x0
10497 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_GET(value) (((value) & 0x00000001) >> 0)
10499 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_CFG_DFX_BYPASS_EN_SET(value) (((value) << 0) & 0x00000001)
10501 #ifndef __ASSEMBLY__
10513 struct ALT_MPFE_IOHMC_REG_CTRLCFG9_s
10515 volatile uint32_t cfg_dfx_bypass_en : 1;
10520 typedef struct ALT_MPFE_IOHMC_REG_CTRLCFG9_s ALT_MPFE_IOHMC_REG_CTRLCFG9_t;
10524 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_RESET 0x00000000
10526 #define ALT_MPFE_IOHMC_REG_CTRLCFG9_OFST 0x4c
10554 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_LSB 0
10556 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_MSB 6
10558 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_WIDTH 7
10560 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_SET_MSK 0x0000007f
10562 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_CLR_MSK 0xffffff80
10564 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_RESET 0x0
10566 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_GET(value) (((value) & 0x0000007f) >> 0)
10568 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL_SET(value) (((value) << 0) & 0x0000007f)
10585 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_LSB 7
10587 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_MSB 12
10589 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_WIDTH 6
10591 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET_MSK 0x00001f80
10593 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_CLR_MSK 0xffffe07f
10595 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_RESET 0x0
10597 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_GET(value) (((value) & 0x00001f80) >> 7)
10599 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET(value) (((value) << 7) & 0x00001f80)
10616 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_LSB 13
10618 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_MSB 18
10620 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_WIDTH 6
10622 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_SET_MSK 0x0007e000
10624 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_CLR_MSK 0xfff81fff
10626 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_RESET 0x0
10628 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_GET(value) (((value) & 0x0007e000) >> 13)
10630 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_CFG_MEM_CLK_DISABLE_ENTRY_CYCLES_SET(value) (((value) << 13) & 0x0007e000)
10632 #ifndef __ASSEMBLY__
10644 struct ALT_MPFE_IOHMC_REG_DRAMTIMING0_s
10646 volatile uint32_t cfg_tcl : 7;
10647 volatile uint32_t cfg_power_saving_exit_cycles : 6;
10648 volatile uint32_t cfg_mem_clk_disable_entry_cycles : 6;
10653 typedef struct ALT_MPFE_IOHMC_REG_DRAMTIMING0_s ALT_MPFE_IOHMC_REG_DRAMTIMING0_t;
10657 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_RESET 0x00000000
10659 #define ALT_MPFE_IOHMC_REG_DRAMTIMING0_OFST 0x50
10693 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_LSB 0
10695 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_MSB 15
10697 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_WIDTH 16
10699 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_SET_MSK 0x0000ffff
10701 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_CLR_MSK 0xffff0000
10703 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_RESET 0x0
10705 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_GET(value) (((value) & 0x0000ffff) >> 0)
10707 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_WRITE_ODT_CHIP_SET(value) (((value) << 0) & 0x0000ffff)
10730 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_LSB 16
10732 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_MSB 31
10734 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_WIDTH 16
10736 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_SET_MSK 0xffff0000
10738 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_CLR_MSK 0x0000ffff
10740 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_RESET 0x0
10742 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_GET(value) (((value) & 0xffff0000) >> 16)
10744 #define ALT_MPFE_IOHMC_REG_DRAMODT0_CFG_READ_ODT_CHIP_SET(value) (((value) << 16) & 0xffff0000)
10746 #ifndef __ASSEMBLY__
10758 struct ALT_MPFE_IOHMC_REG_DRAMODT0_s
10760 volatile uint32_t cfg_write_odt_chip : 16;
10761 volatile uint32_t cfg_read_odt_chip : 16;
10765 typedef struct ALT_MPFE_IOHMC_REG_DRAMODT0_s ALT_MPFE_IOHMC_REG_DRAMODT0_t;
10769 #define ALT_MPFE_IOHMC_REG_DRAMODT0_RESET 0x00000000
10771 #define ALT_MPFE_IOHMC_REG_DRAMODT0_OFST 0x54
10801 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_LSB 0
10803 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_MSB 5
10805 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_WIDTH 6
10807 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_SET_MSK 0x0000003f
10809 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_CLR_MSK 0xffffffc0
10811 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_RESET 0x0
10813 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_GET(value) (((value) & 0x0000003f) >> 0)
10815 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_ON_SET(value) (((value) << 0) & 0x0000003f)
10831 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_LSB 6
10833 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_MSB 11
10835 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_WIDTH 6
10837 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_SET_MSK 0x00000fc0
10839 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_CLR_MSK 0xfffff03f
10841 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_RESET 0x0
10843 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_GET(value) (((value) & 0x00000fc0) >> 6)
10845 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_ON_SET(value) (((value) << 6) & 0x00000fc0)
10861 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_LSB 12
10863 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_MSB 17
10865 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_WIDTH 6
10867 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_SET_MSK 0x0003f000
10869 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_CLR_MSK 0xfffc0fff
10871 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_RESET 0x0
10873 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_GET(value) (((value) & 0x0003f000) >> 12)
10875 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_WR_ODT_PERIOD_SET(value) (((value) << 12) & 0x0003f000)
10891 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_LSB 18
10893 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_MSB 23
10895 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_WIDTH 6
10897 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_SET_MSK 0x00fc0000
10899 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_CLR_MSK 0xff03ffff
10901 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_RESET 0x0
10903 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_GET(value) (((value) & 0x00fc0000) >> 18)
10905 #define ALT_MPFE_IOHMC_REG_DRAMODT1_CFG_RD_ODT_PERIOD_SET(value) (((value) << 18) & 0x00fc0000)
10907 #ifndef __ASSEMBLY__
10919 struct ALT_MPFE_IOHMC_REG_DRAMODT1_s
10921 volatile uint32_t cfg_wr_odt_on : 6;
10922 volatile uint32_t cfg_rd_odt_on : 6;
10923 volatile uint32_t cfg_wr_odt_period : 6;
10924 volatile uint32_t cfg_rd_odt_period : 6;
10929 typedef struct ALT_MPFE_IOHMC_REG_DRAMODT1_s ALT_MPFE_IOHMC_REG_DRAMODT1_t;
10933 #define ALT_MPFE_IOHMC_REG_DRAMODT1_RESET 0x00000000
10935 #define ALT_MPFE_IOHMC_REG_DRAMODT1_OFST 0x58
10970 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_LSB 0
10972 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_MSB 3
10974 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_WIDTH 4
10976 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_SET_MSK 0x0000000f
10978 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_CLR_MSK 0xfffffff0
10980 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_RESET 0x0
10982 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_GET(value) (((value) & 0x0000000f) >> 0)
10984 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_NO_OF_REF_FOR_SELF_RFSH_SET(value) (((value) << 0) & 0x0000000f)
11000 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_LSB 4
11002 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_MSB 4
11004 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_WIDTH 1
11006 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_SET_MSK 0x00000010
11008 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_CLR_MSK 0xffffffef
11010 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_RESET 0x0
11012 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_GET(value) (((value) & 0x00000010) >> 4)
11014 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_EXIT_PDN_FOR_DQSTRK_SET(value) (((value) << 4) & 0x00000010)
11033 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_LSB 5
11035 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_MSB 5
11037 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_WIDTH 1
11039 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_SET_MSK 0x00000020
11041 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_CLR_MSK 0xffffffdf
11043 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_RESET 0x0
11045 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_GET(value) (((value) & 0x00000020) >> 5)
11047 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_REVERT_REF_QUAL_SET(value) (((value) << 5) & 0x00000020)
11062 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_LSB 6
11064 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_MSB 6
11066 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_WIDTH 1
11068 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_SET_MSK 0x00000040
11070 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_CLR_MSK 0xffffffbf
11072 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_RESET 0x0
11074 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_GET(value) (((value) & 0x00000040) >> 6)
11076 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_CMD_VALID_UNGATE_FIX_SET(value) (((value) << 6) & 0x00000040)
11096 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_LSB 7
11098 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_MSB 7
11100 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_WIDTH 1
11102 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_SET_MSK 0x00000080
11104 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_CLR_MSK 0xffffff7f
11106 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_RESET 0x0
11108 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_GET(value) (((value) & 0x00000080) >> 7)
11110 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REF_ACK_DISABLE_SET(value) (((value) << 7) & 0x00000080)
11125 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_LSB 8
11127 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_MSB 8
11129 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_WIDTH 1
11131 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_SET_MSK 0x00000100
11133 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_CLR_MSK 0xfffffeff
11135 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_RESET 0x0
11137 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_GET(value) (((value) & 0x00000100) >> 8)
11139 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_EN_MRNK_RD_FIX_SET(value) (((value) << 8) & 0x00000100)
11159 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_LSB 9
11161 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_MSB 9
11163 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_WIDTH 1
11165 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_SET_MSK 0x00000200
11167 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_CLR_MSK 0xfffffdff
11169 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_RESET 0x0
11171 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_GET(value) (((value) & 0x00000200) >> 9)
11173 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_3DS_MIXED_HEIGHT_REQ_FIX_SET(value) (((value) << 9) & 0x00000200)
11192 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_LSB 10
11194 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_MSB 10
11196 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_WIDTH 1
11198 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_SET_MSK 0x00000400
11200 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_CLR_MSK 0xfffffbff
11202 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_RESET 0x0
11204 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_GET(value) (((value) & 0x00000400) >> 10)
11206 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_CB_PDQS_PERF_FIX_DISABLE_SET(value) (((value) << 10) & 0x00000400)
11223 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_LSB 11
11225 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_MSB 11
11227 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_WIDTH 1
11229 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_SET_MSK 0x00000800
11231 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_CLR_MSK 0xfffff7ff
11233 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_RESET 0x0
11235 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_GET(value) (((value) & 0x00000800) >> 11)
11237 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_SELF_RFSH_DQSTRK_EN_SET(value) (((value) << 11) & 0x00000800)
11252 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_LSB 12
11254 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_MSB 15
11256 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_WIDTH 4
11258 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET_MSK 0x0000f000
11260 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_CLR_MSK 0xffff0fff
11262 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_RESET 0x0
11264 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_GET(value) (((value) & 0x0000f000) >> 12)
11266 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET(value) (((value) << 12) & 0x0000f000)
11281 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_LSB 16
11283 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_MSB 31
11285 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_WIDTH 16
11287 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET_MSK 0xffff0000
11289 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_CLR_MSK 0x0000ffff
11291 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_RESET 0x0
11293 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_GET(value) (((value) & 0xffff0000) >> 16)
11295 #define ALT_MPFE_IOHMC_REG_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET(value) (((value) << 16) & 0xffff0000)
11297 #ifndef __ASSEMBLY__
11309 struct ALT_MPFE_IOHMC_REG_SBCFG0_s
11311 volatile uint32_t cfg_no_of_ref_for_self_rfsh : 4;
11312 volatile uint32_t cfg_exit_pdn_for_dqstrk : 1;
11313 volatile uint32_t cfg_cb_revert_ref_qual : 1;
11314 volatile uint32_t cfg_cb_en_cmd_valid_ungate_fix : 1;
11315 volatile uint32_t cfg_cb_3ds_mixed_height_ref_ack_disable : 1;
11316 volatile uint32_t cfg_cb_en_mrnk_rd_fix : 1;
11317 volatile uint32_t cfg_cb_3ds_mixed_height_req_fix : 1;
11318 volatile uint32_t cfg_cb_pdqs_perf_fix_disable : 1;
11319 volatile uint32_t cfg_self_rfsh_dqstrk_en : 1;
11320 volatile uint32_t cfg_rld3_refresh_seq0 : 4;
11321 volatile uint32_t cfg_rld3_refresh_seq1 : 16;
11325 typedef struct ALT_MPFE_IOHMC_REG_SBCFG0_s ALT_MPFE_IOHMC_REG_SBCFG0_t;
11329 #define ALT_MPFE_IOHMC_REG_SBCFG0_RESET 0x00000000
11331 #define ALT_MPFE_IOHMC_REG_SBCFG0_OFST 0x5c
11357 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_LSB 0
11359 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_MSB 15
11361 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_WIDTH 16
11363 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_SET_MSK 0x0000ffff
11365 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_CLR_MSK 0xffff0000
11367 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_RESET 0x0
11369 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_GET(value) (((value) & 0x0000ffff) >> 0)
11371 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ2_SET(value) (((value) << 0) & 0x0000ffff)
11386 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_LSB 16
11388 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_MSB 31
11390 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_WIDTH 16
11392 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_SET_MSK 0xffff0000
11394 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_CLR_MSK 0x0000ffff
11396 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_RESET 0x0
11398 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_GET(value) (((value) & 0xffff0000) >> 16)
11400 #define ALT_MPFE_IOHMC_REG_SBCFG1_CFG_RLD3_REFRESH_SEQ3_SET(value) (((value) << 16) & 0xffff0000)
11402 #ifndef __ASSEMBLY__
11414 struct ALT_MPFE_IOHMC_REG_SBCFG1_s
11416 volatile uint32_t cfg_rld3_refresh_seq2 : 16;
11417 volatile uint32_t cfg_rld3_refresh_seq3 : 16;
11421 typedef struct ALT_MPFE_IOHMC_REG_SBCFG1_s ALT_MPFE_IOHMC_REG_SBCFG1_t;
11425 #define ALT_MPFE_IOHMC_REG_SBCFG1_RESET 0x00000000
11427 #define ALT_MPFE_IOHMC_REG_SBCFG1_OFST 0x60
11459 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_LSB 0
11461 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_MSB 0
11463 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_WIDTH 1
11465 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_SET_MSK 0x00000001
11467 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_CLR_MSK 0xfffffffe
11469 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_RESET 0x0
11471 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_GET(value) (((value) & 0x00000001) >> 0)
11473 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ZQCAL_DISABLE_SET(value) (((value) << 0) & 0x00000001)
11489 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_LSB 1
11491 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_MSB 1
11493 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_WIDTH 1
11495 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_SET_MSK 0x00000002
11497 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_CLR_MSK 0xfffffffd
11499 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_RESET 0x0
11501 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_GET(value) (((value) & 0x00000002) >> 1)
11503 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_ZQCAL_DISABLE_SET(value) (((value) << 1) & 0x00000002)
11522 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_LSB 2
11524 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_MSB 2
11526 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_WIDTH 1
11528 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_SET_MSK 0x00000004
11530 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_CLR_MSK 0xfffffffb
11532 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_RESET 0x0
11534 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_GET(value) (((value) & 0x00000004) >> 2)
11536 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_MPS_DQSTRK_DISABLE_SET(value) (((value) << 2) & 0x00000004)
11552 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_LSB 3
11554 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_MSB 3
11556 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_WIDTH 1
11558 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_SET_MSK 0x00000008
11560 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_CLR_MSK 0xfffffff7
11562 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_RESET 0x0
11564 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_GET(value) (((value) & 0x00000008) >> 3)
11566 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SB_CG_DISABLE_SET(value) (((value) << 3) & 0x00000008)
11581 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_LSB 4
11583 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_MSB 4
11585 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_WIDTH 1
11587 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_SET_MSK 0x00000010
11589 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_CLR_MSK 0xffffffef
11591 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_RESET 0x0
11593 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_GET(value) (((value) & 0x00000010) >> 4)
11595 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_USER_RFSH_EN_SET(value) (((value) << 4) & 0x00000010)
11611 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_LSB 5
11613 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_MSB 5
11615 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_WIDTH 1
11617 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET_MSK 0x00000020
11619 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_CLR_MSK 0xffffffdf
11621 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_RESET 0x0
11623 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_GET(value) (((value) & 0x00000020) >> 5)
11625 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET(value) (((value) << 5) & 0x00000020)
11648 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_LSB 6
11650 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_MSB 7
11652 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_WIDTH 2
11654 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET_MSK 0x000000c0
11656 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_CLR_MSK 0xffffff3f
11658 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_RESET 0x0
11660 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_GET(value) (((value) & 0x000000c0) >> 6)
11662 #define ALT_MPFE_IOHMC_REG_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET(value) (((value) << 6) & 0x000000c0)
11664 #ifndef __ASSEMBLY__
11676 struct ALT_MPFE_IOHMC_REG_SBCFG2_s
11678 volatile uint32_t cfg_srf_zqcal_disable : 1;
11679 volatile uint32_t cfg_mps_zqcal_disable : 1;
11680 volatile uint32_t cfg_mps_dqstrk_disable : 1;
11681 volatile uint32_t cfg_sb_cg_disable : 1;
11682 volatile uint32_t cfg_user_rfsh_en : 1;
11683 volatile uint32_t cfg_srf_autoexit_en : 1;
11684 volatile uint32_t cfg_srf_entry_exit_block : 2;
11689 typedef struct ALT_MPFE_IOHMC_REG_SBCFG2_s ALT_MPFE_IOHMC_REG_SBCFG2_t;
11693 #define ALT_MPFE_IOHMC_REG_SBCFG2_RESET 0x00000000
11695 #define ALT_MPFE_IOHMC_REG_SBCFG2_OFST 0x64
11721 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_LSB 0
11723 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_MSB 19
11725 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_WIDTH 20
11727 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_SET_MSK 0x000fffff
11729 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_CLR_MSK 0xfff00000
11731 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_RESET 0x0
11733 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_GET(value) (((value) & 0x000fffff) >> 0)
11735 #define ALT_MPFE_IOHMC_REG_SBCFG3_CFG_SB_DDR4_MR3_SET(value) (((value) << 0) & 0x000fffff)
11737 #ifndef __ASSEMBLY__
11749 struct ALT_MPFE_IOHMC_REG_SBCFG3_s
11751 volatile uint32_t cfg_sb_ddr4_mr3 : 20;
11756 typedef struct ALT_MPFE_IOHMC_REG_SBCFG3_s ALT_MPFE_IOHMC_REG_SBCFG3_t;
11760 #define ALT_MPFE_IOHMC_REG_SBCFG3_RESET 0x00000000
11762 #define ALT_MPFE_IOHMC_REG_SBCFG3_OFST 0x68
11788 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_LSB 0
11790 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_MSB 19
11792 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_WIDTH 20
11794 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_SET_MSK 0x000fffff
11796 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_CLR_MSK 0xfff00000
11798 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_RESET 0x0
11800 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_GET(value) (((value) & 0x000fffff) >> 0)
11802 #define ALT_MPFE_IOHMC_REG_SBCFG4_CFG_SB_DDR4_MR4_SET(value) (((value) << 0) & 0x000fffff)
11804 #ifndef __ASSEMBLY__
11816 struct ALT_MPFE_IOHMC_REG_SBCFG4_s
11818 volatile uint32_t cfg_sb_ddr4_mr4 : 20;
11823 typedef struct ALT_MPFE_IOHMC_REG_SBCFG4_s ALT_MPFE_IOHMC_REG_SBCFG4_t;
11827 #define ALT_MPFE_IOHMC_REG_SBCFG4_RESET 0x00000000
11829 #define ALT_MPFE_IOHMC_REG_SBCFG4_OFST 0x6c
11858 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_LSB 0
11860 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_MSB 0
11862 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_WIDTH 1
11864 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_SET_MSK 0x00000001
11866 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_CLR_MSK 0xfffffffe
11868 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_RESET 0x0
11870 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_GET(value) (((value) & 0x00000001) >> 0)
11872 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_SHORT_DQSTRK_CTRL_EN_SET(value) (((value) << 0) & 0x00000001)
11887 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_LSB 1
11889 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_MSB 1
11891 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_WIDTH 1
11893 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_SET_MSK 0x00000002
11895 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_CLR_MSK 0xfffffffd
11897 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_RESET 0x0
11899 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_GET(value) (((value) & 0x00000002) >> 1)
11901 #define ALT_MPFE_IOHMC_REG_SBCFG5_CFG_PERIOD_DQSTRK_CTRL_EN_SET(value) (((value) << 1) & 0x00000002)
11903 #ifndef __ASSEMBLY__
11915 struct ALT_MPFE_IOHMC_REG_SBCFG5_s
11917 volatile uint32_t cfg_short_dqstrk_ctrl_en : 1;
11918 volatile uint32_t cfg_period_dqstrk_ctrl_en : 1;
11923 typedef struct ALT_MPFE_IOHMC_REG_SBCFG5_s ALT_MPFE_IOHMC_REG_SBCFG5_t;
11927 #define ALT_MPFE_IOHMC_REG_SBCFG5_RESET 0x00000000
11929 #define ALT_MPFE_IOHMC_REG_SBCFG5_OFST 0x70
11956 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_LSB 0
11958 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_MSB 15
11960 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_WIDTH 16
11962 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET_MSK 0x0000ffff
11964 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_CLR_MSK 0xffff0000
11966 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_RESET 0x0
11968 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_GET(value) (((value) & 0x0000ffff) >> 0)
11970 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET(value) (((value) << 0) & 0x0000ffff)
11985 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_LSB 16
11987 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_MSB 23
11989 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_WIDTH 8
11991 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET_MSK 0x00ff0000
11993 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_CLR_MSK 0xff00ffff
11995 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_RESET 0x0
11997 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_GET(value) (((value) & 0x00ff0000) >> 16)
11999 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET(value) (((value) << 16) & 0x00ff0000)
12014 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LSB 24
12016 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_MSB 31
12018 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_WIDTH 8
12020 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET_MSK 0xff000000
12022 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_CLR_MSK 0x00ffffff
12024 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_RESET 0x0
12026 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_GET(value) (((value) & 0xff000000) >> 24)
12028 #define ALT_MPFE_IOHMC_REG_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET(value) (((value) << 24) & 0xff000000)
12030 #ifndef __ASSEMBLY__
12042 struct ALT_MPFE_IOHMC_REG_SBCFG6_s
12044 volatile uint32_t cfg_period_dqstrk_interval : 16;
12045 volatile uint32_t cfg_t_param_dqstrk_to_valid_last : 8;
12046 volatile uint32_t cfg_t_param_dqstrk_to_valid : 8;
12050 typedef struct ALT_MPFE_IOHMC_REG_SBCFG6_s ALT_MPFE_IOHMC_REG_SBCFG6_t;
12054 #define ALT_MPFE_IOHMC_REG_SBCFG6_RESET 0x00000000
12056 #define ALT_MPFE_IOHMC_REG_SBCFG6_OFST 0x74
12083 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_LSB 0
12085 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_MSB 6
12087 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_WIDTH 7
12089 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET_MSK 0x0000007f
12091 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_CLR_MSK 0xffffff80
12093 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_RESET 0x0
12095 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_GET(value) (((value) & 0x0000007f) >> 0)
12097 #define ALT_MPFE_IOHMC_REG_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET(value) (((value) << 0) & 0x0000007f)
12099 #ifndef __ASSEMBLY__
12111 struct ALT_MPFE_IOHMC_REG_SBCFG7_s
12113 volatile uint32_t cfg_rfsh_warn_threshold : 7;
12118 typedef struct ALT_MPFE_IOHMC_REG_SBCFG7_s ALT_MPFE_IOHMC_REG_SBCFG7_t;
12122 #define ALT_MPFE_IOHMC_REG_SBCFG7_RESET 0x00000000
12124 #define ALT_MPFE_IOHMC_REG_SBCFG7_OFST 0x78
12154 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_LSB 0
12156 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_MSB 5
12158 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_WIDTH 6
12160 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_SET_MSK 0x0000003f
12162 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_CLR_MSK 0xffffffc0
12164 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_RESET 0x0
12166 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_GET(value) (((value) & 0x0000003f) >> 0)
12168 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_SET(value) (((value) << 0) & 0x0000003f)
12183 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_LSB 6
12185 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_MSB 11
12187 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_WIDTH 6
12189 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_SET_MSK 0x00000fc0
12191 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_CLR_MSK 0xfffff03f
12193 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_RESET 0x0
12195 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_GET(value) (((value) & 0x00000fc0) >> 6)
12197 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_SET(value) (((value) << 6) & 0x00000fc0)
12212 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_LSB 12
12214 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_MSB 17
12216 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_WIDTH 6
12218 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_SET_MSK 0x0003f000
12220 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_CLR_MSK 0xfffc0fff
12222 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_RESET 0x0
12224 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_GET(value) (((value) & 0x0003f000) >> 12)
12226 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_SET(value) (((value) << 12) & 0x0003f000)
12242 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_LSB 18
12244 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_MSB 23
12246 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH 6
12248 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_SET_MSK 0x00fc0000
12250 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_CLR_MSK 0xff03ffff
12252 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_RESET 0x0
12254 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_GET(value) (((value) & 0x00fc0000) >> 18)
12256 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_SET(value) (((value) << 18) & 0x00fc0000)
12271 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_LSB 24
12273 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_MSB 29
12275 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_WIDTH 6
12277 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_SET_MSK 0x3f000000
12279 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_CLR_MSK 0xc0ffffff
12281 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_RESET 0x0
12283 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_GET(value) (((value) & 0x3f000000) >> 24)
12285 #define ALT_MPFE_IOHMC_REG_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_SET(value) (((value) << 24) & 0x3f000000)
12287 #ifndef __ASSEMBLY__
12299 struct ALT_MPFE_IOHMC_REG_CALTIMING0_s
12301 volatile uint32_t cfg_t_param_act_to_rdwr : 6;
12302 volatile uint32_t cfg_t_param_act_to_pch : 6;
12303 volatile uint32_t cfg_t_param_act_to_act : 6;
12304 volatile uint32_t cfg_t_param_act_to_act_diff_bank : 6;
12305 volatile uint32_t cfg_t_param_act_to_act_diff_bg : 6;
12310 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING0_s ALT_MPFE_IOHMC_REG_CALTIMING0_t;
12314 #define ALT_MPFE_IOHMC_REG_CALTIMING0_RESET 0x00000000
12316 #define ALT_MPFE_IOHMC_REG_CALTIMING0_OFST 0x7c
12346 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_LSB 0
12348 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_MSB 5
12350 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_WIDTH 6
12352 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET_MSK 0x0000003f
12354 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_CLR_MSK 0xffffffc0
12356 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_RESET 0x0
12358 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_GET(value) (((value) & 0x0000003f) >> 0)
12360 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET(value) (((value) << 0) & 0x0000003f)
12375 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_LSB 6
12377 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_MSB 11
12379 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH 6
12381 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET_MSK 0x00000fc0
12383 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_CLR_MSK 0xfffff03f
12385 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_RESET 0x0
12387 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_GET(value) (((value) & 0x00000fc0) >> 6)
12389 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET(value) (((value) << 6) & 0x00000fc0)
12404 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_LSB 12
12406 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_MSB 17
12408 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_WIDTH 6
12410 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET_MSK 0x0003f000
12412 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_CLR_MSK 0xfffc0fff
12414 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_RESET 0x0
12416 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_GET(value) (((value) & 0x0003f000) >> 12)
12418 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET(value) (((value) << 12) & 0x0003f000)
12433 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_LSB 18
12435 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_MSB 23
12437 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_WIDTH 6
12439 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET_MSK 0x00fc0000
12441 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_CLR_MSK 0xff03ffff
12443 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_RESET 0x0
12445 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_GET(value) (((value) & 0x00fc0000) >> 18)
12447 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET(value) (((value) << 18) & 0x00fc0000)
12462 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_LSB 24
12464 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_MSB 29
12466 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH 6
12468 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET_MSK 0x3f000000
12470 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_CLR_MSK 0xc0ffffff
12472 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_RESET 0x0
12474 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_GET(value) (((value) & 0x3f000000) >> 24)
12476 #define ALT_MPFE_IOHMC_REG_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET(value) (((value) << 24) & 0x3f000000)
12478 #ifndef __ASSEMBLY__
12490 struct ALT_MPFE_IOHMC_REG_CALTIMING1_s
12492 volatile uint32_t cfg_t_param_rd_to_rd : 6;
12493 volatile uint32_t cfg_t_param_rd_to_rd_diff_chip : 6;
12494 volatile uint32_t cfg_t_param_rd_to_rd_diff_bg : 6;
12495 volatile uint32_t cfg_t_param_rd_to_wr : 6;
12496 volatile uint32_t cfg_t_param_rd_to_wr_diff_chip : 6;
12501 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING1_s ALT_MPFE_IOHMC_REG_CALTIMING1_t;
12505 #define ALT_MPFE_IOHMC_REG_CALTIMING1_RESET 0x00000000
12507 #define ALT_MPFE_IOHMC_REG_CALTIMING1_OFST 0x80
12537 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_LSB 0
12539 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_MSB 5
12541 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_WIDTH 6
12543 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_SET_MSK 0x0000003f
12545 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_CLR_MSK 0xffffffc0
12547 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_RESET 0x0
12549 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_GET(value) (((value) & 0x0000003f) >> 0)
12551 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_SET(value) (((value) << 0) & 0x0000003f)
12566 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_LSB 6
12568 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_MSB 11
12570 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_WIDTH 6
12572 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_SET_MSK 0x00000fc0
12574 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_CLR_MSK 0xfffff03f
12576 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_RESET 0x0
12578 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_GET(value) (((value) & 0x00000fc0) >> 6)
12580 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_SET(value) (((value) << 6) & 0x00000fc0)
12595 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_LSB 12
12597 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_MSB 17
12599 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_WIDTH 6
12601 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_SET_MSK 0x0003f000
12603 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_CLR_MSK 0xfffc0fff
12605 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_RESET 0x0
12607 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_GET(value) (((value) & 0x0003f000) >> 12)
12609 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_SET(value) (((value) << 12) & 0x0003f000)
12624 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_LSB 18
12626 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_MSB 23
12628 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_WIDTH 6
12630 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_SET_MSK 0x00fc0000
12632 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_CLR_MSK 0xff03ffff
12634 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_RESET 0x0
12636 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_GET(value) (((value) & 0x00fc0000) >> 18)
12638 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_SET(value) (((value) << 18) & 0x00fc0000)
12653 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_LSB 24
12655 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_MSB 29
12657 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH 6
12659 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_SET_MSK 0x3f000000
12661 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_CLR_MSK 0xc0ffffff
12663 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_RESET 0x0
12665 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_GET(value) (((value) & 0x3f000000) >> 24)
12667 #define ALT_MPFE_IOHMC_REG_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_SET(value) (((value) << 24) & 0x3f000000)
12669 #ifndef __ASSEMBLY__
12681 struct ALT_MPFE_IOHMC_REG_CALTIMING2_s
12683 volatile uint32_t cfg_t_param_rd_to_wr_diff_bg : 6;
12684 volatile uint32_t cfg_t_param_rd_to_pch : 6;
12685 volatile uint32_t cfg_t_param_rd_ap_to_valid : 6;
12686 volatile uint32_t cfg_t_param_wr_to_wr : 6;
12687 volatile uint32_t cfg_t_param_wr_to_wr_diff_chip : 6;
12692 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING2_s ALT_MPFE_IOHMC_REG_CALTIMING2_t;
12696 #define ALT_MPFE_IOHMC_REG_CALTIMING2_RESET 0x00000000
12698 #define ALT_MPFE_IOHMC_REG_CALTIMING2_OFST 0x84
12728 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_LSB 0
12730 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_MSB 5
12732 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_WIDTH 6
12734 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_SET_MSK 0x0000003f
12736 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_CLR_MSK 0xffffffc0
12738 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_RESET 0x0
12740 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_GET(value) (((value) & 0x0000003f) >> 0)
12742 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_SET(value) (((value) << 0) & 0x0000003f)
12757 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_LSB 6
12759 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_MSB 11
12761 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_WIDTH 6
12763 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_SET_MSK 0x00000fc0
12765 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_CLR_MSK 0xfffff03f
12767 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_RESET 0x0
12769 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_GET(value) (((value) & 0x00000fc0) >> 6)
12771 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_SET(value) (((value) << 6) & 0x00000fc0)
12786 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_LSB 12
12788 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_MSB 17
12790 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH 6
12792 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_SET_MSK 0x0003f000
12794 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_CLR_MSK 0xfffc0fff
12796 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_RESET 0x0
12798 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_GET(value) (((value) & 0x0003f000) >> 12)
12800 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_SET(value) (((value) << 12) & 0x0003f000)
12815 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_LSB 18
12817 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_MSB 23
12819 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_WIDTH 6
12821 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_SET_MSK 0x00fc0000
12823 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_CLR_MSK 0xff03ffff
12825 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_RESET 0x0
12827 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_GET(value) (((value) & 0x00fc0000) >> 18)
12829 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_SET(value) (((value) << 18) & 0x00fc0000)
12844 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_LSB 24
12846 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_MSB 29
12848 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_WIDTH 6
12850 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_SET_MSK 0x3f000000
12852 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_CLR_MSK 0xc0ffffff
12854 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_RESET 0x0
12856 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_GET(value) (((value) & 0x3f000000) >> 24)
12858 #define ALT_MPFE_IOHMC_REG_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_SET(value) (((value) << 24) & 0x3f000000)
12860 #ifndef __ASSEMBLY__
12872 struct ALT_MPFE_IOHMC_REG_CALTIMING3_s
12874 volatile uint32_t cfg_t_param_wr_to_wr_diff_bg : 6;
12875 volatile uint32_t cfg_t_param_wr_to_rd : 6;
12876 volatile uint32_t cfg_t_param_wr_to_rd_diff_chip : 6;
12877 volatile uint32_t cfg_t_param_wr_to_rd_diff_bg : 6;
12878 volatile uint32_t cfg_t_param_wr_to_pch : 6;
12883 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING3_s ALT_MPFE_IOHMC_REG_CALTIMING3_t;
12887 #define ALT_MPFE_IOHMC_REG_CALTIMING3_RESET 0x00000000
12889 #define ALT_MPFE_IOHMC_REG_CALTIMING3_OFST 0x88
12918 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_LSB 0
12920 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_MSB 5
12922 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_WIDTH 6
12924 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET_MSK 0x0000003f
12926 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_CLR_MSK 0xffffffc0
12928 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_RESET 0x0
12930 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_GET(value) (((value) & 0x0000003f) >> 0)
12932 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET(value) (((value) << 0) & 0x0000003f)
12947 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_LSB 6
12949 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_MSB 11
12951 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_WIDTH 6
12953 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET_MSK 0x00000fc0
12955 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_CLR_MSK 0xfffff03f
12957 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_RESET 0x0
12959 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_GET(value) (((value) & 0x00000fc0) >> 6)
12961 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET(value) (((value) << 6) & 0x00000fc0)
12976 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_LSB 12
12978 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_MSB 17
12980 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_WIDTH 6
12982 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET_MSK 0x0003f000
12984 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_CLR_MSK 0xfffc0fff
12986 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_RESET 0x0
12988 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_GET(value) (((value) & 0x0003f000) >> 12)
12990 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET(value) (((value) << 12) & 0x0003f000)
13006 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_LSB 18
13008 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_MSB 25
13010 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_WIDTH 8
13012 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET_MSK 0x03fc0000
13014 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_CLR_MSK 0xfc03ffff
13016 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_RESET 0x0
13018 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_GET(value) (((value) & 0x03fc0000) >> 18)
13020 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET(value) (((value) << 18) & 0x03fc0000)
13035 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_LSB 26
13037 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_MSB 31
13039 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_WIDTH 6
13041 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET_MSK 0xfc000000
13043 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_CLR_MSK 0x03ffffff
13045 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_RESET 0x0
13047 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_GET(value) (((value) & 0xfc000000) >> 26)
13049 #define ALT_MPFE_IOHMC_REG_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET(value) (((value) << 26) & 0xfc000000)
13051 #ifndef __ASSEMBLY__
13063 struct ALT_MPFE_IOHMC_REG_CALTIMING4_s
13065 volatile uint32_t cfg_t_param_wr_ap_to_valid : 6;
13066 volatile uint32_t cfg_t_param_pch_to_valid : 6;
13067 volatile uint32_t cfg_t_param_pch_all_to_valid : 6;
13068 volatile uint32_t cfg_t_param_arf_to_valid : 8;
13069 volatile uint32_t cfg_t_param_pdn_to_valid : 6;
13073 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING4_s ALT_MPFE_IOHMC_REG_CALTIMING4_t;
13077 #define ALT_MPFE_IOHMC_REG_CALTIMING4_RESET 0x00000000
13079 #define ALT_MPFE_IOHMC_REG_CALTIMING4_OFST 0x8c
13106 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_LSB 0
13108 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_MSB 9
13110 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_WIDTH 10
13112 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET_MSK 0x000003ff
13114 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_CLR_MSK 0xfffffc00
13116 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_RESET 0x0
13118 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_GET(value) (((value) & 0x000003ff) >> 0)
13120 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET(value) (((value) << 0) & 0x000003ff)
13135 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_LSB 10
13137 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_MSB 19
13139 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_WIDTH 10
13141 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET_MSK 0x000ffc00
13143 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_CLR_MSK 0xfff003ff
13145 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_RESET 0x0
13147 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_GET(value) (((value) & 0x000ffc00) >> 10)
13149 #define ALT_MPFE_IOHMC_REG_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET(value) (((value) << 10) & 0x000ffc00)
13151 #ifndef __ASSEMBLY__
13163 struct ALT_MPFE_IOHMC_REG_CALTIMING5_s
13165 volatile uint32_t cfg_t_param_srf_to_valid : 10;
13166 volatile uint32_t cfg_t_param_srf_to_zq_cal : 10;
13171 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING5_s ALT_MPFE_IOHMC_REG_CALTIMING5_t;
13175 #define ALT_MPFE_IOHMC_REG_CALTIMING5_RESET 0x00000000
13177 #define ALT_MPFE_IOHMC_REG_CALTIMING5_OFST 0x90
13204 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_LSB 0
13206 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_MSB 12
13208 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_WIDTH 13
13210 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_SET_MSK 0x00001fff
13212 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_CLR_MSK 0xffffe000
13214 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_RESET 0x0
13216 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_GET(value) (((value) & 0x00001fff) >> 0)
13218 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_SET(value) (((value) << 0) & 0x00001fff)
13233 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_LSB 13
13235 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_MSB 28
13237 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_WIDTH 16
13239 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_SET_MSK 0x1fffe000
13241 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_CLR_MSK 0xe0001fff
13243 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_RESET 0x0
13245 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_GET(value) (((value) & 0x1fffe000) >> 13)
13247 #define ALT_MPFE_IOHMC_REG_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_SET(value) (((value) << 13) & 0x1fffe000)
13249 #ifndef __ASSEMBLY__
13261 struct ALT_MPFE_IOHMC_REG_CALTIMING6_s
13263 volatile uint32_t cfg_t_param_arf_period : 13;
13264 volatile uint32_t cfg_t_param_pdn_period : 16;
13269 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING6_s ALT_MPFE_IOHMC_REG_CALTIMING6_t;
13273 #define ALT_MPFE_IOHMC_REG_CALTIMING6_RESET 0x00000000
13275 #define ALT_MPFE_IOHMC_REG_CALTIMING6_OFST 0x94
13304 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_LSB 0
13306 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_MSB 8
13308 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_WIDTH 9
13310 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET_MSK 0x000001ff
13312 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_CLR_MSK 0xfffffe00
13314 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_RESET 0x0
13316 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_GET(value) (((value) & 0x000001ff) >> 0)
13318 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET(value) (((value) << 0) & 0x000001ff)
13333 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_LSB 9
13335 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_MSB 15
13337 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_WIDTH 7
13339 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET_MSK 0x0000fe00
13341 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_CLR_MSK 0xffff01ff
13343 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_RESET 0x0
13345 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_GET(value) (((value) & 0x0000fe00) >> 9)
13347 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET(value) (((value) << 9) & 0x0000fe00)
13362 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_LSB 16
13364 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_MSB 19
13366 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_WIDTH 4
13368 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET_MSK 0x000f0000
13370 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_CLR_MSK 0xfff0ffff
13372 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_RESET 0x0
13374 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_GET(value) (((value) & 0x000f0000) >> 16)
13376 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET(value) (((value) << 16) & 0x000f0000)
13392 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_LSB 20
13394 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_MSB 29
13396 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_WIDTH 10
13398 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET_MSK 0x3ff00000
13400 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_CLR_MSK 0xc00fffff
13402 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_RESET 0x0
13404 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_GET(value) (((value) & 0x3ff00000) >> 20)
13406 #define ALT_MPFE_IOHMC_REG_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET(value) (((value) << 20) & 0x3ff00000)
13408 #ifndef __ASSEMBLY__
13420 struct ALT_MPFE_IOHMC_REG_CALTIMING7_s
13422 volatile uint32_t cfg_t_param_zqcl_to_valid : 9;
13423 volatile uint32_t cfg_t_param_zqcs_to_valid : 7;
13424 volatile uint32_t cfg_t_param_mrs_to_valid : 4;
13425 volatile uint32_t cfg_t_param_mps_to_valid : 10;
13430 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING7_s ALT_MPFE_IOHMC_REG_CALTIMING7_t;
13434 #define ALT_MPFE_IOHMC_REG_CALTIMING7_RESET 0x00000000
13436 #define ALT_MPFE_IOHMC_REG_CALTIMING7_OFST 0x98
13467 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_LSB 0
13469 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_MSB 3
13471 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_WIDTH 4
13473 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET_MSK 0x0000000f
13475 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_CLR_MSK 0xfffffff0
13477 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_RESET 0x0
13479 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_GET(value) (((value) & 0x0000000f) >> 0)
13481 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET(value) (((value) << 0) & 0x0000000f)
13497 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_LSB 4
13499 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_MSB 8
13501 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_WIDTH 5
13503 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET_MSK 0x000001f0
13505 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_CLR_MSK 0xfffffe0f
13507 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_RESET 0x0
13509 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_GET(value) (((value) & 0x000001f0) >> 4)
13511 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET(value) (((value) << 4) & 0x000001f0)
13527 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_LSB 9
13529 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_MSB 12
13531 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_WIDTH 4
13533 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET_MSK 0x00001e00
13535 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_CLR_MSK 0xffffe1ff
13537 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_RESET 0x0
13539 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_GET(value) (((value) & 0x00001e00) >> 9)
13541 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET(value) (((value) << 9) & 0x00001e00)
13557 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_LSB 13
13559 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_MSB 16
13561 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_WIDTH 4
13563 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET_MSK 0x0001e000
13565 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_CLR_MSK 0xfffe1fff
13567 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_RESET 0x0
13569 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_GET(value) (((value) & 0x0001e000) >> 13)
13571 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET(value) (((value) << 13) & 0x0001e000)
13586 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_LSB 17
13588 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_MSB 19
13590 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_WIDTH 3
13592 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET_MSK 0x000e0000
13594 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_CLR_MSK 0xfff1ffff
13596 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_RESET 0x0
13598 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_GET(value) (((value) & 0x000e0000) >> 17)
13600 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET(value) (((value) << 17) & 0x000e0000)
13615 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_LSB 20
13617 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_MSB 27
13619 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_WIDTH 8
13621 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET_MSK 0x0ff00000
13623 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_CLR_MSK 0xf00fffff
13625 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_RESET 0x0
13627 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_GET(value) (((value) & 0x0ff00000) >> 20)
13629 #define ALT_MPFE_IOHMC_REG_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET(value) (((value) << 20) & 0x0ff00000)
13631 #ifndef __ASSEMBLY__
13643 struct ALT_MPFE_IOHMC_REG_CALTIMING8_s
13645 volatile uint32_t cfg_t_param_mrr_to_valid : 4;
13646 volatile uint32_t cfg_t_param_mpr_to_valid : 5;
13647 volatile uint32_t cfg_t_param_mps_exit_cs_to_cke : 4;
13648 volatile uint32_t cfg_t_param_mps_exit_cke_to_cs : 4;
13649 volatile uint32_t cfg_t_param_rld3_multibank_ref_delay : 3;
13650 volatile uint32_t cfg_t_param_mmr_cmd_to_valid : 8;
13655 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING8_s ALT_MPFE_IOHMC_REG_CALTIMING8_t;
13659 #define ALT_MPFE_IOHMC_REG_CALTIMING8_RESET 0x00000000
13661 #define ALT_MPFE_IOHMC_REG_CALTIMING8_OFST 0x9c
13687 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_LSB 0
13689 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_MSB 7
13691 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_WIDTH 8
13693 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_SET_MSK 0x000000ff
13695 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_CLR_MSK 0xffffff00
13697 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_RESET 0x0
13699 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_GET(value) (((value) & 0x000000ff) >> 0)
13701 #define ALT_MPFE_IOHMC_REG_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_SET(value) (((value) << 0) & 0x000000ff)
13703 #ifndef __ASSEMBLY__
13715 struct ALT_MPFE_IOHMC_REG_CALTIMING9_s
13717 volatile uint32_t cfg_t_param_4_act_to_act : 8;
13722 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING9_s ALT_MPFE_IOHMC_REG_CALTIMING9_t;
13726 #define ALT_MPFE_IOHMC_REG_CALTIMING9_RESET 0x00000000
13728 #define ALT_MPFE_IOHMC_REG_CALTIMING9_OFST 0xa0
13754 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_LSB 0
13756 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_MSB 7
13758 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_WIDTH 8
13760 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_SET_MSK 0x000000ff
13762 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_CLR_MSK 0xffffff00
13764 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_RESET 0x0
13766 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_GET(value) (((value) & 0x000000ff) >> 0)
13768 #define ALT_MPFE_IOHMC_REG_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_SET(value) (((value) << 0) & 0x000000ff)
13770 #ifndef __ASSEMBLY__
13782 struct ALT_MPFE_IOHMC_REG_CALTIMING10_s
13784 volatile uint32_t cfg_t_param_16_act_to_act : 8;
13789 typedef struct ALT_MPFE_IOHMC_REG_CALTIMING10_s ALT_MPFE_IOHMC_REG_CALTIMING10_t;
13793 #define ALT_MPFE_IOHMC_REG_CALTIMING10_RESET 0x00000000
13795 #define ALT_MPFE_IOHMC_REG_CALTIMING10_OFST 0xa4
13826 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_LSB 0
13828 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_MSB 4
13830 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_WIDTH 5
13832 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET_MSK 0x0000001f
13834 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_CLR_MSK 0xffffffe0
13836 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_RESET 0x0
13838 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_GET(value) (((value) & 0x0000001f) >> 0)
13840 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET(value) (((value) << 0) & 0x0000001f)
13856 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_LSB 5
13858 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MSB 9
13860 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_WIDTH 5
13862 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET_MSK 0x000003e0
13864 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_CLR_MSK 0xfffffc1f
13866 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_RESET 0x0
13868 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_GET(value) (((value) & 0x000003e0) >> 5)
13870 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET(value) (((value) << 5) & 0x000003e0)
13886 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_LSB 10
13888 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MSB 13
13890 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_WIDTH 4
13892 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET_MSK 0x00003c00
13894 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_CLR_MSK 0xffffc3ff
13896 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_RESET 0x0
13898 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_GET(value) (((value) & 0x00003c00) >> 10)
13900 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET(value) (((value) << 10) & 0x00003c00)
13916 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_LSB 14
13918 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MSB 15
13920 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_WIDTH 2
13922 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET_MSK 0x0000c000
13924 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_CLR_MSK 0xffff3fff
13926 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_RESET 0x0
13928 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_GET(value) (((value) & 0x0000c000) >> 14)
13930 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET(value) (((value) << 14) & 0x0000c000)
13946 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_LSB 16
13948 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_MSB 18
13950 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_WIDTH 3
13952 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET_MSK 0x00070000
13954 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_CLR_MSK 0xfff8ffff
13956 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_RESET 0x0
13958 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_GET(value) (((value) & 0x00070000) >> 16)
13960 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET(value) (((value) << 16) & 0x00070000)
13962 #ifndef __ASSEMBLY__
13974 struct ALT_MPFE_IOHMC_REG_DRAMADDRW_s
13976 volatile uint32_t cfg_col_addr_width : 5;
13977 volatile uint32_t cfg_row_addr_width : 5;
13978 volatile uint32_t cfg_bank_addr_width : 4;
13979 volatile uint32_t cfg_bank_group_addr_width : 2;
13980 volatile uint32_t cfg_cs_addr_width : 3;
13985 typedef struct ALT_MPFE_IOHMC_REG_DRAMADDRW_s ALT_MPFE_IOHMC_REG_DRAMADDRW_t;
13989 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_RESET 0x00000000
13991 #define ALT_MPFE_IOHMC_REG_DRAMADDRW_OFST 0xa8
14018 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_LSB 0
14020 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_MSB 0
14022 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_WIDTH 1
14024 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_SET_MSK 0x00000001
14026 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_CLR_MSK 0xfffffffe
14028 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_RESET 0x0
14030 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_GET(value) (((value) & 0x00000001) >> 0)
14032 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_MR_CMD_TRIGGER_SET(value) (((value) << 0) & 0x00000001)
14034 #ifndef __ASSEMBLY__
14046 struct ALT_MPFE_IOHMC_REG_SIDEBAND0_s
14048 volatile uint32_t mr_cmd_trigger : 1;
14053 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND0_s ALT_MPFE_IOHMC_REG_SIDEBAND0_t;
14057 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_RESET 0x00000000
14059 #define ALT_MPFE_IOHMC_REG_SIDEBAND0_OFST 0xac
14089 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_LSB 0
14091 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_MSB 3
14093 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_WIDTH 4
14095 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_SET_MSK 0x0000000f
14097 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_CLR_MSK 0xfffffff0
14099 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_RESET 0x0
14101 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_GET(value) (((value) & 0x0000000f) >> 0)
14103 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_MMR_REFRESH_REQ_SET(value) (((value) << 0) & 0x0000000f)
14105 #ifndef __ASSEMBLY__
14117 struct ALT_MPFE_IOHMC_REG_SIDEBAND1_s
14119 volatile uint32_t mmr_refresh_req : 4;
14124 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND1_s ALT_MPFE_IOHMC_REG_SIDEBAND1_t;
14128 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_RESET 0x00000000
14130 #define ALT_MPFE_IOHMC_REG_SIDEBAND1_OFST 0xb0
14157 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_LSB 0
14159 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_MSB 0
14161 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_WIDTH 1
14163 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_SET_MSK 0x00000001
14165 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_CLR_MSK 0xfffffffe
14167 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_RESET 0x0
14169 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_GET(value) (((value) & 0x00000001) >> 0)
14171 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_MMR_ZQCAL_LONG_REQ_SET(value) (((value) << 0) & 0x00000001)
14173 #ifndef __ASSEMBLY__
14185 struct ALT_MPFE_IOHMC_REG_SIDEBAND2_s
14187 volatile uint32_t mmr_zqcal_long_req : 1;
14192 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND2_s ALT_MPFE_IOHMC_REG_SIDEBAND2_t;
14196 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_RESET 0x00000000
14198 #define ALT_MPFE_IOHMC_REG_SIDEBAND2_OFST 0xb4
14225 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_LSB 0
14227 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_MSB 0
14229 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_WIDTH 1
14231 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_SET_MSK 0x00000001
14233 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_CLR_MSK 0xfffffffe
14235 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_RESET 0x0
14237 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_GET(value) (((value) & 0x00000001) >> 0)
14239 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_SET(value) (((value) << 0) & 0x00000001)
14241 #ifndef __ASSEMBLY__
14253 struct ALT_MPFE_IOHMC_REG_SIDEBAND3_s
14255 volatile uint32_t mmr_zqcal_short_req : 1;
14260 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND3_s ALT_MPFE_IOHMC_REG_SIDEBAND3_t;
14264 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_RESET 0x00000000
14266 #define ALT_MPFE_IOHMC_REG_SIDEBAND3_OFST 0xb8
14296 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_LSB 0
14298 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_MSB 3
14300 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_WIDTH 4
14302 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_SET_MSK 0x0000000f
14304 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_CLR_MSK 0xfffffff0
14306 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_RESET 0x0
14308 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_GET(value) (((value) & 0x0000000f) >> 0)
14310 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_MMR_SELF_RFSH_REQ_SET(value) (((value) << 0) & 0x0000000f)
14312 #ifndef __ASSEMBLY__
14324 struct ALT_MPFE_IOHMC_REG_SIDEBAND4_s
14326 volatile uint32_t mmr_self_rfsh_req : 4;
14331 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND4_s ALT_MPFE_IOHMC_REG_SIDEBAND4_t;
14335 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_RESET 0x00000000
14337 #define ALT_MPFE_IOHMC_REG_SIDEBAND4_OFST 0xbc
14364 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_LSB 0
14366 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_MSB 0
14368 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_WIDTH 1
14370 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_SET_MSK 0x00000001
14372 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_CLR_MSK 0xfffffffe
14374 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_RESET 0x0
14376 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_GET(value) (((value) & 0x00000001) >> 0)
14378 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_MMR_DPD_MPS_REQ_SET(value) (((value) << 0) & 0x00000001)
14380 #ifndef __ASSEMBLY__
14392 struct ALT_MPFE_IOHMC_REG_SIDEBAND5_s
14394 volatile uint32_t mmr_dpd_mps_req : 1;
14399 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND5_s ALT_MPFE_IOHMC_REG_SIDEBAND5_t;
14403 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_RESET 0x00000000
14405 #define ALT_MPFE_IOHMC_REG_SIDEBAND5_OFST 0xc0
14431 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_LSB 0
14433 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_MSB 0
14435 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_WIDTH 1
14437 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_SET_MSK 0x00000001
14439 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_CLR_MSK 0xfffffffe
14441 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_RESET 0x0
14443 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_GET(value) (((value) & 0x00000001) >> 0)
14445 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_MR_CMD_ACK_SET(value) (((value) << 0) & 0x00000001)
14447 #ifndef __ASSEMBLY__
14459 struct ALT_MPFE_IOHMC_REG_SIDEBAND6_s
14461 const volatile uint32_t mr_cmd_ack : 1;
14466 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND6_s ALT_MPFE_IOHMC_REG_SIDEBAND6_t;
14470 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_RESET 0x00000000
14472 #define ALT_MPFE_IOHMC_REG_SIDEBAND6_OFST 0xc4
14498 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_LSB 0
14500 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_MSB 0
14502 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_WIDTH 1
14504 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_SET_MSK 0x00000001
14506 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_CLR_MSK 0xfffffffe
14508 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_RESET 0x0
14510 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_GET(value) (((value) & 0x00000001) >> 0)
14512 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_MMR_REFRESH_ACK_SET(value) (((value) << 0) & 0x00000001)
14514 #ifndef __ASSEMBLY__
14526 struct ALT_MPFE_IOHMC_REG_SIDEBAND7_s
14528 const volatile uint32_t mmr_refresh_ack : 1;
14533 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND7_s ALT_MPFE_IOHMC_REG_SIDEBAND7_t;
14537 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_RESET 0x00000000
14539 #define ALT_MPFE_IOHMC_REG_SIDEBAND7_OFST 0xc8
14565 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_LSB 0
14567 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_MSB 0
14569 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_WIDTH 1
14571 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_SET_MSK 0x00000001
14573 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_CLR_MSK 0xfffffffe
14575 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_RESET 0x0
14577 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_GET(value) (((value) & 0x00000001) >> 0)
14579 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_MMR_ZQCAL_ACK_SET(value) (((value) << 0) & 0x00000001)
14581 #ifndef __ASSEMBLY__
14593 struct ALT_MPFE_IOHMC_REG_SIDEBAND8_s
14595 const volatile uint32_t mmr_zqcal_ack : 1;
14600 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND8_s ALT_MPFE_IOHMC_REG_SIDEBAND8_t;
14604 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_RESET 0x00000000
14606 #define ALT_MPFE_IOHMC_REG_SIDEBAND8_OFST 0xcc
14632 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_LSB 0
14634 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_MSB 0
14636 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_WIDTH 1
14638 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_SET_MSK 0x00000001
14640 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_CLR_MSK 0xfffffffe
14642 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_RESET 0x0
14644 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_GET(value) (((value) & 0x00000001) >> 0)
14646 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_MMR_SELF_RFSH_ACK_SET(value) (((value) << 0) & 0x00000001)
14648 #ifndef __ASSEMBLY__
14660 struct ALT_MPFE_IOHMC_REG_SIDEBAND9_s
14662 const volatile uint32_t mmr_self_rfsh_ack : 1;
14667 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND9_s ALT_MPFE_IOHMC_REG_SIDEBAND9_t;
14671 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_RESET 0x00000000
14673 #define ALT_MPFE_IOHMC_REG_SIDEBAND9_OFST 0xd0
14700 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_LSB 0
14702 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_MSB 0
14704 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_WIDTH 1
14706 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_SET_MSK 0x00000001
14708 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_CLR_MSK 0xfffffffe
14710 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_RESET 0x0
14712 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_GET(value) (((value) & 0x00000001) >> 0)
14714 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_MMR_DPD_MPS_ACK_SET(value) (((value) << 0) & 0x00000001)
14716 #ifndef __ASSEMBLY__
14728 struct ALT_MPFE_IOHMC_REG_SIDEBAND10_s
14730 const volatile uint32_t mmr_dpd_mps_ack : 1;
14735 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND10_s ALT_MPFE_IOHMC_REG_SIDEBAND10_t;
14739 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_RESET 0x00000000
14741 #define ALT_MPFE_IOHMC_REG_SIDEBAND10_OFST 0xd4
14767 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_LSB 0
14769 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_MSB 0
14771 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_WIDTH 1
14773 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_SET_MSK 0x00000001
14775 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_CLR_MSK 0xfffffffe
14777 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_RESET 0x0
14779 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_GET(value) (((value) & 0x00000001) >> 0)
14781 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_MMR_AUTO_PD_ACK_SET(value) (((value) << 0) & 0x00000001)
14783 #ifndef __ASSEMBLY__
14795 struct ALT_MPFE_IOHMC_REG_SIDEBAND11_s
14797 const volatile uint32_t mmr_auto_pd_ack : 1;
14802 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND11_s ALT_MPFE_IOHMC_REG_SIDEBAND11_t;
14806 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_RESET 0x00000000
14808 #define ALT_MPFE_IOHMC_REG_SIDEBAND11_OFST 0xd8
14843 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_LSB 0
14845 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_MSB 2
14847 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_WIDTH 3
14849 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_SET_MSK 0x00000007
14851 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_CLR_MSK 0xfffffff8
14853 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_RESET 0x0
14855 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_GET(value) (((value) & 0x00000007) >> 0)
14857 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_TYPE_SET(value) (((value) << 0) & 0x00000007)
14872 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_LSB 3
14874 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_MSB 6
14876 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_WIDTH 4
14878 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_SET_MSK 0x00000078
14880 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_CLR_MSK 0xffffff87
14882 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_RESET 0x0
14884 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_GET(value) (((value) & 0x00000078) >> 3)
14886 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_MR_CMD_RANK_SET(value) (((value) << 3) & 0x00000078)
14888 #ifndef __ASSEMBLY__
14900 struct ALT_MPFE_IOHMC_REG_SIDEBAND12_s
14902 volatile uint32_t mr_cmd_type : 3;
14903 volatile uint32_t mr_cmd_rank : 4;
14908 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND12_s ALT_MPFE_IOHMC_REG_SIDEBAND12_t;
14912 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_RESET 0x00000000
14914 #define ALT_MPFE_IOHMC_REG_SIDEBAND12_OFST 0xdc
15003 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_LSB 0
15005 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_MSB 31
15007 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_WIDTH 32
15009 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_SET_MSK 0xffffffff
15011 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_CLR_MSK 0x00000000
15013 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_RESET 0x0
15015 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_GET(value) (((value) & 0xffffffff) >> 0)
15017 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_MR_CMD_OPCODE_SET(value) (((value) << 0) & 0xffffffff)
15019 #ifndef __ASSEMBLY__
15031 struct ALT_MPFE_IOHMC_REG_SIDEBAND13_s
15033 volatile uint32_t mr_cmd_opcode : 32;
15037 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND13_s ALT_MPFE_IOHMC_REG_SIDEBAND13_t;
15041 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_RESET 0x00000000
15043 #define ALT_MPFE_IOHMC_REG_SIDEBAND13_OFST 0xe0
15070 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_LSB 0
15072 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_MSB 15
15074 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_WIDTH 16
15076 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_SET_MSK 0x0000ffff
15078 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_CLR_MSK 0xffff0000
15080 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_RESET 0x0
15082 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_GET(value) (((value) & 0x0000ffff) >> 0)
15084 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_MMR_REFRESH_BANK_SET(value) (((value) << 0) & 0x0000ffff)
15086 #ifndef __ASSEMBLY__
15098 struct ALT_MPFE_IOHMC_REG_SIDEBAND14_s
15100 volatile uint32_t mmr_refresh_bank : 16;
15105 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND14_s ALT_MPFE_IOHMC_REG_SIDEBAND14_t;
15109 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_RESET 0x00000000
15111 #define ALT_MPFE_IOHMC_REG_SIDEBAND14_OFST 0xe4
15137 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_LSB 0
15139 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_MSB 3
15141 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_WIDTH 4
15143 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_SET_MSK 0x0000000f
15145 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_CLR_MSK 0xfffffff0
15147 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_RESET 0x0
15149 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_GET(value) (((value) & 0x0000000f) >> 0)
15151 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_MMR_STALL_RANK_SET(value) (((value) << 0) & 0x0000000f)
15153 #ifndef __ASSEMBLY__
15165 struct ALT_MPFE_IOHMC_REG_SIDEBAND15_s
15167 volatile uint32_t mmr_stall_rank : 4;
15172 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND15_s ALT_MPFE_IOHMC_REG_SIDEBAND15_t;
15176 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_RESET 0x00000000
15178 #define ALT_MPFE_IOHMC_REG_SIDEBAND15_OFST 0xe8
15206 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_LSB 0
15208 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_MSB 0
15210 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_WIDTH 1
15212 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_SET_MSK 0x00000001
15214 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_CLR_MSK 0xfffffffe
15216 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_RESET 0x0
15218 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_GET(value) (((value) & 0x00000001) >> 0)
15220 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_SUCCESS_SET(value) (((value) << 0) & 0x00000001)
15235 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_LSB 1
15237 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_MSB 1
15239 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_WIDTH 1
15241 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_SET_MSK 0x00000002
15243 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_CLR_MSK 0xfffffffd
15245 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_RESET 0x0
15247 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_GET(value) (((value) & 0x00000002) >> 1)
15249 #define ALT_MPFE_IOHMC_REG_DRAMSTS_PHY_CAL_FAIL_SET(value) (((value) << 1) & 0x00000002)
15251 #ifndef __ASSEMBLY__
15263 struct ALT_MPFE_IOHMC_REG_DRAMSTS_s
15265 const volatile uint32_t phy_cal_success : 1;
15266 const volatile uint32_t phy_cal_fail : 1;
15271 typedef struct ALT_MPFE_IOHMC_REG_DRAMSTS_s ALT_MPFE_IOHMC_REG_DRAMSTS_t;
15275 #define ALT_MPFE_IOHMC_REG_DRAMSTS_RESET 0x00000000
15277 #define ALT_MPFE_IOHMC_REG_DRAMSTS_OFST 0xec
15303 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_LSB 0
15305 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_MSB 0
15307 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_WIDTH 1
15309 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_SET_MSK 0x00000001
15311 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_CLR_MSK 0xfffffffe
15313 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_RESET 0x0
15315 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_GET(value) (((value) & 0x00000001) >> 0)
15317 #define ALT_MPFE_IOHMC_REG_DBGDONE_DBG_DONE_SET(value) (((value) << 0) & 0x00000001)
15319 #ifndef __ASSEMBLY__
15331 struct ALT_MPFE_IOHMC_REG_DBGDONE_s
15333 const volatile uint32_t dbg_done : 1;
15338 typedef struct ALT_MPFE_IOHMC_REG_DBGDONE_s ALT_MPFE_IOHMC_REG_DBGDONE_t;
15342 #define ALT_MPFE_IOHMC_REG_DBGDONE_RESET 0x00000000
15344 #define ALT_MPFE_IOHMC_REG_DBGDONE_OFST 0xf0
15369 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_LSB 0
15371 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_MSB 31
15373 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_WIDTH 32
15375 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_SET_MSK 0xffffffff
15377 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_CLR_MSK 0x00000000
15379 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_RESET 0x0
15381 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_GET(value) (((value) & 0xffffffff) >> 0)
15383 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_DBG_SIGNALS_OUT_SET(value) (((value) << 0) & 0xffffffff)
15385 #ifndef __ASSEMBLY__
15397 struct ALT_MPFE_IOHMC_REG_DBGSIGNALS_s
15399 const volatile uint32_t dbg_signals_out : 32;
15403 typedef struct ALT_MPFE_IOHMC_REG_DBGSIGNALS_s ALT_MPFE_IOHMC_REG_DBGSIGNALS_t;
15407 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_RESET 0x00000000
15409 #define ALT_MPFE_IOHMC_REG_DBGSIGNALS_OFST 0xf4
15436 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_LSB 0
15438 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_MSB 0
15440 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_WIDTH 1
15442 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_SET_MSK 0x00000001
15444 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_CLR_MSK 0xfffffffe
15446 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_RESET 0x0
15448 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_GET(value) (((value) & 0x00000001) >> 0)
15450 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ZERO_RESET_SET(value) (((value) << 0) & 0x00000001)
15465 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_LSB 1
15467 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_MSB 1
15469 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_WIDTH 1
15471 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_SET_MSK 0x00000002
15473 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_CLR_MSK 0xfffffffd
15475 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_RESET 0x0
15477 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_GET(value) (((value) & 0x00000002) >> 1)
15479 #define ALT_MPFE_IOHMC_REG_DBGRESET_COUNTER_ONE_RESET_SET(value) (((value) << 1) & 0x00000002)
15481 #ifndef __ASSEMBLY__
15493 struct ALT_MPFE_IOHMC_REG_DBGRESET_s
15495 volatile uint32_t counter_zero_reset : 1;
15496 volatile uint32_t counter_one_reset : 1;
15501 typedef struct ALT_MPFE_IOHMC_REG_DBGRESET_s ALT_MPFE_IOHMC_REG_DBGRESET_t;
15505 #define ALT_MPFE_IOHMC_REG_DBGRESET_RESET 0x00000000
15507 #define ALT_MPFE_IOHMC_REG_DBGRESET_OFST 0xf8
15532 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_LSB 0
15534 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_MSB 31
15536 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_WIDTH 32
15538 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_SET_MSK 0xffffffff
15540 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_CLR_MSK 0x00000000
15542 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_RESET 0x0
15544 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_GET(value) (((value) & 0xffffffff) >> 0)
15546 #define ALT_MPFE_IOHMC_REG_DBGMATCH_COUNTER_ONE_SET(value) (((value) << 0) & 0xffffffff)
15548 #ifndef __ASSEMBLY__
15560 struct ALT_MPFE_IOHMC_REG_DBGMATCH_s
15562 const volatile uint32_t counter_one : 32;
15566 typedef struct ALT_MPFE_IOHMC_REG_DBGMATCH_s ALT_MPFE_IOHMC_REG_DBGMATCH_t;
15570 #define ALT_MPFE_IOHMC_REG_DBGMATCH_RESET 0x00000000
15572 #define ALT_MPFE_IOHMC_REG_DBGMATCH_OFST 0xfc
15597 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_LSB 0
15599 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_MSB 31
15601 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_WIDTH 32
15603 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_SET_MSK 0xffffffff
15605 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_CLR_MSK 0x00000000
15607 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_RESET 0x0
15609 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_GET(value) (((value) & 0xffffffff) >> 0)
15611 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_COUNTER_ZERO_MASK_SET(value) (((value) << 0) & 0xffffffff)
15613 #ifndef __ASSEMBLY__
15625 struct ALT_MPFE_IOHMC_REG_COUNTER0MASK_s
15627 volatile uint32_t counter_zero_mask : 32;
15631 typedef struct ALT_MPFE_IOHMC_REG_COUNTER0MASK_s ALT_MPFE_IOHMC_REG_COUNTER0MASK_t;
15635 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_RESET 0x00000000
15637 #define ALT_MPFE_IOHMC_REG_COUNTER0MASK_OFST 0x100
15662 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_LSB 0
15664 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_MSB 31
15666 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_WIDTH 32
15668 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_SET_MSK 0xffffffff
15670 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_CLR_MSK 0x00000000
15672 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_RESET 0x0
15674 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_GET(value) (((value) & 0xffffffff) >> 0)
15676 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_COUNTER_ONE_MASK_SET(value) (((value) << 0) & 0xffffffff)
15678 #ifndef __ASSEMBLY__
15690 struct ALT_MPFE_IOHMC_REG_COUNTER1MASK_s
15692 volatile uint32_t counter_one_mask : 32;
15696 typedef struct ALT_MPFE_IOHMC_REG_COUNTER1MASK_s ALT_MPFE_IOHMC_REG_COUNTER1MASK_t;
15700 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_RESET 0x00000000
15702 #define ALT_MPFE_IOHMC_REG_COUNTER1MASK_OFST 0x104
15727 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_LSB 0
15729 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_MSB 31
15731 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_WIDTH 32
15733 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_SET_MSK 0xffffffff
15735 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_CLR_MSK 0x00000000
15737 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_RESET 0x0
15739 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_GET(value) (((value) & 0xffffffff) >> 0)
15741 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_COUNTER_ZERO_MATCH_SET(value) (((value) << 0) & 0xffffffff)
15743 #ifndef __ASSEMBLY__
15755 struct ALT_MPFE_IOHMC_REG_COUNTER0MATCH_s
15757 volatile uint32_t counter_zero_match : 32;
15761 typedef struct ALT_MPFE_IOHMC_REG_COUNTER0MATCH_s ALT_MPFE_IOHMC_REG_COUNTER0MATCH_t;
15765 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_RESET 0x00000000
15767 #define ALT_MPFE_IOHMC_REG_COUNTER0MATCH_OFST 0x108
15792 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_LSB 0
15794 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_MSB 31
15796 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_WIDTH 32
15798 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_SET_MSK 0xffffffff
15800 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_CLR_MSK 0x00000000
15802 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_RESET 0x0
15804 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_GET(value) (((value) & 0xffffffff) >> 0)
15806 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_COUNTER_ONE_MATCH_SET(value) (((value) << 0) & 0xffffffff)
15808 #ifndef __ASSEMBLY__
15820 struct ALT_MPFE_IOHMC_REG_COUNTER1MATCH_s
15822 volatile uint32_t counter_one_match : 32;
15826 typedef struct ALT_MPFE_IOHMC_REG_COUNTER1MATCH_s ALT_MPFE_IOHMC_REG_COUNTER1MATCH_t;
15830 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_RESET 0x00000000
15832 #define ALT_MPFE_IOHMC_REG_COUNTER1MATCH_OFST 0x10c
15858 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_LSB 0
15860 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_MSB 15
15862 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_WIDTH 16
15864 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_SET_MSK 0x0000ffff
15866 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_CLR_MSK 0xffff0000
15868 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_RESET 0x0
15870 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_GET(value) (((value) & 0x0000ffff) >> 0)
15872 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_NIOS_RESERVE0_SET(value) (((value) << 0) & 0x0000ffff)
15874 #ifndef __ASSEMBLY__
15886 struct ALT_MPFE_IOHMC_REG_NIOSRESERVE0_s
15888 volatile uint32_t nios_reserve0 : 16;
15893 typedef struct ALT_MPFE_IOHMC_REG_NIOSRESERVE0_s ALT_MPFE_IOHMC_REG_NIOSRESERVE0_t;
15897 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_RESET 0x00000000
15899 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE0_OFST 0x110
15925 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_LSB 0
15927 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_MSB 15
15929 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_WIDTH 16
15931 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_SET_MSK 0x0000ffff
15933 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_CLR_MSK 0xffff0000
15935 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_RESET 0x0
15937 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_GET(value) (((value) & 0x0000ffff) >> 0)
15939 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_NIOS_RESERVE1_SET(value) (((value) << 0) & 0x0000ffff)
15941 #ifndef __ASSEMBLY__
15953 struct ALT_MPFE_IOHMC_REG_NIOSRESERVE1_s
15955 volatile uint32_t nios_reserve1 : 16;
15960 typedef struct ALT_MPFE_IOHMC_REG_NIOSRESERVE1_s ALT_MPFE_IOHMC_REG_NIOSRESERVE1_t;
15964 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_RESET 0x00000000
15966 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE1_OFST 0x114
15992 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_LSB 0
15994 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_MSB 15
15996 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_WIDTH 16
15998 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_SET_MSK 0x0000ffff
16000 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_CLR_MSK 0xffff0000
16002 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_RESET 0x0
16004 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_GET(value) (((value) & 0x0000ffff) >> 0)
16006 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_NIOS_RESERVE2_SET(value) (((value) << 0) & 0x0000ffff)
16008 #ifndef __ASSEMBLY__
16020 struct ALT_MPFE_IOHMC_REG_NIOSRESERVE2_s
16022 volatile uint32_t nios_reserve2 : 16;
16027 typedef struct ALT_MPFE_IOHMC_REG_NIOSRESERVE2_s ALT_MPFE_IOHMC_REG_NIOSRESERVE2_t;
16031 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_RESET 0x00000000
16033 #define ALT_MPFE_IOHMC_REG_NIOSRESERVE2_OFST 0x118
16059 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_LSB 0
16061 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_MSB 19
16063 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_WIDTH 20
16065 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_SET_MSK 0x000fffff
16067 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_CLR_MSK 0xfff00000
16069 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_RESET 0x0
16071 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_GET(value) (((value) & 0x000fffff) >> 0)
16073 #define ALT_MPFE_IOHMC_REG_SBCFG8_CFG_SB_DDR4_MR5_SET(value) (((value) << 0) & 0x000fffff)
16075 #ifndef __ASSEMBLY__
16087 struct ALT_MPFE_IOHMC_REG_SBCFG8_s
16089 volatile uint32_t cfg_sb_ddr4_mr5 : 20;
16094 typedef struct ALT_MPFE_IOHMC_REG_SBCFG8_s ALT_MPFE_IOHMC_REG_SBCFG8_t;
16098 #define ALT_MPFE_IOHMC_REG_SBCFG8_RESET 0x00000000
16100 #define ALT_MPFE_IOHMC_REG_SBCFG8_OFST 0x11c
16128 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_LSB 0
16130 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_MSB 0
16132 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_WIDTH 1
16134 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_SET_MSK 0x00000001
16136 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_CLR_MSK 0xfffffffe
16138 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_RESET 0x0
16140 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_GET(value) (((value) & 0x00000001) >> 0)
16142 #define ALT_MPFE_IOHMC_REG_SBCFG9_CFG_DDR4_MPS_ADDRMIRROR_SET(value) (((value) << 0) & 0x00000001)
16144 #ifndef __ASSEMBLY__
16156 struct ALT_MPFE_IOHMC_REG_SBCFG9_s
16158 volatile uint32_t cfg_ddr4_mps_addrmirror : 1;
16163 typedef struct ALT_MPFE_IOHMC_REG_SBCFG9_s ALT_MPFE_IOHMC_REG_SBCFG9_t;
16167 #define ALT_MPFE_IOHMC_REG_SBCFG9_RESET 0x00000000
16169 #define ALT_MPFE_IOHMC_REG_SBCFG9_OFST 0x120
16210 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_LSB 0
16212 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_MSB 3
16214 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_WIDTH 4
16216 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_SET_MSK 0x0000000f
16218 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_CLR_MSK 0xfffffff0
16220 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_RESET 0x0
16222 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_GET(value) (((value) & 0x0000000f) >> 0)
16224 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM0_SET(value) (((value) << 0) & 0x0000000f)
16249 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_LSB 4
16251 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_MSB 7
16253 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_WIDTH 4
16255 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_SET_MSK 0x000000f0
16257 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_CLR_MSK 0xffffff0f
16259 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_RESET 0x0
16261 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_GET(value) (((value) & 0x000000f0) >> 4)
16263 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM1_SET(value) (((value) << 4) & 0x000000f0)
16288 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_LSB 8
16290 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_MSB 11
16292 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_WIDTH 4
16294 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_SET_MSK 0x00000f00
16296 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_CLR_MSK 0xfffff0ff
16298 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_RESET 0x0
16300 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_GET(value) (((value) & 0x00000f00) >> 8)
16302 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM2_SET(value) (((value) << 8) & 0x00000f00)
16327 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_LSB 12
16329 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_MSB 15
16331 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_WIDTH 4
16333 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_SET_MSK 0x0000f000
16335 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_CLR_MSK 0xffff0fff
16337 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_RESET 0x0
16339 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_GET(value) (((value) & 0x0000f000) >> 12)
16341 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_LR_NUM3_SET(value) (((value) << 12) & 0x0000f000)
16356 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_LSB 16
16358 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_MSB 17
16360 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_WIDTH 2
16362 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_SET_MSK 0x00030000
16364 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_CLR_MSK 0xfffcffff
16366 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_RESET 0x0
16368 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_GET(value) (((value) & 0x00030000) >> 16)
16370 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_CID_ADDR_WIDTH_SET(value) (((value) << 16) & 0x00030000)
16389 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_LSB 18
16391 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_MSB 18
16393 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_WIDTH 1
16395 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_SET_MSK 0x00040000
16397 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_CLR_MSK 0xfffbffff
16399 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_RESET 0x0
16401 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_GET(value) (((value) & 0x00040000) >> 18)
16403 #define ALT_MPFE_IOHMC_REG_3DS0_CFG_3DS_PR_STAG_ENABLE_SET(value) (((value) << 18) & 0x00040000)
16405 #ifndef __ASSEMBLY__
16417 struct ALT_MPFE_IOHMC_REG_3DS0_s
16419 volatile uint32_t cfg_3ds_lr_num0 : 4;
16420 volatile uint32_t cfg_3ds_lr_num1 : 4;
16421 volatile uint32_t cfg_3ds_lr_num2 : 4;
16422 volatile uint32_t cfg_3ds_lr_num3 : 4;
16423 volatile uint32_t cfg_cid_addr_width : 2;
16424 volatile uint32_t cfg_3ds_pr_stag_enable : 1;
16429 typedef struct ALT_MPFE_IOHMC_REG_3DS0_s ALT_MPFE_IOHMC_REG_3DS0_t;
16433 #define ALT_MPFE_IOHMC_REG_3DS0_RESET 0x00000000
16435 #define ALT_MPFE_IOHMC_REG_3DS0_OFST 0x124
16462 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_LSB 0
16464 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_MSB 6
16466 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_WIDTH 7
16468 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_SET_MSK 0x0000007f
16470 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_CLR_MSK 0xffffff80
16472 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_RESET 0x0
16474 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_GET(value) (((value) & 0x0000007f) >> 0)
16476 #define ALT_MPFE_IOHMC_REG_3DS1_CFG_3DS_REF2REF_DLR_SET(value) (((value) << 0) & 0x0000007f)
16478 #ifndef __ASSEMBLY__
16490 struct ALT_MPFE_IOHMC_REG_3DS1_s
16492 volatile uint32_t cfg_3ds_ref2ref_dlr : 7;
16497 typedef struct ALT_MPFE_IOHMC_REG_3DS1_s ALT_MPFE_IOHMC_REG_3DS1_t;
16501 #define ALT_MPFE_IOHMC_REG_3DS1_RESET 0x00000000
16503 #define ALT_MPFE_IOHMC_REG_3DS1_OFST 0x128
16555 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_LSB 0
16557 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_MSB 8
16559 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_WIDTH 9
16561 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_SET_MSK 0x000001ff
16563 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_CLR_MSK 0xfffffe00
16565 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_RESET 0x0
16567 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_GET(value) (((value) & 0x000001ff) >> 0)
16569 #define ALT_MPFE_IOHMC_REG_3DS2_CFG_CHIP_ID_SET(value) (((value) << 0) & 0x000001ff)
16571 #ifndef __ASSEMBLY__
16583 struct ALT_MPFE_IOHMC_REG_3DS2_s
16585 volatile uint32_t cfg_chip_id : 9;
16590 typedef struct ALT_MPFE_IOHMC_REG_3DS2_s ALT_MPFE_IOHMC_REG_3DS2_t;
16594 #define ALT_MPFE_IOHMC_REG_3DS2_RESET 0x00000000
16596 #define ALT_MPFE_IOHMC_REG_3DS2_OFST 0x12c
16629 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_LSB 0
16631 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_MSB 0
16633 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_WIDTH 1
16635 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_SET_MSK 0x00000001
16637 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_CLR_MSK 0xfffffffe
16639 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_RESET 0x0
16641 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_GET(value) (((value) & 0x00000001) >> 0)
16643 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_ARBITER_REG_ENA_SET(value) (((value) << 0) & 0x00000001)
16660 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_LSB 1
16662 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_MSB 1
16664 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_WIDTH 1
16666 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_SET_MSK 0x00000002
16668 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_CLR_MSK 0xfffffffd
16670 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_RESET 0x0
16672 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_GET(value) (((value) & 0x00000002) >> 1)
16674 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_WB_PTR_REG_ENA_SET(value) (((value) << 1) & 0x00000002)
16691 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_LSB 2
16693 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_MSB 2
16695 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_WIDTH 1
16697 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_SET_MSK 0x00000004
16699 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_CLR_MSK 0xfffffffb
16701 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_RESET 0x0
16703 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_GET(value) (((value) & 0x00000004) >> 2)
16705 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_RB_PTR_REG_ENA_SET(value) (((value) << 2) & 0x00000004)
16720 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_LSB 3
16722 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_MSB 3
16724 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_WIDTH 1
16726 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_SET_MSK 0x00000008
16728 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_CLR_MSK 0xfffffff7
16730 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_RESET 0x0
16732 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_GET(value) (((value) & 0x00000008) >> 3)
16734 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_REG_ENA_SET(value) (((value) << 3) & 0x00000008)
16749 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_LSB 5
16751 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_MSB 5
16753 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_WIDTH 1
16755 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_SET_MSK 0x00000020
16757 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_CLR_MSK 0xffffffdf
16759 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_RESET 0x0
16761 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_GET(value) (((value) & 0x00000020) >> 5)
16763 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CTL2DBC_TILE_REG_ENA_SET(value) (((value) << 5) & 0x00000020)
16780 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_LSB 6
16782 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_MSB 6
16784 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_WIDTH 1
16786 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_SET_MSK 0x00000040
16788 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_CLR_MSK 0xffffffbf
16790 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_RESET 0x0
16792 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_GET(value) (((value) & 0x00000040) >> 6)
16794 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_AC_TILE_REG_ENA_SET(value) (((value) << 6) & 0x00000040)
16809 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_LSB 7
16811 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_MSB 7
16813 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_WIDTH 1
16815 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_SET_MSK 0x00000080
16817 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_CLR_MSK 0xffffff7f
16819 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_RESET 0x0
16821 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_GET(value) (((value) & 0x00000080) >> 7)
16823 #define ALT_MPFE_IOHMC_REG_PIPELINE0_CFG_CMD_FIFO_PIPELINE_EN_SET(value) (((value) << 7) & 0x00000080)
16825 #ifndef __ASSEMBLY__
16837 struct ALT_MPFE_IOHMC_REG_PIPELINE0_s
16839 volatile uint32_t cfg_arbiter_reg_ena : 1;
16840 volatile uint32_t cfg_wb_ptr_reg_ena : 1;
16841 volatile uint32_t cfg_rb_ptr_reg_ena : 1;
16842 volatile uint32_t cfg_ctl2dbc_reg_ena : 1;
16844 volatile uint32_t cfg_ctl2dbc_tile_reg_ena : 1;
16845 volatile uint32_t cfg_ac_tile_reg_ena : 1;
16846 volatile uint32_t cfg_cmd_fifo_pipeline_en : 1;
16851 typedef struct ALT_MPFE_IOHMC_REG_PIPELINE0_s ALT_MPFE_IOHMC_REG_PIPELINE0_t;
16855 #define ALT_MPFE_IOHMC_REG_PIPELINE0_RESET 0x00000000
16857 #define ALT_MPFE_IOHMC_REG_PIPELINE0_OFST 0x130
16903 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_LSB 0
16905 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_MSB 7
16907 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_WIDTH 8
16909 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_SET_MSK 0x000000ff
16911 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_CLR_MSK 0xffffff00
16913 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_RESET 0x0
16915 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_GET(value) (((value) & 0x000000ff) >> 0)
16917 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_CFG_MEMCLKGATE_SETTING_SET(value) (((value) << 0) & 0x000000ff)
16919 #ifndef __ASSEMBLY__
16931 struct ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_s
16933 volatile uint32_t cfg_memclkgate_setting : 8;
16938 typedef struct ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_s ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_t;
16942 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_RESET 0x00000000
16944 #define ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_OFST 0x138
17013 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_LSB 0
17015 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_MSB 31
17017 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_WIDTH 32
17019 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_SET_MSK 0xffffffff
17021 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_CLR_MSK 0x00000000
17023 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_RESET 0x0
17025 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_GET(value) (((value) & 0xffffffff) >> 0)
17027 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_MMR_3DS_REFRESH_ACK_SET(value) (((value) << 0) & 0xffffffff)
17029 #ifndef __ASSEMBLY__
17041 struct ALT_MPFE_IOHMC_REG_SIDEBAND16_s
17043 const volatile uint32_t mmr_3ds_refresh_ack : 32;
17047 typedef struct ALT_MPFE_IOHMC_REG_SIDEBAND16_s ALT_MPFE_IOHMC_REG_SIDEBAND16_t;
17051 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_RESET 0x00000000
17053 #define ALT_MPFE_IOHMC_REG_SIDEBAND16_OFST 0x13c
17055 #ifndef __ASSEMBLY__
17067 struct ALT_MPFE_IOHMC_s
17069 volatile ALT_MPFE_IOHMC_REG_DBGCFG0_t reg_dbgcfg0;
17070 volatile ALT_MPFE_IOHMC_REG_DBGCFG1_t reg_dbgcfg1;
17071 volatile ALT_MPFE_IOHMC_REG_DBGCFG2_t reg_dbgcfg2;
17072 volatile ALT_MPFE_IOHMC_REG_DBGCFG3_t reg_dbgcfg3;
17073 volatile ALT_MPFE_IOHMC_REG_DBGCFG4_t reg_dbgcfg4;
17074 volatile ALT_MPFE_IOHMC_REG_DBGCFG5_t reg_dbgcfg5;
17075 volatile ALT_MPFE_IOHMC_REG_DBGCFG6_t reg_dbgcfg6;
17076 volatile ALT_MPFE_IOHMC_REG_RESERVE0_t reg_reserve0;
17077 volatile ALT_MPFE_IOHMC_REG_RESERVE1_t reg_reserve1;
17078 volatile ALT_MPFE_IOHMC_REG_RESERVE2_t reg_reserve2;
17079 volatile ALT_MPFE_IOHMC_REG_CTRLCFG0_t reg_ctrlcfg0;
17080 volatile ALT_MPFE_IOHMC_REG_CTRLCFG1_t reg_ctrlcfg1;
17081 volatile ALT_MPFE_IOHMC_REG_CTRLCFG2_t reg_ctrlcfg2;
17082 volatile ALT_MPFE_IOHMC_REG_CTRLCFG3_t reg_ctrlcfg3;
17083 volatile ALT_MPFE_IOHMC_REG_CTRLCFG4_t reg_ctrlcfg4;
17084 volatile ALT_MPFE_IOHMC_REG_CTRLCFG5_t reg_ctrlcfg5;
17085 volatile ALT_MPFE_IOHMC_REG_CTRLCFG6_t reg_ctrlcfg6;
17086 volatile ALT_MPFE_IOHMC_REG_CTRLCFG7_t reg_ctrlcfg7;
17087 volatile ALT_MPFE_IOHMC_REG_CTRLCFG8_t reg_ctrlcfg8;
17088 volatile ALT_MPFE_IOHMC_REG_CTRLCFG9_t reg_ctrlcfg9;
17089 volatile ALT_MPFE_IOHMC_REG_DRAMTIMING0_t reg_dramtiming0;
17090 volatile ALT_MPFE_IOHMC_REG_DRAMODT0_t reg_dramodt0;
17091 volatile ALT_MPFE_IOHMC_REG_DRAMODT1_t reg_dramodt1;
17092 volatile ALT_MPFE_IOHMC_REG_SBCFG0_t reg_sbcfg0;
17093 volatile ALT_MPFE_IOHMC_REG_SBCFG1_t reg_sbcfg1;
17094 volatile ALT_MPFE_IOHMC_REG_SBCFG2_t reg_sbcfg2;
17095 volatile ALT_MPFE_IOHMC_REG_SBCFG3_t reg_sbcfg3;
17096 volatile ALT_MPFE_IOHMC_REG_SBCFG4_t reg_sbcfg4;
17097 volatile ALT_MPFE_IOHMC_REG_SBCFG5_t reg_sbcfg5;
17098 volatile ALT_MPFE_IOHMC_REG_SBCFG6_t reg_sbcfg6;
17099 volatile ALT_MPFE_IOHMC_REG_SBCFG7_t reg_sbcfg7;
17100 volatile ALT_MPFE_IOHMC_REG_CALTIMING0_t reg_caltiming0;
17101 volatile ALT_MPFE_IOHMC_REG_CALTIMING1_t reg_caltiming1;
17102 volatile ALT_MPFE_IOHMC_REG_CALTIMING2_t reg_caltiming2;
17103 volatile ALT_MPFE_IOHMC_REG_CALTIMING3_t reg_caltiming3;
17104 volatile ALT_MPFE_IOHMC_REG_CALTIMING4_t reg_caltiming4;
17105 volatile ALT_MPFE_IOHMC_REG_CALTIMING5_t reg_caltiming5;
17106 volatile ALT_MPFE_IOHMC_REG_CALTIMING6_t reg_caltiming6;
17107 volatile ALT_MPFE_IOHMC_REG_CALTIMING7_t reg_caltiming7;
17108 volatile ALT_MPFE_IOHMC_REG_CALTIMING8_t reg_caltiming8;
17109 volatile ALT_MPFE_IOHMC_REG_CALTIMING9_t reg_caltiming9;
17110 volatile ALT_MPFE_IOHMC_REG_CALTIMING10_t reg_caltiming10;
17111 volatile ALT_MPFE_IOHMC_REG_DRAMADDRW_t reg_dramaddrw;
17112 volatile ALT_MPFE_IOHMC_REG_SIDEBAND0_t reg_sideband0;
17113 volatile ALT_MPFE_IOHMC_REG_SIDEBAND1_t reg_sideband1;
17114 volatile ALT_MPFE_IOHMC_REG_SIDEBAND2_t reg_sideband2;
17115 volatile ALT_MPFE_IOHMC_REG_SIDEBAND3_t reg_sideband3;
17116 volatile ALT_MPFE_IOHMC_REG_SIDEBAND4_t reg_sideband4;
17117 volatile ALT_MPFE_IOHMC_REG_SIDEBAND5_t reg_sideband5;
17118 volatile ALT_MPFE_IOHMC_REG_SIDEBAND6_t reg_sideband6;
17119 volatile ALT_MPFE_IOHMC_REG_SIDEBAND7_t reg_sideband7;
17120 volatile ALT_MPFE_IOHMC_REG_SIDEBAND8_t reg_sideband8;
17121 volatile ALT_MPFE_IOHMC_REG_SIDEBAND9_t reg_sideband9;
17122 volatile ALT_MPFE_IOHMC_REG_SIDEBAND10_t reg_sideband10;
17123 volatile ALT_MPFE_IOHMC_REG_SIDEBAND11_t reg_sideband11;
17124 volatile ALT_MPFE_IOHMC_REG_SIDEBAND12_t reg_sideband12;
17125 volatile ALT_MPFE_IOHMC_REG_SIDEBAND13_t reg_sideband13;
17126 volatile ALT_MPFE_IOHMC_REG_SIDEBAND14_t reg_sideband14;
17127 volatile ALT_MPFE_IOHMC_REG_SIDEBAND15_t reg_sideband15;
17128 volatile ALT_MPFE_IOHMC_REG_DRAMSTS_t reg_dramsts;
17129 volatile ALT_MPFE_IOHMC_REG_DBGDONE_t reg_dbgdone;
17130 volatile ALT_MPFE_IOHMC_REG_DBGSIGNALS_t reg_dbgsignals;
17131 volatile ALT_MPFE_IOHMC_REG_DBGRESET_t reg_dbgreset;
17132 volatile ALT_MPFE_IOHMC_REG_DBGMATCH_t reg_dbgmatch;
17133 volatile ALT_MPFE_IOHMC_REG_COUNTER0MASK_t reg_counter0mask;
17134 volatile ALT_MPFE_IOHMC_REG_COUNTER1MASK_t reg_counter1mask;
17135 volatile ALT_MPFE_IOHMC_REG_COUNTER0MATCH_t reg_counter0match;
17136 volatile ALT_MPFE_IOHMC_REG_COUNTER1MATCH_t reg_counter1match;
17137 volatile ALT_MPFE_IOHMC_REG_NIOSRESERVE0_t reg_niosreserve0;
17138 volatile ALT_MPFE_IOHMC_REG_NIOSRESERVE1_t reg_niosreserve1;
17139 volatile ALT_MPFE_IOHMC_REG_NIOSRESERVE2_t reg_niosreserve2;
17140 volatile ALT_MPFE_IOHMC_REG_SBCFG8_t reg_sbcfg8;
17141 volatile ALT_MPFE_IOHMC_REG_SBCFG9_t reg_sbcfg9;
17142 volatile ALT_MPFE_IOHMC_REG_3DS0_t reg_3ds0;
17143 volatile ALT_MPFE_IOHMC_REG_3DS1_t reg_3ds1;
17144 volatile ALT_MPFE_IOHMC_REG_3DS2_t reg_3ds2;
17145 volatile ALT_MPFE_IOHMC_REG_PIPELINE0_t reg_pipeline0;
17146 volatile uint32_t _pad_0x134_0x137;
17147 volatile ALT_MPFE_IOHMC_REG_MEMCLOCKGATING0_t reg_memclockgating0;
17148 volatile ALT_MPFE_IOHMC_REG_SIDEBAND16_t reg_sideband16;
17149 volatile uint32_t _pad_0x140_0x190[20];
17153 typedef struct ALT_MPFE_IOHMC_s ALT_MPFE_IOHMC_t;
17155 struct ALT_MPFE_IOHMC_raw_s
17157 volatile uint32_t reg_dbgcfg0;
17158 volatile uint32_t reg_dbgcfg1;
17159 volatile uint32_t reg_dbgcfg2;
17160 volatile uint32_t reg_dbgcfg3;
17161 volatile uint32_t reg_dbgcfg4;
17162 volatile uint32_t reg_dbgcfg5;
17163 volatile uint32_t reg_dbgcfg6;
17164 volatile uint32_t reg_reserve0;
17165 volatile uint32_t reg_reserve1;
17166 volatile uint32_t reg_reserve2;
17167 volatile uint32_t reg_ctrlcfg0;
17168 volatile uint32_t reg_ctrlcfg1;
17169 volatile uint32_t reg_ctrlcfg2;
17170 volatile uint32_t reg_ctrlcfg3;
17171 volatile uint32_t reg_ctrlcfg4;
17172 volatile uint32_t reg_ctrlcfg5;
17173 volatile uint32_t reg_ctrlcfg6;
17174 volatile uint32_t reg_ctrlcfg7;
17175 volatile uint32_t reg_ctrlcfg8;
17176 volatile uint32_t reg_ctrlcfg9;
17177 volatile uint32_t reg_dramtiming0;
17178 volatile uint32_t reg_dramodt0;
17179 volatile uint32_t reg_dramodt1;
17180 volatile uint32_t reg_sbcfg0;
17181 volatile uint32_t reg_sbcfg1;
17182 volatile uint32_t reg_sbcfg2;
17183 volatile uint32_t reg_sbcfg3;
17184 volatile uint32_t reg_sbcfg4;
17185 volatile uint32_t reg_sbcfg5;
17186 volatile uint32_t reg_sbcfg6;
17187 volatile uint32_t reg_sbcfg7;
17188 volatile uint32_t reg_caltiming0;
17189 volatile uint32_t reg_caltiming1;
17190 volatile uint32_t reg_caltiming2;
17191 volatile uint32_t reg_caltiming3;
17192 volatile uint32_t reg_caltiming4;
17193 volatile uint32_t reg_caltiming5;
17194 volatile uint32_t reg_caltiming6;
17195 volatile uint32_t reg_caltiming7;
17196 volatile uint32_t reg_caltiming8;
17197 volatile uint32_t reg_caltiming9;
17198 volatile uint32_t reg_caltiming10;
17199 volatile uint32_t reg_dramaddrw;
17200 volatile uint32_t reg_sideband0;
17201 volatile uint32_t reg_sideband1;
17202 volatile uint32_t reg_sideband2;
17203 volatile uint32_t reg_sideband3;
17204 volatile uint32_t reg_sideband4;
17205 volatile uint32_t reg_sideband5;
17206 volatile uint32_t reg_sideband6;
17207 volatile uint32_t reg_sideband7;
17208 volatile uint32_t reg_sideband8;
17209 volatile uint32_t reg_sideband9;
17210 volatile uint32_t reg_sideband10;
17211 volatile uint32_t reg_sideband11;
17212 volatile uint32_t reg_sideband12;
17213 volatile uint32_t reg_sideband13;
17214 volatile uint32_t reg_sideband14;
17215 volatile uint32_t reg_sideband15;
17216 volatile uint32_t reg_dramsts;
17217 volatile uint32_t reg_dbgdone;
17218 volatile uint32_t reg_dbgsignals;
17219 volatile uint32_t reg_dbgreset;
17220 volatile uint32_t reg_dbgmatch;
17221 volatile uint32_t reg_counter0mask;
17222 volatile uint32_t reg_counter1mask;
17223 volatile uint32_t reg_counter0match;
17224 volatile uint32_t reg_counter1match;
17225 volatile uint32_t reg_niosreserve0;
17226 volatile uint32_t reg_niosreserve1;
17227 volatile uint32_t reg_niosreserve2;
17228 volatile uint32_t reg_sbcfg8;
17229 volatile uint32_t reg_sbcfg9;
17230 volatile uint32_t reg_3ds0;
17231 volatile uint32_t reg_3ds1;
17232 volatile uint32_t reg_3ds2;
17233 volatile uint32_t reg_pipeline0;
17234 volatile uint32_t _pad_0x134_0x137;
17235 volatile uint32_t reg_memclockgating0;
17236 volatile uint32_t reg_sideband16;
17237 volatile uint32_t _pad_0x140_0x190[20];
17241 typedef struct ALT_MPFE_IOHMC_raw_s ALT_MPFE_IOHMC_raw_t;
17272 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_LSB 0
17274 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_MSB 15
17276 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_WIDTH 16
17278 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
17280 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
17282 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_RESET 0x0
17284 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
17286 #define ALT_MPFE_HMC_ADP_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
17288 #ifndef __ASSEMBLY__
17300 struct ALT_MPFE_HMC_ADP_IP_REV_ID_s
17302 volatile uint32_t SIREV : 16;
17307 typedef struct ALT_MPFE_HMC_ADP_IP_REV_ID_s ALT_MPFE_HMC_ADP_IP_REV_ID_t;
17311 #define ALT_MPFE_HMC_ADP_IP_REV_ID_RESET 0x00000000
17313 #define ALT_MPFE_HMC_ADP_IP_REV_ID_OFST 0x0
17356 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_E_X16 0x0
17361 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_E_X32 0x1
17366 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_E_X64 0x2
17369 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_LSB 0
17371 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSB 1
17373 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_WIDTH 2
17375 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_SET_MSK 0x00000003
17377 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_CLR_MSK 0xfffffffc
17379 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_RESET 0x0
17381 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_GET(value) (((value) & 0x00000003) >> 0)
17383 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_SET(value) (((value) << 0) & 0x00000003)
17385 #ifndef __ASSEMBLY__
17397 struct ALT_MPFE_HMC_ADP_DDRIOCTRL_s
17399 volatile uint32_t IO_SIZE : 2;
17404 typedef struct ALT_MPFE_HMC_ADP_DDRIOCTRL_s ALT_MPFE_HMC_ADP_DDRIOCTRL_t;
17408 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_RESET 0x00000000
17410 #define ALT_MPFE_HMC_ADP_DDRIOCTRL_OFST 0x8
17441 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_LSB 0
17443 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_MSB 0
17445 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_WIDTH 1
17447 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_SET_MSK 0x00000001
17449 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_CLR_MSK 0xfffffffe
17451 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_RESET 0x0
17453 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_GET(value) (((value) & 0x00000001) >> 0)
17455 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_CAL_SET(value) (((value) << 0) & 0x00000001)
17472 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_LSB 1
17474 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_MSB 1
17476 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_WIDTH 1
17478 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_SET_MSK 0x00000002
17480 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_CLR_MSK 0xfffffffd
17482 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_RESET 0x0
17484 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_GET(value) (((value) & 0x00000002) >> 1)
17486 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_FAIL_SET(value) (((value) << 1) & 0x00000002)
17488 #ifndef __ASSEMBLY__
17500 struct ALT_MPFE_HMC_ADP_DDRCALSTAT_s
17502 volatile uint32_t CAL : 1;
17503 volatile uint32_t FAIL : 1;
17508 typedef struct ALT_MPFE_HMC_ADP_DDRCALSTAT_s ALT_MPFE_HMC_ADP_DDRCALSTAT_t;
17512 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_RESET 0x00000000
17514 #define ALT_MPFE_HMC_ADP_DDRCALSTAT_OFST 0xc
17537 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_LSB 0
17539 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_MSB 31
17541 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_WIDTH 32
17543 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_SET_MSK 0xffffffff
17545 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_CLR_MSK 0x00000000
17547 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_RESET 0x0
17549 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_GET(value) (((value) & 0xffffffff) >> 0)
17551 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_MPR0_SET(value) (((value) << 0) & 0xffffffff)
17553 #ifndef __ASSEMBLY__
17565 struct ALT_MPFE_HMC_ADP_MPR_0BEAT1_s
17567 volatile uint32_t MPR0 : 32;
17571 typedef struct ALT_MPFE_HMC_ADP_MPR_0BEAT1_s ALT_MPFE_HMC_ADP_MPR_0BEAT1_t;
17575 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_RESET 0x00000000
17577 #define ALT_MPFE_HMC_ADP_MPR_0BEAT1_OFST 0x10
17600 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_LSB 0
17602 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_MSB 31
17604 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_WIDTH 32
17606 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_SET_MSK 0xffffffff
17608 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_CLR_MSK 0x00000000
17610 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_RESET 0x0
17612 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_GET(value) (((value) & 0xffffffff) >> 0)
17614 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_MPR32_SET(value) (((value) << 0) & 0xffffffff)
17616 #ifndef __ASSEMBLY__
17628 struct ALT_MPFE_HMC_ADP_MPR_1BEAT1_s
17630 volatile uint32_t MPR32 : 32;
17634 typedef struct ALT_MPFE_HMC_ADP_MPR_1BEAT1_s ALT_MPFE_HMC_ADP_MPR_1BEAT1_t;
17638 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_RESET 0x00000000
17640 #define ALT_MPFE_HMC_ADP_MPR_1BEAT1_OFST 0x14
17663 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_LSB 0
17665 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_MSB 31
17667 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_WIDTH 32
17669 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_SET_MSK 0xffffffff
17671 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_CLR_MSK 0x00000000
17673 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_RESET 0x0
17675 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_GET(value) (((value) & 0xffffffff) >> 0)
17677 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_MPR64_SET(value) (((value) << 0) & 0xffffffff)
17679 #ifndef __ASSEMBLY__
17691 struct ALT_MPFE_HMC_ADP_MPR_2BEAT1_s
17693 volatile uint32_t MPR64 : 32;
17697 typedef struct ALT_MPFE_HMC_ADP_MPR_2BEAT1_s ALT_MPFE_HMC_ADP_MPR_2BEAT1_t;
17701 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_RESET 0x00000000
17703 #define ALT_MPFE_HMC_ADP_MPR_2BEAT1_OFST 0x18
17726 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_LSB 0
17728 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_MSB 31
17730 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_WIDTH 32
17732 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_SET_MSK 0xffffffff
17734 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_CLR_MSK 0x00000000
17736 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_RESET 0x0
17738 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_GET(value) (((value) & 0xffffffff) >> 0)
17740 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_MPR96_SET(value) (((value) << 0) & 0xffffffff)
17742 #ifndef __ASSEMBLY__
17754 struct ALT_MPFE_HMC_ADP_MPR_3BEAT1_s
17756 volatile uint32_t MPR96 : 32;
17760 typedef struct ALT_MPFE_HMC_ADP_MPR_3BEAT1_s ALT_MPFE_HMC_ADP_MPR_3BEAT1_t;
17764 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_RESET 0x00000000
17766 #define ALT_MPFE_HMC_ADP_MPR_3BEAT1_OFST 0x1c
17789 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_LSB 0
17791 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_MSB 31
17793 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_WIDTH 32
17795 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_SET_MSK 0xffffffff
17797 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_CLR_MSK 0x00000000
17799 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_RESET 0x0
17801 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_GET(value) (((value) & 0xffffffff) >> 0)
17803 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_MPR128_SET(value) (((value) << 0) & 0xffffffff)
17805 #ifndef __ASSEMBLY__
17817 struct ALT_MPFE_HMC_ADP_MPR_4BEAT1_s
17819 volatile uint32_t MPR128 : 32;
17823 typedef struct ALT_MPFE_HMC_ADP_MPR_4BEAT1_s ALT_MPFE_HMC_ADP_MPR_4BEAT1_t;
17827 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_RESET 0x00000000
17829 #define ALT_MPFE_HMC_ADP_MPR_4BEAT1_OFST 0x20
17852 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_LSB 0
17854 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_MSB 31
17856 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_WIDTH 32
17858 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_SET_MSK 0xffffffff
17860 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_CLR_MSK 0x00000000
17862 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_RESET 0x0
17864 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_GET(value) (((value) & 0xffffffff) >> 0)
17866 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_MPR160_SET(value) (((value) << 0) & 0xffffffff)
17868 #ifndef __ASSEMBLY__
17880 struct ALT_MPFE_HMC_ADP_MPR_5BEAT1_s
17882 volatile uint32_t MPR160 : 32;
17886 typedef struct ALT_MPFE_HMC_ADP_MPR_5BEAT1_s ALT_MPFE_HMC_ADP_MPR_5BEAT1_t;
17890 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_RESET 0x00000000
17892 #define ALT_MPFE_HMC_ADP_MPR_5BEAT1_OFST 0x24
17915 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_LSB 0
17917 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_MSB 31
17919 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_WIDTH 32
17921 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_SET_MSK 0xffffffff
17923 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_CLR_MSK 0x00000000
17925 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_RESET 0x0
17927 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_GET(value) (((value) & 0xffffffff) >> 0)
17929 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_MPR192_SET(value) (((value) << 0) & 0xffffffff)
17931 #ifndef __ASSEMBLY__
17943 struct ALT_MPFE_HMC_ADP_MPR_6BEAT1_s
17945 volatile uint32_t MPR192 : 32;
17949 typedef struct ALT_MPFE_HMC_ADP_MPR_6BEAT1_s ALT_MPFE_HMC_ADP_MPR_6BEAT1_t;
17953 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_RESET 0x00000000
17955 #define ALT_MPFE_HMC_ADP_MPR_6BEAT1_OFST 0x28
17978 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_LSB 0
17980 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_MSB 31
17982 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_WIDTH 32
17984 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_SET_MSK 0xffffffff
17986 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_CLR_MSK 0x00000000
17988 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_RESET 0x0
17990 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_GET(value) (((value) & 0xffffffff) >> 0)
17992 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_MPR224_SET(value) (((value) << 0) & 0xffffffff)
17994 #ifndef __ASSEMBLY__
18006 struct ALT_MPFE_HMC_ADP_MPR_7BEAT1_s
18008 volatile uint32_t MPR224 : 32;
18012 typedef struct ALT_MPFE_HMC_ADP_MPR_7BEAT1_s ALT_MPFE_HMC_ADP_MPR_7BEAT1_t;
18016 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_RESET 0x00000000
18018 #define ALT_MPFE_HMC_ADP_MPR_7BEAT1_OFST 0x2c
18041 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_LSB 0
18043 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_MSB 31
18045 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_WIDTH 32
18047 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_SET_MSK 0xffffffff
18049 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_CLR_MSK 0x00000000
18051 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_RESET 0x0
18053 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_GET(value) (((value) & 0xffffffff) >> 0)
18055 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_MPR256_SET(value) (((value) << 0) & 0xffffffff)
18057 #ifndef __ASSEMBLY__
18069 struct ALT_MPFE_HMC_ADP_MPR_8BEAT1_s
18071 volatile uint32_t MPR256 : 32;
18075 typedef struct ALT_MPFE_HMC_ADP_MPR_8BEAT1_s ALT_MPFE_HMC_ADP_MPR_8BEAT1_t;
18079 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_RESET 0x00000000
18081 #define ALT_MPFE_HMC_ADP_MPR_8BEAT1_OFST 0x30
18104 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_LSB 0
18106 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_MSB 31
18108 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_WIDTH 32
18110 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_SET_MSK 0xffffffff
18112 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_CLR_MSK 0x00000000
18114 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_RESET 0x0
18116 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_GET(value) (((value) & 0xffffffff) >> 0)
18118 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_MPR0_SET(value) (((value) << 0) & 0xffffffff)
18120 #ifndef __ASSEMBLY__
18132 struct ALT_MPFE_HMC_ADP_MPR_0BEAT2_s
18134 volatile uint32_t MPR0 : 32;
18138 typedef struct ALT_MPFE_HMC_ADP_MPR_0BEAT2_s ALT_MPFE_HMC_ADP_MPR_0BEAT2_t;
18142 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_RESET 0x00000000
18144 #define ALT_MPFE_HMC_ADP_MPR_0BEAT2_OFST 0x34
18167 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_LSB 0
18169 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_MSB 31
18171 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_WIDTH 32
18173 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_SET_MSK 0xffffffff
18175 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_CLR_MSK 0x00000000
18177 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_RESET 0x0
18179 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_GET(value) (((value) & 0xffffffff) >> 0)
18181 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_MPR32_SET(value) (((value) << 0) & 0xffffffff)
18183 #ifndef __ASSEMBLY__
18195 struct ALT_MPFE_HMC_ADP_MPR_1BEAT2_s
18197 volatile uint32_t MPR32 : 32;
18201 typedef struct ALT_MPFE_HMC_ADP_MPR_1BEAT2_s ALT_MPFE_HMC_ADP_MPR_1BEAT2_t;
18205 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_RESET 0x00000000
18207 #define ALT_MPFE_HMC_ADP_MPR_1BEAT2_OFST 0x38
18230 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_LSB 0
18232 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_MSB 31
18234 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_WIDTH 32
18236 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_SET_MSK 0xffffffff
18238 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_CLR_MSK 0x00000000
18240 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_RESET 0x0
18242 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_GET(value) (((value) & 0xffffffff) >> 0)
18244 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_MPR64_SET(value) (((value) << 0) & 0xffffffff)
18246 #ifndef __ASSEMBLY__
18258 struct ALT_MPFE_HMC_ADP_MPR_2BEAT2_s
18260 volatile uint32_t MPR64 : 32;
18264 typedef struct ALT_MPFE_HMC_ADP_MPR_2BEAT2_s ALT_MPFE_HMC_ADP_MPR_2BEAT2_t;
18268 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_RESET 0x00000000
18270 #define ALT_MPFE_HMC_ADP_MPR_2BEAT2_OFST 0x3c
18293 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_LSB 0
18295 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_MSB 31
18297 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_WIDTH 32
18299 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_SET_MSK 0xffffffff
18301 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_CLR_MSK 0x00000000
18303 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_RESET 0x0
18305 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_GET(value) (((value) & 0xffffffff) >> 0)
18307 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_MPR96_SET(value) (((value) << 0) & 0xffffffff)
18309 #ifndef __ASSEMBLY__
18321 struct ALT_MPFE_HMC_ADP_MPR_3BEAT2_s
18323 volatile uint32_t MPR96 : 32;
18327 typedef struct ALT_MPFE_HMC_ADP_MPR_3BEAT2_s ALT_MPFE_HMC_ADP_MPR_3BEAT2_t;
18331 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_RESET 0x00000000
18333 #define ALT_MPFE_HMC_ADP_MPR_3BEAT2_OFST 0x40
18356 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_LSB 0
18358 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_MSB 31
18360 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_WIDTH 32
18362 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_SET_MSK 0xffffffff
18364 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_CLR_MSK 0x00000000
18366 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_RESET 0x0
18368 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_GET(value) (((value) & 0xffffffff) >> 0)
18370 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_MPR128_SET(value) (((value) << 0) & 0xffffffff)
18372 #ifndef __ASSEMBLY__
18384 struct ALT_MPFE_HMC_ADP_MPR_4BEAT2_s
18386 volatile uint32_t MPR128 : 32;
18390 typedef struct ALT_MPFE_HMC_ADP_MPR_4BEAT2_s ALT_MPFE_HMC_ADP_MPR_4BEAT2_t;
18394 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_RESET 0x00000000
18396 #define ALT_MPFE_HMC_ADP_MPR_4BEAT2_OFST 0x44
18419 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_LSB 0
18421 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_MSB 31
18423 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_WIDTH 32
18425 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_SET_MSK 0xffffffff
18427 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_CLR_MSK 0x00000000
18429 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_RESET 0x0
18431 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_GET(value) (((value) & 0xffffffff) >> 0)
18433 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_MPR160_SET(value) (((value) << 0) & 0xffffffff)
18435 #ifndef __ASSEMBLY__
18447 struct ALT_MPFE_HMC_ADP_MPR_5BEAT2_s
18449 volatile uint32_t MPR160 : 32;
18453 typedef struct ALT_MPFE_HMC_ADP_MPR_5BEAT2_s ALT_MPFE_HMC_ADP_MPR_5BEAT2_t;
18457 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_RESET 0x00000000
18459 #define ALT_MPFE_HMC_ADP_MPR_5BEAT2_OFST 0x48
18482 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_LSB 0
18484 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_MSB 31
18486 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_WIDTH 32
18488 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_SET_MSK 0xffffffff
18490 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_CLR_MSK 0x00000000
18492 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_RESET 0x0
18494 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_GET(value) (((value) & 0xffffffff) >> 0)
18496 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_MPR192_SET(value) (((value) << 0) & 0xffffffff)
18498 #ifndef __ASSEMBLY__
18510 struct ALT_MPFE_HMC_ADP_MPR_6BEAT2_s
18512 volatile uint32_t MPR192 : 32;
18516 typedef struct ALT_MPFE_HMC_ADP_MPR_6BEAT2_s ALT_MPFE_HMC_ADP_MPR_6BEAT2_t;
18520 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_RESET 0x00000000
18522 #define ALT_MPFE_HMC_ADP_MPR_6BEAT2_OFST 0x4c
18545 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_LSB 0
18547 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_MSB 31
18549 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_WIDTH 32
18551 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_SET_MSK 0xffffffff
18553 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_CLR_MSK 0x00000000
18555 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_RESET 0x0
18557 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_GET(value) (((value) & 0xffffffff) >> 0)
18559 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_MPR224_SET(value) (((value) << 0) & 0xffffffff)
18561 #ifndef __ASSEMBLY__
18573 struct ALT_MPFE_HMC_ADP_MPR_7BEAT2_s
18575 volatile uint32_t MPR224 : 32;
18579 typedef struct ALT_MPFE_HMC_ADP_MPR_7BEAT2_s ALT_MPFE_HMC_ADP_MPR_7BEAT2_t;
18583 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_RESET 0x00000000
18585 #define ALT_MPFE_HMC_ADP_MPR_7BEAT2_OFST 0x50
18608 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_LSB 0
18610 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_MSB 31
18612 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_WIDTH 32
18614 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_SET_MSK 0xffffffff
18616 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_CLR_MSK 0x00000000
18618 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_RESET 0x0
18620 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_GET(value) (((value) & 0xffffffff) >> 0)
18622 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_MPR256_SET(value) (((value) << 0) & 0xffffffff)
18624 #ifndef __ASSEMBLY__
18636 struct ALT_MPFE_HMC_ADP_MPR_8BEAT2_s
18638 volatile uint32_t MPR256 : 32;
18642 typedef struct ALT_MPFE_HMC_ADP_MPR_8BEAT2_s ALT_MPFE_HMC_ADP_MPR_8BEAT2_t;
18646 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_RESET 0x00000000
18648 #define ALT_MPFE_HMC_ADP_MPR_8BEAT2_OFST 0x54
18686 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_E_DISABLE 0x0
18691 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_E_ENABLE 0x1
18694 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_LSB 0
18696 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_MSB 0
18698 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_WIDTH 1
18700 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_SET_MSK 0x00000001
18702 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_CLR_MSK 0xfffffffe
18704 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_RESET 0x0
18706 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_GET(value) (((value) & 0x00000001) >> 0)
18708 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_CTRL_SET(value) (((value) << 0) & 0x00000001)
18710 #ifndef __ASSEMBLY__
18722 struct ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_s
18724 volatile uint32_t CTRL : 1;
18729 typedef struct ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_s ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_t;
18733 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_RESET 0x00000000
18735 #define ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_OFST 0x60
18766 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_LSB 0
18768 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_MSB 4
18770 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_WIDTH 5
18772 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_SET_MSK 0x0000001f
18774 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_CLR_MSK 0xffffffe0
18776 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_RESET 0x0
18778 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_GET(value) (((value) & 0x0000001f) >> 0)
18780 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_COL_ADDR_WIDTH_SET(value) (((value) << 0) & 0x0000001f)
18793 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_LSB 5
18795 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_MSB 9
18797 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_WIDTH 5
18799 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_SET_MSK 0x000003e0
18801 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_CLR_MSK 0xfffffc1f
18803 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_RESET 0x0
18805 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_GET(value) (((value) & 0x000003e0) >> 5)
18807 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_ROW_ADDR_WIDTH_SET(value) (((value) << 5) & 0x000003e0)
18820 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_LSB 10
18822 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_MSB 13
18824 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_WIDTH 4
18826 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_SET_MSK 0x00003c00
18828 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_CLR_MSK 0xffffc3ff
18830 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_RESET 0x0
18832 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_GET(value) (((value) & 0x00003c00) >> 10)
18834 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_ADDR_WIDTH_SET(value) (((value) << 10) & 0x00003c00)
18848 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_LSB 14
18850 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_MSB 15
18852 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_WIDTH 2
18854 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_SET_MSK 0x0000c000
18856 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_CLR_MSK 0xffff3fff
18858 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_RESET 0x0
18860 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_GET(value) (((value) & 0x0000c000) >> 14)
18862 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_BANK_GROUP_ADDR_WIDTH_SET(value) (((value) << 14) & 0x0000c000)
18876 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_LSB 16
18878 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_MSB 18
18880 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_WIDTH 3
18882 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_SET_MSK 0x00070000
18884 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_CLR_MSK 0xfff8ffff
18886 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_RESET 0x0
18888 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_GET(value) (((value) & 0x00070000) >> 16)
18890 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_CFG_CS_ADDR_WIDTH_SET(value) (((value) << 16) & 0x00070000)
18892 #ifndef __ASSEMBLY__
18904 struct ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_s
18906 volatile uint32_t CFG_COL_ADDR_WIDTH : 5;
18907 volatile uint32_t CFG_ROW_ADDR_WIDTH : 5;
18908 volatile uint32_t CFG_BANK_ADDR_WIDTH : 4;
18909 volatile uint32_t CFG_BANK_GROUP_ADDR_WIDTH : 2;
18910 volatile uint32_t CFG_CS_ADDR_WIDTH : 3;
18915 typedef struct ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_s ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_t;
18919 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_RESET 0x00000000
18921 #define ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_OFST 0xe0
18966 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_E_DISABLE 0x0
18971 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_E_ENABLE 0x1
18974 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_LSB 0
18976 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_MSB 0
18978 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_WIDTH 1
18980 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK 0x00000001
18982 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_CLR_MSK 0xfffffffe
18984 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_RESET 0x0
18986 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
18988 #define ALT_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
19013 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_E_STAY 0x0
19018 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_E_RESET 0x1
19021 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_LSB 8
19023 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_MSB 8
19025 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_WIDTH 1
19027 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK 0x00000100
19029 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_CLR_MSK 0xfffffeff
19031 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_RESET 0x0
19033 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_GET(value) (((value) & 0x00000100) >> 8)
19035 #define ALT_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET(value) (((value) << 8) & 0x00000100)
19060 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_E_STAY 0x0
19065 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_E_RESET 0x1
19068 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_LSB 16
19070 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_MSB 16
19072 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_WIDTH 1
19074 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK 0x00010000
19076 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_CLR_MSK 0xfffeffff
19078 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_RESET 0x0
19080 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_GET(value) (((value) & 0x00010000) >> 16)
19082 #define ALT_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET(value) (((value) << 16) & 0x00010000)
19084 #ifndef __ASSEMBLY__
19096 struct ALT_MPFE_HMC_ADP_ECCCTRL1_s
19098 volatile uint32_t ECC_EN : 1;
19100 volatile uint32_t CNT_RST : 1;
19102 volatile uint32_t AUTOWB_CNT_RST : 1;
19107 typedef struct ALT_MPFE_HMC_ADP_ECCCTRL1_s ALT_MPFE_HMC_ADP_ECCCTRL1_t;
19111 #define ALT_MPFE_HMC_ADP_ECCCTRL1_RESET 0x00000000
19113 #define ALT_MPFE_HMC_ADP_ECCCTRL1_OFST 0x100
19161 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_E_DISABLE 0x0
19166 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_E_ENABLE 0x1
19169 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_LSB 0
19171 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_MSB 0
19173 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_WIDTH 1
19175 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK 0x00000001
19177 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_CLR_MSK 0xfffffffe
19179 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_RESET 0x0
19181 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_GET(value) (((value) & 0x00000001) >> 0)
19183 #define ALT_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET(value) (((value) << 0) & 0x00000001)
19212 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_E_DISABLE 0x0
19217 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_E_ENABLE 0x1
19220 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_LSB 8
19222 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_MSB 8
19224 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_WIDTH 1
19226 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK 0x00000100
19228 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_CLR_MSK 0xfffffeff
19230 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_RESET 0x0
19232 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_GET(value) (((value) & 0x00000100) >> 8)
19234 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET(value) (((value) << 8) & 0x00000100)
19260 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_E_DISABLE 0x0
19265 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_E_ENABLE 0x1
19268 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_LSB 16
19270 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_MSB 16
19272 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_WIDTH 1
19274 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000
19276 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_CLR_MSK 0xfffeffff
19278 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_RESET 0x0
19280 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_GET(value) (((value) & 0x00010000) >> 16)
19282 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET(value) (((value) << 16) & 0x00010000)
19284 #ifndef __ASSEMBLY__
19296 struct ALT_MPFE_HMC_ADP_ECCCTRL2_s
19298 volatile uint32_t AUTOWB_EN : 1;
19300 volatile uint32_t RMW_EN : 1;
19302 volatile uint32_t OVRW_RB_ECC_EN : 1;
19307 typedef struct ALT_MPFE_HMC_ADP_ECCCTRL2_s ALT_MPFE_HMC_ADP_ECCCTRL2_t;
19311 #define ALT_MPFE_HMC_ADP_ECCCTRL2_RESET 0x00000000
19313 #define ALT_MPFE_HMC_ADP_ECCCTRL2_OFST 0x104
19355 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_E_DISABLE 0x0
19360 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_E_ENABLE 0x1
19363 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_LSB 0
19365 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_MSB 0
19367 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_WIDTH 1
19369 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
19371 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
19373 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_RESET 0x0
19375 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
19377 #define ALT_MPFE_HMC_ADP_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
19405 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_E_DISABLE 0x0
19410 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_E_ENABLE 0x1
19413 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_LSB 1
19415 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_MSB 1
19417 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_WIDTH 1
19419 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_SET_MSK 0x00000002
19421 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_CLR_MSK 0xfffffffd
19423 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_RESET 0x0
19425 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_GET(value) (((value) & 0x00000002) >> 1)
19427 #define ALT_MPFE_HMC_ADP_ERRINTEN_DERRINTEN_SET(value) (((value) << 1) & 0x00000002)
19457 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_E_DISABLE 0x0
19462 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_E_ENABLE 0x1
19465 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_LSB 2
19467 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_MSB 2
19469 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_WIDTH 1
19471 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_SET_MSK 0x00000004
19473 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_CLR_MSK 0xfffffffb
19475 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_RESET 0x0
19477 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_GET(value) (((value) & 0x00000004) >> 2)
19479 #define ALT_MPFE_HMC_ADP_ERRINTEN_HMI_INTREN_SET(value) (((value) << 2) & 0x00000004)
19504 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_E_DISABLE 0x0
19509 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_E_ENABLE 0x1
19512 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_LSB 3
19514 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_MSB 3
19516 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_WIDTH 1
19518 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_SET_MSK 0x00000008
19520 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_CLR_MSK 0xfffffff7
19522 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_RESET 0x0
19524 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_GET(value) (((value) & 0x00000008) >> 3)
19526 #define ALT_MPFE_HMC_ADP_ERRINTEN_SEQ2CORE_INTREN_SET(value) (((value) << 3) & 0x00000008)
19528 #ifndef __ASSEMBLY__
19540 struct ALT_MPFE_HMC_ADP_ERRINTEN_s
19542 volatile uint32_t SERRINTEN : 1;
19543 volatile uint32_t DERRINTEN : 1;
19544 volatile uint32_t HMI_INTREN : 1;
19545 volatile uint32_t SEQ2CORE_INTREN : 1;
19550 typedef struct ALT_MPFE_HMC_ADP_ERRINTEN_s ALT_MPFE_HMC_ADP_ERRINTEN_t;
19554 #define ALT_MPFE_HMC_ADP_ERRINTEN_RESET 0x00000000
19556 #define ALT_MPFE_HMC_ADP_ERRINTEN_OFST 0x110
19601 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_E_STAY 0x0
19606 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_E_SET 0x1
19609 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_LSB 0
19611 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_MSB 0
19613 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_WIDTH 1
19615 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_SET_MSK 0x00000001
19617 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
19619 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_RESET 0x0
19621 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
19623 #define ALT_MPFE_HMC_ADP_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
19652 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_E_STAY 0x0
19657 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_E_SET 0x1
19660 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_LSB 1
19662 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_MSB 1
19664 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_WIDTH 1
19666 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_SET_MSK 0x00000002
19668 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_CLR_MSK 0xfffffffd
19670 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_RESET 0x0
19672 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_GET(value) (((value) & 0x00000002) >> 1)
19674 #define ALT_MPFE_HMC_ADP_ERRINTENS_DERRINTS_SET(value) (((value) << 1) & 0x00000002)
19701 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_E_STAY 0x0
19706 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_E_SET 0x1
19709 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_LSB 2
19711 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_MSB 2
19713 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_WIDTH 1
19715 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_SET_MSK 0x00000004
19717 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_CLR_MSK 0xfffffffb
19719 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_RESET 0x0
19721 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_GET(value) (((value) & 0x00000004) >> 2)
19723 #define ALT_MPFE_HMC_ADP_ERRINTENS_HMI_INTRS_SET(value) (((value) << 2) & 0x00000004)
19750 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_E_STAY 0x0
19755 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_E_SET 0x1
19758 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_LSB 3
19760 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_MSB 3
19762 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_WIDTH 1
19764 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_SET_MSK 0x00000008
19766 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_CLR_MSK 0xfffffff7
19768 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_RESET 0x0
19770 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_GET(value) (((value) & 0x00000008) >> 3)
19772 #define ALT_MPFE_HMC_ADP_ERRINTENS_SEQ2CORE_INTRS_SET(value) (((value) << 3) & 0x00000008)
19774 #ifndef __ASSEMBLY__
19786 struct ALT_MPFE_HMC_ADP_ERRINTENS_s
19788 volatile uint32_t SERRINTS : 1;
19789 volatile uint32_t DERRINTS : 1;
19790 volatile uint32_t HMI_INTRS : 1;
19791 volatile uint32_t SEQ2CORE_INTRS : 1;
19796 typedef struct ALT_MPFE_HMC_ADP_ERRINTENS_s ALT_MPFE_HMC_ADP_ERRINTENS_t;
19800 #define ALT_MPFE_HMC_ADP_ERRINTENS_RESET 0x00000000
19802 #define ALT_MPFE_HMC_ADP_ERRINTENS_OFST 0x114
19847 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_E_STAY 0x0
19852 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_E_RESET 0x1
19855 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_LSB 0
19857 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_MSB 0
19859 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_WIDTH 1
19861 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_SET_MSK 0x00000001
19863 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
19865 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_RESET 0x0
19867 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
19869 #define ALT_MPFE_HMC_ADP_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
19898 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_E_STAY 0x0
19903 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_E_RESET 0x1
19906 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_LSB 1
19908 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_MSB 1
19910 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_WIDTH 1
19912 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_SET_MSK 0x00000002
19914 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_CLR_MSK 0xfffffffd
19916 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_RESET 0x0
19918 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_GET(value) (((value) & 0x00000002) >> 1)
19920 #define ALT_MPFE_HMC_ADP_ERRINTENR_DERRINTR_SET(value) (((value) << 1) & 0x00000002)
19948 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_E_STAY 0x0
19953 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_E_RESET 0x1
19956 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_LSB 2
19958 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_MSB 2
19960 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_WIDTH 1
19962 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_SET_MSK 0x00000004
19964 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_CLR_MSK 0xfffffffb
19966 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_RESET 0x0
19968 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_GET(value) (((value) & 0x00000004) >> 2)
19970 #define ALT_MPFE_HMC_ADP_ERRINTENR_HMI_INTRR_SET(value) (((value) << 2) & 0x00000004)
19997 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_E_STAY 0x0
20002 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_E_RESET 0x1
20005 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_LSB 3
20007 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_MSB 3
20009 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_WIDTH 1
20011 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_SET_MSK 0x00000008
20013 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_CLR_MSK 0xfffffff7
20015 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_RESET 0x0
20017 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_GET(value) (((value) & 0x00000008) >> 3)
20019 #define ALT_MPFE_HMC_ADP_ERRINTENR_SEQ2CORE_INTRR_SET(value) (((value) << 3) & 0x00000008)
20021 #ifndef __ASSEMBLY__
20033 struct ALT_MPFE_HMC_ADP_ERRINTENR_s
20035 volatile uint32_t SERRINTR : 1;
20036 volatile uint32_t DERRINTR : 1;
20037 volatile uint32_t HMI_INTRR : 1;
20038 volatile uint32_t SEQ2CORE_INTRR : 1;
20043 typedef struct ALT_MPFE_HMC_ADP_ERRINTENR_s ALT_MPFE_HMC_ADP_ERRINTENR_t;
20047 #define ALT_MPFE_HMC_ADP_ERRINTENR_RESET 0x00000000
20049 #define ALT_MPFE_HMC_ADP_ERRINTENR_OFST 0x118
20093 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_E_DISABLE 0x0
20098 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_E_ENABLE 0x1
20101 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_LSB 0
20103 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_MSB 0
20105 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_WIDTH 1
20107 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_SET_MSK 0x00000001
20109 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_CLR_MSK 0xfffffffe
20111 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_RESET 0x0
20113 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_GET(value) (((value) & 0x00000001) >> 0)
20115 #define ALT_MPFE_HMC_ADP_INTMODE_INTMODE_SET(value) (((value) << 0) & 0x00000001)
20143 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_E_DISABLE 0x0
20148 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_E_ENABLE 0x1
20151 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_LSB 8
20153 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_MSB 8
20155 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_WIDTH 1
20157 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_SET_MSK 0x00000100
20159 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_CLR_MSK 0xfffffeff
20161 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_RESET 0x0
20163 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_GET(value) (((value) & 0x00000100) >> 8)
20165 #define ALT_MPFE_HMC_ADP_INTMODE_EXT_ADDRPARITY_EN_SET(value) (((value) << 8) & 0x00000100)
20193 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_E_DISABLE 0x0
20198 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_E_ENABLE 0x1
20201 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_LSB 16
20203 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_MSB 16
20205 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_WIDTH 1
20207 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_SET_MSK 0x00010000
20209 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_CLR_MSK 0xfffeffff
20211 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_RESET 0x0
20213 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
20215 #define ALT_MPFE_HMC_ADP_INTMODE_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
20243 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_E_DISABLE 0x0
20248 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_E_ENABLE 0x1
20251 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_LSB 24
20253 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_MSB 24
20255 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_WIDTH 1
20257 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_SET_MSK 0x01000000
20259 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_CLR_MSK 0xfeffffff
20261 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_RESET 0x0
20263 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_GET(value) (((value) & 0x01000000) >> 24)
20265 #define ALT_MPFE_HMC_ADP_INTMODE_AFICAL_EN_SET(value) (((value) << 24) & 0x01000000)
20267 #ifndef __ASSEMBLY__
20279 struct ALT_MPFE_HMC_ADP_INTMODE_s
20281 volatile uint32_t INTMODE : 1;
20283 volatile uint32_t EXT_ADDRPARITY_EN : 1;
20285 volatile uint32_t INTONCMP : 1;
20287 volatile uint32_t AFICAL_EN : 1;
20292 typedef struct ALT_MPFE_HMC_ADP_INTMODE_s ALT_MPFE_HMC_ADP_INTMODE_t;
20296 #define ALT_MPFE_HMC_ADP_INTMODE_RESET 0x00000000
20298 #define ALT_MPFE_HMC_ADP_INTMODE_OFST 0x11c
20336 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_LSB 0
20338 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_MSB 0
20340 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_WIDTH 1
20342 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_SET_MSK 0x00000001
20344 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
20346 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_RESET 0x0
20348 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
20350 #define ALT_MPFE_HMC_ADP_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
20368 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_LSB 1
20370 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_MSB 1
20372 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_WIDTH 1
20374 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_SET_MSK 0x00000002
20376 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_CLR_MSK 0xfffffffd
20378 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_RESET 0x0
20380 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000002) >> 1)
20382 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRPENA_SET(value) (((value) << 1) & 0x00000002)
20400 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_LSB 2
20402 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_MSB 2
20404 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_WIDTH 1
20406 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_SET_MSK 0x00000004
20408 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_CLR_MSK 0xfffffffb
20410 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_RESET 0x0
20412 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_GET(value) (((value) & 0x00000004) >> 2)
20414 #define ALT_MPFE_HMC_ADP_INTSTAT_HMI_PENA_SET(value) (((value) << 2) & 0x00000004)
20432 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_LSB 3
20434 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_MSB 3
20436 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_WIDTH 1
20438 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_SET_MSK 0x00000008
20440 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_CLR_MSK 0xfffffff7
20442 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_RESET 0x0
20444 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_GET(value) (((value) & 0x00000008) >> 3)
20446 #define ALT_MPFE_HMC_ADP_INTSTAT_SEQ2CORE_PENA_SET(value) (((value) << 3) & 0x00000008)
20469 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_LSB 16
20471 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_MSB 16
20473 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_WIDTH 1
20475 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_SET_MSK 0x00010000
20477 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_CLR_MSK 0xfffeffff
20479 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_RESET 0x0
20481 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_GET(value) (((value) & 0x00010000) >> 16)
20483 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRMTCFLG_SET(value) (((value) << 16) & 0x00010000)
20502 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_LSB 17
20504 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_MSB 17
20506 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_WIDTH 1
20508 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_SET_MSK 0x00020000
20510 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_CLR_MSK 0xfffdffff
20512 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_RESET 0x0
20514 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_GET(value) (((value) & 0x00020000) >> 17)
20516 #define ALT_MPFE_HMC_ADP_INTSTAT_ADDRPARFLG_SET(value) (((value) << 17) & 0x00020000)
20536 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_LSB 18
20538 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_MSB 18
20540 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_WIDTH 1
20542 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_SET_MSK 0x00040000
20544 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_CLR_MSK 0xfffbffff
20546 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_RESET 0x0
20548 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_GET(value) (((value) & 0x00040000) >> 18)
20550 #define ALT_MPFE_HMC_ADP_INTSTAT_DERRBUSFLG_SET(value) (((value) << 18) & 0x00040000)
20552 #ifndef __ASSEMBLY__
20564 struct ALT_MPFE_HMC_ADP_INTSTAT_s
20566 volatile uint32_t SERRPENA : 1;
20567 volatile uint32_t DERRPENA : 1;
20568 volatile uint32_t HMI_PENA : 1;
20569 volatile uint32_t SEQ2CORE_PENA : 1;
20571 volatile uint32_t ADDRMTCFLG : 1;
20572 volatile uint32_t ADDRPARFLG : 1;
20573 volatile uint32_t DERRBUSFLG : 1;
20578 typedef struct ALT_MPFE_HMC_ADP_INTSTAT_s ALT_MPFE_HMC_ADP_INTSTAT_t;
20582 #define ALT_MPFE_HMC_ADP_INTSTAT_RESET 0x00000000
20584 #define ALT_MPFE_HMC_ADP_INTSTAT_OFST 0x120
20630 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_E_STAY 0x0
20635 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_E_SET 0x1
20638 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_LSB 0
20640 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_MSB 0
20642 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_WIDTH 1
20644 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_SET_MSK 0x00000001
20646 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_CLR_MSK 0xfffffffe
20648 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_RESET 0x0
20650 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
20652 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
20682 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_E_STAY 0x0
20687 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_E_SET 0x1
20690 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_LSB 8
20692 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_MSB 8
20694 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_WIDTH 1
20696 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_SET_MSK 0x00000100
20698 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_CLR_MSK 0xfffffeff
20700 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_RESET 0x0
20702 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
20704 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
20735 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_E_STAY 0x0
20740 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_E_SET 0x1
20743 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_LSB 16
20745 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_MSB 16
20747 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_WIDTH 1
20749 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_SET_MSK 0x00010000
20751 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_CLR_MSK 0xfffeffff
20753 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_RESET 0x0
20755 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_GET(value) (((value) & 0x00010000) >> 16)
20757 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRMTC_SET(value) (((value) << 16) & 0x00010000)
20787 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_E_STAY 0x0
20792 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_E_SET 0x1
20795 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_LSB 24
20797 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_MSB 24
20799 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_WIDTH 1
20801 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_SET_MSK 0x01000000
20803 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_CLR_MSK 0xfeffffff
20805 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_RESET 0x0
20807 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_GET(value) (((value) & 0x01000000) >> 24)
20809 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_TADDRPAR_SET(value) (((value) << 24) & 0x01000000)
20811 #ifndef __ASSEMBLY__
20823 struct ALT_MPFE_HMC_ADP_DIAGINTTEST_s
20825 volatile uint32_t TSERRA : 1;
20827 volatile uint32_t TDERRA : 1;
20829 volatile uint32_t TADDRMTC : 1;
20831 volatile uint32_t TADDRPAR : 1;
20836 typedef struct ALT_MPFE_HMC_ADP_DIAGINTTEST_s ALT_MPFE_HMC_ADP_DIAGINTTEST_t;
20840 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_RESET 0x00000000
20842 #define ALT_MPFE_HMC_ADP_DIAGINTTEST_OFST 0x124
20881 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_LSB 0
20883 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_MSB 0
20885 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_WIDTH 1
20887 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_SET_MSK 0x00000001
20889 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
20891 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_RESET 0x0
20893 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
20895 #define ALT_MPFE_HMC_ADP_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
20922 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_LSB 8
20924 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_MSB 8
20926 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_WIDTH 1
20928 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_SET_MSK 0x00000100
20930 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_CLR_MSK 0xfffffeff
20932 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_RESET 0x0
20934 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_GET(value) (((value) & 0x00000100) >> 8)
20936 #define ALT_MPFE_HMC_ADP_MODSTAT_AUTOWB_DROP_FLG_SET(value) (((value) << 8) & 0x00000100)
20938 #ifndef __ASSEMBLY__
20950 struct ALT_MPFE_HMC_ADP_MODSTAT_s
20952 volatile uint32_t CMPFLGA : 1;
20954 volatile uint32_t AUTOWB_DROP_FLG : 1;
20959 typedef struct ALT_MPFE_HMC_ADP_MODSTAT_s ALT_MPFE_HMC_ADP_MODSTAT_t;
20963 #define ALT_MPFE_HMC_ADP_MODSTAT_RESET 0x00000000
20965 #define ALT_MPFE_HMC_ADP_MODSTAT_OFST 0x128
20994 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_LSB 0
20996 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_MSB 31
20998 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_WIDTH 32
21000 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_SET_MSK 0xffffffff
21002 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_CLR_MSK 0x00000000
21004 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_RESET 0x0
21006 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_GET(value) (((value) & 0xffffffff) >> 0)
21008 #define ALT_MPFE_HMC_ADP_DERRADDRA_DADDRESS_SET(value) (((value) << 0) & 0xffffffff)
21010 #ifndef __ASSEMBLY__
21022 struct ALT_MPFE_HMC_ADP_DERRADDRA_s
21024 volatile uint32_t DADDRESS : 32;
21028 typedef struct ALT_MPFE_HMC_ADP_DERRADDRA_s ALT_MPFE_HMC_ADP_DERRADDRA_t;
21032 #define ALT_MPFE_HMC_ADP_DERRADDRA_RESET 0x00000000
21034 #define ALT_MPFE_HMC_ADP_DERRADDRA_OFST 0x12c
21061 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_LSB 0
21063 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_MSB 31
21065 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_WIDTH 32
21067 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_SET_MSK 0xffffffff
21069 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_CLR_MSK 0x00000000
21071 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_RESET 0x0
21073 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_GET(value) (((value) & 0xffffffff) >> 0)
21075 #define ALT_MPFE_HMC_ADP_SERRADDRA_SADDRESS_SET(value) (((value) << 0) & 0xffffffff)
21077 #ifndef __ASSEMBLY__
21089 struct ALT_MPFE_HMC_ADP_SERRADDRA_s
21091 volatile uint32_t SADDRESS : 32;
21095 typedef struct ALT_MPFE_HMC_ADP_SERRADDRA_s ALT_MPFE_HMC_ADP_SERRADDRA_t;
21099 #define ALT_MPFE_HMC_ADP_SERRADDRA_RESET 0x00000000
21101 #define ALT_MPFE_HMC_ADP_SERRADDRA_OFST 0x130
21128 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_LSB 0
21130 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_MSB 31
21132 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_WIDTH 32
21134 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_SET_MSK 0xffffffff
21136 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_CLR_MSK 0x00000000
21138 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_RESET 0x0
21140 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_GET(value) (((value) & 0xffffffff) >> 0)
21142 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_SWBADDRESS_SET(value) (((value) << 0) & 0xffffffff)
21144 #ifndef __ASSEMBLY__
21156 struct ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_s
21158 volatile uint32_t SWBADDRESS : 32;
21162 typedef struct ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_s ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_t;
21166 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_RESET 0x00000000
21168 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_OFST 0x138
21203 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_LSB 0
21205 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_MSB 31
21207 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_WIDTH 32
21209 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
21211 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
21213 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_RESET 0x0
21215 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
21217 #define ALT_MPFE_HMC_ADP_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
21219 #ifndef __ASSEMBLY__
21231 struct ALT_MPFE_HMC_ADP_SERRCNTREG_s
21233 volatile uint32_t SERRCNT : 32;
21237 typedef struct ALT_MPFE_HMC_ADP_SERRCNTREG_s ALT_MPFE_HMC_ADP_SERRCNTREG_t;
21241 #define ALT_MPFE_HMC_ADP_SERRCNTREG_RESET 0x00000000
21243 #define ALT_MPFE_HMC_ADP_SERRCNTREG_OFST 0x13c
21278 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_LSB 0
21280 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_MSB 31
21282 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_WIDTH 32
21284 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_SET_MSK 0xffffffff
21286 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_CLR_MSK 0x00000000
21288 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_RESET 0x1
21290 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21292 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_CNT_SET(value) (((value) << 0) & 0xffffffff)
21294 #ifndef __ASSEMBLY__
21306 struct ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_s
21308 volatile uint32_t CNT : 32;
21312 typedef struct ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_s ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_t;
21316 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_RESET 0x00000001
21318 #define ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_OFST 0x140
21344 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_LSB 0
21346 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_MSB 7
21348 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_WIDTH 8
21350 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_SET_MSK 0x000000ff
21352 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_CLR_MSK 0xffffff00
21354 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_RESET 0x0
21356 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
21358 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
21369 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_LSB 8
21371 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_MSB 15
21373 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_WIDTH 8
21375 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_SET_MSK 0x0000ff00
21377 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_CLR_MSK 0xffff00ff
21379 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_RESET 0x0
21381 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
21383 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
21394 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_LSB 16
21396 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_MSB 23
21398 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_WIDTH 8
21400 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_SET_MSK 0x00ff0000
21402 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_CLR_MSK 0xff00ffff
21404 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_RESET 0x0
21406 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
21408 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
21419 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_LSB 24
21421 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_MSB 31
21423 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_WIDTH 8
21425 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_SET_MSK 0xff000000
21427 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_CLR_MSK 0x00ffffff
21429 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_RESET 0x0
21431 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
21433 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
21435 #ifndef __ASSEMBLY__
21447 struct ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_s
21449 volatile uint32_t ECC0BUS : 8;
21450 volatile uint32_t ECC1BUS : 8;
21451 volatile uint32_t ECC2BUS : 8;
21452 volatile uint32_t ECC3BUS : 8;
21456 typedef struct ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_s ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_t;
21460 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_RESET 0x00000000
21462 #define ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_OFST 0x144
21491 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_LSB 0
21493 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_MSB 7
21495 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_WIDTH 8
21497 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_SET_MSK 0x000000ff
21499 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_CLR_MSK 0xffffff00
21501 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_RESET 0x0
21503 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
21505 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
21519 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_LSB 8
21521 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_MSB 15
21523 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_WIDTH 8
21525 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_SET_MSK 0x0000ff00
21527 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_CLR_MSK 0xffff00ff
21529 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_RESET 0x0
21531 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
21533 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
21547 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_LSB 16
21549 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_MSB 23
21551 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_WIDTH 8
21553 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_SET_MSK 0x00ff0000
21555 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_CLR_MSK 0xff00ffff
21557 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_RESET 0x0
21559 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
21561 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
21575 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_LSB 24
21577 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_MSB 31
21579 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_WIDTH 8
21581 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_SET_MSK 0xff000000
21583 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_CLR_MSK 0x00ffffff
21585 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_RESET 0x0
21587 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
21589 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
21591 #ifndef __ASSEMBLY__
21603 struct ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_s
21605 volatile uint32_t ECC0BUS : 8;
21606 volatile uint32_t ECC1BUS : 8;
21607 volatile uint32_t ECC2BUS : 8;
21608 volatile uint32_t ECC3BUS : 8;
21612 typedef struct ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_s ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_t;
21616 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_RESET 0x00000000
21618 #define ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_OFST 0x148
21647 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_LSB 0
21649 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_MSB 7
21651 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_WIDTH 8
21653 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_SET_MSK 0x000000ff
21655 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_CLR_MSK 0xffffff00
21657 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_RESET 0x0
21659 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
21661 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
21676 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_LSB 8
21678 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_MSB 15
21680 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_WIDTH 8
21682 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_SET_MSK 0x0000ff00
21684 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_CLR_MSK 0xffff00ff
21686 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_RESET 0x0
21688 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
21690 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
21705 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_LSB 16
21707 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_MSB 23
21709 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_WIDTH 8
21711 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_SET_MSK 0x00ff0000
21713 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_CLR_MSK 0xff00ffff
21715 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_RESET 0x0
21717 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
21719 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
21734 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_LSB 24
21736 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_MSB 31
21738 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_WIDTH 8
21740 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_SET_MSK 0xff000000
21742 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_CLR_MSK 0x00ffffff
21744 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_RESET 0x0
21746 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
21748 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
21750 #ifndef __ASSEMBLY__
21762 struct ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_s
21764 volatile uint32_t ECC0BUS : 8;
21765 volatile uint32_t ECC1BUS : 8;
21766 volatile uint32_t ECC2BUS : 8;
21767 volatile uint32_t ECC3BUS : 8;
21771 typedef struct ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_s ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_t;
21775 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_RESET 0x00000000
21777 #define ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_OFST 0x14c
21822 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_E_DISABLE 0x0
21827 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_E_ENABLE 0x1
21830 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_LSB 0
21832 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_MSB 0
21834 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_WIDTH 1
21836 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_SET_MSK 0x00000001
21838 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_CLR_MSK 0xfffffffe
21840 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_RESET 0x0
21842 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_GET(value) (((value) & 0x00000001) >> 0)
21844 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_WRDIAGON_SET(value) (((value) << 0) & 0x00000001)
21875 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_E_DISABLE 0x0
21880 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_E_ENABLE 0x1
21883 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_LSB 1
21885 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_MSB 1
21887 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_WIDTH 1
21889 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_SET_MSK 0x00000002
21891 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_CLR_MSK 0xfffffffd
21893 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_RESET 0x0
21895 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_GET(value) (((value) & 0x00000002) >> 1)
21897 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RDDIAGON_SET(value) (((value) << 1) & 0x00000002)
21924 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_E_DISABLE 0x0
21929 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_E_ENABLE 0x1
21932 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_LSB 16
21934 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_MSB 16
21936 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_WIDTH 1
21938 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_SET_MSK 0x00010000
21940 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_CLR_MSK 0xfffeffff
21942 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_RESET 0x0
21944 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_GET(value) (((value) & 0x00010000) >> 16)
21946 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_ECCDIAGON_SET(value) (((value) << 16) & 0x00010000)
21948 #ifndef __ASSEMBLY__
21960 struct ALT_MPFE_HMC_ADP_ECC_DIAGON_s
21962 volatile uint32_t WRDIAGON : 1;
21963 volatile uint32_t RDDIAGON : 1;
21965 volatile uint32_t ECCDIAGON : 1;
21970 typedef struct ALT_MPFE_HMC_ADP_ECC_DIAGON_s ALT_MPFE_HMC_ADP_ECC_DIAGON_t;
21974 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_RESET 0x00000000
21976 #define ALT_MPFE_HMC_ADP_ECC_DIAGON_OFST 0x150
22020 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_LSB 0
22022 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_MSB 0
22024 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_WIDTH 1
22026 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_SET_MSK 0x00000001
22028 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_CLR_MSK 0xfffffffe
22030 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_RESET 0x0
22032 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_GET(value) (((value) & 0x00000001) >> 0)
22034 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0SERRFLG_SET(value) (((value) << 0) & 0x00000001)
22054 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_LSB 1
22056 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_MSB 1
22058 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_WIDTH 1
22060 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_SET_MSK 0x00000002
22062 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_CLR_MSK 0xfffffffd
22064 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_RESET 0x0
22066 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_GET(value) (((value) & 0x00000002) >> 1)
22068 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1SERRFLG_SET(value) (((value) << 1) & 0x00000002)
22088 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_LSB 2
22090 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_MSB 2
22092 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_WIDTH 1
22094 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_SET_MSK 0x00000004
22096 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_CLR_MSK 0xfffffffb
22098 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_RESET 0x0
22100 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_GET(value) (((value) & 0x00000004) >> 2)
22102 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2SERRFLG_SET(value) (((value) << 2) & 0x00000004)
22122 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_LSB 3
22124 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_MSB 3
22126 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_WIDTH 1
22128 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_SET_MSK 0x00000008
22130 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_CLR_MSK 0xfffffff7
22132 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_RESET 0x0
22134 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_GET(value) (((value) & 0x00000008) >> 3)
22136 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3SERRFLG_SET(value) (((value) << 3) & 0x00000008)
22156 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_LSB 4
22158 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_MSB 4
22160 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_WIDTH 1
22162 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_SET_MSK 0x00000010
22164 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_CLR_MSK 0xffffffef
22166 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_RESET 0x0
22168 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_GET(value) (((value) & 0x00000010) >> 4)
22170 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0ADDRFLG_SET(value) (((value) << 4) & 0x00000010)
22190 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_LSB 5
22192 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_MSB 5
22194 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_WIDTH 1
22196 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_SET_MSK 0x00000020
22198 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_CLR_MSK 0xffffffdf
22200 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_RESET 0x0
22202 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_GET(value) (((value) & 0x00000020) >> 5)
22204 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1ADDRFLG_SET(value) (((value) << 5) & 0x00000020)
22224 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_LSB 6
22226 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_MSB 6
22228 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_WIDTH 1
22230 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_SET_MSK 0x00000040
22232 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_CLR_MSK 0xffffffbf
22234 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_RESET 0x0
22236 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_GET(value) (((value) & 0x00000040) >> 6)
22238 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2ADDRFLG_SET(value) (((value) << 6) & 0x00000040)
22258 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_LSB 7
22260 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_MSB 7
22262 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_WIDTH 1
22264 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_SET_MSK 0x00000080
22266 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_CLR_MSK 0xffffff7f
22268 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_RESET 0x0
22270 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_GET(value) (((value) & 0x00000080) >> 7)
22272 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3ADDRFLG_SET(value) (((value) << 7) & 0x00000080)
22292 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_LSB 8
22294 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_MSB 8
22296 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_WIDTH 1
22298 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_SET_MSK 0x00000100
22300 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_CLR_MSK 0xfffffeff
22302 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_RESET 0x0
22304 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_GET(value) (((value) & 0x00000100) >> 8)
22306 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC0DERRFLG_SET(value) (((value) << 8) & 0x00000100)
22326 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_LSB 9
22328 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_MSB 9
22330 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_WIDTH 1
22332 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_SET_MSK 0x00000200
22334 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_CLR_MSK 0xfffffdff
22336 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_RESET 0x0
22338 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_GET(value) (((value) & 0x00000200) >> 9)
22340 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC1DERRFLG_SET(value) (((value) << 9) & 0x00000200)
22360 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_LSB 10
22362 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_MSB 10
22364 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_WIDTH 1
22366 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_SET_MSK 0x00000400
22368 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_CLR_MSK 0xfffffbff
22370 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_RESET 0x0
22372 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_GET(value) (((value) & 0x00000400) >> 10)
22374 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC2DERRFLG_SET(value) (((value) << 10) & 0x00000400)
22394 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_LSB 11
22396 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_MSB 11
22398 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_WIDTH 1
22400 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_SET_MSK 0x00000800
22402 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_CLR_MSK 0xfffff7ff
22404 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_RESET 0x0
22406 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_GET(value) (((value) & 0x00000800) >> 11)
22408 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_DEC3DERRFLG_SET(value) (((value) << 11) & 0x00000800)
22410 #ifndef __ASSEMBLY__
22422 struct ALT_MPFE_HMC_ADP_ECC_DECSTAT_s
22424 volatile uint32_t DEC0SERRFLG : 1;
22425 volatile uint32_t DEC1SERRFLG : 1;
22426 volatile uint32_t DEC2SERRFLG : 1;
22427 volatile uint32_t DEC3SERRFLG : 1;
22428 volatile uint32_t DEC0ADDRFLG : 1;
22429 volatile uint32_t DEC1ADDRFLG : 1;
22430 volatile uint32_t DEC2ADDRFLG : 1;
22431 volatile uint32_t DEC3ADDRFLG : 1;
22432 volatile uint32_t DEC0DERRFLG : 1;
22433 volatile uint32_t DEC1DERRFLG : 1;
22434 volatile uint32_t DEC2DERRFLG : 1;
22435 volatile uint32_t DEC3DERRFLG : 1;
22440 typedef struct ALT_MPFE_HMC_ADP_ECC_DECSTAT_s ALT_MPFE_HMC_ADP_ECC_DECSTAT_t;
22444 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_RESET 0x00000000
22446 #define ALT_MPFE_HMC_ADP_ECC_DECSTAT_OFST 0x154
22472 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_LSB 0
22474 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_MSB 31
22476 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_WIDTH 32
22478 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_SET_MSK 0xffffffff
22480 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_CLR_MSK 0x00000000
22482 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_RESET 0x0
22484 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
22486 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_ADDR_SET(value) (((value) << 0) & 0xffffffff)
22488 #ifndef __ASSEMBLY__
22500 struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_s
22502 volatile uint32_t ADDR : 32;
22506 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_s ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_t;
22510 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_RESET 0x00000000
22512 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_OFST 0x160
22538 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_LSB 0
22540 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_MSB 31
22542 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_WIDTH 32
22544 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_SET_MSK 0xffffffff
22546 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_CLR_MSK 0x00000000
22548 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_RESET 0x0
22550 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
22552 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_ADDR_SET(value) (((value) << 0) & 0xffffffff)
22554 #ifndef __ASSEMBLY__
22566 struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_s
22568 volatile uint32_t ADDR : 32;
22572 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_s ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_t;
22576 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_RESET 0x00000000
22578 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_OFST 0x164
22604 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_LSB 0
22606 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_MSB 31
22608 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_WIDTH 32
22610 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_SET_MSK 0xffffffff
22612 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_CLR_MSK 0x00000000
22614 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_RESET 0x0
22616 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
22618 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_ADDR_SET(value) (((value) << 0) & 0xffffffff)
22620 #ifndef __ASSEMBLY__
22632 struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_s
22634 volatile uint32_t ADDR : 32;
22638 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_s ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_t;
22642 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_RESET 0x00000000
22644 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_OFST 0x168
22670 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_LSB 0
22672 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_MSB 31
22674 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_WIDTH 32
22676 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_SET_MSK 0xffffffff
22678 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_CLR_MSK 0x00000000
22680 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_RESET 0x0
22682 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
22684 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_ADDR_SET(value) (((value) << 0) & 0xffffffff)
22686 #ifndef __ASSEMBLY__
22698 struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_s
22700 volatile uint32_t ADDR : 32;
22704 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_s ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_t;
22708 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_RESET 0x00000000
22710 #define ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_OFST 0x16c
22736 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_LSB 0
22738 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_MSB 7
22740 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_WIDTH 8
22742 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_SET_MSK 0x000000ff
22744 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_CLR_MSK 0xffffff00
22746 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_RESET 0x0
22748 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
22750 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
22761 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_LSB 8
22763 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_MSB 15
22765 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_WIDTH 8
22767 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_SET_MSK 0x0000ff00
22769 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_CLR_MSK 0xffff00ff
22771 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_RESET 0x0
22773 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
22775 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
22786 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_LSB 16
22788 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_MSB 23
22790 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_WIDTH 8
22792 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_SET_MSK 0x00ff0000
22794 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_CLR_MSK 0xff00ffff
22796 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_RESET 0x0
22798 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
22800 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
22811 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_LSB 24
22813 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_MSB 31
22815 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_WIDTH 8
22817 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_SET_MSK 0xff000000
22819 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_CLR_MSK 0x00ffffff
22821 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_RESET 0x0
22823 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
22825 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
22827 #ifndef __ASSEMBLY__
22839 struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_s
22841 volatile uint32_t ECC0BUS : 8;
22842 volatile uint32_t ECC1BUS : 8;
22843 volatile uint32_t ECC2BUS : 8;
22844 volatile uint32_t ECC3BUS : 8;
22848 typedef struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_s ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_t;
22852 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_RESET 0x00000000
22854 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_OFST 0x170
22880 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_LSB 0
22882 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_MSB 7
22884 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_WIDTH 8
22886 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_SET_MSK 0x000000ff
22888 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_CLR_MSK 0xffffff00
22890 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_RESET 0x0
22892 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
22894 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
22905 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_LSB 8
22907 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_MSB 15
22909 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_WIDTH 8
22911 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_SET_MSK 0x0000ff00
22913 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_CLR_MSK 0xffff00ff
22915 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_RESET 0x0
22917 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
22919 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
22930 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_LSB 16
22932 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_MSB 23
22934 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_WIDTH 8
22936 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_SET_MSK 0x00ff0000
22938 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_CLR_MSK 0xff00ffff
22940 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_RESET 0x0
22942 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
22944 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
22955 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_LSB 24
22957 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_MSB 31
22959 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_WIDTH 8
22961 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_SET_MSK 0xff000000
22963 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_CLR_MSK 0x00ffffff
22965 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_RESET 0x0
22967 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
22969 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
22971 #ifndef __ASSEMBLY__
22983 struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_s
22985 volatile uint32_t ECC0BUS : 8;
22986 volatile uint32_t ECC1BUS : 8;
22987 volatile uint32_t ECC2BUS : 8;
22988 volatile uint32_t ECC3BUS : 8;
22992 typedef struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_s ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_t;
22996 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_RESET 0x00000000
22998 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_OFST 0x174
23024 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_LSB 0
23026 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_MSB 7
23028 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_WIDTH 8
23030 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_SET_MSK 0x000000ff
23032 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_CLR_MSK 0xffffff00
23034 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_RESET 0x0
23036 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
23038 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
23049 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_LSB 8
23051 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_MSB 15
23053 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_WIDTH 8
23055 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_SET_MSK 0x0000ff00
23057 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_CLR_MSK 0xffff00ff
23059 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_RESET 0x0
23061 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
23063 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
23074 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_LSB 16
23076 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_MSB 23
23078 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_WIDTH 8
23080 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_SET_MSK 0x00ff0000
23082 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_CLR_MSK 0xff00ffff
23084 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_RESET 0x0
23086 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
23088 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
23099 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_LSB 24
23101 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_MSB 31
23103 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_WIDTH 8
23105 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_SET_MSK 0xff000000
23107 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_CLR_MSK 0x00ffffff
23109 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_RESET 0x0
23111 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
23113 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
23115 #ifndef __ASSEMBLY__
23127 struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_s
23129 volatile uint32_t ECC0BUS : 8;
23130 volatile uint32_t ECC1BUS : 8;
23131 volatile uint32_t ECC2BUS : 8;
23132 volatile uint32_t ECC3BUS : 8;
23136 typedef struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_s ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_t;
23140 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_RESET 0x00000000
23142 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_OFST 0x178
23168 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_LSB 0
23170 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_MSB 7
23172 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_WIDTH 8
23174 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_SET_MSK 0x000000ff
23176 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_CLR_MSK 0xffffff00
23178 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_RESET 0x0
23180 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
23182 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
23193 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_LSB 8
23195 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_MSB 15
23197 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_WIDTH 8
23199 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_SET_MSK 0x0000ff00
23201 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_CLR_MSK 0xffff00ff
23203 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_RESET 0x0
23205 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
23207 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
23218 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_LSB 16
23220 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_MSB 23
23222 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_WIDTH 8
23224 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_SET_MSK 0x00ff0000
23226 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_CLR_MSK 0xff00ffff
23228 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_RESET 0x0
23230 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
23232 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
23243 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_LSB 24
23245 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_MSB 31
23247 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_WIDTH 8
23249 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_SET_MSK 0xff000000
23251 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_CLR_MSK 0x00ffffff
23253 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_RESET 0x0
23255 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
23257 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
23259 #ifndef __ASSEMBLY__
23271 struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_s
23273 volatile uint32_t ECC0BUS : 8;
23274 volatile uint32_t ECC1BUS : 8;
23275 volatile uint32_t ECC2BUS : 8;
23276 volatile uint32_t ECC3BUS : 8;
23280 typedef struct ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_s ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_t;
23284 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_RESET 0x00000000
23286 #define ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_OFST 0x17c
23314 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_LSB 0
23316 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_MSB 4
23318 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_WIDTH 5
23320 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_SET_MSK 0x0000001f
23322 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_CLR_MSK 0xffffffe0
23324 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_RESET 0x0
23326 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_GET(value) (((value) & 0x0000001f) >> 0)
23328 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_ADDR_SET(value) (((value) << 0) & 0x0000001f)
23330 #ifndef __ASSEMBLY__
23342 struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_s
23344 volatile uint32_t ADDR : 5;
23349 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_s ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_t;
23353 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_RESET 0x00000000
23355 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_OFST 0x180
23383 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_LSB 0
23385 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_MSB 4
23387 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_WIDTH 5
23389 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_SET_MSK 0x0000001f
23391 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_CLR_MSK 0xffffffe0
23393 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_RESET 0x0
23395 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_GET(value) (((value) & 0x0000001f) >> 0)
23397 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_ADDR_SET(value) (((value) << 0) & 0x0000001f)
23399 #ifndef __ASSEMBLY__
23411 struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_s
23413 volatile uint32_t ADDR : 5;
23418 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_s ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_t;
23422 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_RESET 0x00000000
23424 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_OFST 0x184
23452 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_LSB 0
23454 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_MSB 4
23456 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_WIDTH 5
23458 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_SET_MSK 0x0000001f
23460 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_CLR_MSK 0xffffffe0
23462 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_RESET 0x0
23464 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_GET(value) (((value) & 0x0000001f) >> 0)
23466 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_ADDR_SET(value) (((value) << 0) & 0x0000001f)
23468 #ifndef __ASSEMBLY__
23480 struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_s
23482 volatile uint32_t ADDR : 5;
23487 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_s ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_t;
23491 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_RESET 0x00000000
23493 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_OFST 0x188
23521 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_LSB 0
23523 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_MSB 4
23525 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_WIDTH 5
23527 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_SET_MSK 0x0000001f
23529 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_CLR_MSK 0xffffffe0
23531 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_RESET 0x0
23533 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_GET(value) (((value) & 0x0000001f) >> 0)
23535 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_ADDR_SET(value) (((value) << 0) & 0x0000001f)
23537 #ifndef __ASSEMBLY__
23549 struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_s
23551 volatile uint32_t ADDR : 5;
23556 typedef struct ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_s ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_t;
23560 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_RESET 0x00000000
23562 #define ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_OFST 0x18c
23592 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_LSB 0
23594 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_MSB 4
23596 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_WIDTH 5
23598 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_SET_MSK 0x0000001f
23600 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_CLR_MSK 0xffffffe0
23602 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_RESET 0x0
23604 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_GET(value) (((value) & 0x0000001f) >> 0)
23606 #define ALT_MPFE_HMC_ADP_DERRHADDR_DADDRESS_SET(value) (((value) << 0) & 0x0000001f)
23608 #ifndef __ASSEMBLY__
23620 struct ALT_MPFE_HMC_ADP_DERRHADDR_s
23622 volatile uint32_t DADDRESS : 5;
23627 typedef struct ALT_MPFE_HMC_ADP_DERRHADDR_s ALT_MPFE_HMC_ADP_DERRHADDR_t;
23631 #define ALT_MPFE_HMC_ADP_DERRHADDR_RESET 0x00000000
23633 #define ALT_MPFE_HMC_ADP_DERRHADDR_OFST 0x1b0
23661 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_LSB 0
23663 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_MSB 4
23665 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_WIDTH 5
23667 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_SET_MSK 0x0000001f
23669 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_CLR_MSK 0xffffffe0
23671 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_RESET 0x0
23673 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_GET(value) (((value) & 0x0000001f) >> 0)
23675 #define ALT_MPFE_HMC_ADP_SERRHADDR_SADDRESS_SET(value) (((value) << 0) & 0x0000001f)
23677 #ifndef __ASSEMBLY__
23689 struct ALT_MPFE_HMC_ADP_SERRHADDR_s
23691 volatile uint32_t SADDRESS : 5;
23696 typedef struct ALT_MPFE_HMC_ADP_SERRHADDR_s ALT_MPFE_HMC_ADP_SERRHADDR_t;
23700 #define ALT_MPFE_HMC_ADP_SERRHADDR_RESET 0x00000000
23702 #define ALT_MPFE_HMC_ADP_SERRHADDR_OFST 0x1b4
23730 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_LSB 0
23732 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_MSB 4
23734 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_WIDTH 5
23736 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_SET_MSK 0x0000001f
23738 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_CLR_MSK 0xffffffe0
23740 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_RESET 0x0
23742 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_GET(value) (((value) & 0x0000001f) >> 0)
23744 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_SWBADDRESS_SET(value) (((value) << 0) & 0x0000001f)
23746 #ifndef __ASSEMBLY__
23758 struct ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_s
23760 volatile uint32_t SWBADDRESS : 5;
23765 typedef struct ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_s ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_t;
23769 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_RESET 0x00000000
23771 #define ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_OFST 0x1bc
23825 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_E_FPGA 0x0
23830 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_E_HPS 0x1
23833 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_LSB 0
23835 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_MSB 0
23837 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_WIDTH 1
23839 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_SET_MSK 0x00000001
23841 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_CLR_MSK 0xfffffffe
23843 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_RESET 0x0
23845 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_GET(value) (((value) & 0x00000001) >> 0)
23847 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE0_SET(value) (((value) << 0) & 0x00000001)
23872 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_E_FPGA 0x0
23877 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_E_HPS 0x1
23880 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_LSB 1
23882 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_MSB 1
23884 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_WIDTH 1
23886 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_SET_MSK 0x00000002
23888 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_CLR_MSK 0xfffffffd
23890 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_RESET 0x0
23892 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_GET(value) (((value) & 0x00000002) >> 1)
23894 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE1_SET(value) (((value) << 1) & 0x00000002)
23919 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_E_FPGA 0x0
23924 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_E_HPS 0x1
23927 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_LSB 2
23929 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_MSB 2
23931 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_WIDTH 1
23933 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_SET_MSK 0x00000004
23935 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_CLR_MSK 0xfffffffb
23937 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_RESET 0x0
23939 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_GET(value) (((value) & 0x00000004) >> 2)
23941 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE2_SET(value) (((value) << 2) & 0x00000004)
23966 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_E_FPGA 0x0
23971 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_E_HPS 0x1
23974 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_LSB 3
23976 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_MSB 3
23978 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_WIDTH 1
23980 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_SET_MSK 0x00000008
23982 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_CLR_MSK 0xfffffff7
23984 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_RESET 0x0
23986 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_GET(value) (((value) & 0x00000008) >> 3)
23988 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_LANE3_SET(value) (((value) << 3) & 0x00000008)
24013 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_E_FPGA 0x0
24018 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_E_HPS 0x1
24021 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_LSB 4
24023 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_MSB 4
24025 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_WIDTH 1
24027 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_SET_MSK 0x00000010
24029 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_CLR_MSK 0xffffffef
24031 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_RESET 0x0
24033 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_GET(value) (((value) & 0x00000010) >> 4)
24035 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEA_HMC_SET(value) (((value) << 4) & 0x00000010)
24060 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_E_FPGA 0x0
24065 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_E_HPS 0x1
24068 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_LSB 8
24070 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_MSB 8
24072 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_WIDTH 1
24074 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_SET_MSK 0x00000100
24076 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_CLR_MSK 0xfffffeff
24078 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_RESET 0x0
24080 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_GET(value) (((value) & 0x00000100) >> 8)
24082 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE0_SET(value) (((value) << 8) & 0x00000100)
24107 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_E_FPGA 0x0
24112 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_E_HPS 0x1
24115 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_LSB 9
24117 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_MSB 9
24119 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_WIDTH 1
24121 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_SET_MSK 0x00000200
24123 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_CLR_MSK 0xfffffdff
24125 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_RESET 0x0
24127 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_GET(value) (((value) & 0x00000200) >> 9)
24129 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE1_SET(value) (((value) << 9) & 0x00000200)
24154 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_E_FPGA 0x0
24159 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_E_HPS 0x1
24162 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_LSB 10
24164 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_MSB 10
24166 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_WIDTH 1
24168 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_SET_MSK 0x00000400
24170 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_CLR_MSK 0xfffffbff
24172 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_RESET 0x0
24174 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_GET(value) (((value) & 0x00000400) >> 10)
24176 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE2_SET(value) (((value) << 10) & 0x00000400)
24201 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_E_FPGA 0x0
24206 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_E_HPS 0x1
24209 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_LSB 11
24211 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_MSB 11
24213 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_WIDTH 1
24215 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_SET_MSK 0x00000800
24217 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_CLR_MSK 0xfffff7ff
24219 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_RESET 0x0
24221 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_GET(value) (((value) & 0x00000800) >> 11)
24223 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_LANE3_SET(value) (((value) << 11) & 0x00000800)
24248 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_E_FPGA 0x0
24253 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_E_HPS 0x1
24256 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_LSB 12
24258 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_MSB 12
24260 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_WIDTH 1
24262 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_SET_MSK 0x00001000
24264 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_CLR_MSK 0xffffefff
24266 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_RESET 0x0
24268 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_GET(value) (((value) & 0x00001000) >> 12)
24270 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEB_HMC_SET(value) (((value) << 12) & 0x00001000)
24295 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_E_FPGA 0x0
24300 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_E_HPS 0x1
24303 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_LSB 16
24305 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_MSB 16
24307 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_WIDTH 1
24309 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_SET_MSK 0x00010000
24311 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_CLR_MSK 0xfffeffff
24313 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_RESET 0x0
24315 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_GET(value) (((value) & 0x00010000) >> 16)
24317 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE0_SET(value) (((value) << 16) & 0x00010000)
24342 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_E_FPGA 0x0
24347 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_E_HPS 0x1
24350 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_LSB 17
24352 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_MSB 17
24354 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_WIDTH 1
24356 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_SET_MSK 0x00020000
24358 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_CLR_MSK 0xfffdffff
24360 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_RESET 0x0
24362 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_GET(value) (((value) & 0x00020000) >> 17)
24364 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE1_SET(value) (((value) << 17) & 0x00020000)
24389 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_E_FPGA 0x0
24394 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_E_HPS 0x1
24397 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_LSB 18
24399 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_MSB 18
24401 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_WIDTH 1
24403 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_SET_MSK 0x00040000
24405 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_CLR_MSK 0xfffbffff
24407 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_RESET 0x0
24409 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_GET(value) (((value) & 0x00040000) >> 18)
24411 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE2_SET(value) (((value) << 18) & 0x00040000)
24436 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_E_FPGA 0x0
24441 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_E_HPS 0x1
24444 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_LSB 19
24446 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_MSB 19
24448 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_WIDTH 1
24450 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_SET_MSK 0x00080000
24452 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_CLR_MSK 0xfff7ffff
24454 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_RESET 0x0
24456 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_GET(value) (((value) & 0x00080000) >> 19)
24458 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_LANE3_SET(value) (((value) << 19) & 0x00080000)
24483 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_E_FPGA 0x0
24488 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_E_HPS 0x1
24491 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_LSB 20
24493 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_MSB 20
24495 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_WIDTH 1
24497 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_SET_MSK 0x00100000
24499 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_CLR_MSK 0xffefffff
24501 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_RESET 0x0
24503 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_GET(value) (((value) & 0x00100000) >> 20)
24505 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_TILEC_HMC_SET(value) (((value) << 20) & 0x00100000)
24507 #ifndef __ASSEMBLY__
24519 struct ALT_MPFE_HMC_ADP_HPSINTFCSEL_s
24521 volatile uint32_t TILEA_LANE0 : 1;
24522 volatile uint32_t TILEA_LANE1 : 1;
24523 volatile uint32_t TILEA_LANE2 : 1;
24524 volatile uint32_t TILEA_LANE3 : 1;
24525 volatile uint32_t TILEA_HMC : 1;
24527 volatile uint32_t TILEB_LANE0 : 1;
24528 volatile uint32_t TILEB_LANE1 : 1;
24529 volatile uint32_t TILEB_LANE2 : 1;
24530 volatile uint32_t TILEB_LANE3 : 1;
24531 volatile uint32_t TILEB_HMC : 1;
24533 volatile uint32_t TILEC_LANE0 : 1;
24534 volatile uint32_t TILEC_LANE1 : 1;
24535 volatile uint32_t TILEC_LANE2 : 1;
24536 volatile uint32_t TILEC_LANE3 : 1;
24537 volatile uint32_t TILEC_HMC : 1;
24542 typedef struct ALT_MPFE_HMC_ADP_HPSINTFCSEL_s ALT_MPFE_HMC_ADP_HPSINTFCSEL_t;
24546 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_RESET 0x00000000
24548 #define ALT_MPFE_HMC_ADP_HPSINTFCSEL_OFST 0x210
24572 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_LSB 0
24574 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_MSB 7
24576 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_WIDTH 8
24578 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_SET_MSK 0x000000ff
24580 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_CLR_MSK 0xffffff00
24582 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_RESET 0x0
24584 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_GET(value) (((value) & 0x000000ff) >> 0)
24586 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_CORE2SEQ_SET(value) (((value) << 0) & 0x000000ff)
24588 #ifndef __ASSEMBLY__
24600 struct ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_s
24602 volatile uint32_t CORE2SEQ : 8;
24607 typedef struct ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_s ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_t;
24611 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_RESET 0x00000000
24613 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_OFST 0x214
24637 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_LSB 0
24639 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_MSB 7
24641 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_WIDTH 8
24643 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_SET_MSK 0x000000ff
24645 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_CLR_MSK 0xffffff00
24647 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_RESET 0x0
24649 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_GET(value) (((value) & 0x000000ff) >> 0)
24651 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE_SET(value) (((value) << 0) & 0x000000ff)
24653 #ifndef __ASSEMBLY__
24665 struct ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_s
24667 volatile uint32_t SEQ2CORE : 8;
24672 typedef struct ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_s ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_t;
24676 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_RESET 0x00000000
24678 #define ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_OFST 0x218
24680 #ifndef __ASSEMBLY__
24692 struct ALT_MPFE_HMC_ADP_s
24694 volatile ALT_MPFE_HMC_ADP_IP_REV_ID_t IP_REV_ID;
24695 volatile uint32_t _pad_0x4_0x7;
24696 volatile ALT_MPFE_HMC_ADP_DDRIOCTRL_t DDRIOCTRL;
24697 volatile ALT_MPFE_HMC_ADP_DDRCALSTAT_t DDRCALSTAT;
24698 volatile ALT_MPFE_HMC_ADP_MPR_0BEAT1_t MPR_0BEAT1;
24699 volatile ALT_MPFE_HMC_ADP_MPR_1BEAT1_t MPR_1BEAT1;
24700 volatile ALT_MPFE_HMC_ADP_MPR_2BEAT1_t MPR_2BEAT1;
24701 volatile ALT_MPFE_HMC_ADP_MPR_3BEAT1_t MPR_3BEAT1;
24702 volatile ALT_MPFE_HMC_ADP_MPR_4BEAT1_t MPR_4BEAT1;
24703 volatile ALT_MPFE_HMC_ADP_MPR_5BEAT1_t MPR_5BEAT1;
24704 volatile ALT_MPFE_HMC_ADP_MPR_6BEAT1_t MPR_6BEAT1;
24705 volatile ALT_MPFE_HMC_ADP_MPR_7BEAT1_t MPR_7BEAT1;
24706 volatile ALT_MPFE_HMC_ADP_MPR_8BEAT1_t MPR_8BEAT1;
24707 volatile ALT_MPFE_HMC_ADP_MPR_0BEAT2_t MPR_0BEAT2;
24708 volatile ALT_MPFE_HMC_ADP_MPR_1BEAT2_t MPR_1BEAT2;
24709 volatile ALT_MPFE_HMC_ADP_MPR_2BEAT2_t MPR_2BEAT2;
24710 volatile ALT_MPFE_HMC_ADP_MPR_3BEAT2_t MPR_3BEAT2;
24711 volatile ALT_MPFE_HMC_ADP_MPR_4BEAT2_t MPR_4BEAT2;
24712 volatile ALT_MPFE_HMC_ADP_MPR_5BEAT2_t MPR_5BEAT2;
24713 volatile ALT_MPFE_HMC_ADP_MPR_6BEAT2_t MPR_6BEAT2;
24714 volatile ALT_MPFE_HMC_ADP_MPR_7BEAT2_t MPR_7BEAT2;
24715 volatile ALT_MPFE_HMC_ADP_MPR_8BEAT2_t MPR_8BEAT2;
24716 volatile uint32_t _pad_0x58_0x5f[2];
24717 volatile ALT_MPFE_HMC_ADP_AUTO_PRECHARGE_t AUTO_PRECHARGE;
24718 volatile uint32_t _pad_0x64_0xdf[31];
24719 volatile ALT_MPFE_HMC_ADP_DRAMADDRWIDTH_t DRAMADDRWIDTH;
24720 volatile uint32_t _pad_0xe4_0xff[7];
24721 volatile ALT_MPFE_HMC_ADP_ECCCTRL1_t ECCCTRL1;
24722 volatile ALT_MPFE_HMC_ADP_ECCCTRL2_t ECCCTRL2;
24723 volatile uint32_t _pad_0x108_0x10f[2];
24724 volatile ALT_MPFE_HMC_ADP_ERRINTEN_t ERRINTEN;
24725 volatile ALT_MPFE_HMC_ADP_ERRINTENS_t ERRINTENS;
24726 volatile ALT_MPFE_HMC_ADP_ERRINTENR_t ERRINTENR;
24727 volatile ALT_MPFE_HMC_ADP_INTMODE_t INTMODE;
24728 volatile ALT_MPFE_HMC_ADP_INTSTAT_t INTSTAT;
24729 volatile ALT_MPFE_HMC_ADP_DIAGINTTEST_t DIAGINTTEST;
24730 volatile ALT_MPFE_HMC_ADP_MODSTAT_t MODSTAT;
24731 volatile ALT_MPFE_HMC_ADP_DERRADDRA_t DERRADDRA;
24732 volatile ALT_MPFE_HMC_ADP_SERRADDRA_t SERRADDRA;
24733 volatile uint32_t _pad_0x134_0x137;
24734 volatile ALT_MPFE_HMC_ADP_AUTOWB_CORRADDR_t AUTOWB_CORRADDR;
24735 volatile ALT_MPFE_HMC_ADP_SERRCNTREG_t SERRCNTREG;
24736 volatile ALT_MPFE_HMC_ADP_AUTOWB_DROP_CNTREG_t AUTOWB_DROP_CNTREG;
24737 volatile ALT_MPFE_HMC_ADP_ECC_REG2WRECCDATABUS_t ECC_REG2WRECCDATABUS;
24738 volatile ALT_MPFE_HMC_ADP_ECC_RDECCDATA2REGBUS_t ECC_RDECCDATA2REGBUS;
24739 volatile ALT_MPFE_HMC_ADP_ECC_REG2RDECCDATABUS_t ECC_REG2RDECCDATABUS;
24740 volatile ALT_MPFE_HMC_ADP_ECC_DIAGON_t ECC_DIAGON;
24741 volatile ALT_MPFE_HMC_ADP_ECC_DECSTAT_t ECC_DECSTAT;
24742 volatile uint32_t _pad_0x158_0x15f[2];
24743 volatile ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_0_t ECC_ERRGENADDR_0;
24744 volatile ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_1_t ECC_ERRGENADDR_1;
24745 volatile ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_2_t ECC_ERRGENADDR_2;
24746 volatile ALT_MPFE_HMC_ADP_ECC_ERRGENADDR_3_t ECC_ERRGENADDR_3;
24747 volatile ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT0_t ECC_REG2RDDATABUS_BEAT0;
24748 volatile ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT1_t ECC_REG2RDDATABUS_BEAT1;
24749 volatile ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT2_t ECC_REG2RDDATABUS_BEAT2;
24750 volatile ALT_MPFE_HMC_ADP_ECC_REG2RDDATABUS_BEAT3_t ECC_REG2RDDATABUS_BEAT3;
24751 volatile ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_0_t ECC_ERRGENHADDR_0;
24752 volatile ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_1_t ECC_ERRGENHADDR_1;
24753 volatile ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_2_t ECC_ERRGENHADDR_2;
24754 volatile ALT_MPFE_HMC_ADP_ECC_ERRGENHADDR_3_t ECC_ERRGENHADDR_3;
24755 volatile uint32_t _pad_0x190_0x1af[8];
24756 volatile ALT_MPFE_HMC_ADP_DERRHADDR_t DERRHADDR;
24757 volatile ALT_MPFE_HMC_ADP_SERRHADDR_t SERRHADDR;
24758 volatile uint32_t _pad_0x1b8_0x1bb;
24759 volatile ALT_MPFE_HMC_ADP_AUTOWB_CORRHADDR_t AUTOWB_CORRHADDR;
24760 volatile uint32_t _pad_0x1c0_0x20f[20];
24761 volatile ALT_MPFE_HMC_ADP_HPSINTFCSEL_t HPSINTFCSEL;
24762 volatile ALT_MPFE_HMC_ADP_RSTHANDSHAKECTRL_t RSTHANDSHAKECTRL;
24763 volatile ALT_MPFE_HMC_ADP_RSTHANDSHAKESTAT_t RSTHANDSHAKESTAT;
24764 volatile uint32_t _pad_0x21c_0x500[185];
24768 typedef struct ALT_MPFE_HMC_ADP_s ALT_MPFE_HMC_ADP_t;
24770 struct ALT_MPFE_HMC_ADP_raw_s
24772 volatile uint32_t IP_REV_ID;
24773 volatile uint32_t _pad_0x4_0x7;
24774 volatile uint32_t DDRIOCTRL;
24775 volatile uint32_t DDRCALSTAT;
24776 volatile uint32_t MPR_0BEAT1;
24777 volatile uint32_t MPR_1BEAT1;
24778 volatile uint32_t MPR_2BEAT1;
24779 volatile uint32_t MPR_3BEAT1;
24780 volatile uint32_t MPR_4BEAT1;
24781 volatile uint32_t MPR_5BEAT1;
24782 volatile uint32_t MPR_6BEAT1;
24783 volatile uint32_t MPR_7BEAT1;
24784 volatile uint32_t MPR_8BEAT1;
24785 volatile uint32_t MPR_0BEAT2;
24786 volatile uint32_t MPR_1BEAT2;
24787 volatile uint32_t MPR_2BEAT2;
24788 volatile uint32_t MPR_3BEAT2;
24789 volatile uint32_t MPR_4BEAT2;
24790 volatile uint32_t MPR_5BEAT2;
24791 volatile uint32_t MPR_6BEAT2;
24792 volatile uint32_t MPR_7BEAT2;
24793 volatile uint32_t MPR_8BEAT2;
24794 volatile uint32_t _pad_0x58_0x5f[2];
24795 volatile uint32_t AUTO_PRECHARGE;
24796 volatile uint32_t _pad_0x64_0xdf[31];
24797 volatile uint32_t DRAMADDRWIDTH;
24798 volatile uint32_t _pad_0xe4_0xff[7];
24799 volatile uint32_t ECCCTRL1;
24800 volatile uint32_t ECCCTRL2;
24801 volatile uint32_t _pad_0x108_0x10f[2];
24802 volatile uint32_t ERRINTEN;
24803 volatile uint32_t ERRINTENS;
24804 volatile uint32_t ERRINTENR;
24805 volatile uint32_t INTMODE;
24806 volatile uint32_t INTSTAT;
24807 volatile uint32_t DIAGINTTEST;
24808 volatile uint32_t MODSTAT;
24809 volatile uint32_t DERRADDRA;
24810 volatile uint32_t SERRADDRA;
24811 volatile uint32_t _pad_0x134_0x137;
24812 volatile uint32_t AUTOWB_CORRADDR;
24813 volatile uint32_t SERRCNTREG;
24814 volatile uint32_t AUTOWB_DROP_CNTREG;
24815 volatile uint32_t ECC_REG2WRECCDATABUS;
24816 volatile uint32_t ECC_RDECCDATA2REGBUS;
24817 volatile uint32_t ECC_REG2RDECCDATABUS;
24818 volatile uint32_t ECC_DIAGON;
24819 volatile uint32_t ECC_DECSTAT;
24820 volatile uint32_t _pad_0x158_0x15f[2];
24821 volatile uint32_t ECC_ERRGENADDR_0;
24822 volatile uint32_t ECC_ERRGENADDR_1;
24823 volatile uint32_t ECC_ERRGENADDR_2;
24824 volatile uint32_t ECC_ERRGENADDR_3;
24825 volatile uint32_t ECC_REG2RDDATABUS_BEAT0;
24826 volatile uint32_t ECC_REG2RDDATABUS_BEAT1;
24827 volatile uint32_t ECC_REG2RDDATABUS_BEAT2;
24828 volatile uint32_t ECC_REG2RDDATABUS_BEAT3;
24829 volatile uint32_t ECC_ERRGENHADDR_0;
24830 volatile uint32_t ECC_ERRGENHADDR_1;
24831 volatile uint32_t ECC_ERRGENHADDR_2;
24832 volatile uint32_t ECC_ERRGENHADDR_3;
24833 volatile uint32_t _pad_0x190_0x1af[8];
24834 volatile uint32_t DERRHADDR;
24835 volatile uint32_t SERRHADDR;
24836 volatile uint32_t _pad_0x1b8_0x1bb;
24837 volatile uint32_t AUTOWB_CORRHADDR;
24838 volatile uint32_t _pad_0x1c0_0x20f[20];
24839 volatile uint32_t HPSINTFCSEL;
24840 volatile uint32_t RSTHANDSHAKECTRL;
24841 volatile uint32_t RSTHANDSHAKESTAT;
24842 volatile uint32_t _pad_0x21c_0x500[185];
24846 typedef struct ALT_MPFE_HMC_ADP_raw_s ALT_MPFE_HMC_ADP_raw_t;
24874 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_LSB 0
24876 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_MSB 7
24878 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_WIDTH 8
24880 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
24882 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
24884 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_RESET 0x7
24886 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
24888 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
24899 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_LSB 8
24901 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_MSB 31
24903 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_WIDTH 24
24905 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
24907 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
24909 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_RESET 0xca7ca6
24911 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
24913 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
24915 #ifndef __ASSEMBLY__
24927 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_s
24929 const volatile uint32_t CORETYPEID : 8;
24930 const volatile uint32_t CORECHECKSUM : 24;
24934 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_t;
24938 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_RESET 0xca7ca607
24940 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_OFST 0x0
24962 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_LSB 0
24964 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_MSB 7
24966 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_WIDTH 8
24968 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_SET_MSK 0x000000ff
24970 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
24972 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_RESET 0x0
24974 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
24976 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
24988 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_LSB 8
24990 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_MSB 31
24992 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_WIDTH 24
24994 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
24996 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
24998 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_RESET 0x148
25000 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
25002 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
25004 #ifndef __ASSEMBLY__
25016 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_s
25018 const volatile uint32_t USERID : 8;
25019 const volatile uint32_t FLEXNOCID : 24;
25023 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_t;
25027 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_RESET 0x00014800
25029 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_OFST 0x4
25051 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_LSB 0
25053 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_MSB 6
25055 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_WIDTH 7
25057 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_SET_MSK 0x0000007f
25059 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_CLR_MSK 0xffffff80
25061 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_RESET 0x0
25063 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_GET(value) (((value) & 0x0000007f) >> 0)
25065 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_ATBID_SET(value) (((value) << 0) & 0x0000007f)
25067 #ifndef __ASSEMBLY__
25079 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_s
25081 volatile uint32_t ATBID : 7;
25086 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_t;
25090 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_RESET 0x00000000
25092 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_OFST 0x8
25114 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_LSB 0
25116 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_MSB 0
25118 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_WIDTH 1
25120 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_SET_MSK 0x00000001
25122 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_CLR_MSK 0xfffffffe
25124 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_RESET 0x0
25126 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_GET(value) (((value) & 0x00000001) >> 0)
25128 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_ATBEN_SET(value) (((value) << 0) & 0x00000001)
25130 #ifndef __ASSEMBLY__
25142 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_s
25144 volatile uint32_t ATBEN : 1;
25149 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_t;
25153 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_RESET 0x00000000
25155 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_OFST 0xc
25177 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_LSB 0
25179 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_MSB 4
25181 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_WIDTH 5
25183 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_SET_MSK 0x0000001f
25185 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_CLR_MSK 0xffffffe0
25187 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_RESET 0x0
25189 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
25191 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_SYNCPERIOD_SET(value) (((value) << 0) & 0x0000001f)
25193 #ifndef __ASSEMBLY__
25205 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_s
25207 volatile uint32_t SYNCPERIOD : 5;
25212 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_t;
25216 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_RESET 0x00000000
25218 #define ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_OFST 0x10
25220 #ifndef __ASSEMBLY__
25232 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_s
25234 volatile ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_COREID_t cs_obs_at_main_AtbEndPoint_Id_CoreId;
25235 volatile ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ID_REVISIONID_t cs_obs_at_main_AtbEndPoint_Id_RevisionId;
25236 volatile ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBID_t cs_obs_at_main_AtbEndPoint_AtbId;
25237 volatile ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_ATBEN_t cs_obs_at_main_AtbEndPoint_AtbEn;
25238 volatile ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_CS_OBS_AT_MAIN_ATBENDPOINT_SYNCPERIOD_t cs_obs_at_main_AtbEndPoint_SyncPeriod;
25239 volatile uint32_t _pad_0x14_0x80[27];
25243 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_t;
25245 struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_raw_s
25247 volatile uint32_t cs_obs_at_main_AtbEndPoint_Id_CoreId;
25248 volatile uint32_t cs_obs_at_main_AtbEndPoint_Id_RevisionId;
25249 volatile uint32_t cs_obs_at_main_AtbEndPoint_AtbId;
25250 volatile uint32_t cs_obs_at_main_AtbEndPoint_AtbEn;
25251 volatile uint32_t cs_obs_at_main_AtbEndPoint_SyncPeriod;
25252 volatile uint32_t _pad_0x14_0x80[27];
25256 typedef struct ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_raw_s ALT_MPFE_CS_OBS_AT_MAIN_ATBENDPT_raw_t;
25284 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
25286 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
25288 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
25290 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
25292 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
25294 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
25296 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
25298 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
25309 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
25311 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
25313 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
25315 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
25317 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
25319 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x89b4d7
25321 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
25323 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
25325 #ifndef __ASSEMBLY__
25337 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_s
25339 const volatile uint32_t CORETYPEID : 8;
25340 const volatile uint32_t CORECHECKSUM : 24;
25344 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_t;
25348 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x89b4d704
25350 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
25372 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
25374 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
25376 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
25378 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
25380 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
25382 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
25384 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
25386 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
25398 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
25400 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
25402 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
25404 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
25406 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
25408 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
25410 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
25412 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
25414 #ifndef __ASSEMBLY__
25426 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
25428 const volatile uint32_t USERID : 8;
25429 const volatile uint32_t FLEXNOCID : 24;
25433 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
25437 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
25439 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
25469 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
25471 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
25473 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
25475 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
25477 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
25479 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
25481 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
25483 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
25497 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
25499 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
25501 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
25503 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
25505 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
25507 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x0
25509 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
25511 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
25522 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
25524 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
25526 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
25528 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
25530 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
25532 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
25534 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
25536 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
25538 #ifndef __ASSEMBLY__
25550 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_s
25552 volatile uint32_t P0 : 2;
25554 volatile uint32_t P1 : 2;
25556 const volatile uint32_t MARK : 1;
25560 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_t;
25564 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000000
25566 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
25591 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
25593 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
25595 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
25597 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
25599 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
25601 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x1
25603 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
25605 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
25607 #ifndef __ASSEMBLY__
25619 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_s
25621 volatile uint32_t MODE : 2;
25626 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_t;
25630 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000001
25632 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
25656 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
25658 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 12
25660 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 13
25662 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00001fff
25664 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xffffe000
25666 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0xbfe
25668 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00001fff) >> 0)
25670 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00001fff)
25672 #ifndef __ASSEMBLY__
25684 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_s
25686 volatile uint32_t BANDWIDTH : 13;
25691 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
25695 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000bfe
25697 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
25722 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
25724 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
25726 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
25728 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
25730 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
25732 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
25734 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
25736 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
25738 #ifndef __ASSEMBLY__
25750 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_s
25752 volatile uint32_t SATURATION : 10;
25757 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_t;
25761 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
25763 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
25789 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
25791 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
25793 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
25795 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
25797 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
25799 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
25801 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
25803 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
25814 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
25816 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
25818 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
25820 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
25822 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
25824 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
25826 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
25828 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
25839 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
25841 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
25843 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
25845 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
25847 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
25849 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
25851 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
25853 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
25855 #ifndef __ASSEMBLY__
25867 struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_s
25869 volatile uint32_t SOCKETQOSEN : 1;
25870 volatile uint32_t EXTTHREN : 1;
25871 volatile uint32_t INTCLKEN : 1;
25876 typedef struct ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
25880 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
25882 #define ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
25884 #ifndef __ASSEMBLY__
25896 struct ALT_MPFE_CCU_MEM0_QOS_s
25898 volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_COREID_t ccu_mem0_I_main_QosGenerator_Id_CoreId;
25899 volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_ID_REVISIONID_t ccu_mem0_I_main_QosGenerator_Id_RevisionId;
25900 volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_PRIORITY_t ccu_mem0_I_main_QosGenerator_Priority;
25901 volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_MODE_t ccu_mem0_I_main_QosGenerator_Mode;
25902 volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_BANDWIDTH_t ccu_mem0_I_main_QosGenerator_Bandwidth;
25903 volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_SATURATION_t ccu_mem0_I_main_QosGenerator_Saturation;
25904 volatile ALT_MPFE_CCU_MEM0_QOS_CCU_MEM0_I_MAIN_QOSGENERATOR_EXTCONTROL_t ccu_mem0_I_main_QosGenerator_ExtControl;
25905 volatile uint32_t _pad_0x1c_0x80[25];
25909 typedef struct ALT_MPFE_CCU_MEM0_QOS_s ALT_MPFE_CCU_MEM0_QOS_t;
25911 struct ALT_MPFE_CCU_MEM0_QOS_raw_s
25913 volatile uint32_t ccu_mem0_I_main_QosGenerator_Id_CoreId;
25914 volatile uint32_t ccu_mem0_I_main_QosGenerator_Id_RevisionId;
25915 volatile uint32_t ccu_mem0_I_main_QosGenerator_Priority;
25916 volatile uint32_t ccu_mem0_I_main_QosGenerator_Mode;
25917 volatile uint32_t ccu_mem0_I_main_QosGenerator_Bandwidth;
25918 volatile uint32_t ccu_mem0_I_main_QosGenerator_Saturation;
25919 volatile uint32_t ccu_mem0_I_main_QosGenerator_ExtControl;
25920 volatile uint32_t _pad_0x1c_0x80[25];
25924 typedef struct ALT_MPFE_CCU_MEM0_QOS_raw_s ALT_MPFE_CCU_MEM0_QOS_raw_t;
25952 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
25954 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
25956 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
25958 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
25960 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
25962 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
25964 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
25966 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
25977 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
25979 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
25981 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
25983 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
25985 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
25987 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x38bac5
25989 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
25991 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
25993 #ifndef __ASSEMBLY__
26005 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_s
26007 const volatile uint32_t CORETYPEID : 8;
26008 const volatile uint32_t CORECHECKSUM : 24;
26012 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_t;
26016 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x38bac504
26018 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
26040 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
26042 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
26044 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
26046 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
26048 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
26050 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
26052 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
26054 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
26066 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
26068 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
26070 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
26072 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
26074 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
26076 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
26078 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
26080 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
26082 #ifndef __ASSEMBLY__
26094 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
26096 const volatile uint32_t USERID : 8;
26097 const volatile uint32_t FLEXNOCID : 24;
26101 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
26105 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
26107 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
26137 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
26139 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
26141 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
26143 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
26145 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
26147 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
26149 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
26151 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
26165 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
26167 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
26169 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
26171 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
26173 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
26175 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
26177 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
26179 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
26190 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
26192 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
26194 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
26196 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
26198 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
26200 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
26202 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
26204 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
26206 #ifndef __ASSEMBLY__
26218 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_s
26220 volatile uint32_t P0 : 2;
26222 volatile uint32_t P1 : 2;
26224 const volatile uint32_t MARK : 1;
26228 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_t;
26232 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
26234 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
26259 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
26261 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
26263 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
26265 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
26267 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
26269 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
26271 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
26273 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
26275 #ifndef __ASSEMBLY__
26287 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_s
26289 volatile uint32_t MODE : 2;
26294 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_t;
26298 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
26300 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
26324 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
26326 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 12
26328 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 13
26330 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00001fff
26332 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xffffe000
26334 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0xc80
26336 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00001fff) >> 0)
26338 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00001fff)
26340 #ifndef __ASSEMBLY__
26352 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_s
26354 volatile uint32_t BANDWIDTH : 13;
26359 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
26363 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000c80
26365 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
26390 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
26392 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
26394 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
26396 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
26398 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
26400 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
26402 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
26404 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
26406 #ifndef __ASSEMBLY__
26418 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_s
26420 volatile uint32_t SATURATION : 10;
26425 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_t;
26429 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
26431 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
26457 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
26459 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
26461 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
26463 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
26465 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
26467 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
26469 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
26471 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
26482 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
26484 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
26486 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
26488 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
26490 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
26492 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
26494 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
26496 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
26507 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
26509 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
26511 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
26513 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
26515 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
26517 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
26519 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
26521 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
26523 #ifndef __ASSEMBLY__
26535 struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_s
26537 volatile uint32_t SOCKETQOSEN : 1;
26538 volatile uint32_t EXTTHREN : 1;
26539 volatile uint32_t INTCLKEN : 1;
26544 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
26548 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
26550 #define ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
26552 #ifndef __ASSEMBLY__
26564 struct ALT_MPFE_F2SDR0_AXI128_QOS_s
26566 volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram0_axi128_I_main_QosGenerator_Id_CoreId;
26567 volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram0_axi128_I_main_QosGenerator_Id_RevisionId;
26568 volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram0_axi128_I_main_QosGenerator_Priority;
26569 volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram0_axi128_I_main_QosGenerator_Mode;
26570 volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram0_axi128_I_main_QosGenerator_Bandwidth;
26571 volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram0_axi128_I_main_QosGenerator_Saturation;
26572 volatile ALT_MPFE_F2SDR0_AXI128_QOS_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram0_axi128_I_main_QosGenerator_ExtControl;
26573 volatile uint32_t _pad_0x1c_0x80[25];
26577 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_s ALT_MPFE_F2SDR0_AXI128_QOS_t;
26579 struct ALT_MPFE_F2SDR0_AXI128_QOS_raw_s
26581 volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_Id_CoreId;
26582 volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_Id_RevisionId;
26583 volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_Priority;
26584 volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_Mode;
26585 volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_Bandwidth;
26586 volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_Saturation;
26587 volatile uint32_t fpga2sdram0_axi128_I_main_QosGenerator_ExtControl;
26588 volatile uint32_t _pad_0x1c_0x80[25];
26592 typedef struct ALT_MPFE_F2SDR0_AXI128_QOS_raw_s ALT_MPFE_F2SDR0_AXI128_QOS_raw_t;
26620 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
26622 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
26624 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
26626 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
26628 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
26630 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
26632 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
26634 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
26645 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
26647 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
26649 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
26651 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
26653 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
26655 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x90f627
26657 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
26659 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
26661 #ifndef __ASSEMBLY__
26673 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_s
26675 const volatile uint32_t CORETYPEID : 8;
26676 const volatile uint32_t CORECHECKSUM : 24;
26680 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_t;
26684 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x90f62704
26686 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
26708 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
26710 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
26712 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
26714 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
26716 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
26718 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
26720 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
26722 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
26734 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
26736 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
26738 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
26740 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
26742 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
26744 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
26746 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
26748 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
26750 #ifndef __ASSEMBLY__
26762 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
26764 const volatile uint32_t USERID : 8;
26765 const volatile uint32_t FLEXNOCID : 24;
26769 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
26773 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
26775 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
26805 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
26807 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
26809 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
26811 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
26813 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
26815 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
26817 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
26819 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
26833 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
26835 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
26837 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
26839 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
26841 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
26843 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
26845 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
26847 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
26858 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
26860 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
26862 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
26864 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
26866 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
26868 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
26870 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
26872 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
26874 #ifndef __ASSEMBLY__
26886 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_s
26888 volatile uint32_t P0 : 2;
26890 volatile uint32_t P1 : 2;
26892 const volatile uint32_t MARK : 1;
26896 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_t;
26900 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
26902 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
26927 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
26929 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
26931 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
26933 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
26935 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
26937 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
26939 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
26941 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
26943 #ifndef __ASSEMBLY__
26955 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_s
26957 volatile uint32_t MODE : 2;
26962 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_t;
26966 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
26968 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
26992 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
26994 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 10
26996 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 11
26998 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x000007ff
27000 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xfffff800
27002 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x280
27004 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x000007ff) >> 0)
27006 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x000007ff)
27008 #ifndef __ASSEMBLY__
27020 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_s
27022 volatile uint32_t BANDWIDTH : 11;
27027 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
27031 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000280
27033 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
27058 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
27060 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
27062 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
27064 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
27066 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
27068 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
27070 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
27072 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
27074 #ifndef __ASSEMBLY__
27086 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_s
27088 volatile uint32_t SATURATION : 10;
27093 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_t;
27097 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
27099 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
27125 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
27127 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
27129 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
27131 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
27133 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
27135 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
27137 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
27139 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
27150 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
27152 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
27154 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
27156 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
27158 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
27160 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
27162 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
27164 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
27175 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
27177 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
27179 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
27181 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
27183 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
27185 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
27187 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
27189 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
27191 #ifndef __ASSEMBLY__
27203 struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_s
27205 volatile uint32_t SOCKETQOSEN : 1;
27206 volatile uint32_t EXTTHREN : 1;
27207 volatile uint32_t INTCLKEN : 1;
27212 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
27216 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
27218 #define ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
27220 #ifndef __ASSEMBLY__
27232 struct ALT_MPFE_F2SDR0_AXI32_QOS_s
27234 volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram0_axi32_I_main_QosGenerator_Id_CoreId;
27235 volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram0_axi32_I_main_QosGenerator_Id_RevisionId;
27236 volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram0_axi32_I_main_QosGenerator_Priority;
27237 volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram0_axi32_I_main_QosGenerator_Mode;
27238 volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram0_axi32_I_main_QosGenerator_Bandwidth;
27239 volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram0_axi32_I_main_QosGenerator_Saturation;
27240 volatile ALT_MPFE_F2SDR0_AXI32_QOS_FPGA2SDRAM0_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram0_axi32_I_main_QosGenerator_ExtControl;
27241 volatile uint32_t _pad_0x1c_0x80[25];
27245 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_s ALT_MPFE_F2SDR0_AXI32_QOS_t;
27247 struct ALT_MPFE_F2SDR0_AXI32_QOS_raw_s
27249 volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_Id_CoreId;
27250 volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_Id_RevisionId;
27251 volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_Priority;
27252 volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_Mode;
27253 volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_Bandwidth;
27254 volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_Saturation;
27255 volatile uint32_t fpga2sdram0_axi32_I_main_QosGenerator_ExtControl;
27256 volatile uint32_t _pad_0x1c_0x80[25];
27260 typedef struct ALT_MPFE_F2SDR0_AXI32_QOS_raw_s ALT_MPFE_F2SDR0_AXI32_QOS_raw_t;
27288 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
27290 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
27292 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
27294 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
27296 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
27298 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
27300 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
27302 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
27313 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
27315 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
27317 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
27319 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
27321 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
27323 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0xb31375
27325 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
27327 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
27329 #ifndef __ASSEMBLY__
27341 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_s
27343 const volatile uint32_t CORETYPEID : 8;
27344 const volatile uint32_t CORECHECKSUM : 24;
27348 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_t;
27352 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0xb3137504
27354 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
27376 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
27378 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
27380 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
27382 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
27384 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
27386 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
27388 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
27390 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
27402 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
27404 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
27406 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
27408 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
27410 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
27412 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
27414 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
27416 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
27418 #ifndef __ASSEMBLY__
27430 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
27432 const volatile uint32_t USERID : 8;
27433 const volatile uint32_t FLEXNOCID : 24;
27437 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
27441 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
27443 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
27473 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
27475 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
27477 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
27479 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
27481 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
27483 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
27485 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
27487 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
27501 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
27503 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
27505 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
27507 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
27509 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
27511 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
27513 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
27515 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
27526 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
27528 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
27530 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
27532 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
27534 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
27536 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
27538 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
27540 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
27542 #ifndef __ASSEMBLY__
27554 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_s
27556 volatile uint32_t P0 : 2;
27558 volatile uint32_t P1 : 2;
27560 const volatile uint32_t MARK : 1;
27564 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_t;
27568 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
27570 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
27595 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
27597 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
27599 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
27601 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
27603 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
27605 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
27607 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
27609 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
27611 #ifndef __ASSEMBLY__
27623 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_s
27625 volatile uint32_t MODE : 2;
27630 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_t;
27634 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
27636 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
27660 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
27662 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 11
27664 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 12
27666 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00000fff
27668 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xfffff000
27670 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x780
27672 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00000fff) >> 0)
27674 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00000fff)
27676 #ifndef __ASSEMBLY__
27688 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_s
27690 volatile uint32_t BANDWIDTH : 12;
27695 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
27699 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000780
27701 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
27726 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
27728 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
27730 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
27732 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
27734 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
27736 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
27738 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
27740 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
27742 #ifndef __ASSEMBLY__
27754 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_s
27756 volatile uint32_t SATURATION : 10;
27761 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_t;
27765 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
27767 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
27793 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
27795 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
27797 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
27799 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
27801 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
27803 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
27805 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
27807 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
27818 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
27820 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
27822 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
27824 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
27826 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
27828 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
27830 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
27832 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
27843 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
27845 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
27847 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
27849 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
27851 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
27853 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
27855 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
27857 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
27859 #ifndef __ASSEMBLY__
27871 struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_s
27873 volatile uint32_t SOCKETQOSEN : 1;
27874 volatile uint32_t EXTTHREN : 1;
27875 volatile uint32_t INTCLKEN : 1;
27880 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
27884 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
27886 #define ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
27888 #ifndef __ASSEMBLY__
27900 struct ALT_MPFE_F2SDR0_AXI64_QOS_s
27902 volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram0_axi64_I_main_QosGenerator_Id_CoreId;
27903 volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram0_axi64_I_main_QosGenerator_Id_RevisionId;
27904 volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram0_axi64_I_main_QosGenerator_Priority;
27905 volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram0_axi64_I_main_QosGenerator_Mode;
27906 volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram0_axi64_I_main_QosGenerator_Bandwidth;
27907 volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram0_axi64_I_main_QosGenerator_Saturation;
27908 volatile ALT_MPFE_F2SDR0_AXI64_QOS_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram0_axi64_I_main_QosGenerator_ExtControl;
27909 volatile uint32_t _pad_0x1c_0x80[25];
27913 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_s ALT_MPFE_F2SDR0_AXI64_QOS_t;
27915 struct ALT_MPFE_F2SDR0_AXI64_QOS_raw_s
27917 volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_Id_CoreId;
27918 volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_Id_RevisionId;
27919 volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_Priority;
27920 volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_Mode;
27921 volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_Bandwidth;
27922 volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_Saturation;
27923 volatile uint32_t fpga2sdram0_axi64_I_main_QosGenerator_ExtControl;
27924 volatile uint32_t _pad_0x1c_0x80[25];
27928 typedef struct ALT_MPFE_F2SDR0_AXI64_QOS_raw_s ALT_MPFE_F2SDR0_AXI64_QOS_raw_t;
27956 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
27958 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
27960 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
27962 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
27964 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
27966 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
27968 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
27970 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
27981 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
27983 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
27985 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
27987 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
27989 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
27991 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x98409b
27993 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
27995 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
27997 #ifndef __ASSEMBLY__
28009 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_s
28011 const volatile uint32_t CORETYPEID : 8;
28012 const volatile uint32_t CORECHECKSUM : 24;
28016 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_t;
28020 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x98409b04
28022 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
28044 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
28046 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
28048 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
28050 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
28052 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
28054 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
28056 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
28058 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
28070 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
28072 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
28074 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
28076 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
28078 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
28080 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
28082 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
28084 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
28086 #ifndef __ASSEMBLY__
28098 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
28100 const volatile uint32_t USERID : 8;
28101 const volatile uint32_t FLEXNOCID : 24;
28105 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
28109 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
28111 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
28141 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
28143 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
28145 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
28147 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
28149 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
28151 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
28153 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
28155 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
28169 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
28171 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
28173 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
28175 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
28177 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
28179 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
28181 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
28183 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
28194 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
28196 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
28198 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
28200 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
28202 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
28204 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
28206 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
28208 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
28210 #ifndef __ASSEMBLY__
28222 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_s
28224 volatile uint32_t P0 : 2;
28226 volatile uint32_t P1 : 2;
28228 const volatile uint32_t MARK : 1;
28232 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_t;
28236 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
28238 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
28263 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
28265 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
28267 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
28269 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
28271 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
28273 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
28275 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
28277 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
28279 #ifndef __ASSEMBLY__
28291 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_s
28293 volatile uint32_t MODE : 2;
28298 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_t;
28302 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
28304 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
28328 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
28330 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 12
28332 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 13
28334 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00001fff
28336 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xffffe000
28338 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x780
28340 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00001fff) >> 0)
28342 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00001fff)
28344 #ifndef __ASSEMBLY__
28356 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_s
28358 volatile uint32_t BANDWIDTH : 13;
28363 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
28367 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000780
28369 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
28394 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
28396 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
28398 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
28400 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
28402 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
28404 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
28406 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
28408 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
28410 #ifndef __ASSEMBLY__
28422 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_s
28424 volatile uint32_t SATURATION : 10;
28429 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_t;
28433 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
28435 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
28461 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
28463 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
28465 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
28467 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
28469 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
28471 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
28473 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
28475 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
28486 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
28488 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
28490 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
28492 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
28494 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
28496 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
28498 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
28500 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
28511 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
28513 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
28515 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
28517 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
28519 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
28521 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
28523 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
28525 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
28527 #ifndef __ASSEMBLY__
28539 struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_s
28541 volatile uint32_t SOCKETQOSEN : 1;
28542 volatile uint32_t EXTTHREN : 1;
28543 volatile uint32_t INTCLKEN : 1;
28548 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
28552 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
28554 #define ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
28556 #ifndef __ASSEMBLY__
28568 struct ALT_MPFE_F2SDR1_AXI128_QOS_s
28570 volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram1_axi128_I_main_QosGenerator_Id_CoreId;
28571 volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram1_axi128_I_main_QosGenerator_Id_RevisionId;
28572 volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram1_axi128_I_main_QosGenerator_Priority;
28573 volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram1_axi128_I_main_QosGenerator_Mode;
28574 volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram1_axi128_I_main_QosGenerator_Bandwidth;
28575 volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram1_axi128_I_main_QosGenerator_Saturation;
28576 volatile ALT_MPFE_F2SDR1_AXI128_QOS_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram1_axi128_I_main_QosGenerator_ExtControl;
28577 volatile uint32_t _pad_0x1c_0x80[25];
28581 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_s ALT_MPFE_F2SDR1_AXI128_QOS_t;
28583 struct ALT_MPFE_F2SDR1_AXI128_QOS_raw_s
28585 volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_Id_CoreId;
28586 volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_Id_RevisionId;
28587 volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_Priority;
28588 volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_Mode;
28589 volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_Bandwidth;
28590 volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_Saturation;
28591 volatile uint32_t fpga2sdram1_axi128_I_main_QosGenerator_ExtControl;
28592 volatile uint32_t _pad_0x1c_0x80[25];
28596 typedef struct ALT_MPFE_F2SDR1_AXI128_QOS_raw_s ALT_MPFE_F2SDR1_AXI128_QOS_raw_t;
28624 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
28626 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
28628 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
28630 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
28632 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
28634 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
28636 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
28638 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
28649 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
28651 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
28653 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
28655 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
28657 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
28659 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x163445
28661 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
28663 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
28665 #ifndef __ASSEMBLY__
28677 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_s
28679 const volatile uint32_t CORETYPEID : 8;
28680 const volatile uint32_t CORECHECKSUM : 24;
28684 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_t;
28688 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x16344504
28690 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
28712 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
28714 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
28716 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
28718 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
28720 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
28722 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
28724 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
28726 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
28738 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
28740 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
28742 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
28744 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
28746 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
28748 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
28750 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
28752 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
28754 #ifndef __ASSEMBLY__
28766 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
28768 const volatile uint32_t USERID : 8;
28769 const volatile uint32_t FLEXNOCID : 24;
28773 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
28777 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
28779 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
28809 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
28811 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
28813 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
28815 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
28817 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
28819 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
28821 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
28823 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
28837 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
28839 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
28841 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
28843 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
28845 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
28847 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
28849 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
28851 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
28862 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
28864 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
28866 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
28868 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
28870 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
28872 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
28874 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
28876 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
28878 #ifndef __ASSEMBLY__
28890 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_s
28892 volatile uint32_t P0 : 2;
28894 volatile uint32_t P1 : 2;
28896 const volatile uint32_t MARK : 1;
28900 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_t;
28904 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
28906 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
28931 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
28933 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
28935 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
28937 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
28939 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
28941 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
28943 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
28945 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
28947 #ifndef __ASSEMBLY__
28959 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_s
28961 volatile uint32_t MODE : 2;
28966 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_t;
28970 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
28972 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
28996 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
28998 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 10
29000 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 11
29002 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x000007ff
29004 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xfffff800
29006 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x280
29008 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x000007ff) >> 0)
29010 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x000007ff)
29012 #ifndef __ASSEMBLY__
29024 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_s
29026 volatile uint32_t BANDWIDTH : 11;
29031 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
29035 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000280
29037 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
29062 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
29064 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
29066 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
29068 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
29070 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
29072 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
29074 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
29076 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
29078 #ifndef __ASSEMBLY__
29090 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_s
29092 volatile uint32_t SATURATION : 10;
29097 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_t;
29101 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
29103 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
29129 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
29131 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
29133 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
29135 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
29137 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
29139 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
29141 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
29143 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
29154 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
29156 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
29158 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
29160 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
29162 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
29164 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
29166 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
29168 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
29179 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
29181 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
29183 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
29185 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
29187 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
29189 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
29191 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
29193 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
29195 #ifndef __ASSEMBLY__
29207 struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_s
29209 volatile uint32_t SOCKETQOSEN : 1;
29210 volatile uint32_t EXTTHREN : 1;
29211 volatile uint32_t INTCLKEN : 1;
29216 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
29220 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
29222 #define ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
29224 #ifndef __ASSEMBLY__
29236 struct ALT_MPFE_F2SDR1_AXI32_QOS_s
29238 volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram1_axi32_I_main_QosGenerator_Id_CoreId;
29239 volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram1_axi32_I_main_QosGenerator_Id_RevisionId;
29240 volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram1_axi32_I_main_QosGenerator_Priority;
29241 volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram1_axi32_I_main_QosGenerator_Mode;
29242 volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram1_axi32_I_main_QosGenerator_Bandwidth;
29243 volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram1_axi32_I_main_QosGenerator_Saturation;
29244 volatile ALT_MPFE_F2SDR1_AXI32_QOS_FPGA2SDRAM1_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram1_axi32_I_main_QosGenerator_ExtControl;
29245 volatile uint32_t _pad_0x1c_0x80[25];
29249 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_s ALT_MPFE_F2SDR1_AXI32_QOS_t;
29251 struct ALT_MPFE_F2SDR1_AXI32_QOS_raw_s
29253 volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_Id_CoreId;
29254 volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_Id_RevisionId;
29255 volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_Priority;
29256 volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_Mode;
29257 volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_Bandwidth;
29258 volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_Saturation;
29259 volatile uint32_t fpga2sdram1_axi32_I_main_QosGenerator_ExtControl;
29260 volatile uint32_t _pad_0x1c_0x80[25];
29264 typedef struct ALT_MPFE_F2SDR1_AXI32_QOS_raw_s ALT_MPFE_F2SDR1_AXI32_QOS_raw_t;
29292 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
29294 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
29296 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
29298 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
29300 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
29302 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
29304 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
29306 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
29317 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
29319 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
29321 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
29323 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
29325 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
29327 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x41ac8b
29329 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
29331 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
29333 #ifndef __ASSEMBLY__
29345 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_s
29347 const volatile uint32_t CORETYPEID : 8;
29348 const volatile uint32_t CORECHECKSUM : 24;
29352 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_t;
29356 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x41ac8b04
29358 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
29380 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
29382 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
29384 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
29386 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
29388 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
29390 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
29392 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
29394 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
29406 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
29408 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
29410 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
29412 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
29414 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
29416 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
29418 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
29420 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
29422 #ifndef __ASSEMBLY__
29434 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
29436 const volatile uint32_t USERID : 8;
29437 const volatile uint32_t FLEXNOCID : 24;
29441 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
29445 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
29447 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
29477 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
29479 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
29481 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
29483 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
29485 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
29487 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
29489 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
29491 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
29505 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
29507 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
29509 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
29511 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
29513 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
29515 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
29517 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
29519 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
29530 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
29532 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
29534 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
29536 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
29538 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
29540 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
29542 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
29544 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
29546 #ifndef __ASSEMBLY__
29558 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_s
29560 volatile uint32_t P0 : 2;
29562 volatile uint32_t P1 : 2;
29564 const volatile uint32_t MARK : 1;
29568 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_t;
29572 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
29574 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
29599 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
29601 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
29603 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
29605 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
29607 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
29609 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
29611 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
29613 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
29615 #ifndef __ASSEMBLY__
29627 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_s
29629 volatile uint32_t MODE : 2;
29634 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_t;
29638 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
29640 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
29664 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
29666 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 11
29668 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 12
29670 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00000fff
29672 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xfffff000
29674 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x780
29676 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00000fff) >> 0)
29678 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00000fff)
29680 #ifndef __ASSEMBLY__
29692 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_s
29694 volatile uint32_t BANDWIDTH : 12;
29699 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
29703 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000780
29705 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
29730 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
29732 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
29734 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
29736 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
29738 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
29740 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
29742 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
29744 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
29746 #ifndef __ASSEMBLY__
29758 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_s
29760 volatile uint32_t SATURATION : 10;
29765 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_t;
29769 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
29771 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
29797 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
29799 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
29801 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
29803 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
29805 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
29807 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
29809 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
29811 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
29822 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
29824 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
29826 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
29828 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
29830 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
29832 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
29834 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
29836 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
29847 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
29849 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
29851 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
29853 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
29855 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
29857 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
29859 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
29861 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
29863 #ifndef __ASSEMBLY__
29875 struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_s
29877 volatile uint32_t SOCKETQOSEN : 1;
29878 volatile uint32_t EXTTHREN : 1;
29879 volatile uint32_t INTCLKEN : 1;
29884 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
29888 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
29890 #define ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
29892 #ifndef __ASSEMBLY__
29904 struct ALT_MPFE_F2SDR1_AXI64_QOS_s
29906 volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram1_axi64_I_main_QosGenerator_Id_CoreId;
29907 volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram1_axi64_I_main_QosGenerator_Id_RevisionId;
29908 volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram1_axi64_I_main_QosGenerator_Priority;
29909 volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram1_axi64_I_main_QosGenerator_Mode;
29910 volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram1_axi64_I_main_QosGenerator_Bandwidth;
29911 volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram1_axi64_I_main_QosGenerator_Saturation;
29912 volatile ALT_MPFE_F2SDR1_AXI64_QOS_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram1_axi64_I_main_QosGenerator_ExtControl;
29913 volatile uint32_t _pad_0x1c_0x80[25];
29917 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_s ALT_MPFE_F2SDR1_AXI64_QOS_t;
29919 struct ALT_MPFE_F2SDR1_AXI64_QOS_raw_s
29921 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Id_CoreId;
29922 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Id_RevisionId;
29923 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Priority;
29924 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Mode;
29925 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Bandwidth;
29926 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_Saturation;
29927 volatile uint32_t fpga2sdram1_axi64_I_main_QosGenerator_ExtControl;
29928 volatile uint32_t _pad_0x1c_0x80[25];
29932 typedef struct ALT_MPFE_F2SDR1_AXI64_QOS_raw_s ALT_MPFE_F2SDR1_AXI64_QOS_raw_t;
29960 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
29962 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
29964 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
29966 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
29968 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
29970 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
29972 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
29974 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
29985 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
29987 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
29989 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
29991 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
29993 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
29995 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0x150ab7
29997 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
29999 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
30001 #ifndef __ASSEMBLY__
30013 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_s
30015 const volatile uint32_t CORETYPEID : 8;
30016 const volatile uint32_t CORECHECKSUM : 24;
30020 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_t;
30024 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0x150ab704
30026 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
30048 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
30050 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
30052 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
30054 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
30056 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
30058 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
30060 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
30062 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
30074 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
30076 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
30078 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
30080 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
30082 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
30084 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
30086 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
30088 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
30090 #ifndef __ASSEMBLY__
30102 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
30104 const volatile uint32_t USERID : 8;
30105 const volatile uint32_t FLEXNOCID : 24;
30109 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
30113 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
30115 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
30145 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
30147 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
30149 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
30151 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
30153 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
30155 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
30157 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
30159 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
30173 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
30175 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
30177 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
30179 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
30181 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
30183 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
30185 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
30187 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
30198 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
30200 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
30202 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
30204 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
30206 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
30208 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
30210 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
30212 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
30214 #ifndef __ASSEMBLY__
30226 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_s
30228 volatile uint32_t P0 : 2;
30230 volatile uint32_t P1 : 2;
30232 const volatile uint32_t MARK : 1;
30236 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_t;
30240 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
30242 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
30267 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
30269 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
30271 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
30273 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
30275 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
30277 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
30279 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
30281 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
30283 #ifndef __ASSEMBLY__
30295 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_s
30297 volatile uint32_t MODE : 2;
30302 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_t;
30306 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
30308 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
30332 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
30334 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 12
30336 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 13
30338 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00001fff
30340 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xffffe000
30342 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0xc80
30344 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00001fff) >> 0)
30346 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00001fff)
30348 #ifndef __ASSEMBLY__
30360 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_s
30362 volatile uint32_t BANDWIDTH : 13;
30367 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
30371 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000c80
30373 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
30398 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
30400 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
30402 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
30404 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
30406 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
30408 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
30410 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
30412 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
30414 #ifndef __ASSEMBLY__
30426 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_s
30428 volatile uint32_t SATURATION : 10;
30433 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_t;
30437 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
30439 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
30465 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
30467 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
30469 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
30471 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
30473 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
30475 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
30477 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
30479 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
30490 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
30492 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
30494 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
30496 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
30498 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
30500 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
30502 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
30504 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
30515 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
30517 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
30519 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
30521 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
30523 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
30525 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
30527 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
30529 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
30531 #ifndef __ASSEMBLY__
30543 struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_s
30545 volatile uint32_t SOCKETQOSEN : 1;
30546 volatile uint32_t EXTTHREN : 1;
30547 volatile uint32_t INTCLKEN : 1;
30552 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
30556 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
30558 #define ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
30560 #ifndef __ASSEMBLY__
30572 struct ALT_MPFE_F2SDR2_AXI128_QOS_s
30574 volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram2_axi128_I_main_QosGenerator_Id_CoreId;
30575 volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram2_axi128_I_main_QosGenerator_Id_RevisionId;
30576 volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram2_axi128_I_main_QosGenerator_Priority;
30577 volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram2_axi128_I_main_QosGenerator_Mode;
30578 volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram2_axi128_I_main_QosGenerator_Bandwidth;
30579 volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram2_axi128_I_main_QosGenerator_Saturation;
30580 volatile ALT_MPFE_F2SDR2_AXI128_QOS_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram2_axi128_I_main_QosGenerator_ExtControl;
30581 volatile uint32_t _pad_0x1c_0x80[25];
30585 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_s ALT_MPFE_F2SDR2_AXI128_QOS_t;
30587 struct ALT_MPFE_F2SDR2_AXI128_QOS_raw_s
30589 volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_Id_CoreId;
30590 volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_Id_RevisionId;
30591 volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_Priority;
30592 volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_Mode;
30593 volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_Bandwidth;
30594 volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_Saturation;
30595 volatile uint32_t fpga2sdram2_axi128_I_main_QosGenerator_ExtControl;
30596 volatile uint32_t _pad_0x1c_0x80[25];
30600 typedef struct ALT_MPFE_F2SDR2_AXI128_QOS_raw_s ALT_MPFE_F2SDR2_AXI128_QOS_raw_t;
30628 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
30630 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
30632 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
30634 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
30636 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
30638 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
30640 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
30642 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
30653 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
30655 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
30657 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
30659 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
30661 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
30663 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0xecc09f
30665 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
30667 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
30669 #ifndef __ASSEMBLY__
30681 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_s
30683 const volatile uint32_t CORETYPEID : 8;
30684 const volatile uint32_t CORECHECKSUM : 24;
30688 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_t;
30692 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0xecc09f04
30694 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
30716 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
30718 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
30720 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
30722 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
30724 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
30726 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
30728 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
30730 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
30742 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
30744 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
30746 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
30748 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
30750 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
30752 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
30754 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
30756 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
30758 #ifndef __ASSEMBLY__
30770 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
30772 const volatile uint32_t USERID : 8;
30773 const volatile uint32_t FLEXNOCID : 24;
30777 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
30781 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
30783 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
30813 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
30815 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
30817 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
30819 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
30821 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
30823 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
30825 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
30827 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
30841 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
30843 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
30845 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
30847 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
30849 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
30851 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
30853 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
30855 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
30866 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
30868 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
30870 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
30872 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
30874 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
30876 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
30878 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
30880 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
30882 #ifndef __ASSEMBLY__
30894 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_s
30896 volatile uint32_t P0 : 2;
30898 volatile uint32_t P1 : 2;
30900 const volatile uint32_t MARK : 1;
30904 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_t;
30908 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
30910 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
30935 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
30937 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
30939 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
30941 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
30943 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
30945 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
30947 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
30949 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
30951 #ifndef __ASSEMBLY__
30963 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_s
30965 volatile uint32_t MODE : 2;
30970 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_t;
30974 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
30976 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
31000 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
31002 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 10
31004 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 11
31006 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x000007ff
31008 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xfffff800
31010 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x280
31012 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x000007ff) >> 0)
31014 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x000007ff)
31016 #ifndef __ASSEMBLY__
31028 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_s
31030 volatile uint32_t BANDWIDTH : 11;
31035 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
31039 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000280
31041 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
31066 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
31068 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
31070 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
31072 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
31074 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
31076 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
31078 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
31080 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
31082 #ifndef __ASSEMBLY__
31094 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_s
31096 volatile uint32_t SATURATION : 10;
31101 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_t;
31105 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
31107 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
31133 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
31135 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
31137 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
31139 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
31141 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
31143 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
31145 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
31147 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
31158 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
31160 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
31162 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
31164 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
31166 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
31168 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
31170 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
31172 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
31183 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
31185 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
31187 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
31189 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
31191 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
31193 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
31195 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
31197 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
31199 #ifndef __ASSEMBLY__
31211 struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_s
31213 volatile uint32_t SOCKETQOSEN : 1;
31214 volatile uint32_t EXTTHREN : 1;
31215 volatile uint32_t INTCLKEN : 1;
31220 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
31224 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
31226 #define ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
31228 #ifndef __ASSEMBLY__
31240 struct ALT_MPFE_F2SDR2_AXI32_QOS_s
31242 volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram2_axi32_I_main_QosGenerator_Id_CoreId;
31243 volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram2_axi32_I_main_QosGenerator_Id_RevisionId;
31244 volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram2_axi32_I_main_QosGenerator_Priority;
31245 volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram2_axi32_I_main_QosGenerator_Mode;
31246 volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram2_axi32_I_main_QosGenerator_Bandwidth;
31247 volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram2_axi32_I_main_QosGenerator_Saturation;
31248 volatile ALT_MPFE_F2SDR2_AXI32_QOS_FPGA2SDRAM2_AXI32_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram2_axi32_I_main_QosGenerator_ExtControl;
31249 volatile uint32_t _pad_0x1c_0x80[25];
31253 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_s ALT_MPFE_F2SDR2_AXI32_QOS_t;
31255 struct ALT_MPFE_F2SDR2_AXI32_QOS_raw_s
31257 volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_Id_CoreId;
31258 volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_Id_RevisionId;
31259 volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_Priority;
31260 volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_Mode;
31261 volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_Bandwidth;
31262 volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_Saturation;
31263 volatile uint32_t fpga2sdram2_axi32_I_main_QosGenerator_ExtControl;
31264 volatile uint32_t _pad_0x1c_0x80[25];
31268 typedef struct ALT_MPFE_F2SDR2_AXI32_QOS_raw_s ALT_MPFE_F2SDR2_AXI32_QOS_raw_t;
31296 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_LSB 0
31298 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_MSB 7
31300 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_WIDTH 8
31302 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
31304 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
31306 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_RESET 0x4
31308 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
31310 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
31321 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_LSB 8
31323 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_MSB 31
31325 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_WIDTH 24
31327 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
31329 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
31331 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_RESET 0xe58cca
31333 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
31335 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
31337 #ifndef __ASSEMBLY__
31349 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_s
31351 const volatile uint32_t CORETYPEID : 8;
31352 const volatile uint32_t CORECHECKSUM : 24;
31356 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_t;
31360 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_RESET 0xe58cca04
31362 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_OFST 0x0
31384 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_LSB 0
31386 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_MSB 7
31388 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_WIDTH 8
31390 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET_MSK 0x000000ff
31392 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
31394 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_RESET 0x0
31396 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
31398 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
31410 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_LSB 8
31412 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_MSB 31
31414 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_WIDTH 24
31416 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
31418 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
31420 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_RESET 0x148
31422 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
31424 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
31426 #ifndef __ASSEMBLY__
31438 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_s
31440 const volatile uint32_t USERID : 8;
31441 const volatile uint32_t FLEXNOCID : 24;
31445 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_t;
31449 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_RESET 0x00014800
31451 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_OFST 0x4
31481 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_LSB 0
31483 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_MSB 1
31485 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_WIDTH 2
31487 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET_MSK 0x00000003
31489 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_CLR_MSK 0xfffffffc
31491 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_RESET 0x0
31493 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_GET(value) (((value) & 0x00000003) >> 0)
31495 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P0_SET(value) (((value) << 0) & 0x00000003)
31509 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_LSB 8
31511 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_MSB 9
31513 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_WIDTH 2
31515 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET_MSK 0x00000300
31517 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_CLR_MSK 0xfffffcff
31519 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_RESET 0x2
31521 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_GET(value) (((value) & 0x00000300) >> 8)
31523 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_P1_SET(value) (((value) << 8) & 0x00000300)
31534 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_LSB 31
31536 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_MSB 31
31538 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_WIDTH 1
31540 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET_MSK 0x80000000
31542 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_CLR_MSK 0x7fffffff
31544 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_RESET 0x1
31546 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_GET(value) (((value) & 0x80000000) >> 31)
31548 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_MARK_SET(value) (((value) << 31) & 0x80000000)
31550 #ifndef __ASSEMBLY__
31562 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_s
31564 volatile uint32_t P0 : 2;
31566 volatile uint32_t P1 : 2;
31568 const volatile uint32_t MARK : 1;
31572 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_t;
31576 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_RESET 0x80000200
31578 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_OFST 0x8
31603 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_LSB 0
31605 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_MSB 1
31607 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_WIDTH 2
31609 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_SET_MSK 0x00000003
31611 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_CLR_MSK 0xfffffffc
31613 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_RESET 0x3
31615 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_GET(value) (((value) & 0x00000003) >> 0)
31617 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_MODE_SET(value) (((value) << 0) & 0x00000003)
31619 #ifndef __ASSEMBLY__
31631 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_s
31633 volatile uint32_t MODE : 2;
31638 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_t;
31642 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_RESET 0x00000003
31644 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_OFST 0xc
31668 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_LSB 0
31670 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MSB 11
31672 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_WIDTH 12
31674 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET_MSK 0x00000fff
31676 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_CLR_MSK 0xfffff000
31678 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_RESET 0x780
31680 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_GET(value) (((value) & 0x00000fff) >> 0)
31682 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00000fff)
31684 #ifndef __ASSEMBLY__
31696 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_s
31698 volatile uint32_t BANDWIDTH : 12;
31703 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_t;
31707 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_RESET 0x00000780
31709 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_OFST 0x10
31734 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_LSB 0
31736 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_MSB 9
31738 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_WIDTH 10
31740 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET_MSK 0x000003ff
31742 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_CLR_MSK 0xfffffc00
31744 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_RESET 0x8
31746 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
31748 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
31750 #ifndef __ASSEMBLY__
31762 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_s
31764 volatile uint32_t SATURATION : 10;
31769 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_t;
31773 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_RESET 0x00000008
31775 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_OFST 0x14
31801 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_LSB 0
31803 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MSB 0
31805 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_WIDTH 1
31807 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET_MSK 0x00000001
31809 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_CLR_MSK 0xfffffffe
31811 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_RESET 0x0
31813 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
31815 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
31826 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_LSB 1
31828 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_MSB 1
31830 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_WIDTH 1
31832 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET_MSK 0x00000002
31834 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_CLR_MSK 0xfffffffd
31836 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_RESET 0x0
31838 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
31840 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
31851 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_LSB 2
31853 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_MSB 2
31855 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_WIDTH 1
31857 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET_MSK 0x00000004
31859 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_CLR_MSK 0xfffffffb
31861 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_RESET 0x0
31863 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
31865 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
31867 #ifndef __ASSEMBLY__
31879 struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_s
31881 volatile uint32_t SOCKETQOSEN : 1;
31882 volatile uint32_t EXTTHREN : 1;
31883 volatile uint32_t INTCLKEN : 1;
31888 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_s ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_t;
31892 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_RESET 0x00000000
31894 #define ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_OFST 0x18
31896 #ifndef __ASSEMBLY__
31908 struct ALT_MPFE_F2SDR2_AXI64_QOS_s
31910 volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_COREID_t fpga2sdram2_axi64_I_main_QosGenerator_Id_CoreId;
31911 volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_ID_REVISIONID_t fpga2sdram2_axi64_I_main_QosGenerator_Id_RevisionId;
31912 volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_PRIORITY_t fpga2sdram2_axi64_I_main_QosGenerator_Priority;
31913 volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_MODE_t fpga2sdram2_axi64_I_main_QosGenerator_Mode;
31914 volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_BANDWIDTH_t fpga2sdram2_axi64_I_main_QosGenerator_Bandwidth;
31915 volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_SATURATION_t fpga2sdram2_axi64_I_main_QosGenerator_Saturation;
31916 volatile ALT_MPFE_F2SDR2_AXI64_QOS_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR_EXTCONTROL_t fpga2sdram2_axi64_I_main_QosGenerator_ExtControl;
31917 volatile uint32_t _pad_0x1c_0x80[25];
31921 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_s ALT_MPFE_F2SDR2_AXI64_QOS_t;
31923 struct ALT_MPFE_F2SDR2_AXI64_QOS_raw_s
31925 volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_Id_CoreId;
31926 volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_Id_RevisionId;
31927 volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_Priority;
31928 volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_Mode;
31929 volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_Bandwidth;
31930 volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_Saturation;
31931 volatile uint32_t fpga2sdram2_axi64_I_main_QosGenerator_ExtControl;
31932 volatile uint32_t _pad_0x1c_0x80[25];
31936 typedef struct ALT_MPFE_F2SDR2_AXI64_QOS_raw_s ALT_MPFE_F2SDR2_AXI64_QOS_raw_t;
31964 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_LSB 0
31966 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_MSB 7
31968 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_WIDTH 8
31970 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_SET_MSK 0x000000ff
31972 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_CLR_MSK 0xffffff00
31974 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_RESET 0xb
31976 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_GET(value) (((value) & 0x000000ff) >> 0)
31978 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORETYPEID_SET(value) (((value) << 0) & 0x000000ff)
31989 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_LSB 8
31991 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_MSB 31
31993 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_WIDTH 24
31995 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_SET_MSK 0xffffff00
31997 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_CLR_MSK 0x000000ff
31999 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_RESET 0x9885cb
32001 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
32003 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_CORECHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
32005 #ifndef __ASSEMBLY__
32017 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_s
32019 const volatile uint32_t CORETYPEID : 8;
32020 const volatile uint32_t CORECHECKSUM : 24;
32024 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_t;
32028 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_RESET 0x9885cb0b
32030 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_OFST 0x0
32052 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_LSB 0
32054 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_MSB 7
32056 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_WIDTH 8
32058 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_SET_MSK 0x000000ff
32060 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_CLR_MSK 0xffffff00
32062 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_RESET 0x0
32064 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_GET(value) (((value) & 0x000000ff) >> 0)
32066 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_USERID_SET(value) (((value) << 0) & 0x000000ff)
32078 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_LSB 8
32080 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_MSB 31
32082 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_WIDTH 24
32084 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_SET_MSK 0xffffff00
32086 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_CLR_MSK 0x000000ff
32088 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_RESET 0x148
32090 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
32092 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
32094 #ifndef __ASSEMBLY__
32106 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_s
32108 const volatile uint32_t USERID : 8;
32109 const volatile uint32_t FLEXNOCID : 24;
32113 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_t;
32117 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_RESET 0x00014800
32119 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_OFST 0x4
32141 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_LSB 0
32143 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_MSB 0
32145 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_WIDTH 1
32147 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_SET_MSK 0x00000001
32149 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_CLR_MSK 0xfffffffe
32151 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_RESET 0x0
32153 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_GET(value) (((value) & 0x00000001) >> 0)
32155 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_FAULTEN_SET(value) (((value) << 0) & 0x00000001)
32157 #ifndef __ASSEMBLY__
32169 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_s
32171 volatile uint32_t FAULTEN : 1;
32176 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_t;
32180 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_RESET 0x00000000
32182 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_OFST 0x8
32204 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_LSB 0
32206 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_MSB 0
32208 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_WIDTH 1
32210 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_SET_MSK 0x00000001
32212 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_CLR_MSK 0xfffffffe
32214 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_RESET 0x0
32216 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_GET(value) (((value) & 0x00000001) >> 0)
32218 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_FAULTSTATUS_SET(value) (((value) << 0) & 0x00000001)
32220 #ifndef __ASSEMBLY__
32232 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_s
32234 const volatile uint32_t FAULTSTATUS : 1;
32239 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_t;
32243 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_RESET 0x00000000
32245 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_OFST 0xc
32278 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_LSB 0
32280 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_MSB 0
32282 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_WIDTH 1
32284 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_SET_MSK 0x00000001
32286 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_CLR_MSK 0xfffffffe
32288 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_RESET 0x0
32290 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_GET(value) (((value) & 0x00000001) >> 0)
32292 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLE_EN_SET(value) (((value) << 0) & 0x00000001)
32303 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_LSB 1
32305 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_MSB 1
32307 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_WIDTH 1
32309 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_SET_MSK 0x00000002
32311 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_CLR_MSK 0xfffffffd
32313 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_RESET 0x0
32315 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_GET(value) (((value) & 0x00000002) >> 1)
32317 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_IDLEACK_EN_SET(value) (((value) << 1) & 0x00000002)
32328 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_LSB 2
32330 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_MSB 2
32332 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_WIDTH 1
32334 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_SET_MSK 0x00000004
32336 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_CLR_MSK 0xfffffffb
32338 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_RESET 0x0
32340 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_GET(value) (((value) & 0x00000004) >> 2)
32342 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_CMD_IDLE_EN_SET(value) (((value) << 2) & 0x00000004)
32353 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_LSB 3
32355 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_MSB 3
32357 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_WIDTH 1
32359 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_SET_MSK 0x00000008
32361 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_CLR_MSK 0xfffffff7
32363 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_RESET 0x0
32365 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_GET(value) (((value) & 0x00000008) >> 3)
32367 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM0_RESP_IDLE_EN_SET(value) (((value) << 3) & 0x00000008)
32378 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_LSB 4
32380 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_MSB 4
32382 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_WIDTH 1
32384 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_SET_MSK 0x00000010
32386 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_CLR_MSK 0xffffffef
32388 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_RESET 0x0
32390 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_GET(value) (((value) & 0x00000010) >> 4)
32392 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLE_EN_SET(value) (((value) << 4) & 0x00000010)
32403 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_LSB 5
32405 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_MSB 5
32407 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_WIDTH 1
32409 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_SET_MSK 0x00000020
32411 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_CLR_MSK 0xffffffdf
32413 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_RESET 0x0
32415 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_GET(value) (((value) & 0x00000020) >> 5)
32417 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_IDLEACK_EN_SET(value) (((value) << 5) & 0x00000020)
32428 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_LSB 6
32430 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_MSB 6
32432 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_WIDTH 1
32434 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_SET_MSK 0x00000040
32436 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_CLR_MSK 0xffffffbf
32438 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_RESET 0x0
32440 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_GET(value) (((value) & 0x00000040) >> 6)
32442 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_CMD_IDLE_EN_SET(value) (((value) << 6) & 0x00000040)
32453 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_LSB 7
32455 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_MSB 7
32457 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_WIDTH 1
32459 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_SET_MSK 0x00000080
32461 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_CLR_MSK 0xffffff7f
32463 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_RESET 0x0
32465 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_GET(value) (((value) & 0x00000080) >> 7)
32467 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM1_RESP_IDLE_EN_SET(value) (((value) << 7) & 0x00000080)
32478 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_LSB 8
32480 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_MSB 8
32482 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_WIDTH 1
32484 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_SET_MSK 0x00000100
32486 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_CLR_MSK 0xfffffeff
32488 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_RESET 0x0
32490 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_GET(value) (((value) & 0x00000100) >> 8)
32492 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLE_EN_SET(value) (((value) << 8) & 0x00000100)
32503 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_LSB 9
32505 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_MSB 9
32507 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_WIDTH 1
32509 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_SET_MSK 0x00000200
32511 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_CLR_MSK 0xfffffdff
32513 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_RESET 0x0
32515 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_GET(value) (((value) & 0x00000200) >> 9)
32517 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_IDLEACK_EN_SET(value) (((value) << 9) & 0x00000200)
32528 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_LSB 10
32530 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_MSB 10
32532 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_WIDTH 1
32534 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_SET_MSK 0x00000400
32536 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_CLR_MSK 0xfffffbff
32538 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_RESET 0x0
32540 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_GET(value) (((value) & 0x00000400) >> 10)
32542 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_CMD_IDLE_EN_SET(value) (((value) << 10) & 0x00000400)
32553 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_LSB 11
32555 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_MSB 11
32557 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_WIDTH 1
32559 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_SET_MSK 0x00000800
32561 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_CLR_MSK 0xfffff7ff
32563 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_RESET 0x0
32565 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_GET(value) (((value) & 0x00000800) >> 11)
32567 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_FPGA2SDRAM2_RESP_IDLE_EN_SET(value) (((value) << 11) & 0x00000800)
32569 #ifndef __ASSEMBLY__
32581 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_s
32583 volatile uint32_t FPGA2SDRAM0_IDLE_EN : 1;
32584 volatile uint32_t FPGA2SDRAM0_IDLEACK_EN : 1;
32585 volatile uint32_t FPGA2SDRAM0_CMD_IDLE_EN : 1;
32586 volatile uint32_t FPGA2SDRAM0_RESP_IDLE_EN : 1;
32587 volatile uint32_t FPGA2SDRAM1_IDLE_EN : 1;
32588 volatile uint32_t FPGA2SDRAM1_IDLEACK_EN : 1;
32589 volatile uint32_t FPGA2SDRAM1_CMD_IDLE_EN : 1;
32590 volatile uint32_t FPGA2SDRAM1_RESP_IDLE_EN : 1;
32591 volatile uint32_t FPGA2SDRAM2_IDLE_EN : 1;
32592 volatile uint32_t FPGA2SDRAM2_IDLEACK_EN : 1;
32593 volatile uint32_t FPGA2SDRAM2_CMD_IDLE_EN : 1;
32594 volatile uint32_t FPGA2SDRAM2_RESP_IDLE_EN : 1;
32599 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_t;
32603 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_RESET 0x00000000
32605 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_OFST 0x10
32638 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_LSB 0
32640 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_MSB 0
32642 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_WIDTH 1
32644 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_SET_MSK 0x00000001
32646 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_CLR_MSK 0xfffffffe
32648 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_RESET 0x0
32650 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_GET(value) (((value) & 0x00000001) >> 0)
32652 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLE_STATUS_SET(value) (((value) << 0) & 0x00000001)
32663 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_LSB 1
32665 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_MSB 1
32667 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_WIDTH 1
32669 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_SET_MSK 0x00000002
32671 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_CLR_MSK 0xfffffffd
32673 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_RESET 0x0
32675 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_GET(value) (((value) & 0x00000002) >> 1)
32677 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_IDLEACK_STATUS_SET(value) (((value) << 1) & 0x00000002)
32688 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_LSB 2
32690 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_MSB 2
32692 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_WIDTH 1
32694 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_SET_MSK 0x00000004
32696 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_CLR_MSK 0xfffffffb
32698 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_RESET 0x0
32700 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_GET(value) (((value) & 0x00000004) >> 2)
32702 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_CMD_IDLE_STATUS_SET(value) (((value) << 2) & 0x00000004)
32713 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_LSB 3
32715 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_MSB 3
32717 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_WIDTH 1
32719 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_SET_MSK 0x00000008
32721 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_CLR_MSK 0xfffffff7
32723 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_RESET 0x0
32725 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_GET(value) (((value) & 0x00000008) >> 3)
32727 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM0_RESP_IDLE_STATUS_SET(value) (((value) << 3) & 0x00000008)
32738 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_LSB 4
32740 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_MSB 4
32742 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_WIDTH 1
32744 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_SET_MSK 0x00000010
32746 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_CLR_MSK 0xffffffef
32748 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_RESET 0x0
32750 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_GET(value) (((value) & 0x00000010) >> 4)
32752 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLE_STATUS_SET(value) (((value) << 4) & 0x00000010)
32763 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_LSB 5
32765 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_MSB 5
32767 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_WIDTH 1
32769 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_SET_MSK 0x00000020
32771 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_CLR_MSK 0xffffffdf
32773 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_RESET 0x0
32775 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_GET(value) (((value) & 0x00000020) >> 5)
32777 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_IDLEACK_STATUS_SET(value) (((value) << 5) & 0x00000020)
32788 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_LSB 6
32790 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_MSB 6
32792 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_WIDTH 1
32794 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_SET_MSK 0x00000040
32796 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_CLR_MSK 0xffffffbf
32798 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_RESET 0x0
32800 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_GET(value) (((value) & 0x00000040) >> 6)
32802 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_CMD_IDLE_STATUS_SET(value) (((value) << 6) & 0x00000040)
32813 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_LSB 7
32815 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_MSB 7
32817 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_WIDTH 1
32819 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_SET_MSK 0x00000080
32821 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_CLR_MSK 0xffffff7f
32823 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_RESET 0x0
32825 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_GET(value) (((value) & 0x00000080) >> 7)
32827 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM1_RESP_IDLE_STATUS_SET(value) (((value) << 7) & 0x00000080)
32838 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_LSB 8
32840 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_MSB 8
32842 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_WIDTH 1
32844 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_SET_MSK 0x00000100
32846 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_CLR_MSK 0xfffffeff
32848 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_RESET 0x0
32850 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_GET(value) (((value) & 0x00000100) >> 8)
32852 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLE_STATUS_SET(value) (((value) << 8) & 0x00000100)
32863 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_LSB 9
32865 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_MSB 9
32867 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_WIDTH 1
32869 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_SET_MSK 0x00000200
32871 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_CLR_MSK 0xfffffdff
32873 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_RESET 0x0
32875 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_GET(value) (((value) & 0x00000200) >> 9)
32877 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_IDLEACK_STATUS_SET(value) (((value) << 9) & 0x00000200)
32888 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_LSB 10
32890 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_MSB 10
32892 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_WIDTH 1
32894 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_SET_MSK 0x00000400
32896 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_CLR_MSK 0xfffffbff
32898 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_RESET 0x0
32900 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_GET(value) (((value) & 0x00000400) >> 10)
32902 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_CMD_IDLE_STATUS_SET(value) (((value) << 10) & 0x00000400)
32913 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_LSB 11
32915 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_MSB 11
32917 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_WIDTH 1
32919 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_SET_MSK 0x00000800
32921 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_CLR_MSK 0xfffff7ff
32923 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_RESET 0x0
32925 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_GET(value) (((value) & 0x00000800) >> 11)
32927 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_FPGA2SDRAM2_RESP_IDLE_STATUS_SET(value) (((value) << 11) & 0x00000800)
32929 #ifndef __ASSEMBLY__
32941 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_s
32943 const volatile uint32_t FPGA2SDRAM0_IDLE_STATUS : 1;
32944 const volatile uint32_t FPGA2SDRAM0_IDLEACK_STATUS : 1;
32945 const volatile uint32_t FPGA2SDRAM0_CMD_IDLE_STATUS : 1;
32946 const volatile uint32_t FPGA2SDRAM0_RESP_IDLE_STATUS : 1;
32947 const volatile uint32_t FPGA2SDRAM1_IDLE_STATUS : 1;
32948 const volatile uint32_t FPGA2SDRAM1_IDLEACK_STATUS : 1;
32949 const volatile uint32_t FPGA2SDRAM1_CMD_IDLE_STATUS : 1;
32950 const volatile uint32_t FPGA2SDRAM1_RESP_IDLE_STATUS : 1;
32951 const volatile uint32_t FPGA2SDRAM2_IDLE_STATUS : 1;
32952 const volatile uint32_t FPGA2SDRAM2_IDLEACK_STATUS : 1;
32953 const volatile uint32_t FPGA2SDRAM2_CMD_IDLE_STATUS : 1;
32954 const volatile uint32_t FPGA2SDRAM2_RESP_IDLE_STATUS : 1;
32959 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_t;
32963 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_RESET 0x00000000
32965 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_OFST 0x14
32995 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_LSB 0
32997 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_MSB 0
32999 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_WIDTH 1
33001 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_SET_MSK 0x00000001
33003 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_CLR_MSK 0xfffffffe
33005 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_RESET 0x0
33007 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_GET(value) (((value) & 0x00000001) >> 0)
33009 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_IDLEREQ_SET_SET(value) (((value) << 0) & 0x00000001)
33020 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_LSB 1
33022 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_MSB 1
33024 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_WIDTH 1
33026 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_SET_MSK 0x00000002
33028 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_CLR_MSK 0xfffffffd
33030 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_RESET 0x0
33032 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_GET(value) (((value) & 0x00000002) >> 1)
33034 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_ENABLE_SET_SET(value) (((value) << 1) & 0x00000002)
33045 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_LSB 2
33047 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_MSB 2
33049 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_WIDTH 1
33051 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_SET_MSK 0x00000004
33053 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_CLR_MSK 0xfffffffb
33055 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_RESET 0x0
33057 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_GET(value) (((value) & 0x00000004) >> 2)
33059 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM0_FORCE_DRAIN_SET_SET(value) (((value) << 2) & 0x00000004)
33070 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_LSB 3
33072 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_MSB 3
33074 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_WIDTH 1
33076 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_SET_MSK 0x00000008
33078 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_CLR_MSK 0xfffffff7
33080 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_RESET 0x0
33082 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_GET(value) (((value) & 0x00000008) >> 3)
33084 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_IDLEREQ_SET_SET(value) (((value) << 3) & 0x00000008)
33095 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_LSB 4
33097 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_MSB 4
33099 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_WIDTH 1
33101 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_SET_MSK 0x00000010
33103 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_CLR_MSK 0xffffffef
33105 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_RESET 0x0
33107 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_GET(value) (((value) & 0x00000010) >> 4)
33109 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_ENABLE_SET_SET(value) (((value) << 4) & 0x00000010)
33120 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_LSB 5
33122 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_MSB 5
33124 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_WIDTH 1
33126 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_SET_MSK 0x00000020
33128 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_CLR_MSK 0xffffffdf
33130 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_RESET 0x0
33132 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_GET(value) (((value) & 0x00000020) >> 5)
33134 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM1_FORCE_DRAIN_SET_SET(value) (((value) << 5) & 0x00000020)
33145 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_LSB 6
33147 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_MSB 6
33149 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_WIDTH 1
33151 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_SET_MSK 0x00000040
33153 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_CLR_MSK 0xffffffbf
33155 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_RESET 0x0
33157 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_GET(value) (((value) & 0x00000040) >> 6)
33159 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_IDLEREQ_SET_SET(value) (((value) << 6) & 0x00000040)
33170 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_LSB 7
33172 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_MSB 7
33174 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_WIDTH 1
33176 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_SET_MSK 0x00000080
33178 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_CLR_MSK 0xffffff7f
33180 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_RESET 0x0
33182 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_GET(value) (((value) & 0x00000080) >> 7)
33184 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_ENABLE_SET_SET(value) (((value) << 7) & 0x00000080)
33195 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_LSB 8
33197 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_MSB 8
33199 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_WIDTH 1
33201 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_SET_MSK 0x00000100
33203 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_CLR_MSK 0xfffffeff
33205 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_RESET 0x0
33207 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_GET(value) (((value) & 0x00000100) >> 8)
33209 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_FPGA2SDRAM2_FORCE_DRAIN_SET_SET(value) (((value) << 8) & 0x00000100)
33211 #ifndef __ASSEMBLY__
33223 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_s
33225 volatile uint32_t FPGA2SDRAM0_IDLEREQ_SET : 1;
33226 volatile uint32_t FPGA2SDRAM0_ENABLE_SET : 1;
33227 volatile uint32_t FPGA2SDRAM0_FORCE_DRAIN_SET : 1;
33228 volatile uint32_t FPGA2SDRAM1_IDLEREQ_SET : 1;
33229 volatile uint32_t FPGA2SDRAM1_ENABLE_SET : 1;
33230 volatile uint32_t FPGA2SDRAM1_FORCE_DRAIN_SET : 1;
33231 volatile uint32_t FPGA2SDRAM2_IDLEREQ_SET : 1;
33232 volatile uint32_t FPGA2SDRAM2_ENABLE_SET : 1;
33233 volatile uint32_t FPGA2SDRAM2_FORCE_DRAIN_SET : 1;
33238 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_t;
33242 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_RESET 0x00000000
33244 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_OFST 0x50
33274 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_LSB 0
33276 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_MSB 0
33278 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_WIDTH 1
33280 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_SET_MSK 0x00000001
33282 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_CLR_MSK 0xfffffffe
33284 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_RESET 0x0
33286 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_GET(value) (((value) & 0x00000001) >> 0)
33288 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_IDLEREQ_CLR_SET(value) (((value) << 0) & 0x00000001)
33299 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_LSB 1
33301 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_MSB 1
33303 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_WIDTH 1
33305 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_SET_MSK 0x00000002
33307 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_CLR_MSK 0xfffffffd
33309 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_RESET 0x0
33311 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_GET(value) (((value) & 0x00000002) >> 1)
33313 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_ENABLE_CLR_SET(value) (((value) << 1) & 0x00000002)
33324 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_LSB 2
33326 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_MSB 2
33328 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_WIDTH 1
33330 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_SET_MSK 0x00000004
33332 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_CLR_MSK 0xfffffffb
33334 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_RESET 0x0
33336 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_GET(value) (((value) & 0x00000004) >> 2)
33338 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM0_FORCE_DRAIN_CLR_SET(value) (((value) << 2) & 0x00000004)
33349 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_LSB 3
33351 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_MSB 3
33353 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_WIDTH 1
33355 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_SET_MSK 0x00000008
33357 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_CLR_MSK 0xfffffff7
33359 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_RESET 0x0
33361 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_GET(value) (((value) & 0x00000008) >> 3)
33363 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_IDLEREQ_CLR_SET(value) (((value) << 3) & 0x00000008)
33374 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_LSB 4
33376 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_MSB 4
33378 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_WIDTH 1
33380 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_SET_MSK 0x00000010
33382 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_CLR_MSK 0xffffffef
33384 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_RESET 0x0
33386 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_GET(value) (((value) & 0x00000010) >> 4)
33388 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_ENABLE_CLR_SET(value) (((value) << 4) & 0x00000010)
33399 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_LSB 5
33401 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_MSB 5
33403 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_WIDTH 1
33405 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_SET_MSK 0x00000020
33407 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_CLR_MSK 0xffffffdf
33409 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_RESET 0x0
33411 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_GET(value) (((value) & 0x00000020) >> 5)
33413 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM1_FORCE_DRAIN_CLR_SET(value) (((value) << 5) & 0x00000020)
33424 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_LSB 6
33426 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_MSB 6
33428 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_WIDTH 1
33430 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_SET_MSK 0x00000040
33432 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_CLR_MSK 0xffffffbf
33434 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_RESET 0x0
33436 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_GET(value) (((value) & 0x00000040) >> 6)
33438 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_IDLEREQ_CLR_SET(value) (((value) << 6) & 0x00000040)
33449 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_LSB 7
33451 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_MSB 7
33453 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_WIDTH 1
33455 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_SET_MSK 0x00000080
33457 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_CLR_MSK 0xffffff7f
33459 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_RESET 0x0
33461 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_GET(value) (((value) & 0x00000080) >> 7)
33463 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_ENABLE_CLR_SET(value) (((value) << 7) & 0x00000080)
33474 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_LSB 8
33476 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_MSB 8
33478 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_WIDTH 1
33480 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_SET_MSK 0x00000100
33482 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_CLR_MSK 0xfffffeff
33484 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_RESET 0x0
33486 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_GET(value) (((value) & 0x00000100) >> 8)
33488 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_FPGA2SDRAM2_FORCE_DRAIN_CLR_SET(value) (((value) << 8) & 0x00000100)
33490 #ifndef __ASSEMBLY__
33502 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_s
33504 volatile uint32_t FPGA2SDRAM0_IDLEREQ_CLR : 1;
33505 volatile uint32_t FPGA2SDRAM0_ENABLE_CLR : 1;
33506 volatile uint32_t FPGA2SDRAM0_FORCE_DRAIN_CLR : 1;
33507 volatile uint32_t FPGA2SDRAM1_IDLEREQ_CLR : 1;
33508 volatile uint32_t FPGA2SDRAM1_ENABLE_CLR : 1;
33509 volatile uint32_t FPGA2SDRAM1_FORCE_DRAIN_CLR : 1;
33510 volatile uint32_t FPGA2SDRAM2_IDLEREQ_CLR : 1;
33511 volatile uint32_t FPGA2SDRAM2_ENABLE_CLR : 1;
33512 volatile uint32_t FPGA2SDRAM2_FORCE_DRAIN_CLR : 1;
33517 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_t;
33521 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_RESET 0x00000000
33523 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_OFST 0x54
33553 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_LSB 0
33555 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_MSB 0
33557 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_WIDTH 1
33559 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_SET_MSK 0x00000001
33561 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_CLR_MSK 0xfffffffe
33563 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_RESET 0x0
33565 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_GET(value) (((value) & 0x00000001) >> 0)
33567 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_IDLEREQ_STATUS_SET(value) (((value) << 0) & 0x00000001)
33578 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_LSB 1
33580 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_MSB 1
33582 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_WIDTH 1
33584 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_SET_MSK 0x00000002
33586 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_CLR_MSK 0xfffffffd
33588 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_RESET 0x0
33590 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_GET(value) (((value) & 0x00000002) >> 1)
33592 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_ENABLE_STATUS_SET(value) (((value) << 1) & 0x00000002)
33603 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_LSB 2
33605 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_MSB 2
33607 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_WIDTH 1
33609 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_SET_MSK 0x00000004
33611 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_CLR_MSK 0xfffffffb
33613 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_RESET 0x0
33615 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_GET(value) (((value) & 0x00000004) >> 2)
33617 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM0_FORCE_DRAIN_STATUS_SET(value) (((value) << 2) & 0x00000004)
33628 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_LSB 3
33630 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_MSB 3
33632 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_WIDTH 1
33634 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_SET_MSK 0x00000008
33636 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_CLR_MSK 0xfffffff7
33638 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_RESET 0x0
33640 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_GET(value) (((value) & 0x00000008) >> 3)
33642 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_IDLEREQ_STATUS_SET(value) (((value) << 3) & 0x00000008)
33653 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_LSB 4
33655 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_MSB 4
33657 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_WIDTH 1
33659 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_SET_MSK 0x00000010
33661 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_CLR_MSK 0xffffffef
33663 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_RESET 0x0
33665 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_GET(value) (((value) & 0x00000010) >> 4)
33667 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_ENABLE_STATUS_SET(value) (((value) << 4) & 0x00000010)
33678 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_LSB 5
33680 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_MSB 5
33682 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_WIDTH 1
33684 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_SET_MSK 0x00000020
33686 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_CLR_MSK 0xffffffdf
33688 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_RESET 0x0
33690 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_GET(value) (((value) & 0x00000020) >> 5)
33692 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM1_FORCE_DRAIN_STATUS_SET(value) (((value) << 5) & 0x00000020)
33703 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_LSB 6
33705 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_MSB 6
33707 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_WIDTH 1
33709 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_SET_MSK 0x00000040
33711 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_CLR_MSK 0xffffffbf
33713 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_RESET 0x0
33715 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_GET(value) (((value) & 0x00000040) >> 6)
33717 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_IDLEREQ_STATUS_SET(value) (((value) << 6) & 0x00000040)
33728 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_LSB 7
33730 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_MSB 7
33732 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_WIDTH 1
33734 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_SET_MSK 0x00000080
33736 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_CLR_MSK 0xffffff7f
33738 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_RESET 0x0
33740 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_GET(value) (((value) & 0x00000080) >> 7)
33742 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_ENABLE_STATUS_SET(value) (((value) << 7) & 0x00000080)
33753 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_LSB 8
33755 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_MSB 8
33757 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_WIDTH 1
33759 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_SET_MSK 0x00000100
33761 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_CLR_MSK 0xfffffeff
33763 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_RESET 0x0
33765 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_GET(value) (((value) & 0x00000100) >> 8)
33767 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_FPGA2SDRAM2_FORCE_DRAIN_STATUS_SET(value) (((value) << 8) & 0x00000100)
33769 #ifndef __ASSEMBLY__
33781 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_s
33783 const volatile uint32_t FPGA2SDRAM0_IDLEREQ_STATUS : 1;
33784 const volatile uint32_t FPGA2SDRAM0_ENABLE_STATUS : 1;
33785 const volatile uint32_t FPGA2SDRAM0_FORCE_DRAIN_STATUS : 1;
33786 const volatile uint32_t FPGA2SDRAM1_IDLEREQ_STATUS : 1;
33787 const volatile uint32_t FPGA2SDRAM1_ENABLE_STATUS : 1;
33788 const volatile uint32_t FPGA2SDRAM1_FORCE_DRAIN_STATUS : 1;
33789 const volatile uint32_t FPGA2SDRAM2_IDLEREQ_STATUS : 1;
33790 const volatile uint32_t FPGA2SDRAM2_ENABLE_STATUS : 1;
33791 const volatile uint32_t FPGA2SDRAM2_FORCE_DRAIN_STATUS : 1;
33796 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_t;
33800 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_RESET 0x00000000
33802 #define ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_OFST 0x58
33804 #ifndef __ASSEMBLY__
33816 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_s
33818 volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_COREID_t fpga2sdram_manager_main_SidebandManager_Id_CoreId;
33819 volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_ID_REVISIONID_t fpga2sdram_manager_main_SidebandManager_Id_RevisionId;
33820 volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTEN_t fpga2sdram_manager_main_SidebandManager_FaultEn;
33821 volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FAULTSTATUS_t fpga2sdram_manager_main_SidebandManager_FaultStatus;
33822 volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINEN0_t fpga2sdram_manager_main_SidebandManager_FlagInEn0;
33823 volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGINSTATUS0_t fpga2sdram_manager_main_SidebandManager_FlagInStatus0;
33824 volatile uint32_t _pad_0x18_0x4f[14];
33825 volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSET0_t fpga2sdram_manager_main_SidebandManager_FlagOutSet0;
33826 volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTCLR0_t fpga2sdram_manager_main_SidebandManager_FlagOutClr0;
33827 volatile ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER_FLAGOUTSTATUS0_t fpga2sdram_manager_main_SidebandManager_FlagOutStatus0;
33828 volatile uint32_t _pad_0x5c_0x100[41];
33832 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_t;
33834 struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_raw_s
33836 volatile uint32_t fpga2sdram_manager_main_SidebandManager_Id_CoreId;
33837 volatile uint32_t fpga2sdram_manager_main_SidebandManager_Id_RevisionId;
33838 volatile uint32_t fpga2sdram_manager_main_SidebandManager_FaultEn;
33839 volatile uint32_t fpga2sdram_manager_main_SidebandManager_FaultStatus;
33840 volatile uint32_t fpga2sdram_manager_main_SidebandManager_FlagInEn0;
33841 volatile uint32_t fpga2sdram_manager_main_SidebandManager_FlagInStatus0;
33842 volatile uint32_t _pad_0x18_0x4f[14];
33843 volatile uint32_t fpga2sdram_manager_main_SidebandManager_FlagOutSet0;
33844 volatile uint32_t fpga2sdram_manager_main_SidebandManager_FlagOutClr0;
33845 volatile uint32_t fpga2sdram_manager_main_SidebandManager_FlagOutStatus0;
33846 volatile uint32_t _pad_0x5c_0x100[41];
33850 typedef struct ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_raw_s ALT_MPFE_F2SDR_MGR_MAIN_SBMGR_raw_t;