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alt_uart.h
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32 
33 /* Altera - ALT_UART */
34 
35 #ifndef __ALT_SOCAL_UART_H__
36 #define __ALT_SOCAL_UART_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : UART
50  *
51  */
52 /*
53  * Register : Receive Buffer Register - RBR
54  *
55  * Receive Buffer Register, reading this register when the DLAB bit is zero;
56  *
57  * Transmit Holding Register, writing to this register when the DLAB is zero;
58  *
59  * Divisor Latch (Low), when DLAB bit is one
60  *
61  * Register Layout
62  *
63  * Bits | Access | Reset | Description
64  * :-------|:-------|:------|:----------------------------
65  * [7:0] | R | 0x0 | ALT_UART_RBR_RBR
66  * [31:8] | R | 0x0 | ALT_UART_RBR_RSVD_RBR_31TO8
67  *
68  */
69 /*
70  * Field : rbr
71  *
72  * Receive Buffer Register:
73  *
74  * This register contains the data byte received on the serial input port (sin)
75  *
76  * in UART mode or the serial infrared input (sir_in) in infrared mode. The data
77  *
78  * in this register is valid only if the Data Ready (DR) bit in the Line status
79  *
80  * Register (LSR) is set.
81  *
82  * If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to
83  *
84  * zero), the data in the RBR must be read before the next data arrives, otherwise
85  *
86  * it will be overwritten, resulting in an overrun error.
87  *
88  * If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one),
89  *
90  * this register accesses the head of the receive FIFO. If the receive FIFO is full
91  *
92  * and this register is not read before the next data character arrives, then the
93  *
94  * data already in the FIFO will be preserved but any incoming data will be lost.
95  *
96  * An overrun error will also occur.
97  *
98  * Field Access Macros:
99  *
100  */
101 /* The Least Significant Bit (LSB) position of the ALT_UART_RBR_RBR register field. */
102 #define ALT_UART_RBR_RBR_LSB 0
103 /* The Most Significant Bit (MSB) position of the ALT_UART_RBR_RBR register field. */
104 #define ALT_UART_RBR_RBR_MSB 7
105 /* The width in bits of the ALT_UART_RBR_RBR register field. */
106 #define ALT_UART_RBR_RBR_WIDTH 8
107 /* The mask used to set the ALT_UART_RBR_RBR register field value. */
108 #define ALT_UART_RBR_RBR_SET_MSK 0x000000ff
109 /* The mask used to clear the ALT_UART_RBR_RBR register field value. */
110 #define ALT_UART_RBR_RBR_CLR_MSK 0xffffff00
111 /* The reset value of the ALT_UART_RBR_RBR register field. */
112 #define ALT_UART_RBR_RBR_RESET 0x0
113 /* Extracts the ALT_UART_RBR_RBR field value from a register. */
114 #define ALT_UART_RBR_RBR_GET(value) (((value) & 0x000000ff) >> 0)
115 /* Produces a ALT_UART_RBR_RBR register field value suitable for setting the register. */
116 #define ALT_UART_RBR_RBR_SET(value) (((value) << 0) & 0x000000ff)
117 
118 /*
119  * Field : RSVD_RBR_31to8
120  *
121  * Reserved bits [31:8] - Read Only
122  *
123  * Field Access Macros:
124  *
125  */
126 /* The Least Significant Bit (LSB) position of the ALT_UART_RBR_RSVD_RBR_31TO8 register field. */
127 #define ALT_UART_RBR_RSVD_RBR_31TO8_LSB 8
128 /* The Most Significant Bit (MSB) position of the ALT_UART_RBR_RSVD_RBR_31TO8 register field. */
129 #define ALT_UART_RBR_RSVD_RBR_31TO8_MSB 31
130 /* The width in bits of the ALT_UART_RBR_RSVD_RBR_31TO8 register field. */
131 #define ALT_UART_RBR_RSVD_RBR_31TO8_WIDTH 24
132 /* The mask used to set the ALT_UART_RBR_RSVD_RBR_31TO8 register field value. */
133 #define ALT_UART_RBR_RSVD_RBR_31TO8_SET_MSK 0xffffff00
134 /* The mask used to clear the ALT_UART_RBR_RSVD_RBR_31TO8 register field value. */
135 #define ALT_UART_RBR_RSVD_RBR_31TO8_CLR_MSK 0x000000ff
136 /* The reset value of the ALT_UART_RBR_RSVD_RBR_31TO8 register field. */
137 #define ALT_UART_RBR_RSVD_RBR_31TO8_RESET 0x0
138 /* Extracts the ALT_UART_RBR_RSVD_RBR_31TO8 field value from a register. */
139 #define ALT_UART_RBR_RSVD_RBR_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
140 /* Produces a ALT_UART_RBR_RSVD_RBR_31TO8 register field value suitable for setting the register. */
141 #define ALT_UART_RBR_RSVD_RBR_31TO8_SET(value) (((value) << 8) & 0xffffff00)
142 
143 #ifndef __ASSEMBLY__
144 /*
145  * WARNING: The C register and register group struct declarations are provided for
146  * convenience and illustrative purposes. They should, however, be used with
147  * caution as the C language standard provides no guarantees about the alignment or
148  * atomicity of device memory accesses. The recommended practice for coding device
149  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
150  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
151  * alt_write_dword() functions for 64 bit registers.
152  *
153  * The struct declaration for register ALT_UART_RBR.
154  */
155 struct ALT_UART_RBR_s
156 {
157  const volatile uint32_t rbr : 8; /* ALT_UART_RBR_RBR */
158  const volatile uint32_t RSVD_RBR_31to8 : 24; /* ALT_UART_RBR_RSVD_RBR_31TO8 */
159 };
160 
161 /* The typedef declaration for register ALT_UART_RBR. */
162 typedef struct ALT_UART_RBR_s ALT_UART_RBR_t;
163 #endif /* __ASSEMBLY__ */
164 
165 /* The reset value of the ALT_UART_RBR register. */
166 #define ALT_UART_RBR_RESET 0x00000000
167 /* The byte offset of the ALT_UART_RBR register from the beginning of the component. */
168 #define ALT_UART_RBR_OFST 0x0
169 /* The address of the ALT_UART_RBR register. */
170 #define ALT_UART_RBR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RBR_OFST))
171 
172 /*
173  * Register : Interrupt Enable Register - IER
174  *
175  * Interrupt Enable Register:
176  *
177  * Interrupt Enable Register, when the DLAB bit is zero; Divisor Latch (High), when
178  * the DLAB bit is one.
179  *
180  * Each of the bits used has a different function and will be detailed in the bit
181  *
182  * field descriptions.
183  *
184  * Register Layout
185  *
186  * Bits | Access | Reset | Description
187  * :-------|:-------|:------|:----------------------------
188  * [0] | RW | 0x0 | ALT_UART_IER_ERBFI
189  * [1] | RW | 0x0 | ALT_UART_IER_ETBEI
190  * [2] | RW | 0x0 | ALT_UART_IER_ELSI
191  * [3] | RW | 0x0 | ALT_UART_IER_EDSSI
192  * [6:4] | R | 0x0 | ALT_UART_IER_RSVD_IER_6TO4
193  * [7] | RW | 0x0 | ALT_UART_IER_PTIME
194  * [31:8] | R | 0x0 | ALT_UART_IER_RSVD_IER_31TO8
195  *
196  */
197 /*
198  * Field : ERBFI
199  *
200  * Interrupt Enable Register: ERBFI, Enable Received Data Available Interrupt.
201  *
202  * This is used to enable/disable the generation of Received Data Available
203  * Interrupt
204  *
205  * and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These
206  * are
207  *
208  * the second highest priority interrupts.
209  *
210  * 0 = disabled
211  *
212  * 1 = enabled
213  *
214  * Field Enumeration Values:
215  *
216  * Enum | Value | Description
217  * :------------------------------|:------|:-------------------------------
218  * ALT_UART_IER_ERBFI_E_DISABLED | 0x0 | Disable Receive data Interrupt
219  * ALT_UART_IER_ERBFI_E_ENABLED | 0x1 | Enable Receive data Interrupt
220  *
221  * Field Access Macros:
222  *
223  */
224 /*
225  * Enumerated value for register field ALT_UART_IER_ERBFI
226  *
227  * Disable Receive data Interrupt
228  */
229 #define ALT_UART_IER_ERBFI_E_DISABLED 0x0
230 /*
231  * Enumerated value for register field ALT_UART_IER_ERBFI
232  *
233  * Enable Receive data Interrupt
234  */
235 #define ALT_UART_IER_ERBFI_E_ENABLED 0x1
236 
237 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_ERBFI register field. */
238 #define ALT_UART_IER_ERBFI_LSB 0
239 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_ERBFI register field. */
240 #define ALT_UART_IER_ERBFI_MSB 0
241 /* The width in bits of the ALT_UART_IER_ERBFI register field. */
242 #define ALT_UART_IER_ERBFI_WIDTH 1
243 /* The mask used to set the ALT_UART_IER_ERBFI register field value. */
244 #define ALT_UART_IER_ERBFI_SET_MSK 0x00000001
245 /* The mask used to clear the ALT_UART_IER_ERBFI register field value. */
246 #define ALT_UART_IER_ERBFI_CLR_MSK 0xfffffffe
247 /* The reset value of the ALT_UART_IER_ERBFI register field. */
248 #define ALT_UART_IER_ERBFI_RESET 0x0
249 /* Extracts the ALT_UART_IER_ERBFI field value from a register. */
250 #define ALT_UART_IER_ERBFI_GET(value) (((value) & 0x00000001) >> 0)
251 /* Produces a ALT_UART_IER_ERBFI register field value suitable for setting the register. */
252 #define ALT_UART_IER_ERBFI_SET(value) (((value) << 0) & 0x00000001)
253 
254 /*
255  * Field : ETBEI
256  *
257  * Interrupt Enable Register: ETBEI, Enable Transmit Holding Register Empty
258  * Interrupt.
259  *
260  * This is used to enable/disable the generation of Transmitter Holding Register
261  * Empty
262  *
263  * Interrupt. This is the third highest priority interrupt.
264  *
265  * 0 = disabled
266  *
267  * 1 = enabled
268  *
269  * Field Enumeration Values:
270  *
271  * Enum | Value | Description
272  * :------------------------------|:------|:---------------------------------
273  * ALT_UART_IER_ETBEI_E_DISABLED | 0x0 | Disable Transmit empty interrupt
274  * ALT_UART_IER_ETBEI_E_ENABLED | 0x1 | Enable Transmit empty interrupt
275  *
276  * Field Access Macros:
277  *
278  */
279 /*
280  * Enumerated value for register field ALT_UART_IER_ETBEI
281  *
282  * Disable Transmit empty interrupt
283  */
284 #define ALT_UART_IER_ETBEI_E_DISABLED 0x0
285 /*
286  * Enumerated value for register field ALT_UART_IER_ETBEI
287  *
288  * Enable Transmit empty interrupt
289  */
290 #define ALT_UART_IER_ETBEI_E_ENABLED 0x1
291 
292 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_ETBEI register field. */
293 #define ALT_UART_IER_ETBEI_LSB 1
294 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_ETBEI register field. */
295 #define ALT_UART_IER_ETBEI_MSB 1
296 /* The width in bits of the ALT_UART_IER_ETBEI register field. */
297 #define ALT_UART_IER_ETBEI_WIDTH 1
298 /* The mask used to set the ALT_UART_IER_ETBEI register field value. */
299 #define ALT_UART_IER_ETBEI_SET_MSK 0x00000002
300 /* The mask used to clear the ALT_UART_IER_ETBEI register field value. */
301 #define ALT_UART_IER_ETBEI_CLR_MSK 0xfffffffd
302 /* The reset value of the ALT_UART_IER_ETBEI register field. */
303 #define ALT_UART_IER_ETBEI_RESET 0x0
304 /* Extracts the ALT_UART_IER_ETBEI field value from a register. */
305 #define ALT_UART_IER_ETBEI_GET(value) (((value) & 0x00000002) >> 1)
306 /* Produces a ALT_UART_IER_ETBEI register field value suitable for setting the register. */
307 #define ALT_UART_IER_ETBEI_SET(value) (((value) << 1) & 0x00000002)
308 
309 /*
310  * Field : ELSI
311  *
312  * Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt.
313  *
314  * This is used to enable/disable the generation of Receiver Line Status Interrupt.
315  *
316  * This is the highest priority interrupt.
317  *
318  * 0 = disabled
319  *
320  * 1 = enabled
321  *
322  * Field Enumeration Values:
323  *
324  * Enum | Value | Description
325  * :-----------------------------|:------|:---------------------------------------
326  * ALT_UART_IER_ELSI_E_DISABLED | 0x0 | Disable Receiver Line Status Interrupt
327  * ALT_UART_IER_ELSI_E_ENABLED | 0x1 | Enable Receiver Line Status Interrupt
328  *
329  * Field Access Macros:
330  *
331  */
332 /*
333  * Enumerated value for register field ALT_UART_IER_ELSI
334  *
335  * Disable Receiver Line Status Interrupt
336  */
337 #define ALT_UART_IER_ELSI_E_DISABLED 0x0
338 /*
339  * Enumerated value for register field ALT_UART_IER_ELSI
340  *
341  * Enable Receiver Line Status Interrupt
342  */
343 #define ALT_UART_IER_ELSI_E_ENABLED 0x1
344 
345 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_ELSI register field. */
346 #define ALT_UART_IER_ELSI_LSB 2
347 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_ELSI register field. */
348 #define ALT_UART_IER_ELSI_MSB 2
349 /* The width in bits of the ALT_UART_IER_ELSI register field. */
350 #define ALT_UART_IER_ELSI_WIDTH 1
351 /* The mask used to set the ALT_UART_IER_ELSI register field value. */
352 #define ALT_UART_IER_ELSI_SET_MSK 0x00000004
353 /* The mask used to clear the ALT_UART_IER_ELSI register field value. */
354 #define ALT_UART_IER_ELSI_CLR_MSK 0xfffffffb
355 /* The reset value of the ALT_UART_IER_ELSI register field. */
356 #define ALT_UART_IER_ELSI_RESET 0x0
357 /* Extracts the ALT_UART_IER_ELSI field value from a register. */
358 #define ALT_UART_IER_ELSI_GET(value) (((value) & 0x00000004) >> 2)
359 /* Produces a ALT_UART_IER_ELSI register field value suitable for setting the register. */
360 #define ALT_UART_IER_ELSI_SET(value) (((value) << 2) & 0x00000004)
361 
362 /*
363  * Field : EDSSI
364  *
365  * Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt.
366  *
367  * This is used to enable/disable the generation of Modem Status Interrupt. This is
368  *
369  * the fourth highest priority interrupt.
370  *
371  * 0 = disabled
372  *
373  * 1 = enabled
374  *
375  * Field Enumeration Values:
376  *
377  * Enum | Value | Description
378  * :------------------------------|:------|:-------------------------------
379  * ALT_UART_IER_EDSSI_E_DISABLED | 0x0 | Disable Modem Status Interrupt
380  * ALT_UART_IER_EDSSI_E_ENABLED | 0x1 | Enable Modem Status Interrupt
381  *
382  * Field Access Macros:
383  *
384  */
385 /*
386  * Enumerated value for register field ALT_UART_IER_EDSSI
387  *
388  * Disable Modem Status Interrupt
389  */
390 #define ALT_UART_IER_EDSSI_E_DISABLED 0x0
391 /*
392  * Enumerated value for register field ALT_UART_IER_EDSSI
393  *
394  * Enable Modem Status Interrupt
395  */
396 #define ALT_UART_IER_EDSSI_E_ENABLED 0x1
397 
398 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_EDSSI register field. */
399 #define ALT_UART_IER_EDSSI_LSB 3
400 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_EDSSI register field. */
401 #define ALT_UART_IER_EDSSI_MSB 3
402 /* The width in bits of the ALT_UART_IER_EDSSI register field. */
403 #define ALT_UART_IER_EDSSI_WIDTH 1
404 /* The mask used to set the ALT_UART_IER_EDSSI register field value. */
405 #define ALT_UART_IER_EDSSI_SET_MSK 0x00000008
406 /* The mask used to clear the ALT_UART_IER_EDSSI register field value. */
407 #define ALT_UART_IER_EDSSI_CLR_MSK 0xfffffff7
408 /* The reset value of the ALT_UART_IER_EDSSI register field. */
409 #define ALT_UART_IER_EDSSI_RESET 0x0
410 /* Extracts the ALT_UART_IER_EDSSI field value from a register. */
411 #define ALT_UART_IER_EDSSI_GET(value) (((value) & 0x00000008) >> 3)
412 /* Produces a ALT_UART_IER_EDSSI register field value suitable for setting the register. */
413 #define ALT_UART_IER_EDSSI_SET(value) (((value) << 3) & 0x00000008)
414 
415 /*
416  * Field : RSVD_IER_6to4
417  *
418  * Reserved bits [6:4] - Read Only
419  *
420  * Field Access Macros:
421  *
422  */
423 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_RSVD_IER_6TO4 register field. */
424 #define ALT_UART_IER_RSVD_IER_6TO4_LSB 4
425 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_RSVD_IER_6TO4 register field. */
426 #define ALT_UART_IER_RSVD_IER_6TO4_MSB 6
427 /* The width in bits of the ALT_UART_IER_RSVD_IER_6TO4 register field. */
428 #define ALT_UART_IER_RSVD_IER_6TO4_WIDTH 3
429 /* The mask used to set the ALT_UART_IER_RSVD_IER_6TO4 register field value. */
430 #define ALT_UART_IER_RSVD_IER_6TO4_SET_MSK 0x00000070
431 /* The mask used to clear the ALT_UART_IER_RSVD_IER_6TO4 register field value. */
432 #define ALT_UART_IER_RSVD_IER_6TO4_CLR_MSK 0xffffff8f
433 /* The reset value of the ALT_UART_IER_RSVD_IER_6TO4 register field. */
434 #define ALT_UART_IER_RSVD_IER_6TO4_RESET 0x0
435 /* Extracts the ALT_UART_IER_RSVD_IER_6TO4 field value from a register. */
436 #define ALT_UART_IER_RSVD_IER_6TO4_GET(value) (((value) & 0x00000070) >> 4)
437 /* Produces a ALT_UART_IER_RSVD_IER_6TO4 register field value suitable for setting the register. */
438 #define ALT_UART_IER_RSVD_IER_6TO4_SET(value) (((value) << 4) & 0x00000070)
439 
440 /*
441  * Field : PTIME
442  *
443  * Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable.
444  *
445  * Writeable only when THRE_MODE_USER == Enabled, always readable. This is used
446  *
447  * to enable/disable the generation of THRE Interrupt.
448  *
449  * 0 = disabled
450  *
451  * 1 = enabled
452  *
453  * Field Enumeration Values:
454  *
455  * Enum | Value | Description
456  * :------------------------------|:------|:-----------------------------------------
457  * ALT_UART_IER_PTIME_E_DISABLED | 0x0 | Disable Programmable THRE Interrupt Mode
458  * ALT_UART_IER_PTIME_E_ENABLED | 0x1 | Enable Programmable THRE Interrupt Mode
459  *
460  * Field Access Macros:
461  *
462  */
463 /*
464  * Enumerated value for register field ALT_UART_IER_PTIME
465  *
466  * Disable Programmable THRE Interrupt Mode
467  */
468 #define ALT_UART_IER_PTIME_E_DISABLED 0x0
469 /*
470  * Enumerated value for register field ALT_UART_IER_PTIME
471  *
472  * Enable Programmable THRE Interrupt Mode
473  */
474 #define ALT_UART_IER_PTIME_E_ENABLED 0x1
475 
476 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_PTIME register field. */
477 #define ALT_UART_IER_PTIME_LSB 7
478 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_PTIME register field. */
479 #define ALT_UART_IER_PTIME_MSB 7
480 /* The width in bits of the ALT_UART_IER_PTIME register field. */
481 #define ALT_UART_IER_PTIME_WIDTH 1
482 /* The mask used to set the ALT_UART_IER_PTIME register field value. */
483 #define ALT_UART_IER_PTIME_SET_MSK 0x00000080
484 /* The mask used to clear the ALT_UART_IER_PTIME register field value. */
485 #define ALT_UART_IER_PTIME_CLR_MSK 0xffffff7f
486 /* The reset value of the ALT_UART_IER_PTIME register field. */
487 #define ALT_UART_IER_PTIME_RESET 0x0
488 /* Extracts the ALT_UART_IER_PTIME field value from a register. */
489 #define ALT_UART_IER_PTIME_GET(value) (((value) & 0x00000080) >> 7)
490 /* Produces a ALT_UART_IER_PTIME register field value suitable for setting the register. */
491 #define ALT_UART_IER_PTIME_SET(value) (((value) << 7) & 0x00000080)
492 
493 /*
494  * Field : RSVD_IER_31to8
495  *
496  * Reserved bits [31:8] - Read Only
497  *
498  * Field Access Macros:
499  *
500  */
501 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_RSVD_IER_31TO8 register field. */
502 #define ALT_UART_IER_RSVD_IER_31TO8_LSB 8
503 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_RSVD_IER_31TO8 register field. */
504 #define ALT_UART_IER_RSVD_IER_31TO8_MSB 31
505 /* The width in bits of the ALT_UART_IER_RSVD_IER_31TO8 register field. */
506 #define ALT_UART_IER_RSVD_IER_31TO8_WIDTH 24
507 /* The mask used to set the ALT_UART_IER_RSVD_IER_31TO8 register field value. */
508 #define ALT_UART_IER_RSVD_IER_31TO8_SET_MSK 0xffffff00
509 /* The mask used to clear the ALT_UART_IER_RSVD_IER_31TO8 register field value. */
510 #define ALT_UART_IER_RSVD_IER_31TO8_CLR_MSK 0x000000ff
511 /* The reset value of the ALT_UART_IER_RSVD_IER_31TO8 register field. */
512 #define ALT_UART_IER_RSVD_IER_31TO8_RESET 0x0
513 /* Extracts the ALT_UART_IER_RSVD_IER_31TO8 field value from a register. */
514 #define ALT_UART_IER_RSVD_IER_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
515 /* Produces a ALT_UART_IER_RSVD_IER_31TO8 register field value suitable for setting the register. */
516 #define ALT_UART_IER_RSVD_IER_31TO8_SET(value) (((value) << 8) & 0xffffff00)
517 
518 #ifndef __ASSEMBLY__
519 /*
520  * WARNING: The C register and register group struct declarations are provided for
521  * convenience and illustrative purposes. They should, however, be used with
522  * caution as the C language standard provides no guarantees about the alignment or
523  * atomicity of device memory accesses. The recommended practice for coding device
524  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
525  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
526  * alt_write_dword() functions for 64 bit registers.
527  *
528  * The struct declaration for register ALT_UART_IER.
529  */
530 struct ALT_UART_IER_s
531 {
532  volatile uint32_t ERBFI : 1; /* ALT_UART_IER_ERBFI */
533  volatile uint32_t ETBEI : 1; /* ALT_UART_IER_ETBEI */
534  volatile uint32_t ELSI : 1; /* ALT_UART_IER_ELSI */
535  volatile uint32_t EDSSI : 1; /* ALT_UART_IER_EDSSI */
536  const volatile uint32_t RSVD_IER_6to4 : 3; /* ALT_UART_IER_RSVD_IER_6TO4 */
537  volatile uint32_t PTIME : 1; /* ALT_UART_IER_PTIME */
538  const volatile uint32_t RSVD_IER_31to8 : 24; /* ALT_UART_IER_RSVD_IER_31TO8 */
539 };
540 
541 /* The typedef declaration for register ALT_UART_IER. */
542 typedef struct ALT_UART_IER_s ALT_UART_IER_t;
543 #endif /* __ASSEMBLY__ */
544 
545 /* The reset value of the ALT_UART_IER register. */
546 #define ALT_UART_IER_RESET 0x00000000
547 /* The byte offset of the ALT_UART_IER register from the beginning of the component. */
548 #define ALT_UART_IER_OFST 0x4
549 /* The address of the ALT_UART_IER register. */
550 #define ALT_UART_IER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IER_OFST))
551 
552 /*
553  * Register : Interrupt Identification Register - IIR
554  *
555  * Interrupt Identification Register
556  *
557  * Register Layout
558  *
559  * Bits | Access | Reset | Description
560  * :-------|:-------|:------|:----------------------------
561  * [3:0] | R | 0x1 | ALT_UART_IIR_IID
562  * [5:4] | R | 0x0 | ALT_UART_IIR_RSVD_IIR_5TO4
563  * [7:6] | R | 0x0 | ALT_UART_IIR_FIFOSE
564  * [31:8] | R | 0x0 | ALT_UART_IIR_RSVD_IIR_31TO8
565  *
566  */
567 /*
568  * Field : IID
569  *
570  * Bits[3:0], Interrupt ID (or IID):
571  *
572  * This indicates the highest priority pending interrupt which can be one of the
573  *
574  * following types:
575  *
576  * 0000 = modem status.
577  *
578  * 0001 = no interrupt pending.
579  *
580  * 0010 = THR empty.
581  *
582  * 0100 = received data available.
583  *
584  * 0110 = receiver line status.
585  *
586  * 0111 = busy detect.
587  *
588  * 1100 = character timeout.
589  *
590  * Note, an interrupt of type 0111 (busy detect) will never get indicated if
591  *
592  * UART_16550_COMPATIBLE == YES in coreConsultant.
593  *
594  * Field Enumeration Values:
595  *
596  * Enum | Value | Description
597  * :-------------------------------------------|:------|:------------------------
598  * ALT_UART_IIR_IID_E_MODEM_STATUS | 0x0 | modem status
599  * ALT_UART_IIR_IID_E_NO_INTERRUPT_PENDING | 0x1 | no interrupt pending
600  * ALT_UART_IIR_IID_E_THR_EMPTY | 0x2 | THR empty
601  * ALT_UART_IIR_IID_E_RECEIVED_DATA_AVAILABLE | 0x4 | received data available
602  * ALT_UART_IIR_IID_E_RECEIVER_LINE_STATUS | 0x5 | receiver line status
603  * ALT_UART_IIR_IID_E_BUSY_DETECT | 0x7 | busy detect
604  * ALT_UART_IIR_IID_E_CHARACTER_TIMEOUT | 0xc | character timeout
605  *
606  * Field Access Macros:
607  *
608  */
609 /*
610  * Enumerated value for register field ALT_UART_IIR_IID
611  *
612  * modem status
613  */
614 #define ALT_UART_IIR_IID_E_MODEM_STATUS 0x0
615 /*
616  * Enumerated value for register field ALT_UART_IIR_IID
617  *
618  * no interrupt pending
619  */
620 #define ALT_UART_IIR_IID_E_NO_INTERRUPT_PENDING 0x1
621 /*
622  * Enumerated value for register field ALT_UART_IIR_IID
623  *
624  * THR empty
625  */
626 #define ALT_UART_IIR_IID_E_THR_EMPTY 0x2
627 /*
628  * Enumerated value for register field ALT_UART_IIR_IID
629  *
630  * received data available
631  */
632 #define ALT_UART_IIR_IID_E_RECEIVED_DATA_AVAILABLE 0x4
633 /*
634  * Enumerated value for register field ALT_UART_IIR_IID
635  *
636  * receiver line status
637  */
638 #define ALT_UART_IIR_IID_E_RECEIVER_LINE_STATUS 0x5
639 /*
640  * Enumerated value for register field ALT_UART_IIR_IID
641  *
642  * busy detect
643  */
644 #define ALT_UART_IIR_IID_E_BUSY_DETECT 0x7
645 /*
646  * Enumerated value for register field ALT_UART_IIR_IID
647  *
648  * character timeout
649  */
650 #define ALT_UART_IIR_IID_E_CHARACTER_TIMEOUT 0xc
651 
652 /* The Least Significant Bit (LSB) position of the ALT_UART_IIR_IID register field. */
653 #define ALT_UART_IIR_IID_LSB 0
654 /* The Most Significant Bit (MSB) position of the ALT_UART_IIR_IID register field. */
655 #define ALT_UART_IIR_IID_MSB 3
656 /* The width in bits of the ALT_UART_IIR_IID register field. */
657 #define ALT_UART_IIR_IID_WIDTH 4
658 /* The mask used to set the ALT_UART_IIR_IID register field value. */
659 #define ALT_UART_IIR_IID_SET_MSK 0x0000000f
660 /* The mask used to clear the ALT_UART_IIR_IID register field value. */
661 #define ALT_UART_IIR_IID_CLR_MSK 0xfffffff0
662 /* The reset value of the ALT_UART_IIR_IID register field. */
663 #define ALT_UART_IIR_IID_RESET 0x1
664 /* Extracts the ALT_UART_IIR_IID field value from a register. */
665 #define ALT_UART_IIR_IID_GET(value) (((value) & 0x0000000f) >> 0)
666 /* Produces a ALT_UART_IIR_IID register field value suitable for setting the register. */
667 #define ALT_UART_IIR_IID_SET(value) (((value) << 0) & 0x0000000f)
668 
669 /*
670  * Field : RSVD_IIR_5to4
671  *
672  * Reserved bits [5:4] - Read Only
673  *
674  * Field Access Macros:
675  *
676  */
677 /* The Least Significant Bit (LSB) position of the ALT_UART_IIR_RSVD_IIR_5TO4 register field. */
678 #define ALT_UART_IIR_RSVD_IIR_5TO4_LSB 4
679 /* The Most Significant Bit (MSB) position of the ALT_UART_IIR_RSVD_IIR_5TO4 register field. */
680 #define ALT_UART_IIR_RSVD_IIR_5TO4_MSB 5
681 /* The width in bits of the ALT_UART_IIR_RSVD_IIR_5TO4 register field. */
682 #define ALT_UART_IIR_RSVD_IIR_5TO4_WIDTH 2
683 /* The mask used to set the ALT_UART_IIR_RSVD_IIR_5TO4 register field value. */
684 #define ALT_UART_IIR_RSVD_IIR_5TO4_SET_MSK 0x00000030
685 /* The mask used to clear the ALT_UART_IIR_RSVD_IIR_5TO4 register field value. */
686 #define ALT_UART_IIR_RSVD_IIR_5TO4_CLR_MSK 0xffffffcf
687 /* The reset value of the ALT_UART_IIR_RSVD_IIR_5TO4 register field. */
688 #define ALT_UART_IIR_RSVD_IIR_5TO4_RESET 0x0
689 /* Extracts the ALT_UART_IIR_RSVD_IIR_5TO4 field value from a register. */
690 #define ALT_UART_IIR_RSVD_IIR_5TO4_GET(value) (((value) & 0x00000030) >> 4)
691 /* Produces a ALT_UART_IIR_RSVD_IIR_5TO4 register field value suitable for setting the register. */
692 #define ALT_UART_IIR_RSVD_IIR_5TO4_SET(value) (((value) << 4) & 0x00000030)
693 
694 /*
695  * Field : FIFOSE
696  *
697  * Bits[7:6], FIFO's Enabled (or FIFOSE):
698  *
699  * This is used to indicate whether the FIFO's are enabled or disabled.
700  *
701  * 00 = disabled.
702  *
703  * 11 = enabled
704  *
705  * Field Enumeration Values:
706  *
707  * Enum | Value | Description
708  * :-------------------------------|:------|:-------------------
709  * ALT_UART_IIR_FIFOSE_E_DISABLED | 0x0 | FIFOs are disabled
710  * ALT_UART_IIR_FIFOSE_E_ENABLED | 0x3 | FIFOs are enabled
711  *
712  * Field Access Macros:
713  *
714  */
715 /*
716  * Enumerated value for register field ALT_UART_IIR_FIFOSE
717  *
718  * FIFOs are disabled
719  */
720 #define ALT_UART_IIR_FIFOSE_E_DISABLED 0x0
721 /*
722  * Enumerated value for register field ALT_UART_IIR_FIFOSE
723  *
724  * FIFOs are enabled
725  */
726 #define ALT_UART_IIR_FIFOSE_E_ENABLED 0x3
727 
728 /* The Least Significant Bit (LSB) position of the ALT_UART_IIR_FIFOSE register field. */
729 #define ALT_UART_IIR_FIFOSE_LSB 6
730 /* The Most Significant Bit (MSB) position of the ALT_UART_IIR_FIFOSE register field. */
731 #define ALT_UART_IIR_FIFOSE_MSB 7
732 /* The width in bits of the ALT_UART_IIR_FIFOSE register field. */
733 #define ALT_UART_IIR_FIFOSE_WIDTH 2
734 /* The mask used to set the ALT_UART_IIR_FIFOSE register field value. */
735 #define ALT_UART_IIR_FIFOSE_SET_MSK 0x000000c0
736 /* The mask used to clear the ALT_UART_IIR_FIFOSE register field value. */
737 #define ALT_UART_IIR_FIFOSE_CLR_MSK 0xffffff3f
738 /* The reset value of the ALT_UART_IIR_FIFOSE register field. */
739 #define ALT_UART_IIR_FIFOSE_RESET 0x0
740 /* Extracts the ALT_UART_IIR_FIFOSE field value from a register. */
741 #define ALT_UART_IIR_FIFOSE_GET(value) (((value) & 0x000000c0) >> 6)
742 /* Produces a ALT_UART_IIR_FIFOSE register field value suitable for setting the register. */
743 #define ALT_UART_IIR_FIFOSE_SET(value) (((value) << 6) & 0x000000c0)
744 
745 /*
746  * Field : RSVD_IIR_31to8
747  *
748  * Reserved bits [31:8] - Read Only
749  *
750  * Field Access Macros:
751  *
752  */
753 /* The Least Significant Bit (LSB) position of the ALT_UART_IIR_RSVD_IIR_31TO8 register field. */
754 #define ALT_UART_IIR_RSVD_IIR_31TO8_LSB 8
755 /* The Most Significant Bit (MSB) position of the ALT_UART_IIR_RSVD_IIR_31TO8 register field. */
756 #define ALT_UART_IIR_RSVD_IIR_31TO8_MSB 31
757 /* The width in bits of the ALT_UART_IIR_RSVD_IIR_31TO8 register field. */
758 #define ALT_UART_IIR_RSVD_IIR_31TO8_WIDTH 24
759 /* The mask used to set the ALT_UART_IIR_RSVD_IIR_31TO8 register field value. */
760 #define ALT_UART_IIR_RSVD_IIR_31TO8_SET_MSK 0xffffff00
761 /* The mask used to clear the ALT_UART_IIR_RSVD_IIR_31TO8 register field value. */
762 #define ALT_UART_IIR_RSVD_IIR_31TO8_CLR_MSK 0x000000ff
763 /* The reset value of the ALT_UART_IIR_RSVD_IIR_31TO8 register field. */
764 #define ALT_UART_IIR_RSVD_IIR_31TO8_RESET 0x0
765 /* Extracts the ALT_UART_IIR_RSVD_IIR_31TO8 field value from a register. */
766 #define ALT_UART_IIR_RSVD_IIR_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
767 /* Produces a ALT_UART_IIR_RSVD_IIR_31TO8 register field value suitable for setting the register. */
768 #define ALT_UART_IIR_RSVD_IIR_31TO8_SET(value) (((value) << 8) & 0xffffff00)
769 
770 #ifndef __ASSEMBLY__
771 /*
772  * WARNING: The C register and register group struct declarations are provided for
773  * convenience and illustrative purposes. They should, however, be used with
774  * caution as the C language standard provides no guarantees about the alignment or
775  * atomicity of device memory accesses. The recommended practice for coding device
776  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
777  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
778  * alt_write_dword() functions for 64 bit registers.
779  *
780  * The struct declaration for register ALT_UART_IIR.
781  */
782 struct ALT_UART_IIR_s
783 {
784  const volatile uint32_t IID : 4; /* ALT_UART_IIR_IID */
785  const volatile uint32_t RSVD_IIR_5to4 : 2; /* ALT_UART_IIR_RSVD_IIR_5TO4 */
786  const volatile uint32_t FIFOSE : 2; /* ALT_UART_IIR_FIFOSE */
787  const volatile uint32_t RSVD_IIR_31to8 : 24; /* ALT_UART_IIR_RSVD_IIR_31TO8 */
788 };
789 
790 /* The typedef declaration for register ALT_UART_IIR. */
791 typedef struct ALT_UART_IIR_s ALT_UART_IIR_t;
792 #endif /* __ASSEMBLY__ */
793 
794 /* The reset value of the ALT_UART_IIR register. */
795 #define ALT_UART_IIR_RESET 0x00000001
796 /* The byte offset of the ALT_UART_IIR register from the beginning of the component. */
797 #define ALT_UART_IIR_OFST 0x8
798 /* The address of the ALT_UART_IIR register. */
799 #define ALT_UART_IIR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IIR_OFST))
800 
801 /*
802  * Register : Line Control Register - LCR
803  *
804  * Line Control Register
805  *
806  * Register Layout
807  *
808  * Bits | Access | Reset | Description
809  * :-------|:-------|:------|:----------------------------
810  * [1:0] | RW | 0x0 | ALT_UART_LCR_DLS
811  * [2] | RW | 0x0 | ALT_UART_LCR_STOP
812  * [3] | RW | 0x0 | ALT_UART_LCR_PEN
813  * [4] | RW | 0x0 | ALT_UART_LCR_EPS
814  * [5] | RW | 0x0 | ALT_UART_LCR_SP
815  * [6] | RW | 0x0 | ALT_UART_LCR_BREAK
816  * [7] | RW | 0x0 | ALT_UART_LCR_DLAB
817  * [31:8] | R | 0x0 | ALT_UART_LCR_RSVD_LCR_31TO8
818  *
819  */
820 /*
821  * Field : DLS
822  *
823  * Data Length Select.
824  *
825  * If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy
826  * (USR[0]
827  *
828  * is zero), otherwise always writable, always readable. This is used to select the
829  *
830  * number of data bits per character that the peripheral will transmit and receive.
831  *
832  * The number of bit that may be selected are as follows:
833  *
834  * 00 = 5 bits
835  *
836  * 01 = 6 bits
837  *
838  * 10 = 7 bits
839  *
840  * 11 = 8 bits
841  *
842  * Field Enumeration Values:
843  *
844  * Enum | Value | Description
845  * :------------------------------|:------|:--------------------------
846  * ALT_UART_LCR_DLS_E_CHAR_5BITS | 0x0 | 5 data bits per character
847  * ALT_UART_LCR_DLS_E_CHAR_6BITS | 0x1 | 6 data bits per character
848  * ALT_UART_LCR_DLS_E_CHAR_7BITS | 0x2 | 7 data bits per character
849  * ALT_UART_LCR_DLS_E_CHAR_8BITS | 0x3 | 8 data bits per character
850  *
851  * Field Access Macros:
852  *
853  */
854 /*
855  * Enumerated value for register field ALT_UART_LCR_DLS
856  *
857  * 5 data bits per character
858  */
859 #define ALT_UART_LCR_DLS_E_CHAR_5BITS 0x0
860 /*
861  * Enumerated value for register field ALT_UART_LCR_DLS
862  *
863  * 6 data bits per character
864  */
865 #define ALT_UART_LCR_DLS_E_CHAR_6BITS 0x1
866 /*
867  * Enumerated value for register field ALT_UART_LCR_DLS
868  *
869  * 7 data bits per character
870  */
871 #define ALT_UART_LCR_DLS_E_CHAR_7BITS 0x2
872 /*
873  * Enumerated value for register field ALT_UART_LCR_DLS
874  *
875  * 8 data bits per character
876  */
877 #define ALT_UART_LCR_DLS_E_CHAR_8BITS 0x3
878 
879 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLS register field. */
880 #define ALT_UART_LCR_DLS_LSB 0
881 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLS register field. */
882 #define ALT_UART_LCR_DLS_MSB 1
883 /* The width in bits of the ALT_UART_LCR_DLS register field. */
884 #define ALT_UART_LCR_DLS_WIDTH 2
885 /* The mask used to set the ALT_UART_LCR_DLS register field value. */
886 #define ALT_UART_LCR_DLS_SET_MSK 0x00000003
887 /* The mask used to clear the ALT_UART_LCR_DLS register field value. */
888 #define ALT_UART_LCR_DLS_CLR_MSK 0xfffffffc
889 /* The reset value of the ALT_UART_LCR_DLS register field. */
890 #define ALT_UART_LCR_DLS_RESET 0x0
891 /* Extracts the ALT_UART_LCR_DLS field value from a register. */
892 #define ALT_UART_LCR_DLS_GET(value) (((value) & 0x00000003) >> 0)
893 /* Produces a ALT_UART_LCR_DLS register field value suitable for setting the register. */
894 #define ALT_UART_LCR_DLS_SET(value) (((value) << 0) & 0x00000003)
895 
896 /*
897  * Field : STOP
898  *
899  * Number of stop bits.
900  *
901  * If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy
902  * (USR[0]
903  *
904  * is zero), otherwise always writable, always readable. This is used to select the
905  * number
906  *
907  * of stop bits per character that the peripheral will transmit and receive. If set
908  * to
909  *
910  * zero, one stop bit is transmitted in the serial data. If set to one and the data
911  *
912  * bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is
913  * transmitted.
914  *
915  * Otherwise, two stop bits are transmitted.
916  *
917  * Note that regardless of the number of stop bits selected the receiver will only
918  *
919  * check the first stop bit.
920  *
921  * 0 = 1 stop bit
922  *
923  * 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero,
924  *
925  * else 2 stop bit
926  *
927  * Field Enumeration Values:
928  *
929  * Enum | Value | Description
930  * :----------------------------------------|:------|:------------------------------------------------
931  * ALT_UART_LCR_STOP_E_STOP_1BIT | 0x0 | 1 stop bit
932  * ALT_UART_LCR_STOP_E_STOP_1_5BIT_OR_2BIT | 0x1 | 1.5 stop bits when DLS (LCR[1:0]) is zero, else
933  * : | | 2 stop bit
934  *
935  * Field Access Macros:
936  *
937  */
938 /*
939  * Enumerated value for register field ALT_UART_LCR_STOP
940  *
941  * 1 stop bit
942  */
943 #define ALT_UART_LCR_STOP_E_STOP_1BIT 0x0
944 /*
945  * Enumerated value for register field ALT_UART_LCR_STOP
946  *
947  * 1.5 stop bits when DLS (LCR[1:0]) is zero,
948  *
949  * else 2 stop bit
950  */
951 #define ALT_UART_LCR_STOP_E_STOP_1_5BIT_OR_2BIT 0x1
952 
953 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_STOP register field. */
954 #define ALT_UART_LCR_STOP_LSB 2
955 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_STOP register field. */
956 #define ALT_UART_LCR_STOP_MSB 2
957 /* The width in bits of the ALT_UART_LCR_STOP register field. */
958 #define ALT_UART_LCR_STOP_WIDTH 1
959 /* The mask used to set the ALT_UART_LCR_STOP register field value. */
960 #define ALT_UART_LCR_STOP_SET_MSK 0x00000004
961 /* The mask used to clear the ALT_UART_LCR_STOP register field value. */
962 #define ALT_UART_LCR_STOP_CLR_MSK 0xfffffffb
963 /* The reset value of the ALT_UART_LCR_STOP register field. */
964 #define ALT_UART_LCR_STOP_RESET 0x0
965 /* Extracts the ALT_UART_LCR_STOP field value from a register. */
966 #define ALT_UART_LCR_STOP_GET(value) (((value) & 0x00000004) >> 2)
967 /* Produces a ALT_UART_LCR_STOP register field value suitable for setting the register. */
968 #define ALT_UART_LCR_STOP_SET(value) (((value) << 2) & 0x00000004)
969 
970 /*
971  * Field : PEN
972  *
973  * Parity Enable.
974  *
975  * If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy
976  * (USR[0]
977  *
978  * is zero), otherwise always writable, always readable. This bit is used to enable
979  *
980  * and disable parity generation and detection in transmitted and received serial
981  *
982  * character respectively.
983  *
984  * 0 = parity disabled
985  *
986  * 1 = parity enabled
987  *
988  * Field Enumeration Values:
989  *
990  * Enum | Value | Description
991  * :----------------------------|:------|:---------------
992  * ALT_UART_LCR_PEN_E_DISABLED | 0x0 | disable parity
993  * ALT_UART_LCR_PEN_E_ENABLED | 0x1 | enable parity
994  *
995  * Field Access Macros:
996  *
997  */
998 /*
999  * Enumerated value for register field ALT_UART_LCR_PEN
1000  *
1001  * disable parity
1002  */
1003 #define ALT_UART_LCR_PEN_E_DISABLED 0x0
1004 /*
1005  * Enumerated value for register field ALT_UART_LCR_PEN
1006  *
1007  * enable parity
1008  */
1009 #define ALT_UART_LCR_PEN_E_ENABLED 0x1
1010 
1011 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_PEN register field. */
1012 #define ALT_UART_LCR_PEN_LSB 3
1013 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_PEN register field. */
1014 #define ALT_UART_LCR_PEN_MSB 3
1015 /* The width in bits of the ALT_UART_LCR_PEN register field. */
1016 #define ALT_UART_LCR_PEN_WIDTH 1
1017 /* The mask used to set the ALT_UART_LCR_PEN register field value. */
1018 #define ALT_UART_LCR_PEN_SET_MSK 0x00000008
1019 /* The mask used to clear the ALT_UART_LCR_PEN register field value. */
1020 #define ALT_UART_LCR_PEN_CLR_MSK 0xfffffff7
1021 /* The reset value of the ALT_UART_LCR_PEN register field. */
1022 #define ALT_UART_LCR_PEN_RESET 0x0
1023 /* Extracts the ALT_UART_LCR_PEN field value from a register. */
1024 #define ALT_UART_LCR_PEN_GET(value) (((value) & 0x00000008) >> 3)
1025 /* Produces a ALT_UART_LCR_PEN register field value suitable for setting the register. */
1026 #define ALT_UART_LCR_PEN_SET(value) (((value) << 3) & 0x00000008)
1027 
1028 /*
1029  * Field : EPS
1030  *
1031  * Even Parity Select.
1032  *
1033  * If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy
1034  * (USR[0]
1035  *
1036  * is zero), otherwise always writable, always readable. This is used to select
1037  *
1038  * between even and odd parity, when parity is enabled (PEN set to one). If set to
1039  *
1040  * one, an even number of logic '1's is transmitted or checked. If set to zero, an
1041  *
1042  * odd number of logic '1's is transmitted or checked.
1043  *
1044  * Field Enumeration Values:
1045  *
1046  * Enum | Value | Description
1047  * :-------------------------------|:------|:-----------------------------------------
1048  * ALT_UART_LCR_EPS_E_ODD_PARITY | 0x0 | an odd parity is transmitted or checked
1049  * ALT_UART_LCR_EPS_E_EVEN_PARITY | 0x1 | an even parity is transmitted or checked
1050  *
1051  * Field Access Macros:
1052  *
1053  */
1054 /*
1055  * Enumerated value for register field ALT_UART_LCR_EPS
1056  *
1057  * an odd parity is transmitted or checked
1058  */
1059 #define ALT_UART_LCR_EPS_E_ODD_PARITY 0x0
1060 /*
1061  * Enumerated value for register field ALT_UART_LCR_EPS
1062  *
1063  * an even parity is transmitted or checked
1064  */
1065 #define ALT_UART_LCR_EPS_E_EVEN_PARITY 0x1
1066 
1067 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_EPS register field. */
1068 #define ALT_UART_LCR_EPS_LSB 4
1069 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_EPS register field. */
1070 #define ALT_UART_LCR_EPS_MSB 4
1071 /* The width in bits of the ALT_UART_LCR_EPS register field. */
1072 #define ALT_UART_LCR_EPS_WIDTH 1
1073 /* The mask used to set the ALT_UART_LCR_EPS register field value. */
1074 #define ALT_UART_LCR_EPS_SET_MSK 0x00000010
1075 /* The mask used to clear the ALT_UART_LCR_EPS register field value. */
1076 #define ALT_UART_LCR_EPS_CLR_MSK 0xffffffef
1077 /* The reset value of the ALT_UART_LCR_EPS register field. */
1078 #define ALT_UART_LCR_EPS_RESET 0x0
1079 /* Extracts the ALT_UART_LCR_EPS field value from a register. */
1080 #define ALT_UART_LCR_EPS_GET(value) (((value) & 0x00000010) >> 4)
1081 /* Produces a ALT_UART_LCR_EPS register field value suitable for setting the register. */
1082 #define ALT_UART_LCR_EPS_SET(value) (((value) << 4) & 0x00000010)
1083 
1084 /*
1085  * Field : SP
1086  *
1087  * From DW_apb_uart_regfile.sv:
1088  *
1089  * // aaraujo @ 17/05/2011 : CRM_9000431453
1090  *
1091  * // Stick parity lcr_ir[5] is now programmable
1092  *
1093  * lcr_ir[5:0] <= ipwdata[5:0];
1094  *
1095  * Field Enumeration Values:
1096  *
1097  * Enum | Value | Description
1098  * :---------------------------|:------|:----------------------
1099  * ALT_UART_LCR_SP_E_DISABLED | 0x0 | Stick parity disabled
1100  * ALT_UART_LCR_SP_E_ENABLED | 0x1 | Stick parity enabled
1101  *
1102  * Field Access Macros:
1103  *
1104  */
1105 /*
1106  * Enumerated value for register field ALT_UART_LCR_SP
1107  *
1108  * Stick parity disabled
1109  */
1110 #define ALT_UART_LCR_SP_E_DISABLED 0x0
1111 /*
1112  * Enumerated value for register field ALT_UART_LCR_SP
1113  *
1114  * Stick parity enabled
1115  */
1116 #define ALT_UART_LCR_SP_E_ENABLED 0x1
1117 
1118 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_SP register field. */
1119 #define ALT_UART_LCR_SP_LSB 5
1120 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_SP register field. */
1121 #define ALT_UART_LCR_SP_MSB 5
1122 /* The width in bits of the ALT_UART_LCR_SP register field. */
1123 #define ALT_UART_LCR_SP_WIDTH 1
1124 /* The mask used to set the ALT_UART_LCR_SP register field value. */
1125 #define ALT_UART_LCR_SP_SET_MSK 0x00000020
1126 /* The mask used to clear the ALT_UART_LCR_SP register field value. */
1127 #define ALT_UART_LCR_SP_CLR_MSK 0xffffffdf
1128 /* The reset value of the ALT_UART_LCR_SP register field. */
1129 #define ALT_UART_LCR_SP_RESET 0x0
1130 /* Extracts the ALT_UART_LCR_SP field value from a register. */
1131 #define ALT_UART_LCR_SP_GET(value) (((value) & 0x00000020) >> 5)
1132 /* Produces a ALT_UART_LCR_SP register field value suitable for setting the register. */
1133 #define ALT_UART_LCR_SP_SET(value) (((value) << 5) & 0x00000020)
1134 
1135 /*
1136  * Field : Break
1137  *
1138  * Break Control Bit.
1139  *
1140  * This is used to cause a break condition to be transmitted to the receiving
1141  * device.
1142  *
1143  * If set to one the serial output is forced to the spacing (logic 0) state. When
1144  *
1145  * not in Loopback Mode, as determined by MCR[4], the sout line is forced low until
1146  *
1147  * the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one)
1148  *
1149  * the sir_out_n line is continuously pulsed. When in Loopback Mode, the break
1150  *
1151  * condition is internally looped back to the receiver and the sir_out_n line is
1152  *
1153  * forced low.
1154  *
1155  * Field Enumeration Values:
1156  *
1157  * Enum | Value | Description
1158  * :------------------------------|:------|:------------------------------------------------
1159  * ALT_UART_LCR_BREAK_E_DISABLED | 0x0 | Serial output is released for data transmission
1160  * ALT_UART_LCR_BREAK_E_ENABLED | 0x1 | Serial output is forced to spacing state
1161  *
1162  * Field Access Macros:
1163  *
1164  */
1165 /*
1166  * Enumerated value for register field ALT_UART_LCR_BREAK
1167  *
1168  * Serial output is released for data transmission
1169  */
1170 #define ALT_UART_LCR_BREAK_E_DISABLED 0x0
1171 /*
1172  * Enumerated value for register field ALT_UART_LCR_BREAK
1173  *
1174  * Serial output is forced to spacing state
1175  */
1176 #define ALT_UART_LCR_BREAK_E_ENABLED 0x1
1177 
1178 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_BREAK register field. */
1179 #define ALT_UART_LCR_BREAK_LSB 6
1180 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_BREAK register field. */
1181 #define ALT_UART_LCR_BREAK_MSB 6
1182 /* The width in bits of the ALT_UART_LCR_BREAK register field. */
1183 #define ALT_UART_LCR_BREAK_WIDTH 1
1184 /* The mask used to set the ALT_UART_LCR_BREAK register field value. */
1185 #define ALT_UART_LCR_BREAK_SET_MSK 0x00000040
1186 /* The mask used to clear the ALT_UART_LCR_BREAK register field value. */
1187 #define ALT_UART_LCR_BREAK_CLR_MSK 0xffffffbf
1188 /* The reset value of the ALT_UART_LCR_BREAK register field. */
1189 #define ALT_UART_LCR_BREAK_RESET 0x0
1190 /* Extracts the ALT_UART_LCR_BREAK field value from a register. */
1191 #define ALT_UART_LCR_BREAK_GET(value) (((value) & 0x00000040) >> 6)
1192 /* Produces a ALT_UART_LCR_BREAK register field value suitable for setting the register. */
1193 #define ALT_UART_LCR_BREAK_SET(value) (((value) << 6) & 0x00000040)
1194 
1195 /*
1196  * Field : DLAB
1197  *
1198  * Divisor Latch Access Bit.
1199  *
1200  * If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy
1201  * (USR[0]
1202  *
1203  * is zero), otherwise always writable, always readable. This bit is used to enable
1204  *
1205  * reading and writing of the Divisor Latch register (DLL and DLH) to set the baud
1206  *
1207  * rate of the UART. This bit must be cleared after initial baud rate setup in
1208  * order
1209  *
1210  * to access other registers.
1211  *
1212  * Field Enumeration Values:
1213  *
1214  * Enum | Value | Description
1215  * :-----------------------------|:------|:----------------------------------------------
1216  * ALT_UART_LCR_DLAB_E_DISABLED | 0x0 | Divisor Latch register is writable only when
1217  * : | | UART Not BUSY
1218  * ALT_UART_LCR_DLAB_E_ENABLED | 0x1 | Divisor Latch register is always readable and
1219  * : | | writable
1220  *
1221  * Field Access Macros:
1222  *
1223  */
1224 /*
1225  * Enumerated value for register field ALT_UART_LCR_DLAB
1226  *
1227  * Divisor Latch register is writable only when UART Not BUSY
1228  */
1229 #define ALT_UART_LCR_DLAB_E_DISABLED 0x0
1230 /*
1231  * Enumerated value for register field ALT_UART_LCR_DLAB
1232  *
1233  * Divisor Latch register is always readable and writable
1234  */
1235 #define ALT_UART_LCR_DLAB_E_ENABLED 0x1
1236 
1237 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLAB register field. */
1238 #define ALT_UART_LCR_DLAB_LSB 7
1239 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLAB register field. */
1240 #define ALT_UART_LCR_DLAB_MSB 7
1241 /* The width in bits of the ALT_UART_LCR_DLAB register field. */
1242 #define ALT_UART_LCR_DLAB_WIDTH 1
1243 /* The mask used to set the ALT_UART_LCR_DLAB register field value. */
1244 #define ALT_UART_LCR_DLAB_SET_MSK 0x00000080
1245 /* The mask used to clear the ALT_UART_LCR_DLAB register field value. */
1246 #define ALT_UART_LCR_DLAB_CLR_MSK 0xffffff7f
1247 /* The reset value of the ALT_UART_LCR_DLAB register field. */
1248 #define ALT_UART_LCR_DLAB_RESET 0x0
1249 /* Extracts the ALT_UART_LCR_DLAB field value from a register. */
1250 #define ALT_UART_LCR_DLAB_GET(value) (((value) & 0x00000080) >> 7)
1251 /* Produces a ALT_UART_LCR_DLAB register field value suitable for setting the register. */
1252 #define ALT_UART_LCR_DLAB_SET(value) (((value) << 7) & 0x00000080)
1253 
1254 /*
1255  * Field : RSVD_LCR_31to8
1256  *
1257  * Reserved bits [31:8] - Read Only
1258  *
1259  * Field Access Macros:
1260  *
1261  */
1262 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_RSVD_LCR_31TO8 register field. */
1263 #define ALT_UART_LCR_RSVD_LCR_31TO8_LSB 8
1264 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_RSVD_LCR_31TO8 register field. */
1265 #define ALT_UART_LCR_RSVD_LCR_31TO8_MSB 31
1266 /* The width in bits of the ALT_UART_LCR_RSVD_LCR_31TO8 register field. */
1267 #define ALT_UART_LCR_RSVD_LCR_31TO8_WIDTH 24
1268 /* The mask used to set the ALT_UART_LCR_RSVD_LCR_31TO8 register field value. */
1269 #define ALT_UART_LCR_RSVD_LCR_31TO8_SET_MSK 0xffffff00
1270 /* The mask used to clear the ALT_UART_LCR_RSVD_LCR_31TO8 register field value. */
1271 #define ALT_UART_LCR_RSVD_LCR_31TO8_CLR_MSK 0x000000ff
1272 /* The reset value of the ALT_UART_LCR_RSVD_LCR_31TO8 register field. */
1273 #define ALT_UART_LCR_RSVD_LCR_31TO8_RESET 0x0
1274 /* Extracts the ALT_UART_LCR_RSVD_LCR_31TO8 field value from a register. */
1275 #define ALT_UART_LCR_RSVD_LCR_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
1276 /* Produces a ALT_UART_LCR_RSVD_LCR_31TO8 register field value suitable for setting the register. */
1277 #define ALT_UART_LCR_RSVD_LCR_31TO8_SET(value) (((value) << 8) & 0xffffff00)
1278 
1279 #ifndef __ASSEMBLY__
1280 /*
1281  * WARNING: The C register and register group struct declarations are provided for
1282  * convenience and illustrative purposes. They should, however, be used with
1283  * caution as the C language standard provides no guarantees about the alignment or
1284  * atomicity of device memory accesses. The recommended practice for coding device
1285  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1286  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1287  * alt_write_dword() functions for 64 bit registers.
1288  *
1289  * The struct declaration for register ALT_UART_LCR.
1290  */
1291 struct ALT_UART_LCR_s
1292 {
1293  volatile uint32_t DLS : 2; /* ALT_UART_LCR_DLS */
1294  volatile uint32_t STOP : 1; /* ALT_UART_LCR_STOP */
1295  volatile uint32_t PEN : 1; /* ALT_UART_LCR_PEN */
1296  volatile uint32_t EPS : 1; /* ALT_UART_LCR_EPS */
1297  volatile uint32_t SP : 1; /* ALT_UART_LCR_SP */
1298  volatile uint32_t Break : 1; /* ALT_UART_LCR_BREAK */
1299  volatile uint32_t DLAB : 1; /* ALT_UART_LCR_DLAB */
1300  const volatile uint32_t RSVD_LCR_31to8 : 24; /* ALT_UART_LCR_RSVD_LCR_31TO8 */
1301 };
1302 
1303 /* The typedef declaration for register ALT_UART_LCR. */
1304 typedef struct ALT_UART_LCR_s ALT_UART_LCR_t;
1305 #endif /* __ASSEMBLY__ */
1306 
1307 /* The reset value of the ALT_UART_LCR register. */
1308 #define ALT_UART_LCR_RESET 0x00000000
1309 /* The byte offset of the ALT_UART_LCR register from the beginning of the component. */
1310 #define ALT_UART_LCR_OFST 0xc
1311 /* The address of the ALT_UART_LCR register. */
1312 #define ALT_UART_LCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LCR_OFST))
1313 
1314 /*
1315  * Register : Modem Control Register - MCR
1316  *
1317  * Modem Control Register
1318  *
1319  * Register Layout
1320  *
1321  * Bits | Access | Reset | Description
1322  * :-------|:-------|:------|:----------------------------
1323  * [0] | RW | 0x0 | ALT_UART_MCR_DTR
1324  * [1] | RW | 0x0 | ALT_UART_MCR_RTS
1325  * [2] | RW | 0x0 | ALT_UART_MCR_OUT1
1326  * [3] | RW | 0x0 | ALT_UART_MCR_OUT2
1327  * [4] | RW | 0x0 | ALT_UART_MCR_LOOPBACK
1328  * [5] | RW | 0x0 | ALT_UART_MCR_AFCE
1329  * [6] | R | 0x0 | ALT_UART_MCR_SIRE
1330  * [31:7] | R | 0x0 | ALT_UART_MCR_RSVD_MCR_31TO7
1331  *
1332  */
1333 /*
1334  * Field : DTR
1335  *
1336  * Data Terminal Ready.
1337  *
1338  * This is used to directly control the Data Terminal Ready (dtr_n) output. The
1339  * value
1340  *
1341  * written to this location is inverted and driven out on dtr_n, that is:
1342  *
1343  * 0 = dtr_n de-asserted (logic 1)
1344  *
1345  * 1 = dtr_n asserted (logic 0)
1346  *
1347  * The Data Terminal Ready output is used to inform the modem or data set that the
1348  *
1349  * UART is ready to establish communications. Note that in Loopback mode (MCR[4]
1350  *
1351  * set to one), the dtr_n output is held inactive high while the value of this
1352  *
1353  * location is internally looped back to an input.
1354  *
1355  * Field Enumeration Values:
1356  *
1357  * Enum | Value | Description
1358  * :----------------------------|:------|:-----------------------------------------------
1359  * ALT_UART_MCR_DTR_E_INACTIVE | 0x0 | Data Terminal Ready dtr_n de-asserted (logic1)
1360  * ALT_UART_MCR_DTR_E_ACTIVE | 0x1 | Data Terminal Ready dtr_n asserted (logic 0)
1361  *
1362  * Field Access Macros:
1363  *
1364  */
1365 /*
1366  * Enumerated value for register field ALT_UART_MCR_DTR
1367  *
1368  * Data Terminal Ready dtr_n de-asserted (logic1)
1369  */
1370 #define ALT_UART_MCR_DTR_E_INACTIVE 0x0
1371 /*
1372  * Enumerated value for register field ALT_UART_MCR_DTR
1373  *
1374  * Data Terminal Ready dtr_n asserted (logic 0)
1375  */
1376 #define ALT_UART_MCR_DTR_E_ACTIVE 0x1
1377 
1378 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_DTR register field. */
1379 #define ALT_UART_MCR_DTR_LSB 0
1380 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_DTR register field. */
1381 #define ALT_UART_MCR_DTR_MSB 0
1382 /* The width in bits of the ALT_UART_MCR_DTR register field. */
1383 #define ALT_UART_MCR_DTR_WIDTH 1
1384 /* The mask used to set the ALT_UART_MCR_DTR register field value. */
1385 #define ALT_UART_MCR_DTR_SET_MSK 0x00000001
1386 /* The mask used to clear the ALT_UART_MCR_DTR register field value. */
1387 #define ALT_UART_MCR_DTR_CLR_MSK 0xfffffffe
1388 /* The reset value of the ALT_UART_MCR_DTR register field. */
1389 #define ALT_UART_MCR_DTR_RESET 0x0
1390 /* Extracts the ALT_UART_MCR_DTR field value from a register. */
1391 #define ALT_UART_MCR_DTR_GET(value) (((value) & 0x00000001) >> 0)
1392 /* Produces a ALT_UART_MCR_DTR register field value suitable for setting the register. */
1393 #define ALT_UART_MCR_DTR_SET(value) (((value) << 0) & 0x00000001)
1394 
1395 /*
1396  * Field : RTS
1397  *
1398  * Request to Send.
1399  *
1400  * This is used to directly control the Request to Send (rts_n) output. The Request
1401  *
1402  * To Send (rts_n) output is used to inform the modem or data set that the UART is
1403  *
1404  * ready to exchange data.
1405  *
1406  * When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal
1407  *
1408  * is set low by programming MCR[1] (RTS) to a high.
1409  *
1410  * In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and
1411  *
1412  * FIFO's enable (FCR[0] set to one), the rts_n output is controlled in the same
1413  * way,
1414  *
1415  * but is also gated with the receiver FIFO threshold trigger (rts_n is inactive
1416  * high
1417  *
1418  * when above the threshold).
1419  *
1420  * The rts_n signal will be de-asserted when MCR[1] is set low.
1421  *
1422  * Note that in Loopback mode (MCR[4] set to one), the rts_n output is held
1423  * inactive
1424  *
1425  * high while the value of this location is internally looped back to an input.
1426  *
1427  * Field Enumeration Values:
1428  *
1429  * Enum | Value | Description
1430  * :----------------------------|:------|:--------------------------------------------
1431  * ALT_UART_MCR_RTS_E_INACTIVE | 0x0 | Request to Send rts_n de-asserted (logic 1)
1432  * ALT_UART_MCR_RTS_E_ACTIVE | 0x1 | Request to Send rts_n asserted (logic 0)
1433  *
1434  * Field Access Macros:
1435  *
1436  */
1437 /*
1438  * Enumerated value for register field ALT_UART_MCR_RTS
1439  *
1440  * Request to Send rts_n de-asserted (logic 1)
1441  */
1442 #define ALT_UART_MCR_RTS_E_INACTIVE 0x0
1443 /*
1444  * Enumerated value for register field ALT_UART_MCR_RTS
1445  *
1446  * Request to Send rts_n asserted (logic 0)
1447  */
1448 #define ALT_UART_MCR_RTS_E_ACTIVE 0x1
1449 
1450 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_RTS register field. */
1451 #define ALT_UART_MCR_RTS_LSB 1
1452 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_RTS register field. */
1453 #define ALT_UART_MCR_RTS_MSB 1
1454 /* The width in bits of the ALT_UART_MCR_RTS register field. */
1455 #define ALT_UART_MCR_RTS_WIDTH 1
1456 /* The mask used to set the ALT_UART_MCR_RTS register field value. */
1457 #define ALT_UART_MCR_RTS_SET_MSK 0x00000002
1458 /* The mask used to clear the ALT_UART_MCR_RTS register field value. */
1459 #define ALT_UART_MCR_RTS_CLR_MSK 0xfffffffd
1460 /* The reset value of the ALT_UART_MCR_RTS register field. */
1461 #define ALT_UART_MCR_RTS_RESET 0x0
1462 /* Extracts the ALT_UART_MCR_RTS field value from a register. */
1463 #define ALT_UART_MCR_RTS_GET(value) (((value) & 0x00000002) >> 1)
1464 /* Produces a ALT_UART_MCR_RTS register field value suitable for setting the register. */
1465 #define ALT_UART_MCR_RTS_SET(value) (((value) << 1) & 0x00000002)
1466 
1467 /*
1468  * Field : OUT1
1469  *
1470  * OUT1.
1471  *
1472  * This is used to directly control the user-designated Output1 (out1_n) output.
1473  * The
1474  *
1475  * value written to this location is inverted and driven out on out1_n, that is:
1476  *
1477  * 0 = out1_n de-asserted (logic 1)
1478  *
1479  * 1 = out1_n asserted (logic 0)
1480  *
1481  * Note that in Loopback mode (MCR[4] set to one), the out1_n output is held
1482  * inactive high
1483  *
1484  * while the value of this location is internally looped back to an input.
1485  *
1486  * Field Enumeration Values:
1487  *
1488  * Enum | Value | Description
1489  * :---------------------------|:------|:-----------------------------
1490  * ALT_UART_MCR_OUT1_E_OUT1_0 | 0x0 | out1_n de-asserted (logic 1)
1491  * ALT_UART_MCR_OUT1_E_OUT1_1 | 0x1 | out1_n asserted (logic 0)
1492  *
1493  * Field Access Macros:
1494  *
1495  */
1496 /*
1497  * Enumerated value for register field ALT_UART_MCR_OUT1
1498  *
1499  * out1_n de-asserted (logic 1)
1500  */
1501 #define ALT_UART_MCR_OUT1_E_OUT1_0 0x0
1502 /*
1503  * Enumerated value for register field ALT_UART_MCR_OUT1
1504  *
1505  * out1_n asserted (logic 0)
1506  */
1507 #define ALT_UART_MCR_OUT1_E_OUT1_1 0x1
1508 
1509 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT1 register field. */
1510 #define ALT_UART_MCR_OUT1_LSB 2
1511 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT1 register field. */
1512 #define ALT_UART_MCR_OUT1_MSB 2
1513 /* The width in bits of the ALT_UART_MCR_OUT1 register field. */
1514 #define ALT_UART_MCR_OUT1_WIDTH 1
1515 /* The mask used to set the ALT_UART_MCR_OUT1 register field value. */
1516 #define ALT_UART_MCR_OUT1_SET_MSK 0x00000004
1517 /* The mask used to clear the ALT_UART_MCR_OUT1 register field value. */
1518 #define ALT_UART_MCR_OUT1_CLR_MSK 0xfffffffb
1519 /* The reset value of the ALT_UART_MCR_OUT1 register field. */
1520 #define ALT_UART_MCR_OUT1_RESET 0x0
1521 /* Extracts the ALT_UART_MCR_OUT1 field value from a register. */
1522 #define ALT_UART_MCR_OUT1_GET(value) (((value) & 0x00000004) >> 2)
1523 /* Produces a ALT_UART_MCR_OUT1 register field value suitable for setting the register. */
1524 #define ALT_UART_MCR_OUT1_SET(value) (((value) << 2) & 0x00000004)
1525 
1526 /*
1527  * Field : OUT2
1528  *
1529  * OUT2.
1530  *
1531  * This is used to directly control the user-designated Output2 (out2_n) output.
1532  * The
1533  *
1534  * value written to this location is inverted and driven out on out2_n, that is:
1535  *
1536  * 0 = out2_n de-asserted (logic 1)
1537  *
1538  * 1 = out2_n asserted (logic 0)
1539  *
1540  * Note that in Loopback mode (MCR[4] set to one), the out2_n output is held
1541  * inactive
1542  *
1543  * high while the value of this location is internally looped back to an input.
1544  *
1545  * Field Enumeration Values:
1546  *
1547  * Enum | Value | Description
1548  * :---------------------------|:------|:-----------------------------
1549  * ALT_UART_MCR_OUT2_E_OUT2_0 | 0x0 | out2_n de-asserted (logic 1)
1550  * ALT_UART_MCR_OUT2_E_OUT2_1 | 0x1 | out2_n asserted (logic 0)
1551  *
1552  * Field Access Macros:
1553  *
1554  */
1555 /*
1556  * Enumerated value for register field ALT_UART_MCR_OUT2
1557  *
1558  * out2_n de-asserted (logic 1)
1559  */
1560 #define ALT_UART_MCR_OUT2_E_OUT2_0 0x0
1561 /*
1562  * Enumerated value for register field ALT_UART_MCR_OUT2
1563  *
1564  * out2_n asserted (logic 0)
1565  */
1566 #define ALT_UART_MCR_OUT2_E_OUT2_1 0x1
1567 
1568 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT2 register field. */
1569 #define ALT_UART_MCR_OUT2_LSB 3
1570 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT2 register field. */
1571 #define ALT_UART_MCR_OUT2_MSB 3
1572 /* The width in bits of the ALT_UART_MCR_OUT2 register field. */
1573 #define ALT_UART_MCR_OUT2_WIDTH 1
1574 /* The mask used to set the ALT_UART_MCR_OUT2 register field value. */
1575 #define ALT_UART_MCR_OUT2_SET_MSK 0x00000008
1576 /* The mask used to clear the ALT_UART_MCR_OUT2 register field value. */
1577 #define ALT_UART_MCR_OUT2_CLR_MSK 0xfffffff7
1578 /* The reset value of the ALT_UART_MCR_OUT2 register field. */
1579 #define ALT_UART_MCR_OUT2_RESET 0x0
1580 /* Extracts the ALT_UART_MCR_OUT2 field value from a register. */
1581 #define ALT_UART_MCR_OUT2_GET(value) (((value) & 0x00000008) >> 3)
1582 /* Produces a ALT_UART_MCR_OUT2 register field value suitable for setting the register. */
1583 #define ALT_UART_MCR_OUT2_SET(value) (((value) << 3) & 0x00000008)
1584 
1585 /*
1586  * Field : LoopBack
1587  *
1588  * LoopBack Bit.
1589  *
1590  * This is used to put the UART into a diagnostic mode for test purposes.
1591  *
1592  * If operating in UART mode (SIR_MODE != Enabled OR NOT active, MCR[6] set to
1593  * zero),
1594  *
1595  * data on the sout line is held high, while serial data output is looped back to
1596  * the
1597  *
1598  * sin line, internally. In this mode all the interrupts are fully functional.
1599  * Also,
1600  *
1601  * in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are
1602  *
1603  * disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are
1604  * looped
1605  *
1606  * back to the inputs, internally.
1607  *
1608  * If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to
1609  * one),
1610  *
1611  * data on the sir_out_n line is held low, while serial data output is inverted and
1612  *
1613  * looped back to the sir_in line.
1614  *
1615  * Field Enumeration Values:
1616  *
1617  * Enum | Value | Description
1618  * :---------------------------------|:------|:-----------------------
1619  * ALT_UART_MCR_LOOPBACK_E_DISABLED | 0x0 | Loopback mode disabled
1620  * ALT_UART_MCR_LOOPBACK_E_ENABLED | 0x1 | Loopback mode enabled
1621  *
1622  * Field Access Macros:
1623  *
1624  */
1625 /*
1626  * Enumerated value for register field ALT_UART_MCR_LOOPBACK
1627  *
1628  * Loopback mode disabled
1629  */
1630 #define ALT_UART_MCR_LOOPBACK_E_DISABLED 0x0
1631 /*
1632  * Enumerated value for register field ALT_UART_MCR_LOOPBACK
1633  *
1634  * Loopback mode enabled
1635  */
1636 #define ALT_UART_MCR_LOOPBACK_E_ENABLED 0x1
1637 
1638 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_LOOPBACK register field. */
1639 #define ALT_UART_MCR_LOOPBACK_LSB 4
1640 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_LOOPBACK register field. */
1641 #define ALT_UART_MCR_LOOPBACK_MSB 4
1642 /* The width in bits of the ALT_UART_MCR_LOOPBACK register field. */
1643 #define ALT_UART_MCR_LOOPBACK_WIDTH 1
1644 /* The mask used to set the ALT_UART_MCR_LOOPBACK register field value. */
1645 #define ALT_UART_MCR_LOOPBACK_SET_MSK 0x00000010
1646 /* The mask used to clear the ALT_UART_MCR_LOOPBACK register field value. */
1647 #define ALT_UART_MCR_LOOPBACK_CLR_MSK 0xffffffef
1648 /* The reset value of the ALT_UART_MCR_LOOPBACK register field. */
1649 #define ALT_UART_MCR_LOOPBACK_RESET 0x0
1650 /* Extracts the ALT_UART_MCR_LOOPBACK field value from a register. */
1651 #define ALT_UART_MCR_LOOPBACK_GET(value) (((value) & 0x00000010) >> 4)
1652 /* Produces a ALT_UART_MCR_LOOPBACK register field value suitable for setting the register. */
1653 #define ALT_UART_MCR_LOOPBACK_SET(value) (((value) << 4) & 0x00000010)
1654 
1655 /*
1656  * Field : AFCE
1657  *
1658  * Auto Flow Control Enable.
1659  *
1660  * Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are
1661  * enabled
1662  *
1663  * and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features
1664  * are
1665  *
1666  * enabled as described in section 5.6 on page 51.
1667  *
1668  * 0 = Auto Flow Control Mode disabled
1669  *
1670  * 1 = Auto Flow Control Mode enabled
1671  *
1672  * Field Enumeration Values:
1673  *
1674  * Enum | Value | Description
1675  * :-----------------------------|:------|:--------------------------------
1676  * ALT_UART_MCR_AFCE_E_DISABLED | 0x0 | Auto Flow Control Mode disabled
1677  * ALT_UART_MCR_AFCE_E_ENABLED | 0x1 | Auto Flow Control Mode enabled
1678  *
1679  * Field Access Macros:
1680  *
1681  */
1682 /*
1683  * Enumerated value for register field ALT_UART_MCR_AFCE
1684  *
1685  * Auto Flow Control Mode disabled
1686  */
1687 #define ALT_UART_MCR_AFCE_E_DISABLED 0x0
1688 /*
1689  * Enumerated value for register field ALT_UART_MCR_AFCE
1690  *
1691  * Auto Flow Control Mode enabled
1692  */
1693 #define ALT_UART_MCR_AFCE_E_ENABLED 0x1
1694 
1695 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_AFCE register field. */
1696 #define ALT_UART_MCR_AFCE_LSB 5
1697 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_AFCE register field. */
1698 #define ALT_UART_MCR_AFCE_MSB 5
1699 /* The width in bits of the ALT_UART_MCR_AFCE register field. */
1700 #define ALT_UART_MCR_AFCE_WIDTH 1
1701 /* The mask used to set the ALT_UART_MCR_AFCE register field value. */
1702 #define ALT_UART_MCR_AFCE_SET_MSK 0x00000020
1703 /* The mask used to clear the ALT_UART_MCR_AFCE register field value. */
1704 #define ALT_UART_MCR_AFCE_CLR_MSK 0xffffffdf
1705 /* The reset value of the ALT_UART_MCR_AFCE register field. */
1706 #define ALT_UART_MCR_AFCE_RESET 0x0
1707 /* Extracts the ALT_UART_MCR_AFCE field value from a register. */
1708 #define ALT_UART_MCR_AFCE_GET(value) (((value) & 0x00000020) >> 5)
1709 /* Produces a ALT_UART_MCR_AFCE register field value suitable for setting the register. */
1710 #define ALT_UART_MCR_AFCE_SET(value) (((value) << 5) & 0x00000020)
1711 
1712 /*
1713  * Field : SIRE
1714  *
1715  * SIR Mode Enable.
1716  *
1717  * Writeable only when SIR_MODE == Enabled, always readable. This is used to
1718  * enable/
1719  *
1720  * disable the IrDA SIR Mode features as described in section 5.2 on page 47.
1721  *
1722  * 0 = IrDA SIR Mode disabled
1723  *
1724  * 1 = IrDA SIR Mode enabled
1725  *
1726  * Field Enumeration Values:
1727  *
1728  * Enum | Value | Description
1729  * :-----------------------------|:------|:-----------------------
1730  * ALT_UART_MCR_SIRE_E_DISABLED | 0x0 | IrDA SIR Mode disabled
1731  * ALT_UART_MCR_SIRE_E_ENABLED | 0x1 | IrDA SIR Mode enabled
1732  *
1733  * Field Access Macros:
1734  *
1735  */
1736 /*
1737  * Enumerated value for register field ALT_UART_MCR_SIRE
1738  *
1739  * IrDA SIR Mode disabled
1740  */
1741 #define ALT_UART_MCR_SIRE_E_DISABLED 0x0
1742 /*
1743  * Enumerated value for register field ALT_UART_MCR_SIRE
1744  *
1745  * IrDA SIR Mode enabled
1746  */
1747 #define ALT_UART_MCR_SIRE_E_ENABLED 0x1
1748 
1749 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_SIRE register field. */
1750 #define ALT_UART_MCR_SIRE_LSB 6
1751 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_SIRE register field. */
1752 #define ALT_UART_MCR_SIRE_MSB 6
1753 /* The width in bits of the ALT_UART_MCR_SIRE register field. */
1754 #define ALT_UART_MCR_SIRE_WIDTH 1
1755 /* The mask used to set the ALT_UART_MCR_SIRE register field value. */
1756 #define ALT_UART_MCR_SIRE_SET_MSK 0x00000040
1757 /* The mask used to clear the ALT_UART_MCR_SIRE register field value. */
1758 #define ALT_UART_MCR_SIRE_CLR_MSK 0xffffffbf
1759 /* The reset value of the ALT_UART_MCR_SIRE register field. */
1760 #define ALT_UART_MCR_SIRE_RESET 0x0
1761 /* Extracts the ALT_UART_MCR_SIRE field value from a register. */
1762 #define ALT_UART_MCR_SIRE_GET(value) (((value) & 0x00000040) >> 6)
1763 /* Produces a ALT_UART_MCR_SIRE register field value suitable for setting the register. */
1764 #define ALT_UART_MCR_SIRE_SET(value) (((value) << 6) & 0x00000040)
1765 
1766 /*
1767  * Field : RSVD_MCR_31to7
1768  *
1769  * Reserved bits [31:7] - Read Only
1770  *
1771  * Field Access Macros:
1772  *
1773  */
1774 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_RSVD_MCR_31TO7 register field. */
1775 #define ALT_UART_MCR_RSVD_MCR_31TO7_LSB 7
1776 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_RSVD_MCR_31TO7 register field. */
1777 #define ALT_UART_MCR_RSVD_MCR_31TO7_MSB 31
1778 /* The width in bits of the ALT_UART_MCR_RSVD_MCR_31TO7 register field. */
1779 #define ALT_UART_MCR_RSVD_MCR_31TO7_WIDTH 25
1780 /* The mask used to set the ALT_UART_MCR_RSVD_MCR_31TO7 register field value. */
1781 #define ALT_UART_MCR_RSVD_MCR_31TO7_SET_MSK 0xffffff80
1782 /* The mask used to clear the ALT_UART_MCR_RSVD_MCR_31TO7 register field value. */
1783 #define ALT_UART_MCR_RSVD_MCR_31TO7_CLR_MSK 0x0000007f
1784 /* The reset value of the ALT_UART_MCR_RSVD_MCR_31TO7 register field. */
1785 #define ALT_UART_MCR_RSVD_MCR_31TO7_RESET 0x0
1786 /* Extracts the ALT_UART_MCR_RSVD_MCR_31TO7 field value from a register. */
1787 #define ALT_UART_MCR_RSVD_MCR_31TO7_GET(value) (((value) & 0xffffff80) >> 7)
1788 /* Produces a ALT_UART_MCR_RSVD_MCR_31TO7 register field value suitable for setting the register. */
1789 #define ALT_UART_MCR_RSVD_MCR_31TO7_SET(value) (((value) << 7) & 0xffffff80)
1790 
1791 #ifndef __ASSEMBLY__
1792 /*
1793  * WARNING: The C register and register group struct declarations are provided for
1794  * convenience and illustrative purposes. They should, however, be used with
1795  * caution as the C language standard provides no guarantees about the alignment or
1796  * atomicity of device memory accesses. The recommended practice for coding device
1797  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1798  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1799  * alt_write_dword() functions for 64 bit registers.
1800  *
1801  * The struct declaration for register ALT_UART_MCR.
1802  */
1803 struct ALT_UART_MCR_s
1804 {
1805  volatile uint32_t DTR : 1; /* ALT_UART_MCR_DTR */
1806  volatile uint32_t RTS : 1; /* ALT_UART_MCR_RTS */
1807  volatile uint32_t OUT1 : 1; /* ALT_UART_MCR_OUT1 */
1808  volatile uint32_t OUT2 : 1; /* ALT_UART_MCR_OUT2 */
1809  volatile uint32_t LoopBack : 1; /* ALT_UART_MCR_LOOPBACK */
1810  volatile uint32_t AFCE : 1; /* ALT_UART_MCR_AFCE */
1811  const volatile uint32_t SIRE : 1; /* ALT_UART_MCR_SIRE */
1812  const volatile uint32_t RSVD_MCR_31to7 : 25; /* ALT_UART_MCR_RSVD_MCR_31TO7 */
1813 };
1814 
1815 /* The typedef declaration for register ALT_UART_MCR. */
1816 typedef struct ALT_UART_MCR_s ALT_UART_MCR_t;
1817 #endif /* __ASSEMBLY__ */
1818 
1819 /* The reset value of the ALT_UART_MCR register. */
1820 #define ALT_UART_MCR_RESET 0x00000000
1821 /* The byte offset of the ALT_UART_MCR register from the beginning of the component. */
1822 #define ALT_UART_MCR_OFST 0x10
1823 /* The address of the ALT_UART_MCR register. */
1824 #define ALT_UART_MCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MCR_OFST))
1825 
1826 /*
1827  * Register : Line Status Register - LSR
1828  *
1829  * Line Status Register
1830  *
1831  * Register Layout
1832  *
1833  * Bits | Access | Reset | Description
1834  * :-------|:-------|:------|:----------------------------
1835  * [0] | R | 0x0 | ALT_UART_LSR_DR
1836  * [1] | R | 0x0 | ALT_UART_LSR_OE
1837  * [2] | R | 0x0 | ALT_UART_LSR_PE
1838  * [3] | R | 0x0 | ALT_UART_LSR_FE
1839  * [4] | R | 0x0 | ALT_UART_LSR_BI
1840  * [5] | R | 0x1 | ALT_UART_LSR_THRE
1841  * [6] | R | 0x1 | ALT_UART_LSR_TEMT
1842  * [7] | R | 0x0 | ALT_UART_LSR_RFE
1843  * [31:8] | R | 0x0 | ALT_UART_LSR_RSVD_LSR_31TO8
1844  *
1845  */
1846 /*
1847  * Field : DR
1848  *
1849  * Data Ready bit.
1850  *
1851  * This is used to indicate that the receiver contains at least one character in
1852  * the
1853  *
1854  * RBR or the receiver FIFO.
1855  *
1856  * 0 = no data ready
1857  *
1858  * 1 = data ready
1859  *
1860  * This bit is cleared when the RBR is read in the non-FIFO mode, or when the
1861  * receiver
1862  *
1863  * FIFO is empty, in the FIFO mode.
1864  *
1865  * Field Enumeration Values:
1866  *
1867  * Enum | Value | Description
1868  * :----------------------------|:------|:---------------
1869  * ALT_UART_LSR_DR_E_NOT_READY | 0x0 | data not ready
1870  * ALT_UART_LSR_DR_E_READY | 0x1 | data ready
1871  *
1872  * Field Access Macros:
1873  *
1874  */
1875 /*
1876  * Enumerated value for register field ALT_UART_LSR_DR
1877  *
1878  * data not ready
1879  */
1880 #define ALT_UART_LSR_DR_E_NOT_READY 0x0
1881 /*
1882  * Enumerated value for register field ALT_UART_LSR_DR
1883  *
1884  * data ready
1885  */
1886 #define ALT_UART_LSR_DR_E_READY 0x1
1887 
1888 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_DR register field. */
1889 #define ALT_UART_LSR_DR_LSB 0
1890 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_DR register field. */
1891 #define ALT_UART_LSR_DR_MSB 0
1892 /* The width in bits of the ALT_UART_LSR_DR register field. */
1893 #define ALT_UART_LSR_DR_WIDTH 1
1894 /* The mask used to set the ALT_UART_LSR_DR register field value. */
1895 #define ALT_UART_LSR_DR_SET_MSK 0x00000001
1896 /* The mask used to clear the ALT_UART_LSR_DR register field value. */
1897 #define ALT_UART_LSR_DR_CLR_MSK 0xfffffffe
1898 /* The reset value of the ALT_UART_LSR_DR register field. */
1899 #define ALT_UART_LSR_DR_RESET 0x0
1900 /* Extracts the ALT_UART_LSR_DR field value from a register. */
1901 #define ALT_UART_LSR_DR_GET(value) (((value) & 0x00000001) >> 0)
1902 /* Produces a ALT_UART_LSR_DR register field value suitable for setting the register. */
1903 #define ALT_UART_LSR_DR_SET(value) (((value) << 0) & 0x00000001)
1904 
1905 /*
1906  * Field : OE
1907  *
1908  * Overrun error bit.
1909  *
1910  * This is used to indicate the occurrence of an overrun error. This occurs if a
1911  * new data
1912  *
1913  * character was received before the previous data was read. In the non-FIFO mode,
1914  * the OE
1915  *
1916  * bit is set when a new character arrives in the receiver before the previous
1917  * character
1918  *
1919  * was read from the RBR. When this happens, the data in the RBR is overwritten. In
1920  * the
1921  *
1922  * FIFO mode, an overrun error occurs when the FIFO is full and a new character
1923  * arrives at
1924  *
1925  * the receiver. The data in the FIFO is retained and the data in the receive shift
1926  * register
1927  *
1928  * is lost.
1929  *
1930  * 0 = no overrun error
1931  *
1932  * 1 = overrun error
1933  *
1934  * Reading the LSR clears the OE bit.
1935  *
1936  * Field Enumeration Values:
1937  *
1938  * Enum | Value | Description
1939  * :------------------------------------|:------|:-----------------
1940  * ALT_UART_LSR_OE_E_NO_OVER_RUN_ERROR | 0x0 | no overrun error
1941  * ALT_UART_LSR_OE_E_OVER_RUN_ERROR | 0x1 | overrun error
1942  *
1943  * Field Access Macros:
1944  *
1945  */
1946 /*
1947  * Enumerated value for register field ALT_UART_LSR_OE
1948  *
1949  * no overrun error
1950  */
1951 #define ALT_UART_LSR_OE_E_NO_OVER_RUN_ERROR 0x0
1952 /*
1953  * Enumerated value for register field ALT_UART_LSR_OE
1954  *
1955  * overrun error
1956  */
1957 #define ALT_UART_LSR_OE_E_OVER_RUN_ERROR 0x1
1958 
1959 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_OE register field. */
1960 #define ALT_UART_LSR_OE_LSB 1
1961 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_OE register field. */
1962 #define ALT_UART_LSR_OE_MSB 1
1963 /* The width in bits of the ALT_UART_LSR_OE register field. */
1964 #define ALT_UART_LSR_OE_WIDTH 1
1965 /* The mask used to set the ALT_UART_LSR_OE register field value. */
1966 #define ALT_UART_LSR_OE_SET_MSK 0x00000002
1967 /* The mask used to clear the ALT_UART_LSR_OE register field value. */
1968 #define ALT_UART_LSR_OE_CLR_MSK 0xfffffffd
1969 /* The reset value of the ALT_UART_LSR_OE register field. */
1970 #define ALT_UART_LSR_OE_RESET 0x0
1971 /* Extracts the ALT_UART_LSR_OE field value from a register. */
1972 #define ALT_UART_LSR_OE_GET(value) (((value) & 0x00000002) >> 1)
1973 /* Produces a ALT_UART_LSR_OE register field value suitable for setting the register. */
1974 #define ALT_UART_LSR_OE_SET(value) (((value) << 1) & 0x00000002)
1975 
1976 /*
1977  * Field : PE
1978  *
1979  * Parity Error bit.
1980  *
1981  * This is used to indicate the occurrence of a parity error in the receiver if the
1982  *
1983  * Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity
1984  * error is
1985  *
1986  * associated with a character received, it is revealed when the character with the
1987  * parity
1988  *
1989  * error arrives at the top of the FIFO.
1990  *
1991  * It should be noted that the Parity Error (PE) bit (LSR[2]) will be set if a
1992  * break
1993  *
1994  * interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]).
1995  *
1996  * 0 = no parity error
1997  *
1998  * 1 = parity error
1999  *
2000  * Reading the LSR clears the PE bit.
2001  *
2002  * Field Enumeration Values:
2003  *
2004  * Enum | Value | Description
2005  * :----------------------------------|:------|:----------------
2006  * ALT_UART_LSR_PE_E_NO_PARITY_ERROR | 0x0 | no parity error
2007  * ALT_UART_LSR_PE_E_PARITY_ERROR | 0x1 | parity error
2008  *
2009  * Field Access Macros:
2010  *
2011  */
2012 /*
2013  * Enumerated value for register field ALT_UART_LSR_PE
2014  *
2015  * no parity error
2016  */
2017 #define ALT_UART_LSR_PE_E_NO_PARITY_ERROR 0x0
2018 /*
2019  * Enumerated value for register field ALT_UART_LSR_PE
2020  *
2021  * parity error
2022  */
2023 #define ALT_UART_LSR_PE_E_PARITY_ERROR 0x1
2024 
2025 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_PE register field. */
2026 #define ALT_UART_LSR_PE_LSB 2
2027 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_PE register field. */
2028 #define ALT_UART_LSR_PE_MSB 2
2029 /* The width in bits of the ALT_UART_LSR_PE register field. */
2030 #define ALT_UART_LSR_PE_WIDTH 1
2031 /* The mask used to set the ALT_UART_LSR_PE register field value. */
2032 #define ALT_UART_LSR_PE_SET_MSK 0x00000004
2033 /* The mask used to clear the ALT_UART_LSR_PE register field value. */
2034 #define ALT_UART_LSR_PE_CLR_MSK 0xfffffffb
2035 /* The reset value of the ALT_UART_LSR_PE register field. */
2036 #define ALT_UART_LSR_PE_RESET 0x0
2037 /* Extracts the ALT_UART_LSR_PE field value from a register. */
2038 #define ALT_UART_LSR_PE_GET(value) (((value) & 0x00000004) >> 2)
2039 /* Produces a ALT_UART_LSR_PE register field value suitable for setting the register. */
2040 #define ALT_UART_LSR_PE_SET(value) (((value) << 2) & 0x00000004)
2041 
2042 /*
2043  * Field : FE
2044  *
2045  * Framing Error bit.
2046  *
2047  * This is used to indicate the occurrence of a framing error in the receiver. A
2048  * framing
2049  *
2050  * error occurs when the receiver does not detect a valid STOP bit in the received
2051  * data.
2052  *
2053  * In the FIFO mode, since the framing error is associated with a character
2054  * received, it
2055  *
2056  * is revealed when the character with the framing error is at the top of the FIFO.
2057  * When
2058  *
2059  * a framing error occurs the UART will try resynchronize. It does this by assuming
2060  * that
2061  *
2062  * the error was due to the start bit of the next character and then continues
2063  * receiving
2064  *
2065  * the other bit i.e. data, and/or parity and stop.
2066  *
2067  * It should be noted that the Framing Error (FE) bit (LSR[3]) will be set if a
2068  * break
2069  *
2070  * interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]).
2071  *
2072  * 0 = no framing error
2073  *
2074  * 1 = framing error
2075  *
2076  * Reading the LSR clears the FE bit.
2077  *
2078  * Field Enumeration Values:
2079  *
2080  * Enum | Value | Description
2081  * :-----------------------------------|:------|:-----------------
2082  * ALT_UART_LSR_FE_E_NO_FRAMING_ERROR | 0x0 | no framing error
2083  * ALT_UART_LSR_FE_E_FRAMING_ERROR | 0x1 | framing error
2084  *
2085  * Field Access Macros:
2086  *
2087  */
2088 /*
2089  * Enumerated value for register field ALT_UART_LSR_FE
2090  *
2091  * no framing error
2092  */
2093 #define ALT_UART_LSR_FE_E_NO_FRAMING_ERROR 0x0
2094 /*
2095  * Enumerated value for register field ALT_UART_LSR_FE
2096  *
2097  * framing error
2098  */
2099 #define ALT_UART_LSR_FE_E_FRAMING_ERROR 0x1
2100 
2101 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_FE register field. */
2102 #define ALT_UART_LSR_FE_LSB 3
2103 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_FE register field. */
2104 #define ALT_UART_LSR_FE_MSB 3
2105 /* The width in bits of the ALT_UART_LSR_FE register field. */
2106 #define ALT_UART_LSR_FE_WIDTH 1
2107 /* The mask used to set the ALT_UART_LSR_FE register field value. */
2108 #define ALT_UART_LSR_FE_SET_MSK 0x00000008
2109 /* The mask used to clear the ALT_UART_LSR_FE register field value. */
2110 #define ALT_UART_LSR_FE_CLR_MSK 0xfffffff7
2111 /* The reset value of the ALT_UART_LSR_FE register field. */
2112 #define ALT_UART_LSR_FE_RESET 0x0
2113 /* Extracts the ALT_UART_LSR_FE field value from a register. */
2114 #define ALT_UART_LSR_FE_GET(value) (((value) & 0x00000008) >> 3)
2115 /* Produces a ALT_UART_LSR_FE register field value suitable for setting the register. */
2116 #define ALT_UART_LSR_FE_SET(value) (((value) << 3) & 0x00000008)
2117 
2118 /*
2119  * Field : BI
2120  *
2121  * Break Interrupt bit.
2122  *
2123  * This is used to indicate the detection of a break sequence on the serial input
2124  * data.
2125  *
2126  * If in UART mode it is set whenever the serial input, sin, is held in a logic
2127  * '0'
2128  *
2129  * state for longer than the sum of start time + data bits + parity + stop bits.
2130  *
2131  * If in infrared mode it is set whenever the serial input, sir_in, is
2132  * continuously
2133  *
2134  * pulsed to logic '0' for longer than the sum of start time + data bits + parity +
2135  * stop
2136  *
2137  * bits.
2138  *
2139  * A break condition on serial input causes one and only one character, consisting
2140  * of
2141  *
2142  * all zeros, to be received by the UART. In the FIFO mode, the character
2143  * associated
2144  *
2145  * with the break condition is carried through the FIFO and is revealed when the
2146  *
2147  * character is at the top of the FIFO. Reading the LSR clears the BI bit. In the
2148  *
2149  * non-FIFO mode, the BI indication occurs immediately and persists until the LSR
2150  * is
2151  *
2152  * read.
2153  *
2154  * Field Enumeration Values:
2155  *
2156  * Enum | Value | Description
2157  * :---------------------------|:------|:---------------------------
2158  * ALT_UART_LSR_BI_E_NO_BREAK | 0x0 | No break sequence detected
2159  * ALT_UART_LSR_BI_E_BREAK | 0x1 | Break sequence detected
2160  *
2161  * Field Access Macros:
2162  *
2163  */
2164 /*
2165  * Enumerated value for register field ALT_UART_LSR_BI
2166  *
2167  * No break sequence detected
2168  */
2169 #define ALT_UART_LSR_BI_E_NO_BREAK 0x0
2170 /*
2171  * Enumerated value for register field ALT_UART_LSR_BI
2172  *
2173  * Break sequence detected
2174  */
2175 #define ALT_UART_LSR_BI_E_BREAK 0x1
2176 
2177 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_BI register field. */
2178 #define ALT_UART_LSR_BI_LSB 4
2179 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_BI register field. */
2180 #define ALT_UART_LSR_BI_MSB 4
2181 /* The width in bits of the ALT_UART_LSR_BI register field. */
2182 #define ALT_UART_LSR_BI_WIDTH 1
2183 /* The mask used to set the ALT_UART_LSR_BI register field value. */
2184 #define ALT_UART_LSR_BI_SET_MSK 0x00000010
2185 /* The mask used to clear the ALT_UART_LSR_BI register field value. */
2186 #define ALT_UART_LSR_BI_CLR_MSK 0xffffffef
2187 /* The reset value of the ALT_UART_LSR_BI register field. */
2188 #define ALT_UART_LSR_BI_RESET 0x0
2189 /* Extracts the ALT_UART_LSR_BI field value from a register. */
2190 #define ALT_UART_LSR_BI_GET(value) (((value) & 0x00000010) >> 4)
2191 /* Produces a ALT_UART_LSR_BI register field value suitable for setting the register. */
2192 #define ALT_UART_LSR_BI_SET(value) (((value) << 4) & 0x00000010)
2193 
2194 /*
2195  * Field : THRE
2196  *
2197  * Transmit Holding Register Empty bit.
2198  *
2199  * If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and
2200  *
2201  * regardless of FIFO's being implemented/enabled or not, this bit indicates that
2202  *
2203  * the THR or TX FIFO is empty. This bit is set whenever data is transferred from
2204  *
2205  * the THR or TX FIFO to the transmitter shift register and no new data has been
2206  *
2207  * written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if
2208  * the
2209  *
2210  * THRE Interrupt is enabled.
2211  *
2212  * If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active
2213  *
2214  * (IER[7] set to one and FCR[0] set to one respectively), the functionality is
2215  * switched
2216  *
2217  * to indicate the transmitter FIFO is full, and no longer controls THRE
2218  * interrupts,
2219  *
2220  * which are then controlled by the FCR[5:4] threshold setting. Programmable THRE
2221  *
2222  * interrupt mode operation is described in detail in section 5.7 on page 52.
2223  *
2224  * Field Enumeration Values:
2225  *
2226  * Enum | Value | Description
2227  * :-----------------------------|:------|:-----------------------------------
2228  * ALT_UART_LSR_THRE_E_DISABLED | 0x0 | THRE interrupt control is disabled
2229  * ALT_UART_LSR_THRE_E_ENABLED | 0x1 | THRE interrupt control is enabled
2230  *
2231  * Field Access Macros:
2232  *
2233  */
2234 /*
2235  * Enumerated value for register field ALT_UART_LSR_THRE
2236  *
2237  * THRE interrupt control is disabled
2238  */
2239 #define ALT_UART_LSR_THRE_E_DISABLED 0x0
2240 /*
2241  * Enumerated value for register field ALT_UART_LSR_THRE
2242  *
2243  * THRE interrupt control is enabled
2244  */
2245 #define ALT_UART_LSR_THRE_E_ENABLED 0x1
2246 
2247 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_THRE register field. */
2248 #define ALT_UART_LSR_THRE_LSB 5
2249 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_THRE register field. */
2250 #define ALT_UART_LSR_THRE_MSB 5
2251 /* The width in bits of the ALT_UART_LSR_THRE register field. */
2252 #define ALT_UART_LSR_THRE_WIDTH 1
2253 /* The mask used to set the ALT_UART_LSR_THRE register field value. */
2254 #define ALT_UART_LSR_THRE_SET_MSK 0x00000020
2255 /* The mask used to clear the ALT_UART_LSR_THRE register field value. */
2256 #define ALT_UART_LSR_THRE_CLR_MSK 0xffffffdf
2257 /* The reset value of the ALT_UART_LSR_THRE register field. */
2258 #define ALT_UART_LSR_THRE_RESET 0x1
2259 /* Extracts the ALT_UART_LSR_THRE field value from a register. */
2260 #define ALT_UART_LSR_THRE_GET(value) (((value) & 0x00000020) >> 5)
2261 /* Produces a ALT_UART_LSR_THRE register field value suitable for setting the register. */
2262 #define ALT_UART_LSR_THRE_SET(value) (((value) << 5) & 0x00000020)
2263 
2264 /*
2265  * Field : TEMT
2266  *
2267  * Transmitter Empty bit.
2268  *
2269  * If in FIFO mode (FIFO_MODE != NONE) and FIFO's enabled (FCR[0] set to one), this
2270  *
2271  * bit is set whenever the Transmitter Shift Register and the FIFO are both empty.
2272  *
2273  * If in the non-FIFO mode or FIFO's are disabled, this bit is set whenever the
2274  *
2275  * Transmitter Holding Register and the Transmitter Shift Register are both empty.
2276  *
2277  * Field Enumeration Values:
2278  *
2279  * Enum | Value | Description
2280  * :-----------------------------|:------|:----------------------
2281  * ALT_UART_LSR_TEMT_E_DISABLED | 0x0 | Transmitter not empty
2282  * ALT_UART_LSR_TEMT_E_ENABLED | 0x1 | Transmitter empty
2283  *
2284  * Field Access Macros:
2285  *
2286  */
2287 /*
2288  * Enumerated value for register field ALT_UART_LSR_TEMT
2289  *
2290  * Transmitter not empty
2291  */
2292 #define ALT_UART_LSR_TEMT_E_DISABLED 0x0
2293 /*
2294  * Enumerated value for register field ALT_UART_LSR_TEMT
2295  *
2296  * Transmitter empty
2297  */
2298 #define ALT_UART_LSR_TEMT_E_ENABLED 0x1
2299 
2300 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_TEMT register field. */
2301 #define ALT_UART_LSR_TEMT_LSB 6
2302 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_TEMT register field. */
2303 #define ALT_UART_LSR_TEMT_MSB 6
2304 /* The width in bits of the ALT_UART_LSR_TEMT register field. */
2305 #define ALT_UART_LSR_TEMT_WIDTH 1
2306 /* The mask used to set the ALT_UART_LSR_TEMT register field value. */
2307 #define ALT_UART_LSR_TEMT_SET_MSK 0x00000040
2308 /* The mask used to clear the ALT_UART_LSR_TEMT register field value. */
2309 #define ALT_UART_LSR_TEMT_CLR_MSK 0xffffffbf
2310 /* The reset value of the ALT_UART_LSR_TEMT register field. */
2311 #define ALT_UART_LSR_TEMT_RESET 0x1
2312 /* Extracts the ALT_UART_LSR_TEMT field value from a register. */
2313 #define ALT_UART_LSR_TEMT_GET(value) (((value) & 0x00000040) >> 6)
2314 /* Produces a ALT_UART_LSR_TEMT register field value suitable for setting the register. */
2315 #define ALT_UART_LSR_TEMT_SET(value) (((value) << 6) & 0x00000040)
2316 
2317 /*
2318  * Field : RFE
2319  *
2320  * Receiver FIFO Error bit.
2321  *
2322  * This bit is only relevant when FIFO_MODE != NONE AND FIFO's are enabled (FCR[0]
2323  *
2324  * set to one). This is used to indicate if there is at least one parity error,
2325  * framing
2326  *
2327  * error, or break indication in the FIFO. That is:
2328  *
2329  * 0 = no error in RX FIFO
2330  *
2331  * 1 = error in RX FIFO
2332  *
2333  * This bit is cleared when the LSR is read and the character with the error is at
2334  * the
2335  *
2336  * top of the receiver FIFO and there are no subsequent errors in the FIFO.
2337  *
2338  * Field Enumeration Values:
2339  *
2340  * Enum | Value | Description
2341  * :------------------------------------|:------|:--------------------
2342  * ALT_UART_LSR_RFE_E_NO_RX_FIFO_ERROR | 0x0 | No error in RX FIFO
2343  * ALT_UART_LSR_RFE_E_RX_FIFO_ERROR | 0x1 | Error in RX FIFO
2344  *
2345  * Field Access Macros:
2346  *
2347  */
2348 /*
2349  * Enumerated value for register field ALT_UART_LSR_RFE
2350  *
2351  * No error in RX FIFO
2352  */
2353 #define ALT_UART_LSR_RFE_E_NO_RX_FIFO_ERROR 0x0
2354 /*
2355  * Enumerated value for register field ALT_UART_LSR_RFE
2356  *
2357  * Error in RX FIFO
2358  */
2359 #define ALT_UART_LSR_RFE_E_RX_FIFO_ERROR 0x1
2360 
2361 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_RFE register field. */
2362 #define ALT_UART_LSR_RFE_LSB 7
2363 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_RFE register field. */
2364 #define ALT_UART_LSR_RFE_MSB 7
2365 /* The width in bits of the ALT_UART_LSR_RFE register field. */
2366 #define ALT_UART_LSR_RFE_WIDTH 1
2367 /* The mask used to set the ALT_UART_LSR_RFE register field value. */
2368 #define ALT_UART_LSR_RFE_SET_MSK 0x00000080
2369 /* The mask used to clear the ALT_UART_LSR_RFE register field value. */
2370 #define ALT_UART_LSR_RFE_CLR_MSK 0xffffff7f
2371 /* The reset value of the ALT_UART_LSR_RFE register field. */
2372 #define ALT_UART_LSR_RFE_RESET 0x0
2373 /* Extracts the ALT_UART_LSR_RFE field value from a register. */
2374 #define ALT_UART_LSR_RFE_GET(value) (((value) & 0x00000080) >> 7)
2375 /* Produces a ALT_UART_LSR_RFE register field value suitable for setting the register. */
2376 #define ALT_UART_LSR_RFE_SET(value) (((value) << 7) & 0x00000080)
2377 
2378 /*
2379  * Field : RSVD_LSR_31to8
2380  *
2381  * Reserved bits [31:8] - Read Only
2382  *
2383  * Field Access Macros:
2384  *
2385  */
2386 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_RSVD_LSR_31TO8 register field. */
2387 #define ALT_UART_LSR_RSVD_LSR_31TO8_LSB 8
2388 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_RSVD_LSR_31TO8 register field. */
2389 #define ALT_UART_LSR_RSVD_LSR_31TO8_MSB 31
2390 /* The width in bits of the ALT_UART_LSR_RSVD_LSR_31TO8 register field. */
2391 #define ALT_UART_LSR_RSVD_LSR_31TO8_WIDTH 24
2392 /* The mask used to set the ALT_UART_LSR_RSVD_LSR_31TO8 register field value. */
2393 #define ALT_UART_LSR_RSVD_LSR_31TO8_SET_MSK 0xffffff00
2394 /* The mask used to clear the ALT_UART_LSR_RSVD_LSR_31TO8 register field value. */
2395 #define ALT_UART_LSR_RSVD_LSR_31TO8_CLR_MSK 0x000000ff
2396 /* The reset value of the ALT_UART_LSR_RSVD_LSR_31TO8 register field. */
2397 #define ALT_UART_LSR_RSVD_LSR_31TO8_RESET 0x0
2398 /* Extracts the ALT_UART_LSR_RSVD_LSR_31TO8 field value from a register. */
2399 #define ALT_UART_LSR_RSVD_LSR_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
2400 /* Produces a ALT_UART_LSR_RSVD_LSR_31TO8 register field value suitable for setting the register. */
2401 #define ALT_UART_LSR_RSVD_LSR_31TO8_SET(value) (((value) << 8) & 0xffffff00)
2402 
2403 #ifndef __ASSEMBLY__
2404 /*
2405  * WARNING: The C register and register group struct declarations are provided for
2406  * convenience and illustrative purposes. They should, however, be used with
2407  * caution as the C language standard provides no guarantees about the alignment or
2408  * atomicity of device memory accesses. The recommended practice for coding device
2409  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2410  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2411  * alt_write_dword() functions for 64 bit registers.
2412  *
2413  * The struct declaration for register ALT_UART_LSR.
2414  */
2415 struct ALT_UART_LSR_s
2416 {
2417  const volatile uint32_t DR : 1; /* ALT_UART_LSR_DR */
2418  const volatile uint32_t OE : 1; /* ALT_UART_LSR_OE */
2419  const volatile uint32_t PE : 1; /* ALT_UART_LSR_PE */
2420  const volatile uint32_t FE : 1; /* ALT_UART_LSR_FE */
2421  const volatile uint32_t BI : 1; /* ALT_UART_LSR_BI */
2422  const volatile uint32_t THRE : 1; /* ALT_UART_LSR_THRE */
2423  const volatile uint32_t TEMT : 1; /* ALT_UART_LSR_TEMT */
2424  const volatile uint32_t RFE : 1; /* ALT_UART_LSR_RFE */
2425  const volatile uint32_t RSVD_LSR_31to8 : 24; /* ALT_UART_LSR_RSVD_LSR_31TO8 */
2426 };
2427 
2428 /* The typedef declaration for register ALT_UART_LSR. */
2429 typedef struct ALT_UART_LSR_s ALT_UART_LSR_t;
2430 #endif /* __ASSEMBLY__ */
2431 
2432 /* The reset value of the ALT_UART_LSR register. */
2433 #define ALT_UART_LSR_RESET 0x00000060
2434 /* The byte offset of the ALT_UART_LSR register from the beginning of the component. */
2435 #define ALT_UART_LSR_OFST 0x14
2436 /* The address of the ALT_UART_LSR register. */
2437 #define ALT_UART_LSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LSR_OFST))
2438 
2439 /*
2440  * Register : Modem Status Register - MSR
2441  *
2442  * Modem Status Register
2443  *
2444  * It should be noted that whenever bits 0, 1, 2 or 3 is set to logic one, to
2445  * indicate
2446  *
2447  * a change on the modem control inputs, a modem status interrupt will be generated
2448  *
2449  * if enabled via the IER regardless of when the change occurred. Since the delta
2450  * bits
2451  *
2452  * (bits 0, 1, 3) can get set after a reset if their respective modem signals are
2453  *
2454  * active (see individual bits for details), a read of the MSR after reset can be
2455  *
2456  * performed to prevent unwanted interrupts.
2457  *
2458  * Register Layout
2459  *
2460  * Bits | Access | Reset | Description
2461  * :-------|:-------|:------|:----------------------------
2462  * [0] | R | 0x0 | ALT_UART_MSR_DCTS
2463  * [1] | R | 0x0 | ALT_UART_MSR_DDSR
2464  * [2] | R | 0x0 | ALT_UART_MSR_TERI
2465  * [3] | R | 0x0 | ALT_UART_MSR_DDCD
2466  * [4] | R | 0x0 | ALT_UART_MSR_CTS
2467  * [5] | R | 0x0 | ALT_UART_MSR_DSR
2468  * [6] | R | 0x0 | ALT_UART_MSR_RI
2469  * [7] | R | 0x0 | ALT_UART_MSR_DCD
2470  * [31:8] | R | 0x0 | ALT_UART_MSR_RSVD_MSR_31TO8
2471  *
2472  */
2473 /*
2474  * Field : DCTS
2475  *
2476  * Delta Clear to Send.
2477  *
2478  * This is used to indicate that the modem control line cts_n has changed since the
2479  *
2480  * last time the MSR was read. That is:
2481  *
2482  * 0 = no change on cts_n since last read of MSR
2483  *
2484  * 1 = change on cts_n since last read of MSR
2485  *
2486  * Reading the MSR clears the DCTS bit.
2487  *
2488  * In Loopback Mode (MCR[4] set to one), DCTS reflects changes on MCR[1] (RTS).
2489  *
2490  * Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a
2491  * reset
2492  *
2493  * occurs (software or otherwise), then the DCTS bit will get set when the reset is
2494  *
2495  * removed if the cts_n signal remains asserted.
2496  *
2497  * Field Enumeration Values:
2498  *
2499  * Enum | Value | Description
2500  * :------------------------------|:------|:------------------------------------------
2501  * ALT_UART_MSR_DCTS_E_NO_CHANGE | 0x0 | No change on cts_n since last read of MSR
2502  * ALT_UART_MSR_DCTS_E_CHANGE | 0x1 | change on cts_n since last read of MSR
2503  *
2504  * Field Access Macros:
2505  *
2506  */
2507 /*
2508  * Enumerated value for register field ALT_UART_MSR_DCTS
2509  *
2510  * No change on cts_n since last read of MSR
2511  */
2512 #define ALT_UART_MSR_DCTS_E_NO_CHANGE 0x0
2513 /*
2514  * Enumerated value for register field ALT_UART_MSR_DCTS
2515  *
2516  * change on cts_n since last read of MSR
2517  */
2518 #define ALT_UART_MSR_DCTS_E_CHANGE 0x1
2519 
2520 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCTS register field. */
2521 #define ALT_UART_MSR_DCTS_LSB 0
2522 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCTS register field. */
2523 #define ALT_UART_MSR_DCTS_MSB 0
2524 /* The width in bits of the ALT_UART_MSR_DCTS register field. */
2525 #define ALT_UART_MSR_DCTS_WIDTH 1
2526 /* The mask used to set the ALT_UART_MSR_DCTS register field value. */
2527 #define ALT_UART_MSR_DCTS_SET_MSK 0x00000001
2528 /* The mask used to clear the ALT_UART_MSR_DCTS register field value. */
2529 #define ALT_UART_MSR_DCTS_CLR_MSK 0xfffffffe
2530 /* The reset value of the ALT_UART_MSR_DCTS register field. */
2531 #define ALT_UART_MSR_DCTS_RESET 0x0
2532 /* Extracts the ALT_UART_MSR_DCTS field value from a register. */
2533 #define ALT_UART_MSR_DCTS_GET(value) (((value) & 0x00000001) >> 0)
2534 /* Produces a ALT_UART_MSR_DCTS register field value suitable for setting the register. */
2535 #define ALT_UART_MSR_DCTS_SET(value) (((value) << 0) & 0x00000001)
2536 
2537 /*
2538  * Field : DDSR
2539  *
2540  * Delta Data Set Ready.
2541  *
2542  * This is used to indicate that the modem control line dsr_n has changed since
2543  *
2544  * the last time the MSR was read. That is:
2545  *
2546  * 0 = no change on dsr_n since last read of MSR
2547  *
2548  * 1 = change on dsr_n since last read of MSR
2549  *
2550  * Reading the MSR clears the DDSR bit.
2551  *
2552  * In Loopback Mode (MCR[4] set to one), DDSR reflects changes on MCR[0] (DTR).
2553  *
2554  * Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a
2555  * reset
2556  *
2557  * occurs (software or otherwise), then the DDSR bit will get set when the reset is
2558  *
2559  * removed if the dsr_n signal remains asserted.
2560  *
2561  * Field Enumeration Values:
2562  *
2563  * Enum | Value | Description
2564  * :------------------------------|:------|:------------------------------------------
2565  * ALT_UART_MSR_DDSR_E_NO_CHANGE | 0x0 | No change on dsr_n since last read of MSR
2566  * ALT_UART_MSR_DDSR_E_CHANGE | 0x1 | change on dsr_n since last read of MSR
2567  *
2568  * Field Access Macros:
2569  *
2570  */
2571 /*
2572  * Enumerated value for register field ALT_UART_MSR_DDSR
2573  *
2574  * No change on dsr_n since last read of MSR
2575  */
2576 #define ALT_UART_MSR_DDSR_E_NO_CHANGE 0x0
2577 /*
2578  * Enumerated value for register field ALT_UART_MSR_DDSR
2579  *
2580  * change on dsr_n since last read of MSR
2581  */
2582 #define ALT_UART_MSR_DDSR_E_CHANGE 0x1
2583 
2584 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDSR register field. */
2585 #define ALT_UART_MSR_DDSR_LSB 1
2586 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDSR register field. */
2587 #define ALT_UART_MSR_DDSR_MSB 1
2588 /* The width in bits of the ALT_UART_MSR_DDSR register field. */
2589 #define ALT_UART_MSR_DDSR_WIDTH 1
2590 /* The mask used to set the ALT_UART_MSR_DDSR register field value. */
2591 #define ALT_UART_MSR_DDSR_SET_MSK 0x00000002
2592 /* The mask used to clear the ALT_UART_MSR_DDSR register field value. */
2593 #define ALT_UART_MSR_DDSR_CLR_MSK 0xfffffffd
2594 /* The reset value of the ALT_UART_MSR_DDSR register field. */
2595 #define ALT_UART_MSR_DDSR_RESET 0x0
2596 /* Extracts the ALT_UART_MSR_DDSR field value from a register. */
2597 #define ALT_UART_MSR_DDSR_GET(value) (((value) & 0x00000002) >> 1)
2598 /* Produces a ALT_UART_MSR_DDSR register field value suitable for setting the register. */
2599 #define ALT_UART_MSR_DDSR_SET(value) (((value) << 1) & 0x00000002)
2600 
2601 /*
2602  * Field : TERI
2603  *
2604  * Trailing Edge of Ring Indicator.
2605  *
2606  * This is used to indicate that a change on the input ri_n (from an active low, to
2607  *
2608  * an inactive high state) has occurred since the last time the MSR was read. That
2609  * is:
2610  *
2611  * 0 = no change on ri_n since last read of MSR
2612  *
2613  * 1 = change on ri_n since last read of MSR
2614  *
2615  * Reading the MSR clears the TERI bit.
2616  *
2617  * In Loopback Mode (MCR[4] set to one), TERI reflects when MCR[2] (Out1) has
2618  * changed
2619  *
2620  * state from a high to a low.
2621  *
2622  * Field Enumeration Values:
2623  *
2624  * Enum | Value | Description
2625  * :------------------------------|:------|:-----------------------------------------
2626  * ALT_UART_MSR_TERI_E_NO_CHANGE | 0x0 | No change on ri_n since last read of MSR
2627  * ALT_UART_MSR_TERI_E_CHANGE | 0x1 | change on ri_n since last read of MSR
2628  *
2629  * Field Access Macros:
2630  *
2631  */
2632 /*
2633  * Enumerated value for register field ALT_UART_MSR_TERI
2634  *
2635  * No change on ri_n since last read of MSR
2636  */
2637 #define ALT_UART_MSR_TERI_E_NO_CHANGE 0x0
2638 /*
2639  * Enumerated value for register field ALT_UART_MSR_TERI
2640  *
2641  * change on ri_n since last read of MSR
2642  */
2643 #define ALT_UART_MSR_TERI_E_CHANGE 0x1
2644 
2645 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_TERI register field. */
2646 #define ALT_UART_MSR_TERI_LSB 2
2647 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_TERI register field. */
2648 #define ALT_UART_MSR_TERI_MSB 2
2649 /* The width in bits of the ALT_UART_MSR_TERI register field. */
2650 #define ALT_UART_MSR_TERI_WIDTH 1
2651 /* The mask used to set the ALT_UART_MSR_TERI register field value. */
2652 #define ALT_UART_MSR_TERI_SET_MSK 0x00000004
2653 /* The mask used to clear the ALT_UART_MSR_TERI register field value. */
2654 #define ALT_UART_MSR_TERI_CLR_MSK 0xfffffffb
2655 /* The reset value of the ALT_UART_MSR_TERI register field. */
2656 #define ALT_UART_MSR_TERI_RESET 0x0
2657 /* Extracts the ALT_UART_MSR_TERI field value from a register. */
2658 #define ALT_UART_MSR_TERI_GET(value) (((value) & 0x00000004) >> 2)
2659 /* Produces a ALT_UART_MSR_TERI register field value suitable for setting the register. */
2660 #define ALT_UART_MSR_TERI_SET(value) (((value) << 2) & 0x00000004)
2661 
2662 /*
2663  * Field : DDCD
2664  *
2665  * Delta Data Carrier Detect.
2666  *
2667  * This is used to indicate that the modem control line dcd_n has changed since the
2668  * last
2669  *
2670  * time the MSR was read. That is:
2671  *
2672  * 0 = no change on dcd_n since last read of MSR
2673  *
2674  * 1 = change on dcd_n since last read of MSR
2675  *
2676  * Reading the MSR clears the DDCD bit.
2677  *
2678  * In Loopback Mode (MCR[4] set to one), DDCD reflects changes on MCR[3] (Out2).
2679  *
2680  * Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a
2681  * reset
2682  *
2683  * occurs (software or otherwise), then the DDCD bit will get set when the reset is
2684  *
2685  * removed if the dcd_n signal remains asserted.
2686  *
2687  * Field Enumeration Values:
2688  *
2689  * Enum | Value | Description
2690  * :------------------------------|:------|:------------------------------------------
2691  * ALT_UART_MSR_DDCD_E_NO_CHANGE | 0x0 | No change on dcd_n since last read of MSR
2692  * ALT_UART_MSR_DDCD_E_CHANGE | 0x1 | change on dcd_n since last read of MSR
2693  *
2694  * Field Access Macros:
2695  *
2696  */
2697 /*
2698  * Enumerated value for register field ALT_UART_MSR_DDCD
2699  *
2700  * No change on dcd_n since last read of MSR
2701  */
2702 #define ALT_UART_MSR_DDCD_E_NO_CHANGE 0x0
2703 /*
2704  * Enumerated value for register field ALT_UART_MSR_DDCD
2705  *
2706  * change on dcd_n since last read of MSR
2707  */
2708 #define ALT_UART_MSR_DDCD_E_CHANGE 0x1
2709 
2710 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDCD register field. */
2711 #define ALT_UART_MSR_DDCD_LSB 3
2712 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDCD register field. */
2713 #define ALT_UART_MSR_DDCD_MSB 3
2714 /* The width in bits of the ALT_UART_MSR_DDCD register field. */
2715 #define ALT_UART_MSR_DDCD_WIDTH 1
2716 /* The mask used to set the ALT_UART_MSR_DDCD register field value. */
2717 #define ALT_UART_MSR_DDCD_SET_MSK 0x00000008
2718 /* The mask used to clear the ALT_UART_MSR_DDCD register field value. */
2719 #define ALT_UART_MSR_DDCD_CLR_MSK 0xfffffff7
2720 /* The reset value of the ALT_UART_MSR_DDCD register field. */
2721 #define ALT_UART_MSR_DDCD_RESET 0x0
2722 /* Extracts the ALT_UART_MSR_DDCD field value from a register. */
2723 #define ALT_UART_MSR_DDCD_GET(value) (((value) & 0x00000008) >> 3)
2724 /* Produces a ALT_UART_MSR_DDCD register field value suitable for setting the register. */
2725 #define ALT_UART_MSR_DDCD_SET(value) (((value) << 3) & 0x00000008)
2726 
2727 /*
2728  * Field : CTS
2729  *
2730  * Clear to Send.
2731  *
2732  * This is used to indicate the current state of the modem control line cts_n. That
2733  * is,
2734  *
2735  * this bit is the complement cts_n. When the Clear to Send input (cts_n) is
2736  * asserted
2737  *
2738  * it is an indication that the modem or data set is ready to exchange data with
2739  * the
2740  *
2741  * DW_apb_uart.
2742  *
2743  * 0 = cts_n input is de-asserted (logic 1)
2744  *
2745  * 1 = cts_n input is asserted (logic 0)
2746  *
2747  * In Loopback Mode (MCR[4] set to one), CTS is the same as MCR[1] (RTS).
2748  *
2749  * Field Enumeration Values:
2750  *
2751  * Enum | Value | Description
2752  * :------------------------------|:------|:-------------------------------------
2753  * ALT_UART_MSR_CTS_E_DEASSERTED | 0x0 | cts_n input is de-asserted (logic 1)
2754  * ALT_UART_MSR_CTS_E_ASSERTED | 0x1 | cts_n input is asserted (logic 0)
2755  *
2756  * Field Access Macros:
2757  *
2758  */
2759 /*
2760  * Enumerated value for register field ALT_UART_MSR_CTS
2761  *
2762  * cts_n input is de-asserted (logic 1)
2763  */
2764 #define ALT_UART_MSR_CTS_E_DEASSERTED 0x0
2765 /*
2766  * Enumerated value for register field ALT_UART_MSR_CTS
2767  *
2768  * cts_n input is asserted (logic 0)
2769  */
2770 #define ALT_UART_MSR_CTS_E_ASSERTED 0x1
2771 
2772 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_CTS register field. */
2773 #define ALT_UART_MSR_CTS_LSB 4
2774 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_CTS register field. */
2775 #define ALT_UART_MSR_CTS_MSB 4
2776 /* The width in bits of the ALT_UART_MSR_CTS register field. */
2777 #define ALT_UART_MSR_CTS_WIDTH 1
2778 /* The mask used to set the ALT_UART_MSR_CTS register field value. */
2779 #define ALT_UART_MSR_CTS_SET_MSK 0x00000010
2780 /* The mask used to clear the ALT_UART_MSR_CTS register field value. */
2781 #define ALT_UART_MSR_CTS_CLR_MSK 0xffffffef
2782 /* The reset value of the ALT_UART_MSR_CTS register field. */
2783 #define ALT_UART_MSR_CTS_RESET 0x0
2784 /* Extracts the ALT_UART_MSR_CTS field value from a register. */
2785 #define ALT_UART_MSR_CTS_GET(value) (((value) & 0x00000010) >> 4)
2786 /* Produces a ALT_UART_MSR_CTS register field value suitable for setting the register. */
2787 #define ALT_UART_MSR_CTS_SET(value) (((value) << 4) & 0x00000010)
2788 
2789 /*
2790  * Field : DSR
2791  *
2792  * Data Set Ready.
2793  *
2794  * This is used to indicate the current state of the modem control line dsr_n. That
2795  * is
2796  *
2797  * this bit is the complement dsr_n. When the Data Set Ready input (dsr_n) is
2798  * asserted
2799  *
2800  * it is an indication that the modem or data set is ready to establish
2801  * communications
2802  *
2803  * with the DW_apb_uart.
2804  *
2805  * 0 = dsr_n input is de-asserted (logic 1)
2806  *
2807  * 1 = dsr_n input is asserted (logic 0)
2808  *
2809  * In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR).
2810  *
2811  * Field Enumeration Values:
2812  *
2813  * Enum | Value | Description
2814  * :------------------------------|:------|:-------------------------------------
2815  * ALT_UART_MSR_DSR_E_DEASSERTED | 0x0 | dsr_n input is de-asserted (logic 1)
2816  * ALT_UART_MSR_DSR_E_ASSERTED | 0x1 | dsr_n input is asserted (logic 0)
2817  *
2818  * Field Access Macros:
2819  *
2820  */
2821 /*
2822  * Enumerated value for register field ALT_UART_MSR_DSR
2823  *
2824  * dsr_n input is de-asserted (logic 1)
2825  */
2826 #define ALT_UART_MSR_DSR_E_DEASSERTED 0x0
2827 /*
2828  * Enumerated value for register field ALT_UART_MSR_DSR
2829  *
2830  * dsr_n input is asserted (logic 0)
2831  */
2832 #define ALT_UART_MSR_DSR_E_ASSERTED 0x1
2833 
2834 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DSR register field. */
2835 #define ALT_UART_MSR_DSR_LSB 5
2836 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DSR register field. */
2837 #define ALT_UART_MSR_DSR_MSB 5
2838 /* The width in bits of the ALT_UART_MSR_DSR register field. */
2839 #define ALT_UART_MSR_DSR_WIDTH 1
2840 /* The mask used to set the ALT_UART_MSR_DSR register field value. */
2841 #define ALT_UART_MSR_DSR_SET_MSK 0x00000020
2842 /* The mask used to clear the ALT_UART_MSR_DSR register field value. */
2843 #define ALT_UART_MSR_DSR_CLR_MSK 0xffffffdf
2844 /* The reset value of the ALT_UART_MSR_DSR register field. */
2845 #define ALT_UART_MSR_DSR_RESET 0x0
2846 /* Extracts the ALT_UART_MSR_DSR field value from a register. */
2847 #define ALT_UART_MSR_DSR_GET(value) (((value) & 0x00000020) >> 5)
2848 /* Produces a ALT_UART_MSR_DSR register field value suitable for setting the register. */
2849 #define ALT_UART_MSR_DSR_SET(value) (((value) << 5) & 0x00000020)
2850 
2851 /*
2852  * Field : RI
2853  *
2854  * Ring Indicator.
2855  *
2856  * This is used to indicate the current state of the modem control line ri_n. That
2857  * is
2858  *
2859  * this bit is the complement ri_n. When the Ring Indicator input (ri_n) is
2860  * asserted
2861  *
2862  * it is an indication that a telephone ringing signal has been received by the
2863  * modem
2864  *
2865  * or data set.
2866  *
2867  * 0 = ri_n input is de-asserted (logic 1)
2868  *
2869  * 1 = ri_n input is asserted (logic 0)
2870  *
2871  * In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1).
2872  *
2873  * Field Enumeration Values:
2874  *
2875  * Enum | Value | Description
2876  * :-----------------------------|:------|:------------------------------------
2877  * ALT_UART_MSR_RI_E_DEASSERTED | 0x0 | ri_n input is de-asserted (logic 1)
2878  * ALT_UART_MSR_RI_E_ASSERTED | 0x1 | ri_n input is asserted (logic 0)
2879  *
2880  * Field Access Macros:
2881  *
2882  */
2883 /*
2884  * Enumerated value for register field ALT_UART_MSR_RI
2885  *
2886  * ri_n input is de-asserted (logic 1)
2887  */
2888 #define ALT_UART_MSR_RI_E_DEASSERTED 0x0
2889 /*
2890  * Enumerated value for register field ALT_UART_MSR_RI
2891  *
2892  * ri_n input is asserted (logic 0)
2893  */
2894 #define ALT_UART_MSR_RI_E_ASSERTED 0x1
2895 
2896 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_RI register field. */
2897 #define ALT_UART_MSR_RI_LSB 6
2898 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_RI register field. */
2899 #define ALT_UART_MSR_RI_MSB 6
2900 /* The width in bits of the ALT_UART_MSR_RI register field. */
2901 #define ALT_UART_MSR_RI_WIDTH 1
2902 /* The mask used to set the ALT_UART_MSR_RI register field value. */
2903 #define ALT_UART_MSR_RI_SET_MSK 0x00000040
2904 /* The mask used to clear the ALT_UART_MSR_RI register field value. */
2905 #define ALT_UART_MSR_RI_CLR_MSK 0xffffffbf
2906 /* The reset value of the ALT_UART_MSR_RI register field. */
2907 #define ALT_UART_MSR_RI_RESET 0x0
2908 /* Extracts the ALT_UART_MSR_RI field value from a register. */
2909 #define ALT_UART_MSR_RI_GET(value) (((value) & 0x00000040) >> 6)
2910 /* Produces a ALT_UART_MSR_RI register field value suitable for setting the register. */
2911 #define ALT_UART_MSR_RI_SET(value) (((value) << 6) & 0x00000040)
2912 
2913 /*
2914  * Field : DCD
2915  *
2916  * Data Carrier Detect.
2917  *
2918  * This is used to indicate the current state of the modem control line dcd_n. That
2919  * is
2920  *
2921  * this bit is the complement dcd_n. When the Data Carrier Detect input (dcd_n) is
2922  *
2923  * asserted it is an indication that the carrier has been detected by the modem or
2924  *
2925  * data set.
2926  *
2927  * 0 = dcd_n input is de-asserted (logic 1)
2928  *
2929  * 1 = dcd_n input is asserted (logic 0)
2930  *
2931  * In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2).
2932  *
2933  * Field Enumeration Values:
2934  *
2935  * Enum | Value | Description
2936  * :------------------------------|:------|:-------------------------------------
2937  * ALT_UART_MSR_DCD_E_DEASSERTED | 0x0 | dcd_n input is de-asserted (logic 1)
2938  * ALT_UART_MSR_DCD_E_ASSERTED | 0x1 | dcd_n input is asserted (logic 0)
2939  *
2940  * Field Access Macros:
2941  *
2942  */
2943 /*
2944  * Enumerated value for register field ALT_UART_MSR_DCD
2945  *
2946  * dcd_n input is de-asserted (logic 1)
2947  */
2948 #define ALT_UART_MSR_DCD_E_DEASSERTED 0x0
2949 /*
2950  * Enumerated value for register field ALT_UART_MSR_DCD
2951  *
2952  * dcd_n input is asserted (logic 0)
2953  */
2954 #define ALT_UART_MSR_DCD_E_ASSERTED 0x1
2955 
2956 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCD register field. */
2957 #define ALT_UART_MSR_DCD_LSB 7
2958 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCD register field. */
2959 #define ALT_UART_MSR_DCD_MSB 7
2960 /* The width in bits of the ALT_UART_MSR_DCD register field. */
2961 #define ALT_UART_MSR_DCD_WIDTH 1
2962 /* The mask used to set the ALT_UART_MSR_DCD register field value. */
2963 #define ALT_UART_MSR_DCD_SET_MSK 0x00000080
2964 /* The mask used to clear the ALT_UART_MSR_DCD register field value. */
2965 #define ALT_UART_MSR_DCD_CLR_MSK 0xffffff7f
2966 /* The reset value of the ALT_UART_MSR_DCD register field. */
2967 #define ALT_UART_MSR_DCD_RESET 0x0
2968 /* Extracts the ALT_UART_MSR_DCD field value from a register. */
2969 #define ALT_UART_MSR_DCD_GET(value) (((value) & 0x00000080) >> 7)
2970 /* Produces a ALT_UART_MSR_DCD register field value suitable for setting the register. */
2971 #define ALT_UART_MSR_DCD_SET(value) (((value) << 7) & 0x00000080)
2972 
2973 /*
2974  * Field : RSVD_MSR_31to8
2975  *
2976  * Reserved bits [31:8] - Read Only
2977  *
2978  * Field Access Macros:
2979  *
2980  */
2981 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_RSVD_MSR_31TO8 register field. */
2982 #define ALT_UART_MSR_RSVD_MSR_31TO8_LSB 8
2983 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_RSVD_MSR_31TO8 register field. */
2984 #define ALT_UART_MSR_RSVD_MSR_31TO8_MSB 31
2985 /* The width in bits of the ALT_UART_MSR_RSVD_MSR_31TO8 register field. */
2986 #define ALT_UART_MSR_RSVD_MSR_31TO8_WIDTH 24
2987 /* The mask used to set the ALT_UART_MSR_RSVD_MSR_31TO8 register field value. */
2988 #define ALT_UART_MSR_RSVD_MSR_31TO8_SET_MSK 0xffffff00
2989 /* The mask used to clear the ALT_UART_MSR_RSVD_MSR_31TO8 register field value. */
2990 #define ALT_UART_MSR_RSVD_MSR_31TO8_CLR_MSK 0x000000ff
2991 /* The reset value of the ALT_UART_MSR_RSVD_MSR_31TO8 register field. */
2992 #define ALT_UART_MSR_RSVD_MSR_31TO8_RESET 0x0
2993 /* Extracts the ALT_UART_MSR_RSVD_MSR_31TO8 field value from a register. */
2994 #define ALT_UART_MSR_RSVD_MSR_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
2995 /* Produces a ALT_UART_MSR_RSVD_MSR_31TO8 register field value suitable for setting the register. */
2996 #define ALT_UART_MSR_RSVD_MSR_31TO8_SET(value) (((value) << 8) & 0xffffff00)
2997 
2998 #ifndef __ASSEMBLY__
2999 /*
3000  * WARNING: The C register and register group struct declarations are provided for
3001  * convenience and illustrative purposes. They should, however, be used with
3002  * caution as the C language standard provides no guarantees about the alignment or
3003  * atomicity of device memory accesses. The recommended practice for coding device
3004  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3005  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3006  * alt_write_dword() functions for 64 bit registers.
3007  *
3008  * The struct declaration for register ALT_UART_MSR.
3009  */
3010 struct ALT_UART_MSR_s
3011 {
3012  const volatile uint32_t DCTS : 1; /* ALT_UART_MSR_DCTS */
3013  const volatile uint32_t DDSR : 1; /* ALT_UART_MSR_DDSR */
3014  const volatile uint32_t TERI : 1; /* ALT_UART_MSR_TERI */
3015  const volatile uint32_t DDCD : 1; /* ALT_UART_MSR_DDCD */
3016  const volatile uint32_t CTS : 1; /* ALT_UART_MSR_CTS */
3017  const volatile uint32_t DSR : 1; /* ALT_UART_MSR_DSR */
3018  const volatile uint32_t RI : 1; /* ALT_UART_MSR_RI */
3019  const volatile uint32_t DCD : 1; /* ALT_UART_MSR_DCD */
3020  const volatile uint32_t RSVD_MSR_31to8 : 24; /* ALT_UART_MSR_RSVD_MSR_31TO8 */
3021 };
3022 
3023 /* The typedef declaration for register ALT_UART_MSR. */
3024 typedef struct ALT_UART_MSR_s ALT_UART_MSR_t;
3025 #endif /* __ASSEMBLY__ */
3026 
3027 /* The reset value of the ALT_UART_MSR register. */
3028 #define ALT_UART_MSR_RESET 0x00000000
3029 /* The byte offset of the ALT_UART_MSR register from the beginning of the component. */
3030 #define ALT_UART_MSR_OFST 0x18
3031 /* The address of the ALT_UART_MSR register. */
3032 #define ALT_UART_MSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MSR_OFST))
3033 
3034 /*
3035  * Register : Scratchpad Register - SCR
3036  *
3037  * Scratchpad Register
3038  *
3039  * Register Layout
3040  *
3041  * Bits | Access | Reset | Description
3042  * :-------|:-------|:------|:----------------------------
3043  * [7:0] | RW | 0x0 | ALT_UART_SCR_SCR
3044  * [31:8] | R | 0x0 | ALT_UART_SCR_RSVD_SCR_31TO8
3045  *
3046  */
3047 /*
3048  * Field : scr
3049  *
3050  * This register is for programmers to use as a temporary storage space. It has no
3051  *
3052  * defined purpose in the DW_apb_uart.
3053  *
3054  * Field Access Macros:
3055  *
3056  */
3057 /* The Least Significant Bit (LSB) position of the ALT_UART_SCR_SCR register field. */
3058 #define ALT_UART_SCR_SCR_LSB 0
3059 /* The Most Significant Bit (MSB) position of the ALT_UART_SCR_SCR register field. */
3060 #define ALT_UART_SCR_SCR_MSB 7
3061 /* The width in bits of the ALT_UART_SCR_SCR register field. */
3062 #define ALT_UART_SCR_SCR_WIDTH 8
3063 /* The mask used to set the ALT_UART_SCR_SCR register field value. */
3064 #define ALT_UART_SCR_SCR_SET_MSK 0x000000ff
3065 /* The mask used to clear the ALT_UART_SCR_SCR register field value. */
3066 #define ALT_UART_SCR_SCR_CLR_MSK 0xffffff00
3067 /* The reset value of the ALT_UART_SCR_SCR register field. */
3068 #define ALT_UART_SCR_SCR_RESET 0x0
3069 /* Extracts the ALT_UART_SCR_SCR field value from a register. */
3070 #define ALT_UART_SCR_SCR_GET(value) (((value) & 0x000000ff) >> 0)
3071 /* Produces a ALT_UART_SCR_SCR register field value suitable for setting the register. */
3072 #define ALT_UART_SCR_SCR_SET(value) (((value) << 0) & 0x000000ff)
3073 
3074 /*
3075  * Field : RSVD_SCR_31to8
3076  *
3077  * Reserved bits [31:8] - Read Only
3078  *
3079  * Field Access Macros:
3080  *
3081  */
3082 /* The Least Significant Bit (LSB) position of the ALT_UART_SCR_RSVD_SCR_31TO8 register field. */
3083 #define ALT_UART_SCR_RSVD_SCR_31TO8_LSB 8
3084 /* The Most Significant Bit (MSB) position of the ALT_UART_SCR_RSVD_SCR_31TO8 register field. */
3085 #define ALT_UART_SCR_RSVD_SCR_31TO8_MSB 31
3086 /* The width in bits of the ALT_UART_SCR_RSVD_SCR_31TO8 register field. */
3087 #define ALT_UART_SCR_RSVD_SCR_31TO8_WIDTH 24
3088 /* The mask used to set the ALT_UART_SCR_RSVD_SCR_31TO8 register field value. */
3089 #define ALT_UART_SCR_RSVD_SCR_31TO8_SET_MSK 0xffffff00
3090 /* The mask used to clear the ALT_UART_SCR_RSVD_SCR_31TO8 register field value. */
3091 #define ALT_UART_SCR_RSVD_SCR_31TO8_CLR_MSK 0x000000ff
3092 /* The reset value of the ALT_UART_SCR_RSVD_SCR_31TO8 register field. */
3093 #define ALT_UART_SCR_RSVD_SCR_31TO8_RESET 0x0
3094 /* Extracts the ALT_UART_SCR_RSVD_SCR_31TO8 field value from a register. */
3095 #define ALT_UART_SCR_RSVD_SCR_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3096 /* Produces a ALT_UART_SCR_RSVD_SCR_31TO8 register field value suitable for setting the register. */
3097 #define ALT_UART_SCR_RSVD_SCR_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3098 
3099 #ifndef __ASSEMBLY__
3100 /*
3101  * WARNING: The C register and register group struct declarations are provided for
3102  * convenience and illustrative purposes. They should, however, be used with
3103  * caution as the C language standard provides no guarantees about the alignment or
3104  * atomicity of device memory accesses. The recommended practice for coding device
3105  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3106  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3107  * alt_write_dword() functions for 64 bit registers.
3108  *
3109  * The struct declaration for register ALT_UART_SCR.
3110  */
3111 struct ALT_UART_SCR_s
3112 {
3113  volatile uint32_t scr : 8; /* ALT_UART_SCR_SCR */
3114  const volatile uint32_t RSVD_SCR_31to8 : 24; /* ALT_UART_SCR_RSVD_SCR_31TO8 */
3115 };
3116 
3117 /* The typedef declaration for register ALT_UART_SCR. */
3118 typedef struct ALT_UART_SCR_s ALT_UART_SCR_t;
3119 #endif /* __ASSEMBLY__ */
3120 
3121 /* The reset value of the ALT_UART_SCR register. */
3122 #define ALT_UART_SCR_RESET 0x00000000
3123 /* The byte offset of the ALT_UART_SCR register from the beginning of the component. */
3124 #define ALT_UART_SCR_OFST 0x1c
3125 /* The address of the ALT_UART_SCR register. */
3126 #define ALT_UART_SCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SCR_OFST))
3127 
3128 /*
3129  * Register : Shadow Receive Buffer Register - SRBR0
3130  *
3131  * Shadow Receive Buffer Register
3132  *
3133  * Register Layout
3134  *
3135  * Bits | Access | Reset | Description
3136  * :-------|:-------|:------|:--------------------------------
3137  * [7:0] | R | 0x0 | ALT_UART_SRBR0_SRBR0
3138  * [31:8] | R | 0x0 | ALT_UART_SRBR0_RSVD_SRBR0_31TO8
3139  *
3140  */
3141 /*
3142  * Field : srbr0
3143  *
3144  * Shadow Receive Buffer Register 0:
3145  *
3146  * This is a shadow register for the RBR and has been allocated sixteen 32-bit
3147  * locations
3148  *
3149  * so as to accommodate burst accesses from the master.
3150  *
3151  * This register contains the data byte received on the serial input port (sin) in
3152  * UART
3153  *
3154  * mode or the serial infrared input (sir_in) in infrared mode. The data in this
3155  * register
3156  *
3157  * is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is
3158  * set.
3159  *
3160  * If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to
3161  * zero), the
3162  *
3163  * data in the RBR must be read before the next data arrives, otherwise it will be
3164  *
3165  * overwritten, resulting in an overrun error.
3166  *
3167  * If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one),
3168  * this
3169  *
3170  * register accesses the head of the receive FIFO. If the receive FIFO is full and
3171  * this
3172  *
3173  * register is not read before the next data character arrives, then the data
3174  * already
3175  *
3176  * in the FIFO will be preserved but any incoming data will be lost. An overrun
3177  * error
3178  *
3179  * will also occur.
3180  *
3181  * Field Access Macros:
3182  *
3183  */
3184 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR0_SRBR0 register field. */
3185 #define ALT_UART_SRBR0_SRBR0_LSB 0
3186 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR0_SRBR0 register field. */
3187 #define ALT_UART_SRBR0_SRBR0_MSB 7
3188 /* The width in bits of the ALT_UART_SRBR0_SRBR0 register field. */
3189 #define ALT_UART_SRBR0_SRBR0_WIDTH 8
3190 /* The mask used to set the ALT_UART_SRBR0_SRBR0 register field value. */
3191 #define ALT_UART_SRBR0_SRBR0_SET_MSK 0x000000ff
3192 /* The mask used to clear the ALT_UART_SRBR0_SRBR0 register field value. */
3193 #define ALT_UART_SRBR0_SRBR0_CLR_MSK 0xffffff00
3194 /* The reset value of the ALT_UART_SRBR0_SRBR0 register field. */
3195 #define ALT_UART_SRBR0_SRBR0_RESET 0x0
3196 /* Extracts the ALT_UART_SRBR0_SRBR0 field value from a register. */
3197 #define ALT_UART_SRBR0_SRBR0_GET(value) (((value) & 0x000000ff) >> 0)
3198 /* Produces a ALT_UART_SRBR0_SRBR0 register field value suitable for setting the register. */
3199 #define ALT_UART_SRBR0_SRBR0_SET(value) (((value) << 0) & 0x000000ff)
3200 
3201 /*
3202  * Field : RSVD_SRBR0_31to8
3203  *
3204  * Reserved bits [31:8] - Read Only
3205  *
3206  * Field Access Macros:
3207  *
3208  */
3209 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR0_RSVD_SRBR0_31TO8 register field. */
3210 #define ALT_UART_SRBR0_RSVD_SRBR0_31TO8_LSB 8
3211 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR0_RSVD_SRBR0_31TO8 register field. */
3212 #define ALT_UART_SRBR0_RSVD_SRBR0_31TO8_MSB 31
3213 /* The width in bits of the ALT_UART_SRBR0_RSVD_SRBR0_31TO8 register field. */
3214 #define ALT_UART_SRBR0_RSVD_SRBR0_31TO8_WIDTH 24
3215 /* The mask used to set the ALT_UART_SRBR0_RSVD_SRBR0_31TO8 register field value. */
3216 #define ALT_UART_SRBR0_RSVD_SRBR0_31TO8_SET_MSK 0xffffff00
3217 /* The mask used to clear the ALT_UART_SRBR0_RSVD_SRBR0_31TO8 register field value. */
3218 #define ALT_UART_SRBR0_RSVD_SRBR0_31TO8_CLR_MSK 0x000000ff
3219 /* The reset value of the ALT_UART_SRBR0_RSVD_SRBR0_31TO8 register field. */
3220 #define ALT_UART_SRBR0_RSVD_SRBR0_31TO8_RESET 0x0
3221 /* Extracts the ALT_UART_SRBR0_RSVD_SRBR0_31TO8 field value from a register. */
3222 #define ALT_UART_SRBR0_RSVD_SRBR0_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3223 /* Produces a ALT_UART_SRBR0_RSVD_SRBR0_31TO8 register field value suitable for setting the register. */
3224 #define ALT_UART_SRBR0_RSVD_SRBR0_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3225 
3226 #ifndef __ASSEMBLY__
3227 /*
3228  * WARNING: The C register and register group struct declarations are provided for
3229  * convenience and illustrative purposes. They should, however, be used with
3230  * caution as the C language standard provides no guarantees about the alignment or
3231  * atomicity of device memory accesses. The recommended practice for coding device
3232  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3233  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3234  * alt_write_dword() functions for 64 bit registers.
3235  *
3236  * The struct declaration for register ALT_UART_SRBR0.
3237  */
3238 struct ALT_UART_SRBR0_s
3239 {
3240  const volatile uint32_t srbr0 : 8; /* ALT_UART_SRBR0_SRBR0 */
3241  const volatile uint32_t RSVD_SRBR0_31to8 : 24; /* ALT_UART_SRBR0_RSVD_SRBR0_31TO8 */
3242 };
3243 
3244 /* The typedef declaration for register ALT_UART_SRBR0. */
3245 typedef struct ALT_UART_SRBR0_s ALT_UART_SRBR0_t;
3246 #endif /* __ASSEMBLY__ */
3247 
3248 /* The reset value of the ALT_UART_SRBR0 register. */
3249 #define ALT_UART_SRBR0_RESET 0x00000000
3250 /* The byte offset of the ALT_UART_SRBR0 register from the beginning of the component. */
3251 #define ALT_UART_SRBR0_OFST 0x30
3252 /* The address of the ALT_UART_SRBR0 register. */
3253 #define ALT_UART_SRBR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR0_OFST))
3254 
3255 /*
3256  * Register : Shadow Receive Buffer Register 1 - SRBR1
3257  *
3258  * Shadow Receive Buffer Register 1
3259  *
3260  * Register Layout
3261  *
3262  * Bits | Access | Reset | Description
3263  * :-------|:-------|:------|:--------------------------------
3264  * [7:0] | R | 0x0 | ALT_UART_SRBR1_SRBR1
3265  * [31:8] | R | 0x0 | ALT_UART_SRBR1_RSVD_SRBR1_31TO8
3266  *
3267  */
3268 /*
3269  * Field : srbr1
3270  *
3271  * See srbr0 description
3272  *
3273  * Field Access Macros:
3274  *
3275  */
3276 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR1_SRBR1 register field. */
3277 #define ALT_UART_SRBR1_SRBR1_LSB 0
3278 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR1_SRBR1 register field. */
3279 #define ALT_UART_SRBR1_SRBR1_MSB 7
3280 /* The width in bits of the ALT_UART_SRBR1_SRBR1 register field. */
3281 #define ALT_UART_SRBR1_SRBR1_WIDTH 8
3282 /* The mask used to set the ALT_UART_SRBR1_SRBR1 register field value. */
3283 #define ALT_UART_SRBR1_SRBR1_SET_MSK 0x000000ff
3284 /* The mask used to clear the ALT_UART_SRBR1_SRBR1 register field value. */
3285 #define ALT_UART_SRBR1_SRBR1_CLR_MSK 0xffffff00
3286 /* The reset value of the ALT_UART_SRBR1_SRBR1 register field. */
3287 #define ALT_UART_SRBR1_SRBR1_RESET 0x0
3288 /* Extracts the ALT_UART_SRBR1_SRBR1 field value from a register. */
3289 #define ALT_UART_SRBR1_SRBR1_GET(value) (((value) & 0x000000ff) >> 0)
3290 /* Produces a ALT_UART_SRBR1_SRBR1 register field value suitable for setting the register. */
3291 #define ALT_UART_SRBR1_SRBR1_SET(value) (((value) << 0) & 0x000000ff)
3292 
3293 /*
3294  * Field : RSVD_SRBR1_31to8
3295  *
3296  * Reserved bits [31:8] - Read Only
3297  *
3298  * Field Access Macros:
3299  *
3300  */
3301 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR1_RSVD_SRBR1_31TO8 register field. */
3302 #define ALT_UART_SRBR1_RSVD_SRBR1_31TO8_LSB 8
3303 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR1_RSVD_SRBR1_31TO8 register field. */
3304 #define ALT_UART_SRBR1_RSVD_SRBR1_31TO8_MSB 31
3305 /* The width in bits of the ALT_UART_SRBR1_RSVD_SRBR1_31TO8 register field. */
3306 #define ALT_UART_SRBR1_RSVD_SRBR1_31TO8_WIDTH 24
3307 /* The mask used to set the ALT_UART_SRBR1_RSVD_SRBR1_31TO8 register field value. */
3308 #define ALT_UART_SRBR1_RSVD_SRBR1_31TO8_SET_MSK 0xffffff00
3309 /* The mask used to clear the ALT_UART_SRBR1_RSVD_SRBR1_31TO8 register field value. */
3310 #define ALT_UART_SRBR1_RSVD_SRBR1_31TO8_CLR_MSK 0x000000ff
3311 /* The reset value of the ALT_UART_SRBR1_RSVD_SRBR1_31TO8 register field. */
3312 #define ALT_UART_SRBR1_RSVD_SRBR1_31TO8_RESET 0x0
3313 /* Extracts the ALT_UART_SRBR1_RSVD_SRBR1_31TO8 field value from a register. */
3314 #define ALT_UART_SRBR1_RSVD_SRBR1_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3315 /* Produces a ALT_UART_SRBR1_RSVD_SRBR1_31TO8 register field value suitable for setting the register. */
3316 #define ALT_UART_SRBR1_RSVD_SRBR1_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3317 
3318 #ifndef __ASSEMBLY__
3319 /*
3320  * WARNING: The C register and register group struct declarations are provided for
3321  * convenience and illustrative purposes. They should, however, be used with
3322  * caution as the C language standard provides no guarantees about the alignment or
3323  * atomicity of device memory accesses. The recommended practice for coding device
3324  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3325  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3326  * alt_write_dword() functions for 64 bit registers.
3327  *
3328  * The struct declaration for register ALT_UART_SRBR1.
3329  */
3330 struct ALT_UART_SRBR1_s
3331 {
3332  const volatile uint32_t srbr1 : 8; /* ALT_UART_SRBR1_SRBR1 */
3333  const volatile uint32_t RSVD_SRBR1_31to8 : 24; /* ALT_UART_SRBR1_RSVD_SRBR1_31TO8 */
3334 };
3335 
3336 /* The typedef declaration for register ALT_UART_SRBR1. */
3337 typedef struct ALT_UART_SRBR1_s ALT_UART_SRBR1_t;
3338 #endif /* __ASSEMBLY__ */
3339 
3340 /* The reset value of the ALT_UART_SRBR1 register. */
3341 #define ALT_UART_SRBR1_RESET 0x00000000
3342 /* The byte offset of the ALT_UART_SRBR1 register from the beginning of the component. */
3343 #define ALT_UART_SRBR1_OFST 0x34
3344 /* The address of the ALT_UART_SRBR1 register. */
3345 #define ALT_UART_SRBR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR1_OFST))
3346 
3347 /*
3348  * Register : Shadow Receive Buffer Register 2 - SRBR2
3349  *
3350  * Shadow Receive Buffer Register 2
3351  *
3352  * Register Layout
3353  *
3354  * Bits | Access | Reset | Description
3355  * :-------|:-------|:------|:--------------------------------
3356  * [7:0] | R | 0x0 | ALT_UART_SRBR2_SRBR2
3357  * [31:8] | R | 0x0 | ALT_UART_SRBR2_RSVD_SRBR2_31TO8
3358  *
3359  */
3360 /*
3361  * Field : srbr2
3362  *
3363  * See srbr0 description
3364  *
3365  * Field Access Macros:
3366  *
3367  */
3368 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR2_SRBR2 register field. */
3369 #define ALT_UART_SRBR2_SRBR2_LSB 0
3370 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR2_SRBR2 register field. */
3371 #define ALT_UART_SRBR2_SRBR2_MSB 7
3372 /* The width in bits of the ALT_UART_SRBR2_SRBR2 register field. */
3373 #define ALT_UART_SRBR2_SRBR2_WIDTH 8
3374 /* The mask used to set the ALT_UART_SRBR2_SRBR2 register field value. */
3375 #define ALT_UART_SRBR2_SRBR2_SET_MSK 0x000000ff
3376 /* The mask used to clear the ALT_UART_SRBR2_SRBR2 register field value. */
3377 #define ALT_UART_SRBR2_SRBR2_CLR_MSK 0xffffff00
3378 /* The reset value of the ALT_UART_SRBR2_SRBR2 register field. */
3379 #define ALT_UART_SRBR2_SRBR2_RESET 0x0
3380 /* Extracts the ALT_UART_SRBR2_SRBR2 field value from a register. */
3381 #define ALT_UART_SRBR2_SRBR2_GET(value) (((value) & 0x000000ff) >> 0)
3382 /* Produces a ALT_UART_SRBR2_SRBR2 register field value suitable for setting the register. */
3383 #define ALT_UART_SRBR2_SRBR2_SET(value) (((value) << 0) & 0x000000ff)
3384 
3385 /*
3386  * Field : RSVD_SRBR2_31to8
3387  *
3388  * Reserved bits [31:8] - Read Only
3389  *
3390  * Field Access Macros:
3391  *
3392  */
3393 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR2_RSVD_SRBR2_31TO8 register field. */
3394 #define ALT_UART_SRBR2_RSVD_SRBR2_31TO8_LSB 8
3395 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR2_RSVD_SRBR2_31TO8 register field. */
3396 #define ALT_UART_SRBR2_RSVD_SRBR2_31TO8_MSB 31
3397 /* The width in bits of the ALT_UART_SRBR2_RSVD_SRBR2_31TO8 register field. */
3398 #define ALT_UART_SRBR2_RSVD_SRBR2_31TO8_WIDTH 24
3399 /* The mask used to set the ALT_UART_SRBR2_RSVD_SRBR2_31TO8 register field value. */
3400 #define ALT_UART_SRBR2_RSVD_SRBR2_31TO8_SET_MSK 0xffffff00
3401 /* The mask used to clear the ALT_UART_SRBR2_RSVD_SRBR2_31TO8 register field value. */
3402 #define ALT_UART_SRBR2_RSVD_SRBR2_31TO8_CLR_MSK 0x000000ff
3403 /* The reset value of the ALT_UART_SRBR2_RSVD_SRBR2_31TO8 register field. */
3404 #define ALT_UART_SRBR2_RSVD_SRBR2_31TO8_RESET 0x0
3405 /* Extracts the ALT_UART_SRBR2_RSVD_SRBR2_31TO8 field value from a register. */
3406 #define ALT_UART_SRBR2_RSVD_SRBR2_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3407 /* Produces a ALT_UART_SRBR2_RSVD_SRBR2_31TO8 register field value suitable for setting the register. */
3408 #define ALT_UART_SRBR2_RSVD_SRBR2_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3409 
3410 #ifndef __ASSEMBLY__
3411 /*
3412  * WARNING: The C register and register group struct declarations are provided for
3413  * convenience and illustrative purposes. They should, however, be used with
3414  * caution as the C language standard provides no guarantees about the alignment or
3415  * atomicity of device memory accesses. The recommended practice for coding device
3416  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3417  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3418  * alt_write_dword() functions for 64 bit registers.
3419  *
3420  * The struct declaration for register ALT_UART_SRBR2.
3421  */
3422 struct ALT_UART_SRBR2_s
3423 {
3424  const volatile uint32_t srbr2 : 8; /* ALT_UART_SRBR2_SRBR2 */
3425  const volatile uint32_t RSVD_SRBR2_31to8 : 24; /* ALT_UART_SRBR2_RSVD_SRBR2_31TO8 */
3426 };
3427 
3428 /* The typedef declaration for register ALT_UART_SRBR2. */
3429 typedef struct ALT_UART_SRBR2_s ALT_UART_SRBR2_t;
3430 #endif /* __ASSEMBLY__ */
3431 
3432 /* The reset value of the ALT_UART_SRBR2 register. */
3433 #define ALT_UART_SRBR2_RESET 0x00000000
3434 /* The byte offset of the ALT_UART_SRBR2 register from the beginning of the component. */
3435 #define ALT_UART_SRBR2_OFST 0x38
3436 /* The address of the ALT_UART_SRBR2 register. */
3437 #define ALT_UART_SRBR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR2_OFST))
3438 
3439 /*
3440  * Register : Shadow Receive Buffer Register 3 - SRBR3
3441  *
3442  * Shadow Receive Buffer Register 3
3443  *
3444  * Register Layout
3445  *
3446  * Bits | Access | Reset | Description
3447  * :-------|:-------|:------|:--------------------------------
3448  * [7:0] | R | 0x0 | ALT_UART_SRBR3_SRBR3
3449  * [31:8] | R | 0x0 | ALT_UART_SRBR3_RSVD_SRBR3_31TO8
3450  *
3451  */
3452 /*
3453  * Field : srbr3
3454  *
3455  * See srbr0 description
3456  *
3457  * Field Access Macros:
3458  *
3459  */
3460 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR3_SRBR3 register field. */
3461 #define ALT_UART_SRBR3_SRBR3_LSB 0
3462 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR3_SRBR3 register field. */
3463 #define ALT_UART_SRBR3_SRBR3_MSB 7
3464 /* The width in bits of the ALT_UART_SRBR3_SRBR3 register field. */
3465 #define ALT_UART_SRBR3_SRBR3_WIDTH 8
3466 /* The mask used to set the ALT_UART_SRBR3_SRBR3 register field value. */
3467 #define ALT_UART_SRBR3_SRBR3_SET_MSK 0x000000ff
3468 /* The mask used to clear the ALT_UART_SRBR3_SRBR3 register field value. */
3469 #define ALT_UART_SRBR3_SRBR3_CLR_MSK 0xffffff00
3470 /* The reset value of the ALT_UART_SRBR3_SRBR3 register field. */
3471 #define ALT_UART_SRBR3_SRBR3_RESET 0x0
3472 /* Extracts the ALT_UART_SRBR3_SRBR3 field value from a register. */
3473 #define ALT_UART_SRBR3_SRBR3_GET(value) (((value) & 0x000000ff) >> 0)
3474 /* Produces a ALT_UART_SRBR3_SRBR3 register field value suitable for setting the register. */
3475 #define ALT_UART_SRBR3_SRBR3_SET(value) (((value) << 0) & 0x000000ff)
3476 
3477 /*
3478  * Field : RSVD_SRBR3_31to8
3479  *
3480  * Reserved bits [31:8] - Read Only
3481  *
3482  * Field Access Macros:
3483  *
3484  */
3485 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR3_RSVD_SRBR3_31TO8 register field. */
3486 #define ALT_UART_SRBR3_RSVD_SRBR3_31TO8_LSB 8
3487 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR3_RSVD_SRBR3_31TO8 register field. */
3488 #define ALT_UART_SRBR3_RSVD_SRBR3_31TO8_MSB 31
3489 /* The width in bits of the ALT_UART_SRBR3_RSVD_SRBR3_31TO8 register field. */
3490 #define ALT_UART_SRBR3_RSVD_SRBR3_31TO8_WIDTH 24
3491 /* The mask used to set the ALT_UART_SRBR3_RSVD_SRBR3_31TO8 register field value. */
3492 #define ALT_UART_SRBR3_RSVD_SRBR3_31TO8_SET_MSK 0xffffff00
3493 /* The mask used to clear the ALT_UART_SRBR3_RSVD_SRBR3_31TO8 register field value. */
3494 #define ALT_UART_SRBR3_RSVD_SRBR3_31TO8_CLR_MSK 0x000000ff
3495 /* The reset value of the ALT_UART_SRBR3_RSVD_SRBR3_31TO8 register field. */
3496 #define ALT_UART_SRBR3_RSVD_SRBR3_31TO8_RESET 0x0
3497 /* Extracts the ALT_UART_SRBR3_RSVD_SRBR3_31TO8 field value from a register. */
3498 #define ALT_UART_SRBR3_RSVD_SRBR3_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3499 /* Produces a ALT_UART_SRBR3_RSVD_SRBR3_31TO8 register field value suitable for setting the register. */
3500 #define ALT_UART_SRBR3_RSVD_SRBR3_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3501 
3502 #ifndef __ASSEMBLY__
3503 /*
3504  * WARNING: The C register and register group struct declarations are provided for
3505  * convenience and illustrative purposes. They should, however, be used with
3506  * caution as the C language standard provides no guarantees about the alignment or
3507  * atomicity of device memory accesses. The recommended practice for coding device
3508  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3509  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3510  * alt_write_dword() functions for 64 bit registers.
3511  *
3512  * The struct declaration for register ALT_UART_SRBR3.
3513  */
3514 struct ALT_UART_SRBR3_s
3515 {
3516  const volatile uint32_t srbr3 : 8; /* ALT_UART_SRBR3_SRBR3 */
3517  const volatile uint32_t RSVD_SRBR3_31to8 : 24; /* ALT_UART_SRBR3_RSVD_SRBR3_31TO8 */
3518 };
3519 
3520 /* The typedef declaration for register ALT_UART_SRBR3. */
3521 typedef struct ALT_UART_SRBR3_s ALT_UART_SRBR3_t;
3522 #endif /* __ASSEMBLY__ */
3523 
3524 /* The reset value of the ALT_UART_SRBR3 register. */
3525 #define ALT_UART_SRBR3_RESET 0x00000000
3526 /* The byte offset of the ALT_UART_SRBR3 register from the beginning of the component. */
3527 #define ALT_UART_SRBR3_OFST 0x3c
3528 /* The address of the ALT_UART_SRBR3 register. */
3529 #define ALT_UART_SRBR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR3_OFST))
3530 
3531 /*
3532  * Register : Shadow Receive Buffer Register 4 - SRBR4
3533  *
3534  * Shadow Receive Buffer Register 4
3535  *
3536  * Register Layout
3537  *
3538  * Bits | Access | Reset | Description
3539  * :-------|:-------|:------|:--------------------------------
3540  * [7:0] | R | 0x0 | ALT_UART_SRBR4_SRBR4
3541  * [31:8] | R | 0x0 | ALT_UART_SRBR4_RSVD_SRBR4_31TO8
3542  *
3543  */
3544 /*
3545  * Field : srbr4
3546  *
3547  * See srbr0 description
3548  *
3549  * Field Access Macros:
3550  *
3551  */
3552 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR4_SRBR4 register field. */
3553 #define ALT_UART_SRBR4_SRBR4_LSB 0
3554 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR4_SRBR4 register field. */
3555 #define ALT_UART_SRBR4_SRBR4_MSB 7
3556 /* The width in bits of the ALT_UART_SRBR4_SRBR4 register field. */
3557 #define ALT_UART_SRBR4_SRBR4_WIDTH 8
3558 /* The mask used to set the ALT_UART_SRBR4_SRBR4 register field value. */
3559 #define ALT_UART_SRBR4_SRBR4_SET_MSK 0x000000ff
3560 /* The mask used to clear the ALT_UART_SRBR4_SRBR4 register field value. */
3561 #define ALT_UART_SRBR4_SRBR4_CLR_MSK 0xffffff00
3562 /* The reset value of the ALT_UART_SRBR4_SRBR4 register field. */
3563 #define ALT_UART_SRBR4_SRBR4_RESET 0x0
3564 /* Extracts the ALT_UART_SRBR4_SRBR4 field value from a register. */
3565 #define ALT_UART_SRBR4_SRBR4_GET(value) (((value) & 0x000000ff) >> 0)
3566 /* Produces a ALT_UART_SRBR4_SRBR4 register field value suitable for setting the register. */
3567 #define ALT_UART_SRBR4_SRBR4_SET(value) (((value) << 0) & 0x000000ff)
3568 
3569 /*
3570  * Field : RSVD_SRBR4_31to8
3571  *
3572  * Reserved bits [31:8] - Read Only
3573  *
3574  * Field Access Macros:
3575  *
3576  */
3577 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR4_RSVD_SRBR4_31TO8 register field. */
3578 #define ALT_UART_SRBR4_RSVD_SRBR4_31TO8_LSB 8
3579 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR4_RSVD_SRBR4_31TO8 register field. */
3580 #define ALT_UART_SRBR4_RSVD_SRBR4_31TO8_MSB 31
3581 /* The width in bits of the ALT_UART_SRBR4_RSVD_SRBR4_31TO8 register field. */
3582 #define ALT_UART_SRBR4_RSVD_SRBR4_31TO8_WIDTH 24
3583 /* The mask used to set the ALT_UART_SRBR4_RSVD_SRBR4_31TO8 register field value. */
3584 #define ALT_UART_SRBR4_RSVD_SRBR4_31TO8_SET_MSK 0xffffff00
3585 /* The mask used to clear the ALT_UART_SRBR4_RSVD_SRBR4_31TO8 register field value. */
3586 #define ALT_UART_SRBR4_RSVD_SRBR4_31TO8_CLR_MSK 0x000000ff
3587 /* The reset value of the ALT_UART_SRBR4_RSVD_SRBR4_31TO8 register field. */
3588 #define ALT_UART_SRBR4_RSVD_SRBR4_31TO8_RESET 0x0
3589 /* Extracts the ALT_UART_SRBR4_RSVD_SRBR4_31TO8 field value from a register. */
3590 #define ALT_UART_SRBR4_RSVD_SRBR4_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3591 /* Produces a ALT_UART_SRBR4_RSVD_SRBR4_31TO8 register field value suitable for setting the register. */
3592 #define ALT_UART_SRBR4_RSVD_SRBR4_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3593 
3594 #ifndef __ASSEMBLY__
3595 /*
3596  * WARNING: The C register and register group struct declarations are provided for
3597  * convenience and illustrative purposes. They should, however, be used with
3598  * caution as the C language standard provides no guarantees about the alignment or
3599  * atomicity of device memory accesses. The recommended practice for coding device
3600  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3601  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3602  * alt_write_dword() functions for 64 bit registers.
3603  *
3604  * The struct declaration for register ALT_UART_SRBR4.
3605  */
3606 struct ALT_UART_SRBR4_s
3607 {
3608  const volatile uint32_t srbr4 : 8; /* ALT_UART_SRBR4_SRBR4 */
3609  const volatile uint32_t RSVD_SRBR4_31to8 : 24; /* ALT_UART_SRBR4_RSVD_SRBR4_31TO8 */
3610 };
3611 
3612 /* The typedef declaration for register ALT_UART_SRBR4. */
3613 typedef struct ALT_UART_SRBR4_s ALT_UART_SRBR4_t;
3614 #endif /* __ASSEMBLY__ */
3615 
3616 /* The reset value of the ALT_UART_SRBR4 register. */
3617 #define ALT_UART_SRBR4_RESET 0x00000000
3618 /* The byte offset of the ALT_UART_SRBR4 register from the beginning of the component. */
3619 #define ALT_UART_SRBR4_OFST 0x40
3620 /* The address of the ALT_UART_SRBR4 register. */
3621 #define ALT_UART_SRBR4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR4_OFST))
3622 
3623 /*
3624  * Register : Shadow Receive Buffer Register 5 - SRBR5
3625  *
3626  * Shadow Receive Buffer Register 5
3627  *
3628  * Register Layout
3629  *
3630  * Bits | Access | Reset | Description
3631  * :-------|:-------|:------|:--------------------------------
3632  * [7:0] | R | 0x0 | ALT_UART_SRBR5_SRBR5
3633  * [31:8] | R | 0x0 | ALT_UART_SRBR5_RSVD_SRBR5_31TO8
3634  *
3635  */
3636 /*
3637  * Field : srbr5
3638  *
3639  * See srbr0 description
3640  *
3641  * Field Access Macros:
3642  *
3643  */
3644 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR5_SRBR5 register field. */
3645 #define ALT_UART_SRBR5_SRBR5_LSB 0
3646 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR5_SRBR5 register field. */
3647 #define ALT_UART_SRBR5_SRBR5_MSB 7
3648 /* The width in bits of the ALT_UART_SRBR5_SRBR5 register field. */
3649 #define ALT_UART_SRBR5_SRBR5_WIDTH 8
3650 /* The mask used to set the ALT_UART_SRBR5_SRBR5 register field value. */
3651 #define ALT_UART_SRBR5_SRBR5_SET_MSK 0x000000ff
3652 /* The mask used to clear the ALT_UART_SRBR5_SRBR5 register field value. */
3653 #define ALT_UART_SRBR5_SRBR5_CLR_MSK 0xffffff00
3654 /* The reset value of the ALT_UART_SRBR5_SRBR5 register field. */
3655 #define ALT_UART_SRBR5_SRBR5_RESET 0x0
3656 /* Extracts the ALT_UART_SRBR5_SRBR5 field value from a register. */
3657 #define ALT_UART_SRBR5_SRBR5_GET(value) (((value) & 0x000000ff) >> 0)
3658 /* Produces a ALT_UART_SRBR5_SRBR5 register field value suitable for setting the register. */
3659 #define ALT_UART_SRBR5_SRBR5_SET(value) (((value) << 0) & 0x000000ff)
3660 
3661 /*
3662  * Field : RSVD_SRBR5_31to8
3663  *
3664  * Reserved bits [31:8] - Read Only
3665  *
3666  * Field Access Macros:
3667  *
3668  */
3669 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR5_RSVD_SRBR5_31TO8 register field. */
3670 #define ALT_UART_SRBR5_RSVD_SRBR5_31TO8_LSB 8
3671 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR5_RSVD_SRBR5_31TO8 register field. */
3672 #define ALT_UART_SRBR5_RSVD_SRBR5_31TO8_MSB 31
3673 /* The width in bits of the ALT_UART_SRBR5_RSVD_SRBR5_31TO8 register field. */
3674 #define ALT_UART_SRBR5_RSVD_SRBR5_31TO8_WIDTH 24
3675 /* The mask used to set the ALT_UART_SRBR5_RSVD_SRBR5_31TO8 register field value. */
3676 #define ALT_UART_SRBR5_RSVD_SRBR5_31TO8_SET_MSK 0xffffff00
3677 /* The mask used to clear the ALT_UART_SRBR5_RSVD_SRBR5_31TO8 register field value. */
3678 #define ALT_UART_SRBR5_RSVD_SRBR5_31TO8_CLR_MSK 0x000000ff
3679 /* The reset value of the ALT_UART_SRBR5_RSVD_SRBR5_31TO8 register field. */
3680 #define ALT_UART_SRBR5_RSVD_SRBR5_31TO8_RESET 0x0
3681 /* Extracts the ALT_UART_SRBR5_RSVD_SRBR5_31TO8 field value from a register. */
3682 #define ALT_UART_SRBR5_RSVD_SRBR5_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3683 /* Produces a ALT_UART_SRBR5_RSVD_SRBR5_31TO8 register field value suitable for setting the register. */
3684 #define ALT_UART_SRBR5_RSVD_SRBR5_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3685 
3686 #ifndef __ASSEMBLY__
3687 /*
3688  * WARNING: The C register and register group struct declarations are provided for
3689  * convenience and illustrative purposes. They should, however, be used with
3690  * caution as the C language standard provides no guarantees about the alignment or
3691  * atomicity of device memory accesses. The recommended practice for coding device
3692  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3693  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3694  * alt_write_dword() functions for 64 bit registers.
3695  *
3696  * The struct declaration for register ALT_UART_SRBR5.
3697  */
3698 struct ALT_UART_SRBR5_s
3699 {
3700  const volatile uint32_t srbr5 : 8; /* ALT_UART_SRBR5_SRBR5 */
3701  const volatile uint32_t RSVD_SRBR5_31to8 : 24; /* ALT_UART_SRBR5_RSVD_SRBR5_31TO8 */
3702 };
3703 
3704 /* The typedef declaration for register ALT_UART_SRBR5. */
3705 typedef struct ALT_UART_SRBR5_s ALT_UART_SRBR5_t;
3706 #endif /* __ASSEMBLY__ */
3707 
3708 /* The reset value of the ALT_UART_SRBR5 register. */
3709 #define ALT_UART_SRBR5_RESET 0x00000000
3710 /* The byte offset of the ALT_UART_SRBR5 register from the beginning of the component. */
3711 #define ALT_UART_SRBR5_OFST 0x44
3712 /* The address of the ALT_UART_SRBR5 register. */
3713 #define ALT_UART_SRBR5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR5_OFST))
3714 
3715 /*
3716  * Register : Shadow Receive Buffer Register 6 - SRBR6
3717  *
3718  * Shadow Receive Buffer Register 6
3719  *
3720  * Register Layout
3721  *
3722  * Bits | Access | Reset | Description
3723  * :-------|:-------|:------|:--------------------------------
3724  * [7:0] | R | 0x0 | ALT_UART_SRBR6_SRBR6
3725  * [31:8] | R | 0x0 | ALT_UART_SRBR6_RSVD_SRBR6_31TO8
3726  *
3727  */
3728 /*
3729  * Field : srbr6
3730  *
3731  * See srbr0 description
3732  *
3733  * Field Access Macros:
3734  *
3735  */
3736 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR6_SRBR6 register field. */
3737 #define ALT_UART_SRBR6_SRBR6_LSB 0
3738 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR6_SRBR6 register field. */
3739 #define ALT_UART_SRBR6_SRBR6_MSB 7
3740 /* The width in bits of the ALT_UART_SRBR6_SRBR6 register field. */
3741 #define ALT_UART_SRBR6_SRBR6_WIDTH 8
3742 /* The mask used to set the ALT_UART_SRBR6_SRBR6 register field value. */
3743 #define ALT_UART_SRBR6_SRBR6_SET_MSK 0x000000ff
3744 /* The mask used to clear the ALT_UART_SRBR6_SRBR6 register field value. */
3745 #define ALT_UART_SRBR6_SRBR6_CLR_MSK 0xffffff00
3746 /* The reset value of the ALT_UART_SRBR6_SRBR6 register field. */
3747 #define ALT_UART_SRBR6_SRBR6_RESET 0x0
3748 /* Extracts the ALT_UART_SRBR6_SRBR6 field value from a register. */
3749 #define ALT_UART_SRBR6_SRBR6_GET(value) (((value) & 0x000000ff) >> 0)
3750 /* Produces a ALT_UART_SRBR6_SRBR6 register field value suitable for setting the register. */
3751 #define ALT_UART_SRBR6_SRBR6_SET(value) (((value) << 0) & 0x000000ff)
3752 
3753 /*
3754  * Field : RSVD_SRBR6_31to8
3755  *
3756  * Reserved bits [31:8] - Read Only
3757  *
3758  * Field Access Macros:
3759  *
3760  */
3761 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR6_RSVD_SRBR6_31TO8 register field. */
3762 #define ALT_UART_SRBR6_RSVD_SRBR6_31TO8_LSB 8
3763 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR6_RSVD_SRBR6_31TO8 register field. */
3764 #define ALT_UART_SRBR6_RSVD_SRBR6_31TO8_MSB 31
3765 /* The width in bits of the ALT_UART_SRBR6_RSVD_SRBR6_31TO8 register field. */
3766 #define ALT_UART_SRBR6_RSVD_SRBR6_31TO8_WIDTH 24
3767 /* The mask used to set the ALT_UART_SRBR6_RSVD_SRBR6_31TO8 register field value. */
3768 #define ALT_UART_SRBR6_RSVD_SRBR6_31TO8_SET_MSK 0xffffff00
3769 /* The mask used to clear the ALT_UART_SRBR6_RSVD_SRBR6_31TO8 register field value. */
3770 #define ALT_UART_SRBR6_RSVD_SRBR6_31TO8_CLR_MSK 0x000000ff
3771 /* The reset value of the ALT_UART_SRBR6_RSVD_SRBR6_31TO8 register field. */
3772 #define ALT_UART_SRBR6_RSVD_SRBR6_31TO8_RESET 0x0
3773 /* Extracts the ALT_UART_SRBR6_RSVD_SRBR6_31TO8 field value from a register. */
3774 #define ALT_UART_SRBR6_RSVD_SRBR6_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3775 /* Produces a ALT_UART_SRBR6_RSVD_SRBR6_31TO8 register field value suitable for setting the register. */
3776 #define ALT_UART_SRBR6_RSVD_SRBR6_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3777 
3778 #ifndef __ASSEMBLY__
3779 /*
3780  * WARNING: The C register and register group struct declarations are provided for
3781  * convenience and illustrative purposes. They should, however, be used with
3782  * caution as the C language standard provides no guarantees about the alignment or
3783  * atomicity of device memory accesses. The recommended practice for coding device
3784  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3785  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3786  * alt_write_dword() functions for 64 bit registers.
3787  *
3788  * The struct declaration for register ALT_UART_SRBR6.
3789  */
3790 struct ALT_UART_SRBR6_s
3791 {
3792  const volatile uint32_t srbr6 : 8; /* ALT_UART_SRBR6_SRBR6 */
3793  const volatile uint32_t RSVD_SRBR6_31to8 : 24; /* ALT_UART_SRBR6_RSVD_SRBR6_31TO8 */
3794 };
3795 
3796 /* The typedef declaration for register ALT_UART_SRBR6. */
3797 typedef struct ALT_UART_SRBR6_s ALT_UART_SRBR6_t;
3798 #endif /* __ASSEMBLY__ */
3799 
3800 /* The reset value of the ALT_UART_SRBR6 register. */
3801 #define ALT_UART_SRBR6_RESET 0x00000000
3802 /* The byte offset of the ALT_UART_SRBR6 register from the beginning of the component. */
3803 #define ALT_UART_SRBR6_OFST 0x48
3804 /* The address of the ALT_UART_SRBR6 register. */
3805 #define ALT_UART_SRBR6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR6_OFST))
3806 
3807 /*
3808  * Register : Shadow Receive Buffer Register 7 - SRBR7
3809  *
3810  * Shadow Receive Buffer Register 7
3811  *
3812  * Register Layout
3813  *
3814  * Bits | Access | Reset | Description
3815  * :-------|:-------|:------|:--------------------------------
3816  * [7:0] | R | 0x0 | ALT_UART_SRBR7_SRBR7
3817  * [31:8] | R | 0x0 | ALT_UART_SRBR7_RSVD_SRBR7_31TO8
3818  *
3819  */
3820 /*
3821  * Field : srbr7
3822  *
3823  * See srbr0 description
3824  *
3825  * Field Access Macros:
3826  *
3827  */
3828 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR7_SRBR7 register field. */
3829 #define ALT_UART_SRBR7_SRBR7_LSB 0
3830 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR7_SRBR7 register field. */
3831 #define ALT_UART_SRBR7_SRBR7_MSB 7
3832 /* The width in bits of the ALT_UART_SRBR7_SRBR7 register field. */
3833 #define ALT_UART_SRBR7_SRBR7_WIDTH 8
3834 /* The mask used to set the ALT_UART_SRBR7_SRBR7 register field value. */
3835 #define ALT_UART_SRBR7_SRBR7_SET_MSK 0x000000ff
3836 /* The mask used to clear the ALT_UART_SRBR7_SRBR7 register field value. */
3837 #define ALT_UART_SRBR7_SRBR7_CLR_MSK 0xffffff00
3838 /* The reset value of the ALT_UART_SRBR7_SRBR7 register field. */
3839 #define ALT_UART_SRBR7_SRBR7_RESET 0x0
3840 /* Extracts the ALT_UART_SRBR7_SRBR7 field value from a register. */
3841 #define ALT_UART_SRBR7_SRBR7_GET(value) (((value) & 0x000000ff) >> 0)
3842 /* Produces a ALT_UART_SRBR7_SRBR7 register field value suitable for setting the register. */
3843 #define ALT_UART_SRBR7_SRBR7_SET(value) (((value) << 0) & 0x000000ff)
3844 
3845 /*
3846  * Field : RSVD_SRBR7_31to8
3847  *
3848  * Reserved bits [31:8] - Read Only
3849  *
3850  * Field Access Macros:
3851  *
3852  */
3853 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR7_RSVD_SRBR7_31TO8 register field. */
3854 #define ALT_UART_SRBR7_RSVD_SRBR7_31TO8_LSB 8
3855 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR7_RSVD_SRBR7_31TO8 register field. */
3856 #define ALT_UART_SRBR7_RSVD_SRBR7_31TO8_MSB 31
3857 /* The width in bits of the ALT_UART_SRBR7_RSVD_SRBR7_31TO8 register field. */
3858 #define ALT_UART_SRBR7_RSVD_SRBR7_31TO8_WIDTH 24
3859 /* The mask used to set the ALT_UART_SRBR7_RSVD_SRBR7_31TO8 register field value. */
3860 #define ALT_UART_SRBR7_RSVD_SRBR7_31TO8_SET_MSK 0xffffff00
3861 /* The mask used to clear the ALT_UART_SRBR7_RSVD_SRBR7_31TO8 register field value. */
3862 #define ALT_UART_SRBR7_RSVD_SRBR7_31TO8_CLR_MSK 0x000000ff
3863 /* The reset value of the ALT_UART_SRBR7_RSVD_SRBR7_31TO8 register field. */
3864 #define ALT_UART_SRBR7_RSVD_SRBR7_31TO8_RESET 0x0
3865 /* Extracts the ALT_UART_SRBR7_RSVD_SRBR7_31TO8 field value from a register. */
3866 #define ALT_UART_SRBR7_RSVD_SRBR7_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3867 /* Produces a ALT_UART_SRBR7_RSVD_SRBR7_31TO8 register field value suitable for setting the register. */
3868 #define ALT_UART_SRBR7_RSVD_SRBR7_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3869 
3870 #ifndef __ASSEMBLY__
3871 /*
3872  * WARNING: The C register and register group struct declarations are provided for
3873  * convenience and illustrative purposes. They should, however, be used with
3874  * caution as the C language standard provides no guarantees about the alignment or
3875  * atomicity of device memory accesses. The recommended practice for coding device
3876  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3877  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3878  * alt_write_dword() functions for 64 bit registers.
3879  *
3880  * The struct declaration for register ALT_UART_SRBR7.
3881  */
3882 struct ALT_UART_SRBR7_s
3883 {
3884  const volatile uint32_t srbr7 : 8; /* ALT_UART_SRBR7_SRBR7 */
3885  const volatile uint32_t RSVD_SRBR7_31to8 : 24; /* ALT_UART_SRBR7_RSVD_SRBR7_31TO8 */
3886 };
3887 
3888 /* The typedef declaration for register ALT_UART_SRBR7. */
3889 typedef struct ALT_UART_SRBR7_s ALT_UART_SRBR7_t;
3890 #endif /* __ASSEMBLY__ */
3891 
3892 /* The reset value of the ALT_UART_SRBR7 register. */
3893 #define ALT_UART_SRBR7_RESET 0x00000000
3894 /* The byte offset of the ALT_UART_SRBR7 register from the beginning of the component. */
3895 #define ALT_UART_SRBR7_OFST 0x4c
3896 /* The address of the ALT_UART_SRBR7 register. */
3897 #define ALT_UART_SRBR7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR7_OFST))
3898 
3899 /*
3900  * Register : Shadow Receive Buffer Register 8 - SRBR8
3901  *
3902  * Shadow Receive Buffer Register 8
3903  *
3904  * Register Layout
3905  *
3906  * Bits | Access | Reset | Description
3907  * :-------|:-------|:------|:--------------------------------
3908  * [7:0] | R | 0x0 | ALT_UART_SRBR8_SRBR8
3909  * [31:8] | R | 0x0 | ALT_UART_SRBR8_RSVD_SRBR8_31TO8
3910  *
3911  */
3912 /*
3913  * Field : srbr8
3914  *
3915  * See srbr0 description
3916  *
3917  * Field Access Macros:
3918  *
3919  */
3920 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR8_SRBR8 register field. */
3921 #define ALT_UART_SRBR8_SRBR8_LSB 0
3922 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR8_SRBR8 register field. */
3923 #define ALT_UART_SRBR8_SRBR8_MSB 7
3924 /* The width in bits of the ALT_UART_SRBR8_SRBR8 register field. */
3925 #define ALT_UART_SRBR8_SRBR8_WIDTH 8
3926 /* The mask used to set the ALT_UART_SRBR8_SRBR8 register field value. */
3927 #define ALT_UART_SRBR8_SRBR8_SET_MSK 0x000000ff
3928 /* The mask used to clear the ALT_UART_SRBR8_SRBR8 register field value. */
3929 #define ALT_UART_SRBR8_SRBR8_CLR_MSK 0xffffff00
3930 /* The reset value of the ALT_UART_SRBR8_SRBR8 register field. */
3931 #define ALT_UART_SRBR8_SRBR8_RESET 0x0
3932 /* Extracts the ALT_UART_SRBR8_SRBR8 field value from a register. */
3933 #define ALT_UART_SRBR8_SRBR8_GET(value) (((value) & 0x000000ff) >> 0)
3934 /* Produces a ALT_UART_SRBR8_SRBR8 register field value suitable for setting the register. */
3935 #define ALT_UART_SRBR8_SRBR8_SET(value) (((value) << 0) & 0x000000ff)
3936 
3937 /*
3938  * Field : RSVD_SRBR8_31to8
3939  *
3940  * Reserved bits [31:8] - Read Only
3941  *
3942  * Field Access Macros:
3943  *
3944  */
3945 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR8_RSVD_SRBR8_31TO8 register field. */
3946 #define ALT_UART_SRBR8_RSVD_SRBR8_31TO8_LSB 8
3947 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR8_RSVD_SRBR8_31TO8 register field. */
3948 #define ALT_UART_SRBR8_RSVD_SRBR8_31TO8_MSB 31
3949 /* The width in bits of the ALT_UART_SRBR8_RSVD_SRBR8_31TO8 register field. */
3950 #define ALT_UART_SRBR8_RSVD_SRBR8_31TO8_WIDTH 24
3951 /* The mask used to set the ALT_UART_SRBR8_RSVD_SRBR8_31TO8 register field value. */
3952 #define ALT_UART_SRBR8_RSVD_SRBR8_31TO8_SET_MSK 0xffffff00
3953 /* The mask used to clear the ALT_UART_SRBR8_RSVD_SRBR8_31TO8 register field value. */
3954 #define ALT_UART_SRBR8_RSVD_SRBR8_31TO8_CLR_MSK 0x000000ff
3955 /* The reset value of the ALT_UART_SRBR8_RSVD_SRBR8_31TO8 register field. */
3956 #define ALT_UART_SRBR8_RSVD_SRBR8_31TO8_RESET 0x0
3957 /* Extracts the ALT_UART_SRBR8_RSVD_SRBR8_31TO8 field value from a register. */
3958 #define ALT_UART_SRBR8_RSVD_SRBR8_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3959 /* Produces a ALT_UART_SRBR8_RSVD_SRBR8_31TO8 register field value suitable for setting the register. */
3960 #define ALT_UART_SRBR8_RSVD_SRBR8_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3961 
3962 #ifndef __ASSEMBLY__
3963 /*
3964  * WARNING: The C register and register group struct declarations are provided for
3965  * convenience and illustrative purposes. They should, however, be used with
3966  * caution as the C language standard provides no guarantees about the alignment or
3967  * atomicity of device memory accesses. The recommended practice for coding device
3968  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3969  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3970  * alt_write_dword() functions for 64 bit registers.
3971  *
3972  * The struct declaration for register ALT_UART_SRBR8.
3973  */
3974 struct ALT_UART_SRBR8_s
3975 {
3976  const volatile uint32_t srbr8 : 8; /* ALT_UART_SRBR8_SRBR8 */
3977  const volatile uint32_t RSVD_SRBR8_31to8 : 24; /* ALT_UART_SRBR8_RSVD_SRBR8_31TO8 */
3978 };
3979 
3980 /* The typedef declaration for register ALT_UART_SRBR8. */
3981 typedef struct ALT_UART_SRBR8_s ALT_UART_SRBR8_t;
3982 #endif /* __ASSEMBLY__ */
3983 
3984 /* The reset value of the ALT_UART_SRBR8 register. */
3985 #define ALT_UART_SRBR8_RESET 0x00000000
3986 /* The byte offset of the ALT_UART_SRBR8 register from the beginning of the component. */
3987 #define ALT_UART_SRBR8_OFST 0x50
3988 /* The address of the ALT_UART_SRBR8 register. */
3989 #define ALT_UART_SRBR8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR8_OFST))
3990 
3991 /*
3992  * Register : Shadow Receive Buffer Register 9 - SRBR9
3993  *
3994  * Shadow Receive Buffer Register 9
3995  *
3996  * Register Layout
3997  *
3998  * Bits | Access | Reset | Description
3999  * :-------|:-------|:------|:--------------------------------
4000  * [7:0] | R | 0x0 | ALT_UART_SRBR9_SRBR9
4001  * [31:8] | R | 0x0 | ALT_UART_SRBR9_RSVD_SRBR9_31TO8
4002  *
4003  */
4004 /*
4005  * Field : srbr9
4006  *
4007  * See srbr0 description
4008  *
4009  * Field Access Macros:
4010  *
4011  */
4012 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR9_SRBR9 register field. */
4013 #define ALT_UART_SRBR9_SRBR9_LSB 0
4014 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR9_SRBR9 register field. */
4015 #define ALT_UART_SRBR9_SRBR9_MSB 7
4016 /* The width in bits of the ALT_UART_SRBR9_SRBR9 register field. */
4017 #define ALT_UART_SRBR9_SRBR9_WIDTH 8
4018 /* The mask used to set the ALT_UART_SRBR9_SRBR9 register field value. */
4019 #define ALT_UART_SRBR9_SRBR9_SET_MSK 0x000000ff
4020 /* The mask used to clear the ALT_UART_SRBR9_SRBR9 register field value. */
4021 #define ALT_UART_SRBR9_SRBR9_CLR_MSK 0xffffff00
4022 /* The reset value of the ALT_UART_SRBR9_SRBR9 register field. */
4023 #define ALT_UART_SRBR9_SRBR9_RESET 0x0
4024 /* Extracts the ALT_UART_SRBR9_SRBR9 field value from a register. */
4025 #define ALT_UART_SRBR9_SRBR9_GET(value) (((value) & 0x000000ff) >> 0)
4026 /* Produces a ALT_UART_SRBR9_SRBR9 register field value suitable for setting the register. */
4027 #define ALT_UART_SRBR9_SRBR9_SET(value) (((value) << 0) & 0x000000ff)
4028 
4029 /*
4030  * Field : RSVD_SRBR9_31to8
4031  *
4032  * Reserved bits [31:8] - Read Only
4033  *
4034  * Field Access Macros:
4035  *
4036  */
4037 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR9_RSVD_SRBR9_31TO8 register field. */
4038 #define ALT_UART_SRBR9_RSVD_SRBR9_31TO8_LSB 8
4039 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR9_RSVD_SRBR9_31TO8 register field. */
4040 #define ALT_UART_SRBR9_RSVD_SRBR9_31TO8_MSB 31
4041 /* The width in bits of the ALT_UART_SRBR9_RSVD_SRBR9_31TO8 register field. */
4042 #define ALT_UART_SRBR9_RSVD_SRBR9_31TO8_WIDTH 24
4043 /* The mask used to set the ALT_UART_SRBR9_RSVD_SRBR9_31TO8 register field value. */
4044 #define ALT_UART_SRBR9_RSVD_SRBR9_31TO8_SET_MSK 0xffffff00
4045 /* The mask used to clear the ALT_UART_SRBR9_RSVD_SRBR9_31TO8 register field value. */
4046 #define ALT_UART_SRBR9_RSVD_SRBR9_31TO8_CLR_MSK 0x000000ff
4047 /* The reset value of the ALT_UART_SRBR9_RSVD_SRBR9_31TO8 register field. */
4048 #define ALT_UART_SRBR9_RSVD_SRBR9_31TO8_RESET 0x0
4049 /* Extracts the ALT_UART_SRBR9_RSVD_SRBR9_31TO8 field value from a register. */
4050 #define ALT_UART_SRBR9_RSVD_SRBR9_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4051 /* Produces a ALT_UART_SRBR9_RSVD_SRBR9_31TO8 register field value suitable for setting the register. */
4052 #define ALT_UART_SRBR9_RSVD_SRBR9_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4053 
4054 #ifndef __ASSEMBLY__
4055 /*
4056  * WARNING: The C register and register group struct declarations are provided for
4057  * convenience and illustrative purposes. They should, however, be used with
4058  * caution as the C language standard provides no guarantees about the alignment or
4059  * atomicity of device memory accesses. The recommended practice for coding device
4060  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4061  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4062  * alt_write_dword() functions for 64 bit registers.
4063  *
4064  * The struct declaration for register ALT_UART_SRBR9.
4065  */
4066 struct ALT_UART_SRBR9_s
4067 {
4068  const volatile uint32_t srbr9 : 8; /* ALT_UART_SRBR9_SRBR9 */
4069  const volatile uint32_t RSVD_SRBR9_31to8 : 24; /* ALT_UART_SRBR9_RSVD_SRBR9_31TO8 */
4070 };
4071 
4072 /* The typedef declaration for register ALT_UART_SRBR9. */
4073 typedef struct ALT_UART_SRBR9_s ALT_UART_SRBR9_t;
4074 #endif /* __ASSEMBLY__ */
4075 
4076 /* The reset value of the ALT_UART_SRBR9 register. */
4077 #define ALT_UART_SRBR9_RESET 0x00000000
4078 /* The byte offset of the ALT_UART_SRBR9 register from the beginning of the component. */
4079 #define ALT_UART_SRBR9_OFST 0x54
4080 /* The address of the ALT_UART_SRBR9 register. */
4081 #define ALT_UART_SRBR9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR9_OFST))
4082 
4083 /*
4084  * Register : Shadow Receive Buffer Register 10 - SRBR10
4085  *
4086  * Shadow Receive Buffer Register 10
4087  *
4088  * Register Layout
4089  *
4090  * Bits | Access | Reset | Description
4091  * :-------|:-------|:------|:----------------------------------
4092  * [7:0] | R | 0x0 | ALT_UART_SRBR10_SRBR10
4093  * [31:8] | R | 0x0 | ALT_UART_SRBR10_RSVD_SRBR10_31TO8
4094  *
4095  */
4096 /*
4097  * Field : srbr10
4098  *
4099  * See srbr0 description
4100  *
4101  * Field Access Macros:
4102  *
4103  */
4104 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR10_SRBR10 register field. */
4105 #define ALT_UART_SRBR10_SRBR10_LSB 0
4106 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR10_SRBR10 register field. */
4107 #define ALT_UART_SRBR10_SRBR10_MSB 7
4108 /* The width in bits of the ALT_UART_SRBR10_SRBR10 register field. */
4109 #define ALT_UART_SRBR10_SRBR10_WIDTH 8
4110 /* The mask used to set the ALT_UART_SRBR10_SRBR10 register field value. */
4111 #define ALT_UART_SRBR10_SRBR10_SET_MSK 0x000000ff
4112 /* The mask used to clear the ALT_UART_SRBR10_SRBR10 register field value. */
4113 #define ALT_UART_SRBR10_SRBR10_CLR_MSK 0xffffff00
4114 /* The reset value of the ALT_UART_SRBR10_SRBR10 register field. */
4115 #define ALT_UART_SRBR10_SRBR10_RESET 0x0
4116 /* Extracts the ALT_UART_SRBR10_SRBR10 field value from a register. */
4117 #define ALT_UART_SRBR10_SRBR10_GET(value) (((value) & 0x000000ff) >> 0)
4118 /* Produces a ALT_UART_SRBR10_SRBR10 register field value suitable for setting the register. */
4119 #define ALT_UART_SRBR10_SRBR10_SET(value) (((value) << 0) & 0x000000ff)
4120 
4121 /*
4122  * Field : RSVD_SRBR10_31to8
4123  *
4124  * Reserved bits [31:8] - Read Only
4125  *
4126  * Field Access Macros:
4127  *
4128  */
4129 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR10_RSVD_SRBR10_31TO8 register field. */
4130 #define ALT_UART_SRBR10_RSVD_SRBR10_31TO8_LSB 8
4131 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR10_RSVD_SRBR10_31TO8 register field. */
4132 #define ALT_UART_SRBR10_RSVD_SRBR10_31TO8_MSB 31
4133 /* The width in bits of the ALT_UART_SRBR10_RSVD_SRBR10_31TO8 register field. */
4134 #define ALT_UART_SRBR10_RSVD_SRBR10_31TO8_WIDTH 24
4135 /* The mask used to set the ALT_UART_SRBR10_RSVD_SRBR10_31TO8 register field value. */
4136 #define ALT_UART_SRBR10_RSVD_SRBR10_31TO8_SET_MSK 0xffffff00
4137 /* The mask used to clear the ALT_UART_SRBR10_RSVD_SRBR10_31TO8 register field value. */
4138 #define ALT_UART_SRBR10_RSVD_SRBR10_31TO8_CLR_MSK 0x000000ff
4139 /* The reset value of the ALT_UART_SRBR10_RSVD_SRBR10_31TO8 register field. */
4140 #define ALT_UART_SRBR10_RSVD_SRBR10_31TO8_RESET 0x0
4141 /* Extracts the ALT_UART_SRBR10_RSVD_SRBR10_31TO8 field value from a register. */
4142 #define ALT_UART_SRBR10_RSVD_SRBR10_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4143 /* Produces a ALT_UART_SRBR10_RSVD_SRBR10_31TO8 register field value suitable for setting the register. */
4144 #define ALT_UART_SRBR10_RSVD_SRBR10_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4145 
4146 #ifndef __ASSEMBLY__
4147 /*
4148  * WARNING: The C register and register group struct declarations are provided for
4149  * convenience and illustrative purposes. They should, however, be used with
4150  * caution as the C language standard provides no guarantees about the alignment or
4151  * atomicity of device memory accesses. The recommended practice for coding device
4152  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4153  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4154  * alt_write_dword() functions for 64 bit registers.
4155  *
4156  * The struct declaration for register ALT_UART_SRBR10.
4157  */
4158 struct ALT_UART_SRBR10_s
4159 {
4160  const volatile uint32_t srbr10 : 8; /* ALT_UART_SRBR10_SRBR10 */
4161  const volatile uint32_t RSVD_SRBR10_31to8 : 24; /* ALT_UART_SRBR10_RSVD_SRBR10_31TO8 */
4162 };
4163 
4164 /* The typedef declaration for register ALT_UART_SRBR10. */
4165 typedef struct ALT_UART_SRBR10_s ALT_UART_SRBR10_t;
4166 #endif /* __ASSEMBLY__ */
4167 
4168 /* The reset value of the ALT_UART_SRBR10 register. */
4169 #define ALT_UART_SRBR10_RESET 0x00000000
4170 /* The byte offset of the ALT_UART_SRBR10 register from the beginning of the component. */
4171 #define ALT_UART_SRBR10_OFST 0x58
4172 /* The address of the ALT_UART_SRBR10 register. */
4173 #define ALT_UART_SRBR10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR10_OFST))
4174 
4175 /*
4176  * Register : Shadow Receive Buffer Register 11 - SRBR11
4177  *
4178  * Shadow Receive Buffer Register 11
4179  *
4180  * Register Layout
4181  *
4182  * Bits | Access | Reset | Description
4183  * :-------|:-------|:------|:----------------------------------
4184  * [7:0] | R | 0x0 | ALT_UART_SRBR11_SRBR11
4185  * [31:8] | R | 0x0 | ALT_UART_SRBR11_RSVD_SRBR11_31TO8
4186  *
4187  */
4188 /*
4189  * Field : srbr11
4190  *
4191  * See srbr0 description
4192  *
4193  * Field Access Macros:
4194  *
4195  */
4196 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR11_SRBR11 register field. */
4197 #define ALT_UART_SRBR11_SRBR11_LSB 0
4198 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR11_SRBR11 register field. */
4199 #define ALT_UART_SRBR11_SRBR11_MSB 7
4200 /* The width in bits of the ALT_UART_SRBR11_SRBR11 register field. */
4201 #define ALT_UART_SRBR11_SRBR11_WIDTH 8
4202 /* The mask used to set the ALT_UART_SRBR11_SRBR11 register field value. */
4203 #define ALT_UART_SRBR11_SRBR11_SET_MSK 0x000000ff
4204 /* The mask used to clear the ALT_UART_SRBR11_SRBR11 register field value. */
4205 #define ALT_UART_SRBR11_SRBR11_CLR_MSK 0xffffff00
4206 /* The reset value of the ALT_UART_SRBR11_SRBR11 register field. */
4207 #define ALT_UART_SRBR11_SRBR11_RESET 0x0
4208 /* Extracts the ALT_UART_SRBR11_SRBR11 field value from a register. */
4209 #define ALT_UART_SRBR11_SRBR11_GET(value) (((value) & 0x000000ff) >> 0)
4210 /* Produces a ALT_UART_SRBR11_SRBR11 register field value suitable for setting the register. */
4211 #define ALT_UART_SRBR11_SRBR11_SET(value) (((value) << 0) & 0x000000ff)
4212 
4213 /*
4214  * Field : RSVD_SRBR11_31to8
4215  *
4216  * Reserved bits [31:8] - Read Only
4217  *
4218  * Field Access Macros:
4219  *
4220  */
4221 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR11_RSVD_SRBR11_31TO8 register field. */
4222 #define ALT_UART_SRBR11_RSVD_SRBR11_31TO8_LSB 8
4223 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR11_RSVD_SRBR11_31TO8 register field. */
4224 #define ALT_UART_SRBR11_RSVD_SRBR11_31TO8_MSB 31
4225 /* The width in bits of the ALT_UART_SRBR11_RSVD_SRBR11_31TO8 register field. */
4226 #define ALT_UART_SRBR11_RSVD_SRBR11_31TO8_WIDTH 24
4227 /* The mask used to set the ALT_UART_SRBR11_RSVD_SRBR11_31TO8 register field value. */
4228 #define ALT_UART_SRBR11_RSVD_SRBR11_31TO8_SET_MSK 0xffffff00
4229 /* The mask used to clear the ALT_UART_SRBR11_RSVD_SRBR11_31TO8 register field value. */
4230 #define ALT_UART_SRBR11_RSVD_SRBR11_31TO8_CLR_MSK 0x000000ff
4231 /* The reset value of the ALT_UART_SRBR11_RSVD_SRBR11_31TO8 register field. */
4232 #define ALT_UART_SRBR11_RSVD_SRBR11_31TO8_RESET 0x0
4233 /* Extracts the ALT_UART_SRBR11_RSVD_SRBR11_31TO8 field value from a register. */
4234 #define ALT_UART_SRBR11_RSVD_SRBR11_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4235 /* Produces a ALT_UART_SRBR11_RSVD_SRBR11_31TO8 register field value suitable for setting the register. */
4236 #define ALT_UART_SRBR11_RSVD_SRBR11_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4237 
4238 #ifndef __ASSEMBLY__
4239 /*
4240  * WARNING: The C register and register group struct declarations are provided for
4241  * convenience and illustrative purposes. They should, however, be used with
4242  * caution as the C language standard provides no guarantees about the alignment or
4243  * atomicity of device memory accesses. The recommended practice for coding device
4244  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4245  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4246  * alt_write_dword() functions for 64 bit registers.
4247  *
4248  * The struct declaration for register ALT_UART_SRBR11.
4249  */
4250 struct ALT_UART_SRBR11_s
4251 {
4252  const volatile uint32_t srbr11 : 8; /* ALT_UART_SRBR11_SRBR11 */
4253  const volatile uint32_t RSVD_SRBR11_31to8 : 24; /* ALT_UART_SRBR11_RSVD_SRBR11_31TO8 */
4254 };
4255 
4256 /* The typedef declaration for register ALT_UART_SRBR11. */
4257 typedef struct ALT_UART_SRBR11_s ALT_UART_SRBR11_t;
4258 #endif /* __ASSEMBLY__ */
4259 
4260 /* The reset value of the ALT_UART_SRBR11 register. */
4261 #define ALT_UART_SRBR11_RESET 0x00000000
4262 /* The byte offset of the ALT_UART_SRBR11 register from the beginning of the component. */
4263 #define ALT_UART_SRBR11_OFST 0x5c
4264 /* The address of the ALT_UART_SRBR11 register. */
4265 #define ALT_UART_SRBR11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR11_OFST))
4266 
4267 /*
4268  * Register : Shadow Receive Buffer Register 12 - SRBR12
4269  *
4270  * Shadow Receive Buffer Register 12
4271  *
4272  * Register Layout
4273  *
4274  * Bits | Access | Reset | Description
4275  * :-------|:-------|:------|:----------------------------------
4276  * [7:0] | R | 0x0 | ALT_UART_SRBR12_SRBR12
4277  * [31:8] | R | 0x0 | ALT_UART_SRBR12_RSVD_SRBR12_31TO8
4278  *
4279  */
4280 /*
4281  * Field : srbr12
4282  *
4283  * See srbr0 description
4284  *
4285  * Field Access Macros:
4286  *
4287  */
4288 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR12_SRBR12 register field. */
4289 #define ALT_UART_SRBR12_SRBR12_LSB 0
4290 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR12_SRBR12 register field. */
4291 #define ALT_UART_SRBR12_SRBR12_MSB 7
4292 /* The width in bits of the ALT_UART_SRBR12_SRBR12 register field. */
4293 #define ALT_UART_SRBR12_SRBR12_WIDTH 8
4294 /* The mask used to set the ALT_UART_SRBR12_SRBR12 register field value. */
4295 #define ALT_UART_SRBR12_SRBR12_SET_MSK 0x000000ff
4296 /* The mask used to clear the ALT_UART_SRBR12_SRBR12 register field value. */
4297 #define ALT_UART_SRBR12_SRBR12_CLR_MSK 0xffffff00
4298 /* The reset value of the ALT_UART_SRBR12_SRBR12 register field. */
4299 #define ALT_UART_SRBR12_SRBR12_RESET 0x0
4300 /* Extracts the ALT_UART_SRBR12_SRBR12 field value from a register. */
4301 #define ALT_UART_SRBR12_SRBR12_GET(value) (((value) & 0x000000ff) >> 0)
4302 /* Produces a ALT_UART_SRBR12_SRBR12 register field value suitable for setting the register. */
4303 #define ALT_UART_SRBR12_SRBR12_SET(value) (((value) << 0) & 0x000000ff)
4304 
4305 /*
4306  * Field : RSVD_SRBR12_31to8
4307  *
4308  * Reserved bits [31:8] - Read Only
4309  *
4310  * Field Access Macros:
4311  *
4312  */
4313 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR12_RSVD_SRBR12_31TO8 register field. */
4314 #define ALT_UART_SRBR12_RSVD_SRBR12_31TO8_LSB 8
4315 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR12_RSVD_SRBR12_31TO8 register field. */
4316 #define ALT_UART_SRBR12_RSVD_SRBR12_31TO8_MSB 31
4317 /* The width in bits of the ALT_UART_SRBR12_RSVD_SRBR12_31TO8 register field. */
4318 #define ALT_UART_SRBR12_RSVD_SRBR12_31TO8_WIDTH 24
4319 /* The mask used to set the ALT_UART_SRBR12_RSVD_SRBR12_31TO8 register field value. */
4320 #define ALT_UART_SRBR12_RSVD_SRBR12_31TO8_SET_MSK 0xffffff00
4321 /* The mask used to clear the ALT_UART_SRBR12_RSVD_SRBR12_31TO8 register field value. */
4322 #define ALT_UART_SRBR12_RSVD_SRBR12_31TO8_CLR_MSK 0x000000ff
4323 /* The reset value of the ALT_UART_SRBR12_RSVD_SRBR12_31TO8 register field. */
4324 #define ALT_UART_SRBR12_RSVD_SRBR12_31TO8_RESET 0x0
4325 /* Extracts the ALT_UART_SRBR12_RSVD_SRBR12_31TO8 field value from a register. */
4326 #define ALT_UART_SRBR12_RSVD_SRBR12_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4327 /* Produces a ALT_UART_SRBR12_RSVD_SRBR12_31TO8 register field value suitable for setting the register. */
4328 #define ALT_UART_SRBR12_RSVD_SRBR12_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4329 
4330 #ifndef __ASSEMBLY__
4331 /*
4332  * WARNING: The C register and register group struct declarations are provided for
4333  * convenience and illustrative purposes. They should, however, be used with
4334  * caution as the C language standard provides no guarantees about the alignment or
4335  * atomicity of device memory accesses. The recommended practice for coding device
4336  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4337  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4338  * alt_write_dword() functions for 64 bit registers.
4339  *
4340  * The struct declaration for register ALT_UART_SRBR12.
4341  */
4342 struct ALT_UART_SRBR12_s
4343 {
4344  const volatile uint32_t srbr12 : 8; /* ALT_UART_SRBR12_SRBR12 */
4345  const volatile uint32_t RSVD_SRBR12_31to8 : 24; /* ALT_UART_SRBR12_RSVD_SRBR12_31TO8 */
4346 };
4347 
4348 /* The typedef declaration for register ALT_UART_SRBR12. */
4349 typedef struct ALT_UART_SRBR12_s ALT_UART_SRBR12_t;
4350 #endif /* __ASSEMBLY__ */
4351 
4352 /* The reset value of the ALT_UART_SRBR12 register. */
4353 #define ALT_UART_SRBR12_RESET 0x00000000
4354 /* The byte offset of the ALT_UART_SRBR12 register from the beginning of the component. */
4355 #define ALT_UART_SRBR12_OFST 0x60
4356 /* The address of the ALT_UART_SRBR12 register. */
4357 #define ALT_UART_SRBR12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR12_OFST))
4358 
4359 /*
4360  * Register : Shadow Receive Buffer Register 13 - SRBR13
4361  *
4362  * Shadow Receive Buffer Register 13
4363  *
4364  * Register Layout
4365  *
4366  * Bits | Access | Reset | Description
4367  * :-------|:-------|:------|:----------------------------------
4368  * [7:0] | R | 0x0 | ALT_UART_SRBR13_SRBR13
4369  * [31:8] | R | 0x0 | ALT_UART_SRBR13_RSVD_SRBR13_31TO8
4370  *
4371  */
4372 /*
4373  * Field : srbr13
4374  *
4375  * See srbr0 description
4376  *
4377  * Field Access Macros:
4378  *
4379  */
4380 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR13_SRBR13 register field. */
4381 #define ALT_UART_SRBR13_SRBR13_LSB 0
4382 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR13_SRBR13 register field. */
4383 #define ALT_UART_SRBR13_SRBR13_MSB 7
4384 /* The width in bits of the ALT_UART_SRBR13_SRBR13 register field. */
4385 #define ALT_UART_SRBR13_SRBR13_WIDTH 8
4386 /* The mask used to set the ALT_UART_SRBR13_SRBR13 register field value. */
4387 #define ALT_UART_SRBR13_SRBR13_SET_MSK 0x000000ff
4388 /* The mask used to clear the ALT_UART_SRBR13_SRBR13 register field value. */
4389 #define ALT_UART_SRBR13_SRBR13_CLR_MSK 0xffffff00
4390 /* The reset value of the ALT_UART_SRBR13_SRBR13 register field. */
4391 #define ALT_UART_SRBR13_SRBR13_RESET 0x0
4392 /* Extracts the ALT_UART_SRBR13_SRBR13 field value from a register. */
4393 #define ALT_UART_SRBR13_SRBR13_GET(value) (((value) & 0x000000ff) >> 0)
4394 /* Produces a ALT_UART_SRBR13_SRBR13 register field value suitable for setting the register. */
4395 #define ALT_UART_SRBR13_SRBR13_SET(value) (((value) << 0) & 0x000000ff)
4396 
4397 /*
4398  * Field : RSVD_SRBR13_31to8
4399  *
4400  * Reserved bits [31:8] - Read Only
4401  *
4402  * Field Access Macros:
4403  *
4404  */
4405 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR13_RSVD_SRBR13_31TO8 register field. */
4406 #define ALT_UART_SRBR13_RSVD_SRBR13_31TO8_LSB 8
4407 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR13_RSVD_SRBR13_31TO8 register field. */
4408 #define ALT_UART_SRBR13_RSVD_SRBR13_31TO8_MSB 31
4409 /* The width in bits of the ALT_UART_SRBR13_RSVD_SRBR13_31TO8 register field. */
4410 #define ALT_UART_SRBR13_RSVD_SRBR13_31TO8_WIDTH 24
4411 /* The mask used to set the ALT_UART_SRBR13_RSVD_SRBR13_31TO8 register field value. */
4412 #define ALT_UART_SRBR13_RSVD_SRBR13_31TO8_SET_MSK 0xffffff00
4413 /* The mask used to clear the ALT_UART_SRBR13_RSVD_SRBR13_31TO8 register field value. */
4414 #define ALT_UART_SRBR13_RSVD_SRBR13_31TO8_CLR_MSK 0x000000ff
4415 /* The reset value of the ALT_UART_SRBR13_RSVD_SRBR13_31TO8 register field. */
4416 #define ALT_UART_SRBR13_RSVD_SRBR13_31TO8_RESET 0x0
4417 /* Extracts the ALT_UART_SRBR13_RSVD_SRBR13_31TO8 field value from a register. */
4418 #define ALT_UART_SRBR13_RSVD_SRBR13_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4419 /* Produces a ALT_UART_SRBR13_RSVD_SRBR13_31TO8 register field value suitable for setting the register. */
4420 #define ALT_UART_SRBR13_RSVD_SRBR13_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4421 
4422 #ifndef __ASSEMBLY__
4423 /*
4424  * WARNING: The C register and register group struct declarations are provided for
4425  * convenience and illustrative purposes. They should, however, be used with
4426  * caution as the C language standard provides no guarantees about the alignment or
4427  * atomicity of device memory accesses. The recommended practice for coding device
4428  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4429  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4430  * alt_write_dword() functions for 64 bit registers.
4431  *
4432  * The struct declaration for register ALT_UART_SRBR13.
4433  */
4434 struct ALT_UART_SRBR13_s
4435 {
4436  const volatile uint32_t srbr13 : 8; /* ALT_UART_SRBR13_SRBR13 */
4437  const volatile uint32_t RSVD_SRBR13_31to8 : 24; /* ALT_UART_SRBR13_RSVD_SRBR13_31TO8 */
4438 };
4439 
4440 /* The typedef declaration for register ALT_UART_SRBR13. */
4441 typedef struct ALT_UART_SRBR13_s ALT_UART_SRBR13_t;
4442 #endif /* __ASSEMBLY__ */
4443 
4444 /* The reset value of the ALT_UART_SRBR13 register. */
4445 #define ALT_UART_SRBR13_RESET 0x00000000
4446 /* The byte offset of the ALT_UART_SRBR13 register from the beginning of the component. */
4447 #define ALT_UART_SRBR13_OFST 0x64
4448 /* The address of the ALT_UART_SRBR13 register. */
4449 #define ALT_UART_SRBR13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR13_OFST))
4450 
4451 /*
4452  * Register : Shadow Receive Buffer Register 14 - SRBR14
4453  *
4454  * Shadow Receive Buffer Register 14
4455  *
4456  * Register Layout
4457  *
4458  * Bits | Access | Reset | Description
4459  * :-------|:-------|:------|:----------------------------------
4460  * [7:0] | R | 0x0 | ALT_UART_SRBR14_SRBR14
4461  * [31:8] | R | 0x0 | ALT_UART_SRBR14_RSVD_SRBR14_31TO8
4462  *
4463  */
4464 /*
4465  * Field : srbr14
4466  *
4467  * See srbr0 description
4468  *
4469  * Field Access Macros:
4470  *
4471  */
4472 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR14_SRBR14 register field. */
4473 #define ALT_UART_SRBR14_SRBR14_LSB 0
4474 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR14_SRBR14 register field. */
4475 #define ALT_UART_SRBR14_SRBR14_MSB 7
4476 /* The width in bits of the ALT_UART_SRBR14_SRBR14 register field. */
4477 #define ALT_UART_SRBR14_SRBR14_WIDTH 8
4478 /* The mask used to set the ALT_UART_SRBR14_SRBR14 register field value. */
4479 #define ALT_UART_SRBR14_SRBR14_SET_MSK 0x000000ff
4480 /* The mask used to clear the ALT_UART_SRBR14_SRBR14 register field value. */
4481 #define ALT_UART_SRBR14_SRBR14_CLR_MSK 0xffffff00
4482 /* The reset value of the ALT_UART_SRBR14_SRBR14 register field. */
4483 #define ALT_UART_SRBR14_SRBR14_RESET 0x0
4484 /* Extracts the ALT_UART_SRBR14_SRBR14 field value from a register. */
4485 #define ALT_UART_SRBR14_SRBR14_GET(value) (((value) & 0x000000ff) >> 0)
4486 /* Produces a ALT_UART_SRBR14_SRBR14 register field value suitable for setting the register. */
4487 #define ALT_UART_SRBR14_SRBR14_SET(value) (((value) << 0) & 0x000000ff)
4488 
4489 /*
4490  * Field : RSVD_SRBR14_31to8
4491  *
4492  * Reserved bits [31:8] - Read Only
4493  *
4494  * Field Access Macros:
4495  *
4496  */
4497 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR14_RSVD_SRBR14_31TO8 register field. */
4498 #define ALT_UART_SRBR14_RSVD_SRBR14_31TO8_LSB 8
4499 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR14_RSVD_SRBR14_31TO8 register field. */
4500 #define ALT_UART_SRBR14_RSVD_SRBR14_31TO8_MSB 31
4501 /* The width in bits of the ALT_UART_SRBR14_RSVD_SRBR14_31TO8 register field. */
4502 #define ALT_UART_SRBR14_RSVD_SRBR14_31TO8_WIDTH 24
4503 /* The mask used to set the ALT_UART_SRBR14_RSVD_SRBR14_31TO8 register field value. */
4504 #define ALT_UART_SRBR14_RSVD_SRBR14_31TO8_SET_MSK 0xffffff00
4505 /* The mask used to clear the ALT_UART_SRBR14_RSVD_SRBR14_31TO8 register field value. */
4506 #define ALT_UART_SRBR14_RSVD_SRBR14_31TO8_CLR_MSK 0x000000ff
4507 /* The reset value of the ALT_UART_SRBR14_RSVD_SRBR14_31TO8 register field. */
4508 #define ALT_UART_SRBR14_RSVD_SRBR14_31TO8_RESET 0x0
4509 /* Extracts the ALT_UART_SRBR14_RSVD_SRBR14_31TO8 field value from a register. */
4510 #define ALT_UART_SRBR14_RSVD_SRBR14_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4511 /* Produces a ALT_UART_SRBR14_RSVD_SRBR14_31TO8 register field value suitable for setting the register. */
4512 #define ALT_UART_SRBR14_RSVD_SRBR14_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4513 
4514 #ifndef __ASSEMBLY__
4515 /*
4516  * WARNING: The C register and register group struct declarations are provided for
4517  * convenience and illustrative purposes. They should, however, be used with
4518  * caution as the C language standard provides no guarantees about the alignment or
4519  * atomicity of device memory accesses. The recommended practice for coding device
4520  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4521  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4522  * alt_write_dword() functions for 64 bit registers.
4523  *
4524  * The struct declaration for register ALT_UART_SRBR14.
4525  */
4526 struct ALT_UART_SRBR14_s
4527 {
4528  const volatile uint32_t srbr14 : 8; /* ALT_UART_SRBR14_SRBR14 */
4529  const volatile uint32_t RSVD_SRBR14_31to8 : 24; /* ALT_UART_SRBR14_RSVD_SRBR14_31TO8 */
4530 };
4531 
4532 /* The typedef declaration for register ALT_UART_SRBR14. */
4533 typedef struct ALT_UART_SRBR14_s ALT_UART_SRBR14_t;
4534 #endif /* __ASSEMBLY__ */
4535 
4536 /* The reset value of the ALT_UART_SRBR14 register. */
4537 #define ALT_UART_SRBR14_RESET 0x00000000
4538 /* The byte offset of the ALT_UART_SRBR14 register from the beginning of the component. */
4539 #define ALT_UART_SRBR14_OFST 0x68
4540 /* The address of the ALT_UART_SRBR14 register. */
4541 #define ALT_UART_SRBR14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR14_OFST))
4542 
4543 /*
4544  * Register : Shadow Receive Buffer Register 15 - SRBR15
4545  *
4546  * Shadow Receive Buffer Register 15
4547  *
4548  * Register Layout
4549  *
4550  * Bits | Access | Reset | Description
4551  * :-------|:-------|:------|:----------------------------------
4552  * [7:0] | R | 0x0 | ALT_UART_SRBR15_SRBR15
4553  * [31:8] | R | 0x0 | ALT_UART_SRBR15_RSVD_SRBR15_31TO8
4554  *
4555  */
4556 /*
4557  * Field : srbr15
4558  *
4559  * See srbr0 description
4560  *
4561  * Field Access Macros:
4562  *
4563  */
4564 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR15_SRBR15 register field. */
4565 #define ALT_UART_SRBR15_SRBR15_LSB 0
4566 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR15_SRBR15 register field. */
4567 #define ALT_UART_SRBR15_SRBR15_MSB 7
4568 /* The width in bits of the ALT_UART_SRBR15_SRBR15 register field. */
4569 #define ALT_UART_SRBR15_SRBR15_WIDTH 8
4570 /* The mask used to set the ALT_UART_SRBR15_SRBR15 register field value. */
4571 #define ALT_UART_SRBR15_SRBR15_SET_MSK 0x000000ff
4572 /* The mask used to clear the ALT_UART_SRBR15_SRBR15 register field value. */
4573 #define ALT_UART_SRBR15_SRBR15_CLR_MSK 0xffffff00
4574 /* The reset value of the ALT_UART_SRBR15_SRBR15 register field. */
4575 #define ALT_UART_SRBR15_SRBR15_RESET 0x0
4576 /* Extracts the ALT_UART_SRBR15_SRBR15 field value from a register. */
4577 #define ALT_UART_SRBR15_SRBR15_GET(value) (((value) & 0x000000ff) >> 0)
4578 /* Produces a ALT_UART_SRBR15_SRBR15 register field value suitable for setting the register. */
4579 #define ALT_UART_SRBR15_SRBR15_SET(value) (((value) << 0) & 0x000000ff)
4580 
4581 /*
4582  * Field : RSVD_SRBR15_31to8
4583  *
4584  * Reserved bits [31:8] - Read Only
4585  *
4586  * Field Access Macros:
4587  *
4588  */
4589 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR15_RSVD_SRBR15_31TO8 register field. */
4590 #define ALT_UART_SRBR15_RSVD_SRBR15_31TO8_LSB 8
4591 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR15_RSVD_SRBR15_31TO8 register field. */
4592 #define ALT_UART_SRBR15_RSVD_SRBR15_31TO8_MSB 31
4593 /* The width in bits of the ALT_UART_SRBR15_RSVD_SRBR15_31TO8 register field. */
4594 #define ALT_UART_SRBR15_RSVD_SRBR15_31TO8_WIDTH 24
4595 /* The mask used to set the ALT_UART_SRBR15_RSVD_SRBR15_31TO8 register field value. */
4596 #define ALT_UART_SRBR15_RSVD_SRBR15_31TO8_SET_MSK 0xffffff00
4597 /* The mask used to clear the ALT_UART_SRBR15_RSVD_SRBR15_31TO8 register field value. */
4598 #define ALT_UART_SRBR15_RSVD_SRBR15_31TO8_CLR_MSK 0x000000ff
4599 /* The reset value of the ALT_UART_SRBR15_RSVD_SRBR15_31TO8 register field. */
4600 #define ALT_UART_SRBR15_RSVD_SRBR15_31TO8_RESET 0x0
4601 /* Extracts the ALT_UART_SRBR15_RSVD_SRBR15_31TO8 field value from a register. */
4602 #define ALT_UART_SRBR15_RSVD_SRBR15_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4603 /* Produces a ALT_UART_SRBR15_RSVD_SRBR15_31TO8 register field value suitable for setting the register. */
4604 #define ALT_UART_SRBR15_RSVD_SRBR15_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4605 
4606 #ifndef __ASSEMBLY__
4607 /*
4608  * WARNING: The C register and register group struct declarations are provided for
4609  * convenience and illustrative purposes. They should, however, be used with
4610  * caution as the C language standard provides no guarantees about the alignment or
4611  * atomicity of device memory accesses. The recommended practice for coding device
4612  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4613  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4614  * alt_write_dword() functions for 64 bit registers.
4615  *
4616  * The struct declaration for register ALT_UART_SRBR15.
4617  */
4618 struct ALT_UART_SRBR15_s
4619 {
4620  const volatile uint32_t srbr15 : 8; /* ALT_UART_SRBR15_SRBR15 */
4621  const volatile uint32_t RSVD_SRBR15_31to8 : 24; /* ALT_UART_SRBR15_RSVD_SRBR15_31TO8 */
4622 };
4623 
4624 /* The typedef declaration for register ALT_UART_SRBR15. */
4625 typedef struct ALT_UART_SRBR15_s ALT_UART_SRBR15_t;
4626 #endif /* __ASSEMBLY__ */
4627 
4628 /* The reset value of the ALT_UART_SRBR15 register. */
4629 #define ALT_UART_SRBR15_RESET 0x00000000
4630 /* The byte offset of the ALT_UART_SRBR15 register from the beginning of the component. */
4631 #define ALT_UART_SRBR15_OFST 0x6c
4632 /* The address of the ALT_UART_SRBR15 register. */
4633 #define ALT_UART_SRBR15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR15_OFST))
4634 
4635 /*
4636  * Register : FIFO Access Register - FAR
4637  *
4638  * FIFO Access Register
4639  *
4640  * Register Layout
4641  *
4642  * Bits | Access | Reset | Description
4643  * :-------|:-------|:------|:----------------------------
4644  * [0] | RW | 0x0 | ALT_UART_FAR_FAR
4645  * [31:1] | R | 0x0 | ALT_UART_FAR_RSVD_FAR_31TO1
4646  *
4647  */
4648 /*
4649  * Field : far
4650  *
4651  * Writes will have no effect when FIFO_ACCESS == No, always readable. This
4652  * register
4653  *
4654  * is use to enable a FIFO access mode for testing, so that the receive FIFO can be
4655  *
4656  * written by the master and the transmit FIFO can be read by the master when
4657  * FIFO's
4658  *
4659  * are implemented and enabled. When FIFO's are not implemented or not enabled it
4660  *
4661  * allows the RBR to be written by the master and the THR to be read by the master.
4662  *
4663  * 0 = FIFO access mode disabled
4664  *
4665  * 1 = FIFO access mode enabled
4666  *
4667  * Note, that when the FIFO access mode is enabled/disabled, the control portion of
4668  *
4669  * the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty.
4670  *
4671  * Field Enumeration Values:
4672  *
4673  * Enum | Value | Description
4674  * :----------------------------|:------|:--------------------------
4675  * ALT_UART_FAR_FAR_E_DISABLED | 0x0 | FIFO access mode disabled
4676  * ALT_UART_FAR_FAR_E_ENABLED | 0x1 | FIFO access mode enabled
4677  *
4678  * Field Access Macros:
4679  *
4680  */
4681 /*
4682  * Enumerated value for register field ALT_UART_FAR_FAR
4683  *
4684  * FIFO access mode disabled
4685  */
4686 #define ALT_UART_FAR_FAR_E_DISABLED 0x0
4687 /*
4688  * Enumerated value for register field ALT_UART_FAR_FAR
4689  *
4690  * FIFO access mode enabled
4691  */
4692 #define ALT_UART_FAR_FAR_E_ENABLED 0x1
4693 
4694 /* The Least Significant Bit (LSB) position of the ALT_UART_FAR_FAR register field. */
4695 #define ALT_UART_FAR_FAR_LSB 0
4696 /* The Most Significant Bit (MSB) position of the ALT_UART_FAR_FAR register field. */
4697 #define ALT_UART_FAR_FAR_MSB 0
4698 /* The width in bits of the ALT_UART_FAR_FAR register field. */
4699 #define ALT_UART_FAR_FAR_WIDTH 1
4700 /* The mask used to set the ALT_UART_FAR_FAR register field value. */
4701 #define ALT_UART_FAR_FAR_SET_MSK 0x00000001
4702 /* The mask used to clear the ALT_UART_FAR_FAR register field value. */
4703 #define ALT_UART_FAR_FAR_CLR_MSK 0xfffffffe
4704 /* The reset value of the ALT_UART_FAR_FAR register field. */
4705 #define ALT_UART_FAR_FAR_RESET 0x0
4706 /* Extracts the ALT_UART_FAR_FAR field value from a register. */
4707 #define ALT_UART_FAR_FAR_GET(value) (((value) & 0x00000001) >> 0)
4708 /* Produces a ALT_UART_FAR_FAR register field value suitable for setting the register. */
4709 #define ALT_UART_FAR_FAR_SET(value) (((value) << 0) & 0x00000001)
4710 
4711 /*
4712  * Field : RSVD_FAR_31to1
4713  *
4714  * Reserved bits [31:1] - Read Only
4715  *
4716  * Field Access Macros:
4717  *
4718  */
4719 /* The Least Significant Bit (LSB) position of the ALT_UART_FAR_RSVD_FAR_31TO1 register field. */
4720 #define ALT_UART_FAR_RSVD_FAR_31TO1_LSB 1
4721 /* The Most Significant Bit (MSB) position of the ALT_UART_FAR_RSVD_FAR_31TO1 register field. */
4722 #define ALT_UART_FAR_RSVD_FAR_31TO1_MSB 31
4723 /* The width in bits of the ALT_UART_FAR_RSVD_FAR_31TO1 register field. */
4724 #define ALT_UART_FAR_RSVD_FAR_31TO1_WIDTH 31
4725 /* The mask used to set the ALT_UART_FAR_RSVD_FAR_31TO1 register field value. */
4726 #define ALT_UART_FAR_RSVD_FAR_31TO1_SET_MSK 0xfffffffe
4727 /* The mask used to clear the ALT_UART_FAR_RSVD_FAR_31TO1 register field value. */
4728 #define ALT_UART_FAR_RSVD_FAR_31TO1_CLR_MSK 0x00000001
4729 /* The reset value of the ALT_UART_FAR_RSVD_FAR_31TO1 register field. */
4730 #define ALT_UART_FAR_RSVD_FAR_31TO1_RESET 0x0
4731 /* Extracts the ALT_UART_FAR_RSVD_FAR_31TO1 field value from a register. */
4732 #define ALT_UART_FAR_RSVD_FAR_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
4733 /* Produces a ALT_UART_FAR_RSVD_FAR_31TO1 register field value suitable for setting the register. */
4734 #define ALT_UART_FAR_RSVD_FAR_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
4735 
4736 #ifndef __ASSEMBLY__
4737 /*
4738  * WARNING: The C register and register group struct declarations are provided for
4739  * convenience and illustrative purposes. They should, however, be used with
4740  * caution as the C language standard provides no guarantees about the alignment or
4741  * atomicity of device memory accesses. The recommended practice for coding device
4742  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4743  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4744  * alt_write_dword() functions for 64 bit registers.
4745  *
4746  * The struct declaration for register ALT_UART_FAR.
4747  */
4748 struct ALT_UART_FAR_s
4749 {
4750  volatile uint32_t far : 1; /* ALT_UART_FAR_FAR */
4751  const volatile uint32_t RSVD_FAR_31to1 : 31; /* ALT_UART_FAR_RSVD_FAR_31TO1 */
4752 };
4753 
4754 /* The typedef declaration for register ALT_UART_FAR. */
4755 typedef struct ALT_UART_FAR_s ALT_UART_FAR_t;
4756 #endif /* __ASSEMBLY__ */
4757 
4758 /* The reset value of the ALT_UART_FAR register. */
4759 #define ALT_UART_FAR_RESET 0x00000000
4760 /* The byte offset of the ALT_UART_FAR register from the beginning of the component. */
4761 #define ALT_UART_FAR_OFST 0x70
4762 /* The address of the ALT_UART_FAR register. */
4763 #define ALT_UART_FAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FAR_OFST))
4764 
4765 /*
4766  * Register : Transmit FIFO Read - TFR
4767  *
4768  * Transmit FIFO Read
4769  *
4770  * Register Layout
4771  *
4772  * Bits | Access | Reset | Description
4773  * :-------|:-------|:------|:----------------------------
4774  * [7:0] | R | 0x0 | ALT_UART_TFR_TFR
4775  * [31:8] | R | 0x0 | ALT_UART_TFR_RSVD_TFR_31TO8
4776  *
4777  */
4778 /*
4779  * Field : tfr
4780  *
4781  * Transmit FIFO Read.
4782  *
4783  * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
4784  * one).
4785  *
4786  * When FIFO's are implemented and enabled, reading this register gives the data at
4787  * the
4788  *
4789  * top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives
4790  * the
4791  *
4792  * next data value that is currently at the top of the FIFO.
4793  *
4794  * When FIFO's are not implemented or not enabled, reading this register gives the
4795  * data
4796  *
4797  * in the THR.
4798  *
4799  * Field Access Macros:
4800  *
4801  */
4802 /* The Least Significant Bit (LSB) position of the ALT_UART_TFR_TFR register field. */
4803 #define ALT_UART_TFR_TFR_LSB 0
4804 /* The Most Significant Bit (MSB) position of the ALT_UART_TFR_TFR register field. */
4805 #define ALT_UART_TFR_TFR_MSB 7
4806 /* The width in bits of the ALT_UART_TFR_TFR register field. */
4807 #define ALT_UART_TFR_TFR_WIDTH 8
4808 /* The mask used to set the ALT_UART_TFR_TFR register field value. */
4809 #define ALT_UART_TFR_TFR_SET_MSK 0x000000ff
4810 /* The mask used to clear the ALT_UART_TFR_TFR register field value. */
4811 #define ALT_UART_TFR_TFR_CLR_MSK 0xffffff00
4812 /* The reset value of the ALT_UART_TFR_TFR register field. */
4813 #define ALT_UART_TFR_TFR_RESET 0x0
4814 /* Extracts the ALT_UART_TFR_TFR field value from a register. */
4815 #define ALT_UART_TFR_TFR_GET(value) (((value) & 0x000000ff) >> 0)
4816 /* Produces a ALT_UART_TFR_TFR register field value suitable for setting the register. */
4817 #define ALT_UART_TFR_TFR_SET(value) (((value) << 0) & 0x000000ff)
4818 
4819 /*
4820  * Field : RSVD_TFR_31to8
4821  *
4822  * Reserved bits [31:8] - Read Only
4823  *
4824  * Field Access Macros:
4825  *
4826  */
4827 /* The Least Significant Bit (LSB) position of the ALT_UART_TFR_RSVD_TFR_31TO8 register field. */
4828 #define ALT_UART_TFR_RSVD_TFR_31TO8_LSB 8
4829 /* The Most Significant Bit (MSB) position of the ALT_UART_TFR_RSVD_TFR_31TO8 register field. */
4830 #define ALT_UART_TFR_RSVD_TFR_31TO8_MSB 31
4831 /* The width in bits of the ALT_UART_TFR_RSVD_TFR_31TO8 register field. */
4832 #define ALT_UART_TFR_RSVD_TFR_31TO8_WIDTH 24
4833 /* The mask used to set the ALT_UART_TFR_RSVD_TFR_31TO8 register field value. */
4834 #define ALT_UART_TFR_RSVD_TFR_31TO8_SET_MSK 0xffffff00
4835 /* The mask used to clear the ALT_UART_TFR_RSVD_TFR_31TO8 register field value. */
4836 #define ALT_UART_TFR_RSVD_TFR_31TO8_CLR_MSK 0x000000ff
4837 /* The reset value of the ALT_UART_TFR_RSVD_TFR_31TO8 register field. */
4838 #define ALT_UART_TFR_RSVD_TFR_31TO8_RESET 0x0
4839 /* Extracts the ALT_UART_TFR_RSVD_TFR_31TO8 field value from a register. */
4840 #define ALT_UART_TFR_RSVD_TFR_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4841 /* Produces a ALT_UART_TFR_RSVD_TFR_31TO8 register field value suitable for setting the register. */
4842 #define ALT_UART_TFR_RSVD_TFR_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4843 
4844 #ifndef __ASSEMBLY__
4845 /*
4846  * WARNING: The C register and register group struct declarations are provided for
4847  * convenience and illustrative purposes. They should, however, be used with
4848  * caution as the C language standard provides no guarantees about the alignment or
4849  * atomicity of device memory accesses. The recommended practice for coding device
4850  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4851  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4852  * alt_write_dword() functions for 64 bit registers.
4853  *
4854  * The struct declaration for register ALT_UART_TFR.
4855  */
4856 struct ALT_UART_TFR_s
4857 {
4858  const volatile uint32_t tfr : 8; /* ALT_UART_TFR_TFR */
4859  const volatile uint32_t RSVD_TFR_31to8 : 24; /* ALT_UART_TFR_RSVD_TFR_31TO8 */
4860 };
4861 
4862 /* The typedef declaration for register ALT_UART_TFR. */
4863 typedef struct ALT_UART_TFR_s ALT_UART_TFR_t;
4864 #endif /* __ASSEMBLY__ */
4865 
4866 /* The reset value of the ALT_UART_TFR register. */
4867 #define ALT_UART_TFR_RESET 0x00000000
4868 /* The byte offset of the ALT_UART_TFR register from the beginning of the component. */
4869 #define ALT_UART_TFR_OFST 0x74
4870 /* The address of the ALT_UART_TFR register. */
4871 #define ALT_UART_TFR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFR_OFST))
4872 
4873 /*
4874  * Register : Receive FIFO Write - RFW
4875  *
4876  * Receive FIFO Write
4877  *
4878  * Register Layout
4879  *
4880  * Bits | Access | Reset | Description
4881  * :--------|:-------|:------|:-----------------------------
4882  * [7:0] | W | 0x0 | ALT_UART_RFW_RFWD
4883  * [8] | W | 0x0 | ALT_UART_RFW_RFPE
4884  * [9] | W | 0x0 | ALT_UART_RFW_RFFE
4885  * [31:10] | R | 0x0 | ALT_UART_RFW_RSVD_RFW_31TO10
4886  *
4887  */
4888 /*
4889  * Field : RFWD
4890  *
4891  * Receive FIFO Write Data.
4892  *
4893  * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
4894  * one).
4895  *
4896  * When FIFO's are implemented and enabled, the data that is written to the RFWD is
4897  * pushed
4898  *
4899  * into the receive FIFO. Each consecutive write pushes the new data to the next
4900  * write
4901  *
4902  * location in the receive FIFO.
4903  *
4904  * When FIFO's are not implemented or not enabled, the data that is written to the
4905  * RFWD
4906  *
4907  * is pushed into the RBR.
4908  *
4909  * Field Access Macros:
4910  *
4911  */
4912 /* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFWD register field. */
4913 #define ALT_UART_RFW_RFWD_LSB 0
4914 /* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFWD register field. */
4915 #define ALT_UART_RFW_RFWD_MSB 7
4916 /* The width in bits of the ALT_UART_RFW_RFWD register field. */
4917 #define ALT_UART_RFW_RFWD_WIDTH 8
4918 /* The mask used to set the ALT_UART_RFW_RFWD register field value. */
4919 #define ALT_UART_RFW_RFWD_SET_MSK 0x000000ff
4920 /* The mask used to clear the ALT_UART_RFW_RFWD register field value. */
4921 #define ALT_UART_RFW_RFWD_CLR_MSK 0xffffff00
4922 /* The reset value of the ALT_UART_RFW_RFWD register field. */
4923 #define ALT_UART_RFW_RFWD_RESET 0x0
4924 /* Extracts the ALT_UART_RFW_RFWD field value from a register. */
4925 #define ALT_UART_RFW_RFWD_GET(value) (((value) & 0x000000ff) >> 0)
4926 /* Produces a ALT_UART_RFW_RFWD register field value suitable for setting the register. */
4927 #define ALT_UART_RFW_RFWD_SET(value) (((value) << 0) & 0x000000ff)
4928 
4929 /*
4930  * Field : RFPE
4931  *
4932  * Receive FIFO Parity Error.
4933  *
4934  * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
4935  * one).
4936  *
4937  * When FIFO's are implemented and enabled, this bit is used to write parity error
4938  *
4939  * detection information to the receive FIFO.
4940  *
4941  * When FIFO's are not implemented or not enabled, this bit is used to write parity
4942  *
4943  * error detection information to the RBR.
4944  *
4945  * Field Enumeration Values:
4946  *
4947  * Enum | Value | Description
4948  * :-----------------------------|:------|:----------------------
4949  * ALT_UART_RFW_RFPE_E_DISABLED | 0x0 | Parity error disabled
4950  * ALT_UART_RFW_RFPE_E_ENABLED | 0x1 | Parity error enabled
4951  *
4952  * Field Access Macros:
4953  *
4954  */
4955 /*
4956  * Enumerated value for register field ALT_UART_RFW_RFPE
4957  *
4958  * Parity error disabled
4959  */
4960 #define ALT_UART_RFW_RFPE_E_DISABLED 0x0
4961 /*
4962  * Enumerated value for register field ALT_UART_RFW_RFPE
4963  *
4964  * Parity error enabled
4965  */
4966 #define ALT_UART_RFW_RFPE_E_ENABLED 0x1
4967 
4968 /* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFPE register field. */
4969 #define ALT_UART_RFW_RFPE_LSB 8
4970 /* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFPE register field. */
4971 #define ALT_UART_RFW_RFPE_MSB 8
4972 /* The width in bits of the ALT_UART_RFW_RFPE register field. */
4973 #define ALT_UART_RFW_RFPE_WIDTH 1
4974 /* The mask used to set the ALT_UART_RFW_RFPE register field value. */
4975 #define ALT_UART_RFW_RFPE_SET_MSK 0x00000100
4976 /* The mask used to clear the ALT_UART_RFW_RFPE register field value. */
4977 #define ALT_UART_RFW_RFPE_CLR_MSK 0xfffffeff
4978 /* The reset value of the ALT_UART_RFW_RFPE register field. */
4979 #define ALT_UART_RFW_RFPE_RESET 0x0
4980 /* Extracts the ALT_UART_RFW_RFPE field value from a register. */
4981 #define ALT_UART_RFW_RFPE_GET(value) (((value) & 0x00000100) >> 8)
4982 /* Produces a ALT_UART_RFW_RFPE register field value suitable for setting the register. */
4983 #define ALT_UART_RFW_RFPE_SET(value) (((value) << 8) & 0x00000100)
4984 
4985 /*
4986  * Field : RFFE
4987  *
4988  * Receive FIFO Framing Error.
4989  *
4990  * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
4991  * one).
4992  *
4993  * When FIFO's are implemented and enabled, this bit is used to write framing error
4994  *
4995  * detection information to the receive FIFO.
4996  *
4997  * When FIFO's are not implemented or not enabled, this bit is used to write
4998  * framing
4999  *
5000  * error detection information to the RBR.
5001  *
5002  * Field Enumeration Values:
5003  *
5004  * Enum | Value | Description
5005  * :-----------------------------|:------|:---------------------
5006  * ALT_UART_RFW_RFFE_E_DISABLED | 0x0 | Frame error disabled
5007  * ALT_UART_RFW_RFFE_E_ENABLED | 0x1 | Frame error enabled
5008  *
5009  * Field Access Macros:
5010  *
5011  */
5012 /*
5013  * Enumerated value for register field ALT_UART_RFW_RFFE
5014  *
5015  * Frame error disabled
5016  */
5017 #define ALT_UART_RFW_RFFE_E_DISABLED 0x0
5018 /*
5019  * Enumerated value for register field ALT_UART_RFW_RFFE
5020  *
5021  * Frame error enabled
5022  */
5023 #define ALT_UART_RFW_RFFE_E_ENABLED 0x1
5024 
5025 /* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFFE register field. */
5026 #define ALT_UART_RFW_RFFE_LSB 9
5027 /* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFFE register field. */
5028 #define ALT_UART_RFW_RFFE_MSB 9
5029 /* The width in bits of the ALT_UART_RFW_RFFE register field. */
5030 #define ALT_UART_RFW_RFFE_WIDTH 1
5031 /* The mask used to set the ALT_UART_RFW_RFFE register field value. */
5032 #define ALT_UART_RFW_RFFE_SET_MSK 0x00000200
5033 /* The mask used to clear the ALT_UART_RFW_RFFE register field value. */
5034 #define ALT_UART_RFW_RFFE_CLR_MSK 0xfffffdff
5035 /* The reset value of the ALT_UART_RFW_RFFE register field. */
5036 #define ALT_UART_RFW_RFFE_RESET 0x0
5037 /* Extracts the ALT_UART_RFW_RFFE field value from a register. */
5038 #define ALT_UART_RFW_RFFE_GET(value) (((value) & 0x00000200) >> 9)
5039 /* Produces a ALT_UART_RFW_RFFE register field value suitable for setting the register. */
5040 #define ALT_UART_RFW_RFFE_SET(value) (((value) << 9) & 0x00000200)
5041 
5042 /*
5043  * Field : RSVD_RFW_31to10
5044  *
5045  * Reserved bits [31:10] - Read Only
5046  *
5047  * Field Access Macros:
5048  *
5049  */
5050 /* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RSVD_RFW_31TO10 register field. */
5051 #define ALT_UART_RFW_RSVD_RFW_31TO10_LSB 10
5052 /* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RSVD_RFW_31TO10 register field. */
5053 #define ALT_UART_RFW_RSVD_RFW_31TO10_MSB 31
5054 /* The width in bits of the ALT_UART_RFW_RSVD_RFW_31TO10 register field. */
5055 #define ALT_UART_RFW_RSVD_RFW_31TO10_WIDTH 22
5056 /* The mask used to set the ALT_UART_RFW_RSVD_RFW_31TO10 register field value. */
5057 #define ALT_UART_RFW_RSVD_RFW_31TO10_SET_MSK 0xfffffc00
5058 /* The mask used to clear the ALT_UART_RFW_RSVD_RFW_31TO10 register field value. */
5059 #define ALT_UART_RFW_RSVD_RFW_31TO10_CLR_MSK 0x000003ff
5060 /* The reset value of the ALT_UART_RFW_RSVD_RFW_31TO10 register field. */
5061 #define ALT_UART_RFW_RSVD_RFW_31TO10_RESET 0x0
5062 /* Extracts the ALT_UART_RFW_RSVD_RFW_31TO10 field value from a register. */
5063 #define ALT_UART_RFW_RSVD_RFW_31TO10_GET(value) (((value) & 0xfffffc00) >> 10)
5064 /* Produces a ALT_UART_RFW_RSVD_RFW_31TO10 register field value suitable for setting the register. */
5065 #define ALT_UART_RFW_RSVD_RFW_31TO10_SET(value) (((value) << 10) & 0xfffffc00)
5066 
5067 #ifndef __ASSEMBLY__
5068 /*
5069  * WARNING: The C register and register group struct declarations are provided for
5070  * convenience and illustrative purposes. They should, however, be used with
5071  * caution as the C language standard provides no guarantees about the alignment or
5072  * atomicity of device memory accesses. The recommended practice for coding device
5073  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5074  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5075  * alt_write_dword() functions for 64 bit registers.
5076  *
5077  * The struct declaration for register ALT_UART_RFW.
5078  */
5079 struct ALT_UART_RFW_s
5080 {
5081  volatile uint32_t RFWD : 8; /* ALT_UART_RFW_RFWD */
5082  volatile uint32_t RFPE : 1; /* ALT_UART_RFW_RFPE */
5083  volatile uint32_t RFFE : 1; /* ALT_UART_RFW_RFFE */
5084  const volatile uint32_t RSVD_RFW_31to10 : 22; /* ALT_UART_RFW_RSVD_RFW_31TO10 */
5085 };
5086 
5087 /* The typedef declaration for register ALT_UART_RFW. */
5088 typedef struct ALT_UART_RFW_s ALT_UART_RFW_t;
5089 #endif /* __ASSEMBLY__ */
5090 
5091 /* The reset value of the ALT_UART_RFW register. */
5092 #define ALT_UART_RFW_RESET 0x00000000
5093 /* The byte offset of the ALT_UART_RFW register from the beginning of the component. */
5094 #define ALT_UART_RFW_OFST 0x78
5095 /* The address of the ALT_UART_RFW register. */
5096 #define ALT_UART_RFW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFW_OFST))
5097 
5098 /*
5099  * Register : UART Status register - USR
5100  *
5101  * UART Status register.
5102  *
5103  * Register Layout
5104  *
5105  * Bits | Access | Reset | Description
5106  * :-------|:-------|:------|:----------------------------
5107  * [0] | R | 0x0 | ALT_UART_USR_RSVD_BUSY
5108  * [1] | R | 0x1 | ALT_UART_USR_TFNF
5109  * [2] | R | 0x1 | ALT_UART_USR_TFE
5110  * [3] | R | 0x0 | ALT_UART_USR_RFNE
5111  * [4] | R | 0x0 | ALT_UART_USR_RFF
5112  * [31:5] | R | 0x0 | ALT_UART_USR_RSVD_USR_31TO5
5113  *
5114  */
5115 /*
5116  * Field : RSVD_BUSY
5117  *
5118  * UART Busy.
5119  *
5120  * This bit is only valid when UART_16550_COMPATIBLE == NO. This indicates that a
5121  * serial
5122  *
5123  * transfer is in progress, when cleared indicates that the DW_apb_uart is idle or
5124  * inactive.
5125  *
5126  * 0 - DW_apb_uart is idle or inactive
5127  *
5128  * 1 - DW_apb_uart is busy (actively transferring data)
5129  *
5130  * Note that it is possible for the UART Busy bit to be cleared even though a new
5131  *
5132  * character may have been sent from another device. That is, if the DW_apb_uart
5133  *
5134  * has no data in the THR and RBR and there is no transmission in progress and a
5135  * start
5136  *
5137  * bit of a new character has just reached the DW_apb_uart. This is due to the fact
5138  *
5139  * that a valid start is not seen until the middle of the bit period and this
5140  * duration
5141  *
5142  * is dependent on the baud divisor that has been programmed. If a second system
5143  * clock
5144  *
5145  * has been implemented (CLOCK_MODE == Enabled) the assertion of this bit will also
5146  * be
5147  *
5148  * delayed by several cycles of the slower clock.
5149  *
5150  * Field Enumeration Values:
5151  *
5152  * Enum | Value | Description
5153  * :------------------------------|:------|:-------------------------------------------------
5154  * ALT_UART_USR_RSVD_BUSY_E_IDLE | 0x0 | DW_apb_uart is idle or inactive
5155  * ALT_UART_USR_RSVD_BUSY_E_BUSY | 0x1 | DW_apb_uart is busy (actively transferring data)
5156  *
5157  * Field Access Macros:
5158  *
5159  */
5160 /*
5161  * Enumerated value for register field ALT_UART_USR_RSVD_BUSY
5162  *
5163  * DW_apb_uart is idle or inactive
5164  */
5165 #define ALT_UART_USR_RSVD_BUSY_E_IDLE 0x0
5166 /*
5167  * Enumerated value for register field ALT_UART_USR_RSVD_BUSY
5168  *
5169  * DW_apb_uart is busy (actively transferring data)
5170  */
5171 #define ALT_UART_USR_RSVD_BUSY_E_BUSY 0x1
5172 
5173 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_RSVD_BUSY register field. */
5174 #define ALT_UART_USR_RSVD_BUSY_LSB 0
5175 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_RSVD_BUSY register field. */
5176 #define ALT_UART_USR_RSVD_BUSY_MSB 0
5177 /* The width in bits of the ALT_UART_USR_RSVD_BUSY register field. */
5178 #define ALT_UART_USR_RSVD_BUSY_WIDTH 1
5179 /* The mask used to set the ALT_UART_USR_RSVD_BUSY register field value. */
5180 #define ALT_UART_USR_RSVD_BUSY_SET_MSK 0x00000001
5181 /* The mask used to clear the ALT_UART_USR_RSVD_BUSY register field value. */
5182 #define ALT_UART_USR_RSVD_BUSY_CLR_MSK 0xfffffffe
5183 /* The reset value of the ALT_UART_USR_RSVD_BUSY register field. */
5184 #define ALT_UART_USR_RSVD_BUSY_RESET 0x0
5185 /* Extracts the ALT_UART_USR_RSVD_BUSY field value from a register. */
5186 #define ALT_UART_USR_RSVD_BUSY_GET(value) (((value) & 0x00000001) >> 0)
5187 /* Produces a ALT_UART_USR_RSVD_BUSY register field value suitable for setting the register. */
5188 #define ALT_UART_USR_RSVD_BUSY_SET(value) (((value) << 0) & 0x00000001)
5189 
5190 /*
5191  * Field : TFNF
5192  *
5193  * Transmit FIFO Not Full.
5194  *
5195  * This bit is only valid when FIFO_STAT == YES. This is used to indicate that the
5196  *
5197  * transmit FIFO in not full.
5198  *
5199  * 0 = Transmit FIFO is full
5200  *
5201  * 1 = Transmit FIFO is not full
5202  *
5203  * This bit is cleared when the TX FIFO is full.
5204  *
5205  * Field Enumeration Values:
5206  *
5207  * Enum | Value | Description
5208  * :-----------------------------|:------|:--------------------------
5209  * ALT_UART_USR_TFNF_E_FULL | 0x0 | Transmit FIFO is full
5210  * ALT_UART_USR_TFNF_E_NOT_FULL | 0x1 | Transmit FIFO is not full
5211  *
5212  * Field Access Macros:
5213  *
5214  */
5215 /*
5216  * Enumerated value for register field ALT_UART_USR_TFNF
5217  *
5218  * Transmit FIFO is full
5219  */
5220 #define ALT_UART_USR_TFNF_E_FULL 0x0
5221 /*
5222  * Enumerated value for register field ALT_UART_USR_TFNF
5223  *
5224  * Transmit FIFO is not full
5225  */
5226 #define ALT_UART_USR_TFNF_E_NOT_FULL 0x1
5227 
5228 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFNF register field. */
5229 #define ALT_UART_USR_TFNF_LSB 1
5230 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFNF register field. */
5231 #define ALT_UART_USR_TFNF_MSB 1
5232 /* The width in bits of the ALT_UART_USR_TFNF register field. */
5233 #define ALT_UART_USR_TFNF_WIDTH 1
5234 /* The mask used to set the ALT_UART_USR_TFNF register field value. */
5235 #define ALT_UART_USR_TFNF_SET_MSK 0x00000002
5236 /* The mask used to clear the ALT_UART_USR_TFNF register field value. */
5237 #define ALT_UART_USR_TFNF_CLR_MSK 0xfffffffd
5238 /* The reset value of the ALT_UART_USR_TFNF register field. */
5239 #define ALT_UART_USR_TFNF_RESET 0x1
5240 /* Extracts the ALT_UART_USR_TFNF field value from a register. */
5241 #define ALT_UART_USR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
5242 /* Produces a ALT_UART_USR_TFNF register field value suitable for setting the register. */
5243 #define ALT_UART_USR_TFNF_SET(value) (((value) << 1) & 0x00000002)
5244 
5245 /*
5246  * Field : TFE
5247  *
5248  * Transmit FIFO Empty.
5249  *
5250  * This bit is only valid when FIFO_STAT == YES. This is used to indicate that the
5251  *
5252  * transmit FIFO is completely empty.
5253  *
5254  * 0 = Transmit FIFO is not empty
5255  *
5256  * 1 = Transmit FIFO is empty
5257  *
5258  * This bit is cleared when the TX FIFO is no longer empty.
5259  *
5260  * Field Enumeration Values:
5261  *
5262  * Enum | Value | Description
5263  * :-----------------------------|:------|:---------------------------
5264  * ALT_UART_USR_TFE_E_NOT_EMPTY | 0x0 | Transmit FIFO is not empty
5265  * ALT_UART_USR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty
5266  *
5267  * Field Access Macros:
5268  *
5269  */
5270 /*
5271  * Enumerated value for register field ALT_UART_USR_TFE
5272  *
5273  * Transmit FIFO is not empty
5274  */
5275 #define ALT_UART_USR_TFE_E_NOT_EMPTY 0x0
5276 /*
5277  * Enumerated value for register field ALT_UART_USR_TFE
5278  *
5279  * Transmit FIFO is empty
5280  */
5281 #define ALT_UART_USR_TFE_E_EMPTY 0x1
5282 
5283 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFE register field. */
5284 #define ALT_UART_USR_TFE_LSB 2
5285 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFE register field. */
5286 #define ALT_UART_USR_TFE_MSB 2
5287 /* The width in bits of the ALT_UART_USR_TFE register field. */
5288 #define ALT_UART_USR_TFE_WIDTH 1
5289 /* The mask used to set the ALT_UART_USR_TFE register field value. */
5290 #define ALT_UART_USR_TFE_SET_MSK 0x00000004
5291 /* The mask used to clear the ALT_UART_USR_TFE register field value. */
5292 #define ALT_UART_USR_TFE_CLR_MSK 0xfffffffb
5293 /* The reset value of the ALT_UART_USR_TFE register field. */
5294 #define ALT_UART_USR_TFE_RESET 0x1
5295 /* Extracts the ALT_UART_USR_TFE field value from a register. */
5296 #define ALT_UART_USR_TFE_GET(value) (((value) & 0x00000004) >> 2)
5297 /* Produces a ALT_UART_USR_TFE register field value suitable for setting the register. */
5298 #define ALT_UART_USR_TFE_SET(value) (((value) << 2) & 0x00000004)
5299 
5300 /*
5301  * Field : RFNE
5302  *
5303  * Receive FIFO Not Empty.
5304  *
5305  * This bit is only valid when FIFO_STAT == YES. This is used to indicate that the
5306  *
5307  * receive FIFO contains one or more entries.
5308  *
5309  * 0 = Receive FIFO is empty
5310  *
5311  * 1 = Receive FIFO is not empty
5312  *
5313  * This bit is cleared when the RX FIFO is empty.
5314  *
5315  * Field Enumeration Values:
5316  *
5317  * Enum | Value | Description
5318  * :------------------------------|:------|:--------------------------
5319  * ALT_UART_USR_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty
5320  * ALT_UART_USR_RFNE_E_NOT_EMPTY | 0x1 | Receive FIFO is not empty
5321  *
5322  * Field Access Macros:
5323  *
5324  */
5325 /*
5326  * Enumerated value for register field ALT_UART_USR_RFNE
5327  *
5328  * Receive FIFO is empty
5329  */
5330 #define ALT_UART_USR_RFNE_E_EMPTY 0x0
5331 /*
5332  * Enumerated value for register field ALT_UART_USR_RFNE
5333  *
5334  * Receive FIFO is not empty
5335  */
5336 #define ALT_UART_USR_RFNE_E_NOT_EMPTY 0x1
5337 
5338 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFNE register field. */
5339 #define ALT_UART_USR_RFNE_LSB 3
5340 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFNE register field. */
5341 #define ALT_UART_USR_RFNE_MSB 3
5342 /* The width in bits of the ALT_UART_USR_RFNE register field. */
5343 #define ALT_UART_USR_RFNE_WIDTH 1
5344 /* The mask used to set the ALT_UART_USR_RFNE register field value. */
5345 #define ALT_UART_USR_RFNE_SET_MSK 0x00000008
5346 /* The mask used to clear the ALT_UART_USR_RFNE register field value. */
5347 #define ALT_UART_USR_RFNE_CLR_MSK 0xfffffff7
5348 /* The reset value of the ALT_UART_USR_RFNE register field. */
5349 #define ALT_UART_USR_RFNE_RESET 0x0
5350 /* Extracts the ALT_UART_USR_RFNE field value from a register. */
5351 #define ALT_UART_USR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
5352 /* Produces a ALT_UART_USR_RFNE register field value suitable for setting the register. */
5353 #define ALT_UART_USR_RFNE_SET(value) (((value) << 3) & 0x00000008)
5354 
5355 /*
5356  * Field : RFF
5357  *
5358  * Receive FIFO Full.
5359  *
5360  * This bit is only valid when FIFO_STAT == YES. This is used to indicate that the
5361  *
5362  * receive FIFO is completely full. That is:
5363  *
5364  * 0 = Receive FIFO not full
5365  *
5366  * 1 = Receive FIFO Full
5367  *
5368  * This bit is cleared when the RX FIFO is no longer full.
5369  *
5370  * Field Enumeration Values:
5371  *
5372  * Enum | Value | Description
5373  * :----------------------------|:------|:----------------------
5374  * ALT_UART_USR_RFF_E_NOT_FULL | 0x0 | Receive FIFO not full
5375  * ALT_UART_USR_RFF_E_FULL | 0x1 | Receive FIFO full
5376  *
5377  * Field Access Macros:
5378  *
5379  */
5380 /*
5381  * Enumerated value for register field ALT_UART_USR_RFF
5382  *
5383  * Receive FIFO not full
5384  */
5385 #define ALT_UART_USR_RFF_E_NOT_FULL 0x0
5386 /*
5387  * Enumerated value for register field ALT_UART_USR_RFF
5388  *
5389  * Receive FIFO full
5390  */
5391 #define ALT_UART_USR_RFF_E_FULL 0x1
5392 
5393 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFF register field. */
5394 #define ALT_UART_USR_RFF_LSB 4
5395 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFF register field. */
5396 #define ALT_UART_USR_RFF_MSB 4
5397 /* The width in bits of the ALT_UART_USR_RFF register field. */
5398 #define ALT_UART_USR_RFF_WIDTH 1
5399 /* The mask used to set the ALT_UART_USR_RFF register field value. */
5400 #define ALT_UART_USR_RFF_SET_MSK 0x00000010
5401 /* The mask used to clear the ALT_UART_USR_RFF register field value. */
5402 #define ALT_UART_USR_RFF_CLR_MSK 0xffffffef
5403 /* The reset value of the ALT_UART_USR_RFF register field. */
5404 #define ALT_UART_USR_RFF_RESET 0x0
5405 /* Extracts the ALT_UART_USR_RFF field value from a register. */
5406 #define ALT_UART_USR_RFF_GET(value) (((value) & 0x00000010) >> 4)
5407 /* Produces a ALT_UART_USR_RFF register field value suitable for setting the register. */
5408 #define ALT_UART_USR_RFF_SET(value) (((value) << 4) & 0x00000010)
5409 
5410 /*
5411  * Field : RSVD_USR_31to5
5412  *
5413  * Reserved bits [31:5] - Read Only
5414  *
5415  * Field Access Macros:
5416  *
5417  */
5418 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_RSVD_USR_31TO5 register field. */
5419 #define ALT_UART_USR_RSVD_USR_31TO5_LSB 5
5420 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_RSVD_USR_31TO5 register field. */
5421 #define ALT_UART_USR_RSVD_USR_31TO5_MSB 31
5422 /* The width in bits of the ALT_UART_USR_RSVD_USR_31TO5 register field. */
5423 #define ALT_UART_USR_RSVD_USR_31TO5_WIDTH 27
5424 /* The mask used to set the ALT_UART_USR_RSVD_USR_31TO5 register field value. */
5425 #define ALT_UART_USR_RSVD_USR_31TO5_SET_MSK 0xffffffe0
5426 /* The mask used to clear the ALT_UART_USR_RSVD_USR_31TO5 register field value. */
5427 #define ALT_UART_USR_RSVD_USR_31TO5_CLR_MSK 0x0000001f
5428 /* The reset value of the ALT_UART_USR_RSVD_USR_31TO5 register field. */
5429 #define ALT_UART_USR_RSVD_USR_31TO5_RESET 0x0
5430 /* Extracts the ALT_UART_USR_RSVD_USR_31TO5 field value from a register. */
5431 #define ALT_UART_USR_RSVD_USR_31TO5_GET(value) (((value) & 0xffffffe0) >> 5)
5432 /* Produces a ALT_UART_USR_RSVD_USR_31TO5 register field value suitable for setting the register. */
5433 #define ALT_UART_USR_RSVD_USR_31TO5_SET(value) (((value) << 5) & 0xffffffe0)
5434 
5435 #ifndef __ASSEMBLY__
5436 /*
5437  * WARNING: The C register and register group struct declarations are provided for
5438  * convenience and illustrative purposes. They should, however, be used with
5439  * caution as the C language standard provides no guarantees about the alignment or
5440  * atomicity of device memory accesses. The recommended practice for coding device
5441  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5442  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5443  * alt_write_dword() functions for 64 bit registers.
5444  *
5445  * The struct declaration for register ALT_UART_USR.
5446  */
5447 struct ALT_UART_USR_s
5448 {
5449  const volatile uint32_t RSVD_BUSY : 1; /* ALT_UART_USR_RSVD_BUSY */
5450  const volatile uint32_t TFNF : 1; /* ALT_UART_USR_TFNF */
5451  const volatile uint32_t TFE : 1; /* ALT_UART_USR_TFE */
5452  const volatile uint32_t RFNE : 1; /* ALT_UART_USR_RFNE */
5453  const volatile uint32_t RFF : 1; /* ALT_UART_USR_RFF */
5454  const volatile uint32_t RSVD_USR_31to5 : 27; /* ALT_UART_USR_RSVD_USR_31TO5 */
5455 };
5456 
5457 /* The typedef declaration for register ALT_UART_USR. */
5458 typedef struct ALT_UART_USR_s ALT_UART_USR_t;
5459 #endif /* __ASSEMBLY__ */
5460 
5461 /* The reset value of the ALT_UART_USR register. */
5462 #define ALT_UART_USR_RESET 0x00000006
5463 /* The byte offset of the ALT_UART_USR register from the beginning of the component. */
5464 #define ALT_UART_USR_OFST 0x7c
5465 /* The address of the ALT_UART_USR register. */
5466 #define ALT_UART_USR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_USR_OFST))
5467 
5468 /*
5469  * Register : Transmit FIFO Level - TFL
5470  *
5471  * Transmit FIFO Level.
5472  *
5473  * This register is valid only when the DW_apb_uart is configured to have
5474  * additional FIFO status registers
5475  *
5476  * implemented (FIFO_STAT = YES). If status registers are not implemented, this
5477  * register does not exist and
5478  *
5479  * reading from this register address returns 0.
5480  *
5481  * Register Layout
5482  *
5483  * Bits | Access | Reset | Description
5484  * :-------|:-------|:------|:-------------------------------------
5485  * [7:0] | R | 0x0 | ALT_UART_TFL_TFL
5486  * [31:8] | R | 0x0 | ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH
5487  *
5488  */
5489 /*
5490  * Field : tfl
5491  *
5492  * Transmit FIFO Level.
5493  *
5494  * This is indicates the number of data entries in the transmit FIFO.
5495  *
5496  * Field Access Macros:
5497  *
5498  */
5499 /* The Least Significant Bit (LSB) position of the ALT_UART_TFL_TFL register field. */
5500 #define ALT_UART_TFL_TFL_LSB 0
5501 /* The Most Significant Bit (MSB) position of the ALT_UART_TFL_TFL register field. */
5502 #define ALT_UART_TFL_TFL_MSB 7
5503 /* The width in bits of the ALT_UART_TFL_TFL register field. */
5504 #define ALT_UART_TFL_TFL_WIDTH 8
5505 /* The mask used to set the ALT_UART_TFL_TFL register field value. */
5506 #define ALT_UART_TFL_TFL_SET_MSK 0x000000ff
5507 /* The mask used to clear the ALT_UART_TFL_TFL register field value. */
5508 #define ALT_UART_TFL_TFL_CLR_MSK 0xffffff00
5509 /* The reset value of the ALT_UART_TFL_TFL register field. */
5510 #define ALT_UART_TFL_TFL_RESET 0x0
5511 /* Extracts the ALT_UART_TFL_TFL field value from a register. */
5512 #define ALT_UART_TFL_TFL_GET(value) (((value) & 0x000000ff) >> 0)
5513 /* Produces a ALT_UART_TFL_TFL register field value suitable for setting the register. */
5514 #define ALT_UART_TFL_TFL_SET(value) (((value) << 0) & 0x000000ff)
5515 
5516 /*
5517  * Field : RSVD_TFL_31toADDR_WIDTH
5518  *
5519  * Reserved bits: 31 downto addr bus width + 1 - Read Only
5520  *
5521  * Field Access Macros:
5522  *
5523  */
5524 /* The Least Significant Bit (LSB) position of the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field. */
5525 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_LSB 8
5526 /* The Most Significant Bit (MSB) position of the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field. */
5527 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_MSB 31
5528 /* The width in bits of the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field. */
5529 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_WIDTH 24
5530 /* The mask used to set the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field value. */
5531 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_SET_MSK 0xffffff00
5532 /* The mask used to clear the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field value. */
5533 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_CLR_MSK 0x000000ff
5534 /* The reset value of the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field. */
5535 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_RESET 0x0
5536 /* Extracts the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH field value from a register. */
5537 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_GET(value) (((value) & 0xffffff00) >> 8)
5538 /* Produces a ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field value suitable for setting the register. */
5539 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_SET(value) (((value) << 8) & 0xffffff00)
5540 
5541 #ifndef __ASSEMBLY__
5542 /*
5543  * WARNING: The C register and register group struct declarations are provided for
5544  * convenience and illustrative purposes. They should, however, be used with
5545  * caution as the C language standard provides no guarantees about the alignment or
5546  * atomicity of device memory accesses. The recommended practice for coding device
5547  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5548  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5549  * alt_write_dword() functions for 64 bit registers.
5550  *
5551  * The struct declaration for register ALT_UART_TFL.
5552  */
5553 struct ALT_UART_TFL_s
5554 {
5555  const volatile uint32_t tfl : 8; /* ALT_UART_TFL_TFL */
5556  const volatile uint32_t RSVD_TFL_31toADDR_WIDTH : 24; /* ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH */
5557 };
5558 
5559 /* The typedef declaration for register ALT_UART_TFL. */
5560 typedef struct ALT_UART_TFL_s ALT_UART_TFL_t;
5561 #endif /* __ASSEMBLY__ */
5562 
5563 /* The reset value of the ALT_UART_TFL register. */
5564 #define ALT_UART_TFL_RESET 0x00000000
5565 /* The byte offset of the ALT_UART_TFL register from the beginning of the component. */
5566 #define ALT_UART_TFL_OFST 0x80
5567 /* The address of the ALT_UART_TFL register. */
5568 #define ALT_UART_TFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFL_OFST))
5569 
5570 /*
5571  * Register : Receive FIFO Level - RFL
5572  *
5573  * Receive FIFO Level.
5574  *
5575  * This register is valid only when the DW_apb_uart is configured to have
5576  * additional FIFO status registers
5577  *
5578  * implemented (FIFO_STAT = YES). If status registers are not implemented, this
5579  * register does not exist and
5580  *
5581  * reading from this register address returns 0.
5582  *
5583  * Register Layout
5584  *
5585  * Bits | Access | Reset | Description
5586  * :-------|:-------|:------|:-------------------------------------
5587  * [7:0] | R | 0x0 | ALT_UART_RFL_RFL
5588  * [31:8] | R | 0x0 | ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH
5589  *
5590  */
5591 /*
5592  * Field : rfl
5593  *
5594  * Receive FIFO Level.
5595  *
5596  * This is indicates the number of data entries in the receive FIFO.
5597  *
5598  * Field Access Macros:
5599  *
5600  */
5601 /* The Least Significant Bit (LSB) position of the ALT_UART_RFL_RFL register field. */
5602 #define ALT_UART_RFL_RFL_LSB 0
5603 /* The Most Significant Bit (MSB) position of the ALT_UART_RFL_RFL register field. */
5604 #define ALT_UART_RFL_RFL_MSB 7
5605 /* The width in bits of the ALT_UART_RFL_RFL register field. */
5606 #define ALT_UART_RFL_RFL_WIDTH 8
5607 /* The mask used to set the ALT_UART_RFL_RFL register field value. */
5608 #define ALT_UART_RFL_RFL_SET_MSK 0x000000ff
5609 /* The mask used to clear the ALT_UART_RFL_RFL register field value. */
5610 #define ALT_UART_RFL_RFL_CLR_MSK 0xffffff00
5611 /* The reset value of the ALT_UART_RFL_RFL register field. */
5612 #define ALT_UART_RFL_RFL_RESET 0x0
5613 /* Extracts the ALT_UART_RFL_RFL field value from a register. */
5614 #define ALT_UART_RFL_RFL_GET(value) (((value) & 0x000000ff) >> 0)
5615 /* Produces a ALT_UART_RFL_RFL register field value suitable for setting the register. */
5616 #define ALT_UART_RFL_RFL_SET(value) (((value) << 0) & 0x000000ff)
5617 
5618 /*
5619  * Field : RSVD_RFL_31toADDR_WIDTH
5620  *
5621  * Reserved bits: 31 downnto addr bus width + 1 - Read Only
5622  *
5623  * Field Access Macros:
5624  *
5625  */
5626 /* The Least Significant Bit (LSB) position of the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field. */
5627 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_LSB 8
5628 /* The Most Significant Bit (MSB) position of the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field. */
5629 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_MSB 31
5630 /* The width in bits of the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field. */
5631 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_WIDTH 24
5632 /* The mask used to set the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field value. */
5633 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_SET_MSK 0xffffff00
5634 /* The mask used to clear the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field value. */
5635 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_CLR_MSK 0x000000ff
5636 /* The reset value of the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field. */
5637 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_RESET 0x0
5638 /* Extracts the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH field value from a register. */
5639 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_GET(value) (((value) & 0xffffff00) >> 8)
5640 /* Produces a ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field value suitable for setting the register. */
5641 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_SET(value) (((value) << 8) & 0xffffff00)
5642 
5643 #ifndef __ASSEMBLY__
5644 /*
5645  * WARNING: The C register and register group struct declarations are provided for
5646  * convenience and illustrative purposes. They should, however, be used with
5647  * caution as the C language standard provides no guarantees about the alignment or
5648  * atomicity of device memory accesses. The recommended practice for coding device
5649  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5650  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5651  * alt_write_dword() functions for 64 bit registers.
5652  *
5653  * The struct declaration for register ALT_UART_RFL.
5654  */
5655 struct ALT_UART_RFL_s
5656 {
5657  const volatile uint32_t rfl : 8; /* ALT_UART_RFL_RFL */
5658  const volatile uint32_t RSVD_RFL_31toADDR_WIDTH : 24; /* ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH */
5659 };
5660 
5661 /* The typedef declaration for register ALT_UART_RFL. */
5662 typedef struct ALT_UART_RFL_s ALT_UART_RFL_t;
5663 #endif /* __ASSEMBLY__ */
5664 
5665 /* The reset value of the ALT_UART_RFL register. */
5666 #define ALT_UART_RFL_RESET 0x00000000
5667 /* The byte offset of the ALT_UART_RFL register from the beginning of the component. */
5668 #define ALT_UART_RFL_OFST 0x84
5669 /* The address of the ALT_UART_RFL register. */
5670 #define ALT_UART_RFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFL_OFST))
5671 
5672 /*
5673  * Register : Software Reset Register - SRR
5674  *
5675  * Software Reset Register.
5676  *
5677  * Register Layout
5678  *
5679  * Bits | Access | Reset | Description
5680  * :-------|:-------|:------|:----------------------------
5681  * [0] | W | 0x0 | ALT_UART_SRR_UR
5682  * [1] | W | 0x0 | ALT_UART_SRR_RFR
5683  * [2] | W | 0x0 | ALT_UART_SRR_XFR
5684  * [31:3] | R | 0x0 | ALT_UART_SRR_RSVD_SRR_31TO3
5685  *
5686  */
5687 /*
5688  * Field : UR
5689  *
5690  * UART Reset.
5691  *
5692  * This asynchronously resets the DW_apb_uart and synchronously removes the reset
5693  *
5694  * assertion. For a two clock implementation both pclk and sclk domains will be
5695  * reset.
5696  *
5697  * Field Enumeration Values:
5698  *
5699  * Enum | Value | Description
5700  * :---------------------------|:------|:--------------
5701  * ALT_UART_SRR_UR_E_NO_RESET | 0x0 | No Uart Reset
5702  * ALT_UART_SRR_UR_E_RESET | 0x1 | Uart reset
5703  *
5704  * Field Access Macros:
5705  *
5706  */
5707 /*
5708  * Enumerated value for register field ALT_UART_SRR_UR
5709  *
5710  * No Uart Reset
5711  */
5712 #define ALT_UART_SRR_UR_E_NO_RESET 0x0
5713 /*
5714  * Enumerated value for register field ALT_UART_SRR_UR
5715  *
5716  * Uart reset
5717  */
5718 #define ALT_UART_SRR_UR_E_RESET 0x1
5719 
5720 /* The Least Significant Bit (LSB) position of the ALT_UART_SRR_UR register field. */
5721 #define ALT_UART_SRR_UR_LSB 0
5722 /* The Most Significant Bit (MSB) position of the ALT_UART_SRR_UR register field. */
5723 #define ALT_UART_SRR_UR_MSB 0
5724 /* The width in bits of the ALT_UART_SRR_UR register field. */
5725 #define ALT_UART_SRR_UR_WIDTH 1
5726 /* The mask used to set the ALT_UART_SRR_UR register field value. */
5727 #define ALT_UART_SRR_UR_SET_MSK 0x00000001
5728 /* The mask used to clear the ALT_UART_SRR_UR register field value. */
5729 #define ALT_UART_SRR_UR_CLR_MSK 0xfffffffe
5730 /* The reset value of the ALT_UART_SRR_UR register field. */
5731 #define ALT_UART_SRR_UR_RESET 0x0
5732 /* Extracts the ALT_UART_SRR_UR field value from a register. */
5733 #define ALT_UART_SRR_UR_GET(value) (((value) & 0x00000001) >> 0)
5734 /* Produces a ALT_UART_SRR_UR register field value suitable for setting the register. */
5735 #define ALT_UART_SRR_UR_SET(value) (((value) << 0) & 0x00000001)
5736 
5737 /*
5738  * Field : RFR
5739  *
5740  * RCVR FIFO Reset.
5741  *
5742  * Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for
5743  *
5744  * the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on
5745  * software
5746  *
5747  * having to store previously written FCR values (which are pretty static) just to
5748  *
5749  * reset the reeive FIFO.
5750  *
5751  * This resets the control portion of the receive FIFO and treats the FIFO as
5752  * empty.
5753  *
5754  * This will also de-assert the DMA RX request and single signals when additional
5755  * DMA
5756  *
5757  * handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is
5758  *
5759  * 'self-clearing' and it is not necessary to clear this bit.
5760  *
5761  * Field Access Macros:
5762  *
5763  */
5764 /* The Least Significant Bit (LSB) position of the ALT_UART_SRR_RFR register field. */
5765 #define ALT_UART_SRR_RFR_LSB 1
5766 /* The Most Significant Bit (MSB) position of the ALT_UART_SRR_RFR register field. */
5767 #define ALT_UART_SRR_RFR_MSB 1
5768 /* The width in bits of the ALT_UART_SRR_RFR register field. */
5769 #define ALT_UART_SRR_RFR_WIDTH 1
5770 /* The mask used to set the ALT_UART_SRR_RFR register field value. */
5771 #define ALT_UART_SRR_RFR_SET_MSK 0x00000002
5772 /* The mask used to clear the ALT_UART_SRR_RFR register field value. */
5773 #define ALT_UART_SRR_RFR_CLR_MSK 0xfffffffd
5774 /* The reset value of the ALT_UART_SRR_RFR register field. */
5775 #define ALT_UART_SRR_RFR_RESET 0x0
5776 /* Extracts the ALT_UART_SRR_RFR field value from a register. */
5777 #define ALT_UART_SRR_RFR_GET(value) (((value) & 0x00000002) >> 1)
5778 /* Produces a ALT_UART_SRR_RFR register field value suitable for setting the register. */
5779 #define ALT_UART_SRR_RFR_SET(value) (((value) << 1) & 0x00000002)
5780 
5781 /*
5782  * Field : XFR
5783  *
5784  * XMIT FIFO Reset.
5785  *
5786  * Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for
5787  *
5788  * the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on
5789  * software
5790  *
5791  * having to store previously written FCR values (which are pretty static) just to
5792  *
5793  * reset the transmit FIFO.
5794  *
5795  * This resets the control portion of the transmit FIFO and treats the FIFO as
5796  * empty.
5797  *
5798  * This will also de-assert the DMA TX request and single signals when additional
5799  * DMA
5800  *
5801  * handshaking signals are selected
5802  *
5803  * Field Access Macros:
5804  *
5805  */
5806 /* The Least Significant Bit (LSB) position of the ALT_UART_SRR_XFR register field. */
5807 #define ALT_UART_SRR_XFR_LSB 2
5808 /* The Most Significant Bit (MSB) position of the ALT_UART_SRR_XFR register field. */
5809 #define ALT_UART_SRR_XFR_MSB 2
5810 /* The width in bits of the ALT_UART_SRR_XFR register field. */
5811 #define ALT_UART_SRR_XFR_WIDTH 1
5812 /* The mask used to set the ALT_UART_SRR_XFR register field value. */
5813 #define ALT_UART_SRR_XFR_SET_MSK 0x00000004
5814 /* The mask used to clear the ALT_UART_SRR_XFR register field value. */
5815 #define ALT_UART_SRR_XFR_CLR_MSK 0xfffffffb
5816 /* The reset value of the ALT_UART_SRR_XFR register field. */
5817 #define ALT_UART_SRR_XFR_RESET 0x0
5818 /* Extracts the ALT_UART_SRR_XFR field value from a register. */
5819 #define ALT_UART_SRR_XFR_GET(value) (((value) & 0x00000004) >> 2)
5820 /* Produces a ALT_UART_SRR_XFR register field value suitable for setting the register. */
5821 #define ALT_UART_SRR_XFR_SET(value) (((value) << 2) & 0x00000004)
5822 
5823 /*
5824  * Field : RSVD_SRR_31to3
5825  *
5826  * Reserved bits [31:3] - Read Only
5827  *
5828  * Field Access Macros:
5829  *
5830  */
5831 /* The Least Significant Bit (LSB) position of the ALT_UART_SRR_RSVD_SRR_31TO3 register field. */
5832 #define ALT_UART_SRR_RSVD_SRR_31TO3_LSB 3
5833 /* The Most Significant Bit (MSB) position of the ALT_UART_SRR_RSVD_SRR_31TO3 register field. */
5834 #define ALT_UART_SRR_RSVD_SRR_31TO3_MSB 31
5835 /* The width in bits of the ALT_UART_SRR_RSVD_SRR_31TO3 register field. */
5836 #define ALT_UART_SRR_RSVD_SRR_31TO3_WIDTH 29
5837 /* The mask used to set the ALT_UART_SRR_RSVD_SRR_31TO3 register field value. */
5838 #define ALT_UART_SRR_RSVD_SRR_31TO3_SET_MSK 0xfffffff8
5839 /* The mask used to clear the ALT_UART_SRR_RSVD_SRR_31TO3 register field value. */
5840 #define ALT_UART_SRR_RSVD_SRR_31TO3_CLR_MSK 0x00000007
5841 /* The reset value of the ALT_UART_SRR_RSVD_SRR_31TO3 register field. */
5842 #define ALT_UART_SRR_RSVD_SRR_31TO3_RESET 0x0
5843 /* Extracts the ALT_UART_SRR_RSVD_SRR_31TO3 field value from a register. */
5844 #define ALT_UART_SRR_RSVD_SRR_31TO3_GET(value) (((value) & 0xfffffff8) >> 3)
5845 /* Produces a ALT_UART_SRR_RSVD_SRR_31TO3 register field value suitable for setting the register. */
5846 #define ALT_UART_SRR_RSVD_SRR_31TO3_SET(value) (((value) << 3) & 0xfffffff8)
5847 
5848 #ifndef __ASSEMBLY__
5849 /*
5850  * WARNING: The C register and register group struct declarations are provided for
5851  * convenience and illustrative purposes. They should, however, be used with
5852  * caution as the C language standard provides no guarantees about the alignment or
5853  * atomicity of device memory accesses. The recommended practice for coding device
5854  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5855  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5856  * alt_write_dword() functions for 64 bit registers.
5857  *
5858  * The struct declaration for register ALT_UART_SRR.
5859  */
5860 struct ALT_UART_SRR_s
5861 {
5862  volatile uint32_t UR : 1; /* ALT_UART_SRR_UR */
5863  volatile uint32_t RFR : 1; /* ALT_UART_SRR_RFR */
5864  volatile uint32_t XFR : 1; /* ALT_UART_SRR_XFR */
5865  const volatile uint32_t RSVD_SRR_31to3 : 29; /* ALT_UART_SRR_RSVD_SRR_31TO3 */
5866 };
5867 
5868 /* The typedef declaration for register ALT_UART_SRR. */
5869 typedef struct ALT_UART_SRR_s ALT_UART_SRR_t;
5870 #endif /* __ASSEMBLY__ */
5871 
5872 /* The reset value of the ALT_UART_SRR register. */
5873 #define ALT_UART_SRR_RESET 0x00000000
5874 /* The byte offset of the ALT_UART_SRR register from the beginning of the component. */
5875 #define ALT_UART_SRR_OFST 0x88
5876 /* The address of the ALT_UART_SRR register. */
5877 #define ALT_UART_SRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRR_OFST))
5878 
5879 /*
5880  * Register : Shadow Request to Send - SRTS
5881  *
5882  * Shadow Request to Send.
5883  *
5884  * Register Layout
5885  *
5886  * Bits | Access | Reset | Description
5887  * :-------|:-------|:------|:------------------------------
5888  * [0] | RW | 0x0 | ALT_UART_SRTS_SRTS
5889  * [31:1] | R | 0x0 | ALT_UART_SRTS_RSVD_SRTS_31TO1
5890  *
5891  */
5892 /*
5893  * Field : srts
5894  *
5895  * Shadow Request to Send.
5896  *
5897  * This is a shadow register for the RTS bit (MCR[1]), this can be used to remove
5898  * the
5899  *
5900  * burden of having to performing a read modify write on the MCR.
5901  *
5902  * This is used to directly control the Request to Send (rts_n) output. The Request
5903  *
5904  * To Send (rts_n) output is used to inform the modem or data set that the UART is
5905  * ready
5906  *
5907  * to exchange data.
5908  *
5909  * When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal
5910  * is
5911  *
5912  * set low by programming MCR[1] (RTS) to a high.
5913  *
5914  * In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and
5915  * FIFO's
5916  *
5917  * enable (FCR[0] set to one), the rts_n output is controlled in the same way, but
5918  * is
5919  *
5920  * also gated with the receiver FIFO threshold trigger (rts_n is inactive high when
5921  *
5922  * above the threshold) only when RTC Flow Trigger is disabled; otherwise it is
5923  * gated by
5924  *
5925  * the receiver FIFO almost-full trigger, where "almost full" refers to two
5926  * available
5927  *
5928  * slots in the FIFO (rts_n is inactive high when above the threshold).
5929  *
5930  * Note that in Loopback mode (MCR[4] set to one), the rts_n output is held
5931  * inactive
5932  *
5933  * high while the value of this location is internally looped back to an input.
5934  *
5935  * Field Enumeration Values:
5936  *
5937  * Enum | Value | Description
5938  * :--------------------------------|:------|:-----------------------------------------
5939  * ALT_UART_SRTS_SRTS_E_DEASSERTED | 0x0 | Shadow Request to Send uart_rts_n logic1
5940  * ALT_UART_SRTS_SRTS_E_ASSERTED | 0x1 | Shadow Request to Send uart_rts_n logic0
5941  *
5942  * Field Access Macros:
5943  *
5944  */
5945 /*
5946  * Enumerated value for register field ALT_UART_SRTS_SRTS
5947  *
5948  * Shadow Request to Send uart_rts_n logic1
5949  */
5950 #define ALT_UART_SRTS_SRTS_E_DEASSERTED 0x0
5951 /*
5952  * Enumerated value for register field ALT_UART_SRTS_SRTS
5953  *
5954  * Shadow Request to Send uart_rts_n logic0
5955  */
5956 #define ALT_UART_SRTS_SRTS_E_ASSERTED 0x1
5957 
5958 /* The Least Significant Bit (LSB) position of the ALT_UART_SRTS_SRTS register field. */
5959 #define ALT_UART_SRTS_SRTS_LSB 0
5960 /* The Most Significant Bit (MSB) position of the ALT_UART_SRTS_SRTS register field. */
5961 #define ALT_UART_SRTS_SRTS_MSB 0
5962 /* The width in bits of the ALT_UART_SRTS_SRTS register field. */
5963 #define ALT_UART_SRTS_SRTS_WIDTH 1
5964 /* The mask used to set the ALT_UART_SRTS_SRTS register field value. */
5965 #define ALT_UART_SRTS_SRTS_SET_MSK 0x00000001
5966 /* The mask used to clear the ALT_UART_SRTS_SRTS register field value. */
5967 #define ALT_UART_SRTS_SRTS_CLR_MSK 0xfffffffe
5968 /* The reset value of the ALT_UART_SRTS_SRTS register field. */
5969 #define ALT_UART_SRTS_SRTS_RESET 0x0
5970 /* Extracts the ALT_UART_SRTS_SRTS field value from a register. */
5971 #define ALT_UART_SRTS_SRTS_GET(value) (((value) & 0x00000001) >> 0)
5972 /* Produces a ALT_UART_SRTS_SRTS register field value suitable for setting the register. */
5973 #define ALT_UART_SRTS_SRTS_SET(value) (((value) << 0) & 0x00000001)
5974 
5975 /*
5976  * Field : RSVD_SRTS_31to1
5977  *
5978  * Reserved bits [31:1] - Read Only
5979  *
5980  * Field Access Macros:
5981  *
5982  */
5983 /* The Least Significant Bit (LSB) position of the ALT_UART_SRTS_RSVD_SRTS_31TO1 register field. */
5984 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_LSB 1
5985 /* The Most Significant Bit (MSB) position of the ALT_UART_SRTS_RSVD_SRTS_31TO1 register field. */
5986 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_MSB 31
5987 /* The width in bits of the ALT_UART_SRTS_RSVD_SRTS_31TO1 register field. */
5988 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_WIDTH 31
5989 /* The mask used to set the ALT_UART_SRTS_RSVD_SRTS_31TO1 register field value. */
5990 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_SET_MSK 0xfffffffe
5991 /* The mask used to clear the ALT_UART_SRTS_RSVD_SRTS_31TO1 register field value. */
5992 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_CLR_MSK 0x00000001
5993 /* The reset value of the ALT_UART_SRTS_RSVD_SRTS_31TO1 register field. */
5994 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_RESET 0x0
5995 /* Extracts the ALT_UART_SRTS_RSVD_SRTS_31TO1 field value from a register. */
5996 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
5997 /* Produces a ALT_UART_SRTS_RSVD_SRTS_31TO1 register field value suitable for setting the register. */
5998 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
5999 
6000 #ifndef __ASSEMBLY__
6001 /*
6002  * WARNING: The C register and register group struct declarations are provided for
6003  * convenience and illustrative purposes. They should, however, be used with
6004  * caution as the C language standard provides no guarantees about the alignment or
6005  * atomicity of device memory accesses. The recommended practice for coding device
6006  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6007  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6008  * alt_write_dword() functions for 64 bit registers.
6009  *
6010  * The struct declaration for register ALT_UART_SRTS.
6011  */
6012 struct ALT_UART_SRTS_s
6013 {
6014  volatile uint32_t srts : 1; /* ALT_UART_SRTS_SRTS */
6015  const volatile uint32_t RSVD_SRTS_31to1 : 31; /* ALT_UART_SRTS_RSVD_SRTS_31TO1 */
6016 };
6017 
6018 /* The typedef declaration for register ALT_UART_SRTS. */
6019 typedef struct ALT_UART_SRTS_s ALT_UART_SRTS_t;
6020 #endif /* __ASSEMBLY__ */
6021 
6022 /* The reset value of the ALT_UART_SRTS register. */
6023 #define ALT_UART_SRTS_RESET 0x00000000
6024 /* The byte offset of the ALT_UART_SRTS register from the beginning of the component. */
6025 #define ALT_UART_SRTS_OFST 0x8c
6026 /* The address of the ALT_UART_SRTS register. */
6027 #define ALT_UART_SRTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRTS_OFST))
6028 
6029 /*
6030  * Register : Shadow Break Control Register - SBCR
6031  *
6032  * Shadow Break Control Register.
6033  *
6034  * Register Layout
6035  *
6036  * Bits | Access | Reset | Description
6037  * :-------|:-------|:------|:------------------------------
6038  * [0] | RW | 0x0 | ALT_UART_SBCR_SBCB
6039  * [31:1] | R | 0x0 | ALT_UART_SBCR_RSVD_SBCR_31TO1
6040  *
6041  */
6042 /*
6043  * Field : sbcb
6044  *
6045  * Shadow Break Control Bit.
6046  *
6047  * This is a shadow register for the Break bit (LCR[6]), this can be used to remove
6048  *
6049  * the burden of having to performing a read modify write on the LCR.
6050  *
6051  * This is used to cause a break condition to be transmitted to the receiving
6052  * device.
6053  *
6054  * If set to one the serial output is forced to the spacing (logic 0) state. When
6055  * not
6056  *
6057  * in Loopback Mode, as determined by MCR[4], the sout line is forced low until the
6058  *
6059  * Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the
6060  *
6061  * sir_out_n line is continuously pulsed. When in Loopback Mode, the break
6062  * condition
6063  *
6064  * is internally looped back to the receiver.
6065  *
6066  * Field Enumeration Values:
6067  *
6068  * Enum | Value | Description
6069  * :------------------------------|:------|:------------------------------------
6070  * ALT_UART_SBCR_SBCB_E_NO_BREAK | 0x0 | No spacing on serial output
6071  * ALT_UART_SBCR_SBCB_E_BREAK | 0x1 | Serial output forced to the spacing
6072  *
6073  * Field Access Macros:
6074  *
6075  */
6076 /*
6077  * Enumerated value for register field ALT_UART_SBCR_SBCB
6078  *
6079  * No spacing on serial output
6080  */
6081 #define ALT_UART_SBCR_SBCB_E_NO_BREAK 0x0
6082 /*
6083  * Enumerated value for register field ALT_UART_SBCR_SBCB
6084  *
6085  * Serial output forced to the spacing
6086  */
6087 #define ALT_UART_SBCR_SBCB_E_BREAK 0x1
6088 
6089 /* The Least Significant Bit (LSB) position of the ALT_UART_SBCR_SBCB register field. */
6090 #define ALT_UART_SBCR_SBCB_LSB 0
6091 /* The Most Significant Bit (MSB) position of the ALT_UART_SBCR_SBCB register field. */
6092 #define ALT_UART_SBCR_SBCB_MSB 0
6093 /* The width in bits of the ALT_UART_SBCR_SBCB register field. */
6094 #define ALT_UART_SBCR_SBCB_WIDTH 1
6095 /* The mask used to set the ALT_UART_SBCR_SBCB register field value. */
6096 #define ALT_UART_SBCR_SBCB_SET_MSK 0x00000001
6097 /* The mask used to clear the ALT_UART_SBCR_SBCB register field value. */
6098 #define ALT_UART_SBCR_SBCB_CLR_MSK 0xfffffffe
6099 /* The reset value of the ALT_UART_SBCR_SBCB register field. */
6100 #define ALT_UART_SBCR_SBCB_RESET 0x0
6101 /* Extracts the ALT_UART_SBCR_SBCB field value from a register. */
6102 #define ALT_UART_SBCR_SBCB_GET(value) (((value) & 0x00000001) >> 0)
6103 /* Produces a ALT_UART_SBCR_SBCB register field value suitable for setting the register. */
6104 #define ALT_UART_SBCR_SBCB_SET(value) (((value) << 0) & 0x00000001)
6105 
6106 /*
6107  * Field : RSVD_SBCR_31to1
6108  *
6109  * Reserved bits [31:1] - Read Only
6110  *
6111  * Field Access Macros:
6112  *
6113  */
6114 /* The Least Significant Bit (LSB) position of the ALT_UART_SBCR_RSVD_SBCR_31TO1 register field. */
6115 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_LSB 1
6116 /* The Most Significant Bit (MSB) position of the ALT_UART_SBCR_RSVD_SBCR_31TO1 register field. */
6117 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_MSB 31
6118 /* The width in bits of the ALT_UART_SBCR_RSVD_SBCR_31TO1 register field. */
6119 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_WIDTH 31
6120 /* The mask used to set the ALT_UART_SBCR_RSVD_SBCR_31TO1 register field value. */
6121 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_SET_MSK 0xfffffffe
6122 /* The mask used to clear the ALT_UART_SBCR_RSVD_SBCR_31TO1 register field value. */
6123 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_CLR_MSK 0x00000001
6124 /* The reset value of the ALT_UART_SBCR_RSVD_SBCR_31TO1 register field. */
6125 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_RESET 0x0
6126 /* Extracts the ALT_UART_SBCR_RSVD_SBCR_31TO1 field value from a register. */
6127 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
6128 /* Produces a ALT_UART_SBCR_RSVD_SBCR_31TO1 register field value suitable for setting the register. */
6129 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
6130 
6131 #ifndef __ASSEMBLY__
6132 /*
6133  * WARNING: The C register and register group struct declarations are provided for
6134  * convenience and illustrative purposes. They should, however, be used with
6135  * caution as the C language standard provides no guarantees about the alignment or
6136  * atomicity of device memory accesses. The recommended practice for coding device
6137  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6138  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6139  * alt_write_dword() functions for 64 bit registers.
6140  *
6141  * The struct declaration for register ALT_UART_SBCR.
6142  */
6143 struct ALT_UART_SBCR_s
6144 {
6145  volatile uint32_t sbcb : 1; /* ALT_UART_SBCR_SBCB */
6146  const volatile uint32_t RSVD_SBCR_31to1 : 31; /* ALT_UART_SBCR_RSVD_SBCR_31TO1 */
6147 };
6148 
6149 /* The typedef declaration for register ALT_UART_SBCR. */
6150 typedef struct ALT_UART_SBCR_s ALT_UART_SBCR_t;
6151 #endif /* __ASSEMBLY__ */
6152 
6153 /* The reset value of the ALT_UART_SBCR register. */
6154 #define ALT_UART_SBCR_RESET 0x00000000
6155 /* The byte offset of the ALT_UART_SBCR register from the beginning of the component. */
6156 #define ALT_UART_SBCR_OFST 0x90
6157 /* The address of the ALT_UART_SBCR register. */
6158 #define ALT_UART_SBCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SBCR_OFST))
6159 
6160 /*
6161  * Register : Shadow DMA Mode - SDMAM
6162  *
6163  * Shadow DMA Mode.
6164  *
6165  * Register Layout
6166  *
6167  * Bits | Access | Reset | Description
6168  * :-------|:-------|:------|:--------------------------------
6169  * [0] | RW | 0x0 | ALT_UART_SDMAM_SDMAM
6170  * [31:1] | R | 0x0 | ALT_UART_SDMAM_RSVD_SDMAM_31TO1
6171  *
6172  */
6173 /*
6174  * Field : sdmam
6175  *
6176  * Shadow DMA Mode.
6177  *
6178  * This is a shadow register for the DMA mode bit (FCR[3]). This can be used to
6179  * remove
6180  *
6181  * the burden of having to store the previously written value to the FCR in memory
6182  * and
6183  *
6184  * having to mask this value so that only the DMA Mode bit gets updated.
6185  *
6186  * This determines the DMA signalling mode used for the dma_tx_req_n and
6187  * dma_rx_req_n
6188  *
6189  * output signals when additional DMA handshaking signals are not selected
6190  *
6191  * (DMA_EXTRA == NO). See section 5.9 on page 54 for details on DMA support.
6192  *
6193  * 0 = mode 0
6194  *
6195  * 1 = mode 1
6196  *
6197  * Field Enumeration Values:
6198  *
6199  * Enum | Value | Description
6200  * :------------------------------|:------|:------------
6201  * ALT_UART_SDMAM_SDMAM_E_MODE_0 | 0x0 | Mode 0
6202  * ALT_UART_SDMAM_SDMAM_E_MODE_1 | 0x1 | Mode 1
6203  *
6204  * Field Access Macros:
6205  *
6206  */
6207 /*
6208  * Enumerated value for register field ALT_UART_SDMAM_SDMAM
6209  *
6210  * Mode 0
6211  */
6212 #define ALT_UART_SDMAM_SDMAM_E_MODE_0 0x0
6213 /*
6214  * Enumerated value for register field ALT_UART_SDMAM_SDMAM
6215  *
6216  * Mode 1
6217  */
6218 #define ALT_UART_SDMAM_SDMAM_E_MODE_1 0x1
6219 
6220 /* The Least Significant Bit (LSB) position of the ALT_UART_SDMAM_SDMAM register field. */
6221 #define ALT_UART_SDMAM_SDMAM_LSB 0
6222 /* The Most Significant Bit (MSB) position of the ALT_UART_SDMAM_SDMAM register field. */
6223 #define ALT_UART_SDMAM_SDMAM_MSB 0
6224 /* The width in bits of the ALT_UART_SDMAM_SDMAM register field. */
6225 #define ALT_UART_SDMAM_SDMAM_WIDTH 1
6226 /* The mask used to set the ALT_UART_SDMAM_SDMAM register field value. */
6227 #define ALT_UART_SDMAM_SDMAM_SET_MSK 0x00000001
6228 /* The mask used to clear the ALT_UART_SDMAM_SDMAM register field value. */
6229 #define ALT_UART_SDMAM_SDMAM_CLR_MSK 0xfffffffe
6230 /* The reset value of the ALT_UART_SDMAM_SDMAM register field. */
6231 #define ALT_UART_SDMAM_SDMAM_RESET 0x0
6232 /* Extracts the ALT_UART_SDMAM_SDMAM field value from a register. */
6233 #define ALT_UART_SDMAM_SDMAM_GET(value) (((value) & 0x00000001) >> 0)
6234 /* Produces a ALT_UART_SDMAM_SDMAM register field value suitable for setting the register. */
6235 #define ALT_UART_SDMAM_SDMAM_SET(value) (((value) << 0) & 0x00000001)
6236 
6237 /*
6238  * Field : RSVD_SDMAM_31to1
6239  *
6240  * Reserved bits [31:1] - Read Only
6241  *
6242  * Field Access Macros:
6243  *
6244  */
6245 /* The Least Significant Bit (LSB) position of the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field. */
6246 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_LSB 1
6247 /* The Most Significant Bit (MSB) position of the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field. */
6248 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_MSB 31
6249 /* The width in bits of the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field. */
6250 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_WIDTH 31
6251 /* The mask used to set the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field value. */
6252 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_SET_MSK 0xfffffffe
6253 /* The mask used to clear the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field value. */
6254 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_CLR_MSK 0x00000001
6255 /* The reset value of the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field. */
6256 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_RESET 0x0
6257 /* Extracts the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 field value from a register. */
6258 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
6259 /* Produces a ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field value suitable for setting the register. */
6260 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
6261 
6262 #ifndef __ASSEMBLY__
6263 /*
6264  * WARNING: The C register and register group struct declarations are provided for
6265  * convenience and illustrative purposes. They should, however, be used with
6266  * caution as the C language standard provides no guarantees about the alignment or
6267  * atomicity of device memory accesses. The recommended practice for coding device
6268  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6269  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6270  * alt_write_dword() functions for 64 bit registers.
6271  *
6272  * The struct declaration for register ALT_UART_SDMAM.
6273  */
6274 struct ALT_UART_SDMAM_s
6275 {
6276  volatile uint32_t sdmam : 1; /* ALT_UART_SDMAM_SDMAM */
6277  const volatile uint32_t RSVD_SDMAM_31to1 : 31; /* ALT_UART_SDMAM_RSVD_SDMAM_31TO1 */
6278 };
6279 
6280 /* The typedef declaration for register ALT_UART_SDMAM. */
6281 typedef struct ALT_UART_SDMAM_s ALT_UART_SDMAM_t;
6282 #endif /* __ASSEMBLY__ */
6283 
6284 /* The reset value of the ALT_UART_SDMAM register. */
6285 #define ALT_UART_SDMAM_RESET 0x00000000
6286 /* The byte offset of the ALT_UART_SDMAM register from the beginning of the component. */
6287 #define ALT_UART_SDMAM_OFST 0x94
6288 /* The address of the ALT_UART_SDMAM register. */
6289 #define ALT_UART_SDMAM_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SDMAM_OFST))
6290 
6291 /*
6292  * Register : Shadow FIFO Enable - SFE
6293  *
6294  * Shadow FIFO Enable
6295  *
6296  * Register Layout
6297  *
6298  * Bits | Access | Reset | Description
6299  * :-------|:-------|:------|:----------------------------
6300  * [0] | RW | 0x0 | ALT_UART_SFE_SFE
6301  * [31:1] | R | 0x0 | ALT_UART_SFE_RSVD_SFE_31TO1
6302  *
6303  */
6304 /*
6305  * Field : sfe
6306  *
6307  * Shadow FIFO Enable.
6308  *
6309  * This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to
6310  *
6311  * remove the burden of having to store the previously written value to the FCR in
6312  *
6313  * memory and having to mask this value so that only the FIFO enable bit gets
6314  * updated.
6315  *
6316  * This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. If this
6317  *
6318  * bit is set to zero (disabled) after being enabled then both the XMIT and RCVR
6319  *
6320  * controller portion of FIFO's will be reset.
6321  *
6322  * Field Enumeration Values:
6323  *
6324  * Enum | Value | Description
6325  * :----------------------------|:------|:-------------------
6326  * ALT_UART_SFE_SFE_E_DISABLED | 0x0 | FIFOs are disabled
6327  * ALT_UART_SFE_SFE_E_ENABLED | 0x1 | FIFOs are enabled
6328  *
6329  * Field Access Macros:
6330  *
6331  */
6332 /*
6333  * Enumerated value for register field ALT_UART_SFE_SFE
6334  *
6335  * FIFOs are disabled
6336  */
6337 #define ALT_UART_SFE_SFE_E_DISABLED 0x0
6338 /*
6339  * Enumerated value for register field ALT_UART_SFE_SFE
6340  *
6341  * FIFOs are enabled
6342  */
6343 #define ALT_UART_SFE_SFE_E_ENABLED 0x1
6344 
6345 /* The Least Significant Bit (LSB) position of the ALT_UART_SFE_SFE register field. */
6346 #define ALT_UART_SFE_SFE_LSB 0
6347 /* The Most Significant Bit (MSB) position of the ALT_UART_SFE_SFE register field. */
6348 #define ALT_UART_SFE_SFE_MSB 0
6349 /* The width in bits of the ALT_UART_SFE_SFE register field. */
6350 #define ALT_UART_SFE_SFE_WIDTH 1
6351 /* The mask used to set the ALT_UART_SFE_SFE register field value. */
6352 #define ALT_UART_SFE_SFE_SET_MSK 0x00000001
6353 /* The mask used to clear the ALT_UART_SFE_SFE register field value. */
6354 #define ALT_UART_SFE_SFE_CLR_MSK 0xfffffffe
6355 /* The reset value of the ALT_UART_SFE_SFE register field. */
6356 #define ALT_UART_SFE_SFE_RESET 0x0
6357 /* Extracts the ALT_UART_SFE_SFE field value from a register. */
6358 #define ALT_UART_SFE_SFE_GET(value) (((value) & 0x00000001) >> 0)
6359 /* Produces a ALT_UART_SFE_SFE register field value suitable for setting the register. */
6360 #define ALT_UART_SFE_SFE_SET(value) (((value) << 0) & 0x00000001)
6361 
6362 /*
6363  * Field : RSVD_SFE_31to1
6364  *
6365  * Reserved bits [31:1] - Read Only
6366  *
6367  * Field Access Macros:
6368  *
6369  */
6370 /* The Least Significant Bit (LSB) position of the ALT_UART_SFE_RSVD_SFE_31TO1 register field. */
6371 #define ALT_UART_SFE_RSVD_SFE_31TO1_LSB 1
6372 /* The Most Significant Bit (MSB) position of the ALT_UART_SFE_RSVD_SFE_31TO1 register field. */
6373 #define ALT_UART_SFE_RSVD_SFE_31TO1_MSB 31
6374 /* The width in bits of the ALT_UART_SFE_RSVD_SFE_31TO1 register field. */
6375 #define ALT_UART_SFE_RSVD_SFE_31TO1_WIDTH 31
6376 /* The mask used to set the ALT_UART_SFE_RSVD_SFE_31TO1 register field value. */
6377 #define ALT_UART_SFE_RSVD_SFE_31TO1_SET_MSK 0xfffffffe
6378 /* The mask used to clear the ALT_UART_SFE_RSVD_SFE_31TO1 register field value. */
6379 #define ALT_UART_SFE_RSVD_SFE_31TO1_CLR_MSK 0x00000001
6380 /* The reset value of the ALT_UART_SFE_RSVD_SFE_31TO1 register field. */
6381 #define ALT_UART_SFE_RSVD_SFE_31TO1_RESET 0x0
6382 /* Extracts the ALT_UART_SFE_RSVD_SFE_31TO1 field value from a register. */
6383 #define ALT_UART_SFE_RSVD_SFE_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
6384 /* Produces a ALT_UART_SFE_RSVD_SFE_31TO1 register field value suitable for setting the register. */
6385 #define ALT_UART_SFE_RSVD_SFE_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
6386 
6387 #ifndef __ASSEMBLY__
6388 /*
6389  * WARNING: The C register and register group struct declarations are provided for
6390  * convenience and illustrative purposes. They should, however, be used with
6391  * caution as the C language standard provides no guarantees about the alignment or
6392  * atomicity of device memory accesses. The recommended practice for coding device
6393  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6394  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6395  * alt_write_dword() functions for 64 bit registers.
6396  *
6397  * The struct declaration for register ALT_UART_SFE.
6398  */
6399 struct ALT_UART_SFE_s
6400 {
6401  volatile uint32_t sfe : 1; /* ALT_UART_SFE_SFE */
6402  const volatile uint32_t RSVD_SFE_31to1 : 31; /* ALT_UART_SFE_RSVD_SFE_31TO1 */
6403 };
6404 
6405 /* The typedef declaration for register ALT_UART_SFE. */
6406 typedef struct ALT_UART_SFE_s ALT_UART_SFE_t;
6407 #endif /* __ASSEMBLY__ */
6408 
6409 /* The reset value of the ALT_UART_SFE register. */
6410 #define ALT_UART_SFE_RESET 0x00000000
6411 /* The byte offset of the ALT_UART_SFE register from the beginning of the component. */
6412 #define ALT_UART_SFE_OFST 0x98
6413 /* The address of the ALT_UART_SFE register. */
6414 #define ALT_UART_SFE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SFE_OFST))
6415 
6416 /*
6417  * Register : Shadow RCVR Trigger - SRT
6418  *
6419  * Shadow RCVR Trigger
6420  *
6421  * Register Layout
6422  *
6423  * Bits | Access | Reset | Description
6424  * :-------|:-------|:------|:----------------------------
6425  * [1:0] | RW | 0x0 | ALT_UART_SRT_SRT
6426  * [31:2] | R | 0x0 | ALT_UART_SRT_RSVD_SRT_31TO2
6427  *
6428  */
6429 /*
6430  * Field : srt
6431  *
6432  * Shadow RCVR Trigger.
6433  *
6434  * This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used
6435  * to
6436  *
6437  * remove the burden of having to store the previously written value to the FCR in
6438  *
6439  * memory and having to mask this value so that only the RCVR trigger bit gets
6440  * updated.
6441  *
6442  * This is used to select the trigger level in the receiver FIFO at which the
6443  * Received
6444  *
6445  * Data Available Interrupt will be generated. It also determines when the
6446  * dma_rx_req_n
6447  *
6448  * signal will be asserted when DMA Mode (FCR[3]) is set to one. The following
6449  * trigger
6450  *
6451  * levels are supported:
6452  *
6453  * 00 = 1 character in the FIFO
6454  *
6455  * 01 = FIFO 1/4 full
6456  *
6457  * 10 = FIFO 1/2 full
6458  *
6459  * 11 = FIFO 2 less than full
6460  *
6461  * Field Enumeration Values:
6462  *
6463  * Enum | Value | Description
6464  * :-------------------------------------|:------|:----------------------
6465  * ALT_UART_SRT_SRT_E_FIFO_CHAR_1 | 0x0 | 1 character in FIFO
6466  * ALT_UART_SRT_SRT_E_FIFO_QUARTER_FULL | 0x1 | FIFO 1/4 full
6467  * ALT_UART_SRT_SRT_E_FIFO_HALF_FULL | 0x2 | FIFO 1/2 full
6468  * ALT_UART_SRT_SRT_E_FIFO_FULL_2 | 0x3 | FIFO 2 less than full
6469  *
6470  * Field Access Macros:
6471  *
6472  */
6473 /*
6474  * Enumerated value for register field ALT_UART_SRT_SRT
6475  *
6476  * 1 character in FIFO
6477  */
6478 #define ALT_UART_SRT_SRT_E_FIFO_CHAR_1 0x0
6479 /*
6480  * Enumerated value for register field ALT_UART_SRT_SRT
6481  *
6482  * FIFO 1/4 full
6483  */
6484 #define ALT_UART_SRT_SRT_E_FIFO_QUARTER_FULL 0x1
6485 /*
6486  * Enumerated value for register field ALT_UART_SRT_SRT
6487  *
6488  * FIFO 1/2 full
6489  */
6490 #define ALT_UART_SRT_SRT_E_FIFO_HALF_FULL 0x2
6491 /*
6492  * Enumerated value for register field ALT_UART_SRT_SRT
6493  *
6494  * FIFO 2 less than full
6495  */
6496 #define ALT_UART_SRT_SRT_E_FIFO_FULL_2 0x3
6497 
6498 /* The Least Significant Bit (LSB) position of the ALT_UART_SRT_SRT register field. */
6499 #define ALT_UART_SRT_SRT_LSB 0
6500 /* The Most Significant Bit (MSB) position of the ALT_UART_SRT_SRT register field. */
6501 #define ALT_UART_SRT_SRT_MSB 1
6502 /* The width in bits of the ALT_UART_SRT_SRT register field. */
6503 #define ALT_UART_SRT_SRT_WIDTH 2
6504 /* The mask used to set the ALT_UART_SRT_SRT register field value. */
6505 #define ALT_UART_SRT_SRT_SET_MSK 0x00000003
6506 /* The mask used to clear the ALT_UART_SRT_SRT register field value. */
6507 #define ALT_UART_SRT_SRT_CLR_MSK 0xfffffffc
6508 /* The reset value of the ALT_UART_SRT_SRT register field. */
6509 #define ALT_UART_SRT_SRT_RESET 0x0
6510 /* Extracts the ALT_UART_SRT_SRT field value from a register. */
6511 #define ALT_UART_SRT_SRT_GET(value) (((value) & 0x00000003) >> 0)
6512 /* Produces a ALT_UART_SRT_SRT register field value suitable for setting the register. */
6513 #define ALT_UART_SRT_SRT_SET(value) (((value) << 0) & 0x00000003)
6514 
6515 /*
6516  * Field : RSVD_SRT_31to2
6517  *
6518  * Reserved bits [31:2] - Read Only
6519  *
6520  * Field Access Macros:
6521  *
6522  */
6523 /* The Least Significant Bit (LSB) position of the ALT_UART_SRT_RSVD_SRT_31TO2 register field. */
6524 #define ALT_UART_SRT_RSVD_SRT_31TO2_LSB 2
6525 /* The Most Significant Bit (MSB) position of the ALT_UART_SRT_RSVD_SRT_31TO2 register field. */
6526 #define ALT_UART_SRT_RSVD_SRT_31TO2_MSB 31
6527 /* The width in bits of the ALT_UART_SRT_RSVD_SRT_31TO2 register field. */
6528 #define ALT_UART_SRT_RSVD_SRT_31TO2_WIDTH 30
6529 /* The mask used to set the ALT_UART_SRT_RSVD_SRT_31TO2 register field value. */
6530 #define ALT_UART_SRT_RSVD_SRT_31TO2_SET_MSK 0xfffffffc
6531 /* The mask used to clear the ALT_UART_SRT_RSVD_SRT_31TO2 register field value. */
6532 #define ALT_UART_SRT_RSVD_SRT_31TO2_CLR_MSK 0x00000003
6533 /* The reset value of the ALT_UART_SRT_RSVD_SRT_31TO2 register field. */
6534 #define ALT_UART_SRT_RSVD_SRT_31TO2_RESET 0x0
6535 /* Extracts the ALT_UART_SRT_RSVD_SRT_31TO2 field value from a register. */
6536 #define ALT_UART_SRT_RSVD_SRT_31TO2_GET(value) (((value) & 0xfffffffc) >> 2)
6537 /* Produces a ALT_UART_SRT_RSVD_SRT_31TO2 register field value suitable for setting the register. */
6538 #define ALT_UART_SRT_RSVD_SRT_31TO2_SET(value) (((value) << 2) & 0xfffffffc)
6539 
6540 #ifndef __ASSEMBLY__
6541 /*
6542  * WARNING: The C register and register group struct declarations are provided for
6543  * convenience and illustrative purposes. They should, however, be used with
6544  * caution as the C language standard provides no guarantees about the alignment or
6545  * atomicity of device memory accesses. The recommended practice for coding device
6546  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6547  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6548  * alt_write_dword() functions for 64 bit registers.
6549  *
6550  * The struct declaration for register ALT_UART_SRT.
6551  */
6552 struct ALT_UART_SRT_s
6553 {
6554  volatile uint32_t srt : 2; /* ALT_UART_SRT_SRT */
6555  const volatile uint32_t RSVD_SRT_31to2 : 30; /* ALT_UART_SRT_RSVD_SRT_31TO2 */
6556 };
6557 
6558 /* The typedef declaration for register ALT_UART_SRT. */
6559 typedef struct ALT_UART_SRT_s ALT_UART_SRT_t;
6560 #endif /* __ASSEMBLY__ */
6561 
6562 /* The reset value of the ALT_UART_SRT register. */
6563 #define ALT_UART_SRT_RESET 0x00000000
6564 /* The byte offset of the ALT_UART_SRT register from the beginning of the component. */
6565 #define ALT_UART_SRT_OFST 0x9c
6566 /* The address of the ALT_UART_SRT register. */
6567 #define ALT_UART_SRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRT_OFST))
6568 
6569 /*
6570  * Register : Shadow TX Empty Trigger - STET
6571  *
6572  * Shadow TX Empty Trigger
6573  *
6574  * Register Layout
6575  *
6576  * Bits | Access | Reset | Description
6577  * :-------|:-------|:------|:------------------------------
6578  * [1:0] | RW | 0x0 | ALT_UART_STET_STET
6579  * [31:2] | R | 0x0 | ALT_UART_STET_RSVD_STET_31TO2
6580  *
6581  */
6582 /*
6583  * Field : stet
6584  *
6585  * Shadow TX Empty Trigger.
6586  *
6587  * This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be
6588  * used
6589  *
6590  * to remove the burden of having to store the previously written value to the FCR
6591  * in
6592  *
6593  * memory and having to mask this value so that only the TX empty trigger bit gets
6594  * updated.
6595  *
6596  * Writes will have no effect when THRE_MODE_USER == Disabled. This is used to
6597  * select the
6598  *
6599  * empty threshold level at which the THRE Interrupts will be generated when the
6600  * mode is
6601  *
6602  * active. These threshold levels are also described in. The following trigger
6603  * levels are
6604  *
6605  * supported:
6606  *
6607  * 00 = FIFO empty
6608  *
6609  * 01 = 2 characters in the FIFO
6610  *
6611  * 10 = FIFO 1/4 full
6612  *
6613  * 11 = FIFO 1/2 full
6614  *
6615  * Field Enumeration Values:
6616  *
6617  * Enum | Value | Description
6618  * :---------------------------------------|:------|:---------------------
6619  * ALT_UART_STET_STET_E_FIFO_EMPTY | 0x0 | FIFO empty
6620  * ALT_UART_STET_STET_E_FIFO_CHAR_2 | 0x1 | 2 characters in FIFO
6621  * ALT_UART_STET_STET_E_FIFO_QUARTER_FULL | 0x2 | FIFO 1/4 full
6622  * ALT_UART_STET_STET_E_FIFO_HALF_FULL | 0x3 | FIFO 1/2 full
6623  *
6624  * Field Access Macros:
6625  *
6626  */
6627 /*
6628  * Enumerated value for register field ALT_UART_STET_STET
6629  *
6630  * FIFO empty
6631  */
6632 #define ALT_UART_STET_STET_E_FIFO_EMPTY 0x0
6633 /*
6634  * Enumerated value for register field ALT_UART_STET_STET
6635  *
6636  * 2 characters in FIFO
6637  */
6638 #define ALT_UART_STET_STET_E_FIFO_CHAR_2 0x1
6639 /*
6640  * Enumerated value for register field ALT_UART_STET_STET
6641  *
6642  * FIFO 1/4 full
6643  */
6644 #define ALT_UART_STET_STET_E_FIFO_QUARTER_FULL 0x2
6645 /*
6646  * Enumerated value for register field ALT_UART_STET_STET
6647  *
6648  * FIFO 1/2 full
6649  */
6650 #define ALT_UART_STET_STET_E_FIFO_HALF_FULL 0x3
6651 
6652 /* The Least Significant Bit (LSB) position of the ALT_UART_STET_STET register field. */
6653 #define ALT_UART_STET_STET_LSB 0
6654 /* The Most Significant Bit (MSB) position of the ALT_UART_STET_STET register field. */
6655 #define ALT_UART_STET_STET_MSB 1
6656 /* The width in bits of the ALT_UART_STET_STET register field. */
6657 #define ALT_UART_STET_STET_WIDTH 2
6658 /* The mask used to set the ALT_UART_STET_STET register field value. */
6659 #define ALT_UART_STET_STET_SET_MSK 0x00000003
6660 /* The mask used to clear the ALT_UART_STET_STET register field value. */
6661 #define ALT_UART_STET_STET_CLR_MSK 0xfffffffc
6662 /* The reset value of the ALT_UART_STET_STET register field. */
6663 #define ALT_UART_STET_STET_RESET 0x0
6664 /* Extracts the ALT_UART_STET_STET field value from a register. */
6665 #define ALT_UART_STET_STET_GET(value) (((value) & 0x00000003) >> 0)
6666 /* Produces a ALT_UART_STET_STET register field value suitable for setting the register. */
6667 #define ALT_UART_STET_STET_SET(value) (((value) << 0) & 0x00000003)
6668 
6669 /*
6670  * Field : RSVD_STET_31to2
6671  *
6672  * Reserved bits [31:2] - Read Only
6673  *
6674  * Field Access Macros:
6675  *
6676  */
6677 /* The Least Significant Bit (LSB) position of the ALT_UART_STET_RSVD_STET_31TO2 register field. */
6678 #define ALT_UART_STET_RSVD_STET_31TO2_LSB 2
6679 /* The Most Significant Bit (MSB) position of the ALT_UART_STET_RSVD_STET_31TO2 register field. */
6680 #define ALT_UART_STET_RSVD_STET_31TO2_MSB 31
6681 /* The width in bits of the ALT_UART_STET_RSVD_STET_31TO2 register field. */
6682 #define ALT_UART_STET_RSVD_STET_31TO2_WIDTH 30
6683 /* The mask used to set the ALT_UART_STET_RSVD_STET_31TO2 register field value. */
6684 #define ALT_UART_STET_RSVD_STET_31TO2_SET_MSK 0xfffffffc
6685 /* The mask used to clear the ALT_UART_STET_RSVD_STET_31TO2 register field value. */
6686 #define ALT_UART_STET_RSVD_STET_31TO2_CLR_MSK 0x00000003
6687 /* The reset value of the ALT_UART_STET_RSVD_STET_31TO2 register field. */
6688 #define ALT_UART_STET_RSVD_STET_31TO2_RESET 0x0
6689 /* Extracts the ALT_UART_STET_RSVD_STET_31TO2 field value from a register. */
6690 #define ALT_UART_STET_RSVD_STET_31TO2_GET(value) (((value) & 0xfffffffc) >> 2)
6691 /* Produces a ALT_UART_STET_RSVD_STET_31TO2 register field value suitable for setting the register. */
6692 #define ALT_UART_STET_RSVD_STET_31TO2_SET(value) (((value) << 2) & 0xfffffffc)
6693 
6694 #ifndef __ASSEMBLY__
6695 /*
6696  * WARNING: The C register and register group struct declarations are provided for
6697  * convenience and illustrative purposes. They should, however, be used with
6698  * caution as the C language standard provides no guarantees about the alignment or
6699  * atomicity of device memory accesses. The recommended practice for coding device
6700  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6701  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6702  * alt_write_dword() functions for 64 bit registers.
6703  *
6704  * The struct declaration for register ALT_UART_STET.
6705  */
6706 struct ALT_UART_STET_s
6707 {
6708  volatile uint32_t stet : 2; /* ALT_UART_STET_STET */
6709  const volatile uint32_t RSVD_STET_31to2 : 30; /* ALT_UART_STET_RSVD_STET_31TO2 */
6710 };
6711 
6712 /* The typedef declaration for register ALT_UART_STET. */
6713 typedef struct ALT_UART_STET_s ALT_UART_STET_t;
6714 #endif /* __ASSEMBLY__ */
6715 
6716 /* The reset value of the ALT_UART_STET register. */
6717 #define ALT_UART_STET_RESET 0x00000000
6718 /* The byte offset of the ALT_UART_STET register from the beginning of the component. */
6719 #define ALT_UART_STET_OFST 0xa0
6720 /* The address of the ALT_UART_STET register. */
6721 #define ALT_UART_STET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STET_OFST))
6722 
6723 /*
6724  * Register : Halt TX - HTX
6725  *
6726  * Halt TX
6727  *
6728  * Register Layout
6729  *
6730  * Bits | Access | Reset | Description
6731  * :-------|:-------|:------|:----------------------------
6732  * [0] | RW | 0x0 | ALT_UART_HTX_HTX
6733  * [31:1] | R | 0x0 | ALT_UART_HTX_RSVD_HTX_31TO1
6734  *
6735  */
6736 /*
6737  * Field : htx
6738  *
6739  * Halt TX.
6740  *
6741  * Writes will have no effect when FIFO_MODE == NONE, always readable. This
6742  * register
6743  *
6744  * is use to halt transmissions for testing, so that the transmit FIFO can be
6745  * filled
6746  *
6747  * by the master when FIFO's are implemented and enabled.
6748  *
6749  * Note, if FIFO's are implemented and not enabled the setting of the halt TX
6750  * register
6751  *
6752  * will have no effect on operation.
6753  *
6754  * 0 = Halt TX disabled
6755  *
6756  * 1 = Halt TX enabled
6757  *
6758  * Field Enumeration Values:
6759  *
6760  * Enum | Value | Description
6761  * :----------------------------|:------|:---------------------------
6762  * ALT_UART_HTX_HTX_E_DISABLED | 0x0 | Halt Transmission disabled
6763  * ALT_UART_HTX_HTX_E_ENABLED | 0x1 | Halt Transmission enabled
6764  *
6765  * Field Access Macros:
6766  *
6767  */
6768 /*
6769  * Enumerated value for register field ALT_UART_HTX_HTX
6770  *
6771  * Halt Transmission disabled
6772  */
6773 #define ALT_UART_HTX_HTX_E_DISABLED 0x0
6774 /*
6775  * Enumerated value for register field ALT_UART_HTX_HTX
6776  *
6777  * Halt Transmission enabled
6778  */
6779 #define ALT_UART_HTX_HTX_E_ENABLED 0x1
6780 
6781 /* The Least Significant Bit (LSB) position of the ALT_UART_HTX_HTX register field. */
6782 #define ALT_UART_HTX_HTX_LSB 0
6783 /* The Most Significant Bit (MSB) position of the ALT_UART_HTX_HTX register field. */
6784 #define ALT_UART_HTX_HTX_MSB 0
6785 /* The width in bits of the ALT_UART_HTX_HTX register field. */
6786 #define ALT_UART_HTX_HTX_WIDTH 1
6787 /* The mask used to set the ALT_UART_HTX_HTX register field value. */
6788 #define ALT_UART_HTX_HTX_SET_MSK 0x00000001
6789 /* The mask used to clear the ALT_UART_HTX_HTX register field value. */
6790 #define ALT_UART_HTX_HTX_CLR_MSK 0xfffffffe
6791 /* The reset value of the ALT_UART_HTX_HTX register field. */
6792 #define ALT_UART_HTX_HTX_RESET 0x0
6793 /* Extracts the ALT_UART_HTX_HTX field value from a register. */
6794 #define ALT_UART_HTX_HTX_GET(value) (((value) & 0x00000001) >> 0)
6795 /* Produces a ALT_UART_HTX_HTX register field value suitable for setting the register. */
6796 #define ALT_UART_HTX_HTX_SET(value) (((value) << 0) & 0x00000001)
6797 
6798 /*
6799  * Field : RSVD_HTX_31to1
6800  *
6801  * Reserved bits [31:1] - Read Only
6802  *
6803  * Field Access Macros:
6804  *
6805  */
6806 /* The Least Significant Bit (LSB) position of the ALT_UART_HTX_RSVD_HTX_31TO1 register field. */
6807 #define ALT_UART_HTX_RSVD_HTX_31TO1_LSB 1
6808 /* The Most Significant Bit (MSB) position of the ALT_UART_HTX_RSVD_HTX_31TO1 register field. */
6809 #define ALT_UART_HTX_RSVD_HTX_31TO1_MSB 31
6810 /* The width in bits of the ALT_UART_HTX_RSVD_HTX_31TO1 register field. */
6811 #define ALT_UART_HTX_RSVD_HTX_31TO1_WIDTH 31
6812 /* The mask used to set the ALT_UART_HTX_RSVD_HTX_31TO1 register field value. */
6813 #define ALT_UART_HTX_RSVD_HTX_31TO1_SET_MSK 0xfffffffe
6814 /* The mask used to clear the ALT_UART_HTX_RSVD_HTX_31TO1 register field value. */
6815 #define ALT_UART_HTX_RSVD_HTX_31TO1_CLR_MSK 0x00000001
6816 /* The reset value of the ALT_UART_HTX_RSVD_HTX_31TO1 register field. */
6817 #define ALT_UART_HTX_RSVD_HTX_31TO1_RESET 0x0
6818 /* Extracts the ALT_UART_HTX_RSVD_HTX_31TO1 field value from a register. */
6819 #define ALT_UART_HTX_RSVD_HTX_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
6820 /* Produces a ALT_UART_HTX_RSVD_HTX_31TO1 register field value suitable for setting the register. */
6821 #define ALT_UART_HTX_RSVD_HTX_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
6822 
6823 #ifndef __ASSEMBLY__
6824 /*
6825  * WARNING: The C register and register group struct declarations are provided for
6826  * convenience and illustrative purposes. They should, however, be used with
6827  * caution as the C language standard provides no guarantees about the alignment or
6828  * atomicity of device memory accesses. The recommended practice for coding device
6829  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6830  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6831  * alt_write_dword() functions for 64 bit registers.
6832  *
6833  * The struct declaration for register ALT_UART_HTX.
6834  */
6835 struct ALT_UART_HTX_s
6836 {
6837  volatile uint32_t htx : 1; /* ALT_UART_HTX_HTX */
6838  const volatile uint32_t RSVD_HTX_31to1 : 31; /* ALT_UART_HTX_RSVD_HTX_31TO1 */
6839 };
6840 
6841 /* The typedef declaration for register ALT_UART_HTX. */
6842 typedef struct ALT_UART_HTX_s ALT_UART_HTX_t;
6843 #endif /* __ASSEMBLY__ */
6844 
6845 /* The reset value of the ALT_UART_HTX register. */
6846 #define ALT_UART_HTX_RESET 0x00000000
6847 /* The byte offset of the ALT_UART_HTX register from the beginning of the component. */
6848 #define ALT_UART_HTX_OFST 0xa4
6849 /* The address of the ALT_UART_HTX register. */
6850 #define ALT_UART_HTX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_HTX_OFST))
6851 
6852 /*
6853  * Register : DMA Software Acknowledge - DMASA
6854  *
6855  * DMA Software Acknowledge
6856  *
6857  * Register Layout
6858  *
6859  * Bits | Access | Reset | Description
6860  * :-------|:-------|:------|:--------------------------------
6861  * [0] | W | 0x0 | ALT_UART_DMASA_DMASA
6862  * [31:1] | R | 0x0 | ALT_UART_DMASA_RSVD_DMASA_31TO1
6863  *
6864  */
6865 /*
6866  * Field : dmasa
6867  *
6868  * DMA Software Acknowledge.
6869  *
6870  * Writes will have no effect when DMA_EXTRA == No. This register is use to
6871  * perform
6872  *
6873  * DMA software acknowledge if a transfer needs to be terminated due to an error
6874  *
6875  * condition. For example, if the DMA disables the channel, then the DW_apb_uart
6876  * should
6877  *
6878  * clear its request. This will cause the TX request, TX single, RX request and RX
6879  *
6880  * single signals to de-assert.
6881  *
6882  * Note that this bit is 'self-clearing' and it is not necessary to clear this bit.
6883  *
6884  * Field Enumeration Values:
6885  *
6886  * Enum | Value | Description
6887  * :--------------------------------|:------|:-------------------------
6888  * ALT_UART_DMASA_DMASA_E_SOFT_ACK | 0x1 | DMA software acknowledge
6889  *
6890  * Field Access Macros:
6891  *
6892  */
6893 /*
6894  * Enumerated value for register field ALT_UART_DMASA_DMASA
6895  *
6896  * DMA software acknowledge
6897  */
6898 #define ALT_UART_DMASA_DMASA_E_SOFT_ACK 0x1
6899 
6900 /* The Least Significant Bit (LSB) position of the ALT_UART_DMASA_DMASA register field. */
6901 #define ALT_UART_DMASA_DMASA_LSB 0
6902 /* The Most Significant Bit (MSB) position of the ALT_UART_DMASA_DMASA register field. */
6903 #define ALT_UART_DMASA_DMASA_MSB 0
6904 /* The width in bits of the ALT_UART_DMASA_DMASA register field. */
6905 #define ALT_UART_DMASA_DMASA_WIDTH 1
6906 /* The mask used to set the ALT_UART_DMASA_DMASA register field value. */
6907 #define ALT_UART_DMASA_DMASA_SET_MSK 0x00000001
6908 /* The mask used to clear the ALT_UART_DMASA_DMASA register field value. */
6909 #define ALT_UART_DMASA_DMASA_CLR_MSK 0xfffffffe
6910 /* The reset value of the ALT_UART_DMASA_DMASA register field. */
6911 #define ALT_UART_DMASA_DMASA_RESET 0x0
6912 /* Extracts the ALT_UART_DMASA_DMASA field value from a register. */
6913 #define ALT_UART_DMASA_DMASA_GET(value) (((value) & 0x00000001) >> 0)
6914 /* Produces a ALT_UART_DMASA_DMASA register field value suitable for setting the register. */
6915 #define ALT_UART_DMASA_DMASA_SET(value) (((value) << 0) & 0x00000001)
6916 
6917 /*
6918  * Field : RSVD_DMASA_31to1
6919  *
6920  * Reserved bits [31:1] - Read Only
6921  *
6922  * Field Access Macros:
6923  *
6924  */
6925 /* The Least Significant Bit (LSB) position of the ALT_UART_DMASA_RSVD_DMASA_31TO1 register field. */
6926 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_LSB 1
6927 /* The Most Significant Bit (MSB) position of the ALT_UART_DMASA_RSVD_DMASA_31TO1 register field. */
6928 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_MSB 31
6929 /* The width in bits of the ALT_UART_DMASA_RSVD_DMASA_31TO1 register field. */
6930 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_WIDTH 31
6931 /* The mask used to set the ALT_UART_DMASA_RSVD_DMASA_31TO1 register field value. */
6932 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_SET_MSK 0xfffffffe
6933 /* The mask used to clear the ALT_UART_DMASA_RSVD_DMASA_31TO1 register field value. */
6934 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_CLR_MSK 0x00000001
6935 /* The reset value of the ALT_UART_DMASA_RSVD_DMASA_31TO1 register field. */
6936 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_RESET 0x0
6937 /* Extracts the ALT_UART_DMASA_RSVD_DMASA_31TO1 field value from a register. */
6938 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
6939 /* Produces a ALT_UART_DMASA_RSVD_DMASA_31TO1 register field value suitable for setting the register. */
6940 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
6941 
6942 #ifndef __ASSEMBLY__
6943 /*
6944  * WARNING: The C register and register group struct declarations are provided for
6945  * convenience and illustrative purposes. They should, however, be used with
6946  * caution as the C language standard provides no guarantees about the alignment or
6947  * atomicity of device memory accesses. The recommended practice for coding device
6948  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6949  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6950  * alt_write_dword() functions for 64 bit registers.
6951  *
6952  * The struct declaration for register ALT_UART_DMASA.
6953  */
6954 struct ALT_UART_DMASA_s
6955 {
6956  volatile uint32_t dmasa : 1; /* ALT_UART_DMASA_DMASA */
6957  const volatile uint32_t RSVD_DMASA_31to1 : 31; /* ALT_UART_DMASA_RSVD_DMASA_31TO1 */
6958 };
6959 
6960 /* The typedef declaration for register ALT_UART_DMASA. */
6961 typedef struct ALT_UART_DMASA_s ALT_UART_DMASA_t;
6962 #endif /* __ASSEMBLY__ */
6963 
6964 /* The reset value of the ALT_UART_DMASA register. */
6965 #define ALT_UART_DMASA_RESET 0x00000000
6966 /* The byte offset of the ALT_UART_DMASA register from the beginning of the component. */
6967 #define ALT_UART_DMASA_OFST 0xa8
6968 /* The address of the ALT_UART_DMASA register. */
6969 #define ALT_UART_DMASA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_DMASA_OFST))
6970 
6971 /*
6972  * Register : Component Parameter Register - CPR
6973  *
6974  * Component Parameter Register
6975  *
6976  * Register Layout
6977  *
6978  * Bits | Access | Reset | Description
6979  * :--------|:-------|:------|:-------------------------------------
6980  * [1:0] | R | 0x2 | ALT_UART_CPR_APB_DATA_WIDTH
6981  * [3:2] | R | 0x0 | ALT_UART_CPR_RSVD_CPR_3TO2
6982  * [4] | R | 0x1 | ALT_UART_CPR_AFCE_MODE
6983  * [5] | R | 0x1 | ALT_UART_CPR_THRE_MODE
6984  * [6] | R | 0x0 | ALT_UART_CPR_SIR_MODE
6985  * [7] | R | 0x0 | ALT_UART_CPR_SIR_LP_MODE
6986  * [8] | R | 0x1 | ALT_UART_CPR_ADDITIONAL_FEAT
6987  * [9] | R | 0x1 | ALT_UART_CPR_FIFO_ACCESS
6988  * [10] | R | 0x1 | ALT_UART_CPR_FIFO_STAT
6989  * [11] | R | 0x1 | ALT_UART_CPR_SHADOW
6990  * [12] | R | 0x1 | ALT_UART_CPR_UART_ADD_ENCODED_PARAMS
6991  * [13] | R | 0x1 | ALT_UART_CPR_DMA_EXTRA
6992  * [15:14] | R | 0x0 | ALT_UART_CPR_RSVD_CPR_15TO14
6993  * [23:16] | R | 0x8 | ALT_UART_CPR_FIFO_MODE
6994  * [31:24] | R | 0x0 | ALT_UART_CPR_RSVD_CPR_31TO24
6995  *
6996  */
6997 /*
6998  * Field : APB_DATA_WIDTH
6999  *
7000  * Encoding of APB_DATA_WIDTH configuration parameter value.
7001  *
7002  * 00 = 8 bits,
7003  *
7004  * 01 = 16 bits,
7005  *
7006  * 10 = 32 bits,
7007  *
7008  * 11 = reserved
7009  *
7010  * Field Enumeration Values:
7011  *
7012  * Enum | Value | Description
7013  * :-----------------------------------------|:------|:--------------------------
7014  * ALT_UART_CPR_APB_DATA_WIDTH_E_APB_8BITS | 0x0 | APB data width is 8 bits
7015  * ALT_UART_CPR_APB_DATA_WIDTH_E_APB_16BITS | 0x1 | APB data width is 16 bits
7016  * ALT_UART_CPR_APB_DATA_WIDTH_E_APB_32BITS | 0x2 | APB data width is 32 bits
7017  *
7018  * Field Access Macros:
7019  *
7020  */
7021 /*
7022  * Enumerated value for register field ALT_UART_CPR_APB_DATA_WIDTH
7023  *
7024  * APB data width is 8 bits
7025  */
7026 #define ALT_UART_CPR_APB_DATA_WIDTH_E_APB_8BITS 0x0
7027 /*
7028  * Enumerated value for register field ALT_UART_CPR_APB_DATA_WIDTH
7029  *
7030  * APB data width is 16 bits
7031  */
7032 #define ALT_UART_CPR_APB_DATA_WIDTH_E_APB_16BITS 0x1
7033 /*
7034  * Enumerated value for register field ALT_UART_CPR_APB_DATA_WIDTH
7035  *
7036  * APB data width is 32 bits
7037  */
7038 #define ALT_UART_CPR_APB_DATA_WIDTH_E_APB_32BITS 0x2
7039 
7040 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_APB_DATA_WIDTH register field. */
7041 #define ALT_UART_CPR_APB_DATA_WIDTH_LSB 0
7042 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_APB_DATA_WIDTH register field. */
7043 #define ALT_UART_CPR_APB_DATA_WIDTH_MSB 1
7044 /* The width in bits of the ALT_UART_CPR_APB_DATA_WIDTH register field. */
7045 #define ALT_UART_CPR_APB_DATA_WIDTH_WIDTH 2
7046 /* The mask used to set the ALT_UART_CPR_APB_DATA_WIDTH register field value. */
7047 #define ALT_UART_CPR_APB_DATA_WIDTH_SET_MSK 0x00000003
7048 /* The mask used to clear the ALT_UART_CPR_APB_DATA_WIDTH register field value. */
7049 #define ALT_UART_CPR_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
7050 /* The reset value of the ALT_UART_CPR_APB_DATA_WIDTH register field. */
7051 #define ALT_UART_CPR_APB_DATA_WIDTH_RESET 0x2
7052 /* Extracts the ALT_UART_CPR_APB_DATA_WIDTH field value from a register. */
7053 #define ALT_UART_CPR_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
7054 /* Produces a ALT_UART_CPR_APB_DATA_WIDTH register field value suitable for setting the register. */
7055 #define ALT_UART_CPR_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
7056 
7057 /*
7058  * Field : RSVD_CPR_3to2
7059  *
7060  * Reserved bits [3:2] - Read Only
7061  *
7062  * Field Access Macros:
7063  *
7064  */
7065 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_RSVD_CPR_3TO2 register field. */
7066 #define ALT_UART_CPR_RSVD_CPR_3TO2_LSB 2
7067 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_RSVD_CPR_3TO2 register field. */
7068 #define ALT_UART_CPR_RSVD_CPR_3TO2_MSB 3
7069 /* The width in bits of the ALT_UART_CPR_RSVD_CPR_3TO2 register field. */
7070 #define ALT_UART_CPR_RSVD_CPR_3TO2_WIDTH 2
7071 /* The mask used to set the ALT_UART_CPR_RSVD_CPR_3TO2 register field value. */
7072 #define ALT_UART_CPR_RSVD_CPR_3TO2_SET_MSK 0x0000000c
7073 /* The mask used to clear the ALT_UART_CPR_RSVD_CPR_3TO2 register field value. */
7074 #define ALT_UART_CPR_RSVD_CPR_3TO2_CLR_MSK 0xfffffff3
7075 /* The reset value of the ALT_UART_CPR_RSVD_CPR_3TO2 register field. */
7076 #define ALT_UART_CPR_RSVD_CPR_3TO2_RESET 0x0
7077 /* Extracts the ALT_UART_CPR_RSVD_CPR_3TO2 field value from a register. */
7078 #define ALT_UART_CPR_RSVD_CPR_3TO2_GET(value) (((value) & 0x0000000c) >> 2)
7079 /* Produces a ALT_UART_CPR_RSVD_CPR_3TO2 register field value suitable for setting the register. */
7080 #define ALT_UART_CPR_RSVD_CPR_3TO2_SET(value) (((value) << 2) & 0x0000000c)
7081 
7082 /*
7083  * Field : AFCE_MODE
7084  *
7085  * Encoding of AFCE_MODE configuration parameter value.
7086  *
7087  * 0 = FALSE,
7088  *
7089  * 1 = TRUE
7090  *
7091  * Field Enumeration Values:
7092  *
7093  * Enum | Value | Description
7094  * :----------------------------------|:------|:-------------------
7095  * ALT_UART_CPR_AFCE_MODE_E_DISABLED | 0x0 | AFCE mode disabled
7096  * ALT_UART_CPR_AFCE_MODE_E_ENABLED | 0x1 | AFCE mode enabled
7097  *
7098  * Field Access Macros:
7099  *
7100  */
7101 /*
7102  * Enumerated value for register field ALT_UART_CPR_AFCE_MODE
7103  *
7104  * AFCE mode disabled
7105  */
7106 #define ALT_UART_CPR_AFCE_MODE_E_DISABLED 0x0
7107 /*
7108  * Enumerated value for register field ALT_UART_CPR_AFCE_MODE
7109  *
7110  * AFCE mode enabled
7111  */
7112 #define ALT_UART_CPR_AFCE_MODE_E_ENABLED 0x1
7113 
7114 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_AFCE_MODE register field. */
7115 #define ALT_UART_CPR_AFCE_MODE_LSB 4
7116 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_AFCE_MODE register field. */
7117 #define ALT_UART_CPR_AFCE_MODE_MSB 4
7118 /* The width in bits of the ALT_UART_CPR_AFCE_MODE register field. */
7119 #define ALT_UART_CPR_AFCE_MODE_WIDTH 1
7120 /* The mask used to set the ALT_UART_CPR_AFCE_MODE register field value. */
7121 #define ALT_UART_CPR_AFCE_MODE_SET_MSK 0x00000010
7122 /* The mask used to clear the ALT_UART_CPR_AFCE_MODE register field value. */
7123 #define ALT_UART_CPR_AFCE_MODE_CLR_MSK 0xffffffef
7124 /* The reset value of the ALT_UART_CPR_AFCE_MODE register field. */
7125 #define ALT_UART_CPR_AFCE_MODE_RESET 0x1
7126 /* Extracts the ALT_UART_CPR_AFCE_MODE field value from a register. */
7127 #define ALT_UART_CPR_AFCE_MODE_GET(value) (((value) & 0x00000010) >> 4)
7128 /* Produces a ALT_UART_CPR_AFCE_MODE register field value suitable for setting the register. */
7129 #define ALT_UART_CPR_AFCE_MODE_SET(value) (((value) << 4) & 0x00000010)
7130 
7131 /*
7132  * Field : THRE_MODE
7133  *
7134  * Encoding of THRE_MODE configuration parameter value.
7135  *
7136  * 0 = FALSE,
7137  *
7138  * 1 = TRUE
7139  *
7140  * Field Enumeration Values:
7141  *
7142  * Enum | Value | Description
7143  * :----------------------------------|:------|:-------------------
7144  * ALT_UART_CPR_THRE_MODE_E_DISABLED | 0x0 | THRE mode disabled
7145  * ALT_UART_CPR_THRE_MODE_E_ENABLED | 0x1 | THRE mode enabled
7146  *
7147  * Field Access Macros:
7148  *
7149  */
7150 /*
7151  * Enumerated value for register field ALT_UART_CPR_THRE_MODE
7152  *
7153  * THRE mode disabled
7154  */
7155 #define ALT_UART_CPR_THRE_MODE_E_DISABLED 0x0
7156 /*
7157  * Enumerated value for register field ALT_UART_CPR_THRE_MODE
7158  *
7159  * THRE mode enabled
7160  */
7161 #define ALT_UART_CPR_THRE_MODE_E_ENABLED 0x1
7162 
7163 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_THRE_MODE register field. */
7164 #define ALT_UART_CPR_THRE_MODE_LSB 5
7165 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_THRE_MODE register field. */
7166 #define ALT_UART_CPR_THRE_MODE_MSB 5
7167 /* The width in bits of the ALT_UART_CPR_THRE_MODE register field. */
7168 #define ALT_UART_CPR_THRE_MODE_WIDTH 1
7169 /* The mask used to set the ALT_UART_CPR_THRE_MODE register field value. */
7170 #define ALT_UART_CPR_THRE_MODE_SET_MSK 0x00000020
7171 /* The mask used to clear the ALT_UART_CPR_THRE_MODE register field value. */
7172 #define ALT_UART_CPR_THRE_MODE_CLR_MSK 0xffffffdf
7173 /* The reset value of the ALT_UART_CPR_THRE_MODE register field. */
7174 #define ALT_UART_CPR_THRE_MODE_RESET 0x1
7175 /* Extracts the ALT_UART_CPR_THRE_MODE field value from a register. */
7176 #define ALT_UART_CPR_THRE_MODE_GET(value) (((value) & 0x00000020) >> 5)
7177 /* Produces a ALT_UART_CPR_THRE_MODE register field value suitable for setting the register. */
7178 #define ALT_UART_CPR_THRE_MODE_SET(value) (((value) << 5) & 0x00000020)
7179 
7180 /*
7181  * Field : SIR_MODE
7182  *
7183  * Encoding of SIR_MODE configuration parameter value.
7184  *
7185  * 0 = FALSE,
7186  *
7187  * 1 = TRUE
7188  *
7189  * Field Enumeration Values:
7190  *
7191  * Enum | Value | Description
7192  * :---------------------------------|:------|:------------------
7193  * ALT_UART_CPR_SIR_MODE_E_DISABLED | 0x0 | SIR mode disabled
7194  * ALT_UART_CPR_SIR_MODE_E_ENABLED | 0x1 | SIR mode enabled
7195  *
7196  * Field Access Macros:
7197  *
7198  */
7199 /*
7200  * Enumerated value for register field ALT_UART_CPR_SIR_MODE
7201  *
7202  * SIR mode disabled
7203  */
7204 #define ALT_UART_CPR_SIR_MODE_E_DISABLED 0x0
7205 /*
7206  * Enumerated value for register field ALT_UART_CPR_SIR_MODE
7207  *
7208  * SIR mode enabled
7209  */
7210 #define ALT_UART_CPR_SIR_MODE_E_ENABLED 0x1
7211 
7212 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_MODE register field. */
7213 #define ALT_UART_CPR_SIR_MODE_LSB 6
7214 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_MODE register field. */
7215 #define ALT_UART_CPR_SIR_MODE_MSB 6
7216 /* The width in bits of the ALT_UART_CPR_SIR_MODE register field. */
7217 #define ALT_UART_CPR_SIR_MODE_WIDTH 1
7218 /* The mask used to set the ALT_UART_CPR_SIR_MODE register field value. */
7219 #define ALT_UART_CPR_SIR_MODE_SET_MSK 0x00000040
7220 /* The mask used to clear the ALT_UART_CPR_SIR_MODE register field value. */
7221 #define ALT_UART_CPR_SIR_MODE_CLR_MSK 0xffffffbf
7222 /* The reset value of the ALT_UART_CPR_SIR_MODE register field. */
7223 #define ALT_UART_CPR_SIR_MODE_RESET 0x0
7224 /* Extracts the ALT_UART_CPR_SIR_MODE field value from a register. */
7225 #define ALT_UART_CPR_SIR_MODE_GET(value) (((value) & 0x00000040) >> 6)
7226 /* Produces a ALT_UART_CPR_SIR_MODE register field value suitable for setting the register. */
7227 #define ALT_UART_CPR_SIR_MODE_SET(value) (((value) << 6) & 0x00000040)
7228 
7229 /*
7230  * Field : SIR_LP_MODE
7231  *
7232  * Encoding of SIR_LP_MODE configuration parameter value.
7233  *
7234  * 0 = FALSE,
7235  *
7236  * 1 = TRUE
7237  *
7238  * Field Enumeration Values:
7239  *
7240  * Enum | Value | Description
7241  * :------------------------------------|:------|:---------------------
7242  * ALT_UART_CPR_SIR_LP_MODE_E_DISABLED | 0x0 | SIR_LP mode disabled
7243  * ALT_UART_CPR_SIR_LP_MODE_E_ENABLED | 0x1 | SIR_LP mode enabled
7244  *
7245  * Field Access Macros:
7246  *
7247  */
7248 /*
7249  * Enumerated value for register field ALT_UART_CPR_SIR_LP_MODE
7250  *
7251  * SIR_LP mode disabled
7252  */
7253 #define ALT_UART_CPR_SIR_LP_MODE_E_DISABLED 0x0
7254 /*
7255  * Enumerated value for register field ALT_UART_CPR_SIR_LP_MODE
7256  *
7257  * SIR_LP mode enabled
7258  */
7259 #define ALT_UART_CPR_SIR_LP_MODE_E_ENABLED 0x1
7260 
7261 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_LP_MODE register field. */
7262 #define ALT_UART_CPR_SIR_LP_MODE_LSB 7
7263 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_LP_MODE register field. */
7264 #define ALT_UART_CPR_SIR_LP_MODE_MSB 7
7265 /* The width in bits of the ALT_UART_CPR_SIR_LP_MODE register field. */
7266 #define ALT_UART_CPR_SIR_LP_MODE_WIDTH 1
7267 /* The mask used to set the ALT_UART_CPR_SIR_LP_MODE register field value. */
7268 #define ALT_UART_CPR_SIR_LP_MODE_SET_MSK 0x00000080
7269 /* The mask used to clear the ALT_UART_CPR_SIR_LP_MODE register field value. */
7270 #define ALT_UART_CPR_SIR_LP_MODE_CLR_MSK 0xffffff7f
7271 /* The reset value of the ALT_UART_CPR_SIR_LP_MODE register field. */
7272 #define ALT_UART_CPR_SIR_LP_MODE_RESET 0x0
7273 /* Extracts the ALT_UART_CPR_SIR_LP_MODE field value from a register. */
7274 #define ALT_UART_CPR_SIR_LP_MODE_GET(value) (((value) & 0x00000080) >> 7)
7275 /* Produces a ALT_UART_CPR_SIR_LP_MODE register field value suitable for setting the register. */
7276 #define ALT_UART_CPR_SIR_LP_MODE_SET(value) (((value) << 7) & 0x00000080)
7277 
7278 /*
7279  * Field : ADDITIONAL_FEAT
7280  *
7281  * Encoding of ADDITIONAL_FEATURES configuration parameter value.
7282  *
7283  * 0 = FALSE,
7284  *
7285  * 1 = TRUE
7286  *
7287  * Field Enumeration Values:
7288  *
7289  * Enum | Value | Description
7290  * :----------------------------------------|:------|:-----------------------------
7291  * ALT_UART_CPR_ADDITIONAL_FEAT_E_DISABLED | 0x0 | Additional features disabled
7292  * ALT_UART_CPR_ADDITIONAL_FEAT_E_ENABLED | 0x1 | Additional features enabled
7293  *
7294  * Field Access Macros:
7295  *
7296  */
7297 /*
7298  * Enumerated value for register field ALT_UART_CPR_ADDITIONAL_FEAT
7299  *
7300  * Additional features disabled
7301  */
7302 #define ALT_UART_CPR_ADDITIONAL_FEAT_E_DISABLED 0x0
7303 /*
7304  * Enumerated value for register field ALT_UART_CPR_ADDITIONAL_FEAT
7305  *
7306  * Additional features enabled
7307  */
7308 #define ALT_UART_CPR_ADDITIONAL_FEAT_E_ENABLED 0x1
7309 
7310 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
7311 #define ALT_UART_CPR_ADDITIONAL_FEAT_LSB 8
7312 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
7313 #define ALT_UART_CPR_ADDITIONAL_FEAT_MSB 8
7314 /* The width in bits of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
7315 #define ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH 1
7316 /* The mask used to set the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */
7317 #define ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK 0x00000100
7318 /* The mask used to clear the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */
7319 #define ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK 0xfffffeff
7320 /* The reset value of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
7321 #define ALT_UART_CPR_ADDITIONAL_FEAT_RESET 0x1
7322 /* Extracts the ALT_UART_CPR_ADDITIONAL_FEAT field value from a register. */
7323 #define ALT_UART_CPR_ADDITIONAL_FEAT_GET(value) (((value) & 0x00000100) >> 8)
7324 /* Produces a ALT_UART_CPR_ADDITIONAL_FEAT register field value suitable for setting the register. */
7325 #define ALT_UART_CPR_ADDITIONAL_FEAT_SET(value) (((value) << 8) & 0x00000100)
7326 
7327 /*
7328  * Field : FIFO_ACCESS
7329  *
7330  * Encoding of FIFO_ACCESS configuration parameter value.
7331  *
7332  * 0 = FALSE,
7333  *
7334  * 1 = TRUE
7335  *
7336  * Field Enumeration Values:
7337  *
7338  * Enum | Value | Description
7339  * :------------------------------------|:------|:---------------------
7340  * ALT_UART_CPR_FIFO_ACCESS_E_DISABLED | 0x0 | FIFO_ACCESS disabled
7341  * ALT_UART_CPR_FIFO_ACCESS_E_ENABLED | 0x1 | FIFO ACCESS enabled
7342  *
7343  * Field Access Macros:
7344  *
7345  */
7346 /*
7347  * Enumerated value for register field ALT_UART_CPR_FIFO_ACCESS
7348  *
7349  * FIFO_ACCESS disabled
7350  */
7351 #define ALT_UART_CPR_FIFO_ACCESS_E_DISABLED 0x0
7352 /*
7353  * Enumerated value for register field ALT_UART_CPR_FIFO_ACCESS
7354  *
7355  * FIFO ACCESS enabled
7356  */
7357 #define ALT_UART_CPR_FIFO_ACCESS_E_ENABLED 0x1
7358 
7359 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */
7360 #define ALT_UART_CPR_FIFO_ACCESS_LSB 9
7361 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */
7362 #define ALT_UART_CPR_FIFO_ACCESS_MSB 9
7363 /* The width in bits of the ALT_UART_CPR_FIFO_ACCESS register field. */
7364 #define ALT_UART_CPR_FIFO_ACCESS_WIDTH 1
7365 /* The mask used to set the ALT_UART_CPR_FIFO_ACCESS register field value. */
7366 #define ALT_UART_CPR_FIFO_ACCESS_SET_MSK 0x00000200
7367 /* The mask used to clear the ALT_UART_CPR_FIFO_ACCESS register field value. */
7368 #define ALT_UART_CPR_FIFO_ACCESS_CLR_MSK 0xfffffdff
7369 /* The reset value of the ALT_UART_CPR_FIFO_ACCESS register field. */
7370 #define ALT_UART_CPR_FIFO_ACCESS_RESET 0x1
7371 /* Extracts the ALT_UART_CPR_FIFO_ACCESS field value from a register. */
7372 #define ALT_UART_CPR_FIFO_ACCESS_GET(value) (((value) & 0x00000200) >> 9)
7373 /* Produces a ALT_UART_CPR_FIFO_ACCESS register field value suitable for setting the register. */
7374 #define ALT_UART_CPR_FIFO_ACCESS_SET(value) (((value) << 9) & 0x00000200)
7375 
7376 /*
7377  * Field : FIFO_STAT
7378  *
7379  * Encoding of FIFO_STAT configuration parameter value.
7380  *
7381  * 0 = FALSE,
7382  *
7383  * 1 = TRUE
7384  *
7385  * Field Enumeration Values:
7386  *
7387  * Enum | Value | Description
7388  * :----------------------------------|:------|:-------------------
7389  * ALT_UART_CPR_FIFO_STAT_E_DISABLED | 0x0 | FIFO_STAT disabled
7390  * ALT_UART_CPR_FIFO_STAT_E_ENABLED | 0x1 | FIFO_STAT enabled
7391  *
7392  * Field Access Macros:
7393  *
7394  */
7395 /*
7396  * Enumerated value for register field ALT_UART_CPR_FIFO_STAT
7397  *
7398  * FIFO_STAT disabled
7399  */
7400 #define ALT_UART_CPR_FIFO_STAT_E_DISABLED 0x0
7401 /*
7402  * Enumerated value for register field ALT_UART_CPR_FIFO_STAT
7403  *
7404  * FIFO_STAT enabled
7405  */
7406 #define ALT_UART_CPR_FIFO_STAT_E_ENABLED 0x1
7407 
7408 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_STAT register field. */
7409 #define ALT_UART_CPR_FIFO_STAT_LSB 10
7410 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_STAT register field. */
7411 #define ALT_UART_CPR_FIFO_STAT_MSB 10
7412 /* The width in bits of the ALT_UART_CPR_FIFO_STAT register field. */
7413 #define ALT_UART_CPR_FIFO_STAT_WIDTH 1
7414 /* The mask used to set the ALT_UART_CPR_FIFO_STAT register field value. */
7415 #define ALT_UART_CPR_FIFO_STAT_SET_MSK 0x00000400
7416 /* The mask used to clear the ALT_UART_CPR_FIFO_STAT register field value. */
7417 #define ALT_UART_CPR_FIFO_STAT_CLR_MSK 0xfffffbff
7418 /* The reset value of the ALT_UART_CPR_FIFO_STAT register field. */
7419 #define ALT_UART_CPR_FIFO_STAT_RESET 0x1
7420 /* Extracts the ALT_UART_CPR_FIFO_STAT field value from a register. */
7421 #define ALT_UART_CPR_FIFO_STAT_GET(value) (((value) & 0x00000400) >> 10)
7422 /* Produces a ALT_UART_CPR_FIFO_STAT register field value suitable for setting the register. */
7423 #define ALT_UART_CPR_FIFO_STAT_SET(value) (((value) << 10) & 0x00000400)
7424 
7425 /*
7426  * Field : SHADOW
7427  *
7428  * Encoding of SHADOW configuration parameter value.
7429  *
7430  * 0 = FALSE,
7431  *
7432  * 1 = TRUE
7433  *
7434  * Field Enumeration Values:
7435  *
7436  * Enum | Value | Description
7437  * :-------------------------------|:------|:----------------
7438  * ALT_UART_CPR_SHADOW_E_DISABLED | 0x0 | SHADOW disabled
7439  * ALT_UART_CPR_SHADOW_E_ENABLED | 0x1 | SHADOW enabled
7440  *
7441  * Field Access Macros:
7442  *
7443  */
7444 /*
7445  * Enumerated value for register field ALT_UART_CPR_SHADOW
7446  *
7447  * SHADOW disabled
7448  */
7449 #define ALT_UART_CPR_SHADOW_E_DISABLED 0x0
7450 /*
7451  * Enumerated value for register field ALT_UART_CPR_SHADOW
7452  *
7453  * SHADOW enabled
7454  */
7455 #define ALT_UART_CPR_SHADOW_E_ENABLED 0x1
7456 
7457 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SHADOW register field. */
7458 #define ALT_UART_CPR_SHADOW_LSB 11
7459 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SHADOW register field. */
7460 #define ALT_UART_CPR_SHADOW_MSB 11
7461 /* The width in bits of the ALT_UART_CPR_SHADOW register field. */
7462 #define ALT_UART_CPR_SHADOW_WIDTH 1
7463 /* The mask used to set the ALT_UART_CPR_SHADOW register field value. */
7464 #define ALT_UART_CPR_SHADOW_SET_MSK 0x00000800
7465 /* The mask used to clear the ALT_UART_CPR_SHADOW register field value. */
7466 #define ALT_UART_CPR_SHADOW_CLR_MSK 0xfffff7ff
7467 /* The reset value of the ALT_UART_CPR_SHADOW register field. */
7468 #define ALT_UART_CPR_SHADOW_RESET 0x1
7469 /* Extracts the ALT_UART_CPR_SHADOW field value from a register. */
7470 #define ALT_UART_CPR_SHADOW_GET(value) (((value) & 0x00000800) >> 11)
7471 /* Produces a ALT_UART_CPR_SHADOW register field value suitable for setting the register. */
7472 #define ALT_UART_CPR_SHADOW_SET(value) (((value) << 11) & 0x00000800)
7473 
7474 /*
7475  * Field : UART_ADD_ENCODED_PARAMS
7476  *
7477  * Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value.
7478  *
7479  * 0 = FALSE,
7480  *
7481  * 1 = TRUE
7482  *
7483  * Field Enumeration Values:
7484  *
7485  * Enum | Value | Description
7486  * :------------------------------------------------|:------|:---------------------------------
7487  * ALT_UART_CPR_UART_ADD_ENCODED_PARAMS_E_DISABLED | 0x0 | UART_ADD_ENCODED_PARAMS disabled
7488  * ALT_UART_CPR_UART_ADD_ENCODED_PARAMS_E_ENABLED | 0x1 | UART_ADD_ENCODED_PARAMS enabled
7489  *
7490  * Field Access Macros:
7491  *
7492  */
7493 /*
7494  * Enumerated value for register field ALT_UART_CPR_UART_ADD_ENCODED_PARAMS
7495  *
7496  * UART_ADD_ENCODED_PARAMS disabled
7497  */
7498 #define ALT_UART_CPR_UART_ADD_ENCODED_PARAMS_E_DISABLED 0x0
7499 /*
7500  * Enumerated value for register field ALT_UART_CPR_UART_ADD_ENCODED_PARAMS
7501  *
7502  * UART_ADD_ENCODED_PARAMS enabled
7503  */
7504 #define ALT_UART_CPR_UART_ADD_ENCODED_PARAMS_E_ENABLED 0x1
7505 
7506 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_UART_ADD_ENCODED_PARAMS register field. */
7507 #define ALT_UART_CPR_UART_ADD_ENCODED_PARAMS_LSB 12
7508 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_UART_ADD_ENCODED_PARAMS register field. */
7509 #define ALT_UART_CPR_UART_ADD_ENCODED_PARAMS_MSB 12
7510 /* The width in bits of the ALT_UART_CPR_UART_ADD_ENCODED_PARAMS register field. */
7511 #define ALT_UART_CPR_UART_ADD_ENCODED_PARAMS_WIDTH 1
7512 /* The mask used to set the ALT_UART_CPR_UART_ADD_ENCODED_PARAMS register field value. */
7513 #define ALT_UART_CPR_UART_ADD_ENCODED_PARAMS_SET_MSK 0x00001000
7514 /* The mask used to clear the ALT_UART_CPR_UART_ADD_ENCODED_PARAMS register field value. */
7515 #define ALT_UART_CPR_UART_ADD_ENCODED_PARAMS_CLR_MSK 0xffffefff
7516 /* The reset value of the ALT_UART_CPR_UART_ADD_ENCODED_PARAMS register field. */
7517 #define ALT_UART_CPR_UART_ADD_ENCODED_PARAMS_RESET 0x1
7518 /* Extracts the ALT_UART_CPR_UART_ADD_ENCODED_PARAMS field value from a register. */
7519 #define ALT_UART_CPR_UART_ADD_ENCODED_PARAMS_GET(value) (((value) & 0x00001000) >> 12)
7520 /* Produces a ALT_UART_CPR_UART_ADD_ENCODED_PARAMS register field value suitable for setting the register. */
7521 #define ALT_UART_CPR_UART_ADD_ENCODED_PARAMS_SET(value) (((value) << 12) & 0x00001000)
7522 
7523 /*
7524  * Field : DMA_EXTRA
7525  *
7526  * Encoding of DMA_EXTRA configuration parameter value.
7527  *
7528  * 0 = FALSE,DW_apb_uart.ralf
7529  *
7530  * 1 = TRUE
7531  *
7532  * Field Enumeration Values:
7533  *
7534  * Enum | Value | Description
7535  * :----------------------------------|:------|:-------------------
7536  * ALT_UART_CPR_DMA_EXTRA_E_DISABLED | 0x0 | DMA_EXTRA disabled
7537  * ALT_UART_CPR_DMA_EXTRA_E_ENABLED | 0x1 | DMA_EXTRA enabled
7538  *
7539  * Field Access Macros:
7540  *
7541  */
7542 /*
7543  * Enumerated value for register field ALT_UART_CPR_DMA_EXTRA
7544  *
7545  * DMA_EXTRA disabled
7546  */
7547 #define ALT_UART_CPR_DMA_EXTRA_E_DISABLED 0x0
7548 /*
7549  * Enumerated value for register field ALT_UART_CPR_DMA_EXTRA
7550  *
7551  * DMA_EXTRA enabled
7552  */
7553 #define ALT_UART_CPR_DMA_EXTRA_E_ENABLED 0x1
7554 
7555 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */
7556 #define ALT_UART_CPR_DMA_EXTRA_LSB 13
7557 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */
7558 #define ALT_UART_CPR_DMA_EXTRA_MSB 13
7559 /* The width in bits of the ALT_UART_CPR_DMA_EXTRA register field. */
7560 #define ALT_UART_CPR_DMA_EXTRA_WIDTH 1
7561 /* The mask used to set the ALT_UART_CPR_DMA_EXTRA register field value. */
7562 #define ALT_UART_CPR_DMA_EXTRA_SET_MSK 0x00002000
7563 /* The mask used to clear the ALT_UART_CPR_DMA_EXTRA register field value. */
7564 #define ALT_UART_CPR_DMA_EXTRA_CLR_MSK 0xffffdfff
7565 /* The reset value of the ALT_UART_CPR_DMA_EXTRA register field. */
7566 #define ALT_UART_CPR_DMA_EXTRA_RESET 0x1
7567 /* Extracts the ALT_UART_CPR_DMA_EXTRA field value from a register. */
7568 #define ALT_UART_CPR_DMA_EXTRA_GET(value) (((value) & 0x00002000) >> 13)
7569 /* Produces a ALT_UART_CPR_DMA_EXTRA register field value suitable for setting the register. */
7570 #define ALT_UART_CPR_DMA_EXTRA_SET(value) (((value) << 13) & 0x00002000)
7571 
7572 /*
7573  * Field : RSVD_CPR_15to14
7574  *
7575  * Reserved bits [15:14] - Read Only
7576  *
7577  * Field Access Macros:
7578  *
7579  */
7580 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_RSVD_CPR_15TO14 register field. */
7581 #define ALT_UART_CPR_RSVD_CPR_15TO14_LSB 14
7582 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_RSVD_CPR_15TO14 register field. */
7583 #define ALT_UART_CPR_RSVD_CPR_15TO14_MSB 15
7584 /* The width in bits of the ALT_UART_CPR_RSVD_CPR_15TO14 register field. */
7585 #define ALT_UART_CPR_RSVD_CPR_15TO14_WIDTH 2
7586 /* The mask used to set the ALT_UART_CPR_RSVD_CPR_15TO14 register field value. */
7587 #define ALT_UART_CPR_RSVD_CPR_15TO14_SET_MSK 0x0000c000
7588 /* The mask used to clear the ALT_UART_CPR_RSVD_CPR_15TO14 register field value. */
7589 #define ALT_UART_CPR_RSVD_CPR_15TO14_CLR_MSK 0xffff3fff
7590 /* The reset value of the ALT_UART_CPR_RSVD_CPR_15TO14 register field. */
7591 #define ALT_UART_CPR_RSVD_CPR_15TO14_RESET 0x0
7592 /* Extracts the ALT_UART_CPR_RSVD_CPR_15TO14 field value from a register. */
7593 #define ALT_UART_CPR_RSVD_CPR_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
7594 /* Produces a ALT_UART_CPR_RSVD_CPR_15TO14 register field value suitable for setting the register. */
7595 #define ALT_UART_CPR_RSVD_CPR_15TO14_SET(value) (((value) << 14) & 0x0000c000)
7596 
7597 /*
7598  * Field : FIFO_MODE
7599  *
7600  * Encoding of FIFO_MODE configuration parameter value.DW_apb_uart.ralf
7601  *
7602  * 0x00 = 0,
7603  *
7604  * 0x01 = 16,
7605  *
7606  * 0x02 = 32,
7607  *
7608  * toset
7609  *
7610  * 0x80 = 2048,
7611  *
7612  * 0x81- 0xff = reserved
7613  *
7614  * Field Enumeration Values:
7615  *
7616  * Enum | Value | Description
7617  * :----------------------------------------|:------|:------------------
7618  * ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_0 | 0x0 | FIFO mode is 0
7619  * ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_16 | 0x1 | FIFO mode is 16
7620  * ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_32 | 0x2 | FIFO mode is 32
7621  * ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_64 | 0x4 | FIFO mode is 64
7622  * ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_128 | 0x8 | FIFO mode is 128
7623  * ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_256 | 0x10 | FIFO mode is 256
7624  * ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_512 | 0x20 | FIFO mode is 512
7625  * ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_1024 | 0x40 | FIFO mode is 1024
7626  * ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_2048 | 0x80 | FIFO mode is 2048
7627  *
7628  * Field Access Macros:
7629  *
7630  */
7631 /*
7632  * Enumerated value for register field ALT_UART_CPR_FIFO_MODE
7633  *
7634  * FIFO mode is 0
7635  */
7636 #define ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_0 0x0
7637 /*
7638  * Enumerated value for register field ALT_UART_CPR_FIFO_MODE
7639  *
7640  * FIFO mode is 16
7641  */
7642 #define ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_16 0x1
7643 /*
7644  * Enumerated value for register field ALT_UART_CPR_FIFO_MODE
7645  *
7646  * FIFO mode is 32
7647  */
7648 #define ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_32 0x2
7649 /*
7650  * Enumerated value for register field ALT_UART_CPR_FIFO_MODE
7651  *
7652  * FIFO mode is 64
7653  */
7654 #define ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_64 0x4
7655 /*
7656  * Enumerated value for register field ALT_UART_CPR_FIFO_MODE
7657  *
7658  * FIFO mode is 128
7659  */
7660 #define ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_128 0x8
7661 /*
7662  * Enumerated value for register field ALT_UART_CPR_FIFO_MODE
7663  *
7664  * FIFO mode is 256
7665  */
7666 #define ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_256 0x10
7667 /*
7668  * Enumerated value for register field ALT_UART_CPR_FIFO_MODE
7669  *
7670  * FIFO mode is 512
7671  */
7672 #define ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_512 0x20
7673 /*
7674  * Enumerated value for register field ALT_UART_CPR_FIFO_MODE
7675  *
7676  * FIFO mode is 1024
7677  */
7678 #define ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_1024 0x40
7679 /*
7680  * Enumerated value for register field ALT_UART_CPR_FIFO_MODE
7681  *
7682  * FIFO mode is 2048
7683  */
7684 #define ALT_UART_CPR_FIFO_MODE_E_FIFO_MODE_2048 0x80
7685 
7686 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_MODE register field. */
7687 #define ALT_UART_CPR_FIFO_MODE_LSB 16
7688 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_MODE register field. */
7689 #define ALT_UART_CPR_FIFO_MODE_MSB 23
7690 /* The width in bits of the ALT_UART_CPR_FIFO_MODE register field. */
7691 #define ALT_UART_CPR_FIFO_MODE_WIDTH 8
7692 /* The mask used to set the ALT_UART_CPR_FIFO_MODE register field value. */
7693 #define ALT_UART_CPR_FIFO_MODE_SET_MSK 0x00ff0000
7694 /* The mask used to clear the ALT_UART_CPR_FIFO_MODE register field value. */
7695 #define ALT_UART_CPR_FIFO_MODE_CLR_MSK 0xff00ffff
7696 /* The reset value of the ALT_UART_CPR_FIFO_MODE register field. */
7697 #define ALT_UART_CPR_FIFO_MODE_RESET 0x8
7698 /* Extracts the ALT_UART_CPR_FIFO_MODE field value from a register. */
7699 #define ALT_UART_CPR_FIFO_MODE_GET(value) (((value) & 0x00ff0000) >> 16)
7700 /* Produces a ALT_UART_CPR_FIFO_MODE register field value suitable for setting the register. */
7701 #define ALT_UART_CPR_FIFO_MODE_SET(value) (((value) << 16) & 0x00ff0000)
7702 
7703 /*
7704  * Field : RSVD_CPR_31to24
7705  *
7706  * Reserved bits [31:24] - Read Only
7707  *
7708  * Field Access Macros:
7709  *
7710  */
7711 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_RSVD_CPR_31TO24 register field. */
7712 #define ALT_UART_CPR_RSVD_CPR_31TO24_LSB 24
7713 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_RSVD_CPR_31TO24 register field. */
7714 #define ALT_UART_CPR_RSVD_CPR_31TO24_MSB 31
7715 /* The width in bits of the ALT_UART_CPR_RSVD_CPR_31TO24 register field. */
7716 #define ALT_UART_CPR_RSVD_CPR_31TO24_WIDTH 8
7717 /* The mask used to set the ALT_UART_CPR_RSVD_CPR_31TO24 register field value. */
7718 #define ALT_UART_CPR_RSVD_CPR_31TO24_SET_MSK 0xff000000
7719 /* The mask used to clear the ALT_UART_CPR_RSVD_CPR_31TO24 register field value. */
7720 #define ALT_UART_CPR_RSVD_CPR_31TO24_CLR_MSK 0x00ffffff
7721 /* The reset value of the ALT_UART_CPR_RSVD_CPR_31TO24 register field. */
7722 #define ALT_UART_CPR_RSVD_CPR_31TO24_RESET 0x0
7723 /* Extracts the ALT_UART_CPR_RSVD_CPR_31TO24 field value from a register. */
7724 #define ALT_UART_CPR_RSVD_CPR_31TO24_GET(value) (((value) & 0xff000000) >> 24)
7725 /* Produces a ALT_UART_CPR_RSVD_CPR_31TO24 register field value suitable for setting the register. */
7726 #define ALT_UART_CPR_RSVD_CPR_31TO24_SET(value) (((value) << 24) & 0xff000000)
7727 
7728 #ifndef __ASSEMBLY__
7729 /*
7730  * WARNING: The C register and register group struct declarations are provided for
7731  * convenience and illustrative purposes. They should, however, be used with
7732  * caution as the C language standard provides no guarantees about the alignment or
7733  * atomicity of device memory accesses. The recommended practice for coding device
7734  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7735  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7736  * alt_write_dword() functions for 64 bit registers.
7737  *
7738  * The struct declaration for register ALT_UART_CPR.
7739  */
7740 struct ALT_UART_CPR_s
7741 {
7742  const volatile uint32_t APB_DATA_WIDTH : 2; /* ALT_UART_CPR_APB_DATA_WIDTH */
7743  const volatile uint32_t RSVD_CPR_3to2 : 2; /* ALT_UART_CPR_RSVD_CPR_3TO2 */
7744  const volatile uint32_t AFCE_MODE : 1; /* ALT_UART_CPR_AFCE_MODE */
7745  const volatile uint32_t THRE_MODE : 1; /* ALT_UART_CPR_THRE_MODE */
7746  const volatile uint32_t SIR_MODE : 1; /* ALT_UART_CPR_SIR_MODE */
7747  const volatile uint32_t SIR_LP_MODE : 1; /* ALT_UART_CPR_SIR_LP_MODE */
7748  const volatile uint32_t ADDITIONAL_FEAT : 1; /* ALT_UART_CPR_ADDITIONAL_FEAT */
7749  const volatile uint32_t FIFO_ACCESS : 1; /* ALT_UART_CPR_FIFO_ACCESS */
7750  const volatile uint32_t FIFO_STAT : 1; /* ALT_UART_CPR_FIFO_STAT */
7751  const volatile uint32_t SHADOW : 1; /* ALT_UART_CPR_SHADOW */
7752  const volatile uint32_t UART_ADD_ENCODED_PARAMS : 1; /* ALT_UART_CPR_UART_ADD_ENCODED_PARAMS */
7753  const volatile uint32_t DMA_EXTRA : 1; /* ALT_UART_CPR_DMA_EXTRA */
7754  const volatile uint32_t RSVD_CPR_15to14 : 2; /* ALT_UART_CPR_RSVD_CPR_15TO14 */
7755  const volatile uint32_t FIFO_MODE : 8; /* ALT_UART_CPR_FIFO_MODE */
7756  const volatile uint32_t RSVD_CPR_31to24 : 8; /* ALT_UART_CPR_RSVD_CPR_31TO24 */
7757 };
7758 
7759 /* The typedef declaration for register ALT_UART_CPR. */
7760 typedef struct ALT_UART_CPR_s ALT_UART_CPR_t;
7761 #endif /* __ASSEMBLY__ */
7762 
7763 /* The reset value of the ALT_UART_CPR register. */
7764 #define ALT_UART_CPR_RESET 0x00083f32
7765 /* The byte offset of the ALT_UART_CPR register from the beginning of the component. */
7766 #define ALT_UART_CPR_OFST 0xf4
7767 /* The address of the ALT_UART_CPR register. */
7768 #define ALT_UART_CPR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CPR_OFST))
7769 
7770 /*
7771  * Register : Component Version - UCV
7772  *
7773  * Component Version
7774  *
7775  * Register Layout
7776  *
7777  * Bits | Access | Reset | Description
7778  * :-------|:-------|:-----------|:------------------------------------
7779  * [31:0] | R | 0x3331352a | ALT_UART_UCV_UART_COMPONENT_VERSION
7780  *
7781  */
7782 /*
7783  * Field : UART_Component_Version
7784  *
7785  * ASCII value for each number in the version, followed by *.
7786  *
7787  * For example 32_30_31_2A represents the version 2.01*
7788  *
7789  * Field Access Macros:
7790  *
7791  */
7792 /* The Least Significant Bit (LSB) position of the ALT_UART_UCV_UART_COMPONENT_VERSION register field. */
7793 #define ALT_UART_UCV_UART_COMPONENT_VERSION_LSB 0
7794 /* The Most Significant Bit (MSB) position of the ALT_UART_UCV_UART_COMPONENT_VERSION register field. */
7795 #define ALT_UART_UCV_UART_COMPONENT_VERSION_MSB 31
7796 /* The width in bits of the ALT_UART_UCV_UART_COMPONENT_VERSION register field. */
7797 #define ALT_UART_UCV_UART_COMPONENT_VERSION_WIDTH 32
7798 /* The mask used to set the ALT_UART_UCV_UART_COMPONENT_VERSION register field value. */
7799 #define ALT_UART_UCV_UART_COMPONENT_VERSION_SET_MSK 0xffffffff
7800 /* The mask used to clear the ALT_UART_UCV_UART_COMPONENT_VERSION register field value. */
7801 #define ALT_UART_UCV_UART_COMPONENT_VERSION_CLR_MSK 0x00000000
7802 /* The reset value of the ALT_UART_UCV_UART_COMPONENT_VERSION register field. */
7803 #define ALT_UART_UCV_UART_COMPONENT_VERSION_RESET 0x3331352a
7804 /* Extracts the ALT_UART_UCV_UART_COMPONENT_VERSION field value from a register. */
7805 #define ALT_UART_UCV_UART_COMPONENT_VERSION_GET(value) (((value) & 0xffffffff) >> 0)
7806 /* Produces a ALT_UART_UCV_UART_COMPONENT_VERSION register field value suitable for setting the register. */
7807 #define ALT_UART_UCV_UART_COMPONENT_VERSION_SET(value) (((value) << 0) & 0xffffffff)
7808 
7809 #ifndef __ASSEMBLY__
7810 /*
7811  * WARNING: The C register and register group struct declarations are provided for
7812  * convenience and illustrative purposes. They should, however, be used with
7813  * caution as the C language standard provides no guarantees about the alignment or
7814  * atomicity of device memory accesses. The recommended practice for coding device
7815  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7816  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7817  * alt_write_dword() functions for 64 bit registers.
7818  *
7819  * The struct declaration for register ALT_UART_UCV.
7820  */
7821 struct ALT_UART_UCV_s
7822 {
7823  const volatile uint32_t UART_Component_Version : 32; /* ALT_UART_UCV_UART_COMPONENT_VERSION */
7824 };
7825 
7826 /* The typedef declaration for register ALT_UART_UCV. */
7827 typedef struct ALT_UART_UCV_s ALT_UART_UCV_t;
7828 #endif /* __ASSEMBLY__ */
7829 
7830 /* The reset value of the ALT_UART_UCV register. */
7831 #define ALT_UART_UCV_RESET 0x3331352a
7832 /* The byte offset of the ALT_UART_UCV register from the beginning of the component. */
7833 #define ALT_UART_UCV_OFST 0xf8
7834 /* The address of the ALT_UART_UCV register. */
7835 #define ALT_UART_UCV_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_UCV_OFST))
7836 
7837 /*
7838  * Register : Component Type Register - CTR
7839  *
7840  * Component Type Register
7841  *
7842  * Register Layout
7843  *
7844  * Bits | Access | Reset | Description
7845  * :-------|:-------|:-----------|:---------------------------
7846  * [31:0] | R | 0x44570110 | ALT_UART_CTR_PERIPHERAL_ID
7847  *
7848  */
7849 /*
7850  * Field : Peripheral_ID
7851  *
7852  * This register contains the peripherals identification code.
7853  *
7854  * Field Access Macros:
7855  *
7856  */
7857 /* The Least Significant Bit (LSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */
7858 #define ALT_UART_CTR_PERIPHERAL_ID_LSB 0
7859 /* The Most Significant Bit (MSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */
7860 #define ALT_UART_CTR_PERIPHERAL_ID_MSB 31
7861 /* The width in bits of the ALT_UART_CTR_PERIPHERAL_ID register field. */
7862 #define ALT_UART_CTR_PERIPHERAL_ID_WIDTH 32
7863 /* The mask used to set the ALT_UART_CTR_PERIPHERAL_ID register field value. */
7864 #define ALT_UART_CTR_PERIPHERAL_ID_SET_MSK 0xffffffff
7865 /* The mask used to clear the ALT_UART_CTR_PERIPHERAL_ID register field value. */
7866 #define ALT_UART_CTR_PERIPHERAL_ID_CLR_MSK 0x00000000
7867 /* The reset value of the ALT_UART_CTR_PERIPHERAL_ID register field. */
7868 #define ALT_UART_CTR_PERIPHERAL_ID_RESET 0x44570110
7869 /* Extracts the ALT_UART_CTR_PERIPHERAL_ID field value from a register. */
7870 #define ALT_UART_CTR_PERIPHERAL_ID_GET(value) (((value) & 0xffffffff) >> 0)
7871 /* Produces a ALT_UART_CTR_PERIPHERAL_ID register field value suitable for setting the register. */
7872 #define ALT_UART_CTR_PERIPHERAL_ID_SET(value) (((value) << 0) & 0xffffffff)
7873 
7874 #ifndef __ASSEMBLY__
7875 /*
7876  * WARNING: The C register and register group struct declarations are provided for
7877  * convenience and illustrative purposes. They should, however, be used with
7878  * caution as the C language standard provides no guarantees about the alignment or
7879  * atomicity of device memory accesses. The recommended practice for coding device
7880  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7881  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7882  * alt_write_dword() functions for 64 bit registers.
7883  *
7884  * The struct declaration for register ALT_UART_CTR.
7885  */
7886 struct ALT_UART_CTR_s
7887 {
7888  const volatile uint32_t Peripheral_ID : 32; /* ALT_UART_CTR_PERIPHERAL_ID */
7889 };
7890 
7891 /* The typedef declaration for register ALT_UART_CTR. */
7892 typedef struct ALT_UART_CTR_s ALT_UART_CTR_t;
7893 #endif /* __ASSEMBLY__ */
7894 
7895 /* The reset value of the ALT_UART_CTR register. */
7896 #define ALT_UART_CTR_RESET 0x44570110
7897 /* The byte offset of the ALT_UART_CTR register from the beginning of the component. */
7898 #define ALT_UART_CTR_OFST 0xfc
7899 /* The address of the ALT_UART_CTR register. */
7900 #define ALT_UART_CTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CTR_OFST))
7901 
7902 #ifndef __ASSEMBLY__
7903 /*
7904  * WARNING: The C register and register group struct declarations are provided for
7905  * convenience and illustrative purposes. They should, however, be used with
7906  * caution as the C language standard provides no guarantees about the alignment or
7907  * atomicity of device memory accesses. The recommended practice for coding device
7908  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7909  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7910  * alt_write_dword() functions for 64 bit registers.
7911  *
7912  * The struct declaration for register group ALT_UART.
7913  */
7914 struct ALT_UART_s
7915 {
7916  volatile ALT_UART_RBR_t RBR; /* ALT_UART_RBR */
7917  volatile ALT_UART_IER_t IER; /* ALT_UART_IER */
7918  volatile ALT_UART_IIR_t IIR; /* ALT_UART_IIR */
7919  volatile ALT_UART_LCR_t LCR; /* ALT_UART_LCR */
7920  volatile ALT_UART_MCR_t MCR; /* ALT_UART_MCR */
7921  volatile ALT_UART_LSR_t LSR; /* ALT_UART_LSR */
7922  volatile ALT_UART_MSR_t MSR; /* ALT_UART_MSR */
7923  volatile ALT_UART_SCR_t SCR; /* ALT_UART_SCR */
7924  volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */
7925  volatile ALT_UART_SRBR0_t SRBR0; /* ALT_UART_SRBR0 */
7926  volatile ALT_UART_SRBR1_t SRBR1; /* ALT_UART_SRBR1 */
7927  volatile ALT_UART_SRBR2_t SRBR2; /* ALT_UART_SRBR2 */
7928  volatile ALT_UART_SRBR3_t SRBR3; /* ALT_UART_SRBR3 */
7929  volatile ALT_UART_SRBR4_t SRBR4; /* ALT_UART_SRBR4 */
7930  volatile ALT_UART_SRBR5_t SRBR5; /* ALT_UART_SRBR5 */
7931  volatile ALT_UART_SRBR6_t SRBR6; /* ALT_UART_SRBR6 */
7932  volatile ALT_UART_SRBR7_t SRBR7; /* ALT_UART_SRBR7 */
7933  volatile ALT_UART_SRBR8_t SRBR8; /* ALT_UART_SRBR8 */
7934  volatile ALT_UART_SRBR9_t SRBR9; /* ALT_UART_SRBR9 */
7935  volatile ALT_UART_SRBR10_t SRBR10; /* ALT_UART_SRBR10 */
7936  volatile ALT_UART_SRBR11_t SRBR11; /* ALT_UART_SRBR11 */
7937  volatile ALT_UART_SRBR12_t SRBR12; /* ALT_UART_SRBR12 */
7938  volatile ALT_UART_SRBR13_t SRBR13; /* ALT_UART_SRBR13 */
7939  volatile ALT_UART_SRBR14_t SRBR14; /* ALT_UART_SRBR14 */
7940  volatile ALT_UART_SRBR15_t SRBR15; /* ALT_UART_SRBR15 */
7941  volatile ALT_UART_FAR_t FAR; /* ALT_UART_FAR */
7942  volatile ALT_UART_TFR_t TFR; /* ALT_UART_TFR */
7943  volatile ALT_UART_RFW_t RFW; /* ALT_UART_RFW */
7944  volatile ALT_UART_USR_t USR; /* ALT_UART_USR */
7945  volatile ALT_UART_TFL_t TFL; /* ALT_UART_TFL */
7946  volatile ALT_UART_RFL_t RFL; /* ALT_UART_RFL */
7947  volatile ALT_UART_SRR_t SRR; /* ALT_UART_SRR */
7948  volatile ALT_UART_SRTS_t SRTS; /* ALT_UART_SRTS */
7949  volatile ALT_UART_SBCR_t SBCR; /* ALT_UART_SBCR */
7950  volatile ALT_UART_SDMAM_t SDMAM; /* ALT_UART_SDMAM */
7951  volatile ALT_UART_SFE_t SFE; /* ALT_UART_SFE */
7952  volatile ALT_UART_SRT_t SRT; /* ALT_UART_SRT */
7953  volatile ALT_UART_STET_t STET; /* ALT_UART_STET */
7954  volatile ALT_UART_HTX_t HTX; /* ALT_UART_HTX */
7955  volatile ALT_UART_DMASA_t DMASA; /* ALT_UART_DMASA */
7956  volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */
7957  volatile ALT_UART_CPR_t CPR; /* ALT_UART_CPR */
7958  volatile ALT_UART_UCV_t UCV; /* ALT_UART_UCV */
7959  volatile ALT_UART_CTR_t CTR; /* ALT_UART_CTR */
7960 };
7961 
7962 /* The typedef declaration for register group ALT_UART. */
7963 typedef struct ALT_UART_s ALT_UART_t;
7964 /* The struct declaration for the raw register contents of register group ALT_UART. */
7965 struct ALT_UART_raw_s
7966 {
7967  volatile uint32_t RBR; /* ALT_UART_RBR */
7968  volatile uint32_t IER; /* ALT_UART_IER */
7969  volatile uint32_t IIR; /* ALT_UART_IIR */
7970  volatile uint32_t LCR; /* ALT_UART_LCR */
7971  volatile uint32_t MCR; /* ALT_UART_MCR */
7972  volatile uint32_t LSR; /* ALT_UART_LSR */
7973  volatile uint32_t MSR; /* ALT_UART_MSR */
7974  volatile uint32_t SCR; /* ALT_UART_SCR */
7975  volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */
7976  volatile uint32_t SRBR0; /* ALT_UART_SRBR0 */
7977  volatile uint32_t SRBR1; /* ALT_UART_SRBR1 */
7978  volatile uint32_t SRBR2; /* ALT_UART_SRBR2 */
7979  volatile uint32_t SRBR3; /* ALT_UART_SRBR3 */
7980  volatile uint32_t SRBR4; /* ALT_UART_SRBR4 */
7981  volatile uint32_t SRBR5; /* ALT_UART_SRBR5 */
7982  volatile uint32_t SRBR6; /* ALT_UART_SRBR6 */
7983  volatile uint32_t SRBR7; /* ALT_UART_SRBR7 */
7984  volatile uint32_t SRBR8; /* ALT_UART_SRBR8 */
7985  volatile uint32_t SRBR9; /* ALT_UART_SRBR9 */
7986  volatile uint32_t SRBR10; /* ALT_UART_SRBR10 */
7987  volatile uint32_t SRBR11; /* ALT_UART_SRBR11 */
7988  volatile uint32_t SRBR12; /* ALT_UART_SRBR12 */
7989  volatile uint32_t SRBR13; /* ALT_UART_SRBR13 */
7990  volatile uint32_t SRBR14; /* ALT_UART_SRBR14 */
7991  volatile uint32_t SRBR15; /* ALT_UART_SRBR15 */
7992  volatile uint32_t FAR; /* ALT_UART_FAR */
7993  volatile uint32_t TFR; /* ALT_UART_TFR */
7994  volatile uint32_t RFW; /* ALT_UART_RFW */
7995  volatile uint32_t USR; /* ALT_UART_USR */
7996  volatile uint32_t TFL; /* ALT_UART_TFL */
7997  volatile uint32_t RFL; /* ALT_UART_RFL */
7998  volatile uint32_t SRR; /* ALT_UART_SRR */
7999  volatile uint32_t SRTS; /* ALT_UART_SRTS */
8000  volatile uint32_t SBCR; /* ALT_UART_SBCR */
8001  volatile uint32_t SDMAM; /* ALT_UART_SDMAM */
8002  volatile uint32_t SFE; /* ALT_UART_SFE */
8003  volatile uint32_t SRT; /* ALT_UART_SRT */
8004  volatile uint32_t STET; /* ALT_UART_STET */
8005  volatile uint32_t HTX; /* ALT_UART_HTX */
8006  volatile uint32_t DMASA; /* ALT_UART_DMASA */
8007  volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */
8008  volatile uint32_t CPR; /* ALT_UART_CPR */
8009  volatile uint32_t UCV; /* ALT_UART_UCV */
8010  volatile uint32_t CTR; /* ALT_UART_CTR */
8011 };
8012 
8013 /* The typedef declaration for the raw register contents of register group ALT_UART. */
8014 typedef struct ALT_UART_raw_s ALT_UART_raw_t;
8015 #endif /* __ASSEMBLY__ */
8016 
8017 
8018 #ifdef __cplusplus
8019 }
8020 #endif /* __cplusplus */
8021 #endif /* __ALT_SOCAL_UART_H__ */
8022