35 #ifndef __ALT_SOCAL_QSPI_H__
36 #define __ALT_SOCAL_QSPI_H__
99 #define ALT_QSPI_CFG_EN_E_DIS 0x0
105 #define ALT_QSPI_CFG_EN_E_EN 0x1
108 #define ALT_QSPI_CFG_EN_LSB 0
110 #define ALT_QSPI_CFG_EN_MSB 0
112 #define ALT_QSPI_CFG_EN_WIDTH 1
114 #define ALT_QSPI_CFG_EN_SET_MSK 0x00000001
116 #define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe
118 #define ALT_QSPI_CFG_EN_RESET 0x0
120 #define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0)
122 #define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001)
144 #define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0
150 #define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1
153 #define ALT_QSPI_CFG_SELCLKPOL_LSB 1
155 #define ALT_QSPI_CFG_SELCLKPOL_MSB 1
157 #define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1
159 #define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002
161 #define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd
163 #define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0
165 #define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1)
167 #define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002)
191 #define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0
197 #define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1
200 #define ALT_QSPI_CFG_SELCLKPHASE_LSB 2
202 #define ALT_QSPI_CFG_SELCLKPHASE_MSB 2
204 #define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1
206 #define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004
208 #define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
210 #define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0
212 #define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2)
214 #define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004)
223 #define ALT_QSPI_CFG_CFG_RESV1_FLD_LSB 3
225 #define ALT_QSPI_CFG_CFG_RESV1_FLD_MSB 6
227 #define ALT_QSPI_CFG_CFG_RESV1_FLD_WIDTH 4
229 #define ALT_QSPI_CFG_CFG_RESV1_FLD_SET_MSK 0x00000078
231 #define ALT_QSPI_CFG_CFG_RESV1_FLD_CLR_MSK 0xffffff87
233 #define ALT_QSPI_CFG_CFG_RESV1_FLD_RESET 0x0
235 #define ALT_QSPI_CFG_CFG_RESV1_FLD_GET(value) (((value) & 0x00000078) >> 3)
237 #define ALT_QSPI_CFG_CFG_RESV1_FLD_SET(value) (((value) << 3) & 0x00000078)
262 #define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0
268 #define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1
271 #define ALT_QSPI_CFG_ENDIRACC_LSB 7
273 #define ALT_QSPI_CFG_ENDIRACC_MSB 7
275 #define ALT_QSPI_CFG_ENDIRACC_WIDTH 1
277 #define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080
279 #define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f
281 #define ALT_QSPI_CFG_ENDIRACC_RESET 0x0
283 #define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7)
285 #define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080)
312 #define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0
318 #define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1
321 #define ALT_QSPI_CFG_ENLEGACYIP_LSB 8
323 #define ALT_QSPI_CFG_ENLEGACYIP_MSB 8
325 #define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1
327 #define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100
329 #define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff
331 #define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0
333 #define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8)
335 #define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100)
358 #define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0
364 #define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1
367 #define ALT_QSPI_CFG_PERSELDEC_LSB 9
369 #define ALT_QSPI_CFG_PERSELDEC_MSB 9
371 #define ALT_QSPI_CFG_PERSELDEC_WIDTH 1
373 #define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200
375 #define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff
377 #define ALT_QSPI_CFG_PERSELDEC_RESET 0x0
379 #define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9)
381 #define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200)
394 #define ALT_QSPI_CFG_PERCSLINES_LSB 10
396 #define ALT_QSPI_CFG_PERCSLINES_MSB 13
398 #define ALT_QSPI_CFG_PERCSLINES_WIDTH 4
400 #define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00
402 #define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff
404 #define ALT_QSPI_CFG_PERCSLINES_RESET 0x0
406 #define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10)
408 #define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00)
431 #define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0
437 #define ALT_QSPI_CFG_WP_E_WRPROTON 0x1
440 #define ALT_QSPI_CFG_WP_LSB 14
442 #define ALT_QSPI_CFG_WP_MSB 14
444 #define ALT_QSPI_CFG_WP_WIDTH 1
446 #define ALT_QSPI_CFG_WP_SET_MSK 0x00004000
448 #define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff
450 #define ALT_QSPI_CFG_WP_RESET 0x0
452 #define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14)
454 #define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000)
477 #define ALT_QSPI_CFG_ENDMA_E_DIS 0x0
483 #define ALT_QSPI_CFG_ENDMA_E_EN 0x1
486 #define ALT_QSPI_CFG_ENDMA_LSB 15
488 #define ALT_QSPI_CFG_ENDMA_MSB 15
490 #define ALT_QSPI_CFG_ENDMA_WIDTH 1
492 #define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000
494 #define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
496 #define ALT_QSPI_CFG_ENDMA_RESET 0x0
498 #define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15)
500 #define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000)
524 #define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0
530 #define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1
533 #define ALT_QSPI_CFG_ENAHBREMAP_LSB 16
535 #define ALT_QSPI_CFG_ENAHBREMAP_MSB 16
537 #define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1
539 #define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000
541 #define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff
543 #define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0
545 #define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16)
547 #define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000)
579 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0
585 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1
588 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17
590 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17
592 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1
594 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000
596 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff
598 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0
600 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17)
602 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000)
633 #define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0
639 #define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1
642 #define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18
644 #define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18
646 #define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1
648 #define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000
650 #define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff
652 #define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0
654 #define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18)
656 #define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000)
692 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0
698 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1
704 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2
710 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3
716 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4
722 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5
728 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6
734 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7
740 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8
746 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9
752 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa
758 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb
764 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc
770 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd
776 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe
782 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf
785 #define ALT_QSPI_CFG_BAUDDIV_LSB 19
787 #define ALT_QSPI_CFG_BAUDDIV_MSB 22
789 #define ALT_QSPI_CFG_BAUDDIV_WIDTH 4
791 #define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000
793 #define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff
795 #define ALT_QSPI_CFG_BAUDDIV_RESET 0xf
797 #define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19)
799 #define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000)
808 #define ALT_QSPI_CFG_CFG_RESV2_FLD_LSB 23
810 #define ALT_QSPI_CFG_CFG_RESV2_FLD_MSB 30
812 #define ALT_QSPI_CFG_CFG_RESV2_FLD_WIDTH 8
814 #define ALT_QSPI_CFG_CFG_RESV2_FLD_SET_MSK 0x7f800000
816 #define ALT_QSPI_CFG_CFG_RESV2_FLD_CLR_MSK 0x807fffff
818 #define ALT_QSPI_CFG_CFG_RESV2_FLD_RESET 0x0
820 #define ALT_QSPI_CFG_CFG_RESV2_FLD_GET(value) (((value) & 0x7f800000) >> 23)
822 #define ALT_QSPI_CFG_CFG_RESV2_FLD_SET(value) (((value) << 23) & 0x7f800000)
845 #define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0
851 #define ALT_QSPI_CFG_IDLE_E_SET 0x1
854 #define ALT_QSPI_CFG_IDLE_LSB 31
856 #define ALT_QSPI_CFG_IDLE_MSB 31
858 #define ALT_QSPI_CFG_IDLE_WIDTH 1
860 #define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000
862 #define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff
864 #define ALT_QSPI_CFG_IDLE_RESET 0x1
866 #define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31)
868 #define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000)
881 struct ALT_QSPI_CFG_s
884 uint32_t selclkpol : 1;
885 uint32_t selclkphase : 1;
886 const uint32_t config_resv1_fld : 4;
887 uint32_t endiracc : 1;
888 uint32_t enlegacyip : 1;
889 uint32_t perseldec : 1;
890 uint32_t percslines : 4;
893 uint32_t enahbremap : 1;
894 uint32_t enterxipnextrd : 1;
895 uint32_t enterxipimm : 1;
896 uint32_t bauddiv : 4;
897 const uint32_t config_resv2_fld : 8;
898 const uint32_t idle : 1;
902 typedef volatile struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t;
906 #define ALT_QSPI_CFG_RESET 0x80780000
908 #define ALT_QSPI_CFG_OFST 0x0
950 #define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3
956 #define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb
959 #define ALT_QSPI_DEVRD_RDOPCODE_LSB 0
961 #define ALT_QSPI_DEVRD_RDOPCODE_MSB 7
963 #define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8
965 #define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff
967 #define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00
969 #define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3
971 #define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0)
973 #define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff)
1004 #define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0
1011 #define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1
1018 #define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2
1021 #define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8
1023 #define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9
1025 #define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2
1027 #define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300
1029 #define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff
1031 #define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0
1033 #define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8)
1035 #define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300)
1044 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_LSB 10
1046 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_MSB 11
1048 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_WIDTH 2
1050 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET_MSK 0x00000c00
1052 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_CLR_MSK 0xfffff3ff
1054 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_RESET 0x0
1056 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_GET(value) (((value) & 0x00000c00) >> 10)
1058 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET(value) (((value) << 10) & 0x00000c00)
1092 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0
1100 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1
1108 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2
1111 #define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12
1113 #define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13
1115 #define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2
1117 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000
1119 #define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff
1121 #define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0
1123 #define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1125 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1134 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_LSB 14
1136 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_MSB 15
1138 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_WIDTH 2
1140 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET_MSK 0x0000c000
1142 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff
1144 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_RESET 0x0
1146 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_GET(value) (((value) & 0x0000c000) >> 14)
1148 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET(value) (((value) << 14) & 0x0000c000)
1184 #define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0
1192 #define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1
1200 #define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2
1203 #define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16
1205 #define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17
1207 #define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2
1209 #define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000
1211 #define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff
1213 #define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0
1215 #define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1217 #define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1226 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_LSB 18
1228 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_MSB 19
1230 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_WIDTH 2
1232 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET_MSK 0x000c0000
1234 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_CLR_MSK 0xfff3ffff
1236 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_RESET 0x0
1238 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_GET(value) (((value) & 0x000c0000) >> 18)
1240 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET(value) (((value) << 18) & 0x000c0000)
1263 #define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0
1269 #define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1
1272 #define ALT_QSPI_DEVRD_ENMODBITS_LSB 20
1274 #define ALT_QSPI_DEVRD_ENMODBITS_MSB 20
1276 #define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1
1278 #define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000
1280 #define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff
1282 #define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0
1284 #define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20)
1286 #define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000)
1295 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_LSB 21
1297 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_MSB 23
1299 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_WIDTH 3
1301 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET_MSK 0x00e00000
1303 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_CLR_MSK 0xff1fffff
1305 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_RESET 0x0
1307 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_GET(value) (((value) & 0x00e00000) >> 21)
1309 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET(value) (((value) << 21) & 0x00e00000)
1320 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24
1322 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28
1324 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5
1326 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000
1328 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff
1330 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0
1332 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1334 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000)
1343 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_LSB 29
1345 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_MSB 31
1347 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_WIDTH 3
1349 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET_MSK 0xe0000000
1351 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_CLR_MSK 0x1fffffff
1353 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_RESET 0x0
1355 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_GET(value) (((value) & 0xe0000000) >> 29)
1357 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET(value) (((value) << 29) & 0xe0000000)
1359 #ifndef __ASSEMBLY__
1370 struct ALT_QSPI_DEVRD_s
1372 uint32_t rdopcode : 8;
1373 uint32_t instwidth : 2;
1374 const uint32_t rd_instr_resv1_fld : 2;
1375 uint32_t addrwidth : 2;
1376 const uint32_t rd_instr_resv2_fld : 2;
1377 uint32_t datawidth : 2;
1378 const uint32_t rd_instr_resv3_fld : 2;
1379 uint32_t enmodebits : 1;
1380 const uint32_t rd_instr_resv4_fld : 3;
1381 uint32_t dummyrdclks : 5;
1382 const uint32_t rd_instr_resv5_fld : 3;
1386 typedef volatile struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t;
1390 #define ALT_QSPI_DEVRD_RESET 0x00000003
1392 #define ALT_QSPI_DEVRD_OFST 0x4
1420 #define ALT_QSPI_DEVWR_WROPCODE_LSB 0
1422 #define ALT_QSPI_DEVWR_WROPCODE_MSB 7
1424 #define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8
1426 #define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff
1428 #define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00
1430 #define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2
1432 #define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0)
1434 #define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff)
1443 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_LSB 8
1445 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_MSB 11
1447 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_WIDTH 4
1449 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET_MSK 0x00000f00
1451 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_CLR_MSK 0xfffff0ff
1453 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_RESET 0x0
1455 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_GET(value) (((value) & 0x00000f00) >> 8)
1457 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET(value) (((value) << 8) & 0x00000f00)
1491 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0
1499 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1
1507 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2
1510 #define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12
1512 #define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13
1514 #define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2
1516 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000
1518 #define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff
1520 #define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0
1522 #define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1524 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1533 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_LSB 14
1535 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_MSB 15
1537 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_WIDTH 2
1539 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET_MSK 0x0000c000
1541 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff
1543 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_RESET 0x0
1545 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_GET(value) (((value) & 0x0000c000) >> 14)
1547 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET(value) (((value) << 14) & 0x0000c000)
1583 #define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0
1591 #define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1
1599 #define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2
1602 #define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16
1604 #define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17
1606 #define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2
1608 #define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000
1610 #define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff
1612 #define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0
1614 #define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1616 #define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1625 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_LSB 18
1627 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_MSB 23
1629 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_WIDTH 6
1631 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET_MSK 0x00fc0000
1633 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_CLR_MSK 0xff03ffff
1635 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_RESET 0x0
1637 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_GET(value) (((value) & 0x00fc0000) >> 18)
1639 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET(value) (((value) << 18) & 0x00fc0000)
1650 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24
1652 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28
1654 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5
1656 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000
1658 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff
1660 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0
1662 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1664 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000)
1673 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_LSB 29
1675 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_MSB 31
1677 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_WIDTH 3
1679 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET_MSK 0xe0000000
1681 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_CLR_MSK 0x1fffffff
1683 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_RESET 0x0
1685 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_GET(value) (((value) & 0xe0000000) >> 29)
1687 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET(value) (((value) << 29) & 0xe0000000)
1689 #ifndef __ASSEMBLY__
1700 struct ALT_QSPI_DEVWR_s
1702 uint32_t wropcode : 8;
1703 const uint32_t wr_instr_resv1_fld : 4;
1704 uint32_t addrwidth : 2;
1705 const uint32_t wr_instr_resv2_fld : 2;
1706 uint32_t datawidth : 2;
1707 const uint32_t wr_instr_resv3_fld : 6;
1708 uint32_t dummywrclks : 5;
1709 const uint32_t wr_instr_resv4_fld : 3;
1713 typedef volatile struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t;
1717 #define ALT_QSPI_DEVWR_RESET 0x00000002
1719 #define ALT_QSPI_DEVWR_OFST 0x8
1748 #define ALT_QSPI_DELAY_INIT_LSB 0
1750 #define ALT_QSPI_DELAY_INIT_MSB 7
1752 #define ALT_QSPI_DELAY_INIT_WIDTH 8
1754 #define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff
1756 #define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00
1758 #define ALT_QSPI_DELAY_INIT_RESET 0x0
1760 #define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0)
1762 #define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff)
1775 #define ALT_QSPI_DELAY_AFTER_LSB 8
1777 #define ALT_QSPI_DELAY_AFTER_MSB 15
1779 #define ALT_QSPI_DELAY_AFTER_WIDTH 8
1781 #define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00
1783 #define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff
1785 #define ALT_QSPI_DELAY_AFTER_RESET 0x0
1787 #define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8)
1789 #define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00)
1802 #define ALT_QSPI_DELAY_BTWN_LSB 16
1804 #define ALT_QSPI_DELAY_BTWN_MSB 23
1806 #define ALT_QSPI_DELAY_BTWN_WIDTH 8
1808 #define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000
1810 #define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff
1812 #define ALT_QSPI_DELAY_BTWN_RESET 0x0
1814 #define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16)
1816 #define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000)
1829 #define ALT_QSPI_DELAY_NSS_LSB 24
1831 #define ALT_QSPI_DELAY_NSS_MSB 31
1833 #define ALT_QSPI_DELAY_NSS_WIDTH 8
1835 #define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000
1837 #define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff
1839 #define ALT_QSPI_DELAY_NSS_RESET 0x0
1841 #define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24)
1843 #define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000)
1845 #ifndef __ASSEMBLY__
1856 struct ALT_QSPI_DELAY_s
1865 typedef volatile struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t;
1869 #define ALT_QSPI_DELAY_RESET 0x00000000
1871 #define ALT_QSPI_DELAY_OFST 0xc
1905 #define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x0
1911 #define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x1
1914 #define ALT_QSPI_RDDATACAP_BYP_LSB 0
1916 #define ALT_QSPI_RDDATACAP_BYP_MSB 0
1918 #define ALT_QSPI_RDDATACAP_BYP_WIDTH 1
1920 #define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001
1922 #define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe
1924 #define ALT_QSPI_RDDATACAP_BYP_RESET 0x1
1926 #define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0)
1928 #define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001)
1939 #define ALT_QSPI_RDDATACAP_DELAY_LSB 1
1941 #define ALT_QSPI_RDDATACAP_DELAY_MSB 4
1943 #define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4
1945 #define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e
1947 #define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1
1949 #define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0
1951 #define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1)
1953 #define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e)
1962 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_LSB 5
1964 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_MSB 31
1966 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_WIDTH 27
1968 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_SET_MSK 0xffffffe0
1970 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_CLR_MSK 0x0000001f
1972 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_RESET 0x0
1974 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_GET(value) (((value) & 0xffffffe0) >> 5)
1976 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_SET(value) (((value) << 5) & 0xffffffe0)
1978 #ifndef __ASSEMBLY__
1989 struct ALT_QSPI_RDDATACAP_s
1993 const uint32_t rd_data_resv_fld : 27;
1997 typedef volatile struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t;
2001 #define ALT_QSPI_RDDATACAP_RESET 0x00000001
2003 #define ALT_QSPI_RDDATACAP_OFST 0x10
2027 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0
2029 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3
2031 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4
2033 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f
2035 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0
2037 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2
2039 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0)
2041 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f)
2053 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4
2055 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15
2057 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12
2059 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0
2061 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f
2063 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100
2065 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4)
2067 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0)
2080 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16
2082 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20
2084 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5
2086 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000
2088 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff
2090 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10
2092 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16)
2094 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000)
2103 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_LSB 21
2105 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_MSB 31
2107 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_WIDTH 11
2109 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_SET_MSK 0xffe00000
2111 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_CLR_MSK 0x001fffff
2113 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_RESET 0x0
2115 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_GET(value) (((value) & 0xffe00000) >> 21)
2117 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_SET(value) (((value) << 21) & 0xffe00000)
2119 #ifndef __ASSEMBLY__
2130 struct ALT_QSPI_DEVSZ_s
2132 uint32_t numaddrbytes : 4;
2133 uint32_t bytesperdevicepage : 12;
2134 uint32_t bytespersubsector : 5;
2135 const uint32_t dev_size_resv_fld : 11;
2139 typedef volatile struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t;
2143 #define ALT_QSPI_DEVSZ_RESET 0x00101002
2145 #define ALT_QSPI_DEVSZ_OFST 0x14
2170 #define ALT_QSPI_SRAMPART_ADDR_LSB 0
2172 #define ALT_QSPI_SRAMPART_ADDR_MSB 7
2174 #define ALT_QSPI_SRAMPART_ADDR_WIDTH 8
2176 #define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x000000ff
2178 #define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff00
2180 #define ALT_QSPI_SRAMPART_ADDR_RESET 0x80
2182 #define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x000000ff) >> 0)
2184 #define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x000000ff)
2193 #define ALT_QSPI_SRAMPART_RESV_FLD_LSB 8
2195 #define ALT_QSPI_SRAMPART_RESV_FLD_MSB 31
2197 #define ALT_QSPI_SRAMPART_RESV_FLD_WIDTH 24
2199 #define ALT_QSPI_SRAMPART_RESV_FLD_SET_MSK 0xffffff00
2201 #define ALT_QSPI_SRAMPART_RESV_FLD_CLR_MSK 0x000000ff
2203 #define ALT_QSPI_SRAMPART_RESV_FLD_RESET 0x0
2205 #define ALT_QSPI_SRAMPART_RESV_FLD_GET(value) (((value) & 0xffffff00) >> 8)
2207 #define ALT_QSPI_SRAMPART_RESV_FLD_SET(value) (((value) << 8) & 0xffffff00)
2209 #ifndef __ASSEMBLY__
2220 struct ALT_QSPI_SRAMPART_s
2223 const uint32_t resv_fld : 24;
2227 typedef volatile struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t;
2231 #define ALT_QSPI_SRAMPART_RESET 0x00000080
2233 #define ALT_QSPI_SRAMPART_OFST 0x18
2257 #define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0
2259 #define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31
2261 #define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32
2263 #define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff
2265 #define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000
2267 #define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0
2269 #define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
2271 #define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff)
2273 #ifndef __ASSEMBLY__
2284 struct ALT_QSPI_INDADDRTRIG_s
2290 typedef volatile struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t;
2294 #define ALT_QSPI_INDADDRTRIG_RESET 0x00000000
2296 #define ALT_QSPI_INDADDRTRIG_OFST 0x1c
2323 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0
2325 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3
2327 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4
2329 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f
2331 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0
2333 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0
2335 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0)
2337 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f)
2346 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_LSB 4
2348 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_MSB 7
2350 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_WIDTH 4
2352 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_SET_MSK 0x000000f0
2354 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_CLR_MSK 0xffffff0f
2356 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_RESET 0x0
2358 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_GET(value) (((value) & 0x000000f0) >> 4)
2360 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_SET(value) (((value) << 4) & 0x000000f0)
2374 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8
2376 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11
2378 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4
2380 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00
2382 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff
2384 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0
2386 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8)
2388 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00)
2397 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_LSB 12
2399 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_MSB 31
2401 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_WIDTH 20
2403 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_SET_MSK 0xfffff000
2405 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_CLR_MSK 0x00000fff
2407 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_RESET 0x0
2409 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_GET(value) (((value) & 0xfffff000) >> 12)
2411 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_SET(value) (((value) << 12) & 0xfffff000)
2413 #ifndef __ASSEMBLY__
2424 struct ALT_QSPI_DMAPER_s
2426 uint32_t numsglreqbytes : 4;
2427 const uint32_t dma_periph_resv1_fld : 4;
2428 uint32_t numburstreqbytes : 4;
2429 const uint32_t dma_periph_resv2_fld : 20;
2433 typedef volatile struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t;
2437 #define ALT_QSPI_DMAPER_RESET 0x00000000
2439 #define ALT_QSPI_DMAPER_OFST 0x20
2461 #define ALT_QSPI_REMAPADDR_VALUE_LSB 0
2463 #define ALT_QSPI_REMAPADDR_VALUE_MSB 31
2465 #define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32
2467 #define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff
2469 #define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000
2471 #define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0
2473 #define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
2475 #define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
2477 #ifndef __ASSEMBLY__
2488 struct ALT_QSPI_REMAPADDR_s
2490 uint32_t value : 32;
2494 typedef volatile struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t;
2498 #define ALT_QSPI_REMAPADDR_RESET 0x00000000
2500 #define ALT_QSPI_REMAPADDR_OFST 0x24
2523 #define ALT_QSPI_MODBIT_MOD_LSB 0
2525 #define ALT_QSPI_MODBIT_MOD_MSB 7
2527 #define ALT_QSPI_MODBIT_MOD_WIDTH 8
2529 #define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff
2531 #define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00
2533 #define ALT_QSPI_MODBIT_MOD_RESET 0x0
2535 #define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0)
2537 #define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff)
2546 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_LSB 8
2548 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_MSB 31
2550 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_WIDTH 24
2552 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_SET_MSK 0xffffff00
2554 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_CLR_MSK 0x000000ff
2556 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_RESET 0x0
2558 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_GET(value) (((value) & 0xffffff00) >> 8)
2560 #define ALT_QSPI_MODBIT_MOD_RESV_FLD_SET(value) (((value) << 8) & 0xffffff00)
2562 #ifndef __ASSEMBLY__
2573 struct ALT_QSPI_MODBIT_s
2576 const uint32_t mode_resv_fld : 24;
2580 typedef volatile struct ALT_QSPI_MODBIT_s ALT_QSPI_MODBIT_t;
2584 #define ALT_QSPI_MODBIT_RESET 0x00000000
2586 #define ALT_QSPI_MODBIT_OFST 0x28
2608 #define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0
2610 #define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15
2612 #define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16
2614 #define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff
2616 #define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000
2618 #define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0
2620 #define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0)
2622 #define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff)
2633 #define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16
2635 #define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31
2637 #define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16
2639 #define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000
2641 #define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff
2643 #define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0
2645 #define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16)
2647 #define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000)
2649 #ifndef __ASSEMBLY__
2660 struct ALT_QSPI_SRAMFILL_s
2662 const uint32_t indrdpart : 16;
2663 const uint32_t indwrpart : 16;
2667 typedef volatile struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t;
2671 #define ALT_QSPI_SRAMFILL_RESET 0x00000000
2673 #define ALT_QSPI_SRAMFILL_OFST 0x2c
2695 #define ALT_QSPI_TXTHRESH_LEVEL_LSB 0
2697 #define ALT_QSPI_TXTHRESH_LEVEL_MSB 3
2699 #define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4
2701 #define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f
2703 #define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2705 #define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1
2707 #define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2709 #define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2718 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_LSB 4
2720 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_MSB 31
2722 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_WIDTH 28
2724 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_SET_MSK 0xfffffff0
2726 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_CLR_MSK 0x0000000f
2728 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_RESET 0x0
2730 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_GET(value) (((value) & 0xfffffff0) >> 4)
2732 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_SET(value) (((value) << 4) & 0xfffffff0)
2734 #ifndef __ASSEMBLY__
2745 struct ALT_QSPI_TXTHRESH_s
2748 const uint32_t tx_thresh_resv_fld : 28;
2752 typedef volatile struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t;
2756 #define ALT_QSPI_TXTHRESH_RESET 0x00000001
2758 #define ALT_QSPI_TXTHRESH_OFST 0x30
2782 #define ALT_QSPI_RXTHRESH_LEVEL_LSB 0
2784 #define ALT_QSPI_RXTHRESH_LEVEL_MSB 3
2786 #define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4
2788 #define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f
2790 #define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2792 #define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1
2794 #define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2796 #define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2805 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_LSB 4
2807 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_MSB 31
2809 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_WIDTH 28
2811 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_SET_MSK 0xfffffff0
2813 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_CLR_MSK 0x0000000f
2815 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_RESET 0x0
2817 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_GET(value) (((value) & 0xfffffff0) >> 4)
2819 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_SET(value) (((value) << 4) & 0xfffffff0)
2821 #ifndef __ASSEMBLY__
2832 struct ALT_QSPI_RXTHRESH_s
2835 const uint32_t rx_thresh_resv_fld : 28;
2839 typedef volatile struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t;
2843 #define ALT_QSPI_RXTHRESH_RESET 0x00000001
2845 #define ALT_QSPI_RXTHRESH_OFST 0x34
2889 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_LSB 0
2891 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_MSB 0
2893 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_WIDTH 1
2895 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_SET_MSK 0x00000001
2897 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_CLR_MSK 0xfffffffe
2899 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_RESET 0x0
2901 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_GET(value) (((value) & 0x00000001) >> 0)
2903 #define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_SET(value) (((value) << 0) & 0x00000001)
2929 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0
2935 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1
2938 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1
2940 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1
2942 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1
2944 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002
2946 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd
2948 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0
2950 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
2952 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
2974 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0
2980 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1
2983 #define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2
2985 #define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2
2987 #define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1
2989 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004
2991 #define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb
2993 #define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0
2995 #define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
2997 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
3020 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0
3026 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1
3029 #define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3
3031 #define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3
3033 #define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1
3035 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008
3037 #define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7
3039 #define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0
3041 #define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3043 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3065 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0
3071 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1
3074 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4
3076 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4
3078 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1
3080 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010
3082 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef
3084 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0
3086 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3088 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3111 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0
3117 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1
3120 #define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5
3122 #define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5
3124 #define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1
3126 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020
3128 #define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf
3130 #define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0
3132 #define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3134 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3156 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0
3162 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1
3165 #define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6
3167 #define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6
3169 #define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1
3171 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040
3173 #define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf
3175 #define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0
3177 #define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3179 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3205 #define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0
3211 #define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1
3214 #define ALT_QSPI_IRQSTAT_RXOVER_LSB 7
3216 #define ALT_QSPI_IRQSTAT_RXOVER_MSB 7
3218 #define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1
3220 #define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080
3222 #define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f
3224 #define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0
3226 #define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3228 #define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3251 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0
3257 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1
3260 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8
3262 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8
3264 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1
3266 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100
3268 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff
3270 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1
3272 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3274 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3297 #define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0
3303 #define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1
3306 #define ALT_QSPI_IRQSTAT_TXFULL_LSB 9
3308 #define ALT_QSPI_IRQSTAT_TXFULL_MSB 9
3310 #define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1
3312 #define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200
3314 #define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff
3316 #define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0
3318 #define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
3320 #define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200)
3343 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0
3349 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1
3352 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10
3354 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10
3356 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1
3358 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400
3360 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff
3362 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0
3364 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
3366 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
3389 #define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0
3395 #define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1
3398 #define ALT_QSPI_IRQSTAT_RXFULL_LSB 11
3400 #define ALT_QSPI_IRQSTAT_RXFULL_MSB 11
3402 #define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1
3404 #define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800
3406 #define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff
3408 #define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0
3410 #define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
3412 #define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800)
3435 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0
3441 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1
3444 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12
3446 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12
3448 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1
3450 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000
3452 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff
3454 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0
3456 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
3458 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
3467 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_LSB 13
3469 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_MSB 31
3471 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_WIDTH 19
3473 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_SET_MSK 0xffffe000
3475 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_CLR_MSK 0x00001fff
3477 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_RESET 0x0
3479 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_GET(value) (((value) & 0xffffe000) >> 13)
3481 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_SET(value) (((value) << 13) & 0xffffe000)
3483 #ifndef __ASSEMBLY__
3494 struct ALT_QSPI_IRQSTAT_s
3496 uint32_t mode_m_fail_fld : 1;
3497 uint32_t underflowdet : 1;
3498 uint32_t indopdone : 1;
3499 uint32_t indrdreject : 1;
3500 uint32_t protwrattempt : 1;
3501 uint32_t illegalacc : 1;
3502 uint32_t indxfrlvl : 1;
3503 uint32_t rxover : 1;
3504 uint32_t txthreshcmp : 1;
3505 uint32_t txfull : 1;
3506 uint32_t rxthreshcmp : 1;
3507 uint32_t rxfull : 1;
3508 uint32_t indsramfull : 1;
3509 const uint32_t irq_stat_resv_fld : 19;
3513 typedef volatile struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t;
3517 #define ALT_QSPI_IRQSTAT_RESET 0x00000100
3519 #define ALT_QSPI_IRQSTAT_OFST 0x40
3555 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_LSB 0
3557 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_MSB 0
3559 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_WIDTH 1
3561 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_SET_MSK 0x00000001
3563 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_CLR_MSK 0xfffffffe
3565 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_RESET 0x0
3567 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_GET(value) (((value) & 0x00000001) >> 0)
3569 #define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_SET(value) (((value) << 0) & 0x00000001)
3589 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0
3595 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1
3598 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1
3600 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1
3602 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1
3604 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002
3606 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd
3608 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0
3610 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
3612 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
3632 #define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0
3638 #define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1
3641 #define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2
3643 #define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2
3645 #define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1
3647 #define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004
3649 #define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb
3651 #define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0
3653 #define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
3655 #define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
3675 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0
3681 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1
3684 #define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3
3686 #define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3
3688 #define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1
3690 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008
3692 #define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7
3694 #define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0
3696 #define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3698 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3718 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0
3724 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1
3727 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4
3729 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4
3731 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1
3733 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010
3735 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef
3737 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0
3739 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3741 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3761 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0
3767 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1
3770 #define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5
3772 #define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5
3774 #define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1
3776 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020
3778 #define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf
3780 #define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0
3782 #define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3784 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3804 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0
3810 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1
3813 #define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6
3815 #define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6
3817 #define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1
3819 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040
3821 #define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf
3823 #define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0
3825 #define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3827 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3847 #define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0
3853 #define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1
3856 #define ALT_QSPI_IRQMSK_RXOVER_LSB 7
3858 #define ALT_QSPI_IRQMSK_RXOVER_MSB 7
3860 #define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1
3862 #define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080
3864 #define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f
3866 #define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0
3868 #define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3870 #define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3890 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0
3896 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1
3899 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8
3901 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8
3903 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1
3905 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100
3907 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff
3909 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0
3911 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3913 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3933 #define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0
3939 #define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1
3942 #define ALT_QSPI_IRQMSK_TXFULL_LSB 9
3944 #define ALT_QSPI_IRQMSK_TXFULL_MSB 9
3946 #define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1
3948 #define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200
3950 #define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff
3952 #define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0
3954 #define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
3956 #define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200)
3976 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0
3982 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1
3985 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10
3987 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10
3989 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1
3991 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400
3993 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff
3995 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0
3997 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
3999 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
4019 #define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0
4025 #define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1
4028 #define ALT_QSPI_IRQMSK_RXFULL_LSB 11
4030 #define ALT_QSPI_IRQMSK_RXFULL_MSB 11
4032 #define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1
4034 #define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800
4036 #define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff
4038 #define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0
4040 #define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
4042 #define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800)
4062 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0
4068 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1
4071 #define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12
4073 #define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12
4075 #define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1
4077 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000
4079 #define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff
4081 #define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0
4083 #define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
4085 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
4094 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_LSB 13
4096 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_MSB 31
4098 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_WIDTH 19
4100 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_SET_MSK 0xffffe000
4102 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_CLR_MSK 0x00001fff
4104 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_RESET 0x0
4106 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_GET(value) (((value) & 0xffffe000) >> 13)
4108 #define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_SET(value) (((value) << 13) & 0xffffe000)
4110 #ifndef __ASSEMBLY__
4121 struct ALT_QSPI_IRQMSK_s
4123 uint32_t mode_m_fail_mask_fld : 1;
4124 uint32_t underflowdet : 1;
4125 uint32_t indopdone : 1;
4126 uint32_t indrdreject : 1;
4127 uint32_t protwrattempt : 1;
4128 uint32_t illegalacc : 1;
4129 uint32_t indxfrlvl : 1;
4130 uint32_t rxover : 1;
4131 uint32_t txthreshcmp : 1;
4132 uint32_t txfull : 1;
4133 uint32_t rxthreshcmp : 1;
4134 uint32_t rxfull : 1;
4135 uint32_t indsramfull : 1;
4136 const uint32_t irq_mask_resv_fld : 19;
4140 typedef volatile struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t;
4144 #define ALT_QSPI_IRQMSK_RESET 0x00000000
4146 #define ALT_QSPI_IRQMSK_OFST 0x44
4169 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0
4171 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31
4173 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32
4175 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff
4177 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000
4179 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0
4181 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
4183 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
4185 #ifndef __ASSEMBLY__
4196 struct ALT_QSPI_LOWWRPROT_s
4198 uint32_t subsector : 32;
4202 typedef volatile struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t;
4206 #define ALT_QSPI_LOWWRPROT_RESET 0x00000000
4208 #define ALT_QSPI_LOWWRPROT_OFST 0x50
4231 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0
4233 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31
4235 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32
4237 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff
4239 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000
4241 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0
4243 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
4245 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
4247 #ifndef __ASSEMBLY__
4258 struct ALT_QSPI_UPPWRPROT_s
4260 uint32_t subsector : 32;
4264 typedef volatile struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t;
4268 #define ALT_QSPI_UPPWRPROT_RESET 0x00000000
4270 #define ALT_QSPI_UPPWRPROT_OFST 0x54
4308 #define ALT_QSPI_WRPROT_INV_E_DIS 0x0
4314 #define ALT_QSPI_WRPROT_INV_E_EN 0x1
4317 #define ALT_QSPI_WRPROT_INV_LSB 0
4319 #define ALT_QSPI_WRPROT_INV_MSB 0
4321 #define ALT_QSPI_WRPROT_INV_WIDTH 1
4323 #define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001
4325 #define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe
4327 #define ALT_QSPI_WRPROT_INV_RESET 0x0
4329 #define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0)
4331 #define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001)
4356 #define ALT_QSPI_WRPROT_EN_E_DIS 0x0
4362 #define ALT_QSPI_WRPROT_EN_E_EN 0x1
4365 #define ALT_QSPI_WRPROT_EN_LSB 1
4367 #define ALT_QSPI_WRPROT_EN_MSB 1
4369 #define ALT_QSPI_WRPROT_EN_WIDTH 1
4371 #define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002
4373 #define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd
4375 #define ALT_QSPI_WRPROT_EN_RESET 0x0
4377 #define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1)
4379 #define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002)
4388 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_LSB 2
4390 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_MSB 31
4392 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_WIDTH 30
4394 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_SET_MSK 0xfffffffc
4396 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_CLR_MSK 0x00000003
4398 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_RESET 0x0
4400 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_GET(value) (((value) & 0xfffffffc) >> 2)
4402 #define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_SET(value) (((value) << 2) & 0xfffffffc)
4404 #ifndef __ASSEMBLY__
4415 struct ALT_QSPI_WRPROT_s
4419 const uint32_t wr_prot_ctrl_resv_fld : 30;
4423 typedef volatile struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t;
4427 #define ALT_QSPI_WRPROT_RESET 0x00000000
4429 #define ALT_QSPI_WRPROT_OFST 0x58
4470 #define ALT_QSPI_INDRD_START_E_DISD 0x0
4476 #define ALT_QSPI_INDRD_START_E_END 0x1
4479 #define ALT_QSPI_INDRD_START_LSB 0
4481 #define ALT_QSPI_INDRD_START_MSB 0
4483 #define ALT_QSPI_INDRD_START_WIDTH 1
4485 #define ALT_QSPI_INDRD_START_SET_MSK 0x00000001
4487 #define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe
4489 #define ALT_QSPI_INDRD_START_RESET 0x0
4491 #define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0)
4493 #define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001)
4515 #define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0
4521 #define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1
4524 #define ALT_QSPI_INDRD_CANCEL_LSB 1
4526 #define ALT_QSPI_INDRD_CANCEL_MSB 1
4528 #define ALT_QSPI_INDRD_CANCEL_WIDTH 1
4530 #define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002
4532 #define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd
4534 #define ALT_QSPI_INDRD_CANCEL_RESET 0x0
4536 #define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
4538 #define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002)
4560 #define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0
4566 #define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1
4569 #define ALT_QSPI_INDRD_RD_STAT_LSB 2
4571 #define ALT_QSPI_INDRD_RD_STAT_MSB 2
4573 #define ALT_QSPI_INDRD_RD_STAT_WIDTH 1
4575 #define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004
4577 #define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb
4579 #define ALT_QSPI_INDRD_RD_STAT_RESET 0x0
4581 #define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2)
4583 #define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004)
4606 #define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0
4612 #define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1
4615 #define ALT_QSPI_INDRD_SRAM_FULL_LSB 3
4617 #define ALT_QSPI_INDRD_SRAM_FULL_MSB 3
4619 #define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1
4621 #define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008
4623 #define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7
4625 #define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0
4627 #define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3)
4629 #define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008)
4651 #define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0
4657 #define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1
4660 #define ALT_QSPI_INDRD_RD_QUEUED_LSB 4
4662 #define ALT_QSPI_INDRD_RD_QUEUED_MSB 4
4664 #define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1
4666 #define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010
4668 #define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef
4670 #define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0
4672 #define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4)
4674 #define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010)
4697 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0
4703 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1
4706 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5
4708 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5
4710 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1
4712 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020
4714 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf
4716 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0
4718 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5)
4720 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020)
4734 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6
4736 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7
4738 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2
4740 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0
4742 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f
4744 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0
4746 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6)
4748 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0)
4757 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_LSB 8
4759 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_MSB 31
4761 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_WIDTH 24
4763 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_SET_MSK 0xffffff00
4765 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_CLR_MSK 0x000000ff
4767 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_RESET 0x0
4769 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_GET(value) (((value) & 0xffffff00) >> 8)
4771 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_SET(value) (((value) << 8) & 0xffffff00)
4773 #ifndef __ASSEMBLY__
4784 struct ALT_QSPI_INDRD_s
4787 uint32_t cancel : 1;
4788 const uint32_t rd_status : 1;
4789 uint32_t sram_full : 1;
4790 const uint32_t rd_queued : 1;
4791 uint32_t ind_ops_done_status : 1;
4792 const uint32_t num_ind_ops_done : 2;
4793 const uint32_t indir_rd_xfer_resv_fld : 24;
4797 typedef volatile struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t;
4801 #define ALT_QSPI_INDRD_RESET 0x00000000
4803 #define ALT_QSPI_INDRD_OFST 0x60
4826 #define ALT_QSPI_INDRDWATER_LEVEL_LSB 0
4828 #define ALT_QSPI_INDRDWATER_LEVEL_MSB 31
4830 #define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32
4832 #define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff
4834 #define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000
4836 #define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0
4838 #define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
4840 #define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
4842 #ifndef __ASSEMBLY__
4853 struct ALT_QSPI_INDRDWATER_s
4855 uint32_t level : 32;
4859 typedef volatile struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t;
4863 #define ALT_QSPI_INDRDWATER_RESET 0x00000000
4865 #define ALT_QSPI_INDRDWATER_OFST 0x64
4887 #define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0
4889 #define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31
4891 #define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32
4893 #define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff
4895 #define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000
4897 #define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0
4899 #define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4901 #define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4903 #ifndef __ASSEMBLY__
4914 struct ALT_QSPI_INDRDSTADDR_s
4920 typedef volatile struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t;
4924 #define ALT_QSPI_INDRDSTADDR_RESET 0x00000000
4926 #define ALT_QSPI_INDRDSTADDR_OFST 0x68
4948 #define ALT_QSPI_INDRDCNT_VALUE_LSB 0
4950 #define ALT_QSPI_INDRDCNT_VALUE_MSB 31
4952 #define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32
4954 #define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff
4956 #define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000
4958 #define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0
4960 #define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4962 #define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4964 #ifndef __ASSEMBLY__
4975 struct ALT_QSPI_INDRDCNT_s
4977 uint32_t value : 32;
4981 typedef volatile struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t;
4985 #define ALT_QSPI_INDRDCNT_RESET 0x00000000
4987 #define ALT_QSPI_INDRDCNT_OFST 0x6c
5028 #define ALT_QSPI_INDWR_START_E_DISD 0x0
5034 #define ALT_QSPI_INDWR_START_E_END 0x1
5037 #define ALT_QSPI_INDWR_START_LSB 0
5039 #define ALT_QSPI_INDWR_START_MSB 0
5041 #define ALT_QSPI_INDWR_START_WIDTH 1
5043 #define ALT_QSPI_INDWR_START_SET_MSK 0x00000001
5045 #define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe
5047 #define ALT_QSPI_INDWR_START_RESET 0x0
5049 #define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0)
5051 #define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001)
5073 #define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0
5079 #define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1
5082 #define ALT_QSPI_INDWR_CANCEL_LSB 1
5084 #define ALT_QSPI_INDWR_CANCEL_MSB 1
5086 #define ALT_QSPI_INDWR_CANCEL_WIDTH 1
5088 #define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002
5090 #define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd
5092 #define ALT_QSPI_INDWR_CANCEL_RESET 0x0
5094 #define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
5096 #define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002)
5118 #define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0
5124 #define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1
5127 #define ALT_QSPI_INDWR_RDSTAT_LSB 2
5129 #define ALT_QSPI_INDWR_RDSTAT_MSB 2
5131 #define ALT_QSPI_INDWR_RDSTAT_WIDTH 1
5133 #define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004
5135 #define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb
5137 #define ALT_QSPI_INDWR_RDSTAT_RESET 0x0
5139 #define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2)
5141 #define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004)
5150 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_LSB 3
5152 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_MSB 3
5154 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_WIDTH 1
5156 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_SET_MSK 0x00000008
5158 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_CLR_MSK 0xfffffff7
5160 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_RESET 0x0
5162 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_GET(value) (((value) & 0x00000008) >> 3)
5164 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_SET(value) (((value) << 3) & 0x00000008)
5186 #define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0
5192 #define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1
5195 #define ALT_QSPI_INDWR_RDQUEUED_LSB 4
5197 #define ALT_QSPI_INDWR_RDQUEUED_MSB 4
5199 #define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1
5201 #define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010
5203 #define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef
5205 #define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0
5207 #define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4)
5209 #define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010)
5232 #define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0
5238 #define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1
5241 #define ALT_QSPI_INDWR_INDDONE_LSB 5
5243 #define ALT_QSPI_INDWR_INDDONE_MSB 5
5245 #define ALT_QSPI_INDWR_INDDONE_WIDTH 1
5247 #define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020
5249 #define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf
5251 #define ALT_QSPI_INDWR_INDDONE_RESET 0x0
5253 #define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5)
5255 #define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020)
5269 #define ALT_QSPI_INDWR_INDCNT_LSB 6
5271 #define ALT_QSPI_INDWR_INDCNT_MSB 7
5273 #define ALT_QSPI_INDWR_INDCNT_WIDTH 2
5275 #define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0
5277 #define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f
5279 #define ALT_QSPI_INDWR_INDCNT_RESET 0x0
5281 #define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6)
5283 #define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0)
5292 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_LSB 8
5294 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_MSB 31
5296 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_WIDTH 24
5298 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_SET_MSK 0xffffff00
5300 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_CLR_MSK 0x000000ff
5302 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_RESET 0x0
5304 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_GET(value) (((value) & 0xffffff00) >> 8)
5306 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_SET(value) (((value) << 8) & 0xffffff00)
5308 #ifndef __ASSEMBLY__
5319 struct ALT_QSPI_INDWR_s
5322 uint32_t cancel : 1;
5323 const uint32_t rdstat : 1;
5324 const uint32_t indir_wr_rsvd_fld : 1;
5325 const uint32_t rdqueued : 1;
5326 uint32_t inddone : 1;
5327 const uint32_t indcnt : 2;
5328 const uint32_t indir_wr_xfer_resv2_fld : 24;
5332 typedef volatile struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t;
5336 #define ALT_QSPI_INDWR_RESET 0x00000000
5338 #define ALT_QSPI_INDWR_OFST 0x70
5362 #define ALT_QSPI_INDWRWATER_LEVEL_LSB 0
5364 #define ALT_QSPI_INDWRWATER_LEVEL_MSB 31
5366 #define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32
5368 #define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff
5370 #define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000
5372 #define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff
5374 #define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
5376 #define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
5378 #ifndef __ASSEMBLY__
5389 struct ALT_QSPI_INDWRWATER_s
5391 uint32_t level : 32;
5395 typedef volatile struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t;
5399 #define ALT_QSPI_INDWRWATER_RESET 0xffffffff
5401 #define ALT_QSPI_INDWRWATER_OFST 0x74
5423 #define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0
5425 #define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31
5427 #define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32
5429 #define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff
5431 #define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000
5433 #define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0
5435 #define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
5437 #define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
5439 #ifndef __ASSEMBLY__
5450 struct ALT_QSPI_INDWRSTADDR_s
5456 typedef volatile struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t;
5460 #define ALT_QSPI_INDWRSTADDR_RESET 0x00000000
5462 #define ALT_QSPI_INDWRSTADDR_OFST 0x78
5484 #define ALT_QSPI_INDWRCNT_VALUE_LSB 0
5486 #define ALT_QSPI_INDWRCNT_VALUE_MSB 31
5488 #define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32
5490 #define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff
5492 #define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000
5494 #define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0
5496 #define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
5498 #define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
5500 #ifndef __ASSEMBLY__
5511 struct ALT_QSPI_INDWRCNT_s
5513 uint32_t value : 32;
5517 typedef volatile struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t;
5521 #define ALT_QSPI_INDWRCNT_RESET 0x00000000
5523 #define ALT_QSPI_INDWRCNT_OFST 0x7c
5566 #define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0
5572 #define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1
5575 #define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0
5577 #define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0
5579 #define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1
5581 #define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001
5583 #define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe
5585 #define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0
5587 #define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0)
5589 #define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001)
5611 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0
5617 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1
5620 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1
5622 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1
5624 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1
5626 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002
5628 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd
5630 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0
5632 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1)
5634 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002)
5643 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_LSB 2
5645 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_MSB 6
5647 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_WIDTH 5
5649 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_SET_MSK 0x0000007c
5651 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_CLR_MSK 0xffffff83
5653 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_RESET 0x0
5655 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_GET(value) (((value) & 0x0000007c) >> 2)
5657 #define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_SET(value) (((value) << 2) & 0x0000007c)
5669 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7
5671 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11
5673 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5
5675 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80
5677 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f
5679 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0
5681 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7)
5683 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80)
5712 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0
5718 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1
5724 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2
5730 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3
5736 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4
5742 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5
5748 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6
5754 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7
5757 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12
5759 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14
5761 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3
5763 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000
5765 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff
5767 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0
5769 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12)
5771 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000)
5794 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0
5800 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1
5803 #define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15
5805 #define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15
5807 #define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1
5809 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000
5811 #define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff
5813 #define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0
5815 #define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15)
5817 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000)
5844 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0
5850 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1
5856 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2
5862 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3
5865 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16
5867 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17
5869 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2
5871 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000
5873 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff
5875 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0
5877 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16)
5879 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000)
5902 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0
5908 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1
5911 #define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18
5913 #define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18
5915 #define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1
5917 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000
5919 #define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff
5921 #define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0
5923 #define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18)
5925 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000)
5948 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0
5954 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1
5957 #define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19
5959 #define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19
5961 #define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1
5963 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000
5965 #define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff
5967 #define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0
5969 #define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19)
5971 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000)
6000 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0
6006 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1
6012 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2
6018 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3
6024 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4
6030 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5
6036 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6
6042 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7
6045 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20
6047 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22
6049 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3
6051 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000
6053 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff
6055 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0
6057 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20)
6059 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000)
6082 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0
6088 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1
6091 #define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23
6093 #define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23
6095 #define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1
6097 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000
6099 #define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff
6101 #define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0
6103 #define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23)
6105 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000)
6126 #define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24
6128 #define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31
6130 #define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8
6132 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000
6134 #define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff
6136 #define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0
6138 #define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24)
6140 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000)
6142 #ifndef __ASSEMBLY__
6153 struct ALT_QSPI_FLSHCMD_s
6155 uint32_t execcmd : 1;
6156 const uint32_t cmdexecstat : 1;
6157 const uint32_t flash_cmd_cntrl_resv1_fld : 5;
6158 uint32_t numdummybytes : 5;
6159 uint32_t numwrdatabytes : 3;
6160 uint32_t enwrdata : 1;
6161 uint32_t numaddrbytes : 2;
6162 uint32_t enmodebit : 1;
6163 uint32_t encmdaddr : 1;
6164 uint32_t numrddatabytes : 3;
6165 uint32_t enrddata : 1;
6166 uint32_t cmdopcode : 8;
6170 typedef volatile struct ALT_QSPI_FLSHCMD_s ALT_QSPI_FLSHCMD_t;
6174 #define ALT_QSPI_FLSHCMD_RESET 0x00000000
6176 #define ALT_QSPI_FLSHCMD_OFST 0x90
6200 #define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0
6202 #define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31
6204 #define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32
6206 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff
6208 #define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000
6210 #define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0
6212 #define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
6214 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
6216 #ifndef __ASSEMBLY__
6227 struct ALT_QSPI_FLSHCMDADDR_s
6233 typedef volatile struct ALT_QSPI_FLSHCMDADDR_s ALT_QSPI_FLSHCMDADDR_t;
6237 #define ALT_QSPI_FLSHCMDADDR_RESET 0x00000000
6239 #define ALT_QSPI_FLSHCMDADDR_OFST 0x94
6263 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0
6265 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31
6267 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32
6269 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff
6271 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000
6273 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0
6275 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6277 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
6279 #ifndef __ASSEMBLY__
6290 struct ALT_QSPI_FLSHCMDRDDATALO_s
6296 typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s ALT_QSPI_FLSHCMDRDDATALO_t;
6300 #define ALT_QSPI_FLSHCMDRDDATALO_RESET 0x00000000
6302 #define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0
6328 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0
6330 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31
6332 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32
6334 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff
6336 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000
6338 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0
6340 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6342 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
6344 #ifndef __ASSEMBLY__
6355 struct ALT_QSPI_FLSHCMDRDDATAUP_s
6361 typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s ALT_QSPI_FLSHCMDRDDATAUP_t;
6365 #define ALT_QSPI_FLSHCMDRDDATAUP_RESET 0x00000000
6367 #define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4
6392 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0
6394 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31
6396 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32
6398 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff
6400 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000
6402 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0
6404 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6406 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
6408 #ifndef __ASSEMBLY__
6419 struct ALT_QSPI_FLSHCMDWRDATALO_s
6425 typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s ALT_QSPI_FLSHCMDWRDATALO_t;
6429 #define ALT_QSPI_FLSHCMDWRDATALO_RESET 0x00000000
6431 #define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8
6456 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0
6458 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31
6460 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32
6462 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff
6464 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000
6466 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0
6468 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6470 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
6472 #ifndef __ASSEMBLY__
6483 struct ALT_QSPI_FLSHCMDWRDATAUP_s
6489 typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s ALT_QSPI_FLSHCMDWRDATAUP_t;
6493 #define ALT_QSPI_FLSHCMDWRDATAUP_RESET 0x00000000
6495 #define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac
6515 #define ALT_QSPI_MODULEID_VALUE_LSB 0
6517 #define ALT_QSPI_MODULEID_VALUE_MSB 24
6519 #define ALT_QSPI_MODULEID_VALUE_WIDTH 25
6521 #define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff
6523 #define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000
6525 #define ALT_QSPI_MODULEID_VALUE_RESET 0x1001
6527 #define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0)
6529 #define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff)
6538 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_LSB 25
6540 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_MSB 31
6542 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_WIDTH 7
6544 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_SET_MSK 0xfe000000
6546 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_CLR_MSK 0x01ffffff
6548 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_RESET 0x0
6550 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_GET(value) (((value) & 0xfe000000) >> 25)
6552 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_SET(value) (((value) << 25) & 0xfe000000)
6554 #ifndef __ASSEMBLY__
6565 struct ALT_QSPI_MODULEID_s
6567 const uint32_t value : 25;
6568 const uint32_t mod_id_resv_fld : 7;
6572 typedef volatile struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t;
6576 #define ALT_QSPI_MODULEID_RESET 0x00001001
6578 #define ALT_QSPI_MODULEID_OFST 0xfc
6580 #ifndef __ASSEMBLY__
6594 ALT_QSPI_DEVRD_t devrd;
6595 ALT_QSPI_DEVWR_t devwr;
6596 ALT_QSPI_DELAY_t delay;
6597 ALT_QSPI_RDDATACAP_t rddatacap;
6598 ALT_QSPI_DEVSZ_t devsz;
6599 ALT_QSPI_SRAMPART_t srampart;
6600 ALT_QSPI_INDADDRTRIG_t indaddrtrig;
6601 ALT_QSPI_DMAPER_t dmaper;
6602 ALT_QSPI_REMAPADDR_t remapaddr;
6603 ALT_QSPI_MODBIT_t modebit;
6604 ALT_QSPI_SRAMFILL_t sramfill;
6605 ALT_QSPI_TXTHRESH_t txthresh;
6606 ALT_QSPI_RXTHRESH_t rxthresh;
6607 volatile uint32_t _pad_0x38_0x3f[2];
6608 ALT_QSPI_IRQSTAT_t irqstat;
6609 ALT_QSPI_IRQMSK_t irqmask;
6610 volatile uint32_t _pad_0x48_0x4f[2];
6611 ALT_QSPI_LOWWRPROT_t lowwrprot;
6612 ALT_QSPI_UPPWRPROT_t uppwrprot;
6613 ALT_QSPI_WRPROT_t wrprot;
6614 volatile uint32_t _pad_0x5c_0x5f;
6615 ALT_QSPI_INDRD_t indrd;
6616 ALT_QSPI_INDRDWATER_t indrdwater;
6617 ALT_QSPI_INDRDSTADDR_t indrdstaddr;
6618 ALT_QSPI_INDRDCNT_t indrdcnt;
6619 ALT_QSPI_INDWR_t indwr;
6620 ALT_QSPI_INDWRWATER_t indwrwater;
6621 ALT_QSPI_INDWRSTADDR_t indwrstaddr;
6622 ALT_QSPI_INDWRCNT_t indwrcnt;
6623 volatile uint32_t _pad_0x80_0x8f[4];
6624 ALT_QSPI_FLSHCMD_t flashcmd;
6625 ALT_QSPI_FLSHCMDADDR_t flashcmdaddr;
6626 volatile uint32_t _pad_0x98_0x9f[2];
6627 ALT_QSPI_FLSHCMDRDDATALO_t flashcmdrddatalo;
6628 ALT_QSPI_FLSHCMDRDDATAUP_t flashcmdrddataup;
6629 ALT_QSPI_FLSHCMDWRDATALO_t flashcmdwrdatalo;
6630 ALT_QSPI_FLSHCMDWRDATAUP_t flashcmdwrdataup;
6631 volatile uint32_t _pad_0xb0_0xfb[19];
6632 ALT_QSPI_MODULEID_t moduleid;
6636 typedef volatile struct ALT_QSPI_s ALT_QSPI_t;
6638 struct ALT_QSPI_raw_s
6640 volatile uint32_t cfg;
6641 volatile uint32_t devrd;
6642 volatile uint32_t devwr;
6643 volatile uint32_t delay;
6644 volatile uint32_t rddatacap;
6645 volatile uint32_t devsz;
6646 volatile uint32_t srampart;
6647 volatile uint32_t indaddrtrig;
6648 volatile uint32_t dmaper;
6649 volatile uint32_t remapaddr;
6650 volatile uint32_t modebit;
6651 volatile uint32_t sramfill;
6652 volatile uint32_t txthresh;
6653 volatile uint32_t rxthresh;
6654 uint32_t _pad_0x38_0x3f[2];
6655 volatile uint32_t irqstat;
6656 volatile uint32_t irqmask;
6657 uint32_t _pad_0x48_0x4f[2];
6658 volatile uint32_t lowwrprot;
6659 volatile uint32_t uppwrprot;
6660 volatile uint32_t wrprot;
6661 uint32_t _pad_0x5c_0x5f;
6662 volatile uint32_t indrd;
6663 volatile uint32_t indrdwater;
6664 volatile uint32_t indrdstaddr;
6665 volatile uint32_t indrdcnt;
6666 volatile uint32_t indwr;
6667 volatile uint32_t indwrwater;
6668 volatile uint32_t indwrstaddr;
6669 volatile uint32_t indwrcnt;
6670 uint32_t _pad_0x80_0x8f[4];
6671 volatile uint32_t flashcmd;
6672 volatile uint32_t flashcmdaddr;
6673 uint32_t _pad_0x98_0x9f[2];
6674 volatile uint32_t flashcmdrddatalo;
6675 volatile uint32_t flashcmdrddataup;
6676 volatile uint32_t flashcmdwrdatalo;
6677 volatile uint32_t flashcmdwrdataup;
6678 uint32_t _pad_0xb0_0xfb[19];
6679 volatile uint32_t moduleid;
6683 typedef volatile struct ALT_QSPI_raw_s ALT_QSPI_raw_t;