Hardware Libraries  20.1
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alt_sdmmc.h
1 /******************************************************************************
2 *
3 * Copyright 2013 Altera Corporation. All Rights Reserved.
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31 ******************************************************************************/
32 
33 /*
34  * $Id: //acds/rel/20.1/embedded/ip/hps/altera_hps/hwlib/include/alt_sdmmc.h#1 $
35  */
36 
37 #ifndef __ALT_SDMMC_H__
38 #define __ALT_SDMMC_H__
39 
40 #include "hwlib.h"
41 
42 #ifdef __cplusplus
43 extern "C"
44 {
45 #endif /* __cplusplus */
46 
47 /******************************************************************************/
148 /******************************************************************************/
161 {
172 
181 typedef struct ALT_SDMMC_CARD_INFO_s
182 {
184  uint32_t rca;
185  uint32_t xfer_speed;
186  uint32_t max_r_blkln;
187  uint32_t max_w_blkln;
190  bool high_speed;
191  uint32_t scr_sd_spec;
192  uint32_t csd_ccc;
193  uint32_t blk_number_high;
194  uint32_t blk_number_low;
203  uint32_t scr_bus_widths;
205 
217 ALT_STATUS_CODE alt_sdmmc_init(void);
218 
226 ALT_STATUS_CODE alt_sdmmc_uninit(void);
227 
235 ALT_STATUS_CODE alt_sdmmc_reset(void);
236 
241 {
245 
251 {
255 
261 {
262  ALT_SDMMC_GO_IDLE_STATE = 0,
263  ALT_SDMMC_ALL_SEND_CID = 2,
264  ALT_SDMMC_SET_RELATIVE_ADDR = 3,
265  ALT_SDMMC_SET_DSR = 4,
266  ALT_SDMMC_SEND_OP_COND = 5,
267  ALT_SDMMC_SWITCH = 6,
268  ALT_SDMMC_SEL_DES_CARD = 7,
269  ALT_SDMMC_IF_COND = 8,
270  ALT_SDMMC_SEND_EXT_CSD = 8,
271  ALT_SDMMC_SEND_CSD = 9,
272  ALT_SDMMC_SEND_CID = 10,
273  ALT_SDMMC_READ_DAT_UNTIL_STOP = 11,
274  ALT_SDMMC_STOP_TRANSMISSION = 12,
275  ALT_SDMMC_SEND_STATUS = 13,
276  ALT_SDMMC_GO_INACTIVE_STATE = 15,
277  ALT_SDMMC_SET_BLOCKLEN = 16,
278  ALT_SDMMC_READ_SINGLE_BLOCK = 17,
279  ALT_SDMMC_READ_MULTIPLE_BLOCK = 18,
280  ALT_SDMMC_WRITE_DAT_UNTIL_STOP = 20,
281  ALT_SDMMC_WRITE_BLOCK = 24,
282  ALT_SDMMC_WRITE_MULTIPLE_BLOCK = 25,
283  ALT_SDMMC_PROGRAM_CID = 26,
284  ALT_SDMMC_PROGRAM_CSD = 27,
285  ALT_SDMMC_SET_WRITE_PROT = 28,
286  ALT_SDMMC_CLR_WRITE_PROT = 29,
287  ALT_SDMMC_SEND_WRITE_PROT = 30,
288  ALT_SDMMC_TAG_SECTOR_START = 32,
289  ALT_SDMMC_TAG_SECTOR_END = 33,
290  ALT_SDMMC_UNTAG_SECTOR = 34,
291  ALT_SDMMC_TAG_ERASE_GROUP_START = 35,
292  ALT_SDMMC_TAG_ERASE_GROUP_END = 36,
293  ALT_SDMMC_UNTAG_ERASE_GROUP = 37,
294  ALT_SDMMC_ERASE = 38,
295  ALT_SDMMC_FAST_IO = 39,
296  ALT_SDMMC_GO_IRQ_STATE = 40,
297  ALT_SDMMC_LOCK_UNLOCK = 42,
298  ALT_SDMMC_APP_CMD = 55,
299  ALT_SDMMC_GEN_CMD = 56,
300  ALT_SDMMC_READ_OCR = 58,
301  ALT_SDMMC_CRC_ON_OFF = 59,
302 
303  ALT_SDMMC_STANDART_CMD_ALL = 60,
304 
305  /* TBD - Commands specific for card type. */
306  ALT_SD_SET_BUS_WIDTH = 6,
307  ALT_SD_SD_STATUS = 13,
308  ALT_SD_SEND_OP_COND = 41,
309  ALT_SD_SEND_SCR = 51,
310 
311  /* TBD - Clock command or command index does not matter... */
312  ALT_SDMMC_CLK_INDEX = -1,
313 
314  ALT_SDMMC_CMD_ALL = ALT_SDMMC_STANDART_CMD_ALL + 1
316 
320 typedef struct ALT_SDMMC_CMD_CONFIG_s
321 {
322  uint32_t cmd_index : 6;
324  uint32_t response_expect : 1;
326  uint32_t response_length_long : 1;
328  uint32_t check_response_crc : 1;
330  uint32_t data_expected : 1;
332  uint32_t write_active : 1;
337  uint32_t stream_mode_active : 1;
339  uint32_t send_auto_stop : 1;
341  uint32_t wait_prvdata_complete : 1;
345  uint32_t stop_abort_cmd : 1;
349  uint32_t send_initialization : 1;
353  uint32_t card_number : 5;
357  uint32_t update_clock_registers_only : 1;
361  uint32_t read_ceata_device : 1;
365  uint32_t ccs_expected : 1;
370  uint32_t enable_boot : 1;
374  uint32_t expect_boot_ack : 1;
380  uint32_t disable_boot : 1;
382  uint32_t boot_mode : 1;
388  uint32_t volt_switch : 1;
390  uint32_t use_hold_reg : 1;
392  uint32_t reserved : 1;
393  uint32_t start_bit : 1;
401 
423 ALT_STATUS_CODE alt_sdmmc_command_send(ALT_SDMMC_CMD_TYPE_t command_type,
424  ALT_SDMMC_CMD_INDEX_t command,
425  uint32_t command_arg,
426  uint32_t *response);
427 
432 typedef struct ALT_SDMMC_RESPONSE_s
433 {
434  uint32_t resp0;
435  uint32_t resp1;
436  uint32_t resp2;
437  uint32_t resp3;
439 
450 ALT_STATUS_CODE alt_sdmmc_read_long_response(ALT_SDMMC_RESPONSE_t *response);
451 
460 uint32_t alt_sdmmc_int_status_get(void);
461 
472 uint32_t alt_sdmmc_int_mask_get(void);
473 
489 ALT_STATUS_CODE alt_sdmmc_int_clear(const uint32_t mask);
490 
512 ALT_STATUS_CODE alt_sdmmc_int_disable(const uint32_t mask);
513 
535 ALT_STATUS_CODE alt_sdmmc_int_enable(const uint32_t mask);
536 
547 {
548  ALT_SDMMC_INT_STATUS_CD = (1UL << 0),
549  ALT_SDMMC_INT_STATUS_RE = (1UL << 1),
558  ALT_SDMMC_INT_STATUS_HTO = (1UL << 10),
560  ALT_SDMMC_INT_STATUS_HLE = (1UL << 12),
561  ALT_SDMMC_INT_STATUS_SBE = (1UL << 13),
562  ALT_SDMMC_INT_STATUS_ACD = (1UL << 14),
563  ALT_SDMMC_INT_STATUS_EBE = (1UL << 15),
568 
569 #if defined (soc_a10)
570 
579 ALT_STATUS_CODE alt_sdmmc_ecc_start(void);
580 
596 ALT_STATUS_CODE alt_sdmmc_ecc_get_correct_data(uint32_t address, uint32_t * data);
597 #endif
598 
601 /******************************************************************************/
622 {
623  ALT_SDMMC_BUS_WIDTH_1 = 1,
624  ALT_SDMMC_BUS_WIDTH_4 = 4,
625  ALT_SDMMC_BUS_WIDTH_8 = 8
627 
632 typedef struct ALT_SDMMC_CARD_MISC_s
633 {
634  uint32_t response_timeout;
637  uint32_t data_timeout;
643  uint32_t block_size;
644  uint32_t debounce_count;
648 
660 ALT_STATUS_CODE alt_sdmmc_card_misc_get(ALT_SDMMC_CARD_MISC_t *card_misc_cfg);
661 
673 ALT_STATUS_CODE alt_sdmmc_card_misc_set(const ALT_SDMMC_CARD_MISC_t *card_misc_cfg);
674 
689 ALT_STATUS_CODE alt_sdmmc_card_bus_width_set(ALT_SDMMC_CARD_INFO_t *card_info, const ALT_SDMMC_BUS_WIDTH_t width);
690 
700 ALT_STATUS_CODE alt_sdmmc_card_block_size_set(const uint16_t block_size);
701 
716 ALT_STATUS_CODE alt_sdmmc_card_identify(ALT_SDMMC_CARD_INFO_t *card_info);
717 
728 uint32_t alt_sdmmc_card_clk_div_get(void);
729 
746 ALT_STATUS_CODE alt_sdmmc_card_clk_div_set(const uint32_t clk_div);
747 
754 uint32_t alt_sdmmc_card_speed_get(void);
755 
770 ALT_STATUS_CODE alt_sdmmc_card_speed_set(ALT_SDMMC_CARD_INFO_t *card_info, uint32_t xfer_speed);
771 
778 ALT_STATUS_CODE alt_sdmmc_card_clk_disable(void);
779 
793 ALT_STATUS_CODE alt_sdmmc_card_clk_enable(const bool use_low_pwr_mode);
794 
803 
812 
826 ALT_STATUS_CODE alt_sdmmc_card_reset(void);
827 
837 bool alt_sdmmc_card_is_detected(void);
838 
849 
860 bool alt_sdmmc_card_pwr_is_on(void);
861 
871 ALT_STATUS_CODE alt_sdmmc_card_pwr_on(void);
872 
881 ALT_STATUS_CODE alt_sdmmc_card_pwr_off(void);
882 
885 /******************************************************************************/
928 {
937  ALT_SDMMC_DMA_INT_STATUS_ALL = 0x337
939 
952 {
956  union DES0
957  {
959  struct
960  {
961  uint32_t : 1;
962  uint32_t dic : 1;
971  uint32_t ld : 1;
977  uint32_t fs : 1;
985  uint32_t ch : 1;
995  uint32_t er : 1;
1006  uint32_t ces : 1;
1020  uint32_t : 24;
1021  uint32_t own : 1;
1032  } fld;
1035  uint32_t raw;
1038  } des0;
1044  union DES1
1045  {
1047  struct
1048  {
1049  uint32_t bs1 : 13;
1066  uint32_t bs2 : 13;
1075  uint32_t : 6;
1077  } fld;
1080  uint32_t raw;
1083  } des1;
1087  union DES2
1088  {
1090  struct
1091  {
1092  uint32_t bap1 : 32;
1100  } fld;
1103  uint32_t raw;
1106  } des2;
1114  union DES3
1115  {
1117  struct
1118  {
1119  uint32_t bap2_or_next : 32;
1136  } fld;
1139  uint32_t raw;
1142  } des3;
1153 
1169 ALT_STATUS_CODE alt_sdmmc_dma_reset(void);
1170 
1187 ALT_STATUS_CODE alt_sdmmc_dma_disable(void);
1188 
1200 ALT_STATUS_CODE alt_sdmmc_is_dma_enabled(void);
1201 
1218 ALT_STATUS_CODE alt_sdmmc_dma_enable(void);
1219 
1225 {
1236 
1270 ALT_STATUS_CODE alt_sdmmc_dma_start(ALT_SDMMC_DMA_BUF_DESC_t *buf_desc_list,
1271  const uint32_t desc_skip_len,
1272  const ALT_SDMMC_DMA_PBL_t burst_len,
1273  const bool use_fixed_burst);
1274 
1285 ALT_STATUS_CODE alt_sdmmc_poll_demand_set(const uint32_t value);
1286 
1295 uint32_t alt_sdmmc_dma_int_status_get(void);
1296 
1308 uint32_t alt_sdmmc_dma_int_mask_get(void);
1309 
1326 ALT_STATUS_CODE alt_sdmmc_dma_int_clear(const uint32_t mask);
1327 
1349 ALT_STATUS_CODE alt_sdmmc_dma_int_disable(const uint32_t mask);
1350 
1372 ALT_STATUS_CODE alt_sdmmc_dma_int_enable(const uint32_t mask);
1373 
1376 /******************************************************************************/
1386 #define ALT_SDMMC_FIFO_NUM_ENTRIES 1024
1387 
1398 ALT_STATUS_CODE alt_sdmmc_fifo_reset(void);
1399 
1405 {
1414 
1434 ALT_STATUS_CODE alt_sdmmc_fifo_param_get(uint32_t *rx_wtrmk, uint32_t *tx_wtrmk,
1435  ALT_SDMMC_MULT_TRANS_t *mult_trans_size);
1436 
1455 ALT_STATUS_CODE alt_sdmmc_fifo_param_set(uint32_t rx_wtrmk, uint32_t tx_wtrmk, ALT_SDMMC_MULT_TRANS_t mult_trans_size);
1456 
1468 
1480 
1490 bool alt_sdmmc_fifo_is_empty(void);
1491 
1501 bool alt_sdmmc_fifo_is_full(void);
1502 
1508 int32_t alt_sdmmc_fifo_count(void);
1509 
1528 ALT_STATUS_CODE alt_sdmmc_fifo_read(void *dest, const size_t size);
1529 
1551 ALT_STATUS_CODE alt_sdmmc_fifo_write(const void *src, const size_t size);
1552 
1555 /******************************************************************************/
1589 ALT_STATUS_CODE alt_sdmmc_read(ALT_SDMMC_CARD_INFO_t *card_info, void *dest, void *src, const size_t size);
1590 
1618 ALT_STATUS_CODE alt_sdmmc_write(ALT_SDMMC_CARD_INFO_t *card_info, void *dest, void *src, const size_t size);
1619 
1624 #ifdef __cplusplus
1625 }
1626 #endif /* __cplusplus */
1627 
1628 #endif /* __ALT_SDMMC_H__ */