Hardware Libraries  20.1
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alt_i2c.h
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32 
33 /* Altera - ALT_I2C */
34 
35 #ifndef __ALT_SOCAL_I2C_H__
36 #define __ALT_SOCAL_I2C_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_I2C
50  *
51  */
52 /*
53  * Register : ic_con
54  *
55  * Name: I2C Control Register
56  *
57  * Size: 10 bits
58  *
59  * Address Offset: 0x00
60  *
61  * Read/Write Access:
62  *
63  * If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0,
64  *
65  * all bits are Read/Write.
66  *
67  * If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.
68  *
69  * This register can be written only when the DW_apb_i2c
70  *
71  * is disabled, which corresponds to the IC_ENABLE[0] register
72  *
73  * being set to 0. Writes at other times have no effect.
74  *
75  * Register Layout
76  *
77  * Bits | Access | Reset | Description
78  * :--------|:-------|:------|:---------------------------------
79  * [0] | RW | 0x1 | ALT_I2C_CON_MST_MOD
80  * [2:1] | RW | 0x2 | ALT_I2C_CON_SPEED
81  * [3] | RW | 0x1 | ALT_I2C_CON_IC_10BITADDR_SLV
82  * [4] | R | 0x1 | ALT_I2C_CON_IC_10BITADDR_MST
83  * [5] | RW | 0x1 | ALT_I2C_CON_IC_RESTART_EN
84  * [6] | RW | 0x1 | ALT_I2C_CON_IC_SLV_DIS
85  * [7] | RW | 0x0 | ALT_I2C_CON_STOP_DET_IFADDRED
86  * [8] | RW | 0x0 | ALT_I2C_CON_TX_EMPTY_CTL
87  * [9] | RW | 0x0 | ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL
88  * [31:10] | R | 0x0 | ALT_I2C_CON_RSVD_IC_CON_31TO10
89  *
90  */
91 /*
92  * Field : master_mode
93  *
94  * This bit controls whether the DW_apb_i2c master is enabled.
95  *
96  * 0: master disabled
97  *
98  * 1: master enabled
99  *
100  * Reset value: IC_MASTER_MODE configuration parameter
101  *
102  * NOTE: Software should ensure that if this bit is written with '1'
103  *
104  * then bit 6 should also be written with a '1'.
105  *
106  * Field Enumeration Values:
107  *
108  * Enum | Value | Description
109  * :--------------------------|:------|:----------------
110  * ALT_I2C_CON_MST_MOD_E_DIS | 0x0 | master disabled
111  * ALT_I2C_CON_MST_MOD_E_EN | 0x1 | master enabled
112  *
113  * Field Access Macros:
114  *
115  */
116 /*
117  * Enumerated value for register field ALT_I2C_CON_MST_MOD
118  *
119  * master disabled
120  */
121 #define ALT_I2C_CON_MST_MOD_E_DIS 0x0
122 /*
123  * Enumerated value for register field ALT_I2C_CON_MST_MOD
124  *
125  * master enabled
126  */
127 #define ALT_I2C_CON_MST_MOD_E_EN 0x1
128 
129 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_MST_MOD register field. */
130 #define ALT_I2C_CON_MST_MOD_LSB 0
131 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_MST_MOD register field. */
132 #define ALT_I2C_CON_MST_MOD_MSB 0
133 /* The width in bits of the ALT_I2C_CON_MST_MOD register field. */
134 #define ALT_I2C_CON_MST_MOD_WIDTH 1
135 /* The mask used to set the ALT_I2C_CON_MST_MOD register field value. */
136 #define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001
137 /* The mask used to clear the ALT_I2C_CON_MST_MOD register field value. */
138 #define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe
139 /* The reset value of the ALT_I2C_CON_MST_MOD register field. */
140 #define ALT_I2C_CON_MST_MOD_RESET 0x1
141 /* Extracts the ALT_I2C_CON_MST_MOD field value from a register. */
142 #define ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0)
143 /* Produces a ALT_I2C_CON_MST_MOD register field value suitable for setting the register. */
144 #define ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001)
145 
146 /*
147  * Field : speed
148  *
149  * These bits control at which speed the DW_apb_i2c operates; its
150  *
151  * setting is relevant only if one is operating the DW_apb_i2c in
152  *
153  * master mode. Hardware protects against illegal values being
154  *
155  * programmed by software. This register should be programmed
156  *
157  * only with a value in the range of 1 to IC_MAX_SPEED_MODE;
158  *
159  * otherwise, hardware updates this register with the value of
160  *
161  * IC_MAX_SPEED_MODE.
162  *
163  * 1: standard mode (100 kbit/s)
164  *
165  * 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)
166  *
167  * 3: high speed mode (3.4 Mbit/s)
168  *
169  * Reset value: IC_MAX_SPEED_MODE configuration
170  *
171  * Field Enumeration Values:
172  *
173  * Enum | Value | Description
174  * :-----------------------------|:------|:---------------------------
175  * ALT_I2C_CON_SPEED_E_STANDARD | 0x1 | standard mode (100 kbit/s)
176  * ALT_I2C_CON_SPEED_E_FAST | 0x2 | fast mode (400 kbit/s)
177  *
178  * Field Access Macros:
179  *
180  */
181 /*
182  * Enumerated value for register field ALT_I2C_CON_SPEED
183  *
184  * standard mode (100 kbit/s)
185  */
186 #define ALT_I2C_CON_SPEED_E_STANDARD 0x1
187 /*
188  * Enumerated value for register field ALT_I2C_CON_SPEED
189  *
190  * fast mode (400 kbit/s)
191  */
192 #define ALT_I2C_CON_SPEED_E_FAST 0x2
193 
194 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_SPEED register field. */
195 #define ALT_I2C_CON_SPEED_LSB 1
196 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_SPEED register field. */
197 #define ALT_I2C_CON_SPEED_MSB 2
198 /* The width in bits of the ALT_I2C_CON_SPEED register field. */
199 #define ALT_I2C_CON_SPEED_WIDTH 2
200 /* The mask used to set the ALT_I2C_CON_SPEED register field value. */
201 #define ALT_I2C_CON_SPEED_SET_MSK 0x00000006
202 /* The mask used to clear the ALT_I2C_CON_SPEED register field value. */
203 #define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9
204 /* The reset value of the ALT_I2C_CON_SPEED register field. */
205 #define ALT_I2C_CON_SPEED_RESET 0x2
206 /* Extracts the ALT_I2C_CON_SPEED field value from a register. */
207 #define ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1)
208 /* Produces a ALT_I2C_CON_SPEED register field value suitable for setting the register. */
209 #define ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006)
210 
211 /*
212  * Field : ic_10bitaddr_slave
213  *
214  * When acting as a slave, this bit controls whether the DW_apb_i2c
215  *
216  * responds to 7- or 10-bit addresses.
217  *
218  * 0: 7-bit addressing. The DW_apb_i2c ignores transactions that
219  *
220  * involve 10-bit addressing; for 7-bit addressing,
221  *
222  * only the lower 7 bits of the IC_SAR register are compared.
223  *
224  * 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit
225  *
226  * addressing transfers that match the full 10 bits of the IC_SAR
227  *
228  * register.
229  *
230  * Reset value: IC_10BITADDR_SLAVE configuration parameter
231  *
232  * Field Enumeration Values:
233  *
234  * Enum | Value | Description
235  * :--------------------------------------------|:------|:------------------
236  * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT | 0x0 | 7-bit addressing
237  * ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT | 0x1 | 10-bit addressing
238  *
239  * Field Access Macros:
240  *
241  */
242 /*
243  * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV
244  *
245  * 7-bit addressing
246  */
247 #define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0
248 /*
249  * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV
250  *
251  * 10-bit addressing
252  */
253 #define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1
254 
255 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */
256 #define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3
257 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */
258 #define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3
259 /* The width in bits of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */
260 #define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1
261 /* The mask used to set the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */
262 #define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008
263 /* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_SLV register field value. */
264 #define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7
265 /* The reset value of the ALT_I2C_CON_IC_10BITADDR_SLV register field. */
266 #define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1
267 /* Extracts the ALT_I2C_CON_IC_10BITADDR_SLV field value from a register. */
268 #define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3)
269 /* Produces a ALT_I2C_CON_IC_10BITADDR_SLV register field value suitable for setting the register. */
270 #define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008)
271 
272 /*
273  * Field : ic_10bitaddr_master
274  *
275  * If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is
276  *
277  * set to 'No' (0), this bit is named IC_10BITADDR_MASTER and
278  *
279  * controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit
280  *
281  * addressing mode when acting as a master.
282  *
283  * If I2C_DYNAMIC_TAR_UPDATE is set to 'Yes' (1), the
284  *
285  * function of this bit is handled by bit 12 of IC_TAR register, and
286  *
287  * becomes a read-only copy called
288  *
289  * IC_10BITADDR_MASTER_rd_only.
290  *
291  * 0: 7-bit addressing
292  *
293  * 1: 10-bit addressing
294  *
295  * Dependencies: If I2C_DYNAMIC_TAR_UPDATE = 1, then this
296  *
297  * bit is read-only. If I2C_DYNAMIC_TAR_UPDATE = 0, then this
298  *
299  * bit can be read or write.
300  *
301  * Reset value: IC_10BITADDR_MASTER configuration
302  *
303  * parameter
304  *
305  * Field Enumeration Values:
306  *
307  * Enum | Value | Description
308  * :--------------------------------------------|:------|:------------------
309  * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT | 0x0 | 7-bit addressing
310  * ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT | 0x1 | 10-bit addressing
311  *
312  * Field Access Macros:
313  *
314  */
315 /*
316  * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST
317  *
318  * 7-bit addressing
319  */
320 #define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0
321 /*
322  * Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST
323  *
324  * 10-bit addressing
325  */
326 #define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1
327 
328 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */
329 #define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4
330 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field. */
331 #define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4
332 /* The width in bits of the ALT_I2C_CON_IC_10BITADDR_MST register field. */
333 #define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1
334 /* The mask used to set the ALT_I2C_CON_IC_10BITADDR_MST register field value. */
335 #define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010
336 /* The mask used to clear the ALT_I2C_CON_IC_10BITADDR_MST register field value. */
337 #define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef
338 /* The reset value of the ALT_I2C_CON_IC_10BITADDR_MST register field. */
339 #define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1
340 /* Extracts the ALT_I2C_CON_IC_10BITADDR_MST field value from a register. */
341 #define ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4)
342 /* Produces a ALT_I2C_CON_IC_10BITADDR_MST register field value suitable for setting the register. */
343 #define ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010)
344 
345 /*
346  * Field : ic_restart_en
347  *
348  * Determines whether RESTART conditions may be sent when
349  *
350  * acting as a master. Some older slaves do not support handling
351  *
352  * RESTART conditions; however, RESTART conditions are used in
353  *
354  * several DW_apb_i2c operations.
355  *
356  * 0: disable
357  *
358  * 1: enable
359  *
360  * When RESTART is disabled, the master is prohibited from
361  *
362  * performing the following functions:
363  *
364  * * Change direction within a transfer (split)
365  *
366  * * Send a START BYTE
367  *
368  * * High-speed mode operation
369  *
370  * * Combined format transfers in 7-bit addressing modes
371  *
372  * * Read operation with a 10-bit address
373  *
374  * * Send multiple bytes per transfer
375  *
376  * By replacing RESTART condition followed by a STOP and a
377  *
378  * subsequent START condition, split operations are broken down
379  *
380  * into multiple DW_apb_i2c transfers. If the above operations are
381  *
382  * performed, it will result in setting bit 6 (TX_ABRT) of the
383  *
384  * IC_RAW_INTR_STAT register.
385  *
386  * Reset value: IC_RESTART_EN configuration parameter
387  *
388  * Field Enumeration Values:
389  *
390  * Enum | Value | Description
391  * :--------------------------------|:------|:-----------------------
392  * ALT_I2C_CON_IC_RESTART_EN_E_DIS | 0x0 | restart master disable
393  * ALT_I2C_CON_IC_RESTART_EN_E_EN | 0x1 | restart master enable
394  *
395  * Field Access Macros:
396  *
397  */
398 /*
399  * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN
400  *
401  * restart master disable
402  */
403 #define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0
404 /*
405  * Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN
406  *
407  * restart master enable
408  */
409 #define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1
410 
411 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */
412 #define ALT_I2C_CON_IC_RESTART_EN_LSB 5
413 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_RESTART_EN register field. */
414 #define ALT_I2C_CON_IC_RESTART_EN_MSB 5
415 /* The width in bits of the ALT_I2C_CON_IC_RESTART_EN register field. */
416 #define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1
417 /* The mask used to set the ALT_I2C_CON_IC_RESTART_EN register field value. */
418 #define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020
419 /* The mask used to clear the ALT_I2C_CON_IC_RESTART_EN register field value. */
420 #define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf
421 /* The reset value of the ALT_I2C_CON_IC_RESTART_EN register field. */
422 #define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1
423 /* Extracts the ALT_I2C_CON_IC_RESTART_EN field value from a register. */
424 #define ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5)
425 /* Produces a ALT_I2C_CON_IC_RESTART_EN register field value suitable for setting the register. */
426 #define ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020)
427 
428 /*
429  * Field : ic_slave_disable
430  *
431  * This bit controls whether I2C has its slave disabled,
432  *
433  * which means once the presetn signal is applied, then
434  *
435  * this bit takes on the value of the configuration parameter
436  *
437  * IC_SLAVE_DISABLE. You have the choice of having the slave enabled
438  *
439  * or disabled after reset is applied, which means software does not
440  *
441  * have to configure the slave. By default, the slave is always enabled
442  *
443  * (in reset state as well). If you need to disable it after reset, set
444  *
445  * this bit to 1.
446  *
447  * If this bit is set (slave is disabled), DW_apb_i2c functions only as
448  *
449  * a master and does not perform any action that requires a slave.
450  *
451  * 0: slave is enabled
452  *
453  * 1: slave is disabled
454  *
455  * Reset value: IC_SLAVE_DISABLE configuration parameter
456  *
457  * NOTE: Software should ensure that if this bit is written with 0,
458  *
459  * then bit 0 should also be written with a 0.
460  *
461  * Field Enumeration Values:
462  *
463  * Enum | Value | Description
464  * :-----------------------------|:------|:--------------
465  * ALT_I2C_CON_IC_SLV_DIS_E_EN | 0x0 | slave enable
466  * ALT_I2C_CON_IC_SLV_DIS_E_DIS | 0x1 | slave disable
467  *
468  * Field Access Macros:
469  *
470  */
471 /*
472  * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS
473  *
474  * slave enable
475  */
476 #define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0
477 /*
478  * Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS
479  *
480  * slave disable
481  */
482 #define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1
483 
484 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */
485 #define ALT_I2C_CON_IC_SLV_DIS_LSB 6
486 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_SLV_DIS register field. */
487 #define ALT_I2C_CON_IC_SLV_DIS_MSB 6
488 /* The width in bits of the ALT_I2C_CON_IC_SLV_DIS register field. */
489 #define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1
490 /* The mask used to set the ALT_I2C_CON_IC_SLV_DIS register field value. */
491 #define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040
492 /* The mask used to clear the ALT_I2C_CON_IC_SLV_DIS register field value. */
493 #define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf
494 /* The reset value of the ALT_I2C_CON_IC_SLV_DIS register field. */
495 #define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1
496 /* Extracts the ALT_I2C_CON_IC_SLV_DIS field value from a register. */
497 #define ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6)
498 /* Produces a ALT_I2C_CON_IC_SLV_DIS register field value suitable for setting the register. */
499 #define ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040)
500 
501 /*
502  * Field : stop_det_ifaddressed
503  *
504  * In slave mode:
505  *
506  * 1: issues the STOP_DET interrrupt only when it is addressed.
507  *
508  * 0: issues the STOP_DET irrespective of whether it's addressed or not.
509  *
510  * Dependencies: This register bit value is applicable in the slave mode only
511  * (MASTER_MODE = 1'b0)
512  *
513  * Reset value: 0x0
514  *
515  * NOTE: During a general call address, this slave does not issue the
516  *
517  * STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if
518  *
519  * the slave responds to the general call address by generating ACK.
520  *
521  * The STOP_DET interrupt is generated only when the transmitted
522  *
523  * address matches the slave address (SAR).
524  *
525  * Field Access Macros:
526  *
527  */
528 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_STOP_DET_IFADDRED register field. */
529 #define ALT_I2C_CON_STOP_DET_IFADDRED_LSB 7
530 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_STOP_DET_IFADDRED register field. */
531 #define ALT_I2C_CON_STOP_DET_IFADDRED_MSB 7
532 /* The width in bits of the ALT_I2C_CON_STOP_DET_IFADDRED register field. */
533 #define ALT_I2C_CON_STOP_DET_IFADDRED_WIDTH 1
534 /* The mask used to set the ALT_I2C_CON_STOP_DET_IFADDRED register field value. */
535 #define ALT_I2C_CON_STOP_DET_IFADDRED_SET_MSK 0x00000080
536 /* The mask used to clear the ALT_I2C_CON_STOP_DET_IFADDRED register field value. */
537 #define ALT_I2C_CON_STOP_DET_IFADDRED_CLR_MSK 0xffffff7f
538 /* The reset value of the ALT_I2C_CON_STOP_DET_IFADDRED register field. */
539 #define ALT_I2C_CON_STOP_DET_IFADDRED_RESET 0x0
540 /* Extracts the ALT_I2C_CON_STOP_DET_IFADDRED field value from a register. */
541 #define ALT_I2C_CON_STOP_DET_IFADDRED_GET(value) (((value) & 0x00000080) >> 7)
542 /* Produces a ALT_I2C_CON_STOP_DET_IFADDRED register field value suitable for setting the register. */
543 #define ALT_I2C_CON_STOP_DET_IFADDRED_SET(value) (((value) << 7) & 0x00000080)
544 
545 /*
546  * Field : tx_empty_ctrl
547  *
548  * This bit controls the generation
549  *
550  * of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.
551  *
552  * Reset value: 0x0.
553  *
554  * Field Access Macros:
555  *
556  */
557 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_TX_EMPTY_CTL register field. */
558 #define ALT_I2C_CON_TX_EMPTY_CTL_LSB 8
559 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_TX_EMPTY_CTL register field. */
560 #define ALT_I2C_CON_TX_EMPTY_CTL_MSB 8
561 /* The width in bits of the ALT_I2C_CON_TX_EMPTY_CTL register field. */
562 #define ALT_I2C_CON_TX_EMPTY_CTL_WIDTH 1
563 /* The mask used to set the ALT_I2C_CON_TX_EMPTY_CTL register field value. */
564 #define ALT_I2C_CON_TX_EMPTY_CTL_SET_MSK 0x00000100
565 /* The mask used to clear the ALT_I2C_CON_TX_EMPTY_CTL register field value. */
566 #define ALT_I2C_CON_TX_EMPTY_CTL_CLR_MSK 0xfffffeff
567 /* The reset value of the ALT_I2C_CON_TX_EMPTY_CTL register field. */
568 #define ALT_I2C_CON_TX_EMPTY_CTL_RESET 0x0
569 /* Extracts the ALT_I2C_CON_TX_EMPTY_CTL field value from a register. */
570 #define ALT_I2C_CON_TX_EMPTY_CTL_GET(value) (((value) & 0x00000100) >> 8)
571 /* Produces a ALT_I2C_CON_TX_EMPTY_CTL register field value suitable for setting the register. */
572 #define ALT_I2C_CON_TX_EMPTY_CTL_SET(value) (((value) << 8) & 0x00000100)
573 
574 /*
575  * Field : rx_fifo_full_hld_ctrl
576  *
577  * This bit controls whether
578  *
579  * DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its
580  * RX_BUFFER_DEPTH,
581  *
582  * as described in the IC_RX_FULL_HLD_BUS_EN parameter.
583  *
584  * Dependencies: This register bit value is applicable only when the
585  *
586  * IC_RX_FULL_HLD_BUS_EN configuration parameter is set to 1.
587  *
588  * If IC_RX_FULL_HLD_BUS_EN = 0, then this bit is read-only.
589  *
590  * If IC_RX_FULL_HLD_BUS_EN = 1, then this bit can be read or write.
591  *
592  * Reset value: 0x0.
593  *
594  * Field Access Macros:
595  *
596  */
597 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field. */
598 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_LSB 9
599 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field. */
600 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_MSB 9
601 /* The width in bits of the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field. */
602 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_WIDTH 1
603 /* The mask used to set the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field value. */
604 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_SET_MSK 0x00000200
605 /* The mask used to clear the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field value. */
606 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_CLR_MSK 0xfffffdff
607 /* The reset value of the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field. */
608 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_RESET 0x0
609 /* Extracts the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL field value from a register. */
610 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_GET(value) (((value) & 0x00000200) >> 9)
611 /* Produces a ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field value suitable for setting the register. */
612 #define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_SET(value) (((value) << 9) & 0x00000200)
613 
614 /*
615  * Field : rsvd_ic_con_31to10
616  *
617  * Reserved bits [31:1] - Read Only
618  *
619  * Field Access Macros:
620  *
621  */
622 /* The Least Significant Bit (LSB) position of the ALT_I2C_CON_RSVD_IC_CON_31TO10 register field. */
623 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_LSB 10
624 /* The Most Significant Bit (MSB) position of the ALT_I2C_CON_RSVD_IC_CON_31TO10 register field. */
625 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_MSB 31
626 /* The width in bits of the ALT_I2C_CON_RSVD_IC_CON_31TO10 register field. */
627 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_WIDTH 22
628 /* The mask used to set the ALT_I2C_CON_RSVD_IC_CON_31TO10 register field value. */
629 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_SET_MSK 0xfffffc00
630 /* The mask used to clear the ALT_I2C_CON_RSVD_IC_CON_31TO10 register field value. */
631 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_CLR_MSK 0x000003ff
632 /* The reset value of the ALT_I2C_CON_RSVD_IC_CON_31TO10 register field. */
633 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_RESET 0x0
634 /* Extracts the ALT_I2C_CON_RSVD_IC_CON_31TO10 field value from a register. */
635 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_GET(value) (((value) & 0xfffffc00) >> 10)
636 /* Produces a ALT_I2C_CON_RSVD_IC_CON_31TO10 register field value suitable for setting the register. */
637 #define ALT_I2C_CON_RSVD_IC_CON_31TO10_SET(value) (((value) << 10) & 0xfffffc00)
638 
639 #ifndef __ASSEMBLY__
640 /*
641  * WARNING: The C register and register group struct declarations are provided for
642  * convenience and illustrative purposes. They should, however, be used with
643  * caution as the C language standard provides no guarantees about the alignment or
644  * atomicity of device memory accesses. The recommended practice for writing
645  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
646  * alt_write_word() functions.
647  *
648  * The struct declaration for register ALT_I2C_CON.
649  */
650 struct ALT_I2C_CON_s
651 {
652  uint32_t master_mode : 1; /* ALT_I2C_CON_MST_MOD */
653  uint32_t speed : 2; /* ALT_I2C_CON_SPEED */
654  uint32_t ic_10bitaddr_slave : 1; /* ALT_I2C_CON_IC_10BITADDR_SLV */
655  const uint32_t ic_10bitaddr_master : 1; /* ALT_I2C_CON_IC_10BITADDR_MST */
656  uint32_t ic_restart_en : 1; /* ALT_I2C_CON_IC_RESTART_EN */
657  uint32_t ic_slave_disable : 1; /* ALT_I2C_CON_IC_SLV_DIS */
658  uint32_t stop_det_ifaddressed : 1; /* ALT_I2C_CON_STOP_DET_IFADDRED */
659  uint32_t tx_empty_ctrl : 1; /* ALT_I2C_CON_TX_EMPTY_CTL */
660  uint32_t rx_fifo_full_hld_ctrl : 1; /* ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL */
661  const uint32_t rsvd_ic_con_31to10 : 22; /* ALT_I2C_CON_RSVD_IC_CON_31TO10 */
662 };
663 
664 /* The typedef declaration for register ALT_I2C_CON. */
665 typedef volatile struct ALT_I2C_CON_s ALT_I2C_CON_t;
666 #endif /* __ASSEMBLY__ */
667 
668 /* The reset value of the ALT_I2C_CON register. */
669 #define ALT_I2C_CON_RESET 0x0000007d
670 /* The byte offset of the ALT_I2C_CON register from the beginning of the component. */
671 #define ALT_I2C_CON_OFST 0x0
672 /* The address of the ALT_I2C_CON register. */
673 #define ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST))
674 
675 /*
676  * Register : ic_tar
677  *
678  * Name: I2C Target Address Register
679  *
680  * Size: 12 bits or 13 bits; 13 bits only when I2C_DYNAMIC_TAR_UPDATE = 1
681  *
682  * Address Offset: 0x04
683  *
684  * Read/Write Access: Read/Write
685  *
686  * If the configuration parameter I2C_DYNAMIC_TAR_UPDATE is set to 'No' (0),
687  *
688  * this register is 12 bits wide, and bits 31:12 are reserved. This register
689  *
690  * can be written to only when IC_ENABLE[0] is set to 0.
691  *
692  * However, if I2C_DYNAMIC_TAR_UPDATE = 1, then the register becomes 13 bits wide.
693  *
694  * All bits can be dynamically updated as long as any set of the following
695  *
696  * conditions are true:
697  *
698  * * DW_apb_i2c is NOT enabled (IC_ENABLE[0] is set to 0);
699  *
700  * or
701  *
702  * * DW_apb_i2c is enabled (IC_ENABLE[0]=1);
703  *
704  * AND
705  *
706  * DW_apb_i2c is NOT engaged in any Master (tx, rx) operation (IC_STATUS[5]=0);
707  *
708  * AND
709  *
710  * DW_apb_i2c is enabled to operate in Master mode (IC_CON[0]=1);
711  *
712  * AND
713  *
714  * there are NO entries in the TX FIFO (IC_STATUS[2]=1)
715  *
716  * Register Layout
717  *
718  * Bits | Access | Reset | Description
719  * :--------|:-------|:------|:-----------------------------
720  * [9:0] | RW | 0x55 | ALT_I2C_TAR_IC_TAR
721  * [10] | RW | 0x0 | ALT_I2C_TAR_GC_OR_START
722  * [11] | RW | 0x0 | ALT_I2C_TAR_SPECIAL
723  * [12] | RW | 0x1 | ALT_I2C_TAR_IC_10BITADDR_MST
724  * [31:13] | ??? | 0x0 | *UNDEFINED*
725  *
726  */
727 /*
728  * Field : ic_tar
729  *
730  * This is the target address for any master transaction. When
731  *
732  * transmitting a General Call, these bits are ignored. To generate a
733  *
734  * START BYTE, the CPU needs to write only once into these bits.
735  *
736  * Reset value: IC_DEFAULT_TAR_SLAVE_ADDR configuration
737  *
738  * parameter
739  *
740  * If the IC_TAR and IC_SAR are the same, loopback exists but the
741  *
742  * FIFOs are shared between master and slave, so full loopback is
743  *
744  * not feasible. Only one direction loopback mode is supported
745  *
746  * (simplex), not duplex. A master cannot transmit to itself; it can
747  *
748  * transmit to only a slave.
749  *
750  * Field Access Macros:
751  *
752  */
753 /* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_TAR register field. */
754 #define ALT_I2C_TAR_IC_TAR_LSB 0
755 /* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_TAR register field. */
756 #define ALT_I2C_TAR_IC_TAR_MSB 9
757 /* The width in bits of the ALT_I2C_TAR_IC_TAR register field. */
758 #define ALT_I2C_TAR_IC_TAR_WIDTH 10
759 /* The mask used to set the ALT_I2C_TAR_IC_TAR register field value. */
760 #define ALT_I2C_TAR_IC_TAR_SET_MSK 0x000003ff
761 /* The mask used to clear the ALT_I2C_TAR_IC_TAR register field value. */
762 #define ALT_I2C_TAR_IC_TAR_CLR_MSK 0xfffffc00
763 /* The reset value of the ALT_I2C_TAR_IC_TAR register field. */
764 #define ALT_I2C_TAR_IC_TAR_RESET 0x55
765 /* Extracts the ALT_I2C_TAR_IC_TAR field value from a register. */
766 #define ALT_I2C_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0)
767 /* Produces a ALT_I2C_TAR_IC_TAR register field value suitable for setting the register. */
768 #define ALT_I2C_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff)
769 
770 /*
771  * Field : gc_or_start
772  *
773  * If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a
774  *
775  * General Call or START byte command is to be performed by the
776  *
777  * DW_apb_i2c.
778  *
779  * 0: General Call Address after issuing a General Call, only writes
780  *
781  * may be performed. Attempting to issue a read command results in
782  *
783  * setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.
784  *
785  * The DW_apb_i2c remains in General Call mode until the
786  *
787  * SPECIAL bit value (bit 11) is cleared.
788  *
789  * 1: START BYTE
790  *
791  * Reset value: 0x0
792  *
793  * Field Enumeration Values:
794  *
795  * Enum | Value | Description
796  * :------------------------------------|:------|:-------------
797  * ALT_I2C_TAR_GC_OR_START_E_GENCALL | 0x0 | General Call
798  * ALT_I2C_TAR_GC_OR_START_E_STARTBYTE | 0x1 | START Byte
799  *
800  * Field Access Macros:
801  *
802  */
803 /*
804  * Enumerated value for register field ALT_I2C_TAR_GC_OR_START
805  *
806  * General Call
807  */
808 #define ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0
809 /*
810  * Enumerated value for register field ALT_I2C_TAR_GC_OR_START
811  *
812  * START Byte
813  */
814 #define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1
815 
816 /* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_GC_OR_START register field. */
817 #define ALT_I2C_TAR_GC_OR_START_LSB 10
818 /* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_GC_OR_START register field. */
819 #define ALT_I2C_TAR_GC_OR_START_MSB 10
820 /* The width in bits of the ALT_I2C_TAR_GC_OR_START register field. */
821 #define ALT_I2C_TAR_GC_OR_START_WIDTH 1
822 /* The mask used to set the ALT_I2C_TAR_GC_OR_START register field value. */
823 #define ALT_I2C_TAR_GC_OR_START_SET_MSK 0x00000400
824 /* The mask used to clear the ALT_I2C_TAR_GC_OR_START register field value. */
825 #define ALT_I2C_TAR_GC_OR_START_CLR_MSK 0xfffffbff
826 /* The reset value of the ALT_I2C_TAR_GC_OR_START register field. */
827 #define ALT_I2C_TAR_GC_OR_START_RESET 0x0
828 /* Extracts the ALT_I2C_TAR_GC_OR_START field value from a register. */
829 #define ALT_I2C_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10)
830 /* Produces a ALT_I2C_TAR_GC_OR_START register field value suitable for setting the register. */
831 #define ALT_I2C_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400)
832 
833 /*
834  * Field : special
835  *
836  * This bit indicates whether software performs a General Call or
837  *
838  * START BYTE command.
839  *
840  * 0: ignore bit 10 GC_OR_START and use IC_TAR normally
841  *
842  * 1: perform special I2C command as specified in GC_OR_START
843  *
844  * bit
845  *
846  * Reset value: 0x0
847  *
848  * Field Enumeration Values:
849  *
850  * Enum | Value | Description
851  * :--------------------------------|:------|:--------------------------------------------
852  * ALT_I2C_TAR_SPECIAL_E_GENCALL | 0x0 | Ignore bit 10 gc_or_start and use ic_tar
853  * : | | normally
854  * ALT_I2C_TAR_SPECIAL_E_STARTBYTE | 0x1 | Perform special I2C command as specified in
855  * : | | gc_or_start
856  *
857  * Field Access Macros:
858  *
859  */
860 /*
861  * Enumerated value for register field ALT_I2C_TAR_SPECIAL
862  *
863  * Ignore bit 10 gc_or_start and use ic_tar normally
864  */
865 #define ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0
866 /*
867  * Enumerated value for register field ALT_I2C_TAR_SPECIAL
868  *
869  * Perform special I2C command as specified in gc_or_start
870  */
871 #define ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1
872 
873 /* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_SPECIAL register field. */
874 #define ALT_I2C_TAR_SPECIAL_LSB 11
875 /* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_SPECIAL register field. */
876 #define ALT_I2C_TAR_SPECIAL_MSB 11
877 /* The width in bits of the ALT_I2C_TAR_SPECIAL register field. */
878 #define ALT_I2C_TAR_SPECIAL_WIDTH 1
879 /* The mask used to set the ALT_I2C_TAR_SPECIAL register field value. */
880 #define ALT_I2C_TAR_SPECIAL_SET_MSK 0x00000800
881 /* The mask used to clear the ALT_I2C_TAR_SPECIAL register field value. */
882 #define ALT_I2C_TAR_SPECIAL_CLR_MSK 0xfffff7ff
883 /* The reset value of the ALT_I2C_TAR_SPECIAL register field. */
884 #define ALT_I2C_TAR_SPECIAL_RESET 0x0
885 /* Extracts the ALT_I2C_TAR_SPECIAL field value from a register. */
886 #define ALT_I2C_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11)
887 /* Produces a ALT_I2C_TAR_SPECIAL register field value suitable for setting the register. */
888 #define ALT_I2C_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800)
889 
890 /*
891  * Field : ic_10bitaddr_master
892  *
893  * This bit controls whether the DW_apb_i2c starts its transfers in 7-
894  *
895  * or 10-bit addressing mode when acting as a master.
896  *
897  * 0: 7-bit addressing
898  *
899  * 1: 10-bit addressing
900  *
901  * Dependencies: This bit exists in this register only if the
902  *
903  * I2C_DYNAMIC_TAR_UPDATE configuration parameter is set
904  *
905  * to 'Yes' (1).
906  *
907  * Reset value: IC_10BITADDR_MASTER configuration
908  *
909  * parameter
910  *
911  * Field Enumeration Values:
912  *
913  * Enum | Value | Description
914  * :---------------------------------------|:------|:----------------------
915  * ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 | 0x0 | Master Address, 7bit
916  * ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 | 0x1 | Master Address, 10bit
917  *
918  * Field Access Macros:
919  *
920  */
921 /*
922  * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST
923  *
924  * Master Address, 7bit
925  */
926 #define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0
927 /*
928  * Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST
929  *
930  * Master Address, 10bit
931  */
932 #define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1
933 
934 /* The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */
935 #define ALT_I2C_TAR_IC_10BITADDR_MST_LSB 12
936 /* The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */
937 #define ALT_I2C_TAR_IC_10BITADDR_MST_MSB 12
938 /* The width in bits of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */
939 #define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH 1
940 /* The mask used to set the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */
941 #define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK 0x00001000
942 /* The mask used to clear the ALT_I2C_TAR_IC_10BITADDR_MST register field value. */
943 #define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK 0xffffefff
944 /* The reset value of the ALT_I2C_TAR_IC_10BITADDR_MST register field. */
945 #define ALT_I2C_TAR_IC_10BITADDR_MST_RESET 0x1
946 /* Extracts the ALT_I2C_TAR_IC_10BITADDR_MST field value from a register. */
947 #define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value) (((value) & 0x00001000) >> 12)
948 /* Produces a ALT_I2C_TAR_IC_10BITADDR_MST register field value suitable for setting the register. */
949 #define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value) (((value) << 12) & 0x00001000)
950 
951 #ifndef __ASSEMBLY__
952 /*
953  * WARNING: The C register and register group struct declarations are provided for
954  * convenience and illustrative purposes. They should, however, be used with
955  * caution as the C language standard provides no guarantees about the alignment or
956  * atomicity of device memory accesses. The recommended practice for writing
957  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
958  * alt_write_word() functions.
959  *
960  * The struct declaration for register ALT_I2C_TAR.
961  */
962 struct ALT_I2C_TAR_s
963 {
964  uint32_t ic_tar : 10; /* ALT_I2C_TAR_IC_TAR */
965  uint32_t gc_or_start : 1; /* ALT_I2C_TAR_GC_OR_START */
966  uint32_t special : 1; /* ALT_I2C_TAR_SPECIAL */
967  uint32_t ic_10bitaddr_master : 1; /* ALT_I2C_TAR_IC_10BITADDR_MST */
968  uint32_t : 19; /* *UNDEFINED* */
969 };
970 
971 /* The typedef declaration for register ALT_I2C_TAR. */
972 typedef volatile struct ALT_I2C_TAR_s ALT_I2C_TAR_t;
973 #endif /* __ASSEMBLY__ */
974 
975 /* The reset value of the ALT_I2C_TAR register. */
976 #define ALT_I2C_TAR_RESET 0x00001055
977 /* The byte offset of the ALT_I2C_TAR register from the beginning of the component. */
978 #define ALT_I2C_TAR_OFST 0x4
979 /* The address of the ALT_I2C_TAR register. */
980 #define ALT_I2C_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST))
981 
982 /*
983  * Register : ic_sar
984  *
985  * Name: I2C Slave Address Register
986  *
987  * Size: 10 bits
988  *
989  * Address Offset: 0x08
990  *
991  * Read/Write Access: Read/Write
992  *
993  * Register Layout
994  *
995  * Bits | Access | Reset | Description
996  * :--------|:-------|:------|:-------------------
997  * [9:0] | RW | 0x55 | ALT_I2C_SAR_IC_SAR
998  * [31:10] | ??? | 0x0 | *UNDEFINED*
999  *
1000  */
1001 /*
1002  * Field : ic_sar
1003  *
1004  * The IC_SAR holds the slave address when the I2C is operating as a slave. For
1005  * 7-bit
1006  *
1007  * addressing, only IC_SAR[6:0] is used.
1008  *
1009  * This register can be written only when the I2C interface is disabled, which
1010  *
1011  * corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times
1012  * have
1013  *
1014  * no effect.
1015  *
1016  * Note
1017  *
1018  * The default values cannot be any of the reserved address locations:
1019  *
1020  * that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the
1021  *
1022  * device is not guaranteed if you program the IC_SAR or IC_TAR to
1023  *
1024  * a reserved value.
1025  *
1026  * Reset value: IC_DEFAULT_SLAVE_ADDR configuration parameter
1027  *
1028  * Field Access Macros:
1029  *
1030  */
1031 /* The Least Significant Bit (LSB) position of the ALT_I2C_SAR_IC_SAR register field. */
1032 #define ALT_I2C_SAR_IC_SAR_LSB 0
1033 /* The Most Significant Bit (MSB) position of the ALT_I2C_SAR_IC_SAR register field. */
1034 #define ALT_I2C_SAR_IC_SAR_MSB 9
1035 /* The width in bits of the ALT_I2C_SAR_IC_SAR register field. */
1036 #define ALT_I2C_SAR_IC_SAR_WIDTH 10
1037 /* The mask used to set the ALT_I2C_SAR_IC_SAR register field value. */
1038 #define ALT_I2C_SAR_IC_SAR_SET_MSK 0x000003ff
1039 /* The mask used to clear the ALT_I2C_SAR_IC_SAR register field value. */
1040 #define ALT_I2C_SAR_IC_SAR_CLR_MSK 0xfffffc00
1041 /* The reset value of the ALT_I2C_SAR_IC_SAR register field. */
1042 #define ALT_I2C_SAR_IC_SAR_RESET 0x55
1043 /* Extracts the ALT_I2C_SAR_IC_SAR field value from a register. */
1044 #define ALT_I2C_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0)
1045 /* Produces a ALT_I2C_SAR_IC_SAR register field value suitable for setting the register. */
1046 #define ALT_I2C_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff)
1047 
1048 #ifndef __ASSEMBLY__
1049 /*
1050  * WARNING: The C register and register group struct declarations are provided for
1051  * convenience and illustrative purposes. They should, however, be used with
1052  * caution as the C language standard provides no guarantees about the alignment or
1053  * atomicity of device memory accesses. The recommended practice for writing
1054  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1055  * alt_write_word() functions.
1056  *
1057  * The struct declaration for register ALT_I2C_SAR.
1058  */
1059 struct ALT_I2C_SAR_s
1060 {
1061  uint32_t ic_sar : 10; /* ALT_I2C_SAR_IC_SAR */
1062  uint32_t : 22; /* *UNDEFINED* */
1063 };
1064 
1065 /* The typedef declaration for register ALT_I2C_SAR. */
1066 typedef volatile struct ALT_I2C_SAR_s ALT_I2C_SAR_t;
1067 #endif /* __ASSEMBLY__ */
1068 
1069 /* The reset value of the ALT_I2C_SAR register. */
1070 #define ALT_I2C_SAR_RESET 0x00000055
1071 /* The byte offset of the ALT_I2C_SAR register from the beginning of the component. */
1072 #define ALT_I2C_SAR_OFST 0x8
1073 /* The address of the ALT_I2C_SAR register. */
1074 #define ALT_I2C_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SAR_OFST))
1075 
1076 /*
1077  * Register : ic_data_cmd
1078  *
1079  * Name: I2C Rx/Tx Data Buffer and Command Register;
1080  *
1081  * this is the register the CPU writes to when
1082  *
1083  * filling the TX FIFO and the CPU reads from when
1084  *
1085  * retrieving bytes from RX FIFO
1086  *
1087  * Size:
1088  *
1089  * When IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 11 bits (writes), 8 bits (read)
1090  *
1091  * When IC_EMPTYFIFO_HOLD_MASTER_EN=0 - 9 bits (writes), 8 bits (read)
1092  *
1093  * Address Offset: 0x10
1094  *
1095  * Read/Write Access: Read/Write
1096  *
1097  * NOTE: With nine bits required for writes,
1098  *
1099  * the DW_apb_i2c requires 16-bit data on the
1100  *
1101  * APB bus transfers when writing into the
1102  *
1103  * transmit FIFO. Eight-bit transfers remain for
1104  *
1105  * reads from the receive FIFO.
1106  *
1107  * Register Layout
1108  *
1109  * Bits | Access | Reset | Description
1110  * :--------|:-------|:------|:-------------------------
1111  * [7:0] | RW | 0x0 | ALT_I2C_DATA_CMD_DAT
1112  * [8] | W | 0x0 | ALT_I2C_DATA_CMD_CMD
1113  * [9] | W | 0x0 | ALT_I2C_DATA_CMD_STOP
1114  * [10] | W | 0x0 | ALT_I2C_DATA_CMD_RESTART
1115  * [31:11] | ??? | 0x0 | *UNDEFINED*
1116  *
1117  */
1118 /*
1119  * Field : dat
1120  *
1121  * This register contains the data to be transmitted or received on the I2C bus.
1122  *
1123  * If you are writing to this register and want to perform a read,
1124  *
1125  * bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read
1126  *
1127  * this register, these bits return the value of data received on the
1128  *
1129  * DW_apb_i2c interface.
1130  *
1131  * Reset value: 0x0
1132  *
1133  * Field Access Macros:
1134  *
1135  */
1136 /* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_DAT register field. */
1137 #define ALT_I2C_DATA_CMD_DAT_LSB 0
1138 /* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_DAT register field. */
1139 #define ALT_I2C_DATA_CMD_DAT_MSB 7
1140 /* The width in bits of the ALT_I2C_DATA_CMD_DAT register field. */
1141 #define ALT_I2C_DATA_CMD_DAT_WIDTH 8
1142 /* The mask used to set the ALT_I2C_DATA_CMD_DAT register field value. */
1143 #define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff
1144 /* The mask used to clear the ALT_I2C_DATA_CMD_DAT register field value. */
1145 #define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00
1146 /* The reset value of the ALT_I2C_DATA_CMD_DAT register field. */
1147 #define ALT_I2C_DATA_CMD_DAT_RESET 0x0
1148 /* Extracts the ALT_I2C_DATA_CMD_DAT field value from a register. */
1149 #define ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0)
1150 /* Produces a ALT_I2C_DATA_CMD_DAT register field value suitable for setting the register. */
1151 #define ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff)
1152 
1153 /*
1154  * Field : cmd
1155  *
1156  * This bit controls whether a read or a write is performed.
1157  *
1158  * This bit does not control the direction when the DW_apb_i2c
1159  *
1160  * acts as a slave. It controls only the direction
1161  *
1162  * when it acts as a master.
1163  *
1164  * 1 = Read
1165  *
1166  * 0 = Write
1167  *
1168  * When a command is entered in the TX FIFO, this bit distinguishes the write and
1169  *
1170  * read commands. In slave-receiver mode, this bit is a 'don't care' because writes
1171  * to
1172  *
1173  * this register are not required. In slave-transmitter mode, a '0' indicates that
1174  * CPU
1175  *
1176  * data is to be transmitted and as DAT or IC_DATA_CMD[7:0].
1177  *
1178  * When programming this bit, you should remember the following: attempting to
1179  *
1180  * perform a read operation after a General Call command has been sent results in a
1181  *
1182  * TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11
1183  *
1184  * (SPECIAL) in the IC_TAR register has been cleared.
1185  *
1186  * If a '1' is written to this bit after receiving a RD_REQ interrupt, then a
1187  * TX_ABRT
1188  *
1189  * interrupt occurs.
1190  *
1191  * NOTE: It is possible that while attempting a master I2C read transfer on
1192  *
1193  * DW_apb_i2c, a RD_REQ interrupt may have occurred simultaneously due to a
1194  *
1195  * remote I2C master addressing DW_apb_i2c. In this type of scenario, DW_apb_i2c
1196  *
1197  * ignores the IC_DATA_CMD write, generates a TX_ABRT interrupt, and waits to
1198  *
1199  * service the RD_REQ interrupt.
1200  *
1201  * Reset value: 0x0
1202  *
1203  * Field Enumeration Values:
1204  *
1205  * Enum | Value | Description
1206  * :--------------------------|:------|:-------------
1207  * ALT_I2C_DATA_CMD_CMD_E_WR | 0x0 | Master Write
1208  * ALT_I2C_DATA_CMD_CMD_E_RD | 0x1 | Master Read
1209  *
1210  * Field Access Macros:
1211  *
1212  */
1213 /*
1214  * Enumerated value for register field ALT_I2C_DATA_CMD_CMD
1215  *
1216  * Master Write
1217  */
1218 #define ALT_I2C_DATA_CMD_CMD_E_WR 0x0
1219 /*
1220  * Enumerated value for register field ALT_I2C_DATA_CMD_CMD
1221  *
1222  * Master Read
1223  */
1224 #define ALT_I2C_DATA_CMD_CMD_E_RD 0x1
1225 
1226 /* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_CMD register field. */
1227 #define ALT_I2C_DATA_CMD_CMD_LSB 8
1228 /* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_CMD register field. */
1229 #define ALT_I2C_DATA_CMD_CMD_MSB 8
1230 /* The width in bits of the ALT_I2C_DATA_CMD_CMD register field. */
1231 #define ALT_I2C_DATA_CMD_CMD_WIDTH 1
1232 /* The mask used to set the ALT_I2C_DATA_CMD_CMD register field value. */
1233 #define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100
1234 /* The mask used to clear the ALT_I2C_DATA_CMD_CMD register field value. */
1235 #define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff
1236 /* The reset value of the ALT_I2C_DATA_CMD_CMD register field. */
1237 #define ALT_I2C_DATA_CMD_CMD_RESET 0x0
1238 /* Extracts the ALT_I2C_DATA_CMD_CMD field value from a register. */
1239 #define ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8)
1240 /* Produces a ALT_I2C_DATA_CMD_CMD register field value suitable for setting the register. */
1241 #define ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100)
1242 
1243 /*
1244  * Field : stop
1245  *
1246  * This bit controls whether a STOP is issued after the byte is sent or received.
1247  *
1248  * This bit is available only if IC_EMPTYFIFO_HOLD_MASTER_EN is configured to 1.
1249  *
1250  * 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is
1251  *
1252  * empty. If the Tx FIFO is not empty, the master immediately tries to start a new
1253  *
1254  * transfer by issuing a START and arbitrating for the bus.
1255  *
1256  * 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO
1257  * is
1258  *
1259  * empty. If the Tx FIFO is not empty, the master continues the current transfer by
1260  *
1261  * sending/receiving data bytes according to the value of the CMD bit. If the Tx
1262  * FIFO
1263  *
1264  * is empty, the master holds the SCL line low and stalls the bus until a new
1265  *
1266  * command is available in the Tx FIFO.
1267  *
1268  * Reset value: 0x0
1269  *
1270  * Field Access Macros:
1271  *
1272  */
1273 /* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_STOP register field. */
1274 #define ALT_I2C_DATA_CMD_STOP_LSB 9
1275 /* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_STOP register field. */
1276 #define ALT_I2C_DATA_CMD_STOP_MSB 9
1277 /* The width in bits of the ALT_I2C_DATA_CMD_STOP register field. */
1278 #define ALT_I2C_DATA_CMD_STOP_WIDTH 1
1279 /* The mask used to set the ALT_I2C_DATA_CMD_STOP register field value. */
1280 #define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200
1281 /* The mask used to clear the ALT_I2C_DATA_CMD_STOP register field value. */
1282 #define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff
1283 /* The reset value of the ALT_I2C_DATA_CMD_STOP register field. */
1284 #define ALT_I2C_DATA_CMD_STOP_RESET 0x0
1285 /* Extracts the ALT_I2C_DATA_CMD_STOP field value from a register. */
1286 #define ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9)
1287 /* Produces a ALT_I2C_DATA_CMD_STOP register field value suitable for setting the register. */
1288 #define ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200)
1289 
1290 /*
1291  * Field : restart
1292  *
1293  * This bit controls whether a RESTART is issued before the byte is sent or
1294  * received.
1295  *
1296  * This bit is available only if IC_EMPTYFIFO_HOLD_MASTER_EN is configured to 1.
1297  *
1298  * 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is
1299  *
1300  * sent/received (according to the value of CMD), regardless of whether or not the
1301  *
1302  * transfer direction is changing from the previous command; if IC_RESTART_EN
1303  *
1304  * is 0, a STOP followed by a START is issued instead.
1305  *
1306  * 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is
1307  *
1308  * changing from the previous command; if IC_RESTART_EN is 0, a STOP followed
1309  *
1310  * by a START is issued instead.
1311  *
1312  * Reset value: 0x0
1313  *
1314  * Field Access Macros:
1315  *
1316  */
1317 /* The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */
1318 #define ALT_I2C_DATA_CMD_RESTART_LSB 10
1319 /* The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_RESTART register field. */
1320 #define ALT_I2C_DATA_CMD_RESTART_MSB 10
1321 /* The width in bits of the ALT_I2C_DATA_CMD_RESTART register field. */
1322 #define ALT_I2C_DATA_CMD_RESTART_WIDTH 1
1323 /* The mask used to set the ALT_I2C_DATA_CMD_RESTART register field value. */
1324 #define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400
1325 /* The mask used to clear the ALT_I2C_DATA_CMD_RESTART register field value. */
1326 #define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff
1327 /* The reset value of the ALT_I2C_DATA_CMD_RESTART register field. */
1328 #define ALT_I2C_DATA_CMD_RESTART_RESET 0x0
1329 /* Extracts the ALT_I2C_DATA_CMD_RESTART field value from a register. */
1330 #define ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10)
1331 /* Produces a ALT_I2C_DATA_CMD_RESTART register field value suitable for setting the register. */
1332 #define ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400)
1333 
1334 #ifndef __ASSEMBLY__
1335 /*
1336  * WARNING: The C register and register group struct declarations are provided for
1337  * convenience and illustrative purposes. They should, however, be used with
1338  * caution as the C language standard provides no guarantees about the alignment or
1339  * atomicity of device memory accesses. The recommended practice for writing
1340  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1341  * alt_write_word() functions.
1342  *
1343  * The struct declaration for register ALT_I2C_DATA_CMD.
1344  */
1345 struct ALT_I2C_DATA_CMD_s
1346 {
1347  uint32_t dat : 8; /* ALT_I2C_DATA_CMD_DAT */
1348  uint32_t cmd : 1; /* ALT_I2C_DATA_CMD_CMD */
1349  uint32_t stop : 1; /* ALT_I2C_DATA_CMD_STOP */
1350  uint32_t restart : 1; /* ALT_I2C_DATA_CMD_RESTART */
1351  uint32_t : 21; /* *UNDEFINED* */
1352 };
1353 
1354 /* The typedef declaration for register ALT_I2C_DATA_CMD. */
1355 typedef volatile struct ALT_I2C_DATA_CMD_s ALT_I2C_DATA_CMD_t;
1356 #endif /* __ASSEMBLY__ */
1357 
1358 /* The reset value of the ALT_I2C_DATA_CMD register. */
1359 #define ALT_I2C_DATA_CMD_RESET 0x00000000
1360 /* The byte offset of the ALT_I2C_DATA_CMD register from the beginning of the component. */
1361 #define ALT_I2C_DATA_CMD_OFST 0x10
1362 /* The address of the ALT_I2C_DATA_CMD register. */
1363 #define ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST))
1364 
1365 /*
1366  * Register : ic_ss_scl_hcnt
1367  *
1368  * Name: Standard Speed I2C Clock SCL High Count Register
1369  *
1370  * Size: 16 bits
1371  *
1372  * Address Offset: 0x14
1373  *
1374  * Read/Write Access: Read/Write
1375  *
1376  * Register Layout
1377  *
1378  * Bits | Access | Reset | Description
1379  * :--------|:-------|:------|:-----------------------------------
1380  * [15:0] | RW | 0x190 | ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT
1381  * [31:16] | ??? | 0x0 | *UNDEFINED*
1382  *
1383  */
1384 /*
1385  * Field : ic_ss_scl_hcnt
1386  *
1387  * This register must be set before any I2C bus transaction can take place to
1388  *
1389  * ensure proper I/O timing. This register sets the SCL clock high-period
1390  *
1391  * count for standard speed.
1392  *
1393  * This register can be written only when the I2C interface is disabled which
1394  *
1395  * corresponds to the IC_ENABLE[0] register being set to 0. Writes at other
1396  *
1397  * times have no effect.
1398  *
1399  * The minimum valid value is 6; hardware prevents values less than this
1400  *
1401  * being written, and if attempted results in 6 being set. For designs with
1402  *
1403  * APB_DATA_WIDTH = 8, the order of programming is important to ensure
1404  *
1405  * the correct operation of the DW_apb_i2c. The lower byte must be
1406  *
1407  * programmed first. Then the upper byte is programmed.
1408  *
1409  * When the configuration parameter IC_HC_COUNT_VALUES is set to 1,
1410  *
1411  * this register is read only.
1412  *
1413  * NOTE: This register must not be programmed to a value higher than
1414  *
1415  * 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle
1416  *
1417  * condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.
1418  *
1419  * Reset value: IC_SS_SCL_HIGH_COUNT configuration parameter
1420  *
1421  * Field Access Macros:
1422  *
1423  */
1424 /* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
1425 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0
1426 /* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
1427 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15
1428 /* The width in bits of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
1429 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16
1430 /* The mask used to set the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */
1431 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff
1432 /* The mask used to clear the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value. */
1433 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000
1434 /* The reset value of the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field. */
1435 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x190
1436 /* Extracts the ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT field value from a register. */
1437 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1438 /* Produces a ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT register field value suitable for setting the register. */
1439 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
1440 
1441 #ifndef __ASSEMBLY__
1442 /*
1443  * WARNING: The C register and register group struct declarations are provided for
1444  * convenience and illustrative purposes. They should, however, be used with
1445  * caution as the C language standard provides no guarantees about the alignment or
1446  * atomicity of device memory accesses. The recommended practice for writing
1447  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1448  * alt_write_word() functions.
1449  *
1450  * The struct declaration for register ALT_I2C_SS_SCL_HCNT.
1451  */
1452 struct ALT_I2C_SS_SCL_HCNT_s
1453 {
1454  uint32_t ic_ss_scl_hcnt : 16; /* ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT */
1455  uint32_t : 16; /* *UNDEFINED* */
1456 };
1457 
1458 /* The typedef declaration for register ALT_I2C_SS_SCL_HCNT. */
1459 typedef volatile struct ALT_I2C_SS_SCL_HCNT_s ALT_I2C_SS_SCL_HCNT_t;
1460 #endif /* __ASSEMBLY__ */
1461 
1462 /* The reset value of the ALT_I2C_SS_SCL_HCNT register. */
1463 #define ALT_I2C_SS_SCL_HCNT_RESET 0x00000190
1464 /* The byte offset of the ALT_I2C_SS_SCL_HCNT register from the beginning of the component. */
1465 #define ALT_I2C_SS_SCL_HCNT_OFST 0x14
1466 /* The address of the ALT_I2C_SS_SCL_HCNT register. */
1467 #define ALT_I2C_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_HCNT_OFST))
1468 
1469 /*
1470  * Register : ic_ss_scl_lcnt
1471  *
1472  * Name: Standard Speed I2C Clock SCL Low Count Register
1473  *
1474  * Size: 16 bits
1475  *
1476  * Address Offset: 0x18
1477  *
1478  * Read/Write Access: Read/Write
1479  *
1480  * Register Layout
1481  *
1482  * Bits | Access | Reset | Description
1483  * :--------|:-------|:------|:-----------------------------------
1484  * [15:0] | RW | 0x1d6 | ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT
1485  * [31:16] | ??? | 0x0 | *UNDEFINED*
1486  *
1487  */
1488 /*
1489  * Field : ic_ss_scl_lcnt
1490  *
1491  * This register must be set before any I2C bus transaction can take place to
1492  *
1493  * ensure proper I/O timing. This register sets the SCL clock low period
1494  *
1495  * count for standard speed.
1496  *
1497  * This register can be written only when the I2C interface is disabled which
1498  *
1499  * corresponds to the IC_ENABLE[0] register being set to 0. Writes at other
1500  *
1501  * times have no effect.
1502  *
1503  * The minimum valid value is 8; hardware prevents values less than this
1504  *
1505  * being written, and if attempted, results in 8 being set. For designs with
1506  *
1507  * APB_DATA_WIDTH = 8, the order of programming is important to
1508  *
1509  * ensure the correct operation of DW_apb_i2c. The lower byte must be
1510  *
1511  * programmed first, and then the upper byte is programmed.
1512  *
1513  * When the configuration parameter IC_HC_COUNT_VALUES is set to 1,
1514  *
1515  * this register is read only.
1516  *
1517  * Reset value: IC_SS_SCL_LOW_COUNT configuration parameter
1518  *
1519  * Field Access Macros:
1520  *
1521  */
1522 /* The Least Significant Bit (LSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
1523 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0
1524 /* The Most Significant Bit (MSB) position of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
1525 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15
1526 /* The width in bits of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
1527 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16
1528 /* The mask used to set the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */
1529 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff
1530 /* The mask used to clear the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value. */
1531 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000
1532 /* The reset value of the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field. */
1533 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x1d6
1534 /* Extracts the ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT field value from a register. */
1535 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1536 /* Produces a ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT register field value suitable for setting the register. */
1537 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
1538 
1539 #ifndef __ASSEMBLY__
1540 /*
1541  * WARNING: The C register and register group struct declarations are provided for
1542  * convenience and illustrative purposes. They should, however, be used with
1543  * caution as the C language standard provides no guarantees about the alignment or
1544  * atomicity of device memory accesses. The recommended practice for writing
1545  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1546  * alt_write_word() functions.
1547  *
1548  * The struct declaration for register ALT_I2C_SS_SCL_LCNT.
1549  */
1550 struct ALT_I2C_SS_SCL_LCNT_s
1551 {
1552  uint32_t ic_ss_scl_lcnt : 16; /* ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT */
1553  uint32_t : 16; /* *UNDEFINED* */
1554 };
1555 
1556 /* The typedef declaration for register ALT_I2C_SS_SCL_LCNT. */
1557 typedef volatile struct ALT_I2C_SS_SCL_LCNT_s ALT_I2C_SS_SCL_LCNT_t;
1558 #endif /* __ASSEMBLY__ */
1559 
1560 /* The reset value of the ALT_I2C_SS_SCL_LCNT register. */
1561 #define ALT_I2C_SS_SCL_LCNT_RESET 0x000001d6
1562 /* The byte offset of the ALT_I2C_SS_SCL_LCNT register from the beginning of the component. */
1563 #define ALT_I2C_SS_SCL_LCNT_OFST 0x18
1564 /* The address of the ALT_I2C_SS_SCL_LCNT register. */
1565 #define ALT_I2C_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_LCNT_OFST))
1566 
1567 /*
1568  * Register : ic_fs_scl_hcnt
1569  *
1570  * Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
1571  *
1572  * Size: 16 bits
1573  *
1574  * Address Offset: 0x1c
1575  *
1576  * Read/Write Access: Read/Write
1577  *
1578  * Register Layout
1579  *
1580  * Bits | Access | Reset | Description
1581  * :--------|:-------|:------|:-----------------------------------
1582  * [15:0] | RW | 0x3c | ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT
1583  * [31:16] | ??? | 0x0 | *UNDEFINED*
1584  *
1585  */
1586 /*
1587  * Field : ic_fs_scl_hcnt
1588  *
1589  * This register must be set before any I2C bus transaction can take place to
1590  *
1591  * ensure proper I/O timing. This register sets the SCL clock high-period
1592  *
1593  * count for fast mode or fast mode plus. It is used in high-speed mode to send the
1594  * Master Code
1595  *
1596  * and START BYTE or General CALL.
1597  *
1598  * This register goes away and becomes read-only returning 0s if
1599  *
1600  * IC_MAX_SPEED_MODE = standard. This register can be written only
1601  *
1602  * when the I2C interface is disabled, which corresponds to the IC_ENABLE[0]
1603  *
1604  * register being set to 0. Writes at other times have no effect.
1605  *
1606  * The minimum valid value is 6; hardware prevents values less than this
1607  *
1608  * being written, and if attempted results in 6 being set. For designs with
1609  *
1610  * APB_DATA_WIDTH == 8 the order of programming is important to
1611  *
1612  * ensure the correct operation of the DW_apb_i2c. The lower byte must be
1613  *
1614  * programmed first. Then the upper byte is programmed.
1615  *
1616  * When the configuration parameter IC_HC_COUNT_VALUES is set to 1,
1617  *
1618  * this register is read only.
1619  *
1620  * Reset value: IC_FS_SCL_HIGH_COUNT configuration parameter
1621  *
1622  * Field Access Macros:
1623  *
1624  */
1625 /* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
1626 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0
1627 /* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
1628 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15
1629 /* The width in bits of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
1630 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16
1631 /* The mask used to set the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */
1632 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff
1633 /* The mask used to clear the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value. */
1634 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000
1635 /* The reset value of the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field. */
1636 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x3c
1637 /* Extracts the ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT field value from a register. */
1638 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1639 /* Produces a ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT register field value suitable for setting the register. */
1640 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
1641 
1642 #ifndef __ASSEMBLY__
1643 /*
1644  * WARNING: The C register and register group struct declarations are provided for
1645  * convenience and illustrative purposes. They should, however, be used with
1646  * caution as the C language standard provides no guarantees about the alignment or
1647  * atomicity of device memory accesses. The recommended practice for writing
1648  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1649  * alt_write_word() functions.
1650  *
1651  * The struct declaration for register ALT_I2C_FS_SCL_HCNT.
1652  */
1653 struct ALT_I2C_FS_SCL_HCNT_s
1654 {
1655  uint32_t ic_fs_scl_hcnt : 16; /* ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT */
1656  uint32_t : 16; /* *UNDEFINED* */
1657 };
1658 
1659 /* The typedef declaration for register ALT_I2C_FS_SCL_HCNT. */
1660 typedef volatile struct ALT_I2C_FS_SCL_HCNT_s ALT_I2C_FS_SCL_HCNT_t;
1661 #endif /* __ASSEMBLY__ */
1662 
1663 /* The reset value of the ALT_I2C_FS_SCL_HCNT register. */
1664 #define ALT_I2C_FS_SCL_HCNT_RESET 0x0000003c
1665 /* The byte offset of the ALT_I2C_FS_SCL_HCNT register from the beginning of the component. */
1666 #define ALT_I2C_FS_SCL_HCNT_OFST 0x1c
1667 /* The address of the ALT_I2C_FS_SCL_HCNT register. */
1668 #define ALT_I2C_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_HCNT_OFST))
1669 
1670 /*
1671  * Register : ic_fs_scl_lcnt
1672  *
1673  * Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
1674  *
1675  * Size: 16 bits
1676  *
1677  * Address Offset: 0x20
1678  *
1679  * Read/Write Access: Read/Write
1680  *
1681  * Register Layout
1682  *
1683  * Bits | Access | Reset | Description
1684  * :--------|:-------|:------|:-----------------------------------
1685  * [15:0] | RW | 0x82 | ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT
1686  * [31:16] | ??? | 0x0 | *UNDEFINED*
1687  *
1688  */
1689 /*
1690  * Field : ic_fs_scl_lcnt
1691  *
1692  * This register must be set before any I2C bus transaction can take place to
1693  *
1694  * ensure proper I/O timing. This register sets the SCL clock low period count
1695  *
1696  * for fast speed. It is used in high-speed mode to send the Master Code and
1697  *
1698  * START BYTE or General CALL.
1699  *
1700  * This register goes away and becomes read-only returning 0s if
1701  *
1702  * IC_MAX_SPEED_MODE = standard.
1703  *
1704  * This register can be written only when the I2C interface is disabled, which
1705  *
1706  * corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times
1707  *
1708  * have no effect.
1709  *
1710  * The minimum valid value is 8; hardware prevents values less than this
1711  *
1712  * being written, and if attempted results in 8 being set. For designs with
1713  *
1714  * APB_DATA_WIDTH = 8 the order of programming is important to ensure
1715  *
1716  * the correct operation of the DW_apb_i2c. The lower byte must be
1717  *
1718  * programmed first. Then the upper byte is programmed. If the value is less
1719  *
1720  * than 8 then the count value gets changed to 8.
1721  *
1722  * When the configuration parameter IC_HC_COUNT_VALUES is set to 1,
1723  *
1724  * this register is read only.
1725  *
1726  * Reset value: IC_FS_SCL_LOW_COUNT configuration parameter
1727  *
1728  * Field Access Macros:
1729  *
1730  */
1731 /* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
1732 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0
1733 /* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
1734 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15
1735 /* The width in bits of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
1736 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16
1737 /* The mask used to set the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */
1738 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff
1739 /* The mask used to clear the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value. */
1740 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000
1741 /* The reset value of the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field. */
1742 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x82
1743 /* Extracts the ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT field value from a register. */
1744 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1745 /* Produces a ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT register field value suitable for setting the register. */
1746 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
1747 
1748 #ifndef __ASSEMBLY__
1749 /*
1750  * WARNING: The C register and register group struct declarations are provided for
1751  * convenience and illustrative purposes. They should, however, be used with
1752  * caution as the C language standard provides no guarantees about the alignment or
1753  * atomicity of device memory accesses. The recommended practice for writing
1754  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1755  * alt_write_word() functions.
1756  *
1757  * The struct declaration for register ALT_I2C_FS_SCL_LCNT.
1758  */
1759 struct ALT_I2C_FS_SCL_LCNT_s
1760 {
1761  uint32_t ic_fs_scl_lcnt : 16; /* ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT */
1762  uint32_t : 16; /* *UNDEFINED* */
1763 };
1764 
1765 /* The typedef declaration for register ALT_I2C_FS_SCL_LCNT. */
1766 typedef volatile struct ALT_I2C_FS_SCL_LCNT_s ALT_I2C_FS_SCL_LCNT_t;
1767 #endif /* __ASSEMBLY__ */
1768 
1769 /* The reset value of the ALT_I2C_FS_SCL_LCNT register. */
1770 #define ALT_I2C_FS_SCL_LCNT_RESET 0x00000082
1771 /* The byte offset of the ALT_I2C_FS_SCL_LCNT register from the beginning of the component. */
1772 #define ALT_I2C_FS_SCL_LCNT_OFST 0x20
1773 /* The address of the ALT_I2C_FS_SCL_LCNT register. */
1774 #define ALT_I2C_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_LCNT_OFST))
1775 
1776 /*
1777  * Register : ic_intr_stat
1778  *
1779  * Name: I2C Interrupt Status Register
1780  *
1781  * Size: 14 bits
1782  *
1783  * Address Offset: 0x2C
1784  *
1785  * Read/Write Access: Read
1786  *
1787  * Each bit in this register has a corresponding mask bit
1788  *
1789  * in the IC_INTR_MASK register. These bits are cleared by reading the matching
1790  *
1791  * interrupt clear register. The unmasked raw versions of these bits are
1792  *
1793  * available in the IC_RAW_INTR_STAT register.
1794  *
1795  * Register Layout
1796  *
1797  * Bits | Access | Reset | Description
1798  * :--------|:-------|:------|:--------------------------------
1799  * [0] | R | 0x0 | ALT_I2C_INTR_STAT_R_RX_UNDER
1800  * [1] | R | 0x0 | ALT_I2C_INTR_STAT_R_RX_OVER
1801  * [2] | R | 0x0 | ALT_I2C_INTR_STAT_R_RX_FULL
1802  * [3] | R | 0x0 | ALT_I2C_INTR_STAT_R_TX_OVER
1803  * [4] | R | 0x0 | ALT_I2C_INTR_STAT_R_TX_EMPTY
1804  * [5] | R | 0x0 | ALT_I2C_INTR_STAT_R_RD_REQ
1805  * [6] | R | 0x0 | ALT_I2C_INTR_STAT_R_TX_ABRT
1806  * [7] | R | 0x0 | ALT_I2C_INTR_STAT_R_RX_DONE
1807  * [8] | R | 0x0 | ALT_I2C_INTR_STAT_R_ACTIVITY
1808  * [9] | R | 0x0 | ALT_I2C_INTR_STAT_R_STOP_DET
1809  * [10] | R | 0x0 | ALT_I2C_INTR_STAT_R_START_DET
1810  * [11] | R | 0x0 | ALT_I2C_INTR_STAT_R_GEN_CALL
1811  * [12] | R | 0x0 | ALT_I2C_INTR_STAT_R_RESTART_DET
1812  * [13] | R | 0x0 | ALT_I2C_INTR_STAT_R_MST_ON_HOLD
1813  * [31:14] | ??? | 0x0 | *UNDEFINED*
1814  *
1815  */
1816 /*
1817  * Field : r_rx_under
1818  *
1819  * Set if the processor attempts to read the receive buffer when it is empty by
1820  *
1821  * reading from the IC_DATA_CMD register. If the module is disabled
1822  *
1823  * (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state
1824  *
1825  * machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
1826  *
1827  * Reset value: 0x0
1828  *
1829  * Field Access Macros:
1830  *
1831  */
1832 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */
1833 #define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0
1834 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */
1835 #define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0
1836 /* The width in bits of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */
1837 #define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1
1838 /* The mask used to set the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */
1839 #define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001
1840 /* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_UNDER register field value. */
1841 #define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe
1842 /* The reset value of the ALT_I2C_INTR_STAT_R_RX_UNDER register field. */
1843 #define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0
1844 /* Extracts the ALT_I2C_INTR_STAT_R_RX_UNDER field value from a register. */
1845 #define ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
1846 /* Produces a ALT_I2C_INTR_STAT_R_RX_UNDER register field value suitable for setting the register. */
1847 #define ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
1848 
1849 /*
1850  * Field : r_rx_over
1851  *
1852  * Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and
1853  *
1854  * an additional byte is received from an external I2C device. The DW_apb_i2c
1855  *
1856  * acknowledges this, but any data bytes received after the FIFO is full are lost.
1857  * If
1858  *
1859  * the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the
1860  *
1861  * master or slave state machines go into idle, and when ic_en goes to 0, this
1862  *
1863  * interrupt is cleared.
1864  *
1865  * NOTE: If the parameter IC_RX_FULL_HLD_BUS_EN=1, then the RX_OVER interrupt is
1866  *
1867  * never set to 1, because the criteria to set this interrupt are never met.
1868  *
1869  * Reset value: 0x0
1870  *
1871  * Field Access Macros:
1872  *
1873  */
1874 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */
1875 #define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1
1876 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */
1877 #define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1
1878 /* The width in bits of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */
1879 #define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1
1880 /* The mask used to set the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */
1881 #define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002
1882 /* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_OVER register field value. */
1883 #define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd
1884 /* The reset value of the ALT_I2C_INTR_STAT_R_RX_OVER register field. */
1885 #define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0
1886 /* Extracts the ALT_I2C_INTR_STAT_R_RX_OVER field value from a register. */
1887 #define ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
1888 /* Produces a ALT_I2C_INTR_STAT_R_RX_OVER register field value suitable for setting the register. */
1889 #define ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
1890 
1891 /*
1892  * Field : r_rx_full
1893  *
1894  * Set when the receive buffer reaches or goes above the RX_TL threshold in the
1895  *
1896  * IC_RX_TL register. It is automatically cleared by hardware when buffer level
1897  *
1898  * goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the
1899  *
1900  * RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this
1901  *
1902  * bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of
1903  *
1904  * the activity that continues.
1905  *
1906  * Reset value: 0x0
1907  *
1908  * Field Access Macros:
1909  *
1910  */
1911 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */
1912 #define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2
1913 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */
1914 #define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2
1915 /* The width in bits of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */
1916 #define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1
1917 /* The mask used to set the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */
1918 #define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004
1919 /* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_FULL register field value. */
1920 #define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb
1921 /* The reset value of the ALT_I2C_INTR_STAT_R_RX_FULL register field. */
1922 #define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0
1923 /* Extracts the ALT_I2C_INTR_STAT_R_RX_FULL field value from a register. */
1924 #define ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
1925 /* Produces a ALT_I2C_INTR_STAT_R_RX_FULL register field value suitable for setting the register. */
1926 #define ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
1927 
1928 /*
1929  * Field : r_tx_over
1930  *
1931  * Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH
1932  *
1933  * and the processor attempts to issue another I2C command by writing to the
1934  *
1935  * IC_DATA_CMD register. When the module is disabled, this bit keeps its level
1936  *
1937  * until the master or slave state machines go into idle, and when ic_en goes to 0,
1938  *
1939  * this interrupt is cleared.
1940  *
1941  * Reset value: 0x0
1942  *
1943  * Field Access Macros:
1944  *
1945  */
1946 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */
1947 #define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3
1948 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */
1949 #define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3
1950 /* The width in bits of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */
1951 #define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1
1952 /* The mask used to set the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */
1953 #define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008
1954 /* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_OVER register field value. */
1955 #define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7
1956 /* The reset value of the ALT_I2C_INTR_STAT_R_TX_OVER register field. */
1957 #define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0
1958 /* Extracts the ALT_I2C_INTR_STAT_R_TX_OVER field value from a register. */
1959 #define ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
1960 /* Produces a ALT_I2C_INTR_STAT_R_TX_OVER register field value suitable for setting the register. */
1961 #define ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
1962 
1963 /*
1964  * Field : r_tx_empty
1965  *
1966  * The behavior of the TX_EMPTY interrupt status differs based on the
1967  *
1968  * TX_EMPTY_CTRL selection in the IC_CON register.
1969  *
1970  * When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or
1971  * below the threshold
1972  *
1973  * value set in the IC_TX_TL register.
1974  *
1975  * When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or
1976  * below the threshold
1977  *
1978  * value set in the IC_TX_TL register and the transmission of the
1979  *
1980  * address/data from the internal shift register for the most recently popped
1981  *
1982  * command is completed.
1983  *
1984  * It is automatically cleared by hardware when the buffer level goes above the
1985  *
1986  * threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in
1987  *
1988  * reset. There the TX FIFO looks like it has no data within it, so this bit is set
1989  *
1990  * to 1, provided there is activity in the master or slave state machines. When
1991  *
1992  * there is no longer any activity, then with ic_en=0, this bit is set to 0.
1993  *
1994  * Reset value: 0x0
1995  *
1996  * Field Access Macros:
1997  *
1998  */
1999 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */
2000 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4
2001 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */
2002 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4
2003 /* The width in bits of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */
2004 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1
2005 /* The mask used to set the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */
2006 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010
2007 /* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value. */
2008 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef
2009 /* The reset value of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field. */
2010 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0
2011 /* Extracts the ALT_I2C_INTR_STAT_R_TX_EMPTY field value from a register. */
2012 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
2013 /* Produces a ALT_I2C_INTR_STAT_R_TX_EMPTY register field value suitable for setting the register. */
2014 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
2015 
2016 /*
2017  * Field : r_rd_req
2018  *
2019  * This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C
2020  *
2021  * master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds
2022  *
2023  * the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which
2024  * means
2025  *
2026  * that the slave has been addressed by a remote master that is asking for data to
2027  *
2028  * be transferred. The processor must respond to this interrupt and then write the
2029  *
2030  * requested data to the IC_DATA_CMD register. This bit is set to 0 just after the
2031  *
2032  * processor reads the IC_CLR_RD_REQ register.
2033  *
2034  * Reset value: 0x0
2035  *
2036  * Field Access Macros:
2037  *
2038  */
2039 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */
2040 #define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5
2041 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */
2042 #define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5
2043 /* The width in bits of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */
2044 #define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1
2045 /* The mask used to set the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */
2046 #define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020
2047 /* The mask used to clear the ALT_I2C_INTR_STAT_R_RD_REQ register field value. */
2048 #define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf
2049 /* The reset value of the ALT_I2C_INTR_STAT_R_RD_REQ register field. */
2050 #define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0
2051 /* Extracts the ALT_I2C_INTR_STAT_R_RD_REQ field value from a register. */
2052 #define ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
2053 /* Produces a ALT_I2C_INTR_STAT_R_RD_REQ register field value suitable for setting the register. */
2054 #define ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
2055 
2056 /*
2057  * Field : r_tx_abrt
2058  *
2059  * This bit indicates if DW_apb_i2c, as an I2C transmitter,
2060  *
2061  * is unable to complete the intended actions on the
2062  *
2063  * contents of the transmit FIFO. This situation can
2064  *
2065  * occur both as an I2C master or an I2C slave, and is
2066  *
2067  * referred to as a 'transmit abort'.
2068  *
2069  * When this bit is set to 1, the IC_TX_ABRT_SOURCE register
2070  *
2071  * indicates the reason why the transmit abort takes places.
2072  *
2073  * NOTE: The DW_apb_i2c flushes/resets/empties the TX FIFO whenever this
2074  *
2075  * bit is set. The TX FIFO remains in this flushed state until the register
2076  *
2077  * IC_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then
2078  *
2079  * ready to accept more data bytes from the APB interface.
2080  *
2081  * Reset value: 0x0
2082  *
2083  * Field Access Macros:
2084  *
2085  */
2086 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */
2087 #define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6
2088 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */
2089 #define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6
2090 /* The width in bits of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */
2091 #define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1
2092 /* The mask used to set the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */
2093 #define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040
2094 /* The mask used to clear the ALT_I2C_INTR_STAT_R_TX_ABRT register field value. */
2095 #define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf
2096 /* The reset value of the ALT_I2C_INTR_STAT_R_TX_ABRT register field. */
2097 #define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0
2098 /* Extracts the ALT_I2C_INTR_STAT_R_TX_ABRT field value from a register. */
2099 #define ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
2100 /* Produces a ALT_I2C_INTR_STAT_R_TX_ABRT register field value suitable for setting the register. */
2101 #define ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
2102 
2103 /*
2104  * Field : r_rx_done
2105  *
2106  * When the DW_apb_i2c is acting as a slave-transmitter,
2107  *
2108  * this bit is set to 1 if the master does not acknowledge
2109  *
2110  * a transmitted byte. This occurs on the last byte of
2111  *
2112  * the transmission, indicating that the transmission is done.
2113  *
2114  * Reset value: 0x0
2115  *
2116  * Field Access Macros:
2117  *
2118  */
2119 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */
2120 #define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7
2121 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */
2122 #define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7
2123 /* The width in bits of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */
2124 #define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1
2125 /* The mask used to set the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */
2126 #define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080
2127 /* The mask used to clear the ALT_I2C_INTR_STAT_R_RX_DONE register field value. */
2128 #define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f
2129 /* The reset value of the ALT_I2C_INTR_STAT_R_RX_DONE register field. */
2130 #define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0
2131 /* Extracts the ALT_I2C_INTR_STAT_R_RX_DONE field value from a register. */
2132 #define ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
2133 /* Produces a ALT_I2C_INTR_STAT_R_RX_DONE register field value suitable for setting the register. */
2134 #define ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
2135 
2136 /*
2137  * Field : r_activity
2138  *
2139  * This bit captures DW_apb_i2c activity and stays set until it is cleared. There
2140  *
2141  * are four ways to clear it:
2142  *
2143  * * Disabling the DW_apb_i2c
2144  *
2145  * * Reading the IC_CLR_ACTIVITY register
2146  *
2147  * * Reading the IC_CLR_INTR register
2148  *
2149  * * System reset
2150  *
2151  * Once this bit is set, it stays set unless one of the four methods is used to
2152  * clear it.
2153  *
2154  * Even if the DW_apb_i2c module is idle, this bit remains set until cleared,
2155  *
2156  * indicating that there was activity on the bus.
2157  *
2158  * Reset value: 0x0
2159  *
2160  * Field Access Macros:
2161  *
2162  */
2163 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */
2164 #define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8
2165 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */
2166 #define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8
2167 /* The width in bits of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */
2168 #define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1
2169 /* The mask used to set the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */
2170 #define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100
2171 /* The mask used to clear the ALT_I2C_INTR_STAT_R_ACTIVITY register field value. */
2172 #define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff
2173 /* The reset value of the ALT_I2C_INTR_STAT_R_ACTIVITY register field. */
2174 #define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0
2175 /* Extracts the ALT_I2C_INTR_STAT_R_ACTIVITY field value from a register. */
2176 #define ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
2177 /* Produces a ALT_I2C_INTR_STAT_R_ACTIVITY register field value suitable for setting the register. */
2178 #define ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
2179 
2180 /*
2181  * Field : r_stop_det
2182  *
2183  * The behavior of the STOP_DET interrupt status differs based on the
2184  *
2185  * STOP_DET_IFADDRESSED selection in the IC_CON register
2186  *
2187  * When STOP_DET_IFADDRESSED =0 : Indicates whether a STOP condition has occurred
2188  * on the I2C interface
2189  *
2190  * regardless of whether DW_apb_i2c is operating in slave or master mode.
2191  *
2192  * In slave mode, a STOP_DET interrupt is generated irrespective of whether
2193  *
2194  * the slave is addressed or not.
2195  *
2196  * When STOP_DET_IFADDRESSED = 1 :
2197  *
2198  * In Master Mode (MASTER_MODE = 1'b1), indicates a STOP condition has occured on
2199  * the I2C interface.
2200  *
2201  * In Slave Mode (MASTER_MODE = 1'b0),STOP_DET interrupt is generated only if the
2202  * slave is addressed.
2203  *
2204  * NOTE: During a general call address, this slave does not issue a STOP_DET
2205  *
2206  * interrupt if STOP_DET_IFADDRESSED=1'b1, even if the slave responds to
2207  *
2208  * the general call address by generating ACK. The STOP_DET interrupt is
2209  *
2210  * generated only when the transmitted address matches the slave address
2211  *
2212  * (SAR).
2213  *
2214  * Reset value: 0x0
2215  *
2216  * Field Access Macros:
2217  *
2218  */
2219 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */
2220 #define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9
2221 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */
2222 #define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9
2223 /* The width in bits of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */
2224 #define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1
2225 /* The mask used to set the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */
2226 #define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200
2227 /* The mask used to clear the ALT_I2C_INTR_STAT_R_STOP_DET register field value. */
2228 #define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff
2229 /* The reset value of the ALT_I2C_INTR_STAT_R_STOP_DET register field. */
2230 #define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0
2231 /* Extracts the ALT_I2C_INTR_STAT_R_STOP_DET field value from a register. */
2232 #define ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
2233 /* Produces a ALT_I2C_INTR_STAT_R_STOP_DET register field value suitable for setting the register. */
2234 #define ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
2235 
2236 /*
2237  * Field : r_start_det
2238  *
2239  * Indicates whether a START or RESTART condition has occurred on the I2C
2240  *
2241  * interface regardless of whether DW_apb_i2c is operating in slave or master
2242  *
2243  * mode.
2244  *
2245  * Reset value: 0x0
2246  *
2247  * Field Access Macros:
2248  *
2249  */
2250 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */
2251 #define ALT_I2C_INTR_STAT_R_START_DET_LSB 10
2252 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field. */
2253 #define ALT_I2C_INTR_STAT_R_START_DET_MSB 10
2254 /* The width in bits of the ALT_I2C_INTR_STAT_R_START_DET register field. */
2255 #define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1
2256 /* The mask used to set the ALT_I2C_INTR_STAT_R_START_DET register field value. */
2257 #define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400
2258 /* The mask used to clear the ALT_I2C_INTR_STAT_R_START_DET register field value. */
2259 #define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff
2260 /* The reset value of the ALT_I2C_INTR_STAT_R_START_DET register field. */
2261 #define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0
2262 /* Extracts the ALT_I2C_INTR_STAT_R_START_DET field value from a register. */
2263 #define ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10)
2264 /* Produces a ALT_I2C_INTR_STAT_R_START_DET register field value suitable for setting the register. */
2265 #define ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400)
2266 
2267 /*
2268  * Field : r_gen_call
2269  *
2270  * Set only when a General Call address is received and it is acknowledged. It
2271  *
2272  * stays set until it is cleared either by disabling DW_apb_i2c or when the CPU
2273  *
2274  * reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the
2275  *
2276  * received data in the Rx buffer.
2277  *
2278  * Reset value: 0x0
2279  *
2280  * Field Access Macros:
2281  *
2282  */
2283 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */
2284 #define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11
2285 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */
2286 #define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11
2287 /* The width in bits of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */
2288 #define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1
2289 /* The mask used to set the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */
2290 #define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800
2291 /* The mask used to clear the ALT_I2C_INTR_STAT_R_GEN_CALL register field value. */
2292 #define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff
2293 /* The reset value of the ALT_I2C_INTR_STAT_R_GEN_CALL register field. */
2294 #define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0
2295 /* Extracts the ALT_I2C_INTR_STAT_R_GEN_CALL field value from a register. */
2296 #define ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
2297 /* Produces a ALT_I2C_INTR_STAT_R_GEN_CALL register field value suitable for setting the register. */
2298 #define ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
2299 
2300 /*
2301  * Field : r_restart_det
2302  *
2303  * Indicates a RESTART condition has occurred on the I2C
2304  *
2305  * interface when DW_apb_i2c is operating in slave mode and addressed. This feature
2306  * is avaliable only when IC_SLV_RESTART_DET_EN is enabled.
2307  *
2308  * Reset value: 0x0
2309  *
2310  * Field Access Macros:
2311  *
2312  */
2313 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RESTART_DET register field. */
2314 #define ALT_I2C_INTR_STAT_R_RESTART_DET_LSB 12
2315 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RESTART_DET register field. */
2316 #define ALT_I2C_INTR_STAT_R_RESTART_DET_MSB 12
2317 /* The width in bits of the ALT_I2C_INTR_STAT_R_RESTART_DET register field. */
2318 #define ALT_I2C_INTR_STAT_R_RESTART_DET_WIDTH 1
2319 /* The mask used to set the ALT_I2C_INTR_STAT_R_RESTART_DET register field value. */
2320 #define ALT_I2C_INTR_STAT_R_RESTART_DET_SET_MSK 0x00001000
2321 /* The mask used to clear the ALT_I2C_INTR_STAT_R_RESTART_DET register field value. */
2322 #define ALT_I2C_INTR_STAT_R_RESTART_DET_CLR_MSK 0xffffefff
2323 /* The reset value of the ALT_I2C_INTR_STAT_R_RESTART_DET register field. */
2324 #define ALT_I2C_INTR_STAT_R_RESTART_DET_RESET 0x0
2325 /* Extracts the ALT_I2C_INTR_STAT_R_RESTART_DET field value from a register. */
2326 #define ALT_I2C_INTR_STAT_R_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
2327 /* Produces a ALT_I2C_INTR_STAT_R_RESTART_DET register field value suitable for setting the register. */
2328 #define ALT_I2C_INTR_STAT_R_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
2329 
2330 /*
2331  * Field : r_master_on_hold
2332  *
2333  * Indicates whether master is holding the bus and TX FIFO is empty.
2334  *
2335  * Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1.
2336  *
2337  * Reset value: 0x0
2338  *
2339  * Field Access Macros:
2340  *
2341  */
2342 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field. */
2343 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_LSB 13
2344 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field. */
2345 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_MSB 13
2346 /* The width in bits of the ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field. */
2347 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_WIDTH 1
2348 /* The mask used to set the ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field value. */
2349 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_SET_MSK 0x00002000
2350 /* The mask used to clear the ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field value. */
2351 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_CLR_MSK 0xffffdfff
2352 /* The reset value of the ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field. */
2353 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_RESET 0x0
2354 /* Extracts the ALT_I2C_INTR_STAT_R_MST_ON_HOLD field value from a register. */
2355 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
2356 /* Produces a ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field value suitable for setting the register. */
2357 #define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
2358 
2359 #ifndef __ASSEMBLY__
2360 /*
2361  * WARNING: The C register and register group struct declarations are provided for
2362  * convenience and illustrative purposes. They should, however, be used with
2363  * caution as the C language standard provides no guarantees about the alignment or
2364  * atomicity of device memory accesses. The recommended practice for writing
2365  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2366  * alt_write_word() functions.
2367  *
2368  * The struct declaration for register ALT_I2C_INTR_STAT.
2369  */
2370 struct ALT_I2C_INTR_STAT_s
2371 {
2372  const uint32_t r_rx_under : 1; /* ALT_I2C_INTR_STAT_R_RX_UNDER */
2373  const uint32_t r_rx_over : 1; /* ALT_I2C_INTR_STAT_R_RX_OVER */
2374  const uint32_t r_rx_full : 1; /* ALT_I2C_INTR_STAT_R_RX_FULL */
2375  const uint32_t r_tx_over : 1; /* ALT_I2C_INTR_STAT_R_TX_OVER */
2376  const uint32_t r_tx_empty : 1; /* ALT_I2C_INTR_STAT_R_TX_EMPTY */
2377  const uint32_t r_rd_req : 1; /* ALT_I2C_INTR_STAT_R_RD_REQ */
2378  const uint32_t r_tx_abrt : 1; /* ALT_I2C_INTR_STAT_R_TX_ABRT */
2379  const uint32_t r_rx_done : 1; /* ALT_I2C_INTR_STAT_R_RX_DONE */
2380  const uint32_t r_activity : 1; /* ALT_I2C_INTR_STAT_R_ACTIVITY */
2381  const uint32_t r_stop_det : 1; /* ALT_I2C_INTR_STAT_R_STOP_DET */
2382  const uint32_t r_start_det : 1; /* ALT_I2C_INTR_STAT_R_START_DET */
2383  const uint32_t r_gen_call : 1; /* ALT_I2C_INTR_STAT_R_GEN_CALL */
2384  const uint32_t r_restart_det : 1; /* ALT_I2C_INTR_STAT_R_RESTART_DET */
2385  const uint32_t r_master_on_hold : 1; /* ALT_I2C_INTR_STAT_R_MST_ON_HOLD */
2386  uint32_t : 18; /* *UNDEFINED* */
2387 };
2388 
2389 /* The typedef declaration for register ALT_I2C_INTR_STAT. */
2390 typedef volatile struct ALT_I2C_INTR_STAT_s ALT_I2C_INTR_STAT_t;
2391 #endif /* __ASSEMBLY__ */
2392 
2393 /* The reset value of the ALT_I2C_INTR_STAT register. */
2394 #define ALT_I2C_INTR_STAT_RESET 0x00000000
2395 /* The byte offset of the ALT_I2C_INTR_STAT register from the beginning of the component. */
2396 #define ALT_I2C_INTR_STAT_OFST 0x2c
2397 /* The address of the ALT_I2C_INTR_STAT register. */
2398 #define ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST))
2399 
2400 /*
2401  * Register : ic_intr_mask
2402  *
2403  * Name: I2C Interrupt Mask Register
2404  *
2405  * Size: 14 bits
2406  *
2407  * Address Offset: 0x30
2408  *
2409  * Read/Write Access: Read/Write However,
2410  *
2411  * if configuration parameter IC_SLV_RESTART_DET = 0, bit 13 is read only;
2412  *
2413  * if configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0 or
2414  * IC_EMPTYFIFO_HOLD_MASTER_EN = 0, bit 14 is read only.
2415  *
2416  * These bits mask their corresponding interrupt status bits.
2417  *
2418  * They are active high; a value of 0 prevents a bit from
2419  *
2420  * generating an interrupt.
2421  *
2422  * Register Layout
2423  *
2424  * Bits | Access | Reset | Description
2425  * :--------|:-------|:------|:-------------------------------
2426  * [0] | RW | 0x1 | ALT_I2C_INTR_MSK_M_RX_UNDER
2427  * [1] | RW | 0x1 | ALT_I2C_INTR_MSK_M_RX_OVER
2428  * [2] | RW | 0x1 | ALT_I2C_INTR_MSK_M_RX_FULL
2429  * [3] | RW | 0x1 | ALT_I2C_INTR_MSK_M_TX_OVER
2430  * [4] | RW | 0x1 | ALT_I2C_INTR_MSK_M_TX_EMPTY
2431  * [5] | RW | 0x1 | ALT_I2C_INTR_MSK_M_RD_REQ
2432  * [6] | RW | 0x1 | ALT_I2C_INTR_MSK_M_TX_ABRT
2433  * [7] | RW | 0x1 | ALT_I2C_INTR_MSK_M_RX_DONE
2434  * [8] | RW | 0x0 | ALT_I2C_INTR_MSK_M_ACTIVITY
2435  * [9] | RW | 0x0 | ALT_I2C_INTR_MSK_M_STOP_DET
2436  * [10] | RW | 0x0 | ALT_I2C_INTR_MSK_M_START_DET
2437  * [11] | RW | 0x1 | ALT_I2C_INTR_MSK_M_GEN_CALL
2438  * [12] | RW | 0x0 | ALT_I2C_INTR_MSK_M_RESTART_DET
2439  * [13] | RW | 0x0 | ALT_I2C_INTR_MSK_M_MST_ON_HOLD
2440  * [31:14] | ??? | 0x0 | *UNDEFINED*
2441  *
2442  */
2443 /*
2444  * Field : m_rx_under
2445  *
2446  * This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.
2447  *
2448  * Reset value: 0x1
2449  *
2450  * Field Access Macros:
2451  *
2452  */
2453 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */
2454 #define ALT_I2C_INTR_MSK_M_RX_UNDER_LSB 0
2455 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */
2456 #define ALT_I2C_INTR_MSK_M_RX_UNDER_MSB 0
2457 /* The width in bits of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */
2458 #define ALT_I2C_INTR_MSK_M_RX_UNDER_WIDTH 1
2459 /* The mask used to set the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */
2460 #define ALT_I2C_INTR_MSK_M_RX_UNDER_SET_MSK 0x00000001
2461 /* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_UNDER register field value. */
2462 #define ALT_I2C_INTR_MSK_M_RX_UNDER_CLR_MSK 0xfffffffe
2463 /* The reset value of the ALT_I2C_INTR_MSK_M_RX_UNDER register field. */
2464 #define ALT_I2C_INTR_MSK_M_RX_UNDER_RESET 0x1
2465 /* Extracts the ALT_I2C_INTR_MSK_M_RX_UNDER field value from a register. */
2466 #define ALT_I2C_INTR_MSK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2467 /* Produces a ALT_I2C_INTR_MSK_M_RX_UNDER register field value suitable for setting the register. */
2468 #define ALT_I2C_INTR_MSK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2469 
2470 /*
2471  * Field : m_rx_over
2472  *
2473  * This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.
2474  *
2475  * Reset value: 0x1
2476  *
2477  * Field Access Macros:
2478  *
2479  */
2480 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */
2481 #define ALT_I2C_INTR_MSK_M_RX_OVER_LSB 1
2482 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */
2483 #define ALT_I2C_INTR_MSK_M_RX_OVER_MSB 1
2484 /* The width in bits of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */
2485 #define ALT_I2C_INTR_MSK_M_RX_OVER_WIDTH 1
2486 /* The mask used to set the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */
2487 #define ALT_I2C_INTR_MSK_M_RX_OVER_SET_MSK 0x00000002
2488 /* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_OVER register field value. */
2489 #define ALT_I2C_INTR_MSK_M_RX_OVER_CLR_MSK 0xfffffffd
2490 /* The reset value of the ALT_I2C_INTR_MSK_M_RX_OVER register field. */
2491 #define ALT_I2C_INTR_MSK_M_RX_OVER_RESET 0x1
2492 /* Extracts the ALT_I2C_INTR_MSK_M_RX_OVER field value from a register. */
2493 #define ALT_I2C_INTR_MSK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
2494 /* Produces a ALT_I2C_INTR_MSK_M_RX_OVER register field value suitable for setting the register. */
2495 #define ALT_I2C_INTR_MSK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
2496 
2497 /*
2498  * Field : m_rx_full
2499  *
2500  * This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.
2501  *
2502  * Reset value: 0x1
2503  *
2504  * Field Access Macros:
2505  *
2506  */
2507 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */
2508 #define ALT_I2C_INTR_MSK_M_RX_FULL_LSB 2
2509 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */
2510 #define ALT_I2C_INTR_MSK_M_RX_FULL_MSB 2
2511 /* The width in bits of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */
2512 #define ALT_I2C_INTR_MSK_M_RX_FULL_WIDTH 1
2513 /* The mask used to set the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */
2514 #define ALT_I2C_INTR_MSK_M_RX_FULL_SET_MSK 0x00000004
2515 /* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_FULL register field value. */
2516 #define ALT_I2C_INTR_MSK_M_RX_FULL_CLR_MSK 0xfffffffb
2517 /* The reset value of the ALT_I2C_INTR_MSK_M_RX_FULL register field. */
2518 #define ALT_I2C_INTR_MSK_M_RX_FULL_RESET 0x1
2519 /* Extracts the ALT_I2C_INTR_MSK_M_RX_FULL field value from a register. */
2520 #define ALT_I2C_INTR_MSK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
2521 /* Produces a ALT_I2C_INTR_MSK_M_RX_FULL register field value suitable for setting the register. */
2522 #define ALT_I2C_INTR_MSK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
2523 
2524 /*
2525  * Field : m_tx_over
2526  *
2527  * This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.
2528  *
2529  * Reset value: 0x1
2530  *
2531  * Field Access Macros:
2532  *
2533  */
2534 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */
2535 #define ALT_I2C_INTR_MSK_M_TX_OVER_LSB 3
2536 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */
2537 #define ALT_I2C_INTR_MSK_M_TX_OVER_MSB 3
2538 /* The width in bits of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */
2539 #define ALT_I2C_INTR_MSK_M_TX_OVER_WIDTH 1
2540 /* The mask used to set the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */
2541 #define ALT_I2C_INTR_MSK_M_TX_OVER_SET_MSK 0x00000008
2542 /* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_OVER register field value. */
2543 #define ALT_I2C_INTR_MSK_M_TX_OVER_CLR_MSK 0xfffffff7
2544 /* The reset value of the ALT_I2C_INTR_MSK_M_TX_OVER register field. */
2545 #define ALT_I2C_INTR_MSK_M_TX_OVER_RESET 0x1
2546 /* Extracts the ALT_I2C_INTR_MSK_M_TX_OVER field value from a register. */
2547 #define ALT_I2C_INTR_MSK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
2548 /* Produces a ALT_I2C_INTR_MSK_M_TX_OVER register field value suitable for setting the register. */
2549 #define ALT_I2C_INTR_MSK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
2550 
2551 /*
2552  * Field : m_tx_empty
2553  *
2554  * This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.
2555  *
2556  * Reset value: 0x1
2557  *
2558  * Field Access Macros:
2559  *
2560  */
2561 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */
2562 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_LSB 4
2563 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */
2564 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_MSB 4
2565 /* The width in bits of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */
2566 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_WIDTH 1
2567 /* The mask used to set the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */
2568 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET_MSK 0x00000010
2569 /* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_EMPTY register field value. */
2570 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_CLR_MSK 0xffffffef
2571 /* The reset value of the ALT_I2C_INTR_MSK_M_TX_EMPTY register field. */
2572 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_RESET 0x1
2573 /* Extracts the ALT_I2C_INTR_MSK_M_TX_EMPTY field value from a register. */
2574 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
2575 /* Produces a ALT_I2C_INTR_MSK_M_TX_EMPTY register field value suitable for setting the register. */
2576 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
2577 
2578 /*
2579  * Field : m_rd_req
2580  *
2581  * This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.
2582  *
2583  * Reset value: 0x1
2584  *
2585  * Field Access Macros:
2586  *
2587  */
2588 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */
2589 #define ALT_I2C_INTR_MSK_M_RD_REQ_LSB 5
2590 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */
2591 #define ALT_I2C_INTR_MSK_M_RD_REQ_MSB 5
2592 /* The width in bits of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */
2593 #define ALT_I2C_INTR_MSK_M_RD_REQ_WIDTH 1
2594 /* The mask used to set the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */
2595 #define ALT_I2C_INTR_MSK_M_RD_REQ_SET_MSK 0x00000020
2596 /* The mask used to clear the ALT_I2C_INTR_MSK_M_RD_REQ register field value. */
2597 #define ALT_I2C_INTR_MSK_M_RD_REQ_CLR_MSK 0xffffffdf
2598 /* The reset value of the ALT_I2C_INTR_MSK_M_RD_REQ register field. */
2599 #define ALT_I2C_INTR_MSK_M_RD_REQ_RESET 0x1
2600 /* Extracts the ALT_I2C_INTR_MSK_M_RD_REQ field value from a register. */
2601 #define ALT_I2C_INTR_MSK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
2602 /* Produces a ALT_I2C_INTR_MSK_M_RD_REQ register field value suitable for setting the register. */
2603 #define ALT_I2C_INTR_MSK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
2604 
2605 /*
2606  * Field : m_tx_abrt
2607  *
2608  * This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.
2609  *
2610  * Reset value: 0x1
2611  *
2612  * Field Access Macros:
2613  *
2614  */
2615 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */
2616 #define ALT_I2C_INTR_MSK_M_TX_ABRT_LSB 6
2617 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */
2618 #define ALT_I2C_INTR_MSK_M_TX_ABRT_MSB 6
2619 /* The width in bits of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */
2620 #define ALT_I2C_INTR_MSK_M_TX_ABRT_WIDTH 1
2621 /* The mask used to set the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */
2622 #define ALT_I2C_INTR_MSK_M_TX_ABRT_SET_MSK 0x00000040
2623 /* The mask used to clear the ALT_I2C_INTR_MSK_M_TX_ABRT register field value. */
2624 #define ALT_I2C_INTR_MSK_M_TX_ABRT_CLR_MSK 0xffffffbf
2625 /* The reset value of the ALT_I2C_INTR_MSK_M_TX_ABRT register field. */
2626 #define ALT_I2C_INTR_MSK_M_TX_ABRT_RESET 0x1
2627 /* Extracts the ALT_I2C_INTR_MSK_M_TX_ABRT field value from a register. */
2628 #define ALT_I2C_INTR_MSK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
2629 /* Produces a ALT_I2C_INTR_MSK_M_TX_ABRT register field value suitable for setting the register. */
2630 #define ALT_I2C_INTR_MSK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
2631 
2632 /*
2633  * Field : m_rx_done
2634  *
2635  * This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.
2636  *
2637  * Reset value: 0x1
2638  *
2639  * Field Access Macros:
2640  *
2641  */
2642 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */
2643 #define ALT_I2C_INTR_MSK_M_RX_DONE_LSB 7
2644 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */
2645 #define ALT_I2C_INTR_MSK_M_RX_DONE_MSB 7
2646 /* The width in bits of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */
2647 #define ALT_I2C_INTR_MSK_M_RX_DONE_WIDTH 1
2648 /* The mask used to set the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */
2649 #define ALT_I2C_INTR_MSK_M_RX_DONE_SET_MSK 0x00000080
2650 /* The mask used to clear the ALT_I2C_INTR_MSK_M_RX_DONE register field value. */
2651 #define ALT_I2C_INTR_MSK_M_RX_DONE_CLR_MSK 0xffffff7f
2652 /* The reset value of the ALT_I2C_INTR_MSK_M_RX_DONE register field. */
2653 #define ALT_I2C_INTR_MSK_M_RX_DONE_RESET 0x1
2654 /* Extracts the ALT_I2C_INTR_MSK_M_RX_DONE field value from a register. */
2655 #define ALT_I2C_INTR_MSK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
2656 /* Produces a ALT_I2C_INTR_MSK_M_RX_DONE register field value suitable for setting the register. */
2657 #define ALT_I2C_INTR_MSK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
2658 
2659 /*
2660  * Field : m_activity
2661  *
2662  * This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.
2663  *
2664  * Reset value: 0x0
2665  *
2666  * Field Access Macros:
2667  *
2668  */
2669 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */
2670 #define ALT_I2C_INTR_MSK_M_ACTIVITY_LSB 8
2671 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */
2672 #define ALT_I2C_INTR_MSK_M_ACTIVITY_MSB 8
2673 /* The width in bits of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */
2674 #define ALT_I2C_INTR_MSK_M_ACTIVITY_WIDTH 1
2675 /* The mask used to set the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */
2676 #define ALT_I2C_INTR_MSK_M_ACTIVITY_SET_MSK 0x00000100
2677 /* The mask used to clear the ALT_I2C_INTR_MSK_M_ACTIVITY register field value. */
2678 #define ALT_I2C_INTR_MSK_M_ACTIVITY_CLR_MSK 0xfffffeff
2679 /* The reset value of the ALT_I2C_INTR_MSK_M_ACTIVITY register field. */
2680 #define ALT_I2C_INTR_MSK_M_ACTIVITY_RESET 0x0
2681 /* Extracts the ALT_I2C_INTR_MSK_M_ACTIVITY field value from a register. */
2682 #define ALT_I2C_INTR_MSK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
2683 /* Produces a ALT_I2C_INTR_MSK_M_ACTIVITY register field value suitable for setting the register. */
2684 #define ALT_I2C_INTR_MSK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
2685 
2686 /*
2687  * Field : m_stop_det
2688  *
2689  * This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.
2690  *
2691  * Reset value: 0x0
2692  *
2693  * Field Access Macros:
2694  *
2695  */
2696 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */
2697 #define ALT_I2C_INTR_MSK_M_STOP_DET_LSB 9
2698 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */
2699 #define ALT_I2C_INTR_MSK_M_STOP_DET_MSB 9
2700 /* The width in bits of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */
2701 #define ALT_I2C_INTR_MSK_M_STOP_DET_WIDTH 1
2702 /* The mask used to set the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */
2703 #define ALT_I2C_INTR_MSK_M_STOP_DET_SET_MSK 0x00000200
2704 /* The mask used to clear the ALT_I2C_INTR_MSK_M_STOP_DET register field value. */
2705 #define ALT_I2C_INTR_MSK_M_STOP_DET_CLR_MSK 0xfffffdff
2706 /* The reset value of the ALT_I2C_INTR_MSK_M_STOP_DET register field. */
2707 #define ALT_I2C_INTR_MSK_M_STOP_DET_RESET 0x0
2708 /* Extracts the ALT_I2C_INTR_MSK_M_STOP_DET field value from a register. */
2709 #define ALT_I2C_INTR_MSK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
2710 /* Produces a ALT_I2C_INTR_MSK_M_STOP_DET register field value suitable for setting the register. */
2711 #define ALT_I2C_INTR_MSK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
2712 
2713 /*
2714  * Field : m_start_det
2715  *
2716  * This bit masks the R_START_DET interrupt in IC_INTR_STAT register.
2717  *
2718  * Reset value: 0x0
2719  *
2720  * Field Access Macros:
2721  *
2722  */
2723 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */
2724 #define ALT_I2C_INTR_MSK_M_START_DET_LSB 10
2725 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_START_DET register field. */
2726 #define ALT_I2C_INTR_MSK_M_START_DET_MSB 10
2727 /* The width in bits of the ALT_I2C_INTR_MSK_M_START_DET register field. */
2728 #define ALT_I2C_INTR_MSK_M_START_DET_WIDTH 1
2729 /* The mask used to set the ALT_I2C_INTR_MSK_M_START_DET register field value. */
2730 #define ALT_I2C_INTR_MSK_M_START_DET_SET_MSK 0x00000400
2731 /* The mask used to clear the ALT_I2C_INTR_MSK_M_START_DET register field value. */
2732 #define ALT_I2C_INTR_MSK_M_START_DET_CLR_MSK 0xfffffbff
2733 /* The reset value of the ALT_I2C_INTR_MSK_M_START_DET register field. */
2734 #define ALT_I2C_INTR_MSK_M_START_DET_RESET 0x0
2735 /* Extracts the ALT_I2C_INTR_MSK_M_START_DET field value from a register. */
2736 #define ALT_I2C_INTR_MSK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10)
2737 /* Produces a ALT_I2C_INTR_MSK_M_START_DET register field value suitable for setting the register. */
2738 #define ALT_I2C_INTR_MSK_M_START_DET_SET(value) (((value) << 10) & 0x00000400)
2739 
2740 /*
2741  * Field : m_gen_call
2742  *
2743  * This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.
2744  *
2745  * Reset value: 0x1
2746  *
2747  * Field Access Macros:
2748  *
2749  */
2750 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */
2751 #define ALT_I2C_INTR_MSK_M_GEN_CALL_LSB 11
2752 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */
2753 #define ALT_I2C_INTR_MSK_M_GEN_CALL_MSB 11
2754 /* The width in bits of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */
2755 #define ALT_I2C_INTR_MSK_M_GEN_CALL_WIDTH 1
2756 /* The mask used to set the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */
2757 #define ALT_I2C_INTR_MSK_M_GEN_CALL_SET_MSK 0x00000800
2758 /* The mask used to clear the ALT_I2C_INTR_MSK_M_GEN_CALL register field value. */
2759 #define ALT_I2C_INTR_MSK_M_GEN_CALL_CLR_MSK 0xfffff7ff
2760 /* The reset value of the ALT_I2C_INTR_MSK_M_GEN_CALL register field. */
2761 #define ALT_I2C_INTR_MSK_M_GEN_CALL_RESET 0x1
2762 /* Extracts the ALT_I2C_INTR_MSK_M_GEN_CALL field value from a register. */
2763 #define ALT_I2C_INTR_MSK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
2764 /* Produces a ALT_I2C_INTR_MSK_M_GEN_CALL register field value suitable for setting the register. */
2765 #define ALT_I2C_INTR_MSK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
2766 
2767 /*
2768  * Field : m_restart_det
2769  *
2770  * This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.
2771  *
2772  * Reset value: 0x0
2773  *
2774  * Field Access Macros:
2775  *
2776  */
2777 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_RESTART_DET register field. */
2778 #define ALT_I2C_INTR_MSK_M_RESTART_DET_LSB 12
2779 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_RESTART_DET register field. */
2780 #define ALT_I2C_INTR_MSK_M_RESTART_DET_MSB 12
2781 /* The width in bits of the ALT_I2C_INTR_MSK_M_RESTART_DET register field. */
2782 #define ALT_I2C_INTR_MSK_M_RESTART_DET_WIDTH 1
2783 /* The mask used to set the ALT_I2C_INTR_MSK_M_RESTART_DET register field value. */
2784 #define ALT_I2C_INTR_MSK_M_RESTART_DET_SET_MSK 0x00001000
2785 /* The mask used to clear the ALT_I2C_INTR_MSK_M_RESTART_DET register field value. */
2786 #define ALT_I2C_INTR_MSK_M_RESTART_DET_CLR_MSK 0xffffefff
2787 /* The reset value of the ALT_I2C_INTR_MSK_M_RESTART_DET register field. */
2788 #define ALT_I2C_INTR_MSK_M_RESTART_DET_RESET 0x0
2789 /* Extracts the ALT_I2C_INTR_MSK_M_RESTART_DET field value from a register. */
2790 #define ALT_I2C_INTR_MSK_M_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
2791 /* Produces a ALT_I2C_INTR_MSK_M_RESTART_DET register field value suitable for setting the register. */
2792 #define ALT_I2C_INTR_MSK_M_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
2793 
2794 /*
2795  * Field : m_master_on_hold
2796  *
2797  * This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register.
2798  *
2799  * Reset value: 0x0
2800  *
2801  * Field Access Macros:
2802  *
2803  */
2804 /* The Least Significant Bit (LSB) position of the ALT_I2C_INTR_MSK_M_MST_ON_HOLD register field. */
2805 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_LSB 13
2806 /* The Most Significant Bit (MSB) position of the ALT_I2C_INTR_MSK_M_MST_ON_HOLD register field. */
2807 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_MSB 13
2808 /* The width in bits of the ALT_I2C_INTR_MSK_M_MST_ON_HOLD register field. */
2809 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_WIDTH 1
2810 /* The mask used to set the ALT_I2C_INTR_MSK_M_MST_ON_HOLD register field value. */
2811 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_SET_MSK 0x00002000
2812 /* The mask used to clear the ALT_I2C_INTR_MSK_M_MST_ON_HOLD register field value. */
2813 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_CLR_MSK 0xffffdfff
2814 /* The reset value of the ALT_I2C_INTR_MSK_M_MST_ON_HOLD register field. */
2815 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_RESET 0x0
2816 /* Extracts the ALT_I2C_INTR_MSK_M_MST_ON_HOLD field value from a register. */
2817 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
2818 /* Produces a ALT_I2C_INTR_MSK_M_MST_ON_HOLD register field value suitable for setting the register. */
2819 #define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
2820 
2821 #ifndef __ASSEMBLY__
2822 /*
2823  * WARNING: The C register and register group struct declarations are provided for
2824  * convenience and illustrative purposes. They should, however, be used with
2825  * caution as the C language standard provides no guarantees about the alignment or
2826  * atomicity of device memory accesses. The recommended practice for writing
2827  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2828  * alt_write_word() functions.
2829  *
2830  * The struct declaration for register ALT_I2C_INTR_MSK.
2831  */
2832 struct ALT_I2C_INTR_MSK_s
2833 {
2834  uint32_t m_rx_under : 1; /* ALT_I2C_INTR_MSK_M_RX_UNDER */
2835  uint32_t m_rx_over : 1; /* ALT_I2C_INTR_MSK_M_RX_OVER */
2836  uint32_t m_rx_full : 1; /* ALT_I2C_INTR_MSK_M_RX_FULL */
2837  uint32_t m_tx_over : 1; /* ALT_I2C_INTR_MSK_M_TX_OVER */
2838  uint32_t m_tx_empty : 1; /* ALT_I2C_INTR_MSK_M_TX_EMPTY */
2839  uint32_t m_rd_req : 1; /* ALT_I2C_INTR_MSK_M_RD_REQ */
2840  uint32_t m_tx_abrt : 1; /* ALT_I2C_INTR_MSK_M_TX_ABRT */
2841  uint32_t m_rx_done : 1; /* ALT_I2C_INTR_MSK_M_RX_DONE */
2842  uint32_t m_activity : 1; /* ALT_I2C_INTR_MSK_M_ACTIVITY */
2843  uint32_t m_stop_det : 1; /* ALT_I2C_INTR_MSK_M_STOP_DET */
2844  uint32_t m_start_det : 1; /* ALT_I2C_INTR_MSK_M_START_DET */
2845  uint32_t m_gen_call : 1; /* ALT_I2C_INTR_MSK_M_GEN_CALL */
2846  uint32_t m_restart_det : 1; /* ALT_I2C_INTR_MSK_M_RESTART_DET */
2847  uint32_t m_master_on_hold : 1; /* ALT_I2C_INTR_MSK_M_MST_ON_HOLD */
2848  uint32_t : 18; /* *UNDEFINED* */
2849 };
2850 
2851 /* The typedef declaration for register ALT_I2C_INTR_MSK. */
2852 typedef volatile struct ALT_I2C_INTR_MSK_s ALT_I2C_INTR_MSK_t;
2853 #endif /* __ASSEMBLY__ */
2854 
2855 /* The reset value of the ALT_I2C_INTR_MSK register. */
2856 #define ALT_I2C_INTR_MSK_RESET 0x000008ff
2857 /* The byte offset of the ALT_I2C_INTR_MSK register from the beginning of the component. */
2858 #define ALT_I2C_INTR_MSK_OFST 0x30
2859 /* The address of the ALT_I2C_INTR_MSK register. */
2860 #define ALT_I2C_INTR_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_MSK_OFST))
2861 
2862 /*
2863  * Register : ic_raw_intr_stat
2864  *
2865  * Name: I2C Raw Interrupt Status Register
2866  *
2867  * Size: 14 bits
2868  *
2869  * Address Offset: 0x34
2870  *
2871  * Read/Write Access: Read
2872  *
2873  * Unlike the IC_INTR_STAT register, these bits are not masked so they
2874  *
2875  * always show the true status of the DW_apb_i2c.
2876  *
2877  * Register Layout
2878  *
2879  * Bits | Access | Reset | Description
2880  * :--------|:-------|:------|:----------------------------------
2881  * [0] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_RX_UNDER
2882  * [1] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_RX_OVER
2883  * [2] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_RX_FULL
2884  * [3] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_TX_OVER
2885  * [4] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_TX_EMPTY
2886  * [5] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_RD_REQ
2887  * [6] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_TX_ABRT
2888  * [7] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_RX_DONE
2889  * [8] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_ACTIVITY
2890  * [9] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_STOP_DET
2891  * [10] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_START_DET
2892  * [11] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_GEN_CALL
2893  * [12] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_RESTART_DET
2894  * [13] | R | 0x0 | ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD
2895  * [31:14] | ??? | 0x0 | *UNDEFINED*
2896  *
2897  */
2898 /*
2899  * Field : rx_under
2900  *
2901  * Set if the processor attempts to read the receive buffer when it is empty by
2902  *
2903  * reading from the IC_DATA_CMD register. If the module is disabled
2904  *
2905  * (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state
2906  *
2907  * machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
2908  *
2909  * Reset value: 0x0
2910  *
2911  * Field Access Macros:
2912  *
2913  */
2914 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */
2915 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_LSB 0
2916 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */
2917 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_MSB 0
2918 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */
2919 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_WIDTH 1
2920 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */
2921 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001
2922 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value. */
2923 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe
2924 /* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_UNDER register field. */
2925 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_RESET 0x0
2926 /* Extracts the ALT_I2C_RAW_INTR_STAT_RX_UNDER field value from a register. */
2927 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2928 /* Produces a ALT_I2C_RAW_INTR_STAT_RX_UNDER register field value suitable for setting the register. */
2929 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2930 
2931 /*
2932  * Field : rx_over
2933  *
2934  * Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and
2935  *
2936  * an additional byte is received from an external I2C device. The DW_apb_i2c
2937  *
2938  * acknowledges this, but any data bytes received after the FIFO is full are lost.
2939  * If
2940  *
2941  * the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the
2942  *
2943  * master or slave state machines go into idle, and when ic_en goes to 0, this
2944  *
2945  * interrupt is cleared.
2946  *
2947  * NOTE: If the parameter IC_RX_FULL_HLD_BUS_EN=1, then the RX_OVER interrupt is
2948  *
2949  * never set to 1, because the criteria to set this interrupt are never met.
2950  *
2951  * Reset value: 0x0
2952  *
2953  * Field Access Macros:
2954  *
2955  */
2956 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */
2957 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_LSB 1
2958 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */
2959 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_MSB 1
2960 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */
2961 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_WIDTH 1
2962 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */
2963 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002
2964 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_OVER register field value. */
2965 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd
2966 /* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_OVER register field. */
2967 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_RESET 0x0
2968 /* Extracts the ALT_I2C_RAW_INTR_STAT_RX_OVER field value from a register. */
2969 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
2970 /* Produces a ALT_I2C_RAW_INTR_STAT_RX_OVER register field value suitable for setting the register. */
2971 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
2972 
2973 /*
2974  * Field : rx_full
2975  *
2976  * Set when the receive buffer reaches or goes above the RX_TL threshold in the
2977  *
2978  * IC_RX_TL register. It is automatically cleared by hardware when buffer level
2979  *
2980  * goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the
2981  *
2982  * RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this
2983  *
2984  * bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of
2985  *
2986  * the activity that continues.
2987  *
2988  * Reset value: 0x0
2989  *
2990  * Field Access Macros:
2991  *
2992  */
2993 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */
2994 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_LSB 2
2995 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */
2996 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_MSB 2
2997 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */
2998 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_WIDTH 1
2999 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */
3000 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004
3001 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_FULL register field value. */
3002 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb
3003 /* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_FULL register field. */
3004 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_RESET 0x0
3005 /* Extracts the ALT_I2C_RAW_INTR_STAT_RX_FULL field value from a register. */
3006 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
3007 /* Produces a ALT_I2C_RAW_INTR_STAT_RX_FULL register field value suitable for setting the register. */
3008 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
3009 
3010 /*
3011  * Field : tx_over
3012  *
3013  * Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH
3014  *
3015  * and the processor attempts to issue another I2C command by writing to the
3016  *
3017  * IC_DATA_CMD register. When the module is disabled, this bit keeps its level
3018  *
3019  * until the master or slave state machines go into idle, and when ic_en goes to 0,
3020  *
3021  * this interrupt is cleared.
3022  *
3023  * Reset value: 0x0
3024  *
3025  * Field Access Macros:
3026  *
3027  */
3028 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */
3029 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_LSB 3
3030 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */
3031 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_MSB 3
3032 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */
3033 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_WIDTH 1
3034 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */
3035 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008
3036 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_OVER register field value. */
3037 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7
3038 /* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_OVER register field. */
3039 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_RESET 0x0
3040 /* Extracts the ALT_I2C_RAW_INTR_STAT_TX_OVER field value from a register. */
3041 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
3042 /* Produces a ALT_I2C_RAW_INTR_STAT_TX_OVER register field value suitable for setting the register. */
3043 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
3044 
3045 /*
3046  * Field : tx_empty
3047  *
3048  * The behavior of the TX_EMPTY interrupt status
3049  *
3050  * differs based on the TX_EMPTY_CTRL selection in the IC_CON register.
3051  *
3052  * When TX_EMPTY_CTRL = 0:
3053  *
3054  * This bit is set to 1 when the transmit buffer is at or below the threshold value
3055  * set in the IC_TX_TL register.
3056  *
3057  * When TX_EMPTY_CTRL = 1:
3058  *
3059  * This bit is set to 1 when the transmit buffer is at or below the threshold
3060  * value.
3061  *
3062  * set in the IC_TX_TL register and the transmission of the address/data from
3063  *
3064  * the internal shift register for the most recently popped command is completed.
3065  *
3066  * It is automatically cleared by hardware when the buffer level goes above the
3067  *
3068  * threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in
3069  *
3070  * reset. There the TX FIFO looks like it has no data within it, so this bit is set
3071  * to 1,
3072  *
3073  * provided there is activity in the master or slave state machines. When there is
3074  * no
3075  *
3076  * longer any activity, then with ic_en=0, this bit is set to 0.
3077  *
3078  * Reset value: 0x0.
3079  *
3080  * Field Access Macros:
3081  *
3082  */
3083 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */
3084 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_LSB 4
3085 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */
3086 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_MSB 4
3087 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */
3088 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
3089 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */
3090 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010
3091 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value. */
3092 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef
3093 /* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field. */
3094 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_RESET 0x0
3095 /* Extracts the ALT_I2C_RAW_INTR_STAT_TX_EMPTY field value from a register. */
3096 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
3097 /* Produces a ALT_I2C_RAW_INTR_STAT_TX_EMPTY register field value suitable for setting the register. */
3098 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
3099 
3100 /*
3101  * Field : rd_req
3102  *
3103  * This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C
3104  *
3105  * master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds
3106  *
3107  * the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which
3108  * means
3109  *
3110  * that the slave has been addressed by a remote master that is asking for data to
3111  *
3112  * be transferred. The processor must respond to this interrupt and then write the
3113  *
3114  * requested data to the IC_DATA_CMD register. This bit is set to 0 just after the
3115  *
3116  * processor reads the IC_CLR_RD_REQ register.
3117  *
3118  * Reset value: 0x0
3119  *
3120  * Field Access Macros:
3121  *
3122  */
3123 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */
3124 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_LSB 5
3125 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */
3126 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_MSB 5
3127 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */
3128 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_WIDTH 1
3129 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */
3130 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020
3131 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RD_REQ register field value. */
3132 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf
3133 /* The reset value of the ALT_I2C_RAW_INTR_STAT_RD_REQ register field. */
3134 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_RESET 0x0
3135 /* Extracts the ALT_I2C_RAW_INTR_STAT_RD_REQ field value from a register. */
3136 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
3137 /* Produces a ALT_I2C_RAW_INTR_STAT_RD_REQ register field value suitable for setting the register. */
3138 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
3139 
3140 /*
3141  * Field : tx_abrt
3142  *
3143  * This bit indicates if DW_apb_i2c, as an I2C transmitter,
3144  *
3145  * is unable to complete the intended actions on the
3146  *
3147  * contents of the transmit FIFO. This situation can
3148  *
3149  * occur both as an I2C master or an I2C slave, and is
3150  *
3151  * referred to as a 'transmit abort'.
3152  *
3153  * When this bit is set to 1, the IC_TX_ABRT_SOURCE register
3154  *
3155  * indicates the reason why the transmit abort takes places.
3156  *
3157  * NOTE: The DW_apb_i2c flushes/resets/empties the TX FIFO whenever this
3158  *
3159  * bit is set. The TX FIFO remains in this flushed state until the register
3160  *
3161  * IC_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then
3162  *
3163  * ready to accept more data bytes from the APB interface.
3164  *
3165  * Reset value: 0x0
3166  *
3167  * Field Access Macros:
3168  *
3169  */
3170 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */
3171 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_LSB 6
3172 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */
3173 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_MSB 6
3174 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */
3175 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_WIDTH 1
3176 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */
3177 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040
3178 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value. */
3179 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf
3180 /* The reset value of the ALT_I2C_RAW_INTR_STAT_TX_ABRT register field. */
3181 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_RESET 0x0
3182 /* Extracts the ALT_I2C_RAW_INTR_STAT_TX_ABRT field value from a register. */
3183 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
3184 /* Produces a ALT_I2C_RAW_INTR_STAT_TX_ABRT register field value suitable for setting the register. */
3185 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
3186 
3187 /*
3188  * Field : rx_done
3189  *
3190  * When the DW_apb_i2c is acting as a slave-transmitter,
3191  *
3192  * this bit is set to 1 if the master does not acknowledge
3193  *
3194  * a transmitted byte. This occurs on the last byte of
3195  *
3196  * the transmission, indicating that the transmission is done.
3197  *
3198  * Reset value: 0x0
3199  *
3200  * Field Access Macros:
3201  *
3202  */
3203 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */
3204 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_LSB 7
3205 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */
3206 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_MSB 7
3207 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */
3208 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_WIDTH 1
3209 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */
3210 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080
3211 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RX_DONE register field value. */
3212 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f
3213 /* The reset value of the ALT_I2C_RAW_INTR_STAT_RX_DONE register field. */
3214 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_RESET 0x0
3215 /* Extracts the ALT_I2C_RAW_INTR_STAT_RX_DONE field value from a register. */
3216 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
3217 /* Produces a ALT_I2C_RAW_INTR_STAT_RX_DONE register field value suitable for setting the register. */
3218 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
3219 
3220 /*
3221  * Field : activity
3222  *
3223  * This bit captures DW_apb_i2c activity and stays set until it is cleared. There
3224  *
3225  * are four ways to clear it:
3226  *
3227  * * Disabling the DW_apb_i2c
3228  *
3229  * * Reading the IC_CLR_ACTIVITY register
3230  *
3231  * * Reading the IC_CLR_INTR register
3232  *
3233  * * System reset
3234  *
3235  * Once this bit is set, it stays set unless one of the four methods is used to
3236  * clear it.
3237  *
3238  * Even if the DW_apb_i2c module is idle, this bit remains set until cleared,
3239  *
3240  * indicating that there was activity on the bus.
3241  *
3242  * Reset value: 0x0
3243  *
3244  * Field Access Macros:
3245  *
3246  */
3247 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */
3248 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_LSB 8
3249 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */
3250 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_MSB 8
3251 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */
3252 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_WIDTH 1
3253 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */
3254 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET_MSK 0x00000100
3255 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value. */
3256 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_CLR_MSK 0xfffffeff
3257 /* The reset value of the ALT_I2C_RAW_INTR_STAT_ACTIVITY register field. */
3258 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_RESET 0x0
3259 /* Extracts the ALT_I2C_RAW_INTR_STAT_ACTIVITY field value from a register. */
3260 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
3261 /* Produces a ALT_I2C_RAW_INTR_STAT_ACTIVITY register field value suitable for setting the register. */
3262 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
3263 
3264 /*
3265  * Field : stop_det
3266  *
3267  * The behavior of the STOP_DET interrupt status
3268  *
3269  * differs based on the STOP_DET_IFADDRESSED selection in the IC_CON register
3270  *
3271  * When STOP_DET_IFADDRESSED =0
3272  *
3273  * Indicates whether a STOP condition has occurred on the I2C interface regardless
3274  *
3275  * of whether DW_apb_i2c is operating in slave or master mode. In slave mode,
3276  *
3277  * a STOP_DET interrupt is generated irrespective of whether the
3278  *
3279  * slave is addressed or not.
3280  *
3281  * When STOP_DET_IFADDRESSED = 1
3282  *
3283  * In Master Mode (MASTER_MODE = 1), indicates a STOP condition has occured on the
3284  * I2C interface.
3285  *
3286  * In Slave Mode (MASTER_MODE = 0), a STOP_DET interrupt is generated only if the
3287  * slave is addressed.
3288  *
3289  * NOTE: During a general call address, this slave does not issue a STOP_DET
3290  *
3291  * interrupt if STOP_DET_IFADDRESSED=1, even if the slave responds to the
3292  *
3293  * general call address by generating ACK. The STOP_DET interrupt is generated
3294  *
3295  * only when the transmitted address matches the slave address (SAR).
3296  *
3297  * Reset value: 0x0.
3298  *
3299  * Field Access Macros:
3300  *
3301  */
3302 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */
3303 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_LSB 9
3304 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */
3305 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_MSB 9
3306 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */
3307 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_WIDTH 1
3308 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */
3309 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200
3310 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_STOP_DET register field value. */
3311 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff
3312 /* The reset value of the ALT_I2C_RAW_INTR_STAT_STOP_DET register field. */
3313 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_RESET 0x0
3314 /* Extracts the ALT_I2C_RAW_INTR_STAT_STOP_DET field value from a register. */
3315 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
3316 /* Produces a ALT_I2C_RAW_INTR_STAT_STOP_DET register field value suitable for setting the register. */
3317 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
3318 
3319 /*
3320  * Field : start_det
3321  *
3322  * Indicates whether a START or RESTART condition has occurred on the I2C
3323  *
3324  * interface regardless of whether DW_apb_i2c is operating in slave or master
3325  *
3326  * mode.
3327  *
3328  * Reset value: 0x0
3329  *
3330  * Field Access Macros:
3331  *
3332  */
3333 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */
3334 #define ALT_I2C_RAW_INTR_STAT_START_DET_LSB 10
3335 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */
3336 #define ALT_I2C_RAW_INTR_STAT_START_DET_MSB 10
3337 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */
3338 #define ALT_I2C_RAW_INTR_STAT_START_DET_WIDTH 1
3339 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */
3340 #define ALT_I2C_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400
3341 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_START_DET register field value. */
3342 #define ALT_I2C_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff
3343 /* The reset value of the ALT_I2C_RAW_INTR_STAT_START_DET register field. */
3344 #define ALT_I2C_RAW_INTR_STAT_START_DET_RESET 0x0
3345 /* Extracts the ALT_I2C_RAW_INTR_STAT_START_DET field value from a register. */
3346 #define ALT_I2C_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10)
3347 /* Produces a ALT_I2C_RAW_INTR_STAT_START_DET register field value suitable for setting the register. */
3348 #define ALT_I2C_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400)
3349 
3350 /*
3351  * Field : gen_call
3352  *
3353  * Set only when a General Call address is received and it is acknowledged. It
3354  *
3355  * stays set until it is cleared either by disabling DW_apb_i2c or when the CPU
3356  *
3357  * reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the
3358  *
3359  * received data in the Rx buffer.
3360  *
3361  * Reset value: 0x0
3362  *
3363  * Field Access Macros:
3364  *
3365  */
3366 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */
3367 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_LSB 11
3368 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */
3369 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_MSB 11
3370 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */
3371 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_WIDTH 1
3372 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */
3373 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800
3374 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value. */
3375 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff
3376 /* The reset value of the ALT_I2C_RAW_INTR_STAT_GEN_CALL register field. */
3377 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_RESET 0x0
3378 /* Extracts the ALT_I2C_RAW_INTR_STAT_GEN_CALL field value from a register. */
3379 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
3380 /* Produces a ALT_I2C_RAW_INTR_STAT_GEN_CALL register field value suitable for setting the register. */
3381 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
3382 
3383 /*
3384  * Field : restart_det
3385  *
3386  * Indicates whether a RESTART condition has occurred on the I2C interface
3387  *
3388  * when DW_apb_i2c is operating in Slave mode and the slave is being addressed.
3389  * Enabled only when IC_SLV_RESTART_DET_EN=1.
3390  *
3391  * (Note:Following are exceptions where the Restart interrupt will not get
3392  * generated.
3393  *
3394  * In the case of High speed Mode or Startbyte transfer, where the Restart comes
3395  * before the Address field as per the
3396  *
3397  * I2C protocol defined format, the Slave is still not in the addressed mode and
3398  * hence will not generate the RESTART_DET interrupt.)
3399  *
3400  * Reset value: 0x0
3401  *
3402  * Field Access Macros:
3403  *
3404  */
3405 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_RESTART_DET register field. */
3406 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_LSB 12
3407 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_RESTART_DET register field. */
3408 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_MSB 12
3409 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_RESTART_DET register field. */
3410 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_WIDTH 1
3411 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_RESTART_DET register field value. */
3412 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_SET_MSK 0x00001000
3413 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_RESTART_DET register field value. */
3414 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_CLR_MSK 0xffffefff
3415 /* The reset value of the ALT_I2C_RAW_INTR_STAT_RESTART_DET register field. */
3416 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_RESET 0x0
3417 /* Extracts the ALT_I2C_RAW_INTR_STAT_RESTART_DET field value from a register. */
3418 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
3419 /* Produces a ALT_I2C_RAW_INTR_STAT_RESTART_DET register field value suitable for setting the register. */
3420 #define ALT_I2C_RAW_INTR_STAT_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
3421 
3422 /*
3423  * Field : master_on_hold
3424  *
3425  * Indicates whether master is holding the bus and TX FIFO is empty.
3426  *
3427  * Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1.
3428  *
3429  * Reset value: 0x0
3430  *
3431  * Field Access Macros:
3432  *
3433  */
3434 /* The Least Significant Bit (LSB) position of the ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD register field. */
3435 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_LSB 13
3436 /* The Most Significant Bit (MSB) position of the ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD register field. */
3437 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_MSB 13
3438 /* The width in bits of the ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD register field. */
3439 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_WIDTH 1
3440 /* The mask used to set the ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD register field value. */
3441 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_SET_MSK 0x00002000
3442 /* The mask used to clear the ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD register field value. */
3443 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_CLR_MSK 0xffffdfff
3444 /* The reset value of the ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD register field. */
3445 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_RESET 0x0
3446 /* Extracts the ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD field value from a register. */
3447 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
3448 /* Produces a ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD register field value suitable for setting the register. */
3449 #define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
3450 
3451 #ifndef __ASSEMBLY__
3452 /*
3453  * WARNING: The C register and register group struct declarations are provided for
3454  * convenience and illustrative purposes. They should, however, be used with
3455  * caution as the C language standard provides no guarantees about the alignment or
3456  * atomicity of device memory accesses. The recommended practice for writing
3457  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3458  * alt_write_word() functions.
3459  *
3460  * The struct declaration for register ALT_I2C_RAW_INTR_STAT.
3461  */
3462 struct ALT_I2C_RAW_INTR_STAT_s
3463 {
3464  const uint32_t rx_under : 1; /* ALT_I2C_RAW_INTR_STAT_RX_UNDER */
3465  const uint32_t rx_over : 1; /* ALT_I2C_RAW_INTR_STAT_RX_OVER */
3466  const uint32_t rx_full : 1; /* ALT_I2C_RAW_INTR_STAT_RX_FULL */
3467  const uint32_t tx_over : 1; /* ALT_I2C_RAW_INTR_STAT_TX_OVER */
3468  const uint32_t tx_empty : 1; /* ALT_I2C_RAW_INTR_STAT_TX_EMPTY */
3469  const uint32_t rd_req : 1; /* ALT_I2C_RAW_INTR_STAT_RD_REQ */
3470  const uint32_t tx_abrt : 1; /* ALT_I2C_RAW_INTR_STAT_TX_ABRT */
3471  const uint32_t rx_done : 1; /* ALT_I2C_RAW_INTR_STAT_RX_DONE */
3472  const uint32_t activity : 1; /* ALT_I2C_RAW_INTR_STAT_ACTIVITY */
3473  const uint32_t stop_det : 1; /* ALT_I2C_RAW_INTR_STAT_STOP_DET */
3474  const uint32_t start_det : 1; /* ALT_I2C_RAW_INTR_STAT_START_DET */
3475  const uint32_t gen_call : 1; /* ALT_I2C_RAW_INTR_STAT_GEN_CALL */
3476  const uint32_t restart_det : 1; /* ALT_I2C_RAW_INTR_STAT_RESTART_DET */
3477  const uint32_t master_on_hold : 1; /* ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD */
3478  uint32_t : 18; /* *UNDEFINED* */
3479 };
3480 
3481 /* The typedef declaration for register ALT_I2C_RAW_INTR_STAT. */
3482 typedef volatile struct ALT_I2C_RAW_INTR_STAT_s ALT_I2C_RAW_INTR_STAT_t;
3483 #endif /* __ASSEMBLY__ */
3484 
3485 /* The reset value of the ALT_I2C_RAW_INTR_STAT register. */
3486 #define ALT_I2C_RAW_INTR_STAT_RESET 0x00000000
3487 /* The byte offset of the ALT_I2C_RAW_INTR_STAT register from the beginning of the component. */
3488 #define ALT_I2C_RAW_INTR_STAT_OFST 0x34
3489 /* The address of the ALT_I2C_RAW_INTR_STAT register. */
3490 #define ALT_I2C_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RAW_INTR_STAT_OFST))
3491 
3492 /*
3493  * Register : ic_rx_tl
3494  *
3495  * Name: I2C Receive FIFO Threshold Register
3496  *
3497  * Size: 8bits
3498  *
3499  * Address Offset: 0x38
3500  *
3501  * Read/Write Access: Read/Write
3502  *
3503  * Register Layout
3504  *
3505  * Bits | Access | Reset | Description
3506  * :-------|:-------|:------|:--------------------
3507  * [7:0] | RW | 0x0 | ALT_I2C_RX_TL_RX_TL
3508  * [31:8] | ??? | 0x0 | *UNDEFINED*
3509  *
3510  */
3511 /*
3512  * Field : rx_tl
3513  *
3514  * Receive FIFO Threshold Level
3515  *
3516  * Controls the level of entries (or above) that triggers
3517  *
3518  * the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register).
3519  *
3520  * The valid range is 0-255, with the additional restriction that
3521  *
3522  * hardware does not allow this value to be set to a value larger
3523  *
3524  * than the depth of the buffer. If an attempt is made to do that,
3525  *
3526  * the actual value set will be the maximum depth of the buffer.
3527  *
3528  * A value of 0 sets the threshold for 1 entry, and a value of 255
3529  *
3530  * sets the threshold for 256 entries.
3531  *
3532  * Reset value: IC_RX_TL configuration parameter
3533  *
3534  * Field Access Macros:
3535  *
3536  */
3537 /* The Least Significant Bit (LSB) position of the ALT_I2C_RX_TL_RX_TL register field. */
3538 #define ALT_I2C_RX_TL_RX_TL_LSB 0
3539 /* The Most Significant Bit (MSB) position of the ALT_I2C_RX_TL_RX_TL register field. */
3540 #define ALT_I2C_RX_TL_RX_TL_MSB 7
3541 /* The width in bits of the ALT_I2C_RX_TL_RX_TL register field. */
3542 #define ALT_I2C_RX_TL_RX_TL_WIDTH 8
3543 /* The mask used to set the ALT_I2C_RX_TL_RX_TL register field value. */
3544 #define ALT_I2C_RX_TL_RX_TL_SET_MSK 0x000000ff
3545 /* The mask used to clear the ALT_I2C_RX_TL_RX_TL register field value. */
3546 #define ALT_I2C_RX_TL_RX_TL_CLR_MSK 0xffffff00
3547 /* The reset value of the ALT_I2C_RX_TL_RX_TL register field. */
3548 #define ALT_I2C_RX_TL_RX_TL_RESET 0x0
3549 /* Extracts the ALT_I2C_RX_TL_RX_TL field value from a register. */
3550 #define ALT_I2C_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0)
3551 /* Produces a ALT_I2C_RX_TL_RX_TL register field value suitable for setting the register. */
3552 #define ALT_I2C_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff)
3553 
3554 #ifndef __ASSEMBLY__
3555 /*
3556  * WARNING: The C register and register group struct declarations are provided for
3557  * convenience and illustrative purposes. They should, however, be used with
3558  * caution as the C language standard provides no guarantees about the alignment or
3559  * atomicity of device memory accesses. The recommended practice for writing
3560  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3561  * alt_write_word() functions.
3562  *
3563  * The struct declaration for register ALT_I2C_RX_TL.
3564  */
3565 struct ALT_I2C_RX_TL_s
3566 {
3567  uint32_t rx_tl : 8; /* ALT_I2C_RX_TL_RX_TL */
3568  uint32_t : 24; /* *UNDEFINED* */
3569 };
3570 
3571 /* The typedef declaration for register ALT_I2C_RX_TL. */
3572 typedef volatile struct ALT_I2C_RX_TL_s ALT_I2C_RX_TL_t;
3573 #endif /* __ASSEMBLY__ */
3574 
3575 /* The reset value of the ALT_I2C_RX_TL register. */
3576 #define ALT_I2C_RX_TL_RESET 0x00000000
3577 /* The byte offset of the ALT_I2C_RX_TL register from the beginning of the component. */
3578 #define ALT_I2C_RX_TL_OFST 0x38
3579 /* The address of the ALT_I2C_RX_TL register. */
3580 #define ALT_I2C_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RX_TL_OFST))
3581 
3582 /*
3583  * Register : ic_tx_tl
3584  *
3585  * Name: I2C Transmit FIFO Threshold Register
3586  *
3587  * Size: 8 bits
3588  *
3589  * Address Offset: 0x3c
3590  *
3591  * Read/Write Access: Read/Write
3592  *
3593  * Register Layout
3594  *
3595  * Bits | Access | Reset | Description
3596  * :-------|:-------|:------|:--------------------
3597  * [7:0] | RW | 0x0 | ALT_I2C_TX_TL_TX_TL
3598  * [31:8] | ??? | 0x0 | *UNDEFINED*
3599  *
3600  */
3601 /*
3602  * Field : tx_tl
3603  *
3604  * Transmit FIFO Threshold Level
3605  *
3606  * Controls the level of entries (or below) that trigger
3607  *
3608  * the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register).
3609  *
3610  * The valid range is 0-255, with the additional restriction that
3611  *
3612  * it may not be set to value larger than the depth of the buffer.
3613  *
3614  * If an attempt is made to do that, the actual value set will be
3615  *
3616  * the maximum depth of the buffer.
3617  *
3618  * A value of 0 sets the threshold for 0 entries, and a value of 255
3619  *
3620  * sets the threshold for 255 entries.
3621  *
3622  * Reset value: IC_TX_TL configuration parameter
3623  *
3624  * Field Access Macros:
3625  *
3626  */
3627 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_TL_TX_TL register field. */
3628 #define ALT_I2C_TX_TL_TX_TL_LSB 0
3629 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_TL_TX_TL register field. */
3630 #define ALT_I2C_TX_TL_TX_TL_MSB 7
3631 /* The width in bits of the ALT_I2C_TX_TL_TX_TL register field. */
3632 #define ALT_I2C_TX_TL_TX_TL_WIDTH 8
3633 /* The mask used to set the ALT_I2C_TX_TL_TX_TL register field value. */
3634 #define ALT_I2C_TX_TL_TX_TL_SET_MSK 0x000000ff
3635 /* The mask used to clear the ALT_I2C_TX_TL_TX_TL register field value. */
3636 #define ALT_I2C_TX_TL_TX_TL_CLR_MSK 0xffffff00
3637 /* The reset value of the ALT_I2C_TX_TL_TX_TL register field. */
3638 #define ALT_I2C_TX_TL_TX_TL_RESET 0x0
3639 /* Extracts the ALT_I2C_TX_TL_TX_TL field value from a register. */
3640 #define ALT_I2C_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0)
3641 /* Produces a ALT_I2C_TX_TL_TX_TL register field value suitable for setting the register. */
3642 #define ALT_I2C_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff)
3643 
3644 #ifndef __ASSEMBLY__
3645 /*
3646  * WARNING: The C register and register group struct declarations are provided for
3647  * convenience and illustrative purposes. They should, however, be used with
3648  * caution as the C language standard provides no guarantees about the alignment or
3649  * atomicity of device memory accesses. The recommended practice for writing
3650  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3651  * alt_write_word() functions.
3652  *
3653  * The struct declaration for register ALT_I2C_TX_TL.
3654  */
3655 struct ALT_I2C_TX_TL_s
3656 {
3657  uint32_t tx_tl : 8; /* ALT_I2C_TX_TL_TX_TL */
3658  uint32_t : 24; /* *UNDEFINED* */
3659 };
3660 
3661 /* The typedef declaration for register ALT_I2C_TX_TL. */
3662 typedef volatile struct ALT_I2C_TX_TL_s ALT_I2C_TX_TL_t;
3663 #endif /* __ASSEMBLY__ */
3664 
3665 /* The reset value of the ALT_I2C_TX_TL register. */
3666 #define ALT_I2C_TX_TL_RESET 0x00000000
3667 /* The byte offset of the ALT_I2C_TX_TL register from the beginning of the component. */
3668 #define ALT_I2C_TX_TL_OFST 0x3c
3669 /* The address of the ALT_I2C_TX_TL register. */
3670 #define ALT_I2C_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_TL_OFST))
3671 
3672 /*
3673  * Register : ic_clr_intr
3674  *
3675  * Name: Clear Combined and Individual Interrupt Register
3676  *
3677  * Size: 1 bit
3678  *
3679  * Address Offset: 0x40
3680  *
3681  * Read/Write Access: Read
3682  *
3683  * Register Layout
3684  *
3685  * Bits | Access | Reset | Description
3686  * :-------|:-------|:------|:--------------------------
3687  * [0] | R | 0x0 | ALT_I2C_CLR_INTR_CLR_INTR
3688  * [31:1] | ??? | 0x0 | *UNDEFINED*
3689  *
3690  */
3691 /*
3692  * Field : clr_intr
3693  *
3694  * Read this register to clear the combined interrupt,
3695  *
3696  * all individual interrupts, and the IC_TX_ABRT_SOURCE register.
3697  *
3698  * This bit does not clear hardware clearable interrupts but software
3699  *
3700  * clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register
3701  *
3702  * for an exception to clearing IC_TX_ABRT_SOURCE.
3703  *
3704  * Reset value: 0x0
3705  *
3706  * Field Access Macros:
3707  *
3708  */
3709 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */
3710 #define ALT_I2C_CLR_INTR_CLR_INTR_LSB 0
3711 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_INTR_CLR_INTR register field. */
3712 #define ALT_I2C_CLR_INTR_CLR_INTR_MSB 0
3713 /* The width in bits of the ALT_I2C_CLR_INTR_CLR_INTR register field. */
3714 #define ALT_I2C_CLR_INTR_CLR_INTR_WIDTH 1
3715 /* The mask used to set the ALT_I2C_CLR_INTR_CLR_INTR register field value. */
3716 #define ALT_I2C_CLR_INTR_CLR_INTR_SET_MSK 0x00000001
3717 /* The mask used to clear the ALT_I2C_CLR_INTR_CLR_INTR register field value. */
3718 #define ALT_I2C_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe
3719 /* The reset value of the ALT_I2C_CLR_INTR_CLR_INTR register field. */
3720 #define ALT_I2C_CLR_INTR_CLR_INTR_RESET 0x0
3721 /* Extracts the ALT_I2C_CLR_INTR_CLR_INTR field value from a register. */
3722 #define ALT_I2C_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0)
3723 /* Produces a ALT_I2C_CLR_INTR_CLR_INTR register field value suitable for setting the register. */
3724 #define ALT_I2C_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001)
3725 
3726 #ifndef __ASSEMBLY__
3727 /*
3728  * WARNING: The C register and register group struct declarations are provided for
3729  * convenience and illustrative purposes. They should, however, be used with
3730  * caution as the C language standard provides no guarantees about the alignment or
3731  * atomicity of device memory accesses. The recommended practice for writing
3732  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3733  * alt_write_word() functions.
3734  *
3735  * The struct declaration for register ALT_I2C_CLR_INTR.
3736  */
3737 struct ALT_I2C_CLR_INTR_s
3738 {
3739  const uint32_t clr_intr : 1; /* ALT_I2C_CLR_INTR_CLR_INTR */
3740  uint32_t : 31; /* *UNDEFINED* */
3741 };
3742 
3743 /* The typedef declaration for register ALT_I2C_CLR_INTR. */
3744 typedef volatile struct ALT_I2C_CLR_INTR_s ALT_I2C_CLR_INTR_t;
3745 #endif /* __ASSEMBLY__ */
3746 
3747 /* The reset value of the ALT_I2C_CLR_INTR register. */
3748 #define ALT_I2C_CLR_INTR_RESET 0x00000000
3749 /* The byte offset of the ALT_I2C_CLR_INTR register from the beginning of the component. */
3750 #define ALT_I2C_CLR_INTR_OFST 0x40
3751 /* The address of the ALT_I2C_CLR_INTR register. */
3752 #define ALT_I2C_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_INTR_OFST))
3753 
3754 /*
3755  * Register : ic_clr_rx_under
3756  *
3757  * Name: Clear RX_UNDER Interrupt Register
3758  *
3759  * Size: 1 bit
3760  *
3761  * Address Offset: 0x44
3762  *
3763  * Read/Write Access: Read
3764  *
3765  * Register Layout
3766  *
3767  * Bits | Access | Reset | Description
3768  * :-------|:-------|:------|:----------------------------------
3769  * [0] | R | 0x0 | ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER
3770  * [31:1] | ??? | 0x0 | *UNDEFINED*
3771  *
3772  */
3773 /*
3774  * Field : clr_rx_under
3775  *
3776  * Read this register to clear the RX_UNDER
3777  *
3778  * interrupt (bit 0) of the IC_RAW_INTR_STAT register.
3779  *
3780  * Reset value: 0x0
3781  *
3782  * Field Access Macros:
3783  *
3784  */
3785 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */
3786 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0
3787 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */
3788 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0
3789 /* The width in bits of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */
3790 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1
3791 /* The mask used to set the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */
3792 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001
3793 /* The mask used to clear the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value. */
3794 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe
3795 /* The reset value of the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field. */
3796 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0
3797 /* Extracts the ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER field value from a register. */
3798 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
3799 /* Produces a ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER register field value suitable for setting the register. */
3800 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
3801 
3802 #ifndef __ASSEMBLY__
3803 /*
3804  * WARNING: The C register and register group struct declarations are provided for
3805  * convenience and illustrative purposes. They should, however, be used with
3806  * caution as the C language standard provides no guarantees about the alignment or
3807  * atomicity of device memory accesses. The recommended practice for writing
3808  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3809  * alt_write_word() functions.
3810  *
3811  * The struct declaration for register ALT_I2C_CLR_RX_UNDER.
3812  */
3813 struct ALT_I2C_CLR_RX_UNDER_s
3814 {
3815  const uint32_t clr_rx_under : 1; /* ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER */
3816  uint32_t : 31; /* *UNDEFINED* */
3817 };
3818 
3819 /* The typedef declaration for register ALT_I2C_CLR_RX_UNDER. */
3820 typedef volatile struct ALT_I2C_CLR_RX_UNDER_s ALT_I2C_CLR_RX_UNDER_t;
3821 #endif /* __ASSEMBLY__ */
3822 
3823 /* The reset value of the ALT_I2C_CLR_RX_UNDER register. */
3824 #define ALT_I2C_CLR_RX_UNDER_RESET 0x00000000
3825 /* The byte offset of the ALT_I2C_CLR_RX_UNDER register from the beginning of the component. */
3826 #define ALT_I2C_CLR_RX_UNDER_OFST 0x44
3827 /* The address of the ALT_I2C_CLR_RX_UNDER register. */
3828 #define ALT_I2C_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_UNDER_OFST))
3829 
3830 /*
3831  * Register : ic_clr_rx_over
3832  *
3833  * Name: Clear RX_OVER Interrupt Register
3834  *
3835  * Size: 1 bit
3836  *
3837  * Address Offset: 0x48
3838  *
3839  * Read/Write Access: Read
3840  *
3841  * Register Layout
3842  *
3843  * Bits | Access | Reset | Description
3844  * :-------|:-------|:------|:--------------------------------
3845  * [0] | R | 0x0 | ALT_I2C_CLR_RX_OVER_CLR_RX_OVER
3846  * [31:1] | ??? | 0x0 | *UNDEFINED*
3847  *
3848  */
3849 /*
3850  * Field : clr_rx_over
3851  *
3852  * Read this register to clear the RX_OVER
3853  *
3854  * interrupt (bit 1) of the IC_RAW_INTR_STAT register.
3855  *
3856  * Reset value: 0x0
3857  *
3858  * Field Access Macros:
3859  *
3860  */
3861 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */
3862 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_LSB 0
3863 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */
3864 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_MSB 0
3865 /* The width in bits of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */
3866 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1
3867 /* The mask used to set the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */
3868 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001
3869 /* The mask used to clear the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value. */
3870 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe
3871 /* The reset value of the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field. */
3872 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0
3873 /* Extracts the ALT_I2C_CLR_RX_OVER_CLR_RX_OVER field value from a register. */
3874 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0)
3875 /* Produces a ALT_I2C_CLR_RX_OVER_CLR_RX_OVER register field value suitable for setting the register. */
3876 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001)
3877 
3878 #ifndef __ASSEMBLY__
3879 /*
3880  * WARNING: The C register and register group struct declarations are provided for
3881  * convenience and illustrative purposes. They should, however, be used with
3882  * caution as the C language standard provides no guarantees about the alignment or
3883  * atomicity of device memory accesses. The recommended practice for writing
3884  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3885  * alt_write_word() functions.
3886  *
3887  * The struct declaration for register ALT_I2C_CLR_RX_OVER.
3888  */
3889 struct ALT_I2C_CLR_RX_OVER_s
3890 {
3891  const uint32_t clr_rx_over : 1; /* ALT_I2C_CLR_RX_OVER_CLR_RX_OVER */
3892  uint32_t : 31; /* *UNDEFINED* */
3893 };
3894 
3895 /* The typedef declaration for register ALT_I2C_CLR_RX_OVER. */
3896 typedef volatile struct ALT_I2C_CLR_RX_OVER_s ALT_I2C_CLR_RX_OVER_t;
3897 #endif /* __ASSEMBLY__ */
3898 
3899 /* The reset value of the ALT_I2C_CLR_RX_OVER register. */
3900 #define ALT_I2C_CLR_RX_OVER_RESET 0x00000000
3901 /* The byte offset of the ALT_I2C_CLR_RX_OVER register from the beginning of the component. */
3902 #define ALT_I2C_CLR_RX_OVER_OFST 0x48
3903 /* The address of the ALT_I2C_CLR_RX_OVER register. */
3904 #define ALT_I2C_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_OVER_OFST))
3905 
3906 /*
3907  * Register : ic_clr_tx_over
3908  *
3909  * Name: Clear TX_OVER Interrupt Register
3910  *
3911  * Size: 1 bit
3912  *
3913  * Address Offset: 0x4c
3914  *
3915  * Read/Write Access: Read
3916  *
3917  * Register Layout
3918  *
3919  * Bits | Access | Reset | Description
3920  * :-------|:-------|:------|:--------------------------------
3921  * [0] | R | 0x0 | ALT_I2C_CLR_TX_OVER_CLR_TX_OVER
3922  * [31:1] | ??? | 0x0 | *UNDEFINED*
3923  *
3924  */
3925 /*
3926  * Field : clr_tx_over
3927  *
3928  * Read this register to clear the TX_OVER
3929  *
3930  * interrupt (bit 3) of the IC_RAW_INTR_STAT register.
3931  *
3932  * Reset value: 0x0
3933  *
3934  * Field Access Macros:
3935  *
3936  */
3937 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */
3938 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_LSB 0
3939 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */
3940 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_MSB 0
3941 /* The width in bits of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */
3942 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1
3943 /* The mask used to set the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */
3944 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001
3945 /* The mask used to clear the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value. */
3946 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe
3947 /* The reset value of the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field. */
3948 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0
3949 /* Extracts the ALT_I2C_CLR_TX_OVER_CLR_TX_OVER field value from a register. */
3950 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0)
3951 /* Produces a ALT_I2C_CLR_TX_OVER_CLR_TX_OVER register field value suitable for setting the register. */
3952 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001)
3953 
3954 #ifndef __ASSEMBLY__
3955 /*
3956  * WARNING: The C register and register group struct declarations are provided for
3957  * convenience and illustrative purposes. They should, however, be used with
3958  * caution as the C language standard provides no guarantees about the alignment or
3959  * atomicity of device memory accesses. The recommended practice for writing
3960  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3961  * alt_write_word() functions.
3962  *
3963  * The struct declaration for register ALT_I2C_CLR_TX_OVER.
3964  */
3965 struct ALT_I2C_CLR_TX_OVER_s
3966 {
3967  const uint32_t clr_tx_over : 1; /* ALT_I2C_CLR_TX_OVER_CLR_TX_OVER */
3968  uint32_t : 31; /* *UNDEFINED* */
3969 };
3970 
3971 /* The typedef declaration for register ALT_I2C_CLR_TX_OVER. */
3972 typedef volatile struct ALT_I2C_CLR_TX_OVER_s ALT_I2C_CLR_TX_OVER_t;
3973 #endif /* __ASSEMBLY__ */
3974 
3975 /* The reset value of the ALT_I2C_CLR_TX_OVER register. */
3976 #define ALT_I2C_CLR_TX_OVER_RESET 0x00000000
3977 /* The byte offset of the ALT_I2C_CLR_TX_OVER register from the beginning of the component. */
3978 #define ALT_I2C_CLR_TX_OVER_OFST 0x4c
3979 /* The address of the ALT_I2C_CLR_TX_OVER register. */
3980 #define ALT_I2C_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_OVER_OFST))
3981 
3982 /*
3983  * Register : ic_clr_rd_req
3984  *
3985  * Name: Clear RD_REQ Interrupt Register
3986  *
3987  * Size: 1 bit
3988  *
3989  * Address Offset: 0x50
3990  *
3991  * Read/Write Access: Read
3992  *
3993  * Register Layout
3994  *
3995  * Bits | Access | Reset | Description
3996  * :-------|:-------|:------|:------------------------------
3997  * [0] | R | 0x0 | ALT_I2C_CLR_RD_REQ_CLR_RD_REQ
3998  * [31:1] | ??? | 0x0 | *UNDEFINED*
3999  *
4000  */
4001 /*
4002  * Field : clr_rd_req
4003  *
4004  * Read this register to clear the RD_REQ
4005  *
4006  * interrupt (bit 5) of the IC_RAW_INTR_STAT register.
4007  *
4008  * Reset value: 0x0
4009  *
4010  * Field Access Macros:
4011  *
4012  */
4013 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */
4014 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_LSB 0
4015 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */
4016 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_MSB 0
4017 /* The width in bits of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */
4018 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1
4019 /* The mask used to set the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */
4020 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001
4021 /* The mask used to clear the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value. */
4022 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe
4023 /* The reset value of the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field. */
4024 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0
4025 /* Extracts the ALT_I2C_CLR_RD_REQ_CLR_RD_REQ field value from a register. */
4026 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0)
4027 /* Produces a ALT_I2C_CLR_RD_REQ_CLR_RD_REQ register field value suitable for setting the register. */
4028 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001)
4029 
4030 #ifndef __ASSEMBLY__
4031 /*
4032  * WARNING: The C register and register group struct declarations are provided for
4033  * convenience and illustrative purposes. They should, however, be used with
4034  * caution as the C language standard provides no guarantees about the alignment or
4035  * atomicity of device memory accesses. The recommended practice for writing
4036  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4037  * alt_write_word() functions.
4038  *
4039  * The struct declaration for register ALT_I2C_CLR_RD_REQ.
4040  */
4041 struct ALT_I2C_CLR_RD_REQ_s
4042 {
4043  const uint32_t clr_rd_req : 1; /* ALT_I2C_CLR_RD_REQ_CLR_RD_REQ */
4044  uint32_t : 31; /* *UNDEFINED* */
4045 };
4046 
4047 /* The typedef declaration for register ALT_I2C_CLR_RD_REQ. */
4048 typedef volatile struct ALT_I2C_CLR_RD_REQ_s ALT_I2C_CLR_RD_REQ_t;
4049 #endif /* __ASSEMBLY__ */
4050 
4051 /* The reset value of the ALT_I2C_CLR_RD_REQ register. */
4052 #define ALT_I2C_CLR_RD_REQ_RESET 0x00000000
4053 /* The byte offset of the ALT_I2C_CLR_RD_REQ register from the beginning of the component. */
4054 #define ALT_I2C_CLR_RD_REQ_OFST 0x50
4055 /* The address of the ALT_I2C_CLR_RD_REQ register. */
4056 #define ALT_I2C_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RD_REQ_OFST))
4057 
4058 /*
4059  * Register : ic_clr_tx_abrt
4060  *
4061  * Name: Clear TX_ABRT Interrupt Register
4062  *
4063  * Size: 1 bit
4064  *
4065  * Address Offset: 0x54
4066  *
4067  * Read/Write Access: Read
4068  *
4069  * Register Layout
4070  *
4071  * Bits | Access | Reset | Description
4072  * :-------|:-------|:------|:-------------------------------
4073  * [0] | R | 0x0 | ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT
4074  * [31:1] | ??? | 0x0 | *UNDEFINED*
4075  *
4076  */
4077 /*
4078  * Field : clr_tx_abort
4079  *
4080  * Read this register to clear the TX_ABRT
4081  *
4082  * interrupt (bit 6) of the IC_RAW_INTR_STAT register,
4083  *
4084  * and the IC_TX_ABRT_SOURCE register.
4085  *
4086  * This also releases the TX FIFO from the flushed/reset
4087  *
4088  * state, allowing more writes to the TX FIFO.
4089  *
4090  * Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for
4091  *
4092  * an exception to clearing IC_TX_ABRT_SOURCE.
4093  *
4094  * Reset value: 0x0
4095  *
4096  * Field Access Macros:
4097  *
4098  */
4099 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */
4100 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_LSB 0
4101 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */
4102 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_MSB 0
4103 /* The width in bits of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */
4104 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_WIDTH 1
4105 /* The mask used to set the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */
4106 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET_MSK 0x00000001
4107 /* The mask used to clear the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value. */
4108 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_CLR_MSK 0xfffffffe
4109 /* The reset value of the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field. */
4110 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_RESET 0x0
4111 /* Extracts the ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT field value from a register. */
4112 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_GET(value) (((value) & 0x00000001) >> 0)
4113 /* Produces a ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT register field value suitable for setting the register. */
4114 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET(value) (((value) << 0) & 0x00000001)
4115 
4116 #ifndef __ASSEMBLY__
4117 /*
4118  * WARNING: The C register and register group struct declarations are provided for
4119  * convenience and illustrative purposes. They should, however, be used with
4120  * caution as the C language standard provides no guarantees about the alignment or
4121  * atomicity of device memory accesses. The recommended practice for writing
4122  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4123  * alt_write_word() functions.
4124  *
4125  * The struct declaration for register ALT_I2C_CLR_TX_ABRT.
4126  */
4127 struct ALT_I2C_CLR_TX_ABRT_s
4128 {
4129  const uint32_t clr_tx_abort : 1; /* ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT */
4130  uint32_t : 31; /* *UNDEFINED* */
4131 };
4132 
4133 /* The typedef declaration for register ALT_I2C_CLR_TX_ABRT. */
4134 typedef volatile struct ALT_I2C_CLR_TX_ABRT_s ALT_I2C_CLR_TX_ABRT_t;
4135 #endif /* __ASSEMBLY__ */
4136 
4137 /* The reset value of the ALT_I2C_CLR_TX_ABRT register. */
4138 #define ALT_I2C_CLR_TX_ABRT_RESET 0x00000000
4139 /* The byte offset of the ALT_I2C_CLR_TX_ABRT register from the beginning of the component. */
4140 #define ALT_I2C_CLR_TX_ABRT_OFST 0x54
4141 /* The address of the ALT_I2C_CLR_TX_ABRT register. */
4142 #define ALT_I2C_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_ABRT_OFST))
4143 
4144 /*
4145  * Register : ic_clr_rx_done
4146  *
4147  * Name: Clear RX_DONE Interrupt Register
4148  *
4149  * Size: 1 bit
4150  *
4151  * Address Offset: 0x58
4152  *
4153  * Read/Write Access: Read
4154  *
4155  * Register Layout
4156  *
4157  * Bits | Access | Reset | Description
4158  * :-------|:-------|:------|:--------------------------------
4159  * [0] | R | 0x0 | ALT_I2C_CLR_RX_DONE_CLR_RX_DONE
4160  * [31:1] | ??? | 0x0 | *UNDEFINED*
4161  *
4162  */
4163 /*
4164  * Field : clr_rx_done
4165  *
4166  * Read this register to clear the RX_DONE
4167  *
4168  * interrupt (bit 7) of the IC_RAW_INTR_STAT register.
4169  *
4170  * Reset value: 0x0
4171  *
4172  * Field Access Macros:
4173  *
4174  */
4175 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */
4176 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_LSB 0
4177 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */
4178 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_MSB 0
4179 /* The width in bits of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */
4180 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1
4181 /* The mask used to set the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */
4182 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001
4183 /* The mask used to clear the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value. */
4184 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe
4185 /* The reset value of the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field. */
4186 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0
4187 /* Extracts the ALT_I2C_CLR_RX_DONE_CLR_RX_DONE field value from a register. */
4188 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0)
4189 /* Produces a ALT_I2C_CLR_RX_DONE_CLR_RX_DONE register field value suitable for setting the register. */
4190 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001)
4191 
4192 #ifndef __ASSEMBLY__
4193 /*
4194  * WARNING: The C register and register group struct declarations are provided for
4195  * convenience and illustrative purposes. They should, however, be used with
4196  * caution as the C language standard provides no guarantees about the alignment or
4197  * atomicity of device memory accesses. The recommended practice for writing
4198  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4199  * alt_write_word() functions.
4200  *
4201  * The struct declaration for register ALT_I2C_CLR_RX_DONE.
4202  */
4203 struct ALT_I2C_CLR_RX_DONE_s
4204 {
4205  const uint32_t clr_rx_done : 1; /* ALT_I2C_CLR_RX_DONE_CLR_RX_DONE */
4206  uint32_t : 31; /* *UNDEFINED* */
4207 };
4208 
4209 /* The typedef declaration for register ALT_I2C_CLR_RX_DONE. */
4210 typedef volatile struct ALT_I2C_CLR_RX_DONE_s ALT_I2C_CLR_RX_DONE_t;
4211 #endif /* __ASSEMBLY__ */
4212 
4213 /* The reset value of the ALT_I2C_CLR_RX_DONE register. */
4214 #define ALT_I2C_CLR_RX_DONE_RESET 0x00000000
4215 /* The byte offset of the ALT_I2C_CLR_RX_DONE register from the beginning of the component. */
4216 #define ALT_I2C_CLR_RX_DONE_OFST 0x58
4217 /* The address of the ALT_I2C_CLR_RX_DONE register. */
4218 #define ALT_I2C_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_DONE_OFST))
4219 
4220 /*
4221  * Register : ic_clr_activity
4222  *
4223  * Name: Clear ACTIVITY Interrupt Register
4224  *
4225  * Size: 1 bit
4226  *
4227  * Address Offset: 0x5c
4228  *
4229  * Read/Write Access: Read
4230  *
4231  * Register Layout
4232  *
4233  * Bits | Access | Reset | Description
4234  * :-------|:-------|:------|:----------------------------------
4235  * [0] | R | 0x0 | ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY
4236  * [31:1] | ??? | 0x0 | *UNDEFINED*
4237  *
4238  */
4239 /*
4240  * Field : clr_activity
4241  *
4242  * Reading this register clears the ACTIVITY
4243  *
4244  * interrupt if the I2C is not active anymore. If the
4245  *
4246  * I2C module is still active on the bus, the ACTIVITY
4247  *
4248  * interrupt bit continues to be set. It is automatically
4249  *
4250  * cleared by hardware if the module is disabled and if
4251  *
4252  * there is no further activity on the bus. The value read
4253  *
4254  * from this register to get status of the ACTIVITY interrupt
4255  *
4256  * (bit 8) of the IC_RAW_INTR_STAT register.
4257  *
4258  * Reset value: 0x0
4259  *
4260  * Field Access Macros:
4261  *
4262  */
4263 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */
4264 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0
4265 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */
4266 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0
4267 /* The width in bits of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */
4268 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1
4269 /* The mask used to set the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */
4270 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001
4271 /* The mask used to clear the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value. */
4272 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe
4273 /* The reset value of the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field. */
4274 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0
4275 /* Extracts the ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY field value from a register. */
4276 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
4277 /* Produces a ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY register field value suitable for setting the register. */
4278 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
4279 
4280 #ifndef __ASSEMBLY__
4281 /*
4282  * WARNING: The C register and register group struct declarations are provided for
4283  * convenience and illustrative purposes. They should, however, be used with
4284  * caution as the C language standard provides no guarantees about the alignment or
4285  * atomicity of device memory accesses. The recommended practice for writing
4286  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4287  * alt_write_word() functions.
4288  *
4289  * The struct declaration for register ALT_I2C_CLR_ACTIVITY.
4290  */
4291 struct ALT_I2C_CLR_ACTIVITY_s
4292 {
4293  const uint32_t clr_activity : 1; /* ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY */
4294  uint32_t : 31; /* *UNDEFINED* */
4295 };
4296 
4297 /* The typedef declaration for register ALT_I2C_CLR_ACTIVITY. */
4298 typedef volatile struct ALT_I2C_CLR_ACTIVITY_s ALT_I2C_CLR_ACTIVITY_t;
4299 #endif /* __ASSEMBLY__ */
4300 
4301 /* The reset value of the ALT_I2C_CLR_ACTIVITY register. */
4302 #define ALT_I2C_CLR_ACTIVITY_RESET 0x00000000
4303 /* The byte offset of the ALT_I2C_CLR_ACTIVITY register from the beginning of the component. */
4304 #define ALT_I2C_CLR_ACTIVITY_OFST 0x5c
4305 /* The address of the ALT_I2C_CLR_ACTIVITY register. */
4306 #define ALT_I2C_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_ACTIVITY_OFST))
4307 
4308 /*
4309  * Register : ic_clr_stop_det
4310  *
4311  * Name: Clear STOP_DET Interrupt Register
4312  *
4313  * Size: 1 bit
4314  *
4315  * Address Offset: 0x60
4316  *
4317  * Read/Write Access: Read
4318  *
4319  * Register Layout
4320  *
4321  * Bits | Access | Reset | Description
4322  * :-------|:-------|:------|:----------------------------------
4323  * [0] | R | 0x0 | ALT_I2C_CLR_STOP_DET_CLR_STOP_DET
4324  * [31:1] | ??? | 0x0 | *UNDEFINED*
4325  *
4326  */
4327 /*
4328  * Field : clr_stop_det
4329  *
4330  * Read this register to clear the STOP_DET
4331  *
4332  * interrupt (bit 9) of the IC_RAW_INTR_STAT register.
4333  *
4334  * Reset value: 0x0
4335  *
4336  * Field Access Macros:
4337  *
4338  */
4339 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */
4340 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_LSB 0
4341 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */
4342 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_MSB 0
4343 /* The width in bits of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */
4344 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1
4345 /* The mask used to set the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */
4346 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001
4347 /* The mask used to clear the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value. */
4348 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe
4349 /* The reset value of the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field. */
4350 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0
4351 /* Extracts the ALT_I2C_CLR_STOP_DET_CLR_STOP_DET field value from a register. */
4352 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0)
4353 /* Produces a ALT_I2C_CLR_STOP_DET_CLR_STOP_DET register field value suitable for setting the register. */
4354 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001)
4355 
4356 #ifndef __ASSEMBLY__
4357 /*
4358  * WARNING: The C register and register group struct declarations are provided for
4359  * convenience and illustrative purposes. They should, however, be used with
4360  * caution as the C language standard provides no guarantees about the alignment or
4361  * atomicity of device memory accesses. The recommended practice for writing
4362  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4363  * alt_write_word() functions.
4364  *
4365  * The struct declaration for register ALT_I2C_CLR_STOP_DET.
4366  */
4367 struct ALT_I2C_CLR_STOP_DET_s
4368 {
4369  const uint32_t clr_stop_det : 1; /* ALT_I2C_CLR_STOP_DET_CLR_STOP_DET */
4370  uint32_t : 31; /* *UNDEFINED* */
4371 };
4372 
4373 /* The typedef declaration for register ALT_I2C_CLR_STOP_DET. */
4374 typedef volatile struct ALT_I2C_CLR_STOP_DET_s ALT_I2C_CLR_STOP_DET_t;
4375 #endif /* __ASSEMBLY__ */
4376 
4377 /* The reset value of the ALT_I2C_CLR_STOP_DET register. */
4378 #define ALT_I2C_CLR_STOP_DET_RESET 0x00000000
4379 /* The byte offset of the ALT_I2C_CLR_STOP_DET register from the beginning of the component. */
4380 #define ALT_I2C_CLR_STOP_DET_OFST 0x60
4381 /* The address of the ALT_I2C_CLR_STOP_DET register. */
4382 #define ALT_I2C_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_STOP_DET_OFST))
4383 
4384 /*
4385  * Register : ic_clr_start_det
4386  *
4387  * Name: Clear START_DET Interrupt Register
4388  *
4389  * Size: 1 bit
4390  *
4391  * Address Offset: 0x64
4392  *
4393  * Read/Write Access: Read
4394  *
4395  * Register Layout
4396  *
4397  * Bits | Access | Reset | Description
4398  * :-------|:-------|:------|:------------------------------------
4399  * [0] | R | 0x0 | ALT_I2C_CLR_START_DET_CLR_START_DET
4400  * [31:1] | ??? | 0x0 | *UNDEFINED*
4401  *
4402  */
4403 /*
4404  * Field : clr_start_det
4405  *
4406  * Read this register to clear the START_DET
4407  *
4408  * interrupt (bit 10) of the IC_RAW_INTR_STAT register.
4409  *
4410  * Reset value: 0x0
4411  *
4412  * Field Access Macros:
4413  *
4414  */
4415 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */
4416 #define ALT_I2C_CLR_START_DET_CLR_START_DET_LSB 0
4417 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */
4418 #define ALT_I2C_CLR_START_DET_CLR_START_DET_MSB 0
4419 /* The width in bits of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */
4420 #define ALT_I2C_CLR_START_DET_CLR_START_DET_WIDTH 1
4421 /* The mask used to set the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */
4422 #define ALT_I2C_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001
4423 /* The mask used to clear the ALT_I2C_CLR_START_DET_CLR_START_DET register field value. */
4424 #define ALT_I2C_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe
4425 /* The reset value of the ALT_I2C_CLR_START_DET_CLR_START_DET register field. */
4426 #define ALT_I2C_CLR_START_DET_CLR_START_DET_RESET 0x0
4427 /* Extracts the ALT_I2C_CLR_START_DET_CLR_START_DET field value from a register. */
4428 #define ALT_I2C_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0)
4429 /* Produces a ALT_I2C_CLR_START_DET_CLR_START_DET register field value suitable for setting the register. */
4430 #define ALT_I2C_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001)
4431 
4432 #ifndef __ASSEMBLY__
4433 /*
4434  * WARNING: The C register and register group struct declarations are provided for
4435  * convenience and illustrative purposes. They should, however, be used with
4436  * caution as the C language standard provides no guarantees about the alignment or
4437  * atomicity of device memory accesses. The recommended practice for writing
4438  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4439  * alt_write_word() functions.
4440  *
4441  * The struct declaration for register ALT_I2C_CLR_START_DET.
4442  */
4443 struct ALT_I2C_CLR_START_DET_s
4444 {
4445  const uint32_t clr_start_det : 1; /* ALT_I2C_CLR_START_DET_CLR_START_DET */
4446  uint32_t : 31; /* *UNDEFINED* */
4447 };
4448 
4449 /* The typedef declaration for register ALT_I2C_CLR_START_DET. */
4450 typedef volatile struct ALT_I2C_CLR_START_DET_s ALT_I2C_CLR_START_DET_t;
4451 #endif /* __ASSEMBLY__ */
4452 
4453 /* The reset value of the ALT_I2C_CLR_START_DET register. */
4454 #define ALT_I2C_CLR_START_DET_RESET 0x00000000
4455 /* The byte offset of the ALT_I2C_CLR_START_DET register from the beginning of the component. */
4456 #define ALT_I2C_CLR_START_DET_OFST 0x64
4457 /* The address of the ALT_I2C_CLR_START_DET register. */
4458 #define ALT_I2C_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_START_DET_OFST))
4459 
4460 /*
4461  * Register : ic_clr_gen_call
4462  *
4463  * Name: Clear GEN_CALL Interrupt Register
4464  *
4465  * Size: 1 bit
4466  *
4467  * Address Offset: 0x68
4468  *
4469  * Read/Write Access: Read
4470  *
4471  * Register Layout
4472  *
4473  * Bits | Access | Reset | Description
4474  * :-------|:-------|:------|:----------------------------------
4475  * [0] | R | 0x0 | ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL
4476  * [31:1] | ??? | 0x0 | *UNDEFINED*
4477  *
4478  */
4479 /*
4480  * Field : clr_gen_call
4481  *
4482  * Read this register to clear the GEN_CALL
4483  *
4484  * interrupt (bit 11) of IC_RAW_INTR_STAT register.
4485  *
4486  * Reset value: 0x0
4487  *
4488  * Field Access Macros:
4489  *
4490  */
4491 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */
4492 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0
4493 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */
4494 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0
4495 /* The width in bits of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */
4496 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1
4497 /* The mask used to set the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */
4498 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001
4499 /* The mask used to clear the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value. */
4500 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe
4501 /* The reset value of the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field. */
4502 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0
4503 /* Extracts the ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL field value from a register. */
4504 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
4505 /* Produces a ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL register field value suitable for setting the register. */
4506 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
4507 
4508 #ifndef __ASSEMBLY__
4509 /*
4510  * WARNING: The C register and register group struct declarations are provided for
4511  * convenience and illustrative purposes. They should, however, be used with
4512  * caution as the C language standard provides no guarantees about the alignment or
4513  * atomicity of device memory accesses. The recommended practice for writing
4514  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4515  * alt_write_word() functions.
4516  *
4517  * The struct declaration for register ALT_I2C_CLR_GEN_CALL.
4518  */
4519 struct ALT_I2C_CLR_GEN_CALL_s
4520 {
4521  const uint32_t clr_gen_call : 1; /* ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL */
4522  uint32_t : 31; /* *UNDEFINED* */
4523 };
4524 
4525 /* The typedef declaration for register ALT_I2C_CLR_GEN_CALL. */
4526 typedef volatile struct ALT_I2C_CLR_GEN_CALL_s ALT_I2C_CLR_GEN_CALL_t;
4527 #endif /* __ASSEMBLY__ */
4528 
4529 /* The reset value of the ALT_I2C_CLR_GEN_CALL register. */
4530 #define ALT_I2C_CLR_GEN_CALL_RESET 0x00000000
4531 /* The byte offset of the ALT_I2C_CLR_GEN_CALL register from the beginning of the component. */
4532 #define ALT_I2C_CLR_GEN_CALL_OFST 0x68
4533 /* The address of the ALT_I2C_CLR_GEN_CALL register. */
4534 #define ALT_I2C_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_GEN_CALL_OFST))
4535 
4536 /*
4537  * Register : ic_enable
4538  *
4539  * Name: I2C Enable Register
4540  *
4541  * Size: 2 bits
4542  *
4543  * Address Offset: 0x6c
4544  *
4545  * Read/Write Access: Read/Write
4546  *
4547  * Register Layout
4548  *
4549  * Bits | Access | Reset | Description
4550  * :-------|:-------|:------|:-----------------
4551  * [0] | RW | 0x0 | ALT_I2C_EN_EN
4552  * [1] | RW | 0x0 | ALT_I2C_EN_TXABT
4553  * [31:2] | ??? | 0x0 | *UNDEFINED*
4554  *
4555  */
4556 /*
4557  * Field : enable
4558  *
4559  * Controls whether the DW_apb_i2c is enabled.
4560  *
4561  * 0: Disables DW_apb_i2c (TX and RX FIFOs are
4562  *
4563  * held in an erased state)
4564  *
4565  * 1: Enables DW_apb_i2c
4566  *
4567  * Software can disable DW_apb_i2c while it is active.
4568  *
4569  * However, it is important that care be taken to ensure
4570  *
4571  * that DW_apb_i2c is disabled properly.
4572  *
4573  * When DW_apb_i2c is disabled, the following occurs:
4574  *
4575  * * The TX FIFO and RX FIFO get flushed.
4576  *
4577  * * Status bits in the IC_INTR_STAT register are still
4578  *
4579  * active until DW_apb_i2c goes into IDLE state.
4580  *
4581  * If the module is transmitting, it stops as well as deletes
4582  *
4583  * the contents of the transmit buffer after the current transfer
4584  *
4585  * is complete. If the module is receiving, the DW_apb_i2c stops
4586  *
4587  * the current transfer at the end of the current byte and does not
4588  *
4589  * acknowledge the transfer.
4590  *
4591  * In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE
4592  *
4593  * parameter set to asynchronous (1), there is a two ic_clk delay
4594  *
4595  * when enabling or disabling the DW_apb_i2c.
4596  *
4597  * Reset value: 0x0
4598  *
4599  * Field Enumeration Values:
4600  *
4601  * Enum | Value | Description
4602  * :--------------------|:------|:-----------------------------------------------
4603  * ALT_I2C_EN_EN_E_DIS | 0x0 | Disables i2c. TX and RX FIFOs are held in an
4604  * : | | erased state
4605  * ALT_I2C_EN_EN_E_EN | 0x1 | Enables i2c. Software can disable i2c while it
4606  * : | | is active
4607  *
4608  * Field Access Macros:
4609  *
4610  */
4611 /*
4612  * Enumerated value for register field ALT_I2C_EN_EN
4613  *
4614  * Disables i2c. TX and RX FIFOs are held in an erased state
4615  */
4616 #define ALT_I2C_EN_EN_E_DIS 0x0
4617 /*
4618  * Enumerated value for register field ALT_I2C_EN_EN
4619  *
4620  * Enables i2c. Software can disable i2c while it is active
4621  */
4622 #define ALT_I2C_EN_EN_E_EN 0x1
4623 
4624 /* The Least Significant Bit (LSB) position of the ALT_I2C_EN_EN register field. */
4625 #define ALT_I2C_EN_EN_LSB 0
4626 /* The Most Significant Bit (MSB) position of the ALT_I2C_EN_EN register field. */
4627 #define ALT_I2C_EN_EN_MSB 0
4628 /* The width in bits of the ALT_I2C_EN_EN register field. */
4629 #define ALT_I2C_EN_EN_WIDTH 1
4630 /* The mask used to set the ALT_I2C_EN_EN register field value. */
4631 #define ALT_I2C_EN_EN_SET_MSK 0x00000001
4632 /* The mask used to clear the ALT_I2C_EN_EN register field value. */
4633 #define ALT_I2C_EN_EN_CLR_MSK 0xfffffffe
4634 /* The reset value of the ALT_I2C_EN_EN register field. */
4635 #define ALT_I2C_EN_EN_RESET 0x0
4636 /* Extracts the ALT_I2C_EN_EN field value from a register. */
4637 #define ALT_I2C_EN_EN_GET(value) (((value) & 0x00000001) >> 0)
4638 /* Produces a ALT_I2C_EN_EN register field value suitable for setting the register. */
4639 #define ALT_I2C_EN_EN_SET(value) (((value) << 0) & 0x00000001)
4640 
4641 /*
4642  * Field : txabort
4643  *
4644  * When set, the controller initiates the transfer abort.
4645  *
4646  * 0: ABORT not initiated or ABORT done
4647  *
4648  * 1: ABORT operation in progress
4649  *
4650  * The software can abort the I2C transfer in master mode by setting this bit. The
4651  * software
4652  *
4653  * can set this bit only when ENABLE is already set; otherwise, the controller
4654  * ignores any
4655  *
4656  * write to ABORT bit. The software cannot clear the ABORT bit once set. In
4657  * response to
4658  *
4659  * an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing
4660  * the
4661  *
4662  * current transfer, then sets the TX_ABORT interrupt after the abort operation.
4663  * The
4664  *
4665  * ABORT bit is cleared automatically after the abort operation.
4666  *
4667  * Reset value: 0x0
4668  *
4669  * Field Access Macros:
4670  *
4671  */
4672 /* The Least Significant Bit (LSB) position of the ALT_I2C_EN_TXABT register field. */
4673 #define ALT_I2C_EN_TXABT_LSB 1
4674 /* The Most Significant Bit (MSB) position of the ALT_I2C_EN_TXABT register field. */
4675 #define ALT_I2C_EN_TXABT_MSB 1
4676 /* The width in bits of the ALT_I2C_EN_TXABT register field. */
4677 #define ALT_I2C_EN_TXABT_WIDTH 1
4678 /* The mask used to set the ALT_I2C_EN_TXABT register field value. */
4679 #define ALT_I2C_EN_TXABT_SET_MSK 0x00000002
4680 /* The mask used to clear the ALT_I2C_EN_TXABT register field value. */
4681 #define ALT_I2C_EN_TXABT_CLR_MSK 0xfffffffd
4682 /* The reset value of the ALT_I2C_EN_TXABT register field. */
4683 #define ALT_I2C_EN_TXABT_RESET 0x0
4684 /* Extracts the ALT_I2C_EN_TXABT field value from a register. */
4685 #define ALT_I2C_EN_TXABT_GET(value) (((value) & 0x00000002) >> 1)
4686 /* Produces a ALT_I2C_EN_TXABT register field value suitable for setting the register. */
4687 #define ALT_I2C_EN_TXABT_SET(value) (((value) << 1) & 0x00000002)
4688 
4689 #ifndef __ASSEMBLY__
4690 /*
4691  * WARNING: The C register and register group struct declarations are provided for
4692  * convenience and illustrative purposes. They should, however, be used with
4693  * caution as the C language standard provides no guarantees about the alignment or
4694  * atomicity of device memory accesses. The recommended practice for writing
4695  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4696  * alt_write_word() functions.
4697  *
4698  * The struct declaration for register ALT_I2C_EN.
4699  */
4700 struct ALT_I2C_EN_s
4701 {
4702  uint32_t enable : 1; /* ALT_I2C_EN_EN */
4703  uint32_t txabort : 1; /* ALT_I2C_EN_TXABT */
4704  uint32_t : 30; /* *UNDEFINED* */
4705 };
4706 
4707 /* The typedef declaration for register ALT_I2C_EN. */
4708 typedef volatile struct ALT_I2C_EN_s ALT_I2C_EN_t;
4709 #endif /* __ASSEMBLY__ */
4710 
4711 /* The reset value of the ALT_I2C_EN register. */
4712 #define ALT_I2C_EN_RESET 0x00000000
4713 /* The byte offset of the ALT_I2C_EN register from the beginning of the component. */
4714 #define ALT_I2C_EN_OFST 0x6c
4715 /* The address of the ALT_I2C_EN register. */
4716 #define ALT_I2C_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_OFST))
4717 
4718 /*
4719  * Register : ic_status
4720  *
4721  * Name: I2C Status Register
4722  *
4723  * Size: 7 bits
4724  *
4725  * Address Offset: 0x70
4726  *
4727  * Read/Write Access: Read
4728  *
4729  * This is a read-only register used to indicate the current
4730  *
4731  * transfer status and FIFO status. The status register may be
4732  *
4733  * read at any time. None of the bits in this register request
4734  *
4735  * an interrupt.
4736  *
4737  * When the I2C is disabled by writing 0 in bit 0 of the
4738  *
4739  * IC_ENABLE register:
4740  *
4741  * * Bits 1 and 2 are set to 1
4742  *
4743  * * Bits 3 and 4 are set to 0
4744  *
4745  * When the master or slave state machines goes to idle
4746  *
4747  * and ic_en=0:
4748  *
4749  * * Bits 5 and 6 are set to 0
4750  *
4751  * Register Layout
4752  *
4753  * Bits | Access | Reset | Description
4754  * :-------|:-------|:------|:--------------------------
4755  * [0] | R | 0x0 | ALT_I2C_STAT_ACTIVITY
4756  * [1] | R | 0x1 | ALT_I2C_STAT_TFNF
4757  * [2] | R | 0x1 | ALT_I2C_STAT_TFE
4758  * [3] | R | 0x0 | ALT_I2C_STAT_RFNE
4759  * [4] | R | 0x0 | ALT_I2C_STAT_RFF
4760  * [5] | R | 0x0 | ALT_I2C_STAT_MST_ACTIVITY
4761  * [6] | R | 0x0 | ALT_I2C_STAT_SLV_ACTIVITY
4762  * [31:7] | ??? | 0x0 | *UNDEFINED*
4763  *
4764  */
4765 /*
4766  * Field : activity
4767  *
4768  * I2C Activity Status.
4769  *
4770  * Reset value: 0x0
4771  *
4772  * Field Access Macros:
4773  *
4774  */
4775 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_ACTIVITY register field. */
4776 #define ALT_I2C_STAT_ACTIVITY_LSB 0
4777 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_ACTIVITY register field. */
4778 #define ALT_I2C_STAT_ACTIVITY_MSB 0
4779 /* The width in bits of the ALT_I2C_STAT_ACTIVITY register field. */
4780 #define ALT_I2C_STAT_ACTIVITY_WIDTH 1
4781 /* The mask used to set the ALT_I2C_STAT_ACTIVITY register field value. */
4782 #define ALT_I2C_STAT_ACTIVITY_SET_MSK 0x00000001
4783 /* The mask used to clear the ALT_I2C_STAT_ACTIVITY register field value. */
4784 #define ALT_I2C_STAT_ACTIVITY_CLR_MSK 0xfffffffe
4785 /* The reset value of the ALT_I2C_STAT_ACTIVITY register field. */
4786 #define ALT_I2C_STAT_ACTIVITY_RESET 0x0
4787 /* Extracts the ALT_I2C_STAT_ACTIVITY field value from a register. */
4788 #define ALT_I2C_STAT_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
4789 /* Produces a ALT_I2C_STAT_ACTIVITY register field value suitable for setting the register. */
4790 #define ALT_I2C_STAT_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
4791 
4792 /*
4793  * Field : tfnf
4794  *
4795  * Transmit FIFO Not Full.
4796  *
4797  * Set when the transmit FIFO contains one or more
4798  *
4799  * empty locations, and is cleared when the FIFO is full.
4800  *
4801  * 0: Transmit FIFO is full
4802  *
4803  * 1: Transmit FIFO is not full
4804  *
4805  * Reset value: 0x1
4806  *
4807  * Field Enumeration Values:
4808  *
4809  * Enum | Value | Description
4810  * :----------------------------|:------|:--------------------------
4811  * ALT_I2C_STAT_TFNF_E_FULL | 0x0 | Transmit FIFO is full
4812  * ALT_I2C_STAT_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full
4813  *
4814  * Field Access Macros:
4815  *
4816  */
4817 /*
4818  * Enumerated value for register field ALT_I2C_STAT_TFNF
4819  *
4820  * Transmit FIFO is full
4821  */
4822 #define ALT_I2C_STAT_TFNF_E_FULL 0x0
4823 /*
4824  * Enumerated value for register field ALT_I2C_STAT_TFNF
4825  *
4826  * Transmit FIFO is not full
4827  */
4828 #define ALT_I2C_STAT_TFNF_E_NOTFULL 0x1
4829 
4830 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFNF register field. */
4831 #define ALT_I2C_STAT_TFNF_LSB 1
4832 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFNF register field. */
4833 #define ALT_I2C_STAT_TFNF_MSB 1
4834 /* The width in bits of the ALT_I2C_STAT_TFNF register field. */
4835 #define ALT_I2C_STAT_TFNF_WIDTH 1
4836 /* The mask used to set the ALT_I2C_STAT_TFNF register field value. */
4837 #define ALT_I2C_STAT_TFNF_SET_MSK 0x00000002
4838 /* The mask used to clear the ALT_I2C_STAT_TFNF register field value. */
4839 #define ALT_I2C_STAT_TFNF_CLR_MSK 0xfffffffd
4840 /* The reset value of the ALT_I2C_STAT_TFNF register field. */
4841 #define ALT_I2C_STAT_TFNF_RESET 0x1
4842 /* Extracts the ALT_I2C_STAT_TFNF field value from a register. */
4843 #define ALT_I2C_STAT_TFNF_GET(value) (((value) & 0x00000002) >> 1)
4844 /* Produces a ALT_I2C_STAT_TFNF register field value suitable for setting the register. */
4845 #define ALT_I2C_STAT_TFNF_SET(value) (((value) << 1) & 0x00000002)
4846 
4847 /*
4848  * Field : tfe
4849  *
4850  * Transmit FIFO Completely Empty.
4851  *
4852  * When the transmit FIFO is completely empty, this bit is set.
4853  *
4854  * When it contains one or more valid entries, this bit is
4855  *
4856  * cleared. This bit field does not request an interrupt.
4857  *
4858  * 0: Transmit FIFO is not empty
4859  *
4860  * 1: Transmit FIFO is empty
4861  *
4862  * Reset value: 0x1
4863  *
4864  * Field Enumeration Values:
4865  *
4866  * Enum | Value | Description
4867  * :----------------------------|:------|:---------------------------
4868  * ALT_I2C_STAT_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty
4869  * ALT_I2C_STAT_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty
4870  *
4871  * Field Access Macros:
4872  *
4873  */
4874 /*
4875  * Enumerated value for register field ALT_I2C_STAT_TFE
4876  *
4877  * Transmit FIFO is not empty
4878  */
4879 #define ALT_I2C_STAT_TFE_E_NOTEMPTY 0x0
4880 /*
4881  * Enumerated value for register field ALT_I2C_STAT_TFE
4882  *
4883  * Transmit FIFO is empty
4884  */
4885 #define ALT_I2C_STAT_TFE_E_EMPTY 0x1
4886 
4887 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_TFE register field. */
4888 #define ALT_I2C_STAT_TFE_LSB 2
4889 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_TFE register field. */
4890 #define ALT_I2C_STAT_TFE_MSB 2
4891 /* The width in bits of the ALT_I2C_STAT_TFE register field. */
4892 #define ALT_I2C_STAT_TFE_WIDTH 1
4893 /* The mask used to set the ALT_I2C_STAT_TFE register field value. */
4894 #define ALT_I2C_STAT_TFE_SET_MSK 0x00000004
4895 /* The mask used to clear the ALT_I2C_STAT_TFE register field value. */
4896 #define ALT_I2C_STAT_TFE_CLR_MSK 0xfffffffb
4897 /* The reset value of the ALT_I2C_STAT_TFE register field. */
4898 #define ALT_I2C_STAT_TFE_RESET 0x1
4899 /* Extracts the ALT_I2C_STAT_TFE field value from a register. */
4900 #define ALT_I2C_STAT_TFE_GET(value) (((value) & 0x00000004) >> 2)
4901 /* Produces a ALT_I2C_STAT_TFE register field value suitable for setting the register. */
4902 #define ALT_I2C_STAT_TFE_SET(value) (((value) << 2) & 0x00000004)
4903 
4904 /*
4905  * Field : rfne
4906  *
4907  * Receive FIFO Not Empty.
4908  *
4909  * This bit is set when the receive FIFO contains one or
4910  *
4911  * more entries; it is cleared when the receive FIFO is empty.
4912  *
4913  * 0: Receive FIFO is empty
4914  *
4915  * 1: Receive FIFO is not empty
4916  *
4917  * Reset value: 0x0
4918  *
4919  * Field Enumeration Values:
4920  *
4921  * Enum | Value | Description
4922  * :-----------------------------|:------|:--------------------------
4923  * ALT_I2C_STAT_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty
4924  * ALT_I2C_STAT_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty
4925  *
4926  * Field Access Macros:
4927  *
4928  */
4929 /*
4930  * Enumerated value for register field ALT_I2C_STAT_RFNE
4931  *
4932  * Receive FIFO is empty
4933  */
4934 #define ALT_I2C_STAT_RFNE_E_EMPTY 0x0
4935 /*
4936  * Enumerated value for register field ALT_I2C_STAT_RFNE
4937  *
4938  * Receive FIFO is not empty
4939  */
4940 #define ALT_I2C_STAT_RFNE_E_NOTEMPTY 0x1
4941 
4942 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFNE register field. */
4943 #define ALT_I2C_STAT_RFNE_LSB 3
4944 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFNE register field. */
4945 #define ALT_I2C_STAT_RFNE_MSB 3
4946 /* The width in bits of the ALT_I2C_STAT_RFNE register field. */
4947 #define ALT_I2C_STAT_RFNE_WIDTH 1
4948 /* The mask used to set the ALT_I2C_STAT_RFNE register field value. */
4949 #define ALT_I2C_STAT_RFNE_SET_MSK 0x00000008
4950 /* The mask used to clear the ALT_I2C_STAT_RFNE register field value. */
4951 #define ALT_I2C_STAT_RFNE_CLR_MSK 0xfffffff7
4952 /* The reset value of the ALT_I2C_STAT_RFNE register field. */
4953 #define ALT_I2C_STAT_RFNE_RESET 0x0
4954 /* Extracts the ALT_I2C_STAT_RFNE field value from a register. */
4955 #define ALT_I2C_STAT_RFNE_GET(value) (((value) & 0x00000008) >> 3)
4956 /* Produces a ALT_I2C_STAT_RFNE register field value suitable for setting the register. */
4957 #define ALT_I2C_STAT_RFNE_SET(value) (((value) << 3) & 0x00000008)
4958 
4959 /*
4960  * Field : rff
4961  *
4962  * Receive FIFO Completely Full.
4963  *
4964  * When the receive FIFO is completely full, this
4965  *
4966  * bit is set. When the receive FIFO contains one
4967  *
4968  * or more empty location, this bit is cleared.
4969  *
4970  * 0: Receive FIFO is not full
4971  *
4972  * 1: Receive FIFO is full
4973  *
4974  * Reset value: 0x0
4975  *
4976  * Field Enumeration Values:
4977  *
4978  * Enum | Value | Description
4979  * :---------------------------|:------|:-------------------------
4980  * ALT_I2C_STAT_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full
4981  * ALT_I2C_STAT_RFF_E_FULL | 0x1 | Receive FIFO is full
4982  *
4983  * Field Access Macros:
4984  *
4985  */
4986 /*
4987  * Enumerated value for register field ALT_I2C_STAT_RFF
4988  *
4989  * Receive FIFO is not full
4990  */
4991 #define ALT_I2C_STAT_RFF_E_NOTFULL 0x0
4992 /*
4993  * Enumerated value for register field ALT_I2C_STAT_RFF
4994  *
4995  * Receive FIFO is full
4996  */
4997 #define ALT_I2C_STAT_RFF_E_FULL 0x1
4998 
4999 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_RFF register field. */
5000 #define ALT_I2C_STAT_RFF_LSB 4
5001 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_RFF register field. */
5002 #define ALT_I2C_STAT_RFF_MSB 4
5003 /* The width in bits of the ALT_I2C_STAT_RFF register field. */
5004 #define ALT_I2C_STAT_RFF_WIDTH 1
5005 /* The mask used to set the ALT_I2C_STAT_RFF register field value. */
5006 #define ALT_I2C_STAT_RFF_SET_MSK 0x00000010
5007 /* The mask used to clear the ALT_I2C_STAT_RFF register field value. */
5008 #define ALT_I2C_STAT_RFF_CLR_MSK 0xffffffef
5009 /* The reset value of the ALT_I2C_STAT_RFF register field. */
5010 #define ALT_I2C_STAT_RFF_RESET 0x0
5011 /* Extracts the ALT_I2C_STAT_RFF field value from a register. */
5012 #define ALT_I2C_STAT_RFF_GET(value) (((value) & 0x00000010) >> 4)
5013 /* Produces a ALT_I2C_STAT_RFF register field value suitable for setting the register. */
5014 #define ALT_I2C_STAT_RFF_SET(value) (((value) << 4) & 0x00000010)
5015 
5016 /*
5017  * Field : mst_activity
5018  *
5019  * Master FSM Activity Status.
5020  *
5021  * When the Master Finite State Machine (FSM) is
5022  *
5023  * not in the IDLE state, this bit is set.
5024  *
5025  * 0: Master FSM is in IDLE state so the Master part
5026  *
5027  * of DW_apb_i2c is not Active
5028  *
5029  * 1: Master FSM is not in IDLE state so the Master
5030  *
5031  * part of DW_apb_i2c is Active
5032  *
5033  * Note
5034  *
5035  * IC_STATUS[0]-that is, ACTIVITY bit-is the OR of
5036  *
5037  * SLV_ACTIVITY and MST_ACTIVITY bits.
5038  *
5039  * Reset value: 0x0
5040  *
5041  * Field Enumeration Values:
5042  *
5043  * Enum | Value | Description
5044  * :------------------------------------|:------|:------------------------------------------------
5045  * ALT_I2C_STAT_MST_ACTIVITY_E_IDLE | 0x0 | Master FSM is in IDLE state. Master part of i2c
5046  * : | | is not Active
5047  * ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE | 0x1 | Master FSM is not in IDLE state. Master part of
5048  * : | | i2c is Active
5049  *
5050  * Field Access Macros:
5051  *
5052  */
5053 /*
5054  * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY
5055  *
5056  * Master FSM is in IDLE state. Master part of i2c is not Active
5057  */
5058 #define ALT_I2C_STAT_MST_ACTIVITY_E_IDLE 0x0
5059 /*
5060  * Enumerated value for register field ALT_I2C_STAT_MST_ACTIVITY
5061  *
5062  * Master FSM is not in IDLE state. Master part of i2c is Active
5063  */
5064 #define ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE 0x1
5065 
5066 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */
5067 #define ALT_I2C_STAT_MST_ACTIVITY_LSB 5
5068 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_MST_ACTIVITY register field. */
5069 #define ALT_I2C_STAT_MST_ACTIVITY_MSB 5
5070 /* The width in bits of the ALT_I2C_STAT_MST_ACTIVITY register field. */
5071 #define ALT_I2C_STAT_MST_ACTIVITY_WIDTH 1
5072 /* The mask used to set the ALT_I2C_STAT_MST_ACTIVITY register field value. */
5073 #define ALT_I2C_STAT_MST_ACTIVITY_SET_MSK 0x00000020
5074 /* The mask used to clear the ALT_I2C_STAT_MST_ACTIVITY register field value. */
5075 #define ALT_I2C_STAT_MST_ACTIVITY_CLR_MSK 0xffffffdf
5076 /* The reset value of the ALT_I2C_STAT_MST_ACTIVITY register field. */
5077 #define ALT_I2C_STAT_MST_ACTIVITY_RESET 0x0
5078 /* Extracts the ALT_I2C_STAT_MST_ACTIVITY field value from a register. */
5079 #define ALT_I2C_STAT_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5)
5080 /* Produces a ALT_I2C_STAT_MST_ACTIVITY register field value suitable for setting the register. */
5081 #define ALT_I2C_STAT_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020)
5082 
5083 /*
5084  * Field : slv_activity
5085  *
5086  * Slave FSM Activity Status.
5087  *
5088  * When the Slave Finite State Machine (FSM) is not
5089  *
5090  * in the IDLE state, this bit is set.
5091  *
5092  * 0: Slave FSM is in IDLE state so the Slave part of
5093  *
5094  * DW_apb_i2c is not Active
5095  *
5096  * 1: Slave FSM is not in IDLE state so the Slave part
5097  *
5098  * of DW_apb_i2c is Active
5099  *
5100  * Reset value: 0x0
5101  *
5102  * Field Enumeration Values:
5103  *
5104  * Enum | Value | Description
5105  * :------------------------------------|:------|:-------------------------------------------------
5106  * ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE | 0x0 | Slave FSM is in IDLE state so the Slave part of
5107  * : | | i2c is not Active
5108  * ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE | 0x1 | Slave FSM is not in IDLE state so the Slave part
5109  * : | | of i2c is Active
5110  *
5111  * Field Access Macros:
5112  *
5113  */
5114 /*
5115  * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY
5116  *
5117  * Slave FSM is in IDLE state so the Slave part of i2c is not Active
5118  */
5119 #define ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE 0x0
5120 /*
5121  * Enumerated value for register field ALT_I2C_STAT_SLV_ACTIVITY
5122  *
5123  * Slave FSM is not in IDLE state so the Slave part of i2c is Active
5124  */
5125 #define ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE 0x1
5126 
5127 /* The Least Significant Bit (LSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */
5128 #define ALT_I2C_STAT_SLV_ACTIVITY_LSB 6
5129 /* The Most Significant Bit (MSB) position of the ALT_I2C_STAT_SLV_ACTIVITY register field. */
5130 #define ALT_I2C_STAT_SLV_ACTIVITY_MSB 6
5131 /* The width in bits of the ALT_I2C_STAT_SLV_ACTIVITY register field. */
5132 #define ALT_I2C_STAT_SLV_ACTIVITY_WIDTH 1
5133 /* The mask used to set the ALT_I2C_STAT_SLV_ACTIVITY register field value. */
5134 #define ALT_I2C_STAT_SLV_ACTIVITY_SET_MSK 0x00000040
5135 /* The mask used to clear the ALT_I2C_STAT_SLV_ACTIVITY register field value. */
5136 #define ALT_I2C_STAT_SLV_ACTIVITY_CLR_MSK 0xffffffbf
5137 /* The reset value of the ALT_I2C_STAT_SLV_ACTIVITY register field. */
5138 #define ALT_I2C_STAT_SLV_ACTIVITY_RESET 0x0
5139 /* Extracts the ALT_I2C_STAT_SLV_ACTIVITY field value from a register. */
5140 #define ALT_I2C_STAT_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6)
5141 /* Produces a ALT_I2C_STAT_SLV_ACTIVITY register field value suitable for setting the register. */
5142 #define ALT_I2C_STAT_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040)
5143 
5144 #ifndef __ASSEMBLY__
5145 /*
5146  * WARNING: The C register and register group struct declarations are provided for
5147  * convenience and illustrative purposes. They should, however, be used with
5148  * caution as the C language standard provides no guarantees about the alignment or
5149  * atomicity of device memory accesses. The recommended practice for writing
5150  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5151  * alt_write_word() functions.
5152  *
5153  * The struct declaration for register ALT_I2C_STAT.
5154  */
5155 struct ALT_I2C_STAT_s
5156 {
5157  const uint32_t activity : 1; /* ALT_I2C_STAT_ACTIVITY */
5158  const uint32_t tfnf : 1; /* ALT_I2C_STAT_TFNF */
5159  const uint32_t tfe : 1; /* ALT_I2C_STAT_TFE */
5160  const uint32_t rfne : 1; /* ALT_I2C_STAT_RFNE */
5161  const uint32_t rff : 1; /* ALT_I2C_STAT_RFF */
5162  const uint32_t mst_activity : 1; /* ALT_I2C_STAT_MST_ACTIVITY */
5163  const uint32_t slv_activity : 1; /* ALT_I2C_STAT_SLV_ACTIVITY */
5164  uint32_t : 25; /* *UNDEFINED* */
5165 };
5166 
5167 /* The typedef declaration for register ALT_I2C_STAT. */
5168 typedef volatile struct ALT_I2C_STAT_s ALT_I2C_STAT_t;
5169 #endif /* __ASSEMBLY__ */
5170 
5171 /* The reset value of the ALT_I2C_STAT register. */
5172 #define ALT_I2C_STAT_RESET 0x00000006
5173 /* The byte offset of the ALT_I2C_STAT register from the beginning of the component. */
5174 #define ALT_I2C_STAT_OFST 0x70
5175 /* The address of the ALT_I2C_STAT register. */
5176 #define ALT_I2C_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_STAT_OFST))
5177 
5178 /*
5179  * Register : ic_txflr
5180  *
5181  * Name: I2C Transmit FIFO Level Register
5182  *
5183  * Size: TX_ABW + 1
5184  *
5185  * Address Offset: 0x74
5186  *
5187  * Read/Write Access: Read
5188  *
5189  * This register contains the number of valid data
5190  *
5191  * entries in the transmit FIFO buffer. It is cleared
5192  *
5193  * whenever:
5194  *
5195  * * The I2C is disabled
5196  *
5197  * * There is a transmit abort that is, TX_ABRT bit is
5198  *
5199  * set in the IC_RAW_INTR_STAT register
5200  *
5201  * * The slave bulk transmit mode is aborted
5202  *
5203  * The register increments whenever data is placed into
5204  *
5205  * the transmit FIFO and decrements when data is
5206  *
5207  * taken from the transmit FIFO.
5208  *
5209  * Register Layout
5210  *
5211  * Bits | Access | Reset | Description
5212  * :-------|:-------|:------|:--------------------
5213  * [6:0] | R | 0x0 | ALT_I2C_TXFLR_TXFLR
5214  * [31:7] | ??? | 0x0 | *UNDEFINED*
5215  *
5216  */
5217 /*
5218  * Field : txflr
5219  *
5220  * Transmit FIFO Level.
5221  *
5222  * Contains the number of valid data entries in the
5223  *
5224  * transmit FIFO.
5225  *
5226  * Reset value: 0x0
5227  *
5228  * Field Access Macros:
5229  *
5230  */
5231 /* The Least Significant Bit (LSB) position of the ALT_I2C_TXFLR_TXFLR register field. */
5232 #define ALT_I2C_TXFLR_TXFLR_LSB 0
5233 /* The Most Significant Bit (MSB) position of the ALT_I2C_TXFLR_TXFLR register field. */
5234 #define ALT_I2C_TXFLR_TXFLR_MSB 6
5235 /* The width in bits of the ALT_I2C_TXFLR_TXFLR register field. */
5236 #define ALT_I2C_TXFLR_TXFLR_WIDTH 7
5237 /* The mask used to set the ALT_I2C_TXFLR_TXFLR register field value. */
5238 #define ALT_I2C_TXFLR_TXFLR_SET_MSK 0x0000007f
5239 /* The mask used to clear the ALT_I2C_TXFLR_TXFLR register field value. */
5240 #define ALT_I2C_TXFLR_TXFLR_CLR_MSK 0xffffff80
5241 /* The reset value of the ALT_I2C_TXFLR_TXFLR register field. */
5242 #define ALT_I2C_TXFLR_TXFLR_RESET 0x0
5243 /* Extracts the ALT_I2C_TXFLR_TXFLR field value from a register. */
5244 #define ALT_I2C_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0)
5245 /* Produces a ALT_I2C_TXFLR_TXFLR register field value suitable for setting the register. */
5246 #define ALT_I2C_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f)
5247 
5248 #ifndef __ASSEMBLY__
5249 /*
5250  * WARNING: The C register and register group struct declarations are provided for
5251  * convenience and illustrative purposes. They should, however, be used with
5252  * caution as the C language standard provides no guarantees about the alignment or
5253  * atomicity of device memory accesses. The recommended practice for writing
5254  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5255  * alt_write_word() functions.
5256  *
5257  * The struct declaration for register ALT_I2C_TXFLR.
5258  */
5259 struct ALT_I2C_TXFLR_s
5260 {
5261  const uint32_t txflr : 7; /* ALT_I2C_TXFLR_TXFLR */
5262  uint32_t : 25; /* *UNDEFINED* */
5263 };
5264 
5265 /* The typedef declaration for register ALT_I2C_TXFLR. */
5266 typedef volatile struct ALT_I2C_TXFLR_s ALT_I2C_TXFLR_t;
5267 #endif /* __ASSEMBLY__ */
5268 
5269 /* The reset value of the ALT_I2C_TXFLR register. */
5270 #define ALT_I2C_TXFLR_RESET 0x00000000
5271 /* The byte offset of the ALT_I2C_TXFLR register from the beginning of the component. */
5272 #define ALT_I2C_TXFLR_OFST 0x74
5273 /* The address of the ALT_I2C_TXFLR register. */
5274 #define ALT_I2C_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TXFLR_OFST))
5275 
5276 /*
5277  * Register : ic_rxflr
5278  *
5279  * Name: I2C Receive FIFO Level Register
5280  *
5281  * Size: RX_ABW + 1
5282  *
5283  * Address Offset: 0x78
5284  *
5285  * Read/Write Access: Read
5286  *
5287  * This register contains the number of valid data
5288  *
5289  * entries in the receive FIFO buffer. It is cleared
5290  *
5291  * whenever:
5292  *
5293  * * The I2C is disabled
5294  *
5295  * * Whenever there is a transmit abort caused by any
5296  *
5297  * of the events tracked in IC_TX_ABRT_SOURCE
5298  *
5299  * The register increments whenever data is placed into
5300  *
5301  * the receive FIFO and decrements when data is
5302  *
5303  * taken from the receive FIFO.
5304  *
5305  * Register Layout
5306  *
5307  * Bits | Access | Reset | Description
5308  * :-------|:-------|:------|:--------------------
5309  * [6:0] | R | 0x0 | ALT_I2C_RXFLR_RXFLR
5310  * [31:7] | ??? | 0x0 | *UNDEFINED*
5311  *
5312  */
5313 /*
5314  * Field : rxflr
5315  *
5316  * Receive FIFO Level.
5317  *
5318  * Contains the number of valid data entries in the
5319  *
5320  * receive FIFO.
5321  *
5322  * Reset value: 0x0
5323  *
5324  * Field Access Macros:
5325  *
5326  */
5327 /* The Least Significant Bit (LSB) position of the ALT_I2C_RXFLR_RXFLR register field. */
5328 #define ALT_I2C_RXFLR_RXFLR_LSB 0
5329 /* The Most Significant Bit (MSB) position of the ALT_I2C_RXFLR_RXFLR register field. */
5330 #define ALT_I2C_RXFLR_RXFLR_MSB 6
5331 /* The width in bits of the ALT_I2C_RXFLR_RXFLR register field. */
5332 #define ALT_I2C_RXFLR_RXFLR_WIDTH 7
5333 /* The mask used to set the ALT_I2C_RXFLR_RXFLR register field value. */
5334 #define ALT_I2C_RXFLR_RXFLR_SET_MSK 0x0000007f
5335 /* The mask used to clear the ALT_I2C_RXFLR_RXFLR register field value. */
5336 #define ALT_I2C_RXFLR_RXFLR_CLR_MSK 0xffffff80
5337 /* The reset value of the ALT_I2C_RXFLR_RXFLR register field. */
5338 #define ALT_I2C_RXFLR_RXFLR_RESET 0x0
5339 /* Extracts the ALT_I2C_RXFLR_RXFLR field value from a register. */
5340 #define ALT_I2C_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0)
5341 /* Produces a ALT_I2C_RXFLR_RXFLR register field value suitable for setting the register. */
5342 #define ALT_I2C_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f)
5343 
5344 #ifndef __ASSEMBLY__
5345 /*
5346  * WARNING: The C register and register group struct declarations are provided for
5347  * convenience and illustrative purposes. They should, however, be used with
5348  * caution as the C language standard provides no guarantees about the alignment or
5349  * atomicity of device memory accesses. The recommended practice for writing
5350  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5351  * alt_write_word() functions.
5352  *
5353  * The struct declaration for register ALT_I2C_RXFLR.
5354  */
5355 struct ALT_I2C_RXFLR_s
5356 {
5357  const uint32_t rxflr : 7; /* ALT_I2C_RXFLR_RXFLR */
5358  uint32_t : 25; /* *UNDEFINED* */
5359 };
5360 
5361 /* The typedef declaration for register ALT_I2C_RXFLR. */
5362 typedef volatile struct ALT_I2C_RXFLR_s ALT_I2C_RXFLR_t;
5363 #endif /* __ASSEMBLY__ */
5364 
5365 /* The reset value of the ALT_I2C_RXFLR register. */
5366 #define ALT_I2C_RXFLR_RESET 0x00000000
5367 /* The byte offset of the ALT_I2C_RXFLR register from the beginning of the component. */
5368 #define ALT_I2C_RXFLR_OFST 0x78
5369 /* The address of the ALT_I2C_RXFLR register. */
5370 #define ALT_I2C_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RXFLR_OFST))
5371 
5372 /*
5373  * Register : ic_sda_hold
5374  *
5375  * Name: I2C SDA Hold Time Length Register
5376  *
5377  * Size: 24 bits
5378  *
5379  * Address Offset: 0x7c
5380  *
5381  * Read/Write Access: Read/Write
5382  *
5383  * The bits [15:0] of this register are used to control the hold time of SDA during
5384  *
5385  * transmit in both slave and master mode (after SCL goes from HIGH to LOW).
5386  *
5387  * The bits [23:16] of this register are used to extend the SDA transition (if any)
5388  *
5389  * whenever SCL is HIGH in the receiver in either master or slave mode.
5390  *
5391  * The values in this register are in units of ic_clk period.
5392  *
5393  * This register controls the amount of time delay.
5394  *
5395  * The relevant I2C requirement is thd:DAT as detailed in the I2C
5396  *
5397  * Bus Specification.
5398  *
5399  * Register Layout
5400  *
5401  * Bits | Access | Reset | Description
5402  * :--------|:-------|:------|:--------------------------------
5403  * [15:0] | RW | 0x1 | ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD
5404  * [23:16] | RW | 0x0 | ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD
5405  * [31:24] | ??? | 0x0 | *UNDEFINED*
5406  *
5407  */
5408 /*
5409  * Field : ic_sda_tx_hold
5410  *
5411  * Sets the required SDA hold time
5412  *
5413  * in units of ic_clk period, when DW_apb_i2c acts as a transmitter.
5414  *
5415  * Reset value: IC_DEFAULT_SDA_HOLD[15:0].
5416  *
5417  * Field Access Macros:
5418  *
5419  */
5420 /* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD register field. */
5421 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_LSB 0
5422 /* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD register field. */
5423 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_MSB 15
5424 /* The width in bits of the ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD register field. */
5425 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_WIDTH 16
5426 /* The mask used to set the ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD register field value. */
5427 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_SET_MSK 0x0000ffff
5428 /* The mask used to clear the ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD register field value. */
5429 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_CLR_MSK 0xffff0000
5430 /* The reset value of the ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD register field. */
5431 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_RESET 0x1
5432 /* Extracts the ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD field value from a register. */
5433 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_GET(value) (((value) & 0x0000ffff) >> 0)
5434 /* Produces a ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD register field value suitable for setting the register. */
5435 #define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_SET(value) (((value) << 0) & 0x0000ffff)
5436 
5437 /*
5438  * Field : ic_sda_rx_hold
5439  *
5440  * Sets the required SDA hold time
5441  *
5442  * in units of ic_clk period, when DW_apb_i2c acts as a receiver.
5443  *
5444  * Reset value: IC_DEFAULT_SDA_HOLD[23:16].
5445  *
5446  * Field Access Macros:
5447  *
5448  */
5449 /* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD register field. */
5450 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_LSB 16
5451 /* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD register field. */
5452 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_MSB 23
5453 /* The width in bits of the ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD register field. */
5454 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_WIDTH 8
5455 /* The mask used to set the ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD register field value. */
5456 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_SET_MSK 0x00ff0000
5457 /* The mask used to clear the ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD register field value. */
5458 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_CLR_MSK 0xff00ffff
5459 /* The reset value of the ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD register field. */
5460 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_RESET 0x0
5461 /* Extracts the ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD field value from a register. */
5462 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_GET(value) (((value) & 0x00ff0000) >> 16)
5463 /* Produces a ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD register field value suitable for setting the register. */
5464 #define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_SET(value) (((value) << 16) & 0x00ff0000)
5465 
5466 #ifndef __ASSEMBLY__
5467 /*
5468  * WARNING: The C register and register group struct declarations are provided for
5469  * convenience and illustrative purposes. They should, however, be used with
5470  * caution as the C language standard provides no guarantees about the alignment or
5471  * atomicity of device memory accesses. The recommended practice for writing
5472  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5473  * alt_write_word() functions.
5474  *
5475  * The struct declaration for register ALT_I2C_SDA_HOLD.
5476  */
5477 struct ALT_I2C_SDA_HOLD_s
5478 {
5479  uint32_t ic_sda_tx_hold : 16; /* ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD */
5480  uint32_t ic_sda_rx_hold : 8; /* ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD */
5481  uint32_t : 8; /* *UNDEFINED* */
5482 };
5483 
5484 /* The typedef declaration for register ALT_I2C_SDA_HOLD. */
5485 typedef volatile struct ALT_I2C_SDA_HOLD_s ALT_I2C_SDA_HOLD_t;
5486 #endif /* __ASSEMBLY__ */
5487 
5488 /* The reset value of the ALT_I2C_SDA_HOLD register. */
5489 #define ALT_I2C_SDA_HOLD_RESET 0x00000001
5490 /* The byte offset of the ALT_I2C_SDA_HOLD register from the beginning of the component. */
5491 #define ALT_I2C_SDA_HOLD_OFST 0x7c
5492 /* The address of the ALT_I2C_SDA_HOLD register. */
5493 #define ALT_I2C_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_HOLD_OFST))
5494 
5495 /*
5496  * Register : ic_tx_abrt_source
5497  *
5498  * Name: I2C Transmit Abort Source Register
5499  *
5500  * Size: 32 bits
5501  *
5502  * Address Offset: 0x80
5503  *
5504  * Read/Write Access: Read
5505  *
5506  * This register has 32 bits that indicate the source
5507  *
5508  * of the TX_ABRT bit. Except for Bit 9, this register is
5509  *
5510  * cleared whenever the IC_CLR_TX_ABRT register or the
5511  *
5512  * IC_CLR_INTR register is read. To clear Bit 9, the source
5513  *
5514  * of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must
5515  *
5516  * be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared
5517  *
5518  * (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).
5519  *
5520  * Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this
5521  *
5522  * bit can be cleared in the same manner as other bits in this
5523  *
5524  * register. If the source of the ABRT_SBYTE_NORSTRT is not fixed
5525  *
5526  * before attempting to clear this bit, Bit 9 clears for one cycle
5527  *
5528  * and is then re-asserted.
5529  *
5530  * Register Layout
5531  *
5532  * Bits | Access | Reset | Description
5533  * :--------|:-------|:------|:-----------------------------------------------
5534  * [0] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK
5535  * [1] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK
5536  * [2] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK
5537  * [3] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK
5538  * [4] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK
5539  * [5] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD
5540  * [6] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET
5541  * [7] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET
5542  * [8] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT
5543  * [9] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT
5544  * [10] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT
5545  * [11] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS
5546  * [12] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ARB_LOST
5547  * [13] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO
5548  * [14] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST
5549  * [15] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX
5550  * [16] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT
5551  * [22:17] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17
5552  * [31:23] | R | 0x0 | ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT
5553  *
5554  */
5555 /*
5556  * Field : abrt_7b_addr_noack
5557  *
5558  * 1: Master is in 7-bit addressing mode
5559  *
5560  * and the address sent was not
5561  *
5562  * acknowledged by any slave.
5563  *
5564  * Reset value: 0x0
5565  *
5566  * Role of DW_apb_i2c: Master-Transmitter
5567  *
5568  * or Master-Receiver
5569  *
5570  * Field Access Macros:
5571  *
5572  */
5573 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */
5574 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB 0
5575 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */
5576 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB 0
5577 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */
5578 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH 1
5579 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */
5580 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001
5581 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value. */
5582 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe
5583 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field. */
5584 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET 0x0
5585 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK field value from a register. */
5586 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0)
5587 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value suitable for setting the register. */
5588 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001)
5589 
5590 /*
5591  * Field : abrt_10addr1_noack
5592  *
5593  * 1: Master is in 10-bit address mode and
5594  *
5595  * the first 10-bit address byte was not
5596  *
5597  * acknowledged by any slave.
5598  *
5599  * Reset value: 0x0
5600  *
5601  * Role of DW_apb_i2c: Master-Transmitter
5602  *
5603  * or Master-Receiver
5604  *
5605  * Field Access Macros:
5606  *
5607  */
5608 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */
5609 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB 1
5610 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */
5611 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB 1
5612 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */
5613 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH 1
5614 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */
5615 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002
5616 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value. */
5617 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd
5618 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field. */
5619 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET 0x0
5620 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK field value from a register. */
5621 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1)
5622 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value suitable for setting the register. */
5623 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002)
5624 
5625 /*
5626  * Field : abrt_10addr2_noack
5627  *
5628  * 1: Master is in 10-bit address mode and
5629  *
5630  * the second address byte of the 10-bit
5631  *
5632  * address was not acknowledged by any slave.
5633  *
5634  * Reset value: 0x0
5635  *
5636  * Role of DW_apb_i2c: Master-Transmitter
5637  *
5638  * or Master-Receiver
5639  *
5640  * Field Access Macros:
5641  *
5642  */
5643 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */
5644 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB 2
5645 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */
5646 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB 2
5647 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */
5648 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH 1
5649 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */
5650 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004
5651 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value. */
5652 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb
5653 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field. */
5654 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET 0x0
5655 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK field value from a register. */
5656 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2)
5657 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value suitable for setting the register. */
5658 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004)
5659 
5660 /*
5661  * Field : abrt_txdata_noack
5662  *
5663  * 1: This is a master-mode only bit.
5664  *
5665  * Master has received an
5666  *
5667  * acknowledgement for the address, but
5668  *
5669  * when it sent data byte(s) following the
5670  *
5671  * address, it did not receive an
5672  *
5673  * acknowledge from the remote slave(s).
5674  *
5675  * Reset value: 0x0
5676  *
5677  * Role of DW_apb_i2c: Master-Transmitter
5678  *
5679  * Field Access Macros:
5680  *
5681  */
5682 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */
5683 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB 3
5684 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */
5685 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB 3
5686 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */
5687 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH 1
5688 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */
5689 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK 0x00000008
5690 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value. */
5691 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7
5692 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field. */
5693 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET 0x0
5694 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK field value from a register. */
5695 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3)
5696 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value suitable for setting the register. */
5697 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008)
5698 
5699 /*
5700  * Field : abrt_gcall_noack
5701  *
5702  * 1: DW_apb_i2c in master mode sent a
5703  *
5704  * General Call and no slave on the bus
5705  *
5706  * acknowledged the General Call.
5707  *
5708  * Reset value: 0x0
5709  *
5710  * Role of DW_apb_i2c: Master-Transmitter
5711  *
5712  * Field Access Macros:
5713  *
5714  */
5715 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */
5716 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB 4
5717 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */
5718 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB 4
5719 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */
5720 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH 1
5721 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */
5722 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK 0x00000010
5723 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value. */
5724 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef
5725 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field. */
5726 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET 0x0
5727 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK field value from a register. */
5728 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4)
5729 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value suitable for setting the register. */
5730 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010)
5731 
5732 /*
5733  * Field : abrt_gcall_read
5734  *
5735  * 1: DW_apb_i2c in master mode sent a
5736  *
5737  * General Call but the user programmed
5738  *
5739  * the byte following the General Call to
5740  *
5741  * be a read from the bus
5742  *
5743  * (IC_DATA_CMD[9] is set to 1).
5744  *
5745  * Reset value: 0x0
5746  *
5747  * Role of DW_apb_i2c: Master-Transmitter
5748  *
5749  * Field Access Macros:
5750  *
5751  */
5752 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */
5753 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB 5
5754 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */
5755 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB 5
5756 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */
5757 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH 1
5758 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */
5759 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK 0x00000020
5760 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value. */
5761 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK 0xffffffdf
5762 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field. */
5763 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET 0x0
5764 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD field value from a register. */
5765 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value) (((value) & 0x00000020) >> 5)
5766 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value suitable for setting the register. */
5767 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value) (((value) << 5) & 0x00000020)
5768 
5769 /*
5770  * Field : abrt_hs_ackdet
5771  *
5772  * 1: Master is in High Speed mode and
5773  *
5774  * the High Speed Master code was
5775  *
5776  * acknowledged (wrong behavior).
5777  *
5778  * Reset value: 0x0
5779  *
5780  * Role of DW_apb_i2c: Master
5781  *
5782  * Field Access Macros:
5783  *
5784  */
5785 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */
5786 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB 6
5787 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */
5788 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB 6
5789 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */
5790 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH 1
5791 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */
5792 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK 0x00000040
5793 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value. */
5794 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf
5795 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field. */
5796 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET 0x0
5797 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET field value from a register. */
5798 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6)
5799 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value suitable for setting the register. */
5800 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040)
5801 
5802 /*
5803  * Field : abrt_sbyte_ackdet
5804  *
5805  * 1: Master has sent a START Byte and
5806  *
5807  * the START Byte was acknowledged (wrong behavior).
5808  *
5809  * Reset value: 0x0
5810  *
5811  * Role of DW_apb_i2c: Master
5812  *
5813  * Field Access Macros:
5814  *
5815  */
5816 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */
5817 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB 7
5818 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */
5819 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB 7
5820 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */
5821 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH 1
5822 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */
5823 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080
5824 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value. */
5825 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f
5826 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field. */
5827 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET 0x0
5828 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET field value from a register. */
5829 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7)
5830 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value suitable for setting the register. */
5831 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080)
5832 
5833 /*
5834  * Field : abrt_hs_norstrt
5835  *
5836  * 1: The restart is disabled
5837  *
5838  * (IC_RESTART_EN bit (IC_CON[5]) =0)
5839  *
5840  * and the user is trying to use the
5841  *
5842  * master to transfer data in High Speed
5843  *
5844  * mode.
5845  *
5846  * Reset value: 0x0
5847  *
5848  * Role of DW_apb_i2c: Master-Transmitter
5849  *
5850  * or Master-Receiver
5851  *
5852  * Field Access Macros:
5853  *
5854  */
5855 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */
5856 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB 8
5857 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */
5858 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB 8
5859 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */
5860 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH 1
5861 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */
5862 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK 0x00000100
5863 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value. */
5864 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff
5865 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field. */
5866 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET 0x0
5867 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT field value from a register. */
5868 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8)
5869 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value suitable for setting the register. */
5870 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100)
5871 
5872 /*
5873  * Field : abrt_sbyte_norstrt
5874  *
5875  * To clear Bit 9, the source of the
5876  *
5877  * ABRT_SBYTE_NORSTRT must be fixed first;
5878  *
5879  * restart must be enabled (IC_CON[5]=1),
5880  *
5881  * the SPECIAL bit must be cleared (IC_TAR[11]),
5882  *
5883  * or the GC_OR_START bit must be cleared
5884  *
5885  * (IC_TAR[10]). Once the source of the
5886  *
5887  * ABRT_SBYTE_NORSTRT is fixed,
5888  *
5889  * then this bit can be cleared in the same
5890  *
5891  * manner as other bits in this register. If
5892  *
5893  * the source of the ABRT_SBYTE_NORSTRT is not fixed
5894  *
5895  * before attempting to clear this bit, bit 9
5896  *
5897  * clears for one cycle and then gets reasserted.
5898  *
5899  * 1: The restart is disabled (IC_RESTART_EN bit
5900  *
5901  * (IC_CON[5]) =0) and the user is trying to
5902  *
5903  * send a START Byte.
5904  *
5905  * Reset value: 0x0
5906  *
5907  * Role of DW_apb_i2c: Master
5908  *
5909  * Field Access Macros:
5910  *
5911  */
5912 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */
5913 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB 9
5914 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */
5915 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB 9
5916 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */
5917 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH 1
5918 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */
5919 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200
5920 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value. */
5921 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff
5922 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field. */
5923 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET 0x0
5924 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT field value from a register. */
5925 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9)
5926 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value suitable for setting the register. */
5927 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200)
5928 
5929 /*
5930  * Field : abrt_10b_rd_norstrt
5931  *
5932  * 1: The restart is disabled
5933  *
5934  * (IC_RESTART_EN bit (IC_CON[5]) =0)
5935  *
5936  * and the master sends a read
5937  *
5938  * command in 10-bit addressing mode.
5939  *
5940  * Reset value: 0x0
5941  *
5942  * Role of DW_apb_i2c: Master-Receiver
5943  *
5944  * Field Access Macros:
5945  *
5946  */
5947 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */
5948 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB 10
5949 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */
5950 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB 10
5951 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */
5952 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH 1
5953 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */
5954 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400
5955 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value. */
5956 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff
5957 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field. */
5958 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET 0x0
5959 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT field value from a register. */
5960 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10)
5961 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value suitable for setting the register. */
5962 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400)
5963 
5964 /*
5965  * Field : abrt_master_dis
5966  *
5967  * 1: User tries to initiate a Master
5968  *
5969  * operation with the Master mode disabled.
5970  *
5971  * Reset value: 0x0
5972  *
5973  * Role of DW_apb_i2c: Master-Transmitter
5974  *
5975  * or Master-Receiver
5976  *
5977  * Field Access Macros:
5978  *
5979  */
5980 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */
5981 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB 11
5982 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */
5983 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB 11
5984 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */
5985 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH 1
5986 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */
5987 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK 0x00000800
5988 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value. */
5989 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK 0xfffff7ff
5990 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field. */
5991 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET 0x0
5992 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS field value from a register. */
5993 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value) (((value) & 0x00000800) >> 11)
5994 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value suitable for setting the register. */
5995 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value) (((value) << 11) & 0x00000800)
5996 
5997 /*
5998  * Field : arb_lost
5999  *
6000  * 1: Master has lost arbitration, or if
6001  *
6002  * IC_TX_ABRT_SOURCE[14] is also
6003  *
6004  * set, then the slave transmitter has lost
6005  *
6006  * arbitration.
6007  *
6008  * Reset value: 0x0
6009  *
6010  * Role of DW_apb_i2c: Master-Transmitter
6011  *
6012  * or Slave-Transmitter
6013  *
6014  * Field Access Macros:
6015  *
6016  */
6017 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */
6018 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB 12
6019 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */
6020 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB 12
6021 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */
6022 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH 1
6023 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */
6024 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK 0x00001000
6025 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value. */
6026 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK 0xffffefff
6027 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field. */
6028 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET 0x0
6029 /* Extracts the ALT_I2C_TX_ABRT_SRC_ARB_LOST field value from a register. */
6030 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12)
6031 /* Produces a ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value suitable for setting the register. */
6032 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value) (((value) << 12) & 0x00001000)
6033 
6034 /*
6035  * Field : abrt_slvflush_txfifo
6036  *
6037  * 1: Slave has received a read command
6038  *
6039  * and some data exists in the TX FIFO so
6040  *
6041  * the slave issues a TX_ABRT interrupt to
6042  *
6043  * flush old data in TX FIFO.
6044  *
6045  * Reset value: 0x0
6046  *
6047  * Role of DW_apb_i2c: Slave-Transmitter
6048  *
6049  * Field Access Macros:
6050  *
6051  */
6052 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */
6053 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB 13
6054 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */
6055 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB 13
6056 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */
6057 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH 1
6058 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */
6059 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000
6060 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value. */
6061 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff
6062 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field. */
6063 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET 0x0
6064 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO field value from a register. */
6065 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13)
6066 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value suitable for setting the register. */
6067 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000)
6068 
6069 /*
6070  * Field : abrt_slv_arblost
6071  *
6072  * 1: Slave lost the bus while transmitting
6073  *
6074  * data to a remote master.
6075  *
6076  * IC_TX_ABRT_SOURCE[12] is set at
6077  *
6078  * the same time.
6079  *
6080  * Note: Even though the slave never
6081  *
6082  * 'owns' the bus, something could go
6083  *
6084  * wrong on the bus. This is a fail safe
6085  *
6086  * check. For instance, during a data
6087  *
6088  * transmission at the low-to-high
6089  *
6090  * transition of SCL, if what is on the data
6091  *
6092  * bus is not what is supposed to be
6093  *
6094  * transmitted, then DW_apb_i2c no
6095  *
6096  * longer own the bus.
6097  *
6098  * Reset value: 0x0
6099  *
6100  * Role of DW_apb_i2c: Slave-Transmitter
6101  *
6102  * Field Access Macros:
6103  *
6104  */
6105 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */
6106 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB 14
6107 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */
6108 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB 14
6109 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */
6110 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH 1
6111 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */
6112 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK 0x00004000
6113 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value. */
6114 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff
6115 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field. */
6116 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET 0x0
6117 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST field value from a register. */
6118 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14)
6119 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value suitable for setting the register. */
6120 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000)
6121 
6122 /*
6123  * Field : abrt_slvrd_intx
6124  *
6125  * 1: When the processor side responds to
6126  *
6127  * a slave mode request for data to be
6128  *
6129  * transmitted to a remote master and user
6130  *
6131  * writes a 1 in CMD (bit 8) of
6132  *
6133  * IC_DATA_CMD register.
6134  *
6135  * Reset value: 0x0
6136  *
6137  * Role of DW_apb_i2c: Slave-Transmitter
6138  *
6139  * Field Access Macros:
6140  *
6141  */
6142 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */
6143 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB 15
6144 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */
6145 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB 15
6146 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */
6147 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH 1
6148 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */
6149 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK 0x00008000
6150 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value. */
6151 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff
6152 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field. */
6153 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET 0x0
6154 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX field value from a register. */
6155 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15)
6156 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value suitable for setting the register. */
6157 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000)
6158 
6159 /*
6160  * Field : abrt_user_abrt
6161  *
6162  * This is a master-mode-only bit. Master has
6163  *
6164  * detected the transfer abort (IC_ENABLE[1])
6165  *
6166  * Reset value: 0x0
6167  *
6168  * Role of DW_apb_i2c: Master-Transmitter
6169  *
6170  * Field Access Macros:
6171  *
6172  */
6173 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field. */
6174 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_LSB 16
6175 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field. */
6176 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_MSB 16
6177 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field. */
6178 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_WIDTH 1
6179 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field value. */
6180 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_SET_MSK 0x00010000
6181 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field value. */
6182 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_CLR_MSK 0xfffeffff
6183 /* The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field. */
6184 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_RESET 0x0
6185 /* Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT field value from a register. */
6186 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_GET(value) (((value) & 0x00010000) >> 16)
6187 /* Produces a ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field value suitable for setting the register. */
6188 #define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_SET(value) (((value) << 16) & 0x00010000)
6189 
6190 /*
6191  * Field : rsvd_ic_tx_abrt_source_22to17
6192  *
6193  * Reserved
6194  *
6195  * Reset value: 0x0
6196  *
6197  * Field Access Macros:
6198  *
6199  */
6200 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field. */
6201 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_LSB 17
6202 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field. */
6203 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_MSB 22
6204 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field. */
6205 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_WIDTH 6
6206 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field value. */
6207 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_SET_MSK 0x007e0000
6208 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field value. */
6209 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_CLR_MSK 0xff81ffff
6210 /* The reset value of the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field. */
6211 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_RESET 0x0
6212 /* Extracts the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 field value from a register. */
6213 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_GET(value) (((value) & 0x007e0000) >> 17)
6214 /* Produces a ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field value suitable for setting the register. */
6215 #define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_SET(value) (((value) << 17) & 0x007e0000)
6216 
6217 /*
6218  * Field : tx_flush_cnt
6219  *
6220  * This field indicates the
6221  *
6222  * number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.
6223  *
6224  * It is cleared whenever I2C is disabled.
6225  *
6226  * Reset value: 0x0
6227  *
6228  * Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
6229  *
6230  * Field Access Macros:
6231  *
6232  */
6233 /* The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field. */
6234 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_LSB 23
6235 /* The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field. */
6236 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_MSB 31
6237 /* The width in bits of the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field. */
6238 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_WIDTH 9
6239 /* The mask used to set the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field value. */
6240 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_SET_MSK 0xff800000
6241 /* The mask used to clear the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field value. */
6242 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_CLR_MSK 0x007fffff
6243 /* The reset value of the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field. */
6244 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_RESET 0x0
6245 /* Extracts the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT field value from a register. */
6246 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_GET(value) (((value) & 0xff800000) >> 23)
6247 /* Produces a ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field value suitable for setting the register. */
6248 #define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_SET(value) (((value) << 23) & 0xff800000)
6249 
6250 #ifndef __ASSEMBLY__
6251 /*
6252  * WARNING: The C register and register group struct declarations are provided for
6253  * convenience and illustrative purposes. They should, however, be used with
6254  * caution as the C language standard provides no guarantees about the alignment or
6255  * atomicity of device memory accesses. The recommended practice for writing
6256  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6257  * alt_write_word() functions.
6258  *
6259  * The struct declaration for register ALT_I2C_TX_ABRT_SRC.
6260  */
6261 struct ALT_I2C_TX_ABRT_SRC_s
6262 {
6263  const uint32_t abrt_7b_addr_noack : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK */
6264  const uint32_t abrt_10addr1_noack : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK */
6265  const uint32_t abrt_10addr2_noack : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK */
6266  const uint32_t abrt_txdata_noack : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK */
6267  const uint32_t abrt_gcall_noack : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK */
6268  const uint32_t abrt_gcall_read : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD */
6269  const uint32_t abrt_hs_ackdet : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET */
6270  const uint32_t abrt_sbyte_ackdet : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET */
6271  const uint32_t abrt_hs_norstrt : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT */
6272  const uint32_t abrt_sbyte_norstrt : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT */
6273  const uint32_t abrt_10b_rd_norstrt : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT */
6274  const uint32_t abrt_master_dis : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS */
6275  const uint32_t arb_lost : 1; /* ALT_I2C_TX_ABRT_SRC_ARB_LOST */
6276  const uint32_t abrt_slvflush_txfifo : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO */
6277  const uint32_t abrt_slv_arblost : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST */
6278  const uint32_t abrt_slvrd_intx : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX */
6279  const uint32_t abrt_user_abrt : 1; /* ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT */
6280  const uint32_t rsvd_ic_tx_abrt_source_22to17 : 6; /* ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 */
6281  const uint32_t tx_flush_cnt : 9; /* ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT */
6282 };
6283 
6284 /* The typedef declaration for register ALT_I2C_TX_ABRT_SRC. */
6285 typedef volatile struct ALT_I2C_TX_ABRT_SRC_s ALT_I2C_TX_ABRT_SRC_t;
6286 #endif /* __ASSEMBLY__ */
6287 
6288 /* The reset value of the ALT_I2C_TX_ABRT_SRC register. */
6289 #define ALT_I2C_TX_ABRT_SRC_RESET 0x00000000
6290 /* The byte offset of the ALT_I2C_TX_ABRT_SRC register from the beginning of the component. */
6291 #define ALT_I2C_TX_ABRT_SRC_OFST 0x80
6292 /* The address of the ALT_I2C_TX_ABRT_SRC register. */
6293 #define ALT_I2C_TX_ABRT_SRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST))
6294 
6295 /*
6296  * Register : ic_slv_data_nack_only
6297  *
6298  * Name: Generate Slave Data NACK Register
6299  *
6300  * Size: 1 bit
6301  *
6302  * Address Offset: 0x84
6303  *
6304  * Read/Write Access: Read/Write
6305  *
6306  * The register is used to generate a NACK for
6307  *
6308  * the data part of a transfer when DW_apb_i2c is
6309  *
6310  * acting as a slave-receiver. This register only
6311  *
6312  * exists when the IC_SLV_DATA_NACK_ONLY parameter
6313  *
6314  * is set to 1. When this parameter disabled, this
6315  *
6316  * register does not exist and writing to the register's
6317  *
6318  * address has no effect.
6319  *
6320  * Register Layout
6321  *
6322  * Bits | Access | Reset | Description
6323  * :-------|:-------|:------|:--------------------------------
6324  * [0] | RW | 0x0 | ALT_I2C_SLV_DATA_NACK_ONLY_NACK
6325  * [31:1] | ??? | 0x0 | *UNDEFINED*
6326  *
6327  */
6328 /*
6329  * Field : nack
6330  *
6331  * Generate NACK.
6332  *
6333  * This NACK generation only occurs when DW_apb_i2c is a
6334  *
6335  * slave-receiver. If this register is set to a value of 1,
6336  *
6337  * it can only generate a NACK after a data byte is received;
6338  *
6339  * hence, the data transfer is aborted and the data received
6340  *
6341  * is not pushed to the receive buffer.
6342  *
6343  * When the register is set to a value of 0, it generates
6344  *
6345  * NACK/ACK, depending on normal criteria.
6346  *
6347  * 1 = generate NACK after data byte received
6348  *
6349  * 0 = generate NACK/ACK normally
6350  *
6351  * Reset value: 0x0
6352  *
6353  * Field Enumeration Values:
6354  *
6355  * Enum | Value | Description
6356  * :---------------------------------------------|:------|:--------------------------------------
6357  * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM | 0x0 | Generate NACK/ACK normally
6358  * ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE | 0x1 | Generate NACK after data byte receive
6359  *
6360  * Field Access Macros:
6361  *
6362  */
6363 /*
6364  * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK
6365  *
6366  * Generate NACK/ACK normally
6367  */
6368 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM 0x0
6369 /*
6370  * Enumerated value for register field ALT_I2C_SLV_DATA_NACK_ONLY_NACK
6371  *
6372  * Generate NACK after data byte receive
6373  */
6374 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE 0x1
6375 
6376 /* The Least Significant Bit (LSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */
6377 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_LSB 0
6378 /* The Most Significant Bit (MSB) position of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */
6379 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_MSB 0
6380 /* The width in bits of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */
6381 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_WIDTH 1
6382 /* The mask used to set the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */
6383 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001
6384 /* The mask used to clear the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value. */
6385 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe
6386 /* The reset value of the ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field. */
6387 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_RESET 0x0
6388 /* Extracts the ALT_I2C_SLV_DATA_NACK_ONLY_NACK field value from a register. */
6389 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0)
6390 /* Produces a ALT_I2C_SLV_DATA_NACK_ONLY_NACK register field value suitable for setting the register. */
6391 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001)
6392 
6393 #ifndef __ASSEMBLY__
6394 /*
6395  * WARNING: The C register and register group struct declarations are provided for
6396  * convenience and illustrative purposes. They should, however, be used with
6397  * caution as the C language standard provides no guarantees about the alignment or
6398  * atomicity of device memory accesses. The recommended practice for writing
6399  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6400  * alt_write_word() functions.
6401  *
6402  * The struct declaration for register ALT_I2C_SLV_DATA_NACK_ONLY.
6403  */
6404 struct ALT_I2C_SLV_DATA_NACK_ONLY_s
6405 {
6406  uint32_t nack : 1; /* ALT_I2C_SLV_DATA_NACK_ONLY_NACK */
6407  uint32_t : 31; /* *UNDEFINED* */
6408 };
6409 
6410 /* The typedef declaration for register ALT_I2C_SLV_DATA_NACK_ONLY. */
6411 typedef volatile struct ALT_I2C_SLV_DATA_NACK_ONLY_s ALT_I2C_SLV_DATA_NACK_ONLY_t;
6412 #endif /* __ASSEMBLY__ */
6413 
6414 /* The reset value of the ALT_I2C_SLV_DATA_NACK_ONLY register. */
6415 #define ALT_I2C_SLV_DATA_NACK_ONLY_RESET 0x00000000
6416 /* The byte offset of the ALT_I2C_SLV_DATA_NACK_ONLY register from the beginning of the component. */
6417 #define ALT_I2C_SLV_DATA_NACK_ONLY_OFST 0x84
6418 /* The address of the ALT_I2C_SLV_DATA_NACK_ONLY register. */
6419 #define ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SLV_DATA_NACK_ONLY_OFST))
6420 
6421 /*
6422  * Register : ic_dma_cr
6423  *
6424  * Name: DMA Control Register
6425  *
6426  * Size: 2 bits
6427  *
6428  * Address Offset: 0x88
6429  *
6430  * Read/Write Access: Read/Write
6431  *
6432  * This register is only valid when DW_apb_i2c is configured
6433  *
6434  * with a set of DMA Controller interface signals (IC_HAS_DMA = 1).
6435  *
6436  * When DW_apb_i2c is not configured for DMA operation, this register
6437  *
6438  * does not exist and writing to the register's address has no
6439  *
6440  * effect and reading from this register address will return zero.
6441  *
6442  * The register is used to enable the DMA Controller interface operation.
6443  *
6444  * There is a separate bit for transmit and receive. This can be programmed
6445  *
6446  * regardless of the state of IC_ENABLE.
6447  *
6448  * Register Layout
6449  *
6450  * Bits | Access | Reset | Description
6451  * :-------|:-------|:------|:------------------------------------
6452  * [0] | RW | 0x0 | ALT_I2C_DMA_CR_RDMAE
6453  * [1] | RW | 0x0 | ALT_I2C_DMA_CR_TDMAE
6454  * [31:2] | R | 0x0 | ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2
6455  *
6456  */
6457 /*
6458  * Field : rdmae
6459  *
6460  * Receive DMA Enable.
6461  *
6462  * This bit enables/disables the receive FIFO DMA
6463  *
6464  * channel.
6465  *
6466  * 0 = Receive DMA disabled
6467  *
6468  * 1 = Receive DMA enabled
6469  *
6470  * Reset value: 0x0
6471  *
6472  * Field Enumeration Values:
6473  *
6474  * Enum | Value | Description
6475  * :---------------------------|:------|:--------------------
6476  * ALT_I2C_DMA_CR_RDMAE_E_DIS | 0x0 | Receive DMA disable
6477  * ALT_I2C_DMA_CR_RDMAE_E_EN | 0x1 | Receive DMA enabled
6478  *
6479  * Field Access Macros:
6480  *
6481  */
6482 /*
6483  * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE
6484  *
6485  * Receive DMA disable
6486  */
6487 #define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0
6488 /*
6489  * Enumerated value for register field ALT_I2C_DMA_CR_RDMAE
6490  *
6491  * Receive DMA enabled
6492  */
6493 #define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1
6494 
6495 /* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */
6496 #define ALT_I2C_DMA_CR_RDMAE_LSB 0
6497 /* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_RDMAE register field. */
6498 #define ALT_I2C_DMA_CR_RDMAE_MSB 0
6499 /* The width in bits of the ALT_I2C_DMA_CR_RDMAE register field. */
6500 #define ALT_I2C_DMA_CR_RDMAE_WIDTH 1
6501 /* The mask used to set the ALT_I2C_DMA_CR_RDMAE register field value. */
6502 #define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001
6503 /* The mask used to clear the ALT_I2C_DMA_CR_RDMAE register field value. */
6504 #define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe
6505 /* The reset value of the ALT_I2C_DMA_CR_RDMAE register field. */
6506 #define ALT_I2C_DMA_CR_RDMAE_RESET 0x0
6507 /* Extracts the ALT_I2C_DMA_CR_RDMAE field value from a register. */
6508 #define ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
6509 /* Produces a ALT_I2C_DMA_CR_RDMAE register field value suitable for setting the register. */
6510 #define ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
6511 
6512 /*
6513  * Field : tdmae
6514  *
6515  * Transmit DMA Enable.
6516  *
6517  * //This bit enables/disables the transmit FIFO DMA
6518  *
6519  * channel.
6520  *
6521  * 0 = Transmit DMA disabled
6522  *
6523  * 1 = Transmit DMA enabled
6524  *
6525  * Reset value: 0x0
6526  *
6527  * Field Enumeration Values:
6528  *
6529  * Enum | Value | Description
6530  * :---------------------------|:------|:---------------------
6531  * ALT_I2C_DMA_CR_TDMAE_E_DIS | 0x0 | Transmit DMA disable
6532  * ALT_I2C_DMA_CR_TDMAE_E_EN | 0x1 | Transmit DMA enabled
6533  *
6534  * Field Access Macros:
6535  *
6536  */
6537 /*
6538  * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE
6539  *
6540  * Transmit DMA disable
6541  */
6542 #define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0
6543 /*
6544  * Enumerated value for register field ALT_I2C_DMA_CR_TDMAE
6545  *
6546  * Transmit DMA enabled
6547  */
6548 #define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1
6549 
6550 /* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */
6551 #define ALT_I2C_DMA_CR_TDMAE_LSB 1
6552 /* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_TDMAE register field. */
6553 #define ALT_I2C_DMA_CR_TDMAE_MSB 1
6554 /* The width in bits of the ALT_I2C_DMA_CR_TDMAE register field. */
6555 #define ALT_I2C_DMA_CR_TDMAE_WIDTH 1
6556 /* The mask used to set the ALT_I2C_DMA_CR_TDMAE register field value. */
6557 #define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002
6558 /* The mask used to clear the ALT_I2C_DMA_CR_TDMAE register field value. */
6559 #define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd
6560 /* The reset value of the ALT_I2C_DMA_CR_TDMAE register field. */
6561 #define ALT_I2C_DMA_CR_TDMAE_RESET 0x0
6562 /* Extracts the ALT_I2C_DMA_CR_TDMAE field value from a register. */
6563 #define ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
6564 /* Produces a ALT_I2C_DMA_CR_TDMAE register field value suitable for setting the register. */
6565 #define ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
6566 
6567 /*
6568  * Field : rsvd_ic_dma_cr_31to2
6569  *
6570  * Reserved bits [31:1] - Read Only
6571  *
6572  * Field Access Macros:
6573  *
6574  */
6575 /* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field. */
6576 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_LSB 2
6577 /* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field. */
6578 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_MSB 31
6579 /* The width in bits of the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field. */
6580 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_WIDTH 30
6581 /* The mask used to set the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field value. */
6582 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_SET_MSK 0xfffffffc
6583 /* The mask used to clear the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field value. */
6584 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_CLR_MSK 0x00000003
6585 /* The reset value of the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field. */
6586 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_RESET 0x0
6587 /* Extracts the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 field value from a register. */
6588 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_GET(value) (((value) & 0xfffffffc) >> 2)
6589 /* Produces a ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field value suitable for setting the register. */
6590 #define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_SET(value) (((value) << 2) & 0xfffffffc)
6591 
6592 #ifndef __ASSEMBLY__
6593 /*
6594  * WARNING: The C register and register group struct declarations are provided for
6595  * convenience and illustrative purposes. They should, however, be used with
6596  * caution as the C language standard provides no guarantees about the alignment or
6597  * atomicity of device memory accesses. The recommended practice for writing
6598  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6599  * alt_write_word() functions.
6600  *
6601  * The struct declaration for register ALT_I2C_DMA_CR.
6602  */
6603 struct ALT_I2C_DMA_CR_s
6604 {
6605  uint32_t rdmae : 1; /* ALT_I2C_DMA_CR_RDMAE */
6606  uint32_t tdmae : 1; /* ALT_I2C_DMA_CR_TDMAE */
6607  const uint32_t rsvd_ic_dma_cr_31to2 : 30; /* ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 */
6608 };
6609 
6610 /* The typedef declaration for register ALT_I2C_DMA_CR. */
6611 typedef volatile struct ALT_I2C_DMA_CR_s ALT_I2C_DMA_CR_t;
6612 #endif /* __ASSEMBLY__ */
6613 
6614 /* The reset value of the ALT_I2C_DMA_CR register. */
6615 #define ALT_I2C_DMA_CR_RESET 0x00000000
6616 /* The byte offset of the ALT_I2C_DMA_CR register from the beginning of the component. */
6617 #define ALT_I2C_DMA_CR_OFST 0x88
6618 /* The address of the ALT_I2C_DMA_CR register. */
6619 #define ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST))
6620 
6621 /*
6622  * Register : ic_dma_tdlr
6623  *
6624  * Name: DMA Transmit Data Level Register
6625  *
6626  * Size: log2(IC_TX_BUFFER_DEPTH) bits
6627  *
6628  * Address Offset: 0x8c
6629  *
6630  * Read/Write Access: Read/Write
6631  *
6632  * This register is only valid when the DW_apb_i2c
6633  *
6634  * is configured with a set of DMA interface signals
6635  *
6636  * (IC_HAS_DMA = 1). When DW_apb_i2c is not configured
6637  *
6638  * for DMA operation, this register does not exist;
6639  *
6640  * writing to its address has no effect; reading from
6641  *
6642  * its address returns zero.
6643  *
6644  * Register Layout
6645  *
6646  * Bits | Access | Reset | Description
6647  * :-------|:-------|:------|:------------------------
6648  * [5:0] | RW | 0x0 | ALT_I2C_DMA_TDLR_DMATDL
6649  * [31:6] | ??? | 0x0 | *UNDEFINED*
6650  *
6651  */
6652 /*
6653  * Field : dmatdl
6654  *
6655  * Transmit Data Level.
6656  *
6657  * This bit field controls the level at which a
6658  *
6659  * DMA request is made by the transmit logic. It
6660  *
6661  * is equal to the watermark level; that is, the
6662  *
6663  * dma_tx_req signal is generated when the number
6664  *
6665  * of valid data entries in the transmit FIFO is
6666  *
6667  * equal to or below this field value, and TDMAE = 1.
6668  *
6669  * Reset value: 0x0
6670  *
6671  * Field Access Macros:
6672  *
6673  */
6674 /* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */
6675 #define ALT_I2C_DMA_TDLR_DMATDL_LSB 0
6676 /* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_TDLR_DMATDL register field. */
6677 #define ALT_I2C_DMA_TDLR_DMATDL_MSB 5
6678 /* The width in bits of the ALT_I2C_DMA_TDLR_DMATDL register field. */
6679 #define ALT_I2C_DMA_TDLR_DMATDL_WIDTH 6
6680 /* The mask used to set the ALT_I2C_DMA_TDLR_DMATDL register field value. */
6681 #define ALT_I2C_DMA_TDLR_DMATDL_SET_MSK 0x0000003f
6682 /* The mask used to clear the ALT_I2C_DMA_TDLR_DMATDL register field value. */
6683 #define ALT_I2C_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0
6684 /* The reset value of the ALT_I2C_DMA_TDLR_DMATDL register field. */
6685 #define ALT_I2C_DMA_TDLR_DMATDL_RESET 0x0
6686 /* Extracts the ALT_I2C_DMA_TDLR_DMATDL field value from a register. */
6687 #define ALT_I2C_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0)
6688 /* Produces a ALT_I2C_DMA_TDLR_DMATDL register field value suitable for setting the register. */
6689 #define ALT_I2C_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f)
6690 
6691 #ifndef __ASSEMBLY__
6692 /*
6693  * WARNING: The C register and register group struct declarations are provided for
6694  * convenience and illustrative purposes. They should, however, be used with
6695  * caution as the C language standard provides no guarantees about the alignment or
6696  * atomicity of device memory accesses. The recommended practice for writing
6697  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6698  * alt_write_word() functions.
6699  *
6700  * The struct declaration for register ALT_I2C_DMA_TDLR.
6701  */
6702 struct ALT_I2C_DMA_TDLR_s
6703 {
6704  uint32_t dmatdl : 6; /* ALT_I2C_DMA_TDLR_DMATDL */
6705  uint32_t : 26; /* *UNDEFINED* */
6706 };
6707 
6708 /* The typedef declaration for register ALT_I2C_DMA_TDLR. */
6709 typedef volatile struct ALT_I2C_DMA_TDLR_s ALT_I2C_DMA_TDLR_t;
6710 #endif /* __ASSEMBLY__ */
6711 
6712 /* The reset value of the ALT_I2C_DMA_TDLR register. */
6713 #define ALT_I2C_DMA_TDLR_RESET 0x00000000
6714 /* The byte offset of the ALT_I2C_DMA_TDLR register from the beginning of the component. */
6715 #define ALT_I2C_DMA_TDLR_OFST 0x8c
6716 /* The address of the ALT_I2C_DMA_TDLR register. */
6717 #define ALT_I2C_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_TDLR_OFST))
6718 
6719 /*
6720  * Register : ic_dma_rdlr
6721  *
6722  * Name: I2C Receive Data Level Register
6723  *
6724  * Size: log2(IC_RX_BUFFER_DEPTH) bits
6725  *
6726  * Address Offset: 0x90
6727  *
6728  * Read/Write Access: Read/Write
6729  *
6730  * This register is only valid when DW_apb_i2c
6731  *
6732  * is configured with a set of DMA interface signals
6733  *
6734  * (IC_HAS_DMA = 1). When DW_apb_i2c is not configured
6735  *
6736  * for DMA operation, this register does not exist;
6737  *
6738  * writing to its address has no effect; reading from
6739  *
6740  * its address returns zero.
6741  *
6742  * Register Layout
6743  *
6744  * Bits | Access | Reset | Description
6745  * :-------|:-------|:------|:------------------------
6746  * [5:0] | RW | 0x0 | ALT_I2C_DMA_RDLR_DMARDL
6747  * [31:6] | ??? | 0x0 | *UNDEFINED*
6748  *
6749  */
6750 /*
6751  * Field : dmardl
6752  *
6753  * Receive Data Level.
6754  *
6755  * This bit field controls the level at which a DMA
6756  *
6757  * request is made by the receive logic. The watermark level =
6758  *
6759  * DMARDL+1; that is, dma_rx_req is generated when the number
6760  *
6761  * of valid data entries in the receive FIFO is equal to or more
6762  *
6763  * than this field value + 1, and RDMAE =1. For instance, when
6764  *
6765  * DMARDL is 0, then dma_rx_req is asserted when 1 or more data
6766  *
6767  * entries are present in the receive FIFO.
6768  *
6769  * Reset value: 0x0
6770  *
6771  * Field Access Macros:
6772  *
6773  */
6774 /* The Least Significant Bit (LSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */
6775 #define ALT_I2C_DMA_RDLR_DMARDL_LSB 0
6776 /* The Most Significant Bit (MSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field. */
6777 #define ALT_I2C_DMA_RDLR_DMARDL_MSB 5
6778 /* The width in bits of the ALT_I2C_DMA_RDLR_DMARDL register field. */
6779 #define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6
6780 /* The mask used to set the ALT_I2C_DMA_RDLR_DMARDL register field value. */
6781 #define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f
6782 /* The mask used to clear the ALT_I2C_DMA_RDLR_DMARDL register field value. */
6783 #define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0
6784 /* The reset value of the ALT_I2C_DMA_RDLR_DMARDL register field. */
6785 #define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0
6786 /* Extracts the ALT_I2C_DMA_RDLR_DMARDL field value from a register. */
6787 #define ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0)
6788 /* Produces a ALT_I2C_DMA_RDLR_DMARDL register field value suitable for setting the register. */
6789 #define ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f)
6790 
6791 #ifndef __ASSEMBLY__
6792 /*
6793  * WARNING: The C register and register group struct declarations are provided for
6794  * convenience and illustrative purposes. They should, however, be used with
6795  * caution as the C language standard provides no guarantees about the alignment or
6796  * atomicity of device memory accesses. The recommended practice for writing
6797  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6798  * alt_write_word() functions.
6799  *
6800  * The struct declaration for register ALT_I2C_DMA_RDLR.
6801  */
6802 struct ALT_I2C_DMA_RDLR_s
6803 {
6804  uint32_t dmardl : 6; /* ALT_I2C_DMA_RDLR_DMARDL */
6805  uint32_t : 26; /* *UNDEFINED* */
6806 };
6807 
6808 /* The typedef declaration for register ALT_I2C_DMA_RDLR. */
6809 typedef volatile struct ALT_I2C_DMA_RDLR_s ALT_I2C_DMA_RDLR_t;
6810 #endif /* __ASSEMBLY__ */
6811 
6812 /* The reset value of the ALT_I2C_DMA_RDLR register. */
6813 #define ALT_I2C_DMA_RDLR_RESET 0x00000000
6814 /* The byte offset of the ALT_I2C_DMA_RDLR register from the beginning of the component. */
6815 #define ALT_I2C_DMA_RDLR_OFST 0x90
6816 /* The address of the ALT_I2C_DMA_RDLR register. */
6817 #define ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST))
6818 
6819 /*
6820  * Register : ic_sda_setup
6821  *
6822  * Name: I2C SDA Setup Register
6823  *
6824  * Size: 8 bits
6825  *
6826  * Address Offset: 0x94
6827  *
6828  * Read/Write Access: Read/Write
6829  *
6830  * This register controls the amount of time delay
6831  *
6832  * (in terms of number of ic_clk clock periods) introduced
6833  *
6834  * in the rising edge of SCL, relative to SDA changing, when
6835  *
6836  * DW_apb_i2c services a read request in a slave-transmitter operation.
6837  *
6838  * The relevant I2C requirement is tSU:DAT (note 4) as detailed in the
6839  *
6840  * I2C Bus Specification.
6841  *
6842  * Register Layout
6843  *
6844  * Bits | Access | Reset | Description
6845  * :-------|:-------|:------|:----------------------------
6846  * [7:0] | RW | 0x64 | ALT_I2C_SDA_SETUP_SDA_SETUP
6847  * [31:8] | ??? | 0x0 | *UNDEFINED*
6848  *
6849  */
6850 /*
6851  * Field : sda_setup
6852  *
6853  * SDA Setup.
6854  *
6855  * It is recommended that if the required delay is 1000ns,
6856  *
6857  * then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP
6858  *
6859  * should be programmed to a value of 11.
6860  *
6861  * Default Reset value: 0x64, but can be hardcoded by setting
6862  *
6863  * the IC_DEFAULT_SDA_SETUP configuration parameter.
6864  *
6865  * Field Access Macros:
6866  *
6867  */
6868 /* The Least Significant Bit (LSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */
6869 #define ALT_I2C_SDA_SETUP_SDA_SETUP_LSB 0
6870 /* The Most Significant Bit (MSB) position of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */
6871 #define ALT_I2C_SDA_SETUP_SDA_SETUP_MSB 7
6872 /* The width in bits of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */
6873 #define ALT_I2C_SDA_SETUP_SDA_SETUP_WIDTH 8
6874 /* The mask used to set the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */
6875 #define ALT_I2C_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff
6876 /* The mask used to clear the ALT_I2C_SDA_SETUP_SDA_SETUP register field value. */
6877 #define ALT_I2C_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00
6878 /* The reset value of the ALT_I2C_SDA_SETUP_SDA_SETUP register field. */
6879 #define ALT_I2C_SDA_SETUP_SDA_SETUP_RESET 0x64
6880 /* Extracts the ALT_I2C_SDA_SETUP_SDA_SETUP field value from a register. */
6881 #define ALT_I2C_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0)
6882 /* Produces a ALT_I2C_SDA_SETUP_SDA_SETUP register field value suitable for setting the register. */
6883 #define ALT_I2C_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff)
6884 
6885 #ifndef __ASSEMBLY__
6886 /*
6887  * WARNING: The C register and register group struct declarations are provided for
6888  * convenience and illustrative purposes. They should, however, be used with
6889  * caution as the C language standard provides no guarantees about the alignment or
6890  * atomicity of device memory accesses. The recommended practice for writing
6891  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6892  * alt_write_word() functions.
6893  *
6894  * The struct declaration for register ALT_I2C_SDA_SETUP.
6895  */
6896 struct ALT_I2C_SDA_SETUP_s
6897 {
6898  uint32_t sda_setup : 8; /* ALT_I2C_SDA_SETUP_SDA_SETUP */
6899  uint32_t : 24; /* *UNDEFINED* */
6900 };
6901 
6902 /* The typedef declaration for register ALT_I2C_SDA_SETUP. */
6903 typedef volatile struct ALT_I2C_SDA_SETUP_s ALT_I2C_SDA_SETUP_t;
6904 #endif /* __ASSEMBLY__ */
6905 
6906 /* The reset value of the ALT_I2C_SDA_SETUP register. */
6907 #define ALT_I2C_SDA_SETUP_RESET 0x00000064
6908 /* The byte offset of the ALT_I2C_SDA_SETUP register from the beginning of the component. */
6909 #define ALT_I2C_SDA_SETUP_OFST 0x94
6910 /* The address of the ALT_I2C_SDA_SETUP register. */
6911 #define ALT_I2C_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_SETUP_OFST))
6912 
6913 /*
6914  * Register : ic_ack_general_call
6915  *
6916  * Name: I2C ACK General Call Register
6917  *
6918  * Size: 1 bit
6919  *
6920  * Address Offset: 0x98
6921  *
6922  * Read/Write Access: Read/Write
6923  *
6924  * The register controls whether DW_apb_i2c responds
6925  *
6926  * with a ACK or NACK when it receives an I2C
6927  *
6928  * General Call address.
6929  *
6930  * Note :This register is applicable only when the DW_apb_i2c is in slave mode
6931  *
6932  * Register Layout
6933  *
6934  * Bits | Access | Reset | Description
6935  * :-------|:-------|:------|:-----------------------------------------------
6936  * [0] | RW | 0x1 | ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL
6937  * [31:1] | R | 0x0 | ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1
6938  *
6939  */
6940 /*
6941  * Field : ack_gen_call
6942  *
6943  * ACK General Call.
6944  *
6945  * When set to 1, DW_apb_i2c responds with a ACK
6946  *
6947  * (by asserting ic_data_oe) when it receives a General Call.
6948  *
6949  * Otherwise, DW_apb_i2c responds with a NACK
6950  *
6951  * (by negating ic_data_oe).
6952  *
6953  * Default Reset value: 0x1, but can be hardcoded by setting the
6954  *
6955  * IC_DEFAULT_ACK_GENERAL_CALL configuration parameter.
6956  *
6957  * Field Enumeration Values:
6958  *
6959  * Enum | Value | Description
6960  * :---------------------------------------------|:------|:-------------------------
6961  * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK | 0x0 | I2C responds with a NACK
6962  * ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK | 0x1 | I2C responds with an ACK
6963  *
6964  * Field Access Macros:
6965  *
6966  */
6967 /*
6968  * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL
6969  *
6970  * I2C responds with a NACK
6971  */
6972 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK 0x0
6973 /*
6974  * Enumerated value for register field ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL
6975  *
6976  * I2C responds with an ACK
6977  */
6978 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK 0x1
6979 
6980 /* The Least Significant Bit (LSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
6981 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0
6982 /* The Most Significant Bit (MSB) position of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
6983 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0
6984 /* The width in bits of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
6985 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1
6986 /* The mask used to set the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */
6987 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001
6988 /* The mask used to clear the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value. */
6989 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe
6990 /* The reset value of the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field. */
6991 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1
6992 /* Extracts the ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL field value from a register. */
6993 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
6994 /* Produces a ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL register field value suitable for setting the register. */
6995 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
6996 
6997 /*
6998  * Field : rsvd_ic_ack_gen_31to1
6999  *
7000  * Reserved bits [31:1] - Read Only
7001  *
7002  * Field Access Macros:
7003  *
7004  */
7005 /* The Least Significant Bit (LSB) position of the ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1 register field. */
7006 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_LSB 1
7007 /* The Most Significant Bit (MSB) position of the ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1 register field. */
7008 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_MSB 31
7009 /* The width in bits of the ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1 register field. */
7010 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_WIDTH 31
7011 /* The mask used to set the ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1 register field value. */
7012 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_SET_MSK 0xfffffffe
7013 /* The mask used to clear the ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1 register field value. */
7014 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_CLR_MSK 0x00000001
7015 /* The reset value of the ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1 register field. */
7016 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_RESET 0x0
7017 /* Extracts the ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1 field value from a register. */
7018 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
7019 /* Produces a ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1 register field value suitable for setting the register. */
7020 #define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
7021 
7022 #ifndef __ASSEMBLY__
7023 /*
7024  * WARNING: The C register and register group struct declarations are provided for
7025  * convenience and illustrative purposes. They should, however, be used with
7026  * caution as the C language standard provides no guarantees about the alignment or
7027  * atomicity of device memory accesses. The recommended practice for writing
7028  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7029  * alt_write_word() functions.
7030  *
7031  * The struct declaration for register ALT_I2C_ACK_GENERAL_CALL.
7032  */
7033 struct ALT_I2C_ACK_GENERAL_CALL_s
7034 {
7035  uint32_t ack_gen_call : 1; /* ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL */
7036  const uint32_t rsvd_ic_ack_gen_31to1 : 31; /* ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1 */
7037 };
7038 
7039 /* The typedef declaration for register ALT_I2C_ACK_GENERAL_CALL. */
7040 typedef volatile struct ALT_I2C_ACK_GENERAL_CALL_s ALT_I2C_ACK_GENERAL_CALL_t;
7041 #endif /* __ASSEMBLY__ */
7042 
7043 /* The reset value of the ALT_I2C_ACK_GENERAL_CALL register. */
7044 #define ALT_I2C_ACK_GENERAL_CALL_RESET 0x00000001
7045 /* The byte offset of the ALT_I2C_ACK_GENERAL_CALL register from the beginning of the component. */
7046 #define ALT_I2C_ACK_GENERAL_CALL_OFST 0x98
7047 /* The address of the ALT_I2C_ACK_GENERAL_CALL register. */
7048 #define ALT_I2C_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_ACK_GENERAL_CALL_OFST))
7049 
7050 /*
7051  * Register : ic_enable_status
7052  *
7053  * Name: I2C Enable Status Register
7054  *
7055  * Size: 3 bits
7056  *
7057  * Address Offset: 0x9C
7058  *
7059  * Read/Write Access: Read
7060  *
7061  * The register is used to report the DW_apb_i2c hardware
7062  *
7063  * status when the IC_ENABLE[0] register is set from 1 to 0;
7064  *
7065  * that is, when DW_apb_i2c is disabled.
7066  *
7067  * If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0,
7068  *
7069  * and bit 0 is forced to 1.
7070  *
7071  * If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid
7072  *
7073  * as soon as bit 0 is read as '0'.
7074  *
7075  * Note
7076  *
7077  * When IC_ENABLE[0] has been written with '0'a delay occurs for
7078  *
7079  * bit 0 to be read as '0' because disabling the DW_apb_i2c
7080  *
7081  * depends on I2C bus activities.
7082  *
7083  * Register Layout
7084  *
7085  * Bits | Access | Reset | Description
7086  * :-------|:-------|:------|:------------------------------------
7087  * [0] | R | 0x0 | ALT_I2C_EN_STAT_IC_EN
7088  * [1] | R | 0x0 | ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY
7089  * [2] | R | 0x0 | ALT_I2C_EN_STAT_SLV_RX_DATA_LOST
7090  * [31:3] | ??? | 0x0 | *UNDEFINED*
7091  *
7092  */
7093 /*
7094  * Field : ic_en
7095  *
7096  * ic_en Status.
7097  *
7098  * This bit always reflects the value driven
7099  *
7100  * on the output port ic_en.
7101  *
7102  * When read as 1, DW_apb_i2c is deemed to be in
7103  *
7104  * an enabled state.
7105  *
7106  * When read as 0, DW_apb_i2c is deemed completely
7107  *
7108  * inactive.
7109  *
7110  * NOTE: The CPU can safely read this bit anytime.
7111  *
7112  * When this bit is read as 0, the CPU can safely
7113  *
7114  * read SLV_RX_DATA_LOST (bit 2) and
7115  *
7116  * SLV_DISABLED_WHILE_BUSY (bit 1).
7117  *
7118  * Reset value: 0x0
7119  *
7120  * Field Access Macros:
7121  *
7122  */
7123 /* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */
7124 #define ALT_I2C_EN_STAT_IC_EN_LSB 0
7125 /* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_IC_EN register field. */
7126 #define ALT_I2C_EN_STAT_IC_EN_MSB 0
7127 /* The width in bits of the ALT_I2C_EN_STAT_IC_EN register field. */
7128 #define ALT_I2C_EN_STAT_IC_EN_WIDTH 1
7129 /* The mask used to set the ALT_I2C_EN_STAT_IC_EN register field value. */
7130 #define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001
7131 /* The mask used to clear the ALT_I2C_EN_STAT_IC_EN register field value. */
7132 #define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe
7133 /* The reset value of the ALT_I2C_EN_STAT_IC_EN register field. */
7134 #define ALT_I2C_EN_STAT_IC_EN_RESET 0x0
7135 /* Extracts the ALT_I2C_EN_STAT_IC_EN field value from a register. */
7136 #define ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0)
7137 /* Produces a ALT_I2C_EN_STAT_IC_EN register field value suitable for setting the register. */
7138 #define ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001)
7139 
7140 /*
7141  * Field : slv_disabled_while_busy
7142  *
7143  * Slave Disabled While Busy (Transmit, Receive).
7144  *
7145  * This bit indicates if a potential or active Slave
7146  *
7147  * operation has been aborted due to the setting bit 0 of
7148  *
7149  * the IC_ENABLE register from 1 to 0. This bit is set
7150  *
7151  * when the CPU writes a 0 to the IC_ENABLE register
7152  *
7153  * while: (a) DW_apb_i2c is receiving the address byte
7154  *
7155  * of the Slave-Transmitter operation from a remote master;
7156  *
7157  * OR, (b) address and data bytes of the Slave-Receiver
7158  *
7159  * operation from a remote master.
7160  *
7161  * When read as 1, DW_apb_i2c is deemed to have forced a
7162  *
7163  * NACK during any part of an I2C transfer, irrespective
7164  *
7165  * of whether the I2C address matches the slave address set
7166  *
7167  * in DW_apb_i2c (IC_SAR register) OR if the transfer is
7168  *
7169  * completed before IC_ENABLE is set to 0 but has not
7170  *
7171  * taken effect.
7172  *
7173  * NOTE: If the remote I2C master terminates the transfer
7174  *
7175  * with a STOP condition before the DW_apb_i2c has a chance
7176  *
7177  * to NACK a transfer, and IC_ENABLE[0] has been set to 0, then
7178  *
7179  * this bit will also be set to 1.
7180  *
7181  * When read as 0, DW_apb_i2c is deemed to have been disabled
7182  *
7183  * when there is master activity, or when the I2C bus is idle.
7184  *
7185  * NOTE: The CPU can safely read this bit when IC_EN (bit 0)
7186  *
7187  * is read as 0.
7188  *
7189  * Reset value: 0x0
7190  *
7191  * Field Access Macros:
7192  *
7193  */
7194 /* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */
7195 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1
7196 /* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */
7197 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1
7198 /* The width in bits of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */
7199 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1
7200 /* The mask used to set the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */
7201 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002
7202 /* The mask used to clear the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value. */
7203 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd
7204 /* The reset value of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field. */
7205 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0
7206 /* Extracts the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY field value from a register. */
7207 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1)
7208 /* Produces a ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value suitable for setting the register. */
7209 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002)
7210 
7211 /*
7212  * Field : slv_rx_data_lost
7213  *
7214  * Slave Received Data Lost.
7215  *
7216  * This bit indicates if a Slave-Receiver operation has been
7217  *
7218  * aborted with at least one data byte received from an
7219  *
7220  * I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0.
7221  *
7222  * When read as 1, DW_apb_i2c is deemed to have been actively engaged
7223  *
7224  * in an aborted I2C transfer (with matching address) and the
7225  *
7226  * data phase of the I2C transfer has been entered, even though
7227  *
7228  * a data byte has been responded with a NACK.
7229  *
7230  * NOTE: If the remote I2C master terminates the transfer with a
7231  *
7232  * STOP condition before the DW_apb_i2c has a chance to NACK a
7233  *
7234  * transfer, and IC_ENABLE[0] has been set to 0, then this bit is
7235  *
7236  * also set to 1.
7237  *
7238  * When read as 0, DW_apb_i2c is deemed to have been disabled without
7239  *
7240  * being actively involved in the data phase of a Slave-Receiver transfer.
7241  *
7242  * NOTE: The CPU can safely read this bit when IC_EN (bit 0) is
7243  *
7244  * read as 0.
7245  *
7246  * Reset value: 0x0
7247  *
7248  * Field Access Macros:
7249  *
7250  */
7251 /* The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */
7252 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2
7253 /* The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */
7254 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2
7255 /* The width in bits of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */
7256 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1
7257 /* The mask used to set the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */
7258 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004
7259 /* The mask used to clear the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value. */
7260 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb
7261 /* The reset value of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field. */
7262 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0
7263 /* Extracts the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST field value from a register. */
7264 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2)
7265 /* Produces a ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value suitable for setting the register. */
7266 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004)
7267 
7268 #ifndef __ASSEMBLY__
7269 /*
7270  * WARNING: The C register and register group struct declarations are provided for
7271  * convenience and illustrative purposes. They should, however, be used with
7272  * caution as the C language standard provides no guarantees about the alignment or
7273  * atomicity of device memory accesses. The recommended practice for writing
7274  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7275  * alt_write_word() functions.
7276  *
7277  * The struct declaration for register ALT_I2C_EN_STAT.
7278  */
7279 struct ALT_I2C_EN_STAT_s
7280 {
7281  const uint32_t ic_en : 1; /* ALT_I2C_EN_STAT_IC_EN */
7282  const uint32_t slv_disabled_while_busy : 1; /* ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY */
7283  const uint32_t slv_rx_data_lost : 1; /* ALT_I2C_EN_STAT_SLV_RX_DATA_LOST */
7284  uint32_t : 29; /* *UNDEFINED* */
7285 };
7286 
7287 /* The typedef declaration for register ALT_I2C_EN_STAT. */
7288 typedef volatile struct ALT_I2C_EN_STAT_s ALT_I2C_EN_STAT_t;
7289 #endif /* __ASSEMBLY__ */
7290 
7291 /* The reset value of the ALT_I2C_EN_STAT register. */
7292 #define ALT_I2C_EN_STAT_RESET 0x00000000
7293 /* The byte offset of the ALT_I2C_EN_STAT register from the beginning of the component. */
7294 #define ALT_I2C_EN_STAT_OFST 0x9c
7295 /* The address of the ALT_I2C_EN_STAT register. */
7296 #define ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST))
7297 
7298 /*
7299  * Register : ic_fs_spklen
7300  *
7301  * Name: I2C SS, FS or FM+ spike suppression limit
7302  *
7303  * Size: 8 bits
7304  *
7305  * Address: 0xA0
7306  *
7307  * Read/Write Access: Read/Write
7308  *
7309  * This register is used to store the duration, measured in ic_clk cycles,
7310  *
7311  * of the longest spike that is filtered out by the spike suppression logic w
7312  *
7313  * hen the component is operating in SS, FS or FM+ modes.
7314  *
7315  * The relevant I2C requirement is tSP (table 4) as detailed in the
7316  *
7317  * I2C Bus Specification. This register must be programmed with a minimum value of
7318  * 1.
7319  *
7320  * Register Layout
7321  *
7322  * Bits | Access | Reset | Description
7323  * :-------|:-------|:------|:-------------------------------
7324  * [7:0] | RW | 0x2 | ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN
7325  * [31:8] | ??? | 0x0 | *UNDEFINED*
7326  *
7327  */
7328 /*
7329  * Field : ic_fs_spklen
7330  *
7331  * This register must be set before any I2C bus transaction can take place to
7332  *
7333  * ensure stable operation. This register sets the duration, measured in ic_clk
7334  * cycles,
7335  *
7336  * of the longest spike in the SCL or SDA lines that will be filtered out by the
7337  * spike
7338  *
7339  * suppression logic.
7340  *
7341  * This register can be written only when the I2C interface is disabled which
7342  *
7343  * corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times
7344  *
7345  * have no effect.
7346  *
7347  * The minimum valid value is 1; hardware prevents values less than this being
7348  *
7349  * written, and if attempted results in 1 being set.
7350  *
7351  * Default Reset value: IC_DEFAULT_FS_SPKLEN configuration parameter.
7352  *
7353  * Field Access Macros:
7354  *
7355  */
7356 /* The Least Significant Bit (LSB) position of the ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN register field. */
7357 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_LSB 0
7358 /* The Most Significant Bit (MSB) position of the ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN register field. */
7359 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_MSB 7
7360 /* The width in bits of the ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN register field. */
7361 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_WIDTH 8
7362 /* The mask used to set the ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN register field value. */
7363 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_SET_MSK 0x000000ff
7364 /* The mask used to clear the ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN register field value. */
7365 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_CLR_MSK 0xffffff00
7366 /* The reset value of the ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN register field. */
7367 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_RESET 0x2
7368 /* Extracts the ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN field value from a register. */
7369 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0)
7370 /* Produces a ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN register field value suitable for setting the register. */
7371 #define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_SET(value) (((value) << 0) & 0x000000ff)
7372 
7373 #ifndef __ASSEMBLY__
7374 /*
7375  * WARNING: The C register and register group struct declarations are provided for
7376  * convenience and illustrative purposes. They should, however, be used with
7377  * caution as the C language standard provides no guarantees about the alignment or
7378  * atomicity of device memory accesses. The recommended practice for writing
7379  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7380  * alt_write_word() functions.
7381  *
7382  * The struct declaration for register ALT_I2C_FS_SPKLEN.
7383  */
7384 struct ALT_I2C_FS_SPKLEN_s
7385 {
7386  uint32_t ic_fs_spklen : 8; /* ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN */
7387  uint32_t : 24; /* *UNDEFINED* */
7388 };
7389 
7390 /* The typedef declaration for register ALT_I2C_FS_SPKLEN. */
7391 typedef volatile struct ALT_I2C_FS_SPKLEN_s ALT_I2C_FS_SPKLEN_t;
7392 #endif /* __ASSEMBLY__ */
7393 
7394 /* The reset value of the ALT_I2C_FS_SPKLEN register. */
7395 #define ALT_I2C_FS_SPKLEN_RESET 0x00000002
7396 /* The byte offset of the ALT_I2C_FS_SPKLEN register from the beginning of the component. */
7397 #define ALT_I2C_FS_SPKLEN_OFST 0xa0
7398 /* The address of the ALT_I2C_FS_SPKLEN register. */
7399 #define ALT_I2C_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SPKLEN_OFST))
7400 
7401 /*
7402  * Register : ic_clr_restart_det
7403  *
7404  * Name: Clear RESTART_DET Interrupt Register
7405  *
7406  * Size: 1 bit
7407  *
7408  * Address Offset: 0xA8
7409  *
7410  * Read/Write Access: Read
7411  *
7412  * Register Layout
7413  *
7414  * Bits | Access | Reset | Description
7415  * :-------|:-------|:------|:----------------------------------------
7416  * [0] | R | 0x0 | ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET
7417  * [31:1] | ??? | 0x0 | *UNDEFINED*
7418  *
7419  */
7420 /*
7421  * Field : clr_restart_det
7422  *
7423  * Read this register to clear the RESTART_DET
7424  *
7425  * interrupt (bit 12) of IC_RAW_INTR_STAT register.
7426  *
7427  * Reset value: 0x0
7428  *
7429  * Field Access Macros:
7430  *
7431  */
7432 /* The Least Significant Bit (LSB) position of the ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET register field. */
7433 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_LSB 0
7434 /* The Most Significant Bit (MSB) position of the ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET register field. */
7435 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_MSB 0
7436 /* The width in bits of the ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET register field. */
7437 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_WIDTH 1
7438 /* The mask used to set the ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET register field value. */
7439 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_SET_MSK 0x00000001
7440 /* The mask used to clear the ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET register field value. */
7441 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_CLR_MSK 0xfffffffe
7442 /* The reset value of the ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET register field. */
7443 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_RESET 0x0
7444 /* Extracts the ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET field value from a register. */
7445 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_GET(value) (((value) & 0x00000001) >> 0)
7446 /* Produces a ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET register field value suitable for setting the register. */
7447 #define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_SET(value) (((value) << 0) & 0x00000001)
7448 
7449 #ifndef __ASSEMBLY__
7450 /*
7451  * WARNING: The C register and register group struct declarations are provided for
7452  * convenience and illustrative purposes. They should, however, be used with
7453  * caution as the C language standard provides no guarantees about the alignment or
7454  * atomicity of device memory accesses. The recommended practice for writing
7455  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7456  * alt_write_word() functions.
7457  *
7458  * The struct declaration for register ALT_I2C_CLR_RESTART_DET.
7459  */
7460 struct ALT_I2C_CLR_RESTART_DET_s
7461 {
7462  const uint32_t clr_restart_det : 1; /* ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET */
7463  uint32_t : 31; /* *UNDEFINED* */
7464 };
7465 
7466 /* The typedef declaration for register ALT_I2C_CLR_RESTART_DET. */
7467 typedef volatile struct ALT_I2C_CLR_RESTART_DET_s ALT_I2C_CLR_RESTART_DET_t;
7468 #endif /* __ASSEMBLY__ */
7469 
7470 /* The reset value of the ALT_I2C_CLR_RESTART_DET register. */
7471 #define ALT_I2C_CLR_RESTART_DET_RESET 0x00000000
7472 /* The byte offset of the ALT_I2C_CLR_RESTART_DET register from the beginning of the component. */
7473 #define ALT_I2C_CLR_RESTART_DET_OFST 0xa8
7474 /* The address of the ALT_I2C_CLR_RESTART_DET register. */
7475 #define ALT_I2C_CLR_RESTART_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RESTART_DET_OFST))
7476 
7477 /*
7478  * Register : ic_comp_param_1
7479  *
7480  * Name: Component Parameter Register 1
7481  *
7482  * Size: 32 bits
7483  *
7484  * Address Offset: 0xf4
7485  *
7486  * Read/Write Access: Read
7487  *
7488  * Note
7489  *
7490  * This is a constant read-only register that contains
7491  *
7492  * encoded information about the component's parameter settings.
7493  *
7494  * The reset value depends on coreConsultant parameter(s).
7495  *
7496  * Register Layout
7497  *
7498  * Bits | Access | Reset | Description
7499  * :--------|:-------|:------|:-------------------------------------
7500  * [1:0] | R | 0x2 | ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH
7501  * [3:2] | R | 0x2 | ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD
7502  * [4] | R | 0x0 | ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES
7503  * [5] | R | 0x1 | ALT_I2C_COMP_PARAM_1_INTR_IO
7504  * [6] | R | 0x1 | ALT_I2C_COMP_PARAM_1_HAS_DMA
7505  * [7] | R | 0x1 | ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS
7506  * [15:8] | R | 0x3f | ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH
7507  * [23:16] | R | 0x3f | ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH
7508  * [31:24] | ??? | 0x0 | *UNDEFINED*
7509  *
7510  */
7511 /*
7512  * Field : apb_data_width
7513  *
7514  * The value of this register is
7515  *
7516  * derived from the APB_DATA_WIDTH coreConsultant
7517  *
7518  * parameter.
7519  *
7520  * 0x0: 8 bits
7521  *
7522  * 0x1: 16 bits
7523  *
7524  * 0x2: 32 bits
7525  *
7526  * 0x3: Reserved
7527  *
7528  * Field Enumeration Values:
7529  *
7530  * Enum | Value | Description
7531  * :--------------------------------------------------|:------|:--------------------------
7532  * ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width is 32 Bits
7533  *
7534  * Field Access Macros:
7535  *
7536  */
7537 /*
7538  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH
7539  *
7540  * APB Data Width is 32 Bits
7541  */
7542 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2
7543 
7544 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */
7545 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0
7546 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */
7547 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1
7548 /* The width in bits of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */
7549 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2
7550 /* The mask used to set the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */
7551 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003
7552 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value. */
7553 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
7554 /* The reset value of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field. */
7555 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2
7556 /* Extracts the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH field value from a register. */
7557 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
7558 /* Produces a ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value suitable for setting the register. */
7559 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
7560 
7561 /*
7562  * Field : max_speed_mode
7563  *
7564  * The value of this register is
7565  *
7566  * derived from the IC_MAX_SPEED_MODE coreConsultant
7567  *
7568  * parameter.
7569  *
7570  * 0x0: Reserved
7571  *
7572  * 0x1: Standard
7573  *
7574  * 0x2: Fast
7575  *
7576  * 0x3: High
7577  *
7578  * Field Enumeration Values:
7579  *
7580  * Enum | Value | Description
7581  * :------------------------------------------|:------|:-----------------------
7582  * ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST | 0x2 | Fast Mode (400 kbit/s)
7583  *
7584  * Field Access Macros:
7585  *
7586  */
7587 /*
7588  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD
7589  *
7590  * Fast Mode (400 kbit/s)
7591  */
7592 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2
7593 
7594 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */
7595 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB 2
7596 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */
7597 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB 3
7598 /* The width in bits of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */
7599 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH 2
7600 /* The mask used to set the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */
7601 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK 0x0000000c
7602 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value. */
7603 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK 0xfffffff3
7604 /* The reset value of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field. */
7605 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET 0x2
7606 /* Extracts the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD field value from a register. */
7607 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value) (((value) & 0x0000000c) >> 2)
7608 /* Produces a ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value suitable for setting the register. */
7609 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value) (((value) << 2) & 0x0000000c)
7610 
7611 /*
7612  * Field : hc_count_values
7613  *
7614  * The value of this register is
7615  *
7616  * derived from the IC_HC_COUNT VALUES coreConsultant
7617  *
7618  * parameter
7619  *
7620  * 0: False
7621  *
7622  * 1: True
7623  *
7624  * Field Enumeration Values:
7625  *
7626  * Enum | Value | Description
7627  * :--------------------------------------------|:------|:--------------------------
7628  * ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR | 0x0 | *CNT registers read/write
7629  *
7630  * Field Access Macros:
7631  *
7632  */
7633 /*
7634  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES
7635  *
7636  * * CNT registers read/write
7637  */
7638 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0
7639 
7640 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */
7641 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4
7642 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */
7643 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4
7644 /* The width in bits of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */
7645 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1
7646 /* The mask used to set the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */
7647 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010
7648 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value. */
7649 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef
7650 /* The reset value of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field. */
7651 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0
7652 /* Extracts the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES field value from a register. */
7653 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4)
7654 /* Produces a ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value suitable for setting the register. */
7655 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010)
7656 
7657 /*
7658  * Field : intr_io
7659  *
7660  * The value of this register is
7661  *
7662  * derived from the IC_INTR_IO coreConsultant
7663  *
7664  * parameter
7665  *
7666  * 0: Individual
7667  *
7668  * 1: Combined
7669  *
7670  * Field Enumeration Values:
7671  *
7672  * Enum | Value | Description
7673  * :----------------------------------------|:------|:--------------------------
7674  * ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED | 0x1 | Combined Interrupt Output
7675  *
7676  * Field Access Macros:
7677  *
7678  */
7679 /*
7680  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_INTR_IO
7681  *
7682  * Combined Interrupt Output
7683  */
7684 #define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1
7685 
7686 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */
7687 #define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB 5
7688 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */
7689 #define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB 5
7690 /* The width in bits of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */
7691 #define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH 1
7692 /* The mask used to set the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */
7693 #define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020
7694 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_INTR_IO register field value. */
7695 #define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf
7696 /* The reset value of the ALT_I2C_COMP_PARAM_1_INTR_IO register field. */
7697 #define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET 0x1
7698 /* Extracts the ALT_I2C_COMP_PARAM_1_INTR_IO field value from a register. */
7699 #define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5)
7700 /* Produces a ALT_I2C_COMP_PARAM_1_INTR_IO register field value suitable for setting the register. */
7701 #define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020)
7702 
7703 /*
7704  * Field : has_dma
7705  *
7706  * The value of this register is
7707  *
7708  * derived from the IC_HAS_DMA coreConsultant
7709  *
7710  * parameter
7711  *
7712  * 0: False
7713  *
7714  * 1: True
7715  *
7716  * Field Enumeration Values:
7717  *
7718  * Enum | Value | Description
7719  * :---------------------------------------|:------|:------------
7720  * ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT | 0x1 | Has DMA
7721  *
7722  * Field Access Macros:
7723  *
7724  */
7725 /*
7726  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_HAS_DMA
7727  *
7728  * Has DMA
7729  */
7730 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1
7731 
7732 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */
7733 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB 6
7734 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */
7735 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB 6
7736 /* The width in bits of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */
7737 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH 1
7738 /* The mask used to set the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */
7739 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040
7740 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value. */
7741 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf
7742 /* The reset value of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field. */
7743 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET 0x1
7744 /* Extracts the ALT_I2C_COMP_PARAM_1_HAS_DMA field value from a register. */
7745 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6)
7746 /* Produces a ALT_I2C_COMP_PARAM_1_HAS_DMA register field value suitable for setting the register. */
7747 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040)
7748 
7749 /*
7750  * Field : add_encoded_params
7751  *
7752  * The value of this register is derived
7753  *
7754  * from the IC_ADD_ENCODED_PARAMS coreConsultant
7755  *
7756  * parameter.
7757  *
7758  * Reading 1 in this bit means that the capability
7759  *
7760  * of reading these encoded parameters via software has been
7761  *
7762  * included. Otherwise, the entire register is 0 regardless of
7763  *
7764  * the setting of any other parameters that are encoded in the
7765  *
7766  * bits.
7767  *
7768  * 0: False
7769  *
7770  * 1: True
7771  *
7772  * Field Enumeration Values:
7773  *
7774  * Enum | Value | Description
7775  * :---------------------------------------------------|:------|:-------------------
7776  * ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Add Encoded Params
7777  *
7778  * Field Access Macros:
7779  *
7780  */
7781 /*
7782  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS
7783  *
7784  * Add Encoded Params
7785  */
7786 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1
7787 
7788 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */
7789 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB 7
7790 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */
7791 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB 7
7792 /* The width in bits of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */
7793 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH 1
7794 /* The mask used to set the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */
7795 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK 0x00000080
7796 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value. */
7797 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK 0xffffff7f
7798 /* The reset value of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field. */
7799 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET 0x1
7800 /* Extracts the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS field value from a register. */
7801 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00000080) >> 7)
7802 /* Produces a ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value suitable for setting the register. */
7803 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value) (((value) << 7) & 0x00000080)
7804 
7805 /*
7806  * Field : rx_buffer_depth
7807  *
7808  * The value of this register is
7809  *
7810  * derived from the IC_RX_BUFFER_DEPTH coreConsultant
7811  *
7812  * parameter.
7813  *
7814  * 0x00: Reserved
7815  *
7816  * 0x01: 2
7817  *
7818  * 0x02: 3
7819  *
7820  * to
7821  *
7822  * 0xFF: 256
7823  *
7824  * Field Enumeration Values:
7825  *
7826  * Enum | Value | Description
7827  * :------------------------------------------------|:------|:-------------------------
7828  * ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Rx Fifo Depth 64 Entries
7829  *
7830  * Field Access Macros:
7831  *
7832  */
7833 /*
7834  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH
7835  *
7836  * Rx Fifo Depth 64 Entries
7837  */
7838 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40
7839 
7840 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */
7841 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB 8
7842 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */
7843 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB 15
7844 /* The width in bits of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */
7845 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH 8
7846 /* The mask used to set the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */
7847 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK 0x0000ff00
7848 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value. */
7849 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK 0xffff00ff
7850 /* The reset value of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field. */
7851 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET 0x3f
7852 /* Extracts the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH field value from a register. */
7853 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8)
7854 /* Produces a ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value suitable for setting the register. */
7855 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value) (((value) << 8) & 0x0000ff00)
7856 
7857 /*
7858  * Field : tx_buffer_depth
7859  *
7860  * The value of this register is derived
7861  *
7862  * from the IC_TX_BUFFER_DEPTH coreConsultant
7863  *
7864  * parameter.
7865  *
7866  * 0x00 = Reserved
7867  *
7868  * 0x01 = 2
7869  *
7870  * 0x02 = 3
7871  *
7872  * to
7873  *
7874  * 0xFF = 256
7875  *
7876  * Field Enumeration Values:
7877  *
7878  * Enum | Value | Description
7879  * :------------------------------------------------|:------|:---------------------------
7880  * ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES | 0x40 | Tx Buffer Depth 64 Entries
7881  *
7882  * Field Access Macros:
7883  *
7884  */
7885 /*
7886  * Enumerated value for register field ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH
7887  *
7888  * Tx Buffer Depth 64 Entries
7889  */
7890 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40
7891 
7892 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */
7893 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB 16
7894 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */
7895 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB 23
7896 /* The width in bits of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */
7897 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH 8
7898 /* The mask used to set the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */
7899 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK 0x00ff0000
7900 /* The mask used to clear the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value. */
7901 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK 0xff00ffff
7902 /* The reset value of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field. */
7903 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET 0x3f
7904 /* Extracts the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH field value from a register. */
7905 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16)
7906 /* Produces a ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value suitable for setting the register. */
7907 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value) (((value) << 16) & 0x00ff0000)
7908 
7909 #ifndef __ASSEMBLY__
7910 /*
7911  * WARNING: The C register and register group struct declarations are provided for
7912  * convenience and illustrative purposes. They should, however, be used with
7913  * caution as the C language standard provides no guarantees about the alignment or
7914  * atomicity of device memory accesses. The recommended practice for writing
7915  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7916  * alt_write_word() functions.
7917  *
7918  * The struct declaration for register ALT_I2C_COMP_PARAM_1.
7919  */
7920 struct ALT_I2C_COMP_PARAM_1_s
7921 {
7922  const uint32_t apb_data_width : 2; /* ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH */
7923  const uint32_t max_speed_mode : 2; /* ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD */
7924  const uint32_t hc_count_values : 1; /* ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES */
7925  const uint32_t intr_io : 1; /* ALT_I2C_COMP_PARAM_1_INTR_IO */
7926  const uint32_t has_dma : 1; /* ALT_I2C_COMP_PARAM_1_HAS_DMA */
7927  const uint32_t add_encoded_params : 1; /* ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS */
7928  const uint32_t rx_buffer_depth : 8; /* ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH */
7929  const uint32_t tx_buffer_depth : 8; /* ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH */
7930  uint32_t : 8; /* *UNDEFINED* */
7931 };
7932 
7933 /* The typedef declaration for register ALT_I2C_COMP_PARAM_1. */
7934 typedef volatile struct ALT_I2C_COMP_PARAM_1_s ALT_I2C_COMP_PARAM_1_t;
7935 #endif /* __ASSEMBLY__ */
7936 
7937 /* The reset value of the ALT_I2C_COMP_PARAM_1 register. */
7938 #define ALT_I2C_COMP_PARAM_1_RESET 0x003f3fea
7939 /* The byte offset of the ALT_I2C_COMP_PARAM_1 register from the beginning of the component. */
7940 #define ALT_I2C_COMP_PARAM_1_OFST 0xf4
7941 /* The address of the ALT_I2C_COMP_PARAM_1 register. */
7942 #define ALT_I2C_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST))
7943 
7944 /*
7945  * Register : ic_comp_version
7946  *
7947  * Name: I2C Component Version Register
7948  *
7949  * Size: 32 bits
7950  *
7951  * Address Offset: 0xf8
7952  *
7953  * Read/Write Access: Read
7954  *
7955  * Register Layout
7956  *
7957  * Bits | Access | Reset | Description
7958  * :-------|:-------|:-----------|:-----------------------------
7959  * [31:0] | R | 0x3132312a | ALT_I2C_COMP_VER_IC_COMP_VER
7960  *
7961  */
7962 /*
7963  * Field : ic_comp_version
7964  *
7965  * Specific values for this register are
7966  *
7967  * described in the Releases Table in the
7968  *
7969  * DW_apb_i2c Release Notes
7970  *
7971  * Field Enumeration Values:
7972  *
7973  * Enum | Value | Description
7974  * :-----------------------------------------|:-----------|:--------------
7975  * ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_21A | 0x3132312a | Version 1.21a
7976  *
7977  * Field Access Macros:
7978  *
7979  */
7980 /*
7981  * Enumerated value for register field ALT_I2C_COMP_VER_IC_COMP_VER
7982  *
7983  * Version 1.21a
7984  */
7985 #define ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_21A 0x3132312a
7986 
7987 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */
7988 #define ALT_I2C_COMP_VER_IC_COMP_VER_LSB 0
7989 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */
7990 #define ALT_I2C_COMP_VER_IC_COMP_VER_MSB 31
7991 /* The width in bits of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */
7992 #define ALT_I2C_COMP_VER_IC_COMP_VER_WIDTH 32
7993 /* The mask used to set the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */
7994 #define ALT_I2C_COMP_VER_IC_COMP_VER_SET_MSK 0xffffffff
7995 /* The mask used to clear the ALT_I2C_COMP_VER_IC_COMP_VER register field value. */
7996 #define ALT_I2C_COMP_VER_IC_COMP_VER_CLR_MSK 0x00000000
7997 /* The reset value of the ALT_I2C_COMP_VER_IC_COMP_VER register field. */
7998 #define ALT_I2C_COMP_VER_IC_COMP_VER_RESET 0x3132312a
7999 /* Extracts the ALT_I2C_COMP_VER_IC_COMP_VER field value from a register. */
8000 #define ALT_I2C_COMP_VER_IC_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0)
8001 /* Produces a ALT_I2C_COMP_VER_IC_COMP_VER register field value suitable for setting the register. */
8002 #define ALT_I2C_COMP_VER_IC_COMP_VER_SET(value) (((value) << 0) & 0xffffffff)
8003 
8004 #ifndef __ASSEMBLY__
8005 /*
8006  * WARNING: The C register and register group struct declarations are provided for
8007  * convenience and illustrative purposes. They should, however, be used with
8008  * caution as the C language standard provides no guarantees about the alignment or
8009  * atomicity of device memory accesses. The recommended practice for writing
8010  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8011  * alt_write_word() functions.
8012  *
8013  * The struct declaration for register ALT_I2C_COMP_VER.
8014  */
8015 struct ALT_I2C_COMP_VER_s
8016 {
8017  const uint32_t ic_comp_version : 32; /* ALT_I2C_COMP_VER_IC_COMP_VER */
8018 };
8019 
8020 /* The typedef declaration for register ALT_I2C_COMP_VER. */
8021 typedef volatile struct ALT_I2C_COMP_VER_s ALT_I2C_COMP_VER_t;
8022 #endif /* __ASSEMBLY__ */
8023 
8024 /* The reset value of the ALT_I2C_COMP_VER register. */
8025 #define ALT_I2C_COMP_VER_RESET 0x3132312a
8026 /* The byte offset of the ALT_I2C_COMP_VER register from the beginning of the component. */
8027 #define ALT_I2C_COMP_VER_OFST 0xf8
8028 /* The address of the ALT_I2C_COMP_VER register. */
8029 #define ALT_I2C_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_VER_OFST))
8030 
8031 /*
8032  * Register : ic_comp_type
8033  *
8034  * Name: I2C Component Type Register
8035  *
8036  * Size: 32 bits
8037  *
8038  * Address Offset: 0xfc
8039  *
8040  * Read/Write Access: Read
8041  *
8042  * Register Layout
8043  *
8044  * Bits | Access | Reset | Description
8045  * :-------|:-------|:-----------|:-------------------------------
8046  * [31:0] | R | 0x44570140 | ALT_I2C_COMP_TYPE_IC_COMP_TYPE
8047  *
8048  */
8049 /*
8050  * Field : ic_comp_type
8051  *
8052  * Designware Component Type number
8053  *
8054  * = 0x44_57_01_40. This assigned unique
8055  *
8056  * hex value is constant and is derived
8057  *
8058  * from the two ASCII letters 'DW' followed
8059  *
8060  * by a 16-bit unsigned number.
8061  *
8062  * Field Access Macros:
8063  *
8064  */
8065 /* The Least Significant Bit (LSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */
8066 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_LSB 0
8067 /* The Most Significant Bit (MSB) position of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */
8068 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_MSB 31
8069 /* The width in bits of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */
8070 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_WIDTH 32
8071 /* The mask used to set the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */
8072 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff
8073 /* The mask used to clear the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value. */
8074 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000
8075 /* The reset value of the ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field. */
8076 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140
8077 /* Extracts the ALT_I2C_COMP_TYPE_IC_COMP_TYPE field value from a register. */
8078 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0)
8079 /* Produces a ALT_I2C_COMP_TYPE_IC_COMP_TYPE register field value suitable for setting the register. */
8080 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff)
8081 
8082 #ifndef __ASSEMBLY__
8083 /*
8084  * WARNING: The C register and register group struct declarations are provided for
8085  * convenience and illustrative purposes. They should, however, be used with
8086  * caution as the C language standard provides no guarantees about the alignment or
8087  * atomicity of device memory accesses. The recommended practice for writing
8088  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8089  * alt_write_word() functions.
8090  *
8091  * The struct declaration for register ALT_I2C_COMP_TYPE.
8092  */
8093 struct ALT_I2C_COMP_TYPE_s
8094 {
8095  const uint32_t ic_comp_type : 32; /* ALT_I2C_COMP_TYPE_IC_COMP_TYPE */
8096 };
8097 
8098 /* The typedef declaration for register ALT_I2C_COMP_TYPE. */
8099 typedef volatile struct ALT_I2C_COMP_TYPE_s ALT_I2C_COMP_TYPE_t;
8100 #endif /* __ASSEMBLY__ */
8101 
8102 /* The reset value of the ALT_I2C_COMP_TYPE register. */
8103 #define ALT_I2C_COMP_TYPE_RESET 0x44570140
8104 /* The byte offset of the ALT_I2C_COMP_TYPE register from the beginning of the component. */
8105 #define ALT_I2C_COMP_TYPE_OFST 0xfc
8106 /* The address of the ALT_I2C_COMP_TYPE register. */
8107 #define ALT_I2C_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_TYPE_OFST))
8108 
8109 #ifndef __ASSEMBLY__
8110 /*
8111  * WARNING: The C register and register group struct declarations are provided for
8112  * convenience and illustrative purposes. They should, however, be used with
8113  * caution as the C language standard provides no guarantees about the alignment or
8114  * atomicity of device memory accesses. The recommended practice for writing
8115  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8116  * alt_write_word() functions.
8117  *
8118  * The struct declaration for register group ALT_I2C.
8119  */
8120 struct ALT_I2C_s
8121 {
8122  ALT_I2C_CON_t ic_con; /* ALT_I2C_CON */
8123  ALT_I2C_TAR_t ic_tar; /* ALT_I2C_TAR */
8124  ALT_I2C_SAR_t ic_sar; /* ALT_I2C_SAR */
8125  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
8126  ALT_I2C_DATA_CMD_t ic_data_cmd; /* ALT_I2C_DATA_CMD */
8127  ALT_I2C_SS_SCL_HCNT_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */
8128  ALT_I2C_SS_SCL_LCNT_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */
8129  ALT_I2C_FS_SCL_HCNT_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */
8130  ALT_I2C_FS_SCL_LCNT_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */
8131  volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */
8132  ALT_I2C_INTR_STAT_t ic_intr_stat; /* ALT_I2C_INTR_STAT */
8133  ALT_I2C_INTR_MSK_t ic_intr_mask; /* ALT_I2C_INTR_MSK */
8134  ALT_I2C_RAW_INTR_STAT_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */
8135  ALT_I2C_RX_TL_t ic_rx_tl; /* ALT_I2C_RX_TL */
8136  ALT_I2C_TX_TL_t ic_tx_tl; /* ALT_I2C_TX_TL */
8137  ALT_I2C_CLR_INTR_t ic_clr_intr; /* ALT_I2C_CLR_INTR */
8138  ALT_I2C_CLR_RX_UNDER_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */
8139  ALT_I2C_CLR_RX_OVER_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */
8140  ALT_I2C_CLR_TX_OVER_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */
8141  ALT_I2C_CLR_RD_REQ_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */
8142  ALT_I2C_CLR_TX_ABRT_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */
8143  ALT_I2C_CLR_RX_DONE_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */
8144  ALT_I2C_CLR_ACTIVITY_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */
8145  ALT_I2C_CLR_STOP_DET_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */
8146  ALT_I2C_CLR_START_DET_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */
8147  ALT_I2C_CLR_GEN_CALL_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */
8148  ALT_I2C_EN_t ic_enable; /* ALT_I2C_EN */
8149  ALT_I2C_STAT_t ic_status; /* ALT_I2C_STAT */
8150  ALT_I2C_TXFLR_t ic_txflr; /* ALT_I2C_TXFLR */
8151  ALT_I2C_RXFLR_t ic_rxflr; /* ALT_I2C_RXFLR */
8152  ALT_I2C_SDA_HOLD_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */
8153  ALT_I2C_TX_ABRT_SRC_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */
8154  ALT_I2C_SLV_DATA_NACK_ONLY_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */
8155  ALT_I2C_DMA_CR_t ic_dma_cr; /* ALT_I2C_DMA_CR */
8156  ALT_I2C_DMA_TDLR_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */
8157  ALT_I2C_DMA_RDLR_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */
8158  ALT_I2C_SDA_SETUP_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */
8159  ALT_I2C_ACK_GENERAL_CALL_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */
8160  ALT_I2C_EN_STAT_t ic_enable_status; /* ALT_I2C_EN_STAT */
8161  ALT_I2C_FS_SPKLEN_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */
8162  volatile uint32_t _pad_0xa4_0xa7; /* *UNDEFINED* */
8163  ALT_I2C_CLR_RESTART_DET_t ic_clr_restart_det; /* ALT_I2C_CLR_RESTART_DET */
8164  volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */
8165  ALT_I2C_COMP_PARAM_1_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */
8166  ALT_I2C_COMP_VER_t ic_comp_version; /* ALT_I2C_COMP_VER */
8167  ALT_I2C_COMP_TYPE_t ic_comp_type; /* ALT_I2C_COMP_TYPE */
8168 };
8169 
8170 /* The typedef declaration for register group ALT_I2C. */
8171 typedef volatile struct ALT_I2C_s ALT_I2C_t;
8172 /* The struct declaration for the raw register contents of register group ALT_I2C. */
8173 struct ALT_I2C_raw_s
8174 {
8175  volatile uint32_t ic_con; /* ALT_I2C_CON */
8176  volatile uint32_t ic_tar; /* ALT_I2C_TAR */
8177  volatile uint32_t ic_sar; /* ALT_I2C_SAR */
8178  uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
8179  volatile uint32_t ic_data_cmd; /* ALT_I2C_DATA_CMD */
8180  volatile uint32_t ic_ss_scl_hcnt; /* ALT_I2C_SS_SCL_HCNT */
8181  volatile uint32_t ic_ss_scl_lcnt; /* ALT_I2C_SS_SCL_LCNT */
8182  volatile uint32_t ic_fs_scl_hcnt; /* ALT_I2C_FS_SCL_HCNT */
8183  volatile uint32_t ic_fs_scl_lcnt; /* ALT_I2C_FS_SCL_LCNT */
8184  uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */
8185  volatile uint32_t ic_intr_stat; /* ALT_I2C_INTR_STAT */
8186  volatile uint32_t ic_intr_mask; /* ALT_I2C_INTR_MSK */
8187  volatile uint32_t ic_raw_intr_stat; /* ALT_I2C_RAW_INTR_STAT */
8188  volatile uint32_t ic_rx_tl; /* ALT_I2C_RX_TL */
8189  volatile uint32_t ic_tx_tl; /* ALT_I2C_TX_TL */
8190  volatile uint32_t ic_clr_intr; /* ALT_I2C_CLR_INTR */
8191  volatile uint32_t ic_clr_rx_under; /* ALT_I2C_CLR_RX_UNDER */
8192  volatile uint32_t ic_clr_rx_over; /* ALT_I2C_CLR_RX_OVER */
8193  volatile uint32_t ic_clr_tx_over; /* ALT_I2C_CLR_TX_OVER */
8194  volatile uint32_t ic_clr_rd_req; /* ALT_I2C_CLR_RD_REQ */
8195  volatile uint32_t ic_clr_tx_abrt; /* ALT_I2C_CLR_TX_ABRT */
8196  volatile uint32_t ic_clr_rx_done; /* ALT_I2C_CLR_RX_DONE */
8197  volatile uint32_t ic_clr_activity; /* ALT_I2C_CLR_ACTIVITY */
8198  volatile uint32_t ic_clr_stop_det; /* ALT_I2C_CLR_STOP_DET */
8199  volatile uint32_t ic_clr_start_det; /* ALT_I2C_CLR_START_DET */
8200  volatile uint32_t ic_clr_gen_call; /* ALT_I2C_CLR_GEN_CALL */
8201  volatile uint32_t ic_enable; /* ALT_I2C_EN */
8202  volatile uint32_t ic_status; /* ALT_I2C_STAT */
8203  volatile uint32_t ic_txflr; /* ALT_I2C_TXFLR */
8204  volatile uint32_t ic_rxflr; /* ALT_I2C_RXFLR */
8205  volatile uint32_t ic_sda_hold; /* ALT_I2C_SDA_HOLD */
8206  volatile uint32_t ic_tx_abrt_source; /* ALT_I2C_TX_ABRT_SRC */
8207  volatile uint32_t ic_slv_data_nack_only; /* ALT_I2C_SLV_DATA_NACK_ONLY */
8208  volatile uint32_t ic_dma_cr; /* ALT_I2C_DMA_CR */
8209  volatile uint32_t ic_dma_tdlr; /* ALT_I2C_DMA_TDLR */
8210  volatile uint32_t ic_dma_rdlr; /* ALT_I2C_DMA_RDLR */
8211  volatile uint32_t ic_sda_setup; /* ALT_I2C_SDA_SETUP */
8212  volatile uint32_t ic_ack_general_call; /* ALT_I2C_ACK_GENERAL_CALL */
8213  volatile uint32_t ic_enable_status; /* ALT_I2C_EN_STAT */
8214  volatile uint32_t ic_fs_spklen; /* ALT_I2C_FS_SPKLEN */
8215  uint32_t _pad_0xa4_0xa7; /* *UNDEFINED* */
8216  volatile uint32_t ic_clr_restart_det; /* ALT_I2C_CLR_RESTART_DET */
8217  uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */
8218  volatile uint32_t ic_comp_param_1; /* ALT_I2C_COMP_PARAM_1 */
8219  volatile uint32_t ic_comp_version; /* ALT_I2C_COMP_VER */
8220  volatile uint32_t ic_comp_type; /* ALT_I2C_COMP_TYPE */
8221 };
8222 
8223 /* The typedef declaration for the raw register contents of register group ALT_I2C. */
8224 typedef volatile struct ALT_I2C_raw_s ALT_I2C_raw_t;
8225 #endif /* __ASSEMBLY__ */
8226 
8227 
8228 #ifdef __cplusplus
8229 }
8230 #endif /* __cplusplus */
8231 #endif /* __ALT_SOCAL_I2C_H__ */
8232