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alt_noc_mpu_prb.h
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32 
33 /* Altera - ALT_NOC_MPU_PRB_H2F_MAIN_PRB */
34 
35 #ifndef __ALT_SOCAL_NOC_MPU_PRB_H__
36 #define __ALT_SOCAL_NOC_MPU_PRB_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_MPU_PRB_H2F_MAIN_PRB
50  *
51  */
52 /*
53  * Register : Probe_SoC2FPGA_main_Probe_Id_CoreId
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :-------|:-------|:--------|:-----------------------------------------
59  * [7:0] | R | 0x6 | ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID
60  * [31:8] | R | 0x567d6 | ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM
61  *
62  */
63 /*
64  * Field : CORETYPEID
65  *
66  * Field identifying the type of IP.
67  *
68  * Field Access Macros:
69  *
70  */
71 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID register field. */
72 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_LSB 0
73 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID register field. */
74 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_MSB 7
75 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID register field. */
76 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_WIDTH 8
77 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID register field value. */
78 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_SET_MSK 0x000000ff
79 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID register field value. */
80 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_CLR_MSK 0xffffff00
81 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID register field. */
82 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_RESET 0x6
83 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID field value from a register. */
84 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
85 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID register field value suitable for setting the register. */
86 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
87 
88 /*
89  * Field : CORECHECKSUM
90  *
91  * Field containing a checksum of the parameters of the IP.
92  *
93  * Field Access Macros:
94  *
95  */
96 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM register field. */
97 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_LSB 8
98 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM register field. */
99 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_MSB 31
100 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM register field. */
101 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_WIDTH 24
102 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM register field value. */
103 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_SET_MSK 0xffffff00
104 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM register field value. */
105 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_CLR_MSK 0x000000ff
106 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM register field. */
107 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_RESET 0x567d6
108 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM field value from a register. */
109 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
110 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM register field value suitable for setting the register. */
111 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
112 
113 #ifndef __ASSEMBLY__
114 /*
115  * WARNING: The C register and register group struct declarations are provided for
116  * convenience and illustrative purposes. They should, however, be used with
117  * caution as the C language standard provides no guarantees about the alignment or
118  * atomicity of device memory accesses. The recommended practice for writing
119  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
120  * alt_write_word() functions.
121  *
122  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_COREID.
123  */
124 struct ALT_NOC_MPU_PRB_H2F_MAIN_COREID_s
125 {
126  const uint32_t CORETYPEID : 8; /* ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID */
127  const uint32_t CORECHECKSUM : 24; /* ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM */
128 };
129 
130 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_COREID. */
131 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_COREID_s ALT_NOC_MPU_PRB_H2F_MAIN_COREID_t;
132 #endif /* __ASSEMBLY__ */
133 
134 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_COREID register. */
135 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_RESET 0x0567d606
136 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_COREID register from the beginning of the component. */
137 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_OFST 0x0
138 
139 /*
140  * Register : Probe_SoC2FPGA_main_Probe_Id_RevisionId
141  *
142  * Register Layout
143  *
144  * Bits | Access | Reset | Description
145  * :-------|:-------|:--------|:-----------------------------------------
146  * [7:0] | R | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID
147  * [31:8] | R | 0x129ff | ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID
148  *
149  */
150 /*
151  * Field : USERID
152  *
153  * Field containing a user defined value, not used anywhere inside the IP itself.
154  *
155  * Field Access Macros:
156  *
157  */
158 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID register field. */
159 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_LSB 0
160 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID register field. */
161 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_MSB 7
162 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID register field. */
163 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_WIDTH 8
164 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID register field value. */
165 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_SET_MSK 0x000000ff
166 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID register field value. */
167 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_CLR_MSK 0xffffff00
168 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID register field. */
169 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_RESET 0x0
170 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID field value from a register. */
171 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
172 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID register field value suitable for setting the register. */
173 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
174 
175 /*
176  * Field : FLEXNOCID
177  *
178  * Field containing the build revision of the software used to generate the IP HDL
179  * code.
180  *
181  * Field Access Macros:
182  *
183  */
184 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID register field. */
185 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_LSB 8
186 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID register field. */
187 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_MSB 31
188 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID register field. */
189 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_WIDTH 24
190 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID register field value. */
191 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_SET_MSK 0xffffff00
192 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID register field value. */
193 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_CLR_MSK 0x000000ff
194 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID register field. */
195 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_RESET 0x129ff
196 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID field value from a register. */
197 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
198 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID register field value suitable for setting the register. */
199 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
200 
201 #ifndef __ASSEMBLY__
202 /*
203  * WARNING: The C register and register group struct declarations are provided for
204  * convenience and illustrative purposes. They should, however, be used with
205  * caution as the C language standard provides no guarantees about the alignment or
206  * atomicity of device memory accesses. The recommended practice for writing
207  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
208  * alt_write_word() functions.
209  *
210  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_REVID.
211  */
212 struct ALT_NOC_MPU_PRB_H2F_MAIN_REVID_s
213 {
214  const uint32_t USERID : 8; /* ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID */
215  const uint32_t FLEXNOCID : 24; /* ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID */
216 };
217 
218 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_REVID. */
219 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_REVID_s ALT_NOC_MPU_PRB_H2F_MAIN_REVID_t;
220 #endif /* __ASSEMBLY__ */
221 
222 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_REVID register. */
223 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_RESET 0x0129ff00
224 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_REVID register from the beginning of the component. */
225 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_OFST 0x4
226 
227 /*
228  * Register : Probe_SoC2FPGA_main_Probe_MainCtl
229  *
230  * Register MainCtl contains probe global control bits. The register has seven bit
231  * fields:
232  *
233  * Register Layout
234  *
235  * Bits | Access | Reset | Description
236  * :-------|:-------|:--------|:-----------------------------------------------------------
237  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN
238  * [1] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN
239  * [2] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN
240  * [3] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN
241  * [4] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN
242  * [5] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP
243  * [6] | R | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD
244  * [7] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN
245  * [31:8] | ??? | Unknown | *UNDEFINED*
246  *
247  */
248 /*
249  * Field : ERREN
250  *
251  * Register field ErrEn enables the probe to send on the ObsTx output any packet
252  * with Error status, independently of filtering mechanisms, thus constituting a
253  * simple supplementary global filter.
254  *
255  * Field Access Macros:
256  *
257  */
258 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN register field. */
259 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_LSB 0
260 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN register field. */
261 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_MSB 0
262 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN register field. */
263 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_WIDTH 1
264 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN register field value. */
265 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_SET_MSK 0x00000001
266 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN register field value. */
267 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_CLR_MSK 0xfffffffe
268 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN register field. */
269 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_RESET 0x0
270 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN field value from a register. */
271 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_GET(value) (((value) & 0x00000001) >> 0)
272 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN register field value suitable for setting the register. */
273 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_SET(value) (((value) << 0) & 0x00000001)
274 
275 /*
276  * Field : TRACEEN
277  *
278  * Register field TraceEn enables the probe to send filtered packets (Trace) on the
279  * ObsTx observation output.
280  *
281  * Field Access Macros:
282  *
283  */
284 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN register field. */
285 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_LSB 1
286 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN register field. */
287 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_MSB 1
288 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN register field. */
289 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_WIDTH 1
290 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN register field value. */
291 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_SET_MSK 0x00000002
292 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN register field value. */
293 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_CLR_MSK 0xfffffffd
294 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN register field. */
295 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_RESET 0x0
296 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN field value from a register. */
297 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_GET(value) (((value) & 0x00000002) >> 1)
298 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN register field value suitable for setting the register. */
299 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_SET(value) (((value) << 1) & 0x00000002)
300 
301 /*
302  * Field : PAYLOADEN
303  *
304  * Register field PayloadEn, when set to 1, enables traces to contain headers and
305  * payload. When set ot 0, only headers are reported.
306  *
307  * Field Access Macros:
308  *
309  */
310 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN register field. */
311 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_LSB 2
312 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN register field. */
313 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_MSB 2
314 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN register field. */
315 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_WIDTH 1
316 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN register field value. */
317 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_SET_MSK 0x00000004
318 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN register field value. */
319 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_CLR_MSK 0xfffffffb
320 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN register field. */
321 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_RESET 0x0
322 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN field value from a register. */
323 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_GET(value) (((value) & 0x00000004) >> 2)
324 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN register field value suitable for setting the register. */
325 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_SET(value) (((value) << 2) & 0x00000004)
326 
327 /*
328  * Field : STATEN
329  *
330  * When set to 1, register field StatEn enables statistics profiling. The probe
331  * sendS statistics results to the output for signal ObsTx. All statistics counters
332  * are cleared when the StatEn bit goes from 0 to 1. When set to 0, counters are
333  * disabled.
334  *
335  * Field Access Macros:
336  *
337  */
338 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN register field. */
339 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_LSB 3
340 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN register field. */
341 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_MSB 3
342 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN register field. */
343 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_WIDTH 1
344 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN register field value. */
345 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_SET_MSK 0x00000008
346 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN register field value. */
347 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_CLR_MSK 0xfffffff7
348 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN register field. */
349 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_RESET 0x0
350 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN field value from a register. */
351 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_GET(value) (((value) & 0x00000008) >> 3)
352 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN register field value suitable for setting the register. */
353 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_SET(value) (((value) << 3) & 0x00000008)
354 
355 /*
356  * Field : ALARMEN
357  *
358  * When set, register field AlarmEn enables the probe to collect alarm-related
359  * information. When the register field bit is null, both TraceAlarm and StatAlarm
360  * outputs are driven to 0.
361  *
362  * Field Access Macros:
363  *
364  */
365 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN register field. */
366 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_LSB 4
367 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN register field. */
368 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_MSB 4
369 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN register field. */
370 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_WIDTH 1
371 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN register field value. */
372 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_SET_MSK 0x00000010
373 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN register field value. */
374 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_CLR_MSK 0xffffffef
375 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN register field. */
376 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_RESET 0x0
377 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN field value from a register. */
378 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_GET(value) (((value) & 0x00000010) >> 4)
379 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN register field value suitable for setting the register. */
380 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_SET(value) (((value) << 4) & 0x00000010)
381 
382 /*
383  * Field : STATCONDDUMP
384  *
385  * When set, register field StatCondDump enables the dump of a statistics frame to
386  * the range of counter values set for registers StatAlarmMin, StatAlarmMax, and
387  * AlarmMode. This field also renders register StatAlarmStatus inoperative. When
388  * parameter statisticsCounterAlarm is set to False, the StatCondDump register bit
389  * is reserved.
390  *
391  * Field Access Macros:
392  *
393  */
394 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP register field. */
395 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_LSB 5
396 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP register field. */
397 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_MSB 5
398 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP register field. */
399 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_WIDTH 1
400 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP register field value. */
401 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_SET_MSK 0x00000020
402 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP register field value. */
403 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_CLR_MSK 0xffffffdf
404 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP register field. */
405 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_RESET 0x0
406 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP field value from a register. */
407 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_GET(value) (((value) & 0x00000020) >> 5)
408 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP register field value suitable for setting the register. */
409 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_SET(value) (((value) << 5) & 0x00000020)
410 
411 /*
412  * Field : INTRUSIVEMODE
413  *
414  * When set to 1, register field IntrusiveMode enables trace operation in Intrusive
415  * flow-control mode. When set to 0, the register enables trace operation in
416  * Overflow flow-control mode
417  *
418  * Field Access Macros:
419  *
420  */
421 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD register field. */
422 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_LSB 6
423 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD register field. */
424 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_MSB 6
425 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD register field. */
426 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_WIDTH 1
427 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD register field value. */
428 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_SET_MSK 0x00000040
429 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD register field value. */
430 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_CLR_MSK 0xffffffbf
431 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD register field. */
432 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_RESET 0x0
433 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD field value from a register. */
434 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_GET(value) (((value) & 0x00000040) >> 6)
435 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD register field value suitable for setting the register. */
436 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_SET(value) (((value) << 6) & 0x00000040)
437 
438 /*
439  * Field : FILTBYTEALWAYSCHAINABLEEN
440  *
441  * When set to 0, filters are mapped to all statistic counters when counting bytes
442  * or enabled bytes. Therefore, only filter events mapped to even counters can be
443  * counted using a pair of chained counters.When set to 1, filters are mapped only
444  * to even statistic counters when counting bytes or enabled bytes. Thus events
445  * from any filter can be counted using a pair of chained counters.
446  *
447  * Field Access Macros:
448  *
449  */
450 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
451 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_LSB 7
452 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
453 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MSB 7
454 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
455 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_WIDTH 1
456 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value. */
457 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET_MSK 0x00000080
458 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value. */
459 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_CLR_MSK 0xffffff7f
460 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
461 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_RESET 0x0
462 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN field value from a register. */
463 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_GET(value) (((value) & 0x00000080) >> 7)
464 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value suitable for setting the register. */
465 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET(value) (((value) << 7) & 0x00000080)
466 
467 #ifndef __ASSEMBLY__
468 /*
469  * WARNING: The C register and register group struct declarations are provided for
470  * convenience and illustrative purposes. They should, however, be used with
471  * caution as the C language standard provides no guarantees about the alignment or
472  * atomicity of device memory accesses. The recommended practice for writing
473  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
474  * alt_write_word() functions.
475  *
476  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL.
477  */
478 struct ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_s
479 {
480  uint32_t ERREN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN */
481  uint32_t TRACEEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN */
482  uint32_t PAYLOADEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN */
483  uint32_t STATEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN */
484  uint32_t ALARMEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN */
485  uint32_t STATCONDDUMP : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP */
486  const uint32_t INTRUSIVEMODE : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD */
487  uint32_t FILTBYTEALWAYSCHAINABLEEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN */
488  uint32_t : 24; /* *UNDEFINED* */
489 };
490 
491 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL. */
492 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_s ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_t;
493 #endif /* __ASSEMBLY__ */
494 
495 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL register. */
496 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_RESET 0x00000000
497 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL register from the beginning of the component. */
498 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_OFST 0x8
499 
500 /*
501  * Register : Probe_SoC2FPGA_main_Probe_CfgCtl
502  *
503  * Register Layout
504  *
505  * Bits | Access | Reset | Description
506  * :-------|:-------|:--------|:---------------------------------------
507  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN
508  * [1] | R | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT
509  * [31:2] | ??? | Unknown | *UNDEFINED*
510  *
511  */
512 /*
513  * Field : GLOBALEN
514  *
515  *
516  * Field Access Macros:
517  *
518  */
519 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN register field. */
520 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_LSB 0
521 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN register field. */
522 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_MSB 0
523 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN register field. */
524 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_WIDTH 1
525 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN register field value. */
526 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_SET_MSK 0x00000001
527 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN register field value. */
528 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_CLR_MSK 0xfffffffe
529 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN register field. */
530 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_RESET 0x0
531 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN field value from a register. */
532 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_GET(value) (((value) & 0x00000001) >> 0)
533 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN register field value suitable for setting the register. */
534 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_SET(value) (((value) << 0) & 0x00000001)
535 
536 /*
537  * Field : ACTIVE
538  *
539  *
540  * Field Access Macros:
541  *
542  */
543 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT register field. */
544 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_LSB 1
545 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT register field. */
546 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_MSB 1
547 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT register field. */
548 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_WIDTH 1
549 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT register field value. */
550 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_SET_MSK 0x00000002
551 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT register field value. */
552 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_CLR_MSK 0xfffffffd
553 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT register field. */
554 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_RESET 0x0
555 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT field value from a register. */
556 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_GET(value) (((value) & 0x00000002) >> 1)
557 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT register field value suitable for setting the register. */
558 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_SET(value) (((value) << 1) & 0x00000002)
559 
560 #ifndef __ASSEMBLY__
561 /*
562  * WARNING: The C register and register group struct declarations are provided for
563  * convenience and illustrative purposes. They should, however, be used with
564  * caution as the C language standard provides no guarantees about the alignment or
565  * atomicity of device memory accesses. The recommended practice for writing
566  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
567  * alt_write_word() functions.
568  *
569  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL.
570  */
571 struct ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_s
572 {
573  uint32_t GLOBALEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN */
574  const uint32_t ACTIVE : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT */
575  uint32_t : 30; /* *UNDEFINED* */
576 };
577 
578 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL. */
579 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_s ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_t;
580 #endif /* __ASSEMBLY__ */
581 
582 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL register. */
583 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_RESET 0x00000000
584 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL register from the beginning of the component. */
585 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_OFST 0xc
586 
587 /*
588  * Register : Probe_SoC2FPGA_main_Probe_TracePortSel
589  *
590  *
591  * Register Layout
592  *
593  * Bits | Access | Reset | Description
594  * :-------|:-------|:--------|:---------------------------------------------------
595  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL
596  * [31:1] | ??? | Unknown | *UNDEFINED*
597  *
598  */
599 /*
600  * Field : TRACEPORTSEL
601  *
602  * Register TracePortSel indicates which generic protocol link is currently being
603  * observed by trace logic.The number of bits in register TracePortSel is equal to
604  * log2 of the value set for parameter nPort.The register can be updated at any
605  * time, but changes only become effective at packet boundaries.
606  *
607  * Field Access Macros:
608  *
609  */
610 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL register field. */
611 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_LSB 0
612 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL register field. */
613 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_MSB 0
614 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL register field. */
615 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_WIDTH 1
616 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL register field value. */
617 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_SET_MSK 0x00000001
618 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL register field value. */
619 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_CLR_MSK 0xfffffffe
620 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL register field. */
621 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_RESET 0x0
622 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL field value from a register. */
623 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_GET(value) (((value) & 0x00000001) >> 0)
624 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL register field value suitable for setting the register. */
625 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_SET(value) (((value) << 0) & 0x00000001)
626 
627 #ifndef __ASSEMBLY__
628 /*
629  * WARNING: The C register and register group struct declarations are provided for
630  * convenience and illustrative purposes. They should, however, be used with
631  * caution as the C language standard provides no guarantees about the alignment or
632  * atomicity of device memory accesses. The recommended practice for writing
633  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
634  * alt_write_word() functions.
635  *
636  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL.
637  */
638 struct ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_s
639 {
640  uint32_t TRACEPORTSEL : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL */
641  uint32_t : 31; /* *UNDEFINED* */
642 };
643 
644 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL. */
645 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_s ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_t;
646 #endif /* __ASSEMBLY__ */
647 
648 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL register. */
649 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_RESET 0x00000000
650 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL register from the beginning of the component. */
651 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_OFST 0x10
652 
653 /*
654  * Register : Probe_SoC2FPGA_main_Probe_FilterLut
655  *
656  *
657  * Register Layout
658  *
659  * Bits | Access | Reset | Description
660  * :-------|:-------|:--------|:---------------------------------------
661  * [3:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT
662  * [31:4] | ??? | Unknown | *UNDEFINED*
663  *
664  */
665 /*
666  * Field : FILTERLUT
667  *
668  * Register FilterLut contains a look-up table that is used to combine filter
669  * outputs in order to trace packets. Packet tracing is enabled when the FilterLut
670  * bit of index (FNout ... F0out) is equal to 1.The number of bits in register
671  * FilterLut is determined by the setting for parameter nFilter, calculated as
672  * 2**nFilter.When parameter nFilter is set to None, FilterLut is reserved.
673  *
674  * Field Access Macros:
675  *
676  */
677 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT register field. */
678 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_LSB 0
679 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT register field. */
680 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_MSB 3
681 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT register field. */
682 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_WIDTH 4
683 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT register field value. */
684 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_SET_MSK 0x0000000f
685 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT register field value. */
686 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_CLR_MSK 0xfffffff0
687 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT register field. */
688 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_RESET 0x0
689 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT field value from a register. */
690 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_GET(value) (((value) & 0x0000000f) >> 0)
691 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT register field value suitable for setting the register. */
692 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_SET(value) (((value) << 0) & 0x0000000f)
693 
694 #ifndef __ASSEMBLY__
695 /*
696  * WARNING: The C register and register group struct declarations are provided for
697  * convenience and illustrative purposes. They should, however, be used with
698  * caution as the C language standard provides no guarantees about the alignment or
699  * atomicity of device memory accesses. The recommended practice for writing
700  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
701  * alt_write_word() functions.
702  *
703  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT.
704  */
705 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_s
706 {
707  uint32_t FILTERLUT : 4; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT */
708  uint32_t : 28; /* *UNDEFINED* */
709 };
710 
711 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT. */
712 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_t;
713 #endif /* __ASSEMBLY__ */
714 
715 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT register. */
716 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_RESET 0x00000000
717 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT register from the beginning of the component. */
718 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_OFST 0x14
719 
720 /*
721  * Register : Probe_SoC2FPGA_main_Probe_TraceAlarmEn
722  *
723  *
724  * Register Layout
725  *
726  * Bits | Access | Reset | Description
727  * :-------|:-------|:--------|:---------------------------------------------------
728  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN
729  * [31:3] | ??? | Unknown | *UNDEFINED*
730  *
731  */
732 /*
733  * Field : TRACEALARMEN
734  *
735  * Register TraceAlarmEn controls which lookup table or filter can set the
736  * TraceAlarm signal output once the trace alarm status is set. The number of bits
737  * in register TraceAlarmEn is determined by the value set for parameter nFilter +
738  * 1.Bit nFilter controls the lookup table output, and bits nFilter:0 control the
739  * corresponding filter output. When parameter nFilter is set to None, TraceAlarmEn
740  * is reserved.
741  *
742  * Field Access Macros:
743  *
744  */
745 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN register field. */
746 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_LSB 0
747 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN register field. */
748 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_MSB 2
749 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN register field. */
750 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_WIDTH 3
751 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN register field value. */
752 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_SET_MSK 0x00000007
753 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN register field value. */
754 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_CLR_MSK 0xfffffff8
755 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN register field. */
756 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_RESET 0x0
757 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN field value from a register. */
758 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_GET(value) (((value) & 0x00000007) >> 0)
759 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN register field value suitable for setting the register. */
760 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_SET(value) (((value) << 0) & 0x00000007)
761 
762 #ifndef __ASSEMBLY__
763 /*
764  * WARNING: The C register and register group struct declarations are provided for
765  * convenience and illustrative purposes. They should, however, be used with
766  * caution as the C language standard provides no guarantees about the alignment or
767  * atomicity of device memory accesses. The recommended practice for writing
768  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
769  * alt_write_word() functions.
770  *
771  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN.
772  */
773 struct ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_s
774 {
775  uint32_t TRACEALARMEN : 3; /* ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN */
776  uint32_t : 29; /* *UNDEFINED* */
777 };
778 
779 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN. */
780 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_s ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_t;
781 #endif /* __ASSEMBLY__ */
782 
783 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN register. */
784 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_RESET 0x00000000
785 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN register from the beginning of the component. */
786 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_OFST 0x18
787 
788 /*
789  * Register : Probe_SoC2FPGA_main_Probe_TraceAlarmStatus
790  *
791  *
792  * Register Layout
793  *
794  * Bits | Access | Reset | Description
795  * :-------|:-------|:--------|:-------------------------------------------------------
796  * [2:0] | R | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT
797  * [31:3] | ??? | Unknown | *UNDEFINED*
798  *
799  */
800 /*
801  * Field : TRACEALARMSTATUS
802  *
803  * Register TraceAlarmStatus is a read-only register that indicates which lookup
804  * table or filter has been matched by a packet, independently of register
805  * TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is
806  * determined by the value set for parameter nFilter + 1.When nFilter is set to
807  * None, TraceAlarmStatus is reserved.
808  *
809  * Field Access Macros:
810  *
811  */
812 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field. */
813 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_LSB 0
814 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field. */
815 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_MSB 2
816 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field. */
817 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_WIDTH 3
818 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field value. */
819 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_SET_MSK 0x00000007
820 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field value. */
821 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_CLR_MSK 0xfffffff8
822 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field. */
823 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_RESET 0x0
824 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT field value from a register. */
825 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_GET(value) (((value) & 0x00000007) >> 0)
826 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field value suitable for setting the register. */
827 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_SET(value) (((value) << 0) & 0x00000007)
828 
829 #ifndef __ASSEMBLY__
830 /*
831  * WARNING: The C register and register group struct declarations are provided for
832  * convenience and illustrative purposes. They should, however, be used with
833  * caution as the C language standard provides no guarantees about the alignment or
834  * atomicity of device memory accesses. The recommended practice for writing
835  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
836  * alt_write_word() functions.
837  *
838  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT.
839  */
840 struct ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_s
841 {
842  const uint32_t TRACEALARMSTATUS : 3; /* ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT */
843  uint32_t : 29; /* *UNDEFINED* */
844 };
845 
846 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT. */
847 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_s ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_t;
848 #endif /* __ASSEMBLY__ */
849 
850 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT register. */
851 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_RESET 0x00000000
852 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT register from the beginning of the component. */
853 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_OFST 0x1c
854 
855 /*
856  * Register : Probe_SoC2FPGA_main_Probe_TraceAlarmClr
857  *
858  *
859  * Register Layout
860  *
861  * Bits | Access | Reset | Description
862  * :-------|:-------|:--------|:-----------------------------------------------------
863  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR
864  * [31:3] | ??? | Unknown | *UNDEFINED*
865  *
866  */
867 /*
868  * Field : TRACEALARMCLR
869  *
870  * Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in
871  * register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal
872  * to (nFilter + 1). When nFilter is set to 0, TraceAlarmClr is reserved.NOTE The
873  * written value is not stored in TraceAlarmClr. A read always returns 0.
874  *
875  * Field Access Macros:
876  *
877  */
878 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR register field. */
879 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_LSB 0
880 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR register field. */
881 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_MSB 2
882 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR register field. */
883 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_WIDTH 3
884 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR register field value. */
885 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x00000007
886 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR register field value. */
887 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xfffffff8
888 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR register field. */
889 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0
890 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR field value from a register. */
891 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_GET(value) (((value) & 0x00000007) >> 0)
892 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR register field value suitable for setting the register. */
893 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_SET(value) (((value) << 0) & 0x00000007)
894 
895 #ifndef __ASSEMBLY__
896 /*
897  * WARNING: The C register and register group struct declarations are provided for
898  * convenience and illustrative purposes. They should, however, be used with
899  * caution as the C language standard provides no guarantees about the alignment or
900  * atomicity of device memory accesses. The recommended practice for writing
901  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
902  * alt_write_word() functions.
903  *
904  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR.
905  */
906 struct ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_s
907 {
908  uint32_t TRACEALARMCLR : 3; /* ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR */
909  uint32_t : 29; /* *UNDEFINED* */
910 };
911 
912 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR. */
913 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_s ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_t;
914 #endif /* __ASSEMBLY__ */
915 
916 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR register. */
917 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_RESET 0x00000000
918 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR register from the beginning of the component. */
919 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_OFST 0x20
920 
921 /*
922  * Register : Probe_SoC2FPGA_main_Probe_StatPeriod
923  *
924  *
925  * Register Layout
926  *
927  * Bits | Access | Reset | Description
928  * :-------|:-------|:--------|:-----------------------------------------------
929  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD
930  * [31:5] | ??? | Unknown | *UNDEFINED*
931  *
932  */
933 /*
934  * Field : STATPERIOD
935  *
936  * Register StatPeriod is a 5-bit register that sets a period, within a range of 2
937  * cycles to 2 gigacycles, during which statistics are collected before being
938  * dumped automatically. Setting the register implicitly enables automatic mode
939  * operation for statistics collection. The period is calculated with the formula:
940  * N_Cycle = 2**StatPeriodWhen register StatPeriod is set to its default value 0,
941  * automatic dump mode is disabled, and register StatGo is activated for manual
942  * mode operation. Note: When parameter statisticsCollection is set to False,
943  * StatPeriod is reserved.
944  *
945  * Field Access Macros:
946  *
947  */
948 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD register field. */
949 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_LSB 0
950 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD register field. */
951 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_MSB 4
952 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD register field. */
953 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_WIDTH 5
954 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD register field value. */
955 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_SET_MSK 0x0000001f
956 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD register field value. */
957 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_CLR_MSK 0xffffffe0
958 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD register field. */
959 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_RESET 0x0
960 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD field value from a register. */
961 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
962 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD register field value suitable for setting the register. */
963 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_SET(value) (((value) << 0) & 0x0000001f)
964 
965 #ifndef __ASSEMBLY__
966 /*
967  * WARNING: The C register and register group struct declarations are provided for
968  * convenience and illustrative purposes. They should, however, be used with
969  * caution as the C language standard provides no guarantees about the alignment or
970  * atomicity of device memory accesses. The recommended practice for writing
971  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
972  * alt_write_word() functions.
973  *
974  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD.
975  */
976 struct ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_s
977 {
978  uint32_t STATPERIOD : 5; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD */
979  uint32_t : 27; /* *UNDEFINED* */
980 };
981 
982 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD. */
983 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_s ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_t;
984 #endif /* __ASSEMBLY__ */
985 
986 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD register. */
987 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_RESET 0x00000000
988 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD register from the beginning of the component. */
989 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_OFST 0x24
990 
991 /*
992  * Register : Probe_SoC2FPGA_main_Probe_StatGo
993  *
994  *
995  * Register Layout
996  *
997  * Bits | Access | Reset | Description
998  * :-------|:-------|:--------|:---------------------------------------
999  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO
1000  * [31:1] | ??? | Unknown | *UNDEFINED*
1001  *
1002  */
1003 /*
1004  * Field : STATGO
1005  *
1006  * Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The
1007  * register is active when statistics collection operates in manual mode, that is,
1008  * when register StatPeriod is set to 0.NOTE The written value is not stored in
1009  * StatGo. A read always returns 0.
1010  *
1011  * Field Access Macros:
1012  *
1013  */
1014 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO register field. */
1015 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_LSB 0
1016 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO register field. */
1017 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_MSB 0
1018 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO register field. */
1019 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_WIDTH 1
1020 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO register field value. */
1021 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_SET_MSK 0x00000001
1022 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO register field value. */
1023 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_CLR_MSK 0xfffffffe
1024 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO register field. */
1025 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_RESET 0x0
1026 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO field value from a register. */
1027 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_GET(value) (((value) & 0x00000001) >> 0)
1028 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO register field value suitable for setting the register. */
1029 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_SET(value) (((value) << 0) & 0x00000001)
1030 
1031 #ifndef __ASSEMBLY__
1032 /*
1033  * WARNING: The C register and register group struct declarations are provided for
1034  * convenience and illustrative purposes. They should, however, be used with
1035  * caution as the C language standard provides no guarantees about the alignment or
1036  * atomicity of device memory accesses. The recommended practice for writing
1037  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1038  * alt_write_word() functions.
1039  *
1040  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATGO.
1041  */
1042 struct ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_s
1043 {
1044  uint32_t STATGO : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO */
1045  uint32_t : 31; /* *UNDEFINED* */
1046 };
1047 
1048 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATGO. */
1049 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_s ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_t;
1050 #endif /* __ASSEMBLY__ */
1051 
1052 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATGO register. */
1053 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_RESET 0x00000000
1054 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_STATGO register from the beginning of the component. */
1055 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_OFST 0x28
1056 
1057 /*
1058  * Register : Probe_SoC2FPGA_main_Probe_StatAlarmMin
1059  *
1060  *
1061  * Register Layout
1062  *
1063  * Bits | Access | Reset | Description
1064  * :-------|:-------|:------|:---------------------------------------------------
1065  * [31:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN
1066  *
1067  */
1068 /*
1069  * Field : STATALARMMIN
1070  *
1071  * Register StatAlarmMin contains the minimum count value used in statistics alarm
1072  * comparisons. The number of bits is equal to twice the value set forparameter
1073  * wStatisticsCounter. When parameter statisticsCounterAlarm is set to False,
1074  * StatAlarmMin is reserved.
1075  *
1076  * Field Access Macros:
1077  *
1078  */
1079 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN register field. */
1080 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_LSB 0
1081 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN register field. */
1082 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_MSB 31
1083 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN register field. */
1084 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_WIDTH 32
1085 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN register field value. */
1086 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_SET_MSK 0xffffffff
1087 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN register field value. */
1088 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_CLR_MSK 0x00000000
1089 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN register field. */
1090 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_RESET 0x0
1091 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN field value from a register. */
1092 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_GET(value) (((value) & 0xffffffff) >> 0)
1093 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN register field value suitable for setting the register. */
1094 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_SET(value) (((value) << 0) & 0xffffffff)
1095 
1096 #ifndef __ASSEMBLY__
1097 /*
1098  * WARNING: The C register and register group struct declarations are provided for
1099  * convenience and illustrative purposes. They should, however, be used with
1100  * caution as the C language standard provides no guarantees about the alignment or
1101  * atomicity of device memory accesses. The recommended practice for writing
1102  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1103  * alt_write_word() functions.
1104  *
1105  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN.
1106  */
1107 struct ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_s
1108 {
1109  uint32_t STATALARMMIN : 32; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN */
1110 };
1111 
1112 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN. */
1113 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_s ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_t;
1114 #endif /* __ASSEMBLY__ */
1115 
1116 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN register. */
1117 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_RESET 0x00000000
1118 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN register from the beginning of the component. */
1119 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_OFST 0x2c
1120 
1121 /*
1122  * Register : Probe_SoC2FPGA_main_Probe_StatAlarmMax
1123  *
1124  *
1125  * Register Layout
1126  *
1127  * Bits | Access | Reset | Description
1128  * :-------|:-------|:------|:---------------------------------------------------
1129  * [31:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX
1130  *
1131  */
1132 /*
1133  * Field : STATALARMMAX
1134  *
1135  * Register StatAlarmMax contains the maximum count value used in statistics alarm
1136  * comparisons.The number of bits is equal to twice the value set for parameter
1137  * wStatisticsCounter. When parameter statisticsCounterAlarm is set to False,
1138  * StatAlarmMax is reserved.
1139  *
1140  * Field Access Macros:
1141  *
1142  */
1143 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX register field. */
1144 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_LSB 0
1145 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX register field. */
1146 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_MSB 31
1147 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX register field. */
1148 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_WIDTH 32
1149 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX register field value. */
1150 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_SET_MSK 0xffffffff
1151 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX register field value. */
1152 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_CLR_MSK 0x00000000
1153 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX register field. */
1154 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_RESET 0x0
1155 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX field value from a register. */
1156 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_GET(value) (((value) & 0xffffffff) >> 0)
1157 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX register field value suitable for setting the register. */
1158 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_SET(value) (((value) << 0) & 0xffffffff)
1159 
1160 #ifndef __ASSEMBLY__
1161 /*
1162  * WARNING: The C register and register group struct declarations are provided for
1163  * convenience and illustrative purposes. They should, however, be used with
1164  * caution as the C language standard provides no guarantees about the alignment or
1165  * atomicity of device memory accesses. The recommended practice for writing
1166  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1167  * alt_write_word() functions.
1168  *
1169  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX.
1170  */
1171 struct ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_s
1172 {
1173  uint32_t STATALARMMAX : 32; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX */
1174 };
1175 
1176 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX. */
1177 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_s ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_t;
1178 #endif /* __ASSEMBLY__ */
1179 
1180 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX register. */
1181 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_RESET 0x00000000
1182 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX register from the beginning of the component. */
1183 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_OFST 0x30
1184 
1185 /*
1186  * Register : Probe_SoC2FPGA_main_Probe_StatAlarmStatus
1187  *
1188  *
1189  * Register Layout
1190  *
1191  * Bits | Access | Reset | Description
1192  * :-------|:-------|:--------|:-----------------------------------------------------
1193  * [0] | R | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT
1194  * [31:1] | ??? | Unknown | *UNDEFINED*
1195  *
1196  */
1197 /*
1198  * Field : STATALARMSTATUS
1199  *
1200  * Register StatAlarmStatus is a read-only 1-bit register indicating that at least
1201  * one statistics counter has exceeded the programmed values for registers
1202  * StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values
1203  * stored in register MainCtl fields StatAlarmStatus and AlarmEn. When parameter
1204  * statisticsCounterAlarm is set to False, StatAlarmStatus is reserved.
1205  *
1206  * Field Access Macros:
1207  *
1208  */
1209 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT register field. */
1210 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_LSB 0
1211 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT register field. */
1212 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_MSB 0
1213 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT register field. */
1214 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_WIDTH 1
1215 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT register field value. */
1216 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_SET_MSK 0x00000001
1217 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT register field value. */
1218 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_CLR_MSK 0xfffffffe
1219 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT register field. */
1220 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_RESET 0x0
1221 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT field value from a register. */
1222 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_GET(value) (((value) & 0x00000001) >> 0)
1223 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT register field value suitable for setting the register. */
1224 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_SET(value) (((value) << 0) & 0x00000001)
1225 
1226 #ifndef __ASSEMBLY__
1227 /*
1228  * WARNING: The C register and register group struct declarations are provided for
1229  * convenience and illustrative purposes. They should, however, be used with
1230  * caution as the C language standard provides no guarantees about the alignment or
1231  * atomicity of device memory accesses. The recommended practice for writing
1232  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1233  * alt_write_word() functions.
1234  *
1235  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT.
1236  */
1237 struct ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_s
1238 {
1239  const uint32_t STATALARMSTATUS : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT */
1240  uint32_t : 31; /* *UNDEFINED* */
1241 };
1242 
1243 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT. */
1244 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_s ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_t;
1245 #endif /* __ASSEMBLY__ */
1246 
1247 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT register. */
1248 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_RESET 0x00000000
1249 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT register from the beginning of the component. */
1250 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_OFST 0x34
1251 
1252 /*
1253  * Register : Probe_SoC2FPGA_main_Probe_StatAlarmClr
1254  *
1255  *
1256  * Register Layout
1257  *
1258  * Bits | Access | Reset | Description
1259  * :-------|:-------|:--------|:---------------------------------------------------
1260  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR
1261  * [31:1] | ??? | Unknown | *UNDEFINED*
1262  *
1263  */
1264 /*
1265  * Field : STATALARMCLR
1266  *
1267  * Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears
1268  * the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to
1269  * False, StatAlarmClr is reserved.NOTE The written value is not stored in
1270  * StatAlarmClr. A read always returns 0.
1271  *
1272  * Field Access Macros:
1273  *
1274  */
1275 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR register field. */
1276 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_LSB 0
1277 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR register field. */
1278 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_MSB 0
1279 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR register field. */
1280 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_WIDTH 1
1281 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR register field value. */
1282 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_SET_MSK 0x00000001
1283 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR register field value. */
1284 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_CLR_MSK 0xfffffffe
1285 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR register field. */
1286 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_RESET 0x0
1287 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR field value from a register. */
1288 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_GET(value) (((value) & 0x00000001) >> 0)
1289 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR register field value suitable for setting the register. */
1290 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_SET(value) (((value) << 0) & 0x00000001)
1291 
1292 #ifndef __ASSEMBLY__
1293 /*
1294  * WARNING: The C register and register group struct declarations are provided for
1295  * convenience and illustrative purposes. They should, however, be used with
1296  * caution as the C language standard provides no guarantees about the alignment or
1297  * atomicity of device memory accesses. The recommended practice for writing
1298  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1299  * alt_write_word() functions.
1300  *
1301  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR.
1302  */
1303 struct ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_s
1304 {
1305  uint32_t STATALARMCLR : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR */
1306  uint32_t : 31; /* *UNDEFINED* */
1307 };
1308 
1309 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR. */
1310 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_s ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_t;
1311 #endif /* __ASSEMBLY__ */
1312 
1313 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR register. */
1314 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_RESET 0x00000000
1315 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR register from the beginning of the component. */
1316 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_OFST 0x38
1317 
1318 /*
1319  * Register : Probe_SoC2FPGA_main_Probe_StatAlarmEn
1320  *
1321  *
1322  * Register Layout
1323  *
1324  * Bits | Access | Reset | Description
1325  * :-------|:-------|:--------|:-------------------------------------------------
1326  * [0] | RW | 0x1 | ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN
1327  * [31:1] | ??? | Unknown | *UNDEFINED*
1328  *
1329  */
1330 /*
1331  * Field : STATALARMEN
1332  *
1333  * Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and
1334  * CtiTrigOut(1) signal interrupts.
1335  *
1336  * Field Access Macros:
1337  *
1338  */
1339 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN register field. */
1340 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_LSB 0
1341 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN register field. */
1342 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_MSB 0
1343 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN register field. */
1344 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_WIDTH 1
1345 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN register field value. */
1346 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_SET_MSK 0x00000001
1347 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN register field value. */
1348 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_CLR_MSK 0xfffffffe
1349 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN register field. */
1350 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_RESET 0x1
1351 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN field value from a register. */
1352 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_GET(value) (((value) & 0x00000001) >> 0)
1353 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN register field value suitable for setting the register. */
1354 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_SET(value) (((value) << 0) & 0x00000001)
1355 
1356 #ifndef __ASSEMBLY__
1357 /*
1358  * WARNING: The C register and register group struct declarations are provided for
1359  * convenience and illustrative purposes. They should, however, be used with
1360  * caution as the C language standard provides no guarantees about the alignment or
1361  * atomicity of device memory accesses. The recommended practice for writing
1362  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1363  * alt_write_word() functions.
1364  *
1365  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN.
1366  */
1367 struct ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_s
1368 {
1369  uint32_t STATALARMEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN */
1370  uint32_t : 31; /* *UNDEFINED* */
1371 };
1372 
1373 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN. */
1374 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_s ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_t;
1375 #endif /* __ASSEMBLY__ */
1376 
1377 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN register. */
1378 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_RESET 0x00000001
1379 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN register from the beginning of the component. */
1380 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_OFST 0x3c
1381 
1382 /*
1383  * Register : Probe_SoC2FPGA_main_Probe_Filters_0_RouteIdBase
1384  *
1385  *
1386  * Register Layout
1387  *
1388  * Bits | Access | Reset | Description
1389  * :--------|:-------|:--------|:---------------------------------------------------------------
1390  * [18:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE
1391  * [31:19] | ??? | Unknown | *UNDEFINED*
1392  *
1393  */
1394 /*
1395  * Field : FILTERS_0_ROUTEIDBASE
1396  *
1397  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
1398  * filter packets.
1399  *
1400  * Field Access Macros:
1401  *
1402  */
1403 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
1404 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_LSB 0
1405 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
1406 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_MSB 18
1407 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
1408 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_WIDTH 19
1409 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field value. */
1410 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET_MSK 0x0007ffff
1411 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field value. */
1412 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_CLR_MSK 0xfff80000
1413 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
1414 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_RESET 0x0
1415 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE field value from a register. */
1416 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
1417 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field value suitable for setting the register. */
1418 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
1419 
1420 #ifndef __ASSEMBLY__
1421 /*
1422  * WARNING: The C register and register group struct declarations are provided for
1423  * convenience and illustrative purposes. They should, however, be used with
1424  * caution as the C language standard provides no guarantees about the alignment or
1425  * atomicity of device memory accesses. The recommended practice for writing
1426  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1427  * alt_write_word() functions.
1428  *
1429  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE.
1430  */
1431 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_s
1432 {
1433  uint32_t FILTERS_0_ROUTEIDBASE : 19; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE */
1434  uint32_t : 13; /* *UNDEFINED* */
1435 };
1436 
1437 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE. */
1438 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_t;
1439 #endif /* __ASSEMBLY__ */
1440 
1441 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE register. */
1442 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_RESET 0x00000000
1443 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE register from the beginning of the component. */
1444 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_OFST 0x44
1445 
1446 /*
1447  * Register : Probe_SoC2FPGA_main_Probe_Filters_0_RouteIdMask
1448  *
1449  *
1450  * Register Layout
1451  *
1452  * Bits | Access | Reset | Description
1453  * :--------|:-------|:--------|:-------------------------------------------------------------
1454  * [18:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK
1455  * [31:19] | ??? | Unknown | *UNDEFINED*
1456  *
1457  */
1458 /*
1459  * Field : FILTERS_0_ROUTEIDMASK
1460  *
1461  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
1462  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
1463  * RouteIdMask = RouteIdBase & RouteIdMask.
1464  *
1465  * Field Access Macros:
1466  *
1467  */
1468 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
1469 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_LSB 0
1470 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
1471 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_MSB 18
1472 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
1473 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_WIDTH 19
1474 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field value. */
1475 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET_MSK 0x0007ffff
1476 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field value. */
1477 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_CLR_MSK 0xfff80000
1478 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
1479 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_RESET 0x0
1480 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK field value from a register. */
1481 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
1482 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field value suitable for setting the register. */
1483 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
1484 
1485 #ifndef __ASSEMBLY__
1486 /*
1487  * WARNING: The C register and register group struct declarations are provided for
1488  * convenience and illustrative purposes. They should, however, be used with
1489  * caution as the C language standard provides no guarantees about the alignment or
1490  * atomicity of device memory accesses. The recommended practice for writing
1491  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1492  * alt_write_word() functions.
1493  *
1494  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK.
1495  */
1496 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_s
1497 {
1498  uint32_t FILTERS_0_ROUTEIDMASK : 19; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK */
1499  uint32_t : 13; /* *UNDEFINED* */
1500 };
1501 
1502 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK. */
1503 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_t;
1504 #endif /* __ASSEMBLY__ */
1505 
1506 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK register. */
1507 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_RESET 0x00000000
1508 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK register from the beginning of the component. */
1509 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_OFST 0x48
1510 
1511 /*
1512  * Register : Probe_SoC2FPGA_main_Probe_Filters_0_AddrBase_Low
1513  *
1514  *
1515  * Register Layout
1516  *
1517  * Bits | Access | Reset | Description
1518  * :-------|:-------|:------|:-----------------------------------------------------------------
1519  * [31:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW
1520  *
1521  */
1522 /*
1523  * Field : FILTERS_0_ADDRBASE_LOW
1524  *
1525  * Address LSB register.
1526  *
1527  * Field Access Macros:
1528  *
1529  */
1530 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
1531 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_LSB 0
1532 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
1533 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_MSB 31
1534 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
1535 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_WIDTH 32
1536 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field value. */
1537 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET_MSK 0xffffffff
1538 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field value. */
1539 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_CLR_MSK 0x00000000
1540 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
1541 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_RESET 0x0
1542 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW field value from a register. */
1543 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
1544 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field value suitable for setting the register. */
1545 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
1546 
1547 #ifndef __ASSEMBLY__
1548 /*
1549  * WARNING: The C register and register group struct declarations are provided for
1550  * convenience and illustrative purposes. They should, however, be used with
1551  * caution as the C language standard provides no guarantees about the alignment or
1552  * atomicity of device memory accesses. The recommended practice for writing
1553  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1554  * alt_write_word() functions.
1555  *
1556  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW.
1557  */
1558 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_s
1559 {
1560  uint32_t FILTERS_0_ADDRBASE_LOW : 32; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW */
1561 };
1562 
1563 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW. */
1564 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_t;
1565 #endif /* __ASSEMBLY__ */
1566 
1567 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW register. */
1568 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_RESET 0x00000000
1569 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW register from the beginning of the component. */
1570 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_OFST 0x4c
1571 
1572 /*
1573  * Register : Probe_SoC2FPGA_main_Probe_Filters_0_WindowSize
1574  *
1575  *
1576  * Register Layout
1577  *
1578  * Bits | Access | Reset | Description
1579  * :-------|:-------|:--------|:-------------------------------------------------------------
1580  * [5:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE
1581  * [31:6] | ??? | Unknown | *UNDEFINED*
1582  *
1583  */
1584 /*
1585  * Field : FILTERS_0_WINDOWSIZE
1586  *
1587  * Register WindowSize contains the encoded address mask used to filter packets.
1588  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
1589  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
1590  * filteringof packets having an intersection with the AddrBase/WindowSize burst
1591  * aligned region, even if the region is smaller than the packet.
1592  *
1593  * Field Access Macros:
1594  *
1595  */
1596 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
1597 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_LSB 0
1598 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
1599 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_MSB 5
1600 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
1601 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_WIDTH 6
1602 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field value. */
1603 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET_MSK 0x0000003f
1604 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field value. */
1605 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_CLR_MSK 0xffffffc0
1606 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
1607 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_RESET 0x0
1608 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE field value from a register. */
1609 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
1610 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field value suitable for setting the register. */
1611 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
1612 
1613 #ifndef __ASSEMBLY__
1614 /*
1615  * WARNING: The C register and register group struct declarations are provided for
1616  * convenience and illustrative purposes. They should, however, be used with
1617  * caution as the C language standard provides no guarantees about the alignment or
1618  * atomicity of device memory accesses. The recommended practice for writing
1619  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1620  * alt_write_word() functions.
1621  *
1622  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE.
1623  */
1624 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_s
1625 {
1626  uint32_t FILTERS_0_WINDOWSIZE : 6; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE */
1627  uint32_t : 26; /* *UNDEFINED* */
1628 };
1629 
1630 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE. */
1631 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_t;
1632 #endif /* __ASSEMBLY__ */
1633 
1634 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE register. */
1635 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_RESET 0x00000000
1636 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE register from the beginning of the component. */
1637 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_OFST 0x54
1638 
1639 /*
1640  * Register : Probe_SoC2FPGA_main_Probe_Filters_0_SecurityBase
1641  *
1642  *
1643  * Register Layout
1644  *
1645  * Bits | Access | Reset | Description
1646  * :-------|:-------|:--------|:-----------------------------------------------------------------
1647  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE
1648  * [31:3] | ??? | Unknown | *UNDEFINED*
1649  *
1650  */
1651 /*
1652  * Field : FILTERS_0_SECURITYBASE
1653  *
1654  * Register SecurityBase contains the security base used to filter packets.
1655  *
1656  * Field Access Macros:
1657  *
1658  */
1659 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
1660 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_LSB 0
1661 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
1662 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_MSB 2
1663 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
1664 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_WIDTH 3
1665 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field value. */
1666 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET_MSK 0x00000007
1667 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field value. */
1668 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_CLR_MSK 0xfffffff8
1669 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
1670 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_RESET 0x0
1671 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE field value from a register. */
1672 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
1673 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field value suitable for setting the register. */
1674 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
1675 
1676 #ifndef __ASSEMBLY__
1677 /*
1678  * WARNING: The C register and register group struct declarations are provided for
1679  * convenience and illustrative purposes. They should, however, be used with
1680  * caution as the C language standard provides no guarantees about the alignment or
1681  * atomicity of device memory accesses. The recommended practice for writing
1682  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1683  * alt_write_word() functions.
1684  *
1685  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE.
1686  */
1687 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_s
1688 {
1689  uint32_t FILTERS_0_SECURITYBASE : 3; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE */
1690  uint32_t : 29; /* *UNDEFINED* */
1691 };
1692 
1693 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE. */
1694 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_t;
1695 #endif /* __ASSEMBLY__ */
1696 
1697 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE register. */
1698 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_RESET 0x00000000
1699 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE register from the beginning of the component. */
1700 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_OFST 0x58
1701 
1702 /*
1703  * Register : Probe_SoC2FPGA_main_Probe_Filters_0_SecurityMask
1704  *
1705  *
1706  * Register Layout
1707  *
1708  * Bits | Access | Reset | Description
1709  * :-------|:-------|:--------|:---------------------------------------------------------------
1710  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK
1711  * [31:3] | ??? | Unknown | *UNDEFINED*
1712  *
1713  */
1714 /*
1715  * Field : FILTERS_0_SECURITYMASK
1716  *
1717  * Register SecurityMask is contains the security mask used to filter packets. A
1718  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
1719  * SecurityMasks.
1720  *
1721  * Field Access Macros:
1722  *
1723  */
1724 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
1725 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_LSB 0
1726 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
1727 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_MSB 2
1728 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
1729 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_WIDTH 3
1730 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field value. */
1731 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET_MSK 0x00000007
1732 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field value. */
1733 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_CLR_MSK 0xfffffff8
1734 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
1735 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_RESET 0x0
1736 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK field value from a register. */
1737 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
1738 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field value suitable for setting the register. */
1739 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
1740 
1741 #ifndef __ASSEMBLY__
1742 /*
1743  * WARNING: The C register and register group struct declarations are provided for
1744  * convenience and illustrative purposes. They should, however, be used with
1745  * caution as the C language standard provides no guarantees about the alignment or
1746  * atomicity of device memory accesses. The recommended practice for writing
1747  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1748  * alt_write_word() functions.
1749  *
1750  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK.
1751  */
1752 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_s
1753 {
1754  uint32_t FILTERS_0_SECURITYMASK : 3; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK */
1755  uint32_t : 29; /* *UNDEFINED* */
1756 };
1757 
1758 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK. */
1759 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_t;
1760 #endif /* __ASSEMBLY__ */
1761 
1762 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK register. */
1763 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_RESET 0x00000000
1764 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK register from the beginning of the component. */
1765 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_OFST 0x5c
1766 
1767 /*
1768  * Register : Probe_SoC2FPGA_main_Probe_Filters_0_Opcode
1769  *
1770  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
1771  * based on packet opcodes (0 disables the filter):
1772  *
1773  * Register Layout
1774  *
1775  * Bits | Access | Reset | Description
1776  * :-------|:-------|:--------|:----------------------------------------------
1777  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN
1778  * [1] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN
1779  * [2] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN
1780  * [3] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN
1781  * [31:4] | ??? | Unknown | *UNDEFINED*
1782  *
1783  */
1784 /*
1785  * Field : RDEN
1786  *
1787  * Selects RD packets.
1788  *
1789  * Field Access Macros:
1790  *
1791  */
1792 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN register field. */
1793 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_LSB 0
1794 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN register field. */
1795 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_MSB 0
1796 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN register field. */
1797 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_WIDTH 1
1798 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN register field value. */
1799 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_SET_MSK 0x00000001
1800 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN register field value. */
1801 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_CLR_MSK 0xfffffffe
1802 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN register field. */
1803 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_RESET 0x0
1804 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN field value from a register. */
1805 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
1806 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN register field value suitable for setting the register. */
1807 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
1808 
1809 /*
1810  * Field : WREN
1811  *
1812  * Selects WR packets.
1813  *
1814  * Field Access Macros:
1815  *
1816  */
1817 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN register field. */
1818 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_LSB 1
1819 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN register field. */
1820 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_MSB 1
1821 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN register field. */
1822 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_WIDTH 1
1823 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN register field value. */
1824 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_SET_MSK 0x00000002
1825 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN register field value. */
1826 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_CLR_MSK 0xfffffffd
1827 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN register field. */
1828 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_RESET 0x0
1829 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN field value from a register. */
1830 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
1831 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN register field value suitable for setting the register. */
1832 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
1833 
1834 /*
1835  * Field : LOCKEN
1836  *
1837  * Selects RDX-WR, RDL, WRC and Linked sequence.
1838  *
1839  * Field Access Macros:
1840  *
1841  */
1842 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN register field. */
1843 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_LSB 2
1844 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN register field. */
1845 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_MSB 2
1846 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN register field. */
1847 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_WIDTH 1
1848 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN register field value. */
1849 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_SET_MSK 0x00000004
1850 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN register field value. */
1851 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
1852 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN register field. */
1853 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_RESET 0x0
1854 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN field value from a register. */
1855 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
1856 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN register field value suitable for setting the register. */
1857 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
1858 
1859 /*
1860  * Field : URGEN
1861  *
1862  * Selects URG packets (urgency).
1863  *
1864  * Field Access Macros:
1865  *
1866  */
1867 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN register field. */
1868 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_LSB 3
1869 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN register field. */
1870 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_MSB 3
1871 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN register field. */
1872 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_WIDTH 1
1873 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN register field value. */
1874 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_SET_MSK 0x00000008
1875 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN register field value. */
1876 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_CLR_MSK 0xfffffff7
1877 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN register field. */
1878 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_RESET 0x0
1879 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN field value from a register. */
1880 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
1881 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN register field value suitable for setting the register. */
1882 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
1883 
1884 #ifndef __ASSEMBLY__
1885 /*
1886  * WARNING: The C register and register group struct declarations are provided for
1887  * convenience and illustrative purposes. They should, however, be used with
1888  * caution as the C language standard provides no guarantees about the alignment or
1889  * atomicity of device memory accesses. The recommended practice for writing
1890  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1891  * alt_write_word() functions.
1892  *
1893  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE.
1894  */
1895 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_s
1896 {
1897  uint32_t RDEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN */
1898  uint32_t WREN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN */
1899  uint32_t LOCKEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN */
1900  uint32_t URGEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN */
1901  uint32_t : 28; /* *UNDEFINED* */
1902 };
1903 
1904 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE. */
1905 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_t;
1906 #endif /* __ASSEMBLY__ */
1907 
1908 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE register. */
1909 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RESET 0x00000000
1910 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE register from the beginning of the component. */
1911 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_OFST 0x60
1912 
1913 /*
1914  * Register : Probe_SoC2FPGA_main_Probe_Filters_0_Status
1915  *
1916  * Register Status is 2-bit register that selects candidate packets based on packet
1917  * status.
1918  *
1919  * Register Layout
1920  *
1921  * Bits | Access | Reset | Description
1922  * :-------|:-------|:--------|:-------------------------------------------
1923  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN
1924  * [1] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN
1925  * [31:2] | ??? | Unknown | *UNDEFINED*
1926  *
1927  */
1928 /*
1929  * Field : REQEN
1930  *
1931  * Selects REQ status packets.
1932  *
1933  * Field Access Macros:
1934  *
1935  */
1936 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN register field. */
1937 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_LSB 0
1938 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN register field. */
1939 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_MSB 0
1940 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN register field. */
1941 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_WIDTH 1
1942 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN register field value. */
1943 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_SET_MSK 0x00000001
1944 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN register field value. */
1945 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_CLR_MSK 0xfffffffe
1946 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN register field. */
1947 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_RESET 0x0
1948 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN field value from a register. */
1949 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
1950 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN register field value suitable for setting the register. */
1951 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
1952 
1953 /*
1954  * Field : RSPEN
1955  *
1956  * Selects RSP and FAIL-CONT status packets.
1957  *
1958  * Field Access Macros:
1959  *
1960  */
1961 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN register field. */
1962 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_LSB 1
1963 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN register field. */
1964 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_MSB 1
1965 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN register field. */
1966 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_WIDTH 1
1967 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN register field value. */
1968 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_SET_MSK 0x00000002
1969 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN register field value. */
1970 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_CLR_MSK 0xfffffffd
1971 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN register field. */
1972 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_RESET 0x0
1973 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN field value from a register. */
1974 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
1975 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN register field value suitable for setting the register. */
1976 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
1977 
1978 #ifndef __ASSEMBLY__
1979 /*
1980  * WARNING: The C register and register group struct declarations are provided for
1981  * convenience and illustrative purposes. They should, however, be used with
1982  * caution as the C language standard provides no guarantees about the alignment or
1983  * atomicity of device memory accesses. The recommended practice for writing
1984  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1985  * alt_write_word() functions.
1986  *
1987  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT.
1988  */
1989 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_s
1990 {
1991  uint32_t REQEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN */
1992  uint32_t RSPEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN */
1993  uint32_t : 30; /* *UNDEFINED* */
1994 };
1995 
1996 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT. */
1997 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_t;
1998 #endif /* __ASSEMBLY__ */
1999 
2000 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT register. */
2001 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RESET 0x00000000
2002 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT register from the beginning of the component. */
2003 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_OFST 0x64
2004 
2005 /*
2006  * Register : Probe_SoC2FPGA_main_Probe_Filters_0_Length
2007  *
2008  *
2009  * Register Layout
2010  *
2011  * Bits | Access | Reset | Description
2012  * :-------|:-------|:--------|:-----------------------------------------------
2013  * [3:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN
2014  * [31:4] | ??? | Unknown | *UNDEFINED*
2015  *
2016  */
2017 /*
2018  * Field : FILTERS_0_LENGTH
2019  *
2020  * Register Length is 4-bit register that selects candidate packets if their number
2021  * of bytes is less than or equal to 2**Length.
2022  *
2023  * Field Access Macros:
2024  *
2025  */
2026 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN register field. */
2027 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_LSB 0
2028 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN register field. */
2029 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_MSB 3
2030 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN register field. */
2031 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_WIDTH 4
2032 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN register field value. */
2033 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_SET_MSK 0x0000000f
2034 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN register field value. */
2035 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_CLR_MSK 0xfffffff0
2036 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN register field. */
2037 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_RESET 0x0
2038 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN field value from a register. */
2039 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_GET(value) (((value) & 0x0000000f) >> 0)
2040 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN register field value suitable for setting the register. */
2041 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_SET(value) (((value) << 0) & 0x0000000f)
2042 
2043 #ifndef __ASSEMBLY__
2044 /*
2045  * WARNING: The C register and register group struct declarations are provided for
2046  * convenience and illustrative purposes. They should, however, be used with
2047  * caution as the C language standard provides no guarantees about the alignment or
2048  * atomicity of device memory accesses. The recommended practice for writing
2049  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2050  * alt_write_word() functions.
2051  *
2052  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN.
2053  */
2054 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_s
2055 {
2056  uint32_t FILTERS_0_LENGTH : 4; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN */
2057  uint32_t : 28; /* *UNDEFINED* */
2058 };
2059 
2060 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN. */
2061 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_t;
2062 #endif /* __ASSEMBLY__ */
2063 
2064 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN register. */
2065 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_RESET 0x00000000
2066 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN register from the beginning of the component. */
2067 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_OFST 0x68
2068 
2069 /*
2070  * Register : Probe_SoC2FPGA_main_Probe_Filters_0_Urgency
2071  *
2072  *
2073  * Register Layout
2074  *
2075  * Bits | Access | Reset | Description
2076  * :-------|:-------|:--------|:-------------------------------------------------------
2077  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY
2078  * [31:2] | ??? | Unknown | *UNDEFINED*
2079  *
2080  */
2081 /*
2082  * Field : FILTERS_0_URGENCY
2083  *
2084  * Register Urgency contains the minimum urgency level used to filter packets. A
2085  * packet is a candidate when its socket urgency is greater than or equal to the
2086  * urgency specified in the register.
2087  *
2088  * Field Access Macros:
2089  *
2090  */
2091 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
2092 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_LSB 0
2093 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
2094 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_MSB 1
2095 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
2096 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_WIDTH 2
2097 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field value. */
2098 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_SET_MSK 0x00000003
2099 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field value. */
2100 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_CLR_MSK 0xfffffffc
2101 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
2102 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_RESET 0x0
2103 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY field value from a register. */
2104 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2105 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field value suitable for setting the register. */
2106 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2107 
2108 #ifndef __ASSEMBLY__
2109 /*
2110  * WARNING: The C register and register group struct declarations are provided for
2111  * convenience and illustrative purposes. They should, however, be used with
2112  * caution as the C language standard provides no guarantees about the alignment or
2113  * atomicity of device memory accesses. The recommended practice for writing
2114  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2115  * alt_write_word() functions.
2116  *
2117  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY.
2118  */
2119 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_s
2120 {
2121  uint32_t FILTERS_0_URGENCY : 2; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY */
2122  uint32_t : 30; /* *UNDEFINED* */
2123 };
2124 
2125 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY. */
2126 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_t;
2127 #endif /* __ASSEMBLY__ */
2128 
2129 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY register. */
2130 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_RESET 0x00000000
2131 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY register from the beginning of the component. */
2132 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_OFST 0x6c
2133 
2134 /*
2135  * Register : Probe_SoC2FPGA_main_Probe_Filters_1_RouteIdBase
2136  *
2137  *
2138  * Register Layout
2139  *
2140  * Bits | Access | Reset | Description
2141  * :--------|:-------|:--------|:---------------------------------------------------------------
2142  * [18:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE
2143  * [31:19] | ??? | Unknown | *UNDEFINED*
2144  *
2145  */
2146 /*
2147  * Field : FILTERS_1_ROUTEIDBASE
2148  *
2149  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
2150  * filter packets.
2151  *
2152  * Field Access Macros:
2153  *
2154  */
2155 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field. */
2156 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_LSB 0
2157 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field. */
2158 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_MSB 18
2159 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field. */
2160 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_WIDTH 19
2161 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field value. */
2162 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET_MSK 0x0007ffff
2163 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field value. */
2164 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_CLR_MSK 0xfff80000
2165 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field. */
2166 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_RESET 0x0
2167 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE field value from a register. */
2168 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
2169 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field value suitable for setting the register. */
2170 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
2171 
2172 #ifndef __ASSEMBLY__
2173 /*
2174  * WARNING: The C register and register group struct declarations are provided for
2175  * convenience and illustrative purposes. They should, however, be used with
2176  * caution as the C language standard provides no guarantees about the alignment or
2177  * atomicity of device memory accesses. The recommended practice for writing
2178  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2179  * alt_write_word() functions.
2180  *
2181  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE.
2182  */
2183 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_s
2184 {
2185  uint32_t FILTERS_1_ROUTEIDBASE : 19; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE */
2186  uint32_t : 13; /* *UNDEFINED* */
2187 };
2188 
2189 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE. */
2190 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_t;
2191 #endif /* __ASSEMBLY__ */
2192 
2193 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE register. */
2194 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_RESET 0x00000000
2195 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE register from the beginning of the component. */
2196 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_OFST 0x80
2197 
2198 /*
2199  * Register : Probe_SoC2FPGA_main_Probe_Filters_1_RouteIdMask
2200  *
2201  *
2202  * Register Layout
2203  *
2204  * Bits | Access | Reset | Description
2205  * :--------|:-------|:--------|:-------------------------------------------------------------
2206  * [18:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK
2207  * [31:19] | ??? | Unknown | *UNDEFINED*
2208  *
2209  */
2210 /*
2211  * Field : FILTERS_1_ROUTEIDMASK
2212  *
2213  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
2214  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
2215  * RouteIdMask = RouteIdBase & RouteIdMask.
2216  *
2217  * Field Access Macros:
2218  *
2219  */
2220 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field. */
2221 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_LSB 0
2222 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field. */
2223 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_MSB 18
2224 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field. */
2225 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_WIDTH 19
2226 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field value. */
2227 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET_MSK 0x0007ffff
2228 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field value. */
2229 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_CLR_MSK 0xfff80000
2230 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field. */
2231 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_RESET 0x0
2232 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK field value from a register. */
2233 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
2234 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field value suitable for setting the register. */
2235 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
2236 
2237 #ifndef __ASSEMBLY__
2238 /*
2239  * WARNING: The C register and register group struct declarations are provided for
2240  * convenience and illustrative purposes. They should, however, be used with
2241  * caution as the C language standard provides no guarantees about the alignment or
2242  * atomicity of device memory accesses. The recommended practice for writing
2243  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2244  * alt_write_word() functions.
2245  *
2246  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK.
2247  */
2248 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_s
2249 {
2250  uint32_t FILTERS_1_ROUTEIDMASK : 19; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK */
2251  uint32_t : 13; /* *UNDEFINED* */
2252 };
2253 
2254 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK. */
2255 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_t;
2256 #endif /* __ASSEMBLY__ */
2257 
2258 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK register. */
2259 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_RESET 0x00000000
2260 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK register from the beginning of the component. */
2261 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_OFST 0x84
2262 
2263 /*
2264  * Register : Probe_SoC2FPGA_main_Probe_Filters_1_AddrBase_Low
2265  *
2266  *
2267  * Register Layout
2268  *
2269  * Bits | Access | Reset | Description
2270  * :-------|:-------|:------|:-----------------------------------------------------------------
2271  * [31:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW
2272  *
2273  */
2274 /*
2275  * Field : FILTERS_1_ADDRBASE_LOW
2276  *
2277  * Address LSB register.
2278  *
2279  * Field Access Macros:
2280  *
2281  */
2282 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field. */
2283 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_LSB 0
2284 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field. */
2285 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_MSB 31
2286 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field. */
2287 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_WIDTH 32
2288 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field value. */
2289 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET_MSK 0xffffffff
2290 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field value. */
2291 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_CLR_MSK 0x00000000
2292 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field. */
2293 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_RESET 0x0
2294 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW field value from a register. */
2295 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
2296 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field value suitable for setting the register. */
2297 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
2298 
2299 #ifndef __ASSEMBLY__
2300 /*
2301  * WARNING: The C register and register group struct declarations are provided for
2302  * convenience and illustrative purposes. They should, however, be used with
2303  * caution as the C language standard provides no guarantees about the alignment or
2304  * atomicity of device memory accesses. The recommended practice for writing
2305  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2306  * alt_write_word() functions.
2307  *
2308  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW.
2309  */
2310 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_s
2311 {
2312  uint32_t FILTERS_1_ADDRBASE_LOW : 32; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW */
2313 };
2314 
2315 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW. */
2316 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_t;
2317 #endif /* __ASSEMBLY__ */
2318 
2319 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW register. */
2320 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_RESET 0x00000000
2321 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW register from the beginning of the component. */
2322 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_OFST 0x88
2323 
2324 /*
2325  * Register : Probe_SoC2FPGA_main_Probe_Filters_1_WindowSize
2326  *
2327  *
2328  * Register Layout
2329  *
2330  * Bits | Access | Reset | Description
2331  * :-------|:-------|:--------|:-------------------------------------------------------------
2332  * [5:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE
2333  * [31:6] | ??? | Unknown | *UNDEFINED*
2334  *
2335  */
2336 /*
2337  * Field : FILTERS_1_WINDOWSIZE
2338  *
2339  * Register WindowSize contains the encoded address mask used to filter packets.
2340  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
2341  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
2342  * filteringof packets having an intersection with the AddrBase/WindowSize burst
2343  * aligned region, even if the region is smaller than the packet.
2344  *
2345  * Field Access Macros:
2346  *
2347  */
2348 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field. */
2349 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_LSB 0
2350 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field. */
2351 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_MSB 5
2352 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field. */
2353 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_WIDTH 6
2354 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field value. */
2355 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET_MSK 0x0000003f
2356 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field value. */
2357 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_CLR_MSK 0xffffffc0
2358 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field. */
2359 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_RESET 0x0
2360 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE field value from a register. */
2361 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
2362 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field value suitable for setting the register. */
2363 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
2364 
2365 #ifndef __ASSEMBLY__
2366 /*
2367  * WARNING: The C register and register group struct declarations are provided for
2368  * convenience and illustrative purposes. They should, however, be used with
2369  * caution as the C language standard provides no guarantees about the alignment or
2370  * atomicity of device memory accesses. The recommended practice for writing
2371  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2372  * alt_write_word() functions.
2373  *
2374  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE.
2375  */
2376 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_s
2377 {
2378  uint32_t FILTERS_1_WINDOWSIZE : 6; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE */
2379  uint32_t : 26; /* *UNDEFINED* */
2380 };
2381 
2382 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE. */
2383 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_t;
2384 #endif /* __ASSEMBLY__ */
2385 
2386 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE register. */
2387 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_RESET 0x00000000
2388 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE register from the beginning of the component. */
2389 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_OFST 0x90
2390 
2391 /*
2392  * Register : Probe_SoC2FPGA_main_Probe_Filters_1_SecurityBase
2393  *
2394  *
2395  * Register Layout
2396  *
2397  * Bits | Access | Reset | Description
2398  * :-------|:-------|:--------|:-----------------------------------------------------------------
2399  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE
2400  * [31:3] | ??? | Unknown | *UNDEFINED*
2401  *
2402  */
2403 /*
2404  * Field : FILTERS_1_SECURITYBASE
2405  *
2406  * Register SecurityBase contains the security base used to filter packets.
2407  *
2408  * Field Access Macros:
2409  *
2410  */
2411 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field. */
2412 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_LSB 0
2413 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field. */
2414 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_MSB 2
2415 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field. */
2416 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_WIDTH 3
2417 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field value. */
2418 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET_MSK 0x00000007
2419 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field value. */
2420 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_CLR_MSK 0xfffffff8
2421 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field. */
2422 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_RESET 0x0
2423 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE field value from a register. */
2424 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
2425 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field value suitable for setting the register. */
2426 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
2427 
2428 #ifndef __ASSEMBLY__
2429 /*
2430  * WARNING: The C register and register group struct declarations are provided for
2431  * convenience and illustrative purposes. They should, however, be used with
2432  * caution as the C language standard provides no guarantees about the alignment or
2433  * atomicity of device memory accesses. The recommended practice for writing
2434  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2435  * alt_write_word() functions.
2436  *
2437  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE.
2438  */
2439 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_s
2440 {
2441  uint32_t FILTERS_1_SECURITYBASE : 3; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE */
2442  uint32_t : 29; /* *UNDEFINED* */
2443 };
2444 
2445 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE. */
2446 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_t;
2447 #endif /* __ASSEMBLY__ */
2448 
2449 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE register. */
2450 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_RESET 0x00000000
2451 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE register from the beginning of the component. */
2452 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_OFST 0x94
2453 
2454 /*
2455  * Register : Probe_SoC2FPGA_main_Probe_Filters_1_SecurityMask
2456  *
2457  *
2458  * Register Layout
2459  *
2460  * Bits | Access | Reset | Description
2461  * :-------|:-------|:--------|:---------------------------------------------------------------
2462  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK
2463  * [31:3] | ??? | Unknown | *UNDEFINED*
2464  *
2465  */
2466 /*
2467  * Field : FILTERS_1_SECURITYMASK
2468  *
2469  * Register SecurityMask is contains the security mask used to filter packets. A
2470  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
2471  * SecurityMasks.
2472  *
2473  * Field Access Macros:
2474  *
2475  */
2476 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field. */
2477 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_LSB 0
2478 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field. */
2479 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_MSB 2
2480 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field. */
2481 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_WIDTH 3
2482 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field value. */
2483 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET_MSK 0x00000007
2484 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field value. */
2485 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_CLR_MSK 0xfffffff8
2486 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field. */
2487 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_RESET 0x0
2488 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK field value from a register. */
2489 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
2490 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field value suitable for setting the register. */
2491 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
2492 
2493 #ifndef __ASSEMBLY__
2494 /*
2495  * WARNING: The C register and register group struct declarations are provided for
2496  * convenience and illustrative purposes. They should, however, be used with
2497  * caution as the C language standard provides no guarantees about the alignment or
2498  * atomicity of device memory accesses. The recommended practice for writing
2499  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2500  * alt_write_word() functions.
2501  *
2502  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK.
2503  */
2504 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_s
2505 {
2506  uint32_t FILTERS_1_SECURITYMASK : 3; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK */
2507  uint32_t : 29; /* *UNDEFINED* */
2508 };
2509 
2510 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK. */
2511 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_t;
2512 #endif /* __ASSEMBLY__ */
2513 
2514 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK register. */
2515 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_RESET 0x00000000
2516 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK register from the beginning of the component. */
2517 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_OFST 0x98
2518 
2519 /*
2520  * Register : Probe_SoC2FPGA_main_Probe_Filters_1_Opcode
2521  *
2522  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
2523  * based on packet opcodes (0 disables the filter):
2524  *
2525  * Register Layout
2526  *
2527  * Bits | Access | Reset | Description
2528  * :-------|:-------|:--------|:----------------------------------------------
2529  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN
2530  * [1] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN
2531  * [2] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN
2532  * [3] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN
2533  * [31:4] | ??? | Unknown | *UNDEFINED*
2534  *
2535  */
2536 /*
2537  * Field : RDEN
2538  *
2539  * Selects RD packets.
2540  *
2541  * Field Access Macros:
2542  *
2543  */
2544 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field. */
2545 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_LSB 0
2546 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field. */
2547 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_MSB 0
2548 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field. */
2549 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_WIDTH 1
2550 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field value. */
2551 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_SET_MSK 0x00000001
2552 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field value. */
2553 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_CLR_MSK 0xfffffffe
2554 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field. */
2555 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_RESET 0x0
2556 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN field value from a register. */
2557 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
2558 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field value suitable for setting the register. */
2559 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
2560 
2561 /*
2562  * Field : WREN
2563  *
2564  * Selects WR packets.
2565  *
2566  * Field Access Macros:
2567  *
2568  */
2569 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field. */
2570 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_LSB 1
2571 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field. */
2572 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_MSB 1
2573 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field. */
2574 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_WIDTH 1
2575 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field value. */
2576 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_SET_MSK 0x00000002
2577 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field value. */
2578 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_CLR_MSK 0xfffffffd
2579 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field. */
2580 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_RESET 0x0
2581 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN field value from a register. */
2582 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
2583 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field value suitable for setting the register. */
2584 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
2585 
2586 /*
2587  * Field : LOCKEN
2588  *
2589  * Selects RDX-WR, RDL, WRC and Linked sequence.
2590  *
2591  * Field Access Macros:
2592  *
2593  */
2594 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field. */
2595 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_LSB 2
2596 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field. */
2597 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_MSB 2
2598 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field. */
2599 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_WIDTH 1
2600 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field value. */
2601 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_SET_MSK 0x00000004
2602 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field value. */
2603 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
2604 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field. */
2605 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_RESET 0x0
2606 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN field value from a register. */
2607 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
2608 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field value suitable for setting the register. */
2609 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
2610 
2611 /*
2612  * Field : URGEN
2613  *
2614  * Selects URG packets (urgency).
2615  *
2616  * Field Access Macros:
2617  *
2618  */
2619 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field. */
2620 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_LSB 3
2621 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field. */
2622 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_MSB 3
2623 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field. */
2624 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_WIDTH 1
2625 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field value. */
2626 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_SET_MSK 0x00000008
2627 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field value. */
2628 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_CLR_MSK 0xfffffff7
2629 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field. */
2630 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_RESET 0x0
2631 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN field value from a register. */
2632 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
2633 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field value suitable for setting the register. */
2634 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
2635 
2636 #ifndef __ASSEMBLY__
2637 /*
2638  * WARNING: The C register and register group struct declarations are provided for
2639  * convenience and illustrative purposes. They should, however, be used with
2640  * caution as the C language standard provides no guarantees about the alignment or
2641  * atomicity of device memory accesses. The recommended practice for writing
2642  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2643  * alt_write_word() functions.
2644  *
2645  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE.
2646  */
2647 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_s
2648 {
2649  uint32_t RDEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN */
2650  uint32_t WREN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN */
2651  uint32_t LOCKEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN */
2652  uint32_t URGEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN */
2653  uint32_t : 28; /* *UNDEFINED* */
2654 };
2655 
2656 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE. */
2657 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_t;
2658 #endif /* __ASSEMBLY__ */
2659 
2660 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE register. */
2661 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RESET 0x00000000
2662 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE register from the beginning of the component. */
2663 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_OFST 0x9c
2664 
2665 /*
2666  * Register : Probe_SoC2FPGA_main_Probe_Filters_1_Status
2667  *
2668  * Register Status is 2-bit register that selects candidate packets based on packet
2669  * status.
2670  *
2671  * Register Layout
2672  *
2673  * Bits | Access | Reset | Description
2674  * :-------|:-------|:--------|:-------------------------------------------
2675  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN
2676  * [1] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN
2677  * [31:2] | ??? | Unknown | *UNDEFINED*
2678  *
2679  */
2680 /*
2681  * Field : REQEN
2682  *
2683  * Selects REQ status packets.
2684  *
2685  * Field Access Macros:
2686  *
2687  */
2688 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN register field. */
2689 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_LSB 0
2690 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN register field. */
2691 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_MSB 0
2692 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN register field. */
2693 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_WIDTH 1
2694 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN register field value. */
2695 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_SET_MSK 0x00000001
2696 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN register field value. */
2697 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_CLR_MSK 0xfffffffe
2698 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN register field. */
2699 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_RESET 0x0
2700 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN field value from a register. */
2701 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
2702 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN register field value suitable for setting the register. */
2703 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
2704 
2705 /*
2706  * Field : RSPEN
2707  *
2708  * Selects RSP and FAIL-CONT status packets.
2709  *
2710  * Field Access Macros:
2711  *
2712  */
2713 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN register field. */
2714 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_LSB 1
2715 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN register field. */
2716 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_MSB 1
2717 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN register field. */
2718 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_WIDTH 1
2719 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN register field value. */
2720 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_SET_MSK 0x00000002
2721 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN register field value. */
2722 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_CLR_MSK 0xfffffffd
2723 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN register field. */
2724 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_RESET 0x0
2725 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN field value from a register. */
2726 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
2727 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN register field value suitable for setting the register. */
2728 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
2729 
2730 #ifndef __ASSEMBLY__
2731 /*
2732  * WARNING: The C register and register group struct declarations are provided for
2733  * convenience and illustrative purposes. They should, however, be used with
2734  * caution as the C language standard provides no guarantees about the alignment or
2735  * atomicity of device memory accesses. The recommended practice for writing
2736  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2737  * alt_write_word() functions.
2738  *
2739  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT.
2740  */
2741 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_s
2742 {
2743  uint32_t REQEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN */
2744  uint32_t RSPEN : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN */
2745  uint32_t : 30; /* *UNDEFINED* */
2746 };
2747 
2748 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT. */
2749 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_t;
2750 #endif /* __ASSEMBLY__ */
2751 
2752 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT register. */
2753 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RESET 0x00000000
2754 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT register from the beginning of the component. */
2755 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_OFST 0xa0
2756 
2757 /*
2758  * Register : Probe_SoC2FPGA_main_Probe_Filters_1_Length
2759  *
2760  *
2761  * Register Layout
2762  *
2763  * Bits | Access | Reset | Description
2764  * :-------|:-------|:--------|:-----------------------------------------------
2765  * [3:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN
2766  * [31:4] | ??? | Unknown | *UNDEFINED*
2767  *
2768  */
2769 /*
2770  * Field : FILTERS_1_LENGTH
2771  *
2772  * Register Length is 4-bit register that selects candidate packets if their number
2773  * of bytes is less than or equal to 2**Length.
2774  *
2775  * Field Access Macros:
2776  *
2777  */
2778 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN register field. */
2779 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_LSB 0
2780 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN register field. */
2781 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_MSB 3
2782 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN register field. */
2783 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_WIDTH 4
2784 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN register field value. */
2785 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_SET_MSK 0x0000000f
2786 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN register field value. */
2787 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_CLR_MSK 0xfffffff0
2788 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN register field. */
2789 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_RESET 0x0
2790 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN field value from a register. */
2791 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_GET(value) (((value) & 0x0000000f) >> 0)
2792 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN register field value suitable for setting the register. */
2793 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_SET(value) (((value) << 0) & 0x0000000f)
2794 
2795 #ifndef __ASSEMBLY__
2796 /*
2797  * WARNING: The C register and register group struct declarations are provided for
2798  * convenience and illustrative purposes. They should, however, be used with
2799  * caution as the C language standard provides no guarantees about the alignment or
2800  * atomicity of device memory accesses. The recommended practice for writing
2801  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2802  * alt_write_word() functions.
2803  *
2804  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN.
2805  */
2806 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_s
2807 {
2808  uint32_t FILTERS_1_LENGTH : 4; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN */
2809  uint32_t : 28; /* *UNDEFINED* */
2810 };
2811 
2812 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN. */
2813 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_t;
2814 #endif /* __ASSEMBLY__ */
2815 
2816 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN register. */
2817 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_RESET 0x00000000
2818 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN register from the beginning of the component. */
2819 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_OFST 0xa4
2820 
2821 /*
2822  * Register : Probe_SoC2FPGA_main_Probe_Filters_1_Urgency
2823  *
2824  *
2825  * Register Layout
2826  *
2827  * Bits | Access | Reset | Description
2828  * :-------|:-------|:--------|:-------------------------------------------------------
2829  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY
2830  * [31:2] | ??? | Unknown | *UNDEFINED*
2831  *
2832  */
2833 /*
2834  * Field : FILTERS_1_URGENCY
2835  *
2836  * Register Urgency contains the minimum urgency level used to filter packets. A
2837  * packet is a candidate when its socket urgency is greater than or equal to the
2838  * urgency specified in the register.
2839  *
2840  * Field Access Macros:
2841  *
2842  */
2843 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field. */
2844 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_LSB 0
2845 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field. */
2846 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_MSB 1
2847 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field. */
2848 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_WIDTH 2
2849 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field value. */
2850 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_SET_MSK 0x00000003
2851 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field value. */
2852 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_CLR_MSK 0xfffffffc
2853 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field. */
2854 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_RESET 0x0
2855 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY field value from a register. */
2856 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2857 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field value suitable for setting the register. */
2858 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2859 
2860 #ifndef __ASSEMBLY__
2861 /*
2862  * WARNING: The C register and register group struct declarations are provided for
2863  * convenience and illustrative purposes. They should, however, be used with
2864  * caution as the C language standard provides no guarantees about the alignment or
2865  * atomicity of device memory accesses. The recommended practice for writing
2866  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2867  * alt_write_word() functions.
2868  *
2869  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY.
2870  */
2871 struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_s
2872 {
2873  uint32_t FILTERS_1_URGENCY : 2; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY */
2874  uint32_t : 30; /* *UNDEFINED* */
2875 };
2876 
2877 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY. */
2878 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_s ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_t;
2879 #endif /* __ASSEMBLY__ */
2880 
2881 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY register. */
2882 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_RESET 0x00000000
2883 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY register from the beginning of the component. */
2884 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_OFST 0xa8
2885 
2886 /*
2887  * Register : Probe_SoC2FPGA_main_Probe_Counters_0_PortSel
2888  *
2889  *
2890  * Register Layout
2891  *
2892  * Bits | Access | Reset | Description
2893  * :-------|:-------|:--------|:---------------------------------------------------------
2894  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL
2895  * [31:1] | ??? | Unknown | *UNDEFINED*
2896  *
2897  */
2898 /*
2899  * Field : COUNTERS_0_PORTSEL
2900  *
2901  * Register PortSel indicates which NTTP link is associated with the counter. The
2902  * register can be changed at any time, with the change effective immediately. The
2903  * LUT and FILTx sources do not depend on this NTTP port selection.
2904  *
2905  * Field Access Macros:
2906  *
2907  */
2908 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field. */
2909 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_LSB 0
2910 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field. */
2911 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_MSB 0
2912 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field. */
2913 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_WIDTH 1
2914 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field value. */
2915 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_SET_MSK 0x00000001
2916 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field value. */
2917 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_CLR_MSK 0xfffffffe
2918 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field. */
2919 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_RESET 0x0
2920 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL field value from a register. */
2921 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
2922 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field value suitable for setting the register. */
2923 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
2924 
2925 #ifndef __ASSEMBLY__
2926 /*
2927  * WARNING: The C register and register group struct declarations are provided for
2928  * convenience and illustrative purposes. They should, however, be used with
2929  * caution as the C language standard provides no guarantees about the alignment or
2930  * atomicity of device memory accesses. The recommended practice for writing
2931  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2932  * alt_write_word() functions.
2933  *
2934  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL.
2935  */
2936 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_s
2937 {
2938  uint32_t COUNTERS_0_PORTSEL : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL */
2939  uint32_t : 31; /* *UNDEFINED* */
2940 };
2941 
2942 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL. */
2943 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_t;
2944 #endif /* __ASSEMBLY__ */
2945 
2946 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL register. */
2947 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_RESET 0x00000000
2948 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL register from the beginning of the component. */
2949 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_OFST 0x134
2950 
2951 /*
2952  * Register : Probe_SoC2FPGA_main_Probe_Counters_0_Src
2953  *
2954  * Register CntSrc indicates the event source used to increment the counter.
2955  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
2956  * Filter) are equivalent to OFF.
2957  *
2958  * Register Layout
2959  *
2960  * Bits | Access | Reset | Description
2961  * :-------|:-------|:--------|:----------------------------------------------
2962  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT
2963  * [31:5] | ??? | Unknown | *UNDEFINED*
2964  *
2965  */
2966 /*
2967  * Field : INTEVENT
2968  *
2969  * Internal packet event
2970  *
2971  * Field Access Macros:
2972  *
2973  */
2974 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT register field. */
2975 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_LSB 0
2976 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT register field. */
2977 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_MSB 4
2978 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT register field. */
2979 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_WIDTH 5
2980 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT register field value. */
2981 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_SET_MSK 0x0000001f
2982 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT register field value. */
2983 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_CLR_MSK 0xffffffe0
2984 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT register field. */
2985 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_RESET 0x0
2986 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT field value from a register. */
2987 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
2988 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT register field value suitable for setting the register. */
2989 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
2990 
2991 #ifndef __ASSEMBLY__
2992 /*
2993  * WARNING: The C register and register group struct declarations are provided for
2994  * convenience and illustrative purposes. They should, however, be used with
2995  * caution as the C language standard provides no guarantees about the alignment or
2996  * atomicity of device memory accesses. The recommended practice for writing
2997  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2998  * alt_write_word() functions.
2999  *
3000  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC.
3001  */
3002 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_s
3003 {
3004  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT */
3005  uint32_t : 27; /* *UNDEFINED* */
3006 };
3007 
3008 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC. */
3009 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_t;
3010 #endif /* __ASSEMBLY__ */
3011 
3012 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC register. */
3013 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_RESET 0x00000000
3014 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC register from the beginning of the component. */
3015 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_OFST 0x138
3016 
3017 /*
3018  * Register : Probe_SoC2FPGA_main_Probe_Counters_0_AlarmMode
3019  *
3020  *
3021  * Register Layout
3022  *
3023  * Bits | Access | Reset | Description
3024  * :-------|:-------|:--------|:-----------------------------------------------------------
3025  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD
3026  * [31:2] | ??? | Unknown | *UNDEFINED*
3027  *
3028  */
3029 /*
3030  * Field : COUNTERS_0_ALARMMODE
3031  *
3032  * Register AlarmMode is a 2-bit register that is present when parameter
3033  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
3034  * behavior of the counter.
3035  *
3036  * Field Access Macros:
3037  *
3038  */
3039 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
3040 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_LSB 0
3041 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
3042 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_MSB 1
3043 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
3044 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_WIDTH 2
3045 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field value. */
3046 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET_MSK 0x00000003
3047 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field value. */
3048 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_CLR_MSK 0xfffffffc
3049 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
3050 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_RESET 0x0
3051 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD field value from a register. */
3052 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
3053 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field value suitable for setting the register. */
3054 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
3055 
3056 #ifndef __ASSEMBLY__
3057 /*
3058  * WARNING: The C register and register group struct declarations are provided for
3059  * convenience and illustrative purposes. They should, however, be used with
3060  * caution as the C language standard provides no guarantees about the alignment or
3061  * atomicity of device memory accesses. The recommended practice for writing
3062  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3063  * alt_write_word() functions.
3064  *
3065  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD.
3066  */
3067 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_s
3068 {
3069  uint32_t COUNTERS_0_ALARMMODE : 2; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD */
3070  uint32_t : 30; /* *UNDEFINED* */
3071 };
3072 
3073 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD. */
3074 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_t;
3075 #endif /* __ASSEMBLY__ */
3076 
3077 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD register. */
3078 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_RESET 0x00000000
3079 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD register from the beginning of the component. */
3080 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_OFST 0x13c
3081 
3082 /*
3083  * Register : Probe_SoC2FPGA_main_Probe_Counters_0_Val
3084  *
3085  *
3086  * Register Layout
3087  *
3088  * Bits | Access | Reset | Description
3089  * :--------|:-------|:--------|:-------------------------------------------------
3090  * [15:0] | R | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL
3091  * [31:16] | ??? | Unknown | *UNDEFINED*
3092  *
3093  */
3094 /*
3095  * Field : COUNTERS_0_VAL
3096  *
3097  * Register Val is a read-only register that is always present. The register
3098  * containsthe statistics counter value either pending StatAlarm output, or when
3099  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
3100  *
3101  * Field Access Macros:
3102  *
3103  */
3104 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field. */
3105 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_LSB 0
3106 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field. */
3107 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_MSB 15
3108 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field. */
3109 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_WIDTH 16
3110 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field value. */
3111 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET_MSK 0x0000ffff
3112 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field value. */
3113 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_CLR_MSK 0xffff0000
3114 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field. */
3115 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_RESET 0x0
3116 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL field value from a register. */
3117 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
3118 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field value suitable for setting the register. */
3119 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET(value) (((value) << 0) & 0x0000ffff)
3120 
3121 #ifndef __ASSEMBLY__
3122 /*
3123  * WARNING: The C register and register group struct declarations are provided for
3124  * convenience and illustrative purposes. They should, however, be used with
3125  * caution as the C language standard provides no guarantees about the alignment or
3126  * atomicity of device memory accesses. The recommended practice for writing
3127  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3128  * alt_write_word() functions.
3129  *
3130  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL.
3131  */
3132 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_s
3133 {
3134  const uint32_t COUNTERS_0_VAL : 16; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL */
3135  uint32_t : 16; /* *UNDEFINED* */
3136 };
3137 
3138 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL. */
3139 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_t;
3140 #endif /* __ASSEMBLY__ */
3141 
3142 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL register. */
3143 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_RESET 0x00000000
3144 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL register from the beginning of the component. */
3145 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_OFST 0x140
3146 
3147 /*
3148  * Register : Probe_SoC2FPGA_main_Probe_Counters_1_PortSel
3149  *
3150  *
3151  * Register Layout
3152  *
3153  * Bits | Access | Reset | Description
3154  * :-------|:-------|:--------|:---------------------------------------------------------
3155  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL
3156  * [31:1] | ??? | Unknown | *UNDEFINED*
3157  *
3158  */
3159 /*
3160  * Field : COUNTERS_1_PORTSEL
3161  *
3162  * Register PortSel indicates which NTTP link is associated with the counter. The
3163  * register can be changed at any time, with the change effective immediately. The
3164  * LUT and FILTx sources do not depend on this NTTP port selection.
3165  *
3166  * Field Access Macros:
3167  *
3168  */
3169 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field. */
3170 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_LSB 0
3171 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field. */
3172 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_MSB 0
3173 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field. */
3174 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_WIDTH 1
3175 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field value. */
3176 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_SET_MSK 0x00000001
3177 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field value. */
3178 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_CLR_MSK 0xfffffffe
3179 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field. */
3180 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_RESET 0x0
3181 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL field value from a register. */
3182 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
3183 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field value suitable for setting the register. */
3184 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
3185 
3186 #ifndef __ASSEMBLY__
3187 /*
3188  * WARNING: The C register and register group struct declarations are provided for
3189  * convenience and illustrative purposes. They should, however, be used with
3190  * caution as the C language standard provides no guarantees about the alignment or
3191  * atomicity of device memory accesses. The recommended practice for writing
3192  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3193  * alt_write_word() functions.
3194  *
3195  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL.
3196  */
3197 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_s
3198 {
3199  uint32_t COUNTERS_1_PORTSEL : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL */
3200  uint32_t : 31; /* *UNDEFINED* */
3201 };
3202 
3203 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL. */
3204 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_t;
3205 #endif /* __ASSEMBLY__ */
3206 
3207 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL register. */
3208 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_RESET 0x00000000
3209 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL register from the beginning of the component. */
3210 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_OFST 0x148
3211 
3212 /*
3213  * Register : Probe_SoC2FPGA_main_Probe_Counters_1_Src
3214  *
3215  * Register CntSrc indicates the event source used to increment the counter.
3216  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
3217  * Filter) are equivalent to OFF.
3218  *
3219  * Register Layout
3220  *
3221  * Bits | Access | Reset | Description
3222  * :-------|:-------|:--------|:----------------------------------------------
3223  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT
3224  * [31:5] | ??? | Unknown | *UNDEFINED*
3225  *
3226  */
3227 /*
3228  * Field : INTEVENT
3229  *
3230  * Internal packet event
3231  *
3232  * Field Access Macros:
3233  *
3234  */
3235 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT register field. */
3236 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_LSB 0
3237 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT register field. */
3238 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_MSB 4
3239 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT register field. */
3240 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_WIDTH 5
3241 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT register field value. */
3242 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_SET_MSK 0x0000001f
3243 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT register field value. */
3244 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_CLR_MSK 0xffffffe0
3245 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT register field. */
3246 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_RESET 0x0
3247 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT field value from a register. */
3248 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
3249 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT register field value suitable for setting the register. */
3250 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
3251 
3252 #ifndef __ASSEMBLY__
3253 /*
3254  * WARNING: The C register and register group struct declarations are provided for
3255  * convenience and illustrative purposes. They should, however, be used with
3256  * caution as the C language standard provides no guarantees about the alignment or
3257  * atomicity of device memory accesses. The recommended practice for writing
3258  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3259  * alt_write_word() functions.
3260  *
3261  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC.
3262  */
3263 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_s
3264 {
3265  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT */
3266  uint32_t : 27; /* *UNDEFINED* */
3267 };
3268 
3269 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC. */
3270 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_t;
3271 #endif /* __ASSEMBLY__ */
3272 
3273 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC register. */
3274 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_RESET 0x00000000
3275 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC register from the beginning of the component. */
3276 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_OFST 0x14c
3277 
3278 /*
3279  * Register : Probe_SoC2FPGA_main_Probe_Counters_1_AlarmMode
3280  *
3281  *
3282  * Register Layout
3283  *
3284  * Bits | Access | Reset | Description
3285  * :-------|:-------|:--------|:-----------------------------------------------------------
3286  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD
3287  * [31:2] | ??? | Unknown | *UNDEFINED*
3288  *
3289  */
3290 /*
3291  * Field : COUNTERS_1_ALARMMODE
3292  *
3293  * Register AlarmMode is a 2-bit register that is present when parameter
3294  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
3295  * behavior of the counter.
3296  *
3297  * Field Access Macros:
3298  *
3299  */
3300 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
3301 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_LSB 0
3302 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
3303 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_MSB 1
3304 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
3305 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_WIDTH 2
3306 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field value. */
3307 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET_MSK 0x00000003
3308 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field value. */
3309 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_CLR_MSK 0xfffffffc
3310 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
3311 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_RESET 0x0
3312 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD field value from a register. */
3313 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
3314 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field value suitable for setting the register. */
3315 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
3316 
3317 #ifndef __ASSEMBLY__
3318 /*
3319  * WARNING: The C register and register group struct declarations are provided for
3320  * convenience and illustrative purposes. They should, however, be used with
3321  * caution as the C language standard provides no guarantees about the alignment or
3322  * atomicity of device memory accesses. The recommended practice for writing
3323  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3324  * alt_write_word() functions.
3325  *
3326  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD.
3327  */
3328 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_s
3329 {
3330  uint32_t COUNTERS_1_ALARMMODE : 2; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD */
3331  uint32_t : 30; /* *UNDEFINED* */
3332 };
3333 
3334 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD. */
3335 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_t;
3336 #endif /* __ASSEMBLY__ */
3337 
3338 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD register. */
3339 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_RESET 0x00000000
3340 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD register from the beginning of the component. */
3341 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_OFST 0x150
3342 
3343 /*
3344  * Register : Probe_SoC2FPGA_main_Probe_Counters_1_Val
3345  *
3346  *
3347  * Register Layout
3348  *
3349  * Bits | Access | Reset | Description
3350  * :--------|:-------|:--------|:-------------------------------------------------
3351  * [15:0] | R | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL
3352  * [31:16] | ??? | Unknown | *UNDEFINED*
3353  *
3354  */
3355 /*
3356  * Field : COUNTERS_1_VAL
3357  *
3358  * Register Val is a read-only register that is always present. The register
3359  * containsthe statistics counter value either pending StatAlarm output, or when
3360  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
3361  *
3362  * Field Access Macros:
3363  *
3364  */
3365 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field. */
3366 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_LSB 0
3367 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field. */
3368 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_MSB 15
3369 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field. */
3370 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_WIDTH 16
3371 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field value. */
3372 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_SET_MSK 0x0000ffff
3373 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field value. */
3374 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_CLR_MSK 0xffff0000
3375 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field. */
3376 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_RESET 0x0
3377 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL field value from a register. */
3378 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
3379 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field value suitable for setting the register. */
3380 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_SET(value) (((value) << 0) & 0x0000ffff)
3381 
3382 #ifndef __ASSEMBLY__
3383 /*
3384  * WARNING: The C register and register group struct declarations are provided for
3385  * convenience and illustrative purposes. They should, however, be used with
3386  * caution as the C language standard provides no guarantees about the alignment or
3387  * atomicity of device memory accesses. The recommended practice for writing
3388  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3389  * alt_write_word() functions.
3390  *
3391  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL.
3392  */
3393 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_s
3394 {
3395  const uint32_t COUNTERS_1_VAL : 16; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL */
3396  uint32_t : 16; /* *UNDEFINED* */
3397 };
3398 
3399 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL. */
3400 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_t;
3401 #endif /* __ASSEMBLY__ */
3402 
3403 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL register. */
3404 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_RESET 0x00000000
3405 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL register from the beginning of the component. */
3406 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_OFST 0x154
3407 
3408 /*
3409  * Register : Probe_SoC2FPGA_main_Probe_Counters_2_PortSel
3410  *
3411  *
3412  * Register Layout
3413  *
3414  * Bits | Access | Reset | Description
3415  * :-------|:-------|:--------|:---------------------------------------------------------
3416  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL
3417  * [31:1] | ??? | Unknown | *UNDEFINED*
3418  *
3419  */
3420 /*
3421  * Field : COUNTERS_2_PORTSEL
3422  *
3423  * Register PortSel indicates which NTTP link is associated with the counter. The
3424  * register can be changed at any time, with the change effective immediately. The
3425  * LUT and FILTx sources do not depend on this NTTP port selection.
3426  *
3427  * Field Access Macros:
3428  *
3429  */
3430 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field. */
3431 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_LSB 0
3432 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field. */
3433 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_MSB 0
3434 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field. */
3435 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_WIDTH 1
3436 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field value. */
3437 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_SET_MSK 0x00000001
3438 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field value. */
3439 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_CLR_MSK 0xfffffffe
3440 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field. */
3441 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_RESET 0x0
3442 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL field value from a register. */
3443 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
3444 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field value suitable for setting the register. */
3445 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
3446 
3447 #ifndef __ASSEMBLY__
3448 /*
3449  * WARNING: The C register and register group struct declarations are provided for
3450  * convenience and illustrative purposes. They should, however, be used with
3451  * caution as the C language standard provides no guarantees about the alignment or
3452  * atomicity of device memory accesses. The recommended practice for writing
3453  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3454  * alt_write_word() functions.
3455  *
3456  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL.
3457  */
3458 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_s
3459 {
3460  uint32_t COUNTERS_2_PORTSEL : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL */
3461  uint32_t : 31; /* *UNDEFINED* */
3462 };
3463 
3464 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL. */
3465 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_t;
3466 #endif /* __ASSEMBLY__ */
3467 
3468 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL register. */
3469 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_RESET 0x00000000
3470 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL register from the beginning of the component. */
3471 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_OFST 0x15c
3472 
3473 /*
3474  * Register : Probe_SoC2FPGA_main_Probe_Counters_2_Src
3475  *
3476  * Register CntSrc indicates the event source used to increment the counter.
3477  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
3478  * Filter) are equivalent to OFF.
3479  *
3480  * Register Layout
3481  *
3482  * Bits | Access | Reset | Description
3483  * :-------|:-------|:--------|:----------------------------------------------
3484  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT
3485  * [31:5] | ??? | Unknown | *UNDEFINED*
3486  *
3487  */
3488 /*
3489  * Field : INTEVENT
3490  *
3491  * Internal packet event
3492  *
3493  * Field Access Macros:
3494  *
3495  */
3496 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT register field. */
3497 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_LSB 0
3498 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT register field. */
3499 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_MSB 4
3500 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT register field. */
3501 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_WIDTH 5
3502 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT register field value. */
3503 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_SET_MSK 0x0000001f
3504 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT register field value. */
3505 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_CLR_MSK 0xffffffe0
3506 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT register field. */
3507 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_RESET 0x0
3508 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT field value from a register. */
3509 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
3510 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT register field value suitable for setting the register. */
3511 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
3512 
3513 #ifndef __ASSEMBLY__
3514 /*
3515  * WARNING: The C register and register group struct declarations are provided for
3516  * convenience and illustrative purposes. They should, however, be used with
3517  * caution as the C language standard provides no guarantees about the alignment or
3518  * atomicity of device memory accesses. The recommended practice for writing
3519  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3520  * alt_write_word() functions.
3521  *
3522  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC.
3523  */
3524 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_s
3525 {
3526  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT */
3527  uint32_t : 27; /* *UNDEFINED* */
3528 };
3529 
3530 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC. */
3531 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_t;
3532 #endif /* __ASSEMBLY__ */
3533 
3534 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC register. */
3535 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_RESET 0x00000000
3536 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC register from the beginning of the component. */
3537 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_OFST 0x160
3538 
3539 /*
3540  * Register : Probe_SoC2FPGA_main_Probe_Counters_2_AlarmMode
3541  *
3542  *
3543  * Register Layout
3544  *
3545  * Bits | Access | Reset | Description
3546  * :-------|:-------|:--------|:-----------------------------------------------------------
3547  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD
3548  * [31:2] | ??? | Unknown | *UNDEFINED*
3549  *
3550  */
3551 /*
3552  * Field : COUNTERS_2_ALARMMODE
3553  *
3554  * Register AlarmMode is a 2-bit register that is present when parameter
3555  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
3556  * behavior of the counter.
3557  *
3558  * Field Access Macros:
3559  *
3560  */
3561 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field. */
3562 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_LSB 0
3563 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field. */
3564 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_MSB 1
3565 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field. */
3566 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_WIDTH 2
3567 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field value. */
3568 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_SET_MSK 0x00000003
3569 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field value. */
3570 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_CLR_MSK 0xfffffffc
3571 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field. */
3572 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_RESET 0x0
3573 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD field value from a register. */
3574 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
3575 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field value suitable for setting the register. */
3576 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
3577 
3578 #ifndef __ASSEMBLY__
3579 /*
3580  * WARNING: The C register and register group struct declarations are provided for
3581  * convenience and illustrative purposes. They should, however, be used with
3582  * caution as the C language standard provides no guarantees about the alignment or
3583  * atomicity of device memory accesses. The recommended practice for writing
3584  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3585  * alt_write_word() functions.
3586  *
3587  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD.
3588  */
3589 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_s
3590 {
3591  uint32_t COUNTERS_2_ALARMMODE : 2; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD */
3592  uint32_t : 30; /* *UNDEFINED* */
3593 };
3594 
3595 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD. */
3596 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_t;
3597 #endif /* __ASSEMBLY__ */
3598 
3599 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD register. */
3600 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_RESET 0x00000000
3601 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD register from the beginning of the component. */
3602 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_OFST 0x164
3603 
3604 /*
3605  * Register : Probe_SoC2FPGA_main_Probe_Counters_2_Val
3606  *
3607  *
3608  * Register Layout
3609  *
3610  * Bits | Access | Reset | Description
3611  * :--------|:-------|:--------|:-------------------------------------------------
3612  * [15:0] | R | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL
3613  * [31:16] | ??? | Unknown | *UNDEFINED*
3614  *
3615  */
3616 /*
3617  * Field : COUNTERS_2_VAL
3618  *
3619  * Register Val is a read-only register that is always present. The register
3620  * containsthe statistics counter value either pending StatAlarm output, or when
3621  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
3622  *
3623  * Field Access Macros:
3624  *
3625  */
3626 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field. */
3627 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_LSB 0
3628 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field. */
3629 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_MSB 15
3630 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field. */
3631 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_WIDTH 16
3632 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field value. */
3633 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_SET_MSK 0x0000ffff
3634 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field value. */
3635 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_CLR_MSK 0xffff0000
3636 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field. */
3637 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_RESET 0x0
3638 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL field value from a register. */
3639 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
3640 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field value suitable for setting the register. */
3641 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_SET(value) (((value) << 0) & 0x0000ffff)
3642 
3643 #ifndef __ASSEMBLY__
3644 /*
3645  * WARNING: The C register and register group struct declarations are provided for
3646  * convenience and illustrative purposes. They should, however, be used with
3647  * caution as the C language standard provides no guarantees about the alignment or
3648  * atomicity of device memory accesses. The recommended practice for writing
3649  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3650  * alt_write_word() functions.
3651  *
3652  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL.
3653  */
3654 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_s
3655 {
3656  const uint32_t COUNTERS_2_VAL : 16; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL */
3657  uint32_t : 16; /* *UNDEFINED* */
3658 };
3659 
3660 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL. */
3661 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_t;
3662 #endif /* __ASSEMBLY__ */
3663 
3664 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL register. */
3665 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_RESET 0x00000000
3666 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL register from the beginning of the component. */
3667 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_OFST 0x168
3668 
3669 /*
3670  * Register : Probe_SoC2FPGA_main_Probe_Counters_3_PortSel
3671  *
3672  *
3673  * Register Layout
3674  *
3675  * Bits | Access | Reset | Description
3676  * :-------|:-------|:--------|:---------------------------------------------------------
3677  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL
3678  * [31:1] | ??? | Unknown | *UNDEFINED*
3679  *
3680  */
3681 /*
3682  * Field : COUNTERS_3_PORTSEL
3683  *
3684  * Register PortSel indicates which NTTP link is associated with the counter. The
3685  * register can be changed at any time, with the change effective immediately. The
3686  * LUT and FILTx sources do not depend on this NTTP port selection.
3687  *
3688  * Field Access Macros:
3689  *
3690  */
3691 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field. */
3692 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_LSB 0
3693 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field. */
3694 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_MSB 0
3695 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field. */
3696 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_WIDTH 1
3697 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field value. */
3698 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_SET_MSK 0x00000001
3699 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field value. */
3700 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_CLR_MSK 0xfffffffe
3701 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field. */
3702 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_RESET 0x0
3703 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL field value from a register. */
3704 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
3705 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field value suitable for setting the register. */
3706 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
3707 
3708 #ifndef __ASSEMBLY__
3709 /*
3710  * WARNING: The C register and register group struct declarations are provided for
3711  * convenience and illustrative purposes. They should, however, be used with
3712  * caution as the C language standard provides no guarantees about the alignment or
3713  * atomicity of device memory accesses. The recommended practice for writing
3714  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3715  * alt_write_word() functions.
3716  *
3717  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL.
3718  */
3719 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_s
3720 {
3721  uint32_t COUNTERS_3_PORTSEL : 1; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL */
3722  uint32_t : 31; /* *UNDEFINED* */
3723 };
3724 
3725 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL. */
3726 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_t;
3727 #endif /* __ASSEMBLY__ */
3728 
3729 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL register. */
3730 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_RESET 0x00000000
3731 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL register from the beginning of the component. */
3732 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_OFST 0x170
3733 
3734 /*
3735  * Register : Probe_SoC2FPGA_main_Probe_Counters_3_Src
3736  *
3737  * Register CntSrc indicates the event source used to increment the counter.
3738  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
3739  * Filter) are equivalent to OFF.
3740  *
3741  * Register Layout
3742  *
3743  * Bits | Access | Reset | Description
3744  * :-------|:-------|:--------|:----------------------------------------------
3745  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT
3746  * [31:5] | ??? | Unknown | *UNDEFINED*
3747  *
3748  */
3749 /*
3750  * Field : INTEVENT
3751  *
3752  * Internal packet event
3753  *
3754  * Field Access Macros:
3755  *
3756  */
3757 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT register field. */
3758 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_LSB 0
3759 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT register field. */
3760 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_MSB 4
3761 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT register field. */
3762 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_WIDTH 5
3763 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT register field value. */
3764 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_SET_MSK 0x0000001f
3765 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT register field value. */
3766 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_CLR_MSK 0xffffffe0
3767 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT register field. */
3768 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_RESET 0x0
3769 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT field value from a register. */
3770 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
3771 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT register field value suitable for setting the register. */
3772 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
3773 
3774 #ifndef __ASSEMBLY__
3775 /*
3776  * WARNING: The C register and register group struct declarations are provided for
3777  * convenience and illustrative purposes. They should, however, be used with
3778  * caution as the C language standard provides no guarantees about the alignment or
3779  * atomicity of device memory accesses. The recommended practice for writing
3780  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3781  * alt_write_word() functions.
3782  *
3783  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC.
3784  */
3785 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_s
3786 {
3787  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT */
3788  uint32_t : 27; /* *UNDEFINED* */
3789 };
3790 
3791 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC. */
3792 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_t;
3793 #endif /* __ASSEMBLY__ */
3794 
3795 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC register. */
3796 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_RESET 0x00000000
3797 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC register from the beginning of the component. */
3798 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_OFST 0x174
3799 
3800 /*
3801  * Register : Probe_SoC2FPGA_main_Probe_Counters_3_AlarmMode
3802  *
3803  *
3804  * Register Layout
3805  *
3806  * Bits | Access | Reset | Description
3807  * :-------|:-------|:--------|:-----------------------------------------------------------
3808  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD
3809  * [31:2] | ??? | Unknown | *UNDEFINED*
3810  *
3811  */
3812 /*
3813  * Field : COUNTERS_3_ALARMMODE
3814  *
3815  * Register AlarmMode is a 2-bit register that is present when parameter
3816  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
3817  * behavior of the counter.
3818  *
3819  * Field Access Macros:
3820  *
3821  */
3822 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field. */
3823 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_LSB 0
3824 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field. */
3825 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_MSB 1
3826 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field. */
3827 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_WIDTH 2
3828 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field value. */
3829 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_SET_MSK 0x00000003
3830 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field value. */
3831 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_CLR_MSK 0xfffffffc
3832 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field. */
3833 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_RESET 0x0
3834 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD field value from a register. */
3835 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
3836 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field value suitable for setting the register. */
3837 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
3838 
3839 #ifndef __ASSEMBLY__
3840 /*
3841  * WARNING: The C register and register group struct declarations are provided for
3842  * convenience and illustrative purposes. They should, however, be used with
3843  * caution as the C language standard provides no guarantees about the alignment or
3844  * atomicity of device memory accesses. The recommended practice for writing
3845  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3846  * alt_write_word() functions.
3847  *
3848  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD.
3849  */
3850 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_s
3851 {
3852  uint32_t COUNTERS_3_ALARMMODE : 2; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD */
3853  uint32_t : 30; /* *UNDEFINED* */
3854 };
3855 
3856 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD. */
3857 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_t;
3858 #endif /* __ASSEMBLY__ */
3859 
3860 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD register. */
3861 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_RESET 0x00000000
3862 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD register from the beginning of the component. */
3863 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_OFST 0x178
3864 
3865 /*
3866  * Register : Probe_SoC2FPGA_main_Probe_Counters_3_Val
3867  *
3868  *
3869  * Register Layout
3870  *
3871  * Bits | Access | Reset | Description
3872  * :--------|:-------|:--------|:-------------------------------------------------
3873  * [15:0] | R | 0x0 | ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL
3874  * [31:16] | ??? | Unknown | *UNDEFINED*
3875  *
3876  */
3877 /*
3878  * Field : COUNTERS_3_VAL
3879  *
3880  * Register Val is a read-only register that is always present. The register
3881  * containsthe statistics counter value either pending StatAlarm output, or when
3882  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
3883  *
3884  * Field Access Macros:
3885  *
3886  */
3887 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field. */
3888 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_LSB 0
3889 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field. */
3890 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_MSB 15
3891 /* The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field. */
3892 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_WIDTH 16
3893 /* The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field value. */
3894 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_SET_MSK 0x0000ffff
3895 /* The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field value. */
3896 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_CLR_MSK 0xffff0000
3897 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field. */
3898 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_RESET 0x0
3899 /* Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL field value from a register. */
3900 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
3901 /* Produces a ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field value suitable for setting the register. */
3902 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_SET(value) (((value) << 0) & 0x0000ffff)
3903 
3904 #ifndef __ASSEMBLY__
3905 /*
3906  * WARNING: The C register and register group struct declarations are provided for
3907  * convenience and illustrative purposes. They should, however, be used with
3908  * caution as the C language standard provides no guarantees about the alignment or
3909  * atomicity of device memory accesses. The recommended practice for writing
3910  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3911  * alt_write_word() functions.
3912  *
3913  * The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL.
3914  */
3915 struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_s
3916 {
3917  const uint32_t COUNTERS_3_VAL : 16; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL */
3918  uint32_t : 16; /* *UNDEFINED* */
3919 };
3920 
3921 /* The typedef declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL. */
3922 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_s ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_t;
3923 #endif /* __ASSEMBLY__ */
3924 
3925 /* The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL register. */
3926 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_RESET 0x00000000
3927 /* The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL register from the beginning of the component. */
3928 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_OFST 0x17c
3929 
3930 #ifndef __ASSEMBLY__
3931 /*
3932  * WARNING: The C register and register group struct declarations are provided for
3933  * convenience and illustrative purposes. They should, however, be used with
3934  * caution as the C language standard provides no guarantees about the alignment or
3935  * atomicity of device memory accesses. The recommended practice for writing
3936  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3937  * alt_write_word() functions.
3938  *
3939  * The struct declaration for register group ALT_NOC_MPU_PRB_H2F_MAIN_PRB.
3940  */
3941 struct ALT_NOC_MPU_PRB_H2F_MAIN_PRB_s
3942 {
3943  ALT_NOC_MPU_PRB_H2F_MAIN_COREID_t Probe_SoC2FPGA_main_Probe_Id_CoreId; /* ALT_NOC_MPU_PRB_H2F_MAIN_COREID */
3944  ALT_NOC_MPU_PRB_H2F_MAIN_REVID_t Probe_SoC2FPGA_main_Probe_Id_RevisionId; /* ALT_NOC_MPU_PRB_H2F_MAIN_REVID */
3945  ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_t Probe_SoC2FPGA_main_Probe_MainCtl; /* ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL */
3946  ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_t Probe_SoC2FPGA_main_Probe_CfgCtl; /* ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL */
3947  ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_t Probe_SoC2FPGA_main_Probe_TracePortSel; /* ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL */
3948  ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_t Probe_SoC2FPGA_main_Probe_FilterLut; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT */
3949  ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_t Probe_SoC2FPGA_main_Probe_TraceAlarmEn; /* ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN */
3950  ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_t Probe_SoC2FPGA_main_Probe_TraceAlarmStatus; /* ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT */
3951  ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_t Probe_SoC2FPGA_main_Probe_TraceAlarmClr; /* ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR */
3952  ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_t Probe_SoC2FPGA_main_Probe_StatPeriod; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD */
3953  ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_t Probe_SoC2FPGA_main_Probe_StatGo; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATGO */
3954  ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_t Probe_SoC2FPGA_main_Probe_StatAlarmMin; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN */
3955  ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_t Probe_SoC2FPGA_main_Probe_StatAlarmMax; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX */
3956  ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_t Probe_SoC2FPGA_main_Probe_StatAlarmStatus; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT */
3957  ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_t Probe_SoC2FPGA_main_Probe_StatAlarmClr; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR */
3958  ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_t Probe_SoC2FPGA_main_Probe_StatAlarmEn; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN */
3959  volatile uint32_t _pad_0x40_0x43; /* *UNDEFINED* */
3960  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_t Probe_SoC2FPGA_main_Probe_Filters_0_RouteIdBase; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE */
3961  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_t Probe_SoC2FPGA_main_Probe_Filters_0_RouteIdMask; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK */
3962  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_t Probe_SoC2FPGA_main_Probe_Filters_0_AddrBase_Low; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW */
3963  volatile uint32_t _pad_0x50_0x53; /* *UNDEFINED* */
3964  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_t Probe_SoC2FPGA_main_Probe_Filters_0_WindowSize; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE */
3965  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_t Probe_SoC2FPGA_main_Probe_Filters_0_SecurityBase; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE */
3966  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_t Probe_SoC2FPGA_main_Probe_Filters_0_SecurityMask; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK */
3967  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_t Probe_SoC2FPGA_main_Probe_Filters_0_Opcode; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE */
3968  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_t Probe_SoC2FPGA_main_Probe_Filters_0_Status; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT */
3969  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_t Probe_SoC2FPGA_main_Probe_Filters_0_Length; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN */
3970  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_t Probe_SoC2FPGA_main_Probe_Filters_0_Urgency; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY */
3971  volatile uint32_t _pad_0x70_0x7f[4]; /* *UNDEFINED* */
3972  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_t Probe_SoC2FPGA_main_Probe_Filters_1_RouteIdBase; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE */
3973  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_t Probe_SoC2FPGA_main_Probe_Filters_1_RouteIdMask; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK */
3974  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_t Probe_SoC2FPGA_main_Probe_Filters_1_AddrBase_Low; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW */
3975  volatile uint32_t _pad_0x8c_0x8f; /* *UNDEFINED* */
3976  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_t Probe_SoC2FPGA_main_Probe_Filters_1_WindowSize; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE */
3977  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_t Probe_SoC2FPGA_main_Probe_Filters_1_SecurityBase; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE */
3978  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_t Probe_SoC2FPGA_main_Probe_Filters_1_SecurityMask; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK */
3979  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_t Probe_SoC2FPGA_main_Probe_Filters_1_Opcode; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE */
3980  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_t Probe_SoC2FPGA_main_Probe_Filters_1_Status; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT */
3981  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_t Probe_SoC2FPGA_main_Probe_Filters_1_Length; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN */
3982  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_t Probe_SoC2FPGA_main_Probe_Filters_1_Urgency; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY */
3983  volatile uint32_t _pad_0xac_0x133[34]; /* *UNDEFINED* */
3984  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_t Probe_SoC2FPGA_main_Probe_Counters_0_PortSel; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL */
3985  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_t Probe_SoC2FPGA_main_Probe_Counters_0_Src; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC */
3986  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_t Probe_SoC2FPGA_main_Probe_Counters_0_AlarmMode; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD */
3987  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_t Probe_SoC2FPGA_main_Probe_Counters_0_Val; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL */
3988  volatile uint32_t _pad_0x144_0x147; /* *UNDEFINED* */
3989  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_t Probe_SoC2FPGA_main_Probe_Counters_1_PortSel; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL */
3990  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_t Probe_SoC2FPGA_main_Probe_Counters_1_Src; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC */
3991  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_t Probe_SoC2FPGA_main_Probe_Counters_1_AlarmMode; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD */
3992  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_t Probe_SoC2FPGA_main_Probe_Counters_1_Val; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL */
3993  volatile uint32_t _pad_0x158_0x15b; /* *UNDEFINED* */
3994  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_t Probe_SoC2FPGA_main_Probe_Counters_2_PortSel; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL */
3995  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_t Probe_SoC2FPGA_main_Probe_Counters_2_Src; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC */
3996  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_t Probe_SoC2FPGA_main_Probe_Counters_2_AlarmMode; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD */
3997  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_t Probe_SoC2FPGA_main_Probe_Counters_2_Val; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL */
3998  volatile uint32_t _pad_0x16c_0x16f; /* *UNDEFINED* */
3999  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_t Probe_SoC2FPGA_main_Probe_Counters_3_PortSel; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL */
4000  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_t Probe_SoC2FPGA_main_Probe_Counters_3_Src; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC */
4001  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_t Probe_SoC2FPGA_main_Probe_Counters_3_AlarmMode; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD */
4002  ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_t Probe_SoC2FPGA_main_Probe_Counters_3_Val; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL */
4003  volatile uint32_t _pad_0x180_0x400[160]; /* *UNDEFINED* */
4004 };
4005 
4006 /* The typedef declaration for register group ALT_NOC_MPU_PRB_H2F_MAIN_PRB. */
4007 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_PRB_s ALT_NOC_MPU_PRB_H2F_MAIN_PRB_t;
4008 /* The struct declaration for the raw register contents of register group ALT_NOC_MPU_PRB_H2F_MAIN_PRB. */
4009 struct ALT_NOC_MPU_PRB_H2F_MAIN_PRB_raw_s
4010 {
4011  volatile uint32_t Probe_SoC2FPGA_main_Probe_Id_CoreId; /* ALT_NOC_MPU_PRB_H2F_MAIN_COREID */
4012  volatile uint32_t Probe_SoC2FPGA_main_Probe_Id_RevisionId; /* ALT_NOC_MPU_PRB_H2F_MAIN_REVID */
4013  volatile uint32_t Probe_SoC2FPGA_main_Probe_MainCtl; /* ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL */
4014  volatile uint32_t Probe_SoC2FPGA_main_Probe_CfgCtl; /* ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL */
4015  volatile uint32_t Probe_SoC2FPGA_main_Probe_TracePortSel; /* ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL */
4016  volatile uint32_t Probe_SoC2FPGA_main_Probe_FilterLut; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT */
4017  volatile uint32_t Probe_SoC2FPGA_main_Probe_TraceAlarmEn; /* ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN */
4018  volatile uint32_t Probe_SoC2FPGA_main_Probe_TraceAlarmStatus; /* ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT */
4019  volatile uint32_t Probe_SoC2FPGA_main_Probe_TraceAlarmClr; /* ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR */
4020  volatile uint32_t Probe_SoC2FPGA_main_Probe_StatPeriod; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD */
4021  volatile uint32_t Probe_SoC2FPGA_main_Probe_StatGo; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATGO */
4022  volatile uint32_t Probe_SoC2FPGA_main_Probe_StatAlarmMin; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN */
4023  volatile uint32_t Probe_SoC2FPGA_main_Probe_StatAlarmMax; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX */
4024  volatile uint32_t Probe_SoC2FPGA_main_Probe_StatAlarmStatus; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT */
4025  volatile uint32_t Probe_SoC2FPGA_main_Probe_StatAlarmClr; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR */
4026  volatile uint32_t Probe_SoC2FPGA_main_Probe_StatAlarmEn; /* ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN */
4027  uint32_t _pad_0x40_0x43; /* *UNDEFINED* */
4028  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_0_RouteIdBase; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE */
4029  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_0_RouteIdMask; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK */
4030  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_0_AddrBase_Low; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW */
4031  uint32_t _pad_0x50_0x53; /* *UNDEFINED* */
4032  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_0_WindowSize; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE */
4033  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_0_SecurityBase; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE */
4034  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_0_SecurityMask; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK */
4035  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_0_Opcode; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE */
4036  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_0_Status; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT */
4037  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_0_Length; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN */
4038  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_0_Urgency; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY */
4039  uint32_t _pad_0x70_0x7f[4]; /* *UNDEFINED* */
4040  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_1_RouteIdBase; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE */
4041  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_1_RouteIdMask; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK */
4042  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_1_AddrBase_Low; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW */
4043  uint32_t _pad_0x8c_0x8f; /* *UNDEFINED* */
4044  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_1_WindowSize; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE */
4045  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_1_SecurityBase; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE */
4046  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_1_SecurityMask; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK */
4047  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_1_Opcode; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE */
4048  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_1_Status; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT */
4049  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_1_Length; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN */
4050  volatile uint32_t Probe_SoC2FPGA_main_Probe_Filters_1_Urgency; /* ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY */
4051  uint32_t _pad_0xac_0x133[34]; /* *UNDEFINED* */
4052  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_0_PortSel; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL */
4053  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_0_Src; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC */
4054  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_0_AlarmMode; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD */
4055  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_0_Val; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL */
4056  uint32_t _pad_0x144_0x147; /* *UNDEFINED* */
4057  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_1_PortSel; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL */
4058  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_1_Src; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC */
4059  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_1_AlarmMode; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD */
4060  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_1_Val; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL */
4061  uint32_t _pad_0x158_0x15b; /* *UNDEFINED* */
4062  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_2_PortSel; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL */
4063  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_2_Src; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC */
4064  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_2_AlarmMode; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD */
4065  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_2_Val; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL */
4066  uint32_t _pad_0x16c_0x16f; /* *UNDEFINED* */
4067  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_3_PortSel; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL */
4068  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_3_Src; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC */
4069  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_3_AlarmMode; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD */
4070  volatile uint32_t Probe_SoC2FPGA_main_Probe_Counters_3_Val; /* ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL */
4071  uint32_t _pad_0x180_0x400[160]; /* *UNDEFINED* */
4072 };
4073 
4074 /* The typedef declaration for the raw register contents of register group ALT_NOC_MPU_PRB_H2F_MAIN_PRB. */
4075 typedef volatile struct ALT_NOC_MPU_PRB_H2F_MAIN_PRB_raw_s ALT_NOC_MPU_PRB_H2F_MAIN_PRB_raw_t;
4076 #endif /* __ASSEMBLY__ */
4077 
4078 
4079 /*
4080  * Component : ALT_NOC_MPU_PRB_EMACS_MAIN_PRB
4081  *
4082  */
4083 /*
4084  * Register : Probe_emacs_main_Probe_Id_CoreId
4085  *
4086  * Register Layout
4087  *
4088  * Bits | Access | Reset | Description
4089  * :-------|:-------|:---------|:-------------------------------------------
4090  * [7:0] | R | 0x6 | ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID
4091  * [31:8] | R | 0xf46f63 | ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM
4092  *
4093  */
4094 /*
4095  * Field : CORETYPEID
4096  *
4097  * Field identifying the type of IP.
4098  *
4099  * Field Access Macros:
4100  *
4101  */
4102 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID register field. */
4103 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_LSB 0
4104 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID register field. */
4105 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_MSB 7
4106 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID register field. */
4107 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_WIDTH 8
4108 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID register field value. */
4109 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_SET_MSK 0x000000ff
4110 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID register field value. */
4111 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_CLR_MSK 0xffffff00
4112 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID register field. */
4113 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_RESET 0x6
4114 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID field value from a register. */
4115 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
4116 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID register field value suitable for setting the register. */
4117 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
4118 
4119 /*
4120  * Field : CORECHECKSUM
4121  *
4122  * Field containing a checksum of the parameters of the IP.
4123  *
4124  * Field Access Macros:
4125  *
4126  */
4127 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM register field. */
4128 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_LSB 8
4129 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM register field. */
4130 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_MSB 31
4131 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM register field. */
4132 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_WIDTH 24
4133 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM register field value. */
4134 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_SET_MSK 0xffffff00
4135 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM register field value. */
4136 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_CLR_MSK 0x000000ff
4137 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM register field. */
4138 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_RESET 0xf46f63
4139 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM field value from a register. */
4140 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
4141 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM register field value suitable for setting the register. */
4142 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
4143 
4144 #ifndef __ASSEMBLY__
4145 /*
4146  * WARNING: The C register and register group struct declarations are provided for
4147  * convenience and illustrative purposes. They should, however, be used with
4148  * caution as the C language standard provides no guarantees about the alignment or
4149  * atomicity of device memory accesses. The recommended practice for writing
4150  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4151  * alt_write_word() functions.
4152  *
4153  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_COREID.
4154  */
4155 struct ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_s
4156 {
4157  const uint32_t CORETYPEID : 8; /* ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID */
4158  const uint32_t CORECHECKSUM : 24; /* ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM */
4159 };
4160 
4161 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_COREID. */
4162 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_s ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_t;
4163 #endif /* __ASSEMBLY__ */
4164 
4165 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID register. */
4166 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_RESET 0xf46f6306
4167 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_COREID register from the beginning of the component. */
4168 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_OFST 0x0
4169 
4170 /*
4171  * Register : Probe_emacs_main_Probe_Id_RevisionId
4172  *
4173  * Register Layout
4174  *
4175  * Bits | Access | Reset | Description
4176  * :-------|:-------|:--------|:-------------------------------------------
4177  * [7:0] | R | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID
4178  * [31:8] | R | 0x129ff | ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID
4179  *
4180  */
4181 /*
4182  * Field : USERID
4183  *
4184  * Field containing a user defined value, not used anywhere inside the IP itself.
4185  *
4186  * Field Access Macros:
4187  *
4188  */
4189 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID register field. */
4190 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_LSB 0
4191 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID register field. */
4192 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_MSB 7
4193 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID register field. */
4194 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_WIDTH 8
4195 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID register field value. */
4196 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_SET_MSK 0x000000ff
4197 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID register field value. */
4198 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_CLR_MSK 0xffffff00
4199 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID register field. */
4200 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_RESET 0x0
4201 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID field value from a register. */
4202 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
4203 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID register field value suitable for setting the register. */
4204 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
4205 
4206 /*
4207  * Field : FLEXNOCID
4208  *
4209  * Field containing the build revision of the software used to generate the IP HDL
4210  * code.
4211  *
4212  * Field Access Macros:
4213  *
4214  */
4215 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID register field. */
4216 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_LSB 8
4217 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID register field. */
4218 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_MSB 31
4219 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID register field. */
4220 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_WIDTH 24
4221 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID register field value. */
4222 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_SET_MSK 0xffffff00
4223 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID register field value. */
4224 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_CLR_MSK 0x000000ff
4225 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID register field. */
4226 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_RESET 0x129ff
4227 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID field value from a register. */
4228 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
4229 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID register field value suitable for setting the register. */
4230 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
4231 
4232 #ifndef __ASSEMBLY__
4233 /*
4234  * WARNING: The C register and register group struct declarations are provided for
4235  * convenience and illustrative purposes. They should, however, be used with
4236  * caution as the C language standard provides no guarantees about the alignment or
4237  * atomicity of device memory accesses. The recommended practice for writing
4238  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4239  * alt_write_word() functions.
4240  *
4241  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_REVID.
4242  */
4243 struct ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_s
4244 {
4245  const uint32_t USERID : 8; /* ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID */
4246  const uint32_t FLEXNOCID : 24; /* ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID */
4247 };
4248 
4249 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_REVID. */
4250 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_s ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_t;
4251 #endif /* __ASSEMBLY__ */
4252 
4253 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID register. */
4254 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_RESET 0x0129ff00
4255 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_REVID register from the beginning of the component. */
4256 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_OFST 0x4
4257 
4258 /*
4259  * Register : Probe_emacs_main_Probe_MainCtl
4260  *
4261  * Register MainCtl contains probe global control bits. The register has seven bit
4262  * fields:
4263  *
4264  * Register Layout
4265  *
4266  * Bits | Access | Reset | Description
4267  * :-------|:-------|:--------|:-------------------------------------------------------------
4268  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN
4269  * [1] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN
4270  * [2] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN
4271  * [3] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN
4272  * [4] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN
4273  * [5] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP
4274  * [6] | R | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD
4275  * [7] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN
4276  * [31:8] | ??? | Unknown | *UNDEFINED*
4277  *
4278  */
4279 /*
4280  * Field : ERREN
4281  *
4282  * Register field ErrEn enables the probe to send on the ObsTx output any packet
4283  * with Error status, independently of filtering mechanisms, thus constituting a
4284  * simple supplementary global filter.
4285  *
4286  * Field Access Macros:
4287  *
4288  */
4289 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN register field. */
4290 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_LSB 0
4291 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN register field. */
4292 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_MSB 0
4293 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN register field. */
4294 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_WIDTH 1
4295 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN register field value. */
4296 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_SET_MSK 0x00000001
4297 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN register field value. */
4298 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_CLR_MSK 0xfffffffe
4299 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN register field. */
4300 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_RESET 0x0
4301 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN field value from a register. */
4302 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_GET(value) (((value) & 0x00000001) >> 0)
4303 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN register field value suitable for setting the register. */
4304 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_SET(value) (((value) << 0) & 0x00000001)
4305 
4306 /*
4307  * Field : TRACEEN
4308  *
4309  * Register field TraceEn enables the probe to send filtered packets (Trace) on the
4310  * ObsTx observation output.
4311  *
4312  * Field Access Macros:
4313  *
4314  */
4315 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN register field. */
4316 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_LSB 1
4317 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN register field. */
4318 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_MSB 1
4319 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN register field. */
4320 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_WIDTH 1
4321 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN register field value. */
4322 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_SET_MSK 0x00000002
4323 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN register field value. */
4324 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_CLR_MSK 0xfffffffd
4325 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN register field. */
4326 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_RESET 0x0
4327 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN field value from a register. */
4328 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_GET(value) (((value) & 0x00000002) >> 1)
4329 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN register field value suitable for setting the register. */
4330 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_SET(value) (((value) << 1) & 0x00000002)
4331 
4332 /*
4333  * Field : PAYLOADEN
4334  *
4335  * Register field PayloadEn, when set to 1, enables traces to contain headers and
4336  * payload. When set ot 0, only headers are reported.
4337  *
4338  * Field Access Macros:
4339  *
4340  */
4341 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN register field. */
4342 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_LSB 2
4343 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN register field. */
4344 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_MSB 2
4345 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN register field. */
4346 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_WIDTH 1
4347 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN register field value. */
4348 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_SET_MSK 0x00000004
4349 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN register field value. */
4350 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_CLR_MSK 0xfffffffb
4351 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN register field. */
4352 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_RESET 0x0
4353 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN field value from a register. */
4354 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_GET(value) (((value) & 0x00000004) >> 2)
4355 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN register field value suitable for setting the register. */
4356 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_SET(value) (((value) << 2) & 0x00000004)
4357 
4358 /*
4359  * Field : STATEN
4360  *
4361  * When set to 1, register field StatEn enables statistics profiling. The probe
4362  * sendS statistics results to the output for signal ObsTx. All statistics counters
4363  * are cleared when the StatEn bit goes from 0 to 1. When set to 0, counters are
4364  * disabled.
4365  *
4366  * Field Access Macros:
4367  *
4368  */
4369 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN register field. */
4370 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_LSB 3
4371 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN register field. */
4372 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_MSB 3
4373 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN register field. */
4374 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_WIDTH 1
4375 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN register field value. */
4376 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_SET_MSK 0x00000008
4377 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN register field value. */
4378 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_CLR_MSK 0xfffffff7
4379 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN register field. */
4380 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_RESET 0x0
4381 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN field value from a register. */
4382 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_GET(value) (((value) & 0x00000008) >> 3)
4383 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN register field value suitable for setting the register. */
4384 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_SET(value) (((value) << 3) & 0x00000008)
4385 
4386 /*
4387  * Field : ALARMEN
4388  *
4389  * When set, register field AlarmEn enables the probe to collect alarm-related
4390  * information. When the register field bit is null, both TraceAlarm and StatAlarm
4391  * outputs are driven to 0.
4392  *
4393  * Field Access Macros:
4394  *
4395  */
4396 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN register field. */
4397 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_LSB 4
4398 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN register field. */
4399 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_MSB 4
4400 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN register field. */
4401 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_WIDTH 1
4402 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN register field value. */
4403 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_SET_MSK 0x00000010
4404 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN register field value. */
4405 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_CLR_MSK 0xffffffef
4406 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN register field. */
4407 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_RESET 0x0
4408 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN field value from a register. */
4409 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_GET(value) (((value) & 0x00000010) >> 4)
4410 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN register field value suitable for setting the register. */
4411 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_SET(value) (((value) << 4) & 0x00000010)
4412 
4413 /*
4414  * Field : STATCONDDUMP
4415  *
4416  * When set, register field StatCondDump enables the dump of a statistics frame to
4417  * the range of counter values set for registers StatAlarmMin, StatAlarmMax, and
4418  * AlarmMode. This field also renders register StatAlarmStatus inoperative. When
4419  * parameter statisticsCounterAlarm is set to False, the StatCondDump register bit
4420  * is reserved.
4421  *
4422  * Field Access Macros:
4423  *
4424  */
4425 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP register field. */
4426 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_LSB 5
4427 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP register field. */
4428 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_MSB 5
4429 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP register field. */
4430 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_WIDTH 1
4431 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP register field value. */
4432 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_SET_MSK 0x00000020
4433 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP register field value. */
4434 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_CLR_MSK 0xffffffdf
4435 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP register field. */
4436 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_RESET 0x0
4437 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP field value from a register. */
4438 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_GET(value) (((value) & 0x00000020) >> 5)
4439 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP register field value suitable for setting the register. */
4440 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_SET(value) (((value) << 5) & 0x00000020)
4441 
4442 /*
4443  * Field : INTRUSIVEMODE
4444  *
4445  * When set to 1, register field IntrusiveMode enables trace operation in Intrusive
4446  * flow-control mode. When set to 0, the register enables trace operation in
4447  * Overflow flow-control mode
4448  *
4449  * Field Access Macros:
4450  *
4451  */
4452 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD register field. */
4453 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_LSB 6
4454 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD register field. */
4455 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_MSB 6
4456 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD register field. */
4457 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_WIDTH 1
4458 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD register field value. */
4459 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_SET_MSK 0x00000040
4460 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD register field value. */
4461 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_CLR_MSK 0xffffffbf
4462 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD register field. */
4463 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_RESET 0x0
4464 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD field value from a register. */
4465 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_GET(value) (((value) & 0x00000040) >> 6)
4466 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD register field value suitable for setting the register. */
4467 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_SET(value) (((value) << 6) & 0x00000040)
4468 
4469 /*
4470  * Field : FILTBYTEALWAYSCHAINABLEEN
4471  *
4472  * When set to 0, filters are mapped to all statistic counters when counting bytes
4473  * or enabled bytes. Therefore, only filter events mapped to even counters can be
4474  * counted using a pair of chained counters.When set to 1, filters are mapped only
4475  * to even statistic counters when counting bytes or enabled bytes. Thus events
4476  * from any filter can be counted using a pair of chained counters.
4477  *
4478  * Field Access Macros:
4479  *
4480  */
4481 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
4482 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_LSB 7
4483 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
4484 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MSB 7
4485 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
4486 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_WIDTH 1
4487 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value. */
4488 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET_MSK 0x00000080
4489 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value. */
4490 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_CLR_MSK 0xffffff7f
4491 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
4492 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_RESET 0x0
4493 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN field value from a register. */
4494 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_GET(value) (((value) & 0x00000080) >> 7)
4495 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value suitable for setting the register. */
4496 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET(value) (((value) << 7) & 0x00000080)
4497 
4498 #ifndef __ASSEMBLY__
4499 /*
4500  * WARNING: The C register and register group struct declarations are provided for
4501  * convenience and illustrative purposes. They should, however, be used with
4502  * caution as the C language standard provides no guarantees about the alignment or
4503  * atomicity of device memory accesses. The recommended practice for writing
4504  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4505  * alt_write_word() functions.
4506  *
4507  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL.
4508  */
4509 struct ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_s
4510 {
4511  uint32_t ERREN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN */
4512  uint32_t TRACEEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN */
4513  uint32_t PAYLOADEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN */
4514  uint32_t STATEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN */
4515  uint32_t ALARMEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN */
4516  uint32_t STATCONDDUMP : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP */
4517  const uint32_t INTRUSIVEMODE : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD */
4518  uint32_t FILTBYTEALWAYSCHAINABLEEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN */
4519  uint32_t : 24; /* *UNDEFINED* */
4520 };
4521 
4522 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL. */
4523 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_s ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_t;
4524 #endif /* __ASSEMBLY__ */
4525 
4526 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL register. */
4527 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_RESET 0x00000000
4528 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL register from the beginning of the component. */
4529 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_OFST 0x8
4530 
4531 /*
4532  * Register : Probe_emacs_main_Probe_CfgCtl
4533  *
4534  * Register Layout
4535  *
4536  * Bits | Access | Reset | Description
4537  * :-------|:-------|:--------|:-----------------------------------------
4538  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN
4539  * [1] | R | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT
4540  * [31:2] | ??? | Unknown | *UNDEFINED*
4541  *
4542  */
4543 /*
4544  * Field : GLOBALEN
4545  *
4546  *
4547  * Field Access Macros:
4548  *
4549  */
4550 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN register field. */
4551 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_LSB 0
4552 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN register field. */
4553 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_MSB 0
4554 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN register field. */
4555 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_WIDTH 1
4556 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN register field value. */
4557 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_SET_MSK 0x00000001
4558 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN register field value. */
4559 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_CLR_MSK 0xfffffffe
4560 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN register field. */
4561 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_RESET 0x0
4562 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN field value from a register. */
4563 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_GET(value) (((value) & 0x00000001) >> 0)
4564 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN register field value suitable for setting the register. */
4565 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_SET(value) (((value) << 0) & 0x00000001)
4566 
4567 /*
4568  * Field : ACTIVE
4569  *
4570  *
4571  * Field Access Macros:
4572  *
4573  */
4574 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT register field. */
4575 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_LSB 1
4576 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT register field. */
4577 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_MSB 1
4578 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT register field. */
4579 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_WIDTH 1
4580 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT register field value. */
4581 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_SET_MSK 0x00000002
4582 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT register field value. */
4583 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_CLR_MSK 0xfffffffd
4584 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT register field. */
4585 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_RESET 0x0
4586 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT field value from a register. */
4587 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_GET(value) (((value) & 0x00000002) >> 1)
4588 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT register field value suitable for setting the register. */
4589 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_SET(value) (((value) << 1) & 0x00000002)
4590 
4591 #ifndef __ASSEMBLY__
4592 /*
4593  * WARNING: The C register and register group struct declarations are provided for
4594  * convenience and illustrative purposes. They should, however, be used with
4595  * caution as the C language standard provides no guarantees about the alignment or
4596  * atomicity of device memory accesses. The recommended practice for writing
4597  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4598  * alt_write_word() functions.
4599  *
4600  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL.
4601  */
4602 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_s
4603 {
4604  uint32_t GLOBALEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN */
4605  const uint32_t ACTIVE : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT */
4606  uint32_t : 30; /* *UNDEFINED* */
4607 };
4608 
4609 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL. */
4610 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_s ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_t;
4611 #endif /* __ASSEMBLY__ */
4612 
4613 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL register. */
4614 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_RESET 0x00000000
4615 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL register from the beginning of the component. */
4616 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_OFST 0xc
4617 
4618 /*
4619  * Register : Probe_emacs_main_Probe_TracePortSel
4620  *
4621  *
4622  * Register Layout
4623  *
4624  * Bits | Access | Reset | Description
4625  * :-------|:-------|:--------|:-----------------------------------------------------
4626  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL
4627  * [31:1] | ??? | Unknown | *UNDEFINED*
4628  *
4629  */
4630 /*
4631  * Field : TRACEPORTSEL
4632  *
4633  * Register TracePortSel indicates which generic protocol link is currently being
4634  * observed by trace logic.The number of bits in register TracePortSel is equal to
4635  * log2 of the value set for parameter nPort.The register can be updated at any
4636  * time, but changes only become effective at packet boundaries.
4637  *
4638  * Field Access Macros:
4639  *
4640  */
4641 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL register field. */
4642 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_LSB 0
4643 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL register field. */
4644 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_MSB 0
4645 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL register field. */
4646 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_WIDTH 1
4647 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL register field value. */
4648 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_SET_MSK 0x00000001
4649 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL register field value. */
4650 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_CLR_MSK 0xfffffffe
4651 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL register field. */
4652 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_RESET 0x0
4653 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL field value from a register. */
4654 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_GET(value) (((value) & 0x00000001) >> 0)
4655 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL register field value suitable for setting the register. */
4656 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_SET(value) (((value) << 0) & 0x00000001)
4657 
4658 #ifndef __ASSEMBLY__
4659 /*
4660  * WARNING: The C register and register group struct declarations are provided for
4661  * convenience and illustrative purposes. They should, however, be used with
4662  * caution as the C language standard provides no guarantees about the alignment or
4663  * atomicity of device memory accesses. The recommended practice for writing
4664  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4665  * alt_write_word() functions.
4666  *
4667  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL.
4668  */
4669 struct ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_s
4670 {
4671  uint32_t TRACEPORTSEL : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL */
4672  uint32_t : 31; /* *UNDEFINED* */
4673 };
4674 
4675 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL. */
4676 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_s ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_t;
4677 #endif /* __ASSEMBLY__ */
4678 
4679 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL register. */
4680 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_RESET 0x00000000
4681 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL register from the beginning of the component. */
4682 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_OFST 0x10
4683 
4684 /*
4685  * Register : Probe_emacs_main_Probe_FilterLut
4686  *
4687  *
4688  * Register Layout
4689  *
4690  * Bits | Access | Reset | Description
4691  * :-------|:-------|:--------|:-----------------------------------------
4692  * [3:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT
4693  * [31:4] | ??? | Unknown | *UNDEFINED*
4694  *
4695  */
4696 /*
4697  * Field : FILTERLUT
4698  *
4699  * Register FilterLut contains a look-up table that is used to combine filter
4700  * outputs in order to trace packets. Packet tracing is enabled when the FilterLut
4701  * bit of index (FNout ... F0out) is equal to 1.The number of bits in register
4702  * FilterLut is determined by the setting for parameter nFilter, calculated as
4703  * 2**nFilter.When parameter nFilter is set to None, FilterLut is reserved.
4704  *
4705  * Field Access Macros:
4706  *
4707  */
4708 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT register field. */
4709 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_LSB 0
4710 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT register field. */
4711 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_MSB 3
4712 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT register field. */
4713 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_WIDTH 4
4714 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT register field value. */
4715 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_SET_MSK 0x0000000f
4716 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT register field value. */
4717 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_CLR_MSK 0xfffffff0
4718 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT register field. */
4719 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_RESET 0x0
4720 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT field value from a register. */
4721 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_GET(value) (((value) & 0x0000000f) >> 0)
4722 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT register field value suitable for setting the register. */
4723 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_SET(value) (((value) << 0) & 0x0000000f)
4724 
4725 #ifndef __ASSEMBLY__
4726 /*
4727  * WARNING: The C register and register group struct declarations are provided for
4728  * convenience and illustrative purposes. They should, however, be used with
4729  * caution as the C language standard provides no guarantees about the alignment or
4730  * atomicity of device memory accesses. The recommended practice for writing
4731  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4732  * alt_write_word() functions.
4733  *
4734  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT.
4735  */
4736 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_s
4737 {
4738  uint32_t FILTERLUT : 4; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT */
4739  uint32_t : 28; /* *UNDEFINED* */
4740 };
4741 
4742 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT. */
4743 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_t;
4744 #endif /* __ASSEMBLY__ */
4745 
4746 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT register. */
4747 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_RESET 0x00000000
4748 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT register from the beginning of the component. */
4749 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_OFST 0x14
4750 
4751 /*
4752  * Register : Probe_emacs_main_Probe_TraceAlarmEn
4753  *
4754  *
4755  * Register Layout
4756  *
4757  * Bits | Access | Reset | Description
4758  * :-------|:-------|:--------|:-----------------------------------------------------
4759  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN
4760  * [31:3] | ??? | Unknown | *UNDEFINED*
4761  *
4762  */
4763 /*
4764  * Field : TRACEALARMEN
4765  *
4766  * Register TraceAlarmEn controls which lookup table or filter can set the
4767  * TraceAlarm signal output once the trace alarm status is set. The number of bits
4768  * in register TraceAlarmEn is determined by the value set for parameter nFilter +
4769  * 1.Bit nFilter controls the lookup table output, and bits nFilter:0 control the
4770  * corresponding filter output. When parameter nFilter is set to None, TraceAlarmEn
4771  * is reserved.
4772  *
4773  * Field Access Macros:
4774  *
4775  */
4776 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN register field. */
4777 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_LSB 0
4778 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN register field. */
4779 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_MSB 2
4780 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN register field. */
4781 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_WIDTH 3
4782 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN register field value. */
4783 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_SET_MSK 0x00000007
4784 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN register field value. */
4785 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_CLR_MSK 0xfffffff8
4786 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN register field. */
4787 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_RESET 0x0
4788 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN field value from a register. */
4789 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_GET(value) (((value) & 0x00000007) >> 0)
4790 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN register field value suitable for setting the register. */
4791 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_SET(value) (((value) << 0) & 0x00000007)
4792 
4793 #ifndef __ASSEMBLY__
4794 /*
4795  * WARNING: The C register and register group struct declarations are provided for
4796  * convenience and illustrative purposes. They should, however, be used with
4797  * caution as the C language standard provides no guarantees about the alignment or
4798  * atomicity of device memory accesses. The recommended practice for writing
4799  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4800  * alt_write_word() functions.
4801  *
4802  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN.
4803  */
4804 struct ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_s
4805 {
4806  uint32_t TRACEALARMEN : 3; /* ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN */
4807  uint32_t : 29; /* *UNDEFINED* */
4808 };
4809 
4810 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN. */
4811 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_s ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_t;
4812 #endif /* __ASSEMBLY__ */
4813 
4814 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN register. */
4815 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_RESET 0x00000000
4816 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN register from the beginning of the component. */
4817 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_OFST 0x18
4818 
4819 /*
4820  * Register : Probe_emacs_main_Probe_TraceAlarmStatus
4821  *
4822  *
4823  * Register Layout
4824  *
4825  * Bits | Access | Reset | Description
4826  * :-------|:-------|:--------|:---------------------------------------------------------
4827  * [2:0] | R | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT
4828  * [31:3] | ??? | Unknown | *UNDEFINED*
4829  *
4830  */
4831 /*
4832  * Field : TRACEALARMSTATUS
4833  *
4834  * Register TraceAlarmStatus is a read-only register that indicates which lookup
4835  * table or filter has been matched by a packet, independently of register
4836  * TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is
4837  * determined by the value set for parameter nFilter + 1.When nFilter is set to
4838  * None, TraceAlarmStatus is reserved.
4839  *
4840  * Field Access Macros:
4841  *
4842  */
4843 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field. */
4844 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_LSB 0
4845 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field. */
4846 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_MSB 2
4847 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field. */
4848 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_WIDTH 3
4849 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field value. */
4850 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_SET_MSK 0x00000007
4851 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field value. */
4852 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_CLR_MSK 0xfffffff8
4853 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field. */
4854 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_RESET 0x0
4855 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT field value from a register. */
4856 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_GET(value) (((value) & 0x00000007) >> 0)
4857 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field value suitable for setting the register. */
4858 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_SET(value) (((value) << 0) & 0x00000007)
4859 
4860 #ifndef __ASSEMBLY__
4861 /*
4862  * WARNING: The C register and register group struct declarations are provided for
4863  * convenience and illustrative purposes. They should, however, be used with
4864  * caution as the C language standard provides no guarantees about the alignment or
4865  * atomicity of device memory accesses. The recommended practice for writing
4866  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4867  * alt_write_word() functions.
4868  *
4869  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT.
4870  */
4871 struct ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_s
4872 {
4873  const uint32_t TRACEALARMSTATUS : 3; /* ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT */
4874  uint32_t : 29; /* *UNDEFINED* */
4875 };
4876 
4877 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT. */
4878 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_s ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_t;
4879 #endif /* __ASSEMBLY__ */
4880 
4881 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT register. */
4882 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_RESET 0x00000000
4883 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT register from the beginning of the component. */
4884 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_OFST 0x1c
4885 
4886 /*
4887  * Register : Probe_emacs_main_Probe_TraceAlarmClr
4888  *
4889  *
4890  * Register Layout
4891  *
4892  * Bits | Access | Reset | Description
4893  * :-------|:-------|:--------|:-------------------------------------------------------
4894  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR
4895  * [31:3] | ??? | Unknown | *UNDEFINED*
4896  *
4897  */
4898 /*
4899  * Field : TRACEALARMCLR
4900  *
4901  * Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in
4902  * register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal
4903  * to (nFilter + 1). When nFilter is set to 0, TraceAlarmClr is reserved.NOTE The
4904  * written value is not stored in TraceAlarmClr. A read always returns 0.
4905  *
4906  * Field Access Macros:
4907  *
4908  */
4909 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR register field. */
4910 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_LSB 0
4911 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR register field. */
4912 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_MSB 2
4913 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR register field. */
4914 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_WIDTH 3
4915 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR register field value. */
4916 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x00000007
4917 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR register field value. */
4918 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xfffffff8
4919 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR register field. */
4920 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0
4921 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR field value from a register. */
4922 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_GET(value) (((value) & 0x00000007) >> 0)
4923 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR register field value suitable for setting the register. */
4924 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_SET(value) (((value) << 0) & 0x00000007)
4925 
4926 #ifndef __ASSEMBLY__
4927 /*
4928  * WARNING: The C register and register group struct declarations are provided for
4929  * convenience and illustrative purposes. They should, however, be used with
4930  * caution as the C language standard provides no guarantees about the alignment or
4931  * atomicity of device memory accesses. The recommended practice for writing
4932  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4933  * alt_write_word() functions.
4934  *
4935  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR.
4936  */
4937 struct ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_s
4938 {
4939  uint32_t TRACEALARMCLR : 3; /* ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR */
4940  uint32_t : 29; /* *UNDEFINED* */
4941 };
4942 
4943 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR. */
4944 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_s ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_t;
4945 #endif /* __ASSEMBLY__ */
4946 
4947 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR register. */
4948 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_RESET 0x00000000
4949 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR register from the beginning of the component. */
4950 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_OFST 0x20
4951 
4952 /*
4953  * Register : Probe_emacs_main_Probe_StatPeriod
4954  *
4955  *
4956  * Register Layout
4957  *
4958  * Bits | Access | Reset | Description
4959  * :-------|:-------|:--------|:-------------------------------------------------
4960  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD
4961  * [31:5] | ??? | Unknown | *UNDEFINED*
4962  *
4963  */
4964 /*
4965  * Field : STATPERIOD
4966  *
4967  * Register StatPeriod is a 5-bit register that sets a period, within a range of 2
4968  * cycles to 2 gigacycles, during which statistics are collected before being
4969  * dumped automatically. Setting the register implicitly enables automatic mode
4970  * operation for statistics collection. The period is calculated with the formula:
4971  * N_Cycle = 2**StatPeriodWhen register StatPeriod is set to its default value 0,
4972  * automatic dump mode is disabled, and register StatGo is activated for manual
4973  * mode operation. Note: When parameter statisticsCollection is set to False,
4974  * StatPeriod is reserved.
4975  *
4976  * Field Access Macros:
4977  *
4978  */
4979 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD register field. */
4980 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_LSB 0
4981 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD register field. */
4982 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_MSB 4
4983 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD register field. */
4984 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_WIDTH 5
4985 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD register field value. */
4986 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_SET_MSK 0x0000001f
4987 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD register field value. */
4988 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_CLR_MSK 0xffffffe0
4989 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD register field. */
4990 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_RESET 0x0
4991 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD field value from a register. */
4992 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
4993 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD register field value suitable for setting the register. */
4994 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_SET(value) (((value) << 0) & 0x0000001f)
4995 
4996 #ifndef __ASSEMBLY__
4997 /*
4998  * WARNING: The C register and register group struct declarations are provided for
4999  * convenience and illustrative purposes. They should, however, be used with
5000  * caution as the C language standard provides no guarantees about the alignment or
5001  * atomicity of device memory accesses. The recommended practice for writing
5002  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5003  * alt_write_word() functions.
5004  *
5005  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD.
5006  */
5007 struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_s
5008 {
5009  uint32_t STATPERIOD : 5; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD */
5010  uint32_t : 27; /* *UNDEFINED* */
5011 };
5012 
5013 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD. */
5014 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_s ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_t;
5015 #endif /* __ASSEMBLY__ */
5016 
5017 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD register. */
5018 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_RESET 0x00000000
5019 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD register from the beginning of the component. */
5020 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_OFST 0x24
5021 
5022 /*
5023  * Register : Probe_emacs_main_Probe_StatGo
5024  *
5025  *
5026  * Register Layout
5027  *
5028  * Bits | Access | Reset | Description
5029  * :-------|:-------|:--------|:-----------------------------------------
5030  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO
5031  * [31:1] | ??? | Unknown | *UNDEFINED*
5032  *
5033  */
5034 /*
5035  * Field : STATGO
5036  *
5037  * Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The
5038  * register is active when statistics collection operates in manual mode, that is,
5039  * when register StatPeriod is set to 0.NOTE The written value is not stored in
5040  * StatGo. A read always returns 0.
5041  *
5042  * Field Access Macros:
5043  *
5044  */
5045 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO register field. */
5046 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_LSB 0
5047 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO register field. */
5048 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_MSB 0
5049 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO register field. */
5050 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_WIDTH 1
5051 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO register field value. */
5052 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_SET_MSK 0x00000001
5053 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO register field value. */
5054 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_CLR_MSK 0xfffffffe
5055 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO register field. */
5056 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_RESET 0x0
5057 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO field value from a register. */
5058 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_GET(value) (((value) & 0x00000001) >> 0)
5059 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO register field value suitable for setting the register. */
5060 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_SET(value) (((value) << 0) & 0x00000001)
5061 
5062 #ifndef __ASSEMBLY__
5063 /*
5064  * WARNING: The C register and register group struct declarations are provided for
5065  * convenience and illustrative purposes. They should, however, be used with
5066  * caution as the C language standard provides no guarantees about the alignment or
5067  * atomicity of device memory accesses. The recommended practice for writing
5068  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5069  * alt_write_word() functions.
5070  *
5071  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO.
5072  */
5073 struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_s
5074 {
5075  uint32_t STATGO : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO */
5076  uint32_t : 31; /* *UNDEFINED* */
5077 };
5078 
5079 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO. */
5080 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_s ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_t;
5081 #endif /* __ASSEMBLY__ */
5082 
5083 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO register. */
5084 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_RESET 0x00000000
5085 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO register from the beginning of the component. */
5086 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_OFST 0x28
5087 
5088 /*
5089  * Register : Probe_emacs_main_Probe_StatAlarmMin
5090  *
5091  *
5092  * Register Layout
5093  *
5094  * Bits | Access | Reset | Description
5095  * :-------|:-------|:------|:-----------------------------------------------------
5096  * [31:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN
5097  *
5098  */
5099 /*
5100  * Field : STATALARMMIN
5101  *
5102  * Register StatAlarmMin contains the minimum count value used in statistics alarm
5103  * comparisons. The number of bits is equal to twice the value set forparameter
5104  * wStatisticsCounter. When parameter statisticsCounterAlarm is set to False,
5105  * StatAlarmMin is reserved.
5106  *
5107  * Field Access Macros:
5108  *
5109  */
5110 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN register field. */
5111 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_LSB 0
5112 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN register field. */
5113 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_MSB 31
5114 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN register field. */
5115 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_WIDTH 32
5116 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN register field value. */
5117 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_SET_MSK 0xffffffff
5118 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN register field value. */
5119 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_CLR_MSK 0x00000000
5120 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN register field. */
5121 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_RESET 0x0
5122 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN field value from a register. */
5123 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_GET(value) (((value) & 0xffffffff) >> 0)
5124 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN register field value suitable for setting the register. */
5125 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_SET(value) (((value) << 0) & 0xffffffff)
5126 
5127 #ifndef __ASSEMBLY__
5128 /*
5129  * WARNING: The C register and register group struct declarations are provided for
5130  * convenience and illustrative purposes. They should, however, be used with
5131  * caution as the C language standard provides no guarantees about the alignment or
5132  * atomicity of device memory accesses. The recommended practice for writing
5133  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5134  * alt_write_word() functions.
5135  *
5136  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN.
5137  */
5138 struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_s
5139 {
5140  uint32_t STATALARMMIN : 32; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN */
5141 };
5142 
5143 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN. */
5144 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_s ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_t;
5145 #endif /* __ASSEMBLY__ */
5146 
5147 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN register. */
5148 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_RESET 0x00000000
5149 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN register from the beginning of the component. */
5150 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_OFST 0x2c
5151 
5152 /*
5153  * Register : Probe_emacs_main_Probe_StatAlarmMax
5154  *
5155  *
5156  * Register Layout
5157  *
5158  * Bits | Access | Reset | Description
5159  * :-------|:-------|:------|:-----------------------------------------------------
5160  * [31:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX
5161  *
5162  */
5163 /*
5164  * Field : STATALARMMAX
5165  *
5166  * Register StatAlarmMax contains the maximum count value used in statistics alarm
5167  * comparisons.The number of bits is equal to twice the value set for parameter
5168  * wStatisticsCounter. When parameter statisticsCounterAlarm is set to False,
5169  * StatAlarmMax is reserved.
5170  *
5171  * Field Access Macros:
5172  *
5173  */
5174 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX register field. */
5175 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_LSB 0
5176 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX register field. */
5177 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_MSB 31
5178 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX register field. */
5179 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_WIDTH 32
5180 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX register field value. */
5181 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_SET_MSK 0xffffffff
5182 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX register field value. */
5183 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_CLR_MSK 0x00000000
5184 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX register field. */
5185 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_RESET 0x0
5186 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX field value from a register. */
5187 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_GET(value) (((value) & 0xffffffff) >> 0)
5188 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX register field value suitable for setting the register. */
5189 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_SET(value) (((value) << 0) & 0xffffffff)
5190 
5191 #ifndef __ASSEMBLY__
5192 /*
5193  * WARNING: The C register and register group struct declarations are provided for
5194  * convenience and illustrative purposes. They should, however, be used with
5195  * caution as the C language standard provides no guarantees about the alignment or
5196  * atomicity of device memory accesses. The recommended practice for writing
5197  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5198  * alt_write_word() functions.
5199  *
5200  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX.
5201  */
5202 struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_s
5203 {
5204  uint32_t STATALARMMAX : 32; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX */
5205 };
5206 
5207 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX. */
5208 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_s ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_t;
5209 #endif /* __ASSEMBLY__ */
5210 
5211 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX register. */
5212 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_RESET 0x00000000
5213 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX register from the beginning of the component. */
5214 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_OFST 0x30
5215 
5216 /*
5217  * Register : Probe_emacs_main_Probe_StatAlarmStatus
5218  *
5219  *
5220  * Register Layout
5221  *
5222  * Bits | Access | Reset | Description
5223  * :-------|:-------|:--------|:-------------------------------------------------------
5224  * [0] | R | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT
5225  * [31:1] | ??? | Unknown | *UNDEFINED*
5226  *
5227  */
5228 /*
5229  * Field : STATALARMSTATUS
5230  *
5231  * Register StatAlarmStatus is a read-only 1-bit register indicating that at least
5232  * one statistics counter has exceeded the programmed values for registers
5233  * StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values
5234  * stored in register MainCtl fields StatAlarmStatus and AlarmEn. When parameter
5235  * statisticsCounterAlarm is set to False, StatAlarmStatus is reserved.
5236  *
5237  * Field Access Macros:
5238  *
5239  */
5240 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT register field. */
5241 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_LSB 0
5242 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT register field. */
5243 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_MSB 0
5244 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT register field. */
5245 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_WIDTH 1
5246 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT register field value. */
5247 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_SET_MSK 0x00000001
5248 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT register field value. */
5249 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_CLR_MSK 0xfffffffe
5250 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT register field. */
5251 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_RESET 0x0
5252 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT field value from a register. */
5253 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_GET(value) (((value) & 0x00000001) >> 0)
5254 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT register field value suitable for setting the register. */
5255 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_SET(value) (((value) << 0) & 0x00000001)
5256 
5257 #ifndef __ASSEMBLY__
5258 /*
5259  * WARNING: The C register and register group struct declarations are provided for
5260  * convenience and illustrative purposes. They should, however, be used with
5261  * caution as the C language standard provides no guarantees about the alignment or
5262  * atomicity of device memory accesses. The recommended practice for writing
5263  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5264  * alt_write_word() functions.
5265  *
5266  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT.
5267  */
5268 struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_s
5269 {
5270  const uint32_t STATALARMSTATUS : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT */
5271  uint32_t : 31; /* *UNDEFINED* */
5272 };
5273 
5274 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT. */
5275 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_s ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_t;
5276 #endif /* __ASSEMBLY__ */
5277 
5278 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT register. */
5279 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_RESET 0x00000000
5280 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT register from the beginning of the component. */
5281 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_OFST 0x34
5282 
5283 /*
5284  * Register : Probe_emacs_main_Probe_StatAlarmClr
5285  *
5286  *
5287  * Register Layout
5288  *
5289  * Bits | Access | Reset | Description
5290  * :-------|:-------|:--------|:-----------------------------------------------------
5291  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR
5292  * [31:1] | ??? | Unknown | *UNDEFINED*
5293  *
5294  */
5295 /*
5296  * Field : STATALARMCLR
5297  *
5298  * Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears
5299  * the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to
5300  * False, StatAlarmClr is reserved.NOTE The written value is not stored in
5301  * StatAlarmClr. A read always returns 0.
5302  *
5303  * Field Access Macros:
5304  *
5305  */
5306 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR register field. */
5307 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_LSB 0
5308 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR register field. */
5309 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_MSB 0
5310 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR register field. */
5311 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_WIDTH 1
5312 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR register field value. */
5313 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_SET_MSK 0x00000001
5314 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR register field value. */
5315 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_CLR_MSK 0xfffffffe
5316 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR register field. */
5317 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_RESET 0x0
5318 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR field value from a register. */
5319 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_GET(value) (((value) & 0x00000001) >> 0)
5320 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR register field value suitable for setting the register. */
5321 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_SET(value) (((value) << 0) & 0x00000001)
5322 
5323 #ifndef __ASSEMBLY__
5324 /*
5325  * WARNING: The C register and register group struct declarations are provided for
5326  * convenience and illustrative purposes. They should, however, be used with
5327  * caution as the C language standard provides no guarantees about the alignment or
5328  * atomicity of device memory accesses. The recommended practice for writing
5329  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5330  * alt_write_word() functions.
5331  *
5332  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR.
5333  */
5334 struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_s
5335 {
5336  uint32_t STATALARMCLR : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR */
5337  uint32_t : 31; /* *UNDEFINED* */
5338 };
5339 
5340 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR. */
5341 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_s ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_t;
5342 #endif /* __ASSEMBLY__ */
5343 
5344 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR register. */
5345 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_RESET 0x00000000
5346 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR register from the beginning of the component. */
5347 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_OFST 0x38
5348 
5349 /*
5350  * Register : Probe_emacs_main_Probe_StatAlarmEn
5351  *
5352  *
5353  * Register Layout
5354  *
5355  * Bits | Access | Reset | Description
5356  * :-------|:-------|:--------|:---------------------------------------------------
5357  * [0] | RW | 0x1 | ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN
5358  * [31:1] | ??? | Unknown | *UNDEFINED*
5359  *
5360  */
5361 /*
5362  * Field : STATALARMEN
5363  *
5364  * Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and
5365  * CtiTrigOut(1) signal interrupts.
5366  *
5367  * Field Access Macros:
5368  *
5369  */
5370 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN register field. */
5371 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_LSB 0
5372 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN register field. */
5373 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_MSB 0
5374 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN register field. */
5375 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_WIDTH 1
5376 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN register field value. */
5377 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_SET_MSK 0x00000001
5378 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN register field value. */
5379 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_CLR_MSK 0xfffffffe
5380 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN register field. */
5381 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_RESET 0x1
5382 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN field value from a register. */
5383 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_GET(value) (((value) & 0x00000001) >> 0)
5384 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN register field value suitable for setting the register. */
5385 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_SET(value) (((value) << 0) & 0x00000001)
5386 
5387 #ifndef __ASSEMBLY__
5388 /*
5389  * WARNING: The C register and register group struct declarations are provided for
5390  * convenience and illustrative purposes. They should, however, be used with
5391  * caution as the C language standard provides no guarantees about the alignment or
5392  * atomicity of device memory accesses. The recommended practice for writing
5393  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5394  * alt_write_word() functions.
5395  *
5396  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN.
5397  */
5398 struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_s
5399 {
5400  uint32_t STATALARMEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN */
5401  uint32_t : 31; /* *UNDEFINED* */
5402 };
5403 
5404 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN. */
5405 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_s ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_t;
5406 #endif /* __ASSEMBLY__ */
5407 
5408 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN register. */
5409 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_RESET 0x00000001
5410 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN register from the beginning of the component. */
5411 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_OFST 0x3c
5412 
5413 /*
5414  * Register : Probe_emacs_main_Probe_Filters_0_RouteIdBase
5415  *
5416  *
5417  * Register Layout
5418  *
5419  * Bits | Access | Reset | Description
5420  * :--------|:-------|:--------|:-----------------------------------------------------------------
5421  * [18:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE
5422  * [31:19] | ??? | Unknown | *UNDEFINED*
5423  *
5424  */
5425 /*
5426  * Field : FILTERS_0_ROUTEIDBASE
5427  *
5428  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
5429  * filter packets.
5430  *
5431  * Field Access Macros:
5432  *
5433  */
5434 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
5435 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_LSB 0
5436 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
5437 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_MSB 18
5438 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
5439 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_WIDTH 19
5440 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field value. */
5441 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET_MSK 0x0007ffff
5442 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field value. */
5443 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_CLR_MSK 0xfff80000
5444 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
5445 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_RESET 0x0
5446 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE field value from a register. */
5447 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
5448 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field value suitable for setting the register. */
5449 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
5450 
5451 #ifndef __ASSEMBLY__
5452 /*
5453  * WARNING: The C register and register group struct declarations are provided for
5454  * convenience and illustrative purposes. They should, however, be used with
5455  * caution as the C language standard provides no guarantees about the alignment or
5456  * atomicity of device memory accesses. The recommended practice for writing
5457  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5458  * alt_write_word() functions.
5459  *
5460  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE.
5461  */
5462 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_s
5463 {
5464  uint32_t FILTERS_0_ROUTEIDBASE : 19; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE */
5465  uint32_t : 13; /* *UNDEFINED* */
5466 };
5467 
5468 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE. */
5469 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_t;
5470 #endif /* __ASSEMBLY__ */
5471 
5472 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE register. */
5473 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_RESET 0x00000000
5474 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE register from the beginning of the component. */
5475 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_OFST 0x44
5476 
5477 /*
5478  * Register : Probe_emacs_main_Probe_Filters_0_RouteIdMask
5479  *
5480  *
5481  * Register Layout
5482  *
5483  * Bits | Access | Reset | Description
5484  * :--------|:-------|:--------|:---------------------------------------------------------------
5485  * [18:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK
5486  * [31:19] | ??? | Unknown | *UNDEFINED*
5487  *
5488  */
5489 /*
5490  * Field : FILTERS_0_ROUTEIDMASK
5491  *
5492  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
5493  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
5494  * RouteIdMask = RouteIdBase & RouteIdMask.
5495  *
5496  * Field Access Macros:
5497  *
5498  */
5499 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
5500 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_LSB 0
5501 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
5502 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_MSB 18
5503 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
5504 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_WIDTH 19
5505 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field value. */
5506 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET_MSK 0x0007ffff
5507 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field value. */
5508 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_CLR_MSK 0xfff80000
5509 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
5510 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_RESET 0x0
5511 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK field value from a register. */
5512 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
5513 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field value suitable for setting the register. */
5514 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
5515 
5516 #ifndef __ASSEMBLY__
5517 /*
5518  * WARNING: The C register and register group struct declarations are provided for
5519  * convenience and illustrative purposes. They should, however, be used with
5520  * caution as the C language standard provides no guarantees about the alignment or
5521  * atomicity of device memory accesses. The recommended practice for writing
5522  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5523  * alt_write_word() functions.
5524  *
5525  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK.
5526  */
5527 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_s
5528 {
5529  uint32_t FILTERS_0_ROUTEIDMASK : 19; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK */
5530  uint32_t : 13; /* *UNDEFINED* */
5531 };
5532 
5533 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK. */
5534 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_t;
5535 #endif /* __ASSEMBLY__ */
5536 
5537 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK register. */
5538 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_RESET 0x00000000
5539 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK register from the beginning of the component. */
5540 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_OFST 0x48
5541 
5542 /*
5543  * Register : Probe_emacs_main_Probe_Filters_0_AddrBase_Low
5544  *
5545  *
5546  * Register Layout
5547  *
5548  * Bits | Access | Reset | Description
5549  * :-------|:-------|:------|:-------------------------------------------------------------------
5550  * [31:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW
5551  *
5552  */
5553 /*
5554  * Field : FILTERS_0_ADDRBASE_LOW
5555  *
5556  * Address LSB register.
5557  *
5558  * Field Access Macros:
5559  *
5560  */
5561 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
5562 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_LSB 0
5563 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
5564 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_MSB 31
5565 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
5566 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_WIDTH 32
5567 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field value. */
5568 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET_MSK 0xffffffff
5569 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field value. */
5570 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_CLR_MSK 0x00000000
5571 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
5572 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_RESET 0x0
5573 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW field value from a register. */
5574 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
5575 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field value suitable for setting the register. */
5576 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
5577 
5578 #ifndef __ASSEMBLY__
5579 /*
5580  * WARNING: The C register and register group struct declarations are provided for
5581  * convenience and illustrative purposes. They should, however, be used with
5582  * caution as the C language standard provides no guarantees about the alignment or
5583  * atomicity of device memory accesses. The recommended practice for writing
5584  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5585  * alt_write_word() functions.
5586  *
5587  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW.
5588  */
5589 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_s
5590 {
5591  uint32_t FILTERS_0_ADDRBASE_LOW : 32; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW */
5592 };
5593 
5594 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW. */
5595 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_t;
5596 #endif /* __ASSEMBLY__ */
5597 
5598 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW register. */
5599 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_RESET 0x00000000
5600 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW register from the beginning of the component. */
5601 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_OFST 0x4c
5602 
5603 /*
5604  * Register : Probe_emacs_main_Probe_Filters_0_WindowSize
5605  *
5606  *
5607  * Register Layout
5608  *
5609  * Bits | Access | Reset | Description
5610  * :-------|:-------|:--------|:---------------------------------------------------------------
5611  * [5:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE
5612  * [31:6] | ??? | Unknown | *UNDEFINED*
5613  *
5614  */
5615 /*
5616  * Field : FILTERS_0_WINDOWSIZE
5617  *
5618  * Register WindowSize contains the encoded address mask used to filter packets.
5619  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
5620  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
5621  * filteringof packets having an intersection with the AddrBase/WindowSize burst
5622  * aligned region, even if the region is smaller than the packet.
5623  *
5624  * Field Access Macros:
5625  *
5626  */
5627 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
5628 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_LSB 0
5629 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
5630 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_MSB 5
5631 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
5632 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_WIDTH 6
5633 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field value. */
5634 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET_MSK 0x0000003f
5635 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field value. */
5636 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_CLR_MSK 0xffffffc0
5637 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
5638 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_RESET 0x0
5639 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE field value from a register. */
5640 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
5641 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field value suitable for setting the register. */
5642 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
5643 
5644 #ifndef __ASSEMBLY__
5645 /*
5646  * WARNING: The C register and register group struct declarations are provided for
5647  * convenience and illustrative purposes. They should, however, be used with
5648  * caution as the C language standard provides no guarantees about the alignment or
5649  * atomicity of device memory accesses. The recommended practice for writing
5650  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5651  * alt_write_word() functions.
5652  *
5653  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE.
5654  */
5655 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_s
5656 {
5657  uint32_t FILTERS_0_WINDOWSIZE : 6; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE */
5658  uint32_t : 26; /* *UNDEFINED* */
5659 };
5660 
5661 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE. */
5662 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_t;
5663 #endif /* __ASSEMBLY__ */
5664 
5665 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE register. */
5666 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_RESET 0x00000000
5667 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE register from the beginning of the component. */
5668 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_OFST 0x54
5669 
5670 /*
5671  * Register : Probe_emacs_main_Probe_Filters_0_SecurityBase
5672  *
5673  *
5674  * Register Layout
5675  *
5676  * Bits | Access | Reset | Description
5677  * :-------|:-------|:--------|:-------------------------------------------------------------------
5678  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE
5679  * [31:3] | ??? | Unknown | *UNDEFINED*
5680  *
5681  */
5682 /*
5683  * Field : FILTERS_0_SECURITYBASE
5684  *
5685  * Register SecurityBase contains the security base used to filter packets.
5686  *
5687  * Field Access Macros:
5688  *
5689  */
5690 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
5691 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_LSB 0
5692 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
5693 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_MSB 2
5694 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
5695 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_WIDTH 3
5696 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field value. */
5697 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET_MSK 0x00000007
5698 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field value. */
5699 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_CLR_MSK 0xfffffff8
5700 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
5701 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_RESET 0x0
5702 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE field value from a register. */
5703 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
5704 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field value suitable for setting the register. */
5705 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
5706 
5707 #ifndef __ASSEMBLY__
5708 /*
5709  * WARNING: The C register and register group struct declarations are provided for
5710  * convenience and illustrative purposes. They should, however, be used with
5711  * caution as the C language standard provides no guarantees about the alignment or
5712  * atomicity of device memory accesses. The recommended practice for writing
5713  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5714  * alt_write_word() functions.
5715  *
5716  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE.
5717  */
5718 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_s
5719 {
5720  uint32_t FILTERS_0_SECURITYBASE : 3; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE */
5721  uint32_t : 29; /* *UNDEFINED* */
5722 };
5723 
5724 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE. */
5725 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_t;
5726 #endif /* __ASSEMBLY__ */
5727 
5728 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE register. */
5729 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_RESET 0x00000000
5730 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE register from the beginning of the component. */
5731 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_OFST 0x58
5732 
5733 /*
5734  * Register : Probe_emacs_main_Probe_Filters_0_SecurityMask
5735  *
5736  *
5737  * Register Layout
5738  *
5739  * Bits | Access | Reset | Description
5740  * :-------|:-------|:--------|:-----------------------------------------------------------------
5741  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK
5742  * [31:3] | ??? | Unknown | *UNDEFINED*
5743  *
5744  */
5745 /*
5746  * Field : FILTERS_0_SECURITYMASK
5747  *
5748  * Register SecurityMask is contains the security mask used to filter packets. A
5749  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
5750  * SecurityMasks.
5751  *
5752  * Field Access Macros:
5753  *
5754  */
5755 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
5756 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_LSB 0
5757 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
5758 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_MSB 2
5759 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
5760 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_WIDTH 3
5761 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field value. */
5762 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET_MSK 0x00000007
5763 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field value. */
5764 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_CLR_MSK 0xfffffff8
5765 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
5766 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_RESET 0x0
5767 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK field value from a register. */
5768 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
5769 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field value suitable for setting the register. */
5770 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
5771 
5772 #ifndef __ASSEMBLY__
5773 /*
5774  * WARNING: The C register and register group struct declarations are provided for
5775  * convenience and illustrative purposes. They should, however, be used with
5776  * caution as the C language standard provides no guarantees about the alignment or
5777  * atomicity of device memory accesses. The recommended practice for writing
5778  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5779  * alt_write_word() functions.
5780  *
5781  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK.
5782  */
5783 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_s
5784 {
5785  uint32_t FILTERS_0_SECURITYMASK : 3; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK */
5786  uint32_t : 29; /* *UNDEFINED* */
5787 };
5788 
5789 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK. */
5790 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_t;
5791 #endif /* __ASSEMBLY__ */
5792 
5793 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK register. */
5794 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_RESET 0x00000000
5795 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK register from the beginning of the component. */
5796 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_OFST 0x5c
5797 
5798 /*
5799  * Register : Probe_emacs_main_Probe_Filters_0_Opcode
5800  *
5801  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
5802  * based on packet opcodes (0 disables the filter):
5803  *
5804  * Register Layout
5805  *
5806  * Bits | Access | Reset | Description
5807  * :-------|:-------|:--------|:------------------------------------------------
5808  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN
5809  * [1] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN
5810  * [2] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN
5811  * [3] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN
5812  * [31:4] | ??? | Unknown | *UNDEFINED*
5813  *
5814  */
5815 /*
5816  * Field : RDEN
5817  *
5818  * Selects RD packets.
5819  *
5820  * Field Access Macros:
5821  *
5822  */
5823 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN register field. */
5824 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_LSB 0
5825 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN register field. */
5826 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_MSB 0
5827 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN register field. */
5828 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_WIDTH 1
5829 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN register field value. */
5830 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_SET_MSK 0x00000001
5831 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN register field value. */
5832 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_CLR_MSK 0xfffffffe
5833 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN register field. */
5834 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_RESET 0x0
5835 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN field value from a register. */
5836 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
5837 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN register field value suitable for setting the register. */
5838 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
5839 
5840 /*
5841  * Field : WREN
5842  *
5843  * Selects WR packets.
5844  *
5845  * Field Access Macros:
5846  *
5847  */
5848 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN register field. */
5849 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_LSB 1
5850 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN register field. */
5851 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_MSB 1
5852 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN register field. */
5853 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_WIDTH 1
5854 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN register field value. */
5855 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_SET_MSK 0x00000002
5856 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN register field value. */
5857 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_CLR_MSK 0xfffffffd
5858 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN register field. */
5859 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_RESET 0x0
5860 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN field value from a register. */
5861 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
5862 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN register field value suitable for setting the register. */
5863 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
5864 
5865 /*
5866  * Field : LOCKEN
5867  *
5868  * Selects RDX-WR, RDL, WRC and Linked sequence.
5869  *
5870  * Field Access Macros:
5871  *
5872  */
5873 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN register field. */
5874 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_LSB 2
5875 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN register field. */
5876 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_MSB 2
5877 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN register field. */
5878 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_WIDTH 1
5879 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN register field value. */
5880 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_SET_MSK 0x00000004
5881 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN register field value. */
5882 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
5883 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN register field. */
5884 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_RESET 0x0
5885 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN field value from a register. */
5886 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
5887 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN register field value suitable for setting the register. */
5888 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
5889 
5890 /*
5891  * Field : URGEN
5892  *
5893  * Selects URG packets (urgency).
5894  *
5895  * Field Access Macros:
5896  *
5897  */
5898 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN register field. */
5899 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_LSB 3
5900 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN register field. */
5901 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_MSB 3
5902 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN register field. */
5903 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_WIDTH 1
5904 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN register field value. */
5905 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_SET_MSK 0x00000008
5906 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN register field value. */
5907 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_CLR_MSK 0xfffffff7
5908 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN register field. */
5909 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_RESET 0x0
5910 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN field value from a register. */
5911 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
5912 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN register field value suitable for setting the register. */
5913 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
5914 
5915 #ifndef __ASSEMBLY__
5916 /*
5917  * WARNING: The C register and register group struct declarations are provided for
5918  * convenience and illustrative purposes. They should, however, be used with
5919  * caution as the C language standard provides no guarantees about the alignment or
5920  * atomicity of device memory accesses. The recommended practice for writing
5921  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5922  * alt_write_word() functions.
5923  *
5924  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE.
5925  */
5926 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_s
5927 {
5928  uint32_t RDEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN */
5929  uint32_t WREN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN */
5930  uint32_t LOCKEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN */
5931  uint32_t URGEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN */
5932  uint32_t : 28; /* *UNDEFINED* */
5933 };
5934 
5935 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE. */
5936 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_t;
5937 #endif /* __ASSEMBLY__ */
5938 
5939 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE register. */
5940 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RESET 0x00000000
5941 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE register from the beginning of the component. */
5942 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_OFST 0x60
5943 
5944 /*
5945  * Register : Probe_emacs_main_Probe_Filters_0_Status
5946  *
5947  * Register Status is 2-bit register that selects candidate packets based on packet
5948  * status.
5949  *
5950  * Register Layout
5951  *
5952  * Bits | Access | Reset | Description
5953  * :-------|:-------|:--------|:---------------------------------------------
5954  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN
5955  * [1] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN
5956  * [31:2] | ??? | Unknown | *UNDEFINED*
5957  *
5958  */
5959 /*
5960  * Field : REQEN
5961  *
5962  * Selects REQ status packets.
5963  *
5964  * Field Access Macros:
5965  *
5966  */
5967 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN register field. */
5968 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_LSB 0
5969 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN register field. */
5970 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_MSB 0
5971 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN register field. */
5972 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_WIDTH 1
5973 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN register field value. */
5974 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_SET_MSK 0x00000001
5975 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN register field value. */
5976 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_CLR_MSK 0xfffffffe
5977 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN register field. */
5978 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_RESET 0x0
5979 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN field value from a register. */
5980 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
5981 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN register field value suitable for setting the register. */
5982 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
5983 
5984 /*
5985  * Field : RSPEN
5986  *
5987  * Selects RSP and FAIL-CONT status packets.
5988  *
5989  * Field Access Macros:
5990  *
5991  */
5992 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN register field. */
5993 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_LSB 1
5994 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN register field. */
5995 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_MSB 1
5996 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN register field. */
5997 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_WIDTH 1
5998 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN register field value. */
5999 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_SET_MSK 0x00000002
6000 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN register field value. */
6001 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_CLR_MSK 0xfffffffd
6002 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN register field. */
6003 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_RESET 0x0
6004 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN field value from a register. */
6005 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
6006 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN register field value suitable for setting the register. */
6007 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
6008 
6009 #ifndef __ASSEMBLY__
6010 /*
6011  * WARNING: The C register and register group struct declarations are provided for
6012  * convenience and illustrative purposes. They should, however, be used with
6013  * caution as the C language standard provides no guarantees about the alignment or
6014  * atomicity of device memory accesses. The recommended practice for writing
6015  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6016  * alt_write_word() functions.
6017  *
6018  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT.
6019  */
6020 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_s
6021 {
6022  uint32_t REQEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN */
6023  uint32_t RSPEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN */
6024  uint32_t : 30; /* *UNDEFINED* */
6025 };
6026 
6027 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT. */
6028 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_t;
6029 #endif /* __ASSEMBLY__ */
6030 
6031 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT register. */
6032 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RESET 0x00000000
6033 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT register from the beginning of the component. */
6034 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_OFST 0x64
6035 
6036 /*
6037  * Register : Probe_emacs_main_Probe_Filters_0_Length
6038  *
6039  *
6040  * Register Layout
6041  *
6042  * Bits | Access | Reset | Description
6043  * :-------|:-------|:--------|:-------------------------------------------------
6044  * [3:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN
6045  * [31:4] | ??? | Unknown | *UNDEFINED*
6046  *
6047  */
6048 /*
6049  * Field : FILTERS_0_LENGTH
6050  *
6051  * Register Length is 4-bit register that selects candidate packets if their number
6052  * of bytes is less than or equal to 2**Length.
6053  *
6054  * Field Access Macros:
6055  *
6056  */
6057 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN register field. */
6058 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_LSB 0
6059 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN register field. */
6060 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_MSB 3
6061 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN register field. */
6062 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_WIDTH 4
6063 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN register field value. */
6064 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_SET_MSK 0x0000000f
6065 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN register field value. */
6066 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_CLR_MSK 0xfffffff0
6067 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN register field. */
6068 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_RESET 0x0
6069 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN field value from a register. */
6070 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_GET(value) (((value) & 0x0000000f) >> 0)
6071 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN register field value suitable for setting the register. */
6072 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_SET(value) (((value) << 0) & 0x0000000f)
6073 
6074 #ifndef __ASSEMBLY__
6075 /*
6076  * WARNING: The C register and register group struct declarations are provided for
6077  * convenience and illustrative purposes. They should, however, be used with
6078  * caution as the C language standard provides no guarantees about the alignment or
6079  * atomicity of device memory accesses. The recommended practice for writing
6080  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6081  * alt_write_word() functions.
6082  *
6083  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN.
6084  */
6085 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_s
6086 {
6087  uint32_t FILTERS_0_LENGTH : 4; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN */
6088  uint32_t : 28; /* *UNDEFINED* */
6089 };
6090 
6091 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN. */
6092 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_t;
6093 #endif /* __ASSEMBLY__ */
6094 
6095 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN register. */
6096 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_RESET 0x00000000
6097 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN register from the beginning of the component. */
6098 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_OFST 0x68
6099 
6100 /*
6101  * Register : Probe_emacs_main_Probe_Filters_0_Urgency
6102  *
6103  *
6104  * Register Layout
6105  *
6106  * Bits | Access | Reset | Description
6107  * :-------|:-------|:--------|:---------------------------------------------------------
6108  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY
6109  * [31:2] | ??? | Unknown | *UNDEFINED*
6110  *
6111  */
6112 /*
6113  * Field : FILTERS_0_URGENCY
6114  *
6115  * Register Urgency contains the minimum urgency level used to filter packets. A
6116  * packet is a candidate when its socket urgency is greater than or equal to the
6117  * urgency specified in the register.
6118  *
6119  * Field Access Macros:
6120  *
6121  */
6122 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
6123 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_LSB 0
6124 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
6125 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_MSB 1
6126 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
6127 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_WIDTH 2
6128 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field value. */
6129 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_SET_MSK 0x00000003
6130 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field value. */
6131 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_CLR_MSK 0xfffffffc
6132 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
6133 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_RESET 0x0
6134 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY field value from a register. */
6135 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
6136 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field value suitable for setting the register. */
6137 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_SET(value) (((value) << 0) & 0x00000003)
6138 
6139 #ifndef __ASSEMBLY__
6140 /*
6141  * WARNING: The C register and register group struct declarations are provided for
6142  * convenience and illustrative purposes. They should, however, be used with
6143  * caution as the C language standard provides no guarantees about the alignment or
6144  * atomicity of device memory accesses. The recommended practice for writing
6145  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6146  * alt_write_word() functions.
6147  *
6148  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY.
6149  */
6150 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_s
6151 {
6152  uint32_t FILTERS_0_URGENCY : 2; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY */
6153  uint32_t : 30; /* *UNDEFINED* */
6154 };
6155 
6156 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY. */
6157 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_t;
6158 #endif /* __ASSEMBLY__ */
6159 
6160 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY register. */
6161 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_RESET 0x00000000
6162 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY register from the beginning of the component. */
6163 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_OFST 0x6c
6164 
6165 /*
6166  * Register : Probe_emacs_main_Probe_Filters_1_RouteIdBase
6167  *
6168  *
6169  * Register Layout
6170  *
6171  * Bits | Access | Reset | Description
6172  * :--------|:-------|:--------|:-----------------------------------------------------------------
6173  * [18:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE
6174  * [31:19] | ??? | Unknown | *UNDEFINED*
6175  *
6176  */
6177 /*
6178  * Field : FILTERS_1_ROUTEIDBASE
6179  *
6180  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
6181  * filter packets.
6182  *
6183  * Field Access Macros:
6184  *
6185  */
6186 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field. */
6187 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_LSB 0
6188 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field. */
6189 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_MSB 18
6190 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field. */
6191 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_WIDTH 19
6192 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field value. */
6193 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET_MSK 0x0007ffff
6194 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field value. */
6195 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_CLR_MSK 0xfff80000
6196 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field. */
6197 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_RESET 0x0
6198 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE field value from a register. */
6199 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
6200 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE register field value suitable for setting the register. */
6201 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
6202 
6203 #ifndef __ASSEMBLY__
6204 /*
6205  * WARNING: The C register and register group struct declarations are provided for
6206  * convenience and illustrative purposes. They should, however, be used with
6207  * caution as the C language standard provides no guarantees about the alignment or
6208  * atomicity of device memory accesses. The recommended practice for writing
6209  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6210  * alt_write_word() functions.
6211  *
6212  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE.
6213  */
6214 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_s
6215 {
6216  uint32_t FILTERS_1_ROUTEIDBASE : 19; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE */
6217  uint32_t : 13; /* *UNDEFINED* */
6218 };
6219 
6220 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE. */
6221 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_t;
6222 #endif /* __ASSEMBLY__ */
6223 
6224 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE register. */
6225 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_RESET 0x00000000
6226 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE register from the beginning of the component. */
6227 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_OFST 0x80
6228 
6229 /*
6230  * Register : Probe_emacs_main_Probe_Filters_1_RouteIdMask
6231  *
6232  *
6233  * Register Layout
6234  *
6235  * Bits | Access | Reset | Description
6236  * :--------|:-------|:--------|:---------------------------------------------------------------
6237  * [18:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK
6238  * [31:19] | ??? | Unknown | *UNDEFINED*
6239  *
6240  */
6241 /*
6242  * Field : FILTERS_1_ROUTEIDMASK
6243  *
6244  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
6245  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
6246  * RouteIdMask = RouteIdBase & RouteIdMask.
6247  *
6248  * Field Access Macros:
6249  *
6250  */
6251 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field. */
6252 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_LSB 0
6253 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field. */
6254 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_MSB 18
6255 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field. */
6256 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_WIDTH 19
6257 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field value. */
6258 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET_MSK 0x0007ffff
6259 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field value. */
6260 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_CLR_MSK 0xfff80000
6261 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field. */
6262 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_RESET 0x0
6263 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK field value from a register. */
6264 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
6265 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK register field value suitable for setting the register. */
6266 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
6267 
6268 #ifndef __ASSEMBLY__
6269 /*
6270  * WARNING: The C register and register group struct declarations are provided for
6271  * convenience and illustrative purposes. They should, however, be used with
6272  * caution as the C language standard provides no guarantees about the alignment or
6273  * atomicity of device memory accesses. The recommended practice for writing
6274  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6275  * alt_write_word() functions.
6276  *
6277  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK.
6278  */
6279 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_s
6280 {
6281  uint32_t FILTERS_1_ROUTEIDMASK : 19; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK */
6282  uint32_t : 13; /* *UNDEFINED* */
6283 };
6284 
6285 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK. */
6286 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_t;
6287 #endif /* __ASSEMBLY__ */
6288 
6289 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK register. */
6290 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_RESET 0x00000000
6291 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK register from the beginning of the component. */
6292 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_OFST 0x84
6293 
6294 /*
6295  * Register : Probe_emacs_main_Probe_Filters_1_AddrBase_Low
6296  *
6297  *
6298  * Register Layout
6299  *
6300  * Bits | Access | Reset | Description
6301  * :-------|:-------|:------|:-------------------------------------------------------------------
6302  * [31:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW
6303  *
6304  */
6305 /*
6306  * Field : FILTERS_1_ADDRBASE_LOW
6307  *
6308  * Address LSB register.
6309  *
6310  * Field Access Macros:
6311  *
6312  */
6313 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field. */
6314 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_LSB 0
6315 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field. */
6316 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_MSB 31
6317 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field. */
6318 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_WIDTH 32
6319 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field value. */
6320 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET_MSK 0xffffffff
6321 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field value. */
6322 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_CLR_MSK 0x00000000
6323 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field. */
6324 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_RESET 0x0
6325 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW field value from a register. */
6326 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
6327 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW register field value suitable for setting the register. */
6328 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
6329 
6330 #ifndef __ASSEMBLY__
6331 /*
6332  * WARNING: The C register and register group struct declarations are provided for
6333  * convenience and illustrative purposes. They should, however, be used with
6334  * caution as the C language standard provides no guarantees about the alignment or
6335  * atomicity of device memory accesses. The recommended practice for writing
6336  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6337  * alt_write_word() functions.
6338  *
6339  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW.
6340  */
6341 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_s
6342 {
6343  uint32_t FILTERS_1_ADDRBASE_LOW : 32; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW */
6344 };
6345 
6346 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW. */
6347 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_t;
6348 #endif /* __ASSEMBLY__ */
6349 
6350 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW register. */
6351 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_RESET 0x00000000
6352 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW register from the beginning of the component. */
6353 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_OFST 0x88
6354 
6355 /*
6356  * Register : Probe_emacs_main_Probe_Filters_1_WindowSize
6357  *
6358  *
6359  * Register Layout
6360  *
6361  * Bits | Access | Reset | Description
6362  * :-------|:-------|:--------|:---------------------------------------------------------------
6363  * [5:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE
6364  * [31:6] | ??? | Unknown | *UNDEFINED*
6365  *
6366  */
6367 /*
6368  * Field : FILTERS_1_WINDOWSIZE
6369  *
6370  * Register WindowSize contains the encoded address mask used to filter packets.
6371  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
6372  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
6373  * filteringof packets having an intersection with the AddrBase/WindowSize burst
6374  * aligned region, even if the region is smaller than the packet.
6375  *
6376  * Field Access Macros:
6377  *
6378  */
6379 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field. */
6380 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_LSB 0
6381 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field. */
6382 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_MSB 5
6383 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field. */
6384 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_WIDTH 6
6385 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field value. */
6386 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET_MSK 0x0000003f
6387 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field value. */
6388 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_CLR_MSK 0xffffffc0
6389 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field. */
6390 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_RESET 0x0
6391 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE field value from a register. */
6392 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
6393 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE register field value suitable for setting the register. */
6394 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
6395 
6396 #ifndef __ASSEMBLY__
6397 /*
6398  * WARNING: The C register and register group struct declarations are provided for
6399  * convenience and illustrative purposes. They should, however, be used with
6400  * caution as the C language standard provides no guarantees about the alignment or
6401  * atomicity of device memory accesses. The recommended practice for writing
6402  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6403  * alt_write_word() functions.
6404  *
6405  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE.
6406  */
6407 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_s
6408 {
6409  uint32_t FILTERS_1_WINDOWSIZE : 6; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE */
6410  uint32_t : 26; /* *UNDEFINED* */
6411 };
6412 
6413 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE. */
6414 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_t;
6415 #endif /* __ASSEMBLY__ */
6416 
6417 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE register. */
6418 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_RESET 0x00000000
6419 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE register from the beginning of the component. */
6420 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_OFST 0x90
6421 
6422 /*
6423  * Register : Probe_emacs_main_Probe_Filters_1_SecurityBase
6424  *
6425  *
6426  * Register Layout
6427  *
6428  * Bits | Access | Reset | Description
6429  * :-------|:-------|:--------|:-------------------------------------------------------------------
6430  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE
6431  * [31:3] | ??? | Unknown | *UNDEFINED*
6432  *
6433  */
6434 /*
6435  * Field : FILTERS_1_SECURITYBASE
6436  *
6437  * Register SecurityBase contains the security base used to filter packets.
6438  *
6439  * Field Access Macros:
6440  *
6441  */
6442 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field. */
6443 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_LSB 0
6444 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field. */
6445 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_MSB 2
6446 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field. */
6447 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_WIDTH 3
6448 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field value. */
6449 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET_MSK 0x00000007
6450 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field value. */
6451 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_CLR_MSK 0xfffffff8
6452 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field. */
6453 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_RESET 0x0
6454 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE field value from a register. */
6455 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
6456 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE register field value suitable for setting the register. */
6457 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
6458 
6459 #ifndef __ASSEMBLY__
6460 /*
6461  * WARNING: The C register and register group struct declarations are provided for
6462  * convenience and illustrative purposes. They should, however, be used with
6463  * caution as the C language standard provides no guarantees about the alignment or
6464  * atomicity of device memory accesses. The recommended practice for writing
6465  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6466  * alt_write_word() functions.
6467  *
6468  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE.
6469  */
6470 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_s
6471 {
6472  uint32_t FILTERS_1_SECURITYBASE : 3; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE */
6473  uint32_t : 29; /* *UNDEFINED* */
6474 };
6475 
6476 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE. */
6477 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_t;
6478 #endif /* __ASSEMBLY__ */
6479 
6480 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE register. */
6481 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_RESET 0x00000000
6482 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE register from the beginning of the component. */
6483 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_OFST 0x94
6484 
6485 /*
6486  * Register : Probe_emacs_main_Probe_Filters_1_SecurityMask
6487  *
6488  *
6489  * Register Layout
6490  *
6491  * Bits | Access | Reset | Description
6492  * :-------|:-------|:--------|:-----------------------------------------------------------------
6493  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK
6494  * [31:3] | ??? | Unknown | *UNDEFINED*
6495  *
6496  */
6497 /*
6498  * Field : FILTERS_1_SECURITYMASK
6499  *
6500  * Register SecurityMask is contains the security mask used to filter packets. A
6501  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
6502  * SecurityMasks.
6503  *
6504  * Field Access Macros:
6505  *
6506  */
6507 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field. */
6508 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_LSB 0
6509 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field. */
6510 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_MSB 2
6511 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field. */
6512 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_WIDTH 3
6513 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field value. */
6514 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET_MSK 0x00000007
6515 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field value. */
6516 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_CLR_MSK 0xfffffff8
6517 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field. */
6518 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_RESET 0x0
6519 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK field value from a register. */
6520 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
6521 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK register field value suitable for setting the register. */
6522 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
6523 
6524 #ifndef __ASSEMBLY__
6525 /*
6526  * WARNING: The C register and register group struct declarations are provided for
6527  * convenience and illustrative purposes. They should, however, be used with
6528  * caution as the C language standard provides no guarantees about the alignment or
6529  * atomicity of device memory accesses. The recommended practice for writing
6530  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6531  * alt_write_word() functions.
6532  *
6533  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK.
6534  */
6535 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_s
6536 {
6537  uint32_t FILTERS_1_SECURITYMASK : 3; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK */
6538  uint32_t : 29; /* *UNDEFINED* */
6539 };
6540 
6541 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK. */
6542 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_t;
6543 #endif /* __ASSEMBLY__ */
6544 
6545 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK register. */
6546 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_RESET 0x00000000
6547 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK register from the beginning of the component. */
6548 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_OFST 0x98
6549 
6550 /*
6551  * Register : Probe_emacs_main_Probe_Filters_1_Opcode
6552  *
6553  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
6554  * based on packet opcodes (0 disables the filter):
6555  *
6556  * Register Layout
6557  *
6558  * Bits | Access | Reset | Description
6559  * :-------|:-------|:--------|:------------------------------------------------
6560  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN
6561  * [1] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN
6562  * [2] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN
6563  * [3] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN
6564  * [31:4] | ??? | Unknown | *UNDEFINED*
6565  *
6566  */
6567 /*
6568  * Field : RDEN
6569  *
6570  * Selects RD packets.
6571  *
6572  * Field Access Macros:
6573  *
6574  */
6575 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN register field. */
6576 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_LSB 0
6577 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN register field. */
6578 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_MSB 0
6579 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN register field. */
6580 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_WIDTH 1
6581 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN register field value. */
6582 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_SET_MSK 0x00000001
6583 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN register field value. */
6584 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_CLR_MSK 0xfffffffe
6585 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN register field. */
6586 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_RESET 0x0
6587 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN field value from a register. */
6588 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
6589 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN register field value suitable for setting the register. */
6590 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
6591 
6592 /*
6593  * Field : WREN
6594  *
6595  * Selects WR packets.
6596  *
6597  * Field Access Macros:
6598  *
6599  */
6600 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN register field. */
6601 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_LSB 1
6602 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN register field. */
6603 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_MSB 1
6604 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN register field. */
6605 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_WIDTH 1
6606 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN register field value. */
6607 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_SET_MSK 0x00000002
6608 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN register field value. */
6609 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_CLR_MSK 0xfffffffd
6610 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN register field. */
6611 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_RESET 0x0
6612 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN field value from a register. */
6613 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
6614 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN register field value suitable for setting the register. */
6615 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
6616 
6617 /*
6618  * Field : LOCKEN
6619  *
6620  * Selects RDX-WR, RDL, WRC and Linked sequence.
6621  *
6622  * Field Access Macros:
6623  *
6624  */
6625 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN register field. */
6626 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_LSB 2
6627 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN register field. */
6628 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_MSB 2
6629 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN register field. */
6630 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_WIDTH 1
6631 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN register field value. */
6632 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_SET_MSK 0x00000004
6633 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN register field value. */
6634 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
6635 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN register field. */
6636 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_RESET 0x0
6637 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN field value from a register. */
6638 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
6639 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN register field value suitable for setting the register. */
6640 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
6641 
6642 /*
6643  * Field : URGEN
6644  *
6645  * Selects URG packets (urgency).
6646  *
6647  * Field Access Macros:
6648  *
6649  */
6650 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN register field. */
6651 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_LSB 3
6652 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN register field. */
6653 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_MSB 3
6654 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN register field. */
6655 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_WIDTH 1
6656 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN register field value. */
6657 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_SET_MSK 0x00000008
6658 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN register field value. */
6659 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_CLR_MSK 0xfffffff7
6660 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN register field. */
6661 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_RESET 0x0
6662 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN field value from a register. */
6663 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
6664 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN register field value suitable for setting the register. */
6665 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
6666 
6667 #ifndef __ASSEMBLY__
6668 /*
6669  * WARNING: The C register and register group struct declarations are provided for
6670  * convenience and illustrative purposes. They should, however, be used with
6671  * caution as the C language standard provides no guarantees about the alignment or
6672  * atomicity of device memory accesses. The recommended practice for writing
6673  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6674  * alt_write_word() functions.
6675  *
6676  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE.
6677  */
6678 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_s
6679 {
6680  uint32_t RDEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN */
6681  uint32_t WREN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN */
6682  uint32_t LOCKEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN */
6683  uint32_t URGEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN */
6684  uint32_t : 28; /* *UNDEFINED* */
6685 };
6686 
6687 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE. */
6688 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_t;
6689 #endif /* __ASSEMBLY__ */
6690 
6691 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE register. */
6692 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RESET 0x00000000
6693 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE register from the beginning of the component. */
6694 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_OFST 0x9c
6695 
6696 /*
6697  * Register : Probe_emacs_main_Probe_Filters_1_Status
6698  *
6699  * Register Status is 2-bit register that selects candidate packets based on packet
6700  * status.
6701  *
6702  * Register Layout
6703  *
6704  * Bits | Access | Reset | Description
6705  * :-------|:-------|:--------|:---------------------------------------------
6706  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN
6707  * [1] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN
6708  * [31:2] | ??? | Unknown | *UNDEFINED*
6709  *
6710  */
6711 /*
6712  * Field : REQEN
6713  *
6714  * Selects REQ status packets.
6715  *
6716  * Field Access Macros:
6717  *
6718  */
6719 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN register field. */
6720 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_LSB 0
6721 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN register field. */
6722 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_MSB 0
6723 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN register field. */
6724 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_WIDTH 1
6725 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN register field value. */
6726 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_SET_MSK 0x00000001
6727 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN register field value. */
6728 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_CLR_MSK 0xfffffffe
6729 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN register field. */
6730 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_RESET 0x0
6731 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN field value from a register. */
6732 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
6733 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN register field value suitable for setting the register. */
6734 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
6735 
6736 /*
6737  * Field : RSPEN
6738  *
6739  * Selects RSP and FAIL-CONT status packets.
6740  *
6741  * Field Access Macros:
6742  *
6743  */
6744 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN register field. */
6745 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_LSB 1
6746 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN register field. */
6747 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_MSB 1
6748 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN register field. */
6749 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_WIDTH 1
6750 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN register field value. */
6751 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_SET_MSK 0x00000002
6752 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN register field value. */
6753 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_CLR_MSK 0xfffffffd
6754 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN register field. */
6755 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_RESET 0x0
6756 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN field value from a register. */
6757 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
6758 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN register field value suitable for setting the register. */
6759 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
6760 
6761 #ifndef __ASSEMBLY__
6762 /*
6763  * WARNING: The C register and register group struct declarations are provided for
6764  * convenience and illustrative purposes. They should, however, be used with
6765  * caution as the C language standard provides no guarantees about the alignment or
6766  * atomicity of device memory accesses. The recommended practice for writing
6767  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6768  * alt_write_word() functions.
6769  *
6770  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT.
6771  */
6772 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_s
6773 {
6774  uint32_t REQEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN */
6775  uint32_t RSPEN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN */
6776  uint32_t : 30; /* *UNDEFINED* */
6777 };
6778 
6779 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT. */
6780 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_t;
6781 #endif /* __ASSEMBLY__ */
6782 
6783 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT register. */
6784 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RESET 0x00000000
6785 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT register from the beginning of the component. */
6786 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_OFST 0xa0
6787 
6788 /*
6789  * Register : Probe_emacs_main_Probe_Filters_1_Length
6790  *
6791  *
6792  * Register Layout
6793  *
6794  * Bits | Access | Reset | Description
6795  * :-------|:-------|:--------|:-------------------------------------------------
6796  * [3:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN
6797  * [31:4] | ??? | Unknown | *UNDEFINED*
6798  *
6799  */
6800 /*
6801  * Field : FILTERS_1_LENGTH
6802  *
6803  * Register Length is 4-bit register that selects candidate packets if their number
6804  * of bytes is less than or equal to 2**Length.
6805  *
6806  * Field Access Macros:
6807  *
6808  */
6809 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN register field. */
6810 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_LSB 0
6811 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN register field. */
6812 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_MSB 3
6813 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN register field. */
6814 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_WIDTH 4
6815 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN register field value. */
6816 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_SET_MSK 0x0000000f
6817 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN register field value. */
6818 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_CLR_MSK 0xfffffff0
6819 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN register field. */
6820 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_RESET 0x0
6821 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN field value from a register. */
6822 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_GET(value) (((value) & 0x0000000f) >> 0)
6823 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN register field value suitable for setting the register. */
6824 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_SET(value) (((value) << 0) & 0x0000000f)
6825 
6826 #ifndef __ASSEMBLY__
6827 /*
6828  * WARNING: The C register and register group struct declarations are provided for
6829  * convenience and illustrative purposes. They should, however, be used with
6830  * caution as the C language standard provides no guarantees about the alignment or
6831  * atomicity of device memory accesses. The recommended practice for writing
6832  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6833  * alt_write_word() functions.
6834  *
6835  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN.
6836  */
6837 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_s
6838 {
6839  uint32_t FILTERS_1_LENGTH : 4; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN */
6840  uint32_t : 28; /* *UNDEFINED* */
6841 };
6842 
6843 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN. */
6844 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_t;
6845 #endif /* __ASSEMBLY__ */
6846 
6847 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN register. */
6848 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_RESET 0x00000000
6849 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN register from the beginning of the component. */
6850 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_OFST 0xa4
6851 
6852 /*
6853  * Register : Probe_emacs_main_Probe_Filters_1_Urgency
6854  *
6855  *
6856  * Register Layout
6857  *
6858  * Bits | Access | Reset | Description
6859  * :-------|:-------|:--------|:---------------------------------------------------------
6860  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY
6861  * [31:2] | ??? | Unknown | *UNDEFINED*
6862  *
6863  */
6864 /*
6865  * Field : FILTERS_1_URGENCY
6866  *
6867  * Register Urgency contains the minimum urgency level used to filter packets. A
6868  * packet is a candidate when its socket urgency is greater than or equal to the
6869  * urgency specified in the register.
6870  *
6871  * Field Access Macros:
6872  *
6873  */
6874 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field. */
6875 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_LSB 0
6876 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field. */
6877 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_MSB 1
6878 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field. */
6879 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_WIDTH 2
6880 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field value. */
6881 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_SET_MSK 0x00000003
6882 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field value. */
6883 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_CLR_MSK 0xfffffffc
6884 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field. */
6885 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_RESET 0x0
6886 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY field value from a register. */
6887 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
6888 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY register field value suitable for setting the register. */
6889 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_SET(value) (((value) << 0) & 0x00000003)
6890 
6891 #ifndef __ASSEMBLY__
6892 /*
6893  * WARNING: The C register and register group struct declarations are provided for
6894  * convenience and illustrative purposes. They should, however, be used with
6895  * caution as the C language standard provides no guarantees about the alignment or
6896  * atomicity of device memory accesses. The recommended practice for writing
6897  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6898  * alt_write_word() functions.
6899  *
6900  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY.
6901  */
6902 struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_s
6903 {
6904  uint32_t FILTERS_1_URGENCY : 2; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY */
6905  uint32_t : 30; /* *UNDEFINED* */
6906 };
6907 
6908 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY. */
6909 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_s ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_t;
6910 #endif /* __ASSEMBLY__ */
6911 
6912 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY register. */
6913 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_RESET 0x00000000
6914 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY register from the beginning of the component. */
6915 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_OFST 0xa8
6916 
6917 /*
6918  * Register : Probe_emacs_main_Probe_Counters_0_PortSel
6919  *
6920  *
6921  * Register Layout
6922  *
6923  * Bits | Access | Reset | Description
6924  * :-------|:-------|:--------|:-----------------------------------------------------------
6925  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL
6926  * [31:1] | ??? | Unknown | *UNDEFINED*
6927  *
6928  */
6929 /*
6930  * Field : COUNTERS_0_PORTSEL
6931  *
6932  * Register PortSel indicates which NTTP link is associated with the counter. The
6933  * register can be changed at any time, with the change effective immediately. The
6934  * LUT and FILTx sources do not depend on this NTTP port selection.
6935  *
6936  * Field Access Macros:
6937  *
6938  */
6939 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field. */
6940 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_LSB 0
6941 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field. */
6942 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_MSB 0
6943 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field. */
6944 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_WIDTH 1
6945 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field value. */
6946 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_SET_MSK 0x00000001
6947 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field value. */
6948 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_CLR_MSK 0xfffffffe
6949 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field. */
6950 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_RESET 0x0
6951 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL field value from a register. */
6952 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
6953 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL register field value suitable for setting the register. */
6954 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
6955 
6956 #ifndef __ASSEMBLY__
6957 /*
6958  * WARNING: The C register and register group struct declarations are provided for
6959  * convenience and illustrative purposes. They should, however, be used with
6960  * caution as the C language standard provides no guarantees about the alignment or
6961  * atomicity of device memory accesses. The recommended practice for writing
6962  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6963  * alt_write_word() functions.
6964  *
6965  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL.
6966  */
6967 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_s
6968 {
6969  uint32_t COUNTERS_0_PORTSEL : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL */
6970  uint32_t : 31; /* *UNDEFINED* */
6971 };
6972 
6973 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL. */
6974 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_t;
6975 #endif /* __ASSEMBLY__ */
6976 
6977 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL register. */
6978 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_RESET 0x00000000
6979 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL register from the beginning of the component. */
6980 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_OFST 0x134
6981 
6982 /*
6983  * Register : Probe_emacs_main_Probe_Counters_0_Src
6984  *
6985  * Register CntSrc indicates the event source used to increment the counter.
6986  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
6987  * Filter) are equivalent to OFF.
6988  *
6989  * Register Layout
6990  *
6991  * Bits | Access | Reset | Description
6992  * :-------|:-------|:--------|:------------------------------------------------
6993  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT
6994  * [5] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT
6995  * [31:6] | ??? | Unknown | *UNDEFINED*
6996  *
6997  */
6998 /*
6999  * Field : INTEVENT
7000  *
7001  * Internal packet event
7002  *
7003  * Field Access Macros:
7004  *
7005  */
7006 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT register field. */
7007 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_LSB 0
7008 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT register field. */
7009 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_MSB 4
7010 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT register field. */
7011 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_WIDTH 5
7012 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT register field value. */
7013 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_SET_MSK 0x0000001f
7014 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT register field value. */
7015 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_CLR_MSK 0xffffffe0
7016 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT register field. */
7017 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_RESET 0x0
7018 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT field value from a register. */
7019 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
7020 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT register field value suitable for setting the register. */
7021 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
7022 
7023 /*
7024  * Field : EXTEVENT
7025  *
7026  * When set to 1 counts the cycles where ExtEvent[IntEvent] = 1. It exists when
7027  * nExtEvent > 0.
7028  *
7029  * Field Access Macros:
7030  *
7031  */
7032 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT register field. */
7033 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_LSB 5
7034 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT register field. */
7035 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_MSB 5
7036 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT register field. */
7037 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_WIDTH 1
7038 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT register field value. */
7039 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_SET_MSK 0x00000020
7040 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT register field value. */
7041 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_CLR_MSK 0xffffffdf
7042 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT register field. */
7043 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_RESET 0x0
7044 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT field value from a register. */
7045 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_GET(value) (((value) & 0x00000020) >> 5)
7046 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT register field value suitable for setting the register. */
7047 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_SET(value) (((value) << 5) & 0x00000020)
7048 
7049 #ifndef __ASSEMBLY__
7050 /*
7051  * WARNING: The C register and register group struct declarations are provided for
7052  * convenience and illustrative purposes. They should, however, be used with
7053  * caution as the C language standard provides no guarantees about the alignment or
7054  * atomicity of device memory accesses. The recommended practice for writing
7055  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7056  * alt_write_word() functions.
7057  *
7058  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC.
7059  */
7060 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_s
7061 {
7062  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT */
7063  uint32_t EXTEVENT : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT */
7064  uint32_t : 26; /* *UNDEFINED* */
7065 };
7066 
7067 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC. */
7068 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_t;
7069 #endif /* __ASSEMBLY__ */
7070 
7071 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC register. */
7072 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_RESET 0x00000000
7073 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC register from the beginning of the component. */
7074 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_OFST 0x138
7075 
7076 /*
7077  * Register : Probe_emacs_main_Probe_Counters_0_AlarmMode
7078  *
7079  *
7080  * Register Layout
7081  *
7082  * Bits | Access | Reset | Description
7083  * :-------|:-------|:--------|:-------------------------------------------------------------
7084  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD
7085  * [31:2] | ??? | Unknown | *UNDEFINED*
7086  *
7087  */
7088 /*
7089  * Field : COUNTERS_0_ALARMMODE
7090  *
7091  * Register AlarmMode is a 2-bit register that is present when parameter
7092  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
7093  * behavior of the counter.
7094  *
7095  * Field Access Macros:
7096  *
7097  */
7098 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
7099 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_LSB 0
7100 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
7101 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_MSB 1
7102 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
7103 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_WIDTH 2
7104 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field value. */
7105 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET_MSK 0x00000003
7106 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field value. */
7107 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_CLR_MSK 0xfffffffc
7108 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
7109 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_RESET 0x0
7110 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD field value from a register. */
7111 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
7112 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field value suitable for setting the register. */
7113 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
7114 
7115 #ifndef __ASSEMBLY__
7116 /*
7117  * WARNING: The C register and register group struct declarations are provided for
7118  * convenience and illustrative purposes. They should, however, be used with
7119  * caution as the C language standard provides no guarantees about the alignment or
7120  * atomicity of device memory accesses. The recommended practice for writing
7121  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7122  * alt_write_word() functions.
7123  *
7124  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD.
7125  */
7126 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_s
7127 {
7128  uint32_t COUNTERS_0_ALARMMODE : 2; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD */
7129  uint32_t : 30; /* *UNDEFINED* */
7130 };
7131 
7132 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD. */
7133 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_t;
7134 #endif /* __ASSEMBLY__ */
7135 
7136 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD register. */
7137 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_RESET 0x00000000
7138 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD register from the beginning of the component. */
7139 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_OFST 0x13c
7140 
7141 /*
7142  * Register : Probe_emacs_main_Probe_Counters_0_Val
7143  *
7144  *
7145  * Register Layout
7146  *
7147  * Bits | Access | Reset | Description
7148  * :--------|:-------|:--------|:---------------------------------------------------
7149  * [15:0] | R | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL
7150  * [31:16] | ??? | Unknown | *UNDEFINED*
7151  *
7152  */
7153 /*
7154  * Field : COUNTERS_0_VAL
7155  *
7156  * Register Val is a read-only register that is always present. The register
7157  * containsthe statistics counter value either pending StatAlarm output, or when
7158  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
7159  *
7160  * Field Access Macros:
7161  *
7162  */
7163 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field. */
7164 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_LSB 0
7165 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field. */
7166 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_MSB 15
7167 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field. */
7168 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_WIDTH 16
7169 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field value. */
7170 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET_MSK 0x0000ffff
7171 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field value. */
7172 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_CLR_MSK 0xffff0000
7173 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field. */
7174 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_RESET 0x0
7175 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL field value from a register. */
7176 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
7177 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field value suitable for setting the register. */
7178 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET(value) (((value) << 0) & 0x0000ffff)
7179 
7180 #ifndef __ASSEMBLY__
7181 /*
7182  * WARNING: The C register and register group struct declarations are provided for
7183  * convenience and illustrative purposes. They should, however, be used with
7184  * caution as the C language standard provides no guarantees about the alignment or
7185  * atomicity of device memory accesses. The recommended practice for writing
7186  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7187  * alt_write_word() functions.
7188  *
7189  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL.
7190  */
7191 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_s
7192 {
7193  const uint32_t COUNTERS_0_VAL : 16; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL */
7194  uint32_t : 16; /* *UNDEFINED* */
7195 };
7196 
7197 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL. */
7198 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_t;
7199 #endif /* __ASSEMBLY__ */
7200 
7201 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL register. */
7202 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_RESET 0x00000000
7203 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL register from the beginning of the component. */
7204 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_OFST 0x140
7205 
7206 /*
7207  * Register : Probe_emacs_main_Probe_Counters_1_PortSel
7208  *
7209  *
7210  * Register Layout
7211  *
7212  * Bits | Access | Reset | Description
7213  * :-------|:-------|:--------|:-----------------------------------------------------------
7214  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL
7215  * [31:1] | ??? | Unknown | *UNDEFINED*
7216  *
7217  */
7218 /*
7219  * Field : COUNTERS_1_PORTSEL
7220  *
7221  * Register PortSel indicates which NTTP link is associated with the counter. The
7222  * register can be changed at any time, with the change effective immediately. The
7223  * LUT and FILTx sources do not depend on this NTTP port selection.
7224  *
7225  * Field Access Macros:
7226  *
7227  */
7228 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field. */
7229 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_LSB 0
7230 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field. */
7231 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_MSB 0
7232 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field. */
7233 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_WIDTH 1
7234 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field value. */
7235 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_SET_MSK 0x00000001
7236 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field value. */
7237 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_CLR_MSK 0xfffffffe
7238 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field. */
7239 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_RESET 0x0
7240 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL field value from a register. */
7241 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
7242 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL register field value suitable for setting the register. */
7243 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
7244 
7245 #ifndef __ASSEMBLY__
7246 /*
7247  * WARNING: The C register and register group struct declarations are provided for
7248  * convenience and illustrative purposes. They should, however, be used with
7249  * caution as the C language standard provides no guarantees about the alignment or
7250  * atomicity of device memory accesses. The recommended practice for writing
7251  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7252  * alt_write_word() functions.
7253  *
7254  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL.
7255  */
7256 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_s
7257 {
7258  uint32_t COUNTERS_1_PORTSEL : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL */
7259  uint32_t : 31; /* *UNDEFINED* */
7260 };
7261 
7262 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL. */
7263 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_t;
7264 #endif /* __ASSEMBLY__ */
7265 
7266 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL register. */
7267 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_RESET 0x00000000
7268 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL register from the beginning of the component. */
7269 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_OFST 0x148
7270 
7271 /*
7272  * Register : Probe_emacs_main_Probe_Counters_1_Src
7273  *
7274  * Register CntSrc indicates the event source used to increment the counter.
7275  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
7276  * Filter) are equivalent to OFF.
7277  *
7278  * Register Layout
7279  *
7280  * Bits | Access | Reset | Description
7281  * :-------|:-------|:--------|:------------------------------------------------
7282  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT
7283  * [5] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT
7284  * [31:6] | ??? | Unknown | *UNDEFINED*
7285  *
7286  */
7287 /*
7288  * Field : INTEVENT
7289  *
7290  * Internal packet event
7291  *
7292  * Field Access Macros:
7293  *
7294  */
7295 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT register field. */
7296 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_LSB 0
7297 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT register field. */
7298 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_MSB 4
7299 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT register field. */
7300 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_WIDTH 5
7301 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT register field value. */
7302 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_SET_MSK 0x0000001f
7303 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT register field value. */
7304 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_CLR_MSK 0xffffffe0
7305 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT register field. */
7306 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_RESET 0x0
7307 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT field value from a register. */
7308 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
7309 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT register field value suitable for setting the register. */
7310 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
7311 
7312 /*
7313  * Field : EXTEVENT
7314  *
7315  * When set to 1 counts the cycles where ExtEvent[IntEvent] = 1. It exists when
7316  * nExtEvent > 0.
7317  *
7318  * Field Access Macros:
7319  *
7320  */
7321 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT register field. */
7322 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_LSB 5
7323 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT register field. */
7324 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_MSB 5
7325 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT register field. */
7326 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_WIDTH 1
7327 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT register field value. */
7328 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_SET_MSK 0x00000020
7329 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT register field value. */
7330 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_CLR_MSK 0xffffffdf
7331 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT register field. */
7332 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_RESET 0x0
7333 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT field value from a register. */
7334 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_GET(value) (((value) & 0x00000020) >> 5)
7335 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT register field value suitable for setting the register. */
7336 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_SET(value) (((value) << 5) & 0x00000020)
7337 
7338 #ifndef __ASSEMBLY__
7339 /*
7340  * WARNING: The C register and register group struct declarations are provided for
7341  * convenience and illustrative purposes. They should, however, be used with
7342  * caution as the C language standard provides no guarantees about the alignment or
7343  * atomicity of device memory accesses. The recommended practice for writing
7344  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7345  * alt_write_word() functions.
7346  *
7347  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC.
7348  */
7349 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_s
7350 {
7351  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT */
7352  uint32_t EXTEVENT : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT */
7353  uint32_t : 26; /* *UNDEFINED* */
7354 };
7355 
7356 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC. */
7357 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_t;
7358 #endif /* __ASSEMBLY__ */
7359 
7360 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC register. */
7361 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_RESET 0x00000000
7362 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC register from the beginning of the component. */
7363 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_OFST 0x14c
7364 
7365 /*
7366  * Register : Probe_emacs_main_Probe_Counters_1_AlarmMode
7367  *
7368  *
7369  * Register Layout
7370  *
7371  * Bits | Access | Reset | Description
7372  * :-------|:-------|:--------|:-------------------------------------------------------------
7373  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD
7374  * [31:2] | ??? | Unknown | *UNDEFINED*
7375  *
7376  */
7377 /*
7378  * Field : COUNTERS_1_ALARMMODE
7379  *
7380  * Register AlarmMode is a 2-bit register that is present when parameter
7381  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
7382  * behavior of the counter.
7383  *
7384  * Field Access Macros:
7385  *
7386  */
7387 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
7388 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_LSB 0
7389 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
7390 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_MSB 1
7391 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
7392 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_WIDTH 2
7393 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field value. */
7394 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET_MSK 0x00000003
7395 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field value. */
7396 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_CLR_MSK 0xfffffffc
7397 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
7398 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_RESET 0x0
7399 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD field value from a register. */
7400 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
7401 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field value suitable for setting the register. */
7402 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
7403 
7404 #ifndef __ASSEMBLY__
7405 /*
7406  * WARNING: The C register and register group struct declarations are provided for
7407  * convenience and illustrative purposes. They should, however, be used with
7408  * caution as the C language standard provides no guarantees about the alignment or
7409  * atomicity of device memory accesses. The recommended practice for writing
7410  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7411  * alt_write_word() functions.
7412  *
7413  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD.
7414  */
7415 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_s
7416 {
7417  uint32_t COUNTERS_1_ALARMMODE : 2; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD */
7418  uint32_t : 30; /* *UNDEFINED* */
7419 };
7420 
7421 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD. */
7422 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_t;
7423 #endif /* __ASSEMBLY__ */
7424 
7425 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD register. */
7426 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_RESET 0x00000000
7427 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD register from the beginning of the component. */
7428 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_OFST 0x150
7429 
7430 /*
7431  * Register : Probe_emacs_main_Probe_Counters_1_Val
7432  *
7433  *
7434  * Register Layout
7435  *
7436  * Bits | Access | Reset | Description
7437  * :--------|:-------|:--------|:---------------------------------------------------
7438  * [15:0] | R | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL
7439  * [31:16] | ??? | Unknown | *UNDEFINED*
7440  *
7441  */
7442 /*
7443  * Field : COUNTERS_1_VAL
7444  *
7445  * Register Val is a read-only register that is always present. The register
7446  * containsthe statistics counter value either pending StatAlarm output, or when
7447  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
7448  *
7449  * Field Access Macros:
7450  *
7451  */
7452 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field. */
7453 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_LSB 0
7454 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field. */
7455 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_MSB 15
7456 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field. */
7457 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_WIDTH 16
7458 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field value. */
7459 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_SET_MSK 0x0000ffff
7460 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field value. */
7461 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_CLR_MSK 0xffff0000
7462 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field. */
7463 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_RESET 0x0
7464 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL field value from a register. */
7465 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
7466 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field value suitable for setting the register. */
7467 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_SET(value) (((value) << 0) & 0x0000ffff)
7468 
7469 #ifndef __ASSEMBLY__
7470 /*
7471  * WARNING: The C register and register group struct declarations are provided for
7472  * convenience and illustrative purposes. They should, however, be used with
7473  * caution as the C language standard provides no guarantees about the alignment or
7474  * atomicity of device memory accesses. The recommended practice for writing
7475  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7476  * alt_write_word() functions.
7477  *
7478  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL.
7479  */
7480 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_s
7481 {
7482  const uint32_t COUNTERS_1_VAL : 16; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL */
7483  uint32_t : 16; /* *UNDEFINED* */
7484 };
7485 
7486 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL. */
7487 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_t;
7488 #endif /* __ASSEMBLY__ */
7489 
7490 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL register. */
7491 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_RESET 0x00000000
7492 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL register from the beginning of the component. */
7493 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_OFST 0x154
7494 
7495 /*
7496  * Register : Probe_emacs_main_Probe_Counters_2_PortSel
7497  *
7498  *
7499  * Register Layout
7500  *
7501  * Bits | Access | Reset | Description
7502  * :-------|:-------|:--------|:-----------------------------------------------------------
7503  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL
7504  * [31:1] | ??? | Unknown | *UNDEFINED*
7505  *
7506  */
7507 /*
7508  * Field : COUNTERS_2_PORTSEL
7509  *
7510  * Register PortSel indicates which NTTP link is associated with the counter. The
7511  * register can be changed at any time, with the change effective immediately. The
7512  * LUT and FILTx sources do not depend on this NTTP port selection.
7513  *
7514  * Field Access Macros:
7515  *
7516  */
7517 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field. */
7518 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_LSB 0
7519 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field. */
7520 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_MSB 0
7521 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field. */
7522 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_WIDTH 1
7523 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field value. */
7524 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_SET_MSK 0x00000001
7525 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field value. */
7526 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_CLR_MSK 0xfffffffe
7527 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field. */
7528 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_RESET 0x0
7529 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL field value from a register. */
7530 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
7531 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL register field value suitable for setting the register. */
7532 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
7533 
7534 #ifndef __ASSEMBLY__
7535 /*
7536  * WARNING: The C register and register group struct declarations are provided for
7537  * convenience and illustrative purposes. They should, however, be used with
7538  * caution as the C language standard provides no guarantees about the alignment or
7539  * atomicity of device memory accesses. The recommended practice for writing
7540  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7541  * alt_write_word() functions.
7542  *
7543  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL.
7544  */
7545 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_s
7546 {
7547  uint32_t COUNTERS_2_PORTSEL : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL */
7548  uint32_t : 31; /* *UNDEFINED* */
7549 };
7550 
7551 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL. */
7552 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_t;
7553 #endif /* __ASSEMBLY__ */
7554 
7555 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL register. */
7556 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_RESET 0x00000000
7557 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL register from the beginning of the component. */
7558 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_OFST 0x15c
7559 
7560 /*
7561  * Register : Probe_emacs_main_Probe_Counters_2_Src
7562  *
7563  * Register CntSrc indicates the event source used to increment the counter.
7564  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
7565  * Filter) are equivalent to OFF.
7566  *
7567  * Register Layout
7568  *
7569  * Bits | Access | Reset | Description
7570  * :-------|:-------|:--------|:------------------------------------------------
7571  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT
7572  * [5] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT
7573  * [31:6] | ??? | Unknown | *UNDEFINED*
7574  *
7575  */
7576 /*
7577  * Field : INTEVENT
7578  *
7579  * Internal packet event
7580  *
7581  * Field Access Macros:
7582  *
7583  */
7584 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT register field. */
7585 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_LSB 0
7586 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT register field. */
7587 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_MSB 4
7588 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT register field. */
7589 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_WIDTH 5
7590 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT register field value. */
7591 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_SET_MSK 0x0000001f
7592 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT register field value. */
7593 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_CLR_MSK 0xffffffe0
7594 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT register field. */
7595 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_RESET 0x0
7596 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT field value from a register. */
7597 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
7598 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT register field value suitable for setting the register. */
7599 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
7600 
7601 /*
7602  * Field : EXTEVENT
7603  *
7604  * When set to 1 counts the cycles where ExtEvent[IntEvent] = 1. It exists when
7605  * nExtEvent > 0.
7606  *
7607  * Field Access Macros:
7608  *
7609  */
7610 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT register field. */
7611 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_LSB 5
7612 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT register field. */
7613 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_MSB 5
7614 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT register field. */
7615 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_WIDTH 1
7616 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT register field value. */
7617 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_SET_MSK 0x00000020
7618 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT register field value. */
7619 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_CLR_MSK 0xffffffdf
7620 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT register field. */
7621 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_RESET 0x0
7622 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT field value from a register. */
7623 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_GET(value) (((value) & 0x00000020) >> 5)
7624 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT register field value suitable for setting the register. */
7625 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_SET(value) (((value) << 5) & 0x00000020)
7626 
7627 #ifndef __ASSEMBLY__
7628 /*
7629  * WARNING: The C register and register group struct declarations are provided for
7630  * convenience and illustrative purposes. They should, however, be used with
7631  * caution as the C language standard provides no guarantees about the alignment or
7632  * atomicity of device memory accesses. The recommended practice for writing
7633  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7634  * alt_write_word() functions.
7635  *
7636  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC.
7637  */
7638 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_s
7639 {
7640  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT */
7641  uint32_t EXTEVENT : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT */
7642  uint32_t : 26; /* *UNDEFINED* */
7643 };
7644 
7645 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC. */
7646 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_t;
7647 #endif /* __ASSEMBLY__ */
7648 
7649 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC register. */
7650 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_RESET 0x00000000
7651 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC register from the beginning of the component. */
7652 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_OFST 0x160
7653 
7654 /*
7655  * Register : Probe_emacs_main_Probe_Counters_2_AlarmMode
7656  *
7657  *
7658  * Register Layout
7659  *
7660  * Bits | Access | Reset | Description
7661  * :-------|:-------|:--------|:-------------------------------------------------------------
7662  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD
7663  * [31:2] | ??? | Unknown | *UNDEFINED*
7664  *
7665  */
7666 /*
7667  * Field : COUNTERS_2_ALARMMODE
7668  *
7669  * Register AlarmMode is a 2-bit register that is present when parameter
7670  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
7671  * behavior of the counter.
7672  *
7673  * Field Access Macros:
7674  *
7675  */
7676 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field. */
7677 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_LSB 0
7678 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field. */
7679 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_MSB 1
7680 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field. */
7681 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_WIDTH 2
7682 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field value. */
7683 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_SET_MSK 0x00000003
7684 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field value. */
7685 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_CLR_MSK 0xfffffffc
7686 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field. */
7687 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_RESET 0x0
7688 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD field value from a register. */
7689 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
7690 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field value suitable for setting the register. */
7691 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
7692 
7693 #ifndef __ASSEMBLY__
7694 /*
7695  * WARNING: The C register and register group struct declarations are provided for
7696  * convenience and illustrative purposes. They should, however, be used with
7697  * caution as the C language standard provides no guarantees about the alignment or
7698  * atomicity of device memory accesses. The recommended practice for writing
7699  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7700  * alt_write_word() functions.
7701  *
7702  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD.
7703  */
7704 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_s
7705 {
7706  uint32_t COUNTERS_2_ALARMMODE : 2; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD */
7707  uint32_t : 30; /* *UNDEFINED* */
7708 };
7709 
7710 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD. */
7711 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_t;
7712 #endif /* __ASSEMBLY__ */
7713 
7714 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD register. */
7715 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_RESET 0x00000000
7716 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD register from the beginning of the component. */
7717 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_OFST 0x164
7718 
7719 /*
7720  * Register : Probe_emacs_main_Probe_Counters_2_Val
7721  *
7722  *
7723  * Register Layout
7724  *
7725  * Bits | Access | Reset | Description
7726  * :--------|:-------|:--------|:---------------------------------------------------
7727  * [15:0] | R | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL
7728  * [31:16] | ??? | Unknown | *UNDEFINED*
7729  *
7730  */
7731 /*
7732  * Field : COUNTERS_2_VAL
7733  *
7734  * Register Val is a read-only register that is always present. The register
7735  * containsthe statistics counter value either pending StatAlarm output, or when
7736  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
7737  *
7738  * Field Access Macros:
7739  *
7740  */
7741 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field. */
7742 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_LSB 0
7743 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field. */
7744 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_MSB 15
7745 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field. */
7746 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_WIDTH 16
7747 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field value. */
7748 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_SET_MSK 0x0000ffff
7749 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field value. */
7750 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_CLR_MSK 0xffff0000
7751 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field. */
7752 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_RESET 0x0
7753 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL field value from a register. */
7754 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
7755 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field value suitable for setting the register. */
7756 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_SET(value) (((value) << 0) & 0x0000ffff)
7757 
7758 #ifndef __ASSEMBLY__
7759 /*
7760  * WARNING: The C register and register group struct declarations are provided for
7761  * convenience and illustrative purposes. They should, however, be used with
7762  * caution as the C language standard provides no guarantees about the alignment or
7763  * atomicity of device memory accesses. The recommended practice for writing
7764  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7765  * alt_write_word() functions.
7766  *
7767  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL.
7768  */
7769 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_s
7770 {
7771  const uint32_t COUNTERS_2_VAL : 16; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL */
7772  uint32_t : 16; /* *UNDEFINED* */
7773 };
7774 
7775 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL. */
7776 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_t;
7777 #endif /* __ASSEMBLY__ */
7778 
7779 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL register. */
7780 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_RESET 0x00000000
7781 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL register from the beginning of the component. */
7782 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_OFST 0x168
7783 
7784 /*
7785  * Register : Probe_emacs_main_Probe_Counters_3_PortSel
7786  *
7787  *
7788  * Register Layout
7789  *
7790  * Bits | Access | Reset | Description
7791  * :-------|:-------|:--------|:-----------------------------------------------------------
7792  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL
7793  * [31:1] | ??? | Unknown | *UNDEFINED*
7794  *
7795  */
7796 /*
7797  * Field : COUNTERS_3_PORTSEL
7798  *
7799  * Register PortSel indicates which NTTP link is associated with the counter. The
7800  * register can be changed at any time, with the change effective immediately. The
7801  * LUT and FILTx sources do not depend on this NTTP port selection.
7802  *
7803  * Field Access Macros:
7804  *
7805  */
7806 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field. */
7807 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_LSB 0
7808 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field. */
7809 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_MSB 0
7810 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field. */
7811 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_WIDTH 1
7812 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field value. */
7813 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_SET_MSK 0x00000001
7814 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field value. */
7815 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_CLR_MSK 0xfffffffe
7816 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field. */
7817 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_RESET 0x0
7818 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL field value from a register. */
7819 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
7820 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL register field value suitable for setting the register. */
7821 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
7822 
7823 #ifndef __ASSEMBLY__
7824 /*
7825  * WARNING: The C register and register group struct declarations are provided for
7826  * convenience and illustrative purposes. They should, however, be used with
7827  * caution as the C language standard provides no guarantees about the alignment or
7828  * atomicity of device memory accesses. The recommended practice for writing
7829  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7830  * alt_write_word() functions.
7831  *
7832  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL.
7833  */
7834 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_s
7835 {
7836  uint32_t COUNTERS_3_PORTSEL : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL */
7837  uint32_t : 31; /* *UNDEFINED* */
7838 };
7839 
7840 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL. */
7841 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_t;
7842 #endif /* __ASSEMBLY__ */
7843 
7844 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL register. */
7845 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_RESET 0x00000000
7846 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL register from the beginning of the component. */
7847 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_OFST 0x170
7848 
7849 /*
7850  * Register : Probe_emacs_main_Probe_Counters_3_Src
7851  *
7852  * Register CntSrc indicates the event source used to increment the counter.
7853  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
7854  * Filter) are equivalent to OFF.
7855  *
7856  * Register Layout
7857  *
7858  * Bits | Access | Reset | Description
7859  * :-------|:-------|:--------|:------------------------------------------------
7860  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT
7861  * [5] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT
7862  * [31:6] | ??? | Unknown | *UNDEFINED*
7863  *
7864  */
7865 /*
7866  * Field : INTEVENT
7867  *
7868  * Internal packet event
7869  *
7870  * Field Access Macros:
7871  *
7872  */
7873 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT register field. */
7874 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_LSB 0
7875 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT register field. */
7876 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_MSB 4
7877 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT register field. */
7878 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_WIDTH 5
7879 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT register field value. */
7880 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_SET_MSK 0x0000001f
7881 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT register field value. */
7882 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_CLR_MSK 0xffffffe0
7883 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT register field. */
7884 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_RESET 0x0
7885 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT field value from a register. */
7886 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
7887 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT register field value suitable for setting the register. */
7888 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
7889 
7890 /*
7891  * Field : EXTEVENT
7892  *
7893  * When set to 1 counts the cycles where ExtEvent[IntEvent] = 1. It exists when
7894  * nExtEvent > 0.
7895  *
7896  * Field Access Macros:
7897  *
7898  */
7899 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT register field. */
7900 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_LSB 5
7901 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT register field. */
7902 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_MSB 5
7903 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT register field. */
7904 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_WIDTH 1
7905 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT register field value. */
7906 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_SET_MSK 0x00000020
7907 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT register field value. */
7908 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_CLR_MSK 0xffffffdf
7909 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT register field. */
7910 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_RESET 0x0
7911 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT field value from a register. */
7912 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_GET(value) (((value) & 0x00000020) >> 5)
7913 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT register field value suitable for setting the register. */
7914 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_SET(value) (((value) << 5) & 0x00000020)
7915 
7916 #ifndef __ASSEMBLY__
7917 /*
7918  * WARNING: The C register and register group struct declarations are provided for
7919  * convenience and illustrative purposes. They should, however, be used with
7920  * caution as the C language standard provides no guarantees about the alignment or
7921  * atomicity of device memory accesses. The recommended practice for writing
7922  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7923  * alt_write_word() functions.
7924  *
7925  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC.
7926  */
7927 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_s
7928 {
7929  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT */
7930  uint32_t EXTEVENT : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT */
7931  uint32_t : 26; /* *UNDEFINED* */
7932 };
7933 
7934 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC. */
7935 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_t;
7936 #endif /* __ASSEMBLY__ */
7937 
7938 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC register. */
7939 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_RESET 0x00000000
7940 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC register from the beginning of the component. */
7941 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_OFST 0x174
7942 
7943 /*
7944  * Register : Probe_emacs_main_Probe_Counters_3_AlarmMode
7945  *
7946  *
7947  * Register Layout
7948  *
7949  * Bits | Access | Reset | Description
7950  * :-------|:-------|:--------|:-------------------------------------------------------------
7951  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD
7952  * [31:2] | ??? | Unknown | *UNDEFINED*
7953  *
7954  */
7955 /*
7956  * Field : COUNTERS_3_ALARMMODE
7957  *
7958  * Register AlarmMode is a 2-bit register that is present when parameter
7959  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
7960  * behavior of the counter.
7961  *
7962  * Field Access Macros:
7963  *
7964  */
7965 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field. */
7966 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_LSB 0
7967 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field. */
7968 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_MSB 1
7969 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field. */
7970 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_WIDTH 2
7971 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field value. */
7972 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_SET_MSK 0x00000003
7973 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field value. */
7974 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_CLR_MSK 0xfffffffc
7975 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field. */
7976 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_RESET 0x0
7977 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD field value from a register. */
7978 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
7979 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field value suitable for setting the register. */
7980 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
7981 
7982 #ifndef __ASSEMBLY__
7983 /*
7984  * WARNING: The C register and register group struct declarations are provided for
7985  * convenience and illustrative purposes. They should, however, be used with
7986  * caution as the C language standard provides no guarantees about the alignment or
7987  * atomicity of device memory accesses. The recommended practice for writing
7988  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7989  * alt_write_word() functions.
7990  *
7991  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD.
7992  */
7993 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_s
7994 {
7995  uint32_t COUNTERS_3_ALARMMODE : 2; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD */
7996  uint32_t : 30; /* *UNDEFINED* */
7997 };
7998 
7999 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD. */
8000 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_t;
8001 #endif /* __ASSEMBLY__ */
8002 
8003 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD register. */
8004 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_RESET 0x00000000
8005 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD register from the beginning of the component. */
8006 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_OFST 0x178
8007 
8008 /*
8009  * Register : Probe_emacs_main_Probe_Counters_3_Val
8010  *
8011  *
8012  * Register Layout
8013  *
8014  * Bits | Access | Reset | Description
8015  * :--------|:-------|:--------|:---------------------------------------------------
8016  * [15:0] | R | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL
8017  * [31:16] | ??? | Unknown | *UNDEFINED*
8018  *
8019  */
8020 /*
8021  * Field : COUNTERS_3_VAL
8022  *
8023  * Register Val is a read-only register that is always present. The register
8024  * containsthe statistics counter value either pending StatAlarm output, or when
8025  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
8026  *
8027  * Field Access Macros:
8028  *
8029  */
8030 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field. */
8031 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_LSB 0
8032 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field. */
8033 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_MSB 15
8034 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field. */
8035 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_WIDTH 16
8036 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field value. */
8037 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_SET_MSK 0x0000ffff
8038 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field value. */
8039 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_CLR_MSK 0xffff0000
8040 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field. */
8041 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_RESET 0x0
8042 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL field value from a register. */
8043 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
8044 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field value suitable for setting the register. */
8045 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_SET(value) (((value) << 0) & 0x0000ffff)
8046 
8047 #ifndef __ASSEMBLY__
8048 /*
8049  * WARNING: The C register and register group struct declarations are provided for
8050  * convenience and illustrative purposes. They should, however, be used with
8051  * caution as the C language standard provides no guarantees about the alignment or
8052  * atomicity of device memory accesses. The recommended practice for writing
8053  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8054  * alt_write_word() functions.
8055  *
8056  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL.
8057  */
8058 struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_s
8059 {
8060  const uint32_t COUNTERS_3_VAL : 16; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL */
8061  uint32_t : 16; /* *UNDEFINED* */
8062 };
8063 
8064 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL. */
8065 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_s ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_t;
8066 #endif /* __ASSEMBLY__ */
8067 
8068 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL register. */
8069 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_RESET 0x00000000
8070 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL register from the beginning of the component. */
8071 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_OFST 0x17c
8072 
8073 #ifndef __ASSEMBLY__
8074 /*
8075  * WARNING: The C register and register group struct declarations are provided for
8076  * convenience and illustrative purposes. They should, however, be used with
8077  * caution as the C language standard provides no guarantees about the alignment or
8078  * atomicity of device memory accesses. The recommended practice for writing
8079  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8080  * alt_write_word() functions.
8081  *
8082  * The struct declaration for register group ALT_NOC_MPU_PRB_EMACS_MAIN_PRB.
8083  */
8084 struct ALT_NOC_MPU_PRB_EMACS_MAIN_PRB_s
8085 {
8086  ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_t Probe_emacs_main_Probe_Id_CoreId; /* ALT_NOC_MPU_PRB_EMACS_MAIN_COREID */
8087  ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_t Probe_emacs_main_Probe_Id_RevisionId; /* ALT_NOC_MPU_PRB_EMACS_MAIN_REVID */
8088  ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_t Probe_emacs_main_Probe_MainCtl; /* ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL */
8089  ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_t Probe_emacs_main_Probe_CfgCtl; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL */
8090  ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_t Probe_emacs_main_Probe_TracePortSel; /* ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL */
8091  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_t Probe_emacs_main_Probe_FilterLut; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT */
8092  ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_t Probe_emacs_main_Probe_TraceAlarmEn; /* ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN */
8093  ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_t Probe_emacs_main_Probe_TraceAlarmStatus; /* ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT */
8094  ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_t Probe_emacs_main_Probe_TraceAlarmClr; /* ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR */
8095  ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_t Probe_emacs_main_Probe_StatPeriod; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD */
8096  ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_t Probe_emacs_main_Probe_StatGo; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO */
8097  ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_t Probe_emacs_main_Probe_StatAlarmMin; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN */
8098  ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_t Probe_emacs_main_Probe_StatAlarmMax; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX */
8099  ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_t Probe_emacs_main_Probe_StatAlarmStatus; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT */
8100  ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_t Probe_emacs_main_Probe_StatAlarmClr; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR */
8101  ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_t Probe_emacs_main_Probe_StatAlarmEn; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN */
8102  volatile uint32_t _pad_0x40_0x43; /* *UNDEFINED* */
8103  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_t Probe_emacs_main_Probe_Filters_0_RouteIdBase; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE */
8104  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_t Probe_emacs_main_Probe_Filters_0_RouteIdMask; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK */
8105  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_t Probe_emacs_main_Probe_Filters_0_AddrBase_Low; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW */
8106  volatile uint32_t _pad_0x50_0x53; /* *UNDEFINED* */
8107  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_t Probe_emacs_main_Probe_Filters_0_WindowSize; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE */
8108  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_t Probe_emacs_main_Probe_Filters_0_SecurityBase; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE */
8109  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_t Probe_emacs_main_Probe_Filters_0_SecurityMask; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK */
8110  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_t Probe_emacs_main_Probe_Filters_0_Opcode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE */
8111  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_t Probe_emacs_main_Probe_Filters_0_Status; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT */
8112  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_t Probe_emacs_main_Probe_Filters_0_Length; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN */
8113  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_t Probe_emacs_main_Probe_Filters_0_Urgency; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY */
8114  volatile uint32_t _pad_0x70_0x7f[4]; /* *UNDEFINED* */
8115  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_t Probe_emacs_main_Probe_Filters_1_RouteIdBase; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE */
8116  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_t Probe_emacs_main_Probe_Filters_1_RouteIdMask; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK */
8117  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_t Probe_emacs_main_Probe_Filters_1_AddrBase_Low; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW */
8118  volatile uint32_t _pad_0x8c_0x8f; /* *UNDEFINED* */
8119  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_t Probe_emacs_main_Probe_Filters_1_WindowSize; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE */
8120  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_t Probe_emacs_main_Probe_Filters_1_SecurityBase; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE */
8121  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_t Probe_emacs_main_Probe_Filters_1_SecurityMask; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK */
8122  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_t Probe_emacs_main_Probe_Filters_1_Opcode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE */
8123  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_t Probe_emacs_main_Probe_Filters_1_Status; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT */
8124  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_t Probe_emacs_main_Probe_Filters_1_Length; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN */
8125  ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_t Probe_emacs_main_Probe_Filters_1_Urgency; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY */
8126  volatile uint32_t _pad_0xac_0x133[34]; /* *UNDEFINED* */
8127  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_t Probe_emacs_main_Probe_Counters_0_PortSel; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL */
8128  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_t Probe_emacs_main_Probe_Counters_0_Src; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC */
8129  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_t Probe_emacs_main_Probe_Counters_0_AlarmMode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD */
8130  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_t Probe_emacs_main_Probe_Counters_0_Val; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL */
8131  volatile uint32_t _pad_0x144_0x147; /* *UNDEFINED* */
8132  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_t Probe_emacs_main_Probe_Counters_1_PortSel; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL */
8133  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_t Probe_emacs_main_Probe_Counters_1_Src; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC */
8134  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_t Probe_emacs_main_Probe_Counters_1_AlarmMode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD */
8135  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_t Probe_emacs_main_Probe_Counters_1_Val; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL */
8136  volatile uint32_t _pad_0x158_0x15b; /* *UNDEFINED* */
8137  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_t Probe_emacs_main_Probe_Counters_2_PortSel; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL */
8138  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_t Probe_emacs_main_Probe_Counters_2_Src; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC */
8139  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_t Probe_emacs_main_Probe_Counters_2_AlarmMode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD */
8140  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_t Probe_emacs_main_Probe_Counters_2_Val; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL */
8141  volatile uint32_t _pad_0x16c_0x16f; /* *UNDEFINED* */
8142  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_t Probe_emacs_main_Probe_Counters_3_PortSel; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL */
8143  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_t Probe_emacs_main_Probe_Counters_3_Src; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC */
8144  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_t Probe_emacs_main_Probe_Counters_3_AlarmMode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD */
8145  ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_t Probe_emacs_main_Probe_Counters_3_Val; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL */
8146  volatile uint32_t _pad_0x180_0x400[160]; /* *UNDEFINED* */
8147 };
8148 
8149 /* The typedef declaration for register group ALT_NOC_MPU_PRB_EMACS_MAIN_PRB. */
8150 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_PRB_s ALT_NOC_MPU_PRB_EMACS_MAIN_PRB_t;
8151 /* The struct declaration for the raw register contents of register group ALT_NOC_MPU_PRB_EMACS_MAIN_PRB. */
8152 struct ALT_NOC_MPU_PRB_EMACS_MAIN_PRB_raw_s
8153 {
8154  volatile uint32_t Probe_emacs_main_Probe_Id_CoreId; /* ALT_NOC_MPU_PRB_EMACS_MAIN_COREID */
8155  volatile uint32_t Probe_emacs_main_Probe_Id_RevisionId; /* ALT_NOC_MPU_PRB_EMACS_MAIN_REVID */
8156  volatile uint32_t Probe_emacs_main_Probe_MainCtl; /* ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL */
8157  volatile uint32_t Probe_emacs_main_Probe_CfgCtl; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL */
8158  volatile uint32_t Probe_emacs_main_Probe_TracePortSel; /* ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL */
8159  volatile uint32_t Probe_emacs_main_Probe_FilterLut; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT */
8160  volatile uint32_t Probe_emacs_main_Probe_TraceAlarmEn; /* ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN */
8161  volatile uint32_t Probe_emacs_main_Probe_TraceAlarmStatus; /* ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT */
8162  volatile uint32_t Probe_emacs_main_Probe_TraceAlarmClr; /* ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR */
8163  volatile uint32_t Probe_emacs_main_Probe_StatPeriod; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD */
8164  volatile uint32_t Probe_emacs_main_Probe_StatGo; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO */
8165  volatile uint32_t Probe_emacs_main_Probe_StatAlarmMin; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN */
8166  volatile uint32_t Probe_emacs_main_Probe_StatAlarmMax; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX */
8167  volatile uint32_t Probe_emacs_main_Probe_StatAlarmStatus; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT */
8168  volatile uint32_t Probe_emacs_main_Probe_StatAlarmClr; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR */
8169  volatile uint32_t Probe_emacs_main_Probe_StatAlarmEn; /* ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN */
8170  uint32_t _pad_0x40_0x43; /* *UNDEFINED* */
8171  volatile uint32_t Probe_emacs_main_Probe_Filters_0_RouteIdBase; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE */
8172  volatile uint32_t Probe_emacs_main_Probe_Filters_0_RouteIdMask; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK */
8173  volatile uint32_t Probe_emacs_main_Probe_Filters_0_AddrBase_Low; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW */
8174  uint32_t _pad_0x50_0x53; /* *UNDEFINED* */
8175  volatile uint32_t Probe_emacs_main_Probe_Filters_0_WindowSize; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE */
8176  volatile uint32_t Probe_emacs_main_Probe_Filters_0_SecurityBase; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE */
8177  volatile uint32_t Probe_emacs_main_Probe_Filters_0_SecurityMask; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK */
8178  volatile uint32_t Probe_emacs_main_Probe_Filters_0_Opcode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE */
8179  volatile uint32_t Probe_emacs_main_Probe_Filters_0_Status; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT */
8180  volatile uint32_t Probe_emacs_main_Probe_Filters_0_Length; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN */
8181  volatile uint32_t Probe_emacs_main_Probe_Filters_0_Urgency; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY */
8182  uint32_t _pad_0x70_0x7f[4]; /* *UNDEFINED* */
8183  volatile uint32_t Probe_emacs_main_Probe_Filters_1_RouteIdBase; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE */
8184  volatile uint32_t Probe_emacs_main_Probe_Filters_1_RouteIdMask; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK */
8185  volatile uint32_t Probe_emacs_main_Probe_Filters_1_AddrBase_Low; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW */
8186  uint32_t _pad_0x8c_0x8f; /* *UNDEFINED* */
8187  volatile uint32_t Probe_emacs_main_Probe_Filters_1_WindowSize; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE */
8188  volatile uint32_t Probe_emacs_main_Probe_Filters_1_SecurityBase; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE */
8189  volatile uint32_t Probe_emacs_main_Probe_Filters_1_SecurityMask; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK */
8190  volatile uint32_t Probe_emacs_main_Probe_Filters_1_Opcode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE */
8191  volatile uint32_t Probe_emacs_main_Probe_Filters_1_Status; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT */
8192  volatile uint32_t Probe_emacs_main_Probe_Filters_1_Length; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN */
8193  volatile uint32_t Probe_emacs_main_Probe_Filters_1_Urgency; /* ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY */
8194  uint32_t _pad_0xac_0x133[34]; /* *UNDEFINED* */
8195  volatile uint32_t Probe_emacs_main_Probe_Counters_0_PortSel; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL */
8196  volatile uint32_t Probe_emacs_main_Probe_Counters_0_Src; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC */
8197  volatile uint32_t Probe_emacs_main_Probe_Counters_0_AlarmMode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD */
8198  volatile uint32_t Probe_emacs_main_Probe_Counters_0_Val; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL */
8199  uint32_t _pad_0x144_0x147; /* *UNDEFINED* */
8200  volatile uint32_t Probe_emacs_main_Probe_Counters_1_PortSel; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL */
8201  volatile uint32_t Probe_emacs_main_Probe_Counters_1_Src; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC */
8202  volatile uint32_t Probe_emacs_main_Probe_Counters_1_AlarmMode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD */
8203  volatile uint32_t Probe_emacs_main_Probe_Counters_1_Val; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL */
8204  uint32_t _pad_0x158_0x15b; /* *UNDEFINED* */
8205  volatile uint32_t Probe_emacs_main_Probe_Counters_2_PortSel; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL */
8206  volatile uint32_t Probe_emacs_main_Probe_Counters_2_Src; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC */
8207  volatile uint32_t Probe_emacs_main_Probe_Counters_2_AlarmMode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD */
8208  volatile uint32_t Probe_emacs_main_Probe_Counters_2_Val; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL */
8209  uint32_t _pad_0x16c_0x16f; /* *UNDEFINED* */
8210  volatile uint32_t Probe_emacs_main_Probe_Counters_3_PortSel; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL */
8211  volatile uint32_t Probe_emacs_main_Probe_Counters_3_Src; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC */
8212  volatile uint32_t Probe_emacs_main_Probe_Counters_3_AlarmMode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD */
8213  volatile uint32_t Probe_emacs_main_Probe_Counters_3_Val; /* ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL */
8214  uint32_t _pad_0x180_0x400[160]; /* *UNDEFINED* */
8215 };
8216 
8217 /* The typedef declaration for the raw register contents of register group ALT_NOC_MPU_PRB_EMACS_MAIN_PRB. */
8218 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_PRB_raw_s ALT_NOC_MPU_PRB_EMACS_MAIN_PRB_raw_t;
8219 #endif /* __ASSEMBLY__ */
8220 
8221 
8222 /*
8223  * Component : ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER
8224  *
8225  */
8226 /*
8227  * Register : Probe_emacs_main_TransactionStatProfiler_Id_CoreId
8228  *
8229  * Register Layout
8230  *
8231  * Bits | Access | Reset | Description
8232  * :-------|:-------|:---------|:------------------------------------------------------------
8233  * [7:0] | R | 0xa | ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID
8234  * [31:8] | R | 0xa6b796 | ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM
8235  *
8236  */
8237 /*
8238  * Field : CORETYPEID
8239  *
8240  * Field identifying the type of IP.
8241  *
8242  * Field Access Macros:
8243  *
8244  */
8245 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID register field. */
8246 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_LSB 0
8247 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID register field. */
8248 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_MSB 7
8249 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID register field. */
8250 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_WIDTH 8
8251 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID register field value. */
8252 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_SET_MSK 0x000000ff
8253 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID register field value. */
8254 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_CLR_MSK 0xffffff00
8255 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID register field. */
8256 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_RESET 0xa
8257 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID field value from a register. */
8258 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
8259 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID register field value suitable for setting the register. */
8260 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
8261 
8262 /*
8263  * Field : CORECHECKSUM
8264  *
8265  * Field containing a checksum of the parameters of the IP.
8266  *
8267  * Field Access Macros:
8268  *
8269  */
8270 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM register field. */
8271 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_LSB 8
8272 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM register field. */
8273 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_MSB 31
8274 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM register field. */
8275 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_WIDTH 24
8276 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM register field value. */
8277 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_SET_MSK 0xffffff00
8278 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM register field value. */
8279 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_CLR_MSK 0x000000ff
8280 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM register field. */
8281 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_RESET 0xa6b796
8282 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM field value from a register. */
8283 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
8284 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM register field value suitable for setting the register. */
8285 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
8286 
8287 #ifndef __ASSEMBLY__
8288 /*
8289  * WARNING: The C register and register group struct declarations are provided for
8290  * convenience and illustrative purposes. They should, however, be used with
8291  * caution as the C language standard provides no guarantees about the alignment or
8292  * atomicity of device memory accesses. The recommended practice for writing
8293  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8294  * alt_write_word() functions.
8295  *
8296  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID.
8297  */
8298 struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_s
8299 {
8300  const uint32_t CORETYPEID : 8; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID */
8301  const uint32_t CORECHECKSUM : 24; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM */
8302 };
8303 
8304 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID. */
8305 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_s ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_t;
8306 #endif /* __ASSEMBLY__ */
8307 
8308 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID register. */
8309 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_RESET 0xa6b7960a
8310 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID register from the beginning of the component. */
8311 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_OFST 0x0
8312 
8313 /*
8314  * Register : Probe_emacs_main_TransactionStatProfiler_Id_RevisionId
8315  *
8316  * Register Layout
8317  *
8318  * Bits | Access | Reset | Description
8319  * :-------|:-------|:--------|:------------------------------------------------------------
8320  * [7:0] | R | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID
8321  * [31:8] | R | 0x129ff | ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID
8322  *
8323  */
8324 /*
8325  * Field : USERID
8326  *
8327  * Field containing a user defined value, not used anywhere inside the IP itself.
8328  *
8329  * Field Access Macros:
8330  *
8331  */
8332 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID register field. */
8333 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_LSB 0
8334 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID register field. */
8335 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_MSB 7
8336 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID register field. */
8337 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_WIDTH 8
8338 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID register field value. */
8339 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_SET_MSK 0x000000ff
8340 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID register field value. */
8341 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_CLR_MSK 0xffffff00
8342 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID register field. */
8343 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_RESET 0x0
8344 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID field value from a register. */
8345 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
8346 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID register field value suitable for setting the register. */
8347 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
8348 
8349 /*
8350  * Field : FLEXNOCID
8351  *
8352  * Field containing the build revision of the software used to generate the IP HDL
8353  * code.
8354  *
8355  * Field Access Macros:
8356  *
8357  */
8358 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID register field. */
8359 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_LSB 8
8360 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID register field. */
8361 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_MSB 31
8362 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID register field. */
8363 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_WIDTH 24
8364 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID register field value. */
8365 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_SET_MSK 0xffffff00
8366 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID register field value. */
8367 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_CLR_MSK 0x000000ff
8368 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID register field. */
8369 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_RESET 0x129ff
8370 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID field value from a register. */
8371 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
8372 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID register field value suitable for setting the register. */
8373 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
8374 
8375 #ifndef __ASSEMBLY__
8376 /*
8377  * WARNING: The C register and register group struct declarations are provided for
8378  * convenience and illustrative purposes. They should, however, be used with
8379  * caution as the C language standard provides no guarantees about the alignment or
8380  * atomicity of device memory accesses. The recommended practice for writing
8381  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8382  * alt_write_word() functions.
8383  *
8384  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID.
8385  */
8386 struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_s
8387 {
8388  const uint32_t USERID : 8; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID */
8389  const uint32_t FLEXNOCID : 24; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID */
8390 };
8391 
8392 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID. */
8393 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_s ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_t;
8394 #endif /* __ASSEMBLY__ */
8395 
8396 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID register. */
8397 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_RESET 0x0129ff00
8398 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID register from the beginning of the component. */
8399 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_OFST 0x4
8400 
8401 /*
8402  * Register : Probe_emacs_main_TransactionStatProfiler_En
8403  *
8404  *
8405  * Register Layout
8406  *
8407  * Bits | Access | Reset | Description
8408  * :-------|:-------|:--------|:--------------------------------------------------
8409  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN
8410  * [31:1] | ??? | Unknown | *UNDEFINED*
8411  *
8412  */
8413 /*
8414  * Field : EN
8415  *
8416  * Register En is a 1-bit register that enables the transaction probe counter unit.
8417  *
8418  * Field Access Macros:
8419  *
8420  */
8421 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN register field. */
8422 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_LSB 0
8423 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN register field. */
8424 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_MSB 0
8425 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN register field. */
8426 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_WIDTH 1
8427 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN register field value. */
8428 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_SET_MSK 0x00000001
8429 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN register field value. */
8430 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_CLR_MSK 0xfffffffe
8431 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN register field. */
8432 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_RESET 0x0
8433 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN field value from a register. */
8434 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_GET(value) (((value) & 0x00000001) >> 0)
8435 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN register field value suitable for setting the register. */
8436 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_SET(value) (((value) << 0) & 0x00000001)
8437 
8438 #ifndef __ASSEMBLY__
8439 /*
8440  * WARNING: The C register and register group struct declarations are provided for
8441  * convenience and illustrative purposes. They should, however, be used with
8442  * caution as the C language standard provides no guarantees about the alignment or
8443  * atomicity of device memory accesses. The recommended practice for writing
8444  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8445  * alt_write_word() functions.
8446  *
8447  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN.
8448  */
8449 struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_s
8450 {
8451  uint32_t EN : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN */
8452  uint32_t : 31; /* *UNDEFINED* */
8453 };
8454 
8455 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN. */
8456 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_s ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_t;
8457 #endif /* __ASSEMBLY__ */
8458 
8459 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN register. */
8460 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_RESET 0x00000000
8461 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN register from the beginning of the component. */
8462 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_OFST 0x8
8463 
8464 /*
8465  * Register : Probe_emacs_main_TransactionStatProfiler_Mode
8466  *
8467  *
8468  * Register Layout
8469  *
8470  * Bits | Access | Reset | Description
8471  * :-------|:-------|:--------|:----------------------------------------------------
8472  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD
8473  * [31:1] | ??? | Unknown | *UNDEFINED*
8474  *
8475  */
8476 /*
8477  * Field : MODE
8478  *
8479  * Register Mode sets the counting mode per observed port. Each bit per observation
8480  * port defines the incrementing mode. (Mode = 0 for Delay, Mode = 1 for Pending)
8481  *
8482  * Field Access Macros:
8483  *
8484  */
8485 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD register field. */
8486 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_LSB 0
8487 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD register field. */
8488 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_MSB 0
8489 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD register field. */
8490 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_WIDTH 1
8491 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD register field value. */
8492 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_SET_MSK 0x00000001
8493 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD register field value. */
8494 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_CLR_MSK 0xfffffffe
8495 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD register field. */
8496 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_RESET 0x0
8497 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD field value from a register. */
8498 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_GET(value) (((value) & 0x00000001) >> 0)
8499 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD register field value suitable for setting the register. */
8500 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_SET(value) (((value) << 0) & 0x00000001)
8501 
8502 #ifndef __ASSEMBLY__
8503 /*
8504  * WARNING: The C register and register group struct declarations are provided for
8505  * convenience and illustrative purposes. They should, however, be used with
8506  * caution as the C language standard provides no guarantees about the alignment or
8507  * atomicity of device memory accesses. The recommended practice for writing
8508  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8509  * alt_write_word() functions.
8510  *
8511  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD.
8512  */
8513 struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_s
8514 {
8515  uint32_t MODE : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD */
8516  uint32_t : 31; /* *UNDEFINED* */
8517 };
8518 
8519 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD. */
8520 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_s ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_t;
8521 #endif /* __ASSEMBLY__ */
8522 
8523 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD register. */
8524 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_RESET 0x00000000
8525 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD register from the beginning of the component. */
8526 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_OFST 0xc
8527 
8528 /*
8529  * Register : Probe_emacs_main_TransactionStatProfiler_Thresholds_0_0
8530  *
8531  *
8532  * Register Layout
8533  *
8534  * Bits | Access | Reset | Description
8535  * :-------|:-------|:--------|:--------------------------------------------------------------------------
8536  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0
8537  * [31:2] | ??? | Unknown | *UNDEFINED*
8538  *
8539  */
8540 /*
8541  * Field : THRESHOLDS_0_0
8542  *
8543  * Register Thresholds_i_j contains the threshold index "0" that allows computation
8544  * of threshold values.
8545  *
8546  * Field Access Macros:
8547  *
8548  */
8549 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0 register field. */
8550 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_LSB 0
8551 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0 register field. */
8552 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MSB 1
8553 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0 register field. */
8554 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_WIDTH 2
8555 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0 register field value. */
8556 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SET_MSK 0x00000003
8557 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0 register field value. */
8558 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_CLR_MSK 0xfffffffc
8559 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0 register field. */
8560 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_RESET 0x0
8561 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0 field value from a register. */
8562 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_GET(value) (((value) & 0x00000003) >> 0)
8563 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0 register field value suitable for setting the register. */
8564 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SET(value) (((value) << 0) & 0x00000003)
8565 
8566 #ifndef __ASSEMBLY__
8567 /*
8568  * WARNING: The C register and register group struct declarations are provided for
8569  * convenience and illustrative purposes. They should, however, be used with
8570  * caution as the C language standard provides no guarantees about the alignment or
8571  * atomicity of device memory accesses. The recommended practice for writing
8572  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8573  * alt_write_word() functions.
8574  *
8575  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0.
8576  */
8577 struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_s
8578 {
8579  uint32_t THRESHOLDS_0_0 : 2; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0 */
8580  uint32_t : 30; /* *UNDEFINED* */
8581 };
8582 
8583 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0. */
8584 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_s ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_t;
8585 #endif /* __ASSEMBLY__ */
8586 
8587 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0 register. */
8588 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_RESET 0x00000000
8589 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0 register from the beginning of the component. */
8590 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_OFST 0x2c
8591 
8592 /*
8593  * Register : Probe_emacs_main_TransactionStatProfiler_Thresholds_0_1
8594  *
8595  *
8596  * Register Layout
8597  *
8598  * Bits | Access | Reset | Description
8599  * :-------|:-------|:--------|:--------------------------------------------------------------------------
8600  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1
8601  * [31:2] | ??? | Unknown | *UNDEFINED*
8602  *
8603  */
8604 /*
8605  * Field : THRESHOLDS_0_1
8606  *
8607  * Register Thresholds_i_j contains the threshold index "1" that allows computation
8608  * of threshold values.
8609  *
8610  * Field Access Macros:
8611  *
8612  */
8613 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1 register field. */
8614 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_LSB 0
8615 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1 register field. */
8616 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MSB 1
8617 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1 register field. */
8618 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_WIDTH 2
8619 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1 register field value. */
8620 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SET_MSK 0x00000003
8621 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1 register field value. */
8622 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_CLR_MSK 0xfffffffc
8623 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1 register field. */
8624 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_RESET 0x0
8625 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1 field value from a register. */
8626 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_GET(value) (((value) & 0x00000003) >> 0)
8627 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1 register field value suitable for setting the register. */
8628 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SET(value) (((value) << 0) & 0x00000003)
8629 
8630 #ifndef __ASSEMBLY__
8631 /*
8632  * WARNING: The C register and register group struct declarations are provided for
8633  * convenience and illustrative purposes. They should, however, be used with
8634  * caution as the C language standard provides no guarantees about the alignment or
8635  * atomicity of device memory accesses. The recommended practice for writing
8636  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8637  * alt_write_word() functions.
8638  *
8639  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1.
8640  */
8641 struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_s
8642 {
8643  uint32_t THRESHOLDS_0_1 : 2; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1 */
8644  uint32_t : 30; /* *UNDEFINED* */
8645 };
8646 
8647 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1. */
8648 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_s ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_t;
8649 #endif /* __ASSEMBLY__ */
8650 
8651 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1 register. */
8652 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_RESET 0x00000000
8653 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1 register from the beginning of the component. */
8654 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_OFST 0x30
8655 
8656 /*
8657  * Register : Probe_emacs_main_TransactionStatProfiler_Thresholds_0_2
8658  *
8659  *
8660  * Register Layout
8661  *
8662  * Bits | Access | Reset | Description
8663  * :-------|:-------|:--------|:--------------------------------------------------------------------------
8664  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2
8665  * [31:2] | ??? | Unknown | *UNDEFINED*
8666  *
8667  */
8668 /*
8669  * Field : THRESHOLDS_0_2
8670  *
8671  * Register Thresholds_i_j contains the threshold index "2" that allows computation
8672  * of threshold values.
8673  *
8674  * Field Access Macros:
8675  *
8676  */
8677 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2 register field. */
8678 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_LSB 0
8679 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2 register field. */
8680 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MSB 1
8681 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2 register field. */
8682 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_WIDTH 2
8683 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2 register field value. */
8684 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SET_MSK 0x00000003
8685 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2 register field value. */
8686 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_CLR_MSK 0xfffffffc
8687 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2 register field. */
8688 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_RESET 0x0
8689 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2 field value from a register. */
8690 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_GET(value) (((value) & 0x00000003) >> 0)
8691 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2 register field value suitable for setting the register. */
8692 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SET(value) (((value) << 0) & 0x00000003)
8693 
8694 #ifndef __ASSEMBLY__
8695 /*
8696  * WARNING: The C register and register group struct declarations are provided for
8697  * convenience and illustrative purposes. They should, however, be used with
8698  * caution as the C language standard provides no guarantees about the alignment or
8699  * atomicity of device memory accesses. The recommended practice for writing
8700  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8701  * alt_write_word() functions.
8702  *
8703  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2.
8704  */
8705 struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_s
8706 {
8707  uint32_t THRESHOLDS_0_2 : 2; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2 */
8708  uint32_t : 30; /* *UNDEFINED* */
8709 };
8710 
8711 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2. */
8712 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_s ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_t;
8713 #endif /* __ASSEMBLY__ */
8714 
8715 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2 register. */
8716 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_RESET 0x00000000
8717 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2 register from the beginning of the component. */
8718 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_OFST 0x34
8719 
8720 /*
8721  * Register : Probe_emacs_main_TransactionStatProfiler_OverflowStatus
8722  *
8723  *
8724  * Register Layout
8725  *
8726  * Bits | Access | Reset | Description
8727  * :-------|:-------|:--------|:------------------------------------------------------------
8728  * [0] | R | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT
8729  * [31:1] | ??? | Unknown | *UNDEFINED*
8730  *
8731  */
8732 /*
8733  * Field : OVERFLOWSTATUS
8734  *
8735  * Bit n of register OverflowStatus is set to 1 if a start event occurs on observed
8736  * port n and eitherof the following conditions occurs: All tenure counters
8737  * allocated to the port are already in use. No tenure lines have been allocated to
8738  * the port. The number of bits in this register is equal to the value set for
8739  * parameter nObservable.
8740  *
8741  * Field Access Macros:
8742  *
8743  */
8744 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT register field. */
8745 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_LSB 0
8746 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT register field. */
8747 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_MSB 0
8748 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT register field. */
8749 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_WIDTH 1
8750 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT register field value. */
8751 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_SET_MSK 0x00000001
8752 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT register field value. */
8753 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_CLR_MSK 0xfffffffe
8754 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT register field. */
8755 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_RESET 0x0
8756 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT field value from a register. */
8757 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_GET(value) (((value) & 0x00000001) >> 0)
8758 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT register field value suitable for setting the register. */
8759 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_SET(value) (((value) << 0) & 0x00000001)
8760 
8761 #ifndef __ASSEMBLY__
8762 /*
8763  * WARNING: The C register and register group struct declarations are provided for
8764  * convenience and illustrative purposes. They should, however, be used with
8765  * caution as the C language standard provides no guarantees about the alignment or
8766  * atomicity of device memory accesses. The recommended practice for writing
8767  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8768  * alt_write_word() functions.
8769  *
8770  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT.
8771  */
8772 struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_s
8773 {
8774  const uint32_t OVERFLOWSTATUS : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT */
8775  uint32_t : 31; /* *UNDEFINED* */
8776 };
8777 
8778 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT. */
8779 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_s ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_t;
8780 #endif /* __ASSEMBLY__ */
8781 
8782 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT register. */
8783 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_RESET 0x00000000
8784 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT register from the beginning of the component. */
8785 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OFST 0x6c
8786 
8787 /*
8788  * Register : Probe_emacs_main_TransactionStatProfiler_OverflowReset
8789  *
8790  *
8791  * Register Layout
8792  *
8793  * Bits | Access | Reset | Description
8794  * :-------|:-------|:--------|:----------------------------------------------------------
8795  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST
8796  * [31:1] | ??? | Unknown | *UNDEFINED*
8797  *
8798  */
8799 /*
8800  * Field : OVERFLOWRESET
8801  *
8802  * Register OverflowReset is a pulse register that clears overflow status bits per
8803  * observed port on each write access. OverflowReset = nObservable. Writing 0x2
8804  * clears the overflow status of observed port 1.
8805  *
8806  * Field Access Macros:
8807  *
8808  */
8809 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST register field. */
8810 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_LSB 0
8811 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST register field. */
8812 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_MSB 0
8813 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST register field. */
8814 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_WIDTH 1
8815 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST register field value. */
8816 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_SET_MSK 0x00000001
8817 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST register field value. */
8818 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_CLR_MSK 0xfffffffe
8819 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST register field. */
8820 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_RESET 0x0
8821 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST field value from a register. */
8822 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_GET(value) (((value) & 0x00000001) >> 0)
8823 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST register field value suitable for setting the register. */
8824 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_SET(value) (((value) << 0) & 0x00000001)
8825 
8826 #ifndef __ASSEMBLY__
8827 /*
8828  * WARNING: The C register and register group struct declarations are provided for
8829  * convenience and illustrative purposes. They should, however, be used with
8830  * caution as the C language standard provides no guarantees about the alignment or
8831  * atomicity of device memory accesses. The recommended practice for writing
8832  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8833  * alt_write_word() functions.
8834  *
8835  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST.
8836  */
8837 struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_s
8838 {
8839  uint32_t OVERFLOWRESET : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST */
8840  uint32_t : 31; /* *UNDEFINED* */
8841 };
8842 
8843 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST. */
8844 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_s ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_t;
8845 #endif /* __ASSEMBLY__ */
8846 
8847 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST register. */
8848 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_RESET 0x00000000
8849 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST register from the beginning of the component. */
8850 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OFST 0x70
8851 
8852 /*
8853  * Register : Probe_emacs_main_TransactionStatProfiler_PendingEventMode
8854  *
8855  *
8856  * Register Layout
8857  *
8858  * Bits | Access | Reset | Description
8859  * :-------|:-------|:--------|:----------------------------------------------------------------------------
8860  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD
8861  * [31:1] | ??? | Unknown | *UNDEFINED*
8862  *
8863  */
8864 /*
8865  * Field : PENDINGEVENTMODE
8866  *
8867  * Register pendingEventMode is a 1-bit register that configures the pending event
8868  * mode. When set to 0 (CYCLE), and when register mode is set to PENDING, the
8869  * pending event is generated on each cycle when the counter is greater than
8870  * zero.When set to 1 (STOP) the pending event is generated on each stop event.
8871  *
8872  * Field Access Macros:
8873  *
8874  */
8875 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD register field. */
8876 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_LSB 0
8877 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD register field. */
8878 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_MSB 0
8879 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD register field. */
8880 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_WIDTH 1
8881 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD register field value. */
8882 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_SET_MSK 0x00000001
8883 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD register field value. */
8884 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_CLR_MSK 0xfffffffe
8885 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD register field. */
8886 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_RESET 0x0
8887 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD field value from a register. */
8888 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_GET(value) (((value) & 0x00000001) >> 0)
8889 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD register field value suitable for setting the register. */
8890 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_SET(value) (((value) << 0) & 0x00000001)
8891 
8892 #ifndef __ASSEMBLY__
8893 /*
8894  * WARNING: The C register and register group struct declarations are provided for
8895  * convenience and illustrative purposes. They should, however, be used with
8896  * caution as the C language standard provides no guarantees about the alignment or
8897  * atomicity of device memory accesses. The recommended practice for writing
8898  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8899  * alt_write_word() functions.
8900  *
8901  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD.
8902  */
8903 struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_s
8904 {
8905  uint32_t PENDINGEVENTMODE : 1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD */
8906  uint32_t : 31; /* *UNDEFINED* */
8907 };
8908 
8909 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD. */
8910 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_s ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_t;
8911 #endif /* __ASSEMBLY__ */
8912 
8913 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD register. */
8914 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_RESET 0x00000000
8915 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD register from the beginning of the component. */
8916 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_OFST 0x74
8917 
8918 /*
8919  * Register : Probe_emacs_main_TransactionStatProfiler_PreScaler
8920  *
8921  *
8922  * Register Layout
8923  *
8924  * Bits | Access | Reset | Description
8925  * :-------|:-------|:--------|:----------------------------------------------------------------
8926  * [7:0] | RW | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER
8927  * [31:8] | ??? | Unknown | *UNDEFINED*
8928  *
8929  */
8930 /*
8931  * Field : PRESCALER
8932  *
8933  * 8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling
8934  * value between 1 (default) and 256. If set to 0, pre-scaling is disabled. If set
8935  * to any other supported value "n", the threshold counter value is divided by (n +
8936  * 1).
8937  *
8938  * Field Access Macros:
8939  *
8940  */
8941 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER register field. */
8942 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_LSB 0
8943 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER register field. */
8944 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_MSB 7
8945 /* The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER register field. */
8946 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_WIDTH 8
8947 /* The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER register field value. */
8948 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_SET_MSK 0x000000ff
8949 /* The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER register field value. */
8950 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_CLR_MSK 0xffffff00
8951 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER register field. */
8952 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_RESET 0x0
8953 /* Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER field value from a register. */
8954 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_GET(value) (((value) & 0x000000ff) >> 0)
8955 /* Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER register field value suitable for setting the register. */
8956 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_SET(value) (((value) << 0) & 0x000000ff)
8957 
8958 #ifndef __ASSEMBLY__
8959 /*
8960  * WARNING: The C register and register group struct declarations are provided for
8961  * convenience and illustrative purposes. They should, however, be used with
8962  * caution as the C language standard provides no guarantees about the alignment or
8963  * atomicity of device memory accesses. The recommended practice for writing
8964  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8965  * alt_write_word() functions.
8966  *
8967  * The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER.
8968  */
8969 struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_s
8970 {
8971  uint32_t PRESCALER : 8; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER */
8972  uint32_t : 24; /* *UNDEFINED* */
8973 };
8974 
8975 /* The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER. */
8976 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_s ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_t;
8977 #endif /* __ASSEMBLY__ */
8978 
8979 /* The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER register. */
8980 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_RESET 0x00000000
8981 /* The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER register from the beginning of the component. */
8982 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_OFST 0x78
8983 
8984 #ifndef __ASSEMBLY__
8985 /*
8986  * WARNING: The C register and register group struct declarations are provided for
8987  * convenience and illustrative purposes. They should, however, be used with
8988  * caution as the C language standard provides no guarantees about the alignment or
8989  * atomicity of device memory accesses. The recommended practice for writing
8990  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8991  * alt_write_word() functions.
8992  *
8993  * The struct declaration for register group ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER.
8994  */
8995 struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_s
8996 {
8997  ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_t Probe_emacs_main_TransactionStatProfiler_Id_CoreId; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID */
8998  ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_t Probe_emacs_main_TransactionStatProfiler_Id_RevisionId; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID */
8999  ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_t Probe_emacs_main_TransactionStatProfiler_En; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN */
9000  ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_t Probe_emacs_main_TransactionStatProfiler_Mode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD */
9001  volatile uint32_t _pad_0x10_0x2b[7]; /* *UNDEFINED* */
9002  ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_t Probe_emacs_main_TransactionStatProfiler_Thresholds_0_0; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0 */
9003  ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_t Probe_emacs_main_TransactionStatProfiler_Thresholds_0_1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1 */
9004  ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_t Probe_emacs_main_TransactionStatProfiler_Thresholds_0_2; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2 */
9005  volatile uint32_t _pad_0x38_0x6b[13]; /* *UNDEFINED* */
9006  ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_t Probe_emacs_main_TransactionStatProfiler_OverflowStatus; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT */
9007  ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_t Probe_emacs_main_TransactionStatProfiler_OverflowReset; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST */
9008  ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_t Probe_emacs_main_TransactionStatProfiler_PendingEventMode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD */
9009  ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_t Probe_emacs_main_TransactionStatProfiler_PreScaler; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER */
9010  volatile uint32_t _pad_0x7c_0x80; /* *UNDEFINED* */
9011 };
9012 
9013 /* The typedef declaration for register group ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER. */
9014 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_s ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_t;
9015 /* The struct declaration for the raw register contents of register group ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER. */
9016 struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_raw_s
9017 {
9018  volatile uint32_t Probe_emacs_main_TransactionStatProfiler_Id_CoreId; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID */
9019  volatile uint32_t Probe_emacs_main_TransactionStatProfiler_Id_RevisionId; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID */
9020  volatile uint32_t Probe_emacs_main_TransactionStatProfiler_En; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN */
9021  volatile uint32_t Probe_emacs_main_TransactionStatProfiler_Mode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD */
9022  uint32_t _pad_0x10_0x2b[7]; /* *UNDEFINED* */
9023  volatile uint32_t Probe_emacs_main_TransactionStatProfiler_Thresholds_0_0; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0 */
9024  volatile uint32_t Probe_emacs_main_TransactionStatProfiler_Thresholds_0_1; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1 */
9025  volatile uint32_t Probe_emacs_main_TransactionStatProfiler_Thresholds_0_2; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2 */
9026  uint32_t _pad_0x38_0x6b[13]; /* *UNDEFINED* */
9027  volatile uint32_t Probe_emacs_main_TransactionStatProfiler_OverflowStatus; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT */
9028  volatile uint32_t Probe_emacs_main_TransactionStatProfiler_OverflowReset; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST */
9029  volatile uint32_t Probe_emacs_main_TransactionStatProfiler_PendingEventMode; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD */
9030  volatile uint32_t Probe_emacs_main_TransactionStatProfiler_PreScaler; /* ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER */
9031  uint32_t _pad_0x7c_0x80; /* *UNDEFINED* */
9032 };
9033 
9034 /* The typedef declaration for the raw register contents of register group ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER. */
9035 typedef volatile struct ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_raw_s ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_raw_t;
9036 #endif /* __ASSEMBLY__ */
9037 
9038 
9039 /*
9040  * Component : ALT_NOC_MPU_PRB_MPU_MAIN_PRB
9041  *
9042  */
9043 /*
9044  * Register : Probe_MPU_main_Probe_Id_CoreId
9045  *
9046  * Register Layout
9047  *
9048  * Bits | Access | Reset | Description
9049  * :-------|:-------|:---------|:-----------------------------------------
9050  * [7:0] | R | 0x6 | ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID
9051  * [31:8] | R | 0xc7360b | ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM
9052  *
9053  */
9054 /*
9055  * Field : CORETYPEID
9056  *
9057  * Field identifying the type of IP.
9058  *
9059  * Field Access Macros:
9060  *
9061  */
9062 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID register field. */
9063 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_LSB 0
9064 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID register field. */
9065 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_MSB 7
9066 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID register field. */
9067 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_WIDTH 8
9068 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID register field value. */
9069 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_SET_MSK 0x000000ff
9070 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID register field value. */
9071 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_CLR_MSK 0xffffff00
9072 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID register field. */
9073 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_RESET 0x6
9074 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID field value from a register. */
9075 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
9076 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID register field value suitable for setting the register. */
9077 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
9078 
9079 /*
9080  * Field : CORECHECKSUM
9081  *
9082  * Field containing a checksum of the parameters of the IP.
9083  *
9084  * Field Access Macros:
9085  *
9086  */
9087 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM register field. */
9088 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_LSB 8
9089 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM register field. */
9090 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_MSB 31
9091 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM register field. */
9092 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_WIDTH 24
9093 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM register field value. */
9094 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_SET_MSK 0xffffff00
9095 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM register field value. */
9096 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_CLR_MSK 0x000000ff
9097 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM register field. */
9098 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_RESET 0xc7360b
9099 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM field value from a register. */
9100 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
9101 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM register field value suitable for setting the register. */
9102 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
9103 
9104 #ifndef __ASSEMBLY__
9105 /*
9106  * WARNING: The C register and register group struct declarations are provided for
9107  * convenience and illustrative purposes. They should, however, be used with
9108  * caution as the C language standard provides no guarantees about the alignment or
9109  * atomicity of device memory accesses. The recommended practice for writing
9110  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9111  * alt_write_word() functions.
9112  *
9113  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_COREID.
9114  */
9115 struct ALT_NOC_MPU_PRB_MPU_MAIN_COREID_s
9116 {
9117  const uint32_t CORETYPEID : 8; /* ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID */
9118  const uint32_t CORECHECKSUM : 24; /* ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM */
9119 };
9120 
9121 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_COREID. */
9122 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_COREID_s ALT_NOC_MPU_PRB_MPU_MAIN_COREID_t;
9123 #endif /* __ASSEMBLY__ */
9124 
9125 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_COREID register. */
9126 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_RESET 0xc7360b06
9127 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_COREID register from the beginning of the component. */
9128 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_OFST 0x0
9129 
9130 /*
9131  * Register : Probe_MPU_main_Probe_Id_RevisionId
9132  *
9133  * Register Layout
9134  *
9135  * Bits | Access | Reset | Description
9136  * :-------|:-------|:--------|:-----------------------------------------
9137  * [7:0] | R | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID
9138  * [31:8] | R | 0x129ff | ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID
9139  *
9140  */
9141 /*
9142  * Field : USERID
9143  *
9144  * Field containing a user defined value, not used anywhere inside the IP itself.
9145  *
9146  * Field Access Macros:
9147  *
9148  */
9149 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID register field. */
9150 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_LSB 0
9151 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID register field. */
9152 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_MSB 7
9153 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID register field. */
9154 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_WIDTH 8
9155 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID register field value. */
9156 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_SET_MSK 0x000000ff
9157 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID register field value. */
9158 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_CLR_MSK 0xffffff00
9159 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID register field. */
9160 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_RESET 0x0
9161 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID field value from a register. */
9162 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
9163 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID register field value suitable for setting the register. */
9164 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
9165 
9166 /*
9167  * Field : FLEXNOCID
9168  *
9169  * Field containing the build revision of the software used to generate the IP HDL
9170  * code.
9171  *
9172  * Field Access Macros:
9173  *
9174  */
9175 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID register field. */
9176 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_LSB 8
9177 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID register field. */
9178 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_MSB 31
9179 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID register field. */
9180 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_WIDTH 24
9181 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID register field value. */
9182 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_SET_MSK 0xffffff00
9183 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID register field value. */
9184 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_CLR_MSK 0x000000ff
9185 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID register field. */
9186 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_RESET 0x129ff
9187 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID field value from a register. */
9188 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
9189 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID register field value suitable for setting the register. */
9190 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
9191 
9192 #ifndef __ASSEMBLY__
9193 /*
9194  * WARNING: The C register and register group struct declarations are provided for
9195  * convenience and illustrative purposes. They should, however, be used with
9196  * caution as the C language standard provides no guarantees about the alignment or
9197  * atomicity of device memory accesses. The recommended practice for writing
9198  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9199  * alt_write_word() functions.
9200  *
9201  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_REVID.
9202  */
9203 struct ALT_NOC_MPU_PRB_MPU_MAIN_REVID_s
9204 {
9205  const uint32_t USERID : 8; /* ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID */
9206  const uint32_t FLEXNOCID : 24; /* ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID */
9207 };
9208 
9209 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_REVID. */
9210 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_REVID_s ALT_NOC_MPU_PRB_MPU_MAIN_REVID_t;
9211 #endif /* __ASSEMBLY__ */
9212 
9213 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_REVID register. */
9214 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_RESET 0x0129ff00
9215 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_REVID register from the beginning of the component. */
9216 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_OFST 0x4
9217 
9218 /*
9219  * Register : Probe_MPU_main_Probe_MainCtl
9220  *
9221  * Register MainCtl contains probe global control bits. The register has seven bit
9222  * fields:
9223  *
9224  * Register Layout
9225  *
9226  * Bits | Access | Reset | Description
9227  * :-------|:-------|:--------|:-----------------------------------------------------------
9228  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN
9229  * [1] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN
9230  * [2] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN
9231  * [3] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN
9232  * [4] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN
9233  * [5] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP
9234  * [6] | R | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD
9235  * [7] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN
9236  * [31:8] | ??? | Unknown | *UNDEFINED*
9237  *
9238  */
9239 /*
9240  * Field : ERREN
9241  *
9242  * Register field ErrEn enables the probe to send on the ObsTx output any packet
9243  * with Error status, independently of filtering mechanisms, thus constituting a
9244  * simple supplementary global filter.
9245  *
9246  * Field Access Macros:
9247  *
9248  */
9249 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN register field. */
9250 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_LSB 0
9251 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN register field. */
9252 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_MSB 0
9253 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN register field. */
9254 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_WIDTH 1
9255 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN register field value. */
9256 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_SET_MSK 0x00000001
9257 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN register field value. */
9258 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_CLR_MSK 0xfffffffe
9259 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN register field. */
9260 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_RESET 0x0
9261 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN field value from a register. */
9262 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_GET(value) (((value) & 0x00000001) >> 0)
9263 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN register field value suitable for setting the register. */
9264 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_SET(value) (((value) << 0) & 0x00000001)
9265 
9266 /*
9267  * Field : TRACEEN
9268  *
9269  * Register field TraceEn enables the probe to send filtered packets (Trace) on the
9270  * ObsTx observation output.
9271  *
9272  * Field Access Macros:
9273  *
9274  */
9275 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN register field. */
9276 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_LSB 1
9277 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN register field. */
9278 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_MSB 1
9279 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN register field. */
9280 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_WIDTH 1
9281 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN register field value. */
9282 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_SET_MSK 0x00000002
9283 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN register field value. */
9284 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_CLR_MSK 0xfffffffd
9285 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN register field. */
9286 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_RESET 0x0
9287 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN field value from a register. */
9288 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_GET(value) (((value) & 0x00000002) >> 1)
9289 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN register field value suitable for setting the register. */
9290 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_SET(value) (((value) << 1) & 0x00000002)
9291 
9292 /*
9293  * Field : PAYLOADEN
9294  *
9295  * Register field PayloadEn, when set to 1, enables traces to contain headers and
9296  * payload. When set ot 0, only headers are reported.
9297  *
9298  * Field Access Macros:
9299  *
9300  */
9301 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN register field. */
9302 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_LSB 2
9303 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN register field. */
9304 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_MSB 2
9305 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN register field. */
9306 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_WIDTH 1
9307 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN register field value. */
9308 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_SET_MSK 0x00000004
9309 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN register field value. */
9310 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_CLR_MSK 0xfffffffb
9311 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN register field. */
9312 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_RESET 0x0
9313 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN field value from a register. */
9314 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_GET(value) (((value) & 0x00000004) >> 2)
9315 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN register field value suitable for setting the register. */
9316 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_SET(value) (((value) << 2) & 0x00000004)
9317 
9318 /*
9319  * Field : STATEN
9320  *
9321  * When set to 1, register field StatEn enables statistics profiling. The probe
9322  * sendS statistics results to the output for signal ObsTx. All statistics counters
9323  * are cleared when the StatEn bit goes from 0 to 1. When set to 0, counters are
9324  * disabled.
9325  *
9326  * Field Access Macros:
9327  *
9328  */
9329 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN register field. */
9330 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_LSB 3
9331 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN register field. */
9332 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_MSB 3
9333 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN register field. */
9334 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_WIDTH 1
9335 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN register field value. */
9336 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_SET_MSK 0x00000008
9337 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN register field value. */
9338 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_CLR_MSK 0xfffffff7
9339 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN register field. */
9340 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_RESET 0x0
9341 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN field value from a register. */
9342 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_GET(value) (((value) & 0x00000008) >> 3)
9343 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN register field value suitable for setting the register. */
9344 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_SET(value) (((value) << 3) & 0x00000008)
9345 
9346 /*
9347  * Field : ALARMEN
9348  *
9349  * When set, register field AlarmEn enables the probe to collect alarm-related
9350  * information. When the register field bit is null, both TraceAlarm and StatAlarm
9351  * outputs are driven to 0.
9352  *
9353  * Field Access Macros:
9354  *
9355  */
9356 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN register field. */
9357 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_LSB 4
9358 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN register field. */
9359 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_MSB 4
9360 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN register field. */
9361 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_WIDTH 1
9362 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN register field value. */
9363 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_SET_MSK 0x00000010
9364 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN register field value. */
9365 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_CLR_MSK 0xffffffef
9366 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN register field. */
9367 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_RESET 0x0
9368 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN field value from a register. */
9369 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_GET(value) (((value) & 0x00000010) >> 4)
9370 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN register field value suitable for setting the register. */
9371 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_SET(value) (((value) << 4) & 0x00000010)
9372 
9373 /*
9374  * Field : STATCONDDUMP
9375  *
9376  * When set, register field StatCondDump enables the dump of a statistics frame to
9377  * the range of counter values set for registers StatAlarmMin, StatAlarmMax, and
9378  * AlarmMode. This field also renders register StatAlarmStatus inoperative. When
9379  * parameter statisticsCounterAlarm is set to False, the StatCondDump register bit
9380  * is reserved.
9381  *
9382  * Field Access Macros:
9383  *
9384  */
9385 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP register field. */
9386 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_LSB 5
9387 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP register field. */
9388 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_MSB 5
9389 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP register field. */
9390 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_WIDTH 1
9391 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP register field value. */
9392 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_SET_MSK 0x00000020
9393 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP register field value. */
9394 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_CLR_MSK 0xffffffdf
9395 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP register field. */
9396 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_RESET 0x0
9397 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP field value from a register. */
9398 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_GET(value) (((value) & 0x00000020) >> 5)
9399 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP register field value suitable for setting the register. */
9400 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_SET(value) (((value) << 5) & 0x00000020)
9401 
9402 /*
9403  * Field : INTRUSIVEMODE
9404  *
9405  * When set to 1, register field IntrusiveMode enables trace operation in Intrusive
9406  * flow-control mode. When set to 0, the register enables trace operation in
9407  * Overflow flow-control mode
9408  *
9409  * Field Access Macros:
9410  *
9411  */
9412 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD register field. */
9413 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_LSB 6
9414 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD register field. */
9415 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_MSB 6
9416 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD register field. */
9417 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_WIDTH 1
9418 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD register field value. */
9419 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_SET_MSK 0x00000040
9420 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD register field value. */
9421 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_CLR_MSK 0xffffffbf
9422 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD register field. */
9423 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_RESET 0x0
9424 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD field value from a register. */
9425 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_GET(value) (((value) & 0x00000040) >> 6)
9426 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD register field value suitable for setting the register. */
9427 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_SET(value) (((value) << 6) & 0x00000040)
9428 
9429 /*
9430  * Field : FILTBYTEALWAYSCHAINABLEEN
9431  *
9432  * When set to 0, filters are mapped to all statistic counters when counting bytes
9433  * or enabled bytes. Therefore, only filter events mapped to even counters can be
9434  * counted using a pair of chained counters.When set to 1, filters are mapped only
9435  * to even statistic counters when counting bytes or enabled bytes. Thus events
9436  * from any filter can be counted using a pair of chained counters.
9437  *
9438  * Field Access Macros:
9439  *
9440  */
9441 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
9442 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_LSB 7
9443 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
9444 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MSB 7
9445 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
9446 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_WIDTH 1
9447 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value. */
9448 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET_MSK 0x00000080
9449 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value. */
9450 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_CLR_MSK 0xffffff7f
9451 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field. */
9452 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_RESET 0x0
9453 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN field value from a register. */
9454 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_GET(value) (((value) & 0x00000080) >> 7)
9455 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN register field value suitable for setting the register. */
9456 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET(value) (((value) << 7) & 0x00000080)
9457 
9458 #ifndef __ASSEMBLY__
9459 /*
9460  * WARNING: The C register and register group struct declarations are provided for
9461  * convenience and illustrative purposes. They should, however, be used with
9462  * caution as the C language standard provides no guarantees about the alignment or
9463  * atomicity of device memory accesses. The recommended practice for writing
9464  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9465  * alt_write_word() functions.
9466  *
9467  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL.
9468  */
9469 struct ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_s
9470 {
9471  uint32_t ERREN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN */
9472  uint32_t TRACEEN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN */
9473  uint32_t PAYLOADEN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN */
9474  uint32_t STATEN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN */
9475  uint32_t ALARMEN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN */
9476  uint32_t STATCONDDUMP : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP */
9477  const uint32_t INTRUSIVEMODE : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD */
9478  uint32_t FILTBYTEALWAYSCHAINABLEEN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN */
9479  uint32_t : 24; /* *UNDEFINED* */
9480 };
9481 
9482 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL. */
9483 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_s ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_t;
9484 #endif /* __ASSEMBLY__ */
9485 
9486 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL register. */
9487 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_RESET 0x00000000
9488 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL register from the beginning of the component. */
9489 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_OFST 0x8
9490 
9491 /*
9492  * Register : Probe_MPU_main_Probe_CfgCtl
9493  *
9494  * Register Layout
9495  *
9496  * Bits | Access | Reset | Description
9497  * :-------|:-------|:--------|:---------------------------------------
9498  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN
9499  * [1] | R | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT
9500  * [31:2] | ??? | Unknown | *UNDEFINED*
9501  *
9502  */
9503 /*
9504  * Field : GLOBALEN
9505  *
9506  *
9507  * Field Access Macros:
9508  *
9509  */
9510 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN register field. */
9511 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_LSB 0
9512 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN register field. */
9513 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_MSB 0
9514 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN register field. */
9515 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_WIDTH 1
9516 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN register field value. */
9517 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_SET_MSK 0x00000001
9518 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN register field value. */
9519 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_CLR_MSK 0xfffffffe
9520 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN register field. */
9521 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_RESET 0x0
9522 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN field value from a register. */
9523 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_GET(value) (((value) & 0x00000001) >> 0)
9524 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN register field value suitable for setting the register. */
9525 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_SET(value) (((value) << 0) & 0x00000001)
9526 
9527 /*
9528  * Field : ACTIVE
9529  *
9530  *
9531  * Field Access Macros:
9532  *
9533  */
9534 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT register field. */
9535 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_LSB 1
9536 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT register field. */
9537 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_MSB 1
9538 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT register field. */
9539 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_WIDTH 1
9540 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT register field value. */
9541 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_SET_MSK 0x00000002
9542 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT register field value. */
9543 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_CLR_MSK 0xfffffffd
9544 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT register field. */
9545 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_RESET 0x0
9546 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT field value from a register. */
9547 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_GET(value) (((value) & 0x00000002) >> 1)
9548 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT register field value suitable for setting the register. */
9549 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_SET(value) (((value) << 1) & 0x00000002)
9550 
9551 #ifndef __ASSEMBLY__
9552 /*
9553  * WARNING: The C register and register group struct declarations are provided for
9554  * convenience and illustrative purposes. They should, however, be used with
9555  * caution as the C language standard provides no guarantees about the alignment or
9556  * atomicity of device memory accesses. The recommended practice for writing
9557  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9558  * alt_write_word() functions.
9559  *
9560  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL.
9561  */
9562 struct ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_s
9563 {
9564  uint32_t GLOBALEN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN */
9565  const uint32_t ACTIVE : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT */
9566  uint32_t : 30; /* *UNDEFINED* */
9567 };
9568 
9569 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL. */
9570 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_s ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_t;
9571 #endif /* __ASSEMBLY__ */
9572 
9573 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL register. */
9574 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_RESET 0x00000000
9575 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL register from the beginning of the component. */
9576 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_OFST 0xc
9577 
9578 /*
9579  * Register : Probe_MPU_main_Probe_FilterLut
9580  *
9581  *
9582  * Register Layout
9583  *
9584  * Bits | Access | Reset | Description
9585  * :-------|:-------|:--------|:---------------------------------------
9586  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT
9587  * [31:2] | ??? | Unknown | *UNDEFINED*
9588  *
9589  */
9590 /*
9591  * Field : FILTERLUT
9592  *
9593  * Register FilterLut contains a look-up table that is used to combine filter
9594  * outputs in order to trace packets. Packet tracing is enabled when the FilterLut
9595  * bit of index (FNout ... F0out) is equal to 1.The number of bits in register
9596  * FilterLut is determined by the setting for parameter nFilter, calculated as
9597  * 2**nFilter.When parameter nFilter is set to None, FilterLut is reserved.
9598  *
9599  * Field Access Macros:
9600  *
9601  */
9602 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT register field. */
9603 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_LSB 0
9604 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT register field. */
9605 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_MSB 1
9606 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT register field. */
9607 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_WIDTH 2
9608 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT register field value. */
9609 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_SET_MSK 0x00000003
9610 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT register field value. */
9611 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_CLR_MSK 0xfffffffc
9612 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT register field. */
9613 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_RESET 0x0
9614 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT field value from a register. */
9615 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_GET(value) (((value) & 0x00000003) >> 0)
9616 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT register field value suitable for setting the register. */
9617 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_SET(value) (((value) << 0) & 0x00000003)
9618 
9619 #ifndef __ASSEMBLY__
9620 /*
9621  * WARNING: The C register and register group struct declarations are provided for
9622  * convenience and illustrative purposes. They should, however, be used with
9623  * caution as the C language standard provides no guarantees about the alignment or
9624  * atomicity of device memory accesses. The recommended practice for writing
9625  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9626  * alt_write_word() functions.
9627  *
9628  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT.
9629  */
9630 struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_s
9631 {
9632  uint32_t FILTERLUT : 2; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT */
9633  uint32_t : 30; /* *UNDEFINED* */
9634 };
9635 
9636 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT. */
9637 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_s ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_t;
9638 #endif /* __ASSEMBLY__ */
9639 
9640 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT register. */
9641 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_RESET 0x00000000
9642 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT register from the beginning of the component. */
9643 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_OFST 0x14
9644 
9645 /*
9646  * Register : Probe_MPU_main_Probe_TraceAlarmEn
9647  *
9648  *
9649  * Register Layout
9650  *
9651  * Bits | Access | Reset | Description
9652  * :-------|:-------|:--------|:---------------------------------------------------
9653  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN
9654  * [31:2] | ??? | Unknown | *UNDEFINED*
9655  *
9656  */
9657 /*
9658  * Field : TRACEALARMEN
9659  *
9660  * Register TraceAlarmEn controls which lookup table or filter can set the
9661  * TraceAlarm signal output once the trace alarm status is set. The number of bits
9662  * in register TraceAlarmEn is determined by the value set for parameter nFilter +
9663  * 1.Bit nFilter controls the lookup table output, and bits nFilter:0 control the
9664  * corresponding filter output. When parameter nFilter is set to None, TraceAlarmEn
9665  * is reserved.
9666  *
9667  * Field Access Macros:
9668  *
9669  */
9670 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN register field. */
9671 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_LSB 0
9672 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN register field. */
9673 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_MSB 1
9674 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN register field. */
9675 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_WIDTH 2
9676 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN register field value. */
9677 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_SET_MSK 0x00000003
9678 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN register field value. */
9679 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_CLR_MSK 0xfffffffc
9680 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN register field. */
9681 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_RESET 0x0
9682 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN field value from a register. */
9683 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_GET(value) (((value) & 0x00000003) >> 0)
9684 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN register field value suitable for setting the register. */
9685 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_SET(value) (((value) << 0) & 0x00000003)
9686 
9687 #ifndef __ASSEMBLY__
9688 /*
9689  * WARNING: The C register and register group struct declarations are provided for
9690  * convenience and illustrative purposes. They should, however, be used with
9691  * caution as the C language standard provides no guarantees about the alignment or
9692  * atomicity of device memory accesses. The recommended practice for writing
9693  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9694  * alt_write_word() functions.
9695  *
9696  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN.
9697  */
9698 struct ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_s
9699 {
9700  uint32_t TRACEALARMEN : 2; /* ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN */
9701  uint32_t : 30; /* *UNDEFINED* */
9702 };
9703 
9704 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN. */
9705 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_s ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_t;
9706 #endif /* __ASSEMBLY__ */
9707 
9708 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN register. */
9709 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_RESET 0x00000000
9710 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN register from the beginning of the component. */
9711 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_OFST 0x18
9712 
9713 /*
9714  * Register : Probe_MPU_main_Probe_TraceAlarmStatus
9715  *
9716  *
9717  * Register Layout
9718  *
9719  * Bits | Access | Reset | Description
9720  * :-------|:-------|:--------|:-------------------------------------------------------
9721  * [1:0] | R | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT
9722  * [31:2] | ??? | Unknown | *UNDEFINED*
9723  *
9724  */
9725 /*
9726  * Field : TRACEALARMSTATUS
9727  *
9728  * Register TraceAlarmStatus is a read-only register that indicates which lookup
9729  * table or filter has been matched by a packet, independently of register
9730  * TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is
9731  * determined by the value set for parameter nFilter + 1.When nFilter is set to
9732  * None, TraceAlarmStatus is reserved.
9733  *
9734  * Field Access Macros:
9735  *
9736  */
9737 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field. */
9738 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_LSB 0
9739 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field. */
9740 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_MSB 1
9741 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field. */
9742 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_WIDTH 2
9743 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field value. */
9744 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_SET_MSK 0x00000003
9745 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field value. */
9746 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_CLR_MSK 0xfffffffc
9747 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field. */
9748 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_RESET 0x0
9749 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT field value from a register. */
9750 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_GET(value) (((value) & 0x00000003) >> 0)
9751 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT register field value suitable for setting the register. */
9752 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_SET(value) (((value) << 0) & 0x00000003)
9753 
9754 #ifndef __ASSEMBLY__
9755 /*
9756  * WARNING: The C register and register group struct declarations are provided for
9757  * convenience and illustrative purposes. They should, however, be used with
9758  * caution as the C language standard provides no guarantees about the alignment or
9759  * atomicity of device memory accesses. The recommended practice for writing
9760  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9761  * alt_write_word() functions.
9762  *
9763  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT.
9764  */
9765 struct ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_s
9766 {
9767  const uint32_t TRACEALARMSTATUS : 2; /* ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT */
9768  uint32_t : 30; /* *UNDEFINED* */
9769 };
9770 
9771 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT. */
9772 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_s ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_t;
9773 #endif /* __ASSEMBLY__ */
9774 
9775 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT register. */
9776 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_RESET 0x00000000
9777 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT register from the beginning of the component. */
9778 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_OFST 0x1c
9779 
9780 /*
9781  * Register : Probe_MPU_main_Probe_TraceAlarmClr
9782  *
9783  *
9784  * Register Layout
9785  *
9786  * Bits | Access | Reset | Description
9787  * :-------|:-------|:--------|:-----------------------------------------------------
9788  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR
9789  * [31:2] | ??? | Unknown | *UNDEFINED*
9790  *
9791  */
9792 /*
9793  * Field : TRACEALARMCLR
9794  *
9795  * Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in
9796  * register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal
9797  * to (nFilter + 1). When nFilter is set to 0, TraceAlarmClr is reserved.NOTE The
9798  * written value is not stored in TraceAlarmClr. A read always returns 0.
9799  *
9800  * Field Access Macros:
9801  *
9802  */
9803 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR register field. */
9804 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_LSB 0
9805 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR register field. */
9806 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_MSB 1
9807 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR register field. */
9808 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_WIDTH 2
9809 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR register field value. */
9810 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x00000003
9811 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR register field value. */
9812 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xfffffffc
9813 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR register field. */
9814 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0
9815 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR field value from a register. */
9816 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_GET(value) (((value) & 0x00000003) >> 0)
9817 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR register field value suitable for setting the register. */
9818 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_SET(value) (((value) << 0) & 0x00000003)
9819 
9820 #ifndef __ASSEMBLY__
9821 /*
9822  * WARNING: The C register and register group struct declarations are provided for
9823  * convenience and illustrative purposes. They should, however, be used with
9824  * caution as the C language standard provides no guarantees about the alignment or
9825  * atomicity of device memory accesses. The recommended practice for writing
9826  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9827  * alt_write_word() functions.
9828  *
9829  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR.
9830  */
9831 struct ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_s
9832 {
9833  uint32_t TRACEALARMCLR : 2; /* ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR */
9834  uint32_t : 30; /* *UNDEFINED* */
9835 };
9836 
9837 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR. */
9838 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_s ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_t;
9839 #endif /* __ASSEMBLY__ */
9840 
9841 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR register. */
9842 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_RESET 0x00000000
9843 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR register from the beginning of the component. */
9844 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_OFST 0x20
9845 
9846 /*
9847  * Register : Probe_MPU_main_Probe_StatPeriod
9848  *
9849  *
9850  * Register Layout
9851  *
9852  * Bits | Access | Reset | Description
9853  * :-------|:-------|:--------|:-----------------------------------------------
9854  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD
9855  * [31:5] | ??? | Unknown | *UNDEFINED*
9856  *
9857  */
9858 /*
9859  * Field : STATPERIOD
9860  *
9861  * Register StatPeriod is a 5-bit register that sets a period, within a range of 2
9862  * cycles to 2 gigacycles, during which statistics are collected before being
9863  * dumped automatically. Setting the register implicitly enables automatic mode
9864  * operation for statistics collection. The period is calculated with the formula:
9865  * N_Cycle = 2**StatPeriodWhen register StatPeriod is set to its default value 0,
9866  * automatic dump mode is disabled, and register StatGo is activated for manual
9867  * mode operation. Note: When parameter statisticsCollection is set to False,
9868  * StatPeriod is reserved.
9869  *
9870  * Field Access Macros:
9871  *
9872  */
9873 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD register field. */
9874 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_LSB 0
9875 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD register field. */
9876 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_MSB 4
9877 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD register field. */
9878 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_WIDTH 5
9879 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD register field value. */
9880 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_SET_MSK 0x0000001f
9881 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD register field value. */
9882 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_CLR_MSK 0xffffffe0
9883 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD register field. */
9884 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_RESET 0x0
9885 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD field value from a register. */
9886 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
9887 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD register field value suitable for setting the register. */
9888 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_SET(value) (((value) << 0) & 0x0000001f)
9889 
9890 #ifndef __ASSEMBLY__
9891 /*
9892  * WARNING: The C register and register group struct declarations are provided for
9893  * convenience and illustrative purposes. They should, however, be used with
9894  * caution as the C language standard provides no guarantees about the alignment or
9895  * atomicity of device memory accesses. The recommended practice for writing
9896  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9897  * alt_write_word() functions.
9898  *
9899  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD.
9900  */
9901 struct ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_s
9902 {
9903  uint32_t STATPERIOD : 5; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD */
9904  uint32_t : 27; /* *UNDEFINED* */
9905 };
9906 
9907 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD. */
9908 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_s ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_t;
9909 #endif /* __ASSEMBLY__ */
9910 
9911 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD register. */
9912 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_RESET 0x00000000
9913 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD register from the beginning of the component. */
9914 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_OFST 0x24
9915 
9916 /*
9917  * Register : Probe_MPU_main_Probe_StatGo
9918  *
9919  *
9920  * Register Layout
9921  *
9922  * Bits | Access | Reset | Description
9923  * :-------|:-------|:--------|:---------------------------------------
9924  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO
9925  * [31:1] | ??? | Unknown | *UNDEFINED*
9926  *
9927  */
9928 /*
9929  * Field : STATGO
9930  *
9931  * Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The
9932  * register is active when statistics collection operates in manual mode, that is,
9933  * when register StatPeriod is set to 0.NOTE The written value is not stored in
9934  * StatGo. A read always returns 0.
9935  *
9936  * Field Access Macros:
9937  *
9938  */
9939 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO register field. */
9940 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_LSB 0
9941 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO register field. */
9942 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_MSB 0
9943 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO register field. */
9944 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_WIDTH 1
9945 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO register field value. */
9946 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_SET_MSK 0x00000001
9947 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO register field value. */
9948 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_CLR_MSK 0xfffffffe
9949 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO register field. */
9950 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_RESET 0x0
9951 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO field value from a register. */
9952 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_GET(value) (((value) & 0x00000001) >> 0)
9953 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO register field value suitable for setting the register. */
9954 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_SET(value) (((value) << 0) & 0x00000001)
9955 
9956 #ifndef __ASSEMBLY__
9957 /*
9958  * WARNING: The C register and register group struct declarations are provided for
9959  * convenience and illustrative purposes. They should, however, be used with
9960  * caution as the C language standard provides no guarantees about the alignment or
9961  * atomicity of device memory accesses. The recommended practice for writing
9962  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9963  * alt_write_word() functions.
9964  *
9965  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATGO.
9966  */
9967 struct ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_s
9968 {
9969  uint32_t STATGO : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO */
9970  uint32_t : 31; /* *UNDEFINED* */
9971 };
9972 
9973 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATGO. */
9974 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_s ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_t;
9975 #endif /* __ASSEMBLY__ */
9976 
9977 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATGO register. */
9978 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_RESET 0x00000000
9979 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_STATGO register from the beginning of the component. */
9980 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_OFST 0x28
9981 
9982 /*
9983  * Register : Probe_MPU_main_Probe_StatAlarmMin
9984  *
9985  *
9986  * Register Layout
9987  *
9988  * Bits | Access | Reset | Description
9989  * :-------|:-------|:------|:---------------------------------------------------
9990  * [31:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN
9991  *
9992  */
9993 /*
9994  * Field : STATALARMMIN
9995  *
9996  * Register StatAlarmMin contains the minimum count value used in statistics alarm
9997  * comparisons. The number of bits is equal to twice the value set forparameter
9998  * wStatisticsCounter. When parameter statisticsCounterAlarm is set to False,
9999  * StatAlarmMin is reserved.
10000  *
10001  * Field Access Macros:
10002  *
10003  */
10004 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN register field. */
10005 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_LSB 0
10006 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN register field. */
10007 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_MSB 31
10008 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN register field. */
10009 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_WIDTH 32
10010 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN register field value. */
10011 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_SET_MSK 0xffffffff
10012 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN register field value. */
10013 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_CLR_MSK 0x00000000
10014 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN register field. */
10015 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_RESET 0x0
10016 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN field value from a register. */
10017 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_GET(value) (((value) & 0xffffffff) >> 0)
10018 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN register field value suitable for setting the register. */
10019 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_SET(value) (((value) << 0) & 0xffffffff)
10020 
10021 #ifndef __ASSEMBLY__
10022 /*
10023  * WARNING: The C register and register group struct declarations are provided for
10024  * convenience and illustrative purposes. They should, however, be used with
10025  * caution as the C language standard provides no guarantees about the alignment or
10026  * atomicity of device memory accesses. The recommended practice for writing
10027  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10028  * alt_write_word() functions.
10029  *
10030  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN.
10031  */
10032 struct ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_s
10033 {
10034  uint32_t STATALARMMIN : 32; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN */
10035 };
10036 
10037 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN. */
10038 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_s ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_t;
10039 #endif /* __ASSEMBLY__ */
10040 
10041 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN register. */
10042 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_RESET 0x00000000
10043 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN register from the beginning of the component. */
10044 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_OFST 0x2c
10045 
10046 /*
10047  * Register : Probe_MPU_main_Probe_StatAlarmMax
10048  *
10049  *
10050  * Register Layout
10051  *
10052  * Bits | Access | Reset | Description
10053  * :-------|:-------|:------|:---------------------------------------------------
10054  * [31:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX
10055  *
10056  */
10057 /*
10058  * Field : STATALARMMAX
10059  *
10060  * Register StatAlarmMax contains the maximum count value used in statistics alarm
10061  * comparisons.The number of bits is equal to twice the value set for parameter
10062  * wStatisticsCounter. When parameter statisticsCounterAlarm is set to False,
10063  * StatAlarmMax is reserved.
10064  *
10065  * Field Access Macros:
10066  *
10067  */
10068 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX register field. */
10069 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_LSB 0
10070 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX register field. */
10071 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_MSB 31
10072 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX register field. */
10073 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_WIDTH 32
10074 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX register field value. */
10075 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_SET_MSK 0xffffffff
10076 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX register field value. */
10077 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_CLR_MSK 0x00000000
10078 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX register field. */
10079 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_RESET 0x0
10080 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX field value from a register. */
10081 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_GET(value) (((value) & 0xffffffff) >> 0)
10082 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX register field value suitable for setting the register. */
10083 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_SET(value) (((value) << 0) & 0xffffffff)
10084 
10085 #ifndef __ASSEMBLY__
10086 /*
10087  * WARNING: The C register and register group struct declarations are provided for
10088  * convenience and illustrative purposes. They should, however, be used with
10089  * caution as the C language standard provides no guarantees about the alignment or
10090  * atomicity of device memory accesses. The recommended practice for writing
10091  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10092  * alt_write_word() functions.
10093  *
10094  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX.
10095  */
10096 struct ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_s
10097 {
10098  uint32_t STATALARMMAX : 32; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX */
10099 };
10100 
10101 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX. */
10102 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_s ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_t;
10103 #endif /* __ASSEMBLY__ */
10104 
10105 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX register. */
10106 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_RESET 0x00000000
10107 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX register from the beginning of the component. */
10108 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_OFST 0x30
10109 
10110 /*
10111  * Register : Probe_MPU_main_Probe_StatAlarmStatus
10112  *
10113  *
10114  * Register Layout
10115  *
10116  * Bits | Access | Reset | Description
10117  * :-------|:-------|:--------|:-----------------------------------------------------
10118  * [0] | R | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT
10119  * [31:1] | ??? | Unknown | *UNDEFINED*
10120  *
10121  */
10122 /*
10123  * Field : STATALARMSTATUS
10124  *
10125  * Register StatAlarmStatus is a read-only 1-bit register indicating that at least
10126  * one statistics counter has exceeded the programmed values for registers
10127  * StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values
10128  * stored in register MainCtl fields StatAlarmStatus and AlarmEn. When parameter
10129  * statisticsCounterAlarm is set to False, StatAlarmStatus is reserved.
10130  *
10131  * Field Access Macros:
10132  *
10133  */
10134 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT register field. */
10135 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_LSB 0
10136 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT register field. */
10137 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_MSB 0
10138 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT register field. */
10139 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_WIDTH 1
10140 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT register field value. */
10141 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_SET_MSK 0x00000001
10142 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT register field value. */
10143 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_CLR_MSK 0xfffffffe
10144 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT register field. */
10145 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_RESET 0x0
10146 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT field value from a register. */
10147 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_GET(value) (((value) & 0x00000001) >> 0)
10148 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT register field value suitable for setting the register. */
10149 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_SET(value) (((value) << 0) & 0x00000001)
10150 
10151 #ifndef __ASSEMBLY__
10152 /*
10153  * WARNING: The C register and register group struct declarations are provided for
10154  * convenience and illustrative purposes. They should, however, be used with
10155  * caution as the C language standard provides no guarantees about the alignment or
10156  * atomicity of device memory accesses. The recommended practice for writing
10157  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10158  * alt_write_word() functions.
10159  *
10160  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT.
10161  */
10162 struct ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_s
10163 {
10164  const uint32_t STATALARMSTATUS : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT */
10165  uint32_t : 31; /* *UNDEFINED* */
10166 };
10167 
10168 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT. */
10169 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_s ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_t;
10170 #endif /* __ASSEMBLY__ */
10171 
10172 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT register. */
10173 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_RESET 0x00000000
10174 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT register from the beginning of the component. */
10175 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_OFST 0x34
10176 
10177 /*
10178  * Register : Probe_MPU_main_Probe_StatAlarmClr
10179  *
10180  *
10181  * Register Layout
10182  *
10183  * Bits | Access | Reset | Description
10184  * :-------|:-------|:--------|:---------------------------------------------------
10185  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR
10186  * [31:1] | ??? | Unknown | *UNDEFINED*
10187  *
10188  */
10189 /*
10190  * Field : STATALARMCLR
10191  *
10192  * Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears
10193  * the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to
10194  * False, StatAlarmClr is reserved.NOTE The written value is not stored in
10195  * StatAlarmClr. A read always returns 0.
10196  *
10197  * Field Access Macros:
10198  *
10199  */
10200 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR register field. */
10201 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_LSB 0
10202 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR register field. */
10203 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_MSB 0
10204 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR register field. */
10205 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_WIDTH 1
10206 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR register field value. */
10207 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_SET_MSK 0x00000001
10208 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR register field value. */
10209 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_CLR_MSK 0xfffffffe
10210 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR register field. */
10211 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_RESET 0x0
10212 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR field value from a register. */
10213 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_GET(value) (((value) & 0x00000001) >> 0)
10214 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR register field value suitable for setting the register. */
10215 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_SET(value) (((value) << 0) & 0x00000001)
10216 
10217 #ifndef __ASSEMBLY__
10218 /*
10219  * WARNING: The C register and register group struct declarations are provided for
10220  * convenience and illustrative purposes. They should, however, be used with
10221  * caution as the C language standard provides no guarantees about the alignment or
10222  * atomicity of device memory accesses. The recommended practice for writing
10223  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10224  * alt_write_word() functions.
10225  *
10226  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR.
10227  */
10228 struct ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_s
10229 {
10230  uint32_t STATALARMCLR : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR */
10231  uint32_t : 31; /* *UNDEFINED* */
10232 };
10233 
10234 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR. */
10235 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_s ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_t;
10236 #endif /* __ASSEMBLY__ */
10237 
10238 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR register. */
10239 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_RESET 0x00000000
10240 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR register from the beginning of the component. */
10241 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_OFST 0x38
10242 
10243 /*
10244  * Register : Probe_MPU_main_Probe_StatAlarmEn
10245  *
10246  *
10247  * Register Layout
10248  *
10249  * Bits | Access | Reset | Description
10250  * :-------|:-------|:--------|:-------------------------------------------------
10251  * [0] | RW | 0x1 | ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN
10252  * [31:1] | ??? | Unknown | *UNDEFINED*
10253  *
10254  */
10255 /*
10256  * Field : STATALARMEN
10257  *
10258  * Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and
10259  * CtiTrigOut(1) signal interrupts.
10260  *
10261  * Field Access Macros:
10262  *
10263  */
10264 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN register field. */
10265 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_LSB 0
10266 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN register field. */
10267 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_MSB 0
10268 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN register field. */
10269 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_WIDTH 1
10270 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN register field value. */
10271 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_SET_MSK 0x00000001
10272 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN register field value. */
10273 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_CLR_MSK 0xfffffffe
10274 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN register field. */
10275 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_RESET 0x1
10276 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN field value from a register. */
10277 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_GET(value) (((value) & 0x00000001) >> 0)
10278 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN register field value suitable for setting the register. */
10279 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_SET(value) (((value) << 0) & 0x00000001)
10280 
10281 #ifndef __ASSEMBLY__
10282 /*
10283  * WARNING: The C register and register group struct declarations are provided for
10284  * convenience and illustrative purposes. They should, however, be used with
10285  * caution as the C language standard provides no guarantees about the alignment or
10286  * atomicity of device memory accesses. The recommended practice for writing
10287  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10288  * alt_write_word() functions.
10289  *
10290  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN.
10291  */
10292 struct ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_s
10293 {
10294  uint32_t STATALARMEN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN */
10295  uint32_t : 31; /* *UNDEFINED* */
10296 };
10297 
10298 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN. */
10299 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_s ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_t;
10300 #endif /* __ASSEMBLY__ */
10301 
10302 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN register. */
10303 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_RESET 0x00000001
10304 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN register from the beginning of the component. */
10305 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_OFST 0x3c
10306 
10307 /*
10308  * Register : Probe_MPU_main_Probe_Filters_0_RouteIdBase
10309  *
10310  *
10311  * Register Layout
10312  *
10313  * Bits | Access | Reset | Description
10314  * :--------|:-------|:--------|:---------------------------------------------------------------
10315  * [18:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE
10316  * [31:19] | ??? | Unknown | *UNDEFINED*
10317  *
10318  */
10319 /*
10320  * Field : FILTERS_0_ROUTEIDBASE
10321  *
10322  * Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to
10323  * filter packets.
10324  *
10325  * Field Access Macros:
10326  *
10327  */
10328 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
10329 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_LSB 0
10330 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
10331 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_MSB 18
10332 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
10333 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_WIDTH 19
10334 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field value. */
10335 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET_MSK 0x0007ffff
10336 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field value. */
10337 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_CLR_MSK 0xfff80000
10338 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field. */
10339 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_RESET 0x0
10340 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE field value from a register. */
10341 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
10342 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE register field value suitable for setting the register. */
10343 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
10344 
10345 #ifndef __ASSEMBLY__
10346 /*
10347  * WARNING: The C register and register group struct declarations are provided for
10348  * convenience and illustrative purposes. They should, however, be used with
10349  * caution as the C language standard provides no guarantees about the alignment or
10350  * atomicity of device memory accesses. The recommended practice for writing
10351  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10352  * alt_write_word() functions.
10353  *
10354  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE.
10355  */
10356 struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_s
10357 {
10358  uint32_t FILTERS_0_ROUTEIDBASE : 19; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE */
10359  uint32_t : 13; /* *UNDEFINED* */
10360 };
10361 
10362 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE. */
10363 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_s ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_t;
10364 #endif /* __ASSEMBLY__ */
10365 
10366 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE register. */
10367 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_RESET 0x00000000
10368 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE register from the beginning of the component. */
10369 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_OFST 0x44
10370 
10371 /*
10372  * Register : Probe_MPU_main_Probe_Filters_0_RouteIdMask
10373  *
10374  *
10375  * Register Layout
10376  *
10377  * Bits | Access | Reset | Description
10378  * :--------|:-------|:--------|:-------------------------------------------------------------
10379  * [18:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK
10380  * [31:19] | ??? | Unknown | *UNDEFINED*
10381  *
10382  */
10383 /*
10384  * Field : FILTERS_0_ROUTEIDMASK
10385  *
10386  * Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter
10387  * packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId &
10388  * RouteIdMask = RouteIdBase & RouteIdMask.
10389  *
10390  * Field Access Macros:
10391  *
10392  */
10393 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
10394 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_LSB 0
10395 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
10396 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_MSB 18
10397 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
10398 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_WIDTH 19
10399 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field value. */
10400 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET_MSK 0x0007ffff
10401 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field value. */
10402 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_CLR_MSK 0xfff80000
10403 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field. */
10404 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_RESET 0x0
10405 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK field value from a register. */
10406 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
10407 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK register field value suitable for setting the register. */
10408 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
10409 
10410 #ifndef __ASSEMBLY__
10411 /*
10412  * WARNING: The C register and register group struct declarations are provided for
10413  * convenience and illustrative purposes. They should, however, be used with
10414  * caution as the C language standard provides no guarantees about the alignment or
10415  * atomicity of device memory accesses. The recommended practice for writing
10416  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10417  * alt_write_word() functions.
10418  *
10419  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK.
10420  */
10421 struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_s
10422 {
10423  uint32_t FILTERS_0_ROUTEIDMASK : 19; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK */
10424  uint32_t : 13; /* *UNDEFINED* */
10425 };
10426 
10427 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK. */
10428 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_s ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_t;
10429 #endif /* __ASSEMBLY__ */
10430 
10431 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK register. */
10432 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_RESET 0x00000000
10433 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK register from the beginning of the component. */
10434 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_OFST 0x48
10435 
10436 /*
10437  * Register : Probe_MPU_main_Probe_Filters_0_AddrBase_Low
10438  *
10439  *
10440  * Register Layout
10441  *
10442  * Bits | Access | Reset | Description
10443  * :-------|:-------|:------|:-----------------------------------------------------------------
10444  * [31:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW
10445  *
10446  */
10447 /*
10448  * Field : FILTERS_0_ADDRBASE_LOW
10449  *
10450  * Address LSB register.
10451  *
10452  * Field Access Macros:
10453  *
10454  */
10455 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
10456 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_LSB 0
10457 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
10458 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_MSB 31
10459 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
10460 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_WIDTH 32
10461 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field value. */
10462 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET_MSK 0xffffffff
10463 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field value. */
10464 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_CLR_MSK 0x00000000
10465 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field. */
10466 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_RESET 0x0
10467 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW field value from a register. */
10468 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
10469 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW register field value suitable for setting the register. */
10470 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
10471 
10472 #ifndef __ASSEMBLY__
10473 /*
10474  * WARNING: The C register and register group struct declarations are provided for
10475  * convenience and illustrative purposes. They should, however, be used with
10476  * caution as the C language standard provides no guarantees about the alignment or
10477  * atomicity of device memory accesses. The recommended practice for writing
10478  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10479  * alt_write_word() functions.
10480  *
10481  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW.
10482  */
10483 struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_s
10484 {
10485  uint32_t FILTERS_0_ADDRBASE_LOW : 32; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW */
10486 };
10487 
10488 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW. */
10489 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_s ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_t;
10490 #endif /* __ASSEMBLY__ */
10491 
10492 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW register. */
10493 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_RESET 0x00000000
10494 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW register from the beginning of the component. */
10495 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_OFST 0x4c
10496 
10497 /*
10498  * Register : Probe_MPU_main_Probe_Filters_0_WindowSize
10499  *
10500  *
10501  * Register Layout
10502  *
10503  * Bits | Access | Reset | Description
10504  * :-------|:-------|:--------|:-------------------------------------------------------------
10505  * [5:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE
10506  * [31:6] | ??? | Unknown | *UNDEFINED*
10507  *
10508  */
10509 /*
10510  * Field : FILTERS_0_WINDOWSIZE
10511  *
10512  * Register WindowSize contains the encoded address mask used to filter packets.
10513  * The effective Mask value is equal to ~(2max(WindowSize, packet.Len) - 1). A
10514  * packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows
10515  * filteringof packets having an intersection with the AddrBase/WindowSize burst
10516  * aligned region, even if the region is smaller than the packet.
10517  *
10518  * Field Access Macros:
10519  *
10520  */
10521 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
10522 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_LSB 0
10523 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
10524 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_MSB 5
10525 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
10526 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_WIDTH 6
10527 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field value. */
10528 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET_MSK 0x0000003f
10529 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field value. */
10530 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_CLR_MSK 0xffffffc0
10531 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field. */
10532 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_RESET 0x0
10533 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE field value from a register. */
10534 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
10535 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE register field value suitable for setting the register. */
10536 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
10537 
10538 #ifndef __ASSEMBLY__
10539 /*
10540  * WARNING: The C register and register group struct declarations are provided for
10541  * convenience and illustrative purposes. They should, however, be used with
10542  * caution as the C language standard provides no guarantees about the alignment or
10543  * atomicity of device memory accesses. The recommended practice for writing
10544  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10545  * alt_write_word() functions.
10546  *
10547  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE.
10548  */
10549 struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_s
10550 {
10551  uint32_t FILTERS_0_WINDOWSIZE : 6; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE */
10552  uint32_t : 26; /* *UNDEFINED* */
10553 };
10554 
10555 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE. */
10556 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_s ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_t;
10557 #endif /* __ASSEMBLY__ */
10558 
10559 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE register. */
10560 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_RESET 0x00000000
10561 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE register from the beginning of the component. */
10562 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_OFST 0x54
10563 
10564 /*
10565  * Register : Probe_MPU_main_Probe_Filters_0_SecurityBase
10566  *
10567  *
10568  * Register Layout
10569  *
10570  * Bits | Access | Reset | Description
10571  * :-------|:-------|:--------|:-----------------------------------------------------------------
10572  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE
10573  * [31:3] | ??? | Unknown | *UNDEFINED*
10574  *
10575  */
10576 /*
10577  * Field : FILTERS_0_SECURITYBASE
10578  *
10579  * Register SecurityBase contains the security base used to filter packets.
10580  *
10581  * Field Access Macros:
10582  *
10583  */
10584 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
10585 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_LSB 0
10586 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
10587 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_MSB 2
10588 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
10589 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_WIDTH 3
10590 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field value. */
10591 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET_MSK 0x00000007
10592 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field value. */
10593 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_CLR_MSK 0xfffffff8
10594 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field. */
10595 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_RESET 0x0
10596 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE field value from a register. */
10597 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
10598 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE register field value suitable for setting the register. */
10599 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
10600 
10601 #ifndef __ASSEMBLY__
10602 /*
10603  * WARNING: The C register and register group struct declarations are provided for
10604  * convenience and illustrative purposes. They should, however, be used with
10605  * caution as the C language standard provides no guarantees about the alignment or
10606  * atomicity of device memory accesses. The recommended practice for writing
10607  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10608  * alt_write_word() functions.
10609  *
10610  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE.
10611  */
10612 struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_s
10613 {
10614  uint32_t FILTERS_0_SECURITYBASE : 3; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE */
10615  uint32_t : 29; /* *UNDEFINED* */
10616 };
10617 
10618 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE. */
10619 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_s ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_t;
10620 #endif /* __ASSEMBLY__ */
10621 
10622 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE register. */
10623 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_RESET 0x00000000
10624 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE register from the beginning of the component. */
10625 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_OFST 0x58
10626 
10627 /*
10628  * Register : Probe_MPU_main_Probe_Filters_0_SecurityMask
10629  *
10630  *
10631  * Register Layout
10632  *
10633  * Bits | Access | Reset | Description
10634  * :-------|:-------|:--------|:---------------------------------------------------------------
10635  * [2:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK
10636  * [31:3] | ??? | Unknown | *UNDEFINED*
10637  *
10638  */
10639 /*
10640  * Field : FILTERS_0_SECURITYMASK
10641  *
10642  * Register SecurityMask is contains the security mask used to filter packets. A
10643  * packet is a candidate when: packet.Security & SecurityMask = SecurityBase &
10644  * SecurityMasks.
10645  *
10646  * Field Access Macros:
10647  *
10648  */
10649 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
10650 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_LSB 0
10651 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
10652 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_MSB 2
10653 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
10654 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_WIDTH 3
10655 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field value. */
10656 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET_MSK 0x00000007
10657 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field value. */
10658 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_CLR_MSK 0xfffffff8
10659 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field. */
10660 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_RESET 0x0
10661 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK field value from a register. */
10662 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
10663 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK register field value suitable for setting the register. */
10664 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
10665 
10666 #ifndef __ASSEMBLY__
10667 /*
10668  * WARNING: The C register and register group struct declarations are provided for
10669  * convenience and illustrative purposes. They should, however, be used with
10670  * caution as the C language standard provides no guarantees about the alignment or
10671  * atomicity of device memory accesses. The recommended practice for writing
10672  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10673  * alt_write_word() functions.
10674  *
10675  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK.
10676  */
10677 struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_s
10678 {
10679  uint32_t FILTERS_0_SECURITYMASK : 3; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK */
10680  uint32_t : 29; /* *UNDEFINED* */
10681 };
10682 
10683 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK. */
10684 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_s ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_t;
10685 #endif /* __ASSEMBLY__ */
10686 
10687 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK register. */
10688 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_RESET 0x00000000
10689 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK register from the beginning of the component. */
10690 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_OFST 0x5c
10691 
10692 /*
10693  * Register : Probe_MPU_main_Probe_Filters_0_Opcode
10694  *
10695  * Packet Probe register Opcode is a 4-bit register that selects candidate packets
10696  * based on packet opcodes (0 disables the filter):
10697  *
10698  * Register Layout
10699  *
10700  * Bits | Access | Reset | Description
10701  * :-------|:-------|:--------|:----------------------------------------------
10702  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN
10703  * [1] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN
10704  * [2] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN
10705  * [3] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN
10706  * [31:4] | ??? | Unknown | *UNDEFINED*
10707  *
10708  */
10709 /*
10710  * Field : RDEN
10711  *
10712  * Selects RD packets.
10713  *
10714  * Field Access Macros:
10715  *
10716  */
10717 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN register field. */
10718 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_LSB 0
10719 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN register field. */
10720 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_MSB 0
10721 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN register field. */
10722 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_WIDTH 1
10723 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN register field value. */
10724 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_SET_MSK 0x00000001
10725 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN register field value. */
10726 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_CLR_MSK 0xfffffffe
10727 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN register field. */
10728 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_RESET 0x0
10729 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN field value from a register. */
10730 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
10731 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN register field value suitable for setting the register. */
10732 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
10733 
10734 /*
10735  * Field : WREN
10736  *
10737  * Selects WR packets.
10738  *
10739  * Field Access Macros:
10740  *
10741  */
10742 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN register field. */
10743 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_LSB 1
10744 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN register field. */
10745 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_MSB 1
10746 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN register field. */
10747 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_WIDTH 1
10748 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN register field value. */
10749 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_SET_MSK 0x00000002
10750 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN register field value. */
10751 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_CLR_MSK 0xfffffffd
10752 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN register field. */
10753 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_RESET 0x0
10754 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN field value from a register. */
10755 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
10756 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN register field value suitable for setting the register. */
10757 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
10758 
10759 /*
10760  * Field : LOCKEN
10761  *
10762  * Selects RDX-WR, RDL, WRC and Linked sequence.
10763  *
10764  * Field Access Macros:
10765  *
10766  */
10767 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN register field. */
10768 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_LSB 2
10769 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN register field. */
10770 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_MSB 2
10771 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN register field. */
10772 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_WIDTH 1
10773 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN register field value. */
10774 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_SET_MSK 0x00000004
10775 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN register field value. */
10776 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
10777 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN register field. */
10778 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_RESET 0x0
10779 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN field value from a register. */
10780 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
10781 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN register field value suitable for setting the register. */
10782 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
10783 
10784 /*
10785  * Field : URGEN
10786  *
10787  * Selects URG packets (urgency).
10788  *
10789  * Field Access Macros:
10790  *
10791  */
10792 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN register field. */
10793 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_LSB 3
10794 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN register field. */
10795 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_MSB 3
10796 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN register field. */
10797 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_WIDTH 1
10798 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN register field value. */
10799 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_SET_MSK 0x00000008
10800 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN register field value. */
10801 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_CLR_MSK 0xfffffff7
10802 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN register field. */
10803 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_RESET 0x0
10804 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN field value from a register. */
10805 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
10806 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN register field value suitable for setting the register. */
10807 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
10808 
10809 #ifndef __ASSEMBLY__
10810 /*
10811  * WARNING: The C register and register group struct declarations are provided for
10812  * convenience and illustrative purposes. They should, however, be used with
10813  * caution as the C language standard provides no guarantees about the alignment or
10814  * atomicity of device memory accesses. The recommended practice for writing
10815  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10816  * alt_write_word() functions.
10817  *
10818  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE.
10819  */
10820 struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_s
10821 {
10822  uint32_t RDEN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN */
10823  uint32_t WREN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN */
10824  uint32_t LOCKEN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN */
10825  uint32_t URGEN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN */
10826  uint32_t : 28; /* *UNDEFINED* */
10827 };
10828 
10829 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE. */
10830 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_s ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_t;
10831 #endif /* __ASSEMBLY__ */
10832 
10833 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE register. */
10834 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RESET 0x00000000
10835 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE register from the beginning of the component. */
10836 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_OFST 0x60
10837 
10838 /*
10839  * Register : Probe_MPU_main_Probe_Filters_0_Status
10840  *
10841  * Register Status is 2-bit register that selects candidate packets based on packet
10842  * status.
10843  *
10844  * Register Layout
10845  *
10846  * Bits | Access | Reset | Description
10847  * :-------|:-------|:--------|:-------------------------------------------
10848  * [0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN
10849  * [1] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN
10850  * [31:2] | ??? | Unknown | *UNDEFINED*
10851  *
10852  */
10853 /*
10854  * Field : REQEN
10855  *
10856  * Selects REQ status packets.
10857  *
10858  * Field Access Macros:
10859  *
10860  */
10861 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN register field. */
10862 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_LSB 0
10863 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN register field. */
10864 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_MSB 0
10865 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN register field. */
10866 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_WIDTH 1
10867 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN register field value. */
10868 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_SET_MSK 0x00000001
10869 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN register field value. */
10870 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_CLR_MSK 0xfffffffe
10871 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN register field. */
10872 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_RESET 0x0
10873 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN field value from a register. */
10874 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
10875 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN register field value suitable for setting the register. */
10876 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
10877 
10878 /*
10879  * Field : RSPEN
10880  *
10881  * Selects RSP and FAIL-CONT status packets.
10882  *
10883  * Field Access Macros:
10884  *
10885  */
10886 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN register field. */
10887 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_LSB 1
10888 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN register field. */
10889 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_MSB 1
10890 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN register field. */
10891 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_WIDTH 1
10892 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN register field value. */
10893 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_SET_MSK 0x00000002
10894 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN register field value. */
10895 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_CLR_MSK 0xfffffffd
10896 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN register field. */
10897 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_RESET 0x0
10898 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN field value from a register. */
10899 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
10900 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN register field value suitable for setting the register. */
10901 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
10902 
10903 #ifndef __ASSEMBLY__
10904 /*
10905  * WARNING: The C register and register group struct declarations are provided for
10906  * convenience and illustrative purposes. They should, however, be used with
10907  * caution as the C language standard provides no guarantees about the alignment or
10908  * atomicity of device memory accesses. The recommended practice for writing
10909  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10910  * alt_write_word() functions.
10911  *
10912  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT.
10913  */
10914 struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_s
10915 {
10916  uint32_t REQEN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN */
10917  uint32_t RSPEN : 1; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN */
10918  uint32_t : 30; /* *UNDEFINED* */
10919 };
10920 
10921 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT. */
10922 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_s ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_t;
10923 #endif /* __ASSEMBLY__ */
10924 
10925 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT register. */
10926 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RESET 0x00000000
10927 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT register from the beginning of the component. */
10928 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_OFST 0x64
10929 
10930 /*
10931  * Register : Probe_MPU_main_Probe_Filters_0_Length
10932  *
10933  *
10934  * Register Layout
10935  *
10936  * Bits | Access | Reset | Description
10937  * :-------|:-------|:--------|:-----------------------------------------------
10938  * [3:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN
10939  * [31:4] | ??? | Unknown | *UNDEFINED*
10940  *
10941  */
10942 /*
10943  * Field : FILTERS_0_LENGTH
10944  *
10945  * Register Length is 4-bit register that selects candidate packets if their number
10946  * of bytes is less than or equal to 2**Length.
10947  *
10948  * Field Access Macros:
10949  *
10950  */
10951 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN register field. */
10952 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_LSB 0
10953 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN register field. */
10954 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_MSB 3
10955 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN register field. */
10956 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_WIDTH 4
10957 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN register field value. */
10958 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_SET_MSK 0x0000000f
10959 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN register field value. */
10960 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_CLR_MSK 0xfffffff0
10961 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN register field. */
10962 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_RESET 0x0
10963 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN field value from a register. */
10964 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_GET(value) (((value) & 0x0000000f) >> 0)
10965 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN register field value suitable for setting the register. */
10966 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_SET(value) (((value) << 0) & 0x0000000f)
10967 
10968 #ifndef __ASSEMBLY__
10969 /*
10970  * WARNING: The C register and register group struct declarations are provided for
10971  * convenience and illustrative purposes. They should, however, be used with
10972  * caution as the C language standard provides no guarantees about the alignment or
10973  * atomicity of device memory accesses. The recommended practice for writing
10974  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10975  * alt_write_word() functions.
10976  *
10977  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN.
10978  */
10979 struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_s
10980 {
10981  uint32_t FILTERS_0_LENGTH : 4; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN */
10982  uint32_t : 28; /* *UNDEFINED* */
10983 };
10984 
10985 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN. */
10986 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_s ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_t;
10987 #endif /* __ASSEMBLY__ */
10988 
10989 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN register. */
10990 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_RESET 0x00000000
10991 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN register from the beginning of the component. */
10992 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_OFST 0x68
10993 
10994 /*
10995  * Register : Probe_MPU_main_Probe_Filters_0_Urgency
10996  *
10997  *
10998  * Register Layout
10999  *
11000  * Bits | Access | Reset | Description
11001  * :-------|:-------|:--------|:-------------------------------------------------------
11002  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY
11003  * [31:2] | ??? | Unknown | *UNDEFINED*
11004  *
11005  */
11006 /*
11007  * Field : FILTERS_0_URGENCY
11008  *
11009  * Register Urgency contains the minimum urgency level used to filter packets. A
11010  * packet is a candidate when its socket urgency is greater than or equal to the
11011  * urgency specified in the register.
11012  *
11013  * Field Access Macros:
11014  *
11015  */
11016 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
11017 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_LSB 0
11018 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
11019 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_MSB 1
11020 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
11021 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_WIDTH 2
11022 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field value. */
11023 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_SET_MSK 0x00000003
11024 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field value. */
11025 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_CLR_MSK 0xfffffffc
11026 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field. */
11027 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_RESET 0x0
11028 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY field value from a register. */
11029 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
11030 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY register field value suitable for setting the register. */
11031 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_SET(value) (((value) << 0) & 0x00000003)
11032 
11033 #ifndef __ASSEMBLY__
11034 /*
11035  * WARNING: The C register and register group struct declarations are provided for
11036  * convenience and illustrative purposes. They should, however, be used with
11037  * caution as the C language standard provides no guarantees about the alignment or
11038  * atomicity of device memory accesses. The recommended practice for writing
11039  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11040  * alt_write_word() functions.
11041  *
11042  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY.
11043  */
11044 struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_s
11045 {
11046  uint32_t FILTERS_0_URGENCY : 2; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY */
11047  uint32_t : 30; /* *UNDEFINED* */
11048 };
11049 
11050 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY. */
11051 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_s ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_t;
11052 #endif /* __ASSEMBLY__ */
11053 
11054 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY register. */
11055 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_RESET 0x00000000
11056 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY register from the beginning of the component. */
11057 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_OFST 0x6c
11058 
11059 /*
11060  * Register : Probe_MPU_main_Probe_Counters_0_Src
11061  *
11062  * Register CntSrc indicates the event source used to increment the counter.
11063  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
11064  * Filter) are equivalent to OFF.
11065  *
11066  * Register Layout
11067  *
11068  * Bits | Access | Reset | Description
11069  * :-------|:-------|:--------|:----------------------------------------------
11070  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT
11071  * [31:5] | ??? | Unknown | *UNDEFINED*
11072  *
11073  */
11074 /*
11075  * Field : INTEVENT
11076  *
11077  * Internal packet event
11078  *
11079  * Field Access Macros:
11080  *
11081  */
11082 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT register field. */
11083 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_LSB 0
11084 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT register field. */
11085 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_MSB 4
11086 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT register field. */
11087 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_WIDTH 5
11088 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT register field value. */
11089 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_SET_MSK 0x0000001f
11090 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT register field value. */
11091 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_CLR_MSK 0xffffffe0
11092 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT register field. */
11093 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_RESET 0x0
11094 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT field value from a register. */
11095 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
11096 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT register field value suitable for setting the register. */
11097 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
11098 
11099 #ifndef __ASSEMBLY__
11100 /*
11101  * WARNING: The C register and register group struct declarations are provided for
11102  * convenience and illustrative purposes. They should, however, be used with
11103  * caution as the C language standard provides no guarantees about the alignment or
11104  * atomicity of device memory accesses. The recommended practice for writing
11105  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11106  * alt_write_word() functions.
11107  *
11108  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC.
11109  */
11110 struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_s
11111 {
11112  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT */
11113  uint32_t : 27; /* *UNDEFINED* */
11114 };
11115 
11116 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC. */
11117 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_s ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_t;
11118 #endif /* __ASSEMBLY__ */
11119 
11120 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC register. */
11121 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_RESET 0x00000000
11122 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC register from the beginning of the component. */
11123 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_OFST 0x138
11124 
11125 /*
11126  * Register : Probe_MPU_main_Probe_Counters_0_AlarmMode
11127  *
11128  *
11129  * Register Layout
11130  *
11131  * Bits | Access | Reset | Description
11132  * :-------|:-------|:--------|:-----------------------------------------------------------
11133  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD
11134  * [31:2] | ??? | Unknown | *UNDEFINED*
11135  *
11136  */
11137 /*
11138  * Field : COUNTERS_0_ALARMMODE
11139  *
11140  * Register AlarmMode is a 2-bit register that is present when parameter
11141  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
11142  * behavior of the counter.
11143  *
11144  * Field Access Macros:
11145  *
11146  */
11147 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
11148 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_LSB 0
11149 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
11150 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_MSB 1
11151 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
11152 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_WIDTH 2
11153 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field value. */
11154 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET_MSK 0x00000003
11155 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field value. */
11156 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_CLR_MSK 0xfffffffc
11157 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field. */
11158 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_RESET 0x0
11159 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD field value from a register. */
11160 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
11161 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD register field value suitable for setting the register. */
11162 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
11163 
11164 #ifndef __ASSEMBLY__
11165 /*
11166  * WARNING: The C register and register group struct declarations are provided for
11167  * convenience and illustrative purposes. They should, however, be used with
11168  * caution as the C language standard provides no guarantees about the alignment or
11169  * atomicity of device memory accesses. The recommended practice for writing
11170  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11171  * alt_write_word() functions.
11172  *
11173  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD.
11174  */
11175 struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_s
11176 {
11177  uint32_t COUNTERS_0_ALARMMODE : 2; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD */
11178  uint32_t : 30; /* *UNDEFINED* */
11179 };
11180 
11181 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD. */
11182 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_s ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_t;
11183 #endif /* __ASSEMBLY__ */
11184 
11185 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD register. */
11186 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_RESET 0x00000000
11187 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD register from the beginning of the component. */
11188 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_OFST 0x13c
11189 
11190 /*
11191  * Register : Probe_MPU_main_Probe_Counters_0_Val
11192  *
11193  *
11194  * Register Layout
11195  *
11196  * Bits | Access | Reset | Description
11197  * :--------|:-------|:--------|:-------------------------------------------------
11198  * [15:0] | R | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL
11199  * [31:16] | ??? | Unknown | *UNDEFINED*
11200  *
11201  */
11202 /*
11203  * Field : COUNTERS_0_VAL
11204  *
11205  * Register Val is a read-only register that is always present. The register
11206  * containsthe statistics counter value either pending StatAlarm output, or when
11207  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
11208  *
11209  * Field Access Macros:
11210  *
11211  */
11212 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field. */
11213 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_LSB 0
11214 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field. */
11215 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_MSB 15
11216 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field. */
11217 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_WIDTH 16
11218 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field value. */
11219 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET_MSK 0x0000ffff
11220 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field value. */
11221 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_CLR_MSK 0xffff0000
11222 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field. */
11223 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_RESET 0x0
11224 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL field value from a register. */
11225 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
11226 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field value suitable for setting the register. */
11227 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET(value) (((value) << 0) & 0x0000ffff)
11228 
11229 #ifndef __ASSEMBLY__
11230 /*
11231  * WARNING: The C register and register group struct declarations are provided for
11232  * convenience and illustrative purposes. They should, however, be used with
11233  * caution as the C language standard provides no guarantees about the alignment or
11234  * atomicity of device memory accesses. The recommended practice for writing
11235  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11236  * alt_write_word() functions.
11237  *
11238  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL.
11239  */
11240 struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_s
11241 {
11242  const uint32_t COUNTERS_0_VAL : 16; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL */
11243  uint32_t : 16; /* *UNDEFINED* */
11244 };
11245 
11246 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL. */
11247 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_s ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_t;
11248 #endif /* __ASSEMBLY__ */
11249 
11250 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL register. */
11251 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_RESET 0x00000000
11252 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL register from the beginning of the component. */
11253 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_OFST 0x140
11254 
11255 /*
11256  * Register : Probe_MPU_main_Probe_Counters_1_Src
11257  *
11258  * Register CntSrc indicates the event source used to increment the counter.
11259  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
11260  * Filter) are equivalent to OFF.
11261  *
11262  * Register Layout
11263  *
11264  * Bits | Access | Reset | Description
11265  * :-------|:-------|:--------|:----------------------------------------------
11266  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT
11267  * [31:5] | ??? | Unknown | *UNDEFINED*
11268  *
11269  */
11270 /*
11271  * Field : INTEVENT
11272  *
11273  * Internal packet event
11274  *
11275  * Field Access Macros:
11276  *
11277  */
11278 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT register field. */
11279 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_LSB 0
11280 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT register field. */
11281 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_MSB 4
11282 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT register field. */
11283 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_WIDTH 5
11284 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT register field value. */
11285 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_SET_MSK 0x0000001f
11286 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT register field value. */
11287 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_CLR_MSK 0xffffffe0
11288 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT register field. */
11289 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_RESET 0x0
11290 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT field value from a register. */
11291 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
11292 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT register field value suitable for setting the register. */
11293 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
11294 
11295 #ifndef __ASSEMBLY__
11296 /*
11297  * WARNING: The C register and register group struct declarations are provided for
11298  * convenience and illustrative purposes. They should, however, be used with
11299  * caution as the C language standard provides no guarantees about the alignment or
11300  * atomicity of device memory accesses. The recommended practice for writing
11301  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11302  * alt_write_word() functions.
11303  *
11304  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC.
11305  */
11306 struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_s
11307 {
11308  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT */
11309  uint32_t : 27; /* *UNDEFINED* */
11310 };
11311 
11312 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC. */
11313 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_s ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_t;
11314 #endif /* __ASSEMBLY__ */
11315 
11316 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC register. */
11317 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_RESET 0x00000000
11318 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC register from the beginning of the component. */
11319 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_OFST 0x14c
11320 
11321 /*
11322  * Register : Probe_MPU_main_Probe_Counters_1_AlarmMode
11323  *
11324  *
11325  * Register Layout
11326  *
11327  * Bits | Access | Reset | Description
11328  * :-------|:-------|:--------|:-----------------------------------------------------------
11329  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD
11330  * [31:2] | ??? | Unknown | *UNDEFINED*
11331  *
11332  */
11333 /*
11334  * Field : COUNTERS_1_ALARMMODE
11335  *
11336  * Register AlarmMode is a 2-bit register that is present when parameter
11337  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
11338  * behavior of the counter.
11339  *
11340  * Field Access Macros:
11341  *
11342  */
11343 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
11344 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_LSB 0
11345 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
11346 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_MSB 1
11347 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
11348 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_WIDTH 2
11349 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field value. */
11350 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET_MSK 0x00000003
11351 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field value. */
11352 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_CLR_MSK 0xfffffffc
11353 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field. */
11354 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_RESET 0x0
11355 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD field value from a register. */
11356 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
11357 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD register field value suitable for setting the register. */
11358 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
11359 
11360 #ifndef __ASSEMBLY__
11361 /*
11362  * WARNING: The C register and register group struct declarations are provided for
11363  * convenience and illustrative purposes. They should, however, be used with
11364  * caution as the C language standard provides no guarantees about the alignment or
11365  * atomicity of device memory accesses. The recommended practice for writing
11366  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11367  * alt_write_word() functions.
11368  *
11369  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD.
11370  */
11371 struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_s
11372 {
11373  uint32_t COUNTERS_1_ALARMMODE : 2; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD */
11374  uint32_t : 30; /* *UNDEFINED* */
11375 };
11376 
11377 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD. */
11378 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_s ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_t;
11379 #endif /* __ASSEMBLY__ */
11380 
11381 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD register. */
11382 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_RESET 0x00000000
11383 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD register from the beginning of the component. */
11384 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_OFST 0x150
11385 
11386 /*
11387  * Register : Probe_MPU_main_Probe_Counters_1_Val
11388  *
11389  *
11390  * Register Layout
11391  *
11392  * Bits | Access | Reset | Description
11393  * :--------|:-------|:--------|:-------------------------------------------------
11394  * [15:0] | R | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL
11395  * [31:16] | ??? | Unknown | *UNDEFINED*
11396  *
11397  */
11398 /*
11399  * Field : COUNTERS_1_VAL
11400  *
11401  * Register Val is a read-only register that is always present. The register
11402  * containsthe statistics counter value either pending StatAlarm output, or when
11403  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
11404  *
11405  * Field Access Macros:
11406  *
11407  */
11408 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field. */
11409 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_LSB 0
11410 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field. */
11411 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_MSB 15
11412 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field. */
11413 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_WIDTH 16
11414 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field value. */
11415 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_SET_MSK 0x0000ffff
11416 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field value. */
11417 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_CLR_MSK 0xffff0000
11418 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field. */
11419 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_RESET 0x0
11420 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL field value from a register. */
11421 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
11422 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL register field value suitable for setting the register. */
11423 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_SET(value) (((value) << 0) & 0x0000ffff)
11424 
11425 #ifndef __ASSEMBLY__
11426 /*
11427  * WARNING: The C register and register group struct declarations are provided for
11428  * convenience and illustrative purposes. They should, however, be used with
11429  * caution as the C language standard provides no guarantees about the alignment or
11430  * atomicity of device memory accesses. The recommended practice for writing
11431  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11432  * alt_write_word() functions.
11433  *
11434  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL.
11435  */
11436 struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_s
11437 {
11438  const uint32_t COUNTERS_1_VAL : 16; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL */
11439  uint32_t : 16; /* *UNDEFINED* */
11440 };
11441 
11442 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL. */
11443 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_s ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_t;
11444 #endif /* __ASSEMBLY__ */
11445 
11446 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL register. */
11447 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_RESET 0x00000000
11448 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL register from the beginning of the component. */
11449 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_OFST 0x154
11450 
11451 /*
11452  * Register : Probe_MPU_main_Probe_Counters_2_Src
11453  *
11454  * Register CntSrc indicates the event source used to increment the counter.
11455  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
11456  * Filter) are equivalent to OFF.
11457  *
11458  * Register Layout
11459  *
11460  * Bits | Access | Reset | Description
11461  * :-------|:-------|:--------|:----------------------------------------------
11462  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT
11463  * [31:5] | ??? | Unknown | *UNDEFINED*
11464  *
11465  */
11466 /*
11467  * Field : INTEVENT
11468  *
11469  * Internal packet event
11470  *
11471  * Field Access Macros:
11472  *
11473  */
11474 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT register field. */
11475 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_LSB 0
11476 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT register field. */
11477 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_MSB 4
11478 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT register field. */
11479 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_WIDTH 5
11480 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT register field value. */
11481 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_SET_MSK 0x0000001f
11482 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT register field value. */
11483 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_CLR_MSK 0xffffffe0
11484 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT register field. */
11485 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_RESET 0x0
11486 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT field value from a register. */
11487 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
11488 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT register field value suitable for setting the register. */
11489 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
11490 
11491 #ifndef __ASSEMBLY__
11492 /*
11493  * WARNING: The C register and register group struct declarations are provided for
11494  * convenience and illustrative purposes. They should, however, be used with
11495  * caution as the C language standard provides no guarantees about the alignment or
11496  * atomicity of device memory accesses. The recommended practice for writing
11497  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11498  * alt_write_word() functions.
11499  *
11500  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC.
11501  */
11502 struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_s
11503 {
11504  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT */
11505  uint32_t : 27; /* *UNDEFINED* */
11506 };
11507 
11508 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC. */
11509 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_s ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_t;
11510 #endif /* __ASSEMBLY__ */
11511 
11512 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC register. */
11513 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_RESET 0x00000000
11514 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC register from the beginning of the component. */
11515 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_OFST 0x160
11516 
11517 /*
11518  * Register : Probe_MPU_main_Probe_Counters_2_AlarmMode
11519  *
11520  *
11521  * Register Layout
11522  *
11523  * Bits | Access | Reset | Description
11524  * :-------|:-------|:--------|:-----------------------------------------------------------
11525  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD
11526  * [31:2] | ??? | Unknown | *UNDEFINED*
11527  *
11528  */
11529 /*
11530  * Field : COUNTERS_2_ALARMMODE
11531  *
11532  * Register AlarmMode is a 2-bit register that is present when parameter
11533  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
11534  * behavior of the counter.
11535  *
11536  * Field Access Macros:
11537  *
11538  */
11539 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field. */
11540 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_LSB 0
11541 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field. */
11542 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_MSB 1
11543 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field. */
11544 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_WIDTH 2
11545 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field value. */
11546 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_SET_MSK 0x00000003
11547 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field value. */
11548 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_CLR_MSK 0xfffffffc
11549 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field. */
11550 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_RESET 0x0
11551 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD field value from a register. */
11552 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
11553 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD register field value suitable for setting the register. */
11554 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
11555 
11556 #ifndef __ASSEMBLY__
11557 /*
11558  * WARNING: The C register and register group struct declarations are provided for
11559  * convenience and illustrative purposes. They should, however, be used with
11560  * caution as the C language standard provides no guarantees about the alignment or
11561  * atomicity of device memory accesses. The recommended practice for writing
11562  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11563  * alt_write_word() functions.
11564  *
11565  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD.
11566  */
11567 struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_s
11568 {
11569  uint32_t COUNTERS_2_ALARMMODE : 2; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD */
11570  uint32_t : 30; /* *UNDEFINED* */
11571 };
11572 
11573 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD. */
11574 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_s ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_t;
11575 #endif /* __ASSEMBLY__ */
11576 
11577 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD register. */
11578 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_RESET 0x00000000
11579 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD register from the beginning of the component. */
11580 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_OFST 0x164
11581 
11582 /*
11583  * Register : Probe_MPU_main_Probe_Counters_2_Val
11584  *
11585  *
11586  * Register Layout
11587  *
11588  * Bits | Access | Reset | Description
11589  * :--------|:-------|:--------|:-------------------------------------------------
11590  * [15:0] | R | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL
11591  * [31:16] | ??? | Unknown | *UNDEFINED*
11592  *
11593  */
11594 /*
11595  * Field : COUNTERS_2_VAL
11596  *
11597  * Register Val is a read-only register that is always present. The register
11598  * containsthe statistics counter value either pending StatAlarm output, or when
11599  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
11600  *
11601  * Field Access Macros:
11602  *
11603  */
11604 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field. */
11605 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_LSB 0
11606 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field. */
11607 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_MSB 15
11608 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field. */
11609 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_WIDTH 16
11610 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field value. */
11611 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_SET_MSK 0x0000ffff
11612 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field value. */
11613 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_CLR_MSK 0xffff0000
11614 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field. */
11615 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_RESET 0x0
11616 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL field value from a register. */
11617 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
11618 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL register field value suitable for setting the register. */
11619 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_SET(value) (((value) << 0) & 0x0000ffff)
11620 
11621 #ifndef __ASSEMBLY__
11622 /*
11623  * WARNING: The C register and register group struct declarations are provided for
11624  * convenience and illustrative purposes. They should, however, be used with
11625  * caution as the C language standard provides no guarantees about the alignment or
11626  * atomicity of device memory accesses. The recommended practice for writing
11627  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11628  * alt_write_word() functions.
11629  *
11630  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL.
11631  */
11632 struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_s
11633 {
11634  const uint32_t COUNTERS_2_VAL : 16; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL */
11635  uint32_t : 16; /* *UNDEFINED* */
11636 };
11637 
11638 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL. */
11639 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_s ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_t;
11640 #endif /* __ASSEMBLY__ */
11641 
11642 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL register. */
11643 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_RESET 0x00000000
11644 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL register from the beginning of the component. */
11645 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_OFST 0x168
11646 
11647 /*
11648  * Register : Probe_MPU_main_Probe_Counters_3_Src
11649  *
11650  * Register CntSrc indicates the event source used to increment the counter.
11651  * Unassigned values (non-existing Press level or ExtEvent index, or unimplemented
11652  * Filter) are equivalent to OFF.
11653  *
11654  * Register Layout
11655  *
11656  * Bits | Access | Reset | Description
11657  * :-------|:-------|:--------|:----------------------------------------------
11658  * [4:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT
11659  * [31:5] | ??? | Unknown | *UNDEFINED*
11660  *
11661  */
11662 /*
11663  * Field : INTEVENT
11664  *
11665  * Internal packet event
11666  *
11667  * Field Access Macros:
11668  *
11669  */
11670 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT register field. */
11671 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_LSB 0
11672 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT register field. */
11673 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_MSB 4
11674 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT register field. */
11675 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_WIDTH 5
11676 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT register field value. */
11677 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_SET_MSK 0x0000001f
11678 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT register field value. */
11679 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_CLR_MSK 0xffffffe0
11680 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT register field. */
11681 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_RESET 0x0
11682 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT field value from a register. */
11683 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
11684 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT register field value suitable for setting the register. */
11685 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
11686 
11687 #ifndef __ASSEMBLY__
11688 /*
11689  * WARNING: The C register and register group struct declarations are provided for
11690  * convenience and illustrative purposes. They should, however, be used with
11691  * caution as the C language standard provides no guarantees about the alignment or
11692  * atomicity of device memory accesses. The recommended practice for writing
11693  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11694  * alt_write_word() functions.
11695  *
11696  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC.
11697  */
11698 struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_s
11699 {
11700  uint32_t INTEVENT : 5; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT */
11701  uint32_t : 27; /* *UNDEFINED* */
11702 };
11703 
11704 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC. */
11705 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_s ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_t;
11706 #endif /* __ASSEMBLY__ */
11707 
11708 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC register. */
11709 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_RESET 0x00000000
11710 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC register from the beginning of the component. */
11711 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_OFST 0x174
11712 
11713 /*
11714  * Register : Probe_MPU_main_Probe_Counters_3_AlarmMode
11715  *
11716  *
11717  * Register Layout
11718  *
11719  * Bits | Access | Reset | Description
11720  * :-------|:-------|:--------|:-----------------------------------------------------------
11721  * [1:0] | RW | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD
11722  * [31:2] | ??? | Unknown | *UNDEFINED*
11723  *
11724  */
11725 /*
11726  * Field : COUNTERS_3_ALARMMODE
11727  *
11728  * Register AlarmMode is a 2-bit register that is present when parameter
11729  * statisticsCounterAlarm is set to True. The register defines the statistics-alarm
11730  * behavior of the counter.
11731  *
11732  * Field Access Macros:
11733  *
11734  */
11735 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field. */
11736 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_LSB 0
11737 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field. */
11738 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_MSB 1
11739 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field. */
11740 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_WIDTH 2
11741 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field value. */
11742 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_SET_MSK 0x00000003
11743 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field value. */
11744 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_CLR_MSK 0xfffffffc
11745 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field. */
11746 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_RESET 0x0
11747 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD field value from a register. */
11748 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
11749 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD register field value suitable for setting the register. */
11750 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
11751 
11752 #ifndef __ASSEMBLY__
11753 /*
11754  * WARNING: The C register and register group struct declarations are provided for
11755  * convenience and illustrative purposes. They should, however, be used with
11756  * caution as the C language standard provides no guarantees about the alignment or
11757  * atomicity of device memory accesses. The recommended practice for writing
11758  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11759  * alt_write_word() functions.
11760  *
11761  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD.
11762  */
11763 struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_s
11764 {
11765  uint32_t COUNTERS_3_ALARMMODE : 2; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD */
11766  uint32_t : 30; /* *UNDEFINED* */
11767 };
11768 
11769 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD. */
11770 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_s ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_t;
11771 #endif /* __ASSEMBLY__ */
11772 
11773 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD register. */
11774 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_RESET 0x00000000
11775 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD register from the beginning of the component. */
11776 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_OFST 0x178
11777 
11778 /*
11779  * Register : Probe_MPU_main_Probe_Counters_3_Val
11780  *
11781  *
11782  * Register Layout
11783  *
11784  * Bits | Access | Reset | Description
11785  * :--------|:-------|:--------|:-------------------------------------------------
11786  * [15:0] | R | 0x0 | ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL
11787  * [31:16] | ??? | Unknown | *UNDEFINED*
11788  *
11789  */
11790 /*
11791  * Field : COUNTERS_3_VAL
11792  *
11793  * Register Val is a read-only register that is always present. The register
11794  * containsthe statistics counter value either pending StatAlarm output, or when
11795  * statisticscollection is suspended subsequent to triggers or signal statSuspend.
11796  *
11797  * Field Access Macros:
11798  *
11799  */
11800 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field. */
11801 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_LSB 0
11802 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field. */
11803 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_MSB 15
11804 /* The width in bits of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field. */
11805 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_WIDTH 16
11806 /* The mask used to set the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field value. */
11807 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_SET_MSK 0x0000ffff
11808 /* The mask used to clear the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field value. */
11809 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_CLR_MSK 0xffff0000
11810 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field. */
11811 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_RESET 0x0
11812 /* Extracts the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL field value from a register. */
11813 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
11814 /* Produces a ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL register field value suitable for setting the register. */
11815 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_SET(value) (((value) << 0) & 0x0000ffff)
11816 
11817 #ifndef __ASSEMBLY__
11818 /*
11819  * WARNING: The C register and register group struct declarations are provided for
11820  * convenience and illustrative purposes. They should, however, be used with
11821  * caution as the C language standard provides no guarantees about the alignment or
11822  * atomicity of device memory accesses. The recommended practice for writing
11823  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11824  * alt_write_word() functions.
11825  *
11826  * The struct declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL.
11827  */
11828 struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_s
11829 {
11830  const uint32_t COUNTERS_3_VAL : 16; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL */
11831  uint32_t : 16; /* *UNDEFINED* */
11832 };
11833 
11834 /* The typedef declaration for register ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL. */
11835 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_s ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_t;
11836 #endif /* __ASSEMBLY__ */
11837 
11838 /* The reset value of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL register. */
11839 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_RESET 0x00000000
11840 /* The byte offset of the ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL register from the beginning of the component. */
11841 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_OFST 0x17c
11842 
11843 #ifndef __ASSEMBLY__
11844 /*
11845  * WARNING: The C register and register group struct declarations are provided for
11846  * convenience and illustrative purposes. They should, however, be used with
11847  * caution as the C language standard provides no guarantees about the alignment or
11848  * atomicity of device memory accesses. The recommended practice for writing
11849  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11850  * alt_write_word() functions.
11851  *
11852  * The struct declaration for register group ALT_NOC_MPU_PRB_MPU_MAIN_PRB.
11853  */
11854 struct ALT_NOC_MPU_PRB_MPU_MAIN_PRB_s
11855 {
11856  ALT_NOC_MPU_PRB_MPU_MAIN_COREID_t Probe_MPU_main_Probe_Id_CoreId; /* ALT_NOC_MPU_PRB_MPU_MAIN_COREID */
11857  ALT_NOC_MPU_PRB_MPU_MAIN_REVID_t Probe_MPU_main_Probe_Id_RevisionId; /* ALT_NOC_MPU_PRB_MPU_MAIN_REVID */
11858  ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_t Probe_MPU_main_Probe_MainCtl; /* ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL */
11859  ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_t Probe_MPU_main_Probe_CfgCtl; /* ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL */
11860  volatile uint32_t _pad_0x10_0x13; /* *UNDEFINED* */
11861  ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_t Probe_MPU_main_Probe_FilterLut; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT */
11862  ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_t Probe_MPU_main_Probe_TraceAlarmEn; /* ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN */
11863  ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_t Probe_MPU_main_Probe_TraceAlarmStatus; /* ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT */
11864  ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_t Probe_MPU_main_Probe_TraceAlarmClr; /* ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR */
11865  ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_t Probe_MPU_main_Probe_StatPeriod; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD */
11866  ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_t Probe_MPU_main_Probe_StatGo; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATGO */
11867  ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_t Probe_MPU_main_Probe_StatAlarmMin; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN */
11868  ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_t Probe_MPU_main_Probe_StatAlarmMax; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX */
11869  ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_t Probe_MPU_main_Probe_StatAlarmStatus; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT */
11870  ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_t Probe_MPU_main_Probe_StatAlarmClr; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR */
11871  ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_t Probe_MPU_main_Probe_StatAlarmEn; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN */
11872  volatile uint32_t _pad_0x40_0x43; /* *UNDEFINED* */
11873  ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_t Probe_MPU_main_Probe_Filters_0_RouteIdBase; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE */
11874  ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_t Probe_MPU_main_Probe_Filters_0_RouteIdMask; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK */
11875  ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_t Probe_MPU_main_Probe_Filters_0_AddrBase_Low; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW */
11876  volatile uint32_t _pad_0x50_0x53; /* *UNDEFINED* */
11877  ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_t Probe_MPU_main_Probe_Filters_0_WindowSize; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE */
11878  ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_t Probe_MPU_main_Probe_Filters_0_SecurityBase; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE */
11879  ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_t Probe_MPU_main_Probe_Filters_0_SecurityMask; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK */
11880  ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_t Probe_MPU_main_Probe_Filters_0_Opcode; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE */
11881  ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_t Probe_MPU_main_Probe_Filters_0_Status; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT */
11882  ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_t Probe_MPU_main_Probe_Filters_0_Length; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN */
11883  ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_t Probe_MPU_main_Probe_Filters_0_Urgency; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY */
11884  volatile uint32_t _pad_0x70_0x137[50]; /* *UNDEFINED* */
11885  ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_t Probe_MPU_main_Probe_Counters_0_Src; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC */
11886  ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_t Probe_MPU_main_Probe_Counters_0_AlarmMode; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD */
11887  ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_t Probe_MPU_main_Probe_Counters_0_Val; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL */
11888  volatile uint32_t _pad_0x144_0x14b[2]; /* *UNDEFINED* */
11889  ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_t Probe_MPU_main_Probe_Counters_1_Src; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC */
11890  ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_t Probe_MPU_main_Probe_Counters_1_AlarmMode; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD */
11891  ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_t Probe_MPU_main_Probe_Counters_1_Val; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL */
11892  volatile uint32_t _pad_0x158_0x15f[2]; /* *UNDEFINED* */
11893  ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_t Probe_MPU_main_Probe_Counters_2_Src; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC */
11894  ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_t Probe_MPU_main_Probe_Counters_2_AlarmMode; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD */
11895  ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_t Probe_MPU_main_Probe_Counters_2_Val; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL */
11896  volatile uint32_t _pad_0x16c_0x173[2]; /* *UNDEFINED* */
11897  ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_t Probe_MPU_main_Probe_Counters_3_Src; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC */
11898  ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_t Probe_MPU_main_Probe_Counters_3_AlarmMode; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD */
11899  ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_t Probe_MPU_main_Probe_Counters_3_Val; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL */
11900  volatile uint32_t _pad_0x180_0x400[160]; /* *UNDEFINED* */
11901 };
11902 
11903 /* The typedef declaration for register group ALT_NOC_MPU_PRB_MPU_MAIN_PRB. */
11904 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_PRB_s ALT_NOC_MPU_PRB_MPU_MAIN_PRB_t;
11905 /* The struct declaration for the raw register contents of register group ALT_NOC_MPU_PRB_MPU_MAIN_PRB. */
11906 struct ALT_NOC_MPU_PRB_MPU_MAIN_PRB_raw_s
11907 {
11908  volatile uint32_t Probe_MPU_main_Probe_Id_CoreId; /* ALT_NOC_MPU_PRB_MPU_MAIN_COREID */
11909  volatile uint32_t Probe_MPU_main_Probe_Id_RevisionId; /* ALT_NOC_MPU_PRB_MPU_MAIN_REVID */
11910  volatile uint32_t Probe_MPU_main_Probe_MainCtl; /* ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL */
11911  volatile uint32_t Probe_MPU_main_Probe_CfgCtl; /* ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL */
11912  uint32_t _pad_0x10_0x13; /* *UNDEFINED* */
11913  volatile uint32_t Probe_MPU_main_Probe_FilterLut; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT */
11914  volatile uint32_t Probe_MPU_main_Probe_TraceAlarmEn; /* ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN */
11915  volatile uint32_t Probe_MPU_main_Probe_TraceAlarmStatus; /* ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT */
11916  volatile uint32_t Probe_MPU_main_Probe_TraceAlarmClr; /* ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR */
11917  volatile uint32_t Probe_MPU_main_Probe_StatPeriod; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD */
11918  volatile uint32_t Probe_MPU_main_Probe_StatGo; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATGO */
11919  volatile uint32_t Probe_MPU_main_Probe_StatAlarmMin; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN */
11920  volatile uint32_t Probe_MPU_main_Probe_StatAlarmMax; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX */
11921  volatile uint32_t Probe_MPU_main_Probe_StatAlarmStatus; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT */
11922  volatile uint32_t Probe_MPU_main_Probe_StatAlarmClr; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR */
11923  volatile uint32_t Probe_MPU_main_Probe_StatAlarmEn; /* ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN */
11924  uint32_t _pad_0x40_0x43; /* *UNDEFINED* */
11925  volatile uint32_t Probe_MPU_main_Probe_Filters_0_RouteIdBase; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE */
11926  volatile uint32_t Probe_MPU_main_Probe_Filters_0_RouteIdMask; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK */
11927  volatile uint32_t Probe_MPU_main_Probe_Filters_0_AddrBase_Low; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW */
11928  uint32_t _pad_0x50_0x53; /* *UNDEFINED* */
11929  volatile uint32_t Probe_MPU_main_Probe_Filters_0_WindowSize; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE */
11930  volatile uint32_t Probe_MPU_main_Probe_Filters_0_SecurityBase; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE */
11931  volatile uint32_t Probe_MPU_main_Probe_Filters_0_SecurityMask; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK */
11932  volatile uint32_t Probe_MPU_main_Probe_Filters_0_Opcode; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE */
11933  volatile uint32_t Probe_MPU_main_Probe_Filters_0_Status; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT */
11934  volatile uint32_t Probe_MPU_main_Probe_Filters_0_Length; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN */
11935  volatile uint32_t Probe_MPU_main_Probe_Filters_0_Urgency; /* ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY */
11936  uint32_t _pad_0x70_0x137[50]; /* *UNDEFINED* */
11937  volatile uint32_t Probe_MPU_main_Probe_Counters_0_Src; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC */
11938  volatile uint32_t Probe_MPU_main_Probe_Counters_0_AlarmMode; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD */
11939  volatile uint32_t Probe_MPU_main_Probe_Counters_0_Val; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL */
11940  uint32_t _pad_0x144_0x14b[2]; /* *UNDEFINED* */
11941  volatile uint32_t Probe_MPU_main_Probe_Counters_1_Src; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC */
11942  volatile uint32_t Probe_MPU_main_Probe_Counters_1_AlarmMode; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD */
11943  volatile uint32_t Probe_MPU_main_Probe_Counters_1_Val; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL */
11944  uint32_t _pad_0x158_0x15f[2]; /* *UNDEFINED* */
11945  volatile uint32_t Probe_MPU_main_Probe_Counters_2_Src; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC */
11946  volatile uint32_t Probe_MPU_main_Probe_Counters_2_AlarmMode; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD */
11947  volatile uint32_t Probe_MPU_main_Probe_Counters_2_Val; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL */
11948  uint32_t _pad_0x16c_0x173[2]; /* *UNDEFINED* */
11949  volatile uint32_t Probe_MPU_main_Probe_Counters_3_Src; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC */
11950  volatile uint32_t Probe_MPU_main_Probe_Counters_3_AlarmMode; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD */
11951  volatile uint32_t Probe_MPU_main_Probe_Counters_3_Val; /* ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL */
11952  uint32_t _pad_0x180_0x400[160]; /* *UNDEFINED* */
11953 };
11954 
11955 /* The typedef declaration for the raw register contents of register group ALT_NOC_MPU_PRB_MPU_MAIN_PRB. */
11956 typedef volatile struct ALT_NOC_MPU_PRB_MPU_MAIN_PRB_raw_s ALT_NOC_MPU_PRB_MPU_MAIN_PRB_raw_t;
11957 #endif /* __ASSEMBLY__ */
11958 
11959 
11960 #ifdef __cplusplus
11961 }
11962 #endif /* __cplusplus */
11963 #endif /* __ALT_SOCAL_NOC_MPU_PRB_H__ */
11964