Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
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alt_fpgamgr.h
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32 
33 /* Altera - ALT_FPGAMGR */
34 
35 #ifndef __ALTERA_ALT_FPGAMGR_H__
36 #define __ALTERA_ALT_FPGAMGR_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : FPGA Manager Module - ALT_FPGAMGR
45  * FPGA Manager Module
46  *
47  * Registers in the FPGA Manager module accessible via its APB slave
48  *
49  */
50 /*
51  * Register : Status Register - stat
52  *
53  * Provides status fields for software for the FPGA Manager.
54  *
55  * The Mode field tells software what configuration phase the FPGA currently is in.
56  * For regular configuration through the PINs or through the HPS, these states map
57  * directly to customer configuration documentation.
58  *
59  * For Configuration Via PCI Express (CVP), the IOCSR configuration is done through
60  * the PINS or through HPS. Then the complete configuration is done through the
61  * PCI Express Bus. When CVP is being done, InitPhase indicates only IOCSR
62  * configuration has completed. CVP_CONF_DONE is available in the CB Monitor for
63  * observation by software.
64  *
65  * The MSEL field provides a read only register for software to read the MSEL value
66  * driven from the external pins.
67  *
68  * Register Layout
69  *
70  * Bits | Access | Reset | Description
71  * :-------|:-------|:------|:------------
72  * [2:0] | RW | 0x5 | Mode
73  * [7:3] | R | 0x8 | MSEL
74  * [31:8] | ??? | 0x0 | *UNDEFINED*
75  *
76  */
77 /*
78  * Field : Mode - mode
79  *
80  * Reports FPGA state
81  *
82  * Field Enumeration Values:
83  *
84  * Enum | Value | Description
85  * :---------------------------------|:------|:---------------------------------------------
86  * ALT_FPGAMGR_STAT_MOD_E_FPGAOFF | 0x0 | FPGA Powered Off
87  * ALT_FPGAMGR_STAT_MOD_E_RSTPHASE | 0x1 | FPGA in Reset Phase
88  * ALT_FPGAMGR_STAT_MOD_E_CFGPHASE | 0x2 | FPGA in Configuration Phase
89  * ALT_FPGAMGR_STAT_MOD_E_INITPHASE | 0x3 | FPGA in Initialization Phase. In CVP
90  * : | | configuration, this state indicates IO
91  * : | | configuration has completed.
92  * ALT_FPGAMGR_STAT_MOD_E_USERMOD | 0x4 | FPGA in User Mode
93  * ALT_FPGAMGR_STAT_MOD_E_UNKNOWN | 0x5 | FPGA state has not yet been determined. This
94  * : | | only occurs briefly after reset.
95  *
96  * Field Access Macros:
97  *
98  */
99 /*
100  * Enumerated value for register field ALT_FPGAMGR_STAT_MOD
101  *
102  * FPGA Powered Off
103  */
104 #define ALT_FPGAMGR_STAT_MOD_E_FPGAOFF 0x0
105 /*
106  * Enumerated value for register field ALT_FPGAMGR_STAT_MOD
107  *
108  * FPGA in Reset Phase
109  */
110 #define ALT_FPGAMGR_STAT_MOD_E_RSTPHASE 0x1
111 /*
112  * Enumerated value for register field ALT_FPGAMGR_STAT_MOD
113  *
114  * FPGA in Configuration Phase
115  */
116 #define ALT_FPGAMGR_STAT_MOD_E_CFGPHASE 0x2
117 /*
118  * Enumerated value for register field ALT_FPGAMGR_STAT_MOD
119  *
120  * FPGA in Initialization Phase. In CVP configuration, this state indicates IO
121  * configuration has completed.
122  */
123 #define ALT_FPGAMGR_STAT_MOD_E_INITPHASE 0x3
124 /*
125  * Enumerated value for register field ALT_FPGAMGR_STAT_MOD
126  *
127  * FPGA in User Mode
128  */
129 #define ALT_FPGAMGR_STAT_MOD_E_USERMOD 0x4
130 /*
131  * Enumerated value for register field ALT_FPGAMGR_STAT_MOD
132  *
133  * FPGA state has not yet been determined. This only occurs briefly after reset.
134  */
135 #define ALT_FPGAMGR_STAT_MOD_E_UNKNOWN 0x5
136 
137 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_STAT_MOD register field. */
138 #define ALT_FPGAMGR_STAT_MOD_LSB 0
139 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_STAT_MOD register field. */
140 #define ALT_FPGAMGR_STAT_MOD_MSB 2
141 /* The width in bits of the ALT_FPGAMGR_STAT_MOD register field. */
142 #define ALT_FPGAMGR_STAT_MOD_WIDTH 3
143 /* The mask used to set the ALT_FPGAMGR_STAT_MOD register field value. */
144 #define ALT_FPGAMGR_STAT_MOD_SET_MSK 0x00000007
145 /* The mask used to clear the ALT_FPGAMGR_STAT_MOD register field value. */
146 #define ALT_FPGAMGR_STAT_MOD_CLR_MSK 0xfffffff8
147 /* The reset value of the ALT_FPGAMGR_STAT_MOD register field. */
148 #define ALT_FPGAMGR_STAT_MOD_RESET 0x5
149 /* Extracts the ALT_FPGAMGR_STAT_MOD field value from a register. */
150 #define ALT_FPGAMGR_STAT_MOD_GET(value) (((value) & 0x00000007) >> 0)
151 /* Produces a ALT_FPGAMGR_STAT_MOD register field value suitable for setting the register. */
152 #define ALT_FPGAMGR_STAT_MOD_SET(value) (((value) << 0) & 0x00000007)
153 
154 /*
155  * Field : MSEL - msel
156  *
157  * This read-only field allows software to observe the MSEL inputs from the device
158  * pins. The MSEL pins define the FPGA configuration mode.
159  *
160  * Field Enumeration Values:
161  *
162  * Enum | Value | Description
163  * :---------------------------------------------|:------|:-------------------------------------------------
164  * ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_NOAES_NODC | 0x0 | 16-bit Passive Parallel with Fast Power on Reset
165  * : | | Delay; No AES Encryption; No Data Compression.
166  * : | | CDRATIO must be programmed to x1
167  * ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AES_NODC | 0x1 | 16-bit Passive Parallel with Fast Power on Reset
168  * : | | Delay; With AES Encryption; No Data Compression.
169  * : | | CDRATIO must be programmed to x4
170  * ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AESOPT_DC | 0x2 | 16-bit Passive Parallel with Fast Power on Reset
171  * : | | Delay; AES Optional; With Data Compression.
172  * : | | CDRATIO must be programmed to x8
173  * ALT_FPGAMGR_STAT_MSEL_E_RSVD3 | 0x3 | Reserved
174  * ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_NOAES_NODC | 0x4 | 16-bit Passive Parallel with Slow Power on Reset
175  * : | | Delay; No AES Encryption; No Data Compression.
176  * : | | CDRATIO must be programmed to x1
177  * ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AES_NODC | 0x5 | 16-bit Passive Parallel with Slow Power on Reset
178  * : | | Delay; With AES Encryption; No Data Compression.
179  * : | | CDRATIO must be programmed to x4
180  * ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AESOPT_DC | 0x6 | 16-bit Passive Parallel with Slow Power on Reset
181  * : | | Delay; AES Optional; With Data Compression.
182  * : | | CDRATIO must be programmed to x8
183  * ALT_FPGAMGR_STAT_MSEL_E_RSVD7 | 0x7 | Reserved
184  * ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_NOAES_NODC | 0x8 | 32-bit Passive Parallel with Fast Power on Reset
185  * : | | Delay; No AES Encryption; No Data Compression.
186  * : | | CDRATIO must be programmed to x1
187  * ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AES_NODC | 0x9 | 32-bit Passive Parallel with Fast Power on Reset
188  * : | | Delay; With AES Encryption; No Data Compression.
189  * : | | CDRATIO must be programmed to x4
190  * ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AESOPT_DC | 0xa | 32-bit Passive Parallel with Fast Power on Reset
191  * : | | Delay; AES Optional; With Data Compression.
192  * : | | CDRATIO must be programmed to x8
193  * ALT_FPGAMGR_STAT_MSEL_E_RSVD11 | 0xb | Reserved
194  * ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_NOAES_NODC | 0xc | 32-bit Passive Parallel with Slow Power on Reset
195  * : | | Delay; No AES Encryption; No Data Compression.
196  * : | | CDRATIO must be programmed to x1
197  * ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AES_NODC | 0xd | 32-bit Passive Parallel with Slow Power on Reset
198  * : | | Delay; With AES Encryption; No Data Compression.
199  * : | | CDRATIO must be programmed to x4
200  * ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AESOPT_DC | 0xe | 32-bit Passive Parallel with Slow Power on Reset
201  * : | | Delay; AES Optional; With Data Compression.
202  * : | | CDRATIO must be programmed to x8
203  * ALT_FPGAMGR_STAT_MSEL_E_RSVD15 | 0xf | Reserved
204  * ALT_FPGAMGR_STAT_MSEL_E_RSVD16 | 0x10 | Reserved
205  * ALT_FPGAMGR_STAT_MSEL_E_RSVD17 | 0x11 | Reserved
206  * ALT_FPGAMGR_STAT_MSEL_E_RSVD18 | 0x12 | Reserved
207  * ALT_FPGAMGR_STAT_MSEL_E_RSVD19 | 0x13 | Reserved
208  * ALT_FPGAMGR_STAT_MSEL_E_RSVD20 | 0x14 | Reserved
209  * ALT_FPGAMGR_STAT_MSEL_E_RSVD21 | 0x15 | Reserved
210  * ALT_FPGAMGR_STAT_MSEL_E_RSVD22 | 0x16 | Reserved
211  * ALT_FPGAMGR_STAT_MSEL_E_RSVD23 | 0x17 | Reserved
212  * ALT_FPGAMGR_STAT_MSEL_E_RSVD24 | 0x18 | Reserved
213  * ALT_FPGAMGR_STAT_MSEL_E_RSVD25 | 0x19 | Reserved
214  * ALT_FPGAMGR_STAT_MSEL_E_RSVD26 | 0x1a | Reserved
215  * ALT_FPGAMGR_STAT_MSEL_E_RSVD27 | 0x1b | Reserved
216  * ALT_FPGAMGR_STAT_MSEL_E_RSVD28 | 0x1c | Reserved
217  * ALT_FPGAMGR_STAT_MSEL_E_RSVD29 | 0x1d | Reserved
218  * ALT_FPGAMGR_STAT_MSEL_E_RSVD30 | 0x1e | Reserved
219  * ALT_FPGAMGR_STAT_MSEL_E_RSVD31 | 0x1f | Reserved
220  *
221  * Field Access Macros:
222  *
223  */
224 /*
225  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
226  *
227  * 16-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No
228  * Data Compression.
229  *
230  * CDRATIO must be programmed to x1
231  */
232 #define ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_NOAES_NODC 0x0
233 /*
234  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
235  *
236  * 16-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No
237  * Data Compression.
238  *
239  * CDRATIO must be programmed to x4
240  */
241 #define ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AES_NODC 0x1
242 /*
243  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
244  *
245  * 16-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data
246  * Compression.
247  *
248  * CDRATIO must be programmed to x8
249  */
250 #define ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AESOPT_DC 0x2
251 /*
252  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
253  *
254  * Reserved
255  */
256 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD3 0x3
257 /*
258  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
259  *
260  * 16-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No
261  * Data Compression.
262  *
263  * CDRATIO must be programmed to x1
264  */
265 #define ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_NOAES_NODC 0x4
266 /*
267  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
268  *
269  * 16-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No
270  * Data Compression.
271  *
272  * CDRATIO must be programmed to x4
273  */
274 #define ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AES_NODC 0x5
275 /*
276  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
277  *
278  * 16-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data
279  * Compression.
280  *
281  * CDRATIO must be programmed to x8
282  */
283 #define ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AESOPT_DC 0x6
284 /*
285  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
286  *
287  * Reserved
288  */
289 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD7 0x7
290 /*
291  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
292  *
293  * 32-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No
294  * Data Compression.
295  *
296  * CDRATIO must be programmed to x1
297  */
298 #define ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_NOAES_NODC 0x8
299 /*
300  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
301  *
302  * 32-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No
303  * Data Compression.
304  *
305  * CDRATIO must be programmed to x4
306  */
307 #define ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AES_NODC 0x9
308 /*
309  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
310  *
311  * 32-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data
312  * Compression.
313  *
314  * CDRATIO must be programmed to x8
315  */
316 #define ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AESOPT_DC 0xa
317 /*
318  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
319  *
320  * Reserved
321  */
322 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD11 0xb
323 /*
324  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
325  *
326  * 32-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No
327  * Data Compression.
328  *
329  * CDRATIO must be programmed to x1
330  */
331 #define ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_NOAES_NODC 0xc
332 /*
333  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
334  *
335  * 32-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No
336  * Data Compression.
337  *
338  * CDRATIO must be programmed to x4
339  */
340 #define ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AES_NODC 0xd
341 /*
342  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
343  *
344  * 32-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data
345  * Compression.
346  *
347  * CDRATIO must be programmed to x8
348  */
349 #define ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AESOPT_DC 0xe
350 /*
351  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
352  *
353  * Reserved
354  */
355 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD15 0xf
356 /*
357  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
358  *
359  * Reserved
360  */
361 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD16 0x10
362 /*
363  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
364  *
365  * Reserved
366  */
367 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD17 0x11
368 /*
369  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
370  *
371  * Reserved
372  */
373 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD18 0x12
374 /*
375  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
376  *
377  * Reserved
378  */
379 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD19 0x13
380 /*
381  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
382  *
383  * Reserved
384  */
385 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD20 0x14
386 /*
387  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
388  *
389  * Reserved
390  */
391 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD21 0x15
392 /*
393  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
394  *
395  * Reserved
396  */
397 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD22 0x16
398 /*
399  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
400  *
401  * Reserved
402  */
403 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD23 0x17
404 /*
405  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
406  *
407  * Reserved
408  */
409 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD24 0x18
410 /*
411  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
412  *
413  * Reserved
414  */
415 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD25 0x19
416 /*
417  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
418  *
419  * Reserved
420  */
421 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD26 0x1a
422 /*
423  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
424  *
425  * Reserved
426  */
427 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD27 0x1b
428 /*
429  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
430  *
431  * Reserved
432  */
433 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD28 0x1c
434 /*
435  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
436  *
437  * Reserved
438  */
439 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD29 0x1d
440 /*
441  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
442  *
443  * Reserved
444  */
445 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD30 0x1e
446 /*
447  * Enumerated value for register field ALT_FPGAMGR_STAT_MSEL
448  *
449  * Reserved
450  */
451 #define ALT_FPGAMGR_STAT_MSEL_E_RSVD31 0x1f
452 
453 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_STAT_MSEL register field. */
454 #define ALT_FPGAMGR_STAT_MSEL_LSB 3
455 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_STAT_MSEL register field. */
456 #define ALT_FPGAMGR_STAT_MSEL_MSB 7
457 /* The width in bits of the ALT_FPGAMGR_STAT_MSEL register field. */
458 #define ALT_FPGAMGR_STAT_MSEL_WIDTH 5
459 /* The mask used to set the ALT_FPGAMGR_STAT_MSEL register field value. */
460 #define ALT_FPGAMGR_STAT_MSEL_SET_MSK 0x000000f8
461 /* The mask used to clear the ALT_FPGAMGR_STAT_MSEL register field value. */
462 #define ALT_FPGAMGR_STAT_MSEL_CLR_MSK 0xffffff07
463 /* The reset value of the ALT_FPGAMGR_STAT_MSEL register field. */
464 #define ALT_FPGAMGR_STAT_MSEL_RESET 0x8
465 /* Extracts the ALT_FPGAMGR_STAT_MSEL field value from a register. */
466 #define ALT_FPGAMGR_STAT_MSEL_GET(value) (((value) & 0x000000f8) >> 3)
467 /* Produces a ALT_FPGAMGR_STAT_MSEL register field value suitable for setting the register. */
468 #define ALT_FPGAMGR_STAT_MSEL_SET(value) (((value) << 3) & 0x000000f8)
469 
470 #ifndef __ASSEMBLY__
471 /*
472  * WARNING: The C register and register group struct declarations are provided for
473  * convenience and illustrative purposes. They should, however, be used with
474  * caution as the C language standard provides no guarantees about the alignment or
475  * atomicity of device memory accesses. The recommended practice for writing
476  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
477  * alt_write_word() functions.
478  *
479  * The struct declaration for register ALT_FPGAMGR_STAT.
480  */
481 struct ALT_FPGAMGR_STAT_s
482 {
483  uint32_t mode : 3; /* Mode */
484  const uint32_t msel : 5; /* MSEL */
485  uint32_t : 24; /* *UNDEFINED* */
486 };
487 
488 /* The typedef declaration for register ALT_FPGAMGR_STAT. */
489 typedef volatile struct ALT_FPGAMGR_STAT_s ALT_FPGAMGR_STAT_t;
490 #endif /* __ASSEMBLY__ */
491 
492 /* The byte offset of the ALT_FPGAMGR_STAT register from the beginning of the component. */
493 #define ALT_FPGAMGR_STAT_OFST 0x0
494 
495 /*
496  * Register : Control Register - ctrl
497  *
498  * Allows HPS to control FPGA configuration.
499  *
500  * The NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields drive signals to the FPGA
501  * Control Block that are logically ORed into their respective pins. These signals
502  * are always driven independent of the value of EN. The polarity of the
503  * NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields is inverted relative to their
504  * associated pins.
505  *
506  * The MSEL (external pins), CDRATIO and CFGWDTH signals determine the mode of
507  * operation for Normal Configuration. For Partial Reconfiguration, CDRATIO is used
508  * to set the appropriate clock to data ratio, and CFGWDTH should always be set to
509  * 16-bit Passive Parallel.
510  *
511  * AXICFGEN is used to enable transfer of configuration data by enabling or
512  * disabling DCLK during data transfers.
513  *
514  * Register Layout
515  *
516  * Bits | Access | Reset | Description
517  * :--------|:-------|:------|:-------------------------
518  * [0] | RW | 0x0 | Enable
519  * [1] | RW | 0x0 | nCE
520  * [2] | RW | 0x0 | nCONFIG Pull-Down
521  * [3] | RW | 0x0 | nSTATUS Pull-Down
522  * [4] | RW | 0x0 | CONF_DONE Pull-Down
523  * [5] | RW | 0x0 | Partial Reconfiguration
524  * [7:6] | RW | 0x0 | CD Ratio
525  * [8] | RW | 0x0 | AXI Configuration Enable
526  * [9] | RW | 0x1 | Configuration Data Width
527  * [31:10] | ??? | 0x0 | *UNDEFINED*
528  *
529  */
530 /*
531  * Field : Enable - en
532  *
533  * Controls whether the FPGA configuration pins or HPS FPGA Manager drive
534  * configuration inputs to the CB.
535  *
536  * Field Enumeration Values:
537  *
538  * Enum | Value | Description
539  * :---------------------------------------|:------|:------------------------------------------------
540  * ALT_FPGAMGR_CTL_EN_E_FPGA_PINS_CTL_CFG | 0x0 | FPGA configuration pins drive configuration
541  * : | | inputs to the CB. Used when FPGA is configured
542  * : | | by means other than the HPS.
543  * ALT_FPGAMGR_CTL_EN_E_FPGAMGR_CTLS_CFG | 0x1 | FPGA Manager drives configuration inputs to the
544  * : | | CB. Used when HPS configures the FPGA.
545  *
546  * Field Access Macros:
547  *
548  */
549 /*
550  * Enumerated value for register field ALT_FPGAMGR_CTL_EN
551  *
552  * FPGA configuration pins drive configuration inputs to the CB. Used when FPGA is
553  * configured by means other than the HPS.
554  */
555 #define ALT_FPGAMGR_CTL_EN_E_FPGA_PINS_CTL_CFG 0x0
556 /*
557  * Enumerated value for register field ALT_FPGAMGR_CTL_EN
558  *
559  * FPGA Manager drives configuration inputs to the CB. Used when HPS configures the
560  * FPGA.
561  */
562 #define ALT_FPGAMGR_CTL_EN_E_FPGAMGR_CTLS_CFG 0x1
563 
564 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_EN register field. */
565 #define ALT_FPGAMGR_CTL_EN_LSB 0
566 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_EN register field. */
567 #define ALT_FPGAMGR_CTL_EN_MSB 0
568 /* The width in bits of the ALT_FPGAMGR_CTL_EN register field. */
569 #define ALT_FPGAMGR_CTL_EN_WIDTH 1
570 /* The mask used to set the ALT_FPGAMGR_CTL_EN register field value. */
571 #define ALT_FPGAMGR_CTL_EN_SET_MSK 0x00000001
572 /* The mask used to clear the ALT_FPGAMGR_CTL_EN register field value. */
573 #define ALT_FPGAMGR_CTL_EN_CLR_MSK 0xfffffffe
574 /* The reset value of the ALT_FPGAMGR_CTL_EN register field. */
575 #define ALT_FPGAMGR_CTL_EN_RESET 0x0
576 /* Extracts the ALT_FPGAMGR_CTL_EN field value from a register. */
577 #define ALT_FPGAMGR_CTL_EN_GET(value) (((value) & 0x00000001) >> 0)
578 /* Produces a ALT_FPGAMGR_CTL_EN register field value suitable for setting the register. */
579 #define ALT_FPGAMGR_CTL_EN_SET(value) (((value) << 0) & 0x00000001)
580 
581 /*
582  * Field : nCE - nce
583  *
584  * This field drives the active-low Chip Enable (nCE) signal to the CB. It should
585  * be set to 0 (configuration enabled) before CTRL.EN is set.
586  *
587  * This field only effects the FPGA if CTRL.EN is 1.
588  *
589  * Field Enumeration Values:
590  *
591  * Enum | Value | Description
592  * :-------------------------------|:------|:------------------------------------------------
593  * ALT_FPGAMGR_CTL_NCE_E_CFG_END | 0x0 | Configuration is enabled. The nCE to the CB is
594  * : | | driven to 0.
595  * ALT_FPGAMGR_CTL_NCE_E_CFG_DISD | 0x1 | Configuration is disabled. The nCE to the CB is
596  * : | | driven to 1.
597  *
598  * Field Access Macros:
599  *
600  */
601 /*
602  * Enumerated value for register field ALT_FPGAMGR_CTL_NCE
603  *
604  * Configuration is enabled. The nCE to the CB is driven to 0.
605  */
606 #define ALT_FPGAMGR_CTL_NCE_E_CFG_END 0x0
607 /*
608  * Enumerated value for register field ALT_FPGAMGR_CTL_NCE
609  *
610  * Configuration is disabled. The nCE to the CB is driven to 1.
611  */
612 #define ALT_FPGAMGR_CTL_NCE_E_CFG_DISD 0x1
613 
614 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_NCE register field. */
615 #define ALT_FPGAMGR_CTL_NCE_LSB 1
616 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_NCE register field. */
617 #define ALT_FPGAMGR_CTL_NCE_MSB 1
618 /* The width in bits of the ALT_FPGAMGR_CTL_NCE register field. */
619 #define ALT_FPGAMGR_CTL_NCE_WIDTH 1
620 /* The mask used to set the ALT_FPGAMGR_CTL_NCE register field value. */
621 #define ALT_FPGAMGR_CTL_NCE_SET_MSK 0x00000002
622 /* The mask used to clear the ALT_FPGAMGR_CTL_NCE register field value. */
623 #define ALT_FPGAMGR_CTL_NCE_CLR_MSK 0xfffffffd
624 /* The reset value of the ALT_FPGAMGR_CTL_NCE register field. */
625 #define ALT_FPGAMGR_CTL_NCE_RESET 0x0
626 /* Extracts the ALT_FPGAMGR_CTL_NCE field value from a register. */
627 #define ALT_FPGAMGR_CTL_NCE_GET(value) (((value) & 0x00000002) >> 1)
628 /* Produces a ALT_FPGAMGR_CTL_NCE register field value suitable for setting the register. */
629 #define ALT_FPGAMGR_CTL_NCE_SET(value) (((value) << 1) & 0x00000002)
630 
631 /*
632  * Field : nCONFIG Pull-Down - nconfigpull
633  *
634  * The nCONFIG input is used to put the FPGA into its reset phase. If the FPGA was
635  * configured, its operation stops and it will have to be configured again to start
636  * operation.
637  *
638  * Field Enumeration Values:
639  *
640  * Enum | Value | Description
641  * :-----------------------------------------|:------|:-------------------------------------------------
642  * ALT_FPGAMGR_CTL_NCFGPULL_E_DONT_PULLDOWN | 0x0 | Don't pull-down nCONFIG input to the CB.
643  * ALT_FPGAMGR_CTL_NCFGPULL_E_PULLDOWN | 0x1 | Pull-down nCONFIG input to the CB. This puts the
644  * : | | FPGA in reset phase and restarts configuration.
645  *
646  * Field Access Macros:
647  *
648  */
649 /*
650  * Enumerated value for register field ALT_FPGAMGR_CTL_NCFGPULL
651  *
652  * Don't pull-down nCONFIG input to the CB.
653  */
654 #define ALT_FPGAMGR_CTL_NCFGPULL_E_DONT_PULLDOWN 0x0
655 /*
656  * Enumerated value for register field ALT_FPGAMGR_CTL_NCFGPULL
657  *
658  * Pull-down nCONFIG input to the CB. This puts the FPGA in reset phase and
659  * restarts configuration.
660  */
661 #define ALT_FPGAMGR_CTL_NCFGPULL_E_PULLDOWN 0x1
662 
663 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_NCFGPULL register field. */
664 #define ALT_FPGAMGR_CTL_NCFGPULL_LSB 2
665 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_NCFGPULL register field. */
666 #define ALT_FPGAMGR_CTL_NCFGPULL_MSB 2
667 /* The width in bits of the ALT_FPGAMGR_CTL_NCFGPULL register field. */
668 #define ALT_FPGAMGR_CTL_NCFGPULL_WIDTH 1
669 /* The mask used to set the ALT_FPGAMGR_CTL_NCFGPULL register field value. */
670 #define ALT_FPGAMGR_CTL_NCFGPULL_SET_MSK 0x00000004
671 /* The mask used to clear the ALT_FPGAMGR_CTL_NCFGPULL register field value. */
672 #define ALT_FPGAMGR_CTL_NCFGPULL_CLR_MSK 0xfffffffb
673 /* The reset value of the ALT_FPGAMGR_CTL_NCFGPULL register field. */
674 #define ALT_FPGAMGR_CTL_NCFGPULL_RESET 0x0
675 /* Extracts the ALT_FPGAMGR_CTL_NCFGPULL field value from a register. */
676 #define ALT_FPGAMGR_CTL_NCFGPULL_GET(value) (((value) & 0x00000004) >> 2)
677 /* Produces a ALT_FPGAMGR_CTL_NCFGPULL register field value suitable for setting the register. */
678 #define ALT_FPGAMGR_CTL_NCFGPULL_SET(value) (((value) << 2) & 0x00000004)
679 
680 /*
681  * Field : nSTATUS Pull-Down - nstatuspull
682  *
683  * Pulls down nSTATUS input to the CB
684  *
685  * Field Enumeration Values:
686  *
687  * Enum | Value | Description
688  * :------------------------------------------|:------|:-----------------------------------------
689  * ALT_FPGAMGR_CTL_NSTATPULL_E_DONT_PULLDOWN | 0x0 | Don't pull-down nSTATUS input to the CB.
690  * ALT_FPGAMGR_CTL_NSTATPULL_E_PULLDOWN | 0x1 | Pull-down nSTATUS input to the CB.
691  *
692  * Field Access Macros:
693  *
694  */
695 /*
696  * Enumerated value for register field ALT_FPGAMGR_CTL_NSTATPULL
697  *
698  * Don't pull-down nSTATUS input to the CB.
699  */
700 #define ALT_FPGAMGR_CTL_NSTATPULL_E_DONT_PULLDOWN 0x0
701 /*
702  * Enumerated value for register field ALT_FPGAMGR_CTL_NSTATPULL
703  *
704  * Pull-down nSTATUS input to the CB.
705  */
706 #define ALT_FPGAMGR_CTL_NSTATPULL_E_PULLDOWN 0x1
707 
708 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_NSTATPULL register field. */
709 #define ALT_FPGAMGR_CTL_NSTATPULL_LSB 3
710 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_NSTATPULL register field. */
711 #define ALT_FPGAMGR_CTL_NSTATPULL_MSB 3
712 /* The width in bits of the ALT_FPGAMGR_CTL_NSTATPULL register field. */
713 #define ALT_FPGAMGR_CTL_NSTATPULL_WIDTH 1
714 /* The mask used to set the ALT_FPGAMGR_CTL_NSTATPULL register field value. */
715 #define ALT_FPGAMGR_CTL_NSTATPULL_SET_MSK 0x00000008
716 /* The mask used to clear the ALT_FPGAMGR_CTL_NSTATPULL register field value. */
717 #define ALT_FPGAMGR_CTL_NSTATPULL_CLR_MSK 0xfffffff7
718 /* The reset value of the ALT_FPGAMGR_CTL_NSTATPULL register field. */
719 #define ALT_FPGAMGR_CTL_NSTATPULL_RESET 0x0
720 /* Extracts the ALT_FPGAMGR_CTL_NSTATPULL field value from a register. */
721 #define ALT_FPGAMGR_CTL_NSTATPULL_GET(value) (((value) & 0x00000008) >> 3)
722 /* Produces a ALT_FPGAMGR_CTL_NSTATPULL register field value suitable for setting the register. */
723 #define ALT_FPGAMGR_CTL_NSTATPULL_SET(value) (((value) << 3) & 0x00000008)
724 
725 /*
726  * Field : CONF_DONE Pull-Down - confdonepull
727  *
728  * Pulls down CONF_DONE input to the CB
729  *
730  * Field Enumeration Values:
731  *
732  * Enum | Value | Description
733  * :---------------------------------------------|:------|:-------------------------------------------
734  * ALT_FPGAMGR_CTL_CONFDONEPULL_E_DONT_PULLDOWN | 0x0 | Don't pull-down CONF_DONE input to the CB.
735  * ALT_FPGAMGR_CTL_CONFDONEPULL_E_PULLDOWN | 0x1 | Pull-down CONF_DONE input to the CB.
736  *
737  * Field Access Macros:
738  *
739  */
740 /*
741  * Enumerated value for register field ALT_FPGAMGR_CTL_CONFDONEPULL
742  *
743  * Don't pull-down CONF_DONE input to the CB.
744  */
745 #define ALT_FPGAMGR_CTL_CONFDONEPULL_E_DONT_PULLDOWN 0x0
746 /*
747  * Enumerated value for register field ALT_FPGAMGR_CTL_CONFDONEPULL
748  *
749  * Pull-down CONF_DONE input to the CB.
750  */
751 #define ALT_FPGAMGR_CTL_CONFDONEPULL_E_PULLDOWN 0x1
752 
753 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_CONFDONEPULL register field. */
754 #define ALT_FPGAMGR_CTL_CONFDONEPULL_LSB 4
755 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_CONFDONEPULL register field. */
756 #define ALT_FPGAMGR_CTL_CONFDONEPULL_MSB 4
757 /* The width in bits of the ALT_FPGAMGR_CTL_CONFDONEPULL register field. */
758 #define ALT_FPGAMGR_CTL_CONFDONEPULL_WIDTH 1
759 /* The mask used to set the ALT_FPGAMGR_CTL_CONFDONEPULL register field value. */
760 #define ALT_FPGAMGR_CTL_CONFDONEPULL_SET_MSK 0x00000010
761 /* The mask used to clear the ALT_FPGAMGR_CTL_CONFDONEPULL register field value. */
762 #define ALT_FPGAMGR_CTL_CONFDONEPULL_CLR_MSK 0xffffffef
763 /* The reset value of the ALT_FPGAMGR_CTL_CONFDONEPULL register field. */
764 #define ALT_FPGAMGR_CTL_CONFDONEPULL_RESET 0x0
765 /* Extracts the ALT_FPGAMGR_CTL_CONFDONEPULL field value from a register. */
766 #define ALT_FPGAMGR_CTL_CONFDONEPULL_GET(value) (((value) & 0x00000010) >> 4)
767 /* Produces a ALT_FPGAMGR_CTL_CONFDONEPULL register field value suitable for setting the register. */
768 #define ALT_FPGAMGR_CTL_CONFDONEPULL_SET(value) (((value) << 4) & 0x00000010)
769 
770 /*
771  * Field : Partial Reconfiguration - prreq
772  *
773  * This field is used to assert PR_REQUEST to request partial reconfiguration while
774  * the FPGA is in User Mode. This field only affects the FPGA if CTRL.EN is 1.
775  *
776  * Field Enumeration Values:
777  *
778  * Enum | Value | Description
779  * :---------------------------------|:------|:------------------------------------
780  * ALT_FPGAMGR_CTL_PRREQ_E_DEASSERT | 0x0 | De-assert PR_REQUEST (driven to 0).
781  * ALT_FPGAMGR_CTL_PRREQ_E_ASSERT | 0x1 | Assert PR_REQUEST (driven to 1).
782  *
783  * Field Access Macros:
784  *
785  */
786 /*
787  * Enumerated value for register field ALT_FPGAMGR_CTL_PRREQ
788  *
789  * De-assert PR_REQUEST (driven to 0).
790  */
791 #define ALT_FPGAMGR_CTL_PRREQ_E_DEASSERT 0x0
792 /*
793  * Enumerated value for register field ALT_FPGAMGR_CTL_PRREQ
794  *
795  * Assert PR_REQUEST (driven to 1).
796  */
797 #define ALT_FPGAMGR_CTL_PRREQ_E_ASSERT 0x1
798 
799 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_PRREQ register field. */
800 #define ALT_FPGAMGR_CTL_PRREQ_LSB 5
801 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_PRREQ register field. */
802 #define ALT_FPGAMGR_CTL_PRREQ_MSB 5
803 /* The width in bits of the ALT_FPGAMGR_CTL_PRREQ register field. */
804 #define ALT_FPGAMGR_CTL_PRREQ_WIDTH 1
805 /* The mask used to set the ALT_FPGAMGR_CTL_PRREQ register field value. */
806 #define ALT_FPGAMGR_CTL_PRREQ_SET_MSK 0x00000020
807 /* The mask used to clear the ALT_FPGAMGR_CTL_PRREQ register field value. */
808 #define ALT_FPGAMGR_CTL_PRREQ_CLR_MSK 0xffffffdf
809 /* The reset value of the ALT_FPGAMGR_CTL_PRREQ register field. */
810 #define ALT_FPGAMGR_CTL_PRREQ_RESET 0x0
811 /* Extracts the ALT_FPGAMGR_CTL_PRREQ field value from a register. */
812 #define ALT_FPGAMGR_CTL_PRREQ_GET(value) (((value) & 0x00000020) >> 5)
813 /* Produces a ALT_FPGAMGR_CTL_PRREQ register field value suitable for setting the register. */
814 #define ALT_FPGAMGR_CTL_PRREQ_SET(value) (((value) << 5) & 0x00000020)
815 
816 /*
817  * Field : CD Ratio - cdratio
818  *
819  * This field controls the Clock to Data Ratio (CDRATIO) for Normal Configuration
820  * and Partial Reconfiguration data transfer from the AXI Slave to the FPGA.
821  *
822  * For Normal Configuration, the value in this field must be set to be consistent
823  * to the implied CD ratio of the MSEL setting.
824  *
825  * For Partial Reconfiguration, the value in this field must be set to the same
826  * clock to data ratio in the options bits in the Normal Configuration file.
827  *
828  * Field Enumeration Values:
829  *
830  * Enum | Value | Description
831  * :-----------------------------|:------|:-------------
832  * ALT_FPGAMGR_CTL_CDRATIO_E_X1 | 0x0 | CDRATIO of 1
833  * ALT_FPGAMGR_CTL_CDRATIO_E_X2 | 0x1 | CDRATIO of 2
834  * ALT_FPGAMGR_CTL_CDRATIO_E_X4 | 0x2 | CDRATIO of 4
835  * ALT_FPGAMGR_CTL_CDRATIO_E_X8 | 0x3 | CDRATIO of 8
836  *
837  * Field Access Macros:
838  *
839  */
840 /*
841  * Enumerated value for register field ALT_FPGAMGR_CTL_CDRATIO
842  *
843  * CDRATIO of 1
844  */
845 #define ALT_FPGAMGR_CTL_CDRATIO_E_X1 0x0
846 /*
847  * Enumerated value for register field ALT_FPGAMGR_CTL_CDRATIO
848  *
849  * CDRATIO of 2
850  */
851 #define ALT_FPGAMGR_CTL_CDRATIO_E_X2 0x1
852 /*
853  * Enumerated value for register field ALT_FPGAMGR_CTL_CDRATIO
854  *
855  * CDRATIO of 4
856  */
857 #define ALT_FPGAMGR_CTL_CDRATIO_E_X4 0x2
858 /*
859  * Enumerated value for register field ALT_FPGAMGR_CTL_CDRATIO
860  *
861  * CDRATIO of 8
862  */
863 #define ALT_FPGAMGR_CTL_CDRATIO_E_X8 0x3
864 
865 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_CDRATIO register field. */
866 #define ALT_FPGAMGR_CTL_CDRATIO_LSB 6
867 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_CDRATIO register field. */
868 #define ALT_FPGAMGR_CTL_CDRATIO_MSB 7
869 /* The width in bits of the ALT_FPGAMGR_CTL_CDRATIO register field. */
870 #define ALT_FPGAMGR_CTL_CDRATIO_WIDTH 2
871 /* The mask used to set the ALT_FPGAMGR_CTL_CDRATIO register field value. */
872 #define ALT_FPGAMGR_CTL_CDRATIO_SET_MSK 0x000000c0
873 /* The mask used to clear the ALT_FPGAMGR_CTL_CDRATIO register field value. */
874 #define ALT_FPGAMGR_CTL_CDRATIO_CLR_MSK 0xffffff3f
875 /* The reset value of the ALT_FPGAMGR_CTL_CDRATIO register field. */
876 #define ALT_FPGAMGR_CTL_CDRATIO_RESET 0x0
877 /* Extracts the ALT_FPGAMGR_CTL_CDRATIO field value from a register. */
878 #define ALT_FPGAMGR_CTL_CDRATIO_GET(value) (((value) & 0x000000c0) >> 6)
879 /* Produces a ALT_FPGAMGR_CTL_CDRATIO register field value suitable for setting the register. */
880 #define ALT_FPGAMGR_CTL_CDRATIO_SET(value) (((value) << 6) & 0x000000c0)
881 
882 /*
883  * Field : AXI Configuration Enable - axicfgen
884  *
885  * There are strict SW initialization steps for configuration, partial
886  * configuration and error cases. When SW is sending configuration files, this bit
887  * must be set before the file is transferred on the AXI bus. This bit enables the
888  * DCLK during the AXI configuration data transfers.
889  *
890  * Note, the AXI and configuration datapaths remain active irregardless of the
891  * state of this bit. Simply, if the AXI slave is enabled, the DCLK to the CB
892  * will be active. If disabled, the DCLK to the CB will not be active. So AXI
893  * transfers destined to the FPGA Manager when AXIEN is 0, will complete normally
894  * from the HPS perspective.
895  *
896  * This field only affects the FPGA if CTRL.EN is 1.
897  *
898  * Field Enumeration Values:
899  *
900  * Enum | Value | Description
901  * :--------------------------------|:------|:---------------------------------------------
902  * ALT_FPGAMGR_CTL_AXICFGEN_E_DISD | 0x0 | Incoming AXI data transfers will be ignored.
903  * : | | DCLK will not toggle during data transfer.
904  * ALT_FPGAMGR_CTL_AXICFGEN_E_END | 0x1 | AXI data transfer to CB is active. DCLK will
905  * : | | toggle during data transfer.
906  *
907  * Field Access Macros:
908  *
909  */
910 /*
911  * Enumerated value for register field ALT_FPGAMGR_CTL_AXICFGEN
912  *
913  * Incoming AXI data transfers will be ignored. DCLK will not toggle during data
914  * transfer.
915  */
916 #define ALT_FPGAMGR_CTL_AXICFGEN_E_DISD 0x0
917 /*
918  * Enumerated value for register field ALT_FPGAMGR_CTL_AXICFGEN
919  *
920  * AXI data transfer to CB is active. DCLK will toggle during data transfer.
921  */
922 #define ALT_FPGAMGR_CTL_AXICFGEN_E_END 0x1
923 
924 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_AXICFGEN register field. */
925 #define ALT_FPGAMGR_CTL_AXICFGEN_LSB 8
926 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_AXICFGEN register field. */
927 #define ALT_FPGAMGR_CTL_AXICFGEN_MSB 8
928 /* The width in bits of the ALT_FPGAMGR_CTL_AXICFGEN register field. */
929 #define ALT_FPGAMGR_CTL_AXICFGEN_WIDTH 1
930 /* The mask used to set the ALT_FPGAMGR_CTL_AXICFGEN register field value. */
931 #define ALT_FPGAMGR_CTL_AXICFGEN_SET_MSK 0x00000100
932 /* The mask used to clear the ALT_FPGAMGR_CTL_AXICFGEN register field value. */
933 #define ALT_FPGAMGR_CTL_AXICFGEN_CLR_MSK 0xfffffeff
934 /* The reset value of the ALT_FPGAMGR_CTL_AXICFGEN register field. */
935 #define ALT_FPGAMGR_CTL_AXICFGEN_RESET 0x0
936 /* Extracts the ALT_FPGAMGR_CTL_AXICFGEN field value from a register. */
937 #define ALT_FPGAMGR_CTL_AXICFGEN_GET(value) (((value) & 0x00000100) >> 8)
938 /* Produces a ALT_FPGAMGR_CTL_AXICFGEN register field value suitable for setting the register. */
939 #define ALT_FPGAMGR_CTL_AXICFGEN_SET(value) (((value) << 8) & 0x00000100)
940 
941 /*
942  * Field : Configuration Data Width - cfgwdth
943  *
944  * This field determines the Configuration Passive Parallel data bus width when HPS
945  * configures the FPGA. Only 32-bit Passive Parallel or 16-bit Passive Parallel
946  * are supported.
947  *
948  * When HPS does Normal Configuration, configuration should use 32-bit Passive
949  * Parallel Mode. The external pins MSEL must be set appropriately for the
950  * configuration selected.
951  *
952  * For Partial Reconfiguration, 16-bit Passive Parallel must be used.
953  *
954  * Field Enumeration Values:
955  *
956  * Enum | Value | Description
957  * :--------------------------------|:------|:------------------------
958  * ALT_FPGAMGR_CTL_CFGWDTH_E_PPX16 | 0x0 | 16-bit Passive Parallel
959  * ALT_FPGAMGR_CTL_CFGWDTH_E_PPX32 | 0x1 | 32-bit Passive Parallel
960  *
961  * Field Access Macros:
962  *
963  */
964 /*
965  * Enumerated value for register field ALT_FPGAMGR_CTL_CFGWDTH
966  *
967  * 16-bit Passive Parallel
968  */
969 #define ALT_FPGAMGR_CTL_CFGWDTH_E_PPX16 0x0
970 /*
971  * Enumerated value for register field ALT_FPGAMGR_CTL_CFGWDTH
972  *
973  * 32-bit Passive Parallel
974  */
975 #define ALT_FPGAMGR_CTL_CFGWDTH_E_PPX32 0x1
976 
977 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_CFGWDTH register field. */
978 #define ALT_FPGAMGR_CTL_CFGWDTH_LSB 9
979 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_CFGWDTH register field. */
980 #define ALT_FPGAMGR_CTL_CFGWDTH_MSB 9
981 /* The width in bits of the ALT_FPGAMGR_CTL_CFGWDTH register field. */
982 #define ALT_FPGAMGR_CTL_CFGWDTH_WIDTH 1
983 /* The mask used to set the ALT_FPGAMGR_CTL_CFGWDTH register field value. */
984 #define ALT_FPGAMGR_CTL_CFGWDTH_SET_MSK 0x00000200
985 /* The mask used to clear the ALT_FPGAMGR_CTL_CFGWDTH register field value. */
986 #define ALT_FPGAMGR_CTL_CFGWDTH_CLR_MSK 0xfffffdff
987 /* The reset value of the ALT_FPGAMGR_CTL_CFGWDTH register field. */
988 #define ALT_FPGAMGR_CTL_CFGWDTH_RESET 0x1
989 /* Extracts the ALT_FPGAMGR_CTL_CFGWDTH field value from a register. */
990 #define ALT_FPGAMGR_CTL_CFGWDTH_GET(value) (((value) & 0x00000200) >> 9)
991 /* Produces a ALT_FPGAMGR_CTL_CFGWDTH register field value suitable for setting the register. */
992 #define ALT_FPGAMGR_CTL_CFGWDTH_SET(value) (((value) << 9) & 0x00000200)
993 
994 #ifndef __ASSEMBLY__
995 /*
996  * WARNING: The C register and register group struct declarations are provided for
997  * convenience and illustrative purposes. They should, however, be used with
998  * caution as the C language standard provides no guarantees about the alignment or
999  * atomicity of device memory accesses. The recommended practice for writing
1000  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1001  * alt_write_word() functions.
1002  *
1003  * The struct declaration for register ALT_FPGAMGR_CTL.
1004  */
1005 struct ALT_FPGAMGR_CTL_s
1006 {
1007  uint32_t en : 1; /* Enable */
1008  uint32_t nce : 1; /* nCE */
1009  uint32_t nconfigpull : 1; /* nCONFIG Pull-Down */
1010  uint32_t nstatuspull : 1; /* nSTATUS Pull-Down */
1011  uint32_t confdonepull : 1; /* CONF_DONE Pull-Down */
1012  uint32_t prreq : 1; /* Partial Reconfiguration */
1013  uint32_t cdratio : 2; /* CD Ratio */
1014  uint32_t axicfgen : 1; /* AXI Configuration Enable */
1015  uint32_t cfgwdth : 1; /* Configuration Data Width */
1016  uint32_t : 22; /* *UNDEFINED* */
1017 };
1018 
1019 /* The typedef declaration for register ALT_FPGAMGR_CTL. */
1020 typedef volatile struct ALT_FPGAMGR_CTL_s ALT_FPGAMGR_CTL_t;
1021 #endif /* __ASSEMBLY__ */
1022 
1023 /* The byte offset of the ALT_FPGAMGR_CTL register from the beginning of the component. */
1024 #define ALT_FPGAMGR_CTL_OFST 0x4
1025 
1026 /*
1027  * Register : DCLK Count Register - dclkcnt
1028  *
1029  * Used to give software control in enabling DCLK at any time.
1030  *
1031  * SW will need control of the DCLK in specific configuration and partial
1032  * reconfiguration initialization steps to send spurious DCLKs required by the CB.
1033  * SW takes ownership for DCLK during normal configuration, partial
1034  * reconfiguration, error scenerio handshakes including SEU CRC error during
1035  * partial reconfiguration, SW early abort of partial reconfiguration, and
1036  * initializatin phase DCLK driving.
1037  *
1038  * During initialization phase, a configuration image loaded into the FPGA can
1039  * request that DCLK be used as the initialization phase clock instead of the
1040  * default internal oscillator or optionally the CLKUSR pin. In the case that DCLK
1041  * is requested, the DCLKCNT register is used by software to control DCLK during
1042  * the initialization phase.
1043  *
1044  * Software should poll the DCLKSTAT.DCNTDONE write one to clear register to be set
1045  * when the correct number of DCLKs have completed. Software should clear
1046  * DCLKSTAT.DCNTDONE before writing to the DCLKCNT register again.
1047  *
1048  * This field only affects the FPGA if CTRL.EN is 1.
1049  *
1050  * Register Layout
1051  *
1052  * Bits | Access | Reset | Description
1053  * :-------|:-------|:------|:------------
1054  * [31:0] | RW | 0x0 | Count
1055  *
1056  */
1057 /*
1058  * Field : Count - cnt
1059  *
1060  * Controls DCLK counter.
1061  *
1062  * Software writes a non-zero value into CNT and the FPGA Manager generates the
1063  * specified number of DCLK pulses and decrements COUNT. This register will read
1064  * back the original value written by software.
1065  *
1066  * Software can write CNT at any time.
1067  *
1068  * Field Access Macros:
1069  *
1070  */
1071 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_DCLKCNT_CNT register field. */
1072 #define ALT_FPGAMGR_DCLKCNT_CNT_LSB 0
1073 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_DCLKCNT_CNT register field. */
1074 #define ALT_FPGAMGR_DCLKCNT_CNT_MSB 31
1075 /* The width in bits of the ALT_FPGAMGR_DCLKCNT_CNT register field. */
1076 #define ALT_FPGAMGR_DCLKCNT_CNT_WIDTH 32
1077 /* The mask used to set the ALT_FPGAMGR_DCLKCNT_CNT register field value. */
1078 #define ALT_FPGAMGR_DCLKCNT_CNT_SET_MSK 0xffffffff
1079 /* The mask used to clear the ALT_FPGAMGR_DCLKCNT_CNT register field value. */
1080 #define ALT_FPGAMGR_DCLKCNT_CNT_CLR_MSK 0x00000000
1081 /* The reset value of the ALT_FPGAMGR_DCLKCNT_CNT register field. */
1082 #define ALT_FPGAMGR_DCLKCNT_CNT_RESET 0x0
1083 /* Extracts the ALT_FPGAMGR_DCLKCNT_CNT field value from a register. */
1084 #define ALT_FPGAMGR_DCLKCNT_CNT_GET(value) (((value) & 0xffffffff) >> 0)
1085 /* Produces a ALT_FPGAMGR_DCLKCNT_CNT register field value suitable for setting the register. */
1086 #define ALT_FPGAMGR_DCLKCNT_CNT_SET(value) (((value) << 0) & 0xffffffff)
1087 
1088 #ifndef __ASSEMBLY__
1089 /*
1090  * WARNING: The C register and register group struct declarations are provided for
1091  * convenience and illustrative purposes. They should, however, be used with
1092  * caution as the C language standard provides no guarantees about the alignment or
1093  * atomicity of device memory accesses. The recommended practice for writing
1094  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1095  * alt_write_word() functions.
1096  *
1097  * The struct declaration for register ALT_FPGAMGR_DCLKCNT.
1098  */
1099 struct ALT_FPGAMGR_DCLKCNT_s
1100 {
1101  uint32_t cnt : 32; /* Count */
1102 };
1103 
1104 /* The typedef declaration for register ALT_FPGAMGR_DCLKCNT. */
1105 typedef volatile struct ALT_FPGAMGR_DCLKCNT_s ALT_FPGAMGR_DCLKCNT_t;
1106 #endif /* __ASSEMBLY__ */
1107 
1108 /* The byte offset of the ALT_FPGAMGR_DCLKCNT register from the beginning of the component. */
1109 #define ALT_FPGAMGR_DCLKCNT_OFST 0x8
1110 
1111 /*
1112  * Register : DCLK Status Register - dclkstat
1113  *
1114  * This write one to clear register indicates that the DCLKCNT has counted down to
1115  * zero. The DCLKCNT is used by software to drive spurious DCLKs to the FPGA.
1116  * Software will poll this bit after writing DCLKCNT to know when all of the DCLKs
1117  * have been sent.
1118  *
1119  * Register Layout
1120  *
1121  * Bits | Access | Reset | Description
1122  * :-------|:-------|:------|:----------------
1123  * [0] | RW | 0x0 | DCLK Count Done
1124  * [31:1] | ??? | 0x0 | *UNDEFINED*
1125  *
1126  */
1127 /*
1128  * Field : DCLK Count Done - dcntdone
1129  *
1130  * This bit is write one to clear. This bit gets set after the DCLKCNT has
1131  * counted down to zero (transition from 1 to 0).
1132  *
1133  * Field Enumeration Values:
1134  *
1135  * Enum | Value | Description
1136  * :----------------------------------------|:------|:--------------------------------
1137  * ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_NOTDONE | 0x0 | DCLKCNT is still counting down.
1138  * ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_DONE | 0x1 | DCLKCNT is done counting down.
1139  *
1140  * Field Access Macros:
1141  *
1142  */
1143 /*
1144  * Enumerated value for register field ALT_FPGAMGR_DCLKSTAT_DCNTDONE
1145  *
1146  * DCLKCNT is still counting down.
1147  */
1148 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_NOTDONE 0x0
1149 /*
1150  * Enumerated value for register field ALT_FPGAMGR_DCLKSTAT_DCNTDONE
1151  *
1152  * DCLKCNT is done counting down.
1153  */
1154 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_DONE 0x1
1155 
1156 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field. */
1157 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_LSB 0
1158 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field. */
1159 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_MSB 0
1160 /* The width in bits of the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field. */
1161 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_WIDTH 1
1162 /* The mask used to set the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field value. */
1163 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_SET_MSK 0x00000001
1164 /* The mask used to clear the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field value. */
1165 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_CLR_MSK 0xfffffffe
1166 /* The reset value of the ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field. */
1167 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_RESET 0x0
1168 /* Extracts the ALT_FPGAMGR_DCLKSTAT_DCNTDONE field value from a register. */
1169 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_GET(value) (((value) & 0x00000001) >> 0)
1170 /* Produces a ALT_FPGAMGR_DCLKSTAT_DCNTDONE register field value suitable for setting the register. */
1171 #define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_SET(value) (((value) << 0) & 0x00000001)
1172 
1173 #ifndef __ASSEMBLY__
1174 /*
1175  * WARNING: The C register and register group struct declarations are provided for
1176  * convenience and illustrative purposes. They should, however, be used with
1177  * caution as the C language standard provides no guarantees about the alignment or
1178  * atomicity of device memory accesses. The recommended practice for writing
1179  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1180  * alt_write_word() functions.
1181  *
1182  * The struct declaration for register ALT_FPGAMGR_DCLKSTAT.
1183  */
1184 struct ALT_FPGAMGR_DCLKSTAT_s
1185 {
1186  uint32_t dcntdone : 1; /* DCLK Count Done */
1187  uint32_t : 31; /* *UNDEFINED* */
1188 };
1189 
1190 /* The typedef declaration for register ALT_FPGAMGR_DCLKSTAT. */
1191 typedef volatile struct ALT_FPGAMGR_DCLKSTAT_s ALT_FPGAMGR_DCLKSTAT_t;
1192 #endif /* __ASSEMBLY__ */
1193 
1194 /* The byte offset of the ALT_FPGAMGR_DCLKSTAT register from the beginning of the component. */
1195 #define ALT_FPGAMGR_DCLKSTAT_OFST 0xc
1196 
1197 /*
1198  * Register : General-Purpose Output Register - gpo
1199  *
1200  * Provides a low-latency, low-performance, and simple way to drive general-purpose
1201  * signals to the FPGA fabric.
1202  *
1203  * Register Layout
1204  *
1205  * Bits | Access | Reset | Description
1206  * :-------|:-------|:------|:------------
1207  * [31:0] | RW | 0x0 | Value
1208  *
1209  */
1210 /*
1211  * Field : Value - value
1212  *
1213  * Drives h2f_gp[31:0] with specified value. When read, returns the current value
1214  * being driven to the FPGA fabric.
1215  *
1216  * Field Access Macros:
1217  *
1218  */
1219 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_GPO_VALUE register field. */
1220 #define ALT_FPGAMGR_GPO_VALUE_LSB 0
1221 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_GPO_VALUE register field. */
1222 #define ALT_FPGAMGR_GPO_VALUE_MSB 31
1223 /* The width in bits of the ALT_FPGAMGR_GPO_VALUE register field. */
1224 #define ALT_FPGAMGR_GPO_VALUE_WIDTH 32
1225 /* The mask used to set the ALT_FPGAMGR_GPO_VALUE register field value. */
1226 #define ALT_FPGAMGR_GPO_VALUE_SET_MSK 0xffffffff
1227 /* The mask used to clear the ALT_FPGAMGR_GPO_VALUE register field value. */
1228 #define ALT_FPGAMGR_GPO_VALUE_CLR_MSK 0x00000000
1229 /* The reset value of the ALT_FPGAMGR_GPO_VALUE register field. */
1230 #define ALT_FPGAMGR_GPO_VALUE_RESET 0x0
1231 /* Extracts the ALT_FPGAMGR_GPO_VALUE field value from a register. */
1232 #define ALT_FPGAMGR_GPO_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
1233 /* Produces a ALT_FPGAMGR_GPO_VALUE register field value suitable for setting the register. */
1234 #define ALT_FPGAMGR_GPO_VALUE_SET(value) (((value) << 0) & 0xffffffff)
1235 
1236 #ifndef __ASSEMBLY__
1237 /*
1238  * WARNING: The C register and register group struct declarations are provided for
1239  * convenience and illustrative purposes. They should, however, be used with
1240  * caution as the C language standard provides no guarantees about the alignment or
1241  * atomicity of device memory accesses. The recommended practice for writing
1242  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1243  * alt_write_word() functions.
1244  *
1245  * The struct declaration for register ALT_FPGAMGR_GPO.
1246  */
1247 struct ALT_FPGAMGR_GPO_s
1248 {
1249  uint32_t value : 32; /* Value */
1250 };
1251 
1252 /* The typedef declaration for register ALT_FPGAMGR_GPO. */
1253 typedef volatile struct ALT_FPGAMGR_GPO_s ALT_FPGAMGR_GPO_t;
1254 #endif /* __ASSEMBLY__ */
1255 
1256 /* The byte offset of the ALT_FPGAMGR_GPO register from the beginning of the component. */
1257 #define ALT_FPGAMGR_GPO_OFST 0x10
1258 
1259 /*
1260  * Register : General-Purpose Input Register - gpi
1261  *
1262  * Provides a low-latency, low-performance, and simple way to read general-purpose
1263  * signals driven from the FPGA fabric.
1264  *
1265  * Register Layout
1266  *
1267  * Bits | Access | Reset | Description
1268  * :-------|:-------|:--------|:------------
1269  * [31:0] | R | Unknown | Value
1270  *
1271  */
1272 /*
1273  * Field : Value - value
1274  *
1275  * The value being driven from the FPGA fabric on f2h_gp[31:0]. If the FPGA is not
1276  * in User Mode, the value of this field is undefined.
1277  *
1278  * Field Access Macros:
1279  *
1280  */
1281 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_GPI_VALUE register field. */
1282 #define ALT_FPGAMGR_GPI_VALUE_LSB 0
1283 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_GPI_VALUE register field. */
1284 #define ALT_FPGAMGR_GPI_VALUE_MSB 31
1285 /* The width in bits of the ALT_FPGAMGR_GPI_VALUE register field. */
1286 #define ALT_FPGAMGR_GPI_VALUE_WIDTH 32
1287 /* The mask used to set the ALT_FPGAMGR_GPI_VALUE register field value. */
1288 #define ALT_FPGAMGR_GPI_VALUE_SET_MSK 0xffffffff
1289 /* The mask used to clear the ALT_FPGAMGR_GPI_VALUE register field value. */
1290 #define ALT_FPGAMGR_GPI_VALUE_CLR_MSK 0x00000000
1291 /* The reset value of the ALT_FPGAMGR_GPI_VALUE register field is UNKNOWN. */
1292 #define ALT_FPGAMGR_GPI_VALUE_RESET 0x0
1293 /* Extracts the ALT_FPGAMGR_GPI_VALUE field value from a register. */
1294 #define ALT_FPGAMGR_GPI_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
1295 /* Produces a ALT_FPGAMGR_GPI_VALUE register field value suitable for setting the register. */
1296 #define ALT_FPGAMGR_GPI_VALUE_SET(value) (((value) << 0) & 0xffffffff)
1297 
1298 #ifndef __ASSEMBLY__
1299 /*
1300  * WARNING: The C register and register group struct declarations are provided for
1301  * convenience and illustrative purposes. They should, however, be used with
1302  * caution as the C language standard provides no guarantees about the alignment or
1303  * atomicity of device memory accesses. The recommended practice for writing
1304  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1305  * alt_write_word() functions.
1306  *
1307  * The struct declaration for register ALT_FPGAMGR_GPI.
1308  */
1309 struct ALT_FPGAMGR_GPI_s
1310 {
1311  const uint32_t value : 32; /* Value */
1312 };
1313 
1314 /* The typedef declaration for register ALT_FPGAMGR_GPI. */
1315 typedef volatile struct ALT_FPGAMGR_GPI_s ALT_FPGAMGR_GPI_t;
1316 #endif /* __ASSEMBLY__ */
1317 
1318 /* The byte offset of the ALT_FPGAMGR_GPI register from the beginning of the component. */
1319 #define ALT_FPGAMGR_GPI_OFST 0x14
1320 
1321 /*
1322  * Register : Miscellaneous Input Register - misci
1323  *
1324  * Provides a low-latency, low-performance, and simple way to read specific
1325  * handshaking signals driven from the FPGA fabric.
1326  *
1327  * Register Layout
1328  *
1329  * Bits | Access | Reset | Description
1330  * :-------|:-------|:--------|:--------------------------
1331  * [0] | R | Unknown | Boot From FPGA on Failure
1332  * [1] | R | Unknown | Boot From FPGA Ready
1333  * [31:2] | ??? | 0x0 | *UNDEFINED*
1334  *
1335  */
1336 /*
1337  * Field : Boot From FPGA on Failure - bootFPGAfail
1338  *
1339  * The value of the f2h_boot_from_fpga_on_failure signal from the FPGA fabric. If
1340  * the FPGA is not in User Mode, the value of this field is undefined.
1341  *
1342  * 1 = Boot ROM will boot from FPGA if boot from normal boot device fails.
1343  *
1344  * 0 = Boot ROM will not boot from FPGA if boot from normal boot device fails.
1345  *
1346  * Field Access Macros:
1347  *
1348  */
1349 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field. */
1350 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_LSB 0
1351 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field. */
1352 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_MSB 0
1353 /* The width in bits of the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field. */
1354 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_WIDTH 1
1355 /* The mask used to set the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field value. */
1356 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_SET_MSK 0x00000001
1357 /* The mask used to clear the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field value. */
1358 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_CLR_MSK 0xfffffffe
1359 /* The reset value of the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field is UNKNOWN. */
1360 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_RESET 0x0
1361 /* Extracts the ALT_FPGAMGR_MISCI_BOOTFPGAFAIL field value from a register. */
1362 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_GET(value) (((value) & 0x00000001) >> 0)
1363 /* Produces a ALT_FPGAMGR_MISCI_BOOTFPGAFAIL register field value suitable for setting the register. */
1364 #define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_SET(value) (((value) << 0) & 0x00000001)
1365 
1366 /*
1367  * Field : Boot From FPGA Ready - bootFPGArdy
1368  *
1369  * The value of the f2h_boot_from_fpga_ready signal from the FPGA fabric. If the
1370  * FPGA is not in User Mode, the value of this field is undefined.
1371  *
1372  * 1 = FPGA fabric is ready to accept AXI master requests from the HPS2FPGA bridge.
1373  *
1374  * 0 = FPGA fabric is not ready (probably still processing a reset).
1375  *
1376  * Field Access Macros:
1377  *
1378  */
1379 /* The Least Significant Bit (LSB) position of the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field. */
1380 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_LSB 1
1381 /* The Most Significant Bit (MSB) position of the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field. */
1382 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_MSB 1
1383 /* The width in bits of the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field. */
1384 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_WIDTH 1
1385 /* The mask used to set the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field value. */
1386 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_SET_MSK 0x00000002
1387 /* The mask used to clear the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field value. */
1388 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_CLR_MSK 0xfffffffd
1389 /* The reset value of the ALT_FPGAMGR_MISCI_BOOTFPGARDY register field is UNKNOWN. */
1390 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_RESET 0x0
1391 /* Extracts the ALT_FPGAMGR_MISCI_BOOTFPGARDY field value from a register. */
1392 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_GET(value) (((value) & 0x00000002) >> 1)
1393 /* Produces a ALT_FPGAMGR_MISCI_BOOTFPGARDY register field value suitable for setting the register. */
1394 #define ALT_FPGAMGR_MISCI_BOOTFPGARDY_SET(value) (((value) << 1) & 0x00000002)
1395 
1396 #ifndef __ASSEMBLY__
1397 /*
1398  * WARNING: The C register and register group struct declarations are provided for
1399  * convenience and illustrative purposes. They should, however, be used with
1400  * caution as the C language standard provides no guarantees about the alignment or
1401  * atomicity of device memory accesses. The recommended practice for writing
1402  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1403  * alt_write_word() functions.
1404  *
1405  * The struct declaration for register ALT_FPGAMGR_MISCI.
1406  */
1407 struct ALT_FPGAMGR_MISCI_s
1408 {
1409  const uint32_t bootFPGAfail : 1; /* Boot From FPGA on Failure */
1410  const uint32_t bootFPGArdy : 1; /* Boot From FPGA Ready */
1411  uint32_t : 30; /* *UNDEFINED* */
1412 };
1413 
1414 /* The typedef declaration for register ALT_FPGAMGR_MISCI. */
1415 typedef volatile struct ALT_FPGAMGR_MISCI_s ALT_FPGAMGR_MISCI_t;
1416 #endif /* __ASSEMBLY__ */
1417 
1418 /* The byte offset of the ALT_FPGAMGR_MISCI register from the beginning of the component. */
1419 #define ALT_FPGAMGR_MISCI_OFST 0x18
1420 
1421 /*
1422  * Register Group : Configuration Monitor (MON) Registers - ALT_MON
1423  * Configuration Monitor (MON) Registers
1424  *
1425  * The Configuration Monitor allows software to poll or be interrupted by changes
1426  * in the FPGA state. The Configuration Monitor is an instantiation of a Synopsys
1427  * GPIO. Only registers relevant to the MON operation are shown.
1428  *
1429  * The GPIO inputs are connected to the following signals:[list][*]nSTATUS - Driven
1430  * to 0 by the FPGA in this device if the FPGA is in Reset Phase or if the FPGA
1431  * detected an error during the Configuration Phase.[*]CONF_DONE - Driven to 0 by
1432  * the FPGA in this device during the Reset Phase and driven to 1 when the FPGA
1433  * Configuration Phase is done.[*]INIT_DONE - Driven to 0 by the FPGA in this
1434  * device during the Configuration Phase and driven to 1 when the FPGA
1435  * Initialization Phase is done.[*]CRC_ERROR - CRC error indicator. A CRC_ERROR
1436  * value of 1 indicates that the FPGA detected a CRC error while in User
1437  * Mode.[*]CVP_CONF_DONE - Configuration via PCIe done indicator. A CVP_CONF_DONE
1438  * value of 1 indicates that CVP is done.[*]PR_READY - Partial reconfiguration
1439  * ready indicator. A PR_READY value of 1 indicates that the FPGA is ready to
1440  * receive partial reconfiguration or external scrubbing data.[*]PR_ERROR - Partial
1441  * reconfiguration error indicator. A PR_ERROR value of 1 indicates that the FPGA
1442  * detected an error during partial reconfiguration or external
1443  * scrubbing.[*]PR_DONE - Partial reconfiguration done indicator. A PR_DONE value
1444  * of 1 indicates partial reconfiguration or external scrubbing is done.[*]nCONFIG
1445  * Pin - Value of the nCONFIG pin. This can be pulled-down by the FPGA in this
1446  * device or logic external to this device connected to the nCONFIG pin. See the
1447  * description of the nCONFIG field in this register to understand when the FPGA in
1448  * this device pulls-down the nCONFIG pin. Logic external to this device pulls-down
1449  * the nCONFIG pin to put the FPGA into the Reset Phase.[*]nSTATUS Pin - Value of
1450  * the nSTATUS pin. This can be pulled-down by the FPGA in this device or logic
1451  * external to this device connected to the nSTATUS pin. See the description of the
1452  * nSTATUS field in this register to understand when the FPGA in this device pulls-
1453  * down the nSTATUS pin. Logic external to this device pulls-down the nSTATUS pin
1454  * during Configuration Phase or Initialization Phase if it detected an
1455  * error.[*]CONF_DONE Pin - Value of the CONF_DONE pin. This can be pulled-down by
1456  * the FPGA in this device or logic external to this device connected to the
1457  * CONF_DONE pin. See the description of the CONF_DONE field in this register to
1458  * understand when the FPGA in this device pulls-down the CONF_DONE pin. See FPGA
1459  * documentation to determine how logic external to this device drives
1460  * CONF_DONE.[*]FPGA_POWER_ON - FPGA powered on indicator
1461  *
1462  * [list][*]0 = FPGA portion of device is powered off.[*]1 = FPGA portion of device
1463  * is powered on.[/list][/list]
1464  *
1465  */
1466 /*
1467  * Register : Interrupt Enable Register - gpio_inten
1468  *
1469  * Allows each bit of Port A to be configured to generate an interrupt or not.
1470  *
1471  * Register Layout
1472  *
1473  * Bits | Access | Reset | Description
1474  * :--------|:-------|:------|:---------------------------------------
1475  * [0] | RW | 0x0 | Interrupt Enable Field (nSTATUS)
1476  * [1] | RW | 0x0 | Interrupt Enable Field (CONF_DONE)
1477  * [2] | RW | 0x0 | Interrupt Enable Field (INIT_DONE)
1478  * [3] | RW | 0x0 | Interrupt Enable Field (CRC_ERROR)
1479  * [4] | RW | 0x0 | Interrupt Enable Field (CVP_CONF_DONE)
1480  * [5] | RW | 0x0 | Interrupt Enable Field (PR_READY)
1481  * [6] | RW | 0x0 | Interrupt Enable Field (PR_ERROR)
1482  * [7] | RW | 0x0 | Interrupt Enable Field (PR_DONE)
1483  * [8] | RW | 0x0 | Interrupt Enable Field (nCONFIG Pin)
1484  * [9] | RW | 0x0 | Interrupt Enable Field (nSTATUS Pin)
1485  * [10] | RW | 0x0 | Interrupt Enable Field (CONF_DONE Pin)
1486  * [11] | RW | 0x0 | Interrupt Enable Field (FPGA_POWER_ON)
1487  * [31:12] | ??? | 0x0 | *UNDEFINED*
1488  *
1489  */
1490 /*
1491  * Field : Interrupt Enable Field (nSTATUS) - ns
1492  *
1493  * Enables interrupt generation for nSTATUS
1494  *
1495  * Field Enumeration Values:
1496  *
1497  * Enum | Value | Description
1498  * :----------------------------|:------|:------------------
1499  * ALT_MON_GPIO_INTEN_NS_E_DIS | 0x0 | Disable Interrupt
1500  * ALT_MON_GPIO_INTEN_NS_E_EN | 0x1 | Enable Interrupt
1501  *
1502  * Field Access Macros:
1503  *
1504  */
1505 /*
1506  * Enumerated value for register field ALT_MON_GPIO_INTEN_NS
1507  *
1508  * Disable Interrupt
1509  */
1510 #define ALT_MON_GPIO_INTEN_NS_E_DIS 0x0
1511 /*
1512  * Enumerated value for register field ALT_MON_GPIO_INTEN_NS
1513  *
1514  * Enable Interrupt
1515  */
1516 #define ALT_MON_GPIO_INTEN_NS_E_EN 0x1
1517 
1518 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_NS register field. */
1519 #define ALT_MON_GPIO_INTEN_NS_LSB 0
1520 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_NS register field. */
1521 #define ALT_MON_GPIO_INTEN_NS_MSB 0
1522 /* The width in bits of the ALT_MON_GPIO_INTEN_NS register field. */
1523 #define ALT_MON_GPIO_INTEN_NS_WIDTH 1
1524 /* The mask used to set the ALT_MON_GPIO_INTEN_NS register field value. */
1525 #define ALT_MON_GPIO_INTEN_NS_SET_MSK 0x00000001
1526 /* The mask used to clear the ALT_MON_GPIO_INTEN_NS register field value. */
1527 #define ALT_MON_GPIO_INTEN_NS_CLR_MSK 0xfffffffe
1528 /* The reset value of the ALT_MON_GPIO_INTEN_NS register field. */
1529 #define ALT_MON_GPIO_INTEN_NS_RESET 0x0
1530 /* Extracts the ALT_MON_GPIO_INTEN_NS field value from a register. */
1531 #define ALT_MON_GPIO_INTEN_NS_GET(value) (((value) & 0x00000001) >> 0)
1532 /* Produces a ALT_MON_GPIO_INTEN_NS register field value suitable for setting the register. */
1533 #define ALT_MON_GPIO_INTEN_NS_SET(value) (((value) << 0) & 0x00000001)
1534 
1535 /*
1536  * Field : Interrupt Enable Field (CONF_DONE) - cd
1537  *
1538  * Enables interrupt generation for CONF_DONE
1539  *
1540  * Field Enumeration Values:
1541  *
1542  * Enum | Value | Description
1543  * :----------------------------|:------|:------------------
1544  * ALT_MON_GPIO_INTEN_CD_E_DIS | 0x0 | Disable Interrupt
1545  * ALT_MON_GPIO_INTEN_CD_E_EN | 0x1 | Enable Interrupt
1546  *
1547  * Field Access Macros:
1548  *
1549  */
1550 /*
1551  * Enumerated value for register field ALT_MON_GPIO_INTEN_CD
1552  *
1553  * Disable Interrupt
1554  */
1555 #define ALT_MON_GPIO_INTEN_CD_E_DIS 0x0
1556 /*
1557  * Enumerated value for register field ALT_MON_GPIO_INTEN_CD
1558  *
1559  * Enable Interrupt
1560  */
1561 #define ALT_MON_GPIO_INTEN_CD_E_EN 0x1
1562 
1563 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_CD register field. */
1564 #define ALT_MON_GPIO_INTEN_CD_LSB 1
1565 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_CD register field. */
1566 #define ALT_MON_GPIO_INTEN_CD_MSB 1
1567 /* The width in bits of the ALT_MON_GPIO_INTEN_CD register field. */
1568 #define ALT_MON_GPIO_INTEN_CD_WIDTH 1
1569 /* The mask used to set the ALT_MON_GPIO_INTEN_CD register field value. */
1570 #define ALT_MON_GPIO_INTEN_CD_SET_MSK 0x00000002
1571 /* The mask used to clear the ALT_MON_GPIO_INTEN_CD register field value. */
1572 #define ALT_MON_GPIO_INTEN_CD_CLR_MSK 0xfffffffd
1573 /* The reset value of the ALT_MON_GPIO_INTEN_CD register field. */
1574 #define ALT_MON_GPIO_INTEN_CD_RESET 0x0
1575 /* Extracts the ALT_MON_GPIO_INTEN_CD field value from a register. */
1576 #define ALT_MON_GPIO_INTEN_CD_GET(value) (((value) & 0x00000002) >> 1)
1577 /* Produces a ALT_MON_GPIO_INTEN_CD register field value suitable for setting the register. */
1578 #define ALT_MON_GPIO_INTEN_CD_SET(value) (((value) << 1) & 0x00000002)
1579 
1580 /*
1581  * Field : Interrupt Enable Field (INIT_DONE) - id
1582  *
1583  * Enables interrupt generation for INIT_DONE
1584  *
1585  * Field Enumeration Values:
1586  *
1587  * Enum | Value | Description
1588  * :----------------------------|:------|:------------------
1589  * ALT_MON_GPIO_INTEN_ID_E_DIS | 0x0 | Disable Interrupt
1590  * ALT_MON_GPIO_INTEN_ID_E_EN | 0x1 | Enable Interrupt
1591  *
1592  * Field Access Macros:
1593  *
1594  */
1595 /*
1596  * Enumerated value for register field ALT_MON_GPIO_INTEN_ID
1597  *
1598  * Disable Interrupt
1599  */
1600 #define ALT_MON_GPIO_INTEN_ID_E_DIS 0x0
1601 /*
1602  * Enumerated value for register field ALT_MON_GPIO_INTEN_ID
1603  *
1604  * Enable Interrupt
1605  */
1606 #define ALT_MON_GPIO_INTEN_ID_E_EN 0x1
1607 
1608 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_ID register field. */
1609 #define ALT_MON_GPIO_INTEN_ID_LSB 2
1610 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_ID register field. */
1611 #define ALT_MON_GPIO_INTEN_ID_MSB 2
1612 /* The width in bits of the ALT_MON_GPIO_INTEN_ID register field. */
1613 #define ALT_MON_GPIO_INTEN_ID_WIDTH 1
1614 /* The mask used to set the ALT_MON_GPIO_INTEN_ID register field value. */
1615 #define ALT_MON_GPIO_INTEN_ID_SET_MSK 0x00000004
1616 /* The mask used to clear the ALT_MON_GPIO_INTEN_ID register field value. */
1617 #define ALT_MON_GPIO_INTEN_ID_CLR_MSK 0xfffffffb
1618 /* The reset value of the ALT_MON_GPIO_INTEN_ID register field. */
1619 #define ALT_MON_GPIO_INTEN_ID_RESET 0x0
1620 /* Extracts the ALT_MON_GPIO_INTEN_ID field value from a register. */
1621 #define ALT_MON_GPIO_INTEN_ID_GET(value) (((value) & 0x00000004) >> 2)
1622 /* Produces a ALT_MON_GPIO_INTEN_ID register field value suitable for setting the register. */
1623 #define ALT_MON_GPIO_INTEN_ID_SET(value) (((value) << 2) & 0x00000004)
1624 
1625 /*
1626  * Field : Interrupt Enable Field (CRC_ERROR) - crc
1627  *
1628  * Enables interrupt generation for CRC_ERROR
1629  *
1630  * Field Enumeration Values:
1631  *
1632  * Enum | Value | Description
1633  * :-----------------------------|:------|:------------------
1634  * ALT_MON_GPIO_INTEN_CRC_E_DIS | 0x0 | Disable Interrupt
1635  * ALT_MON_GPIO_INTEN_CRC_E_EN | 0x1 | Enable Interrupt
1636  *
1637  * Field Access Macros:
1638  *
1639  */
1640 /*
1641  * Enumerated value for register field ALT_MON_GPIO_INTEN_CRC
1642  *
1643  * Disable Interrupt
1644  */
1645 #define ALT_MON_GPIO_INTEN_CRC_E_DIS 0x0
1646 /*
1647  * Enumerated value for register field ALT_MON_GPIO_INTEN_CRC
1648  *
1649  * Enable Interrupt
1650  */
1651 #define ALT_MON_GPIO_INTEN_CRC_E_EN 0x1
1652 
1653 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_CRC register field. */
1654 #define ALT_MON_GPIO_INTEN_CRC_LSB 3
1655 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_CRC register field. */
1656 #define ALT_MON_GPIO_INTEN_CRC_MSB 3
1657 /* The width in bits of the ALT_MON_GPIO_INTEN_CRC register field. */
1658 #define ALT_MON_GPIO_INTEN_CRC_WIDTH 1
1659 /* The mask used to set the ALT_MON_GPIO_INTEN_CRC register field value. */
1660 #define ALT_MON_GPIO_INTEN_CRC_SET_MSK 0x00000008
1661 /* The mask used to clear the ALT_MON_GPIO_INTEN_CRC register field value. */
1662 #define ALT_MON_GPIO_INTEN_CRC_CLR_MSK 0xfffffff7
1663 /* The reset value of the ALT_MON_GPIO_INTEN_CRC register field. */
1664 #define ALT_MON_GPIO_INTEN_CRC_RESET 0x0
1665 /* Extracts the ALT_MON_GPIO_INTEN_CRC field value from a register. */
1666 #define ALT_MON_GPIO_INTEN_CRC_GET(value) (((value) & 0x00000008) >> 3)
1667 /* Produces a ALT_MON_GPIO_INTEN_CRC register field value suitable for setting the register. */
1668 #define ALT_MON_GPIO_INTEN_CRC_SET(value) (((value) << 3) & 0x00000008)
1669 
1670 /*
1671  * Field : Interrupt Enable Field (CVP_CONF_DONE) - ccd
1672  *
1673  * Enables interrupt generation for CVP_CONF_DONE
1674  *
1675  * Field Enumeration Values:
1676  *
1677  * Enum | Value | Description
1678  * :-----------------------------|:------|:------------------
1679  * ALT_MON_GPIO_INTEN_CCD_E_DIS | 0x0 | Disable Interrupt
1680  * ALT_MON_GPIO_INTEN_CCD_E_EN | 0x1 | Enable Interrupt
1681  *
1682  * Field Access Macros:
1683  *
1684  */
1685 /*
1686  * Enumerated value for register field ALT_MON_GPIO_INTEN_CCD
1687  *
1688  * Disable Interrupt
1689  */
1690 #define ALT_MON_GPIO_INTEN_CCD_E_DIS 0x0
1691 /*
1692  * Enumerated value for register field ALT_MON_GPIO_INTEN_CCD
1693  *
1694  * Enable Interrupt
1695  */
1696 #define ALT_MON_GPIO_INTEN_CCD_E_EN 0x1
1697 
1698 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_CCD register field. */
1699 #define ALT_MON_GPIO_INTEN_CCD_LSB 4
1700 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_CCD register field. */
1701 #define ALT_MON_GPIO_INTEN_CCD_MSB 4
1702 /* The width in bits of the ALT_MON_GPIO_INTEN_CCD register field. */
1703 #define ALT_MON_GPIO_INTEN_CCD_WIDTH 1
1704 /* The mask used to set the ALT_MON_GPIO_INTEN_CCD register field value. */
1705 #define ALT_MON_GPIO_INTEN_CCD_SET_MSK 0x00000010
1706 /* The mask used to clear the ALT_MON_GPIO_INTEN_CCD register field value. */
1707 #define ALT_MON_GPIO_INTEN_CCD_CLR_MSK 0xffffffef
1708 /* The reset value of the ALT_MON_GPIO_INTEN_CCD register field. */
1709 #define ALT_MON_GPIO_INTEN_CCD_RESET 0x0
1710 /* Extracts the ALT_MON_GPIO_INTEN_CCD field value from a register. */
1711 #define ALT_MON_GPIO_INTEN_CCD_GET(value) (((value) & 0x00000010) >> 4)
1712 /* Produces a ALT_MON_GPIO_INTEN_CCD register field value suitable for setting the register. */
1713 #define ALT_MON_GPIO_INTEN_CCD_SET(value) (((value) << 4) & 0x00000010)
1714 
1715 /*
1716  * Field : Interrupt Enable Field (PR_READY) - prr
1717  *
1718  * Enables interrupt generation for PR_READY
1719  *
1720  * Field Enumeration Values:
1721  *
1722  * Enum | Value | Description
1723  * :-----------------------------|:------|:------------------
1724  * ALT_MON_GPIO_INTEN_PRR_E_DIS | 0x0 | Disable Interrupt
1725  * ALT_MON_GPIO_INTEN_PRR_E_EN | 0x1 | Enable Interrupt
1726  *
1727  * Field Access Macros:
1728  *
1729  */
1730 /*
1731  * Enumerated value for register field ALT_MON_GPIO_INTEN_PRR
1732  *
1733  * Disable Interrupt
1734  */
1735 #define ALT_MON_GPIO_INTEN_PRR_E_DIS 0x0
1736 /*
1737  * Enumerated value for register field ALT_MON_GPIO_INTEN_PRR
1738  *
1739  * Enable Interrupt
1740  */
1741 #define ALT_MON_GPIO_INTEN_PRR_E_EN 0x1
1742 
1743 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_PRR register field. */
1744 #define ALT_MON_GPIO_INTEN_PRR_LSB 5
1745 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_PRR register field. */
1746 #define ALT_MON_GPIO_INTEN_PRR_MSB 5
1747 /* The width in bits of the ALT_MON_GPIO_INTEN_PRR register field. */
1748 #define ALT_MON_GPIO_INTEN_PRR_WIDTH 1
1749 /* The mask used to set the ALT_MON_GPIO_INTEN_PRR register field value. */
1750 #define ALT_MON_GPIO_INTEN_PRR_SET_MSK 0x00000020
1751 /* The mask used to clear the ALT_MON_GPIO_INTEN_PRR register field value. */
1752 #define ALT_MON_GPIO_INTEN_PRR_CLR_MSK 0xffffffdf
1753 /* The reset value of the ALT_MON_GPIO_INTEN_PRR register field. */
1754 #define ALT_MON_GPIO_INTEN_PRR_RESET 0x0
1755 /* Extracts the ALT_MON_GPIO_INTEN_PRR field value from a register. */
1756 #define ALT_MON_GPIO_INTEN_PRR_GET(value) (((value) & 0x00000020) >> 5)
1757 /* Produces a ALT_MON_GPIO_INTEN_PRR register field value suitable for setting the register. */
1758 #define ALT_MON_GPIO_INTEN_PRR_SET(value) (((value) << 5) & 0x00000020)
1759 
1760 /*
1761  * Field : Interrupt Enable Field (PR_ERROR) - pre
1762  *
1763  * Enables interrupt generation for PR_ERROR
1764  *
1765  * Field Enumeration Values:
1766  *
1767  * Enum | Value | Description
1768  * :-----------------------------|:------|:------------------
1769  * ALT_MON_GPIO_INTEN_PRE_E_DIS | 0x0 | Disable Interrupt
1770  * ALT_MON_GPIO_INTEN_PRE_E_EN | 0x1 | Enable Interrupt
1771  *
1772  * Field Access Macros:
1773  *
1774  */
1775 /*
1776  * Enumerated value for register field ALT_MON_GPIO_INTEN_PRE
1777  *
1778  * Disable Interrupt
1779  */
1780 #define ALT_MON_GPIO_INTEN_PRE_E_DIS 0x0
1781 /*
1782  * Enumerated value for register field ALT_MON_GPIO_INTEN_PRE
1783  *
1784  * Enable Interrupt
1785  */
1786 #define ALT_MON_GPIO_INTEN_PRE_E_EN 0x1
1787 
1788 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_PRE register field. */
1789 #define ALT_MON_GPIO_INTEN_PRE_LSB 6
1790 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_PRE register field. */
1791 #define ALT_MON_GPIO_INTEN_PRE_MSB 6
1792 /* The width in bits of the ALT_MON_GPIO_INTEN_PRE register field. */
1793 #define ALT_MON_GPIO_INTEN_PRE_WIDTH 1
1794 /* The mask used to set the ALT_MON_GPIO_INTEN_PRE register field value. */
1795 #define ALT_MON_GPIO_INTEN_PRE_SET_MSK 0x00000040
1796 /* The mask used to clear the ALT_MON_GPIO_INTEN_PRE register field value. */
1797 #define ALT_MON_GPIO_INTEN_PRE_CLR_MSK 0xffffffbf
1798 /* The reset value of the ALT_MON_GPIO_INTEN_PRE register field. */
1799 #define ALT_MON_GPIO_INTEN_PRE_RESET 0x0
1800 /* Extracts the ALT_MON_GPIO_INTEN_PRE field value from a register. */
1801 #define ALT_MON_GPIO_INTEN_PRE_GET(value) (((value) & 0x00000040) >> 6)
1802 /* Produces a ALT_MON_GPIO_INTEN_PRE register field value suitable for setting the register. */
1803 #define ALT_MON_GPIO_INTEN_PRE_SET(value) (((value) << 6) & 0x00000040)
1804 
1805 /*
1806  * Field : Interrupt Enable Field (PR_DONE) - prd
1807  *
1808  * Enables interrupt generation for PR_DONE
1809  *
1810  * Field Enumeration Values:
1811  *
1812  * Enum | Value | Description
1813  * :-----------------------------|:------|:------------------
1814  * ALT_MON_GPIO_INTEN_PRD_E_DIS | 0x0 | Disable Interrupt
1815  * ALT_MON_GPIO_INTEN_PRD_E_EN | 0x1 | Enable Interrupt
1816  *
1817  * Field Access Macros:
1818  *
1819  */
1820 /*
1821  * Enumerated value for register field ALT_MON_GPIO_INTEN_PRD
1822  *
1823  * Disable Interrupt
1824  */
1825 #define ALT_MON_GPIO_INTEN_PRD_E_DIS 0x0
1826 /*
1827  * Enumerated value for register field ALT_MON_GPIO_INTEN_PRD
1828  *
1829  * Enable Interrupt
1830  */
1831 #define ALT_MON_GPIO_INTEN_PRD_E_EN 0x1
1832 
1833 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_PRD register field. */
1834 #define ALT_MON_GPIO_INTEN_PRD_LSB 7
1835 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_PRD register field. */
1836 #define ALT_MON_GPIO_INTEN_PRD_MSB 7
1837 /* The width in bits of the ALT_MON_GPIO_INTEN_PRD register field. */
1838 #define ALT_MON_GPIO_INTEN_PRD_WIDTH 1
1839 /* The mask used to set the ALT_MON_GPIO_INTEN_PRD register field value. */
1840 #define ALT_MON_GPIO_INTEN_PRD_SET_MSK 0x00000080
1841 /* The mask used to clear the ALT_MON_GPIO_INTEN_PRD register field value. */
1842 #define ALT_MON_GPIO_INTEN_PRD_CLR_MSK 0xffffff7f
1843 /* The reset value of the ALT_MON_GPIO_INTEN_PRD register field. */
1844 #define ALT_MON_GPIO_INTEN_PRD_RESET 0x0
1845 /* Extracts the ALT_MON_GPIO_INTEN_PRD field value from a register. */
1846 #define ALT_MON_GPIO_INTEN_PRD_GET(value) (((value) & 0x00000080) >> 7)
1847 /* Produces a ALT_MON_GPIO_INTEN_PRD register field value suitable for setting the register. */
1848 #define ALT_MON_GPIO_INTEN_PRD_SET(value) (((value) << 7) & 0x00000080)
1849 
1850 /*
1851  * Field : Interrupt Enable Field (nCONFIG Pin) - ncp
1852  *
1853  * Enables interrupt generation for nCONFIG Pin
1854  *
1855  * Field Enumeration Values:
1856  *
1857  * Enum | Value | Description
1858  * :-----------------------------|:------|:------------------
1859  * ALT_MON_GPIO_INTEN_NCP_E_DIS | 0x0 | Disable Interrupt
1860  * ALT_MON_GPIO_INTEN_NCP_E_EN | 0x1 | Enable Interrupt
1861  *
1862  * Field Access Macros:
1863  *
1864  */
1865 /*
1866  * Enumerated value for register field ALT_MON_GPIO_INTEN_NCP
1867  *
1868  * Disable Interrupt
1869  */
1870 #define ALT_MON_GPIO_INTEN_NCP_E_DIS 0x0
1871 /*
1872  * Enumerated value for register field ALT_MON_GPIO_INTEN_NCP
1873  *
1874  * Enable Interrupt
1875  */
1876 #define ALT_MON_GPIO_INTEN_NCP_E_EN 0x1
1877 
1878 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_NCP register field. */
1879 #define ALT_MON_GPIO_INTEN_NCP_LSB 8
1880 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_NCP register field. */
1881 #define ALT_MON_GPIO_INTEN_NCP_MSB 8
1882 /* The width in bits of the ALT_MON_GPIO_INTEN_NCP register field. */
1883 #define ALT_MON_GPIO_INTEN_NCP_WIDTH 1
1884 /* The mask used to set the ALT_MON_GPIO_INTEN_NCP register field value. */
1885 #define ALT_MON_GPIO_INTEN_NCP_SET_MSK 0x00000100
1886 /* The mask used to clear the ALT_MON_GPIO_INTEN_NCP register field value. */
1887 #define ALT_MON_GPIO_INTEN_NCP_CLR_MSK 0xfffffeff
1888 /* The reset value of the ALT_MON_GPIO_INTEN_NCP register field. */
1889 #define ALT_MON_GPIO_INTEN_NCP_RESET 0x0
1890 /* Extracts the ALT_MON_GPIO_INTEN_NCP field value from a register. */
1891 #define ALT_MON_GPIO_INTEN_NCP_GET(value) (((value) & 0x00000100) >> 8)
1892 /* Produces a ALT_MON_GPIO_INTEN_NCP register field value suitable for setting the register. */
1893 #define ALT_MON_GPIO_INTEN_NCP_SET(value) (((value) << 8) & 0x00000100)
1894 
1895 /*
1896  * Field : Interrupt Enable Field (nSTATUS Pin) - nsp
1897  *
1898  * Enables interrupt generation for nSTATUS Pin
1899  *
1900  * Field Enumeration Values:
1901  *
1902  * Enum | Value | Description
1903  * :-----------------------------|:------|:------------------
1904  * ALT_MON_GPIO_INTEN_NSP_E_DIS | 0x0 | Disable Interrupt
1905  * ALT_MON_GPIO_INTEN_NSP_E_EN | 0x1 | Enable Interrupt
1906  *
1907  * Field Access Macros:
1908  *
1909  */
1910 /*
1911  * Enumerated value for register field ALT_MON_GPIO_INTEN_NSP
1912  *
1913  * Disable Interrupt
1914  */
1915 #define ALT_MON_GPIO_INTEN_NSP_E_DIS 0x0
1916 /*
1917  * Enumerated value for register field ALT_MON_GPIO_INTEN_NSP
1918  *
1919  * Enable Interrupt
1920  */
1921 #define ALT_MON_GPIO_INTEN_NSP_E_EN 0x1
1922 
1923 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_NSP register field. */
1924 #define ALT_MON_GPIO_INTEN_NSP_LSB 9
1925 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_NSP register field. */
1926 #define ALT_MON_GPIO_INTEN_NSP_MSB 9
1927 /* The width in bits of the ALT_MON_GPIO_INTEN_NSP register field. */
1928 #define ALT_MON_GPIO_INTEN_NSP_WIDTH 1
1929 /* The mask used to set the ALT_MON_GPIO_INTEN_NSP register field value. */
1930 #define ALT_MON_GPIO_INTEN_NSP_SET_MSK 0x00000200
1931 /* The mask used to clear the ALT_MON_GPIO_INTEN_NSP register field value. */
1932 #define ALT_MON_GPIO_INTEN_NSP_CLR_MSK 0xfffffdff
1933 /* The reset value of the ALT_MON_GPIO_INTEN_NSP register field. */
1934 #define ALT_MON_GPIO_INTEN_NSP_RESET 0x0
1935 /* Extracts the ALT_MON_GPIO_INTEN_NSP field value from a register. */
1936 #define ALT_MON_GPIO_INTEN_NSP_GET(value) (((value) & 0x00000200) >> 9)
1937 /* Produces a ALT_MON_GPIO_INTEN_NSP register field value suitable for setting the register. */
1938 #define ALT_MON_GPIO_INTEN_NSP_SET(value) (((value) << 9) & 0x00000200)
1939 
1940 /*
1941  * Field : Interrupt Enable Field (CONF_DONE Pin) - cdp
1942  *
1943  * Enables interrupt generation for CONF_DONE Pin
1944  *
1945  * Field Enumeration Values:
1946  *
1947  * Enum | Value | Description
1948  * :-----------------------------|:------|:------------------
1949  * ALT_MON_GPIO_INTEN_CDP_E_DIS | 0x0 | Disable Interrupt
1950  * ALT_MON_GPIO_INTEN_CDP_E_EN | 0x1 | Enable Interrupt
1951  *
1952  * Field Access Macros:
1953  *
1954  */
1955 /*
1956  * Enumerated value for register field ALT_MON_GPIO_INTEN_CDP
1957  *
1958  * Disable Interrupt
1959  */
1960 #define ALT_MON_GPIO_INTEN_CDP_E_DIS 0x0
1961 /*
1962  * Enumerated value for register field ALT_MON_GPIO_INTEN_CDP
1963  *
1964  * Enable Interrupt
1965  */
1966 #define ALT_MON_GPIO_INTEN_CDP_E_EN 0x1
1967 
1968 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_CDP register field. */
1969 #define ALT_MON_GPIO_INTEN_CDP_LSB 10
1970 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_CDP register field. */
1971 #define ALT_MON_GPIO_INTEN_CDP_MSB 10
1972 /* The width in bits of the ALT_MON_GPIO_INTEN_CDP register field. */
1973 #define ALT_MON_GPIO_INTEN_CDP_WIDTH 1
1974 /* The mask used to set the ALT_MON_GPIO_INTEN_CDP register field value. */
1975 #define ALT_MON_GPIO_INTEN_CDP_SET_MSK 0x00000400
1976 /* The mask used to clear the ALT_MON_GPIO_INTEN_CDP register field value. */
1977 #define ALT_MON_GPIO_INTEN_CDP_CLR_MSK 0xfffffbff
1978 /* The reset value of the ALT_MON_GPIO_INTEN_CDP register field. */
1979 #define ALT_MON_GPIO_INTEN_CDP_RESET 0x0
1980 /* Extracts the ALT_MON_GPIO_INTEN_CDP field value from a register. */
1981 #define ALT_MON_GPIO_INTEN_CDP_GET(value) (((value) & 0x00000400) >> 10)
1982 /* Produces a ALT_MON_GPIO_INTEN_CDP register field value suitable for setting the register. */
1983 #define ALT_MON_GPIO_INTEN_CDP_SET(value) (((value) << 10) & 0x00000400)
1984 
1985 /*
1986  * Field : Interrupt Enable Field (FPGA_POWER_ON) - fpo
1987  *
1988  * Enables interrupt generation for FPGA_POWER_ON
1989  *
1990  * Field Enumeration Values:
1991  *
1992  * Enum | Value | Description
1993  * :-----------------------------|:------|:------------------
1994  * ALT_MON_GPIO_INTEN_FPO_E_DIS | 0x0 | Disable Interrupt
1995  * ALT_MON_GPIO_INTEN_FPO_E_EN | 0x1 | Enable Interrupt
1996  *
1997  * Field Access Macros:
1998  *
1999  */
2000 /*
2001  * Enumerated value for register field ALT_MON_GPIO_INTEN_FPO
2002  *
2003  * Disable Interrupt
2004  */
2005 #define ALT_MON_GPIO_INTEN_FPO_E_DIS 0x0
2006 /*
2007  * Enumerated value for register field ALT_MON_GPIO_INTEN_FPO
2008  *
2009  * Enable Interrupt
2010  */
2011 #define ALT_MON_GPIO_INTEN_FPO_E_EN 0x1
2012 
2013 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTEN_FPO register field. */
2014 #define ALT_MON_GPIO_INTEN_FPO_LSB 11
2015 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTEN_FPO register field. */
2016 #define ALT_MON_GPIO_INTEN_FPO_MSB 11
2017 /* The width in bits of the ALT_MON_GPIO_INTEN_FPO register field. */
2018 #define ALT_MON_GPIO_INTEN_FPO_WIDTH 1
2019 /* The mask used to set the ALT_MON_GPIO_INTEN_FPO register field value. */
2020 #define ALT_MON_GPIO_INTEN_FPO_SET_MSK 0x00000800
2021 /* The mask used to clear the ALT_MON_GPIO_INTEN_FPO register field value. */
2022 #define ALT_MON_GPIO_INTEN_FPO_CLR_MSK 0xfffff7ff
2023 /* The reset value of the ALT_MON_GPIO_INTEN_FPO register field. */
2024 #define ALT_MON_GPIO_INTEN_FPO_RESET 0x0
2025 /* Extracts the ALT_MON_GPIO_INTEN_FPO field value from a register. */
2026 #define ALT_MON_GPIO_INTEN_FPO_GET(value) (((value) & 0x00000800) >> 11)
2027 /* Produces a ALT_MON_GPIO_INTEN_FPO register field value suitable for setting the register. */
2028 #define ALT_MON_GPIO_INTEN_FPO_SET(value) (((value) << 11) & 0x00000800)
2029 
2030 #ifndef __ASSEMBLY__
2031 /*
2032  * WARNING: The C register and register group struct declarations are provided for
2033  * convenience and illustrative purposes. They should, however, be used with
2034  * caution as the C language standard provides no guarantees about the alignment or
2035  * atomicity of device memory accesses. The recommended practice for writing
2036  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2037  * alt_write_word() functions.
2038  *
2039  * The struct declaration for register ALT_MON_GPIO_INTEN.
2040  */
2041 struct ALT_MON_GPIO_INTEN_s
2042 {
2043  uint32_t ns : 1; /* Interrupt Enable Field (nSTATUS) */
2044  uint32_t cd : 1; /* Interrupt Enable Field (CONF_DONE) */
2045  uint32_t id : 1; /* Interrupt Enable Field (INIT_DONE) */
2046  uint32_t crc : 1; /* Interrupt Enable Field (CRC_ERROR) */
2047  uint32_t ccd : 1; /* Interrupt Enable Field (CVP_CONF_DONE) */
2048  uint32_t prr : 1; /* Interrupt Enable Field (PR_READY) */
2049  uint32_t pre : 1; /* Interrupt Enable Field (PR_ERROR) */
2050  uint32_t prd : 1; /* Interrupt Enable Field (PR_DONE) */
2051  uint32_t ncp : 1; /* Interrupt Enable Field (nCONFIG Pin) */
2052  uint32_t nsp : 1; /* Interrupt Enable Field (nSTATUS Pin) */
2053  uint32_t cdp : 1; /* Interrupt Enable Field (CONF_DONE Pin) */
2054  uint32_t fpo : 1; /* Interrupt Enable Field (FPGA_POWER_ON) */
2055  uint32_t : 20; /* *UNDEFINED* */
2056 };
2057 
2058 /* The typedef declaration for register ALT_MON_GPIO_INTEN. */
2059 typedef volatile struct ALT_MON_GPIO_INTEN_s ALT_MON_GPIO_INTEN_t;
2060 #endif /* __ASSEMBLY__ */
2061 
2062 /* The byte offset of the ALT_MON_GPIO_INTEN register from the beginning of the component. */
2063 #define ALT_MON_GPIO_INTEN_OFST 0x30
2064 /* The address of the ALT_MON_GPIO_INTEN register. */
2065 #define ALT_MON_GPIO_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_INTEN_OFST))
2066 
2067 /*
2068  * Register : Interrupt Mask Register - gpio_intmask
2069  *
2070  * This register has 12 individual interrupt masks for the MON. Controls whether an
2071  * interrupt on Port A can create an interrupt for the interrupt controller by not
2072  * masking it. By default, all interrupts bits are unmasked. Whenever a 1 is
2073  * written to a bit in this register, it masks the interrupt generation capability
2074  * for this signal; otherwise interrupts are allowed through. The unmasked status
2075  * can be read as well as the resultant status after masking.
2076  *
2077  * Register Layout
2078  *
2079  * Bits | Access | Reset | Description
2080  * :--------|:-------|:------|:-------------------------------------
2081  * [0] | RW | 0x0 | Interrupt Mask Field (nSTATUS)
2082  * [1] | RW | 0x0 | Interrupt Mask Field (CONF_DONE)
2083  * [2] | RW | 0x0 | Interrupt Mask Field (INIT_DONE)
2084  * [3] | RW | 0x0 | Interrupt Mask Field (CRC_ERROR)
2085  * [4] | RW | 0x0 | Interrupt Mask Field (CVP_CONF_DONE)
2086  * [5] | RW | 0x0 | Interrupt Mask Field (PR_READY)
2087  * [6] | RW | 0x0 | Interrupt Mask Field (PR_ERROR)
2088  * [7] | RW | 0x0 | Interrupt Mask Field (PR_DONE)
2089  * [8] | RW | 0x0 | Interrupt Mask Field (nCONFIG Pin)
2090  * [9] | RW | 0x0 | Interrupt Mask Field (nSTATUS Pin)
2091  * [10] | RW | 0x0 | Interrupt Mask Field (CONF_DONE Pin)
2092  * [11] | RW | 0x0 | Interrupt Mask Field (FPGA_POWER_ON)
2093  * [31:12] | ??? | 0x0 | *UNDEFINED*
2094  *
2095  */
2096 /*
2097  * Field : Interrupt Mask Field (nSTATUS) - ns
2098  *
2099  * Controls whether an interrupt for nSTATUS can generate an interrupt to the
2100  * interrupt controller by not masking it. The unmasked status can be read as well
2101  * as the resultant status after masking.
2102  *
2103  * Field Enumeration Values:
2104  *
2105  * Enum | Value | Description
2106  * :-----------------------------|:------|:-----------------
2107  * ALT_MON_GPIO_INTMSK_NS_E_DIS | 0x0 | Unmask Interrupt
2108  * ALT_MON_GPIO_INTMSK_NS_E_EN | 0x1 | Mask Interrupt
2109  *
2110  * Field Access Macros:
2111  *
2112  */
2113 /*
2114  * Enumerated value for register field ALT_MON_GPIO_INTMSK_NS
2115  *
2116  * Unmask Interrupt
2117  */
2118 #define ALT_MON_GPIO_INTMSK_NS_E_DIS 0x0
2119 /*
2120  * Enumerated value for register field ALT_MON_GPIO_INTMSK_NS
2121  *
2122  * Mask Interrupt
2123  */
2124 #define ALT_MON_GPIO_INTMSK_NS_E_EN 0x1
2125 
2126 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_NS register field. */
2127 #define ALT_MON_GPIO_INTMSK_NS_LSB 0
2128 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_NS register field. */
2129 #define ALT_MON_GPIO_INTMSK_NS_MSB 0
2130 /* The width in bits of the ALT_MON_GPIO_INTMSK_NS register field. */
2131 #define ALT_MON_GPIO_INTMSK_NS_WIDTH 1
2132 /* The mask used to set the ALT_MON_GPIO_INTMSK_NS register field value. */
2133 #define ALT_MON_GPIO_INTMSK_NS_SET_MSK 0x00000001
2134 /* The mask used to clear the ALT_MON_GPIO_INTMSK_NS register field value. */
2135 #define ALT_MON_GPIO_INTMSK_NS_CLR_MSK 0xfffffffe
2136 /* The reset value of the ALT_MON_GPIO_INTMSK_NS register field. */
2137 #define ALT_MON_GPIO_INTMSK_NS_RESET 0x0
2138 /* Extracts the ALT_MON_GPIO_INTMSK_NS field value from a register. */
2139 #define ALT_MON_GPIO_INTMSK_NS_GET(value) (((value) & 0x00000001) >> 0)
2140 /* Produces a ALT_MON_GPIO_INTMSK_NS register field value suitable for setting the register. */
2141 #define ALT_MON_GPIO_INTMSK_NS_SET(value) (((value) << 0) & 0x00000001)
2142 
2143 /*
2144  * Field : Interrupt Mask Field (CONF_DONE) - cd
2145  *
2146  * Controls whether an interrupt for CONF_DONE can generate an interrupt to the
2147  * interrupt controller by not masking it. The unmasked status can be read as well
2148  * as the resultant status after masking.
2149  *
2150  * Field Enumeration Values:
2151  *
2152  * Enum | Value | Description
2153  * :-----------------------------|:------|:-----------------
2154  * ALT_MON_GPIO_INTMSK_CD_E_DIS | 0x0 | Unmask Interrupt
2155  * ALT_MON_GPIO_INTMSK_CD_E_EN | 0x1 | Mask Interrupt
2156  *
2157  * Field Access Macros:
2158  *
2159  */
2160 /*
2161  * Enumerated value for register field ALT_MON_GPIO_INTMSK_CD
2162  *
2163  * Unmask Interrupt
2164  */
2165 #define ALT_MON_GPIO_INTMSK_CD_E_DIS 0x0
2166 /*
2167  * Enumerated value for register field ALT_MON_GPIO_INTMSK_CD
2168  *
2169  * Mask Interrupt
2170  */
2171 #define ALT_MON_GPIO_INTMSK_CD_E_EN 0x1
2172 
2173 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_CD register field. */
2174 #define ALT_MON_GPIO_INTMSK_CD_LSB 1
2175 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_CD register field. */
2176 #define ALT_MON_GPIO_INTMSK_CD_MSB 1
2177 /* The width in bits of the ALT_MON_GPIO_INTMSK_CD register field. */
2178 #define ALT_MON_GPIO_INTMSK_CD_WIDTH 1
2179 /* The mask used to set the ALT_MON_GPIO_INTMSK_CD register field value. */
2180 #define ALT_MON_GPIO_INTMSK_CD_SET_MSK 0x00000002
2181 /* The mask used to clear the ALT_MON_GPIO_INTMSK_CD register field value. */
2182 #define ALT_MON_GPIO_INTMSK_CD_CLR_MSK 0xfffffffd
2183 /* The reset value of the ALT_MON_GPIO_INTMSK_CD register field. */
2184 #define ALT_MON_GPIO_INTMSK_CD_RESET 0x0
2185 /* Extracts the ALT_MON_GPIO_INTMSK_CD field value from a register. */
2186 #define ALT_MON_GPIO_INTMSK_CD_GET(value) (((value) & 0x00000002) >> 1)
2187 /* Produces a ALT_MON_GPIO_INTMSK_CD register field value suitable for setting the register. */
2188 #define ALT_MON_GPIO_INTMSK_CD_SET(value) (((value) << 1) & 0x00000002)
2189 
2190 /*
2191  * Field : Interrupt Mask Field (INIT_DONE) - id
2192  *
2193  * Controls whether an interrupt for INIT_DONE can generate an interrupt to the
2194  * interrupt controller by not masking it. The unmasked status can be read as well
2195  * as the resultant status after masking.
2196  *
2197  * Field Enumeration Values:
2198  *
2199  * Enum | Value | Description
2200  * :-----------------------------|:------|:-----------------
2201  * ALT_MON_GPIO_INTMSK_ID_E_DIS | 0x0 | Unmask Interrupt
2202  * ALT_MON_GPIO_INTMSK_ID_E_EN | 0x1 | Mask Interrupt
2203  *
2204  * Field Access Macros:
2205  *
2206  */
2207 /*
2208  * Enumerated value for register field ALT_MON_GPIO_INTMSK_ID
2209  *
2210  * Unmask Interrupt
2211  */
2212 #define ALT_MON_GPIO_INTMSK_ID_E_DIS 0x0
2213 /*
2214  * Enumerated value for register field ALT_MON_GPIO_INTMSK_ID
2215  *
2216  * Mask Interrupt
2217  */
2218 #define ALT_MON_GPIO_INTMSK_ID_E_EN 0x1
2219 
2220 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_ID register field. */
2221 #define ALT_MON_GPIO_INTMSK_ID_LSB 2
2222 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_ID register field. */
2223 #define ALT_MON_GPIO_INTMSK_ID_MSB 2
2224 /* The width in bits of the ALT_MON_GPIO_INTMSK_ID register field. */
2225 #define ALT_MON_GPIO_INTMSK_ID_WIDTH 1
2226 /* The mask used to set the ALT_MON_GPIO_INTMSK_ID register field value. */
2227 #define ALT_MON_GPIO_INTMSK_ID_SET_MSK 0x00000004
2228 /* The mask used to clear the ALT_MON_GPIO_INTMSK_ID register field value. */
2229 #define ALT_MON_GPIO_INTMSK_ID_CLR_MSK 0xfffffffb
2230 /* The reset value of the ALT_MON_GPIO_INTMSK_ID register field. */
2231 #define ALT_MON_GPIO_INTMSK_ID_RESET 0x0
2232 /* Extracts the ALT_MON_GPIO_INTMSK_ID field value from a register. */
2233 #define ALT_MON_GPIO_INTMSK_ID_GET(value) (((value) & 0x00000004) >> 2)
2234 /* Produces a ALT_MON_GPIO_INTMSK_ID register field value suitable for setting the register. */
2235 #define ALT_MON_GPIO_INTMSK_ID_SET(value) (((value) << 2) & 0x00000004)
2236 
2237 /*
2238  * Field : Interrupt Mask Field (CRC_ERROR) - crc
2239  *
2240  * Controls whether an interrupt for CRC_ERROR can generate an interrupt to the
2241  * interrupt controller by not masking it. The unmasked status can be read as well
2242  * as the resultant status after masking.
2243  *
2244  * Field Enumeration Values:
2245  *
2246  * Enum | Value | Description
2247  * :------------------------------|:------|:-----------------
2248  * ALT_MON_GPIO_INTMSK_CRC_E_DIS | 0x0 | Unmask Interrupt
2249  * ALT_MON_GPIO_INTMSK_CRC_E_EN | 0x1 | Mask Interrupt
2250  *
2251  * Field Access Macros:
2252  *
2253  */
2254 /*
2255  * Enumerated value for register field ALT_MON_GPIO_INTMSK_CRC
2256  *
2257  * Unmask Interrupt
2258  */
2259 #define ALT_MON_GPIO_INTMSK_CRC_E_DIS 0x0
2260 /*
2261  * Enumerated value for register field ALT_MON_GPIO_INTMSK_CRC
2262  *
2263  * Mask Interrupt
2264  */
2265 #define ALT_MON_GPIO_INTMSK_CRC_E_EN 0x1
2266 
2267 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_CRC register field. */
2268 #define ALT_MON_GPIO_INTMSK_CRC_LSB 3
2269 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_CRC register field. */
2270 #define ALT_MON_GPIO_INTMSK_CRC_MSB 3
2271 /* The width in bits of the ALT_MON_GPIO_INTMSK_CRC register field. */
2272 #define ALT_MON_GPIO_INTMSK_CRC_WIDTH 1
2273 /* The mask used to set the ALT_MON_GPIO_INTMSK_CRC register field value. */
2274 #define ALT_MON_GPIO_INTMSK_CRC_SET_MSK 0x00000008
2275 /* The mask used to clear the ALT_MON_GPIO_INTMSK_CRC register field value. */
2276 #define ALT_MON_GPIO_INTMSK_CRC_CLR_MSK 0xfffffff7
2277 /* The reset value of the ALT_MON_GPIO_INTMSK_CRC register field. */
2278 #define ALT_MON_GPIO_INTMSK_CRC_RESET 0x0
2279 /* Extracts the ALT_MON_GPIO_INTMSK_CRC field value from a register. */
2280 #define ALT_MON_GPIO_INTMSK_CRC_GET(value) (((value) & 0x00000008) >> 3)
2281 /* Produces a ALT_MON_GPIO_INTMSK_CRC register field value suitable for setting the register. */
2282 #define ALT_MON_GPIO_INTMSK_CRC_SET(value) (((value) << 3) & 0x00000008)
2283 
2284 /*
2285  * Field : Interrupt Mask Field (CVP_CONF_DONE) - ccd
2286  *
2287  * Controls whether an interrupt for CVP_CONF_DONE can generate an interrupt to the
2288  * interrupt controller by not masking it. The unmasked status can be read as well
2289  * as the resultant status after masking.
2290  *
2291  * Field Enumeration Values:
2292  *
2293  * Enum | Value | Description
2294  * :------------------------------|:------|:-----------------
2295  * ALT_MON_GPIO_INTMSK_CCD_E_DIS | 0x0 | Unmask Interrupt
2296  * ALT_MON_GPIO_INTMSK_CCD_E_EN | 0x1 | Mask Interrupt
2297  *
2298  * Field Access Macros:
2299  *
2300  */
2301 /*
2302  * Enumerated value for register field ALT_MON_GPIO_INTMSK_CCD
2303  *
2304  * Unmask Interrupt
2305  */
2306 #define ALT_MON_GPIO_INTMSK_CCD_E_DIS 0x0
2307 /*
2308  * Enumerated value for register field ALT_MON_GPIO_INTMSK_CCD
2309  *
2310  * Mask Interrupt
2311  */
2312 #define ALT_MON_GPIO_INTMSK_CCD_E_EN 0x1
2313 
2314 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_CCD register field. */
2315 #define ALT_MON_GPIO_INTMSK_CCD_LSB 4
2316 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_CCD register field. */
2317 #define ALT_MON_GPIO_INTMSK_CCD_MSB 4
2318 /* The width in bits of the ALT_MON_GPIO_INTMSK_CCD register field. */
2319 #define ALT_MON_GPIO_INTMSK_CCD_WIDTH 1
2320 /* The mask used to set the ALT_MON_GPIO_INTMSK_CCD register field value. */
2321 #define ALT_MON_GPIO_INTMSK_CCD_SET_MSK 0x00000010
2322 /* The mask used to clear the ALT_MON_GPIO_INTMSK_CCD register field value. */
2323 #define ALT_MON_GPIO_INTMSK_CCD_CLR_MSK 0xffffffef
2324 /* The reset value of the ALT_MON_GPIO_INTMSK_CCD register field. */
2325 #define ALT_MON_GPIO_INTMSK_CCD_RESET 0x0
2326 /* Extracts the ALT_MON_GPIO_INTMSK_CCD field value from a register. */
2327 #define ALT_MON_GPIO_INTMSK_CCD_GET(value) (((value) & 0x00000010) >> 4)
2328 /* Produces a ALT_MON_GPIO_INTMSK_CCD register field value suitable for setting the register. */
2329 #define ALT_MON_GPIO_INTMSK_CCD_SET(value) (((value) << 4) & 0x00000010)
2330 
2331 /*
2332  * Field : Interrupt Mask Field (PR_READY) - prr
2333  *
2334  * Controls whether an interrupt for PR_READY can generate an interrupt to the
2335  * interrupt controller by not masking it. The unmasked status can be read as well
2336  * as the resultant status after masking.
2337  *
2338  * Field Enumeration Values:
2339  *
2340  * Enum | Value | Description
2341  * :------------------------------|:------|:-----------------
2342  * ALT_MON_GPIO_INTMSK_PRR_E_DIS | 0x0 | Unmask Interrupt
2343  * ALT_MON_GPIO_INTMSK_PRR_E_EN | 0x1 | Mask Interrupt
2344  *
2345  * Field Access Macros:
2346  *
2347  */
2348 /*
2349  * Enumerated value for register field ALT_MON_GPIO_INTMSK_PRR
2350  *
2351  * Unmask Interrupt
2352  */
2353 #define ALT_MON_GPIO_INTMSK_PRR_E_DIS 0x0
2354 /*
2355  * Enumerated value for register field ALT_MON_GPIO_INTMSK_PRR
2356  *
2357  * Mask Interrupt
2358  */
2359 #define ALT_MON_GPIO_INTMSK_PRR_E_EN 0x1
2360 
2361 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_PRR register field. */
2362 #define ALT_MON_GPIO_INTMSK_PRR_LSB 5
2363 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_PRR register field. */
2364 #define ALT_MON_GPIO_INTMSK_PRR_MSB 5
2365 /* The width in bits of the ALT_MON_GPIO_INTMSK_PRR register field. */
2366 #define ALT_MON_GPIO_INTMSK_PRR_WIDTH 1
2367 /* The mask used to set the ALT_MON_GPIO_INTMSK_PRR register field value. */
2368 #define ALT_MON_GPIO_INTMSK_PRR_SET_MSK 0x00000020
2369 /* The mask used to clear the ALT_MON_GPIO_INTMSK_PRR register field value. */
2370 #define ALT_MON_GPIO_INTMSK_PRR_CLR_MSK 0xffffffdf
2371 /* The reset value of the ALT_MON_GPIO_INTMSK_PRR register field. */
2372 #define ALT_MON_GPIO_INTMSK_PRR_RESET 0x0
2373 /* Extracts the ALT_MON_GPIO_INTMSK_PRR field value from a register. */
2374 #define ALT_MON_GPIO_INTMSK_PRR_GET(value) (((value) & 0x00000020) >> 5)
2375 /* Produces a ALT_MON_GPIO_INTMSK_PRR register field value suitable for setting the register. */
2376 #define ALT_MON_GPIO_INTMSK_PRR_SET(value) (((value) << 5) & 0x00000020)
2377 
2378 /*
2379  * Field : Interrupt Mask Field (PR_ERROR) - pre
2380  *
2381  * Controls whether an interrupt for PR_ERROR can generate an interrupt to the
2382  * interrupt controller by not masking it. The unmasked status can be read as well
2383  * as the resultant status after masking.
2384  *
2385  * Field Enumeration Values:
2386  *
2387  * Enum | Value | Description
2388  * :------------------------------|:------|:-----------------
2389  * ALT_MON_GPIO_INTMSK_PRE_E_DIS | 0x0 | Unmask Interrupt
2390  * ALT_MON_GPIO_INTMSK_PRE_E_EN | 0x1 | Mask Interrupt
2391  *
2392  * Field Access Macros:
2393  *
2394  */
2395 /*
2396  * Enumerated value for register field ALT_MON_GPIO_INTMSK_PRE
2397  *
2398  * Unmask Interrupt
2399  */
2400 #define ALT_MON_GPIO_INTMSK_PRE_E_DIS 0x0
2401 /*
2402  * Enumerated value for register field ALT_MON_GPIO_INTMSK_PRE
2403  *
2404  * Mask Interrupt
2405  */
2406 #define ALT_MON_GPIO_INTMSK_PRE_E_EN 0x1
2407 
2408 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_PRE register field. */
2409 #define ALT_MON_GPIO_INTMSK_PRE_LSB 6
2410 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_PRE register field. */
2411 #define ALT_MON_GPIO_INTMSK_PRE_MSB 6
2412 /* The width in bits of the ALT_MON_GPIO_INTMSK_PRE register field. */
2413 #define ALT_MON_GPIO_INTMSK_PRE_WIDTH 1
2414 /* The mask used to set the ALT_MON_GPIO_INTMSK_PRE register field value. */
2415 #define ALT_MON_GPIO_INTMSK_PRE_SET_MSK 0x00000040
2416 /* The mask used to clear the ALT_MON_GPIO_INTMSK_PRE register field value. */
2417 #define ALT_MON_GPIO_INTMSK_PRE_CLR_MSK 0xffffffbf
2418 /* The reset value of the ALT_MON_GPIO_INTMSK_PRE register field. */
2419 #define ALT_MON_GPIO_INTMSK_PRE_RESET 0x0
2420 /* Extracts the ALT_MON_GPIO_INTMSK_PRE field value from a register. */
2421 #define ALT_MON_GPIO_INTMSK_PRE_GET(value) (((value) & 0x00000040) >> 6)
2422 /* Produces a ALT_MON_GPIO_INTMSK_PRE register field value suitable for setting the register. */
2423 #define ALT_MON_GPIO_INTMSK_PRE_SET(value) (((value) << 6) & 0x00000040)
2424 
2425 /*
2426  * Field : Interrupt Mask Field (PR_DONE) - prd
2427  *
2428  * Controls whether an interrupt for PR_DONE can generate an interrupt to the
2429  * interrupt controller by not masking it. The unmasked status can be read as well
2430  * as the resultant status after masking.
2431  *
2432  * Field Enumeration Values:
2433  *
2434  * Enum | Value | Description
2435  * :------------------------------|:------|:-----------------
2436  * ALT_MON_GPIO_INTMSK_PRD_E_DIS | 0x0 | Unmask Interrupt
2437  * ALT_MON_GPIO_INTMSK_PRD_E_EN | 0x1 | Mask Interrupt
2438  *
2439  * Field Access Macros:
2440  *
2441  */
2442 /*
2443  * Enumerated value for register field ALT_MON_GPIO_INTMSK_PRD
2444  *
2445  * Unmask Interrupt
2446  */
2447 #define ALT_MON_GPIO_INTMSK_PRD_E_DIS 0x0
2448 /*
2449  * Enumerated value for register field ALT_MON_GPIO_INTMSK_PRD
2450  *
2451  * Mask Interrupt
2452  */
2453 #define ALT_MON_GPIO_INTMSK_PRD_E_EN 0x1
2454 
2455 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_PRD register field. */
2456 #define ALT_MON_GPIO_INTMSK_PRD_LSB 7
2457 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_PRD register field. */
2458 #define ALT_MON_GPIO_INTMSK_PRD_MSB 7
2459 /* The width in bits of the ALT_MON_GPIO_INTMSK_PRD register field. */
2460 #define ALT_MON_GPIO_INTMSK_PRD_WIDTH 1
2461 /* The mask used to set the ALT_MON_GPIO_INTMSK_PRD register field value. */
2462 #define ALT_MON_GPIO_INTMSK_PRD_SET_MSK 0x00000080
2463 /* The mask used to clear the ALT_MON_GPIO_INTMSK_PRD register field value. */
2464 #define ALT_MON_GPIO_INTMSK_PRD_CLR_MSK 0xffffff7f
2465 /* The reset value of the ALT_MON_GPIO_INTMSK_PRD register field. */
2466 #define ALT_MON_GPIO_INTMSK_PRD_RESET 0x0
2467 /* Extracts the ALT_MON_GPIO_INTMSK_PRD field value from a register. */
2468 #define ALT_MON_GPIO_INTMSK_PRD_GET(value) (((value) & 0x00000080) >> 7)
2469 /* Produces a ALT_MON_GPIO_INTMSK_PRD register field value suitable for setting the register. */
2470 #define ALT_MON_GPIO_INTMSK_PRD_SET(value) (((value) << 7) & 0x00000080)
2471 
2472 /*
2473  * Field : Interrupt Mask Field (nCONFIG Pin) - ncp
2474  *
2475  * Controls whether an interrupt for nCONFIG Pin can generate an interrupt to the
2476  * interrupt controller by not masking it. The unmasked status can be read as well
2477  * as the resultant status after masking.
2478  *
2479  * Field Enumeration Values:
2480  *
2481  * Enum | Value | Description
2482  * :------------------------------|:------|:-----------------
2483  * ALT_MON_GPIO_INTMSK_NCP_E_DIS | 0x0 | Unmask Interrupt
2484  * ALT_MON_GPIO_INTMSK_NCP_E_EN | 0x1 | Mask Interrupt
2485  *
2486  * Field Access Macros:
2487  *
2488  */
2489 /*
2490  * Enumerated value for register field ALT_MON_GPIO_INTMSK_NCP
2491  *
2492  * Unmask Interrupt
2493  */
2494 #define ALT_MON_GPIO_INTMSK_NCP_E_DIS 0x0
2495 /*
2496  * Enumerated value for register field ALT_MON_GPIO_INTMSK_NCP
2497  *
2498  * Mask Interrupt
2499  */
2500 #define ALT_MON_GPIO_INTMSK_NCP_E_EN 0x1
2501 
2502 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_NCP register field. */
2503 #define ALT_MON_GPIO_INTMSK_NCP_LSB 8
2504 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_NCP register field. */
2505 #define ALT_MON_GPIO_INTMSK_NCP_MSB 8
2506 /* The width in bits of the ALT_MON_GPIO_INTMSK_NCP register field. */
2507 #define ALT_MON_GPIO_INTMSK_NCP_WIDTH 1
2508 /* The mask used to set the ALT_MON_GPIO_INTMSK_NCP register field value. */
2509 #define ALT_MON_GPIO_INTMSK_NCP_SET_MSK 0x00000100
2510 /* The mask used to clear the ALT_MON_GPIO_INTMSK_NCP register field value. */
2511 #define ALT_MON_GPIO_INTMSK_NCP_CLR_MSK 0xfffffeff
2512 /* The reset value of the ALT_MON_GPIO_INTMSK_NCP register field. */
2513 #define ALT_MON_GPIO_INTMSK_NCP_RESET 0x0
2514 /* Extracts the ALT_MON_GPIO_INTMSK_NCP field value from a register. */
2515 #define ALT_MON_GPIO_INTMSK_NCP_GET(value) (((value) & 0x00000100) >> 8)
2516 /* Produces a ALT_MON_GPIO_INTMSK_NCP register field value suitable for setting the register. */
2517 #define ALT_MON_GPIO_INTMSK_NCP_SET(value) (((value) << 8) & 0x00000100)
2518 
2519 /*
2520  * Field : Interrupt Mask Field (nSTATUS Pin) - nsp
2521  *
2522  * Controls whether an interrupt for nSTATUS Pin can generate an interrupt to the
2523  * interrupt controller by not masking it. The unmasked status can be read as well
2524  * as the resultant status after masking.
2525  *
2526  * Field Enumeration Values:
2527  *
2528  * Enum | Value | Description
2529  * :------------------------------|:------|:-----------------
2530  * ALT_MON_GPIO_INTMSK_NSP_E_DIS | 0x0 | Unmask Interrupt
2531  * ALT_MON_GPIO_INTMSK_NSP_E_EN | 0x1 | Mask Interrupt
2532  *
2533  * Field Access Macros:
2534  *
2535  */
2536 /*
2537  * Enumerated value for register field ALT_MON_GPIO_INTMSK_NSP
2538  *
2539  * Unmask Interrupt
2540  */
2541 #define ALT_MON_GPIO_INTMSK_NSP_E_DIS 0x0
2542 /*
2543  * Enumerated value for register field ALT_MON_GPIO_INTMSK_NSP
2544  *
2545  * Mask Interrupt
2546  */
2547 #define ALT_MON_GPIO_INTMSK_NSP_E_EN 0x1
2548 
2549 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_NSP register field. */
2550 #define ALT_MON_GPIO_INTMSK_NSP_LSB 9
2551 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_NSP register field. */
2552 #define ALT_MON_GPIO_INTMSK_NSP_MSB 9
2553 /* The width in bits of the ALT_MON_GPIO_INTMSK_NSP register field. */
2554 #define ALT_MON_GPIO_INTMSK_NSP_WIDTH 1
2555 /* The mask used to set the ALT_MON_GPIO_INTMSK_NSP register field value. */
2556 #define ALT_MON_GPIO_INTMSK_NSP_SET_MSK 0x00000200
2557 /* The mask used to clear the ALT_MON_GPIO_INTMSK_NSP register field value. */
2558 #define ALT_MON_GPIO_INTMSK_NSP_CLR_MSK 0xfffffdff
2559 /* The reset value of the ALT_MON_GPIO_INTMSK_NSP register field. */
2560 #define ALT_MON_GPIO_INTMSK_NSP_RESET 0x0
2561 /* Extracts the ALT_MON_GPIO_INTMSK_NSP field value from a register. */
2562 #define ALT_MON_GPIO_INTMSK_NSP_GET(value) (((value) & 0x00000200) >> 9)
2563 /* Produces a ALT_MON_GPIO_INTMSK_NSP register field value suitable for setting the register. */
2564 #define ALT_MON_GPIO_INTMSK_NSP_SET(value) (((value) << 9) & 0x00000200)
2565 
2566 /*
2567  * Field : Interrupt Mask Field (CONF_DONE Pin) - cdp
2568  *
2569  * Controls whether an interrupt for CONF_DONE Pin can generate an interrupt to the
2570  * interrupt controller by not masking it. The unmasked status can be read as well
2571  * as the resultant status after masking.
2572  *
2573  * Field Enumeration Values:
2574  *
2575  * Enum | Value | Description
2576  * :------------------------------|:------|:-----------------
2577  * ALT_MON_GPIO_INTMSK_CDP_E_DIS | 0x0 | Unmask Interrupt
2578  * ALT_MON_GPIO_INTMSK_CDP_E_EN | 0x1 | Mask Interrupt
2579  *
2580  * Field Access Macros:
2581  *
2582  */
2583 /*
2584  * Enumerated value for register field ALT_MON_GPIO_INTMSK_CDP
2585  *
2586  * Unmask Interrupt
2587  */
2588 #define ALT_MON_GPIO_INTMSK_CDP_E_DIS 0x0
2589 /*
2590  * Enumerated value for register field ALT_MON_GPIO_INTMSK_CDP
2591  *
2592  * Mask Interrupt
2593  */
2594 #define ALT_MON_GPIO_INTMSK_CDP_E_EN 0x1
2595 
2596 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_CDP register field. */
2597 #define ALT_MON_GPIO_INTMSK_CDP_LSB 10
2598 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_CDP register field. */
2599 #define ALT_MON_GPIO_INTMSK_CDP_MSB 10
2600 /* The width in bits of the ALT_MON_GPIO_INTMSK_CDP register field. */
2601 #define ALT_MON_GPIO_INTMSK_CDP_WIDTH 1
2602 /* The mask used to set the ALT_MON_GPIO_INTMSK_CDP register field value. */
2603 #define ALT_MON_GPIO_INTMSK_CDP_SET_MSK 0x00000400
2604 /* The mask used to clear the ALT_MON_GPIO_INTMSK_CDP register field value. */
2605 #define ALT_MON_GPIO_INTMSK_CDP_CLR_MSK 0xfffffbff
2606 /* The reset value of the ALT_MON_GPIO_INTMSK_CDP register field. */
2607 #define ALT_MON_GPIO_INTMSK_CDP_RESET 0x0
2608 /* Extracts the ALT_MON_GPIO_INTMSK_CDP field value from a register. */
2609 #define ALT_MON_GPIO_INTMSK_CDP_GET(value) (((value) & 0x00000400) >> 10)
2610 /* Produces a ALT_MON_GPIO_INTMSK_CDP register field value suitable for setting the register. */
2611 #define ALT_MON_GPIO_INTMSK_CDP_SET(value) (((value) << 10) & 0x00000400)
2612 
2613 /*
2614  * Field : Interrupt Mask Field (FPGA_POWER_ON) - fpo
2615  *
2616  * Controls whether an interrupt for FPGA_POWER_ON can generate an interrupt to the
2617  * interrupt controller by not masking it. The unmasked status can be read as well
2618  * as the resultant status after masking.
2619  *
2620  * Field Enumeration Values:
2621  *
2622  * Enum | Value | Description
2623  * :------------------------------|:------|:-----------------
2624  * ALT_MON_GPIO_INTMSK_FPO_E_DIS | 0x0 | Unmask Interrupt
2625  * ALT_MON_GPIO_INTMSK_FPO_E_EN | 0x1 | Mask Interrupt
2626  *
2627  * Field Access Macros:
2628  *
2629  */
2630 /*
2631  * Enumerated value for register field ALT_MON_GPIO_INTMSK_FPO
2632  *
2633  * Unmask Interrupt
2634  */
2635 #define ALT_MON_GPIO_INTMSK_FPO_E_DIS 0x0
2636 /*
2637  * Enumerated value for register field ALT_MON_GPIO_INTMSK_FPO
2638  *
2639  * Mask Interrupt
2640  */
2641 #define ALT_MON_GPIO_INTMSK_FPO_E_EN 0x1
2642 
2643 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTMSK_FPO register field. */
2644 #define ALT_MON_GPIO_INTMSK_FPO_LSB 11
2645 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTMSK_FPO register field. */
2646 #define ALT_MON_GPIO_INTMSK_FPO_MSB 11
2647 /* The width in bits of the ALT_MON_GPIO_INTMSK_FPO register field. */
2648 #define ALT_MON_GPIO_INTMSK_FPO_WIDTH 1
2649 /* The mask used to set the ALT_MON_GPIO_INTMSK_FPO register field value. */
2650 #define ALT_MON_GPIO_INTMSK_FPO_SET_MSK 0x00000800
2651 /* The mask used to clear the ALT_MON_GPIO_INTMSK_FPO register field value. */
2652 #define ALT_MON_GPIO_INTMSK_FPO_CLR_MSK 0xfffff7ff
2653 /* The reset value of the ALT_MON_GPIO_INTMSK_FPO register field. */
2654 #define ALT_MON_GPIO_INTMSK_FPO_RESET 0x0
2655 /* Extracts the ALT_MON_GPIO_INTMSK_FPO field value from a register. */
2656 #define ALT_MON_GPIO_INTMSK_FPO_GET(value) (((value) & 0x00000800) >> 11)
2657 /* Produces a ALT_MON_GPIO_INTMSK_FPO register field value suitable for setting the register. */
2658 #define ALT_MON_GPIO_INTMSK_FPO_SET(value) (((value) << 11) & 0x00000800)
2659 
2660 #ifndef __ASSEMBLY__
2661 /*
2662  * WARNING: The C register and register group struct declarations are provided for
2663  * convenience and illustrative purposes. They should, however, be used with
2664  * caution as the C language standard provides no guarantees about the alignment or
2665  * atomicity of device memory accesses. The recommended practice for writing
2666  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2667  * alt_write_word() functions.
2668  *
2669  * The struct declaration for register ALT_MON_GPIO_INTMSK.
2670  */
2671 struct ALT_MON_GPIO_INTMSK_s
2672 {
2673  uint32_t ns : 1; /* Interrupt Mask Field (nSTATUS) */
2674  uint32_t cd : 1; /* Interrupt Mask Field (CONF_DONE) */
2675  uint32_t id : 1; /* Interrupt Mask Field (INIT_DONE) */
2676  uint32_t crc : 1; /* Interrupt Mask Field (CRC_ERROR) */
2677  uint32_t ccd : 1; /* Interrupt Mask Field (CVP_CONF_DONE) */
2678  uint32_t prr : 1; /* Interrupt Mask Field (PR_READY) */
2679  uint32_t pre : 1; /* Interrupt Mask Field (PR_ERROR) */
2680  uint32_t prd : 1; /* Interrupt Mask Field (PR_DONE) */
2681  uint32_t ncp : 1; /* Interrupt Mask Field (nCONFIG Pin) */
2682  uint32_t nsp : 1; /* Interrupt Mask Field (nSTATUS Pin) */
2683  uint32_t cdp : 1; /* Interrupt Mask Field (CONF_DONE Pin) */
2684  uint32_t fpo : 1; /* Interrupt Mask Field (FPGA_POWER_ON) */
2685  uint32_t : 20; /* *UNDEFINED* */
2686 };
2687 
2688 /* The typedef declaration for register ALT_MON_GPIO_INTMSK. */
2689 typedef volatile struct ALT_MON_GPIO_INTMSK_s ALT_MON_GPIO_INTMSK_t;
2690 #endif /* __ASSEMBLY__ */
2691 
2692 /* The byte offset of the ALT_MON_GPIO_INTMSK register from the beginning of the component. */
2693 #define ALT_MON_GPIO_INTMSK_OFST 0x34
2694 /* The address of the ALT_MON_GPIO_INTMSK register. */
2695 #define ALT_MON_GPIO_INTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_INTMSK_OFST))
2696 
2697 /*
2698  * Register : Interrupt Level Register - gpio_inttype_level
2699  *
2700  * The interrupt level register defines the type of interrupt (edge or level) for
2701  * each GPIO input.
2702  *
2703  * Register Layout
2704  *
2705  * Bits | Access | Reset | Description
2706  * :--------|:-------|:------|:--------------------------------------
2707  * [0] | RW | 0x0 | Interrupt Level Field (nSTATUS)
2708  * [1] | RW | 0x0 | Interrupt Level Field (CONF_DONE)
2709  * [2] | RW | 0x0 | Interrupt Level Field (INIT_DONE)
2710  * [3] | RW | 0x0 | Interrupt Level Field (CRC_ERROR)
2711  * [4] | RW | 0x0 | Interrupt Level Field (CVP_CONF_DONE)
2712  * [5] | RW | 0x0 | Interrupt Level Field (PR_READY)
2713  * [6] | RW | 0x0 | Interrupt Level Field (PR_ERROR)
2714  * [7] | RW | 0x0 | Interrupt Level Field (PR_DONE)
2715  * [8] | RW | 0x0 | Interrupt Level Field (nCONFIG Pin)
2716  * [9] | RW | 0x0 | Interrupt Level Field (nSTATUS Pin)
2717  * [10] | RW | 0x0 | Interrupt Level Field (CONF_DONE Pin)
2718  * [11] | RW | 0x0 | Interrupt Level Field (FPGA_POWER_ON)
2719  * [31:12] | ??? | 0x0 | *UNDEFINED*
2720  *
2721  */
2722 /*
2723  * Field : Interrupt Level Field (nSTATUS) - ns
2724  *
2725  * Controls whether the level of nSTATUS or an edge on nSTATUS generates an
2726  * interrupt.
2727  *
2728  * Field Enumeration Values:
2729  *
2730  * Enum | Value | Description
2731  * :--------------------------------------|:------|:----------------
2732  * ALT_MON_GPIO_INTTYPE_LEVEL_NS_E_LEVEL | 0x0 | Level-sensitive
2733  * ALT_MON_GPIO_INTTYPE_LEVEL_NS_E_EDGE | 0x1 | Edge-sensitive
2734  *
2735  * Field Access Macros:
2736  *
2737  */
2738 /*
2739  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_NS
2740  *
2741  * Level-sensitive
2742  */
2743 #define ALT_MON_GPIO_INTTYPE_LEVEL_NS_E_LEVEL 0x0
2744 /*
2745  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_NS
2746  *
2747  * Edge-sensitive
2748  */
2749 #define ALT_MON_GPIO_INTTYPE_LEVEL_NS_E_EDGE 0x1
2750 
2751 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_NS register field. */
2752 #define ALT_MON_GPIO_INTTYPE_LEVEL_NS_LSB 0
2753 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_NS register field. */
2754 #define ALT_MON_GPIO_INTTYPE_LEVEL_NS_MSB 0
2755 /* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_NS register field. */
2756 #define ALT_MON_GPIO_INTTYPE_LEVEL_NS_WIDTH 1
2757 /* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_NS register field value. */
2758 #define ALT_MON_GPIO_INTTYPE_LEVEL_NS_SET_MSK 0x00000001
2759 /* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_NS register field value. */
2760 #define ALT_MON_GPIO_INTTYPE_LEVEL_NS_CLR_MSK 0xfffffffe
2761 /* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_NS register field. */
2762 #define ALT_MON_GPIO_INTTYPE_LEVEL_NS_RESET 0x0
2763 /* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_NS field value from a register. */
2764 #define ALT_MON_GPIO_INTTYPE_LEVEL_NS_GET(value) (((value) & 0x00000001) >> 0)
2765 /* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_NS register field value suitable for setting the register. */
2766 #define ALT_MON_GPIO_INTTYPE_LEVEL_NS_SET(value) (((value) << 0) & 0x00000001)
2767 
2768 /*
2769  * Field : Interrupt Level Field (CONF_DONE) - cd
2770  *
2771  * Controls whether the level of CONF_DONE or an edge on CONF_DONE generates an
2772  * interrupt.
2773  *
2774  * Field Enumeration Values:
2775  *
2776  * Enum | Value | Description
2777  * :--------------------------------------|:------|:----------------
2778  * ALT_MON_GPIO_INTTYPE_LEVEL_CD_E_LEVEL | 0x0 | Level-sensitive
2779  * ALT_MON_GPIO_INTTYPE_LEVEL_CD_E_EDGE | 0x1 | Edge-sensitive
2780  *
2781  * Field Access Macros:
2782  *
2783  */
2784 /*
2785  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CD
2786  *
2787  * Level-sensitive
2788  */
2789 #define ALT_MON_GPIO_INTTYPE_LEVEL_CD_E_LEVEL 0x0
2790 /*
2791  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CD
2792  *
2793  * Edge-sensitive
2794  */
2795 #define ALT_MON_GPIO_INTTYPE_LEVEL_CD_E_EDGE 0x1
2796 
2797 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CD register field. */
2798 #define ALT_MON_GPIO_INTTYPE_LEVEL_CD_LSB 1
2799 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CD register field. */
2800 #define ALT_MON_GPIO_INTTYPE_LEVEL_CD_MSB 1
2801 /* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_CD register field. */
2802 #define ALT_MON_GPIO_INTTYPE_LEVEL_CD_WIDTH 1
2803 /* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_CD register field value. */
2804 #define ALT_MON_GPIO_INTTYPE_LEVEL_CD_SET_MSK 0x00000002
2805 /* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_CD register field value. */
2806 #define ALT_MON_GPIO_INTTYPE_LEVEL_CD_CLR_MSK 0xfffffffd
2807 /* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_CD register field. */
2808 #define ALT_MON_GPIO_INTTYPE_LEVEL_CD_RESET 0x0
2809 /* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_CD field value from a register. */
2810 #define ALT_MON_GPIO_INTTYPE_LEVEL_CD_GET(value) (((value) & 0x00000002) >> 1)
2811 /* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_CD register field value suitable for setting the register. */
2812 #define ALT_MON_GPIO_INTTYPE_LEVEL_CD_SET(value) (((value) << 1) & 0x00000002)
2813 
2814 /*
2815  * Field : Interrupt Level Field (INIT_DONE) - id
2816  *
2817  * Controls whether the level of INIT_DONE or an edge on INIT_DONE generates an
2818  * interrupt.
2819  *
2820  * Field Enumeration Values:
2821  *
2822  * Enum | Value | Description
2823  * :--------------------------------------|:------|:----------------
2824  * ALT_MON_GPIO_INTTYPE_LEVEL_ID_E_LEVEL | 0x0 | Level-sensitive
2825  * ALT_MON_GPIO_INTTYPE_LEVEL_ID_E_EDGE | 0x1 | Edge-sensitive
2826  *
2827  * Field Access Macros:
2828  *
2829  */
2830 /*
2831  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_ID
2832  *
2833  * Level-sensitive
2834  */
2835 #define ALT_MON_GPIO_INTTYPE_LEVEL_ID_E_LEVEL 0x0
2836 /*
2837  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_ID
2838  *
2839  * Edge-sensitive
2840  */
2841 #define ALT_MON_GPIO_INTTYPE_LEVEL_ID_E_EDGE 0x1
2842 
2843 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_ID register field. */
2844 #define ALT_MON_GPIO_INTTYPE_LEVEL_ID_LSB 2
2845 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_ID register field. */
2846 #define ALT_MON_GPIO_INTTYPE_LEVEL_ID_MSB 2
2847 /* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_ID register field. */
2848 #define ALT_MON_GPIO_INTTYPE_LEVEL_ID_WIDTH 1
2849 /* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_ID register field value. */
2850 #define ALT_MON_GPIO_INTTYPE_LEVEL_ID_SET_MSK 0x00000004
2851 /* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_ID register field value. */
2852 #define ALT_MON_GPIO_INTTYPE_LEVEL_ID_CLR_MSK 0xfffffffb
2853 /* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_ID register field. */
2854 #define ALT_MON_GPIO_INTTYPE_LEVEL_ID_RESET 0x0
2855 /* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_ID field value from a register. */
2856 #define ALT_MON_GPIO_INTTYPE_LEVEL_ID_GET(value) (((value) & 0x00000004) >> 2)
2857 /* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_ID register field value suitable for setting the register. */
2858 #define ALT_MON_GPIO_INTTYPE_LEVEL_ID_SET(value) (((value) << 2) & 0x00000004)
2859 
2860 /*
2861  * Field : Interrupt Level Field (CRC_ERROR) - crc
2862  *
2863  * Controls whether the level of CRC_ERROR or an edge on CRC_ERROR generates an
2864  * interrupt.
2865  *
2866  * Field Enumeration Values:
2867  *
2868  * Enum | Value | Description
2869  * :---------------------------------------|:------|:----------------
2870  * ALT_MON_GPIO_INTTYPE_LEVEL_CRC_E_LEVEL | 0x0 | Level-sensitive
2871  * ALT_MON_GPIO_INTTYPE_LEVEL_CRC_E_EDGE | 0x1 | Edge-sensitive
2872  *
2873  * Field Access Macros:
2874  *
2875  */
2876 /*
2877  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CRC
2878  *
2879  * Level-sensitive
2880  */
2881 #define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_E_LEVEL 0x0
2882 /*
2883  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CRC
2884  *
2885  * Edge-sensitive
2886  */
2887 #define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_E_EDGE 0x1
2888 
2889 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field. */
2890 #define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_LSB 3
2891 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field. */
2892 #define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_MSB 3
2893 /* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field. */
2894 #define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_WIDTH 1
2895 /* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field value. */
2896 #define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_SET_MSK 0x00000008
2897 /* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field value. */
2898 #define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_CLR_MSK 0xfffffff7
2899 /* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field. */
2900 #define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_RESET 0x0
2901 /* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_CRC field value from a register. */
2902 #define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_GET(value) (((value) & 0x00000008) >> 3)
2903 /* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_CRC register field value suitable for setting the register. */
2904 #define ALT_MON_GPIO_INTTYPE_LEVEL_CRC_SET(value) (((value) << 3) & 0x00000008)
2905 
2906 /*
2907  * Field : Interrupt Level Field (CVP_CONF_DONE) - ccd
2908  *
2909  * Controls whether the level of CVP_CONF_DONE or an edge on CVP_CONF_DONE
2910  * generates an interrupt.
2911  *
2912  * Field Enumeration Values:
2913  *
2914  * Enum | Value | Description
2915  * :---------------------------------------|:------|:----------------
2916  * ALT_MON_GPIO_INTTYPE_LEVEL_CCD_E_LEVEL | 0x0 | Level-sensitive
2917  * ALT_MON_GPIO_INTTYPE_LEVEL_CCD_E_EDGE | 0x1 | Edge-sensitive
2918  *
2919  * Field Access Macros:
2920  *
2921  */
2922 /*
2923  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CCD
2924  *
2925  * Level-sensitive
2926  */
2927 #define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_E_LEVEL 0x0
2928 /*
2929  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CCD
2930  *
2931  * Edge-sensitive
2932  */
2933 #define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_E_EDGE 0x1
2934 
2935 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field. */
2936 #define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_LSB 4
2937 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field. */
2938 #define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_MSB 4
2939 /* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field. */
2940 #define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_WIDTH 1
2941 /* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field value. */
2942 #define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_SET_MSK 0x00000010
2943 /* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field value. */
2944 #define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_CLR_MSK 0xffffffef
2945 /* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field. */
2946 #define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_RESET 0x0
2947 /* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_CCD field value from a register. */
2948 #define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_GET(value) (((value) & 0x00000010) >> 4)
2949 /* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_CCD register field value suitable for setting the register. */
2950 #define ALT_MON_GPIO_INTTYPE_LEVEL_CCD_SET(value) (((value) << 4) & 0x00000010)
2951 
2952 /*
2953  * Field : Interrupt Level Field (PR_READY) - prr
2954  *
2955  * Controls whether the level of PR_READY or an edge on PR_READY generates an
2956  * interrupt.
2957  *
2958  * Field Enumeration Values:
2959  *
2960  * Enum | Value | Description
2961  * :---------------------------------------|:------|:----------------
2962  * ALT_MON_GPIO_INTTYPE_LEVEL_PRR_E_LEVEL | 0x0 | Level-sensitive
2963  * ALT_MON_GPIO_INTTYPE_LEVEL_PRR_E_EDGE | 0x1 | Edge-sensitive
2964  *
2965  * Field Access Macros:
2966  *
2967  */
2968 /*
2969  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_PRR
2970  *
2971  * Level-sensitive
2972  */
2973 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_E_LEVEL 0x0
2974 /*
2975  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_PRR
2976  *
2977  * Edge-sensitive
2978  */
2979 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_E_EDGE 0x1
2980 
2981 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field. */
2982 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_LSB 5
2983 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field. */
2984 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_MSB 5
2985 /* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field. */
2986 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_WIDTH 1
2987 /* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field value. */
2988 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_SET_MSK 0x00000020
2989 /* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field value. */
2990 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_CLR_MSK 0xffffffdf
2991 /* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field. */
2992 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_RESET 0x0
2993 /* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_PRR field value from a register. */
2994 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_GET(value) (((value) & 0x00000020) >> 5)
2995 /* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_PRR register field value suitable for setting the register. */
2996 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRR_SET(value) (((value) << 5) & 0x00000020)
2997 
2998 /*
2999  * Field : Interrupt Level Field (PR_ERROR) - pre
3000  *
3001  * Controls whether the level of PR_ERROR or an edge on PR_ERROR generates an
3002  * interrupt.
3003  *
3004  * Field Enumeration Values:
3005  *
3006  * Enum | Value | Description
3007  * :---------------------------------------|:------|:----------------
3008  * ALT_MON_GPIO_INTTYPE_LEVEL_PRE_E_LEVEL | 0x0 | Level-sensitive
3009  * ALT_MON_GPIO_INTTYPE_LEVEL_PRE_E_EDGE | 0x1 | Edge-sensitive
3010  *
3011  * Field Access Macros:
3012  *
3013  */
3014 /*
3015  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_PRE
3016  *
3017  * Level-sensitive
3018  */
3019 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_E_LEVEL 0x0
3020 /*
3021  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_PRE
3022  *
3023  * Edge-sensitive
3024  */
3025 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_E_EDGE 0x1
3026 
3027 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field. */
3028 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_LSB 6
3029 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field. */
3030 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_MSB 6
3031 /* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field. */
3032 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_WIDTH 1
3033 /* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field value. */
3034 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_SET_MSK 0x00000040
3035 /* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field value. */
3036 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_CLR_MSK 0xffffffbf
3037 /* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field. */
3038 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_RESET 0x0
3039 /* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_PRE field value from a register. */
3040 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_GET(value) (((value) & 0x00000040) >> 6)
3041 /* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_PRE register field value suitable for setting the register. */
3042 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRE_SET(value) (((value) << 6) & 0x00000040)
3043 
3044 /*
3045  * Field : Interrupt Level Field (PR_DONE) - prd
3046  *
3047  * Controls whether the level of PR_DONE or an edge on PR_DONE generates an
3048  * interrupt.
3049  *
3050  * Field Enumeration Values:
3051  *
3052  * Enum | Value | Description
3053  * :---------------------------------------|:------|:----------------
3054  * ALT_MON_GPIO_INTTYPE_LEVEL_PRD_E_LEVEL | 0x0 | Level-sensitive
3055  * ALT_MON_GPIO_INTTYPE_LEVEL_PRD_E_EDGE | 0x1 | Edge-sensitive
3056  *
3057  * Field Access Macros:
3058  *
3059  */
3060 /*
3061  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_PRD
3062  *
3063  * Level-sensitive
3064  */
3065 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_E_LEVEL 0x0
3066 /*
3067  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_PRD
3068  *
3069  * Edge-sensitive
3070  */
3071 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_E_EDGE 0x1
3072 
3073 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field. */
3074 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_LSB 7
3075 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field. */
3076 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_MSB 7
3077 /* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field. */
3078 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_WIDTH 1
3079 /* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field value. */
3080 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_SET_MSK 0x00000080
3081 /* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field value. */
3082 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_CLR_MSK 0xffffff7f
3083 /* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field. */
3084 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_RESET 0x0
3085 /* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_PRD field value from a register. */
3086 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_GET(value) (((value) & 0x00000080) >> 7)
3087 /* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_PRD register field value suitable for setting the register. */
3088 #define ALT_MON_GPIO_INTTYPE_LEVEL_PRD_SET(value) (((value) << 7) & 0x00000080)
3089 
3090 /*
3091  * Field : Interrupt Level Field (nCONFIG Pin) - ncp
3092  *
3093  * Controls whether the level of nCONFIG Pin or an edge on nCONFIG Pin generates an
3094  * interrupt.
3095  *
3096  * Field Enumeration Values:
3097  *
3098  * Enum | Value | Description
3099  * :---------------------------------------|:------|:----------------
3100  * ALT_MON_GPIO_INTTYPE_LEVEL_NCP_E_LEVEL | 0x0 | Level-sensitive
3101  * ALT_MON_GPIO_INTTYPE_LEVEL_NCP_E_EDGE | 0x1 | Edge-sensitive
3102  *
3103  * Field Access Macros:
3104  *
3105  */
3106 /*
3107  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_NCP
3108  *
3109  * Level-sensitive
3110  */
3111 #define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_E_LEVEL 0x0
3112 /*
3113  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_NCP
3114  *
3115  * Edge-sensitive
3116  */
3117 #define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_E_EDGE 0x1
3118 
3119 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field. */
3120 #define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_LSB 8
3121 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field. */
3122 #define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_MSB 8
3123 /* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field. */
3124 #define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_WIDTH 1
3125 /* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field value. */
3126 #define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_SET_MSK 0x00000100
3127 /* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field value. */
3128 #define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_CLR_MSK 0xfffffeff
3129 /* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field. */
3130 #define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_RESET 0x0
3131 /* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_NCP field value from a register. */
3132 #define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_GET(value) (((value) & 0x00000100) >> 8)
3133 /* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_NCP register field value suitable for setting the register. */
3134 #define ALT_MON_GPIO_INTTYPE_LEVEL_NCP_SET(value) (((value) << 8) & 0x00000100)
3135 
3136 /*
3137  * Field : Interrupt Level Field (nSTATUS Pin) - nsp
3138  *
3139  * Controls whether the level of nSTATUS Pin or an edge on nSTATUS Pin generates an
3140  * interrupt.
3141  *
3142  * Field Enumeration Values:
3143  *
3144  * Enum | Value | Description
3145  * :---------------------------------------|:------|:----------------
3146  * ALT_MON_GPIO_INTTYPE_LEVEL_NSP_E_LEVEL | 0x0 | Level-sensitive
3147  * ALT_MON_GPIO_INTTYPE_LEVEL_NSP_E_EDGE | 0x1 | Edge-sensitive
3148  *
3149  * Field Access Macros:
3150  *
3151  */
3152 /*
3153  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_NSP
3154  *
3155  * Level-sensitive
3156  */
3157 #define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_E_LEVEL 0x0
3158 /*
3159  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_NSP
3160  *
3161  * Edge-sensitive
3162  */
3163 #define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_E_EDGE 0x1
3164 
3165 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field. */
3166 #define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_LSB 9
3167 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field. */
3168 #define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_MSB 9
3169 /* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field. */
3170 #define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_WIDTH 1
3171 /* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field value. */
3172 #define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_SET_MSK 0x00000200
3173 /* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field value. */
3174 #define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_CLR_MSK 0xfffffdff
3175 /* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field. */
3176 #define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_RESET 0x0
3177 /* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_NSP field value from a register. */
3178 #define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_GET(value) (((value) & 0x00000200) >> 9)
3179 /* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_NSP register field value suitable for setting the register. */
3180 #define ALT_MON_GPIO_INTTYPE_LEVEL_NSP_SET(value) (((value) << 9) & 0x00000200)
3181 
3182 /*
3183  * Field : Interrupt Level Field (CONF_DONE Pin) - cdp
3184  *
3185  * Controls whether the level of CONF_DONE Pin or an edge on CONF_DONE Pin
3186  * generates an interrupt.
3187  *
3188  * Field Enumeration Values:
3189  *
3190  * Enum | Value | Description
3191  * :---------------------------------------|:------|:----------------
3192  * ALT_MON_GPIO_INTTYPE_LEVEL_CDP_E_LEVEL | 0x0 | Level-sensitive
3193  * ALT_MON_GPIO_INTTYPE_LEVEL_CDP_E_EDGE | 0x1 | Edge-sensitive
3194  *
3195  * Field Access Macros:
3196  *
3197  */
3198 /*
3199  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CDP
3200  *
3201  * Level-sensitive
3202  */
3203 #define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_E_LEVEL 0x0
3204 /*
3205  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_CDP
3206  *
3207  * Edge-sensitive
3208  */
3209 #define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_E_EDGE 0x1
3210 
3211 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field. */
3212 #define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_LSB 10
3213 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field. */
3214 #define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_MSB 10
3215 /* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field. */
3216 #define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_WIDTH 1
3217 /* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field value. */
3218 #define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_SET_MSK 0x00000400
3219 /* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field value. */
3220 #define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_CLR_MSK 0xfffffbff
3221 /* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field. */
3222 #define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_RESET 0x0
3223 /* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_CDP field value from a register. */
3224 #define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_GET(value) (((value) & 0x00000400) >> 10)
3225 /* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_CDP register field value suitable for setting the register. */
3226 #define ALT_MON_GPIO_INTTYPE_LEVEL_CDP_SET(value) (((value) << 10) & 0x00000400)
3227 
3228 /*
3229  * Field : Interrupt Level Field (FPGA_POWER_ON) - fpo
3230  *
3231  * Controls whether the level of FPGA_POWER_ON or an edge on FPGA_POWER_ON
3232  * generates an interrupt.
3233  *
3234  * Field Enumeration Values:
3235  *
3236  * Enum | Value | Description
3237  * :---------------------------------------|:------|:----------------
3238  * ALT_MON_GPIO_INTTYPE_LEVEL_FPO_E_LEVEL | 0x0 | Level-sensitive
3239  * ALT_MON_GPIO_INTTYPE_LEVEL_FPO_E_EDGE | 0x1 | Edge-sensitive
3240  *
3241  * Field Access Macros:
3242  *
3243  */
3244 /*
3245  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_FPO
3246  *
3247  * Level-sensitive
3248  */
3249 #define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_E_LEVEL 0x0
3250 /*
3251  * Enumerated value for register field ALT_MON_GPIO_INTTYPE_LEVEL_FPO
3252  *
3253  * Edge-sensitive
3254  */
3255 #define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_E_EDGE 0x1
3256 
3257 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field. */
3258 #define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_LSB 11
3259 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field. */
3260 #define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_MSB 11
3261 /* The width in bits of the ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field. */
3262 #define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_WIDTH 1
3263 /* The mask used to set the ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field value. */
3264 #define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_SET_MSK 0x00000800
3265 /* The mask used to clear the ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field value. */
3266 #define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_CLR_MSK 0xfffff7ff
3267 /* The reset value of the ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field. */
3268 #define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_RESET 0x0
3269 /* Extracts the ALT_MON_GPIO_INTTYPE_LEVEL_FPO field value from a register. */
3270 #define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_GET(value) (((value) & 0x00000800) >> 11)
3271 /* Produces a ALT_MON_GPIO_INTTYPE_LEVEL_FPO register field value suitable for setting the register. */
3272 #define ALT_MON_GPIO_INTTYPE_LEVEL_FPO_SET(value) (((value) << 11) & 0x00000800)
3273 
3274 #ifndef __ASSEMBLY__
3275 /*
3276  * WARNING: The C register and register group struct declarations are provided for
3277  * convenience and illustrative purposes. They should, however, be used with
3278  * caution as the C language standard provides no guarantees about the alignment or
3279  * atomicity of device memory accesses. The recommended practice for writing
3280  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3281  * alt_write_word() functions.
3282  *
3283  * The struct declaration for register ALT_MON_GPIO_INTTYPE_LEVEL.
3284  */
3285 struct ALT_MON_GPIO_INTTYPE_LEVEL_s
3286 {
3287  uint32_t ns : 1; /* Interrupt Level Field (nSTATUS) */
3288  uint32_t cd : 1; /* Interrupt Level Field (CONF_DONE) */
3289  uint32_t id : 1; /* Interrupt Level Field (INIT_DONE) */
3290  uint32_t crc : 1; /* Interrupt Level Field (CRC_ERROR) */
3291  uint32_t ccd : 1; /* Interrupt Level Field (CVP_CONF_DONE) */
3292  uint32_t prr : 1; /* Interrupt Level Field (PR_READY) */
3293  uint32_t pre : 1; /* Interrupt Level Field (PR_ERROR) */
3294  uint32_t prd : 1; /* Interrupt Level Field (PR_DONE) */
3295  uint32_t ncp : 1; /* Interrupt Level Field (nCONFIG Pin) */
3296  uint32_t nsp : 1; /* Interrupt Level Field (nSTATUS Pin) */
3297  uint32_t cdp : 1; /* Interrupt Level Field (CONF_DONE Pin) */
3298  uint32_t fpo : 1; /* Interrupt Level Field (FPGA_POWER_ON) */
3299  uint32_t : 20; /* *UNDEFINED* */
3300 };
3301 
3302 /* The typedef declaration for register ALT_MON_GPIO_INTTYPE_LEVEL. */
3303 typedef volatile struct ALT_MON_GPIO_INTTYPE_LEVEL_s ALT_MON_GPIO_INTTYPE_LEVEL_t;
3304 #endif /* __ASSEMBLY__ */
3305 
3306 /* The byte offset of the ALT_MON_GPIO_INTTYPE_LEVEL register from the beginning of the component. */
3307 #define ALT_MON_GPIO_INTTYPE_LEVEL_OFST 0x38
3308 /* The address of the ALT_MON_GPIO_INTTYPE_LEVEL register. */
3309 #define ALT_MON_GPIO_INTTYPE_LEVEL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_INTTYPE_LEVEL_OFST))
3310 
3311 /*
3312  * Register : Interrupt Polarity Register - gpio_int_polarity
3313  *
3314  * Controls the polarity of interrupts that can occur on each GPIO input.
3315  *
3316  * Register Layout
3317  *
3318  * Bits | Access | Reset | Description
3319  * :--------|:-------|:------|:---------------------------------------
3320  * [0] | RW | 0x0 | Polarity Control Field (nSTATUS)
3321  * [1] | RW | 0x0 | Polarity Control Field (CONF_DONE)
3322  * [2] | RW | 0x0 | Polarity Control Field (INIT_DONE)
3323  * [3] | RW | 0x0 | Polarity Control Field (CRC_ERROR)
3324  * [4] | RW | 0x0 | Polarity Control Field (CVP_CONF_DONE)
3325  * [5] | RW | 0x0 | Polarity Control Field (PR_READY)
3326  * [6] | RW | 0x0 | Polarity Control Field (PR_ERROR)
3327  * [7] | RW | 0x0 | Polarity Control Field (PR_DONE)
3328  * [8] | RW | 0x0 | Polarity Control Field (nCONFIG Pin)
3329  * [9] | RW | 0x0 | Polarity Control Field (nSTATUS Pin)
3330  * [10] | RW | 0x0 | Polarity Control Field (CONF_DONE Pin)
3331  * [11] | RW | 0x0 | Polarity Control Field (FPGA_POWER_ON)
3332  * [31:12] | ??? | 0x0 | *UNDEFINED*
3333  *
3334  */
3335 /*
3336  * Field : Polarity Control Field (nSTATUS) - ns
3337  *
3338  * Controls the polarity of edge or level sensitivity for nSTATUS
3339  *
3340  * Field Enumeration Values:
3341  *
3342  * Enum | Value | Description
3343  * :----------------------------------|:------|:------------
3344  * ALT_MON_GPIO_INT_POL_NS_E_ACTLOW | 0x0 | Active low
3345  * ALT_MON_GPIO_INT_POL_NS_E_ACTHIGH | 0x1 | Active high
3346  *
3347  * Field Access Macros:
3348  *
3349  */
3350 /*
3351  * Enumerated value for register field ALT_MON_GPIO_INT_POL_NS
3352  *
3353  * Active low
3354  */
3355 #define ALT_MON_GPIO_INT_POL_NS_E_ACTLOW 0x0
3356 /*
3357  * Enumerated value for register field ALT_MON_GPIO_INT_POL_NS
3358  *
3359  * Active high
3360  */
3361 #define ALT_MON_GPIO_INT_POL_NS_E_ACTHIGH 0x1
3362 
3363 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_NS register field. */
3364 #define ALT_MON_GPIO_INT_POL_NS_LSB 0
3365 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_NS register field. */
3366 #define ALT_MON_GPIO_INT_POL_NS_MSB 0
3367 /* The width in bits of the ALT_MON_GPIO_INT_POL_NS register field. */
3368 #define ALT_MON_GPIO_INT_POL_NS_WIDTH 1
3369 /* The mask used to set the ALT_MON_GPIO_INT_POL_NS register field value. */
3370 #define ALT_MON_GPIO_INT_POL_NS_SET_MSK 0x00000001
3371 /* The mask used to clear the ALT_MON_GPIO_INT_POL_NS register field value. */
3372 #define ALT_MON_GPIO_INT_POL_NS_CLR_MSK 0xfffffffe
3373 /* The reset value of the ALT_MON_GPIO_INT_POL_NS register field. */
3374 #define ALT_MON_GPIO_INT_POL_NS_RESET 0x0
3375 /* Extracts the ALT_MON_GPIO_INT_POL_NS field value from a register. */
3376 #define ALT_MON_GPIO_INT_POL_NS_GET(value) (((value) & 0x00000001) >> 0)
3377 /* Produces a ALT_MON_GPIO_INT_POL_NS register field value suitable for setting the register. */
3378 #define ALT_MON_GPIO_INT_POL_NS_SET(value) (((value) << 0) & 0x00000001)
3379 
3380 /*
3381  * Field : Polarity Control Field (CONF_DONE) - cd
3382  *
3383  * Controls the polarity of edge or level sensitivity for CONF_DONE
3384  *
3385  * Field Enumeration Values:
3386  *
3387  * Enum | Value | Description
3388  * :----------------------------------|:------|:------------
3389  * ALT_MON_GPIO_INT_POL_CD_E_ACTLOW | 0x0 | Active low
3390  * ALT_MON_GPIO_INT_POL_CD_E_ACTHIGH | 0x1 | Active high
3391  *
3392  * Field Access Macros:
3393  *
3394  */
3395 /*
3396  * Enumerated value for register field ALT_MON_GPIO_INT_POL_CD
3397  *
3398  * Active low
3399  */
3400 #define ALT_MON_GPIO_INT_POL_CD_E_ACTLOW 0x0
3401 /*
3402  * Enumerated value for register field ALT_MON_GPIO_INT_POL_CD
3403  *
3404  * Active high
3405  */
3406 #define ALT_MON_GPIO_INT_POL_CD_E_ACTHIGH 0x1
3407 
3408 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_CD register field. */
3409 #define ALT_MON_GPIO_INT_POL_CD_LSB 1
3410 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_CD register field. */
3411 #define ALT_MON_GPIO_INT_POL_CD_MSB 1
3412 /* The width in bits of the ALT_MON_GPIO_INT_POL_CD register field. */
3413 #define ALT_MON_GPIO_INT_POL_CD_WIDTH 1
3414 /* The mask used to set the ALT_MON_GPIO_INT_POL_CD register field value. */
3415 #define ALT_MON_GPIO_INT_POL_CD_SET_MSK 0x00000002
3416 /* The mask used to clear the ALT_MON_GPIO_INT_POL_CD register field value. */
3417 #define ALT_MON_GPIO_INT_POL_CD_CLR_MSK 0xfffffffd
3418 /* The reset value of the ALT_MON_GPIO_INT_POL_CD register field. */
3419 #define ALT_MON_GPIO_INT_POL_CD_RESET 0x0
3420 /* Extracts the ALT_MON_GPIO_INT_POL_CD field value from a register. */
3421 #define ALT_MON_GPIO_INT_POL_CD_GET(value) (((value) & 0x00000002) >> 1)
3422 /* Produces a ALT_MON_GPIO_INT_POL_CD register field value suitable for setting the register. */
3423 #define ALT_MON_GPIO_INT_POL_CD_SET(value) (((value) << 1) & 0x00000002)
3424 
3425 /*
3426  * Field : Polarity Control Field (INIT_DONE) - id
3427  *
3428  * Controls the polarity of edge or level sensitivity for INIT_DONE
3429  *
3430  * Field Enumeration Values:
3431  *
3432  * Enum | Value | Description
3433  * :----------------------------------|:------|:------------
3434  * ALT_MON_GPIO_INT_POL_ID_E_ACTLOW | 0x0 | Active low
3435  * ALT_MON_GPIO_INT_POL_ID_E_ACTHIGH | 0x1 | Active high
3436  *
3437  * Field Access Macros:
3438  *
3439  */
3440 /*
3441  * Enumerated value for register field ALT_MON_GPIO_INT_POL_ID
3442  *
3443  * Active low
3444  */
3445 #define ALT_MON_GPIO_INT_POL_ID_E_ACTLOW 0x0
3446 /*
3447  * Enumerated value for register field ALT_MON_GPIO_INT_POL_ID
3448  *
3449  * Active high
3450  */
3451 #define ALT_MON_GPIO_INT_POL_ID_E_ACTHIGH 0x1
3452 
3453 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_ID register field. */
3454 #define ALT_MON_GPIO_INT_POL_ID_LSB 2
3455 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_ID register field. */
3456 #define ALT_MON_GPIO_INT_POL_ID_MSB 2
3457 /* The width in bits of the ALT_MON_GPIO_INT_POL_ID register field. */
3458 #define ALT_MON_GPIO_INT_POL_ID_WIDTH 1
3459 /* The mask used to set the ALT_MON_GPIO_INT_POL_ID register field value. */
3460 #define ALT_MON_GPIO_INT_POL_ID_SET_MSK 0x00000004
3461 /* The mask used to clear the ALT_MON_GPIO_INT_POL_ID register field value. */
3462 #define ALT_MON_GPIO_INT_POL_ID_CLR_MSK 0xfffffffb
3463 /* The reset value of the ALT_MON_GPIO_INT_POL_ID register field. */
3464 #define ALT_MON_GPIO_INT_POL_ID_RESET 0x0
3465 /* Extracts the ALT_MON_GPIO_INT_POL_ID field value from a register. */
3466 #define ALT_MON_GPIO_INT_POL_ID_GET(value) (((value) & 0x00000004) >> 2)
3467 /* Produces a ALT_MON_GPIO_INT_POL_ID register field value suitable for setting the register. */
3468 #define ALT_MON_GPIO_INT_POL_ID_SET(value) (((value) << 2) & 0x00000004)
3469 
3470 /*
3471  * Field : Polarity Control Field (CRC_ERROR) - crc
3472  *
3473  * Controls the polarity of edge or level sensitivity for CRC_ERROR
3474  *
3475  * Field Enumeration Values:
3476  *
3477  * Enum | Value | Description
3478  * :-----------------------------------|:------|:------------
3479  * ALT_MON_GPIO_INT_POL_CRC_E_ACTLOW | 0x0 | Active low
3480  * ALT_MON_GPIO_INT_POL_CRC_E_ACTHIGH | 0x1 | Active high
3481  *
3482  * Field Access Macros:
3483  *
3484  */
3485 /*
3486  * Enumerated value for register field ALT_MON_GPIO_INT_POL_CRC
3487  *
3488  * Active low
3489  */
3490 #define ALT_MON_GPIO_INT_POL_CRC_E_ACTLOW 0x0
3491 /*
3492  * Enumerated value for register field ALT_MON_GPIO_INT_POL_CRC
3493  *
3494  * Active high
3495  */
3496 #define ALT_MON_GPIO_INT_POL_CRC_E_ACTHIGH 0x1
3497 
3498 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_CRC register field. */
3499 #define ALT_MON_GPIO_INT_POL_CRC_LSB 3
3500 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_CRC register field. */
3501 #define ALT_MON_GPIO_INT_POL_CRC_MSB 3
3502 /* The width in bits of the ALT_MON_GPIO_INT_POL_CRC register field. */
3503 #define ALT_MON_GPIO_INT_POL_CRC_WIDTH 1
3504 /* The mask used to set the ALT_MON_GPIO_INT_POL_CRC register field value. */
3505 #define ALT_MON_GPIO_INT_POL_CRC_SET_MSK 0x00000008
3506 /* The mask used to clear the ALT_MON_GPIO_INT_POL_CRC register field value. */
3507 #define ALT_MON_GPIO_INT_POL_CRC_CLR_MSK 0xfffffff7
3508 /* The reset value of the ALT_MON_GPIO_INT_POL_CRC register field. */
3509 #define ALT_MON_GPIO_INT_POL_CRC_RESET 0x0
3510 /* Extracts the ALT_MON_GPIO_INT_POL_CRC field value from a register. */
3511 #define ALT_MON_GPIO_INT_POL_CRC_GET(value) (((value) & 0x00000008) >> 3)
3512 /* Produces a ALT_MON_GPIO_INT_POL_CRC register field value suitable for setting the register. */
3513 #define ALT_MON_GPIO_INT_POL_CRC_SET(value) (((value) << 3) & 0x00000008)
3514 
3515 /*
3516  * Field : Polarity Control Field (CVP_CONF_DONE) - ccd
3517  *
3518  * Controls the polarity of edge or level sensitivity for CVP_CONF_DONE
3519  *
3520  * Field Enumeration Values:
3521  *
3522  * Enum | Value | Description
3523  * :-----------------------------------|:------|:------------
3524  * ALT_MON_GPIO_INT_POL_CCD_E_ACTLOW | 0x0 | Active low
3525  * ALT_MON_GPIO_INT_POL_CCD_E_ACTHIGH | 0x1 | Active high
3526  *
3527  * Field Access Macros:
3528  *
3529  */
3530 /*
3531  * Enumerated value for register field ALT_MON_GPIO_INT_POL_CCD
3532  *
3533  * Active low
3534  */
3535 #define ALT_MON_GPIO_INT_POL_CCD_E_ACTLOW 0x0
3536 /*
3537  * Enumerated value for register field ALT_MON_GPIO_INT_POL_CCD
3538  *
3539  * Active high
3540  */
3541 #define ALT_MON_GPIO_INT_POL_CCD_E_ACTHIGH 0x1
3542 
3543 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_CCD register field. */
3544 #define ALT_MON_GPIO_INT_POL_CCD_LSB 4
3545 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_CCD register field. */
3546 #define ALT_MON_GPIO_INT_POL_CCD_MSB 4
3547 /* The width in bits of the ALT_MON_GPIO_INT_POL_CCD register field. */
3548 #define ALT_MON_GPIO_INT_POL_CCD_WIDTH 1
3549 /* The mask used to set the ALT_MON_GPIO_INT_POL_CCD register field value. */
3550 #define ALT_MON_GPIO_INT_POL_CCD_SET_MSK 0x00000010
3551 /* The mask used to clear the ALT_MON_GPIO_INT_POL_CCD register field value. */
3552 #define ALT_MON_GPIO_INT_POL_CCD_CLR_MSK 0xffffffef
3553 /* The reset value of the ALT_MON_GPIO_INT_POL_CCD register field. */
3554 #define ALT_MON_GPIO_INT_POL_CCD_RESET 0x0
3555 /* Extracts the ALT_MON_GPIO_INT_POL_CCD field value from a register. */
3556 #define ALT_MON_GPIO_INT_POL_CCD_GET(value) (((value) & 0x00000010) >> 4)
3557 /* Produces a ALT_MON_GPIO_INT_POL_CCD register field value suitable for setting the register. */
3558 #define ALT_MON_GPIO_INT_POL_CCD_SET(value) (((value) << 4) & 0x00000010)
3559 
3560 /*
3561  * Field : Polarity Control Field (PR_READY) - prr
3562  *
3563  * Controls the polarity of edge or level sensitivity for PR_READY
3564  *
3565  * Field Enumeration Values:
3566  *
3567  * Enum | Value | Description
3568  * :-----------------------------------|:------|:------------
3569  * ALT_MON_GPIO_INT_POL_PRR_E_ACTLOW | 0x0 | Active low
3570  * ALT_MON_GPIO_INT_POL_PRR_E_ACTHIGH | 0x1 | Active high
3571  *
3572  * Field Access Macros:
3573  *
3574  */
3575 /*
3576  * Enumerated value for register field ALT_MON_GPIO_INT_POL_PRR
3577  *
3578  * Active low
3579  */
3580 #define ALT_MON_GPIO_INT_POL_PRR_E_ACTLOW 0x0
3581 /*
3582  * Enumerated value for register field ALT_MON_GPIO_INT_POL_PRR
3583  *
3584  * Active high
3585  */
3586 #define ALT_MON_GPIO_INT_POL_PRR_E_ACTHIGH 0x1
3587 
3588 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_PRR register field. */
3589 #define ALT_MON_GPIO_INT_POL_PRR_LSB 5
3590 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_PRR register field. */
3591 #define ALT_MON_GPIO_INT_POL_PRR_MSB 5
3592 /* The width in bits of the ALT_MON_GPIO_INT_POL_PRR register field. */
3593 #define ALT_MON_GPIO_INT_POL_PRR_WIDTH 1
3594 /* The mask used to set the ALT_MON_GPIO_INT_POL_PRR register field value. */
3595 #define ALT_MON_GPIO_INT_POL_PRR_SET_MSK 0x00000020
3596 /* The mask used to clear the ALT_MON_GPIO_INT_POL_PRR register field value. */
3597 #define ALT_MON_GPIO_INT_POL_PRR_CLR_MSK 0xffffffdf
3598 /* The reset value of the ALT_MON_GPIO_INT_POL_PRR register field. */
3599 #define ALT_MON_GPIO_INT_POL_PRR_RESET 0x0
3600 /* Extracts the ALT_MON_GPIO_INT_POL_PRR field value from a register. */
3601 #define ALT_MON_GPIO_INT_POL_PRR_GET(value) (((value) & 0x00000020) >> 5)
3602 /* Produces a ALT_MON_GPIO_INT_POL_PRR register field value suitable for setting the register. */
3603 #define ALT_MON_GPIO_INT_POL_PRR_SET(value) (((value) << 5) & 0x00000020)
3604 
3605 /*
3606  * Field : Polarity Control Field (PR_ERROR) - pre
3607  *
3608  * Controls the polarity of edge or level sensitivity for PR_ERROR
3609  *
3610  * Field Enumeration Values:
3611  *
3612  * Enum | Value | Description
3613  * :-----------------------------------|:------|:------------
3614  * ALT_MON_GPIO_INT_POL_PRE_E_ACTLOW | 0x0 | Active low
3615  * ALT_MON_GPIO_INT_POL_PRE_E_ACTHIGH | 0x1 | Active high
3616  *
3617  * Field Access Macros:
3618  *
3619  */
3620 /*
3621  * Enumerated value for register field ALT_MON_GPIO_INT_POL_PRE
3622  *
3623  * Active low
3624  */
3625 #define ALT_MON_GPIO_INT_POL_PRE_E_ACTLOW 0x0
3626 /*
3627  * Enumerated value for register field ALT_MON_GPIO_INT_POL_PRE
3628  *
3629  * Active high
3630  */
3631 #define ALT_MON_GPIO_INT_POL_PRE_E_ACTHIGH 0x1
3632 
3633 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_PRE register field. */
3634 #define ALT_MON_GPIO_INT_POL_PRE_LSB 6
3635 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_PRE register field. */
3636 #define ALT_MON_GPIO_INT_POL_PRE_MSB 6
3637 /* The width in bits of the ALT_MON_GPIO_INT_POL_PRE register field. */
3638 #define ALT_MON_GPIO_INT_POL_PRE_WIDTH 1
3639 /* The mask used to set the ALT_MON_GPIO_INT_POL_PRE register field value. */
3640 #define ALT_MON_GPIO_INT_POL_PRE_SET_MSK 0x00000040
3641 /* The mask used to clear the ALT_MON_GPIO_INT_POL_PRE register field value. */
3642 #define ALT_MON_GPIO_INT_POL_PRE_CLR_MSK 0xffffffbf
3643 /* The reset value of the ALT_MON_GPIO_INT_POL_PRE register field. */
3644 #define ALT_MON_GPIO_INT_POL_PRE_RESET 0x0
3645 /* Extracts the ALT_MON_GPIO_INT_POL_PRE field value from a register. */
3646 #define ALT_MON_GPIO_INT_POL_PRE_GET(value) (((value) & 0x00000040) >> 6)
3647 /* Produces a ALT_MON_GPIO_INT_POL_PRE register field value suitable for setting the register. */
3648 #define ALT_MON_GPIO_INT_POL_PRE_SET(value) (((value) << 6) & 0x00000040)
3649 
3650 /*
3651  * Field : Polarity Control Field (PR_DONE) - prd
3652  *
3653  * Controls the polarity of edge or level sensitivity for PR_DONE
3654  *
3655  * Field Enumeration Values:
3656  *
3657  * Enum | Value | Description
3658  * :-----------------------------------|:------|:------------
3659  * ALT_MON_GPIO_INT_POL_PRD_E_ACTLOW | 0x0 | Active low
3660  * ALT_MON_GPIO_INT_POL_PRD_E_ACTHIGH | 0x1 | Active high
3661  *
3662  * Field Access Macros:
3663  *
3664  */
3665 /*
3666  * Enumerated value for register field ALT_MON_GPIO_INT_POL_PRD
3667  *
3668  * Active low
3669  */
3670 #define ALT_MON_GPIO_INT_POL_PRD_E_ACTLOW 0x0
3671 /*
3672  * Enumerated value for register field ALT_MON_GPIO_INT_POL_PRD
3673  *
3674  * Active high
3675  */
3676 #define ALT_MON_GPIO_INT_POL_PRD_E_ACTHIGH 0x1
3677 
3678 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_PRD register field. */
3679 #define ALT_MON_GPIO_INT_POL_PRD_LSB 7
3680 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_PRD register field. */
3681 #define ALT_MON_GPIO_INT_POL_PRD_MSB 7
3682 /* The width in bits of the ALT_MON_GPIO_INT_POL_PRD register field. */
3683 #define ALT_MON_GPIO_INT_POL_PRD_WIDTH 1
3684 /* The mask used to set the ALT_MON_GPIO_INT_POL_PRD register field value. */
3685 #define ALT_MON_GPIO_INT_POL_PRD_SET_MSK 0x00000080
3686 /* The mask used to clear the ALT_MON_GPIO_INT_POL_PRD register field value. */
3687 #define ALT_MON_GPIO_INT_POL_PRD_CLR_MSK 0xffffff7f
3688 /* The reset value of the ALT_MON_GPIO_INT_POL_PRD register field. */
3689 #define ALT_MON_GPIO_INT_POL_PRD_RESET 0x0
3690 /* Extracts the ALT_MON_GPIO_INT_POL_PRD field value from a register. */
3691 #define ALT_MON_GPIO_INT_POL_PRD_GET(value) (((value) & 0x00000080) >> 7)
3692 /* Produces a ALT_MON_GPIO_INT_POL_PRD register field value suitable for setting the register. */
3693 #define ALT_MON_GPIO_INT_POL_PRD_SET(value) (((value) << 7) & 0x00000080)
3694 
3695 /*
3696  * Field : Polarity Control Field (nCONFIG Pin) - ncp
3697  *
3698  * Controls the polarity of edge or level sensitivity for nCONFIG Pin
3699  *
3700  * Field Enumeration Values:
3701  *
3702  * Enum | Value | Description
3703  * :-----------------------------------|:------|:------------
3704  * ALT_MON_GPIO_INT_POL_NCP_E_ACTLOW | 0x0 | Active low
3705  * ALT_MON_GPIO_INT_POL_NCP_E_ACTHIGH | 0x1 | Active high
3706  *
3707  * Field Access Macros:
3708  *
3709  */
3710 /*
3711  * Enumerated value for register field ALT_MON_GPIO_INT_POL_NCP
3712  *
3713  * Active low
3714  */
3715 #define ALT_MON_GPIO_INT_POL_NCP_E_ACTLOW 0x0
3716 /*
3717  * Enumerated value for register field ALT_MON_GPIO_INT_POL_NCP
3718  *
3719  * Active high
3720  */
3721 #define ALT_MON_GPIO_INT_POL_NCP_E_ACTHIGH 0x1
3722 
3723 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_NCP register field. */
3724 #define ALT_MON_GPIO_INT_POL_NCP_LSB 8
3725 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_NCP register field. */
3726 #define ALT_MON_GPIO_INT_POL_NCP_MSB 8
3727 /* The width in bits of the ALT_MON_GPIO_INT_POL_NCP register field. */
3728 #define ALT_MON_GPIO_INT_POL_NCP_WIDTH 1
3729 /* The mask used to set the ALT_MON_GPIO_INT_POL_NCP register field value. */
3730 #define ALT_MON_GPIO_INT_POL_NCP_SET_MSK 0x00000100
3731 /* The mask used to clear the ALT_MON_GPIO_INT_POL_NCP register field value. */
3732 #define ALT_MON_GPIO_INT_POL_NCP_CLR_MSK 0xfffffeff
3733 /* The reset value of the ALT_MON_GPIO_INT_POL_NCP register field. */
3734 #define ALT_MON_GPIO_INT_POL_NCP_RESET 0x0
3735 /* Extracts the ALT_MON_GPIO_INT_POL_NCP field value from a register. */
3736 #define ALT_MON_GPIO_INT_POL_NCP_GET(value) (((value) & 0x00000100) >> 8)
3737 /* Produces a ALT_MON_GPIO_INT_POL_NCP register field value suitable for setting the register. */
3738 #define ALT_MON_GPIO_INT_POL_NCP_SET(value) (((value) << 8) & 0x00000100)
3739 
3740 /*
3741  * Field : Polarity Control Field (nSTATUS Pin) - nsp
3742  *
3743  * Controls the polarity of edge or level sensitivity for nSTATUS Pin
3744  *
3745  * Field Enumeration Values:
3746  *
3747  * Enum | Value | Description
3748  * :-----------------------------------|:------|:------------
3749  * ALT_MON_GPIO_INT_POL_NSP_E_ACTLOW | 0x0 | Active low
3750  * ALT_MON_GPIO_INT_POL_NSP_E_ACTHIGH | 0x1 | Active high
3751  *
3752  * Field Access Macros:
3753  *
3754  */
3755 /*
3756  * Enumerated value for register field ALT_MON_GPIO_INT_POL_NSP
3757  *
3758  * Active low
3759  */
3760 #define ALT_MON_GPIO_INT_POL_NSP_E_ACTLOW 0x0
3761 /*
3762  * Enumerated value for register field ALT_MON_GPIO_INT_POL_NSP
3763  *
3764  * Active high
3765  */
3766 #define ALT_MON_GPIO_INT_POL_NSP_E_ACTHIGH 0x1
3767 
3768 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_NSP register field. */
3769 #define ALT_MON_GPIO_INT_POL_NSP_LSB 9
3770 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_NSP register field. */
3771 #define ALT_MON_GPIO_INT_POL_NSP_MSB 9
3772 /* The width in bits of the ALT_MON_GPIO_INT_POL_NSP register field. */
3773 #define ALT_MON_GPIO_INT_POL_NSP_WIDTH 1
3774 /* The mask used to set the ALT_MON_GPIO_INT_POL_NSP register field value. */
3775 #define ALT_MON_GPIO_INT_POL_NSP_SET_MSK 0x00000200
3776 /* The mask used to clear the ALT_MON_GPIO_INT_POL_NSP register field value. */
3777 #define ALT_MON_GPIO_INT_POL_NSP_CLR_MSK 0xfffffdff
3778 /* The reset value of the ALT_MON_GPIO_INT_POL_NSP register field. */
3779 #define ALT_MON_GPIO_INT_POL_NSP_RESET 0x0
3780 /* Extracts the ALT_MON_GPIO_INT_POL_NSP field value from a register. */
3781 #define ALT_MON_GPIO_INT_POL_NSP_GET(value) (((value) & 0x00000200) >> 9)
3782 /* Produces a ALT_MON_GPIO_INT_POL_NSP register field value suitable for setting the register. */
3783 #define ALT_MON_GPIO_INT_POL_NSP_SET(value) (((value) << 9) & 0x00000200)
3784 
3785 /*
3786  * Field : Polarity Control Field (CONF_DONE Pin) - cdp
3787  *
3788  * Controls the polarity of edge or level sensitivity for CONF_DONE Pin
3789  *
3790  * Field Enumeration Values:
3791  *
3792  * Enum | Value | Description
3793  * :-----------------------------------|:------|:------------
3794  * ALT_MON_GPIO_INT_POL_CDP_E_ACTLOW | 0x0 | Active low
3795  * ALT_MON_GPIO_INT_POL_CDP_E_ACTHIGH | 0x1 | Active high
3796  *
3797  * Field Access Macros:
3798  *
3799  */
3800 /*
3801  * Enumerated value for register field ALT_MON_GPIO_INT_POL_CDP
3802  *
3803  * Active low
3804  */
3805 #define ALT_MON_GPIO_INT_POL_CDP_E_ACTLOW 0x0
3806 /*
3807  * Enumerated value for register field ALT_MON_GPIO_INT_POL_CDP
3808  *
3809  * Active high
3810  */
3811 #define ALT_MON_GPIO_INT_POL_CDP_E_ACTHIGH 0x1
3812 
3813 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_CDP register field. */
3814 #define ALT_MON_GPIO_INT_POL_CDP_LSB 10
3815 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_CDP register field. */
3816 #define ALT_MON_GPIO_INT_POL_CDP_MSB 10
3817 /* The width in bits of the ALT_MON_GPIO_INT_POL_CDP register field. */
3818 #define ALT_MON_GPIO_INT_POL_CDP_WIDTH 1
3819 /* The mask used to set the ALT_MON_GPIO_INT_POL_CDP register field value. */
3820 #define ALT_MON_GPIO_INT_POL_CDP_SET_MSK 0x00000400
3821 /* The mask used to clear the ALT_MON_GPIO_INT_POL_CDP register field value. */
3822 #define ALT_MON_GPIO_INT_POL_CDP_CLR_MSK 0xfffffbff
3823 /* The reset value of the ALT_MON_GPIO_INT_POL_CDP register field. */
3824 #define ALT_MON_GPIO_INT_POL_CDP_RESET 0x0
3825 /* Extracts the ALT_MON_GPIO_INT_POL_CDP field value from a register. */
3826 #define ALT_MON_GPIO_INT_POL_CDP_GET(value) (((value) & 0x00000400) >> 10)
3827 /* Produces a ALT_MON_GPIO_INT_POL_CDP register field value suitable for setting the register. */
3828 #define ALT_MON_GPIO_INT_POL_CDP_SET(value) (((value) << 10) & 0x00000400)
3829 
3830 /*
3831  * Field : Polarity Control Field (FPGA_POWER_ON) - fpo
3832  *
3833  * Controls the polarity of edge or level sensitivity for FPGA_POWER_ON
3834  *
3835  * Field Enumeration Values:
3836  *
3837  * Enum | Value | Description
3838  * :-----------------------------------|:------|:------------
3839  * ALT_MON_GPIO_INT_POL_FPO_E_ACTLOW | 0x0 | Active low
3840  * ALT_MON_GPIO_INT_POL_FPO_E_ACTHIGH | 0x1 | Active high
3841  *
3842  * Field Access Macros:
3843  *
3844  */
3845 /*
3846  * Enumerated value for register field ALT_MON_GPIO_INT_POL_FPO
3847  *
3848  * Active low
3849  */
3850 #define ALT_MON_GPIO_INT_POL_FPO_E_ACTLOW 0x0
3851 /*
3852  * Enumerated value for register field ALT_MON_GPIO_INT_POL_FPO
3853  *
3854  * Active high
3855  */
3856 #define ALT_MON_GPIO_INT_POL_FPO_E_ACTHIGH 0x1
3857 
3858 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INT_POL_FPO register field. */
3859 #define ALT_MON_GPIO_INT_POL_FPO_LSB 11
3860 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INT_POL_FPO register field. */
3861 #define ALT_MON_GPIO_INT_POL_FPO_MSB 11
3862 /* The width in bits of the ALT_MON_GPIO_INT_POL_FPO register field. */
3863 #define ALT_MON_GPIO_INT_POL_FPO_WIDTH 1
3864 /* The mask used to set the ALT_MON_GPIO_INT_POL_FPO register field value. */
3865 #define ALT_MON_GPIO_INT_POL_FPO_SET_MSK 0x00000800
3866 /* The mask used to clear the ALT_MON_GPIO_INT_POL_FPO register field value. */
3867 #define ALT_MON_GPIO_INT_POL_FPO_CLR_MSK 0xfffff7ff
3868 /* The reset value of the ALT_MON_GPIO_INT_POL_FPO register field. */
3869 #define ALT_MON_GPIO_INT_POL_FPO_RESET 0x0
3870 /* Extracts the ALT_MON_GPIO_INT_POL_FPO field value from a register. */
3871 #define ALT_MON_GPIO_INT_POL_FPO_GET(value) (((value) & 0x00000800) >> 11)
3872 /* Produces a ALT_MON_GPIO_INT_POL_FPO register field value suitable for setting the register. */
3873 #define ALT_MON_GPIO_INT_POL_FPO_SET(value) (((value) << 11) & 0x00000800)
3874 
3875 #ifndef __ASSEMBLY__
3876 /*
3877  * WARNING: The C register and register group struct declarations are provided for
3878  * convenience and illustrative purposes. They should, however, be used with
3879  * caution as the C language standard provides no guarantees about the alignment or
3880  * atomicity of device memory accesses. The recommended practice for writing
3881  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3882  * alt_write_word() functions.
3883  *
3884  * The struct declaration for register ALT_MON_GPIO_INT_POL.
3885  */
3886 struct ALT_MON_GPIO_INT_POL_s
3887 {
3888  uint32_t ns : 1; /* Polarity Control Field (nSTATUS) */
3889  uint32_t cd : 1; /* Polarity Control Field (CONF_DONE) */
3890  uint32_t id : 1; /* Polarity Control Field (INIT_DONE) */
3891  uint32_t crc : 1; /* Polarity Control Field (CRC_ERROR) */
3892  uint32_t ccd : 1; /* Polarity Control Field (CVP_CONF_DONE) */
3893  uint32_t prr : 1; /* Polarity Control Field (PR_READY) */
3894  uint32_t pre : 1; /* Polarity Control Field (PR_ERROR) */
3895  uint32_t prd : 1; /* Polarity Control Field (PR_DONE) */
3896  uint32_t ncp : 1; /* Polarity Control Field (nCONFIG Pin) */
3897  uint32_t nsp : 1; /* Polarity Control Field (nSTATUS Pin) */
3898  uint32_t cdp : 1; /* Polarity Control Field (CONF_DONE Pin) */
3899  uint32_t fpo : 1; /* Polarity Control Field (FPGA_POWER_ON) */
3900  uint32_t : 20; /* *UNDEFINED* */
3901 };
3902 
3903 /* The typedef declaration for register ALT_MON_GPIO_INT_POL. */
3904 typedef volatile struct ALT_MON_GPIO_INT_POL_s ALT_MON_GPIO_INT_POL_t;
3905 #endif /* __ASSEMBLY__ */
3906 
3907 /* The byte offset of the ALT_MON_GPIO_INT_POL register from the beginning of the component. */
3908 #define ALT_MON_GPIO_INT_POL_OFST 0x3c
3909 /* The address of the ALT_MON_GPIO_INT_POL register. */
3910 #define ALT_MON_GPIO_INT_POL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_INT_POL_OFST))
3911 
3912 /*
3913  * Register : Interrupt Status Register - gpio_intstatus
3914  *
3915  * Reports on interrupt status for each GPIO input. The interrupt status includes
3916  * the effects of masking.
3917  *
3918  * Register Layout
3919  *
3920  * Bits | Access | Reset | Description
3921  * :--------|:-------|:------|:---------------------------------------
3922  * [0] | R | 0x0 | Interrupt Status Field (nSTATUS)
3923  * [1] | R | 0x0 | Interrupt Status Field (CONF_DONE)
3924  * [2] | R | 0x0 | Interrupt Status Field (INIT_DONE)
3925  * [3] | R | 0x0 | Interrupt Status Field (CRC_ERROR)
3926  * [4] | R | 0x0 | Interrupt Status Field (CVP_CONF_DONE)
3927  * [5] | R | 0x0 | Interrupt Status Field (PR_READY)
3928  * [6] | R | 0x0 | Interrupt Status Field (PR_ERROR)
3929  * [7] | R | 0x0 | Interrupt Status Field (PR_DONE)
3930  * [8] | R | 0x0 | Interrupt Status Field (nCONFIG Pin)
3931  * [9] | R | 0x0 | Interrupt Status Field (nSTATUS Pin)
3932  * [10] | R | 0x0 | Interrupt Status Field (CONF_DONE Pin)
3933  * [11] | R | 0x0 | Interrupt Status Field (FPGA_POWER_ON)
3934  * [31:12] | ??? | 0x0 | *UNDEFINED*
3935  *
3936  */
3937 /*
3938  * Field : Interrupt Status Field (nSTATUS) - ns
3939  *
3940  * Indicates whether nSTATUS has an active interrupt or not (after masking).
3941  *
3942  * Field Enumeration Values:
3943  *
3944  * Enum | Value | Description
3945  * :--------------------------------|:------|:------------
3946  * ALT_MON_GPIO_INTSTAT_NS_E_INACT | 0x0 | Inactive
3947  * ALT_MON_GPIO_INTSTAT_NS_E_ACT | 0x1 | Active
3948  *
3949  * Field Access Macros:
3950  *
3951  */
3952 /*
3953  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_NS
3954  *
3955  * Inactive
3956  */
3957 #define ALT_MON_GPIO_INTSTAT_NS_E_INACT 0x0
3958 /*
3959  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_NS
3960  *
3961  * Active
3962  */
3963 #define ALT_MON_GPIO_INTSTAT_NS_E_ACT 0x1
3964 
3965 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_NS register field. */
3966 #define ALT_MON_GPIO_INTSTAT_NS_LSB 0
3967 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_NS register field. */
3968 #define ALT_MON_GPIO_INTSTAT_NS_MSB 0
3969 /* The width in bits of the ALT_MON_GPIO_INTSTAT_NS register field. */
3970 #define ALT_MON_GPIO_INTSTAT_NS_WIDTH 1
3971 /* The mask used to set the ALT_MON_GPIO_INTSTAT_NS register field value. */
3972 #define ALT_MON_GPIO_INTSTAT_NS_SET_MSK 0x00000001
3973 /* The mask used to clear the ALT_MON_GPIO_INTSTAT_NS register field value. */
3974 #define ALT_MON_GPIO_INTSTAT_NS_CLR_MSK 0xfffffffe
3975 /* The reset value of the ALT_MON_GPIO_INTSTAT_NS register field. */
3976 #define ALT_MON_GPIO_INTSTAT_NS_RESET 0x0
3977 /* Extracts the ALT_MON_GPIO_INTSTAT_NS field value from a register. */
3978 #define ALT_MON_GPIO_INTSTAT_NS_GET(value) (((value) & 0x00000001) >> 0)
3979 /* Produces a ALT_MON_GPIO_INTSTAT_NS register field value suitable for setting the register. */
3980 #define ALT_MON_GPIO_INTSTAT_NS_SET(value) (((value) << 0) & 0x00000001)
3981 
3982 /*
3983  * Field : Interrupt Status Field (CONF_DONE) - cd
3984  *
3985  * Indicates whether CONF_DONE has an active interrupt or not (after masking).
3986  *
3987  * Field Enumeration Values:
3988  *
3989  * Enum | Value | Description
3990  * :--------------------------------|:------|:------------
3991  * ALT_MON_GPIO_INTSTAT_CD_E_INACT | 0x0 | Inactive
3992  * ALT_MON_GPIO_INTSTAT_CD_E_ACT | 0x1 | Active
3993  *
3994  * Field Access Macros:
3995  *
3996  */
3997 /*
3998  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CD
3999  *
4000  * Inactive
4001  */
4002 #define ALT_MON_GPIO_INTSTAT_CD_E_INACT 0x0
4003 /*
4004  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CD
4005  *
4006  * Active
4007  */
4008 #define ALT_MON_GPIO_INTSTAT_CD_E_ACT 0x1
4009 
4010 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_CD register field. */
4011 #define ALT_MON_GPIO_INTSTAT_CD_LSB 1
4012 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_CD register field. */
4013 #define ALT_MON_GPIO_INTSTAT_CD_MSB 1
4014 /* The width in bits of the ALT_MON_GPIO_INTSTAT_CD register field. */
4015 #define ALT_MON_GPIO_INTSTAT_CD_WIDTH 1
4016 /* The mask used to set the ALT_MON_GPIO_INTSTAT_CD register field value. */
4017 #define ALT_MON_GPIO_INTSTAT_CD_SET_MSK 0x00000002
4018 /* The mask used to clear the ALT_MON_GPIO_INTSTAT_CD register field value. */
4019 #define ALT_MON_GPIO_INTSTAT_CD_CLR_MSK 0xfffffffd
4020 /* The reset value of the ALT_MON_GPIO_INTSTAT_CD register field. */
4021 #define ALT_MON_GPIO_INTSTAT_CD_RESET 0x0
4022 /* Extracts the ALT_MON_GPIO_INTSTAT_CD field value from a register. */
4023 #define ALT_MON_GPIO_INTSTAT_CD_GET(value) (((value) & 0x00000002) >> 1)
4024 /* Produces a ALT_MON_GPIO_INTSTAT_CD register field value suitable for setting the register. */
4025 #define ALT_MON_GPIO_INTSTAT_CD_SET(value) (((value) << 1) & 0x00000002)
4026 
4027 /*
4028  * Field : Interrupt Status Field (INIT_DONE) - id
4029  *
4030  * Indicates whether INIT_DONE has an active interrupt or not (after masking).
4031  *
4032  * Field Enumeration Values:
4033  *
4034  * Enum | Value | Description
4035  * :--------------------------------|:------|:------------
4036  * ALT_MON_GPIO_INTSTAT_ID_E_INACT | 0x0 | Inactive
4037  * ALT_MON_GPIO_INTSTAT_ID_E_ACT | 0x1 | Active
4038  *
4039  * Field Access Macros:
4040  *
4041  */
4042 /*
4043  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_ID
4044  *
4045  * Inactive
4046  */
4047 #define ALT_MON_GPIO_INTSTAT_ID_E_INACT 0x0
4048 /*
4049  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_ID
4050  *
4051  * Active
4052  */
4053 #define ALT_MON_GPIO_INTSTAT_ID_E_ACT 0x1
4054 
4055 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_ID register field. */
4056 #define ALT_MON_GPIO_INTSTAT_ID_LSB 2
4057 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_ID register field. */
4058 #define ALT_MON_GPIO_INTSTAT_ID_MSB 2
4059 /* The width in bits of the ALT_MON_GPIO_INTSTAT_ID register field. */
4060 #define ALT_MON_GPIO_INTSTAT_ID_WIDTH 1
4061 /* The mask used to set the ALT_MON_GPIO_INTSTAT_ID register field value. */
4062 #define ALT_MON_GPIO_INTSTAT_ID_SET_MSK 0x00000004
4063 /* The mask used to clear the ALT_MON_GPIO_INTSTAT_ID register field value. */
4064 #define ALT_MON_GPIO_INTSTAT_ID_CLR_MSK 0xfffffffb
4065 /* The reset value of the ALT_MON_GPIO_INTSTAT_ID register field. */
4066 #define ALT_MON_GPIO_INTSTAT_ID_RESET 0x0
4067 /* Extracts the ALT_MON_GPIO_INTSTAT_ID field value from a register. */
4068 #define ALT_MON_GPIO_INTSTAT_ID_GET(value) (((value) & 0x00000004) >> 2)
4069 /* Produces a ALT_MON_GPIO_INTSTAT_ID register field value suitable for setting the register. */
4070 #define ALT_MON_GPIO_INTSTAT_ID_SET(value) (((value) << 2) & 0x00000004)
4071 
4072 /*
4073  * Field : Interrupt Status Field (CRC_ERROR) - crc
4074  *
4075  * Indicates whether CRC_ERROR has an active interrupt or not (after masking).
4076  *
4077  * Field Enumeration Values:
4078  *
4079  * Enum | Value | Description
4080  * :---------------------------------|:------|:------------
4081  * ALT_MON_GPIO_INTSTAT_CRC_E_INACT | 0x0 | Inactive
4082  * ALT_MON_GPIO_INTSTAT_CRC_E_ACT | 0x1 | Active
4083  *
4084  * Field Access Macros:
4085  *
4086  */
4087 /*
4088  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CRC
4089  *
4090  * Inactive
4091  */
4092 #define ALT_MON_GPIO_INTSTAT_CRC_E_INACT 0x0
4093 /*
4094  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CRC
4095  *
4096  * Active
4097  */
4098 #define ALT_MON_GPIO_INTSTAT_CRC_E_ACT 0x1
4099 
4100 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_CRC register field. */
4101 #define ALT_MON_GPIO_INTSTAT_CRC_LSB 3
4102 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_CRC register field. */
4103 #define ALT_MON_GPIO_INTSTAT_CRC_MSB 3
4104 /* The width in bits of the ALT_MON_GPIO_INTSTAT_CRC register field. */
4105 #define ALT_MON_GPIO_INTSTAT_CRC_WIDTH 1
4106 /* The mask used to set the ALT_MON_GPIO_INTSTAT_CRC register field value. */
4107 #define ALT_MON_GPIO_INTSTAT_CRC_SET_MSK 0x00000008
4108 /* The mask used to clear the ALT_MON_GPIO_INTSTAT_CRC register field value. */
4109 #define ALT_MON_GPIO_INTSTAT_CRC_CLR_MSK 0xfffffff7
4110 /* The reset value of the ALT_MON_GPIO_INTSTAT_CRC register field. */
4111 #define ALT_MON_GPIO_INTSTAT_CRC_RESET 0x0
4112 /* Extracts the ALT_MON_GPIO_INTSTAT_CRC field value from a register. */
4113 #define ALT_MON_GPIO_INTSTAT_CRC_GET(value) (((value) & 0x00000008) >> 3)
4114 /* Produces a ALT_MON_GPIO_INTSTAT_CRC register field value suitable for setting the register. */
4115 #define ALT_MON_GPIO_INTSTAT_CRC_SET(value) (((value) << 3) & 0x00000008)
4116 
4117 /*
4118  * Field : Interrupt Status Field (CVP_CONF_DONE) - ccd
4119  *
4120  * Indicates whether CVP_CONF_DONE has an active interrupt or not (after masking).
4121  *
4122  * Field Enumeration Values:
4123  *
4124  * Enum | Value | Description
4125  * :---------------------------------|:------|:------------
4126  * ALT_MON_GPIO_INTSTAT_CCD_E_INACT | 0x0 | Inactive
4127  * ALT_MON_GPIO_INTSTAT_CCD_E_ACT | 0x1 | Active
4128  *
4129  * Field Access Macros:
4130  *
4131  */
4132 /*
4133  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CCD
4134  *
4135  * Inactive
4136  */
4137 #define ALT_MON_GPIO_INTSTAT_CCD_E_INACT 0x0
4138 /*
4139  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CCD
4140  *
4141  * Active
4142  */
4143 #define ALT_MON_GPIO_INTSTAT_CCD_E_ACT 0x1
4144 
4145 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_CCD register field. */
4146 #define ALT_MON_GPIO_INTSTAT_CCD_LSB 4
4147 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_CCD register field. */
4148 #define ALT_MON_GPIO_INTSTAT_CCD_MSB 4
4149 /* The width in bits of the ALT_MON_GPIO_INTSTAT_CCD register field. */
4150 #define ALT_MON_GPIO_INTSTAT_CCD_WIDTH 1
4151 /* The mask used to set the ALT_MON_GPIO_INTSTAT_CCD register field value. */
4152 #define ALT_MON_GPIO_INTSTAT_CCD_SET_MSK 0x00000010
4153 /* The mask used to clear the ALT_MON_GPIO_INTSTAT_CCD register field value. */
4154 #define ALT_MON_GPIO_INTSTAT_CCD_CLR_MSK 0xffffffef
4155 /* The reset value of the ALT_MON_GPIO_INTSTAT_CCD register field. */
4156 #define ALT_MON_GPIO_INTSTAT_CCD_RESET 0x0
4157 /* Extracts the ALT_MON_GPIO_INTSTAT_CCD field value from a register. */
4158 #define ALT_MON_GPIO_INTSTAT_CCD_GET(value) (((value) & 0x00000010) >> 4)
4159 /* Produces a ALT_MON_GPIO_INTSTAT_CCD register field value suitable for setting the register. */
4160 #define ALT_MON_GPIO_INTSTAT_CCD_SET(value) (((value) << 4) & 0x00000010)
4161 
4162 /*
4163  * Field : Interrupt Status Field (PR_READY) - prr
4164  *
4165  * Indicates whether PR_READY has an active interrupt or not (after masking).
4166  *
4167  * Field Enumeration Values:
4168  *
4169  * Enum | Value | Description
4170  * :---------------------------------|:------|:------------
4171  * ALT_MON_GPIO_INTSTAT_PRR_E_INACT | 0x0 | Inactive
4172  * ALT_MON_GPIO_INTSTAT_PRR_E_ACT | 0x1 | Active
4173  *
4174  * Field Access Macros:
4175  *
4176  */
4177 /*
4178  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_PRR
4179  *
4180  * Inactive
4181  */
4182 #define ALT_MON_GPIO_INTSTAT_PRR_E_INACT 0x0
4183 /*
4184  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_PRR
4185  *
4186  * Active
4187  */
4188 #define ALT_MON_GPIO_INTSTAT_PRR_E_ACT 0x1
4189 
4190 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_PRR register field. */
4191 #define ALT_MON_GPIO_INTSTAT_PRR_LSB 5
4192 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_PRR register field. */
4193 #define ALT_MON_GPIO_INTSTAT_PRR_MSB 5
4194 /* The width in bits of the ALT_MON_GPIO_INTSTAT_PRR register field. */
4195 #define ALT_MON_GPIO_INTSTAT_PRR_WIDTH 1
4196 /* The mask used to set the ALT_MON_GPIO_INTSTAT_PRR register field value. */
4197 #define ALT_MON_GPIO_INTSTAT_PRR_SET_MSK 0x00000020
4198 /* The mask used to clear the ALT_MON_GPIO_INTSTAT_PRR register field value. */
4199 #define ALT_MON_GPIO_INTSTAT_PRR_CLR_MSK 0xffffffdf
4200 /* The reset value of the ALT_MON_GPIO_INTSTAT_PRR register field. */
4201 #define ALT_MON_GPIO_INTSTAT_PRR_RESET 0x0
4202 /* Extracts the ALT_MON_GPIO_INTSTAT_PRR field value from a register. */
4203 #define ALT_MON_GPIO_INTSTAT_PRR_GET(value) (((value) & 0x00000020) >> 5)
4204 /* Produces a ALT_MON_GPIO_INTSTAT_PRR register field value suitable for setting the register. */
4205 #define ALT_MON_GPIO_INTSTAT_PRR_SET(value) (((value) << 5) & 0x00000020)
4206 
4207 /*
4208  * Field : Interrupt Status Field (PR_ERROR) - pre
4209  *
4210  * Indicates whether PR_ERROR has an active interrupt or not (after masking).
4211  *
4212  * Field Enumeration Values:
4213  *
4214  * Enum | Value | Description
4215  * :---------------------------------|:------|:------------
4216  * ALT_MON_GPIO_INTSTAT_PRE_E_INACT | 0x0 | Inactive
4217  * ALT_MON_GPIO_INTSTAT_PRE_E_ACT | 0x1 | Active
4218  *
4219  * Field Access Macros:
4220  *
4221  */
4222 /*
4223  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_PRE
4224  *
4225  * Inactive
4226  */
4227 #define ALT_MON_GPIO_INTSTAT_PRE_E_INACT 0x0
4228 /*
4229  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_PRE
4230  *
4231  * Active
4232  */
4233 #define ALT_MON_GPIO_INTSTAT_PRE_E_ACT 0x1
4234 
4235 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_PRE register field. */
4236 #define ALT_MON_GPIO_INTSTAT_PRE_LSB 6
4237 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_PRE register field. */
4238 #define ALT_MON_GPIO_INTSTAT_PRE_MSB 6
4239 /* The width in bits of the ALT_MON_GPIO_INTSTAT_PRE register field. */
4240 #define ALT_MON_GPIO_INTSTAT_PRE_WIDTH 1
4241 /* The mask used to set the ALT_MON_GPIO_INTSTAT_PRE register field value. */
4242 #define ALT_MON_GPIO_INTSTAT_PRE_SET_MSK 0x00000040
4243 /* The mask used to clear the ALT_MON_GPIO_INTSTAT_PRE register field value. */
4244 #define ALT_MON_GPIO_INTSTAT_PRE_CLR_MSK 0xffffffbf
4245 /* The reset value of the ALT_MON_GPIO_INTSTAT_PRE register field. */
4246 #define ALT_MON_GPIO_INTSTAT_PRE_RESET 0x0
4247 /* Extracts the ALT_MON_GPIO_INTSTAT_PRE field value from a register. */
4248 #define ALT_MON_GPIO_INTSTAT_PRE_GET(value) (((value) & 0x00000040) >> 6)
4249 /* Produces a ALT_MON_GPIO_INTSTAT_PRE register field value suitable for setting the register. */
4250 #define ALT_MON_GPIO_INTSTAT_PRE_SET(value) (((value) << 6) & 0x00000040)
4251 
4252 /*
4253  * Field : Interrupt Status Field (PR_DONE) - prd
4254  *
4255  * Indicates whether PR_DONE has an active interrupt or not (after masking).
4256  *
4257  * Field Enumeration Values:
4258  *
4259  * Enum | Value | Description
4260  * :---------------------------------|:------|:------------
4261  * ALT_MON_GPIO_INTSTAT_PRD_E_INACT | 0x0 | Inactive
4262  * ALT_MON_GPIO_INTSTAT_PRD_E_ACT | 0x1 | Active
4263  *
4264  * Field Access Macros:
4265  *
4266  */
4267 /*
4268  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_PRD
4269  *
4270  * Inactive
4271  */
4272 #define ALT_MON_GPIO_INTSTAT_PRD_E_INACT 0x0
4273 /*
4274  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_PRD
4275  *
4276  * Active
4277  */
4278 #define ALT_MON_GPIO_INTSTAT_PRD_E_ACT 0x1
4279 
4280 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_PRD register field. */
4281 #define ALT_MON_GPIO_INTSTAT_PRD_LSB 7
4282 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_PRD register field. */
4283 #define ALT_MON_GPIO_INTSTAT_PRD_MSB 7
4284 /* The width in bits of the ALT_MON_GPIO_INTSTAT_PRD register field. */
4285 #define ALT_MON_GPIO_INTSTAT_PRD_WIDTH 1
4286 /* The mask used to set the ALT_MON_GPIO_INTSTAT_PRD register field value. */
4287 #define ALT_MON_GPIO_INTSTAT_PRD_SET_MSK 0x00000080
4288 /* The mask used to clear the ALT_MON_GPIO_INTSTAT_PRD register field value. */
4289 #define ALT_MON_GPIO_INTSTAT_PRD_CLR_MSK 0xffffff7f
4290 /* The reset value of the ALT_MON_GPIO_INTSTAT_PRD register field. */
4291 #define ALT_MON_GPIO_INTSTAT_PRD_RESET 0x0
4292 /* Extracts the ALT_MON_GPIO_INTSTAT_PRD field value from a register. */
4293 #define ALT_MON_GPIO_INTSTAT_PRD_GET(value) (((value) & 0x00000080) >> 7)
4294 /* Produces a ALT_MON_GPIO_INTSTAT_PRD register field value suitable for setting the register. */
4295 #define ALT_MON_GPIO_INTSTAT_PRD_SET(value) (((value) << 7) & 0x00000080)
4296 
4297 /*
4298  * Field : Interrupt Status Field (nCONFIG Pin) - ncp
4299  *
4300  * Indicates whether nCONFIG Pin has an active interrupt or not (after masking).
4301  *
4302  * Field Enumeration Values:
4303  *
4304  * Enum | Value | Description
4305  * :---------------------------------|:------|:------------
4306  * ALT_MON_GPIO_INTSTAT_NCP_E_INACT | 0x0 | Inactive
4307  * ALT_MON_GPIO_INTSTAT_NCP_E_ACT | 0x1 | Active
4308  *
4309  * Field Access Macros:
4310  *
4311  */
4312 /*
4313  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_NCP
4314  *
4315  * Inactive
4316  */
4317 #define ALT_MON_GPIO_INTSTAT_NCP_E_INACT 0x0
4318 /*
4319  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_NCP
4320  *
4321  * Active
4322  */
4323 #define ALT_MON_GPIO_INTSTAT_NCP_E_ACT 0x1
4324 
4325 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_NCP register field. */
4326 #define ALT_MON_GPIO_INTSTAT_NCP_LSB 8
4327 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_NCP register field. */
4328 #define ALT_MON_GPIO_INTSTAT_NCP_MSB 8
4329 /* The width in bits of the ALT_MON_GPIO_INTSTAT_NCP register field. */
4330 #define ALT_MON_GPIO_INTSTAT_NCP_WIDTH 1
4331 /* The mask used to set the ALT_MON_GPIO_INTSTAT_NCP register field value. */
4332 #define ALT_MON_GPIO_INTSTAT_NCP_SET_MSK 0x00000100
4333 /* The mask used to clear the ALT_MON_GPIO_INTSTAT_NCP register field value. */
4334 #define ALT_MON_GPIO_INTSTAT_NCP_CLR_MSK 0xfffffeff
4335 /* The reset value of the ALT_MON_GPIO_INTSTAT_NCP register field. */
4336 #define ALT_MON_GPIO_INTSTAT_NCP_RESET 0x0
4337 /* Extracts the ALT_MON_GPIO_INTSTAT_NCP field value from a register. */
4338 #define ALT_MON_GPIO_INTSTAT_NCP_GET(value) (((value) & 0x00000100) >> 8)
4339 /* Produces a ALT_MON_GPIO_INTSTAT_NCP register field value suitable for setting the register. */
4340 #define ALT_MON_GPIO_INTSTAT_NCP_SET(value) (((value) << 8) & 0x00000100)
4341 
4342 /*
4343  * Field : Interrupt Status Field (nSTATUS Pin) - nsp
4344  *
4345  * Indicates whether nSTATUS Pin has an active interrupt or not (after masking).
4346  *
4347  * Field Enumeration Values:
4348  *
4349  * Enum | Value | Description
4350  * :---------------------------------|:------|:------------
4351  * ALT_MON_GPIO_INTSTAT_NSP_E_INACT | 0x0 | Inactive
4352  * ALT_MON_GPIO_INTSTAT_NSP_E_ACT | 0x1 | Active
4353  *
4354  * Field Access Macros:
4355  *
4356  */
4357 /*
4358  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_NSP
4359  *
4360  * Inactive
4361  */
4362 #define ALT_MON_GPIO_INTSTAT_NSP_E_INACT 0x0
4363 /*
4364  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_NSP
4365  *
4366  * Active
4367  */
4368 #define ALT_MON_GPIO_INTSTAT_NSP_E_ACT 0x1
4369 
4370 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_NSP register field. */
4371 #define ALT_MON_GPIO_INTSTAT_NSP_LSB 9
4372 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_NSP register field. */
4373 #define ALT_MON_GPIO_INTSTAT_NSP_MSB 9
4374 /* The width in bits of the ALT_MON_GPIO_INTSTAT_NSP register field. */
4375 #define ALT_MON_GPIO_INTSTAT_NSP_WIDTH 1
4376 /* The mask used to set the ALT_MON_GPIO_INTSTAT_NSP register field value. */
4377 #define ALT_MON_GPIO_INTSTAT_NSP_SET_MSK 0x00000200
4378 /* The mask used to clear the ALT_MON_GPIO_INTSTAT_NSP register field value. */
4379 #define ALT_MON_GPIO_INTSTAT_NSP_CLR_MSK 0xfffffdff
4380 /* The reset value of the ALT_MON_GPIO_INTSTAT_NSP register field. */
4381 #define ALT_MON_GPIO_INTSTAT_NSP_RESET 0x0
4382 /* Extracts the ALT_MON_GPIO_INTSTAT_NSP field value from a register. */
4383 #define ALT_MON_GPIO_INTSTAT_NSP_GET(value) (((value) & 0x00000200) >> 9)
4384 /* Produces a ALT_MON_GPIO_INTSTAT_NSP register field value suitable for setting the register. */
4385 #define ALT_MON_GPIO_INTSTAT_NSP_SET(value) (((value) << 9) & 0x00000200)
4386 
4387 /*
4388  * Field : Interrupt Status Field (CONF_DONE Pin) - cdp
4389  *
4390  * Indicates whether CONF_DONE Pin has an active interrupt or not (after masking).
4391  *
4392  * Field Enumeration Values:
4393  *
4394  * Enum | Value | Description
4395  * :---------------------------------|:------|:------------
4396  * ALT_MON_GPIO_INTSTAT_CDP_E_INACT | 0x0 | Inactive
4397  * ALT_MON_GPIO_INTSTAT_CDP_E_ACT | 0x1 | Active
4398  *
4399  * Field Access Macros:
4400  *
4401  */
4402 /*
4403  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CDP
4404  *
4405  * Inactive
4406  */
4407 #define ALT_MON_GPIO_INTSTAT_CDP_E_INACT 0x0
4408 /*
4409  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_CDP
4410  *
4411  * Active
4412  */
4413 #define ALT_MON_GPIO_INTSTAT_CDP_E_ACT 0x1
4414 
4415 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_CDP register field. */
4416 #define ALT_MON_GPIO_INTSTAT_CDP_LSB 10
4417 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_CDP register field. */
4418 #define ALT_MON_GPIO_INTSTAT_CDP_MSB 10
4419 /* The width in bits of the ALT_MON_GPIO_INTSTAT_CDP register field. */
4420 #define ALT_MON_GPIO_INTSTAT_CDP_WIDTH 1
4421 /* The mask used to set the ALT_MON_GPIO_INTSTAT_CDP register field value. */
4422 #define ALT_MON_GPIO_INTSTAT_CDP_SET_MSK 0x00000400
4423 /* The mask used to clear the ALT_MON_GPIO_INTSTAT_CDP register field value. */
4424 #define ALT_MON_GPIO_INTSTAT_CDP_CLR_MSK 0xfffffbff
4425 /* The reset value of the ALT_MON_GPIO_INTSTAT_CDP register field. */
4426 #define ALT_MON_GPIO_INTSTAT_CDP_RESET 0x0
4427 /* Extracts the ALT_MON_GPIO_INTSTAT_CDP field value from a register. */
4428 #define ALT_MON_GPIO_INTSTAT_CDP_GET(value) (((value) & 0x00000400) >> 10)
4429 /* Produces a ALT_MON_GPIO_INTSTAT_CDP register field value suitable for setting the register. */
4430 #define ALT_MON_GPIO_INTSTAT_CDP_SET(value) (((value) << 10) & 0x00000400)
4431 
4432 /*
4433  * Field : Interrupt Status Field (FPGA_POWER_ON) - fpo
4434  *
4435  * Indicates whether FPGA_POWER_ON has an active interrupt or not (after masking).
4436  *
4437  * Field Enumeration Values:
4438  *
4439  * Enum | Value | Description
4440  * :---------------------------------|:------|:------------
4441  * ALT_MON_GPIO_INTSTAT_FPO_E_INACT | 0x0 | Inactive
4442  * ALT_MON_GPIO_INTSTAT_FPO_E_ACT | 0x1 | Active
4443  *
4444  * Field Access Macros:
4445  *
4446  */
4447 /*
4448  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_FPO
4449  *
4450  * Inactive
4451  */
4452 #define ALT_MON_GPIO_INTSTAT_FPO_E_INACT 0x0
4453 /*
4454  * Enumerated value for register field ALT_MON_GPIO_INTSTAT_FPO
4455  *
4456  * Active
4457  */
4458 #define ALT_MON_GPIO_INTSTAT_FPO_E_ACT 0x1
4459 
4460 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_INTSTAT_FPO register field. */
4461 #define ALT_MON_GPIO_INTSTAT_FPO_LSB 11
4462 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_INTSTAT_FPO register field. */
4463 #define ALT_MON_GPIO_INTSTAT_FPO_MSB 11
4464 /* The width in bits of the ALT_MON_GPIO_INTSTAT_FPO register field. */
4465 #define ALT_MON_GPIO_INTSTAT_FPO_WIDTH 1
4466 /* The mask used to set the ALT_MON_GPIO_INTSTAT_FPO register field value. */
4467 #define ALT_MON_GPIO_INTSTAT_FPO_SET_MSK 0x00000800
4468 /* The mask used to clear the ALT_MON_GPIO_INTSTAT_FPO register field value. */
4469 #define ALT_MON_GPIO_INTSTAT_FPO_CLR_MSK 0xfffff7ff
4470 /* The reset value of the ALT_MON_GPIO_INTSTAT_FPO register field. */
4471 #define ALT_MON_GPIO_INTSTAT_FPO_RESET 0x0
4472 /* Extracts the ALT_MON_GPIO_INTSTAT_FPO field value from a register. */
4473 #define ALT_MON_GPIO_INTSTAT_FPO_GET(value) (((value) & 0x00000800) >> 11)
4474 /* Produces a ALT_MON_GPIO_INTSTAT_FPO register field value suitable for setting the register. */
4475 #define ALT_MON_GPIO_INTSTAT_FPO_SET(value) (((value) << 11) & 0x00000800)
4476 
4477 #ifndef __ASSEMBLY__
4478 /*
4479  * WARNING: The C register and register group struct declarations are provided for
4480  * convenience and illustrative purposes. They should, however, be used with
4481  * caution as the C language standard provides no guarantees about the alignment or
4482  * atomicity of device memory accesses. The recommended practice for writing
4483  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4484  * alt_write_word() functions.
4485  *
4486  * The struct declaration for register ALT_MON_GPIO_INTSTAT.
4487  */
4488 struct ALT_MON_GPIO_INTSTAT_s
4489 {
4490  const uint32_t ns : 1; /* Interrupt Status Field (nSTATUS) */
4491  const uint32_t cd : 1; /* Interrupt Status Field (CONF_DONE) */
4492  const uint32_t id : 1; /* Interrupt Status Field (INIT_DONE) */
4493  const uint32_t crc : 1; /* Interrupt Status Field (CRC_ERROR) */
4494  const uint32_t ccd : 1; /* Interrupt Status Field (CVP_CONF_DONE) */
4495  const uint32_t prr : 1; /* Interrupt Status Field (PR_READY) */
4496  const uint32_t pre : 1; /* Interrupt Status Field (PR_ERROR) */
4497  const uint32_t prd : 1; /* Interrupt Status Field (PR_DONE) */
4498  const uint32_t ncp : 1; /* Interrupt Status Field (nCONFIG Pin) */
4499  const uint32_t nsp : 1; /* Interrupt Status Field (nSTATUS Pin) */
4500  const uint32_t cdp : 1; /* Interrupt Status Field (CONF_DONE Pin) */
4501  const uint32_t fpo : 1; /* Interrupt Status Field (FPGA_POWER_ON) */
4502  uint32_t : 20; /* *UNDEFINED* */
4503 };
4504 
4505 /* The typedef declaration for register ALT_MON_GPIO_INTSTAT. */
4506 typedef volatile struct ALT_MON_GPIO_INTSTAT_s ALT_MON_GPIO_INTSTAT_t;
4507 #endif /* __ASSEMBLY__ */
4508 
4509 /* The byte offset of the ALT_MON_GPIO_INTSTAT register from the beginning of the component. */
4510 #define ALT_MON_GPIO_INTSTAT_OFST 0x40
4511 /* The address of the ALT_MON_GPIO_INTSTAT register. */
4512 #define ALT_MON_GPIO_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_INTSTAT_OFST))
4513 
4514 /*
4515  * Register : Raw Interrupt Status Register - gpio_raw_intstatus
4516  *
4517  * Reports on raw interrupt status for each GPIO input. The raw interrupt status
4518  * excludes the effects of masking.
4519  *
4520  * Register Layout
4521  *
4522  * Bits | Access | Reset | Description
4523  * :--------|:-------|:------|:-------------------------------------------
4524  * [0] | R | 0x0 | Raw Interrupt Status Field (nSTATUS)
4525  * [1] | R | 0x0 | Raw Interrupt Status Field (CONF_DONE)
4526  * [2] | R | 0x0 | Raw Interrupt Status Field (INIT_DONE)
4527  * [3] | R | 0x0 | Raw Interrupt Status Field (CRC_ERROR)
4528  * [4] | R | 0x0 | Raw Interrupt Status Field (CVP_CONF_DONE)
4529  * [5] | R | 0x0 | Raw Interrupt Status Field (PR_READY)
4530  * [6] | R | 0x0 | Raw Interrupt Status Field (PR_ERROR)
4531  * [7] | R | 0x0 | Raw Interrupt Status Field (PR_DONE)
4532  * [8] | R | 0x0 | Raw Interrupt Status Field (nCONFIG Pin)
4533  * [9] | R | 0x0 | Raw Interrupt Status Field (nSTATUS Pin)
4534  * [10] | R | 0x0 | Raw Interrupt Status Field (CONF_DONE Pin)
4535  * [11] | R | 0x0 | Raw Interrupt Status Field (FPGA_POWER_ON)
4536  * [31:12] | ??? | 0x0 | *UNDEFINED*
4537  *
4538  */
4539 /*
4540  * Field : Raw Interrupt Status Field (nSTATUS) - ns
4541  *
4542  * Indicates whether nSTATUS has an active interrupt or not (before masking).
4543  *
4544  * Field Enumeration Values:
4545  *
4546  * Enum | Value | Description
4547  * :------------------------------------|:------|:------------
4548  * ALT_MON_GPIO_RAW_INTSTAT_NS_E_INACT | 0x0 | Inactive
4549  * ALT_MON_GPIO_RAW_INTSTAT_NS_E_ACT | 0x1 | Active
4550  *
4551  * Field Access Macros:
4552  *
4553  */
4554 /*
4555  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_NS
4556  *
4557  * Inactive
4558  */
4559 #define ALT_MON_GPIO_RAW_INTSTAT_NS_E_INACT 0x0
4560 /*
4561  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_NS
4562  *
4563  * Active
4564  */
4565 #define ALT_MON_GPIO_RAW_INTSTAT_NS_E_ACT 0x1
4566 
4567 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_NS register field. */
4568 #define ALT_MON_GPIO_RAW_INTSTAT_NS_LSB 0
4569 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_NS register field. */
4570 #define ALT_MON_GPIO_RAW_INTSTAT_NS_MSB 0
4571 /* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_NS register field. */
4572 #define ALT_MON_GPIO_RAW_INTSTAT_NS_WIDTH 1
4573 /* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_NS register field value. */
4574 #define ALT_MON_GPIO_RAW_INTSTAT_NS_SET_MSK 0x00000001
4575 /* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_NS register field value. */
4576 #define ALT_MON_GPIO_RAW_INTSTAT_NS_CLR_MSK 0xfffffffe
4577 /* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_NS register field. */
4578 #define ALT_MON_GPIO_RAW_INTSTAT_NS_RESET 0x0
4579 /* Extracts the ALT_MON_GPIO_RAW_INTSTAT_NS field value from a register. */
4580 #define ALT_MON_GPIO_RAW_INTSTAT_NS_GET(value) (((value) & 0x00000001) >> 0)
4581 /* Produces a ALT_MON_GPIO_RAW_INTSTAT_NS register field value suitable for setting the register. */
4582 #define ALT_MON_GPIO_RAW_INTSTAT_NS_SET(value) (((value) << 0) & 0x00000001)
4583 
4584 /*
4585  * Field : Raw Interrupt Status Field (CONF_DONE) - cd
4586  *
4587  * Indicates whether CONF_DONE has an active interrupt or not (before masking).
4588  *
4589  * Field Enumeration Values:
4590  *
4591  * Enum | Value | Description
4592  * :------------------------------------|:------|:------------
4593  * ALT_MON_GPIO_RAW_INTSTAT_CD_E_INACT | 0x0 | Inactive
4594  * ALT_MON_GPIO_RAW_INTSTAT_CD_E_ACT | 0x1 | Active
4595  *
4596  * Field Access Macros:
4597  *
4598  */
4599 /*
4600  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CD
4601  *
4602  * Inactive
4603  */
4604 #define ALT_MON_GPIO_RAW_INTSTAT_CD_E_INACT 0x0
4605 /*
4606  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CD
4607  *
4608  * Active
4609  */
4610 #define ALT_MON_GPIO_RAW_INTSTAT_CD_E_ACT 0x1
4611 
4612 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CD register field. */
4613 #define ALT_MON_GPIO_RAW_INTSTAT_CD_LSB 1
4614 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CD register field. */
4615 #define ALT_MON_GPIO_RAW_INTSTAT_CD_MSB 1
4616 /* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_CD register field. */
4617 #define ALT_MON_GPIO_RAW_INTSTAT_CD_WIDTH 1
4618 /* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_CD register field value. */
4619 #define ALT_MON_GPIO_RAW_INTSTAT_CD_SET_MSK 0x00000002
4620 /* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_CD register field value. */
4621 #define ALT_MON_GPIO_RAW_INTSTAT_CD_CLR_MSK 0xfffffffd
4622 /* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_CD register field. */
4623 #define ALT_MON_GPIO_RAW_INTSTAT_CD_RESET 0x0
4624 /* Extracts the ALT_MON_GPIO_RAW_INTSTAT_CD field value from a register. */
4625 #define ALT_MON_GPIO_RAW_INTSTAT_CD_GET(value) (((value) & 0x00000002) >> 1)
4626 /* Produces a ALT_MON_GPIO_RAW_INTSTAT_CD register field value suitable for setting the register. */
4627 #define ALT_MON_GPIO_RAW_INTSTAT_CD_SET(value) (((value) << 1) & 0x00000002)
4628 
4629 /*
4630  * Field : Raw Interrupt Status Field (INIT_DONE) - id
4631  *
4632  * Indicates whether INIT_DONE has an active interrupt or not (before masking).
4633  *
4634  * Field Enumeration Values:
4635  *
4636  * Enum | Value | Description
4637  * :------------------------------------|:------|:------------
4638  * ALT_MON_GPIO_RAW_INTSTAT_ID_E_INACT | 0x0 | Inactive
4639  * ALT_MON_GPIO_RAW_INTSTAT_ID_E_ACT | 0x1 | Active
4640  *
4641  * Field Access Macros:
4642  *
4643  */
4644 /*
4645  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_ID
4646  *
4647  * Inactive
4648  */
4649 #define ALT_MON_GPIO_RAW_INTSTAT_ID_E_INACT 0x0
4650 /*
4651  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_ID
4652  *
4653  * Active
4654  */
4655 #define ALT_MON_GPIO_RAW_INTSTAT_ID_E_ACT 0x1
4656 
4657 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_ID register field. */
4658 #define ALT_MON_GPIO_RAW_INTSTAT_ID_LSB 2
4659 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_ID register field. */
4660 #define ALT_MON_GPIO_RAW_INTSTAT_ID_MSB 2
4661 /* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_ID register field. */
4662 #define ALT_MON_GPIO_RAW_INTSTAT_ID_WIDTH 1
4663 /* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_ID register field value. */
4664 #define ALT_MON_GPIO_RAW_INTSTAT_ID_SET_MSK 0x00000004
4665 /* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_ID register field value. */
4666 #define ALT_MON_GPIO_RAW_INTSTAT_ID_CLR_MSK 0xfffffffb
4667 /* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_ID register field. */
4668 #define ALT_MON_GPIO_RAW_INTSTAT_ID_RESET 0x0
4669 /* Extracts the ALT_MON_GPIO_RAW_INTSTAT_ID field value from a register. */
4670 #define ALT_MON_GPIO_RAW_INTSTAT_ID_GET(value) (((value) & 0x00000004) >> 2)
4671 /* Produces a ALT_MON_GPIO_RAW_INTSTAT_ID register field value suitable for setting the register. */
4672 #define ALT_MON_GPIO_RAW_INTSTAT_ID_SET(value) (((value) << 2) & 0x00000004)
4673 
4674 /*
4675  * Field : Raw Interrupt Status Field (CRC_ERROR) - crc
4676  *
4677  * Indicates whether CRC_ERROR has an active interrupt or not (before masking).
4678  *
4679  * Field Enumeration Values:
4680  *
4681  * Enum | Value | Description
4682  * :-------------------------------------|:------|:------------
4683  * ALT_MON_GPIO_RAW_INTSTAT_CRC_E_INACT | 0x0 | Inactive
4684  * ALT_MON_GPIO_RAW_INTSTAT_CRC_E_ACT | 0x1 | Active
4685  *
4686  * Field Access Macros:
4687  *
4688  */
4689 /*
4690  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CRC
4691  *
4692  * Inactive
4693  */
4694 #define ALT_MON_GPIO_RAW_INTSTAT_CRC_E_INACT 0x0
4695 /*
4696  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CRC
4697  *
4698  * Active
4699  */
4700 #define ALT_MON_GPIO_RAW_INTSTAT_CRC_E_ACT 0x1
4701 
4702 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CRC register field. */
4703 #define ALT_MON_GPIO_RAW_INTSTAT_CRC_LSB 3
4704 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CRC register field. */
4705 #define ALT_MON_GPIO_RAW_INTSTAT_CRC_MSB 3
4706 /* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_CRC register field. */
4707 #define ALT_MON_GPIO_RAW_INTSTAT_CRC_WIDTH 1
4708 /* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_CRC register field value. */
4709 #define ALT_MON_GPIO_RAW_INTSTAT_CRC_SET_MSK 0x00000008
4710 /* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_CRC register field value. */
4711 #define ALT_MON_GPIO_RAW_INTSTAT_CRC_CLR_MSK 0xfffffff7
4712 /* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_CRC register field. */
4713 #define ALT_MON_GPIO_RAW_INTSTAT_CRC_RESET 0x0
4714 /* Extracts the ALT_MON_GPIO_RAW_INTSTAT_CRC field value from a register. */
4715 #define ALT_MON_GPIO_RAW_INTSTAT_CRC_GET(value) (((value) & 0x00000008) >> 3)
4716 /* Produces a ALT_MON_GPIO_RAW_INTSTAT_CRC register field value suitable for setting the register. */
4717 #define ALT_MON_GPIO_RAW_INTSTAT_CRC_SET(value) (((value) << 3) & 0x00000008)
4718 
4719 /*
4720  * Field : Raw Interrupt Status Field (CVP_CONF_DONE) - ccd
4721  *
4722  * Indicates whether CVP_CONF_DONE has an active interrupt or not (before masking).
4723  *
4724  * Field Enumeration Values:
4725  *
4726  * Enum | Value | Description
4727  * :-------------------------------------|:------|:------------
4728  * ALT_MON_GPIO_RAW_INTSTAT_CCD_E_INACT | 0x0 | Inactive
4729  * ALT_MON_GPIO_RAW_INTSTAT_CCD_E_ACT | 0x1 | Active
4730  *
4731  * Field Access Macros:
4732  *
4733  */
4734 /*
4735  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CCD
4736  *
4737  * Inactive
4738  */
4739 #define ALT_MON_GPIO_RAW_INTSTAT_CCD_E_INACT 0x0
4740 /*
4741  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CCD
4742  *
4743  * Active
4744  */
4745 #define ALT_MON_GPIO_RAW_INTSTAT_CCD_E_ACT 0x1
4746 
4747 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CCD register field. */
4748 #define ALT_MON_GPIO_RAW_INTSTAT_CCD_LSB 4
4749 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CCD register field. */
4750 #define ALT_MON_GPIO_RAW_INTSTAT_CCD_MSB 4
4751 /* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_CCD register field. */
4752 #define ALT_MON_GPIO_RAW_INTSTAT_CCD_WIDTH 1
4753 /* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_CCD register field value. */
4754 #define ALT_MON_GPIO_RAW_INTSTAT_CCD_SET_MSK 0x00000010
4755 /* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_CCD register field value. */
4756 #define ALT_MON_GPIO_RAW_INTSTAT_CCD_CLR_MSK 0xffffffef
4757 /* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_CCD register field. */
4758 #define ALT_MON_GPIO_RAW_INTSTAT_CCD_RESET 0x0
4759 /* Extracts the ALT_MON_GPIO_RAW_INTSTAT_CCD field value from a register. */
4760 #define ALT_MON_GPIO_RAW_INTSTAT_CCD_GET(value) (((value) & 0x00000010) >> 4)
4761 /* Produces a ALT_MON_GPIO_RAW_INTSTAT_CCD register field value suitable for setting the register. */
4762 #define ALT_MON_GPIO_RAW_INTSTAT_CCD_SET(value) (((value) << 4) & 0x00000010)
4763 
4764 /*
4765  * Field : Raw Interrupt Status Field (PR_READY) - prr
4766  *
4767  * Indicates whether PR_READY has an active interrupt or not (before masking).
4768  *
4769  * Field Enumeration Values:
4770  *
4771  * Enum | Value | Description
4772  * :-------------------------------------|:------|:------------
4773  * ALT_MON_GPIO_RAW_INTSTAT_PRR_E_INACT | 0x0 | Inactive
4774  * ALT_MON_GPIO_RAW_INTSTAT_PRR_E_ACT | 0x1 | Active
4775  *
4776  * Field Access Macros:
4777  *
4778  */
4779 /*
4780  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_PRR
4781  *
4782  * Inactive
4783  */
4784 #define ALT_MON_GPIO_RAW_INTSTAT_PRR_E_INACT 0x0
4785 /*
4786  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_PRR
4787  *
4788  * Active
4789  */
4790 #define ALT_MON_GPIO_RAW_INTSTAT_PRR_E_ACT 0x1
4791 
4792 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_PRR register field. */
4793 #define ALT_MON_GPIO_RAW_INTSTAT_PRR_LSB 5
4794 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_PRR register field. */
4795 #define ALT_MON_GPIO_RAW_INTSTAT_PRR_MSB 5
4796 /* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_PRR register field. */
4797 #define ALT_MON_GPIO_RAW_INTSTAT_PRR_WIDTH 1
4798 /* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_PRR register field value. */
4799 #define ALT_MON_GPIO_RAW_INTSTAT_PRR_SET_MSK 0x00000020
4800 /* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_PRR register field value. */
4801 #define ALT_MON_GPIO_RAW_INTSTAT_PRR_CLR_MSK 0xffffffdf
4802 /* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_PRR register field. */
4803 #define ALT_MON_GPIO_RAW_INTSTAT_PRR_RESET 0x0
4804 /* Extracts the ALT_MON_GPIO_RAW_INTSTAT_PRR field value from a register. */
4805 #define ALT_MON_GPIO_RAW_INTSTAT_PRR_GET(value) (((value) & 0x00000020) >> 5)
4806 /* Produces a ALT_MON_GPIO_RAW_INTSTAT_PRR register field value suitable for setting the register. */
4807 #define ALT_MON_GPIO_RAW_INTSTAT_PRR_SET(value) (((value) << 5) & 0x00000020)
4808 
4809 /*
4810  * Field : Raw Interrupt Status Field (PR_ERROR) - pre
4811  *
4812  * Indicates whether PR_ERROR has an active interrupt or not (before masking).
4813  *
4814  * Field Enumeration Values:
4815  *
4816  * Enum | Value | Description
4817  * :-------------------------------------|:------|:------------
4818  * ALT_MON_GPIO_RAW_INTSTAT_PRE_E_INACT | 0x0 | Inactive
4819  * ALT_MON_GPIO_RAW_INTSTAT_PRE_E_ACT | 0x1 | Active
4820  *
4821  * Field Access Macros:
4822  *
4823  */
4824 /*
4825  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_PRE
4826  *
4827  * Inactive
4828  */
4829 #define ALT_MON_GPIO_RAW_INTSTAT_PRE_E_INACT 0x0
4830 /*
4831  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_PRE
4832  *
4833  * Active
4834  */
4835 #define ALT_MON_GPIO_RAW_INTSTAT_PRE_E_ACT 0x1
4836 
4837 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_PRE register field. */
4838 #define ALT_MON_GPIO_RAW_INTSTAT_PRE_LSB 6
4839 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_PRE register field. */
4840 #define ALT_MON_GPIO_RAW_INTSTAT_PRE_MSB 6
4841 /* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_PRE register field. */
4842 #define ALT_MON_GPIO_RAW_INTSTAT_PRE_WIDTH 1
4843 /* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_PRE register field value. */
4844 #define ALT_MON_GPIO_RAW_INTSTAT_PRE_SET_MSK 0x00000040
4845 /* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_PRE register field value. */
4846 #define ALT_MON_GPIO_RAW_INTSTAT_PRE_CLR_MSK 0xffffffbf
4847 /* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_PRE register field. */
4848 #define ALT_MON_GPIO_RAW_INTSTAT_PRE_RESET 0x0
4849 /* Extracts the ALT_MON_GPIO_RAW_INTSTAT_PRE field value from a register. */
4850 #define ALT_MON_GPIO_RAW_INTSTAT_PRE_GET(value) (((value) & 0x00000040) >> 6)
4851 /* Produces a ALT_MON_GPIO_RAW_INTSTAT_PRE register field value suitable for setting the register. */
4852 #define ALT_MON_GPIO_RAW_INTSTAT_PRE_SET(value) (((value) << 6) & 0x00000040)
4853 
4854 /*
4855  * Field : Raw Interrupt Status Field (PR_DONE) - prd
4856  *
4857  * Indicates whether PR_DONE has an active interrupt or not (before masking).
4858  *
4859  * Field Enumeration Values:
4860  *
4861  * Enum | Value | Description
4862  * :-------------------------------------|:------|:------------
4863  * ALT_MON_GPIO_RAW_INTSTAT_PRD_E_INACT | 0x0 | Inactive
4864  * ALT_MON_GPIO_RAW_INTSTAT_PRD_E_ACT | 0x1 | Active
4865  *
4866  * Field Access Macros:
4867  *
4868  */
4869 /*
4870  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_PRD
4871  *
4872  * Inactive
4873  */
4874 #define ALT_MON_GPIO_RAW_INTSTAT_PRD_E_INACT 0x0
4875 /*
4876  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_PRD
4877  *
4878  * Active
4879  */
4880 #define ALT_MON_GPIO_RAW_INTSTAT_PRD_E_ACT 0x1
4881 
4882 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_PRD register field. */
4883 #define ALT_MON_GPIO_RAW_INTSTAT_PRD_LSB 7
4884 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_PRD register field. */
4885 #define ALT_MON_GPIO_RAW_INTSTAT_PRD_MSB 7
4886 /* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_PRD register field. */
4887 #define ALT_MON_GPIO_RAW_INTSTAT_PRD_WIDTH 1
4888 /* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_PRD register field value. */
4889 #define ALT_MON_GPIO_RAW_INTSTAT_PRD_SET_MSK 0x00000080
4890 /* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_PRD register field value. */
4891 #define ALT_MON_GPIO_RAW_INTSTAT_PRD_CLR_MSK 0xffffff7f
4892 /* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_PRD register field. */
4893 #define ALT_MON_GPIO_RAW_INTSTAT_PRD_RESET 0x0
4894 /* Extracts the ALT_MON_GPIO_RAW_INTSTAT_PRD field value from a register. */
4895 #define ALT_MON_GPIO_RAW_INTSTAT_PRD_GET(value) (((value) & 0x00000080) >> 7)
4896 /* Produces a ALT_MON_GPIO_RAW_INTSTAT_PRD register field value suitable for setting the register. */
4897 #define ALT_MON_GPIO_RAW_INTSTAT_PRD_SET(value) (((value) << 7) & 0x00000080)
4898 
4899 /*
4900  * Field : Raw Interrupt Status Field (nCONFIG Pin) - ncp
4901  *
4902  * Indicates whether nCONFIG Pin has an active interrupt or not (before masking).
4903  *
4904  * Field Enumeration Values:
4905  *
4906  * Enum | Value | Description
4907  * :-------------------------------------|:------|:------------
4908  * ALT_MON_GPIO_RAW_INTSTAT_NCP_E_INACT | 0x0 | Inactive
4909  * ALT_MON_GPIO_RAW_INTSTAT_NCP_E_ACT | 0x1 | Active
4910  *
4911  * Field Access Macros:
4912  *
4913  */
4914 /*
4915  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_NCP
4916  *
4917  * Inactive
4918  */
4919 #define ALT_MON_GPIO_RAW_INTSTAT_NCP_E_INACT 0x0
4920 /*
4921  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_NCP
4922  *
4923  * Active
4924  */
4925 #define ALT_MON_GPIO_RAW_INTSTAT_NCP_E_ACT 0x1
4926 
4927 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_NCP register field. */
4928 #define ALT_MON_GPIO_RAW_INTSTAT_NCP_LSB 8
4929 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_NCP register field. */
4930 #define ALT_MON_GPIO_RAW_INTSTAT_NCP_MSB 8
4931 /* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_NCP register field. */
4932 #define ALT_MON_GPIO_RAW_INTSTAT_NCP_WIDTH 1
4933 /* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_NCP register field value. */
4934 #define ALT_MON_GPIO_RAW_INTSTAT_NCP_SET_MSK 0x00000100
4935 /* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_NCP register field value. */
4936 #define ALT_MON_GPIO_RAW_INTSTAT_NCP_CLR_MSK 0xfffffeff
4937 /* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_NCP register field. */
4938 #define ALT_MON_GPIO_RAW_INTSTAT_NCP_RESET 0x0
4939 /* Extracts the ALT_MON_GPIO_RAW_INTSTAT_NCP field value from a register. */
4940 #define ALT_MON_GPIO_RAW_INTSTAT_NCP_GET(value) (((value) & 0x00000100) >> 8)
4941 /* Produces a ALT_MON_GPIO_RAW_INTSTAT_NCP register field value suitable for setting the register. */
4942 #define ALT_MON_GPIO_RAW_INTSTAT_NCP_SET(value) (((value) << 8) & 0x00000100)
4943 
4944 /*
4945  * Field : Raw Interrupt Status Field (nSTATUS Pin) - nsp
4946  *
4947  * Indicates whether nSTATUS Pin has an active interrupt or not (before masking).
4948  *
4949  * Field Enumeration Values:
4950  *
4951  * Enum | Value | Description
4952  * :-------------------------------------|:------|:------------
4953  * ALT_MON_GPIO_RAW_INTSTAT_NSP_E_INACT | 0x0 | Inactive
4954  * ALT_MON_GPIO_RAW_INTSTAT_NSP_E_ACT | 0x1 | Active
4955  *
4956  * Field Access Macros:
4957  *
4958  */
4959 /*
4960  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_NSP
4961  *
4962  * Inactive
4963  */
4964 #define ALT_MON_GPIO_RAW_INTSTAT_NSP_E_INACT 0x0
4965 /*
4966  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_NSP
4967  *
4968  * Active
4969  */
4970 #define ALT_MON_GPIO_RAW_INTSTAT_NSP_E_ACT 0x1
4971 
4972 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_NSP register field. */
4973 #define ALT_MON_GPIO_RAW_INTSTAT_NSP_LSB 9
4974 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_NSP register field. */
4975 #define ALT_MON_GPIO_RAW_INTSTAT_NSP_MSB 9
4976 /* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_NSP register field. */
4977 #define ALT_MON_GPIO_RAW_INTSTAT_NSP_WIDTH 1
4978 /* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_NSP register field value. */
4979 #define ALT_MON_GPIO_RAW_INTSTAT_NSP_SET_MSK 0x00000200
4980 /* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_NSP register field value. */
4981 #define ALT_MON_GPIO_RAW_INTSTAT_NSP_CLR_MSK 0xfffffdff
4982 /* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_NSP register field. */
4983 #define ALT_MON_GPIO_RAW_INTSTAT_NSP_RESET 0x0
4984 /* Extracts the ALT_MON_GPIO_RAW_INTSTAT_NSP field value from a register. */
4985 #define ALT_MON_GPIO_RAW_INTSTAT_NSP_GET(value) (((value) & 0x00000200) >> 9)
4986 /* Produces a ALT_MON_GPIO_RAW_INTSTAT_NSP register field value suitable for setting the register. */
4987 #define ALT_MON_GPIO_RAW_INTSTAT_NSP_SET(value) (((value) << 9) & 0x00000200)
4988 
4989 /*
4990  * Field : Raw Interrupt Status Field (CONF_DONE Pin) - cdp
4991  *
4992  * Indicates whether CONF_DONE Pin has an active interrupt or not (before masking).
4993  *
4994  * Field Enumeration Values:
4995  *
4996  * Enum | Value | Description
4997  * :-------------------------------------|:------|:------------
4998  * ALT_MON_GPIO_RAW_INTSTAT_CDP_E_INACT | 0x0 | Inactive
4999  * ALT_MON_GPIO_RAW_INTSTAT_CDP_E_ACT | 0x1 | Active
5000  *
5001  * Field Access Macros:
5002  *
5003  */
5004 /*
5005  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CDP
5006  *
5007  * Inactive
5008  */
5009 #define ALT_MON_GPIO_RAW_INTSTAT_CDP_E_INACT 0x0
5010 /*
5011  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_CDP
5012  *
5013  * Active
5014  */
5015 #define ALT_MON_GPIO_RAW_INTSTAT_CDP_E_ACT 0x1
5016 
5017 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CDP register field. */
5018 #define ALT_MON_GPIO_RAW_INTSTAT_CDP_LSB 10
5019 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_CDP register field. */
5020 #define ALT_MON_GPIO_RAW_INTSTAT_CDP_MSB 10
5021 /* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_CDP register field. */
5022 #define ALT_MON_GPIO_RAW_INTSTAT_CDP_WIDTH 1
5023 /* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_CDP register field value. */
5024 #define ALT_MON_GPIO_RAW_INTSTAT_CDP_SET_MSK 0x00000400
5025 /* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_CDP register field value. */
5026 #define ALT_MON_GPIO_RAW_INTSTAT_CDP_CLR_MSK 0xfffffbff
5027 /* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_CDP register field. */
5028 #define ALT_MON_GPIO_RAW_INTSTAT_CDP_RESET 0x0
5029 /* Extracts the ALT_MON_GPIO_RAW_INTSTAT_CDP field value from a register. */
5030 #define ALT_MON_GPIO_RAW_INTSTAT_CDP_GET(value) (((value) & 0x00000400) >> 10)
5031 /* Produces a ALT_MON_GPIO_RAW_INTSTAT_CDP register field value suitable for setting the register. */
5032 #define ALT_MON_GPIO_RAW_INTSTAT_CDP_SET(value) (((value) << 10) & 0x00000400)
5033 
5034 /*
5035  * Field : Raw Interrupt Status Field (FPGA_POWER_ON) - fpo
5036  *
5037  * Indicates whether FPGA_POWER_ON has an active interrupt or not (before masking).
5038  *
5039  * Field Enumeration Values:
5040  *
5041  * Enum | Value | Description
5042  * :-------------------------------------|:------|:------------
5043  * ALT_MON_GPIO_RAW_INTSTAT_FPO_E_INACT | 0x0 | Inactive
5044  * ALT_MON_GPIO_RAW_INTSTAT_FPO_E_ACT | 0x1 | Active
5045  *
5046  * Field Access Macros:
5047  *
5048  */
5049 /*
5050  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_FPO
5051  *
5052  * Inactive
5053  */
5054 #define ALT_MON_GPIO_RAW_INTSTAT_FPO_E_INACT 0x0
5055 /*
5056  * Enumerated value for register field ALT_MON_GPIO_RAW_INTSTAT_FPO
5057  *
5058  * Active
5059  */
5060 #define ALT_MON_GPIO_RAW_INTSTAT_FPO_E_ACT 0x1
5061 
5062 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_RAW_INTSTAT_FPO register field. */
5063 #define ALT_MON_GPIO_RAW_INTSTAT_FPO_LSB 11
5064 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_RAW_INTSTAT_FPO register field. */
5065 #define ALT_MON_GPIO_RAW_INTSTAT_FPO_MSB 11
5066 /* The width in bits of the ALT_MON_GPIO_RAW_INTSTAT_FPO register field. */
5067 #define ALT_MON_GPIO_RAW_INTSTAT_FPO_WIDTH 1
5068 /* The mask used to set the ALT_MON_GPIO_RAW_INTSTAT_FPO register field value. */
5069 #define ALT_MON_GPIO_RAW_INTSTAT_FPO_SET_MSK 0x00000800
5070 /* The mask used to clear the ALT_MON_GPIO_RAW_INTSTAT_FPO register field value. */
5071 #define ALT_MON_GPIO_RAW_INTSTAT_FPO_CLR_MSK 0xfffff7ff
5072 /* The reset value of the ALT_MON_GPIO_RAW_INTSTAT_FPO register field. */
5073 #define ALT_MON_GPIO_RAW_INTSTAT_FPO_RESET 0x0
5074 /* Extracts the ALT_MON_GPIO_RAW_INTSTAT_FPO field value from a register. */
5075 #define ALT_MON_GPIO_RAW_INTSTAT_FPO_GET(value) (((value) & 0x00000800) >> 11)
5076 /* Produces a ALT_MON_GPIO_RAW_INTSTAT_FPO register field value suitable for setting the register. */
5077 #define ALT_MON_GPIO_RAW_INTSTAT_FPO_SET(value) (((value) << 11) & 0x00000800)
5078 
5079 #ifndef __ASSEMBLY__
5080 /*
5081  * WARNING: The C register and register group struct declarations are provided for
5082  * convenience and illustrative purposes. They should, however, be used with
5083  * caution as the C language standard provides no guarantees about the alignment or
5084  * atomicity of device memory accesses. The recommended practice for writing
5085  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5086  * alt_write_word() functions.
5087  *
5088  * The struct declaration for register ALT_MON_GPIO_RAW_INTSTAT.
5089  */
5090 struct ALT_MON_GPIO_RAW_INTSTAT_s
5091 {
5092  const uint32_t ns : 1; /* Raw Interrupt Status Field (nSTATUS) */
5093  const uint32_t cd : 1; /* Raw Interrupt Status Field (CONF_DONE) */
5094  const uint32_t id : 1; /* Raw Interrupt Status Field (INIT_DONE) */
5095  const uint32_t crc : 1; /* Raw Interrupt Status Field (CRC_ERROR) */
5096  const uint32_t ccd : 1; /* Raw Interrupt Status Field (CVP_CONF_DONE) */
5097  const uint32_t prr : 1; /* Raw Interrupt Status Field (PR_READY) */
5098  const uint32_t pre : 1; /* Raw Interrupt Status Field (PR_ERROR) */
5099  const uint32_t prd : 1; /* Raw Interrupt Status Field (PR_DONE) */
5100  const uint32_t ncp : 1; /* Raw Interrupt Status Field (nCONFIG Pin) */
5101  const uint32_t nsp : 1; /* Raw Interrupt Status Field (nSTATUS Pin) */
5102  const uint32_t cdp : 1; /* Raw Interrupt Status Field (CONF_DONE Pin) */
5103  const uint32_t fpo : 1; /* Raw Interrupt Status Field (FPGA_POWER_ON) */
5104  uint32_t : 20; /* *UNDEFINED* */
5105 };
5106 
5107 /* The typedef declaration for register ALT_MON_GPIO_RAW_INTSTAT. */
5108 typedef volatile struct ALT_MON_GPIO_RAW_INTSTAT_s ALT_MON_GPIO_RAW_INTSTAT_t;
5109 #endif /* __ASSEMBLY__ */
5110 
5111 /* The byte offset of the ALT_MON_GPIO_RAW_INTSTAT register from the beginning of the component. */
5112 #define ALT_MON_GPIO_RAW_INTSTAT_OFST 0x44
5113 /* The address of the ALT_MON_GPIO_RAW_INTSTAT register. */
5114 #define ALT_MON_GPIO_RAW_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_RAW_INTSTAT_OFST))
5115 
5116 /*
5117  * Register : Clear Interrupt Register - gpio_porta_eoi
5118  *
5119  * This register is written by software to clear edge interrupts generated by each
5120  * individual GPIO input. This register always reads back as zero.
5121  *
5122  * Register Layout
5123  *
5124  * Bits | Access | Reset | Description
5125  * :--------|:-------|:------|:-------------------------------------------
5126  * [0] | W | 0x0 | Clear Edge Interrupt Field (nSTATUS)
5127  * [1] | W | 0x0 | Clear Edge Interrupt Field (CONF_DONE)
5128  * [2] | W | 0x0 | Clear Edge Interrupt Field (INIT_DONE)
5129  * [3] | W | 0x0 | Clear Edge Interrupt Field (CRC_ERROR)
5130  * [4] | W | 0x0 | Clear Edge Interrupt Field (CVP_CONF_DONE)
5131  * [5] | W | 0x0 | Clear Edge Interrupt Field (PR_READY)
5132  * [6] | W | 0x0 | Clear Edge Interrupt Field (PR_ERROR)
5133  * [7] | W | 0x0 | Clear Edge Interrupt Field (PR_DONE)
5134  * [8] | W | 0x0 | Clear Edge Interrupt Field (nCONFIG Pin)
5135  * [9] | W | 0x0 | Clear Edge Interrupt Field (nSTATUS Pin)
5136  * [10] | W | 0x0 | Clear Edge Interrupt Field (CONF_DONE Pin)
5137  * [11] | W | 0x0 | Clear Edge Interrupt Field (FPGA_POWER_ON)
5138  * [31:12] | ??? | 0x0 | *UNDEFINED*
5139  *
5140  */
5141 /*
5142  * Field : Clear Edge Interrupt Field (nSTATUS) - ns
5143  *
5144  * Used by software to clear an nSTATUS edge interrupt.
5145  *
5146  * Field Enumeration Values:
5147  *
5148  * Enum | Value | Description
5149  * :----------------------------------|:------|:-------------------
5150  * ALT_MON_GPIO_PORTA_EOI_NS_E_NOCLR | 0x0 | No interrupt clear
5151  * ALT_MON_GPIO_PORTA_EOI_NS_E_CLR | 0x1 | Clear interrupt
5152  *
5153  * Field Access Macros:
5154  *
5155  */
5156 /*
5157  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_NS
5158  *
5159  * No interrupt clear
5160  */
5161 #define ALT_MON_GPIO_PORTA_EOI_NS_E_NOCLR 0x0
5162 /*
5163  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_NS
5164  *
5165  * Clear interrupt
5166  */
5167 #define ALT_MON_GPIO_PORTA_EOI_NS_E_CLR 0x1
5168 
5169 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_NS register field. */
5170 #define ALT_MON_GPIO_PORTA_EOI_NS_LSB 0
5171 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_NS register field. */
5172 #define ALT_MON_GPIO_PORTA_EOI_NS_MSB 0
5173 /* The width in bits of the ALT_MON_GPIO_PORTA_EOI_NS register field. */
5174 #define ALT_MON_GPIO_PORTA_EOI_NS_WIDTH 1
5175 /* The mask used to set the ALT_MON_GPIO_PORTA_EOI_NS register field value. */
5176 #define ALT_MON_GPIO_PORTA_EOI_NS_SET_MSK 0x00000001
5177 /* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_NS register field value. */
5178 #define ALT_MON_GPIO_PORTA_EOI_NS_CLR_MSK 0xfffffffe
5179 /* The reset value of the ALT_MON_GPIO_PORTA_EOI_NS register field. */
5180 #define ALT_MON_GPIO_PORTA_EOI_NS_RESET 0x0
5181 /* Extracts the ALT_MON_GPIO_PORTA_EOI_NS field value from a register. */
5182 #define ALT_MON_GPIO_PORTA_EOI_NS_GET(value) (((value) & 0x00000001) >> 0)
5183 /* Produces a ALT_MON_GPIO_PORTA_EOI_NS register field value suitable for setting the register. */
5184 #define ALT_MON_GPIO_PORTA_EOI_NS_SET(value) (((value) << 0) & 0x00000001)
5185 
5186 /*
5187  * Field : Clear Edge Interrupt Field (CONF_DONE) - cd
5188  *
5189  * Used by software to clear an CONF_DONE edge interrupt.
5190  *
5191  * Field Enumeration Values:
5192  *
5193  * Enum | Value | Description
5194  * :----------------------------------|:------|:-------------------
5195  * ALT_MON_GPIO_PORTA_EOI_CD_E_NOCLR | 0x0 | No interrupt clear
5196  * ALT_MON_GPIO_PORTA_EOI_CD_E_CLR | 0x1 | Clear interrupt
5197  *
5198  * Field Access Macros:
5199  *
5200  */
5201 /*
5202  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CD
5203  *
5204  * No interrupt clear
5205  */
5206 #define ALT_MON_GPIO_PORTA_EOI_CD_E_NOCLR 0x0
5207 /*
5208  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CD
5209  *
5210  * Clear interrupt
5211  */
5212 #define ALT_MON_GPIO_PORTA_EOI_CD_E_CLR 0x1
5213 
5214 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_CD register field. */
5215 #define ALT_MON_GPIO_PORTA_EOI_CD_LSB 1
5216 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_CD register field. */
5217 #define ALT_MON_GPIO_PORTA_EOI_CD_MSB 1
5218 /* The width in bits of the ALT_MON_GPIO_PORTA_EOI_CD register field. */
5219 #define ALT_MON_GPIO_PORTA_EOI_CD_WIDTH 1
5220 /* The mask used to set the ALT_MON_GPIO_PORTA_EOI_CD register field value. */
5221 #define ALT_MON_GPIO_PORTA_EOI_CD_SET_MSK 0x00000002
5222 /* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_CD register field value. */
5223 #define ALT_MON_GPIO_PORTA_EOI_CD_CLR_MSK 0xfffffffd
5224 /* The reset value of the ALT_MON_GPIO_PORTA_EOI_CD register field. */
5225 #define ALT_MON_GPIO_PORTA_EOI_CD_RESET 0x0
5226 /* Extracts the ALT_MON_GPIO_PORTA_EOI_CD field value from a register. */
5227 #define ALT_MON_GPIO_PORTA_EOI_CD_GET(value) (((value) & 0x00000002) >> 1)
5228 /* Produces a ALT_MON_GPIO_PORTA_EOI_CD register field value suitable for setting the register. */
5229 #define ALT_MON_GPIO_PORTA_EOI_CD_SET(value) (((value) << 1) & 0x00000002)
5230 
5231 /*
5232  * Field : Clear Edge Interrupt Field (INIT_DONE) - id
5233  *
5234  * Used by software to clear an INIT_DONE edge interrupt.
5235  *
5236  * Field Enumeration Values:
5237  *
5238  * Enum | Value | Description
5239  * :----------------------------------|:------|:-------------------
5240  * ALT_MON_GPIO_PORTA_EOI_ID_E_NOCLR | 0x0 | No interrupt clear
5241  * ALT_MON_GPIO_PORTA_EOI_ID_E_CLR | 0x1 | Clear interrupt
5242  *
5243  * Field Access Macros:
5244  *
5245  */
5246 /*
5247  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_ID
5248  *
5249  * No interrupt clear
5250  */
5251 #define ALT_MON_GPIO_PORTA_EOI_ID_E_NOCLR 0x0
5252 /*
5253  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_ID
5254  *
5255  * Clear interrupt
5256  */
5257 #define ALT_MON_GPIO_PORTA_EOI_ID_E_CLR 0x1
5258 
5259 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_ID register field. */
5260 #define ALT_MON_GPIO_PORTA_EOI_ID_LSB 2
5261 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_ID register field. */
5262 #define ALT_MON_GPIO_PORTA_EOI_ID_MSB 2
5263 /* The width in bits of the ALT_MON_GPIO_PORTA_EOI_ID register field. */
5264 #define ALT_MON_GPIO_PORTA_EOI_ID_WIDTH 1
5265 /* The mask used to set the ALT_MON_GPIO_PORTA_EOI_ID register field value. */
5266 #define ALT_MON_GPIO_PORTA_EOI_ID_SET_MSK 0x00000004
5267 /* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_ID register field value. */
5268 #define ALT_MON_GPIO_PORTA_EOI_ID_CLR_MSK 0xfffffffb
5269 /* The reset value of the ALT_MON_GPIO_PORTA_EOI_ID register field. */
5270 #define ALT_MON_GPIO_PORTA_EOI_ID_RESET 0x0
5271 /* Extracts the ALT_MON_GPIO_PORTA_EOI_ID field value from a register. */
5272 #define ALT_MON_GPIO_PORTA_EOI_ID_GET(value) (((value) & 0x00000004) >> 2)
5273 /* Produces a ALT_MON_GPIO_PORTA_EOI_ID register field value suitable for setting the register. */
5274 #define ALT_MON_GPIO_PORTA_EOI_ID_SET(value) (((value) << 2) & 0x00000004)
5275 
5276 /*
5277  * Field : Clear Edge Interrupt Field (CRC_ERROR) - crc
5278  *
5279  * Used by software to clear an CRC_ERROR edge interrupt.
5280  *
5281  * Field Enumeration Values:
5282  *
5283  * Enum | Value | Description
5284  * :-----------------------------------|:------|:-------------------
5285  * ALT_MON_GPIO_PORTA_EOI_CRC_E_NOCLR | 0x0 | No interrupt clear
5286  * ALT_MON_GPIO_PORTA_EOI_CRC_E_CLR | 0x1 | Clear interrupt
5287  *
5288  * Field Access Macros:
5289  *
5290  */
5291 /*
5292  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CRC
5293  *
5294  * No interrupt clear
5295  */
5296 #define ALT_MON_GPIO_PORTA_EOI_CRC_E_NOCLR 0x0
5297 /*
5298  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CRC
5299  *
5300  * Clear interrupt
5301  */
5302 #define ALT_MON_GPIO_PORTA_EOI_CRC_E_CLR 0x1
5303 
5304 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_CRC register field. */
5305 #define ALT_MON_GPIO_PORTA_EOI_CRC_LSB 3
5306 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_CRC register field. */
5307 #define ALT_MON_GPIO_PORTA_EOI_CRC_MSB 3
5308 /* The width in bits of the ALT_MON_GPIO_PORTA_EOI_CRC register field. */
5309 #define ALT_MON_GPIO_PORTA_EOI_CRC_WIDTH 1
5310 /* The mask used to set the ALT_MON_GPIO_PORTA_EOI_CRC register field value. */
5311 #define ALT_MON_GPIO_PORTA_EOI_CRC_SET_MSK 0x00000008
5312 /* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_CRC register field value. */
5313 #define ALT_MON_GPIO_PORTA_EOI_CRC_CLR_MSK 0xfffffff7
5314 /* The reset value of the ALT_MON_GPIO_PORTA_EOI_CRC register field. */
5315 #define ALT_MON_GPIO_PORTA_EOI_CRC_RESET 0x0
5316 /* Extracts the ALT_MON_GPIO_PORTA_EOI_CRC field value from a register. */
5317 #define ALT_MON_GPIO_PORTA_EOI_CRC_GET(value) (((value) & 0x00000008) >> 3)
5318 /* Produces a ALT_MON_GPIO_PORTA_EOI_CRC register field value suitable for setting the register. */
5319 #define ALT_MON_GPIO_PORTA_EOI_CRC_SET(value) (((value) << 3) & 0x00000008)
5320 
5321 /*
5322  * Field : Clear Edge Interrupt Field (CVP_CONF_DONE) - ccd
5323  *
5324  * Used by software to clear an CVP_CONF_DONE edge interrupt.
5325  *
5326  * Field Enumeration Values:
5327  *
5328  * Enum | Value | Description
5329  * :-----------------------------------|:------|:-------------------
5330  * ALT_MON_GPIO_PORTA_EOI_CCD_E_NOCLR | 0x0 | No interrupt clear
5331  * ALT_MON_GPIO_PORTA_EOI_CCD_E_CLR | 0x1 | Clear interrupt
5332  *
5333  * Field Access Macros:
5334  *
5335  */
5336 /*
5337  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CCD
5338  *
5339  * No interrupt clear
5340  */
5341 #define ALT_MON_GPIO_PORTA_EOI_CCD_E_NOCLR 0x0
5342 /*
5343  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CCD
5344  *
5345  * Clear interrupt
5346  */
5347 #define ALT_MON_GPIO_PORTA_EOI_CCD_E_CLR 0x1
5348 
5349 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_CCD register field. */
5350 #define ALT_MON_GPIO_PORTA_EOI_CCD_LSB 4
5351 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_CCD register field. */
5352 #define ALT_MON_GPIO_PORTA_EOI_CCD_MSB 4
5353 /* The width in bits of the ALT_MON_GPIO_PORTA_EOI_CCD register field. */
5354 #define ALT_MON_GPIO_PORTA_EOI_CCD_WIDTH 1
5355 /* The mask used to set the ALT_MON_GPIO_PORTA_EOI_CCD register field value. */
5356 #define ALT_MON_GPIO_PORTA_EOI_CCD_SET_MSK 0x00000010
5357 /* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_CCD register field value. */
5358 #define ALT_MON_GPIO_PORTA_EOI_CCD_CLR_MSK 0xffffffef
5359 /* The reset value of the ALT_MON_GPIO_PORTA_EOI_CCD register field. */
5360 #define ALT_MON_GPIO_PORTA_EOI_CCD_RESET 0x0
5361 /* Extracts the ALT_MON_GPIO_PORTA_EOI_CCD field value from a register. */
5362 #define ALT_MON_GPIO_PORTA_EOI_CCD_GET(value) (((value) & 0x00000010) >> 4)
5363 /* Produces a ALT_MON_GPIO_PORTA_EOI_CCD register field value suitable for setting the register. */
5364 #define ALT_MON_GPIO_PORTA_EOI_CCD_SET(value) (((value) << 4) & 0x00000010)
5365 
5366 /*
5367  * Field : Clear Edge Interrupt Field (PR_READY) - prr
5368  *
5369  * Used by software to clear an PR_READY edge interrupt.
5370  *
5371  * Field Enumeration Values:
5372  *
5373  * Enum | Value | Description
5374  * :-----------------------------------|:------|:-------------------
5375  * ALT_MON_GPIO_PORTA_EOI_PRR_E_NOCLR | 0x0 | No interrupt clear
5376  * ALT_MON_GPIO_PORTA_EOI_PRR_E_CLR | 0x1 | Clear interrupt
5377  *
5378  * Field Access Macros:
5379  *
5380  */
5381 /*
5382  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_PRR
5383  *
5384  * No interrupt clear
5385  */
5386 #define ALT_MON_GPIO_PORTA_EOI_PRR_E_NOCLR 0x0
5387 /*
5388  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_PRR
5389  *
5390  * Clear interrupt
5391  */
5392 #define ALT_MON_GPIO_PORTA_EOI_PRR_E_CLR 0x1
5393 
5394 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_PRR register field. */
5395 #define ALT_MON_GPIO_PORTA_EOI_PRR_LSB 5
5396 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_PRR register field. */
5397 #define ALT_MON_GPIO_PORTA_EOI_PRR_MSB 5
5398 /* The width in bits of the ALT_MON_GPIO_PORTA_EOI_PRR register field. */
5399 #define ALT_MON_GPIO_PORTA_EOI_PRR_WIDTH 1
5400 /* The mask used to set the ALT_MON_GPIO_PORTA_EOI_PRR register field value. */
5401 #define ALT_MON_GPIO_PORTA_EOI_PRR_SET_MSK 0x00000020
5402 /* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_PRR register field value. */
5403 #define ALT_MON_GPIO_PORTA_EOI_PRR_CLR_MSK 0xffffffdf
5404 /* The reset value of the ALT_MON_GPIO_PORTA_EOI_PRR register field. */
5405 #define ALT_MON_GPIO_PORTA_EOI_PRR_RESET 0x0
5406 /* Extracts the ALT_MON_GPIO_PORTA_EOI_PRR field value from a register. */
5407 #define ALT_MON_GPIO_PORTA_EOI_PRR_GET(value) (((value) & 0x00000020) >> 5)
5408 /* Produces a ALT_MON_GPIO_PORTA_EOI_PRR register field value suitable for setting the register. */
5409 #define ALT_MON_GPIO_PORTA_EOI_PRR_SET(value) (((value) << 5) & 0x00000020)
5410 
5411 /*
5412  * Field : Clear Edge Interrupt Field (PR_ERROR) - pre
5413  *
5414  * Used by software to clear an PR_ERROR edge interrupt.
5415  *
5416  * Field Enumeration Values:
5417  *
5418  * Enum | Value | Description
5419  * :-----------------------------------|:------|:-------------------
5420  * ALT_MON_GPIO_PORTA_EOI_PRE_E_NOCLR | 0x0 | No interrupt clear
5421  * ALT_MON_GPIO_PORTA_EOI_PRE_E_CLR | 0x1 | Clear interrupt
5422  *
5423  * Field Access Macros:
5424  *
5425  */
5426 /*
5427  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_PRE
5428  *
5429  * No interrupt clear
5430  */
5431 #define ALT_MON_GPIO_PORTA_EOI_PRE_E_NOCLR 0x0
5432 /*
5433  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_PRE
5434  *
5435  * Clear interrupt
5436  */
5437 #define ALT_MON_GPIO_PORTA_EOI_PRE_E_CLR 0x1
5438 
5439 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_PRE register field. */
5440 #define ALT_MON_GPIO_PORTA_EOI_PRE_LSB 6
5441 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_PRE register field. */
5442 #define ALT_MON_GPIO_PORTA_EOI_PRE_MSB 6
5443 /* The width in bits of the ALT_MON_GPIO_PORTA_EOI_PRE register field. */
5444 #define ALT_MON_GPIO_PORTA_EOI_PRE_WIDTH 1
5445 /* The mask used to set the ALT_MON_GPIO_PORTA_EOI_PRE register field value. */
5446 #define ALT_MON_GPIO_PORTA_EOI_PRE_SET_MSK 0x00000040
5447 /* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_PRE register field value. */
5448 #define ALT_MON_GPIO_PORTA_EOI_PRE_CLR_MSK 0xffffffbf
5449 /* The reset value of the ALT_MON_GPIO_PORTA_EOI_PRE register field. */
5450 #define ALT_MON_GPIO_PORTA_EOI_PRE_RESET 0x0
5451 /* Extracts the ALT_MON_GPIO_PORTA_EOI_PRE field value from a register. */
5452 #define ALT_MON_GPIO_PORTA_EOI_PRE_GET(value) (((value) & 0x00000040) >> 6)
5453 /* Produces a ALT_MON_GPIO_PORTA_EOI_PRE register field value suitable for setting the register. */
5454 #define ALT_MON_GPIO_PORTA_EOI_PRE_SET(value) (((value) << 6) & 0x00000040)
5455 
5456 /*
5457  * Field : Clear Edge Interrupt Field (PR_DONE) - prd
5458  *
5459  * Used by software to clear an PR_DONE edge interrupt.
5460  *
5461  * Field Enumeration Values:
5462  *
5463  * Enum | Value | Description
5464  * :-----------------------------------|:------|:-------------------
5465  * ALT_MON_GPIO_PORTA_EOI_PRD_E_NOCLR | 0x0 | No interrupt clear
5466  * ALT_MON_GPIO_PORTA_EOI_PRD_E_CLR | 0x1 | Clear interrupt
5467  *
5468  * Field Access Macros:
5469  *
5470  */
5471 /*
5472  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_PRD
5473  *
5474  * No interrupt clear
5475  */
5476 #define ALT_MON_GPIO_PORTA_EOI_PRD_E_NOCLR 0x0
5477 /*
5478  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_PRD
5479  *
5480  * Clear interrupt
5481  */
5482 #define ALT_MON_GPIO_PORTA_EOI_PRD_E_CLR 0x1
5483 
5484 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_PRD register field. */
5485 #define ALT_MON_GPIO_PORTA_EOI_PRD_LSB 7
5486 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_PRD register field. */
5487 #define ALT_MON_GPIO_PORTA_EOI_PRD_MSB 7
5488 /* The width in bits of the ALT_MON_GPIO_PORTA_EOI_PRD register field. */
5489 #define ALT_MON_GPIO_PORTA_EOI_PRD_WIDTH 1
5490 /* The mask used to set the ALT_MON_GPIO_PORTA_EOI_PRD register field value. */
5491 #define ALT_MON_GPIO_PORTA_EOI_PRD_SET_MSK 0x00000080
5492 /* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_PRD register field value. */
5493 #define ALT_MON_GPIO_PORTA_EOI_PRD_CLR_MSK 0xffffff7f
5494 /* The reset value of the ALT_MON_GPIO_PORTA_EOI_PRD register field. */
5495 #define ALT_MON_GPIO_PORTA_EOI_PRD_RESET 0x0
5496 /* Extracts the ALT_MON_GPIO_PORTA_EOI_PRD field value from a register. */
5497 #define ALT_MON_GPIO_PORTA_EOI_PRD_GET(value) (((value) & 0x00000080) >> 7)
5498 /* Produces a ALT_MON_GPIO_PORTA_EOI_PRD register field value suitable for setting the register. */
5499 #define ALT_MON_GPIO_PORTA_EOI_PRD_SET(value) (((value) << 7) & 0x00000080)
5500 
5501 /*
5502  * Field : Clear Edge Interrupt Field (nCONFIG Pin) - ncp
5503  *
5504  * Used by software to clear an nCONFIG Pin edge interrupt.
5505  *
5506  * Field Enumeration Values:
5507  *
5508  * Enum | Value | Description
5509  * :-----------------------------------|:------|:-------------------
5510  * ALT_MON_GPIO_PORTA_EOI_NCP_E_NOCLR | 0x0 | No interrupt clear
5511  * ALT_MON_GPIO_PORTA_EOI_NCP_E_CLR | 0x1 | Clear interrupt
5512  *
5513  * Field Access Macros:
5514  *
5515  */
5516 /*
5517  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_NCP
5518  *
5519  * No interrupt clear
5520  */
5521 #define ALT_MON_GPIO_PORTA_EOI_NCP_E_NOCLR 0x0
5522 /*
5523  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_NCP
5524  *
5525  * Clear interrupt
5526  */
5527 #define ALT_MON_GPIO_PORTA_EOI_NCP_E_CLR 0x1
5528 
5529 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_NCP register field. */
5530 #define ALT_MON_GPIO_PORTA_EOI_NCP_LSB 8
5531 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_NCP register field. */
5532 #define ALT_MON_GPIO_PORTA_EOI_NCP_MSB 8
5533 /* The width in bits of the ALT_MON_GPIO_PORTA_EOI_NCP register field. */
5534 #define ALT_MON_GPIO_PORTA_EOI_NCP_WIDTH 1
5535 /* The mask used to set the ALT_MON_GPIO_PORTA_EOI_NCP register field value. */
5536 #define ALT_MON_GPIO_PORTA_EOI_NCP_SET_MSK 0x00000100
5537 /* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_NCP register field value. */
5538 #define ALT_MON_GPIO_PORTA_EOI_NCP_CLR_MSK 0xfffffeff
5539 /* The reset value of the ALT_MON_GPIO_PORTA_EOI_NCP register field. */
5540 #define ALT_MON_GPIO_PORTA_EOI_NCP_RESET 0x0
5541 /* Extracts the ALT_MON_GPIO_PORTA_EOI_NCP field value from a register. */
5542 #define ALT_MON_GPIO_PORTA_EOI_NCP_GET(value) (((value) & 0x00000100) >> 8)
5543 /* Produces a ALT_MON_GPIO_PORTA_EOI_NCP register field value suitable for setting the register. */
5544 #define ALT_MON_GPIO_PORTA_EOI_NCP_SET(value) (((value) << 8) & 0x00000100)
5545 
5546 /*
5547  * Field : Clear Edge Interrupt Field (nSTATUS Pin) - nsp
5548  *
5549  * Used by software to clear an nSTATUS Pin edge interrupt.
5550  *
5551  * Field Enumeration Values:
5552  *
5553  * Enum | Value | Description
5554  * :-----------------------------------|:------|:-------------------
5555  * ALT_MON_GPIO_PORTA_EOI_NSP_E_NOCLR | 0x0 | No interrupt clear
5556  * ALT_MON_GPIO_PORTA_EOI_NSP_E_CLR | 0x1 | Clear interrupt
5557  *
5558  * Field Access Macros:
5559  *
5560  */
5561 /*
5562  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_NSP
5563  *
5564  * No interrupt clear
5565  */
5566 #define ALT_MON_GPIO_PORTA_EOI_NSP_E_NOCLR 0x0
5567 /*
5568  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_NSP
5569  *
5570  * Clear interrupt
5571  */
5572 #define ALT_MON_GPIO_PORTA_EOI_NSP_E_CLR 0x1
5573 
5574 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_NSP register field. */
5575 #define ALT_MON_GPIO_PORTA_EOI_NSP_LSB 9
5576 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_NSP register field. */
5577 #define ALT_MON_GPIO_PORTA_EOI_NSP_MSB 9
5578 /* The width in bits of the ALT_MON_GPIO_PORTA_EOI_NSP register field. */
5579 #define ALT_MON_GPIO_PORTA_EOI_NSP_WIDTH 1
5580 /* The mask used to set the ALT_MON_GPIO_PORTA_EOI_NSP register field value. */
5581 #define ALT_MON_GPIO_PORTA_EOI_NSP_SET_MSK 0x00000200
5582 /* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_NSP register field value. */
5583 #define ALT_MON_GPIO_PORTA_EOI_NSP_CLR_MSK 0xfffffdff
5584 /* The reset value of the ALT_MON_GPIO_PORTA_EOI_NSP register field. */
5585 #define ALT_MON_GPIO_PORTA_EOI_NSP_RESET 0x0
5586 /* Extracts the ALT_MON_GPIO_PORTA_EOI_NSP field value from a register. */
5587 #define ALT_MON_GPIO_PORTA_EOI_NSP_GET(value) (((value) & 0x00000200) >> 9)
5588 /* Produces a ALT_MON_GPIO_PORTA_EOI_NSP register field value suitable for setting the register. */
5589 #define ALT_MON_GPIO_PORTA_EOI_NSP_SET(value) (((value) << 9) & 0x00000200)
5590 
5591 /*
5592  * Field : Clear Edge Interrupt Field (CONF_DONE Pin) - cdp
5593  *
5594  * Used by software to clear an CONF_DONE Pin edge interrupt.
5595  *
5596  * Field Enumeration Values:
5597  *
5598  * Enum | Value | Description
5599  * :-----------------------------------|:------|:-------------------
5600  * ALT_MON_GPIO_PORTA_EOI_CDP_E_NOCLR | 0x0 | No interrupt clear
5601  * ALT_MON_GPIO_PORTA_EOI_CDP_E_CLR | 0x1 | Clear interrupt
5602  *
5603  * Field Access Macros:
5604  *
5605  */
5606 /*
5607  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CDP
5608  *
5609  * No interrupt clear
5610  */
5611 #define ALT_MON_GPIO_PORTA_EOI_CDP_E_NOCLR 0x0
5612 /*
5613  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_CDP
5614  *
5615  * Clear interrupt
5616  */
5617 #define ALT_MON_GPIO_PORTA_EOI_CDP_E_CLR 0x1
5618 
5619 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_CDP register field. */
5620 #define ALT_MON_GPIO_PORTA_EOI_CDP_LSB 10
5621 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_CDP register field. */
5622 #define ALT_MON_GPIO_PORTA_EOI_CDP_MSB 10
5623 /* The width in bits of the ALT_MON_GPIO_PORTA_EOI_CDP register field. */
5624 #define ALT_MON_GPIO_PORTA_EOI_CDP_WIDTH 1
5625 /* The mask used to set the ALT_MON_GPIO_PORTA_EOI_CDP register field value. */
5626 #define ALT_MON_GPIO_PORTA_EOI_CDP_SET_MSK 0x00000400
5627 /* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_CDP register field value. */
5628 #define ALT_MON_GPIO_PORTA_EOI_CDP_CLR_MSK 0xfffffbff
5629 /* The reset value of the ALT_MON_GPIO_PORTA_EOI_CDP register field. */
5630 #define ALT_MON_GPIO_PORTA_EOI_CDP_RESET 0x0
5631 /* Extracts the ALT_MON_GPIO_PORTA_EOI_CDP field value from a register. */
5632 #define ALT_MON_GPIO_PORTA_EOI_CDP_GET(value) (((value) & 0x00000400) >> 10)
5633 /* Produces a ALT_MON_GPIO_PORTA_EOI_CDP register field value suitable for setting the register. */
5634 #define ALT_MON_GPIO_PORTA_EOI_CDP_SET(value) (((value) << 10) & 0x00000400)
5635 
5636 /*
5637  * Field : Clear Edge Interrupt Field (FPGA_POWER_ON) - fpo
5638  *
5639  * Used by software to clear an FPGA_POWER_ON edge interrupt.
5640  *
5641  * Field Enumeration Values:
5642  *
5643  * Enum | Value | Description
5644  * :-----------------------------------|:------|:-------------------
5645  * ALT_MON_GPIO_PORTA_EOI_FPO_E_NOCLR | 0x0 | No interrupt clear
5646  * ALT_MON_GPIO_PORTA_EOI_FPO_E_CLR | 0x1 | Clear interrupt
5647  *
5648  * Field Access Macros:
5649  *
5650  */
5651 /*
5652  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_FPO
5653  *
5654  * No interrupt clear
5655  */
5656 #define ALT_MON_GPIO_PORTA_EOI_FPO_E_NOCLR 0x0
5657 /*
5658  * Enumerated value for register field ALT_MON_GPIO_PORTA_EOI_FPO
5659  *
5660  * Clear interrupt
5661  */
5662 #define ALT_MON_GPIO_PORTA_EOI_FPO_E_CLR 0x1
5663 
5664 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_PORTA_EOI_FPO register field. */
5665 #define ALT_MON_GPIO_PORTA_EOI_FPO_LSB 11
5666 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_PORTA_EOI_FPO register field. */
5667 #define ALT_MON_GPIO_PORTA_EOI_FPO_MSB 11
5668 /* The width in bits of the ALT_MON_GPIO_PORTA_EOI_FPO register field. */
5669 #define ALT_MON_GPIO_PORTA_EOI_FPO_WIDTH 1
5670 /* The mask used to set the ALT_MON_GPIO_PORTA_EOI_FPO register field value. */
5671 #define ALT_MON_GPIO_PORTA_EOI_FPO_SET_MSK 0x00000800
5672 /* The mask used to clear the ALT_MON_GPIO_PORTA_EOI_FPO register field value. */
5673 #define ALT_MON_GPIO_PORTA_EOI_FPO_CLR_MSK 0xfffff7ff
5674 /* The reset value of the ALT_MON_GPIO_PORTA_EOI_FPO register field. */
5675 #define ALT_MON_GPIO_PORTA_EOI_FPO_RESET 0x0
5676 /* Extracts the ALT_MON_GPIO_PORTA_EOI_FPO field value from a register. */
5677 #define ALT_MON_GPIO_PORTA_EOI_FPO_GET(value) (((value) & 0x00000800) >> 11)
5678 /* Produces a ALT_MON_GPIO_PORTA_EOI_FPO register field value suitable for setting the register. */
5679 #define ALT_MON_GPIO_PORTA_EOI_FPO_SET(value) (((value) << 11) & 0x00000800)
5680 
5681 #ifndef __ASSEMBLY__
5682 /*
5683  * WARNING: The C register and register group struct declarations are provided for
5684  * convenience and illustrative purposes. They should, however, be used with
5685  * caution as the C language standard provides no guarantees about the alignment or
5686  * atomicity of device memory accesses. The recommended practice for writing
5687  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5688  * alt_write_word() functions.
5689  *
5690  * The struct declaration for register ALT_MON_GPIO_PORTA_EOI.
5691  */
5692 struct ALT_MON_GPIO_PORTA_EOI_s
5693 {
5694  uint32_t ns : 1; /* Clear Edge Interrupt Field (nSTATUS) */
5695  uint32_t cd : 1; /* Clear Edge Interrupt Field (CONF_DONE) */
5696  uint32_t id : 1; /* Clear Edge Interrupt Field (INIT_DONE) */
5697  uint32_t crc : 1; /* Clear Edge Interrupt Field (CRC_ERROR) */
5698  uint32_t ccd : 1; /* Clear Edge Interrupt Field (CVP_CONF_DONE) */
5699  uint32_t prr : 1; /* Clear Edge Interrupt Field (PR_READY) */
5700  uint32_t pre : 1; /* Clear Edge Interrupt Field (PR_ERROR) */
5701  uint32_t prd : 1; /* Clear Edge Interrupt Field (PR_DONE) */
5702  uint32_t ncp : 1; /* Clear Edge Interrupt Field (nCONFIG Pin) */
5703  uint32_t nsp : 1; /* Clear Edge Interrupt Field (nSTATUS Pin) */
5704  uint32_t cdp : 1; /* Clear Edge Interrupt Field (CONF_DONE Pin) */
5705  uint32_t fpo : 1; /* Clear Edge Interrupt Field (FPGA_POWER_ON) */
5706  uint32_t : 20; /* *UNDEFINED* */
5707 };
5708 
5709 /* The typedef declaration for register ALT_MON_GPIO_PORTA_EOI. */
5710 typedef volatile struct ALT_MON_GPIO_PORTA_EOI_s ALT_MON_GPIO_PORTA_EOI_t;
5711 #endif /* __ASSEMBLY__ */
5712 
5713 /* The byte offset of the ALT_MON_GPIO_PORTA_EOI register from the beginning of the component. */
5714 #define ALT_MON_GPIO_PORTA_EOI_OFST 0x4c
5715 /* The address of the ALT_MON_GPIO_PORTA_EOI register. */
5716 #define ALT_MON_GPIO_PORTA_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_PORTA_EOI_OFST))
5717 
5718 /*
5719  * Register : External Port A Register - gpio_ext_porta
5720  *
5721  * Reading this register reads the values of the GPIO inputs.
5722  *
5723  * Register Layout
5724  *
5725  * Bits | Access | Reset | Description
5726  * :--------|:-------|:------|:------------------------------------
5727  * [0] | R | 0x0 | External Port Field (nSTATUS)
5728  * [1] | R | 0x0 | External Port Field (CONF_DONE)
5729  * [2] | R | 0x0 | External Port Field (INIT_DONE)
5730  * [3] | R | 0x0 | External Port Field (CRC_ERROR)
5731  * [4] | R | 0x0 | External Port Field (CVP_CONF_DONE)
5732  * [5] | R | 0x0 | External Port Field (PR_READY)
5733  * [6] | R | 0x0 | External Port Field (PR_ERROR)
5734  * [7] | R | 0x0 | External Port Field (PR_DONE)
5735  * [8] | R | 0x0 | External Port Field (nCONFIG Pin)
5736  * [9] | R | 0x0 | External Port Field (nSTATUS Pin)
5737  * [10] | R | 0x0 | External Port Field (CONF_DONE Pin)
5738  * [11] | R | 0x0 | External Port Field (FPGA_POWER_ON)
5739  * [31:12] | ??? | 0x0 | *UNDEFINED*
5740  *
5741  */
5742 /*
5743  * Field : External Port Field (nSTATUS) - ns
5744  *
5745  * Reading this provides the value of nSTATUS
5746  *
5747  * Field Access Macros:
5748  *
5749  */
5750 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_NS register field. */
5751 #define ALT_MON_GPIO_EXT_PORTA_NS_LSB 0
5752 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_NS register field. */
5753 #define ALT_MON_GPIO_EXT_PORTA_NS_MSB 0
5754 /* The width in bits of the ALT_MON_GPIO_EXT_PORTA_NS register field. */
5755 #define ALT_MON_GPIO_EXT_PORTA_NS_WIDTH 1
5756 /* The mask used to set the ALT_MON_GPIO_EXT_PORTA_NS register field value. */
5757 #define ALT_MON_GPIO_EXT_PORTA_NS_SET_MSK 0x00000001
5758 /* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_NS register field value. */
5759 #define ALT_MON_GPIO_EXT_PORTA_NS_CLR_MSK 0xfffffffe
5760 /* The reset value of the ALT_MON_GPIO_EXT_PORTA_NS register field. */
5761 #define ALT_MON_GPIO_EXT_PORTA_NS_RESET 0x0
5762 /* Extracts the ALT_MON_GPIO_EXT_PORTA_NS field value from a register. */
5763 #define ALT_MON_GPIO_EXT_PORTA_NS_GET(value) (((value) & 0x00000001) >> 0)
5764 /* Produces a ALT_MON_GPIO_EXT_PORTA_NS register field value suitable for setting the register. */
5765 #define ALT_MON_GPIO_EXT_PORTA_NS_SET(value) (((value) << 0) & 0x00000001)
5766 
5767 /*
5768  * Field : External Port Field (CONF_DONE) - cd
5769  *
5770  * Reading this provides the value of CONF_DONE
5771  *
5772  * Field Access Macros:
5773  *
5774  */
5775 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_CD register field. */
5776 #define ALT_MON_GPIO_EXT_PORTA_CD_LSB 1
5777 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_CD register field. */
5778 #define ALT_MON_GPIO_EXT_PORTA_CD_MSB 1
5779 /* The width in bits of the ALT_MON_GPIO_EXT_PORTA_CD register field. */
5780 #define ALT_MON_GPIO_EXT_PORTA_CD_WIDTH 1
5781 /* The mask used to set the ALT_MON_GPIO_EXT_PORTA_CD register field value. */
5782 #define ALT_MON_GPIO_EXT_PORTA_CD_SET_MSK 0x00000002
5783 /* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_CD register field value. */
5784 #define ALT_MON_GPIO_EXT_PORTA_CD_CLR_MSK 0xfffffffd
5785 /* The reset value of the ALT_MON_GPIO_EXT_PORTA_CD register field. */
5786 #define ALT_MON_GPIO_EXT_PORTA_CD_RESET 0x0
5787 /* Extracts the ALT_MON_GPIO_EXT_PORTA_CD field value from a register. */
5788 #define ALT_MON_GPIO_EXT_PORTA_CD_GET(value) (((value) & 0x00000002) >> 1)
5789 /* Produces a ALT_MON_GPIO_EXT_PORTA_CD register field value suitable for setting the register. */
5790 #define ALT_MON_GPIO_EXT_PORTA_CD_SET(value) (((value) << 1) & 0x00000002)
5791 
5792 /*
5793  * Field : External Port Field (INIT_DONE) - id
5794  *
5795  * Reading this provides the value of INIT_DONE
5796  *
5797  * Field Access Macros:
5798  *
5799  */
5800 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_ID register field. */
5801 #define ALT_MON_GPIO_EXT_PORTA_ID_LSB 2
5802 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_ID register field. */
5803 #define ALT_MON_GPIO_EXT_PORTA_ID_MSB 2
5804 /* The width in bits of the ALT_MON_GPIO_EXT_PORTA_ID register field. */
5805 #define ALT_MON_GPIO_EXT_PORTA_ID_WIDTH 1
5806 /* The mask used to set the ALT_MON_GPIO_EXT_PORTA_ID register field value. */
5807 #define ALT_MON_GPIO_EXT_PORTA_ID_SET_MSK 0x00000004
5808 /* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_ID register field value. */
5809 #define ALT_MON_GPIO_EXT_PORTA_ID_CLR_MSK 0xfffffffb
5810 /* The reset value of the ALT_MON_GPIO_EXT_PORTA_ID register field. */
5811 #define ALT_MON_GPIO_EXT_PORTA_ID_RESET 0x0
5812 /* Extracts the ALT_MON_GPIO_EXT_PORTA_ID field value from a register. */
5813 #define ALT_MON_GPIO_EXT_PORTA_ID_GET(value) (((value) & 0x00000004) >> 2)
5814 /* Produces a ALT_MON_GPIO_EXT_PORTA_ID register field value suitable for setting the register. */
5815 #define ALT_MON_GPIO_EXT_PORTA_ID_SET(value) (((value) << 2) & 0x00000004)
5816 
5817 /*
5818  * Field : External Port Field (CRC_ERROR) - crc
5819  *
5820  * Reading this provides the value of CRC_ERROR
5821  *
5822  * Field Access Macros:
5823  *
5824  */
5825 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_CRC register field. */
5826 #define ALT_MON_GPIO_EXT_PORTA_CRC_LSB 3
5827 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_CRC register field. */
5828 #define ALT_MON_GPIO_EXT_PORTA_CRC_MSB 3
5829 /* The width in bits of the ALT_MON_GPIO_EXT_PORTA_CRC register field. */
5830 #define ALT_MON_GPIO_EXT_PORTA_CRC_WIDTH 1
5831 /* The mask used to set the ALT_MON_GPIO_EXT_PORTA_CRC register field value. */
5832 #define ALT_MON_GPIO_EXT_PORTA_CRC_SET_MSK 0x00000008
5833 /* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_CRC register field value. */
5834 #define ALT_MON_GPIO_EXT_PORTA_CRC_CLR_MSK 0xfffffff7
5835 /* The reset value of the ALT_MON_GPIO_EXT_PORTA_CRC register field. */
5836 #define ALT_MON_GPIO_EXT_PORTA_CRC_RESET 0x0
5837 /* Extracts the ALT_MON_GPIO_EXT_PORTA_CRC field value from a register. */
5838 #define ALT_MON_GPIO_EXT_PORTA_CRC_GET(value) (((value) & 0x00000008) >> 3)
5839 /* Produces a ALT_MON_GPIO_EXT_PORTA_CRC register field value suitable for setting the register. */
5840 #define ALT_MON_GPIO_EXT_PORTA_CRC_SET(value) (((value) << 3) & 0x00000008)
5841 
5842 /*
5843  * Field : External Port Field (CVP_CONF_DONE) - ccd
5844  *
5845  * Reading this provides the value of CVP_CONF_DONE
5846  *
5847  * Field Access Macros:
5848  *
5849  */
5850 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_CCD register field. */
5851 #define ALT_MON_GPIO_EXT_PORTA_CCD_LSB 4
5852 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_CCD register field. */
5853 #define ALT_MON_GPIO_EXT_PORTA_CCD_MSB 4
5854 /* The width in bits of the ALT_MON_GPIO_EXT_PORTA_CCD register field. */
5855 #define ALT_MON_GPIO_EXT_PORTA_CCD_WIDTH 1
5856 /* The mask used to set the ALT_MON_GPIO_EXT_PORTA_CCD register field value. */
5857 #define ALT_MON_GPIO_EXT_PORTA_CCD_SET_MSK 0x00000010
5858 /* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_CCD register field value. */
5859 #define ALT_MON_GPIO_EXT_PORTA_CCD_CLR_MSK 0xffffffef
5860 /* The reset value of the ALT_MON_GPIO_EXT_PORTA_CCD register field. */
5861 #define ALT_MON_GPIO_EXT_PORTA_CCD_RESET 0x0
5862 /* Extracts the ALT_MON_GPIO_EXT_PORTA_CCD field value from a register. */
5863 #define ALT_MON_GPIO_EXT_PORTA_CCD_GET(value) (((value) & 0x00000010) >> 4)
5864 /* Produces a ALT_MON_GPIO_EXT_PORTA_CCD register field value suitable for setting the register. */
5865 #define ALT_MON_GPIO_EXT_PORTA_CCD_SET(value) (((value) << 4) & 0x00000010)
5866 
5867 /*
5868  * Field : External Port Field (PR_READY) - prr
5869  *
5870  * Reading this provides the value of PR_READY
5871  *
5872  * Field Access Macros:
5873  *
5874  */
5875 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_PRR register field. */
5876 #define ALT_MON_GPIO_EXT_PORTA_PRR_LSB 5
5877 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_PRR register field. */
5878 #define ALT_MON_GPIO_EXT_PORTA_PRR_MSB 5
5879 /* The width in bits of the ALT_MON_GPIO_EXT_PORTA_PRR register field. */
5880 #define ALT_MON_GPIO_EXT_PORTA_PRR_WIDTH 1
5881 /* The mask used to set the ALT_MON_GPIO_EXT_PORTA_PRR register field value. */
5882 #define ALT_MON_GPIO_EXT_PORTA_PRR_SET_MSK 0x00000020
5883 /* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_PRR register field value. */
5884 #define ALT_MON_GPIO_EXT_PORTA_PRR_CLR_MSK 0xffffffdf
5885 /* The reset value of the ALT_MON_GPIO_EXT_PORTA_PRR register field. */
5886 #define ALT_MON_GPIO_EXT_PORTA_PRR_RESET 0x0
5887 /* Extracts the ALT_MON_GPIO_EXT_PORTA_PRR field value from a register. */
5888 #define ALT_MON_GPIO_EXT_PORTA_PRR_GET(value) (((value) & 0x00000020) >> 5)
5889 /* Produces a ALT_MON_GPIO_EXT_PORTA_PRR register field value suitable for setting the register. */
5890 #define ALT_MON_GPIO_EXT_PORTA_PRR_SET(value) (((value) << 5) & 0x00000020)
5891 
5892 /*
5893  * Field : External Port Field (PR_ERROR) - pre
5894  *
5895  * Reading this provides the value of PR_ERROR
5896  *
5897  * Field Access Macros:
5898  *
5899  */
5900 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_PRE register field. */
5901 #define ALT_MON_GPIO_EXT_PORTA_PRE_LSB 6
5902 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_PRE register field. */
5903 #define ALT_MON_GPIO_EXT_PORTA_PRE_MSB 6
5904 /* The width in bits of the ALT_MON_GPIO_EXT_PORTA_PRE register field. */
5905 #define ALT_MON_GPIO_EXT_PORTA_PRE_WIDTH 1
5906 /* The mask used to set the ALT_MON_GPIO_EXT_PORTA_PRE register field value. */
5907 #define ALT_MON_GPIO_EXT_PORTA_PRE_SET_MSK 0x00000040
5908 /* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_PRE register field value. */
5909 #define ALT_MON_GPIO_EXT_PORTA_PRE_CLR_MSK 0xffffffbf
5910 /* The reset value of the ALT_MON_GPIO_EXT_PORTA_PRE register field. */
5911 #define ALT_MON_GPIO_EXT_PORTA_PRE_RESET 0x0
5912 /* Extracts the ALT_MON_GPIO_EXT_PORTA_PRE field value from a register. */
5913 #define ALT_MON_GPIO_EXT_PORTA_PRE_GET(value) (((value) & 0x00000040) >> 6)
5914 /* Produces a ALT_MON_GPIO_EXT_PORTA_PRE register field value suitable for setting the register. */
5915 #define ALT_MON_GPIO_EXT_PORTA_PRE_SET(value) (((value) << 6) & 0x00000040)
5916 
5917 /*
5918  * Field : External Port Field (PR_DONE) - prd
5919  *
5920  * Reading this provides the value of PR_DONE
5921  *
5922  * Field Access Macros:
5923  *
5924  */
5925 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_PRD register field. */
5926 #define ALT_MON_GPIO_EXT_PORTA_PRD_LSB 7
5927 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_PRD register field. */
5928 #define ALT_MON_GPIO_EXT_PORTA_PRD_MSB 7
5929 /* The width in bits of the ALT_MON_GPIO_EXT_PORTA_PRD register field. */
5930 #define ALT_MON_GPIO_EXT_PORTA_PRD_WIDTH 1
5931 /* The mask used to set the ALT_MON_GPIO_EXT_PORTA_PRD register field value. */
5932 #define ALT_MON_GPIO_EXT_PORTA_PRD_SET_MSK 0x00000080
5933 /* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_PRD register field value. */
5934 #define ALT_MON_GPIO_EXT_PORTA_PRD_CLR_MSK 0xffffff7f
5935 /* The reset value of the ALT_MON_GPIO_EXT_PORTA_PRD register field. */
5936 #define ALT_MON_GPIO_EXT_PORTA_PRD_RESET 0x0
5937 /* Extracts the ALT_MON_GPIO_EXT_PORTA_PRD field value from a register. */
5938 #define ALT_MON_GPIO_EXT_PORTA_PRD_GET(value) (((value) & 0x00000080) >> 7)
5939 /* Produces a ALT_MON_GPIO_EXT_PORTA_PRD register field value suitable for setting the register. */
5940 #define ALT_MON_GPIO_EXT_PORTA_PRD_SET(value) (((value) << 7) & 0x00000080)
5941 
5942 /*
5943  * Field : External Port Field (nCONFIG Pin) - ncp
5944  *
5945  * Reading this provides the value of nCONFIG Pin
5946  *
5947  * Field Access Macros:
5948  *
5949  */
5950 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_NCP register field. */
5951 #define ALT_MON_GPIO_EXT_PORTA_NCP_LSB 8
5952 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_NCP register field. */
5953 #define ALT_MON_GPIO_EXT_PORTA_NCP_MSB 8
5954 /* The width in bits of the ALT_MON_GPIO_EXT_PORTA_NCP register field. */
5955 #define ALT_MON_GPIO_EXT_PORTA_NCP_WIDTH 1
5956 /* The mask used to set the ALT_MON_GPIO_EXT_PORTA_NCP register field value. */
5957 #define ALT_MON_GPIO_EXT_PORTA_NCP_SET_MSK 0x00000100
5958 /* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_NCP register field value. */
5959 #define ALT_MON_GPIO_EXT_PORTA_NCP_CLR_MSK 0xfffffeff
5960 /* The reset value of the ALT_MON_GPIO_EXT_PORTA_NCP register field. */
5961 #define ALT_MON_GPIO_EXT_PORTA_NCP_RESET 0x0
5962 /* Extracts the ALT_MON_GPIO_EXT_PORTA_NCP field value from a register. */
5963 #define ALT_MON_GPIO_EXT_PORTA_NCP_GET(value) (((value) & 0x00000100) >> 8)
5964 /* Produces a ALT_MON_GPIO_EXT_PORTA_NCP register field value suitable for setting the register. */
5965 #define ALT_MON_GPIO_EXT_PORTA_NCP_SET(value) (((value) << 8) & 0x00000100)
5966 
5967 /*
5968  * Field : External Port Field (nSTATUS Pin) - nsp
5969  *
5970  * Reading this provides the value of nSTATUS Pin
5971  *
5972  * Field Access Macros:
5973  *
5974  */
5975 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_NSP register field. */
5976 #define ALT_MON_GPIO_EXT_PORTA_NSP_LSB 9
5977 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_NSP register field. */
5978 #define ALT_MON_GPIO_EXT_PORTA_NSP_MSB 9
5979 /* The width in bits of the ALT_MON_GPIO_EXT_PORTA_NSP register field. */
5980 #define ALT_MON_GPIO_EXT_PORTA_NSP_WIDTH 1
5981 /* The mask used to set the ALT_MON_GPIO_EXT_PORTA_NSP register field value. */
5982 #define ALT_MON_GPIO_EXT_PORTA_NSP_SET_MSK 0x00000200
5983 /* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_NSP register field value. */
5984 #define ALT_MON_GPIO_EXT_PORTA_NSP_CLR_MSK 0xfffffdff
5985 /* The reset value of the ALT_MON_GPIO_EXT_PORTA_NSP register field. */
5986 #define ALT_MON_GPIO_EXT_PORTA_NSP_RESET 0x0
5987 /* Extracts the ALT_MON_GPIO_EXT_PORTA_NSP field value from a register. */
5988 #define ALT_MON_GPIO_EXT_PORTA_NSP_GET(value) (((value) & 0x00000200) >> 9)
5989 /* Produces a ALT_MON_GPIO_EXT_PORTA_NSP register field value suitable for setting the register. */
5990 #define ALT_MON_GPIO_EXT_PORTA_NSP_SET(value) (((value) << 9) & 0x00000200)
5991 
5992 /*
5993  * Field : External Port Field (CONF_DONE Pin) - cdp
5994  *
5995  * Reading this provides the value of CONF_DONE Pin
5996  *
5997  * Field Access Macros:
5998  *
5999  */
6000 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_CDP register field. */
6001 #define ALT_MON_GPIO_EXT_PORTA_CDP_LSB 10
6002 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_CDP register field. */
6003 #define ALT_MON_GPIO_EXT_PORTA_CDP_MSB 10
6004 /* The width in bits of the ALT_MON_GPIO_EXT_PORTA_CDP register field. */
6005 #define ALT_MON_GPIO_EXT_PORTA_CDP_WIDTH 1
6006 /* The mask used to set the ALT_MON_GPIO_EXT_PORTA_CDP register field value. */
6007 #define ALT_MON_GPIO_EXT_PORTA_CDP_SET_MSK 0x00000400
6008 /* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_CDP register field value. */
6009 #define ALT_MON_GPIO_EXT_PORTA_CDP_CLR_MSK 0xfffffbff
6010 /* The reset value of the ALT_MON_GPIO_EXT_PORTA_CDP register field. */
6011 #define ALT_MON_GPIO_EXT_PORTA_CDP_RESET 0x0
6012 /* Extracts the ALT_MON_GPIO_EXT_PORTA_CDP field value from a register. */
6013 #define ALT_MON_GPIO_EXT_PORTA_CDP_GET(value) (((value) & 0x00000400) >> 10)
6014 /* Produces a ALT_MON_GPIO_EXT_PORTA_CDP register field value suitable for setting the register. */
6015 #define ALT_MON_GPIO_EXT_PORTA_CDP_SET(value) (((value) << 10) & 0x00000400)
6016 
6017 /*
6018  * Field : External Port Field (FPGA_POWER_ON) - fpo
6019  *
6020  * Reading this provides the value of FPGA_POWER_ON
6021  *
6022  * Field Access Macros:
6023  *
6024  */
6025 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_EXT_PORTA_FPO register field. */
6026 #define ALT_MON_GPIO_EXT_PORTA_FPO_LSB 11
6027 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_EXT_PORTA_FPO register field. */
6028 #define ALT_MON_GPIO_EXT_PORTA_FPO_MSB 11
6029 /* The width in bits of the ALT_MON_GPIO_EXT_PORTA_FPO register field. */
6030 #define ALT_MON_GPIO_EXT_PORTA_FPO_WIDTH 1
6031 /* The mask used to set the ALT_MON_GPIO_EXT_PORTA_FPO register field value. */
6032 #define ALT_MON_GPIO_EXT_PORTA_FPO_SET_MSK 0x00000800
6033 /* The mask used to clear the ALT_MON_GPIO_EXT_PORTA_FPO register field value. */
6034 #define ALT_MON_GPIO_EXT_PORTA_FPO_CLR_MSK 0xfffff7ff
6035 /* The reset value of the ALT_MON_GPIO_EXT_PORTA_FPO register field. */
6036 #define ALT_MON_GPIO_EXT_PORTA_FPO_RESET 0x0
6037 /* Extracts the ALT_MON_GPIO_EXT_PORTA_FPO field value from a register. */
6038 #define ALT_MON_GPIO_EXT_PORTA_FPO_GET(value) (((value) & 0x00000800) >> 11)
6039 /* Produces a ALT_MON_GPIO_EXT_PORTA_FPO register field value suitable for setting the register. */
6040 #define ALT_MON_GPIO_EXT_PORTA_FPO_SET(value) (((value) << 11) & 0x00000800)
6041 
6042 #ifndef __ASSEMBLY__
6043 /*
6044  * WARNING: The C register and register group struct declarations are provided for
6045  * convenience and illustrative purposes. They should, however, be used with
6046  * caution as the C language standard provides no guarantees about the alignment or
6047  * atomicity of device memory accesses. The recommended practice for writing
6048  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6049  * alt_write_word() functions.
6050  *
6051  * The struct declaration for register ALT_MON_GPIO_EXT_PORTA.
6052  */
6053 struct ALT_MON_GPIO_EXT_PORTA_s
6054 {
6055  const uint32_t ns : 1; /* External Port Field (nSTATUS) */
6056  const uint32_t cd : 1; /* External Port Field (CONF_DONE) */
6057  const uint32_t id : 1; /* External Port Field (INIT_DONE) */
6058  const uint32_t crc : 1; /* External Port Field (CRC_ERROR) */
6059  const uint32_t ccd : 1; /* External Port Field (CVP_CONF_DONE) */
6060  const uint32_t prr : 1; /* External Port Field (PR_READY) */
6061  const uint32_t pre : 1; /* External Port Field (PR_ERROR) */
6062  const uint32_t prd : 1; /* External Port Field (PR_DONE) */
6063  const uint32_t ncp : 1; /* External Port Field (nCONFIG Pin) */
6064  const uint32_t nsp : 1; /* External Port Field (nSTATUS Pin) */
6065  const uint32_t cdp : 1; /* External Port Field (CONF_DONE Pin) */
6066  const uint32_t fpo : 1; /* External Port Field (FPGA_POWER_ON) */
6067  uint32_t : 20; /* *UNDEFINED* */
6068 };
6069 
6070 /* The typedef declaration for register ALT_MON_GPIO_EXT_PORTA. */
6071 typedef volatile struct ALT_MON_GPIO_EXT_PORTA_s ALT_MON_GPIO_EXT_PORTA_t;
6072 #endif /* __ASSEMBLY__ */
6073 
6074 /* The byte offset of the ALT_MON_GPIO_EXT_PORTA register from the beginning of the component. */
6075 #define ALT_MON_GPIO_EXT_PORTA_OFST 0x50
6076 /* The address of the ALT_MON_GPIO_EXT_PORTA register. */
6077 #define ALT_MON_GPIO_EXT_PORTA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_EXT_PORTA_OFST))
6078 
6079 /*
6080  * Register : Synchronization Level Register - gpio_ls_sync
6081  *
6082  * The Synchronization level register is used to synchronize inputs to the
6083  * l4_mp_clk. All MON interrupts are already synchronized before the GPIO instance
6084  * so it is not necessary to setup this register to enable synchronization.
6085  *
6086  * Register Layout
6087  *
6088  * Bits | Access | Reset | Description
6089  * :-------|:-------|:------|:----------------------------
6090  * [0] | RW | 0x0 | Synchronization Level Field
6091  * [31:1] | ??? | 0x0 | *UNDEFINED*
6092  *
6093  */
6094 /*
6095  * Field : Synchronization Level Field - gpio_ls_sync
6096  *
6097  * The level-sensitive interrupts is synchronized to l4_mp_clk.
6098  *
6099  * Field Enumeration Values:
6100  *
6101  * Enum | Value | Description
6102  * :-------------------------------------------|:------|:--------------------------------
6103  * ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC | 0x0 | No synchronization to l4_mp_clk
6104  * ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC | 0x1 | Synchronize to l4_mp_clk
6105  *
6106  * Field Access Macros:
6107  *
6108  */
6109 /*
6110  * Enumerated value for register field ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC
6111  *
6112  * No synchronization to l4_mp_clk
6113  */
6114 #define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC 0x0
6115 /*
6116  * Enumerated value for register field ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC
6117  *
6118  * Synchronize to l4_mp_clk
6119  */
6120 #define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC 0x1
6121 
6122 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
6123 #define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_LSB 0
6124 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
6125 #define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_MSB 0
6126 /* The width in bits of the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
6127 #define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_WIDTH 1
6128 /* The mask used to set the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
6129 #define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_SET_MSK 0x00000001
6130 /* The mask used to clear the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
6131 #define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_CLR_MSK 0xfffffffe
6132 /* The reset value of the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
6133 #define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_RESET 0x0
6134 /* Extracts the ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC field value from a register. */
6135 #define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_GET(value) (((value) & 0x00000001) >> 0)
6136 /* Produces a ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC register field value suitable for setting the register. */
6137 #define ALT_MON_GPIO_LS_SYNC_GPIO_LS_SYNC_SET(value) (((value) << 0) & 0x00000001)
6138 
6139 #ifndef __ASSEMBLY__
6140 /*
6141  * WARNING: The C register and register group struct declarations are provided for
6142  * convenience and illustrative purposes. They should, however, be used with
6143  * caution as the C language standard provides no guarantees about the alignment or
6144  * atomicity of device memory accesses. The recommended practice for writing
6145  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6146  * alt_write_word() functions.
6147  *
6148  * The struct declaration for register ALT_MON_GPIO_LS_SYNC.
6149  */
6150 struct ALT_MON_GPIO_LS_SYNC_s
6151 {
6152  uint32_t gpio_ls_sync : 1; /* Synchronization Level Field */
6153  uint32_t : 31; /* *UNDEFINED* */
6154 };
6155 
6156 /* The typedef declaration for register ALT_MON_GPIO_LS_SYNC. */
6157 typedef volatile struct ALT_MON_GPIO_LS_SYNC_s ALT_MON_GPIO_LS_SYNC_t;
6158 #endif /* __ASSEMBLY__ */
6159 
6160 /* The byte offset of the ALT_MON_GPIO_LS_SYNC register from the beginning of the component. */
6161 #define ALT_MON_GPIO_LS_SYNC_OFST 0x60
6162 /* The address of the ALT_MON_GPIO_LS_SYNC register. */
6163 #define ALT_MON_GPIO_LS_SYNC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_LS_SYNC_OFST))
6164 
6165 /*
6166  * Register : GPIO Version Register - gpio_ver_id_code
6167  *
6168  * GPIO Component Version
6169  *
6170  * Register Layout
6171  *
6172  * Bits | Access | Reset | Description
6173  * :-------|:-------|:-----------|:------------------------------
6174  * [31:0] | R | 0x3230382a | ASCII Component Version Field
6175  *
6176  */
6177 /*
6178  * Field : ASCII Component Version Field - gpio_ver_id_code
6179  *
6180  * ASCII value for each number in the version, followed by *. For example.
6181  * 32_30_31_2A represents the version 2.01
6182  *
6183  * Field Access Macros:
6184  *
6185  */
6186 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
6187 #define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_LSB 0
6188 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
6189 #define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_MSB 31
6190 /* The width in bits of the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
6191 #define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_WIDTH 32
6192 /* The mask used to set the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
6193 #define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET_MSK 0xffffffff
6194 /* The mask used to clear the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
6195 #define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_CLR_MSK 0x00000000
6196 /* The reset value of the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
6197 #define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_RESET 0x3230382a
6198 /* Extracts the ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE field value from a register. */
6199 #define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0)
6200 /* Produces a ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value suitable for setting the register. */
6201 #define ALT_MON_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET(value) (((value) << 0) & 0xffffffff)
6202 
6203 #ifndef __ASSEMBLY__
6204 /*
6205  * WARNING: The C register and register group struct declarations are provided for
6206  * convenience and illustrative purposes. They should, however, be used with
6207  * caution as the C language standard provides no guarantees about the alignment or
6208  * atomicity of device memory accesses. The recommended practice for writing
6209  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6210  * alt_write_word() functions.
6211  *
6212  * The struct declaration for register ALT_MON_GPIO_VER_ID_CODE.
6213  */
6214 struct ALT_MON_GPIO_VER_ID_CODE_s
6215 {
6216  const uint32_t gpio_ver_id_code : 32; /* ASCII Component Version Field */
6217 };
6218 
6219 /* The typedef declaration for register ALT_MON_GPIO_VER_ID_CODE. */
6220 typedef volatile struct ALT_MON_GPIO_VER_ID_CODE_s ALT_MON_GPIO_VER_ID_CODE_t;
6221 #endif /* __ASSEMBLY__ */
6222 
6223 /* The byte offset of the ALT_MON_GPIO_VER_ID_CODE register from the beginning of the component. */
6224 #define ALT_MON_GPIO_VER_ID_CODE_OFST 0x6c
6225 /* The address of the ALT_MON_GPIO_VER_ID_CODE register. */
6226 #define ALT_MON_GPIO_VER_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_VER_ID_CODE_OFST))
6227 
6228 /*
6229  * Register : Configuration Register 2 - gpio_config_reg2
6230  *
6231  * Specifies the bit width of port A.
6232  *
6233  * Register Layout
6234  *
6235  * Bits | Access | Reset | Description
6236  * :--------|:-------|:------|:----------------------
6237  * [4:0] | R | 0xb | Port A Width (less 1)
6238  * [9:5] | R | 0x7 | Port B Width (less 1)
6239  * [14:10] | R | 0x7 | Port C Width (less 1)
6240  * [19:15] | R | 0x7 | Port D Width (less 1)
6241  * [31:20] | ??? | 0x0 | *UNDEFINED*
6242  *
6243  */
6244 /*
6245  * Field : Port A Width (less 1) - encoded_id_pwidth_a
6246  *
6247  * Specifies the width of GPIO Port A. The value 11 represents the 12-bit width
6248  * less one.
6249  *
6250  * Field Enumeration Values:
6251  *
6252  * Enum | Value | Description
6253  * :-----------------------------------------------------------|:------|:--------------------------
6254  * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
6255  * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE12BITS | 0xb | Width (less 1) of 12 bits
6256  *
6257  * Field Access Macros:
6258  *
6259  */
6260 /*
6261  * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
6262  *
6263  * Width (less 1) of 8 bits
6264  */
6265 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS 0x7
6266 /*
6267  * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
6268  *
6269  * Width (less 1) of 12 bits
6270  */
6271 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE12BITS 0xb
6272 
6273 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
6274 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_LSB 0
6275 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
6276 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_MSB 4
6277 /* The width in bits of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
6278 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_WIDTH 5
6279 /* The mask used to set the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */
6280 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET_MSK 0x0000001f
6281 /* The mask used to clear the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */
6282 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_CLR_MSK 0xffffffe0
6283 /* The reset value of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
6284 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_RESET 0xb
6285 /* Extracts the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A field value from a register. */
6286 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_GET(value) (((value) & 0x0000001f) >> 0)
6287 /* Produces a ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value suitable for setting the register. */
6288 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET(value) (((value) << 0) & 0x0000001f)
6289 
6290 /*
6291  * Field : Port B Width (less 1) - encoded_id_pwidth_b
6292  *
6293  * Specifies the width of GPIO Port B. Ignored because there is no Port B in the
6294  * GPIO.
6295  *
6296  * Field Enumeration Values:
6297  *
6298  * Enum | Value | Description
6299  * :-----------------------------------------------------------|:------|:--------------------------
6300  * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
6301  * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE12BITS | 0xb | Width (less 1) of 12 bits
6302  *
6303  * Field Access Macros:
6304  *
6305  */
6306 /*
6307  * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
6308  *
6309  * Width (less 1) of 8 bits
6310  */
6311 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS 0x7
6312 /*
6313  * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
6314  *
6315  * Width (less 1) of 12 bits
6316  */
6317 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE12BITS 0xb
6318 
6319 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
6320 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_LSB 5
6321 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
6322 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_MSB 9
6323 /* The width in bits of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
6324 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_WIDTH 5
6325 /* The mask used to set the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */
6326 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET_MSK 0x000003e0
6327 /* The mask used to clear the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */
6328 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_CLR_MSK 0xfffffc1f
6329 /* The reset value of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
6330 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_RESET 0x7
6331 /* Extracts the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B field value from a register. */
6332 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_GET(value) (((value) & 0x000003e0) >> 5)
6333 /* Produces a ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value suitable for setting the register. */
6334 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET(value) (((value) << 5) & 0x000003e0)
6335 
6336 /*
6337  * Field : Port C Width (less 1) - encoded_id_pwidth_c
6338  *
6339  * Specifies the width of GPIO Port C. Ignored because there is no Port C in the
6340  * GPIO.
6341  *
6342  * Field Enumeration Values:
6343  *
6344  * Enum | Value | Description
6345  * :-----------------------------------------------------------|:------|:--------------------------
6346  * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
6347  * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE12BITS | 0xb | Width (less 1) of 12 bits
6348  *
6349  * Field Access Macros:
6350  *
6351  */
6352 /*
6353  * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
6354  *
6355  * Width (less 1) of 8 bits
6356  */
6357 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS 0x7
6358 /*
6359  * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
6360  *
6361  * Width (less 1) of 12 bits
6362  */
6363 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE12BITS 0xb
6364 
6365 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
6366 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_LSB 10
6367 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
6368 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_MSB 14
6369 /* The width in bits of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
6370 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_WIDTH 5
6371 /* The mask used to set the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */
6372 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET_MSK 0x00007c00
6373 /* The mask used to clear the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */
6374 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_CLR_MSK 0xffff83ff
6375 /* The reset value of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
6376 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_RESET 0x7
6377 /* Extracts the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C field value from a register. */
6378 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_GET(value) (((value) & 0x00007c00) >> 10)
6379 /* Produces a ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value suitable for setting the register. */
6380 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET(value) (((value) << 10) & 0x00007c00)
6381 
6382 /*
6383  * Field : Port D Width (less 1) - encoded_id_pwidth_d
6384  *
6385  * Specifies the width of GPIO Port D. Ignored because there is no Port D in the
6386  * GPIO.
6387  *
6388  * Field Enumeration Values:
6389  *
6390  * Enum | Value | Description
6391  * :-----------------------------------------------------------|:------|:--------------------------
6392  * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
6393  * ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE12BITS | 0xb | Width (less 1) of 12 bits
6394  *
6395  * Field Access Macros:
6396  *
6397  */
6398 /*
6399  * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
6400  *
6401  * Width (less 1) of 8 bits
6402  */
6403 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS 0x7
6404 /*
6405  * Enumerated value for register field ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
6406  *
6407  * Width (less 1) of 12 bits
6408  */
6409 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE12BITS 0xb
6410 
6411 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
6412 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_LSB 15
6413 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
6414 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_MSB 19
6415 /* The width in bits of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
6416 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_WIDTH 5
6417 /* The mask used to set the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */
6418 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET_MSK 0x000f8000
6419 /* The mask used to clear the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */
6420 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_CLR_MSK 0xfff07fff
6421 /* The reset value of the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
6422 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_RESET 0x7
6423 /* Extracts the ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D field value from a register. */
6424 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_GET(value) (((value) & 0x000f8000) >> 15)
6425 /* Produces a ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value suitable for setting the register. */
6426 #define ALT_MON_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET(value) (((value) << 15) & 0x000f8000)
6427 
6428 #ifndef __ASSEMBLY__
6429 /*
6430  * WARNING: The C register and register group struct declarations are provided for
6431  * convenience and illustrative purposes. They should, however, be used with
6432  * caution as the C language standard provides no guarantees about the alignment or
6433  * atomicity of device memory accesses. The recommended practice for writing
6434  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6435  * alt_write_word() functions.
6436  *
6437  * The struct declaration for register ALT_MON_GPIO_CFG_REG2.
6438  */
6439 struct ALT_MON_GPIO_CFG_REG2_s
6440 {
6441  const uint32_t encoded_id_pwidth_a : 5; /* Port A Width (less 1) */
6442  const uint32_t encoded_id_pwidth_b : 5; /* Port B Width (less 1) */
6443  const uint32_t encoded_id_pwidth_c : 5; /* Port C Width (less 1) */
6444  const uint32_t encoded_id_pwidth_d : 5; /* Port D Width (less 1) */
6445  uint32_t : 12; /* *UNDEFINED* */
6446 };
6447 
6448 /* The typedef declaration for register ALT_MON_GPIO_CFG_REG2. */
6449 typedef volatile struct ALT_MON_GPIO_CFG_REG2_s ALT_MON_GPIO_CFG_REG2_t;
6450 #endif /* __ASSEMBLY__ */
6451 
6452 /* The byte offset of the ALT_MON_GPIO_CFG_REG2 register from the beginning of the component. */
6453 #define ALT_MON_GPIO_CFG_REG2_OFST 0x70
6454 /* The address of the ALT_MON_GPIO_CFG_REG2 register. */
6455 #define ALT_MON_GPIO_CFG_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_CFG_REG2_OFST))
6456 
6457 /*
6458  * Register : Configuration Register 1 - gpio_config_reg1
6459  *
6460  * Reports settings of various GPIO configuration parameters
6461  *
6462  * Register Layout
6463  *
6464  * Bits | Access | Reset | Description
6465  * :--------|:-------|:------|:----------------------------------
6466  * [1:0] | R | 0x2 | APB DATA WIDTH
6467  * [3:2] | R | 0x0 | NUM PORTS
6468  * [4] | R | 0x1 | PORT A SINGLE CTL
6469  * [5] | R | 0x1 | PORT B SINGLE CTL
6470  * [6] | R | 0x1 | PORT C SINGLE CTL
6471  * [7] | R | 0x1 | PORT D SINGLE CTL
6472  * [8] | R | 0x0 | HW PORTA
6473  * [11:9] | ??? | 0x0 | *UNDEFINED*
6474  * [12] | R | 0x1 | Port A Interrupt Field
6475  * [13] | R | 0x0 | Debounce Field
6476  * [14] | R | 0x1 | Encoded GPIO Parameters Available
6477  * [15] | R | 0x0 | ID Field
6478  * [20:16] | R | 0x1f | Encoded ID Width Field
6479  * [31:21] | ??? | 0x0 | *UNDEFINED*
6480  *
6481  */
6482 /*
6483  * Field : APB DATA WIDTH - apb_data_width
6484  *
6485  * Fixed to support an APB data bus width of 32-bits.
6486  *
6487  * Field Enumeration Values:
6488  *
6489  * Enum | Value | Description
6490  * :---------------------------------------------------|:------|:-------------------------
6491  * ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits
6492  *
6493  * Field Access Macros:
6494  *
6495  */
6496 /*
6497  * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH
6498  *
6499  * APB Data Width = 32-bits
6500  */
6501 #define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2
6502 
6503 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
6504 #define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_LSB 0
6505 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
6506 #define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_MSB 1
6507 /* The width in bits of the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
6508 #define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_WIDTH 2
6509 /* The mask used to set the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */
6510 #define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_SET_MSK 0x00000003
6511 /* The mask used to clear the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */
6512 #define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
6513 /* The reset value of the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
6514 #define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_RESET 0x2
6515 /* Extracts the ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH field value from a register. */
6516 #define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
6517 /* Produces a ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH register field value suitable for setting the register. */
6518 #define ALT_MON_GPIO_CFG_REG1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
6519 
6520 /*
6521  * Field : NUM PORTS - num_ports
6522  *
6523  * The value of this register is fixed at one port (Port A).
6524  *
6525  * Field Enumeration Values:
6526  *
6527  * Enum | Value | Description
6528  * :-------------------------------------------|:------|:-------------------------
6529  * ALT_MON_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA | 0x0 | Number of GPIO Ports = 1
6530  *
6531  * Field Access Macros:
6532  *
6533  */
6534 /*
6535  * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_NUM_PORTS
6536  *
6537  * Number of GPIO Ports = 1
6538  */
6539 #define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA 0x0
6540 
6541 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field. */
6542 #define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_LSB 2
6543 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field. */
6544 #define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_MSB 3
6545 /* The width in bits of the ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field. */
6546 #define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_WIDTH 2
6547 /* The mask used to set the ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field value. */
6548 #define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_SET_MSK 0x0000000c
6549 /* The mask used to clear the ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field value. */
6550 #define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_CLR_MSK 0xfffffff3
6551 /* The reset value of the ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field. */
6552 #define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_RESET 0x0
6553 /* Extracts the ALT_MON_GPIO_CFG_REG1_NUM_PORTS field value from a register. */
6554 #define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_GET(value) (((value) & 0x0000000c) >> 2)
6555 /* Produces a ALT_MON_GPIO_CFG_REG1_NUM_PORTS register field value suitable for setting the register. */
6556 #define ALT_MON_GPIO_CFG_REG1_NUM_PORTS_SET(value) (((value) << 2) & 0x0000000c)
6557 
6558 /*
6559  * Field : PORT A SINGLE CTL - porta_single_ctl
6560  *
6561  * Indicates the mode of operation of Port A to be software controlled only.
6562  *
6563  * Field Enumeration Values:
6564  *
6565  * Enum | Value | Description
6566  * :-----------------------------------------------------|:------|:-----------------------------------------
6567  * ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
6568  *
6569  * Field Access Macros:
6570  *
6571  */
6572 /*
6573  * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL
6574  *
6575  * Software Enabled Individual Port Control
6576  */
6577 #define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY 0x1
6578 
6579 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
6580 #define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_LSB 4
6581 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
6582 #define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_MSB 4
6583 /* The width in bits of the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
6584 #define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_WIDTH 1
6585 /* The mask used to set the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */
6586 #define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET_MSK 0x00000010
6587 /* The mask used to clear the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */
6588 #define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_CLR_MSK 0xffffffef
6589 /* The reset value of the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
6590 #define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_RESET 0x1
6591 /* Extracts the ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL field value from a register. */
6592 #define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_GET(value) (((value) & 0x00000010) >> 4)
6593 /* Produces a ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value suitable for setting the register. */
6594 #define ALT_MON_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET(value) (((value) << 4) & 0x00000010)
6595 
6596 /*
6597  * Field : PORT B SINGLE CTL - portb_single_ctl
6598  *
6599  * Indicates the mode of operation of Port B to be software controlled only.
6600  * Ignored because there is no Port B in the GPIO.
6601  *
6602  * Field Enumeration Values:
6603  *
6604  * Enum | Value | Description
6605  * :-----------------------------------------------------|:------|:-----------------------------------------
6606  * ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
6607  *
6608  * Field Access Macros:
6609  *
6610  */
6611 /*
6612  * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL
6613  *
6614  * Software Enabled Individual Port Control
6615  */
6616 #define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY 0x1
6617 
6618 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
6619 #define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_LSB 5
6620 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
6621 #define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_MSB 5
6622 /* The width in bits of the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
6623 #define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_WIDTH 1
6624 /* The mask used to set the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */
6625 #define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET_MSK 0x00000020
6626 /* The mask used to clear the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */
6627 #define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_CLR_MSK 0xffffffdf
6628 /* The reset value of the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
6629 #define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_RESET 0x1
6630 /* Extracts the ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL field value from a register. */
6631 #define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_GET(value) (((value) & 0x00000020) >> 5)
6632 /* Produces a ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value suitable for setting the register. */
6633 #define ALT_MON_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET(value) (((value) << 5) & 0x00000020)
6634 
6635 /*
6636  * Field : PORT C SINGLE CTL - portc_single_ctl
6637  *
6638  * Indicates the mode of operation of Port C to be software controlled only.
6639  * Ignored because there is no Port C in the GPIO.
6640  *
6641  * Field Enumeration Values:
6642  *
6643  * Enum | Value | Description
6644  * :-----------------------------------------------------|:------|:-----------------------------------------
6645  * ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
6646  *
6647  * Field Access Macros:
6648  *
6649  */
6650 /*
6651  * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL
6652  *
6653  * Software Enabled Individual Port Control
6654  */
6655 #define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY 0x1
6656 
6657 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
6658 #define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_LSB 6
6659 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
6660 #define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_MSB 6
6661 /* The width in bits of the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
6662 #define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_WIDTH 1
6663 /* The mask used to set the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */
6664 #define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET_MSK 0x00000040
6665 /* The mask used to clear the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */
6666 #define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_CLR_MSK 0xffffffbf
6667 /* The reset value of the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
6668 #define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_RESET 0x1
6669 /* Extracts the ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL field value from a register. */
6670 #define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_GET(value) (((value) & 0x00000040) >> 6)
6671 /* Produces a ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value suitable for setting the register. */
6672 #define ALT_MON_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET(value) (((value) << 6) & 0x00000040)
6673 
6674 /*
6675  * Field : PORT D SINGLE CTL - portd_single_ctl
6676  *
6677  * Indicates the mode of operation of Port D to be software controlled only.
6678  * Ignored because there is no Port D in the GPIO.
6679  *
6680  * Field Enumeration Values:
6681  *
6682  * Enum | Value | Description
6683  * :-----------------------------------------------------|:------|:-----------------------------------------
6684  * ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
6685  *
6686  * Field Access Macros:
6687  *
6688  */
6689 /*
6690  * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL
6691  *
6692  * Software Enabled Individual Port Control
6693  */
6694 #define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY 0x1
6695 
6696 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
6697 #define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_LSB 7
6698 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
6699 #define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_MSB 7
6700 /* The width in bits of the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
6701 #define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_WIDTH 1
6702 /* The mask used to set the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */
6703 #define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET_MSK 0x00000080
6704 /* The mask used to clear the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */
6705 #define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_CLR_MSK 0xffffff7f
6706 /* The reset value of the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
6707 #define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_RESET 0x1
6708 /* Extracts the ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL field value from a register. */
6709 #define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_GET(value) (((value) & 0x00000080) >> 7)
6710 /* Produces a ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value suitable for setting the register. */
6711 #define ALT_MON_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET(value) (((value) << 7) & 0x00000080)
6712 
6713 /*
6714  * Field : HW PORTA - hw_porta
6715  *
6716  * The value is fixed to enable Port A configuration to be controlled by software
6717  * only.
6718  *
6719  * Field Enumeration Values:
6720  *
6721  * Enum | Value | Description
6722  * :---------------------------------------------|:------|:---------------------------------------
6723  * ALT_MON_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD | 0x0 | Software Configuration Control Enabled
6724  *
6725  * Field Access Macros:
6726  *
6727  */
6728 /*
6729  * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_HW_PORTA
6730  *
6731  * Software Configuration Control Enabled
6732  */
6733 #define ALT_MON_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD 0x0
6734 
6735 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_HW_PORTA register field. */
6736 #define ALT_MON_GPIO_CFG_REG1_HW_PORTA_LSB 8
6737 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_HW_PORTA register field. */
6738 #define ALT_MON_GPIO_CFG_REG1_HW_PORTA_MSB 8
6739 /* The width in bits of the ALT_MON_GPIO_CFG_REG1_HW_PORTA register field. */
6740 #define ALT_MON_GPIO_CFG_REG1_HW_PORTA_WIDTH 1
6741 /* The mask used to set the ALT_MON_GPIO_CFG_REG1_HW_PORTA register field value. */
6742 #define ALT_MON_GPIO_CFG_REG1_HW_PORTA_SET_MSK 0x00000100
6743 /* The mask used to clear the ALT_MON_GPIO_CFG_REG1_HW_PORTA register field value. */
6744 #define ALT_MON_GPIO_CFG_REG1_HW_PORTA_CLR_MSK 0xfffffeff
6745 /* The reset value of the ALT_MON_GPIO_CFG_REG1_HW_PORTA register field. */
6746 #define ALT_MON_GPIO_CFG_REG1_HW_PORTA_RESET 0x0
6747 /* Extracts the ALT_MON_GPIO_CFG_REG1_HW_PORTA field value from a register. */
6748 #define ALT_MON_GPIO_CFG_REG1_HW_PORTA_GET(value) (((value) & 0x00000100) >> 8)
6749 /* Produces a ALT_MON_GPIO_CFG_REG1_HW_PORTA register field value suitable for setting the register. */
6750 #define ALT_MON_GPIO_CFG_REG1_HW_PORTA_SET(value) (((value) << 8) & 0x00000100)
6751 
6752 /*
6753  * Field : Port A Interrupt Field - porta_intr
6754  *
6755  * The value of this field is fixed to allow interrupts on Port A.
6756  *
6757  * Field Enumeration Values:
6758  *
6759  * Enum | Value | Description
6760  * :-----------------------------------------------|:------|:--------------------------
6761  * ALT_MON_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR | 0x1 | Port A Interrupts Enabled
6762  *
6763  * Field Access Macros:
6764  *
6765  */
6766 /*
6767  * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_PORTA_INTR
6768  *
6769  * Port A Interrupts Enabled
6770  */
6771 #define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR 0x1
6772 
6773 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field. */
6774 #define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_LSB 12
6775 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field. */
6776 #define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_MSB 12
6777 /* The width in bits of the ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field. */
6778 #define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_WIDTH 1
6779 /* The mask used to set the ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field value. */
6780 #define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_SET_MSK 0x00001000
6781 /* The mask used to clear the ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field value. */
6782 #define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_CLR_MSK 0xffffefff
6783 /* The reset value of the ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field. */
6784 #define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_RESET 0x1
6785 /* Extracts the ALT_MON_GPIO_CFG_REG1_PORTA_INTR field value from a register. */
6786 #define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_GET(value) (((value) & 0x00001000) >> 12)
6787 /* Produces a ALT_MON_GPIO_CFG_REG1_PORTA_INTR register field value suitable for setting the register. */
6788 #define ALT_MON_GPIO_CFG_REG1_PORTA_INTR_SET(value) (((value) << 12) & 0x00001000)
6789 
6790 /*
6791  * Field : Debounce Field - debounce
6792  *
6793  * The value of this field is fixed to not allow debouncing of the Port A signals.
6794  *
6795  * Field Enumeration Values:
6796  *
6797  * Enum | Value | Description
6798  * :------------------------------------------------|:------|:---------------------
6799  * ALT_MON_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA_DISD | 0x0 | Debounce is Disabled
6800  *
6801  * Field Access Macros:
6802  *
6803  */
6804 /*
6805  * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_DEBOUNCE
6806  *
6807  * Debounce is Disabled
6808  */
6809 #define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA_DISD 0x0
6810 
6811 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field. */
6812 #define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_LSB 13
6813 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field. */
6814 #define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_MSB 13
6815 /* The width in bits of the ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field. */
6816 #define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_WIDTH 1
6817 /* The mask used to set the ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field value. */
6818 #define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_SET_MSK 0x00002000
6819 /* The mask used to clear the ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field value. */
6820 #define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_CLR_MSK 0xffffdfff
6821 /* The reset value of the ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field. */
6822 #define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_RESET 0x0
6823 /* Extracts the ALT_MON_GPIO_CFG_REG1_DEBOUNCE field value from a register. */
6824 #define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_GET(value) (((value) & 0x00002000) >> 13)
6825 /* Produces a ALT_MON_GPIO_CFG_REG1_DEBOUNCE register field value suitable for setting the register. */
6826 #define ALT_MON_GPIO_CFG_REG1_DEBOUNCE_SET(value) (((value) << 13) & 0x00002000)
6827 
6828 /*
6829  * Field : Encoded GPIO Parameters Available - add_encoded_params
6830  *
6831  * Fixed to allow the indentification of the Designware IP component.
6832  *
6833  * Field Enumeration Values:
6834  *
6835  * Enum | Value | Description
6836  * :----------------------------------------------------|:------|:--------------------------
6837  * ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Enable IP indentification
6838  *
6839  * Field Access Macros:
6840  *
6841  */
6842 /*
6843  * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS
6844  *
6845  * Enable IP indentification
6846  */
6847 #define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1
6848 
6849 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
6850 #define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_LSB 14
6851 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
6852 #define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_MSB 14
6853 /* The width in bits of the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
6854 #define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_WIDTH 1
6855 /* The mask used to set the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */
6856 #define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET_MSK 0x00004000
6857 /* The mask used to clear the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */
6858 #define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_CLR_MSK 0xffffbfff
6859 /* The reset value of the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
6860 #define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_RESET 0x1
6861 /* Extracts the ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS field value from a register. */
6862 #define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00004000) >> 14)
6863 /* Produces a ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value suitable for setting the register. */
6864 #define ALT_MON_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET(value) (((value) << 14) & 0x00004000)
6865 
6866 /*
6867  * Field : ID Field - gpio_id
6868  *
6869  * Provides an ID code value
6870  *
6871  * Field Enumeration Values:
6872  *
6873  * Enum | Value | Description
6874  * :------------------------------------------------|:------|:-------------------------------
6875  * ALT_MON_GPIO_CFG_REG1_GPIO_ID_E_IDCODE_EXCLUDED | 0x0 | GPIO ID Code Register Excluded
6876  *
6877  * Field Access Macros:
6878  *
6879  */
6880 /*
6881  * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_GPIO_ID
6882  *
6883  * GPIO ID Code Register Excluded
6884  */
6885 #define ALT_MON_GPIO_CFG_REG1_GPIO_ID_E_IDCODE_EXCLUDED 0x0
6886 
6887 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_GPIO_ID register field. */
6888 #define ALT_MON_GPIO_CFG_REG1_GPIO_ID_LSB 15
6889 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_GPIO_ID register field. */
6890 #define ALT_MON_GPIO_CFG_REG1_GPIO_ID_MSB 15
6891 /* The width in bits of the ALT_MON_GPIO_CFG_REG1_GPIO_ID register field. */
6892 #define ALT_MON_GPIO_CFG_REG1_GPIO_ID_WIDTH 1
6893 /* The mask used to set the ALT_MON_GPIO_CFG_REG1_GPIO_ID register field value. */
6894 #define ALT_MON_GPIO_CFG_REG1_GPIO_ID_SET_MSK 0x00008000
6895 /* The mask used to clear the ALT_MON_GPIO_CFG_REG1_GPIO_ID register field value. */
6896 #define ALT_MON_GPIO_CFG_REG1_GPIO_ID_CLR_MSK 0xffff7fff
6897 /* The reset value of the ALT_MON_GPIO_CFG_REG1_GPIO_ID register field. */
6898 #define ALT_MON_GPIO_CFG_REG1_GPIO_ID_RESET 0x0
6899 /* Extracts the ALT_MON_GPIO_CFG_REG1_GPIO_ID field value from a register. */
6900 #define ALT_MON_GPIO_CFG_REG1_GPIO_ID_GET(value) (((value) & 0x00008000) >> 15)
6901 /* Produces a ALT_MON_GPIO_CFG_REG1_GPIO_ID register field value suitable for setting the register. */
6902 #define ALT_MON_GPIO_CFG_REG1_GPIO_ID_SET(value) (((value) << 15) & 0x00008000)
6903 
6904 /*
6905  * Field : Encoded ID Width Field - encoded_id_width
6906  *
6907  * This value is fixed at 32 bits.
6908  *
6909  * Field Enumeration Values:
6910  *
6911  * Enum | Value | Description
6912  * :------------------------------------------------|:------|:------------------
6913  * ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH | 0x1f | Width of ID Field
6914  *
6915  * Field Access Macros:
6916  *
6917  */
6918 /*
6919  * Enumerated value for register field ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH
6920  *
6921  * Width of ID Field
6922  */
6923 #define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH 0x1f
6924 
6925 /* The Least Significant Bit (LSB) position of the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
6926 #define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_LSB 16
6927 /* The Most Significant Bit (MSB) position of the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
6928 #define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_MSB 20
6929 /* The width in bits of the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
6930 #define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_WIDTH 5
6931 /* The mask used to set the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */
6932 #define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_SET_MSK 0x001f0000
6933 /* The mask used to clear the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */
6934 #define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_CLR_MSK 0xffe0ffff
6935 /* The reset value of the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
6936 #define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_RESET 0x1f
6937 /* Extracts the ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH field value from a register. */
6938 #define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_GET(value) (((value) & 0x001f0000) >> 16)
6939 /* Produces a ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH register field value suitable for setting the register. */
6940 #define ALT_MON_GPIO_CFG_REG1_ENC_ID_WIDTH_SET(value) (((value) << 16) & 0x001f0000)
6941 
6942 #ifndef __ASSEMBLY__
6943 /*
6944  * WARNING: The C register and register group struct declarations are provided for
6945  * convenience and illustrative purposes. They should, however, be used with
6946  * caution as the C language standard provides no guarantees about the alignment or
6947  * atomicity of device memory accesses. The recommended practice for writing
6948  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6949  * alt_write_word() functions.
6950  *
6951  * The struct declaration for register ALT_MON_GPIO_CFG_REG1.
6952  */
6953 struct ALT_MON_GPIO_CFG_REG1_s
6954 {
6955  const uint32_t apb_data_width : 2; /* APB DATA WIDTH */
6956  const uint32_t num_ports : 2; /* NUM PORTS */
6957  const uint32_t porta_single_ctl : 1; /* PORT A SINGLE CTL */
6958  const uint32_t portb_single_ctl : 1; /* PORT B SINGLE CTL */
6959  const uint32_t portc_single_ctl : 1; /* PORT C SINGLE CTL */
6960  const uint32_t portd_single_ctl : 1; /* PORT D SINGLE CTL */
6961  const uint32_t hw_porta : 1; /* HW PORTA */
6962  uint32_t : 3; /* *UNDEFINED* */
6963  const uint32_t porta_intr : 1; /* Port A Interrupt Field */
6964  const uint32_t debounce : 1; /* Debounce Field */
6965  const uint32_t add_encoded_params : 1; /* Encoded GPIO Parameters Available */
6966  const uint32_t gpio_id : 1; /* ID Field */
6967  const uint32_t encoded_id_width : 5; /* Encoded ID Width Field */
6968  uint32_t : 11; /* *UNDEFINED* */
6969 };
6970 
6971 /* The typedef declaration for register ALT_MON_GPIO_CFG_REG1. */
6972 typedef volatile struct ALT_MON_GPIO_CFG_REG1_s ALT_MON_GPIO_CFG_REG1_t;
6973 #endif /* __ASSEMBLY__ */
6974 
6975 /* The byte offset of the ALT_MON_GPIO_CFG_REG1 register from the beginning of the component. */
6976 #define ALT_MON_GPIO_CFG_REG1_OFST 0x74
6977 /* The address of the ALT_MON_GPIO_CFG_REG1 register. */
6978 #define ALT_MON_GPIO_CFG_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_MON_GPIO_CFG_REG1_OFST))
6979 
6980 #ifndef __ASSEMBLY__
6981 /*
6982  * WARNING: The C register and register group struct declarations are provided for
6983  * convenience and illustrative purposes. They should, however, be used with
6984  * caution as the C language standard provides no guarantees about the alignment or
6985  * atomicity of device memory accesses. The recommended practice for writing
6986  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6987  * alt_write_word() functions.
6988  *
6989  * The struct declaration for register group ALT_MON.
6990  */
6991 struct ALT_MON_s
6992 {
6993  volatile uint32_t _pad_0x0_0x2f[12]; /* *UNDEFINED* */
6994  ALT_MON_GPIO_INTEN_t gpio_inten; /* ALT_MON_GPIO_INTEN */
6995  ALT_MON_GPIO_INTMSK_t gpio_intmask; /* ALT_MON_GPIO_INTMSK */
6996  ALT_MON_GPIO_INTTYPE_LEVEL_t gpio_inttype_level; /* ALT_MON_GPIO_INTTYPE_LEVEL */
6997  ALT_MON_GPIO_INT_POL_t gpio_int_polarity; /* ALT_MON_GPIO_INT_POL */
6998  ALT_MON_GPIO_INTSTAT_t gpio_intstatus; /* ALT_MON_GPIO_INTSTAT */
6999  ALT_MON_GPIO_RAW_INTSTAT_t gpio_raw_intstatus; /* ALT_MON_GPIO_RAW_INTSTAT */
7000  volatile uint32_t _pad_0x48_0x4b; /* *UNDEFINED* */
7001  ALT_MON_GPIO_PORTA_EOI_t gpio_porta_eoi; /* ALT_MON_GPIO_PORTA_EOI */
7002  ALT_MON_GPIO_EXT_PORTA_t gpio_ext_porta; /* ALT_MON_GPIO_EXT_PORTA */
7003  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
7004  ALT_MON_GPIO_LS_SYNC_t gpio_ls_sync; /* ALT_MON_GPIO_LS_SYNC */
7005  volatile uint32_t _pad_0x64_0x6b[2]; /* *UNDEFINED* */
7006  ALT_MON_GPIO_VER_ID_CODE_t gpio_ver_id_code; /* ALT_MON_GPIO_VER_ID_CODE */
7007  ALT_MON_GPIO_CFG_REG2_t gpio_config_reg2; /* ALT_MON_GPIO_CFG_REG2 */
7008  ALT_MON_GPIO_CFG_REG1_t gpio_config_reg1; /* ALT_MON_GPIO_CFG_REG1 */
7009  volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */
7010 };
7011 
7012 /* The typedef declaration for register group ALT_MON. */
7013 typedef volatile struct ALT_MON_s ALT_MON_t;
7014 /* The struct declaration for the raw register contents of register group ALT_MON. */
7015 struct ALT_MON_raw_s
7016 {
7017  uint32_t _pad_0x0_0x2f[12]; /* *UNDEFINED* */
7018  volatile uint32_t gpio_inten; /* ALT_MON_GPIO_INTEN */
7019  volatile uint32_t gpio_intmask; /* ALT_MON_GPIO_INTMSK */
7020  volatile uint32_t gpio_inttype_level; /* ALT_MON_GPIO_INTTYPE_LEVEL */
7021  volatile uint32_t gpio_int_polarity; /* ALT_MON_GPIO_INT_POL */
7022  volatile uint32_t gpio_intstatus; /* ALT_MON_GPIO_INTSTAT */
7023  volatile uint32_t gpio_raw_intstatus; /* ALT_MON_GPIO_RAW_INTSTAT */
7024  uint32_t _pad_0x48_0x4b; /* *UNDEFINED* */
7025  volatile uint32_t gpio_porta_eoi; /* ALT_MON_GPIO_PORTA_EOI */
7026  volatile uint32_t gpio_ext_porta; /* ALT_MON_GPIO_EXT_PORTA */
7027  uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
7028  volatile uint32_t gpio_ls_sync; /* ALT_MON_GPIO_LS_SYNC */
7029  uint32_t _pad_0x64_0x6b[2]; /* *UNDEFINED* */
7030  volatile uint32_t gpio_ver_id_code; /* ALT_MON_GPIO_VER_ID_CODE */
7031  volatile uint32_t gpio_config_reg2; /* ALT_MON_GPIO_CFG_REG2 */
7032  volatile uint32_t gpio_config_reg1; /* ALT_MON_GPIO_CFG_REG1 */
7033  uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */
7034 };
7035 
7036 /* The typedef declaration for the raw register contents of register group ALT_MON. */
7037 typedef volatile struct ALT_MON_raw_s ALT_MON_raw_t;
7038 #endif /* __ASSEMBLY__ */
7039 
7040 
7041 #ifndef __ASSEMBLY__
7042 /*
7043  * WARNING: The C register and register group struct declarations are provided for
7044  * convenience and illustrative purposes. They should, however, be used with
7045  * caution as the C language standard provides no guarantees about the alignment or
7046  * atomicity of device memory accesses. The recommended practice for writing
7047  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7048  * alt_write_word() functions.
7049  *
7050  * The struct declaration for register group ALT_FPGAMGR.
7051  */
7052 struct ALT_FPGAMGR_s
7053 {
7054  ALT_FPGAMGR_STAT_t stat; /* ALT_FPGAMGR_STAT */
7055  ALT_FPGAMGR_CTL_t ctrl; /* ALT_FPGAMGR_CTL */
7056  ALT_FPGAMGR_DCLKCNT_t dclkcnt; /* ALT_FPGAMGR_DCLKCNT */
7057  ALT_FPGAMGR_DCLKSTAT_t dclkstat; /* ALT_FPGAMGR_DCLKSTAT */
7058  ALT_FPGAMGR_GPO_t gpo; /* ALT_FPGAMGR_GPO */
7059  ALT_FPGAMGR_GPI_t gpi; /* ALT_FPGAMGR_GPI */
7060  ALT_FPGAMGR_MISCI_t misci; /* ALT_FPGAMGR_MISCI */
7061  volatile uint32_t _pad_0x1c_0x7ff[505]; /* *UNDEFINED* */
7062  ALT_MON_t mon; /* ALT_MON */
7063  volatile uint32_t _pad_0x880_0x1000[480]; /* *UNDEFINED* */
7064 };
7065 
7066 /* The typedef declaration for register group ALT_FPGAMGR. */
7067 typedef volatile struct ALT_FPGAMGR_s ALT_FPGAMGR_t;
7068 /* The struct declaration for the raw register contents of register group ALT_FPGAMGR. */
7069 struct ALT_FPGAMGR_raw_s
7070 {
7071  volatile uint32_t stat; /* ALT_FPGAMGR_STAT */
7072  volatile uint32_t ctrl; /* ALT_FPGAMGR_CTL */
7073  volatile uint32_t dclkcnt; /* ALT_FPGAMGR_DCLKCNT */
7074  volatile uint32_t dclkstat; /* ALT_FPGAMGR_DCLKSTAT */
7075  volatile uint32_t gpo; /* ALT_FPGAMGR_GPO */
7076  volatile uint32_t gpi; /* ALT_FPGAMGR_GPI */
7077  volatile uint32_t misci; /* ALT_FPGAMGR_MISCI */
7078  uint32_t _pad_0x1c_0x7ff[505]; /* *UNDEFINED* */
7079  ALT_MON_raw_t mon; /* ALT_MON */
7080  uint32_t _pad_0x880_0x1000[480]; /* *UNDEFINED* */
7081 };
7082 
7083 /* The typedef declaration for the raw register contents of register group ALT_FPGAMGR. */
7084 typedef volatile struct ALT_FPGAMGR_raw_s ALT_FPGAMGR_raw_t;
7085 #endif /* __ASSEMBLY__ */
7086 
7087 
7088 #ifdef __cplusplus
7089 }
7090 #endif /* __cplusplus */
7091 #endif /* __ALTERA_ALT_FPGAMGR_H__ */
7092