Hardware Libraries  20.1
Stratix 10 SoC Hardware Manager
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups
alt_soc_noc_fw_mpfe_csr.h
1 /***********************************************************************************
2 * *
3 * Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
4 * *
5 * Redistribution and use in source and binary forms, with or without *
6 * modification, are permitted provided that the following conditions are met: *
7 * *
8 * 1. Redistributions of source code must retain the above copyright notice, *
9 * this list of conditions and the following disclaimer. *
10 * *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, *
12 * this list of conditions and the following disclaimer in the documentation *
13 * and/or other materials provided with the distribution. *
14 * *
15 * 3. Neither the name of the copyright holder nor the names of its contributors *
16 * may be used to endorse or promote products derived from this software without *
17 * specific prior written permission. *
18 * *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
29 * POSSIBILITY OF SUCH DAMAGE. *
30 * *
31 ***********************************************************************************/
32 
33 /* Altera - ALT_SOC_NOC_FW_MPFE_CSR */
34 
35 #ifndef __ALT_SOCAL_SOC_NOC_FW_MPFE_CSR_H__
36 #define __ALT_SOCAL_SOC_NOC_FW_MPFE_CSR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : SOC_NOC_FW_MPFE_CSR
50  * MPFE Security Control Registers (SCR)
51  *
52  */
53 /*
54  * Register : hmc_register
55  *
56  * Per-Master Security bit for hmc_register
57  *
58  * Register Layout
59  *
60  * Bits | Access | Reset | Description
61  * :--------|:-------|:------|:----------------------------------------------
62  * [0] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU
63  * [7:1] | ??? | 0x0 | *UNDEFINED*
64  * [8] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC
65  * [15:9] | ??? | 0x0 | *UNDEFINED*
66  * [16] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP
67  * [31:17] | ??? | 0x0 | *UNDEFINED*
68  *
69  */
70 /*
71  * Field : mpu
72  *
73  * Security bit configuration for transactions from mpu to hmc_register. When
74  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
75  * Non-Secure transactions are allowed.
76  *
77  * Field Access Macros:
78  *
79  */
80 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU register field. */
81 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_LSB 0
82 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU register field. */
83 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_MSB 0
84 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU register field. */
85 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_WIDTH 1
86 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU register field value. */
87 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_SET_MSK 0x00000001
88 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU register field value. */
89 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_CLR_MSK 0xfffffffe
90 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU register field. */
91 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_RESET 0x0
92 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU field value from a register. */
93 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_GET(value) (((value) & 0x00000001) >> 0)
94 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU register field value suitable for setting the register. */
95 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU_SET(value) (((value) << 0) & 0x00000001)
96 
97 /*
98  * Field : fpga2soc
99  *
100  * Security bit configuration for transactions from fpga2soc to hmc_register. When
101  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
102  * Non-Secure transactions are allowed.
103  *
104  * Field Access Macros:
105  *
106  */
107 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC register field. */
108 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_LSB 8
109 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC register field. */
110 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_MSB 8
111 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC register field. */
112 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_WIDTH 1
113 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC register field value. */
114 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_SET_MSK 0x00000100
115 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC register field value. */
116 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_CLR_MSK 0xfffffeff
117 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC register field. */
118 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_RESET 0x0
119 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC field value from a register. */
120 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_GET(value) (((value) & 0x00000100) >> 8)
121 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC register field value suitable for setting the register. */
122 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC_SET(value) (((value) << 8) & 0x00000100)
123 
124 /*
125  * Field : axi_ap
126  *
127  * Security bit configuration for transactions from axi_ap to hmc_register. When
128  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
129  * Non-Secure transactions are allowed.
130  *
131  * Field Access Macros:
132  *
133  */
134 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP register field. */
135 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_LSB 16
136 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP register field. */
137 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_MSB 16
138 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP register field. */
139 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_WIDTH 1
140 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP register field value. */
141 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_SET_MSK 0x00010000
142 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP register field value. */
143 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_CLR_MSK 0xfffeffff
144 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP register field. */
145 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_RESET 0x0
146 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP field value from a register. */
147 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_GET(value) (((value) & 0x00010000) >> 16)
148 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP register field value suitable for setting the register. */
149 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP_SET(value) (((value) << 16) & 0x00010000)
150 
151 #ifndef __ASSEMBLY__
152 /*
153  * WARNING: The C register and register group struct declarations are provided for
154  * convenience and illustrative purposes. They should, however, be used with
155  * caution as the C language standard provides no guarantees about the alignment or
156  * atomicity of device memory accesses. The recommended practice for coding device
157  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
158  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
159  * alt_write_dword() functions for 64 bit registers.
160  *
161  * The struct declaration for register ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER.
162  */
163 struct ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_s
164 {
165  volatile uint32_t mpu : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_MPU */
166  uint32_t : 7; /* *UNDEFINED* */
167  volatile uint32_t fpga2soc : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_FPGA2SOC */
168  uint32_t : 7; /* *UNDEFINED* */
169  volatile uint32_t axi_ap : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_AXI_AP */
170  uint32_t : 15; /* *UNDEFINED* */
171 };
172 
173 /* The typedef declaration for register ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER. */
174 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_s ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_t;
175 #endif /* __ASSEMBLY__ */
176 
177 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER register. */
178 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_RESET 0x00000000
179 /* The byte offset of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER register from the beginning of the component. */
180 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_OFST 0x0
181 
182 /*
183  * Register : hmc_adaptor_register
184  *
185  * Per-Master Security bit for hmc_adaptor_register
186  *
187  * Register Layout
188  *
189  * Bits | Access | Reset | Description
190  * :--------|:-------|:------|:------------------------------------------------------
191  * [0] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU
192  * [7:1] | ??? | 0x0 | *UNDEFINED*
193  * [8] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC
194  * [15:9] | ??? | 0x0 | *UNDEFINED*
195  * [16] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP
196  * [31:17] | ??? | 0x0 | *UNDEFINED*
197  *
198  */
199 /*
200  * Field : mpu
201  *
202  * Security bit configuration for transactions from mpu to hmc_adaptor_register.
203  * When cleared (0), only Secure transactions are allowed. When set (1), both
204  * Secure and Non-Secure transactions are allowed.
205  *
206  * Field Access Macros:
207  *
208  */
209 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU register field. */
210 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_LSB 0
211 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU register field. */
212 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_MSB 0
213 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU register field. */
214 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_WIDTH 1
215 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU register field value. */
216 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_SET_MSK 0x00000001
217 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU register field value. */
218 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_CLR_MSK 0xfffffffe
219 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU register field. */
220 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_RESET 0x0
221 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU field value from a register. */
222 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_GET(value) (((value) & 0x00000001) >> 0)
223 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU register field value suitable for setting the register. */
224 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU_SET(value) (((value) << 0) & 0x00000001)
225 
226 /*
227  * Field : fpga2soc
228  *
229  * Security bit configuration for transactions from fpga2soc to
230  * hmc_adaptor_register. When cleared (0), only Secure transactions are allowed.
231  * When set (1), both Secure and Non-Secure transactions are allowed.
232  *
233  * Field Access Macros:
234  *
235  */
236 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC register field. */
237 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_LSB 8
238 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC register field. */
239 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_MSB 8
240 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC register field. */
241 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_WIDTH 1
242 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC register field value. */
243 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_SET_MSK 0x00000100
244 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC register field value. */
245 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_CLR_MSK 0xfffffeff
246 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC register field. */
247 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_RESET 0x0
248 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC field value from a register. */
249 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_GET(value) (((value) & 0x00000100) >> 8)
250 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC register field value suitable for setting the register. */
251 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC_SET(value) (((value) << 8) & 0x00000100)
252 
253 /*
254  * Field : axi_ap
255  *
256  * Security bit configuration for transactions from axi_ap to hmc_adaptor_register.
257  * When cleared (0), only Secure transactions are allowed. When set (1), both
258  * Secure and Non-Secure transactions are allowed.
259  *
260  * Field Access Macros:
261  *
262  */
263 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP register field. */
264 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_LSB 16
265 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP register field. */
266 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_MSB 16
267 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP register field. */
268 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_WIDTH 1
269 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP register field value. */
270 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_SET_MSK 0x00010000
271 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP register field value. */
272 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_CLR_MSK 0xfffeffff
273 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP register field. */
274 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_RESET 0x0
275 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP field value from a register. */
276 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_GET(value) (((value) & 0x00010000) >> 16)
277 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP register field value suitable for setting the register. */
278 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP_SET(value) (((value) << 16) & 0x00010000)
279 
280 #ifndef __ASSEMBLY__
281 /*
282  * WARNING: The C register and register group struct declarations are provided for
283  * convenience and illustrative purposes. They should, however, be used with
284  * caution as the C language standard provides no guarantees about the alignment or
285  * atomicity of device memory accesses. The recommended practice for coding device
286  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
287  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
288  * alt_write_dword() functions for 64 bit registers.
289  *
290  * The struct declaration for register ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER.
291  */
292 struct ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_s
293 {
294  volatile uint32_t mpu : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_MPU */
295  uint32_t : 7; /* *UNDEFINED* */
296  volatile uint32_t fpga2soc : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_FPGA2SOC */
297  uint32_t : 7; /* *UNDEFINED* */
298  volatile uint32_t axi_ap : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_AXI_AP */
299  uint32_t : 15; /* *UNDEFINED* */
300 };
301 
302 /* The typedef declaration for register ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER. */
303 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_s ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_t;
304 #endif /* __ASSEMBLY__ */
305 
306 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER register. */
307 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_RESET 0x00000000
308 /* The byte offset of the ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER register from the beginning of the component. */
309 #define ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_OFST 0x4
310 
311 /*
312  * Register : noc_scheduler_csr
313  *
314  * Per-Master Security bit for ddr_scheduler_register
315  *
316  * Register Layout
317  *
318  * Bits | Access | Reset | Description
319  * :--------|:-------|:------|:---------------------------------------------------
320  * [0] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU
321  * [7:1] | ??? | 0x0 | *UNDEFINED*
322  * [8] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC
323  * [15:9] | ??? | 0x0 | *UNDEFINED*
324  * [16] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP
325  * [31:17] | ??? | 0x0 | *UNDEFINED*
326  *
327  */
328 /*
329  * Field : mpu
330  *
331  * Security bit configuration for transactions from mpu to ddr_scheduler_register.
332  * When cleared (0), only Secure transactions are allowed. When set (1), both
333  * Secure and Non-Secure transactions are allowed.
334  *
335  * Field Access Macros:
336  *
337  */
338 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU register field. */
339 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_LSB 0
340 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU register field. */
341 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_MSB 0
342 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU register field. */
343 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_WIDTH 1
344 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU register field value. */
345 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_SET_MSK 0x00000001
346 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU register field value. */
347 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_CLR_MSK 0xfffffffe
348 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU register field. */
349 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_RESET 0x0
350 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU field value from a register. */
351 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_GET(value) (((value) & 0x00000001) >> 0)
352 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU register field value suitable for setting the register. */
353 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU_SET(value) (((value) << 0) & 0x00000001)
354 
355 /*
356  * Field : fpga2soc
357  *
358  * Security bit configuration for transactions from fpga2soc to
359  * ddr_scheduler_register. When cleared (0), only Secure transactions are allowed.
360  * When set (1), both Secure and Non-Secure transactions are allowed.
361  *
362  * Field Access Macros:
363  *
364  */
365 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC register field. */
366 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_LSB 8
367 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC register field. */
368 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_MSB 8
369 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC register field. */
370 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_WIDTH 1
371 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC register field value. */
372 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_SET_MSK 0x00000100
373 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC register field value. */
374 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_CLR_MSK 0xfffffeff
375 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC register field. */
376 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_RESET 0x0
377 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC field value from a register. */
378 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_GET(value) (((value) & 0x00000100) >> 8)
379 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC register field value suitable for setting the register. */
380 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC_SET(value) (((value) << 8) & 0x00000100)
381 
382 /*
383  * Field : axi_ap
384  *
385  * Security bit configuration for transactions from axi_ap to
386  * ddr_scheduler_register. When cleared (0), only Secure transactions are allowed.
387  * When set (1), both Secure and Non-Secure transactions are allowed.
388  *
389  * Field Access Macros:
390  *
391  */
392 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP register field. */
393 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_LSB 16
394 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP register field. */
395 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_MSB 16
396 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP register field. */
397 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_WIDTH 1
398 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP register field value. */
399 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_SET_MSK 0x00010000
400 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP register field value. */
401 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_CLR_MSK 0xfffeffff
402 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP register field. */
403 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_RESET 0x0
404 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP field value from a register. */
405 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_GET(value) (((value) & 0x00010000) >> 16)
406 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP register field value suitable for setting the register. */
407 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP_SET(value) (((value) << 16) & 0x00010000)
408 
409 #ifndef __ASSEMBLY__
410 /*
411  * WARNING: The C register and register group struct declarations are provided for
412  * convenience and illustrative purposes. They should, however, be used with
413  * caution as the C language standard provides no guarantees about the alignment or
414  * atomicity of device memory accesses. The recommended practice for coding device
415  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
416  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
417  * alt_write_dword() functions for 64 bit registers.
418  *
419  * The struct declaration for register ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR.
420  */
421 struct ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_s
422 {
423  volatile uint32_t mpu : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_MPU */
424  uint32_t : 7; /* *UNDEFINED* */
425  volatile uint32_t fpga2soc : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_FPGA2SOC */
426  uint32_t : 7; /* *UNDEFINED* */
427  volatile uint32_t axi_ap : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_AXI_AP */
428  uint32_t : 15; /* *UNDEFINED* */
429 };
430 
431 /* The typedef declaration for register ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR. */
432 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_s ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_t;
433 #endif /* __ASSEMBLY__ */
434 
435 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR register. */
436 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_RESET 0x00000000
437 /* The byte offset of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR register from the beginning of the component. */
438 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_OFST 0x8
439 
440 /*
441  * Register : noc_qos
442  *
443  * Per-Master Security bit for noc_qos_register
444  *
445  * Register Layout
446  *
447  * Bits | Access | Reset | Description
448  * :--------|:-------|:------|:-----------------------------------------
449  * [0] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU
450  * [7:1] | ??? | 0x0 | *UNDEFINED*
451  * [8] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC
452  * [15:9] | ??? | 0x0 | *UNDEFINED*
453  * [16] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP
454  * [31:17] | ??? | 0x0 | *UNDEFINED*
455  *
456  */
457 /*
458  * Field : mpu
459  *
460  * Security bit configuration for transactions from mpu to noc_qos. When cleared
461  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
462  * Secure transactions are allowed.
463  *
464  * Field Access Macros:
465  *
466  */
467 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU register field. */
468 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_LSB 0
469 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU register field. */
470 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_MSB 0
471 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU register field. */
472 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_WIDTH 1
473 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU register field value. */
474 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_SET_MSK 0x00000001
475 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU register field value. */
476 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_CLR_MSK 0xfffffffe
477 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU register field. */
478 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_RESET 0x0
479 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU field value from a register. */
480 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_GET(value) (((value) & 0x00000001) >> 0)
481 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU register field value suitable for setting the register. */
482 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU_SET(value) (((value) << 0) & 0x00000001)
483 
484 /*
485  * Field : fpga2soc
486  *
487  * Security bit configuration for transactions from fpga2soc to noc_qos. When
488  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
489  * Non-Secure transactions are allowed.
490  *
491  * Field Access Macros:
492  *
493  */
494 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC register field. */
495 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_LSB 8
496 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC register field. */
497 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_MSB 8
498 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC register field. */
499 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_WIDTH 1
500 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC register field value. */
501 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_SET_MSK 0x00000100
502 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC register field value. */
503 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_CLR_MSK 0xfffffeff
504 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC register field. */
505 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_RESET 0x0
506 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC field value from a register. */
507 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_GET(value) (((value) & 0x00000100) >> 8)
508 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC register field value suitable for setting the register. */
509 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC_SET(value) (((value) << 8) & 0x00000100)
510 
511 /*
512  * Field : axi_ap
513  *
514  * Security bit configuration for transactions from axi_ap to noc_qos. When cleared
515  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
516  * Secure transactions are allowed.
517  *
518  * Field Access Macros:
519  *
520  */
521 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP register field. */
522 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_LSB 16
523 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP register field. */
524 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_MSB 16
525 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP register field. */
526 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_WIDTH 1
527 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP register field value. */
528 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_SET_MSK 0x00010000
529 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP register field value. */
530 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_CLR_MSK 0xfffeffff
531 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP register field. */
532 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_RESET 0x0
533 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP field value from a register. */
534 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_GET(value) (((value) & 0x00010000) >> 16)
535 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP register field value suitable for setting the register. */
536 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP_SET(value) (((value) << 16) & 0x00010000)
537 
538 #ifndef __ASSEMBLY__
539 /*
540  * WARNING: The C register and register group struct declarations are provided for
541  * convenience and illustrative purposes. They should, however, be used with
542  * caution as the C language standard provides no guarantees about the alignment or
543  * atomicity of device memory accesses. The recommended practice for coding device
544  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
545  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
546  * alt_write_dword() functions for 64 bit registers.
547  *
548  * The struct declaration for register ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS.
549  */
550 struct ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_s
551 {
552  volatile uint32_t mpu : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_MPU */
553  uint32_t : 7; /* *UNDEFINED* */
554  volatile uint32_t fpga2soc : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_FPGA2SOC */
555  uint32_t : 7; /* *UNDEFINED* */
556  volatile uint32_t axi_ap : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_AXI_AP */
557  uint32_t : 15; /* *UNDEFINED* */
558 };
559 
560 /* The typedef declaration for register ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS. */
561 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_s ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_t;
562 #endif /* __ASSEMBLY__ */
563 
564 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS register. */
565 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_RESET 0x00000000
566 /* The byte offset of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS register from the beginning of the component. */
567 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_OFST 0x10
568 
569 /*
570  * Register : noc_probes
571  *
572  * Per-Master Security bit for noc_probes_register
573  *
574  * Register Layout
575  *
576  * Bits | Access | Reset | Description
577  * :--------|:-------|:------|:--------------------------------------------
578  * [0] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU
579  * [7:1] | ??? | 0x0 | *UNDEFINED*
580  * [8] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC
581  * [15:9] | ??? | 0x0 | *UNDEFINED*
582  * [16] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP
583  * [31:17] | ??? | 0x0 | *UNDEFINED*
584  *
585  */
586 /*
587  * Field : mpu
588  *
589  * Security bit configuration for transactions from mpu to noc_probes. When cleared
590  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
591  * Secure transactions are allowed.
592  *
593  * Field Access Macros:
594  *
595  */
596 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU register field. */
597 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_LSB 0
598 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU register field. */
599 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_MSB 0
600 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU register field. */
601 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_WIDTH 1
602 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU register field value. */
603 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_SET_MSK 0x00000001
604 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU register field value. */
605 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_CLR_MSK 0xfffffffe
606 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU register field. */
607 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_RESET 0x0
608 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU field value from a register. */
609 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_GET(value) (((value) & 0x00000001) >> 0)
610 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU register field value suitable for setting the register. */
611 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU_SET(value) (((value) << 0) & 0x00000001)
612 
613 /*
614  * Field : fpga2soc
615  *
616  * Security bit configuration for transactions from mpu to noc_probes. When cleared
617  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
618  * Secure transactions are allowed.
619  *
620  * Field Access Macros:
621  *
622  */
623 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC register field. */
624 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_LSB 8
625 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC register field. */
626 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_MSB 8
627 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC register field. */
628 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_WIDTH 1
629 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC register field value. */
630 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_SET_MSK 0x00000100
631 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC register field value. */
632 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_CLR_MSK 0xfffffeff
633 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC register field. */
634 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_RESET 0x0
635 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC field value from a register. */
636 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_GET(value) (((value) & 0x00000100) >> 8)
637 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC register field value suitable for setting the register. */
638 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC_SET(value) (((value) << 8) & 0x00000100)
639 
640 /*
641  * Field : axi_ap
642  *
643  * Security bit configuration for transactions from axi_ap to noc_probes. When
644  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
645  * Non-Secure transactions are allowed.
646  *
647  * Field Access Macros:
648  *
649  */
650 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP register field. */
651 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_LSB 16
652 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP register field. */
653 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_MSB 16
654 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP register field. */
655 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_WIDTH 1
656 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP register field value. */
657 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_SET_MSK 0x00010000
658 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP register field value. */
659 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_CLR_MSK 0xfffeffff
660 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP register field. */
661 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_RESET 0x0
662 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP field value from a register. */
663 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_GET(value) (((value) & 0x00010000) >> 16)
664 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP register field value suitable for setting the register. */
665 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP_SET(value) (((value) << 16) & 0x00010000)
666 
667 #ifndef __ASSEMBLY__
668 /*
669  * WARNING: The C register and register group struct declarations are provided for
670  * convenience and illustrative purposes. They should, however, be used with
671  * caution as the C language standard provides no guarantees about the alignment or
672  * atomicity of device memory accesses. The recommended practice for coding device
673  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
674  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
675  * alt_write_dword() functions for 64 bit registers.
676  *
677  * The struct declaration for register ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES.
678  */
679 struct ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_s
680 {
681  volatile uint32_t mpu : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_MPU */
682  uint32_t : 7; /* *UNDEFINED* */
683  volatile uint32_t fpga2soc : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_FPGA2SOC */
684  uint32_t : 7; /* *UNDEFINED* */
685  volatile uint32_t axi_ap : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_AXI_AP */
686  uint32_t : 15; /* *UNDEFINED* */
687 };
688 
689 /* The typedef declaration for register ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES. */
690 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_s ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_t;
691 #endif /* __ASSEMBLY__ */
692 
693 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES register. */
694 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_RESET 0x00000000
695 /* The byte offset of the ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES register from the beginning of the component. */
696 #define ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_OFST 0x14
697 
698 /*
699  * Register : fpga2sdram_sidebandmgr
700  *
701  * Per-Master Security bit for fpga2sdram_sidebandmgr
702  *
703  * Register Layout
704  *
705  * Bits | Access | Reset | Description
706  * :--------|:-------|:------|:--------------------------------------------------------
707  * [0] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU
708  * [7:1] | ??? | 0x0 | *UNDEFINED*
709  * [8] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC
710  * [15:9] | ??? | 0x0 | *UNDEFINED*
711  * [16] | RW | 0x0 | ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP
712  * [31:17] | ??? | 0x0 | *UNDEFINED*
713  *
714  */
715 /*
716  * Field : mpu
717  *
718  * Security bit configuration for transactions from mpu to fpga2sdram_sidebandmgr.
719  * When cleared (0), only Secure transactions are allowed. When set (1), both
720  * Secure and Non-Secure transactions are allowed.
721  *
722  * Field Access Macros:
723  *
724  */
725 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU register field. */
726 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_LSB 0
727 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU register field. */
728 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_MSB 0
729 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU register field. */
730 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_WIDTH 1
731 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU register field value. */
732 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_SET_MSK 0x00000001
733 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU register field value. */
734 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_CLR_MSK 0xfffffffe
735 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU register field. */
736 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_RESET 0x0
737 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU field value from a register. */
738 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_GET(value) (((value) & 0x00000001) >> 0)
739 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU register field value suitable for setting the register. */
740 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU_SET(value) (((value) << 0) & 0x00000001)
741 
742 /*
743  * Field : fpga2soc
744  *
745  * Security bit configuration for transactions from fpga2soc to
746  * fpga2sdram_sidebandmgr. When cleared (0), only Secure transactions are allowed.
747  * When set (1), both Secure and Non-Secure transactions are allowed.
748  *
749  * Field Access Macros:
750  *
751  */
752 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC register field. */
753 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_LSB 8
754 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC register field. */
755 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_MSB 8
756 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC register field. */
757 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_WIDTH 1
758 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC register field value. */
759 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_SET_MSK 0x00000100
760 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC register field value. */
761 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_CLR_MSK 0xfffffeff
762 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC register field. */
763 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_RESET 0x0
764 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC field value from a register. */
765 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_GET(value) (((value) & 0x00000100) >> 8)
766 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC register field value suitable for setting the register. */
767 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC_SET(value) (((value) << 8) & 0x00000100)
768 
769 /*
770  * Field : axi_ap
771  *
772  * Security bit configuration for transactions from axi_ap to
773  * fpga2sdram_sidebandmgr. When cleared (0), only Secure transactions are allowed.
774  * When set (1), both Secure and Non-Secure transactions are allowed.
775  *
776  * Field Access Macros:
777  *
778  */
779 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP register field. */
780 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_LSB 16
781 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP register field. */
782 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_MSB 16
783 /* The width in bits of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP register field. */
784 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_WIDTH 1
785 /* The mask used to set the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP register field value. */
786 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_SET_MSK 0x00010000
787 /* The mask used to clear the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP register field value. */
788 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_CLR_MSK 0xfffeffff
789 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP register field. */
790 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_RESET 0x0
791 /* Extracts the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP field value from a register. */
792 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_GET(value) (((value) & 0x00010000) >> 16)
793 /* Produces a ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP register field value suitable for setting the register. */
794 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP_SET(value) (((value) << 16) & 0x00010000)
795 
796 #ifndef __ASSEMBLY__
797 /*
798  * WARNING: The C register and register group struct declarations are provided for
799  * convenience and illustrative purposes. They should, however, be used with
800  * caution as the C language standard provides no guarantees about the alignment or
801  * atomicity of device memory accesses. The recommended practice for coding device
802  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
803  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
804  * alt_write_dword() functions for 64 bit registers.
805  *
806  * The struct declaration for register ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR.
807  */
808 struct ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_s
809 {
810  volatile uint32_t mpu : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_MPU */
811  uint32_t : 7; /* *UNDEFINED* */
812  volatile uint32_t fpga2soc : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_FPGA2SOC */
813  uint32_t : 7; /* *UNDEFINED* */
814  volatile uint32_t axi_ap : 1; /* ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_AXI_AP */
815  uint32_t : 15; /* *UNDEFINED* */
816 };
817 
818 /* The typedef declaration for register ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR. */
819 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_s ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_t;
820 #endif /* __ASSEMBLY__ */
821 
822 /* The reset value of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR register. */
823 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_RESET 0x00000000
824 /* The byte offset of the ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR register from the beginning of the component. */
825 #define ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_OFST 0x18
826 
827 #ifndef __ASSEMBLY__
828 /*
829  * WARNING: The C register and register group struct declarations are provided for
830  * convenience and illustrative purposes. They should, however, be used with
831  * caution as the C language standard provides no guarantees about the alignment or
832  * atomicity of device memory accesses. The recommended practice for coding device
833  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
834  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
835  * alt_write_dword() functions for 64 bit registers.
836  *
837  * The struct declaration for register group ALT_SOC_NOC_FW_MPFE_CSR.
838  */
839 struct ALT_SOC_NOC_FW_MPFE_CSR_s
840 {
841  volatile ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER_t hmc_register; /* ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER */
842  volatile ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER_t hmc_adaptor_register; /* ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER */
843  volatile ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR_t noc_scheduler_csr; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR */
844  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
845  volatile ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS_t noc_qos; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS */
846  volatile ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES_t noc_probes; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES */
847  volatile ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR_t fpga2sdram_sidebandmgr; /* ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR */
848  volatile uint32_t _pad_0x1c_0x100[57]; /* *UNDEFINED* */
849 };
850 
851 /* The typedef declaration for register group ALT_SOC_NOC_FW_MPFE_CSR. */
852 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_s ALT_SOC_NOC_FW_MPFE_CSR_t;
853 /* The struct declaration for the raw register contents of register group ALT_SOC_NOC_FW_MPFE_CSR. */
854 struct ALT_SOC_NOC_FW_MPFE_CSR_raw_s
855 {
856  volatile uint32_t hmc_register; /* ALT_SOC_NOC_FW_MPFE_CSR_HMC_REGISTER */
857  volatile uint32_t hmc_adaptor_register; /* ALT_SOC_NOC_FW_MPFE_CSR_HMC_ADAPTOR_REGISTER */
858  volatile uint32_t noc_scheduler_csr; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_SCHEDULER_CSR */
859  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
860  volatile uint32_t noc_qos; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_QOS */
861  volatile uint32_t noc_probes; /* ALT_SOC_NOC_FW_MPFE_CSR_NOC_PROBES */
862  volatile uint32_t fpga2sdram_sidebandmgr; /* ALT_SOC_NOC_FW_MPFE_CSR_FPGA2SDRAM_SIDEBANDMGR */
863  volatile uint32_t _pad_0x1c_0x100[57]; /* *UNDEFINED* */
864 };
865 
866 /* The typedef declaration for the raw register contents of register group ALT_SOC_NOC_FW_MPFE_CSR. */
867 typedef struct ALT_SOC_NOC_FW_MPFE_CSR_raw_s ALT_SOC_NOC_FW_MPFE_CSR_raw_t;
868 #endif /* __ASSEMBLY__ */
869 
870 
871 #ifdef __cplusplus
872 }
873 #endif /* __cplusplus */
874 #endif /* __ALT_SOCAL_SOC_NOC_FW_MPFE_CSR_H__ */
875