Altera SoCAL  20.1
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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alt_sdr.h
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32 
33 /* Altera - ALT_SDR */
34 
35 #ifndef __ALTERA_ALT_SDR_H__
36 #define __ALTERA_ALT_SDR_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : SDRAM Controller - ALT_SDR
45  * SDRAM Controller
46  *
47  * Address map for the SDRAM Interface registers
48  *
49  */
50 /*
51  * Register Group : SDRAM Controller Module - ALT_SDR_CTL
52  * SDRAM Controller Module
53  *
54  * Address map for the SDRAM controller and multi-port front-end.
55  *
56  * All registers in this group reset to zero.
57  *
58  */
59 /*
60  * Register : Controller Configuration Register - ctrlcfg
61  *
62  * The Controller Configuration Register determines the behavior of the controller.
63  *
64  * Register Layout
65  *
66  * Bits | Access | Reset | Description
67  * :--------|:-------|:--------|:---------------------------
68  * [2:0] | RW | Unknown | DRAM Memory Type
69  * [7:3] | RW | Unknown | DRAM Memory Burst Length
70  * [9:8] | RW | Unknown | Address Interleaving Order
71  * [10] | RW | Unknown | ECC Enable
72  * [11] | RW | Unknown | ECC Auto-Correction Enable
73  * [12] | RW | Unknown | TBD
74  * [13] | RW | Unknown | Generate Single Bit Errors
75  * [14] | RW | Unknown | Generate Double Bit Errors
76  * [15] | RW | Unknown | Command Reorder Enable
77  * [21:16] | RW | Unknown | Starvation Limit
78  * [22] | RW | Unknown | DQS Tracking Enable
79  * [23] | RW | Unknown | No DM Pins Present
80  * [24] | RW | Unknown | Burst Interrupt Enable
81  * [25] | RW | Unknown | Burst Terminate Enable
82  * [31:26] | ??? | Unknown | *UNDEFINED*
83  *
84  */
85 /*
86  * Field : DRAM Memory Type - memtype
87  *
88  * Selects memory type. Program this field with one of the following binary values,
89  * "001" for DDR2 SDRAM, "010" for DDR3 SDRAM, "011"
90  * for LPDDR1 SDRAM or "100" for LPDDR2 SDRAM.
91  *
92  * Field Access Macros:
93  *
94  */
95 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */
96 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_LSB 0
97 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */
98 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_MSB 2
99 /* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field. */
100 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_WIDTH 3
101 /* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */
102 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET_MSK 0x00000007
103 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value. */
104 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_CLR_MSK 0xfffffff8
105 /* The reset value of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field is UNKNOWN. */
106 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_RESET 0x0
107 /* Extracts the ALT_SDR_CTL_CTLCFG_MEMTYPE field value from a register. */
108 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_GET(value) (((value) & 0x00000007) >> 0)
109 /* Produces a ALT_SDR_CTL_CTLCFG_MEMTYPE register field value suitable for setting the register. */
110 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET(value) (((value) << 0) & 0x00000007)
111 
112 /*
113  * Field : DRAM Memory Burst Length - membl
114  *
115  * Configures burst length as a static decimal value. Legal values are valid for
116  * JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, this
117  * should be programmed with 8 (binary &quot;01000&quot;), for DDR2 it can be
118  * either 4 or 8 depending on the exact DRAM chip. LPDDR2 can be programmed with
119  * 4, 8, or 16 and LPDDR can be programmed with 2, 4, or 8. You must also program
120  * the membl field in the staticcfg register.
121  *
122  * Field Access Macros:
123  *
124  */
125 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */
126 #define ALT_SDR_CTL_CTLCFG_MEMBL_LSB 3
127 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */
128 #define ALT_SDR_CTL_CTLCFG_MEMBL_MSB 7
129 /* The width in bits of the ALT_SDR_CTL_CTLCFG_MEMBL register field. */
130 #define ALT_SDR_CTL_CTLCFG_MEMBL_WIDTH 5
131 /* The mask used to set the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */
132 #define ALT_SDR_CTL_CTLCFG_MEMBL_SET_MSK 0x000000f8
133 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMBL register field value. */
134 #define ALT_SDR_CTL_CTLCFG_MEMBL_CLR_MSK 0xffffff07
135 /* The reset value of the ALT_SDR_CTL_CTLCFG_MEMBL register field is UNKNOWN. */
136 #define ALT_SDR_CTL_CTLCFG_MEMBL_RESET 0x0
137 /* Extracts the ALT_SDR_CTL_CTLCFG_MEMBL field value from a register. */
138 #define ALT_SDR_CTL_CTLCFG_MEMBL_GET(value) (((value) & 0x000000f8) >> 3)
139 /* Produces a ALT_SDR_CTL_CTLCFG_MEMBL register field value suitable for setting the register. */
140 #define ALT_SDR_CTL_CTLCFG_MEMBL_SET(value) (((value) << 3) & 0x000000f8)
141 
142 /*
143  * Field : Address Interleaving Order - addrorder
144  *
145  * Selects the order for address interleaving. Programming this field with
146  * different values gives different mappings between the AXI or Avalon-MM address
147  * and the SDRAM address. Program this field with the following binary values to
148  * select the ordering. &quot;00&quot; - chip, row, bank, column, &quot;01&quot; -
149  * chip, bank, row, column, &quot;10&quot;-row, chip, bank, column
150  *
151  * Field Access Macros:
152  *
153  */
154 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */
155 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_LSB 8
156 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */
157 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_MSB 9
158 /* The width in bits of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field. */
159 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_WIDTH 2
160 /* The mask used to set the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */
161 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET_MSK 0x00000300
162 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value. */
163 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_CLR_MSK 0xfffffcff
164 /* The reset value of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field is UNKNOWN. */
165 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_RESET 0x0
166 /* Extracts the ALT_SDR_CTL_CTLCFG_ADDRORDER field value from a register. */
167 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_GET(value) (((value) & 0x00000300) >> 8)
168 /* Produces a ALT_SDR_CTL_CTLCFG_ADDRORDER register field value suitable for setting the register. */
169 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET(value) (((value) << 8) & 0x00000300)
170 
171 /*
172  * Field : ECC Enable - eccen
173  *
174  * Enable the generation and checking of ECC. This bit must only be set if the
175  * memory connected to the SDRAM interface is 24 or 40 bits wide. If you set this,
176  * you must clear the useeccasdata field in the staticcfg register.
177  *
178  * Field Access Macros:
179  *
180  */
181 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */
182 #define ALT_SDR_CTL_CTLCFG_ECCEN_LSB 10
183 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */
184 #define ALT_SDR_CTL_CTLCFG_ECCEN_MSB 10
185 /* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCEN register field. */
186 #define ALT_SDR_CTL_CTLCFG_ECCEN_WIDTH 1
187 /* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */
188 #define ALT_SDR_CTL_CTLCFG_ECCEN_SET_MSK 0x00000400
189 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCEN register field value. */
190 #define ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK 0xfffffbff
191 /* The reset value of the ALT_SDR_CTL_CTLCFG_ECCEN register field is UNKNOWN. */
192 #define ALT_SDR_CTL_CTLCFG_ECCEN_RESET 0x0
193 /* Extracts the ALT_SDR_CTL_CTLCFG_ECCEN field value from a register. */
194 #define ALT_SDR_CTL_CTLCFG_ECCEN_GET(value) (((value) & 0x00000400) >> 10)
195 /* Produces a ALT_SDR_CTL_CTLCFG_ECCEN register field value suitable for setting the register. */
196 #define ALT_SDR_CTL_CTLCFG_ECCEN_SET(value) (((value) << 10) & 0x00000400)
197 
198 /*
199  * Field : ECC Auto-Correction Enable - ecccorren
200  *
201  * Enable auto correction of the read data returned when single bit error is
202  * detected.
203  *
204  * Field Access Macros:
205  *
206  */
207 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */
208 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_LSB 11
209 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */
210 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_MSB 11
211 /* The width in bits of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field. */
212 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_WIDTH 1
213 /* The mask used to set the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */
214 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET_MSK 0x00000800
215 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value. */
216 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_CLR_MSK 0xfffff7ff
217 /* The reset value of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field is UNKNOWN. */
218 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_RESET 0x0
219 /* Extracts the ALT_SDR_CTL_CTLCFG_ECCCORREN field value from a register. */
220 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_GET(value) (((value) & 0x00000800) >> 11)
221 /* Produces a ALT_SDR_CTL_CTLCFG_ECCCORREN register field value suitable for setting the register. */
222 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET(value) (((value) << 11) & 0x00000800)
223 
224 /*
225  * Field : TBD - cfg_enable_ecc_code_overwrites
226  *
227  * Set to a one to enable ECC overwrites. ECC overwrites occur when a correctable
228  * ECC error is seen and cause a new read/modify/write to be scheduled for that
229  * location to clear the ECC error.
230  *
231  * Field Access Macros:
232  *
233  */
234 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */
235 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_LSB 12
236 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */
237 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_MSB 12
238 /* The width in bits of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field. */
239 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_WIDTH 1
240 /* The mask used to set the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */
241 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET_MSK 0x00001000
242 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value. */
243 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_CLR_MSK 0xffffefff
244 /* The reset value of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field is UNKNOWN. */
245 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_RESET 0x0
246 /* Extracts the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS field value from a register. */
247 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_GET(value) (((value) & 0x00001000) >> 12)
248 /* Produces a ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value suitable for setting the register. */
249 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET(value) (((value) << 12) & 0x00001000)
250 
251 /*
252  * Field : Generate Single Bit Errors - gensbe
253  *
254  * Enable the deliberate insertion of single bit errors in data written to memory.
255  * This should only be used for testing purposes.
256  *
257  * Field Access Macros:
258  *
259  */
260 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */
261 #define ALT_SDR_CTL_CTLCFG_GENSBE_LSB 13
262 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */
263 #define ALT_SDR_CTL_CTLCFG_GENSBE_MSB 13
264 /* The width in bits of the ALT_SDR_CTL_CTLCFG_GENSBE register field. */
265 #define ALT_SDR_CTL_CTLCFG_GENSBE_WIDTH 1
266 /* The mask used to set the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */
267 #define ALT_SDR_CTL_CTLCFG_GENSBE_SET_MSK 0x00002000
268 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENSBE register field value. */
269 #define ALT_SDR_CTL_CTLCFG_GENSBE_CLR_MSK 0xffffdfff
270 /* The reset value of the ALT_SDR_CTL_CTLCFG_GENSBE register field is UNKNOWN. */
271 #define ALT_SDR_CTL_CTLCFG_GENSBE_RESET 0x0
272 /* Extracts the ALT_SDR_CTL_CTLCFG_GENSBE field value from a register. */
273 #define ALT_SDR_CTL_CTLCFG_GENSBE_GET(value) (((value) & 0x00002000) >> 13)
274 /* Produces a ALT_SDR_CTL_CTLCFG_GENSBE register field value suitable for setting the register. */
275 #define ALT_SDR_CTL_CTLCFG_GENSBE_SET(value) (((value) << 13) & 0x00002000)
276 
277 /*
278  * Field : Generate Double Bit Errors - gendbe
279  *
280  * Enable the deliberate insertion of double bit errors in data written to memory.
281  * This should only be used for testing purposes.
282  *
283  * Field Access Macros:
284  *
285  */
286 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */
287 #define ALT_SDR_CTL_CTLCFG_GENDBE_LSB 14
288 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */
289 #define ALT_SDR_CTL_CTLCFG_GENDBE_MSB 14
290 /* The width in bits of the ALT_SDR_CTL_CTLCFG_GENDBE register field. */
291 #define ALT_SDR_CTL_CTLCFG_GENDBE_WIDTH 1
292 /* The mask used to set the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */
293 #define ALT_SDR_CTL_CTLCFG_GENDBE_SET_MSK 0x00004000
294 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_GENDBE register field value. */
295 #define ALT_SDR_CTL_CTLCFG_GENDBE_CLR_MSK 0xffffbfff
296 /* The reset value of the ALT_SDR_CTL_CTLCFG_GENDBE register field is UNKNOWN. */
297 #define ALT_SDR_CTL_CTLCFG_GENDBE_RESET 0x0
298 /* Extracts the ALT_SDR_CTL_CTLCFG_GENDBE field value from a register. */
299 #define ALT_SDR_CTL_CTLCFG_GENDBE_GET(value) (((value) & 0x00004000) >> 14)
300 /* Produces a ALT_SDR_CTL_CTLCFG_GENDBE register field value suitable for setting the register. */
301 #define ALT_SDR_CTL_CTLCFG_GENDBE_SET(value) (((value) << 14) & 0x00004000)
302 
303 /*
304  * Field : Command Reorder Enable - reorderen
305  *
306  * This bit controls whether the controller can re-order operations to optimize
307  * SDRAM bandwidth. It should generally be set to a one.
308  *
309  * Field Access Macros:
310  *
311  */
312 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */
313 #define ALT_SDR_CTL_CTLCFG_REORDEREN_LSB 15
314 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */
315 #define ALT_SDR_CTL_CTLCFG_REORDEREN_MSB 15
316 /* The width in bits of the ALT_SDR_CTL_CTLCFG_REORDEREN register field. */
317 #define ALT_SDR_CTL_CTLCFG_REORDEREN_WIDTH 1
318 /* The mask used to set the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */
319 #define ALT_SDR_CTL_CTLCFG_REORDEREN_SET_MSK 0x00008000
320 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_REORDEREN register field value. */
321 #define ALT_SDR_CTL_CTLCFG_REORDEREN_CLR_MSK 0xffff7fff
322 /* The reset value of the ALT_SDR_CTL_CTLCFG_REORDEREN register field is UNKNOWN. */
323 #define ALT_SDR_CTL_CTLCFG_REORDEREN_RESET 0x0
324 /* Extracts the ALT_SDR_CTL_CTLCFG_REORDEREN field value from a register. */
325 #define ALT_SDR_CTL_CTLCFG_REORDEREN_GET(value) (((value) & 0x00008000) >> 15)
326 /* Produces a ALT_SDR_CTL_CTLCFG_REORDEREN register field value suitable for setting the register. */
327 #define ALT_SDR_CTL_CTLCFG_REORDEREN_SET(value) (((value) << 15) & 0x00008000)
328 
329 /*
330  * Field : Starvation Limit - starvelimit
331  *
332  * Specifies the number of DRAM burst transactions an individual transaction will
333  * allow to reorder ahead of it before its priority is raised in the memory
334  * controller.
335  *
336  * Field Access Macros:
337  *
338  */
339 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */
340 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_LSB 16
341 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */
342 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_MSB 21
343 /* The width in bits of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field. */
344 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_WIDTH 6
345 /* The mask used to set the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */
346 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET_MSK 0x003f0000
347 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value. */
348 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_CLR_MSK 0xffc0ffff
349 /* The reset value of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field is UNKNOWN. */
350 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_RESET 0x0
351 /* Extracts the ALT_SDR_CTL_CTLCFG_STARVELIMIT field value from a register. */
352 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_GET(value) (((value) & 0x003f0000) >> 16)
353 /* Produces a ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value suitable for setting the register. */
354 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET(value) (((value) << 16) & 0x003f0000)
355 
356 /*
357  * Field : DQS Tracking Enable - dqstrken
358  *
359  * Enables DQS tracking in the PHY.
360  *
361  * Field Access Macros:
362  *
363  */
364 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */
365 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_LSB 22
366 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */
367 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_MSB 22
368 /* The width in bits of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field. */
369 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_WIDTH 1
370 /* The mask used to set the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */
371 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET_MSK 0x00400000
372 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value. */
373 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_CLR_MSK 0xffbfffff
374 /* The reset value of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field is UNKNOWN. */
375 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_RESET 0x0
376 /* Extracts the ALT_SDR_CTL_CTLCFG_DQSTRKEN field value from a register. */
377 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_GET(value) (((value) & 0x00400000) >> 22)
378 /* Produces a ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value suitable for setting the register. */
379 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET(value) (((value) << 22) & 0x00400000)
380 
381 /*
382  * Field : No DM Pins Present - nodmpins
383  *
384  * Set to a one to enable DRAM operation if no DM pins are connected.
385  *
386  * Field Access Macros:
387  *
388  */
389 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */
390 #define ALT_SDR_CTL_CTLCFG_NODMPINS_LSB 23
391 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */
392 #define ALT_SDR_CTL_CTLCFG_NODMPINS_MSB 23
393 /* The width in bits of the ALT_SDR_CTL_CTLCFG_NODMPINS register field. */
394 #define ALT_SDR_CTL_CTLCFG_NODMPINS_WIDTH 1
395 /* The mask used to set the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */
396 #define ALT_SDR_CTL_CTLCFG_NODMPINS_SET_MSK 0x00800000
397 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_NODMPINS register field value. */
398 #define ALT_SDR_CTL_CTLCFG_NODMPINS_CLR_MSK 0xff7fffff
399 /* The reset value of the ALT_SDR_CTL_CTLCFG_NODMPINS register field is UNKNOWN. */
400 #define ALT_SDR_CTL_CTLCFG_NODMPINS_RESET 0x0
401 /* Extracts the ALT_SDR_CTL_CTLCFG_NODMPINS field value from a register. */
402 #define ALT_SDR_CTL_CTLCFG_NODMPINS_GET(value) (((value) & 0x00800000) >> 23)
403 /* Produces a ALT_SDR_CTL_CTLCFG_NODMPINS register field value suitable for setting the register. */
404 #define ALT_SDR_CTL_CTLCFG_NODMPINS_SET(value) (((value) << 23) & 0x00800000)
405 
406 /*
407  * Field : Burst Interrupt Enable - burstintren
408  *
409  * Set to a one to enable the controller to issue burst interrupt commands. This
410  * must only be set when the DRAM memory type is LPDDR2.
411  *
412  * Field Access Macros:
413  *
414  */
415 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */
416 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_LSB 24
417 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */
418 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_MSB 24
419 /* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field. */
420 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_WIDTH 1
421 /* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */
422 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET_MSK 0x01000000
423 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value. */
424 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_CLR_MSK 0xfeffffff
425 /* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field is UNKNOWN. */
426 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_RESET 0x0
427 /* Extracts the ALT_SDR_CTL_CTLCFG_BURSTINTREN field value from a register. */
428 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_GET(value) (((value) & 0x01000000) >> 24)
429 /* Produces a ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value suitable for setting the register. */
430 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET(value) (((value) << 24) & 0x01000000)
431 
432 /*
433  * Field : Burst Terminate Enable - bursttermen
434  *
435  * Set to a one to enable the controller to issue burst terminate commands. This
436  * must only be set when the DRAM memory type is LPDDR2.
437  *
438  * Field Access Macros:
439  *
440  */
441 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */
442 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_LSB 25
443 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */
444 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_MSB 25
445 /* The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field. */
446 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_WIDTH 1
447 /* The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */
448 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET_MSK 0x02000000
449 /* The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value. */
450 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_CLR_MSK 0xfdffffff
451 /* The reset value of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field is UNKNOWN. */
452 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_RESET 0x0
453 /* Extracts the ALT_SDR_CTL_CTLCFG_BURSTTERMEN field value from a register. */
454 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_GET(value) (((value) & 0x02000000) >> 25)
455 /* Produces a ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value suitable for setting the register. */
456 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET(value) (((value) << 25) & 0x02000000)
457 
458 #ifndef __ASSEMBLY__
459 /*
460  * WARNING: The C register and register group struct declarations are provided for
461  * convenience and illustrative purposes. They should, however, be used with
462  * caution as the C language standard provides no guarantees about the alignment or
463  * atomicity of device memory accesses. The recommended practice for writing
464  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
465  * alt_write_word() functions.
466  *
467  * The struct declaration for register ALT_SDR_CTL_CTLCFG.
468  */
469 struct ALT_SDR_CTL_CTLCFG_s
470 {
471  uint32_t memtype : 3; /* DRAM Memory Type */
472  uint32_t membl : 5; /* DRAM Memory Burst Length */
473  uint32_t addrorder : 2; /* Address Interleaving Order */
474  uint32_t eccen : 1; /* ECC Enable */
475  uint32_t ecccorren : 1; /* ECC Auto-Correction Enable */
476  uint32_t cfg_enable_ecc_code_overwrites : 1; /* TBD */
477  uint32_t gensbe : 1; /* Generate Single Bit Errors */
478  uint32_t gendbe : 1; /* Generate Double Bit Errors */
479  uint32_t reorderen : 1; /* Command Reorder Enable */
480  uint32_t starvelimit : 6; /* Starvation Limit */
481  uint32_t dqstrken : 1; /* DQS Tracking Enable */
482  uint32_t nodmpins : 1; /* No DM Pins Present */
483  uint32_t burstintren : 1; /* Burst Interrupt Enable */
484  uint32_t bursttermen : 1; /* Burst Terminate Enable */
485  uint32_t : 6; /* *UNDEFINED* */
486 };
487 
488 /* The typedef declaration for register ALT_SDR_CTL_CTLCFG. */
489 typedef volatile struct ALT_SDR_CTL_CTLCFG_s ALT_SDR_CTL_CTLCFG_t;
490 #endif /* __ASSEMBLY__ */
491 
492 /* The byte offset of the ALT_SDR_CTL_CTLCFG register from the beginning of the component. */
493 #define ALT_SDR_CTL_CTLCFG_OFST 0x0
494 
495 /*
496  * Register : DRAM Timings 1 Register - dramtiming1
497  *
498  * This register implements JEDEC standardized timing parameters. It should be
499  * programmed in clock cycles, for the value specified by the memory vendor.
500  *
501  * Register Layout
502  *
503  * Bits | Access | Reset | Description
504  * :--------|:-------|:--------|:---------------------------
505  * [3:0] | RW | Unknown | CAS Write Latency
506  * [8:4] | RW | Unknown | Additive Latency
507  * [13:9] | RW | Unknown | CAS Read Latency
508  * [17:14] | RW | Unknown | Activate to Activate Delay
509  * [23:18] | RW | Unknown | Four Activate Window Time
510  * [31:24] | RW | Unknown | Refresh Cycle Time
511  *
512  */
513 /*
514  * Field : CAS Write Latency - tcwl
515  *
516  * Memory write latency.
517  *
518  * Field Access Macros:
519  *
520  */
521 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */
522 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_LSB 0
523 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */
524 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_MSB 3
525 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field. */
526 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_WIDTH 4
527 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */
528 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET_MSK 0x0000000f
529 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value. */
530 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_CLR_MSK 0xfffffff0
531 /* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field is UNKNOWN. */
532 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_RESET 0x0
533 /* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCWL field value from a register. */
534 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_GET(value) (((value) & 0x0000000f) >> 0)
535 /* Produces a ALT_SDR_CTL_DRAMTIMING1_TCWL register field value suitable for setting the register. */
536 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET(value) (((value) << 0) & 0x0000000f)
537 
538 /*
539  * Field : Additive Latency - tal
540  *
541  * Memory additive latency.
542  *
543  * Field Access Macros:
544  *
545  */
546 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */
547 #define ALT_SDR_CTL_DRAMTIMING1_TAL_LSB 4
548 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */
549 #define ALT_SDR_CTL_DRAMTIMING1_TAL_MSB 8
550 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TAL register field. */
551 #define ALT_SDR_CTL_DRAMTIMING1_TAL_WIDTH 5
552 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */
553 #define ALT_SDR_CTL_DRAMTIMING1_TAL_SET_MSK 0x000001f0
554 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TAL register field value. */
555 #define ALT_SDR_CTL_DRAMTIMING1_TAL_CLR_MSK 0xfffffe0f
556 /* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TAL register field is UNKNOWN. */
557 #define ALT_SDR_CTL_DRAMTIMING1_TAL_RESET 0x0
558 /* Extracts the ALT_SDR_CTL_DRAMTIMING1_TAL field value from a register. */
559 #define ALT_SDR_CTL_DRAMTIMING1_TAL_GET(value) (((value) & 0x000001f0) >> 4)
560 /* Produces a ALT_SDR_CTL_DRAMTIMING1_TAL register field value suitable for setting the register. */
561 #define ALT_SDR_CTL_DRAMTIMING1_TAL_SET(value) (((value) << 4) & 0x000001f0)
562 
563 /*
564  * Field : CAS Read Latency - tcl
565  *
566  * Memory read latency.
567  *
568  * Field Access Macros:
569  *
570  */
571 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */
572 #define ALT_SDR_CTL_DRAMTIMING1_TCL_LSB 9
573 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */
574 #define ALT_SDR_CTL_DRAMTIMING1_TCL_MSB 13
575 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCL register field. */
576 #define ALT_SDR_CTL_DRAMTIMING1_TCL_WIDTH 5
577 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */
578 #define ALT_SDR_CTL_DRAMTIMING1_TCL_SET_MSK 0x00003e00
579 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCL register field value. */
580 #define ALT_SDR_CTL_DRAMTIMING1_TCL_CLR_MSK 0xffffc1ff
581 /* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCL register field is UNKNOWN. */
582 #define ALT_SDR_CTL_DRAMTIMING1_TCL_RESET 0x0
583 /* Extracts the ALT_SDR_CTL_DRAMTIMING1_TCL field value from a register. */
584 #define ALT_SDR_CTL_DRAMTIMING1_TCL_GET(value) (((value) & 0x00003e00) >> 9)
585 /* Produces a ALT_SDR_CTL_DRAMTIMING1_TCL register field value suitable for setting the register. */
586 #define ALT_SDR_CTL_DRAMTIMING1_TCL_SET(value) (((value) << 9) & 0x00003e00)
587 
588 /*
589  * Field : Activate to Activate Delay - trrd
590  *
591  * The activate to activate, different banks timing parameter.
592  *
593  * Field Access Macros:
594  *
595  */
596 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */
597 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_LSB 14
598 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */
599 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_MSB 17
600 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field. */
601 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_WIDTH 4
602 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */
603 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET_MSK 0x0003c000
604 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value. */
605 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_CLR_MSK 0xfffc3fff
606 /* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field is UNKNOWN. */
607 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_RESET 0x0
608 /* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRRD field value from a register. */
609 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_GET(value) (((value) & 0x0003c000) >> 14)
610 /* Produces a ALT_SDR_CTL_DRAMTIMING1_TRRD register field value suitable for setting the register. */
611 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET(value) (((value) << 14) & 0x0003c000)
612 
613 /*
614  * Field : Four Activate Window Time - tfaw
615  *
616  * The four-activate window timing parameter.
617  *
618  * Field Access Macros:
619  *
620  */
621 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */
622 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_LSB 18
623 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */
624 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_MSB 23
625 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field. */
626 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_WIDTH 6
627 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */
628 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET_MSK 0x00fc0000
629 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value. */
630 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_CLR_MSK 0xff03ffff
631 /* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field is UNKNOWN. */
632 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_RESET 0x0
633 /* Extracts the ALT_SDR_CTL_DRAMTIMING1_TFAW field value from a register. */
634 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_GET(value) (((value) & 0x00fc0000) >> 18)
635 /* Produces a ALT_SDR_CTL_DRAMTIMING1_TFAW register field value suitable for setting the register. */
636 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET(value) (((value) << 18) & 0x00fc0000)
637 
638 /*
639  * Field : Refresh Cycle Time - trfc
640  *
641  * The refresh cycle timing parameter.
642  *
643  * Field Access Macros:
644  *
645  */
646 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */
647 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_LSB 24
648 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */
649 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_MSB 31
650 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field. */
651 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_WIDTH 8
652 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */
653 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET_MSK 0xff000000
654 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value. */
655 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_CLR_MSK 0x00ffffff
656 /* The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field is UNKNOWN. */
657 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_RESET 0x0
658 /* Extracts the ALT_SDR_CTL_DRAMTIMING1_TRFC field value from a register. */
659 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_GET(value) (((value) & 0xff000000) >> 24)
660 /* Produces a ALT_SDR_CTL_DRAMTIMING1_TRFC register field value suitable for setting the register. */
661 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET(value) (((value) << 24) & 0xff000000)
662 
663 #ifndef __ASSEMBLY__
664 /*
665  * WARNING: The C register and register group struct declarations are provided for
666  * convenience and illustrative purposes. They should, however, be used with
667  * caution as the C language standard provides no guarantees about the alignment or
668  * atomicity of device memory accesses. The recommended practice for writing
669  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
670  * alt_write_word() functions.
671  *
672  * The struct declaration for register ALT_SDR_CTL_DRAMTIMING1.
673  */
674 struct ALT_SDR_CTL_DRAMTIMING1_s
675 {
676  uint32_t tcwl : 4; /* CAS Write Latency */
677  uint32_t tal : 5; /* Additive Latency */
678  uint32_t tcl : 5; /* CAS Read Latency */
679  uint32_t trrd : 4; /* Activate to Activate Delay */
680  uint32_t tfaw : 6; /* Four Activate Window Time */
681  uint32_t trfc : 8; /* Refresh Cycle Time */
682 };
683 
684 /* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING1. */
685 typedef volatile struct ALT_SDR_CTL_DRAMTIMING1_s ALT_SDR_CTL_DRAMTIMING1_t;
686 #endif /* __ASSEMBLY__ */
687 
688 /* The byte offset of the ALT_SDR_CTL_DRAMTIMING1 register from the beginning of the component. */
689 #define ALT_SDR_CTL_DRAMTIMING1_OFST 0x4
690 
691 /*
692  * Register : DRAM Timings 2 Register - dramtiming2
693  *
694  * This register implements JEDEC standardized timing parameters. It should be
695  * programmed in clock cycles, for the value specified by the memory vendor.
696  *
697  * Register Layout
698  *
699  * Bits | Access | Reset | Description
700  * :--------|:-------|:--------|:--------------------------------
701  * [12:0] | RW | Unknown | Refresh Interval
702  * [16:13] | RW | Unknown | Activate to Read or Write Delay
703  * [20:17] | RW | Unknown | Row Precharge Time
704  * [24:21] | RW | Unknown | Write Recovery Time
705  * [28:25] | RW | Unknown | Write to Read Time
706  * [31:29] | ??? | 0x0 | *UNDEFINED*
707  *
708  */
709 /*
710  * Field : Refresh Interval - trefi
711  *
712  * The refresh interval timing parameter.
713  *
714  * Field Access Macros:
715  *
716  */
717 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */
718 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_LSB 0
719 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */
720 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_MSB 12
721 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field. */
722 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_WIDTH 13
723 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */
724 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET_MSK 0x00001fff
725 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value. */
726 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_CLR_MSK 0xffffe000
727 /* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field is UNKNOWN. */
728 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_RESET 0x0
729 /* Extracts the ALT_SDR_CTL_DRAMTIMING2_TREFI field value from a register. */
730 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_GET(value) (((value) & 0x00001fff) >> 0)
731 /* Produces a ALT_SDR_CTL_DRAMTIMING2_TREFI register field value suitable for setting the register. */
732 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET(value) (((value) << 0) & 0x00001fff)
733 
734 /*
735  * Field : Activate to Read or Write Delay - trcd
736  *
737  * The activate to read/write timing parameter.
738  *
739  * Field Access Macros:
740  *
741  */
742 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */
743 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_LSB 13
744 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */
745 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_MSB 16
746 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field. */
747 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_WIDTH 4
748 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */
749 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET_MSK 0x0001e000
750 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value. */
751 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_CLR_MSK 0xfffe1fff
752 /* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field is UNKNOWN. */
753 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_RESET 0x0
754 /* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRCD field value from a register. */
755 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_GET(value) (((value) & 0x0001e000) >> 13)
756 /* Produces a ALT_SDR_CTL_DRAMTIMING2_TRCD register field value suitable for setting the register. */
757 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET(value) (((value) << 13) & 0x0001e000)
758 
759 /*
760  * Field : Row Precharge Time - trp
761  *
762  * The precharge to activate timing parameter.
763  *
764  * Field Access Macros:
765  *
766  */
767 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */
768 #define ALT_SDR_CTL_DRAMTIMING2_TRP_LSB 17
769 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */
770 #define ALT_SDR_CTL_DRAMTIMING2_TRP_MSB 20
771 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRP register field. */
772 #define ALT_SDR_CTL_DRAMTIMING2_TRP_WIDTH 4
773 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */
774 #define ALT_SDR_CTL_DRAMTIMING2_TRP_SET_MSK 0x001e0000
775 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRP register field value. */
776 #define ALT_SDR_CTL_DRAMTIMING2_TRP_CLR_MSK 0xffe1ffff
777 /* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRP register field is UNKNOWN. */
778 #define ALT_SDR_CTL_DRAMTIMING2_TRP_RESET 0x0
779 /* Extracts the ALT_SDR_CTL_DRAMTIMING2_TRP field value from a register. */
780 #define ALT_SDR_CTL_DRAMTIMING2_TRP_GET(value) (((value) & 0x001e0000) >> 17)
781 /* Produces a ALT_SDR_CTL_DRAMTIMING2_TRP register field value suitable for setting the register. */
782 #define ALT_SDR_CTL_DRAMTIMING2_TRP_SET(value) (((value) << 17) & 0x001e0000)
783 
784 /*
785  * Field : Write Recovery Time - twr
786  *
787  * The write recovery timing.
788  *
789  * Field Access Macros:
790  *
791  */
792 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */
793 #define ALT_SDR_CTL_DRAMTIMING2_TWR_LSB 21
794 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */
795 #define ALT_SDR_CTL_DRAMTIMING2_TWR_MSB 24
796 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWR register field. */
797 #define ALT_SDR_CTL_DRAMTIMING2_TWR_WIDTH 4
798 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */
799 #define ALT_SDR_CTL_DRAMTIMING2_TWR_SET_MSK 0x01e00000
800 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWR register field value. */
801 #define ALT_SDR_CTL_DRAMTIMING2_TWR_CLR_MSK 0xfe1fffff
802 /* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWR register field is UNKNOWN. */
803 #define ALT_SDR_CTL_DRAMTIMING2_TWR_RESET 0x0
804 /* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWR field value from a register. */
805 #define ALT_SDR_CTL_DRAMTIMING2_TWR_GET(value) (((value) & 0x01e00000) >> 21)
806 /* Produces a ALT_SDR_CTL_DRAMTIMING2_TWR register field value suitable for setting the register. */
807 #define ALT_SDR_CTL_DRAMTIMING2_TWR_SET(value) (((value) << 21) & 0x01e00000)
808 
809 /*
810  * Field : Write to Read Time - twtr
811  *
812  * The write to read timing parameter.
813  *
814  * Field Access Macros:
815  *
816  */
817 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */
818 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_LSB 25
819 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */
820 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_MSB 28
821 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field. */
822 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_WIDTH 4
823 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */
824 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET_MSK 0x1e000000
825 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value. */
826 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_CLR_MSK 0xe1ffffff
827 /* The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field is UNKNOWN. */
828 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_RESET 0x0
829 /* Extracts the ALT_SDR_CTL_DRAMTIMING2_TWTR field value from a register. */
830 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_GET(value) (((value) & 0x1e000000) >> 25)
831 /* Produces a ALT_SDR_CTL_DRAMTIMING2_TWTR register field value suitable for setting the register. */
832 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET(value) (((value) << 25) & 0x1e000000)
833 
834 #ifndef __ASSEMBLY__
835 /*
836  * WARNING: The C register and register group struct declarations are provided for
837  * convenience and illustrative purposes. They should, however, be used with
838  * caution as the C language standard provides no guarantees about the alignment or
839  * atomicity of device memory accesses. The recommended practice for writing
840  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
841  * alt_write_word() functions.
842  *
843  * The struct declaration for register ALT_SDR_CTL_DRAMTIMING2.
844  */
845 struct ALT_SDR_CTL_DRAMTIMING2_s
846 {
847  uint32_t trefi : 13; /* Refresh Interval */
848  uint32_t trcd : 4; /* Activate to Read or Write Delay */
849  uint32_t trp : 4; /* Row Precharge Time */
850  uint32_t twr : 4; /* Write Recovery Time */
851  uint32_t twtr : 4; /* Write to Read Time */
852  uint32_t : 3; /* *UNDEFINED* */
853 };
854 
855 /* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING2. */
856 typedef volatile struct ALT_SDR_CTL_DRAMTIMING2_s ALT_SDR_CTL_DRAMTIMING2_t;
857 #endif /* __ASSEMBLY__ */
858 
859 /* The byte offset of the ALT_SDR_CTL_DRAMTIMING2 register from the beginning of the component. */
860 #define ALT_SDR_CTL_DRAMTIMING2_OFST 0x8
861 
862 /*
863  * Register : DRAM Timings 3 Register - dramtiming3
864  *
865  * This register implements JEDEC standardized timing parameters. It should be
866  * programmed in clock cycles, for the value specified by the memory vendor.
867  *
868  * Register Layout
869  *
870  * Bits | Access | Reset | Description
871  * :--------|:-------|:--------|:--------------------------------
872  * [3:0] | RW | Unknown | Read to Precharge Time
873  * [8:4] | RW | Unknown | Activate to Precharge Time
874  * [14:9] | RW | Unknown | Row Cycle Time
875  * [18:15] | RW | Unknown | Mode Register Programming Delay
876  * [22:19] | RW | Unknown | CAS to CAS Delay
877  * [31:23] | ??? | 0x0 | *UNDEFINED*
878  *
879  */
880 /*
881  * Field : Read to Precharge Time - trtp
882  *
883  * The read to precharge timing parameter.
884  *
885  * Field Access Macros:
886  *
887  */
888 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */
889 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_LSB 0
890 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */
891 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_MSB 3
892 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field. */
893 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_WIDTH 4
894 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */
895 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET_MSK 0x0000000f
896 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value. */
897 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_CLR_MSK 0xfffffff0
898 /* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field is UNKNOWN. */
899 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_RESET 0x0
900 /* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRTP field value from a register. */
901 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_GET(value) (((value) & 0x0000000f) >> 0)
902 /* Produces a ALT_SDR_CTL_DRAMTIMING3_TRTP register field value suitable for setting the register. */
903 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET(value) (((value) << 0) & 0x0000000f)
904 
905 /*
906  * Field : Activate to Precharge Time - tras
907  *
908  * The activate to precharge timing parameter.
909  *
910  * Field Access Macros:
911  *
912  */
913 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */
914 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_LSB 4
915 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */
916 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_MSB 8
917 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field. */
918 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_WIDTH 5
919 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */
920 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET_MSK 0x000001f0
921 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value. */
922 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_CLR_MSK 0xfffffe0f
923 /* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field is UNKNOWN. */
924 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_RESET 0x0
925 /* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRAS field value from a register. */
926 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_GET(value) (((value) & 0x000001f0) >> 4)
927 /* Produces a ALT_SDR_CTL_DRAMTIMING3_TRAS register field value suitable for setting the register. */
928 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET(value) (((value) << 4) & 0x000001f0)
929 
930 /*
931  * Field : Row Cycle Time - trc
932  *
933  * The activate to activate timing parameter.
934  *
935  * Field Access Macros:
936  *
937  */
938 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */
939 #define ALT_SDR_CTL_DRAMTIMING3_TRC_LSB 9
940 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */
941 #define ALT_SDR_CTL_DRAMTIMING3_TRC_MSB 14
942 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRC register field. */
943 #define ALT_SDR_CTL_DRAMTIMING3_TRC_WIDTH 6
944 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */
945 #define ALT_SDR_CTL_DRAMTIMING3_TRC_SET_MSK 0x00007e00
946 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRC register field value. */
947 #define ALT_SDR_CTL_DRAMTIMING3_TRC_CLR_MSK 0xffff81ff
948 /* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRC register field is UNKNOWN. */
949 #define ALT_SDR_CTL_DRAMTIMING3_TRC_RESET 0x0
950 /* Extracts the ALT_SDR_CTL_DRAMTIMING3_TRC field value from a register. */
951 #define ALT_SDR_CTL_DRAMTIMING3_TRC_GET(value) (((value) & 0x00007e00) >> 9)
952 /* Produces a ALT_SDR_CTL_DRAMTIMING3_TRC register field value suitable for setting the register. */
953 #define ALT_SDR_CTL_DRAMTIMING3_TRC_SET(value) (((value) << 9) & 0x00007e00)
954 
955 /*
956  * Field : Mode Register Programming Delay - tmrd
957  *
958  * Mode register timing parameter.
959  *
960  * Field Access Macros:
961  *
962  */
963 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */
964 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_LSB 15
965 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */
966 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_MSB 18
967 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field. */
968 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_WIDTH 4
969 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */
970 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET_MSK 0x00078000
971 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value. */
972 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_CLR_MSK 0xfff87fff
973 /* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field is UNKNOWN. */
974 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_RESET 0x0
975 /* Extracts the ALT_SDR_CTL_DRAMTIMING3_TMRD field value from a register. */
976 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_GET(value) (((value) & 0x00078000) >> 15)
977 /* Produces a ALT_SDR_CTL_DRAMTIMING3_TMRD register field value suitable for setting the register. */
978 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET(value) (((value) << 15) & 0x00078000)
979 
980 /*
981  * Field : CAS to CAS Delay - tccd
982  *
983  * The CAS to CAS delay time.
984  *
985  * Field Access Macros:
986  *
987  */
988 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */
989 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_LSB 19
990 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */
991 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_MSB 22
992 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field. */
993 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_WIDTH 4
994 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */
995 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET_MSK 0x00780000
996 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value. */
997 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_CLR_MSK 0xff87ffff
998 /* The reset value of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field is UNKNOWN. */
999 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_RESET 0x0
1000 /* Extracts the ALT_SDR_CTL_DRAMTIMING3_TCCD field value from a register. */
1001 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_GET(value) (((value) & 0x00780000) >> 19)
1002 /* Produces a ALT_SDR_CTL_DRAMTIMING3_TCCD register field value suitable for setting the register. */
1003 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET(value) (((value) << 19) & 0x00780000)
1004 
1005 #ifndef __ASSEMBLY__
1006 /*
1007  * WARNING: The C register and register group struct declarations are provided for
1008  * convenience and illustrative purposes. They should, however, be used with
1009  * caution as the C language standard provides no guarantees about the alignment or
1010  * atomicity of device memory accesses. The recommended practice for writing
1011  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1012  * alt_write_word() functions.
1013  *
1014  * The struct declaration for register ALT_SDR_CTL_DRAMTIMING3.
1015  */
1016 struct ALT_SDR_CTL_DRAMTIMING3_s
1017 {
1018  uint32_t trtp : 4; /* Read to Precharge Time */
1019  uint32_t tras : 5; /* Activate to Precharge Time */
1020  uint32_t trc : 6; /* Row Cycle Time */
1021  uint32_t tmrd : 4; /* Mode Register Programming Delay */
1022  uint32_t tccd : 4; /* CAS to CAS Delay */
1023  uint32_t : 9; /* *UNDEFINED* */
1024 };
1025 
1026 /* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING3. */
1027 typedef volatile struct ALT_SDR_CTL_DRAMTIMING3_s ALT_SDR_CTL_DRAMTIMING3_t;
1028 #endif /* __ASSEMBLY__ */
1029 
1030 /* The byte offset of the ALT_SDR_CTL_DRAMTIMING3 register from the beginning of the component. */
1031 #define ALT_SDR_CTL_DRAMTIMING3_OFST 0xc
1032 
1033 /*
1034  * Register : DRAM Timings 4 Register - dramtiming4
1035  *
1036  * This register implements JEDEC standardized timing parameters. It should be
1037  * programmed in clock cycles, for the value specified by the memory vendor.
1038  *
1039  * Register Layout
1040  *
1041  * Bits | Access | Reset | Description
1042  * :--------|:-------|:--------|:-------------------------------
1043  * [9:0] | RW | Unknown | Self-refresh Exit
1044  * [19:10] | RW | Unknown | Power Down Exit
1045  * [23:20] | RW | Unknown | Minimum Low Power State Cycles
1046  * [31:24] | ??? | 0x0 | *UNDEFINED*
1047  *
1048  */
1049 /*
1050  * Field : Self-refresh Exit - selfrfshexit
1051  *
1052  * The self refresh exit cycles, tXS.
1053  *
1054  * Field Access Macros:
1055  *
1056  */
1057 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */
1058 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_LSB 0
1059 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */
1060 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_MSB 9
1061 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field. */
1062 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_WIDTH 10
1063 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */
1064 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET_MSK 0x000003ff
1065 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value. */
1066 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_CLR_MSK 0xfffffc00
1067 /* The reset value of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field is UNKNOWN. */
1068 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_RESET 0x0
1069 /* Extracts the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT field value from a register. */
1070 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_GET(value) (((value) & 0x000003ff) >> 0)
1071 /* Produces a ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value suitable for setting the register. */
1072 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET(value) (((value) << 0) & 0x000003ff)
1073 
1074 /*
1075  * Field : Power Down Exit - pwrdownexit
1076  *
1077  * The power down exit cycles, tXPDLL.
1078  *
1079  * Field Access Macros:
1080  *
1081  */
1082 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */
1083 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_LSB 10
1084 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */
1085 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_MSB 19
1086 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field. */
1087 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_WIDTH 10
1088 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */
1089 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET_MSK 0x000ffc00
1090 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value. */
1091 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_CLR_MSK 0xfff003ff
1092 /* The reset value of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field is UNKNOWN. */
1093 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_RESET 0x0
1094 /* Extracts the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT field value from a register. */
1095 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_GET(value) (((value) & 0x000ffc00) >> 10)
1096 /* Produces a ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value suitable for setting the register. */
1097 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET(value) (((value) << 10) & 0x000ffc00)
1098 
1099 /*
1100  * Field : Minimum Low Power State Cycles - minpwrsavecycles
1101  *
1102  * The minimum number of cycles to stay in a low power state. This applies to both
1103  * power down and self-refresh and should be set to the greater of tPD and tCKESR.
1104  *
1105  * Field Access Macros:
1106  *
1107  */
1108 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */
1109 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
1110 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */
1111 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_MSB 23
1112 /* The width in bits of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field. */
1113 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_WIDTH 4
1114 /* The mask used to set the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */
1115 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET_MSK 0x00f00000
1116 /* The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value. */
1117 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_CLR_MSK 0xff0fffff
1118 /* The reset value of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field is UNKNOWN. */
1119 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_RESET 0x0
1120 /* Extracts the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES field value from a register. */
1121 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_GET(value) (((value) & 0x00f00000) >> 20)
1122 /* Produces a ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value suitable for setting the register. */
1123 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET(value) (((value) << 20) & 0x00f00000)
1124 
1125 #ifndef __ASSEMBLY__
1126 /*
1127  * WARNING: The C register and register group struct declarations are provided for
1128  * convenience and illustrative purposes. They should, however, be used with
1129  * caution as the C language standard provides no guarantees about the alignment or
1130  * atomicity of device memory accesses. The recommended practice for writing
1131  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1132  * alt_write_word() functions.
1133  *
1134  * The struct declaration for register ALT_SDR_CTL_DRAMTIMING4.
1135  */
1136 struct ALT_SDR_CTL_DRAMTIMING4_s
1137 {
1138  uint32_t selfrfshexit : 10; /* Self-refresh Exit */
1139  uint32_t pwrdownexit : 10; /* Power Down Exit */
1140  uint32_t minpwrsavecycles : 4; /* Minimum Low Power State Cycles */
1141  uint32_t : 8; /* *UNDEFINED* */
1142 };
1143 
1144 /* The typedef declaration for register ALT_SDR_CTL_DRAMTIMING4. */
1145 typedef volatile struct ALT_SDR_CTL_DRAMTIMING4_s ALT_SDR_CTL_DRAMTIMING4_t;
1146 #endif /* __ASSEMBLY__ */
1147 
1148 /* The byte offset of the ALT_SDR_CTL_DRAMTIMING4 register from the beginning of the component. */
1149 #define ALT_SDR_CTL_DRAMTIMING4_OFST 0x10
1150 
1151 /*
1152  * Register : Lower Power Timing Register - lowpwrtiming
1153  *
1154  * This register controls the behavior of the low power logic in the controller.
1155  *
1156  * Register Layout
1157  *
1158  * Bits | Access | Reset | Description
1159  * :--------|:-------|:--------|:---------------------------
1160  * [15:0] | RW | Unknown | Auto-power Down Cycles
1161  * [19:16] | RW | Unknown | Clock Disable Delay Cycles
1162  * [31:20] | ??? | 0x0 | *UNDEFINED*
1163  *
1164  */
1165 /*
1166  * Field : Auto-power Down Cycles - autopdcycles
1167  *
1168  * The number of idle clock cycles after which the controller should place the
1169  * memory into power-down mode.
1170  *
1171  * Field Access Macros:
1172  *
1173  */
1174 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */
1175 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
1176 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */
1177 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_MSB 15
1178 /* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field. */
1179 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_WIDTH 16
1180 /* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */
1181 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET_MSK 0x0000ffff
1182 /* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value. */
1183 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_CLR_MSK 0xffff0000
1184 /* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field is UNKNOWN. */
1185 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_RESET 0x0
1186 /* Extracts the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES field value from a register. */
1187 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_GET(value) (((value) & 0x0000ffff) >> 0)
1188 /* Produces a ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value suitable for setting the register. */
1189 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET(value) (((value) << 0) & 0x0000ffff)
1190 
1191 /*
1192  * Field : Clock Disable Delay Cycles - clkdisablecycles
1193  *
1194  * Set to a the number of clocks after the execution of an self-refresh to stop the
1195  * clock. This register is generally set based on PHY design latency and should
1196  * generally not be changed.
1197  *
1198  * Field Access Macros:
1199  *
1200  */
1201 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */
1202 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_LSB 16
1203 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */
1204 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_MSB 19
1205 /* The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field. */
1206 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_WIDTH 4
1207 /* The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */
1208 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET_MSK 0x000f0000
1209 /* The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value. */
1210 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_CLR_MSK 0xfff0ffff
1211 /* The reset value of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field is UNKNOWN. */
1212 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_RESET 0x0
1213 /* Extracts the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES field value from a register. */
1214 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_GET(value) (((value) & 0x000f0000) >> 16)
1215 /* Produces a ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value suitable for setting the register. */
1216 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET(value) (((value) << 16) & 0x000f0000)
1217 
1218 #ifndef __ASSEMBLY__
1219 /*
1220  * WARNING: The C register and register group struct declarations are provided for
1221  * convenience and illustrative purposes. They should, however, be used with
1222  * caution as the C language standard provides no guarantees about the alignment or
1223  * atomicity of device memory accesses. The recommended practice for writing
1224  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1225  * alt_write_word() functions.
1226  *
1227  * The struct declaration for register ALT_SDR_CTL_LOWPWRTIMING.
1228  */
1229 struct ALT_SDR_CTL_LOWPWRTIMING_s
1230 {
1231  uint32_t autopdcycles : 16; /* Auto-power Down Cycles */
1232  uint32_t clkdisablecycles : 4; /* Clock Disable Delay Cycles */
1233  uint32_t : 12; /* *UNDEFINED* */
1234 };
1235 
1236 /* The typedef declaration for register ALT_SDR_CTL_LOWPWRTIMING. */
1237 typedef volatile struct ALT_SDR_CTL_LOWPWRTIMING_s ALT_SDR_CTL_LOWPWRTIMING_t;
1238 #endif /* __ASSEMBLY__ */
1239 
1240 /* The byte offset of the ALT_SDR_CTL_LOWPWRTIMING register from the beginning of the component. */
1241 #define ALT_SDR_CTL_LOWPWRTIMING_OFST 0x14
1242 
1243 /*
1244  * Register : ODT Control Register - dramodt
1245  *
1246  * This register controls which ODT pin is asserted during reads or writes. Bits
1247  * [1:0] control which ODT pin is asserted during to accesses to chip select 0,
1248  * bits [3:2] which ODT pin is asserted during accesses to chip select 1. For
1249  * example, a value of &quot;1001&quot; will cause ODT[0] to be asserted for
1250  * accesses to CS[0], and ODT[1] to be asserted for access to CS[1] pin. Set this
1251  * to &quot;0001&quot; if there is only one chip select available.
1252  *
1253  * Register Layout
1254  *
1255  * Bits | Access | Reset | Description
1256  * :-------|:-------|:--------|:------------------
1257  * [3:0] | RW | Unknown | Write ODT Control
1258  * [7:4] | RW | Unknown | Read ODT Control
1259  * [31:8] | ??? | 0x0 | *UNDEFINED*
1260  *
1261  */
1262 /*
1263  * Field : Write ODT Control - cfg_write_odt_chip
1264  *
1265  * This register controls which ODT pin is asserted during writes.
1266  *
1267  * Field Access Macros:
1268  *
1269  */
1270 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */
1271 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_LSB 0
1272 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */
1273 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_MSB 3
1274 /* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field. */
1275 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_WIDTH 4
1276 /* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */
1277 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET_MSK 0x0000000f
1278 /* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value. */
1279 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_CLR_MSK 0xfffffff0
1280 /* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field is UNKNOWN. */
1281 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_RESET 0x0
1282 /* Extracts the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP field value from a register. */
1283 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_GET(value) (((value) & 0x0000000f) >> 0)
1284 /* Produces a ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value suitable for setting the register. */
1285 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET(value) (((value) << 0) & 0x0000000f)
1286 
1287 /*
1288  * Field : Read ODT Control - cfg_read_odt_chip
1289  *
1290  * This register controls which ODT pin is asserted during reads.
1291  *
1292  * Field Access Macros:
1293  *
1294  */
1295 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */
1296 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_LSB 4
1297 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */
1298 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_MSB 7
1299 /* The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field. */
1300 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_WIDTH 4
1301 /* The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */
1302 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET_MSK 0x000000f0
1303 /* The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value. */
1304 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_CLR_MSK 0xffffff0f
1305 /* The reset value of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field is UNKNOWN. */
1306 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_RESET 0x0
1307 /* Extracts the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP field value from a register. */
1308 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_GET(value) (((value) & 0x000000f0) >> 4)
1309 /* Produces a ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value suitable for setting the register. */
1310 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET(value) (((value) << 4) & 0x000000f0)
1311 
1312 #ifndef __ASSEMBLY__
1313 /*
1314  * WARNING: The C register and register group struct declarations are provided for
1315  * convenience and illustrative purposes. They should, however, be used with
1316  * caution as the C language standard provides no guarantees about the alignment or
1317  * atomicity of device memory accesses. The recommended practice for writing
1318  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1319  * alt_write_word() functions.
1320  *
1321  * The struct declaration for register ALT_SDR_CTL_DRAMODT.
1322  */
1323 struct ALT_SDR_CTL_DRAMODT_s
1324 {
1325  uint32_t cfg_write_odt_chip : 4; /* Write ODT Control */
1326  uint32_t cfg_read_odt_chip : 4; /* Read ODT Control */
1327  uint32_t : 24; /* *UNDEFINED* */
1328 };
1329 
1330 /* The typedef declaration for register ALT_SDR_CTL_DRAMODT. */
1331 typedef volatile struct ALT_SDR_CTL_DRAMODT_s ALT_SDR_CTL_DRAMODT_t;
1332 #endif /* __ASSEMBLY__ */
1333 
1334 /* The byte offset of the ALT_SDR_CTL_DRAMODT register from the beginning of the component. */
1335 #define ALT_SDR_CTL_DRAMODT_OFST 0x18
1336 
1337 /*
1338  * Register : DRAM Address Widths Register - dramaddrw
1339  *
1340  * This register configures the width of the various address fields of the DRAM.
1341  * The values specified in this register must match the memory devices being used.
1342  *
1343  * Register Layout
1344  *
1345  * Bits | Access | Reset | Description
1346  * :--------|:-------|:--------|:-------------------------
1347  * [4:0] | RW | Unknown | DRAM Column Address Bits
1348  * [9:5] | RW | Unknown | DRAM Row Address Bits
1349  * [12:10] | RW | Unknown | DRAM Bank Address Bits
1350  * [15:13] | RW | Unknown | DRAM Chip Address Bits
1351  * [31:16] | ??? | 0x0 | *UNDEFINED*
1352  *
1353  */
1354 /*
1355  * Field : DRAM Column Address Bits - colbits
1356  *
1357  * The number of column address bits for the memory devices in your memory
1358  * interface.
1359  *
1360  * Field Access Macros:
1361  *
1362  */
1363 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */
1364 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_LSB 0
1365 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */
1366 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_MSB 4
1367 /* The width in bits of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field. */
1368 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_WIDTH 5
1369 /* The mask used to set the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */
1370 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET_MSK 0x0000001f
1371 /* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_COLBITS register field value. */
1372 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_CLR_MSK 0xffffffe0
1373 /* The reset value of the ALT_SDR_CTL_DRAMADDRW_COLBITS register field is UNKNOWN. */
1374 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_RESET 0x0
1375 /* Extracts the ALT_SDR_CTL_DRAMADDRW_COLBITS field value from a register. */
1376 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_GET(value) (((value) & 0x0000001f) >> 0)
1377 /* Produces a ALT_SDR_CTL_DRAMADDRW_COLBITS register field value suitable for setting the register. */
1378 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET(value) (((value) << 0) & 0x0000001f)
1379 
1380 /*
1381  * Field : DRAM Row Address Bits - rowbits
1382  *
1383  * The number of row address bits for the memory devices in your memory interface.
1384  *
1385  * Field Access Macros:
1386  *
1387  */
1388 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */
1389 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_LSB 5
1390 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */
1391 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_MSB 9
1392 /* The width in bits of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field. */
1393 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_WIDTH 5
1394 /* The mask used to set the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */
1395 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET_MSK 0x000003e0
1396 /* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value. */
1397 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_CLR_MSK 0xfffffc1f
1398 /* The reset value of the ALT_SDR_CTL_DRAMADDRW_ROWBITS register field is UNKNOWN. */
1399 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_RESET 0x0
1400 /* Extracts the ALT_SDR_CTL_DRAMADDRW_ROWBITS field value from a register. */
1401 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_GET(value) (((value) & 0x000003e0) >> 5)
1402 /* Produces a ALT_SDR_CTL_DRAMADDRW_ROWBITS register field value suitable for setting the register. */
1403 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET(value) (((value) << 5) & 0x000003e0)
1404 
1405 /*
1406  * Field : DRAM Bank Address Bits - bankbits
1407  *
1408  * The number of bank address bits for the memory devices in your memory interface.
1409  *
1410  * Field Access Macros:
1411  *
1412  */
1413 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */
1414 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_LSB 10
1415 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */
1416 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_MSB 12
1417 /* The width in bits of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field. */
1418 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_WIDTH 3
1419 /* The mask used to set the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */
1420 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET_MSK 0x00001c00
1421 /* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value. */
1422 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_CLR_MSK 0xffffe3ff
1423 /* The reset value of the ALT_SDR_CTL_DRAMADDRW_BANKBITS register field is UNKNOWN. */
1424 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_RESET 0x0
1425 /* Extracts the ALT_SDR_CTL_DRAMADDRW_BANKBITS field value from a register. */
1426 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_GET(value) (((value) & 0x00001c00) >> 10)
1427 /* Produces a ALT_SDR_CTL_DRAMADDRW_BANKBITS register field value suitable for setting the register. */
1428 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET(value) (((value) << 10) & 0x00001c00)
1429 
1430 /*
1431  * Field : DRAM Chip Address Bits - csbits
1432  *
1433  * The number of chip select address bits for the memory devices in your memory
1434  * interface.
1435  *
1436  * Field Access Macros:
1437  *
1438  */
1439 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */
1440 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_LSB 13
1441 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */
1442 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_MSB 15
1443 /* The width in bits of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field. */
1444 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_WIDTH 3
1445 /* The mask used to set the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */
1446 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET_MSK 0x0000e000
1447 /* The mask used to clear the ALT_SDR_CTL_DRAMADDRW_CSBITS register field value. */
1448 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_CLR_MSK 0xffff1fff
1449 /* The reset value of the ALT_SDR_CTL_DRAMADDRW_CSBITS register field is UNKNOWN. */
1450 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_RESET 0x0
1451 /* Extracts the ALT_SDR_CTL_DRAMADDRW_CSBITS field value from a register. */
1452 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_GET(value) (((value) & 0x0000e000) >> 13)
1453 /* Produces a ALT_SDR_CTL_DRAMADDRW_CSBITS register field value suitable for setting the register. */
1454 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET(value) (((value) << 13) & 0x0000e000)
1455 
1456 #ifndef __ASSEMBLY__
1457 /*
1458  * WARNING: The C register and register group struct declarations are provided for
1459  * convenience and illustrative purposes. They should, however, be used with
1460  * caution as the C language standard provides no guarantees about the alignment or
1461  * atomicity of device memory accesses. The recommended practice for writing
1462  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1463  * alt_write_word() functions.
1464  *
1465  * The struct declaration for register ALT_SDR_CTL_DRAMADDRW.
1466  */
1467 struct ALT_SDR_CTL_DRAMADDRW_s
1468 {
1469  uint32_t colbits : 5; /* DRAM Column Address Bits */
1470  uint32_t rowbits : 5; /* DRAM Row Address Bits */
1471  uint32_t bankbits : 3; /* DRAM Bank Address Bits */
1472  uint32_t csbits : 3; /* DRAM Chip Address Bits */
1473  uint32_t : 16; /* *UNDEFINED* */
1474 };
1475 
1476 /* The typedef declaration for register ALT_SDR_CTL_DRAMADDRW. */
1477 typedef volatile struct ALT_SDR_CTL_DRAMADDRW_s ALT_SDR_CTL_DRAMADDRW_t;
1478 #endif /* __ASSEMBLY__ */
1479 
1480 /* The byte offset of the ALT_SDR_CTL_DRAMADDRW register from the beginning of the component. */
1481 #define ALT_SDR_CTL_DRAMADDRW_OFST 0x2c
1482 
1483 /*
1484  * Register : DRAM Interface Data Width Register - dramifwidth
1485  *
1486  *
1487  * Register Layout
1488  *
1489  * Bits | Access | Reset | Description
1490  * :-------|:-------|:--------|:--------------------------
1491  * [7:0] | RW | Unknown | DRAM Interface Data Width
1492  * [31:8] | ??? | 0x0 | *UNDEFINED*
1493  *
1494  */
1495 /*
1496  * Field : DRAM Interface Data Width - ifwidth
1497  *
1498  * This register controls the interface width of the SDRAM interface, including any
1499  * bits used for ECC. For example, for a 32-bit interface with ECC, program this
1500  * register with 0x28. You must also program the ctrlwidth register.
1501  *
1502  * Field Access Macros:
1503  *
1504  */
1505 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */
1506 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_LSB 0
1507 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */
1508 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_MSB 7
1509 /* The width in bits of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field. */
1510 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_WIDTH 8
1511 /* The mask used to set the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */
1512 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET_MSK 0x000000ff
1513 /* The mask used to clear the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value. */
1514 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_CLR_MSK 0xffffff00
1515 /* The reset value of the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field is UNKNOWN. */
1516 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_RESET 0x0
1517 /* Extracts the ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH field value from a register. */
1518 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_GET(value) (((value) & 0x000000ff) >> 0)
1519 /* Produces a ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH register field value suitable for setting the register. */
1520 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET(value) (((value) << 0) & 0x000000ff)
1521 
1522 #ifndef __ASSEMBLY__
1523 /*
1524  * WARNING: The C register and register group struct declarations are provided for
1525  * convenience and illustrative purposes. They should, however, be used with
1526  * caution as the C language standard provides no guarantees about the alignment or
1527  * atomicity of device memory accesses. The recommended practice for writing
1528  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1529  * alt_write_word() functions.
1530  *
1531  * The struct declaration for register ALT_SDR_CTL_DRAMIFWIDTH.
1532  */
1533 struct ALT_SDR_CTL_DRAMIFWIDTH_s
1534 {
1535  uint32_t ifwidth : 8; /* DRAM Interface Data Width */
1536  uint32_t : 24; /* *UNDEFINED* */
1537 };
1538 
1539 /* The typedef declaration for register ALT_SDR_CTL_DRAMIFWIDTH. */
1540 typedef volatile struct ALT_SDR_CTL_DRAMIFWIDTH_s ALT_SDR_CTL_DRAMIFWIDTH_t;
1541 #endif /* __ASSEMBLY__ */
1542 
1543 /* The byte offset of the ALT_SDR_CTL_DRAMIFWIDTH register from the beginning of the component. */
1544 #define ALT_SDR_CTL_DRAMIFWIDTH_OFST 0x30
1545 
1546 /*
1547  * Register : DRAM Devices Data Width Register - dramdevwidth
1548  *
1549  *
1550  * Register Layout
1551  *
1552  * Bits | Access | Reset | Description
1553  * :-------|:-------|:--------|:------------------------
1554  * [3:0] | RW | Unknown | DRAM Devices Data Width
1555  * [31:4] | ??? | 0x0 | *UNDEFINED*
1556  *
1557  */
1558 /*
1559  * Field : DRAM Devices Data Width - devwidth
1560  *
1561  * This register specifies the width of the physical DRAM chips, for example 8 or
1562  * 16.
1563  *
1564  * Field Access Macros:
1565  *
1566  */
1567 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */
1568 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_LSB 0
1569 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */
1570 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_MSB 3
1571 /* The width in bits of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field. */
1572 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_WIDTH 4
1573 /* The mask used to set the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */
1574 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET_MSK 0x0000000f
1575 /* The mask used to clear the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value. */
1576 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_CLR_MSK 0xfffffff0
1577 /* The reset value of the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field is UNKNOWN. */
1578 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_RESET 0x0
1579 /* Extracts the ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH field value from a register. */
1580 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_GET(value) (((value) & 0x0000000f) >> 0)
1581 /* Produces a ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH register field value suitable for setting the register. */
1582 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET(value) (((value) << 0) & 0x0000000f)
1583 
1584 #ifndef __ASSEMBLY__
1585 /*
1586  * WARNING: The C register and register group struct declarations are provided for
1587  * convenience and illustrative purposes. They should, however, be used with
1588  * caution as the C language standard provides no guarantees about the alignment or
1589  * atomicity of device memory accesses. The recommended practice for writing
1590  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1591  * alt_write_word() functions.
1592  *
1593  * The struct declaration for register ALT_SDR_CTL_DRAMDEVWIDTH.
1594  */
1595 struct ALT_SDR_CTL_DRAMDEVWIDTH_s
1596 {
1597  uint32_t devwidth : 4; /* DRAM Devices Data Width */
1598  uint32_t : 28; /* *UNDEFINED* */
1599 };
1600 
1601 /* The typedef declaration for register ALT_SDR_CTL_DRAMDEVWIDTH. */
1602 typedef volatile struct ALT_SDR_CTL_DRAMDEVWIDTH_s ALT_SDR_CTL_DRAMDEVWIDTH_t;
1603 #endif /* __ASSEMBLY__ */
1604 
1605 /* The byte offset of the ALT_SDR_CTL_DRAMDEVWIDTH register from the beginning of the component. */
1606 #define ALT_SDR_CTL_DRAMDEVWIDTH_OFST 0x34
1607 
1608 /*
1609  * Register : DRAM Status Register - dramsts
1610  *
1611  * This register provides the status of the calibration and ECC logic.
1612  *
1613  * Register Layout
1614  *
1615  * Bits | Access | Reset | Description
1616  * :-------|:-------|:--------|:----------------------------
1617  * [0] | RW | Unknown | PHY Calibration Successful
1618  * [1] | RW | Unknown | PHY Calibration Failed
1619  * [2] | RW | Unknown | Single Bit Error Seen
1620  * [3] | RW | Unknown | Double Bit Error Seen
1621  * [4] | RW | Unknown | ECC Auto-Correction Dropped
1622  * [31:5] | ??? | 0x0 | *UNDEFINED*
1623  *
1624  */
1625 /*
1626  * Field : PHY Calibration Successful - calsuccess
1627  *
1628  * This bit will be set to 1 if the PHY was able to successfully calibrate.
1629  *
1630  * Field Access Macros:
1631  *
1632  */
1633 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */
1634 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_LSB 0
1635 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */
1636 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_MSB 0
1637 /* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field. */
1638 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_WIDTH 1
1639 /* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */
1640 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET_MSK 0x00000001
1641 /* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value. */
1642 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_CLR_MSK 0xfffffffe
1643 /* The reset value of the ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field is UNKNOWN. */
1644 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_RESET 0x0
1645 /* Extracts the ALT_SDR_CTL_DRAMSTS_CALSUCCESS field value from a register. */
1646 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_GET(value) (((value) & 0x00000001) >> 0)
1647 /* Produces a ALT_SDR_CTL_DRAMSTS_CALSUCCESS register field value suitable for setting the register. */
1648 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET(value) (((value) << 0) & 0x00000001)
1649 
1650 /*
1651  * Field : PHY Calibration Failed - calfail
1652  *
1653  * This bit will be set to 1 if the PHY was unable to calibrate.
1654  *
1655  * Field Access Macros:
1656  *
1657  */
1658 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */
1659 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_LSB 1
1660 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */
1661 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_MSB 1
1662 /* The width in bits of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field. */
1663 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_WIDTH 1
1664 /* The mask used to set the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */
1665 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET_MSK 0x00000002
1666 /* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CALFAIL register field value. */
1667 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_CLR_MSK 0xfffffffd
1668 /* The reset value of the ALT_SDR_CTL_DRAMSTS_CALFAIL register field is UNKNOWN. */
1669 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_RESET 0x0
1670 /* Extracts the ALT_SDR_CTL_DRAMSTS_CALFAIL field value from a register. */
1671 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_GET(value) (((value) & 0x00000002) >> 1)
1672 /* Produces a ALT_SDR_CTL_DRAMSTS_CALFAIL register field value suitable for setting the register. */
1673 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET(value) (((value) << 1) & 0x00000002)
1674 
1675 /*
1676  * Field : Single Bit Error Seen - sbeerr
1677  *
1678  * This bit will be set to 1 if there have been any ECC single bit errors detected.
1679  *
1680  * Field Access Macros:
1681  *
1682  */
1683 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */
1684 #define ALT_SDR_CTL_DRAMSTS_SBEERR_LSB 2
1685 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */
1686 #define ALT_SDR_CTL_DRAMSTS_SBEERR_MSB 2
1687 /* The width in bits of the ALT_SDR_CTL_DRAMSTS_SBEERR register field. */
1688 #define ALT_SDR_CTL_DRAMSTS_SBEERR_WIDTH 1
1689 /* The mask used to set the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */
1690 #define ALT_SDR_CTL_DRAMSTS_SBEERR_SET_MSK 0x00000004
1691 /* The mask used to clear the ALT_SDR_CTL_DRAMSTS_SBEERR register field value. */
1692 #define ALT_SDR_CTL_DRAMSTS_SBEERR_CLR_MSK 0xfffffffb
1693 /* The reset value of the ALT_SDR_CTL_DRAMSTS_SBEERR register field is UNKNOWN. */
1694 #define ALT_SDR_CTL_DRAMSTS_SBEERR_RESET 0x0
1695 /* Extracts the ALT_SDR_CTL_DRAMSTS_SBEERR field value from a register. */
1696 #define ALT_SDR_CTL_DRAMSTS_SBEERR_GET(value) (((value) & 0x00000004) >> 2)
1697 /* Produces a ALT_SDR_CTL_DRAMSTS_SBEERR register field value suitable for setting the register. */
1698 #define ALT_SDR_CTL_DRAMSTS_SBEERR_SET(value) (((value) << 2) & 0x00000004)
1699 
1700 /*
1701  * Field : Double Bit Error Seen - dbeerr
1702  *
1703  * This bit will be set to 1 if there have been any ECC double bit errors detected.
1704  *
1705  * Field Access Macros:
1706  *
1707  */
1708 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */
1709 #define ALT_SDR_CTL_DRAMSTS_DBEERR_LSB 3
1710 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */
1711 #define ALT_SDR_CTL_DRAMSTS_DBEERR_MSB 3
1712 /* The width in bits of the ALT_SDR_CTL_DRAMSTS_DBEERR register field. */
1713 #define ALT_SDR_CTL_DRAMSTS_DBEERR_WIDTH 1
1714 /* The mask used to set the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */
1715 #define ALT_SDR_CTL_DRAMSTS_DBEERR_SET_MSK 0x00000008
1716 /* The mask used to clear the ALT_SDR_CTL_DRAMSTS_DBEERR register field value. */
1717 #define ALT_SDR_CTL_DRAMSTS_DBEERR_CLR_MSK 0xfffffff7
1718 /* The reset value of the ALT_SDR_CTL_DRAMSTS_DBEERR register field is UNKNOWN. */
1719 #define ALT_SDR_CTL_DRAMSTS_DBEERR_RESET 0x0
1720 /* Extracts the ALT_SDR_CTL_DRAMSTS_DBEERR field value from a register. */
1721 #define ALT_SDR_CTL_DRAMSTS_DBEERR_GET(value) (((value) & 0x00000008) >> 3)
1722 /* Produces a ALT_SDR_CTL_DRAMSTS_DBEERR register field value suitable for setting the register. */
1723 #define ALT_SDR_CTL_DRAMSTS_DBEERR_SET(value) (((value) << 3) & 0x00000008)
1724 
1725 /*
1726  * Field : ECC Auto-Correction Dropped - corrdrop
1727  *
1728  * This bit will be set to 1 if there any auto-corrections have been dropped.
1729  *
1730  * Field Access Macros:
1731  *
1732  */
1733 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */
1734 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_LSB 4
1735 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */
1736 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_MSB 4
1737 /* The width in bits of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field. */
1738 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_WIDTH 1
1739 /* The mask used to set the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */
1740 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET_MSK 0x00000010
1741 /* The mask used to clear the ALT_SDR_CTL_DRAMSTS_CORRDROP register field value. */
1742 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_CLR_MSK 0xffffffef
1743 /* The reset value of the ALT_SDR_CTL_DRAMSTS_CORRDROP register field is UNKNOWN. */
1744 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_RESET 0x0
1745 /* Extracts the ALT_SDR_CTL_DRAMSTS_CORRDROP field value from a register. */
1746 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_GET(value) (((value) & 0x00000010) >> 4)
1747 /* Produces a ALT_SDR_CTL_DRAMSTS_CORRDROP register field value suitable for setting the register. */
1748 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET(value) (((value) << 4) & 0x00000010)
1749 
1750 #ifndef __ASSEMBLY__
1751 /*
1752  * WARNING: The C register and register group struct declarations are provided for
1753  * convenience and illustrative purposes. They should, however, be used with
1754  * caution as the C language standard provides no guarantees about the alignment or
1755  * atomicity of device memory accesses. The recommended practice for writing
1756  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1757  * alt_write_word() functions.
1758  *
1759  * The struct declaration for register ALT_SDR_CTL_DRAMSTS.
1760  */
1761 struct ALT_SDR_CTL_DRAMSTS_s
1762 {
1763  uint32_t calsuccess : 1; /* PHY Calibration Successful */
1764  uint32_t calfail : 1; /* PHY Calibration Failed */
1765  uint32_t sbeerr : 1; /* Single Bit Error Seen */
1766  uint32_t dbeerr : 1; /* Double Bit Error Seen */
1767  uint32_t corrdrop : 1; /* ECC Auto-Correction Dropped */
1768  uint32_t : 27; /* *UNDEFINED* */
1769 };
1770 
1771 /* The typedef declaration for register ALT_SDR_CTL_DRAMSTS. */
1772 typedef volatile struct ALT_SDR_CTL_DRAMSTS_s ALT_SDR_CTL_DRAMSTS_t;
1773 #endif /* __ASSEMBLY__ */
1774 
1775 /* The byte offset of the ALT_SDR_CTL_DRAMSTS register from the beginning of the component. */
1776 #define ALT_SDR_CTL_DRAMSTS_OFST 0x38
1777 
1778 /*
1779  * Register : ECC Interrupt Register - dramintr
1780  *
1781  *
1782  * Register Layout
1783  *
1784  * Bits | Access | Reset | Description
1785  * :-------|:-------|:--------|:---------------------------------------
1786  * [0] | RW | Unknown | Interrupt Enable
1787  * [1] | RW | Unknown | Mask Single Bit Error Interrupt
1788  * [2] | RW | Unknown | Mask Double Bit Error Interrupt
1789  * [3] | RW | Unknown | Mask Dropped Auto-correction Interrupt
1790  * [4] | RW | Unknown | Clear Interrupt Signal
1791  * [31:5] | ??? | 0x0 | *UNDEFINED*
1792  *
1793  */
1794 /*
1795  * Field : Interrupt Enable - intren
1796  *
1797  * Enable the interrupt output.
1798  *
1799  * Field Access Macros:
1800  *
1801  */
1802 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */
1803 #define ALT_SDR_CTL_DRAMINTR_INTREN_LSB 0
1804 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */
1805 #define ALT_SDR_CTL_DRAMINTR_INTREN_MSB 0
1806 /* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTREN register field. */
1807 #define ALT_SDR_CTL_DRAMINTR_INTREN_WIDTH 1
1808 /* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */
1809 #define ALT_SDR_CTL_DRAMINTR_INTREN_SET_MSK 0x00000001
1810 /* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTREN register field value. */
1811 #define ALT_SDR_CTL_DRAMINTR_INTREN_CLR_MSK 0xfffffffe
1812 /* The reset value of the ALT_SDR_CTL_DRAMINTR_INTREN register field is UNKNOWN. */
1813 #define ALT_SDR_CTL_DRAMINTR_INTREN_RESET 0x0
1814 /* Extracts the ALT_SDR_CTL_DRAMINTR_INTREN field value from a register. */
1815 #define ALT_SDR_CTL_DRAMINTR_INTREN_GET(value) (((value) & 0x00000001) >> 0)
1816 /* Produces a ALT_SDR_CTL_DRAMINTR_INTREN register field value suitable for setting the register. */
1817 #define ALT_SDR_CTL_DRAMINTR_INTREN_SET(value) (((value) << 0) & 0x00000001)
1818 
1819 /*
1820  * Field : Mask Single Bit Error Interrupt - sbemask
1821  *
1822  * Mask the single bit error interrupt.
1823  *
1824  * Field Access Macros:
1825  *
1826  */
1827 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */
1828 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_LSB 1
1829 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */
1830 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_MSB 1
1831 /* The width in bits of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field. */
1832 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_WIDTH 1
1833 /* The mask used to set the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */
1834 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET_MSK 0x00000002
1835 /* The mask used to clear the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value. */
1836 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_CLR_MSK 0xfffffffd
1837 /* The reset value of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field is UNKNOWN. */
1838 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_RESET 0x0
1839 /* Extracts the ALT_SDR_CTL_DRAMINTR_SBEMSK field value from a register. */
1840 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_GET(value) (((value) & 0x00000002) >> 1)
1841 /* Produces a ALT_SDR_CTL_DRAMINTR_SBEMSK register field value suitable for setting the register. */
1842 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET(value) (((value) << 1) & 0x00000002)
1843 
1844 /*
1845  * Field : Mask Double Bit Error Interrupt - dbemask
1846  *
1847  * Mask the double bit error interrupt.
1848  *
1849  * Field Access Macros:
1850  *
1851  */
1852 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */
1853 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_LSB 2
1854 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */
1855 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_MSB 2
1856 /* The width in bits of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field. */
1857 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_WIDTH 1
1858 /* The mask used to set the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */
1859 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET_MSK 0x00000004
1860 /* The mask used to clear the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value. */
1861 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_CLR_MSK 0xfffffffb
1862 /* The reset value of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field is UNKNOWN. */
1863 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_RESET 0x0
1864 /* Extracts the ALT_SDR_CTL_DRAMINTR_DBEMSK field value from a register. */
1865 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_GET(value) (((value) & 0x00000004) >> 2)
1866 /* Produces a ALT_SDR_CTL_DRAMINTR_DBEMSK register field value suitable for setting the register. */
1867 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET(value) (((value) << 2) & 0x00000004)
1868 
1869 /*
1870  * Field : Mask Dropped Auto-correction Interrupt - corrdropmask
1871  *
1872  * Set this bit to a one to mask interrupts for an ECC correction write back
1873  * needing to be dropped. This indicates a burst of memory errors in a short
1874  * period of time.
1875  *
1876  * Field Access Macros:
1877  *
1878  */
1879 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */
1880 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_LSB 3
1881 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */
1882 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_MSB 3
1883 /* The width in bits of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field. */
1884 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_WIDTH 1
1885 /* The mask used to set the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */
1886 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET_MSK 0x00000008
1887 /* The mask used to clear the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value. */
1888 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_CLR_MSK 0xfffffff7
1889 /* The reset value of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field is UNKNOWN. */
1890 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_RESET 0x0
1891 /* Extracts the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK field value from a register. */
1892 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_GET(value) (((value) & 0x00000008) >> 3)
1893 /* Produces a ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value suitable for setting the register. */
1894 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET(value) (((value) << 3) & 0x00000008)
1895 
1896 /*
1897  * Field : Clear Interrupt Signal - intrclr
1898  *
1899  * Writing to this self-clearing bit clears the interrupt signal. Writing to this
1900  * bit also clears the error count and error address registers.
1901  *
1902  * Field Access Macros:
1903  *
1904  */
1905 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */
1906 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_LSB 4
1907 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */
1908 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_MSB 4
1909 /* The width in bits of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field. */
1910 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_WIDTH 1
1911 /* The mask used to set the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */
1912 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET_MSK 0x00000010
1913 /* The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value. */
1914 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_CLR_MSK 0xffffffef
1915 /* The reset value of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field is UNKNOWN. */
1916 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_RESET 0x0
1917 /* Extracts the ALT_SDR_CTL_DRAMINTR_INTRCLR field value from a register. */
1918 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_GET(value) (((value) & 0x00000010) >> 4)
1919 /* Produces a ALT_SDR_CTL_DRAMINTR_INTRCLR register field value suitable for setting the register. */
1920 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET(value) (((value) << 4) & 0x00000010)
1921 
1922 #ifndef __ASSEMBLY__
1923 /*
1924  * WARNING: The C register and register group struct declarations are provided for
1925  * convenience and illustrative purposes. They should, however, be used with
1926  * caution as the C language standard provides no guarantees about the alignment or
1927  * atomicity of device memory accesses. The recommended practice for writing
1928  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1929  * alt_write_word() functions.
1930  *
1931  * The struct declaration for register ALT_SDR_CTL_DRAMINTR.
1932  */
1933 struct ALT_SDR_CTL_DRAMINTR_s
1934 {
1935  uint32_t intren : 1; /* Interrupt Enable */
1936  uint32_t sbemask : 1; /* Mask Single Bit Error Interrupt */
1937  uint32_t dbemask : 1; /* Mask Double Bit Error Interrupt */
1938  uint32_t corrdropmask : 1; /* Mask Dropped Auto-correction Interrupt */
1939  uint32_t intrclr : 1; /* Clear Interrupt Signal */
1940  uint32_t : 27; /* *UNDEFINED* */
1941 };
1942 
1943 /* The typedef declaration for register ALT_SDR_CTL_DRAMINTR. */
1944 typedef volatile struct ALT_SDR_CTL_DRAMINTR_s ALT_SDR_CTL_DRAMINTR_t;
1945 #endif /* __ASSEMBLY__ */
1946 
1947 /* The byte offset of the ALT_SDR_CTL_DRAMINTR register from the beginning of the component. */
1948 #define ALT_SDR_CTL_DRAMINTR_OFST 0x3c
1949 
1950 /*
1951  * Register : ECC Single Bit Error Count Register - sbecount
1952  *
1953  *
1954  * Register Layout
1955  *
1956  * Bits | Access | Reset | Description
1957  * :-------|:-------|:--------|:-----------------------
1958  * [7:0] | RW | Unknown | Single Bit Error Count
1959  * [31:8] | ??? | 0x0 | *UNDEFINED*
1960  *
1961  */
1962 /*
1963  * Field : Single Bit Error Count - count
1964  *
1965  * Reports the number of single bit errors that have occurred since the status
1966  * register counters were last cleared.
1967  *
1968  * Field Access Macros:
1969  *
1970  */
1971 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */
1972 #define ALT_SDR_CTL_SBECOUNT_COUNT_LSB 0
1973 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */
1974 #define ALT_SDR_CTL_SBECOUNT_COUNT_MSB 7
1975 /* The width in bits of the ALT_SDR_CTL_SBECOUNT_COUNT register field. */
1976 #define ALT_SDR_CTL_SBECOUNT_COUNT_WIDTH 8
1977 /* The mask used to set the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */
1978 #define ALT_SDR_CTL_SBECOUNT_COUNT_SET_MSK 0x000000ff
1979 /* The mask used to clear the ALT_SDR_CTL_SBECOUNT_COUNT register field value. */
1980 #define ALT_SDR_CTL_SBECOUNT_COUNT_CLR_MSK 0xffffff00
1981 /* The reset value of the ALT_SDR_CTL_SBECOUNT_COUNT register field is UNKNOWN. */
1982 #define ALT_SDR_CTL_SBECOUNT_COUNT_RESET 0x0
1983 /* Extracts the ALT_SDR_CTL_SBECOUNT_COUNT field value from a register. */
1984 #define ALT_SDR_CTL_SBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0)
1985 /* Produces a ALT_SDR_CTL_SBECOUNT_COUNT register field value suitable for setting the register. */
1986 #define ALT_SDR_CTL_SBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff)
1987 
1988 #ifndef __ASSEMBLY__
1989 /*
1990  * WARNING: The C register and register group struct declarations are provided for
1991  * convenience and illustrative purposes. They should, however, be used with
1992  * caution as the C language standard provides no guarantees about the alignment or
1993  * atomicity of device memory accesses. The recommended practice for writing
1994  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1995  * alt_write_word() functions.
1996  *
1997  * The struct declaration for register ALT_SDR_CTL_SBECOUNT.
1998  */
1999 struct ALT_SDR_CTL_SBECOUNT_s
2000 {
2001  uint32_t count : 8; /* Single Bit Error Count */
2002  uint32_t : 24; /* *UNDEFINED* */
2003 };
2004 
2005 /* The typedef declaration for register ALT_SDR_CTL_SBECOUNT. */
2006 typedef volatile struct ALT_SDR_CTL_SBECOUNT_s ALT_SDR_CTL_SBECOUNT_t;
2007 #endif /* __ASSEMBLY__ */
2008 
2009 /* The byte offset of the ALT_SDR_CTL_SBECOUNT register from the beginning of the component. */
2010 #define ALT_SDR_CTL_SBECOUNT_OFST 0x40
2011 
2012 /*
2013  * Register : ECC Double Bit Error Count Register - dbecount
2014  *
2015  *
2016  * Register Layout
2017  *
2018  * Bits | Access | Reset | Description
2019  * :-------|:-------|:--------|:-----------------------
2020  * [7:0] | RW | Unknown | Double Bit Error Count
2021  * [31:8] | ??? | 0x0 | *UNDEFINED*
2022  *
2023  */
2024 /*
2025  * Field : Double Bit Error Count - count
2026  *
2027  * Reports the number of double bit errors that have occurred since the status
2028  * register counters were last cleared.
2029  *
2030  * Field Access Macros:
2031  *
2032  */
2033 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */
2034 #define ALT_SDR_CTL_DBECOUNT_COUNT_LSB 0
2035 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */
2036 #define ALT_SDR_CTL_DBECOUNT_COUNT_MSB 7
2037 /* The width in bits of the ALT_SDR_CTL_DBECOUNT_COUNT register field. */
2038 #define ALT_SDR_CTL_DBECOUNT_COUNT_WIDTH 8
2039 /* The mask used to set the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */
2040 #define ALT_SDR_CTL_DBECOUNT_COUNT_SET_MSK 0x000000ff
2041 /* The mask used to clear the ALT_SDR_CTL_DBECOUNT_COUNT register field value. */
2042 #define ALT_SDR_CTL_DBECOUNT_COUNT_CLR_MSK 0xffffff00
2043 /* The reset value of the ALT_SDR_CTL_DBECOUNT_COUNT register field is UNKNOWN. */
2044 #define ALT_SDR_CTL_DBECOUNT_COUNT_RESET 0x0
2045 /* Extracts the ALT_SDR_CTL_DBECOUNT_COUNT field value from a register. */
2046 #define ALT_SDR_CTL_DBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0)
2047 /* Produces a ALT_SDR_CTL_DBECOUNT_COUNT register field value suitable for setting the register. */
2048 #define ALT_SDR_CTL_DBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff)
2049 
2050 #ifndef __ASSEMBLY__
2051 /*
2052  * WARNING: The C register and register group struct declarations are provided for
2053  * convenience and illustrative purposes. They should, however, be used with
2054  * caution as the C language standard provides no guarantees about the alignment or
2055  * atomicity of device memory accesses. The recommended practice for writing
2056  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2057  * alt_write_word() functions.
2058  *
2059  * The struct declaration for register ALT_SDR_CTL_DBECOUNT.
2060  */
2061 struct ALT_SDR_CTL_DBECOUNT_s
2062 {
2063  uint32_t count : 8; /* Double Bit Error Count */
2064  uint32_t : 24; /* *UNDEFINED* */
2065 };
2066 
2067 /* The typedef declaration for register ALT_SDR_CTL_DBECOUNT. */
2068 typedef volatile struct ALT_SDR_CTL_DBECOUNT_s ALT_SDR_CTL_DBECOUNT_t;
2069 #endif /* __ASSEMBLY__ */
2070 
2071 /* The byte offset of the ALT_SDR_CTL_DBECOUNT register from the beginning of the component. */
2072 #define ALT_SDR_CTL_DBECOUNT_OFST 0x44
2073 
2074 /*
2075  * Register : ECC Error Address Register - erraddr
2076  *
2077  *
2078  * Register Layout
2079  *
2080  * Bits | Access | Reset | Description
2081  * :-------|:-------|:--------|:------------------
2082  * [31:0] | RW | Unknown | ECC Error Address
2083  *
2084  */
2085 /*
2086  * Field : ECC Error Address - addr
2087  *
2088  * The address of the most recent ECC error.
2089  *
2090  * Field Access Macros:
2091  *
2092  */
2093 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */
2094 #define ALT_SDR_CTL_ERRADDR_ADDR_LSB 0
2095 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_ERRADDR_ADDR register field. */
2096 #define ALT_SDR_CTL_ERRADDR_ADDR_MSB 31
2097 /* The width in bits of the ALT_SDR_CTL_ERRADDR_ADDR register field. */
2098 #define ALT_SDR_CTL_ERRADDR_ADDR_WIDTH 32
2099 /* The mask used to set the ALT_SDR_CTL_ERRADDR_ADDR register field value. */
2100 #define ALT_SDR_CTL_ERRADDR_ADDR_SET_MSK 0xffffffff
2101 /* The mask used to clear the ALT_SDR_CTL_ERRADDR_ADDR register field value. */
2102 #define ALT_SDR_CTL_ERRADDR_ADDR_CLR_MSK 0x00000000
2103 /* The reset value of the ALT_SDR_CTL_ERRADDR_ADDR register field is UNKNOWN. */
2104 #define ALT_SDR_CTL_ERRADDR_ADDR_RESET 0x0
2105 /* Extracts the ALT_SDR_CTL_ERRADDR_ADDR field value from a register. */
2106 #define ALT_SDR_CTL_ERRADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
2107 /* Produces a ALT_SDR_CTL_ERRADDR_ADDR register field value suitable for setting the register. */
2108 #define ALT_SDR_CTL_ERRADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
2109 
2110 #ifndef __ASSEMBLY__
2111 /*
2112  * WARNING: The C register and register group struct declarations are provided for
2113  * convenience and illustrative purposes. They should, however, be used with
2114  * caution as the C language standard provides no guarantees about the alignment or
2115  * atomicity of device memory accesses. The recommended practice for writing
2116  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2117  * alt_write_word() functions.
2118  *
2119  * The struct declaration for register ALT_SDR_CTL_ERRADDR.
2120  */
2121 struct ALT_SDR_CTL_ERRADDR_s
2122 {
2123  uint32_t addr : 32; /* ECC Error Address */
2124 };
2125 
2126 /* The typedef declaration for register ALT_SDR_CTL_ERRADDR. */
2127 typedef volatile struct ALT_SDR_CTL_ERRADDR_s ALT_SDR_CTL_ERRADDR_t;
2128 #endif /* __ASSEMBLY__ */
2129 
2130 /* The byte offset of the ALT_SDR_CTL_ERRADDR register from the beginning of the component. */
2131 #define ALT_SDR_CTL_ERRADDR_OFST 0x48
2132 
2133 /*
2134  * Register : ECC Auto-correction Dropped Count Register - dropcount
2135  *
2136  *
2137  * Register Layout
2138  *
2139  * Bits | Access | Reset | Description
2140  * :-------|:-------|:--------|:------------------------------
2141  * [7:0] | RW | Unknown | Dropped Auto-correction Count
2142  * [31:8] | ??? | 0x0 | *UNDEFINED*
2143  *
2144  */
2145 /*
2146  * Field : Dropped Auto-correction Count - corrdropcount
2147  *
2148  * This gives the count of the number of ECC write back transactions dropped due to
2149  * the internal FIFO overflowing.
2150  *
2151  * Field Access Macros:
2152  *
2153  */
2154 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */
2155 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_LSB 0
2156 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */
2157 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_MSB 7
2158 /* The width in bits of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field. */
2159 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_WIDTH 8
2160 /* The mask used to set the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */
2161 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET_MSK 0x000000ff
2162 /* The mask used to clear the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value. */
2163 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_CLR_MSK 0xffffff00
2164 /* The reset value of the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field is UNKNOWN. */
2165 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_RESET 0x0
2166 /* Extracts the ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT field value from a register. */
2167 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_GET(value) (((value) & 0x000000ff) >> 0)
2168 /* Produces a ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT register field value suitable for setting the register. */
2169 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET(value) (((value) << 0) & 0x000000ff)
2170 
2171 #ifndef __ASSEMBLY__
2172 /*
2173  * WARNING: The C register and register group struct declarations are provided for
2174  * convenience and illustrative purposes. They should, however, be used with
2175  * caution as the C language standard provides no guarantees about the alignment or
2176  * atomicity of device memory accesses. The recommended practice for writing
2177  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2178  * alt_write_word() functions.
2179  *
2180  * The struct declaration for register ALT_SDR_CTL_DROPCOUNT.
2181  */
2182 struct ALT_SDR_CTL_DROPCOUNT_s
2183 {
2184  uint32_t corrdropcount : 8; /* Dropped Auto-correction Count */
2185  uint32_t : 24; /* *UNDEFINED* */
2186 };
2187 
2188 /* The typedef declaration for register ALT_SDR_CTL_DROPCOUNT. */
2189 typedef volatile struct ALT_SDR_CTL_DROPCOUNT_s ALT_SDR_CTL_DROPCOUNT_t;
2190 #endif /* __ASSEMBLY__ */
2191 
2192 /* The byte offset of the ALT_SDR_CTL_DROPCOUNT register from the beginning of the component. */
2193 #define ALT_SDR_CTL_DROPCOUNT_OFST 0x4c
2194 
2195 /*
2196  * Register : ECC Auto-correction Dropped Address Register - dropaddr
2197  *
2198  *
2199  * Register Layout
2200  *
2201  * Bits | Access | Reset | Description
2202  * :-------|:-------|:--------|:--------------------------------
2203  * [31:0] | RW | Unknown | Dropped Auto-correction Address
2204  *
2205  */
2206 /*
2207  * Field : Dropped Auto-correction Address - corrdropaddr
2208  *
2209  * This register gives the last address which was dropped.
2210  *
2211  * Field Access Macros:
2212  *
2213  */
2214 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */
2215 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_LSB 0
2216 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */
2217 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_MSB 31
2218 /* The width in bits of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field. */
2219 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_WIDTH 32
2220 /* The mask used to set the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */
2221 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET_MSK 0xffffffff
2222 /* The mask used to clear the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value. */
2223 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_CLR_MSK 0x00000000
2224 /* The reset value of the ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field is UNKNOWN. */
2225 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_RESET 0x0
2226 /* Extracts the ALT_SDR_CTL_DROPADDR_CORRDROPADDR field value from a register. */
2227 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_GET(value) (((value) & 0xffffffff) >> 0)
2228 /* Produces a ALT_SDR_CTL_DROPADDR_CORRDROPADDR register field value suitable for setting the register. */
2229 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET(value) (((value) << 0) & 0xffffffff)
2230 
2231 #ifndef __ASSEMBLY__
2232 /*
2233  * WARNING: The C register and register group struct declarations are provided for
2234  * convenience and illustrative purposes. They should, however, be used with
2235  * caution as the C language standard provides no guarantees about the alignment or
2236  * atomicity of device memory accesses. The recommended practice for writing
2237  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2238  * alt_write_word() functions.
2239  *
2240  * The struct declaration for register ALT_SDR_CTL_DROPADDR.
2241  */
2242 struct ALT_SDR_CTL_DROPADDR_s
2243 {
2244  uint32_t corrdropaddr : 32; /* Dropped Auto-correction Address */
2245 };
2246 
2247 /* The typedef declaration for register ALT_SDR_CTL_DROPADDR. */
2248 typedef volatile struct ALT_SDR_CTL_DROPADDR_s ALT_SDR_CTL_DROPADDR_t;
2249 #endif /* __ASSEMBLY__ */
2250 
2251 /* The byte offset of the ALT_SDR_CTL_DROPADDR register from the beginning of the component. */
2252 #define ALT_SDR_CTL_DROPADDR_OFST 0x50
2253 
2254 /*
2255  * Register : Low Power Control Register - lowpwreq
2256  *
2257  * This register instructs the controller to put the DRAM into a power down state.
2258  * Note that some commands are only valid for certain memory types.
2259  *
2260  * Register Layout
2261  *
2262  * Bits | Access | Reset | Description
2263  * :-------|:-------|:--------|:---------------------------------
2264  * [0] | RW | Unknown | Deep Power Down Request
2265  * [2:1] | RW | Unknown | Deep Power Down Chip Select Mask
2266  * [3] | RW | Unknown | Self-refresh Request
2267  * [5:4] | RW | Unknown | Self-refresh Chip Select Mask
2268  * [31:6] | ??? | 0x0 | *UNDEFINED*
2269  *
2270  */
2271 /*
2272  * Field : Deep Power Down Request - deeppwrdnreq
2273  *
2274  * Write a one to this bit to request a deep power down. This bit should only be
2275  * written with LPDDR2 DRAMs, DDR3 DRAMs do not support deep power down.
2276  *
2277  * Field Access Macros:
2278  *
2279  */
2280 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */
2281 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_LSB 0
2282 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */
2283 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_MSB 0
2284 /* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field. */
2285 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_WIDTH 1
2286 /* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */
2287 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET_MSK 0x00000001
2288 /* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value. */
2289 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_CLR_MSK 0xfffffffe
2290 /* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field is UNKNOWN. */
2291 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_RESET 0x0
2292 /* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ field value from a register. */
2293 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_GET(value) (((value) & 0x00000001) >> 0)
2294 /* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value suitable for setting the register. */
2295 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET(value) (((value) << 0) & 0x00000001)
2296 
2297 /*
2298  * Field : Deep Power Down Chip Select Mask - deeppwrdnmask
2299  *
2300  * Write ones to this register to select which DRAM chip selects will be powered
2301  * down. Typical usage is to set both of these bits when deeppwrdnreq is set but
2302  * the controller does support putting a single chip into deep power down and
2303  * keeping the other chip running.
2304  *
2305  * Field Access Macros:
2306  *
2307  */
2308 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */
2309 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_LSB 1
2310 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */
2311 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_MSB 2
2312 /* The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field. */
2313 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_WIDTH 2
2314 /* The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */
2315 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET_MSK 0x00000006
2316 /* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value. */
2317 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_CLR_MSK 0xfffffff9
2318 /* The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field is UNKNOWN. */
2319 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_RESET 0x0
2320 /* Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK field value from a register. */
2321 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_GET(value) (((value) & 0x00000006) >> 1)
2322 /* Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value suitable for setting the register. */
2323 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET(value) (((value) << 1) & 0x00000006)
2324 
2325 /*
2326  * Field : Self-refresh Request - selfrshreq
2327  *
2328  * Write a one to this bit to request the RAM be put into a self refresh state.
2329  * This bit is treated as a static value so the RAM will remain in self-refresh as
2330  * long as this register bit is set to a one. This power down mode can be selected
2331  * for all DRAMs supported by the controller.
2332  *
2333  * Field Access Macros:
2334  *
2335  */
2336 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */
2337 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_LSB 3
2338 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */
2339 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_MSB 3
2340 /* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field. */
2341 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_WIDTH 1
2342 /* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */
2343 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET_MSK 0x00000008
2344 /* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value. */
2345 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_CLR_MSK 0xfffffff7
2346 /* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field is UNKNOWN. */
2347 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_RESET 0x0
2348 /* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ field value from a register. */
2349 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_GET(value) (((value) & 0x00000008) >> 3)
2350 /* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value suitable for setting the register. */
2351 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET(value) (((value) << 3) & 0x00000008)
2352 
2353 /*
2354  * Field : Self-refresh Chip Select Mask - selfrfshmask
2355  *
2356  * Write a one to each bit of this field to have a self refresh request apply to
2357  * both chips.
2358  *
2359  * Field Access Macros:
2360  *
2361  */
2362 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */
2363 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_LSB 4
2364 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */
2365 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_MSB 5
2366 /* The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field. */
2367 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_WIDTH 2
2368 /* The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */
2369 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET_MSK 0x00000030
2370 /* The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value. */
2371 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_CLR_MSK 0xffffffcf
2372 /* The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field is UNKNOWN. */
2373 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_RESET 0x0
2374 /* Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK field value from a register. */
2375 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_GET(value) (((value) & 0x00000030) >> 4)
2376 /* Produces a ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value suitable for setting the register. */
2377 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET(value) (((value) << 4) & 0x00000030)
2378 
2379 #ifndef __ASSEMBLY__
2380 /*
2381  * WARNING: The C register and register group struct declarations are provided for
2382  * convenience and illustrative purposes. They should, however, be used with
2383  * caution as the C language standard provides no guarantees about the alignment or
2384  * atomicity of device memory accesses. The recommended practice for writing
2385  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2386  * alt_write_word() functions.
2387  *
2388  * The struct declaration for register ALT_SDR_CTL_LOWPWREQ.
2389  */
2390 struct ALT_SDR_CTL_LOWPWREQ_s
2391 {
2392  uint32_t deeppwrdnreq : 1; /* Deep Power Down Request */
2393  uint32_t deeppwrdnmask : 2; /* Deep Power Down Chip Select Mask */
2394  uint32_t selfrshreq : 1; /* Self-refresh Request */
2395  uint32_t selfrfshmask : 2; /* Self-refresh Chip Select Mask */
2396  uint32_t : 26; /* *UNDEFINED* */
2397 };
2398 
2399 /* The typedef declaration for register ALT_SDR_CTL_LOWPWREQ. */
2400 typedef volatile struct ALT_SDR_CTL_LOWPWREQ_s ALT_SDR_CTL_LOWPWREQ_t;
2401 #endif /* __ASSEMBLY__ */
2402 
2403 /* The byte offset of the ALT_SDR_CTL_LOWPWREQ register from the beginning of the component. */
2404 #define ALT_SDR_CTL_LOWPWREQ_OFST 0x54
2405 
2406 /*
2407  * Register : Low Power Acknowledge Register - lowpwrack
2408  *
2409  * This register gives the status of the power down commands requested by the Low
2410  * Power Control register.
2411  *
2412  * Register Layout
2413  *
2414  * Bits | Access | Reset | Description
2415  * :-------|:-------|:--------|:----------------------------
2416  * [0] | RW | Unknown | Deep Power Down Acknowledge
2417  * [1] | RW | Unknown | Self-refresh Acknowledge
2418  * [31:2] | ??? | 0x0 | *UNDEFINED*
2419  *
2420  */
2421 /*
2422  * Field : Deep Power Down Acknowledge - deeppwrdnack
2423  *
2424  * This bit is set to a one after a deep power down has been executed
2425  *
2426  * Field Access Macros:
2427  *
2428  */
2429 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */
2430 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_LSB 0
2431 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */
2432 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_MSB 0
2433 /* The width in bits of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field. */
2434 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_WIDTH 1
2435 /* The mask used to set the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */
2436 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET_MSK 0x00000001
2437 /* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value. */
2438 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_CLR_MSK 0xfffffffe
2439 /* The reset value of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field is UNKNOWN. */
2440 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_RESET 0x0
2441 /* Extracts the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK field value from a register. */
2442 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_GET(value) (((value) & 0x00000001) >> 0)
2443 /* Produces a ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value suitable for setting the register. */
2444 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET(value) (((value) << 0) & 0x00000001)
2445 
2446 /*
2447  * Field : Self-refresh Acknowledge - selfrfshack
2448  *
2449  * This bit is a one to indicate that the controller is in a self-refresh state.
2450  *
2451  * Field Access Macros:
2452  *
2453  */
2454 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */
2455 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_LSB 1
2456 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */
2457 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_MSB 1
2458 /* The width in bits of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field. */
2459 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_WIDTH 1
2460 /* The mask used to set the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */
2461 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET_MSK 0x00000002
2462 /* The mask used to clear the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value. */
2463 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_CLR_MSK 0xfffffffd
2464 /* The reset value of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field is UNKNOWN. */
2465 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_RESET 0x0
2466 /* Extracts the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK field value from a register. */
2467 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_GET(value) (((value) & 0x00000002) >> 1)
2468 /* Produces a ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value suitable for setting the register. */
2469 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET(value) (((value) << 1) & 0x00000002)
2470 
2471 #ifndef __ASSEMBLY__
2472 /*
2473  * WARNING: The C register and register group struct declarations are provided for
2474  * convenience and illustrative purposes. They should, however, be used with
2475  * caution as the C language standard provides no guarantees about the alignment or
2476  * atomicity of device memory accesses. The recommended practice for writing
2477  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2478  * alt_write_word() functions.
2479  *
2480  * The struct declaration for register ALT_SDR_CTL_LOWPWRACK.
2481  */
2482 struct ALT_SDR_CTL_LOWPWRACK_s
2483 {
2484  uint32_t deeppwrdnack : 1; /* Deep Power Down Acknowledge */
2485  uint32_t selfrfshack : 1; /* Self-refresh Acknowledge */
2486  uint32_t : 30; /* *UNDEFINED* */
2487 };
2488 
2489 /* The typedef declaration for register ALT_SDR_CTL_LOWPWRACK. */
2490 typedef volatile struct ALT_SDR_CTL_LOWPWRACK_s ALT_SDR_CTL_LOWPWRACK_t;
2491 #endif /* __ASSEMBLY__ */
2492 
2493 /* The byte offset of the ALT_SDR_CTL_LOWPWRACK register from the beginning of the component. */
2494 #define ALT_SDR_CTL_LOWPWRACK_OFST 0x58
2495 
2496 /*
2497  * Register : Static Configuration Register - staticcfg
2498  *
2499  * This register controls configuration values which cannot be updated while
2500  * transactions are flowing.
2501  *
2502  * You should write once to this register with the membl and eccen fields set to
2503  * your desired configuration, and then write to the register again with membl and
2504  * eccen and the applycfg bit set. The applycfg bit is write only.
2505  *
2506  * Register Layout
2507  *
2508  * Bits | Access | Reset | Description
2509  * :-------|:-------|:--------|:----------------------------
2510  * [1:0] | RW | Unknown | Memory Burst Length
2511  * [2] | RW | Unknown | Use ECC Bits As Data
2512  * [3] | RW | Unknown | Apply Configuration Changes
2513  * [31:4] | ??? | 0x0 | *UNDEFINED*
2514  *
2515  */
2516 /*
2517  * Field : Memory Burst Length - membl
2518  *
2519  * This field specifies the DRAM burst length. Write the following values to set
2520  * the a burst length appropriate for the specific DRAM being used. &quot;00&quot;
2521  * for burst length 2, &quot;01&quot; for burst length 4, &quot;10&quot; for burst
2522  * length 8. If you set this, you must also set the membl field in the ctrlcfg
2523  * register.
2524  *
2525  * Field Access Macros:
2526  *
2527  */
2528 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */
2529 #define ALT_SDR_CTL_STATICCFG_MEMBL_LSB 0
2530 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */
2531 #define ALT_SDR_CTL_STATICCFG_MEMBL_MSB 1
2532 /* The width in bits of the ALT_SDR_CTL_STATICCFG_MEMBL register field. */
2533 #define ALT_SDR_CTL_STATICCFG_MEMBL_WIDTH 2
2534 /* The mask used to set the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */
2535 #define ALT_SDR_CTL_STATICCFG_MEMBL_SET_MSK 0x00000003
2536 /* The mask used to clear the ALT_SDR_CTL_STATICCFG_MEMBL register field value. */
2537 #define ALT_SDR_CTL_STATICCFG_MEMBL_CLR_MSK 0xfffffffc
2538 /* The reset value of the ALT_SDR_CTL_STATICCFG_MEMBL register field is UNKNOWN. */
2539 #define ALT_SDR_CTL_STATICCFG_MEMBL_RESET 0x0
2540 /* Extracts the ALT_SDR_CTL_STATICCFG_MEMBL field value from a register. */
2541 #define ALT_SDR_CTL_STATICCFG_MEMBL_GET(value) (((value) & 0x00000003) >> 0)
2542 /* Produces a ALT_SDR_CTL_STATICCFG_MEMBL register field value suitable for setting the register. */
2543 #define ALT_SDR_CTL_STATICCFG_MEMBL_SET(value) (((value) << 0) & 0x00000003)
2544 
2545 /*
2546  * Field : Use ECC Bits As Data - useeccasdata
2547  *
2548  * This field allows the FPGA ports to directly access the extra data bits that are
2549  * normally used to hold the ECC code. The interface width must be set to 24 or 40
2550  * in the dramifwidth register. If you set this, you must clear the eccen field in
2551  * the ctrlcfg register.
2552  *
2553  * Field Access Macros:
2554  *
2555  */
2556 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */
2557 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_LSB 2
2558 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */
2559 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_MSB 2
2560 /* The width in bits of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field. */
2561 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_WIDTH 1
2562 /* The mask used to set the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */
2563 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET_MSK 0x00000004
2564 /* The mask used to clear the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value. */
2565 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_CLR_MSK 0xfffffffb
2566 /* The reset value of the ALT_SDR_CTL_STATICCFG_USEECCASDATA register field is UNKNOWN. */
2567 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_RESET 0x0
2568 /* Extracts the ALT_SDR_CTL_STATICCFG_USEECCASDATA field value from a register. */
2569 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_GET(value) (((value) & 0x00000004) >> 2)
2570 /* Produces a ALT_SDR_CTL_STATICCFG_USEECCASDATA register field value suitable for setting the register. */
2571 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET(value) (((value) << 2) & 0x00000004)
2572 
2573 /*
2574  * Field : Apply Configuration Changes - applycfg
2575  *
2576  * Write with this bit set to apply all the settings loaded in SDR registers to the
2577  * memory interface. This bit is write-only and always returns 0 if read.
2578  *
2579  * Field Access Macros:
2580  *
2581  */
2582 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */
2583 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_LSB 3
2584 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */
2585 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_MSB 3
2586 /* The width in bits of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field. */
2587 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_WIDTH 1
2588 /* The mask used to set the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */
2589 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET_MSK 0x00000008
2590 /* The mask used to clear the ALT_SDR_CTL_STATICCFG_APPLYCFG register field value. */
2591 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_CLR_MSK 0xfffffff7
2592 /* The reset value of the ALT_SDR_CTL_STATICCFG_APPLYCFG register field is UNKNOWN. */
2593 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_RESET 0x0
2594 /* Extracts the ALT_SDR_CTL_STATICCFG_APPLYCFG field value from a register. */
2595 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_GET(value) (((value) & 0x00000008) >> 3)
2596 /* Produces a ALT_SDR_CTL_STATICCFG_APPLYCFG register field value suitable for setting the register. */
2597 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET(value) (((value) << 3) & 0x00000008)
2598 
2599 #ifndef __ASSEMBLY__
2600 /*
2601  * WARNING: The C register and register group struct declarations are provided for
2602  * convenience and illustrative purposes. They should, however, be used with
2603  * caution as the C language standard provides no guarantees about the alignment or
2604  * atomicity of device memory accesses. The recommended practice for writing
2605  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2606  * alt_write_word() functions.
2607  *
2608  * The struct declaration for register ALT_SDR_CTL_STATICCFG.
2609  */
2610 struct ALT_SDR_CTL_STATICCFG_s
2611 {
2612  uint32_t membl : 2; /* Memory Burst Length */
2613  uint32_t useeccasdata : 1; /* Use ECC Bits As Data */
2614  uint32_t applycfg : 1; /* Apply Configuration Changes */
2615  uint32_t : 28; /* *UNDEFINED* */
2616 };
2617 
2618 /* The typedef declaration for register ALT_SDR_CTL_STATICCFG. */
2619 typedef volatile struct ALT_SDR_CTL_STATICCFG_s ALT_SDR_CTL_STATICCFG_t;
2620 #endif /* __ASSEMBLY__ */
2621 
2622 /* The byte offset of the ALT_SDR_CTL_STATICCFG register from the beginning of the component. */
2623 #define ALT_SDR_CTL_STATICCFG_OFST 0x5c
2624 
2625 /*
2626  * Register : Memory Controller Width Register - ctrlwidth
2627  *
2628  * This register controls the width of the physical DRAM interface.
2629  *
2630  * Register Layout
2631  *
2632  * Bits | Access | Reset | Description
2633  * :-------|:-------|:--------|:---------------------------
2634  * [1:0] | RW | Unknown | Controller Interface Width
2635  * [31:2] | ??? | 0x0 | *UNDEFINED*
2636  *
2637  */
2638 /*
2639  * Field : Controller Interface Width - ctrlwidth
2640  *
2641  * Specifies controller DRAM interface width, with the following encoding.
2642  * &quot;00&quot; for 8-bit, &quot;01&quot; for 16-bit (no ECC) or 24-bit (ECC
2643  * enabled), &quot;10&quot; for 32-bit (no ECC) or 40-bit (ECC enabled). You must
2644  * also program the dramifwidth register.
2645  *
2646  * Field Access Macros:
2647  *
2648  */
2649 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */
2650 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_LSB 0
2651 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */
2652 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_MSB 1
2653 /* The width in bits of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field. */
2654 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_WIDTH 2
2655 /* The mask used to set the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */
2656 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET_MSK 0x00000003
2657 /* The mask used to clear the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value. */
2658 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_CLR_MSK 0xfffffffc
2659 /* The reset value of the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field is UNKNOWN. */
2660 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_RESET 0x0
2661 /* Extracts the ALT_SDR_CTL_CTLWIDTH_CTLWIDTH field value from a register. */
2662 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_GET(value) (((value) & 0x00000003) >> 0)
2663 /* Produces a ALT_SDR_CTL_CTLWIDTH_CTLWIDTH register field value suitable for setting the register. */
2664 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET(value) (((value) << 0) & 0x00000003)
2665 
2666 #ifndef __ASSEMBLY__
2667 /*
2668  * WARNING: The C register and register group struct declarations are provided for
2669  * convenience and illustrative purposes. They should, however, be used with
2670  * caution as the C language standard provides no guarantees about the alignment or
2671  * atomicity of device memory accesses. The recommended practice for writing
2672  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2673  * alt_write_word() functions.
2674  *
2675  * The struct declaration for register ALT_SDR_CTL_CTLWIDTH.
2676  */
2677 struct ALT_SDR_CTL_CTLWIDTH_s
2678 {
2679  uint32_t ctrlwidth : 2; /* Controller Interface Width */
2680  uint32_t : 30; /* *UNDEFINED* */
2681 };
2682 
2683 /* The typedef declaration for register ALT_SDR_CTL_CTLWIDTH. */
2684 typedef volatile struct ALT_SDR_CTL_CTLWIDTH_s ALT_SDR_CTL_CTLWIDTH_t;
2685 #endif /* __ASSEMBLY__ */
2686 
2687 /* The byte offset of the ALT_SDR_CTL_CTLWIDTH register from the beginning of the component. */
2688 #define ALT_SDR_CTL_CTLWIDTH_OFST 0x60
2689 
2690 /*
2691  * Register : Port Configuration Register - portcfg
2692  *
2693  * This register should be set to a zero in any bit which corresponds to a port
2694  * which does mostly sequential memory accesses. For ports with highly random
2695  * accesses, the bit should be set to a one.
2696  *
2697  * Register Layout
2698  *
2699  * Bits | Access | Reset | Description
2700  * :--------|:-------|:--------|:----------------------
2701  * [9:0] | ??? | Unknown | *UNDEFINED*
2702  * [19:10] | RW | Unknown | Auto-precharge Enable
2703  * [31:20] | ??? | 0x0 | *UNDEFINED*
2704  *
2705  */
2706 /*
2707  * Field : Auto-precharge Enable - autopchen
2708  *
2709  * One bit per control port. Set bit N to a 1 to have the controller request an
2710  * automatic precharge following bus command completion (close the row
2711  * automatically). Set to a zero to request that the controller attempt to keep a
2712  * row open. For random dominated operations this register should be set to a 1
2713  * for all active ports.
2714  *
2715  * Field Access Macros:
2716  *
2717  */
2718 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */
2719 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_LSB 10
2720 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */
2721 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_MSB 19
2722 /* The width in bits of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field. */
2723 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_WIDTH 10
2724 /* The mask used to set the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */
2725 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET_MSK 0x000ffc00
2726 /* The mask used to clear the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value. */
2727 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_CLR_MSK 0xfff003ff
2728 /* The reset value of the ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field is UNKNOWN. */
2729 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_RESET 0x0
2730 /* Extracts the ALT_SDR_CTL_PORTCFG_AUTOPCHEN field value from a register. */
2731 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_GET(value) (((value) & 0x000ffc00) >> 10)
2732 /* Produces a ALT_SDR_CTL_PORTCFG_AUTOPCHEN register field value suitable for setting the register. */
2733 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET(value) (((value) << 10) & 0x000ffc00)
2734 
2735 #ifndef __ASSEMBLY__
2736 /*
2737  * WARNING: The C register and register group struct declarations are provided for
2738  * convenience and illustrative purposes. They should, however, be used with
2739  * caution as the C language standard provides no guarantees about the alignment or
2740  * atomicity of device memory accesses. The recommended practice for writing
2741  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2742  * alt_write_word() functions.
2743  *
2744  * The struct declaration for register ALT_SDR_CTL_PORTCFG.
2745  */
2746 struct ALT_SDR_CTL_PORTCFG_s
2747 {
2748  uint32_t : 10; /* *UNDEFINED* */
2749  uint32_t autopchen : 10; /* Auto-precharge Enable */
2750  uint32_t : 12; /* *UNDEFINED* */
2751 };
2752 
2753 /* The typedef declaration for register ALT_SDR_CTL_PORTCFG. */
2754 typedef volatile struct ALT_SDR_CTL_PORTCFG_s ALT_SDR_CTL_PORTCFG_t;
2755 #endif /* __ASSEMBLY__ */
2756 
2757 /* The byte offset of the ALT_SDR_CTL_PORTCFG register from the beginning of the component. */
2758 #define ALT_SDR_CTL_PORTCFG_OFST 0x7c
2759 
2760 /*
2761  * Register : FPGA Ports Reset Control Register - fpgaportrst
2762  *
2763  * This register implements functionality to allow the CPU to control when the MPFE
2764  * will enable the ports to the FPGA fabric.
2765  *
2766  * Register Layout
2767  *
2768  * Bits | Access | Reset | Description
2769  * :--------|:-------|:--------|:-------------------
2770  * [13:0] | RW | Unknown | Port Reset Control
2771  * [31:14] | ??? | 0x0 | *UNDEFINED*
2772  *
2773  */
2774 /*
2775  * Field : Port Reset Control - portrstn
2776  *
2777  * This register should be written to with a 1 to enable the selected FPGA port to
2778  * exit reset. Writing a bit to a zero will stretch the port reset until the
2779  * register is written. Read data ports are connected to bits 3:0, with read data
2780  * port 0 at bit 0 to read data port 3 at bit 3. Write data ports 0 to 3 are mapped
2781  * to 4 to 7, with write data port 0 connected to bit 4 to write data port 3 at bit
2782  * 7. Command ports are connected to bits 8 to 13, with command port 0 at bit 8 to
2783  * command port 5 at bit 13. Expected usage would be to set all the bits at the
2784  * same time but setting some bits to a zero and others to a one is supported.
2785  *
2786  * Field Access Macros:
2787  *
2788  */
2789 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */
2790 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_LSB 0
2791 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */
2792 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSB 13
2793 /* The width in bits of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field. */
2794 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_WIDTH 14
2795 /* The mask used to set the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */
2796 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET_MSK 0x00003fff
2797 /* The mask used to clear the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value. */
2798 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_CLR_MSK 0xffffc000
2799 /* The reset value of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field is UNKNOWN. */
2800 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_RESET 0x0
2801 /* Extracts the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN field value from a register. */
2802 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_GET(value) (((value) & 0x00003fff) >> 0)
2803 /* Produces a ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value suitable for setting the register. */
2804 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET(value) (((value) << 0) & 0x00003fff)
2805 
2806 #ifndef __ASSEMBLY__
2807 /*
2808  * WARNING: The C register and register group struct declarations are provided for
2809  * convenience and illustrative purposes. They should, however, be used with
2810  * caution as the C language standard provides no guarantees about the alignment or
2811  * atomicity of device memory accesses. The recommended practice for writing
2812  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2813  * alt_write_word() functions.
2814  *
2815  * The struct declaration for register ALT_SDR_CTL_FPGAPORTRST.
2816  */
2817 struct ALT_SDR_CTL_FPGAPORTRST_s
2818 {
2819  uint32_t portrstn : 14; /* Port Reset Control */
2820  uint32_t : 18; /* *UNDEFINED* */
2821 };
2822 
2823 /* The typedef declaration for register ALT_SDR_CTL_FPGAPORTRST. */
2824 typedef volatile struct ALT_SDR_CTL_FPGAPORTRST_s ALT_SDR_CTL_FPGAPORTRST_t;
2825 #endif /* __ASSEMBLY__ */
2826 
2827 /* The byte offset of the ALT_SDR_CTL_FPGAPORTRST register from the beginning of the component. */
2828 #define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80
2829 
2830 /*
2831  * Register : Memory Protection Port Default Register - protportdefault
2832  *
2833  * This register controls the default protection assignment for a port. Ports
2834  * which have explicit rules which define regions which are illegal to access
2835  * should set the bits to pass by default. Ports which have explicit rules which
2836  * define legal areas should set the bit to force all transactions to fail.
2837  * Leaving this register to all zeros should be used for systems which do not
2838  * desire any protection from the memory controller.
2839  *
2840  * Register Layout
2841  *
2842  * Bits | Access | Reset | Description
2843  * :--------|:-------|:--------|:--------------------
2844  * [9:0] | RW | Unknown | Port Default Action
2845  * [31:10] | ??? | 0x0 | *UNDEFINED*
2846  *
2847  */
2848 /*
2849  * Field : Port Default Action - portdefault
2850  *
2851  * Determines the default action for a transactions from a port. Set a bit to a
2852  * zero to indicate that all accesses from the port should pass by default, set a
2853  * bit to a one if the default protection is to fail the access.
2854  *
2855  * Field Access Macros:
2856  *
2857  */
2858 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */
2859 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_LSB 0
2860 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */
2861 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_MSB 9
2862 /* The width in bits of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field. */
2863 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_WIDTH 10
2864 /* The mask used to set the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */
2865 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET_MSK 0x000003ff
2866 /* The mask used to clear the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value. */
2867 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_CLR_MSK 0xfffffc00
2868 /* The reset value of the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field is UNKNOWN. */
2869 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_RESET 0x0
2870 /* Extracts the ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT field value from a register. */
2871 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_GET(value) (((value) & 0x000003ff) >> 0)
2872 /* Produces a ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT register field value suitable for setting the register. */
2873 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET(value) (((value) << 0) & 0x000003ff)
2874 
2875 #ifndef __ASSEMBLY__
2876 /*
2877  * WARNING: The C register and register group struct declarations are provided for
2878  * convenience and illustrative purposes. They should, however, be used with
2879  * caution as the C language standard provides no guarantees about the alignment or
2880  * atomicity of device memory accesses. The recommended practice for writing
2881  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2882  * alt_write_word() functions.
2883  *
2884  * The struct declaration for register ALT_SDR_CTL_PROTPORTDEFAULT.
2885  */
2886 struct ALT_SDR_CTL_PROTPORTDEFAULT_s
2887 {
2888  uint32_t portdefault : 10; /* Port Default Action */
2889  uint32_t : 22; /* *UNDEFINED* */
2890 };
2891 
2892 /* The typedef declaration for register ALT_SDR_CTL_PROTPORTDEFAULT. */
2893 typedef volatile struct ALT_SDR_CTL_PROTPORTDEFAULT_s ALT_SDR_CTL_PROTPORTDEFAULT_t;
2894 #endif /* __ASSEMBLY__ */
2895 
2896 /* The byte offset of the ALT_SDR_CTL_PROTPORTDEFAULT register from the beginning of the component. */
2897 #define ALT_SDR_CTL_PROTPORTDEFAULT_OFST 0x8c
2898 
2899 /*
2900  * Register : Memory Protection Address Register - protruleaddr
2901  *
2902  * This register is used to control the memory protection for port 0 transactions.
2903  * Address ranges can either be used to allow access to memory regions or disallow
2904  * access to memory regions. If trustzone is being used, access can be enabled for
2905  * protected transactions or disabled for unprotected transactions. The default
2906  * state of this register is to allow all access. Address values used for
2907  * protection are only physical addresses.
2908  *
2909  * Register Layout
2910  *
2911  * Bits | Access | Reset | Description
2912  * :--------|:-------|:--------|:-------------
2913  * [11:0] | RW | Unknown | Low Address
2914  * [23:12] | RW | Unknown | High Address
2915  * [31:24] | ??? | 0x0 | *UNDEFINED*
2916  *
2917  */
2918 /*
2919  * Field : Low Address - lowaddr
2920  *
2921  * Lower 12 bits of the address for a check. Address is compared to be less than
2922  * or equal to the address of a transaction. Note that since AXI transactions
2923  * cannot cross a 4K byte boundary, the transaction start and transaction end
2924  * address must also fall within the same 1MByte block pointed to by this address
2925  * pointer.
2926  *
2927  * Field Access Macros:
2928  *
2929  */
2930 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */
2931 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_LSB 0
2932 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */
2933 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_MSB 11
2934 /* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field. */
2935 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_WIDTH 12
2936 /* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */
2937 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET_MSK 0x00000fff
2938 /* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value. */
2939 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_CLR_MSK 0xfffff000
2940 /* The reset value of the ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field is UNKNOWN. */
2941 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_RESET 0x0
2942 /* Extracts the ALT_SDR_CTL_PROTRULEADDR_LOWADDR field value from a register. */
2943 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_GET(value) (((value) & 0x00000fff) >> 0)
2944 /* Produces a ALT_SDR_CTL_PROTRULEADDR_LOWADDR register field value suitable for setting the register. */
2945 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET(value) (((value) << 0) & 0x00000fff)
2946 
2947 /*
2948  * Field : High Address - highaddr
2949  *
2950  * Upper 12 bits of the address for a check. Address is compared to be greater
2951  * than or equal to the address of a transaction. Note that since AXI transactions
2952  * cannot cross a 4K byte boundary, the transaction start and transaction end
2953  * address must also fall within the same 1MByte block pointed to by this address
2954  * pointer.
2955  *
2956  * Field Access Macros:
2957  *
2958  */
2959 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */
2960 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_LSB 12
2961 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */
2962 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_MSB 23
2963 /* The width in bits of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field. */
2964 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_WIDTH 12
2965 /* The mask used to set the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */
2966 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET_MSK 0x00fff000
2967 /* The mask used to clear the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value. */
2968 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_CLR_MSK 0xff000fff
2969 /* The reset value of the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field is UNKNOWN. */
2970 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_RESET 0x0
2971 /* Extracts the ALT_SDR_CTL_PROTRULEADDR_HIGHADDR field value from a register. */
2972 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_GET(value) (((value) & 0x00fff000) >> 12)
2973 /* Produces a ALT_SDR_CTL_PROTRULEADDR_HIGHADDR register field value suitable for setting the register. */
2974 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET(value) (((value) << 12) & 0x00fff000)
2975 
2976 #ifndef __ASSEMBLY__
2977 /*
2978  * WARNING: The C register and register group struct declarations are provided for
2979  * convenience and illustrative purposes. They should, however, be used with
2980  * caution as the C language standard provides no guarantees about the alignment or
2981  * atomicity of device memory accesses. The recommended practice for writing
2982  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2983  * alt_write_word() functions.
2984  *
2985  * The struct declaration for register ALT_SDR_CTL_PROTRULEADDR.
2986  */
2987 struct ALT_SDR_CTL_PROTRULEADDR_s
2988 {
2989  uint32_t lowaddr : 12; /* Low Address */
2990  uint32_t highaddr : 12; /* High Address */
2991  uint32_t : 8; /* *UNDEFINED* */
2992 };
2993 
2994 /* The typedef declaration for register ALT_SDR_CTL_PROTRULEADDR. */
2995 typedef volatile struct ALT_SDR_CTL_PROTRULEADDR_s ALT_SDR_CTL_PROTRULEADDR_t;
2996 #endif /* __ASSEMBLY__ */
2997 
2998 /* The byte offset of the ALT_SDR_CTL_PROTRULEADDR register from the beginning of the component. */
2999 #define ALT_SDR_CTL_PROTRULEADDR_OFST 0x90
3000 
3001 /*
3002  * Register : Memory Protection ID Register - protruleid
3003  *
3004  *
3005  * Register Layout
3006  *
3007  * Bits | Access | Reset | Description
3008  * :--------|:-------|:--------|:------------
3009  * [11:0] | RW | Unknown | Low ID
3010  * [23:12] | RW | Unknown | High ID
3011  * [31:24] | ??? | 0x0 | *UNDEFINED*
3012  *
3013  */
3014 /*
3015  * Field : Low ID - lowid
3016  *
3017  * AxID for the protection rule. Incoming AxID needs to be greater than or equal
3018  * to this value. For all AxIDs from a port, AxID high should be programmed to all
3019  * ones.
3020  *
3021  * Field Access Macros:
3022  *
3023  */
3024 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */
3025 #define ALT_SDR_CTL_PROTRULEID_LOWID_LSB 0
3026 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */
3027 #define ALT_SDR_CTL_PROTRULEID_LOWID_MSB 11
3028 /* The width in bits of the ALT_SDR_CTL_PROTRULEID_LOWID register field. */
3029 #define ALT_SDR_CTL_PROTRULEID_LOWID_WIDTH 12
3030 /* The mask used to set the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */
3031 #define ALT_SDR_CTL_PROTRULEID_LOWID_SET_MSK 0x00000fff
3032 /* The mask used to clear the ALT_SDR_CTL_PROTRULEID_LOWID register field value. */
3033 #define ALT_SDR_CTL_PROTRULEID_LOWID_CLR_MSK 0xfffff000
3034 /* The reset value of the ALT_SDR_CTL_PROTRULEID_LOWID register field is UNKNOWN. */
3035 #define ALT_SDR_CTL_PROTRULEID_LOWID_RESET 0x0
3036 /* Extracts the ALT_SDR_CTL_PROTRULEID_LOWID field value from a register. */
3037 #define ALT_SDR_CTL_PROTRULEID_LOWID_GET(value) (((value) & 0x00000fff) >> 0)
3038 /* Produces a ALT_SDR_CTL_PROTRULEID_LOWID register field value suitable for setting the register. */
3039 #define ALT_SDR_CTL_PROTRULEID_LOWID_SET(value) (((value) << 0) & 0x00000fff)
3040 
3041 /*
3042  * Field : High ID - highid
3043  *
3044  * AxID for the protection rule. Incoming AxID needs to be less than or equal to
3045  * this value. For all AxIDs from a port, AxID high should be programmed to all
3046  * ones.
3047  *
3048  * Field Access Macros:
3049  *
3050  */
3051 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */
3052 #define ALT_SDR_CTL_PROTRULEID_HIGHID_LSB 12
3053 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */
3054 #define ALT_SDR_CTL_PROTRULEID_HIGHID_MSB 23
3055 /* The width in bits of the ALT_SDR_CTL_PROTRULEID_HIGHID register field. */
3056 #define ALT_SDR_CTL_PROTRULEID_HIGHID_WIDTH 12
3057 /* The mask used to set the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */
3058 #define ALT_SDR_CTL_PROTRULEID_HIGHID_SET_MSK 0x00fff000
3059 /* The mask used to clear the ALT_SDR_CTL_PROTRULEID_HIGHID register field value. */
3060 #define ALT_SDR_CTL_PROTRULEID_HIGHID_CLR_MSK 0xff000fff
3061 /* The reset value of the ALT_SDR_CTL_PROTRULEID_HIGHID register field is UNKNOWN. */
3062 #define ALT_SDR_CTL_PROTRULEID_HIGHID_RESET 0x0
3063 /* Extracts the ALT_SDR_CTL_PROTRULEID_HIGHID field value from a register. */
3064 #define ALT_SDR_CTL_PROTRULEID_HIGHID_GET(value) (((value) & 0x00fff000) >> 12)
3065 /* Produces a ALT_SDR_CTL_PROTRULEID_HIGHID register field value suitable for setting the register. */
3066 #define ALT_SDR_CTL_PROTRULEID_HIGHID_SET(value) (((value) << 12) & 0x00fff000)
3067 
3068 #ifndef __ASSEMBLY__
3069 /*
3070  * WARNING: The C register and register group struct declarations are provided for
3071  * convenience and illustrative purposes. They should, however, be used with
3072  * caution as the C language standard provides no guarantees about the alignment or
3073  * atomicity of device memory accesses. The recommended practice for writing
3074  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3075  * alt_write_word() functions.
3076  *
3077  * The struct declaration for register ALT_SDR_CTL_PROTRULEID.
3078  */
3079 struct ALT_SDR_CTL_PROTRULEID_s
3080 {
3081  uint32_t lowid : 12; /* Low ID */
3082  uint32_t highid : 12; /* High ID */
3083  uint32_t : 8; /* *UNDEFINED* */
3084 };
3085 
3086 /* The typedef declaration for register ALT_SDR_CTL_PROTRULEID. */
3087 typedef volatile struct ALT_SDR_CTL_PROTRULEID_s ALT_SDR_CTL_PROTRULEID_t;
3088 #endif /* __ASSEMBLY__ */
3089 
3090 /* The byte offset of the ALT_SDR_CTL_PROTRULEID register from the beginning of the component. */
3091 #define ALT_SDR_CTL_PROTRULEID_OFST 0x94
3092 
3093 /*
3094  * Register : Memory Protection Rule Data Register - protruledata
3095  *
3096  *
3097  * Register Layout
3098  *
3099  * Bits | Access | Reset | Description
3100  * :--------|:-------|:--------|:----------------------
3101  * [1:0] | RW | Unknown | Security Bit Behavior
3102  * [2] | RW | Unknown | Valid Rule
3103  * [12:3] | RW | Unknown | Port Mask
3104  * [13] | RW | Unknown | Rule Results
3105  * [31:14] | ??? | 0x0 | *UNDEFINED*
3106  *
3107  */
3108 /*
3109  * Field : Security Bit Behavior - security
3110  *
3111  * A value of 2'b00 will make the rule apply to secure transactions.
3112  *
3113  * A value of 2'b01 will make the rule apply to non-secure transactions.
3114  *
3115  * A value of 2'b10 or 2'b11 will make the rule apply to secure and non-secure
3116  * transactions.
3117  *
3118  * Field Access Macros:
3119  *
3120  */
3121 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */
3122 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_LSB 0
3123 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */
3124 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_MSB 1
3125 /* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field. */
3126 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_WIDTH 2
3127 /* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */
3128 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET_MSK 0x00000003
3129 /* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value. */
3130 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_CLR_MSK 0xfffffffc
3131 /* The reset value of the ALT_SDR_CTL_PROTRULEDATA_SECURITY register field is UNKNOWN. */
3132 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_RESET 0x0
3133 /* Extracts the ALT_SDR_CTL_PROTRULEDATA_SECURITY field value from a register. */
3134 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_GET(value) (((value) & 0x00000003) >> 0)
3135 /* Produces a ALT_SDR_CTL_PROTRULEDATA_SECURITY register field value suitable for setting the register. */
3136 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET(value) (((value) << 0) & 0x00000003)
3137 
3138 /*
3139  * Field : Valid Rule - validrule
3140  *
3141  * Set to bit to a one to make a rule valid, set to a zero to invalidate a rule.
3142  *
3143  * Field Access Macros:
3144  *
3145  */
3146 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */
3147 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_LSB 2
3148 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */
3149 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_MSB 2
3150 /* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field. */
3151 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_WIDTH 1
3152 /* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */
3153 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET_MSK 0x00000004
3154 /* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value. */
3155 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_CLR_MSK 0xfffffffb
3156 /* The reset value of the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field is UNKNOWN. */
3157 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_RESET 0x0
3158 /* Extracts the ALT_SDR_CTL_PROTRULEDATA_VALIDRULE field value from a register. */
3159 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_GET(value) (((value) & 0x00000004) >> 2)
3160 /* Produces a ALT_SDR_CTL_PROTRULEDATA_VALIDRULE register field value suitable for setting the register. */
3161 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET(value) (((value) << 2) & 0x00000004)
3162 
3163 /*
3164  * Field : Port Mask - portmask
3165  *
3166  * Set bit x to a one to have this rule apply to port x, set bit x to a zero to
3167  * have the rule not apply to a port.&#10;Note that port 0-port 5 are the FPGA
3168  * fabric ports, port 6 is L3 read, port 7 is CPU read, port 8 is L3 write, port 9
3169  * is CPU write.
3170  *
3171  * Field Access Macros:
3172  *
3173  */
3174 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */
3175 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_LSB 3
3176 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */
3177 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_MSB 12
3178 /* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field. */
3179 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_WIDTH 10
3180 /* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */
3181 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET_MSK 0x00001ff8
3182 /* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value. */
3183 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_CLR_MSK 0xffffe007
3184 /* The reset value of the ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field is UNKNOWN. */
3185 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_RESET 0x0
3186 /* Extracts the ALT_SDR_CTL_PROTRULEDATA_PORTMSK field value from a register. */
3187 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_GET(value) (((value) & 0x00001ff8) >> 3)
3188 /* Produces a ALT_SDR_CTL_PROTRULEDATA_PORTMSK register field value suitable for setting the register. */
3189 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET(value) (((value) << 3) & 0x00001ff8)
3190 
3191 /*
3192  * Field : Rule Results - ruleresult
3193  *
3194  * Set this bit to a one to force a protection failure, zero to allow the access
3195  * the succeed
3196  *
3197  * Field Access Macros:
3198  *
3199  */
3200 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */
3201 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_LSB 13
3202 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */
3203 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_MSB 13
3204 /* The width in bits of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field. */
3205 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_WIDTH 1
3206 /* The mask used to set the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */
3207 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET_MSK 0x00002000
3208 /* The mask used to clear the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value. */
3209 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_CLR_MSK 0xffffdfff
3210 /* The reset value of the ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field is UNKNOWN. */
3211 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_RESET 0x0
3212 /* Extracts the ALT_SDR_CTL_PROTRULEDATA_RULERESULT field value from a register. */
3213 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_GET(value) (((value) & 0x00002000) >> 13)
3214 /* Produces a ALT_SDR_CTL_PROTRULEDATA_RULERESULT register field value suitable for setting the register. */
3215 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET(value) (((value) << 13) & 0x00002000)
3216 
3217 #ifndef __ASSEMBLY__
3218 /*
3219  * WARNING: The C register and register group struct declarations are provided for
3220  * convenience and illustrative purposes. They should, however, be used with
3221  * caution as the C language standard provides no guarantees about the alignment or
3222  * atomicity of device memory accesses. The recommended practice for writing
3223  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3224  * alt_write_word() functions.
3225  *
3226  * The struct declaration for register ALT_SDR_CTL_PROTRULEDATA.
3227  */
3228 struct ALT_SDR_CTL_PROTRULEDATA_s
3229 {
3230  uint32_t security : 2; /* Security Bit Behavior */
3231  uint32_t validrule : 1; /* Valid Rule */
3232  uint32_t portmask : 10; /* Port Mask */
3233  uint32_t ruleresult : 1; /* Rule Results */
3234  uint32_t : 18; /* *UNDEFINED* */
3235 };
3236 
3237 /* The typedef declaration for register ALT_SDR_CTL_PROTRULEDATA. */
3238 typedef volatile struct ALT_SDR_CTL_PROTRULEDATA_s ALT_SDR_CTL_PROTRULEDATA_t;
3239 #endif /* __ASSEMBLY__ */
3240 
3241 /* The byte offset of the ALT_SDR_CTL_PROTRULEDATA register from the beginning of the component. */
3242 #define ALT_SDR_CTL_PROTRULEDATA_OFST 0x98
3243 
3244 /*
3245  * Register : Memory Protection Rule Read-Write Register - protrulerdwr
3246  *
3247  * This register is used to perform read and write operations to the internal
3248  * protection table.
3249  *
3250  * Register Layout
3251  *
3252  * Bits | Access | Reset | Description
3253  * :-------|:-------|:--------|:------------
3254  * [4:0] | RW | Unknown | Rule Offset
3255  * [5] | RW | Unknown | Rule Write
3256  * [6] | RW | Unknown | Rule Read
3257  * [31:7] | ??? | 0x0 | *UNDEFINED*
3258  *
3259  */
3260 /*
3261  * Field : Rule Offset - ruleoffset
3262  *
3263  * This field defines which of the 20 rules in the protection table you want to
3264  * read or write.
3265  *
3266  * Field Access Macros:
3267  *
3268  */
3269 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */
3270 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_LSB 0
3271 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */
3272 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_MSB 4
3273 /* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field. */
3274 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_WIDTH 5
3275 /* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */
3276 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET_MSK 0x0000001f
3277 /* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value. */
3278 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_CLR_MSK 0xffffffe0
3279 /* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field is UNKNOWN. */
3280 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_RESET 0x0
3281 /* Extracts the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET field value from a register. */
3282 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_GET(value) (((value) & 0x0000001f) >> 0)
3283 /* Produces a ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value suitable for setting the register. */
3284 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET(value) (((value) << 0) & 0x0000001f)
3285 
3286 /*
3287  * Field : Rule Write - writerule
3288  *
3289  * Write to this bit to have the memory_prot_data register to the table at the
3290  * offset specified by port_offset. Bit automatically clears after a single cycle
3291  * and the write operation is complete.
3292  *
3293  * Field Access Macros:
3294  *
3295  */
3296 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */
3297 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_LSB 5
3298 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */
3299 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_MSB 5
3300 /* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field. */
3301 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_WIDTH 1
3302 /* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */
3303 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET_MSK 0x00000020
3304 /* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value. */
3305 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_CLR_MSK 0xffffffdf
3306 /* The reset value of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field is UNKNOWN. */
3307 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_RESET 0x0
3308 /* Extracts the ALT_SDR_CTL_PROTRULERDWR_WRRULE field value from a register. */
3309 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_GET(value) (((value) & 0x00000020) >> 5)
3310 /* Produces a ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value suitable for setting the register. */
3311 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET(value) (((value) << 5) & 0x00000020)
3312 
3313 /*
3314  * Field : Rule Read - readrule
3315  *
3316  * Write to this bit to have the memory_prot_data register loaded with the value
3317  * from the internal protection table at offset. Table value will be loaded before
3318  * a rdy is returned so read data from the register will be correct for any follow-
3319  * on reads to the memory_prot_data register.
3320  *
3321  * Field Access Macros:
3322  *
3323  */
3324 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */
3325 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_LSB 6
3326 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */
3327 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_MSB 6
3328 /* The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field. */
3329 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_WIDTH 1
3330 /* The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */
3331 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET_MSK 0x00000040
3332 /* The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value. */
3333 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_CLR_MSK 0xffffffbf
3334 /* The reset value of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field is UNKNOWN. */
3335 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_RESET 0x0
3336 /* Extracts the ALT_SDR_CTL_PROTRULERDWR_RDRULE field value from a register. */
3337 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_GET(value) (((value) & 0x00000040) >> 6)
3338 /* Produces a ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value suitable for setting the register. */
3339 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET(value) (((value) << 6) & 0x00000040)
3340 
3341 #ifndef __ASSEMBLY__
3342 /*
3343  * WARNING: The C register and register group struct declarations are provided for
3344  * convenience and illustrative purposes. They should, however, be used with
3345  * caution as the C language standard provides no guarantees about the alignment or
3346  * atomicity of device memory accesses. The recommended practice for writing
3347  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3348  * alt_write_word() functions.
3349  *
3350  * The struct declaration for register ALT_SDR_CTL_PROTRULERDWR.
3351  */
3352 struct ALT_SDR_CTL_PROTRULERDWR_s
3353 {
3354  uint32_t ruleoffset : 5; /* Rule Offset */
3355  uint32_t writerule : 1; /* Rule Write */
3356  uint32_t readrule : 1; /* Rule Read */
3357  uint32_t : 25; /* *UNDEFINED* */
3358 };
3359 
3360 /* The typedef declaration for register ALT_SDR_CTL_PROTRULERDWR. */
3361 typedef volatile struct ALT_SDR_CTL_PROTRULERDWR_s ALT_SDR_CTL_PROTRULERDWR_t;
3362 #endif /* __ASSEMBLY__ */
3363 
3364 /* The byte offset of the ALT_SDR_CTL_PROTRULERDWR register from the beginning of the component. */
3365 #define ALT_SDR_CTL_PROTRULERDWR_OFST 0x9c
3366 
3367 /*
3368  * Register : QOS Control Register - qoslowpri
3369  *
3370  * This register controls the mapping of AXI4 QOS received from the FPGA fabric to
3371  * the internal priority used for traffic prioritization.
3372  *
3373  * Register Layout
3374  *
3375  * Bits | Access | Reset | Description
3376  * :--------|:-------|:--------|:-----------------------
3377  * [19:0] | RW | Unknown | Low Priority QoS Value
3378  * [31:20] | ??? | 0x0 | *UNDEFINED*
3379  *
3380  */
3381 /*
3382  * Field : Low Priority QoS Value - lowpriorityval
3383  *
3384  * This 20 bit field is a 2 bit field for each of the 10 ports. The field used for
3385  * each port in this register controls the priority used for a port
3386  *
3387  * Field Access Macros:
3388  *
3389  */
3390 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */
3391 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_LSB 0
3392 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */
3393 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_MSB 19
3394 /* The width in bits of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field. */
3395 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_WIDTH 20
3396 /* The mask used to set the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */
3397 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET_MSK 0x000fffff
3398 /* The mask used to clear the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value. */
3399 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_CLR_MSK 0xfff00000
3400 /* The reset value of the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field is UNKNOWN. */
3401 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_RESET 0x0
3402 /* Extracts the ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL field value from a register. */
3403 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0)
3404 /* Produces a ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL register field value suitable for setting the register. */
3405 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff)
3406 
3407 #ifndef __ASSEMBLY__
3408 /*
3409  * WARNING: The C register and register group struct declarations are provided for
3410  * convenience and illustrative purposes. They should, however, be used with
3411  * caution as the C language standard provides no guarantees about the alignment or
3412  * atomicity of device memory accesses. The recommended practice for writing
3413  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3414  * alt_write_word() functions.
3415  *
3416  * The struct declaration for register ALT_SDR_CTL_QOSLOWPRI.
3417  */
3418 struct ALT_SDR_CTL_QOSLOWPRI_s
3419 {
3420  uint32_t lowpriorityval : 20; /* Low Priority QoS Value */
3421  uint32_t : 12; /* *UNDEFINED* */
3422 };
3423 
3424 /* The typedef declaration for register ALT_SDR_CTL_QOSLOWPRI. */
3425 typedef volatile struct ALT_SDR_CTL_QOSLOWPRI_s ALT_SDR_CTL_QOSLOWPRI_t;
3426 #endif /* __ASSEMBLY__ */
3427 
3428 /* The byte offset of the ALT_SDR_CTL_QOSLOWPRI register from the beginning of the component. */
3429 #define ALT_SDR_CTL_QOSLOWPRI_OFST 0xa0
3430 
3431 /*
3432  * Register : qoshighpri Register - qoshighpri
3433  *
3434  *
3435  * Register Layout
3436  *
3437  * Bits | Access | Reset | Description
3438  * :--------|:-------|:--------|:------------------------
3439  * [19:0] | RW | Unknown | High Priority QoS Value
3440  * [31:20] | ??? | 0x0 | *UNDEFINED*
3441  *
3442  */
3443 /*
3444  * Field : High Priority QoS Value - highpriorityval
3445  *
3446  * This 20 bit field is a 2 bit field for each of the 10 ports. The field used for
3447  * each port in this register controls the priority used for a port
3448  *
3449  * Field Access Macros:
3450  *
3451  */
3452 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */
3453 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_LSB 0
3454 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */
3455 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_MSB 19
3456 /* The width in bits of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field. */
3457 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_WIDTH 20
3458 /* The mask used to set the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */
3459 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET_MSK 0x000fffff
3460 /* The mask used to clear the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value. */
3461 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_CLR_MSK 0xfff00000
3462 /* The reset value of the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field is UNKNOWN. */
3463 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_RESET 0x0
3464 /* Extracts the ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL field value from a register. */
3465 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0)
3466 /* Produces a ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL register field value suitable for setting the register. */
3467 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff)
3468 
3469 #ifndef __ASSEMBLY__
3470 /*
3471  * WARNING: The C register and register group struct declarations are provided for
3472  * convenience and illustrative purposes. They should, however, be used with
3473  * caution as the C language standard provides no guarantees about the alignment or
3474  * atomicity of device memory accesses. The recommended practice for writing
3475  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3476  * alt_write_word() functions.
3477  *
3478  * The struct declaration for register ALT_SDR_CTL_QOSHIGHPRI.
3479  */
3480 struct ALT_SDR_CTL_QOSHIGHPRI_s
3481 {
3482  uint32_t highpriorityval : 20; /* High Priority QoS Value */
3483  uint32_t : 12; /* *UNDEFINED* */
3484 };
3485 
3486 /* The typedef declaration for register ALT_SDR_CTL_QOSHIGHPRI. */
3487 typedef volatile struct ALT_SDR_CTL_QOSHIGHPRI_s ALT_SDR_CTL_QOSHIGHPRI_t;
3488 #endif /* __ASSEMBLY__ */
3489 
3490 /* The byte offset of the ALT_SDR_CTL_QOSHIGHPRI register from the beginning of the component. */
3491 #define ALT_SDR_CTL_QOSHIGHPRI_OFST 0xa4
3492 
3493 /*
3494  * Register : qospriorityen Register - qospriorityen
3495  *
3496  *
3497  * Register Layout
3498  *
3499  * Bits | Access | Reset | Description
3500  * :--------|:-------|:--------|:--------------------
3501  * [9:0] | RW | Unknown | Per-Port QoS Enable
3502  * [31:10] | ??? | 0x0 | *UNDEFINED*
3503  *
3504  */
3505 /*
3506  * Field : Per-Port QoS Enable - priorityen
3507  *
3508  * This 10 bit field is set to a one to enable QOS usage for a port.
3509  *
3510  * Field Access Macros:
3511  *
3512  */
3513 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */
3514 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_LSB 0
3515 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */
3516 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_MSB 9
3517 /* The width in bits of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field. */
3518 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_WIDTH 10
3519 /* The mask used to set the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */
3520 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET_MSK 0x000003ff
3521 /* The mask used to clear the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value. */
3522 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_CLR_MSK 0xfffffc00
3523 /* The reset value of the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field is UNKNOWN. */
3524 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_RESET 0x0
3525 /* Extracts the ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN field value from a register. */
3526 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_GET(value) (((value) & 0x000003ff) >> 0)
3527 /* Produces a ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN register field value suitable for setting the register. */
3528 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET(value) (((value) << 0) & 0x000003ff)
3529 
3530 #ifndef __ASSEMBLY__
3531 /*
3532  * WARNING: The C register and register group struct declarations are provided for
3533  * convenience and illustrative purposes. They should, however, be used with
3534  * caution as the C language standard provides no guarantees about the alignment or
3535  * atomicity of device memory accesses. The recommended practice for writing
3536  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3537  * alt_write_word() functions.
3538  *
3539  * The struct declaration for register ALT_SDR_CTL_QOSPRIORITYEN.
3540  */
3541 struct ALT_SDR_CTL_QOSPRIORITYEN_s
3542 {
3543  uint32_t priorityen : 10; /* Per-Port QoS Enable */
3544  uint32_t : 22; /* *UNDEFINED* */
3545 };
3546 
3547 /* The typedef declaration for register ALT_SDR_CTL_QOSPRIORITYEN. */
3548 typedef volatile struct ALT_SDR_CTL_QOSPRIORITYEN_s ALT_SDR_CTL_QOSPRIORITYEN_t;
3549 #endif /* __ASSEMBLY__ */
3550 
3551 /* The byte offset of the ALT_SDR_CTL_QOSPRIORITYEN register from the beginning of the component. */
3552 #define ALT_SDR_CTL_QOSPRIORITYEN_OFST 0xa8
3553 
3554 /*
3555  * Register : Scheduler priority Register - mppriority
3556  *
3557  * This register is used to configure the DRAM burst operation scheduling.
3558  *
3559  * Register Layout
3560  *
3561  * Bits | Access | Reset | Description
3562  * :--------|:-------|:--------|:---------------------
3563  * [29:0] | RW | Unknown | Port User Priorities
3564  * [31:30] | ??? | 0x0 | *UNDEFINED*
3565  *
3566  */
3567 /*
3568  * Field : Port User Priorities - userpriority
3569  *
3570  * Set absolute user priority of the port. Each port is represented by a 3 bit
3571  * value, 000=lowest priority, 111=highest priority. Port 0 is bits 2:0. Port
3572  * number offset corresponds to the control port assignment.
3573  *
3574  * Field Access Macros:
3575  *
3576  */
3577 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */
3578 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_LSB 0
3579 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */
3580 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_MSB 29
3581 /* The width in bits of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field. */
3582 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_WIDTH 30
3583 /* The mask used to set the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */
3584 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET_MSK 0x3fffffff
3585 /* The mask used to clear the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value. */
3586 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_CLR_MSK 0xc0000000
3587 /* The reset value of the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field is UNKNOWN. */
3588 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_RESET 0x0
3589 /* Extracts the ALT_SDR_CTL_MPPRIORITY_USERPRIORITY field value from a register. */
3590 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_GET(value) (((value) & 0x3fffffff) >> 0)
3591 /* Produces a ALT_SDR_CTL_MPPRIORITY_USERPRIORITY register field value suitable for setting the register. */
3592 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET(value) (((value) << 0) & 0x3fffffff)
3593 
3594 #ifndef __ASSEMBLY__
3595 /*
3596  * WARNING: The C register and register group struct declarations are provided for
3597  * convenience and illustrative purposes. They should, however, be used with
3598  * caution as the C language standard provides no guarantees about the alignment or
3599  * atomicity of device memory accesses. The recommended practice for writing
3600  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3601  * alt_write_word() functions.
3602  *
3603  * The struct declaration for register ALT_SDR_CTL_MPPRIORITY.
3604  */
3605 struct ALT_SDR_CTL_MPPRIORITY_s
3606 {
3607  uint32_t userpriority : 30; /* Port User Priorities */
3608  uint32_t : 2; /* *UNDEFINED* */
3609 };
3610 
3611 /* The typedef declaration for register ALT_SDR_CTL_MPPRIORITY. */
3612 typedef volatile struct ALT_SDR_CTL_MPPRIORITY_s ALT_SDR_CTL_MPPRIORITY_t;
3613 #endif /* __ASSEMBLY__ */
3614 
3615 /* The byte offset of the ALT_SDR_CTL_MPPRIORITY register from the beginning of the component. */
3616 #define ALT_SDR_CTL_MPPRIORITY_OFST 0xac
3617 
3618 /*
3619  * Register : Controller Command Pool Priority Remap Register - remappriority
3620  *
3621  * This register controls the priority for transactions in the controller command
3622  * pool.
3623  *
3624  * Register Layout
3625  *
3626  * Bits | Access | Reset | Description
3627  * :-------|:-------|:--------|:---------------
3628  * [7:0] | RW | Unknown | Priority Remap
3629  * [31:8] | ??? | 0x0 | *UNDEFINED*
3630  *
3631  */
3632 /*
3633  * Field : Priority Remap - priorityremap
3634  *
3635  * Set bit N of this register to the value to a one to enable the controller
3636  * command pool priority bit of a transaction from MPFE priority N
3637  *
3638  * Field Access Macros:
3639  *
3640  */
3641 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */
3642 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_LSB 0
3643 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */
3644 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_MSB 7
3645 /* The width in bits of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field. */
3646 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_WIDTH 8
3647 /* The mask used to set the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */
3648 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET_MSK 0x000000ff
3649 /* The mask used to clear the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value. */
3650 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_CLR_MSK 0xffffff00
3651 /* The reset value of the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field is UNKNOWN. */
3652 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_RESET 0x0
3653 /* Extracts the ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP field value from a register. */
3654 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_GET(value) (((value) & 0x000000ff) >> 0)
3655 /* Produces a ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP register field value suitable for setting the register. */
3656 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET(value) (((value) << 0) & 0x000000ff)
3657 
3658 #ifndef __ASSEMBLY__
3659 /*
3660  * WARNING: The C register and register group struct declarations are provided for
3661  * convenience and illustrative purposes. They should, however, be used with
3662  * caution as the C language standard provides no guarantees about the alignment or
3663  * atomicity of device memory accesses. The recommended practice for writing
3664  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3665  * alt_write_word() functions.
3666  *
3667  * The struct declaration for register ALT_SDR_CTL_REMAPPRIORITY.
3668  */
3669 struct ALT_SDR_CTL_REMAPPRIORITY_s
3670 {
3671  uint32_t priorityremap : 8; /* Priority Remap */
3672  uint32_t : 24; /* *UNDEFINED* */
3673 };
3674 
3675 /* The typedef declaration for register ALT_SDR_CTL_REMAPPRIORITY. */
3676 typedef volatile struct ALT_SDR_CTL_REMAPPRIORITY_s ALT_SDR_CTL_REMAPPRIORITY_t;
3677 #endif /* __ASSEMBLY__ */
3678 
3679 /* The byte offset of the ALT_SDR_CTL_REMAPPRIORITY register from the beginning of the component. */
3680 #define ALT_SDR_CTL_REMAPPRIORITY_OFST 0xe0
3681 
3682 /*
3683  * Register Group : Port Sum of Weight Register - ALT_SDR_CTL_MPWT
3684  * Port Sum of Weight Register
3685  *
3686  * This register is used to configure the DRAM burst operation scheduling.
3687  *
3688  */
3689 /*
3690  * Register : Port Sum of Weight Register[1/4] - mpweight_0_4
3691  *
3692  * This register is used to configure the DRAM burst operation scheduling.
3693  *
3694  * Register Layout
3695  *
3696  * Bits | Access | Reset | Description
3697  * :-------|:-------|:--------|:--------------------------
3698  * [31:0] | RW | Unknown | Port Static Weights[31:0]
3699  *
3700  */
3701 /*
3702  * Field : Port Static Weights[31:0] - staticweight_31_0
3703  *
3704  * Set static weight of the port. Each port is programmed with a 5 bit value.
3705  * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45
3706  *
3707  * Field Access Macros:
3708  *
3709  */
3710 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */
3711 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_LSB 0
3712 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */
3713 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_MSB 31
3714 /* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field. */
3715 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_WIDTH 32
3716 /* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */
3717 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET_MSK 0xffffffff
3718 /* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value. */
3719 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_CLR_MSK 0x00000000
3720 /* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field is UNKNOWN. */
3721 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_RESET 0x0
3722 /* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 field value from a register. */
3723 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_GET(value) (((value) & 0xffffffff) >> 0)
3724 /* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0 register field value suitable for setting the register. */
3725 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET(value) (((value) << 0) & 0xffffffff)
3726 
3727 #ifndef __ASSEMBLY__
3728 /*
3729  * WARNING: The C register and register group struct declarations are provided for
3730  * convenience and illustrative purposes. They should, however, be used with
3731  * caution as the C language standard provides no guarantees about the alignment or
3732  * atomicity of device memory accesses. The recommended practice for writing
3733  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3734  * alt_write_word() functions.
3735  *
3736  * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4.
3737  */
3738 struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s
3739 {
3740  uint32_t staticweight_31_0 : 32; /* Port Static Weights[31:0] */
3741 };
3742 
3743 /* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_0_4. */
3744 typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t;
3745 #endif /* __ASSEMBLY__ */
3746 
3747 /* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register from the beginning of the component. */
3748 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST 0x0
3749 /* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 register. */
3750 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST))
3751 
3752 /*
3753  * Register : Port Sum of Weight Register[2/4] - mpweight_1_4
3754  *
3755  * This register is used to configure the DRAM burst operation scheduling.
3756  *
3757  * Register Layout
3758  *
3759  * Bits | Access | Reset | Description
3760  * :--------|:-------|:--------|:---------------------------
3761  * [17:0] | RW | Unknown | Port Static Weights[49:32]
3762  * [31:18] | RW | Unknown | Port Sum of Weights[13:0]
3763  *
3764  */
3765 /*
3766  * Field : Port Static Weights[49:32] - staticweight_49_32
3767  *
3768  * Set static weight of the port. Each port is programmed with a 5 bit value.
3769  * Port 0 is bits 4:0, port 1 is bits 9:5, up to port 9 being bits 49:45
3770  *
3771  * Field Access Macros:
3772  *
3773  */
3774 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */
3775 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_LSB 0
3776 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */
3777 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_MSB 17
3778 /* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field. */
3779 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_WIDTH 18
3780 /* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */
3781 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET_MSK 0x0003ffff
3782 /* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value. */
3783 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_CLR_MSK 0xfffc0000
3784 /* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field is UNKNOWN. */
3785 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_RESET 0x0
3786 /* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 field value from a register. */
3787 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_GET(value) (((value) & 0x0003ffff) >> 0)
3788 /* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32 register field value suitable for setting the register. */
3789 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET(value) (((value) << 0) & 0x0003ffff)
3790 
3791 /*
3792  * Field : Port Sum of Weights[13:0] - sumofweights_13_0
3793  *
3794  * Set the sum of static weights for particular user priority. This register is
3795  * used as part of the deficit round robin implementation. It should be set to the
3796  * sum of the weights for the ports
3797  *
3798  * Field Access Macros:
3799  *
3800  */
3801 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */
3802 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_LSB 18
3803 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */
3804 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_MSB 31
3805 /* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field. */
3806 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_WIDTH 14
3807 /* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */
3808 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET_MSK 0xfffc0000
3809 /* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value. */
3810 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_CLR_MSK 0x0003ffff
3811 /* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field is UNKNOWN. */
3812 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_RESET 0x0
3813 /* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 field value from a register. */
3814 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_GET(value) (((value) & 0xfffc0000) >> 18)
3815 /* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0 register field value suitable for setting the register. */
3816 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET(value) (((value) << 18) & 0xfffc0000)
3817 
3818 #ifndef __ASSEMBLY__
3819 /*
3820  * WARNING: The C register and register group struct declarations are provided for
3821  * convenience and illustrative purposes. They should, however, be used with
3822  * caution as the C language standard provides no guarantees about the alignment or
3823  * atomicity of device memory accesses. The recommended practice for writing
3824  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3825  * alt_write_word() functions.
3826  *
3827  * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4.
3828  */
3829 struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s
3830 {
3831  uint32_t staticweight_49_32 : 18; /* Port Static Weights[49:32] */
3832  uint32_t sumofweights_13_0 : 14; /* Port Sum of Weights[13:0] */
3833 };
3834 
3835 /* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_1_4. */
3836 typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t;
3837 #endif /* __ASSEMBLY__ */
3838 
3839 /* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register from the beginning of the component. */
3840 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST 0x4
3841 /* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 register. */
3842 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST))
3843 
3844 /*
3845  * Register : Port Sum of Weight Register[3/4] - mpweight_2_4
3846  *
3847  * This register is used to configure the DRAM burst operation scheduling.
3848  *
3849  * Register Layout
3850  *
3851  * Bits | Access | Reset | Description
3852  * :-------|:-------|:--------|:---------------------------
3853  * [31:0] | RW | Unknown | Port Sum of Weights[45:14]
3854  *
3855  */
3856 /*
3857  * Field : Port Sum of Weights[45:14] - sumofweights_45_14
3858  *
3859  * Set the sum of static weights for particular user priority. This register is
3860  * used as part of the deficit round robin implementation. It should be set to the
3861  * sum of the weights for the ports
3862  *
3863  * Field Access Macros:
3864  *
3865  */
3866 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */
3867 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_LSB 0
3868 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */
3869 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_MSB 31
3870 /* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field. */
3871 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_WIDTH 32
3872 /* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */
3873 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET_MSK 0xffffffff
3874 /* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value. */
3875 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_CLR_MSK 0x00000000
3876 /* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field is UNKNOWN. */
3877 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_RESET 0x0
3878 /* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 field value from a register. */
3879 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_GET(value) (((value) & 0xffffffff) >> 0)
3880 /* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14 register field value suitable for setting the register. */
3881 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET(value) (((value) << 0) & 0xffffffff)
3882 
3883 #ifndef __ASSEMBLY__
3884 /*
3885  * WARNING: The C register and register group struct declarations are provided for
3886  * convenience and illustrative purposes. They should, however, be used with
3887  * caution as the C language standard provides no guarantees about the alignment or
3888  * atomicity of device memory accesses. The recommended practice for writing
3889  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3890  * alt_write_word() functions.
3891  *
3892  * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4.
3893  */
3894 struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s
3895 {
3896  uint32_t sumofweights_45_14 : 32; /* Port Sum of Weights[45:14] */
3897 };
3898 
3899 /* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_2_4. */
3900 typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t;
3901 #endif /* __ASSEMBLY__ */
3902 
3903 /* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register from the beginning of the component. */
3904 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST 0x8
3905 /* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 register. */
3906 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST))
3907 
3908 /*
3909  * Register : Port Sum of Weight Register[4/4] - mpweight_3_4
3910  *
3911  * This register is used to configure the DRAM burst operation scheduling.
3912  *
3913  * Register Layout
3914  *
3915  * Bits | Access | Reset | Description
3916  * :--------|:-------|:--------|:---------------------------
3917  * [17:0] | RW | Unknown | Port Sum of Weights[63:46]
3918  * [31:18] | ??? | 0x0 | *UNDEFINED*
3919  *
3920  */
3921 /*
3922  * Field : Port Sum of Weights[63:46] - sumofweights_63_46
3923  *
3924  * Set the sum of static weights for particular user priority. This register is
3925  * used as part of the deficit round robin implementation. It should be set to the
3926  * sum of the weights for the ports
3927  *
3928  * Field Access Macros:
3929  *
3930  */
3931 /* The Least Significant Bit (LSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */
3932 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_LSB 0
3933 /* The Most Significant Bit (MSB) position of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */
3934 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_MSB 17
3935 /* The width in bits of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field. */
3936 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_WIDTH 18
3937 /* The mask used to set the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */
3938 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET_MSK 0x0003ffff
3939 /* The mask used to clear the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value. */
3940 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_CLR_MSK 0xfffc0000
3941 /* The reset value of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field is UNKNOWN. */
3942 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_RESET 0x0
3943 /* Extracts the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 field value from a register. */
3944 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_GET(value) (((value) & 0x0003ffff) >> 0)
3945 /* Produces a ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46 register field value suitable for setting the register. */
3946 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET(value) (((value) << 0) & 0x0003ffff)
3947 
3948 #ifndef __ASSEMBLY__
3949 /*
3950  * WARNING: The C register and register group struct declarations are provided for
3951  * convenience and illustrative purposes. They should, however, be used with
3952  * caution as the C language standard provides no guarantees about the alignment or
3953  * atomicity of device memory accesses. The recommended practice for writing
3954  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3955  * alt_write_word() functions.
3956  *
3957  * The struct declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4.
3958  */
3959 struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s
3960 {
3961  uint32_t sumofweights_63_46 : 18; /* Port Sum of Weights[63:46] */
3962  uint32_t : 14; /* *UNDEFINED* */
3963 };
3964 
3965 /* The typedef declaration for register ALT_SDR_CTL_MPWT_MPWEIGHT_3_4. */
3966 typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t;
3967 #endif /* __ASSEMBLY__ */
3968 
3969 /* The byte offset of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register from the beginning of the component. */
3970 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST 0xc
3971 /* The address of the ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 register. */
3972 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST))
3973 
3974 #ifndef __ASSEMBLY__
3975 /*
3976  * WARNING: The C register and register group struct declarations are provided for
3977  * convenience and illustrative purposes. They should, however, be used with
3978  * caution as the C language standard provides no guarantees about the alignment or
3979  * atomicity of device memory accesses. The recommended practice for writing
3980  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3981  * alt_write_word() functions.
3982  *
3983  * The struct declaration for register group ALT_SDR_CTL_MPWT.
3984  */
3985 struct ALT_SDR_CTL_MPWT_s
3986 {
3987  ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t mpweight_0_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */
3988  ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t mpweight_1_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */
3989  ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t mpweight_2_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */
3990  ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t mpweight_3_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */
3991 };
3992 
3993 /* The typedef declaration for register group ALT_SDR_CTL_MPWT. */
3994 typedef volatile struct ALT_SDR_CTL_MPWT_s ALT_SDR_CTL_MPWT_t;
3995 /* The struct declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */
3996 struct ALT_SDR_CTL_MPWT_raw_s
3997 {
3998  volatile uint32_t mpweight_0_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_0_4 */
3999  volatile uint32_t mpweight_1_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_1_4 */
4000  volatile uint32_t mpweight_2_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_2_4 */
4001  volatile uint32_t mpweight_3_4; /* ALT_SDR_CTL_MPWT_MPWEIGHT_3_4 */
4002 };
4003 
4004 /* The typedef declaration for the raw register contents of register group ALT_SDR_CTL_MPWT. */
4005 typedef volatile struct ALT_SDR_CTL_MPWT_raw_s ALT_SDR_CTL_MPWT_raw_t;
4006 #endif /* __ASSEMBLY__ */
4007 
4008 
4009 #ifndef __ASSEMBLY__
4010 /*
4011  * WARNING: The C register and register group struct declarations are provided for
4012  * convenience and illustrative purposes. They should, however, be used with
4013  * caution as the C language standard provides no guarantees about the alignment or
4014  * atomicity of device memory accesses. The recommended practice for writing
4015  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4016  * alt_write_word() functions.
4017  *
4018  * The struct declaration for register group ALT_SDR_CTL.
4019  */
4020 struct ALT_SDR_CTL_s
4021 {
4022  ALT_SDR_CTL_CTLCFG_t ctrlcfg; /* ALT_SDR_CTL_CTLCFG */
4023  ALT_SDR_CTL_DRAMTIMING1_t dramtiming1; /* ALT_SDR_CTL_DRAMTIMING1 */
4024  ALT_SDR_CTL_DRAMTIMING2_t dramtiming2; /* ALT_SDR_CTL_DRAMTIMING2 */
4025  ALT_SDR_CTL_DRAMTIMING3_t dramtiming3; /* ALT_SDR_CTL_DRAMTIMING3 */
4026  ALT_SDR_CTL_DRAMTIMING4_t dramtiming4; /* ALT_SDR_CTL_DRAMTIMING4 */
4027  ALT_SDR_CTL_LOWPWRTIMING_t lowpwrtiming; /* ALT_SDR_CTL_LOWPWRTIMING */
4028  ALT_SDR_CTL_DRAMODT_t dramodt; /* ALT_SDR_CTL_DRAMODT */
4029  volatile uint32_t _pad_0x1c_0x2b[4]; /* *UNDEFINED* */
4030  ALT_SDR_CTL_DRAMADDRW_t dramaddrw; /* ALT_SDR_CTL_DRAMADDRW */
4031  ALT_SDR_CTL_DRAMIFWIDTH_t dramifwidth; /* ALT_SDR_CTL_DRAMIFWIDTH */
4032  ALT_SDR_CTL_DRAMDEVWIDTH_t dramdevwidth; /* ALT_SDR_CTL_DRAMDEVWIDTH */
4033  ALT_SDR_CTL_DRAMSTS_t dramsts; /* ALT_SDR_CTL_DRAMSTS */
4034  ALT_SDR_CTL_DRAMINTR_t dramintr; /* ALT_SDR_CTL_DRAMINTR */
4035  ALT_SDR_CTL_SBECOUNT_t sbecount; /* ALT_SDR_CTL_SBECOUNT */
4036  ALT_SDR_CTL_DBECOUNT_t dbecount; /* ALT_SDR_CTL_DBECOUNT */
4037  ALT_SDR_CTL_ERRADDR_t erraddr; /* ALT_SDR_CTL_ERRADDR */
4038  ALT_SDR_CTL_DROPCOUNT_t dropcount; /* ALT_SDR_CTL_DROPCOUNT */
4039  ALT_SDR_CTL_DROPADDR_t dropaddr; /* ALT_SDR_CTL_DROPADDR */
4040  ALT_SDR_CTL_LOWPWREQ_t lowpwreq; /* ALT_SDR_CTL_LOWPWREQ */
4041  ALT_SDR_CTL_LOWPWRACK_t lowpwrack; /* ALT_SDR_CTL_LOWPWRACK */
4042  ALT_SDR_CTL_STATICCFG_t staticcfg; /* ALT_SDR_CTL_STATICCFG */
4043  ALT_SDR_CTL_CTLWIDTH_t ctrlwidth; /* ALT_SDR_CTL_CTLWIDTH */
4044  volatile uint32_t _pad_0x64_0x7b[6]; /* *UNDEFINED* */
4045  ALT_SDR_CTL_PORTCFG_t portcfg; /* ALT_SDR_CTL_PORTCFG */
4046  ALT_SDR_CTL_FPGAPORTRST_t fpgaportrst; /* ALT_SDR_CTL_FPGAPORTRST */
4047  volatile uint32_t _pad_0x84_0x8b[2]; /* *UNDEFINED* */
4048  ALT_SDR_CTL_PROTPORTDEFAULT_t protportdefault; /* ALT_SDR_CTL_PROTPORTDEFAULT */
4049  ALT_SDR_CTL_PROTRULEADDR_t protruleaddr; /* ALT_SDR_CTL_PROTRULEADDR */
4050  ALT_SDR_CTL_PROTRULEID_t protruleid; /* ALT_SDR_CTL_PROTRULEID */
4051  ALT_SDR_CTL_PROTRULEDATA_t protruledata; /* ALT_SDR_CTL_PROTRULEDATA */
4052  ALT_SDR_CTL_PROTRULERDWR_t protrulerdwr; /* ALT_SDR_CTL_PROTRULERDWR */
4053  ALT_SDR_CTL_QOSLOWPRI_t qoslowpri; /* ALT_SDR_CTL_QOSLOWPRI */
4054  ALT_SDR_CTL_QOSHIGHPRI_t qoshighpri; /* ALT_SDR_CTL_QOSHIGHPRI */
4055  ALT_SDR_CTL_QOSPRIORITYEN_t qospriorityen; /* ALT_SDR_CTL_QOSPRIORITYEN */
4056  ALT_SDR_CTL_MPPRIORITY_t mppriority; /* ALT_SDR_CTL_MPPRIORITY */
4057  ALT_SDR_CTL_MPWT_t ctrlgrp_mpweight; /* ALT_SDR_CTL_MPWT */
4058  volatile uint32_t _pad_0xc0_0xdf[8]; /* *UNDEFINED* */
4059  ALT_SDR_CTL_REMAPPRIORITY_t remappriority; /* ALT_SDR_CTL_REMAPPRIORITY */
4060  volatile uint32_t _pad_0xe4_0x1000[967]; /* *UNDEFINED* */
4061 };
4062 
4063 /* The typedef declaration for register group ALT_SDR_CTL. */
4064 typedef volatile struct ALT_SDR_CTL_s ALT_SDR_CTL_t;
4065 /* The struct declaration for the raw register contents of register group ALT_SDR_CTL. */
4066 struct ALT_SDR_CTL_raw_s
4067 {
4068  volatile uint32_t ctrlcfg; /* ALT_SDR_CTL_CTLCFG */
4069  volatile uint32_t dramtiming1; /* ALT_SDR_CTL_DRAMTIMING1 */
4070  volatile uint32_t dramtiming2; /* ALT_SDR_CTL_DRAMTIMING2 */
4071  volatile uint32_t dramtiming3; /* ALT_SDR_CTL_DRAMTIMING3 */
4072  volatile uint32_t dramtiming4; /* ALT_SDR_CTL_DRAMTIMING4 */
4073  volatile uint32_t lowpwrtiming; /* ALT_SDR_CTL_LOWPWRTIMING */
4074  volatile uint32_t dramodt; /* ALT_SDR_CTL_DRAMODT */
4075  uint32_t _pad_0x1c_0x2b[4]; /* *UNDEFINED* */
4076  volatile uint32_t dramaddrw; /* ALT_SDR_CTL_DRAMADDRW */
4077  volatile uint32_t dramifwidth; /* ALT_SDR_CTL_DRAMIFWIDTH */
4078  volatile uint32_t dramdevwidth; /* ALT_SDR_CTL_DRAMDEVWIDTH */
4079  volatile uint32_t dramsts; /* ALT_SDR_CTL_DRAMSTS */
4080  volatile uint32_t dramintr; /* ALT_SDR_CTL_DRAMINTR */
4081  volatile uint32_t sbecount; /* ALT_SDR_CTL_SBECOUNT */
4082  volatile uint32_t dbecount; /* ALT_SDR_CTL_DBECOUNT */
4083  volatile uint32_t erraddr; /* ALT_SDR_CTL_ERRADDR */
4084  volatile uint32_t dropcount; /* ALT_SDR_CTL_DROPCOUNT */
4085  volatile uint32_t dropaddr; /* ALT_SDR_CTL_DROPADDR */
4086  volatile uint32_t lowpwreq; /* ALT_SDR_CTL_LOWPWREQ */
4087  volatile uint32_t lowpwrack; /* ALT_SDR_CTL_LOWPWRACK */
4088  volatile uint32_t staticcfg; /* ALT_SDR_CTL_STATICCFG */
4089  volatile uint32_t ctrlwidth; /* ALT_SDR_CTL_CTLWIDTH */
4090  uint32_t _pad_0x64_0x7b[6]; /* *UNDEFINED* */
4091  volatile uint32_t portcfg; /* ALT_SDR_CTL_PORTCFG */
4092  volatile uint32_t fpgaportrst; /* ALT_SDR_CTL_FPGAPORTRST */
4093  uint32_t _pad_0x84_0x8b[2]; /* *UNDEFINED* */
4094  volatile uint32_t protportdefault; /* ALT_SDR_CTL_PROTPORTDEFAULT */
4095  volatile uint32_t protruleaddr; /* ALT_SDR_CTL_PROTRULEADDR */
4096  volatile uint32_t protruleid; /* ALT_SDR_CTL_PROTRULEID */
4097  volatile uint32_t protruledata; /* ALT_SDR_CTL_PROTRULEDATA */
4098  volatile uint32_t protrulerdwr; /* ALT_SDR_CTL_PROTRULERDWR */
4099  volatile uint32_t qoslowpri; /* ALT_SDR_CTL_QOSLOWPRI */
4100  volatile uint32_t qoshighpri; /* ALT_SDR_CTL_QOSHIGHPRI */
4101  volatile uint32_t qospriorityen; /* ALT_SDR_CTL_QOSPRIORITYEN */
4102  volatile uint32_t mppriority; /* ALT_SDR_CTL_MPPRIORITY */
4103  ALT_SDR_CTL_MPWT_raw_t ctrlgrp_mpweight; /* ALT_SDR_CTL_MPWT */
4104  uint32_t _pad_0xc0_0xdf[8]; /* *UNDEFINED* */
4105  volatile uint32_t remappriority; /* ALT_SDR_CTL_REMAPPRIORITY */
4106  uint32_t _pad_0xe4_0x1000[967]; /* *UNDEFINED* */
4107 };
4108 
4109 /* The typedef declaration for the raw register contents of register group ALT_SDR_CTL. */
4110 typedef volatile struct ALT_SDR_CTL_raw_s ALT_SDR_CTL_raw_t;
4111 #endif /* __ASSEMBLY__ */
4112 
4113 
4114 #ifndef __ASSEMBLY__
4115 /*
4116  * WARNING: The C register and register group struct declarations are provided for
4117  * convenience and illustrative purposes. They should, however, be used with
4118  * caution as the C language standard provides no guarantees about the alignment or
4119  * atomicity of device memory accesses. The recommended practice for writing
4120  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4121  * alt_write_word() functions.
4122  *
4123  * The struct declaration for register group ALT_SDR.
4124  */
4125 struct ALT_SDR_s
4126 {
4127  volatile uint32_t _pad_0x0_0x4fff[5120]; /* *UNDEFINED* */
4128  ALT_SDR_CTL_t ctrlgrp; /* ALT_SDR_CTL */
4129  volatile uint32_t _pad_0x6000_0x20000[26624]; /* *UNDEFINED* */
4130 };
4131 
4132 /* The typedef declaration for register group ALT_SDR. */
4133 typedef volatile struct ALT_SDR_s ALT_SDR_t;
4134 /* The struct declaration for the raw register contents of register group ALT_SDR. */
4135 struct ALT_SDR_raw_s
4136 {
4137  uint32_t _pad_0x0_0x4fff[5120]; /* *UNDEFINED* */
4138  ALT_SDR_CTL_raw_t ctrlgrp; /* ALT_SDR_CTL */
4139  uint32_t _pad_0x6000_0x20000[26624]; /* *UNDEFINED* */
4140 };
4141 
4142 /* The typedef declaration for the raw register contents of register group ALT_SDR. */
4143 typedef volatile struct ALT_SDR_raw_s ALT_SDR_raw_t;
4144 #endif /* __ASSEMBLY__ */
4145 
4146 
4147 #ifdef __cplusplus
4148 }
4149 #endif /* __cplusplus */
4150 #endif /* __ALTERA_ALT_SDR_H__ */
4151