Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
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alt_sdmmc.h
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32 
33 /* Altera - ALT_SDMMC */
34 
35 #ifndef __ALT_SOCAL_SDMMC_H__
36 #define __ALT_SOCAL_SDMMC_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_SDMMC
50  *
51  */
52 /*
53  * Register : ctrl
54  *
55  * Control register
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :--------|:-------|:------|:------------------------------------
61  * [0] | RW | 0x0 | ALT_SDMMC_CTL_CTLLER_RST
62  * [1] | RW | 0x0 | ALT_SDMMC_CTL_FIFO_RST
63  * [2] | RW | 0x0 | ALT_SDMMC_CTL_DMA_RST
64  * [3] | ??? | 0x0 | *UNDEFINED*
65  * [4] | RW | 0x0 | ALT_SDMMC_CTL_INT_EN
66  * [5] | RW | 0x0 | ALT_SDMMC_CTL_DMA_EN
67  * [6] | RW | 0x0 | ALT_SDMMC_CTL_RD_WAIT
68  * [7] | RW | 0x0 | ALT_SDMMC_CTL_SEND_IRQ_RESPONSE
69  * [8] | RW | 0x0 | ALT_SDMMC_CTL_ABT_RD_DATA
70  * [9] | RW | 0x0 | ALT_SDMMC_CTL_SEND_CCSD
71  * [10] | RW | 0x0 | ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD
72  * [11] | RW | 0x0 | ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT
73  * [15:12] | ??? | 0x0 | *UNDEFINED*
74  * [19:16] | RW | 0x0 | ALT_SDMMC_CTL_CARD_VOLTAGE_A
75  * [23:20] | RW | 0x0 | ALT_SDMMC_CTL_CARD_VOLTAGE_B
76  * [24] | RW | 0x0 | ALT_SDMMC_CTL_EN_OD_PULLUP
77  * [25] | RW | 0x0 | ALT_SDMMC_CTL_USE_INTERNAL_DMAC
78  * [31:26] | ??? | 0x0 | *UNDEFINED*
79  *
80  */
81 /*
82  * Field : controller_reset
83  *
84  * 0-No change
85  *
86  * 1-Reset DWC_mobile_storage controller
87  *
88  * To reset controller, firmware should set bit to 1. This bit is auto-cleared
89  * after two AHB and two cclk_in clock cycles.
90  *
91  * This resets:
92  *
93  * * BIU/CIU interface
94  *
95  * * CIU and state machines
96  *
97  * * abort_read_data, send_irq_response, and read_wait bits of Control register
98  *
99  * * start_cmd bit of Command register
100  *
101  * Does not affect any registers or DMA interface, or FIFO or host
102  *
103  * interrupts
104  *
105  * Field Enumeration Values:
106  *
107  * Enum | Value | Description
108  * :------------------------------------|:------|:------------------------
109  * ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE | 0x0 | No change -default
110  * ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE | 0x1 | Reset SD/MMC controller
111  *
112  * Field Access Macros:
113  *
114  */
115 /*
116  * Enumerated value for register field ALT_SDMMC_CTL_CTLLER_RST
117  *
118  * No change -default
119  */
120 #define ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE 0x0
121 /*
122  * Enumerated value for register field ALT_SDMMC_CTL_CTLLER_RST
123  *
124  * Reset SD/MMC controller
125  */
126 #define ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE 0x1
127 
128 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CTLLER_RST register field. */
129 #define ALT_SDMMC_CTL_CTLLER_RST_LSB 0
130 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CTLLER_RST register field. */
131 #define ALT_SDMMC_CTL_CTLLER_RST_MSB 0
132 /* The width in bits of the ALT_SDMMC_CTL_CTLLER_RST register field. */
133 #define ALT_SDMMC_CTL_CTLLER_RST_WIDTH 1
134 /* The mask used to set the ALT_SDMMC_CTL_CTLLER_RST register field value. */
135 #define ALT_SDMMC_CTL_CTLLER_RST_SET_MSK 0x00000001
136 /* The mask used to clear the ALT_SDMMC_CTL_CTLLER_RST register field value. */
137 #define ALT_SDMMC_CTL_CTLLER_RST_CLR_MSK 0xfffffffe
138 /* The reset value of the ALT_SDMMC_CTL_CTLLER_RST register field. */
139 #define ALT_SDMMC_CTL_CTLLER_RST_RESET 0x0
140 /* Extracts the ALT_SDMMC_CTL_CTLLER_RST field value from a register. */
141 #define ALT_SDMMC_CTL_CTLLER_RST_GET(value) (((value) & 0x00000001) >> 0)
142 /* Produces a ALT_SDMMC_CTL_CTLLER_RST register field value suitable for setting the register. */
143 #define ALT_SDMMC_CTL_CTLLER_RST_SET(value) (((value) << 0) & 0x00000001)
144 
145 /*
146  * Field : fifo_reset
147  *
148  * 0-No change
149  *
150  * 1-Reset to data FIFO To reset FIFO pointers
151  *
152  * To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after
153  * completion of reset operation.
154  *
155  * Field Enumeration Values:
156  *
157  * Enum | Value | Description
158  * :----------------------------------|:------|:------------------------------------------
159  * ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE | 0x0 | No change
160  * ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE | 0x1 | Reset to data FIFO To reset FIFO pointers
161  *
162  * Field Access Macros:
163  *
164  */
165 /*
166  * Enumerated value for register field ALT_SDMMC_CTL_FIFO_RST
167  *
168  * No change
169  */
170 #define ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE 0x0
171 /*
172  * Enumerated value for register field ALT_SDMMC_CTL_FIFO_RST
173  *
174  * Reset to data FIFO To reset FIFO pointers
175  */
176 #define ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE 0x1
177 
178 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_FIFO_RST register field. */
179 #define ALT_SDMMC_CTL_FIFO_RST_LSB 1
180 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_FIFO_RST register field. */
181 #define ALT_SDMMC_CTL_FIFO_RST_MSB 1
182 /* The width in bits of the ALT_SDMMC_CTL_FIFO_RST register field. */
183 #define ALT_SDMMC_CTL_FIFO_RST_WIDTH 1
184 /* The mask used to set the ALT_SDMMC_CTL_FIFO_RST register field value. */
185 #define ALT_SDMMC_CTL_FIFO_RST_SET_MSK 0x00000002
186 /* The mask used to clear the ALT_SDMMC_CTL_FIFO_RST register field value. */
187 #define ALT_SDMMC_CTL_FIFO_RST_CLR_MSK 0xfffffffd
188 /* The reset value of the ALT_SDMMC_CTL_FIFO_RST register field. */
189 #define ALT_SDMMC_CTL_FIFO_RST_RESET 0x0
190 /* Extracts the ALT_SDMMC_CTL_FIFO_RST field value from a register. */
191 #define ALT_SDMMC_CTL_FIFO_RST_GET(value) (((value) & 0x00000002) >> 1)
192 /* Produces a ALT_SDMMC_CTL_FIFO_RST register field value suitable for setting the register. */
193 #define ALT_SDMMC_CTL_FIFO_RST_SET(value) (((value) << 1) & 0x00000002)
194 
195 /*
196  * Field : dma_reset
197  *
198  * 0-No change
199  *
200  * 1-Reset internal DMA interface control logic
201  *
202  * To reset DMA interface, firmware should set bit to 1. This bit is
203  *
204  * auto-cleared after two AHB clocks.
205  *
206  * Field Enumeration Values:
207  *
208  * Enum | Value | Description
209  * :---------------------------------|:------|:-------------------------------------------
210  * ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE | 0x0 | No change
211  * ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE | 0x1 | Reset internal DMA interface control logic
212  *
213  * Field Access Macros:
214  *
215  */
216 /*
217  * Enumerated value for register field ALT_SDMMC_CTL_DMA_RST
218  *
219  * No change
220  */
221 #define ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE 0x0
222 /*
223  * Enumerated value for register field ALT_SDMMC_CTL_DMA_RST
224  *
225  * Reset internal DMA interface control logic
226  */
227 #define ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE 0x1
228 
229 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_DMA_RST register field. */
230 #define ALT_SDMMC_CTL_DMA_RST_LSB 2
231 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_DMA_RST register field. */
232 #define ALT_SDMMC_CTL_DMA_RST_MSB 2
233 /* The width in bits of the ALT_SDMMC_CTL_DMA_RST register field. */
234 #define ALT_SDMMC_CTL_DMA_RST_WIDTH 1
235 /* The mask used to set the ALT_SDMMC_CTL_DMA_RST register field value. */
236 #define ALT_SDMMC_CTL_DMA_RST_SET_MSK 0x00000004
237 /* The mask used to clear the ALT_SDMMC_CTL_DMA_RST register field value. */
238 #define ALT_SDMMC_CTL_DMA_RST_CLR_MSK 0xfffffffb
239 /* The reset value of the ALT_SDMMC_CTL_DMA_RST register field. */
240 #define ALT_SDMMC_CTL_DMA_RST_RESET 0x0
241 /* Extracts the ALT_SDMMC_CTL_DMA_RST field value from a register. */
242 #define ALT_SDMMC_CTL_DMA_RST_GET(value) (((value) & 0x00000004) >> 2)
243 /* Produces a ALT_SDMMC_CTL_DMA_RST register field value suitable for setting the register. */
244 #define ALT_SDMMC_CTL_DMA_RST_SET(value) (((value) << 2) & 0x00000004)
245 
246 /*
247  * Field : int_enable
248  *
249  * Global interrupt enable/disable bit:
250  *
251  * 0-Disable interrupts
252  *
253  * 1-Enable interrupts
254  *
255  * The int port is 1 only when this bit is 1 and one or more unmasked
256  *
257  * interrupts are set.
258  *
259  * Field Enumeration Values:
260  *
261  * Enum | Value | Description
262  * :----------------------------|:------|:-------------------
263  * ALT_SDMMC_CTL_INT_EN_E_DISD | 0x0 | Disable Interrupts
264  * ALT_SDMMC_CTL_INT_EN_E_END | 0x1 | Enable interrupts
265  *
266  * Field Access Macros:
267  *
268  */
269 /*
270  * Enumerated value for register field ALT_SDMMC_CTL_INT_EN
271  *
272  * Disable Interrupts
273  */
274 #define ALT_SDMMC_CTL_INT_EN_E_DISD 0x0
275 /*
276  * Enumerated value for register field ALT_SDMMC_CTL_INT_EN
277  *
278  * Enable interrupts
279  */
280 #define ALT_SDMMC_CTL_INT_EN_E_END 0x1
281 
282 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_INT_EN register field. */
283 #define ALT_SDMMC_CTL_INT_EN_LSB 4
284 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_INT_EN register field. */
285 #define ALT_SDMMC_CTL_INT_EN_MSB 4
286 /* The width in bits of the ALT_SDMMC_CTL_INT_EN register field. */
287 #define ALT_SDMMC_CTL_INT_EN_WIDTH 1
288 /* The mask used to set the ALT_SDMMC_CTL_INT_EN register field value. */
289 #define ALT_SDMMC_CTL_INT_EN_SET_MSK 0x00000010
290 /* The mask used to clear the ALT_SDMMC_CTL_INT_EN register field value. */
291 #define ALT_SDMMC_CTL_INT_EN_CLR_MSK 0xffffffef
292 /* The reset value of the ALT_SDMMC_CTL_INT_EN register field. */
293 #define ALT_SDMMC_CTL_INT_EN_RESET 0x0
294 /* Extracts the ALT_SDMMC_CTL_INT_EN field value from a register. */
295 #define ALT_SDMMC_CTL_INT_EN_GET(value) (((value) & 0x00000010) >> 4)
296 /* Produces a ALT_SDMMC_CTL_INT_EN register field value suitable for setting the register. */
297 #define ALT_SDMMC_CTL_INT_EN_SET(value) (((value) << 4) & 0x00000010)
298 
299 /*
300  * Field : dma_enable
301  *
302  * 0-Disable DMA transfer mode
303  *
304  * 1-Enable DMA transfer mode
305  *
306  * Valid only if DWC_mobile_storage configured for External DMA interface.
307  *
308  * Field Access Macros:
309  *
310  */
311 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_DMA_EN register field. */
312 #define ALT_SDMMC_CTL_DMA_EN_LSB 5
313 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_DMA_EN register field. */
314 #define ALT_SDMMC_CTL_DMA_EN_MSB 5
315 /* The width in bits of the ALT_SDMMC_CTL_DMA_EN register field. */
316 #define ALT_SDMMC_CTL_DMA_EN_WIDTH 1
317 /* The mask used to set the ALT_SDMMC_CTL_DMA_EN register field value. */
318 #define ALT_SDMMC_CTL_DMA_EN_SET_MSK 0x00000020
319 /* The mask used to clear the ALT_SDMMC_CTL_DMA_EN register field value. */
320 #define ALT_SDMMC_CTL_DMA_EN_CLR_MSK 0xffffffdf
321 /* The reset value of the ALT_SDMMC_CTL_DMA_EN register field. */
322 #define ALT_SDMMC_CTL_DMA_EN_RESET 0x0
323 /* Extracts the ALT_SDMMC_CTL_DMA_EN field value from a register. */
324 #define ALT_SDMMC_CTL_DMA_EN_GET(value) (((value) & 0x00000020) >> 5)
325 /* Produces a ALT_SDMMC_CTL_DMA_EN register field value suitable for setting the register. */
326 #define ALT_SDMMC_CTL_DMA_EN_SET(value) (((value) << 5) & 0x00000020)
327 
328 /*
329  * Field : read_wait
330  *
331  * 0-Clear read wait
332  *
333  * 1-Assert read wait
334  *
335  * For sending read-wait to SDIO cards.
336  *
337  * Field Enumeration Values:
338  *
339  * Enum | Value | Description
340  * :---------------------------------|:------|:-----------------
341  * ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT | 0x0 | Read Wait
342  * ALT_SDMMC_CTL_RD_WAIT_E_ASSERT | 0x1 | Assert Read Wait
343  *
344  * Field Access Macros:
345  *
346  */
347 /*
348  * Enumerated value for register field ALT_SDMMC_CTL_RD_WAIT
349  *
350  * Read Wait
351  */
352 #define ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT 0x0
353 /*
354  * Enumerated value for register field ALT_SDMMC_CTL_RD_WAIT
355  *
356  * Assert Read Wait
357  */
358 #define ALT_SDMMC_CTL_RD_WAIT_E_ASSERT 0x1
359 
360 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_RD_WAIT register field. */
361 #define ALT_SDMMC_CTL_RD_WAIT_LSB 6
362 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_RD_WAIT register field. */
363 #define ALT_SDMMC_CTL_RD_WAIT_MSB 6
364 /* The width in bits of the ALT_SDMMC_CTL_RD_WAIT register field. */
365 #define ALT_SDMMC_CTL_RD_WAIT_WIDTH 1
366 /* The mask used to set the ALT_SDMMC_CTL_RD_WAIT register field value. */
367 #define ALT_SDMMC_CTL_RD_WAIT_SET_MSK 0x00000040
368 /* The mask used to clear the ALT_SDMMC_CTL_RD_WAIT register field value. */
369 #define ALT_SDMMC_CTL_RD_WAIT_CLR_MSK 0xffffffbf
370 /* The reset value of the ALT_SDMMC_CTL_RD_WAIT register field. */
371 #define ALT_SDMMC_CTL_RD_WAIT_RESET 0x0
372 /* Extracts the ALT_SDMMC_CTL_RD_WAIT field value from a register. */
373 #define ALT_SDMMC_CTL_RD_WAIT_GET(value) (((value) & 0x00000040) >> 6)
374 /* Produces a ALT_SDMMC_CTL_RD_WAIT register field value suitable for setting the register. */
375 #define ALT_SDMMC_CTL_RD_WAIT_SET(value) (((value) << 6) & 0x00000040)
376 
377 /*
378  * Field : send_irq_response
379  *
380  * 0-No Change in this
381  *
382  * 1-Send auto IRQ response
383  *
384  * Bit automatically clears once response is sent.
385  *
386  * To wait for MMC card interrupts, host issues CMD40, and DWC_mobile_storage waits
387  * for interrupt response from MMC card(s). In meantime, if host wants
388  * DWC_mobile_storage to exit waiting for interrupt state, it can set this bit, at
389  * which time DWC_mobile_storage command state-machine sends CMD40 response on bus
390  * and returns to idle state.
391  *
392  * Field Enumeration Values:
393  *
394  * Enum | Value | Description
395  * :-------------------------------------------|:------|:-----------------------
396  * ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE | 0x0 | No change
397  * ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE | 0x1 | Send auto IRQ response
398  *
399  * Field Access Macros:
400  *
401  */
402 /*
403  * Enumerated value for register field ALT_SDMMC_CTL_SEND_IRQ_RESPONSE
404  *
405  * No change
406  */
407 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE 0x0
408 /*
409  * Enumerated value for register field ALT_SDMMC_CTL_SEND_IRQ_RESPONSE
410  *
411  * Send auto IRQ response
412  */
413 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE 0x1
414 
415 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field. */
416 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_LSB 7
417 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field. */
418 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_MSB 7
419 /* The width in bits of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field. */
420 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_WIDTH 1
421 /* The mask used to set the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value. */
422 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET_MSK 0x00000080
423 /* The mask used to clear the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value. */
424 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_CLR_MSK 0xffffff7f
425 /* The reset value of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field. */
426 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_RESET 0x0
427 /* Extracts the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE field value from a register. */
428 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_GET(value) (((value) & 0x00000080) >> 7)
429 /* Produces a ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value suitable for setting the register. */
430 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET(value) (((value) << 7) & 0x00000080)
431 
432 /*
433  * Field : abort_read_data
434  *
435  * 0-No change
436  *
437  * 1-After suspend command is issued during read-transfer, software
438  *
439  * polls card to find when suspend happened. Once suspend occurs,software sets bit
440  * to reset data state-machine, which is waiting for next block of data. Bit
441  * automatically clears once data statemachine resets to idle.
442  *
443  * Used in SDIO card suspend sequence.
444  *
445  * Field Enumeration Values:
446  *
447  * Enum | Value | Description
448  * :-------------------------------------|:------|:------------
449  * ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE | 0x0 | No change
450  * ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE | 0x1 | Abort Read
451  *
452  * Field Access Macros:
453  *
454  */
455 /*
456  * Enumerated value for register field ALT_SDMMC_CTL_ABT_RD_DATA
457  *
458  * No change
459  */
460 #define ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE 0x0
461 /*
462  * Enumerated value for register field ALT_SDMMC_CTL_ABT_RD_DATA
463  *
464  * Abort Read
465  */
466 #define ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE 0x1
467 
468 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_ABT_RD_DATA register field. */
469 #define ALT_SDMMC_CTL_ABT_RD_DATA_LSB 8
470 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_ABT_RD_DATA register field. */
471 #define ALT_SDMMC_CTL_ABT_RD_DATA_MSB 8
472 /* The width in bits of the ALT_SDMMC_CTL_ABT_RD_DATA register field. */
473 #define ALT_SDMMC_CTL_ABT_RD_DATA_WIDTH 1
474 /* The mask used to set the ALT_SDMMC_CTL_ABT_RD_DATA register field value. */
475 #define ALT_SDMMC_CTL_ABT_RD_DATA_SET_MSK 0x00000100
476 /* The mask used to clear the ALT_SDMMC_CTL_ABT_RD_DATA register field value. */
477 #define ALT_SDMMC_CTL_ABT_RD_DATA_CLR_MSK 0xfffffeff
478 /* The reset value of the ALT_SDMMC_CTL_ABT_RD_DATA register field. */
479 #define ALT_SDMMC_CTL_ABT_RD_DATA_RESET 0x0
480 /* Extracts the ALT_SDMMC_CTL_ABT_RD_DATA field value from a register. */
481 #define ALT_SDMMC_CTL_ABT_RD_DATA_GET(value) (((value) & 0x00000100) >> 8)
482 /* Produces a ALT_SDMMC_CTL_ABT_RD_DATA register field value suitable for setting the register. */
483 #define ALT_SDMMC_CTL_ABT_RD_DATA_SET(value) (((value) << 8) & 0x00000100)
484 
485 /*
486  * Field : send_ccsd
487  *
488  * 0-Clear this bit if DWC_mobile_storage does not reset the bit
489  * 1-Send Command Completion Signal Disable (CCSD) to CE-ATA
490  *
491  * device
492  *
493  * Field Enumeration Values:
494  *
495  * Enum | Value | Description
496  * :-----------------------------------|:------|:-------------------------------------------------
497  * ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT | 0x0 | Clear bit if SD/MMC does not reset the bit
498  * ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT | 0x1 | Send Command Completion Signal Disable (CCSD) to
499  * : | | CE-ATA device
500  *
501  * Field Access Macros:
502  *
503  */
504 /*
505  * Enumerated value for register field ALT_SDMMC_CTL_SEND_CCSD
506  *
507  * Clear bit if SD/MMC does not reset the bit
508  */
509 #define ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT 0x0
510 /*
511  * Enumerated value for register field ALT_SDMMC_CTL_SEND_CCSD
512  *
513  * Send Command Completion Signal Disable (CCSD) to CE-ATA device
514  */
515 #define ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT 0x1
516 
517 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_CCSD register field. */
518 #define ALT_SDMMC_CTL_SEND_CCSD_LSB 9
519 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_CCSD register field. */
520 #define ALT_SDMMC_CTL_SEND_CCSD_MSB 9
521 /* The width in bits of the ALT_SDMMC_CTL_SEND_CCSD register field. */
522 #define ALT_SDMMC_CTL_SEND_CCSD_WIDTH 1
523 /* The mask used to set the ALT_SDMMC_CTL_SEND_CCSD register field value. */
524 #define ALT_SDMMC_CTL_SEND_CCSD_SET_MSK 0x00000200
525 /* The mask used to clear the ALT_SDMMC_CTL_SEND_CCSD register field value. */
526 #define ALT_SDMMC_CTL_SEND_CCSD_CLR_MSK 0xfffffdff
527 /* The reset value of the ALT_SDMMC_CTL_SEND_CCSD register field. */
528 #define ALT_SDMMC_CTL_SEND_CCSD_RESET 0x0
529 /* Extracts the ALT_SDMMC_CTL_SEND_CCSD field value from a register. */
530 #define ALT_SDMMC_CTL_SEND_CCSD_GET(value) (((value) & 0x00000200) >> 9)
531 /* Produces a ALT_SDMMC_CTL_SEND_CCSD register field value suitable for setting the register. */
532 #define ALT_SDMMC_CTL_SEND_CCSD_SET(value) (((value) << 9) & 0x00000200)
533 
534 /*
535  * Field : send_auto_stop_ccsd
536  *
537  * 0-Clear bit if DWC_mobile_storage does not reset the bit
538  *
539  * 1-Send internally generated STOP after sending CCSD to
540  *
541  * CE-ATA device
542  *
543  * Field Enumeration Values:
544  *
545  * Enum | Value | Description
546  * :---------------------------------------------|:------|:-------------------------------------------
547  * ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT | 0x0 | Clear bit if SD/MMC does not reset the bit
548  * ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT | 0x1 | Send internally generated STOP.
549  *
550  * Field Access Macros:
551  *
552  */
553 /*
554  * Enumerated value for register field ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD
555  *
556  * Clear bit if SD/MMC does not reset the bit
557  */
558 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT 0x0
559 /*
560  * Enumerated value for register field ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD
561  *
562  * Send internally generated STOP.
563  */
564 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT 0x1
565 
566 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field. */
567 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_LSB 10
568 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field. */
569 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_MSB 10
570 /* The width in bits of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field. */
571 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_WIDTH 1
572 /* The mask used to set the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value. */
573 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET_MSK 0x00000400
574 /* The mask used to clear the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value. */
575 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_CLR_MSK 0xfffffbff
576 /* The reset value of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field. */
577 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_RESET 0x0
578 /* Extracts the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD field value from a register. */
579 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_GET(value) (((value) & 0x00000400) >> 10)
580 /* Produces a ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value suitable for setting the register. */
581 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET(value) (((value) << 10) & 0x00000400)
582 
583 /*
584  * Field : ceata_device_interrupt_status
585  *
586  * 0-Interrupts not enabled in CE-ATA device
587  *
588  * 1-Interrupts are enabled in CE-ATA device
589  *
590  * Field Enumeration Values:
591  *
592  * Enum | Value | Description
593  * :-------------------------------------------|:------|:----------------------------------------
594  * ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD | 0x0 | Interrupts not enabled in CE-ATA device
595  * ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END | 0x1 | Interrupts are enabled in CE-ATA device
596  *
597  * Field Access Macros:
598  *
599  */
600 /*
601  * Enumerated value for register field ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT
602  *
603  * Interrupts not enabled in CE-ATA device
604  */
605 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD 0x0
606 /*
607  * Enumerated value for register field ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT
608  *
609  * Interrupts are enabled in CE-ATA device
610  */
611 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END 0x1
612 
613 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field. */
614 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_LSB 11
615 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field. */
616 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_MSB 11
617 /* The width in bits of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field. */
618 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_WIDTH 1
619 /* The mask used to set the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value. */
620 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET_MSK 0x00000800
621 /* The mask used to clear the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value. */
622 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_CLR_MSK 0xfffff7ff
623 /* The reset value of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field. */
624 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_RESET 0x0
625 /* Extracts the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT field value from a register. */
626 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_GET(value) (((value) & 0x00000800) >> 11)
627 /* Produces a ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value suitable for setting the register. */
628 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET(value) (((value) << 11) & 0x00000800)
629 
630 /*
631  * Field : card_voltage_a
632  *
633  * Card regulator-A voltage setting; output to card_volt_a port.
634  *
635  * Optional feature; ports can be used as general-purpose outputs
636  *
637  * Field Access Macros:
638  *
639  */
640 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CARD_VOLTAGE_A register field. */
641 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_LSB 16
642 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CARD_VOLTAGE_A register field. */
643 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_MSB 19
644 /* The width in bits of the ALT_SDMMC_CTL_CARD_VOLTAGE_A register field. */
645 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_WIDTH 4
646 /* The mask used to set the ALT_SDMMC_CTL_CARD_VOLTAGE_A register field value. */
647 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_SET_MSK 0x000f0000
648 /* The mask used to clear the ALT_SDMMC_CTL_CARD_VOLTAGE_A register field value. */
649 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_CLR_MSK 0xfff0ffff
650 /* The reset value of the ALT_SDMMC_CTL_CARD_VOLTAGE_A register field. */
651 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_RESET 0x0
652 /* Extracts the ALT_SDMMC_CTL_CARD_VOLTAGE_A field value from a register. */
653 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_GET(value) (((value) & 0x000f0000) >> 16)
654 /* Produces a ALT_SDMMC_CTL_CARD_VOLTAGE_A register field value suitable for setting the register. */
655 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_SET(value) (((value) << 16) & 0x000f0000)
656 
657 /*
658  * Field : card_voltage_b
659  *
660  * Card regulator-B voltage setting; output to card_volt_b port.
661  *
662  * Optional feature; ports can be used as general-purpose outputs
663  *
664  * Field Access Macros:
665  *
666  */
667 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CARD_VOLTAGE_B register field. */
668 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_LSB 20
669 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CARD_VOLTAGE_B register field. */
670 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_MSB 23
671 /* The width in bits of the ALT_SDMMC_CTL_CARD_VOLTAGE_B register field. */
672 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_WIDTH 4
673 /* The mask used to set the ALT_SDMMC_CTL_CARD_VOLTAGE_B register field value. */
674 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_SET_MSK 0x00f00000
675 /* The mask used to clear the ALT_SDMMC_CTL_CARD_VOLTAGE_B register field value. */
676 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_CLR_MSK 0xff0fffff
677 /* The reset value of the ALT_SDMMC_CTL_CARD_VOLTAGE_B register field. */
678 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_RESET 0x0
679 /* Extracts the ALT_SDMMC_CTL_CARD_VOLTAGE_B field value from a register. */
680 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_GET(value) (((value) & 0x00f00000) >> 20)
681 /* Produces a ALT_SDMMC_CTL_CARD_VOLTAGE_B register field value suitable for setting the register. */
682 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_SET(value) (((value) << 20) & 0x00f00000)
683 
684 /*
685  * Field : enable_od_pullup
686  *
687  * External open-drain pullup
688  *
689  * 0-Disable
690  *
691  * 1-Enable
692  *
693  * Inverted value of this bit is output to ccmd_od_pullup_en_n port.
694  *
695  * When bit is set, command output always driven in open-drive mode; that is,
696  * DWC_mobile_storage drives either 0 or high impedance, and does not drive hard 1.
697  *
698  * Field Access Macros:
699  *
700  */
701 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_EN_OD_PULLUP register field. */
702 #define ALT_SDMMC_CTL_EN_OD_PULLUP_LSB 24
703 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_EN_OD_PULLUP register field. */
704 #define ALT_SDMMC_CTL_EN_OD_PULLUP_MSB 24
705 /* The width in bits of the ALT_SDMMC_CTL_EN_OD_PULLUP register field. */
706 #define ALT_SDMMC_CTL_EN_OD_PULLUP_WIDTH 1
707 /* The mask used to set the ALT_SDMMC_CTL_EN_OD_PULLUP register field value. */
708 #define ALT_SDMMC_CTL_EN_OD_PULLUP_SET_MSK 0x01000000
709 /* The mask used to clear the ALT_SDMMC_CTL_EN_OD_PULLUP register field value. */
710 #define ALT_SDMMC_CTL_EN_OD_PULLUP_CLR_MSK 0xfeffffff
711 /* The reset value of the ALT_SDMMC_CTL_EN_OD_PULLUP register field. */
712 #define ALT_SDMMC_CTL_EN_OD_PULLUP_RESET 0x0
713 /* Extracts the ALT_SDMMC_CTL_EN_OD_PULLUP field value from a register. */
714 #define ALT_SDMMC_CTL_EN_OD_PULLUP_GET(value) (((value) & 0x01000000) >> 24)
715 /* Produces a ALT_SDMMC_CTL_EN_OD_PULLUP register field value suitable for setting the register. */
716 #define ALT_SDMMC_CTL_EN_OD_PULLUP_SET(value) (((value) << 24) & 0x01000000)
717 
718 /*
719  * Field : use_internal_dmac
720  *
721  * Present only for the Internal DMAC configuration; else, it is reserved.
722  *
723  * 0-The host performs data transfers through the slave interface
724  *
725  * 1-Internal DMAC used for data transfer
726  *
727  * Field Enumeration Values:
728  *
729  * Enum | Value | Description
730  * :---------------------------------------|:------|:--------------------------------------------
731  * ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD | 0x0 | The host performs data transfers thru slave
732  * : | | interface
733  * ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END | 0x1 | Internal DMAC used for data transfer
734  *
735  * Field Access Macros:
736  *
737  */
738 /*
739  * Enumerated value for register field ALT_SDMMC_CTL_USE_INTERNAL_DMAC
740  *
741  * The host performs data transfers thru slave interface
742  */
743 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD 0x0
744 /*
745  * Enumerated value for register field ALT_SDMMC_CTL_USE_INTERNAL_DMAC
746  *
747  * Internal DMAC used for data transfer
748  */
749 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END 0x1
750 
751 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field. */
752 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_LSB 25
753 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field. */
754 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_MSB 25
755 /* The width in bits of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field. */
756 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_WIDTH 1
757 /* The mask used to set the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value. */
758 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET_MSK 0x02000000
759 /* The mask used to clear the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value. */
760 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_CLR_MSK 0xfdffffff
761 /* The reset value of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field. */
762 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_RESET 0x0
763 /* Extracts the ALT_SDMMC_CTL_USE_INTERNAL_DMAC field value from a register. */
764 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_GET(value) (((value) & 0x02000000) >> 25)
765 /* Produces a ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value suitable for setting the register. */
766 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET(value) (((value) << 25) & 0x02000000)
767 
768 #ifndef __ASSEMBLY__
769 /*
770  * WARNING: The C register and register group struct declarations are provided for
771  * convenience and illustrative purposes. They should, however, be used with
772  * caution as the C language standard provides no guarantees about the alignment or
773  * atomicity of device memory accesses. The recommended practice for writing
774  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
775  * alt_write_word() functions.
776  *
777  * The struct declaration for register ALT_SDMMC_CTL.
778  */
779 struct ALT_SDMMC_CTL_s
780 {
781  uint32_t controller_reset : 1; /* ALT_SDMMC_CTL_CTLLER_RST */
782  uint32_t fifo_reset : 1; /* ALT_SDMMC_CTL_FIFO_RST */
783  uint32_t dma_reset : 1; /* ALT_SDMMC_CTL_DMA_RST */
784  uint32_t : 1; /* *UNDEFINED* */
785  uint32_t int_enable : 1; /* ALT_SDMMC_CTL_INT_EN */
786  uint32_t dma_enable : 1; /* ALT_SDMMC_CTL_DMA_EN */
787  uint32_t read_wait : 1; /* ALT_SDMMC_CTL_RD_WAIT */
788  uint32_t send_irq_response : 1; /* ALT_SDMMC_CTL_SEND_IRQ_RESPONSE */
789  uint32_t abort_read_data : 1; /* ALT_SDMMC_CTL_ABT_RD_DATA */
790  uint32_t send_ccsd : 1; /* ALT_SDMMC_CTL_SEND_CCSD */
791  uint32_t send_auto_stop_ccsd : 1; /* ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD */
792  uint32_t ceata_device_interrupt_status : 1; /* ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT */
793  uint32_t : 4; /* *UNDEFINED* */
794  uint32_t card_voltage_a : 4; /* ALT_SDMMC_CTL_CARD_VOLTAGE_A */
795  uint32_t card_voltage_b : 4; /* ALT_SDMMC_CTL_CARD_VOLTAGE_B */
796  uint32_t enable_od_pullup : 1; /* ALT_SDMMC_CTL_EN_OD_PULLUP */
797  uint32_t use_internal_dmac : 1; /* ALT_SDMMC_CTL_USE_INTERNAL_DMAC */
798  uint32_t : 6; /* *UNDEFINED* */
799 };
800 
801 /* The typedef declaration for register ALT_SDMMC_CTL. */
802 typedef volatile struct ALT_SDMMC_CTL_s ALT_SDMMC_CTL_t;
803 #endif /* __ASSEMBLY__ */
804 
805 /* The reset value of the ALT_SDMMC_CTL register. */
806 #define ALT_SDMMC_CTL_RESET 0x00000000
807 /* The byte offset of the ALT_SDMMC_CTL register from the beginning of the component. */
808 #define ALT_SDMMC_CTL_OFST 0x0
809 
810 /*
811  * Register : pwren
812  *
813  * Power Enable Register
814  *
815  * Register Layout
816  *
817  * Bits | Access | Reset | Description
818  * :-------|:-------|:------|:-------------------------
819  * [0] | RW | 0x0 | ALT_SDMMC_PWREN_POWER_EN
820  * [31:1] | ??? | 0x0 | *UNDEFINED*
821  *
822  */
823 /*
824  * Field : power_enable
825  *
826  * Power on/off switch for up to 16 cards; for example, bit[0] controls card 0.Once
827  * power is turned on, firmware should wait for regulator/switch ramp-up time
828  * before trying to initialize card.
829  *
830  * 0-power off
831  *
832  * 1-power on
833  *
834  * Only NUM_CARDS number of bits are implemented.Bit values output to card_power_en
835  * port. Optional feature; ports can be used as general-purpose outputs.
836  *
837  * Field Enumeration Values:
838  *
839  * Enum | Value | Description
840  * :-------------------------------|:------|:------------
841  * ALT_SDMMC_PWREN_POWER_EN_E_OFF | 0x0 | Power Off
842  * ALT_SDMMC_PWREN_POWER_EN_E_ON | 0x1 | Power On
843  *
844  * Field Access Macros:
845  *
846  */
847 /*
848  * Enumerated value for register field ALT_SDMMC_PWREN_POWER_EN
849  *
850  * Power Off
851  */
852 #define ALT_SDMMC_PWREN_POWER_EN_E_OFF 0x0
853 /*
854  * Enumerated value for register field ALT_SDMMC_PWREN_POWER_EN
855  *
856  * Power On
857  */
858 #define ALT_SDMMC_PWREN_POWER_EN_E_ON 0x1
859 
860 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_PWREN_POWER_EN register field. */
861 #define ALT_SDMMC_PWREN_POWER_EN_LSB 0
862 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_PWREN_POWER_EN register field. */
863 #define ALT_SDMMC_PWREN_POWER_EN_MSB 0
864 /* The width in bits of the ALT_SDMMC_PWREN_POWER_EN register field. */
865 #define ALT_SDMMC_PWREN_POWER_EN_WIDTH 1
866 /* The mask used to set the ALT_SDMMC_PWREN_POWER_EN register field value. */
867 #define ALT_SDMMC_PWREN_POWER_EN_SET_MSK 0x00000001
868 /* The mask used to clear the ALT_SDMMC_PWREN_POWER_EN register field value. */
869 #define ALT_SDMMC_PWREN_POWER_EN_CLR_MSK 0xfffffffe
870 /* The reset value of the ALT_SDMMC_PWREN_POWER_EN register field. */
871 #define ALT_SDMMC_PWREN_POWER_EN_RESET 0x0
872 /* Extracts the ALT_SDMMC_PWREN_POWER_EN field value from a register. */
873 #define ALT_SDMMC_PWREN_POWER_EN_GET(value) (((value) & 0x00000001) >> 0)
874 /* Produces a ALT_SDMMC_PWREN_POWER_EN register field value suitable for setting the register. */
875 #define ALT_SDMMC_PWREN_POWER_EN_SET(value) (((value) << 0) & 0x00000001)
876 
877 #ifndef __ASSEMBLY__
878 /*
879  * WARNING: The C register and register group struct declarations are provided for
880  * convenience and illustrative purposes. They should, however, be used with
881  * caution as the C language standard provides no guarantees about the alignment or
882  * atomicity of device memory accesses. The recommended practice for writing
883  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
884  * alt_write_word() functions.
885  *
886  * The struct declaration for register ALT_SDMMC_PWREN.
887  */
888 struct ALT_SDMMC_PWREN_s
889 {
890  uint32_t power_enable : 1; /* ALT_SDMMC_PWREN_POWER_EN */
891  uint32_t : 31; /* *UNDEFINED* */
892 };
893 
894 /* The typedef declaration for register ALT_SDMMC_PWREN. */
895 typedef volatile struct ALT_SDMMC_PWREN_s ALT_SDMMC_PWREN_t;
896 #endif /* __ASSEMBLY__ */
897 
898 /* The reset value of the ALT_SDMMC_PWREN register. */
899 #define ALT_SDMMC_PWREN_RESET 0x00000000
900 /* The byte offset of the ALT_SDMMC_PWREN register from the beginning of the component. */
901 #define ALT_SDMMC_PWREN_OFST 0x4
902 
903 /*
904  * Register : clkdiv
905  *
906  * Clock Divider Register
907  *
908  * Register Layout
909  *
910  * Bits | Access | Reset | Description
911  * :--------|:-------|:------|:---------------------------
912  * [7:0] | RW | 0x0 | ALT_SDMMC_CLKDIV_CLK_DIVR0
913  * [15:8] | R | 0x0 | ALT_SDMMC_CLKDIV_CLK_DIVR1
914  * [23:16] | R | 0x0 | ALT_SDMMC_CLKDIV_CLK_DIVR2
915  * [31:24] | R | 0x0 | ALT_SDMMC_CLKDIV_CLK_DIVR3
916  *
917  */
918 /*
919  * Field : clk_divider0
920  *
921  * Clock divider-0 value. Clock division is 2*n. For example, value of 0 means
922  * divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2,
923  * value of "ff" means divide by 2*255 = 510, and so on.
924  *
925  * Field Access Macros:
926  *
927  */
928 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field. */
929 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_LSB 0
930 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field. */
931 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_MSB 7
932 /* The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field. */
933 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_WIDTH 8
934 /* The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value. */
935 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET_MSK 0x000000ff
936 /* The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value. */
937 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_CLR_MSK 0xffffff00
938 /* The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field. */
939 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_RESET 0x0
940 /* Extracts the ALT_SDMMC_CLKDIV_CLK_DIVR0 field value from a register. */
941 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_GET(value) (((value) & 0x000000ff) >> 0)
942 /* Produces a ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value suitable for setting the register. */
943 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET(value) (((value) << 0) & 0x000000ff)
944 
945 /*
946  * Field : clk_divider1
947  *
948  * Clock divider-1 value. Clock division is 2*n. For example, value of 0 means
949  * divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2,
950  * value of "ff" means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode,
951  * bits not implemented because only one clock divider is supported
952  *
953  * Field Access Macros:
954  *
955  */
956 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR1 register field. */
957 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_LSB 8
958 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR1 register field. */
959 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_MSB 15
960 /* The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVR1 register field. */
961 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_WIDTH 8
962 /* The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVR1 register field value. */
963 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_SET_MSK 0x0000ff00
964 /* The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVR1 register field value. */
965 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_CLR_MSK 0xffff00ff
966 /* The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVR1 register field. */
967 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_RESET 0x0
968 /* Extracts the ALT_SDMMC_CLKDIV_CLK_DIVR1 field value from a register. */
969 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_GET(value) (((value) & 0x0000ff00) >> 8)
970 /* Produces a ALT_SDMMC_CLKDIV_CLK_DIVR1 register field value suitable for setting the register. */
971 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_SET(value) (((value) << 8) & 0x0000ff00)
972 
973 /*
974  * Field : clk_divider2
975  *
976  * Clock divider-2 value. Clock division is 2*n. For example, value of 0 means
977  * divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2,
978  * value of "ff" means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode,
979  * bits not implemented because only one clock divider is supported.
980  *
981  * Field Access Macros:
982  *
983  */
984 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR2 register field. */
985 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_LSB 16
986 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR2 register field. */
987 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_MSB 23
988 /* The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVR2 register field. */
989 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_WIDTH 8
990 /* The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVR2 register field value. */
991 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_SET_MSK 0x00ff0000
992 /* The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVR2 register field value. */
993 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_CLR_MSK 0xff00ffff
994 /* The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVR2 register field. */
995 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_RESET 0x0
996 /* Extracts the ALT_SDMMC_CLKDIV_CLK_DIVR2 field value from a register. */
997 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_GET(value) (((value) & 0x00ff0000) >> 16)
998 /* Produces a ALT_SDMMC_CLKDIV_CLK_DIVR2 register field value suitable for setting the register. */
999 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_SET(value) (((value) << 16) & 0x00ff0000)
1000 
1001 /*
1002  * Field : clk_divider3
1003  *
1004  * Clock divider-3 value. Clock division is 2*n. For example, value of 0 means
1005  * divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a
1006  * value of "ff" means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode,
1007  * bits not implemented because only one clock divider is supported.
1008  *
1009  * Field Access Macros:
1010  *
1011  */
1012 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR3 register field. */
1013 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_LSB 24
1014 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR3 register field. */
1015 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_MSB 31
1016 /* The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVR3 register field. */
1017 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_WIDTH 8
1018 /* The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVR3 register field value. */
1019 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_SET_MSK 0xff000000
1020 /* The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVR3 register field value. */
1021 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_CLR_MSK 0x00ffffff
1022 /* The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVR3 register field. */
1023 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_RESET 0x0
1024 /* Extracts the ALT_SDMMC_CLKDIV_CLK_DIVR3 field value from a register. */
1025 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_GET(value) (((value) & 0xff000000) >> 24)
1026 /* Produces a ALT_SDMMC_CLKDIV_CLK_DIVR3 register field value suitable for setting the register. */
1027 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_SET(value) (((value) << 24) & 0xff000000)
1028 
1029 #ifndef __ASSEMBLY__
1030 /*
1031  * WARNING: The C register and register group struct declarations are provided for
1032  * convenience and illustrative purposes. They should, however, be used with
1033  * caution as the C language standard provides no guarantees about the alignment or
1034  * atomicity of device memory accesses. The recommended practice for writing
1035  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1036  * alt_write_word() functions.
1037  *
1038  * The struct declaration for register ALT_SDMMC_CLKDIV.
1039  */
1040 struct ALT_SDMMC_CLKDIV_s
1041 {
1042  uint32_t clk_divider0 : 8; /* ALT_SDMMC_CLKDIV_CLK_DIVR0 */
1043  const uint32_t clk_divider1 : 8; /* ALT_SDMMC_CLKDIV_CLK_DIVR1 */
1044  const uint32_t clk_divider2 : 8; /* ALT_SDMMC_CLKDIV_CLK_DIVR2 */
1045  const uint32_t clk_divider3 : 8; /* ALT_SDMMC_CLKDIV_CLK_DIVR3 */
1046 };
1047 
1048 /* The typedef declaration for register ALT_SDMMC_CLKDIV. */
1049 typedef volatile struct ALT_SDMMC_CLKDIV_s ALT_SDMMC_CLKDIV_t;
1050 #endif /* __ASSEMBLY__ */
1051 
1052 /* The reset value of the ALT_SDMMC_CLKDIV register. */
1053 #define ALT_SDMMC_CLKDIV_RESET 0x00000000
1054 /* The byte offset of the ALT_SDMMC_CLKDIV register from the beginning of the component. */
1055 #define ALT_SDMMC_CLKDIV_OFST 0x8
1056 
1057 /*
1058  * Register : clksrc
1059  *
1060  * Clock Source Register
1061  *
1062  * Register Layout
1063  *
1064  * Bits | Access | Reset | Description
1065  * :-------|:-------|:------|:-------------------------
1066  * [31:0] | R | 0x0 | ALT_SDMMC_CLKSRC_CLK_SRC
1067  *
1068  */
1069 /*
1070  * Field : clk_source
1071  *
1072  * Clock divider source for up to 16 SD cards supported. Each card has two bits
1073  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
1074  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
1075  * on bit value.
1076  *
1077  * 00 Clock divider 0
1078  *
1079  * 01 Clock divider 1
1080  *
1081  * 10 Clock divider 2
1082  *
1083  * 11 Clock divider 3
1084  *
1085  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
1086  * always from clock divider 0, and this register is not implemented.
1087  *
1088  * Field Enumeration Values:
1089  *
1090  * Enum | Value | Description
1091  * :-----------------------------------|:------|:----------------
1092  * ALT_SDMMC_CLKSRC_CLK_SRC_E_CLKDIV0 | 0x0 | Clock divider 0
1093  *
1094  * Field Access Macros:
1095  *
1096  */
1097 /*
1098  * Enumerated value for register field ALT_SDMMC_CLKSRC_CLK_SRC
1099  *
1100  * Clock divider 0
1101  */
1102 #define ALT_SDMMC_CLKSRC_CLK_SRC_E_CLKDIV0 0x0
1103 
1104 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CLK_SRC register field. */
1105 #define ALT_SDMMC_CLKSRC_CLK_SRC_LSB 0
1106 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CLK_SRC register field. */
1107 #define ALT_SDMMC_CLKSRC_CLK_SRC_MSB 31
1108 /* The width in bits of the ALT_SDMMC_CLKSRC_CLK_SRC register field. */
1109 #define ALT_SDMMC_CLKSRC_CLK_SRC_WIDTH 32
1110 /* The mask used to set the ALT_SDMMC_CLKSRC_CLK_SRC register field value. */
1111 #define ALT_SDMMC_CLKSRC_CLK_SRC_SET_MSK 0xffffffff
1112 /* The mask used to clear the ALT_SDMMC_CLKSRC_CLK_SRC register field value. */
1113 #define ALT_SDMMC_CLKSRC_CLK_SRC_CLR_MSK 0x00000000
1114 /* The reset value of the ALT_SDMMC_CLKSRC_CLK_SRC register field. */
1115 #define ALT_SDMMC_CLKSRC_CLK_SRC_RESET 0x0
1116 /* Extracts the ALT_SDMMC_CLKSRC_CLK_SRC field value from a register. */
1117 #define ALT_SDMMC_CLKSRC_CLK_SRC_GET(value) (((value) & 0xffffffff) >> 0)
1118 /* Produces a ALT_SDMMC_CLKSRC_CLK_SRC register field value suitable for setting the register. */
1119 #define ALT_SDMMC_CLKSRC_CLK_SRC_SET(value) (((value) << 0) & 0xffffffff)
1120 
1121 #ifndef __ASSEMBLY__
1122 /*
1123  * WARNING: The C register and register group struct declarations are provided for
1124  * convenience and illustrative purposes. They should, however, be used with
1125  * caution as the C language standard provides no guarantees about the alignment or
1126  * atomicity of device memory accesses. The recommended practice for writing
1127  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1128  * alt_write_word() functions.
1129  *
1130  * The struct declaration for register ALT_SDMMC_CLKSRC.
1131  */
1132 struct ALT_SDMMC_CLKSRC_s
1133 {
1134  const uint32_t clk_source : 32; /* ALT_SDMMC_CLKSRC_CLK_SRC */
1135 };
1136 
1137 /* The typedef declaration for register ALT_SDMMC_CLKSRC. */
1138 typedef volatile struct ALT_SDMMC_CLKSRC_s ALT_SDMMC_CLKSRC_t;
1139 #endif /* __ASSEMBLY__ */
1140 
1141 /* The reset value of the ALT_SDMMC_CLKSRC register. */
1142 #define ALT_SDMMC_CLKSRC_RESET 0x00000000
1143 /* The byte offset of the ALT_SDMMC_CLKSRC register from the beginning of the component. */
1144 #define ALT_SDMMC_CLKSRC_OFST 0xc
1145 
1146 /*
1147  * Register : clkena
1148  *
1149  * Clock Enable Register
1150  *
1151  * Register Layout
1152  *
1153  * Bits | Access | Reset | Description
1154  * :--------|:-------|:------|:--------------------------------
1155  * [0] | RW | 0x0 | ALT_SDMMC_CLKENA_CCLK_EN
1156  * [15:1] | ??? | 0x0 | *UNDEFINED*
1157  * [16] | RW | 0x0 | ALT_SDMMC_CLKENA_CCLK_LOW_POWER
1158  * [31:17] | ??? | 0x0 | *UNDEFINED*
1159  *
1160  */
1161 /*
1162  * Field : cclk_enable
1163  *
1164  * Clock-enable control for up to 16 SD card clocks and one MMC card clock
1165  * supported.
1166  *
1167  * 0-Clock disabled
1168  *
1169  * 1-Clock enabled
1170  *
1171  * In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_enable[0]
1172  * is used.
1173  *
1174  * Field Enumeration Values:
1175  *
1176  * Enum | Value | Description
1177  * :--------------------------------|:------|:---------------
1178  * ALT_SDMMC_CLKENA_CCLK_EN_E_DISD | 0x0 | SD/MMC Disable
1179  * ALT_SDMMC_CLKENA_CCLK_EN_E_END | 0x1 | SD/MMC Enable
1180  *
1181  * Field Access Macros:
1182  *
1183  */
1184 /*
1185  * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_EN
1186  *
1187  * SD/MMC Disable
1188  */
1189 #define ALT_SDMMC_CLKENA_CCLK_EN_E_DISD 0x0
1190 /*
1191  * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_EN
1192  *
1193  * SD/MMC Enable
1194  */
1195 #define ALT_SDMMC_CLKENA_CCLK_EN_E_END 0x1
1196 
1197 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKENA_CCLK_EN register field. */
1198 #define ALT_SDMMC_CLKENA_CCLK_EN_LSB 0
1199 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKENA_CCLK_EN register field. */
1200 #define ALT_SDMMC_CLKENA_CCLK_EN_MSB 0
1201 /* The width in bits of the ALT_SDMMC_CLKENA_CCLK_EN register field. */
1202 #define ALT_SDMMC_CLKENA_CCLK_EN_WIDTH 1
1203 /* The mask used to set the ALT_SDMMC_CLKENA_CCLK_EN register field value. */
1204 #define ALT_SDMMC_CLKENA_CCLK_EN_SET_MSK 0x00000001
1205 /* The mask used to clear the ALT_SDMMC_CLKENA_CCLK_EN register field value. */
1206 #define ALT_SDMMC_CLKENA_CCLK_EN_CLR_MSK 0xfffffffe
1207 /* The reset value of the ALT_SDMMC_CLKENA_CCLK_EN register field. */
1208 #define ALT_SDMMC_CLKENA_CCLK_EN_RESET 0x0
1209 /* Extracts the ALT_SDMMC_CLKENA_CCLK_EN field value from a register. */
1210 #define ALT_SDMMC_CLKENA_CCLK_EN_GET(value) (((value) & 0x00000001) >> 0)
1211 /* Produces a ALT_SDMMC_CLKENA_CCLK_EN register field value suitable for setting the register. */
1212 #define ALT_SDMMC_CLKENA_CCLK_EN_SET(value) (((value) << 0) & 0x00000001)
1213 
1214 /*
1215  * Field : cclk_low_power
1216  *
1217  * Low-power control for up to 16 SD card clocks and one MMC card clock supported.
1218  *
1219  * 0-Non-low-power mode
1220  *
1221  * 1-Low-power mode; stop clock when card in IDLE (should be normally set to only
1222  * MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock
1223  * should not be stopped).
1224  *
1225  * In MMC-Ver3.3-only mode, since there is only one cclk_out, only
1226  * cclk_low_power[0] is used.
1227  *
1228  * Field Enumeration Values:
1229  *
1230  * Enum | Value | Description
1231  * :---------------------------------------|:------|:-------------------
1232  * ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_DISD | 0x0 | Non-low-power mode
1233  * ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_END | 0x1 | Low-power mode
1234  *
1235  * Field Access Macros:
1236  *
1237  */
1238 /*
1239  * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_LOW_POWER
1240  *
1241  * Non-low-power mode
1242  */
1243 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_DISD 0x0
1244 /*
1245  * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_LOW_POWER
1246  *
1247  * Low-power mode
1248  */
1249 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_END 0x1
1250 
1251 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field. */
1252 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_LSB 16
1253 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field. */
1254 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_MSB 16
1255 /* The width in bits of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field. */
1256 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_WIDTH 1
1257 /* The mask used to set the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field value. */
1258 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET_MSK 0x00010000
1259 /* The mask used to clear the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field value. */
1260 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_CLR_MSK 0xfffeffff
1261 /* The reset value of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field. */
1262 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_RESET 0x0
1263 /* Extracts the ALT_SDMMC_CLKENA_CCLK_LOW_POWER field value from a register. */
1264 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_GET(value) (((value) & 0x00010000) >> 16)
1265 /* Produces a ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field value suitable for setting the register. */
1266 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET(value) (((value) << 16) & 0x00010000)
1267 
1268 #ifndef __ASSEMBLY__
1269 /*
1270  * WARNING: The C register and register group struct declarations are provided for
1271  * convenience and illustrative purposes. They should, however, be used with
1272  * caution as the C language standard provides no guarantees about the alignment or
1273  * atomicity of device memory accesses. The recommended practice for writing
1274  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1275  * alt_write_word() functions.
1276  *
1277  * The struct declaration for register ALT_SDMMC_CLKENA.
1278  */
1279 struct ALT_SDMMC_CLKENA_s
1280 {
1281  uint32_t cclk_enable : 1; /* ALT_SDMMC_CLKENA_CCLK_EN */
1282  uint32_t : 15; /* *UNDEFINED* */
1283  uint32_t cclk_low_power : 1; /* ALT_SDMMC_CLKENA_CCLK_LOW_POWER */
1284  uint32_t : 15; /* *UNDEFINED* */
1285 };
1286 
1287 /* The typedef declaration for register ALT_SDMMC_CLKENA. */
1288 typedef volatile struct ALT_SDMMC_CLKENA_s ALT_SDMMC_CLKENA_t;
1289 #endif /* __ASSEMBLY__ */
1290 
1291 /* The reset value of the ALT_SDMMC_CLKENA register. */
1292 #define ALT_SDMMC_CLKENA_RESET 0x00000000
1293 /* The byte offset of the ALT_SDMMC_CLKENA register from the beginning of the component. */
1294 #define ALT_SDMMC_CLKENA_OFST 0x10
1295 
1296 /*
1297  * Register : tmout
1298  *
1299  * Timeout Register
1300  *
1301  * Register Layout
1302  *
1303  * Bits | Access | Reset | Description
1304  * :-------|:-------|:---------|:-----------------------------
1305  * [7:0] | RW | 0x40 | ALT_SDMMC_TMOUT_RESPONSE_TMO
1306  * [31:8] | RW | 0xffffff | ALT_SDMMC_TMOUT_DATA_TMO
1307  *
1308  */
1309 /*
1310  * Field : response_timeout
1311  *
1312  * Response timeout value.
1313  *
1314  * Value is in number of card output clocks cclk_out.
1315  *
1316  * Field Access Macros:
1317  *
1318  */
1319 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_TMOUT_RESPONSE_TMO register field. */
1320 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_LSB 0
1321 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_TMOUT_RESPONSE_TMO register field. */
1322 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_MSB 7
1323 /* The width in bits of the ALT_SDMMC_TMOUT_RESPONSE_TMO register field. */
1324 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_WIDTH 8
1325 /* The mask used to set the ALT_SDMMC_TMOUT_RESPONSE_TMO register field value. */
1326 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET_MSK 0x000000ff
1327 /* The mask used to clear the ALT_SDMMC_TMOUT_RESPONSE_TMO register field value. */
1328 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_CLR_MSK 0xffffff00
1329 /* The reset value of the ALT_SDMMC_TMOUT_RESPONSE_TMO register field. */
1330 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_RESET 0x40
1331 /* Extracts the ALT_SDMMC_TMOUT_RESPONSE_TMO field value from a register. */
1332 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_GET(value) (((value) & 0x000000ff) >> 0)
1333 /* Produces a ALT_SDMMC_TMOUT_RESPONSE_TMO register field value suitable for setting the register. */
1334 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET(value) (((value) << 0) & 0x000000ff)
1335 
1336 /*
1337  * Field : data_timeout
1338  *
1339  * Value for card Data Read Timeout; same value also used for Data
1340  *
1341  * Starvation by Host timeout. The timeout counter is started only after the card
1342  * clock is stopped.Value is in number of card output clocks cclk_out of selected
1343  * card.
1344  *
1345  * Note: The software timer should be used if the timeout value is in the order
1346  *
1347  * of 100 ms. In this case, read data timeout interrupt needs to be disabled.
1348  *
1349  * Field Access Macros:
1350  *
1351  */
1352 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_TMOUT_DATA_TMO register field. */
1353 #define ALT_SDMMC_TMOUT_DATA_TMO_LSB 8
1354 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_TMOUT_DATA_TMO register field. */
1355 #define ALT_SDMMC_TMOUT_DATA_TMO_MSB 31
1356 /* The width in bits of the ALT_SDMMC_TMOUT_DATA_TMO register field. */
1357 #define ALT_SDMMC_TMOUT_DATA_TMO_WIDTH 24
1358 /* The mask used to set the ALT_SDMMC_TMOUT_DATA_TMO register field value. */
1359 #define ALT_SDMMC_TMOUT_DATA_TMO_SET_MSK 0xffffff00
1360 /* The mask used to clear the ALT_SDMMC_TMOUT_DATA_TMO register field value. */
1361 #define ALT_SDMMC_TMOUT_DATA_TMO_CLR_MSK 0x000000ff
1362 /* The reset value of the ALT_SDMMC_TMOUT_DATA_TMO register field. */
1363 #define ALT_SDMMC_TMOUT_DATA_TMO_RESET 0xffffff
1364 /* Extracts the ALT_SDMMC_TMOUT_DATA_TMO field value from a register. */
1365 #define ALT_SDMMC_TMOUT_DATA_TMO_GET(value) (((value) & 0xffffff00) >> 8)
1366 /* Produces a ALT_SDMMC_TMOUT_DATA_TMO register field value suitable for setting the register. */
1367 #define ALT_SDMMC_TMOUT_DATA_TMO_SET(value) (((value) << 8) & 0xffffff00)
1368 
1369 #ifndef __ASSEMBLY__
1370 /*
1371  * WARNING: The C register and register group struct declarations are provided for
1372  * convenience and illustrative purposes. They should, however, be used with
1373  * caution as the C language standard provides no guarantees about the alignment or
1374  * atomicity of device memory accesses. The recommended practice for writing
1375  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1376  * alt_write_word() functions.
1377  *
1378  * The struct declaration for register ALT_SDMMC_TMOUT.
1379  */
1380 struct ALT_SDMMC_TMOUT_s
1381 {
1382  uint32_t response_timeout : 8; /* ALT_SDMMC_TMOUT_RESPONSE_TMO */
1383  uint32_t data_timeout : 24; /* ALT_SDMMC_TMOUT_DATA_TMO */
1384 };
1385 
1386 /* The typedef declaration for register ALT_SDMMC_TMOUT. */
1387 typedef volatile struct ALT_SDMMC_TMOUT_s ALT_SDMMC_TMOUT_t;
1388 #endif /* __ASSEMBLY__ */
1389 
1390 /* The reset value of the ALT_SDMMC_TMOUT register. */
1391 #define ALT_SDMMC_TMOUT_RESET 0xffffff40
1392 /* The byte offset of the ALT_SDMMC_TMOUT register from the beginning of the component. */
1393 #define ALT_SDMMC_TMOUT_OFST 0x14
1394 
1395 /*
1396  * Register : ctype
1397  *
1398  * Card Type Register
1399  *
1400  * Register Layout
1401  *
1402  * Bits | Access | Reset | Description
1403  * :--------|:-------|:------|:----------------------------
1404  * [0] | RW | 0x0 | ALT_SDMMC_CTYPE_CARD_WIDTH2
1405  * [15:1] | ??? | 0x0 | *UNDEFINED*
1406  * [16] | RW | 0x0 | ALT_SDMMC_CTYPE_CARD_WIDTH1
1407  * [31:17] | ??? | 0x0 | *UNDEFINED*
1408  *
1409  */
1410 /*
1411  * Field : card_width2
1412  *
1413  * One bit per card indicates if card is 1-bit or 4-bit:
1414  *
1415  * 0-1-bit mode
1416  *
1417  * 1-4-bit mode
1418  *
1419  * Bit[15] corresponds to card[15], bit[0] corresponds to card[0].
1420  *
1421  * Only NUM_CARDS*2 number of bits are implemented.
1422  *
1423  * Field Enumeration Values:
1424  *
1425  * Enum | Value | Description
1426  * :--------------------------------------|:------|:------------
1427  * ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD1BIT | 0x0 | 1-bit mode
1428  * ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD4BIT | 0x1 | 4-bit mode
1429  *
1430  * Field Access Macros:
1431  *
1432  */
1433 /*
1434  * Enumerated value for register field ALT_SDMMC_CTYPE_CARD_WIDTH2
1435  *
1436  * 1-bit mode
1437  */
1438 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD1BIT 0x0
1439 /*
1440  * Enumerated value for register field ALT_SDMMC_CTYPE_CARD_WIDTH2
1441  *
1442  * 4-bit mode
1443  */
1444 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD4BIT 0x1
1445 
1446 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field. */
1447 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_LSB 0
1448 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field. */
1449 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_MSB 0
1450 /* The width in bits of the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field. */
1451 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_WIDTH 1
1452 /* The mask used to set the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field value. */
1453 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET_MSK 0x00000001
1454 /* The mask used to clear the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field value. */
1455 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_CLR_MSK 0xfffffffe
1456 /* The reset value of the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field. */
1457 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_RESET 0x0
1458 /* Extracts the ALT_SDMMC_CTYPE_CARD_WIDTH2 field value from a register. */
1459 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_GET(value) (((value) & 0x00000001) >> 0)
1460 /* Produces a ALT_SDMMC_CTYPE_CARD_WIDTH2 register field value suitable for setting the register. */
1461 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET(value) (((value) << 0) & 0x00000001)
1462 
1463 /*
1464  * Field : card_width1
1465  *
1466  * One bit per card indicates if card is 8-bit:
1467  *
1468  * 0-Non 8-bit mode
1469  *
1470  * 1-8-bit mode
1471  *
1472  * Bit[31] corresponds to card[15]; bit[16] corresponds to card[0].
1473  *
1474  * Field Enumeration Values:
1475  *
1476  * Enum | Value | Description
1477  * :--------------------------------------|:------|:---------------
1478  * ALT_SDMMC_CTYPE_CARD_WIDTH1_E_NON8BIT | 0x0 | Non 8-bit mode
1479  * ALT_SDMMC_CTYPE_CARD_WIDTH1_E_MOD8BIT | 0x1 | 8-bit mode
1480  *
1481  * Field Access Macros:
1482  *
1483  */
1484 /*
1485  * Enumerated value for register field ALT_SDMMC_CTYPE_CARD_WIDTH1
1486  *
1487  * Non 8-bit mode
1488  */
1489 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_NON8BIT 0x0
1490 /*
1491  * Enumerated value for register field ALT_SDMMC_CTYPE_CARD_WIDTH1
1492  *
1493  * 8-bit mode
1494  */
1495 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_MOD8BIT 0x1
1496 
1497 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field. */
1498 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_LSB 16
1499 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field. */
1500 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_MSB 16
1501 /* The width in bits of the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field. */
1502 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_WIDTH 1
1503 /* The mask used to set the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field value. */
1504 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET_MSK 0x00010000
1505 /* The mask used to clear the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field value. */
1506 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_CLR_MSK 0xfffeffff
1507 /* The reset value of the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field. */
1508 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_RESET 0x0
1509 /* Extracts the ALT_SDMMC_CTYPE_CARD_WIDTH1 field value from a register. */
1510 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_GET(value) (((value) & 0x00010000) >> 16)
1511 /* Produces a ALT_SDMMC_CTYPE_CARD_WIDTH1 register field value suitable for setting the register. */
1512 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET(value) (((value) << 16) & 0x00010000)
1513 
1514 #ifndef __ASSEMBLY__
1515 /*
1516  * WARNING: The C register and register group struct declarations are provided for
1517  * convenience and illustrative purposes. They should, however, be used with
1518  * caution as the C language standard provides no guarantees about the alignment or
1519  * atomicity of device memory accesses. The recommended practice for writing
1520  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1521  * alt_write_word() functions.
1522  *
1523  * The struct declaration for register ALT_SDMMC_CTYPE.
1524  */
1525 struct ALT_SDMMC_CTYPE_s
1526 {
1527  uint32_t card_width2 : 1; /* ALT_SDMMC_CTYPE_CARD_WIDTH2 */
1528  uint32_t : 15; /* *UNDEFINED* */
1529  uint32_t card_width1 : 1; /* ALT_SDMMC_CTYPE_CARD_WIDTH1 */
1530  uint32_t : 15; /* *UNDEFINED* */
1531 };
1532 
1533 /* The typedef declaration for register ALT_SDMMC_CTYPE. */
1534 typedef volatile struct ALT_SDMMC_CTYPE_s ALT_SDMMC_CTYPE_t;
1535 #endif /* __ASSEMBLY__ */
1536 
1537 /* The reset value of the ALT_SDMMC_CTYPE register. */
1538 #define ALT_SDMMC_CTYPE_RESET 0x00000000
1539 /* The byte offset of the ALT_SDMMC_CTYPE register from the beginning of the component. */
1540 #define ALT_SDMMC_CTYPE_OFST 0x18
1541 
1542 /*
1543  * Register : blksiz
1544  *
1545  * Block Size Register
1546  *
1547  * Register Layout
1548  *
1549  * Bits | Access | Reset | Description
1550  * :--------|:-------|:------|:----------------------------
1551  * [15:0] | RW | 0x200 | ALT_SDMMC_BLKSIZ_BLOCK_SIZE
1552  * [31:16] | ??? | 0x0 | *UNDEFINED*
1553  *
1554  */
1555 /*
1556  * Field : block_size
1557  *
1558  * Block size
1559  *
1560  * Field Access Macros:
1561  *
1562  */
1563 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */
1564 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_LSB 0
1565 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */
1566 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_MSB 15
1567 /* The width in bits of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */
1568 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_WIDTH 16
1569 /* The mask used to set the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field value. */
1570 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET_MSK 0x0000ffff
1571 /* The mask used to clear the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field value. */
1572 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_CLR_MSK 0xffff0000
1573 /* The reset value of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */
1574 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_RESET 0x200
1575 /* Extracts the ALT_SDMMC_BLKSIZ_BLOCK_SIZE field value from a register. */
1576 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_GET(value) (((value) & 0x0000ffff) >> 0)
1577 /* Produces a ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field value suitable for setting the register. */
1578 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET(value) (((value) << 0) & 0x0000ffff)
1579 
1580 #ifndef __ASSEMBLY__
1581 /*
1582  * WARNING: The C register and register group struct declarations are provided for
1583  * convenience and illustrative purposes. They should, however, be used with
1584  * caution as the C language standard provides no guarantees about the alignment or
1585  * atomicity of device memory accesses. The recommended practice for writing
1586  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1587  * alt_write_word() functions.
1588  *
1589  * The struct declaration for register ALT_SDMMC_BLKSIZ.
1590  */
1591 struct ALT_SDMMC_BLKSIZ_s
1592 {
1593  uint32_t block_size : 16; /* ALT_SDMMC_BLKSIZ_BLOCK_SIZE */
1594  uint32_t : 16; /* *UNDEFINED* */
1595 };
1596 
1597 /* The typedef declaration for register ALT_SDMMC_BLKSIZ. */
1598 typedef volatile struct ALT_SDMMC_BLKSIZ_s ALT_SDMMC_BLKSIZ_t;
1599 #endif /* __ASSEMBLY__ */
1600 
1601 /* The reset value of the ALT_SDMMC_BLKSIZ register. */
1602 #define ALT_SDMMC_BLKSIZ_RESET 0x00000200
1603 /* The byte offset of the ALT_SDMMC_BLKSIZ register from the beginning of the component. */
1604 #define ALT_SDMMC_BLKSIZ_OFST 0x1c
1605 
1606 /*
1607  * Register : bytcnt
1608  *
1609  * Byte Count Register
1610  *
1611  * Register Layout
1612  *
1613  * Bits | Access | Reset | Description
1614  * :-------|:-------|:------|:----------------------------
1615  * [31:0] | RW | 0x200 | ALT_SDMMC_BYTCNT_BYTE_COUNT
1616  *
1617  */
1618 /*
1619  * Field : byte_count
1620  *
1621  * Number of bytes to be transferred; should be integer multiple of Block Size for
1622  * block transfers.
1623  *
1624  * For undefined number of byte transfers, byte count should be set to 0. When byte
1625  * count is set to 0, it is responsibility of host to explicitly send stop/abort
1626  * command to terminate data transfer.
1627  *
1628  * Field Access Macros:
1629  *
1630  */
1631 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */
1632 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_LSB 0
1633 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */
1634 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_MSB 31
1635 /* The width in bits of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */
1636 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_WIDTH 32
1637 /* The mask used to set the ALT_SDMMC_BYTCNT_BYTE_COUNT register field value. */
1638 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET_MSK 0xffffffff
1639 /* The mask used to clear the ALT_SDMMC_BYTCNT_BYTE_COUNT register field value. */
1640 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_CLR_MSK 0x00000000
1641 /* The reset value of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */
1642 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_RESET 0x200
1643 /* Extracts the ALT_SDMMC_BYTCNT_BYTE_COUNT field value from a register. */
1644 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
1645 /* Produces a ALT_SDMMC_BYTCNT_BYTE_COUNT register field value suitable for setting the register. */
1646 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
1647 
1648 #ifndef __ASSEMBLY__
1649 /*
1650  * WARNING: The C register and register group struct declarations are provided for
1651  * convenience and illustrative purposes. They should, however, be used with
1652  * caution as the C language standard provides no guarantees about the alignment or
1653  * atomicity of device memory accesses. The recommended practice for writing
1654  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1655  * alt_write_word() functions.
1656  *
1657  * The struct declaration for register ALT_SDMMC_BYTCNT.
1658  */
1659 struct ALT_SDMMC_BYTCNT_s
1660 {
1661  uint32_t byte_count : 32; /* ALT_SDMMC_BYTCNT_BYTE_COUNT */
1662 };
1663 
1664 /* The typedef declaration for register ALT_SDMMC_BYTCNT. */
1665 typedef volatile struct ALT_SDMMC_BYTCNT_s ALT_SDMMC_BYTCNT_t;
1666 #endif /* __ASSEMBLY__ */
1667 
1668 /* The reset value of the ALT_SDMMC_BYTCNT register. */
1669 #define ALT_SDMMC_BYTCNT_RESET 0x00000200
1670 /* The byte offset of the ALT_SDMMC_BYTCNT register from the beginning of the component. */
1671 #define ALT_SDMMC_BYTCNT_OFST 0x20
1672 
1673 /*
1674  * Register : intmask
1675  *
1676  * Interrupt Mask Register
1677  *
1678  * Register Layout
1679  *
1680  * Bits | Access | Reset | Description
1681  * :--------|:-------|:------|:--------------------------------
1682  * [0] | RW | 0x0 | Interrupt Mask
1683  * [1] | RW | 0x0 | Interrupt Mask
1684  * [2] | RW | 0x0 | Command Done
1685  * [3] | RW | 0x0 | Data Transfer Over
1686  * [4] | RW | 0x0 | Transmit FIFO Data Request
1687  * [5] | RW | 0x0 | Receive FIFO Data Request (
1688  * [6] | RW | 0x0 | Response CRC Error
1689  * [7] | RW | 0x0 | Data CRC Error
1690  * [8] | RW | 0x0 | Response Timeout
1691  * [9] | RW | 0x0 | Data Read Timeout
1692  * [10] | RW | 0x0 | Data Starvation Host Timeout
1693  * [11] | RW | 0x0 | FIFO Underrun Overrun Error
1694  * [12] | RW | 0x0 | Hardware Locked Write Error
1695  * [13] | RW | 0x0 | Start-bit Error
1696  * [14] | RW | 0x0 | Auto Command Done
1697  * [15] | RW | 0x0 | End-bit Error Read Write no CRC
1698  * [31:16] | RW | 0x0 | ALT_SDMMC_INTMSK_SDIO_INT_MSK
1699  *
1700  */
1701 /*
1702  * Field : Interrupt Mask - cd
1703  *
1704  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1705  * enables interrupt.
1706  *
1707  * Field Enumeration Values:
1708  *
1709  * Enum | Value | Description
1710  * :----------------------------|:------|:--------------------
1711  * ALT_SDMMC_INTMSK_CD_E_MSK | 0x0 | Card Detected Mask
1712  * ALT_SDMMC_INTMSK_CD_E_NOMSK | 0x1 | Card Detect No Mask
1713  *
1714  * Field Access Macros:
1715  *
1716  */
1717 /*
1718  * Enumerated value for register field ALT_SDMMC_INTMSK_CD
1719  *
1720  * Card Detected Mask
1721  */
1722 #define ALT_SDMMC_INTMSK_CD_E_MSK 0x0
1723 /*
1724  * Enumerated value for register field ALT_SDMMC_INTMSK_CD
1725  *
1726  * Card Detect No Mask
1727  */
1728 #define ALT_SDMMC_INTMSK_CD_E_NOMSK 0x1
1729 
1730 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_CD register field. */
1731 #define ALT_SDMMC_INTMSK_CD_LSB 0
1732 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_CD register field. */
1733 #define ALT_SDMMC_INTMSK_CD_MSB 0
1734 /* The width in bits of the ALT_SDMMC_INTMSK_CD register field. */
1735 #define ALT_SDMMC_INTMSK_CD_WIDTH 1
1736 /* The mask used to set the ALT_SDMMC_INTMSK_CD register field value. */
1737 #define ALT_SDMMC_INTMSK_CD_SET_MSK 0x00000001
1738 /* The mask used to clear the ALT_SDMMC_INTMSK_CD register field value. */
1739 #define ALT_SDMMC_INTMSK_CD_CLR_MSK 0xfffffffe
1740 /* The reset value of the ALT_SDMMC_INTMSK_CD register field. */
1741 #define ALT_SDMMC_INTMSK_CD_RESET 0x0
1742 /* Extracts the ALT_SDMMC_INTMSK_CD field value from a register. */
1743 #define ALT_SDMMC_INTMSK_CD_GET(value) (((value) & 0x00000001) >> 0)
1744 /* Produces a ALT_SDMMC_INTMSK_CD register field value suitable for setting the register. */
1745 #define ALT_SDMMC_INTMSK_CD_SET(value) (((value) << 0) & 0x00000001)
1746 
1747 /*
1748  * Field : Interrupt Mask - re
1749  *
1750  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1751  * enables interrupt.
1752  *
1753  * Field Enumeration Values:
1754  *
1755  * Enum | Value | Description
1756  * :----------------------------|:------|:-----------------------
1757  * ALT_SDMMC_INTMSK_RE_E_MSK | 0x0 | Response error Mask
1758  * ALT_SDMMC_INTMSK_RE_E_NOMSK | 0x1 | Response error No Mask
1759  *
1760  * Field Access Macros:
1761  *
1762  */
1763 /*
1764  * Enumerated value for register field ALT_SDMMC_INTMSK_RE
1765  *
1766  * Response error Mask
1767  */
1768 #define ALT_SDMMC_INTMSK_RE_E_MSK 0x0
1769 /*
1770  * Enumerated value for register field ALT_SDMMC_INTMSK_RE
1771  *
1772  * Response error No Mask
1773  */
1774 #define ALT_SDMMC_INTMSK_RE_E_NOMSK 0x1
1775 
1776 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RE register field. */
1777 #define ALT_SDMMC_INTMSK_RE_LSB 1
1778 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RE register field. */
1779 #define ALT_SDMMC_INTMSK_RE_MSB 1
1780 /* The width in bits of the ALT_SDMMC_INTMSK_RE register field. */
1781 #define ALT_SDMMC_INTMSK_RE_WIDTH 1
1782 /* The mask used to set the ALT_SDMMC_INTMSK_RE register field value. */
1783 #define ALT_SDMMC_INTMSK_RE_SET_MSK 0x00000002
1784 /* The mask used to clear the ALT_SDMMC_INTMSK_RE register field value. */
1785 #define ALT_SDMMC_INTMSK_RE_CLR_MSK 0xfffffffd
1786 /* The reset value of the ALT_SDMMC_INTMSK_RE register field. */
1787 #define ALT_SDMMC_INTMSK_RE_RESET 0x0
1788 /* Extracts the ALT_SDMMC_INTMSK_RE field value from a register. */
1789 #define ALT_SDMMC_INTMSK_RE_GET(value) (((value) & 0x00000002) >> 1)
1790 /* Produces a ALT_SDMMC_INTMSK_RE register field value suitable for setting the register. */
1791 #define ALT_SDMMC_INTMSK_RE_SET(value) (((value) << 1) & 0x00000002)
1792 
1793 /*
1794  * Field : Command Done - cmd
1795  *
1796  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1797  * enables interrupt.
1798  *
1799  * Field Enumeration Values:
1800  *
1801  * Enum | Value | Description
1802  * :-----------------------------|:------|:---------------------
1803  * ALT_SDMMC_INTMSK_CMD_E_MSK | 0x0 | Command Done Mask
1804  * ALT_SDMMC_INTMSK_CMD_E_NOMSK | 0x1 | Command Done No Mask
1805  *
1806  * Field Access Macros:
1807  *
1808  */
1809 /*
1810  * Enumerated value for register field ALT_SDMMC_INTMSK_CMD
1811  *
1812  * Command Done Mask
1813  */
1814 #define ALT_SDMMC_INTMSK_CMD_E_MSK 0x0
1815 /*
1816  * Enumerated value for register field ALT_SDMMC_INTMSK_CMD
1817  *
1818  * Command Done No Mask
1819  */
1820 #define ALT_SDMMC_INTMSK_CMD_E_NOMSK 0x1
1821 
1822 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_CMD register field. */
1823 #define ALT_SDMMC_INTMSK_CMD_LSB 2
1824 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_CMD register field. */
1825 #define ALT_SDMMC_INTMSK_CMD_MSB 2
1826 /* The width in bits of the ALT_SDMMC_INTMSK_CMD register field. */
1827 #define ALT_SDMMC_INTMSK_CMD_WIDTH 1
1828 /* The mask used to set the ALT_SDMMC_INTMSK_CMD register field value. */
1829 #define ALT_SDMMC_INTMSK_CMD_SET_MSK 0x00000004
1830 /* The mask used to clear the ALT_SDMMC_INTMSK_CMD register field value. */
1831 #define ALT_SDMMC_INTMSK_CMD_CLR_MSK 0xfffffffb
1832 /* The reset value of the ALT_SDMMC_INTMSK_CMD register field. */
1833 #define ALT_SDMMC_INTMSK_CMD_RESET 0x0
1834 /* Extracts the ALT_SDMMC_INTMSK_CMD field value from a register. */
1835 #define ALT_SDMMC_INTMSK_CMD_GET(value) (((value) & 0x00000004) >> 2)
1836 /* Produces a ALT_SDMMC_INTMSK_CMD register field value suitable for setting the register. */
1837 #define ALT_SDMMC_INTMSK_CMD_SET(value) (((value) << 2) & 0x00000004)
1838 
1839 /*
1840  * Field : Data Transfer Over - dto
1841  *
1842  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1843  * enables interrupt.
1844  *
1845  * Field Enumeration Values:
1846  *
1847  * Enum | Value | Description
1848  * :-----------------------------|:------|:---------------------------
1849  * ALT_SDMMC_INTMSK_DTO_E_MSK | 0x0 | Data transfer over Mask
1850  * ALT_SDMMC_INTMSK_DTO_E_NOMSK | 0x1 | Data transfer over No Mask
1851  *
1852  * Field Access Macros:
1853  *
1854  */
1855 /*
1856  * Enumerated value for register field ALT_SDMMC_INTMSK_DTO
1857  *
1858  * Data transfer over Mask
1859  */
1860 #define ALT_SDMMC_INTMSK_DTO_E_MSK 0x0
1861 /*
1862  * Enumerated value for register field ALT_SDMMC_INTMSK_DTO
1863  *
1864  * Data transfer over No Mask
1865  */
1866 #define ALT_SDMMC_INTMSK_DTO_E_NOMSK 0x1
1867 
1868 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_DTO register field. */
1869 #define ALT_SDMMC_INTMSK_DTO_LSB 3
1870 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_DTO register field. */
1871 #define ALT_SDMMC_INTMSK_DTO_MSB 3
1872 /* The width in bits of the ALT_SDMMC_INTMSK_DTO register field. */
1873 #define ALT_SDMMC_INTMSK_DTO_WIDTH 1
1874 /* The mask used to set the ALT_SDMMC_INTMSK_DTO register field value. */
1875 #define ALT_SDMMC_INTMSK_DTO_SET_MSK 0x00000008
1876 /* The mask used to clear the ALT_SDMMC_INTMSK_DTO register field value. */
1877 #define ALT_SDMMC_INTMSK_DTO_CLR_MSK 0xfffffff7
1878 /* The reset value of the ALT_SDMMC_INTMSK_DTO register field. */
1879 #define ALT_SDMMC_INTMSK_DTO_RESET 0x0
1880 /* Extracts the ALT_SDMMC_INTMSK_DTO field value from a register. */
1881 #define ALT_SDMMC_INTMSK_DTO_GET(value) (((value) & 0x00000008) >> 3)
1882 /* Produces a ALT_SDMMC_INTMSK_DTO register field value suitable for setting the register. */
1883 #define ALT_SDMMC_INTMSK_DTO_SET(value) (((value) << 3) & 0x00000008)
1884 
1885 /*
1886  * Field : Transmit FIFO Data Request - txdr
1887  *
1888  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1889  * enables interrupt.
1890  *
1891  * Field Enumeration Values:
1892  *
1893  * Enum | Value | Description
1894  * :------------------------------|:------|:-----------------------------------
1895  * ALT_SDMMC_INTMSK_TXDR_E_MSK | 0x0 | Transmit FIFO data request Mask
1896  * ALT_SDMMC_INTMSK_TXDR_E_NOMSK | 0x1 | Transmit FIFO data request No Mask
1897  *
1898  * Field Access Macros:
1899  *
1900  */
1901 /*
1902  * Enumerated value for register field ALT_SDMMC_INTMSK_TXDR
1903  *
1904  * Transmit FIFO data request Mask
1905  */
1906 #define ALT_SDMMC_INTMSK_TXDR_E_MSK 0x0
1907 /*
1908  * Enumerated value for register field ALT_SDMMC_INTMSK_TXDR
1909  *
1910  * Transmit FIFO data request No Mask
1911  */
1912 #define ALT_SDMMC_INTMSK_TXDR_E_NOMSK 0x1
1913 
1914 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_TXDR register field. */
1915 #define ALT_SDMMC_INTMSK_TXDR_LSB 4
1916 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_TXDR register field. */
1917 #define ALT_SDMMC_INTMSK_TXDR_MSB 4
1918 /* The width in bits of the ALT_SDMMC_INTMSK_TXDR register field. */
1919 #define ALT_SDMMC_INTMSK_TXDR_WIDTH 1
1920 /* The mask used to set the ALT_SDMMC_INTMSK_TXDR register field value. */
1921 #define ALT_SDMMC_INTMSK_TXDR_SET_MSK 0x00000010
1922 /* The mask used to clear the ALT_SDMMC_INTMSK_TXDR register field value. */
1923 #define ALT_SDMMC_INTMSK_TXDR_CLR_MSK 0xffffffef
1924 /* The reset value of the ALT_SDMMC_INTMSK_TXDR register field. */
1925 #define ALT_SDMMC_INTMSK_TXDR_RESET 0x0
1926 /* Extracts the ALT_SDMMC_INTMSK_TXDR field value from a register. */
1927 #define ALT_SDMMC_INTMSK_TXDR_GET(value) (((value) & 0x00000010) >> 4)
1928 /* Produces a ALT_SDMMC_INTMSK_TXDR register field value suitable for setting the register. */
1929 #define ALT_SDMMC_INTMSK_TXDR_SET(value) (((value) << 4) & 0x00000010)
1930 
1931 /*
1932  * Field : Receive FIFO Data Request ( - rxdr
1933  *
1934  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1935  * enables interrupt.
1936  *
1937  * Field Enumeration Values:
1938  *
1939  * Enum | Value | Description
1940  * :------------------------------|:------|:----------------------------------
1941  * ALT_SDMMC_INTMSK_RXDR_E_MSK | 0x0 | Receive FIFO data request Mask
1942  * ALT_SDMMC_INTMSK_RXDR_E_NOMSK | 0x1 | Receive FIFO data request No Mask
1943  *
1944  * Field Access Macros:
1945  *
1946  */
1947 /*
1948  * Enumerated value for register field ALT_SDMMC_INTMSK_RXDR
1949  *
1950  * Receive FIFO data request Mask
1951  */
1952 #define ALT_SDMMC_INTMSK_RXDR_E_MSK 0x0
1953 /*
1954  * Enumerated value for register field ALT_SDMMC_INTMSK_RXDR
1955  *
1956  * Receive FIFO data request No Mask
1957  */
1958 #define ALT_SDMMC_INTMSK_RXDR_E_NOMSK 0x1
1959 
1960 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RXDR register field. */
1961 #define ALT_SDMMC_INTMSK_RXDR_LSB 5
1962 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RXDR register field. */
1963 #define ALT_SDMMC_INTMSK_RXDR_MSB 5
1964 /* The width in bits of the ALT_SDMMC_INTMSK_RXDR register field. */
1965 #define ALT_SDMMC_INTMSK_RXDR_WIDTH 1
1966 /* The mask used to set the ALT_SDMMC_INTMSK_RXDR register field value. */
1967 #define ALT_SDMMC_INTMSK_RXDR_SET_MSK 0x00000020
1968 /* The mask used to clear the ALT_SDMMC_INTMSK_RXDR register field value. */
1969 #define ALT_SDMMC_INTMSK_RXDR_CLR_MSK 0xffffffdf
1970 /* The reset value of the ALT_SDMMC_INTMSK_RXDR register field. */
1971 #define ALT_SDMMC_INTMSK_RXDR_RESET 0x0
1972 /* Extracts the ALT_SDMMC_INTMSK_RXDR field value from a register. */
1973 #define ALT_SDMMC_INTMSK_RXDR_GET(value) (((value) & 0x00000020) >> 5)
1974 /* Produces a ALT_SDMMC_INTMSK_RXDR register field value suitable for setting the register. */
1975 #define ALT_SDMMC_INTMSK_RXDR_SET(value) (((value) << 5) & 0x00000020)
1976 
1977 /*
1978  * Field : Response CRC Error - rcrc
1979  *
1980  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1981  * enables interrupt.
1982  *
1983  * Field Enumeration Values:
1984  *
1985  * Enum | Value | Description
1986  * :------------------------------|:------|:---------------------------
1987  * ALT_SDMMC_INTMSK_RCRC_E_MSK | 0x0 | Response CRC error Mask
1988  * ALT_SDMMC_INTMSK_RCRC_E_NOMSK | 0x1 | Response CRC error No Mask
1989  *
1990  * Field Access Macros:
1991  *
1992  */
1993 /*
1994  * Enumerated value for register field ALT_SDMMC_INTMSK_RCRC
1995  *
1996  * Response CRC error Mask
1997  */
1998 #define ALT_SDMMC_INTMSK_RCRC_E_MSK 0x0
1999 /*
2000  * Enumerated value for register field ALT_SDMMC_INTMSK_RCRC
2001  *
2002  * Response CRC error No Mask
2003  */
2004 #define ALT_SDMMC_INTMSK_RCRC_E_NOMSK 0x1
2005 
2006 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RCRC register field. */
2007 #define ALT_SDMMC_INTMSK_RCRC_LSB 6
2008 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RCRC register field. */
2009 #define ALT_SDMMC_INTMSK_RCRC_MSB 6
2010 /* The width in bits of the ALT_SDMMC_INTMSK_RCRC register field. */
2011 #define ALT_SDMMC_INTMSK_RCRC_WIDTH 1
2012 /* The mask used to set the ALT_SDMMC_INTMSK_RCRC register field value. */
2013 #define ALT_SDMMC_INTMSK_RCRC_SET_MSK 0x00000040
2014 /* The mask used to clear the ALT_SDMMC_INTMSK_RCRC register field value. */
2015 #define ALT_SDMMC_INTMSK_RCRC_CLR_MSK 0xffffffbf
2016 /* The reset value of the ALT_SDMMC_INTMSK_RCRC register field. */
2017 #define ALT_SDMMC_INTMSK_RCRC_RESET 0x0
2018 /* Extracts the ALT_SDMMC_INTMSK_RCRC field value from a register. */
2019 #define ALT_SDMMC_INTMSK_RCRC_GET(value) (((value) & 0x00000040) >> 6)
2020 /* Produces a ALT_SDMMC_INTMSK_RCRC register field value suitable for setting the register. */
2021 #define ALT_SDMMC_INTMSK_RCRC_SET(value) (((value) << 6) & 0x00000040)
2022 
2023 /*
2024  * Field : Data CRC Error - dcrc
2025  *
2026  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
2027  * enables interrupt.
2028  *
2029  * Field Enumeration Values:
2030  *
2031  * Enum | Value | Description
2032  * :------------------------------|:------|:-----------------------
2033  * ALT_SDMMC_INTMSK_DCRC_E_MSK | 0x0 | Data CRC error Mask
2034  * ALT_SDMMC_INTMSK_DCRC_E_NOMSK | 0x1 | Data CRC error No Mask
2035  *
2036  * Field Access Macros:
2037  *
2038  */
2039 /*
2040  * Enumerated value for register field ALT_SDMMC_INTMSK_DCRC
2041  *
2042  * Data CRC error Mask
2043  */
2044 #define ALT_SDMMC_INTMSK_DCRC_E_MSK 0x0
2045 /*
2046  * Enumerated value for register field ALT_SDMMC_INTMSK_DCRC
2047  *
2048  * Data CRC error No Mask
2049  */
2050 #define ALT_SDMMC_INTMSK_DCRC_E_NOMSK 0x1
2051 
2052 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_DCRC register field. */
2053 #define ALT_SDMMC_INTMSK_DCRC_LSB 7
2054 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_DCRC register field. */
2055 #define ALT_SDMMC_INTMSK_DCRC_MSB 7
2056 /* The width in bits of the ALT_SDMMC_INTMSK_DCRC register field. */
2057 #define ALT_SDMMC_INTMSK_DCRC_WIDTH 1
2058 /* The mask used to set the ALT_SDMMC_INTMSK_DCRC register field value. */
2059 #define ALT_SDMMC_INTMSK_DCRC_SET_MSK 0x00000080
2060 /* The mask used to clear the ALT_SDMMC_INTMSK_DCRC register field value. */
2061 #define ALT_SDMMC_INTMSK_DCRC_CLR_MSK 0xffffff7f
2062 /* The reset value of the ALT_SDMMC_INTMSK_DCRC register field. */
2063 #define ALT_SDMMC_INTMSK_DCRC_RESET 0x0
2064 /* Extracts the ALT_SDMMC_INTMSK_DCRC field value from a register. */
2065 #define ALT_SDMMC_INTMSK_DCRC_GET(value) (((value) & 0x00000080) >> 7)
2066 /* Produces a ALT_SDMMC_INTMSK_DCRC register field value suitable for setting the register. */
2067 #define ALT_SDMMC_INTMSK_DCRC_SET(value) (((value) << 7) & 0x00000080)
2068 
2069 /*
2070  * Field : Response Timeout - rto
2071  *
2072  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
2073  * enables interrupt.
2074  *
2075  * Field Enumeration Values:
2076  *
2077  * Enum | Value | Description
2078  * :-----------------------------|:------|:-------------------------
2079  * ALT_SDMMC_INTMSK_RTO_E_MSK | 0x0 | Response timeout Mask
2080  * ALT_SDMMC_INTMSK_RTO_E_NOMSK | 0x1 | Response timeout No Mask
2081  *
2082  * Field Access Macros:
2083  *
2084  */
2085 /*
2086  * Enumerated value for register field ALT_SDMMC_INTMSK_RTO
2087  *
2088  * Response timeout Mask
2089  */
2090 #define ALT_SDMMC_INTMSK_RTO_E_MSK 0x0
2091 /*
2092  * Enumerated value for register field ALT_SDMMC_INTMSK_RTO
2093  *
2094  * Response timeout No Mask
2095  */
2096 #define ALT_SDMMC_INTMSK_RTO_E_NOMSK 0x1
2097 
2098 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RTO register field. */
2099 #define ALT_SDMMC_INTMSK_RTO_LSB 8
2100 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RTO register field. */
2101 #define ALT_SDMMC_INTMSK_RTO_MSB 8
2102 /* The width in bits of the ALT_SDMMC_INTMSK_RTO register field. */
2103 #define ALT_SDMMC_INTMSK_RTO_WIDTH 1
2104 /* The mask used to set the ALT_SDMMC_INTMSK_RTO register field value. */
2105 #define ALT_SDMMC_INTMSK_RTO_SET_MSK 0x00000100
2106 /* The mask used to clear the ALT_SDMMC_INTMSK_RTO register field value. */
2107 #define ALT_SDMMC_INTMSK_RTO_CLR_MSK 0xfffffeff
2108 /* The reset value of the ALT_SDMMC_INTMSK_RTO register field. */
2109 #define ALT_SDMMC_INTMSK_RTO_RESET 0x0
2110 /* Extracts the ALT_SDMMC_INTMSK_RTO field value from a register. */
2111 #define ALT_SDMMC_INTMSK_RTO_GET(value) (((value) & 0x00000100) >> 8)
2112 /* Produces a ALT_SDMMC_INTMSK_RTO register field value suitable for setting the register. */
2113 #define ALT_SDMMC_INTMSK_RTO_SET(value) (((value) << 8) & 0x00000100)
2114 
2115 /*
2116  * Field : Data Read Timeout - drt
2117  *
2118  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
2119  * enables interrupt.
2120  *
2121  * Field Enumeration Values:
2122  *
2123  * Enum | Value | Description
2124  * :-----------------------------|:------|:--------------------------
2125  * ALT_SDMMC_INTMSK_DRT_E_MSK | 0x0 | Data read timeout Mask
2126  * ALT_SDMMC_INTMSK_DRT_E_NOMSK | 0x1 | Data read timeout No Mask
2127  *
2128  * Field Access Macros:
2129  *
2130  */
2131 /*
2132  * Enumerated value for register field ALT_SDMMC_INTMSK_DRT
2133  *
2134  * Data read timeout Mask
2135  */
2136 #define ALT_SDMMC_INTMSK_DRT_E_MSK 0x0
2137 /*
2138  * Enumerated value for register field ALT_SDMMC_INTMSK_DRT
2139  *
2140  * Data read timeout No Mask
2141  */
2142 #define ALT_SDMMC_INTMSK_DRT_E_NOMSK 0x1
2143 
2144 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_DRT register field. */
2145 #define ALT_SDMMC_INTMSK_DRT_LSB 9
2146 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_DRT register field. */
2147 #define ALT_SDMMC_INTMSK_DRT_MSB 9
2148 /* The width in bits of the ALT_SDMMC_INTMSK_DRT register field. */
2149 #define ALT_SDMMC_INTMSK_DRT_WIDTH 1
2150 /* The mask used to set the ALT_SDMMC_INTMSK_DRT register field value. */
2151 #define ALT_SDMMC_INTMSK_DRT_SET_MSK 0x00000200
2152 /* The mask used to clear the ALT_SDMMC_INTMSK_DRT register field value. */
2153 #define ALT_SDMMC_INTMSK_DRT_CLR_MSK 0xfffffdff
2154 /* The reset value of the ALT_SDMMC_INTMSK_DRT register field. */
2155 #define ALT_SDMMC_INTMSK_DRT_RESET 0x0
2156 /* Extracts the ALT_SDMMC_INTMSK_DRT field value from a register. */
2157 #define ALT_SDMMC_INTMSK_DRT_GET(value) (((value) & 0x00000200) >> 9)
2158 /* Produces a ALT_SDMMC_INTMSK_DRT register field value suitable for setting the register. */
2159 #define ALT_SDMMC_INTMSK_DRT_SET(value) (((value) << 9) & 0x00000200)
2160 
2161 /*
2162  * Field : Data Starvation Host Timeout - hto
2163  *
2164  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
2165  * enables interrupt.
2166  *
2167  * Field Enumeration Values:
2168  *
2169  * Enum | Value | Description
2170  * :-----------------------------|:------|:----------------------------------------
2171  * ALT_SDMMC_INTMSK_HTO_E_MSK | 0x0 | Data starvation by host timeout Mask
2172  * ALT_SDMMC_INTMSK_HTO_E_NOMSK | 0x1 | Data starvation by host timeout No Mask
2173  *
2174  * Field Access Macros:
2175  *
2176  */
2177 /*
2178  * Enumerated value for register field ALT_SDMMC_INTMSK_HTO
2179  *
2180  * Data starvation by host timeout Mask
2181  */
2182 #define ALT_SDMMC_INTMSK_HTO_E_MSK 0x0
2183 /*
2184  * Enumerated value for register field ALT_SDMMC_INTMSK_HTO
2185  *
2186  * Data starvation by host timeout No Mask
2187  */
2188 #define ALT_SDMMC_INTMSK_HTO_E_NOMSK 0x1
2189 
2190 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_HTO register field. */
2191 #define ALT_SDMMC_INTMSK_HTO_LSB 10
2192 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_HTO register field. */
2193 #define ALT_SDMMC_INTMSK_HTO_MSB 10
2194 /* The width in bits of the ALT_SDMMC_INTMSK_HTO register field. */
2195 #define ALT_SDMMC_INTMSK_HTO_WIDTH 1
2196 /* The mask used to set the ALT_SDMMC_INTMSK_HTO register field value. */
2197 #define ALT_SDMMC_INTMSK_HTO_SET_MSK 0x00000400
2198 /* The mask used to clear the ALT_SDMMC_INTMSK_HTO register field value. */
2199 #define ALT_SDMMC_INTMSK_HTO_CLR_MSK 0xfffffbff
2200 /* The reset value of the ALT_SDMMC_INTMSK_HTO register field. */
2201 #define ALT_SDMMC_INTMSK_HTO_RESET 0x0
2202 /* Extracts the ALT_SDMMC_INTMSK_HTO field value from a register. */
2203 #define ALT_SDMMC_INTMSK_HTO_GET(value) (((value) & 0x00000400) >> 10)
2204 /* Produces a ALT_SDMMC_INTMSK_HTO register field value suitable for setting the register. */
2205 #define ALT_SDMMC_INTMSK_HTO_SET(value) (((value) << 10) & 0x00000400)
2206 
2207 /*
2208  * Field : FIFO Underrun Overrun Error - frun
2209  *
2210  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
2211  * enables interrupt.
2212  *
2213  * Field Enumeration Values:
2214  *
2215  * Enum | Value | Description
2216  * :------------------------------|:------|:------------------------------------
2217  * ALT_SDMMC_INTMSK_FRUN_E_MSK | 0x0 | FIFO underrun/overrun error Mask
2218  * ALT_SDMMC_INTMSK_FRUN_E_NOMSK | 0x1 | FIFO underrun/overrun error No Mask
2219  *
2220  * Field Access Macros:
2221  *
2222  */
2223 /*
2224  * Enumerated value for register field ALT_SDMMC_INTMSK_FRUN
2225  *
2226  * FIFO underrun/overrun error Mask
2227  */
2228 #define ALT_SDMMC_INTMSK_FRUN_E_MSK 0x0
2229 /*
2230  * Enumerated value for register field ALT_SDMMC_INTMSK_FRUN
2231  *
2232  * FIFO underrun/overrun error No Mask
2233  */
2234 #define ALT_SDMMC_INTMSK_FRUN_E_NOMSK 0x1
2235 
2236 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_FRUN register field. */
2237 #define ALT_SDMMC_INTMSK_FRUN_LSB 11
2238 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_FRUN register field. */
2239 #define ALT_SDMMC_INTMSK_FRUN_MSB 11
2240 /* The width in bits of the ALT_SDMMC_INTMSK_FRUN register field. */
2241 #define ALT_SDMMC_INTMSK_FRUN_WIDTH 1
2242 /* The mask used to set the ALT_SDMMC_INTMSK_FRUN register field value. */
2243 #define ALT_SDMMC_INTMSK_FRUN_SET_MSK 0x00000800
2244 /* The mask used to clear the ALT_SDMMC_INTMSK_FRUN register field value. */
2245 #define ALT_SDMMC_INTMSK_FRUN_CLR_MSK 0xfffff7ff
2246 /* The reset value of the ALT_SDMMC_INTMSK_FRUN register field. */
2247 #define ALT_SDMMC_INTMSK_FRUN_RESET 0x0
2248 /* Extracts the ALT_SDMMC_INTMSK_FRUN field value from a register. */
2249 #define ALT_SDMMC_INTMSK_FRUN_GET(value) (((value) & 0x00000800) >> 11)
2250 /* Produces a ALT_SDMMC_INTMSK_FRUN register field value suitable for setting the register. */
2251 #define ALT_SDMMC_INTMSK_FRUN_SET(value) (((value) << 11) & 0x00000800)
2252 
2253 /*
2254  * Field : Hardware Locked Write Error - hle
2255  *
2256  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
2257  * enables interrupt.
2258  *
2259  * Field Enumeration Values:
2260  *
2261  * Enum | Value | Description
2262  * :-----------------------------|:------|:------------------------------------
2263  * ALT_SDMMC_INTMSK_HLE_E_MSK | 0x0 | Hardware locked write error Mask
2264  * ALT_SDMMC_INTMSK_HLE_E_NOMSK | 0x1 | Hardware locked write error No Mask
2265  *
2266  * Field Access Macros:
2267  *
2268  */
2269 /*
2270  * Enumerated value for register field ALT_SDMMC_INTMSK_HLE
2271  *
2272  * Hardware locked write error Mask
2273  */
2274 #define ALT_SDMMC_INTMSK_HLE_E_MSK 0x0
2275 /*
2276  * Enumerated value for register field ALT_SDMMC_INTMSK_HLE
2277  *
2278  * Hardware locked write error No Mask
2279  */
2280 #define ALT_SDMMC_INTMSK_HLE_E_NOMSK 0x1
2281 
2282 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_HLE register field. */
2283 #define ALT_SDMMC_INTMSK_HLE_LSB 12
2284 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_HLE register field. */
2285 #define ALT_SDMMC_INTMSK_HLE_MSB 12
2286 /* The width in bits of the ALT_SDMMC_INTMSK_HLE register field. */
2287 #define ALT_SDMMC_INTMSK_HLE_WIDTH 1
2288 /* The mask used to set the ALT_SDMMC_INTMSK_HLE register field value. */
2289 #define ALT_SDMMC_INTMSK_HLE_SET_MSK 0x00001000
2290 /* The mask used to clear the ALT_SDMMC_INTMSK_HLE register field value. */
2291 #define ALT_SDMMC_INTMSK_HLE_CLR_MSK 0xffffefff
2292 /* The reset value of the ALT_SDMMC_INTMSK_HLE register field. */
2293 #define ALT_SDMMC_INTMSK_HLE_RESET 0x0
2294 /* Extracts the ALT_SDMMC_INTMSK_HLE field value from a register. */
2295 #define ALT_SDMMC_INTMSK_HLE_GET(value) (((value) & 0x00001000) >> 12)
2296 /* Produces a ALT_SDMMC_INTMSK_HLE register field value suitable for setting the register. */
2297 #define ALT_SDMMC_INTMSK_HLE_SET(value) (((value) << 12) & 0x00001000)
2298 
2299 /*
2300  * Field : Start-bit Error - sbe
2301  *
2302  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
2303  * enables interrupt.
2304  *
2305  * Field Enumeration Values:
2306  *
2307  * Enum | Value | Description
2308  * :-----------------------------|:------|:------------------------
2309  * ALT_SDMMC_INTMSK_SBE_E_MSK | 0x0 | Start-bit error Mask
2310  * ALT_SDMMC_INTMSK_SBE_E_NOMSK | 0x1 | Start-bit error No Mask
2311  *
2312  * Field Access Macros:
2313  *
2314  */
2315 /*
2316  * Enumerated value for register field ALT_SDMMC_INTMSK_SBE
2317  *
2318  * Start-bit error Mask
2319  */
2320 #define ALT_SDMMC_INTMSK_SBE_E_MSK 0x0
2321 /*
2322  * Enumerated value for register field ALT_SDMMC_INTMSK_SBE
2323  *
2324  * Start-bit error No Mask
2325  */
2326 #define ALT_SDMMC_INTMSK_SBE_E_NOMSK 0x1
2327 
2328 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_SBE register field. */
2329 #define ALT_SDMMC_INTMSK_SBE_LSB 13
2330 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_SBE register field. */
2331 #define ALT_SDMMC_INTMSK_SBE_MSB 13
2332 /* The width in bits of the ALT_SDMMC_INTMSK_SBE register field. */
2333 #define ALT_SDMMC_INTMSK_SBE_WIDTH 1
2334 /* The mask used to set the ALT_SDMMC_INTMSK_SBE register field value. */
2335 #define ALT_SDMMC_INTMSK_SBE_SET_MSK 0x00002000
2336 /* The mask used to clear the ALT_SDMMC_INTMSK_SBE register field value. */
2337 #define ALT_SDMMC_INTMSK_SBE_CLR_MSK 0xffffdfff
2338 /* The reset value of the ALT_SDMMC_INTMSK_SBE register field. */
2339 #define ALT_SDMMC_INTMSK_SBE_RESET 0x0
2340 /* Extracts the ALT_SDMMC_INTMSK_SBE field value from a register. */
2341 #define ALT_SDMMC_INTMSK_SBE_GET(value) (((value) & 0x00002000) >> 13)
2342 /* Produces a ALT_SDMMC_INTMSK_SBE register field value suitable for setting the register. */
2343 #define ALT_SDMMC_INTMSK_SBE_SET(value) (((value) << 13) & 0x00002000)
2344 
2345 /*
2346  * Field : Auto Command Done - acd
2347  *
2348  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
2349  * enables interrupt.
2350  *
2351  * Field Enumeration Values:
2352  *
2353  * Enum | Value | Description
2354  * :-----------------------------|:------|:--------------------------
2355  * ALT_SDMMC_INTMSK_ACD_E_MSK | 0x0 | Auto command done Mask
2356  * ALT_SDMMC_INTMSK_ACD_E_NOMSK | 0x1 | Auto command done No Mask
2357  *
2358  * Field Access Macros:
2359  *
2360  */
2361 /*
2362  * Enumerated value for register field ALT_SDMMC_INTMSK_ACD
2363  *
2364  * Auto command done Mask
2365  */
2366 #define ALT_SDMMC_INTMSK_ACD_E_MSK 0x0
2367 /*
2368  * Enumerated value for register field ALT_SDMMC_INTMSK_ACD
2369  *
2370  * Auto command done No Mask
2371  */
2372 #define ALT_SDMMC_INTMSK_ACD_E_NOMSK 0x1
2373 
2374 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_ACD register field. */
2375 #define ALT_SDMMC_INTMSK_ACD_LSB 14
2376 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_ACD register field. */
2377 #define ALT_SDMMC_INTMSK_ACD_MSB 14
2378 /* The width in bits of the ALT_SDMMC_INTMSK_ACD register field. */
2379 #define ALT_SDMMC_INTMSK_ACD_WIDTH 1
2380 /* The mask used to set the ALT_SDMMC_INTMSK_ACD register field value. */
2381 #define ALT_SDMMC_INTMSK_ACD_SET_MSK 0x00004000
2382 /* The mask used to clear the ALT_SDMMC_INTMSK_ACD register field value. */
2383 #define ALT_SDMMC_INTMSK_ACD_CLR_MSK 0xffffbfff
2384 /* The reset value of the ALT_SDMMC_INTMSK_ACD register field. */
2385 #define ALT_SDMMC_INTMSK_ACD_RESET 0x0
2386 /* Extracts the ALT_SDMMC_INTMSK_ACD field value from a register. */
2387 #define ALT_SDMMC_INTMSK_ACD_GET(value) (((value) & 0x00004000) >> 14)
2388 /* Produces a ALT_SDMMC_INTMSK_ACD register field value suitable for setting the register. */
2389 #define ALT_SDMMC_INTMSK_ACD_SET(value) (((value) << 14) & 0x00004000)
2390 
2391 /*
2392  * Field : End-bit Error Read Write no CRC - ebe
2393  *
2394  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
2395  * enables interrupt.
2396  *
2397  * Field Enumeration Values:
2398  *
2399  * Enum | Value | Description
2400  * :-----------------------------|:------|:----------------------
2401  * ALT_SDMMC_INTMSK_EBE_E_MSK | 0x0 | End-bit error Mask
2402  * ALT_SDMMC_INTMSK_EBE_E_NOMSK | 0x1 | End-bit error No Mask
2403  *
2404  * Field Access Macros:
2405  *
2406  */
2407 /*
2408  * Enumerated value for register field ALT_SDMMC_INTMSK_EBE
2409  *
2410  * End-bit error Mask
2411  */
2412 #define ALT_SDMMC_INTMSK_EBE_E_MSK 0x0
2413 /*
2414  * Enumerated value for register field ALT_SDMMC_INTMSK_EBE
2415  *
2416  * End-bit error No Mask
2417  */
2418 #define ALT_SDMMC_INTMSK_EBE_E_NOMSK 0x1
2419 
2420 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_EBE register field. */
2421 #define ALT_SDMMC_INTMSK_EBE_LSB 15
2422 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_EBE register field. */
2423 #define ALT_SDMMC_INTMSK_EBE_MSB 15
2424 /* The width in bits of the ALT_SDMMC_INTMSK_EBE register field. */
2425 #define ALT_SDMMC_INTMSK_EBE_WIDTH 1
2426 /* The mask used to set the ALT_SDMMC_INTMSK_EBE register field value. */
2427 #define ALT_SDMMC_INTMSK_EBE_SET_MSK 0x00008000
2428 /* The mask used to clear the ALT_SDMMC_INTMSK_EBE register field value. */
2429 #define ALT_SDMMC_INTMSK_EBE_CLR_MSK 0xffff7fff
2430 /* The reset value of the ALT_SDMMC_INTMSK_EBE register field. */
2431 #define ALT_SDMMC_INTMSK_EBE_RESET 0x0
2432 /* Extracts the ALT_SDMMC_INTMSK_EBE field value from a register. */
2433 #define ALT_SDMMC_INTMSK_EBE_GET(value) (((value) & 0x00008000) >> 15)
2434 /* Produces a ALT_SDMMC_INTMSK_EBE register field value suitable for setting the register. */
2435 #define ALT_SDMMC_INTMSK_EBE_SET(value) (((value) << 15) & 0x00008000)
2436 
2437 /*
2438  * Field : sdio_int_mask
2439  *
2440  * Mask SDIO interrupts
2441  *
2442  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
2443  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
2444  * masks an interrupt, and 1 enables an interrupt.
2445  *
2446  * In MMC-Ver3.3-only mode, these bits are always 0.
2447  *
2448  * Field Enumeration Values:
2449  *
2450  * Enum | Value | Description
2451  * :-------------------------------------|:------|:-----------------------------
2452  * ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_DISD | 0x0 | SDIO Mask Interrupt Disabled
2453  * ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_END | 0x1 | SDIO Interrupt Enabled
2454  *
2455  * Field Access Macros:
2456  *
2457  */
2458 /*
2459  * Enumerated value for register field ALT_SDMMC_INTMSK_SDIO_INT_MSK
2460  *
2461  * SDIO Mask Interrupt Disabled
2462  */
2463 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_DISD 0x0
2464 /*
2465  * Enumerated value for register field ALT_SDMMC_INTMSK_SDIO_INT_MSK
2466  *
2467  * SDIO Interrupt Enabled
2468  */
2469 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_END 0x1
2470 
2471 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field. */
2472 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_LSB 16
2473 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field. */
2474 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_MSB 31
2475 /* The width in bits of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field. */
2476 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_WIDTH 16
2477 /* The mask used to set the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field value. */
2478 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET_MSK 0xffff0000
2479 /* The mask used to clear the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field value. */
2480 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_CLR_MSK 0x0000ffff
2481 /* The reset value of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field. */
2482 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_RESET 0x0
2483 /* Extracts the ALT_SDMMC_INTMSK_SDIO_INT_MSK field value from a register. */
2484 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_GET(value) (((value) & 0xffff0000) >> 16)
2485 /* Produces a ALT_SDMMC_INTMSK_SDIO_INT_MSK register field value suitable for setting the register. */
2486 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET(value) (((value) << 16) & 0xffff0000)
2487 
2488 #ifndef __ASSEMBLY__
2489 /*
2490  * WARNING: The C register and register group struct declarations are provided for
2491  * convenience and illustrative purposes. They should, however, be used with
2492  * caution as the C language standard provides no guarantees about the alignment or
2493  * atomicity of device memory accesses. The recommended practice for writing
2494  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2495  * alt_write_word() functions.
2496  *
2497  * The struct declaration for register ALT_SDMMC_INTMSK.
2498  */
2499 struct ALT_SDMMC_INTMSK_s
2500 {
2501  uint32_t cd : 1; /* Interrupt Mask */
2502  uint32_t re : 1; /* Interrupt Mask */
2503  uint32_t cmd : 1; /* Command Done */
2504  uint32_t dto : 1; /* Data Transfer Over */
2505  uint32_t txdr : 1; /* Transmit FIFO Data Request */
2506  uint32_t rxdr : 1; /* Receive FIFO Data Request ( */
2507  uint32_t rcrc : 1; /* Response CRC Error */
2508  uint32_t dcrc : 1; /* Data CRC Error */
2509  uint32_t rto : 1; /* Response Timeout */
2510  uint32_t drt : 1; /* Data Read Timeout */
2511  uint32_t hto : 1; /* Data Starvation Host Timeout */
2512  uint32_t frun : 1; /* FIFO Underrun Overrun Error */
2513  uint32_t hle : 1; /* Hardware Locked Write Error */
2514  uint32_t sbe : 1; /* Start-bit Error */
2515  uint32_t acd : 1; /* Auto Command Done */
2516  uint32_t ebe : 1; /* End-bit Error Read Write no CRC */
2517  uint32_t sdio_int_mask : 16; /* ALT_SDMMC_INTMSK_SDIO_INT_MSK */
2518 };
2519 
2520 /* The typedef declaration for register ALT_SDMMC_INTMSK. */
2521 typedef volatile struct ALT_SDMMC_INTMSK_s ALT_SDMMC_INTMSK_t;
2522 #endif /* __ASSEMBLY__ */
2523 
2524 /* The reset value of the ALT_SDMMC_INTMSK register. */
2525 #define ALT_SDMMC_INTMSK_RESET 0x00000000
2526 /* The byte offset of the ALT_SDMMC_INTMSK register from the beginning of the component. */
2527 #define ALT_SDMMC_INTMSK_OFST 0x24
2528 
2529 /*
2530  * Register : cmdarg
2531  *
2532  * Command Argument Register
2533  *
2534  * Register Layout
2535  *
2536  * Bits | Access | Reset | Description
2537  * :-------|:-------|:------|:-------------------------
2538  * [31:0] | RW | 0x0 | ALT_SDMMC_CMDARG_CMD_ARG
2539  *
2540  */
2541 /*
2542  * Field : cmd_arg
2543  *
2544  * Value indicates command argument to be passed to card
2545  *
2546  * Field Access Macros:
2547  *
2548  */
2549 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMDARG_CMD_ARG register field. */
2550 #define ALT_SDMMC_CMDARG_CMD_ARG_LSB 0
2551 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMDARG_CMD_ARG register field. */
2552 #define ALT_SDMMC_CMDARG_CMD_ARG_MSB 31
2553 /* The width in bits of the ALT_SDMMC_CMDARG_CMD_ARG register field. */
2554 #define ALT_SDMMC_CMDARG_CMD_ARG_WIDTH 32
2555 /* The mask used to set the ALT_SDMMC_CMDARG_CMD_ARG register field value. */
2556 #define ALT_SDMMC_CMDARG_CMD_ARG_SET_MSK 0xffffffff
2557 /* The mask used to clear the ALT_SDMMC_CMDARG_CMD_ARG register field value. */
2558 #define ALT_SDMMC_CMDARG_CMD_ARG_CLR_MSK 0x00000000
2559 /* The reset value of the ALT_SDMMC_CMDARG_CMD_ARG register field. */
2560 #define ALT_SDMMC_CMDARG_CMD_ARG_RESET 0x0
2561 /* Extracts the ALT_SDMMC_CMDARG_CMD_ARG field value from a register. */
2562 #define ALT_SDMMC_CMDARG_CMD_ARG_GET(value) (((value) & 0xffffffff) >> 0)
2563 /* Produces a ALT_SDMMC_CMDARG_CMD_ARG register field value suitable for setting the register. */
2564 #define ALT_SDMMC_CMDARG_CMD_ARG_SET(value) (((value) << 0) & 0xffffffff)
2565 
2566 #ifndef __ASSEMBLY__
2567 /*
2568  * WARNING: The C register and register group struct declarations are provided for
2569  * convenience and illustrative purposes. They should, however, be used with
2570  * caution as the C language standard provides no guarantees about the alignment or
2571  * atomicity of device memory accesses. The recommended practice for writing
2572  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2573  * alt_write_word() functions.
2574  *
2575  * The struct declaration for register ALT_SDMMC_CMDARG.
2576  */
2577 struct ALT_SDMMC_CMDARG_s
2578 {
2579  uint32_t cmd_arg : 32; /* ALT_SDMMC_CMDARG_CMD_ARG */
2580 };
2581 
2582 /* The typedef declaration for register ALT_SDMMC_CMDARG. */
2583 typedef volatile struct ALT_SDMMC_CMDARG_s ALT_SDMMC_CMDARG_t;
2584 #endif /* __ASSEMBLY__ */
2585 
2586 /* The reset value of the ALT_SDMMC_CMDARG register. */
2587 #define ALT_SDMMC_CMDARG_RESET 0x00000000
2588 /* The byte offset of the ALT_SDMMC_CMDARG register from the beginning of the component. */
2589 #define ALT_SDMMC_CMDARG_OFST 0x28
2590 
2591 /*
2592  * Register : cmd
2593  *
2594  * Command Register
2595  *
2596  * Register Layout
2597  *
2598  * Bits | Access | Reset | Description
2599  * :--------|:-------|:------|:------------------------------------
2600  * [5:0] | RW | 0x0 | ALT_SDMMC_CMD_CMD_INDEX
2601  * [6] | RW | 0x0 | ALT_SDMMC_CMD_RESPONSE_EXPECT
2602  * [7] | RW | 0x0 | ALT_SDMMC_CMD_RESPONSE_LEN
2603  * [8] | RW | 0x0 | ALT_SDMMC_CMD_CHECK_RESPONSE_CRC
2604  * [9] | RW | 0x0 | ALT_SDMMC_CMD_DATA_EXPECTED
2605  * [10] | RW | 0x0 | ALT_SDMMC_CMD_RD_WR
2606  * [11] | RW | 0x0 | ALT_SDMMC_CMD_TFR_MOD
2607  * [12] | RW | 0x0 | ALT_SDMMC_CMD_SEND_AUTO_STOP
2608  * [13] | RW | 0x0 | ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE
2609  * [14] | RW | 0x0 | ALT_SDMMC_CMD_STOP_ABT_CMD
2610  * [15] | RW | 0x0 | ALT_SDMMC_CMD_SEND_INITIALIZATION
2611  * [20:16] | RW | 0x0 | ALT_SDMMC_CMD_CARD_NUMBER
2612  * [21] | RW | 0x0 | ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY
2613  * [22] | RW | 0x0 | ALT_SDMMC_CMD_RD_CEATA_DEVICE
2614  * [23] | RW | 0x0 | ALT_SDMMC_CMD_CCS_EXPECTED
2615  * [24] | RW | 0x0 | ALT_SDMMC_CMD_EN_BOOT
2616  * [25] | RW | 0x0 | ALT_SDMMC_CMD_EXPECT_BOOT_ACK
2617  * [26] | RW | 0x0 | ALT_SDMMC_CMD_DIS_BOOT
2618  * [27] | RW | 0x0 | ALT_SDMMC_CMD_BOOT_MOD
2619  * [28] | RW | 0x0 | ALT_SDMMC_CMD_VOLT_SWITCH
2620  * [29] | RW | 0x1 | ALT_SDMMC_CMD_USE_HOLD_REG
2621  * [30] | ??? | 0x0 | *UNDEFINED*
2622  * [31] | RW | 0x0 | ALT_SDMMC_CMD_START_CMD
2623  *
2624  */
2625 /*
2626  * Field : cmd_index
2627  *
2628  * Command index
2629  *
2630  * Field Access Macros:
2631  *
2632  */
2633 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CMD_INDEX register field. */
2634 #define ALT_SDMMC_CMD_CMD_INDEX_LSB 0
2635 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CMD_INDEX register field. */
2636 #define ALT_SDMMC_CMD_CMD_INDEX_MSB 5
2637 /* The width in bits of the ALT_SDMMC_CMD_CMD_INDEX register field. */
2638 #define ALT_SDMMC_CMD_CMD_INDEX_WIDTH 6
2639 /* The mask used to set the ALT_SDMMC_CMD_CMD_INDEX register field value. */
2640 #define ALT_SDMMC_CMD_CMD_INDEX_SET_MSK 0x0000003f
2641 /* The mask used to clear the ALT_SDMMC_CMD_CMD_INDEX register field value. */
2642 #define ALT_SDMMC_CMD_CMD_INDEX_CLR_MSK 0xffffffc0
2643 /* The reset value of the ALT_SDMMC_CMD_CMD_INDEX register field. */
2644 #define ALT_SDMMC_CMD_CMD_INDEX_RESET 0x0
2645 /* Extracts the ALT_SDMMC_CMD_CMD_INDEX field value from a register. */
2646 #define ALT_SDMMC_CMD_CMD_INDEX_GET(value) (((value) & 0x0000003f) >> 0)
2647 /* Produces a ALT_SDMMC_CMD_CMD_INDEX register field value suitable for setting the register. */
2648 #define ALT_SDMMC_CMD_CMD_INDEX_SET(value) (((value) << 0) & 0x0000003f)
2649 
2650 /*
2651  * Field : response_expect
2652  *
2653  * 0-No response expected from card
2654  *
2655  * 1-Response expected from card
2656  *
2657  * Field Enumeration Values:
2658  *
2659  * Enum | Value | Description
2660  * :---------------------------------------|:------|:-------------------------------
2661  * ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP | 0x0 | No response expected from card
2662  * ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NORESP | 0x1 | Response expected from card
2663  *
2664  * Field Access Macros:
2665  *
2666  */
2667 /*
2668  * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_EXPECT
2669  *
2670  * No response expected from card
2671  */
2672 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP 0x0
2673 /*
2674  * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_EXPECT
2675  *
2676  * Response expected from card
2677  */
2678 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NORESP 0x1
2679 
2680 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */
2681 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_LSB 6
2682 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */
2683 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_MSB 6
2684 /* The width in bits of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */
2685 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_WIDTH 1
2686 /* The mask used to set the ALT_SDMMC_CMD_RESPONSE_EXPECT register field value. */
2687 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET_MSK 0x00000040
2688 /* The mask used to clear the ALT_SDMMC_CMD_RESPONSE_EXPECT register field value. */
2689 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_CLR_MSK 0xffffffbf
2690 /* The reset value of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */
2691 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_RESET 0x0
2692 /* Extracts the ALT_SDMMC_CMD_RESPONSE_EXPECT field value from a register. */
2693 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_GET(value) (((value) & 0x00000040) >> 6)
2694 /* Produces a ALT_SDMMC_CMD_RESPONSE_EXPECT register field value suitable for setting the register. */
2695 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET(value) (((value) << 6) & 0x00000040)
2696 
2697 /*
2698  * Field : response_length
2699  *
2700  * 0-Short response expected from card
2701  *
2702  * 1-Long response expected from card
2703  *
2704  * Field Enumeration Values:
2705  *
2706  * Enum | Value | Description
2707  * :-----------------------------------|:------|:----------------------------------
2708  * ALT_SDMMC_CMD_RESPONSE_LEN_E_SHORT | 0x0 | Short response expected from card
2709  * ALT_SDMMC_CMD_RESPONSE_LEN_E_LONG | 0x1 | Long response expected from card
2710  *
2711  * Field Access Macros:
2712  *
2713  */
2714 /*
2715  * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_LEN
2716  *
2717  * Short response expected from card
2718  */
2719 #define ALT_SDMMC_CMD_RESPONSE_LEN_E_SHORT 0x0
2720 /*
2721  * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_LEN
2722  *
2723  * Long response expected from card
2724  */
2725 #define ALT_SDMMC_CMD_RESPONSE_LEN_E_LONG 0x1
2726 
2727 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RESPONSE_LEN register field. */
2728 #define ALT_SDMMC_CMD_RESPONSE_LEN_LSB 7
2729 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RESPONSE_LEN register field. */
2730 #define ALT_SDMMC_CMD_RESPONSE_LEN_MSB 7
2731 /* The width in bits of the ALT_SDMMC_CMD_RESPONSE_LEN register field. */
2732 #define ALT_SDMMC_CMD_RESPONSE_LEN_WIDTH 1
2733 /* The mask used to set the ALT_SDMMC_CMD_RESPONSE_LEN register field value. */
2734 #define ALT_SDMMC_CMD_RESPONSE_LEN_SET_MSK 0x00000080
2735 /* The mask used to clear the ALT_SDMMC_CMD_RESPONSE_LEN register field value. */
2736 #define ALT_SDMMC_CMD_RESPONSE_LEN_CLR_MSK 0xffffff7f
2737 /* The reset value of the ALT_SDMMC_CMD_RESPONSE_LEN register field. */
2738 #define ALT_SDMMC_CMD_RESPONSE_LEN_RESET 0x0
2739 /* Extracts the ALT_SDMMC_CMD_RESPONSE_LEN field value from a register. */
2740 #define ALT_SDMMC_CMD_RESPONSE_LEN_GET(value) (((value) & 0x00000080) >> 7)
2741 /* Produces a ALT_SDMMC_CMD_RESPONSE_LEN register field value suitable for setting the register. */
2742 #define ALT_SDMMC_CMD_RESPONSE_LEN_SET(value) (((value) << 7) & 0x00000080)
2743 
2744 /*
2745  * Field : check_response_crc
2746  *
2747  * 0-Do not check response CRC
2748  *
2749  * 1-Check response CRC
2750  *
2751  * Some of command responses do not return valid CRC bits. Software should disable
2752  * CRC checks for those commands in order to disable CRC checking by controller.
2753  *
2754  * Field Enumeration Values:
2755  *
2756  * Enum | Value | Description
2757  * :-----------------------------------------|:------|:--------------------------
2758  * ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_NOCHK | 0x0 | Do not check response CRC
2759  * ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_CHK | 0x1 | Check Response CRC
2760  *
2761  * Field Access Macros:
2762  *
2763  */
2764 /*
2765  * Enumerated value for register field ALT_SDMMC_CMD_CHECK_RESPONSE_CRC
2766  *
2767  * Do not check response CRC
2768  */
2769 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_NOCHK 0x0
2770 /*
2771  * Enumerated value for register field ALT_SDMMC_CMD_CHECK_RESPONSE_CRC
2772  *
2773  * Check Response CRC
2774  */
2775 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_CHK 0x1
2776 
2777 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */
2778 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_LSB 8
2779 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */
2780 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_MSB 8
2781 /* The width in bits of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */
2782 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_WIDTH 1
2783 /* The mask used to set the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value. */
2784 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET_MSK 0x00000100
2785 /* The mask used to clear the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value. */
2786 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_CLR_MSK 0xfffffeff
2787 /* The reset value of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */
2788 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_RESET 0x0
2789 /* Extracts the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC field value from a register. */
2790 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_GET(value) (((value) & 0x00000100) >> 8)
2791 /* Produces a ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value suitable for setting the register. */
2792 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET(value) (((value) << 8) & 0x00000100)
2793 
2794 /*
2795  * Field : data_expected
2796  *
2797  * 0-No data transfer expected (read/write)
2798  *
2799  * 1-Data transfer expected (read/write)
2800  *
2801  * Field Enumeration Values:
2802  *
2803  * Enum | Value | Description
2804  * :-------------------------------------------|:------|:---------------------------------------
2805  * ALT_SDMMC_CMD_DATA_EXPECTED_E_NODATXFEREXP | 0x0 | No data transfer expected (read/write)
2806  * ALT_SDMMC_CMD_DATA_EXPECTED_E_DATAXFEREXP | 0x1 | Data transfer expected (read/write)
2807  *
2808  * Field Access Macros:
2809  *
2810  */
2811 /*
2812  * Enumerated value for register field ALT_SDMMC_CMD_DATA_EXPECTED
2813  *
2814  * No data transfer expected (read/write)
2815  */
2816 #define ALT_SDMMC_CMD_DATA_EXPECTED_E_NODATXFEREXP 0x0
2817 /*
2818  * Enumerated value for register field ALT_SDMMC_CMD_DATA_EXPECTED
2819  *
2820  * Data transfer expected (read/write)
2821  */
2822 #define ALT_SDMMC_CMD_DATA_EXPECTED_E_DATAXFEREXP 0x1
2823 
2824 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */
2825 #define ALT_SDMMC_CMD_DATA_EXPECTED_LSB 9
2826 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */
2827 #define ALT_SDMMC_CMD_DATA_EXPECTED_MSB 9
2828 /* The width in bits of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */
2829 #define ALT_SDMMC_CMD_DATA_EXPECTED_WIDTH 1
2830 /* The mask used to set the ALT_SDMMC_CMD_DATA_EXPECTED register field value. */
2831 #define ALT_SDMMC_CMD_DATA_EXPECTED_SET_MSK 0x00000200
2832 /* The mask used to clear the ALT_SDMMC_CMD_DATA_EXPECTED register field value. */
2833 #define ALT_SDMMC_CMD_DATA_EXPECTED_CLR_MSK 0xfffffdff
2834 /* The reset value of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */
2835 #define ALT_SDMMC_CMD_DATA_EXPECTED_RESET 0x0
2836 /* Extracts the ALT_SDMMC_CMD_DATA_EXPECTED field value from a register. */
2837 #define ALT_SDMMC_CMD_DATA_EXPECTED_GET(value) (((value) & 0x00000200) >> 9)
2838 /* Produces a ALT_SDMMC_CMD_DATA_EXPECTED register field value suitable for setting the register. */
2839 #define ALT_SDMMC_CMD_DATA_EXPECTED_SET(value) (((value) << 9) & 0x00000200)
2840 
2841 /*
2842  * Field : read_write
2843  *
2844  * 0-Read from card
2845  *
2846  * 1-Write to card
2847  *
2848  * Don't care if no data expected from card.
2849  *
2850  * Field Enumeration Values:
2851  *
2852  * Enum | Value | Description
2853  * :-------------------------|:------|:---------------
2854  * ALT_SDMMC_CMD_RD_WR_E_RD | 0x0 | Read from card
2855  * ALT_SDMMC_CMD_RD_WR_E_WR | 0x1 | Write to card
2856  *
2857  * Field Access Macros:
2858  *
2859  */
2860 /*
2861  * Enumerated value for register field ALT_SDMMC_CMD_RD_WR
2862  *
2863  * Read from card
2864  */
2865 #define ALT_SDMMC_CMD_RD_WR_E_RD 0x0
2866 /*
2867  * Enumerated value for register field ALT_SDMMC_CMD_RD_WR
2868  *
2869  * Write to card
2870  */
2871 #define ALT_SDMMC_CMD_RD_WR_E_WR 0x1
2872 
2873 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RD_WR register field. */
2874 #define ALT_SDMMC_CMD_RD_WR_LSB 10
2875 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RD_WR register field. */
2876 #define ALT_SDMMC_CMD_RD_WR_MSB 10
2877 /* The width in bits of the ALT_SDMMC_CMD_RD_WR register field. */
2878 #define ALT_SDMMC_CMD_RD_WR_WIDTH 1
2879 /* The mask used to set the ALT_SDMMC_CMD_RD_WR register field value. */
2880 #define ALT_SDMMC_CMD_RD_WR_SET_MSK 0x00000400
2881 /* The mask used to clear the ALT_SDMMC_CMD_RD_WR register field value. */
2882 #define ALT_SDMMC_CMD_RD_WR_CLR_MSK 0xfffffbff
2883 /* The reset value of the ALT_SDMMC_CMD_RD_WR register field. */
2884 #define ALT_SDMMC_CMD_RD_WR_RESET 0x0
2885 /* Extracts the ALT_SDMMC_CMD_RD_WR field value from a register. */
2886 #define ALT_SDMMC_CMD_RD_WR_GET(value) (((value) & 0x00000400) >> 10)
2887 /* Produces a ALT_SDMMC_CMD_RD_WR register field value suitable for setting the register. */
2888 #define ALT_SDMMC_CMD_RD_WR_SET(value) (((value) << 10) & 0x00000400)
2889 
2890 /*
2891  * Field : transfer_mode
2892  *
2893  * 0-Block data transfer command
2894  *
2895  * 1-Stream data transfer command
2896  *
2897  * Don't care if no data expected.
2898  *
2899  * Field Enumeration Values:
2900  *
2901  * Enum | Value | Description
2902  * :----------------------------|:------|:-----------------------------
2903  * ALT_SDMMC_CMD_TFR_MOD_E_BLK | 0x0 | Block data transfer command
2904  * ALT_SDMMC_CMD_TFR_MOD_E_STR | 0x1 | Stream data transfer command
2905  *
2906  * Field Access Macros:
2907  *
2908  */
2909 /*
2910  * Enumerated value for register field ALT_SDMMC_CMD_TFR_MOD
2911  *
2912  * Block data transfer command
2913  */
2914 #define ALT_SDMMC_CMD_TFR_MOD_E_BLK 0x0
2915 /*
2916  * Enumerated value for register field ALT_SDMMC_CMD_TFR_MOD
2917  *
2918  * Stream data transfer command
2919  */
2920 #define ALT_SDMMC_CMD_TFR_MOD_E_STR 0x1
2921 
2922 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_TFR_MOD register field. */
2923 #define ALT_SDMMC_CMD_TFR_MOD_LSB 11
2924 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_TFR_MOD register field. */
2925 #define ALT_SDMMC_CMD_TFR_MOD_MSB 11
2926 /* The width in bits of the ALT_SDMMC_CMD_TFR_MOD register field. */
2927 #define ALT_SDMMC_CMD_TFR_MOD_WIDTH 1
2928 /* The mask used to set the ALT_SDMMC_CMD_TFR_MOD register field value. */
2929 #define ALT_SDMMC_CMD_TFR_MOD_SET_MSK 0x00000800
2930 /* The mask used to clear the ALT_SDMMC_CMD_TFR_MOD register field value. */
2931 #define ALT_SDMMC_CMD_TFR_MOD_CLR_MSK 0xfffff7ff
2932 /* The reset value of the ALT_SDMMC_CMD_TFR_MOD register field. */
2933 #define ALT_SDMMC_CMD_TFR_MOD_RESET 0x0
2934 /* Extracts the ALT_SDMMC_CMD_TFR_MOD field value from a register. */
2935 #define ALT_SDMMC_CMD_TFR_MOD_GET(value) (((value) & 0x00000800) >> 11)
2936 /* Produces a ALT_SDMMC_CMD_TFR_MOD register field value suitable for setting the register. */
2937 #define ALT_SDMMC_CMD_TFR_MOD_SET(value) (((value) << 11) & 0x00000800)
2938 
2939 /*
2940  * Field : send_auto_stop
2941  *
2942  * 0-No stop command sent at end of data transfer
2943  *
2944  * 1-Send stop command at end of data transfer
2945  *
2946  * When set, DWC_mobile_storage sends stop command to SD_MMC_CEATA cards at end of
2947  * data transfer.
2948  *
2949  * * when send_auto_stop bit should be set, since some data
2950  *
2951  * transfers do not need explicit stop commands
2952  *
2953  * * open-ended transfers that software should explicitly send to
2954  *
2955  * stop command
2956  *
2957  * Additionally, when "resume" is sent to resume suspended memory access of SD-
2958  * Combo card bit should be set correctly if suspended data transfer needs
2959  * send_auto_stop.Don't care if no data expected from card.
2960  *
2961  * Field Enumeration Values:
2962  *
2963  * Enum | Value | Description
2964  * :--------------------------------------|:------|:---------------------------------------------
2965  * ALT_SDMMC_CMD_SEND_AUTO_STOP_E_NOSEND | 0x0 | No stop command sent at end of data transfer
2966  * ALT_SDMMC_CMD_SEND_AUTO_STOP_E_SEND | 0x1 | Send stop command at end of data transfer
2967  *
2968  * Field Access Macros:
2969  *
2970  */
2971 /*
2972  * Enumerated value for register field ALT_SDMMC_CMD_SEND_AUTO_STOP
2973  *
2974  * No stop command sent at end of data transfer
2975  */
2976 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_NOSEND 0x0
2977 /*
2978  * Enumerated value for register field ALT_SDMMC_CMD_SEND_AUTO_STOP
2979  *
2980  * Send stop command at end of data transfer
2981  */
2982 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_SEND 0x1
2983 
2984 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */
2985 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_LSB 12
2986 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */
2987 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_MSB 12
2988 /* The width in bits of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */
2989 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_WIDTH 1
2990 /* The mask used to set the ALT_SDMMC_CMD_SEND_AUTO_STOP register field value. */
2991 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET_MSK 0x00001000
2992 /* The mask used to clear the ALT_SDMMC_CMD_SEND_AUTO_STOP register field value. */
2993 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_CLR_MSK 0xffffefff
2994 /* The reset value of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */
2995 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_RESET 0x0
2996 /* Extracts the ALT_SDMMC_CMD_SEND_AUTO_STOP field value from a register. */
2997 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_GET(value) (((value) & 0x00001000) >> 12)
2998 /* Produces a ALT_SDMMC_CMD_SEND_AUTO_STOP register field value suitable for setting the register. */
2999 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET(value) (((value) << 12) & 0x00001000)
3000 
3001 /*
3002  * Field : wait_prvdata_complete
3003  *
3004  * 0-Send command at once, even if previous data transfer has not
3005  *
3006  * completed
3007  *
3008  * 1-Wait for previous data transfer completion before sending
3009  *
3010  * command
3011  *
3012  * The wait_prvdata_complete = 0 option typically used to query status of card
3013  * during data transfer or to stop current data transfer;card_number should be same
3014  * as in previous command.
3015  *
3016  * Field Enumeration Values:
3017  *
3018  * Enum | Value | Description
3019  * :---------------------------------------------|:------|:-------------------------------------------
3020  * ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NOWAIT | 0x0 | Send command at once
3021  * ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT | 0x1 | Wait for previous data transfer completion
3022  *
3023  * Field Access Macros:
3024  *
3025  */
3026 /*
3027  * Enumerated value for register field ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE
3028  *
3029  * Send command at once
3030  */
3031 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NOWAIT 0x0
3032 /*
3033  * Enumerated value for register field ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE
3034  *
3035  * Wait for previous data transfer completion
3036  */
3037 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT 0x1
3038 
3039 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */
3040 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_LSB 13
3041 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */
3042 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_MSB 13
3043 /* The width in bits of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */
3044 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_WIDTH 1
3045 /* The mask used to set the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value. */
3046 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET_MSK 0x00002000
3047 /* The mask used to clear the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value. */
3048 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_CLR_MSK 0xffffdfff
3049 /* The reset value of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */
3050 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_RESET 0x0
3051 /* Extracts the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE field value from a register. */
3052 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_GET(value) (((value) & 0x00002000) >> 13)
3053 /* Produces a ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value suitable for setting the register. */
3054 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET(value) (((value) << 13) & 0x00002000)
3055 
3056 /*
3057  * Field : stop_abort_cmd
3058  *
3059  * 0-Neither stop nor abort command to stop current data transfer
3060  *
3061  * in progress. If abort is sent to function-number currently
3062  *
3063  * selected or not in data-transfer mode, then bit should be set
3064  *
3065  * to 0.
3066  *
3067  * 1-Stop or abort command intended to stop current data transfer
3068  *
3069  * in progress.
3070  *
3071  * When open-ended or predefined data transfer is in progress, and host issues stop
3072  * or abort command to stop data transfer, bit should be set so that command/data
3073  * state-machines of CIU can return correctly to idle state. This is also
3074  * applicable for Boot mode transfers. To Abort boot mode, this bit should be set
3075  * along with CMD[26] = disable_boot.
3076  *
3077  * Field Enumeration Values:
3078  *
3079  * Enum | Value | Description
3080  * :----------------------------------------|:------|:-------------------------------------------------
3081  * ALT_SDMMC_CMD_STOP_ABT_CMD_E_NOSTOPABRT | 0x0 | Don't stop or abort command to stop current data
3082  * : | | transfer in progress
3083  * ALT_SDMMC_CMD_STOP_ABT_CMD_E_STOPABRT | 0x1 | Stop or Abort command, intended to stop current
3084  * : | | data transfer in progress
3085  *
3086  * Field Access Macros:
3087  *
3088  */
3089 /*
3090  * Enumerated value for register field ALT_SDMMC_CMD_STOP_ABT_CMD
3091  *
3092  * Don't stop or abort command to stop current data transfer in progress
3093  */
3094 #define ALT_SDMMC_CMD_STOP_ABT_CMD_E_NOSTOPABRT 0x0
3095 /*
3096  * Enumerated value for register field ALT_SDMMC_CMD_STOP_ABT_CMD
3097  *
3098  * Stop or Abort command, intended to stop current data transfer in progress
3099  */
3100 #define ALT_SDMMC_CMD_STOP_ABT_CMD_E_STOPABRT 0x1
3101 
3102 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_STOP_ABT_CMD register field. */
3103 #define ALT_SDMMC_CMD_STOP_ABT_CMD_LSB 14
3104 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_STOP_ABT_CMD register field. */
3105 #define ALT_SDMMC_CMD_STOP_ABT_CMD_MSB 14
3106 /* The width in bits of the ALT_SDMMC_CMD_STOP_ABT_CMD register field. */
3107 #define ALT_SDMMC_CMD_STOP_ABT_CMD_WIDTH 1
3108 /* The mask used to set the ALT_SDMMC_CMD_STOP_ABT_CMD register field value. */
3109 #define ALT_SDMMC_CMD_STOP_ABT_CMD_SET_MSK 0x00004000
3110 /* The mask used to clear the ALT_SDMMC_CMD_STOP_ABT_CMD register field value. */
3111 #define ALT_SDMMC_CMD_STOP_ABT_CMD_CLR_MSK 0xffffbfff
3112 /* The reset value of the ALT_SDMMC_CMD_STOP_ABT_CMD register field. */
3113 #define ALT_SDMMC_CMD_STOP_ABT_CMD_RESET 0x0
3114 /* Extracts the ALT_SDMMC_CMD_STOP_ABT_CMD field value from a register. */
3115 #define ALT_SDMMC_CMD_STOP_ABT_CMD_GET(value) (((value) & 0x00004000) >> 14)
3116 /* Produces a ALT_SDMMC_CMD_STOP_ABT_CMD register field value suitable for setting the register. */
3117 #define ALT_SDMMC_CMD_STOP_ABT_CMD_SET(value) (((value) << 14) & 0x00004000)
3118 
3119 /*
3120  * Field : send_initialization
3121  *
3122  * 0-Do not send initialization sequence (80 clocks of 1) before
3123  *
3124  * sending this command
3125  *
3126  * 1-Send initialization sequence before sending this command
3127  *
3128  * After power on, 80 clocks must be sent to card for initialization before sending
3129  * any commands to card. Bit should be set while sending first command to card so
3130  * that controller will initialize clocks before sending command to card. This bit
3131  * should not be set for either of the boot modes (alternate or mandatory).
3132  *
3133  * Field Enumeration Values:
3134  *
3135  * Enum | Value | Description
3136  * :-------------------------------------------|:------|:-------------------------------------------------
3137  * ALT_SDMMC_CMD_SEND_INITIALIZATION_E_NOINIT | 0x0 | Do not send initialization sequence (80 clocks
3138  * : | | of 1) before sending this command
3139  * ALT_SDMMC_CMD_SEND_INITIALIZATION_E_INIT | 0x1 | Send initialization sequence before sending this
3140  * : | | command
3141  *
3142  * Field Access Macros:
3143  *
3144  */
3145 /*
3146  * Enumerated value for register field ALT_SDMMC_CMD_SEND_INITIALIZATION
3147  *
3148  * Do not send initialization sequence (80 clocks of 1) before sending this command
3149  */
3150 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_NOINIT 0x0
3151 /*
3152  * Enumerated value for register field ALT_SDMMC_CMD_SEND_INITIALIZATION
3153  *
3154  * Send initialization sequence before sending this command
3155  */
3156 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_INIT 0x1
3157 
3158 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */
3159 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_LSB 15
3160 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */
3161 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_MSB 15
3162 /* The width in bits of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */
3163 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_WIDTH 1
3164 /* The mask used to set the ALT_SDMMC_CMD_SEND_INITIALIZATION register field value. */
3165 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET_MSK 0x00008000
3166 /* The mask used to clear the ALT_SDMMC_CMD_SEND_INITIALIZATION register field value. */
3167 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_CLR_MSK 0xffff7fff
3168 /* The reset value of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */
3169 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_RESET 0x0
3170 /* Extracts the ALT_SDMMC_CMD_SEND_INITIALIZATION field value from a register. */
3171 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_GET(value) (((value) & 0x00008000) >> 15)
3172 /* Produces a ALT_SDMMC_CMD_SEND_INITIALIZATION register field value suitable for setting the register. */
3173 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET(value) (((value) << 15) & 0x00008000)
3174 
3175 /*
3176  * Field : card_number
3177  *
3178  * Card number in use. Represents physical slot number of card being
3179  *
3180  * accessed. In MMC-Ver3.3-only mode, up to 30 cards are supported; in SD-only
3181  * mode, up to 16 cards are supported. Registered version of this is reflected on
3182  * dw_dma_card_num and ge_dma_card_num ports, which can be used to create separate
3183  * DMA requests, if needed.
3184  *
3185  * In addition, in SD mode this is used to mux or demux signals from selected card
3186  * because each card is interfaced to
3187  *
3188  * DWC_mobile_storage by separate bus.
3189  *
3190  * Field Access Macros:
3191  *
3192  */
3193 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CARD_NUMBER register field. */
3194 #define ALT_SDMMC_CMD_CARD_NUMBER_LSB 16
3195 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CARD_NUMBER register field. */
3196 #define ALT_SDMMC_CMD_CARD_NUMBER_MSB 20
3197 /* The width in bits of the ALT_SDMMC_CMD_CARD_NUMBER register field. */
3198 #define ALT_SDMMC_CMD_CARD_NUMBER_WIDTH 5
3199 /* The mask used to set the ALT_SDMMC_CMD_CARD_NUMBER register field value. */
3200 #define ALT_SDMMC_CMD_CARD_NUMBER_SET_MSK 0x001f0000
3201 /* The mask used to clear the ALT_SDMMC_CMD_CARD_NUMBER register field value. */
3202 #define ALT_SDMMC_CMD_CARD_NUMBER_CLR_MSK 0xffe0ffff
3203 /* The reset value of the ALT_SDMMC_CMD_CARD_NUMBER register field. */
3204 #define ALT_SDMMC_CMD_CARD_NUMBER_RESET 0x0
3205 /* Extracts the ALT_SDMMC_CMD_CARD_NUMBER field value from a register. */
3206 #define ALT_SDMMC_CMD_CARD_NUMBER_GET(value) (((value) & 0x001f0000) >> 16)
3207 /* Produces a ALT_SDMMC_CMD_CARD_NUMBER register field value suitable for setting the register. */
3208 #define ALT_SDMMC_CMD_CARD_NUMBER_SET(value) (((value) << 16) & 0x001f0000)
3209 
3210 /*
3211  * Field : update_clock_registers_only
3212  *
3213  * 0-Normal command sequence
3214  *
3215  * 1-Do not send commands, just update clock register value into
3216  *
3217  * card clock domain
3218  *
3219  * Following register values transferred into card clock domain: CLKDIV, CLRSRC,
3220  * CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-
3221  * frequency mode); provided in order to change clock frequency or stop clock
3222  * without having to send command to cards.During normal command sequence, when
3223  * update_clock_registers_only = 0, following control registers are transferred
3224  * from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE,BLKSIZ, BYTCNT. CIU uses new register
3225  * values for new command sequence to card(s).When bit is set, there are no Command
3226  * Done interrupts because no
3227  *
3228  * command is sent to SD_MMC_CEATA cards.
3229  *
3230  * Field Enumeration Values:
3231  *
3232  * Enum | Value | Description
3233  * :-------------------------------------------------|:------|:-------------------------------------------------
3234  * ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_NORMCMD | 0x0 | Normal command sequence
3235  * ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_UPDATCLKREG | 0x1 | Do not send commands, just update clock register
3236  * : | | value into card clock domain
3237  *
3238  * Field Access Macros:
3239  *
3240  */
3241 /*
3242  * Enumerated value for register field ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY
3243  *
3244  * Normal command sequence
3245  */
3246 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_NORMCMD 0x0
3247 /*
3248  * Enumerated value for register field ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY
3249  *
3250  * Do not send commands, just update clock register value into card clock domain
3251  */
3252 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_UPDATCLKREG 0x1
3253 
3254 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field. */
3255 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_LSB 21
3256 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field. */
3257 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_MSB 21
3258 /* The width in bits of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field. */
3259 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_WIDTH 1
3260 /* The mask used to set the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field value. */
3261 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET_MSK 0x00200000
3262 /* The mask used to clear the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field value. */
3263 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_CLR_MSK 0xffdfffff
3264 /* The reset value of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field. */
3265 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_RESET 0x0
3266 /* Extracts the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY field value from a register. */
3267 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_GET(value) (((value) & 0x00200000) >> 21)
3268 /* Produces a ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field value suitable for setting the register. */
3269 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET(value) (((value) << 21) & 0x00200000)
3270 
3271 /*
3272  * Field : read_ceata_device
3273  *
3274  * 0-Host is not performing read access (RW_REG or RW_BLK)
3275  *
3276  * towards CE-ATA device
3277  *
3278  * 1-Host is performing read access (RW_REG or RW_BLK)
3279  *
3280  * towards CE-ATA device
3281  *
3282  * Software should set this bit to indicate that CE-ATA device is being accessed
3283  * for read transfer. This bit is used to disable read data timeout indication
3284  * while performing CE-ATA read transfers.Maximum value of I/O transmission delay
3285  * can be no less than 10 seconds. DWC_mobile_storage should not indicate read data
3286  * timeout while waiting for data from CE-ATA device.
3287  *
3288  * Field Enumeration Values:
3289  *
3290  * Enum | Value | Description
3291  * :-------------------------------------|:------|:----------------------------------------------
3292  * ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_NORD | 0x0 | Host is not performing read access (RW_REG or
3293  * : | | RW_BLK) towards CE-ATA device
3294  * ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_RD | 0x1 | Host is performing read access (RW_REG or
3295  * : | | RW_BLK) towards CE-ATA device
3296  *
3297  * Field Access Macros:
3298  *
3299  */
3300 /*
3301  * Enumerated value for register field ALT_SDMMC_CMD_RD_CEATA_DEVICE
3302  *
3303  * Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device
3304  */
3305 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_NORD 0x0
3306 /*
3307  * Enumerated value for register field ALT_SDMMC_CMD_RD_CEATA_DEVICE
3308  *
3309  * Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device
3310  */
3311 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_RD 0x1
3312 
3313 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field. */
3314 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_LSB 22
3315 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field. */
3316 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_MSB 22
3317 /* The width in bits of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field. */
3318 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_WIDTH 1
3319 /* The mask used to set the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field value. */
3320 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET_MSK 0x00400000
3321 /* The mask used to clear the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field value. */
3322 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_CLR_MSK 0xffbfffff
3323 /* The reset value of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field. */
3324 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_RESET 0x0
3325 /* Extracts the ALT_SDMMC_CMD_RD_CEATA_DEVICE field value from a register. */
3326 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_GET(value) (((value) & 0x00400000) >> 22)
3327 /* Produces a ALT_SDMMC_CMD_RD_CEATA_DEVICE register field value suitable for setting the register. */
3328 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET(value) (((value) << 22) & 0x00400000)
3329 
3330 /*
3331  * Field : ccs_expected
3332  *
3333  * 0-Interrupts are not enabled in CE-ATA device (nIEN = 1 in
3334  *
3335  * ATA control register), or command does not expect CCS
3336  *
3337  * from device
3338  *
3339  * 1-Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK
3340  *
3341  * command expects command completion signal from CE-ATA device
3342  *
3343  * If the command expects Command Completion Signal (CCS) from the CE-ATA device,
3344  * the software should set this control bit.DWC_mobile_storage sets Data Transfer
3345  * Over (DTO) bit in RINTSTS register and generates interrupt to host if Data
3346  * Transfer Over interrupt is not masked.
3347  *
3348  * Field Enumeration Values:
3349  *
3350  * Enum | Value | Description
3351  * :----------------------------------|:------|:------------------------------------------------
3352  * ALT_SDMMC_CMD_CCS_EXPECTED_E_DISD | 0x0 | Interrupts are not enabled in CE-ATA device
3353  * : | | (nIEN = 1 in ATA control register), or command
3354  * : | | does not expect CCS from device
3355  * ALT_SDMMC_CMD_CCS_EXPECTED_E_END | 0x1 | Interrupts are enabled in CE-ATA device (nIEN =
3356  * : | | 0), and RW_BLK command expects command
3357  * : | | completion signal from CE-ATA device
3358  *
3359  * Field Access Macros:
3360  *
3361  */
3362 /*
3363  * Enumerated value for register field ALT_SDMMC_CMD_CCS_EXPECTED
3364  *
3365  * Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register),
3366  * or command does not expect CCS from device
3367  */
3368 #define ALT_SDMMC_CMD_CCS_EXPECTED_E_DISD 0x0
3369 /*
3370  * Enumerated value for register field ALT_SDMMC_CMD_CCS_EXPECTED
3371  *
3372  * Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects
3373  * command completion signal from CE-ATA device
3374  */
3375 #define ALT_SDMMC_CMD_CCS_EXPECTED_E_END 0x1
3376 
3377 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */
3378 #define ALT_SDMMC_CMD_CCS_EXPECTED_LSB 23
3379 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */
3380 #define ALT_SDMMC_CMD_CCS_EXPECTED_MSB 23
3381 /* The width in bits of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */
3382 #define ALT_SDMMC_CMD_CCS_EXPECTED_WIDTH 1
3383 /* The mask used to set the ALT_SDMMC_CMD_CCS_EXPECTED register field value. */
3384 #define ALT_SDMMC_CMD_CCS_EXPECTED_SET_MSK 0x00800000
3385 /* The mask used to clear the ALT_SDMMC_CMD_CCS_EXPECTED register field value. */
3386 #define ALT_SDMMC_CMD_CCS_EXPECTED_CLR_MSK 0xff7fffff
3387 /* The reset value of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */
3388 #define ALT_SDMMC_CMD_CCS_EXPECTED_RESET 0x0
3389 /* Extracts the ALT_SDMMC_CMD_CCS_EXPECTED field value from a register. */
3390 #define ALT_SDMMC_CMD_CCS_EXPECTED_GET(value) (((value) & 0x00800000) >> 23)
3391 /* Produces a ALT_SDMMC_CMD_CCS_EXPECTED register field value suitable for setting the register. */
3392 #define ALT_SDMMC_CMD_CCS_EXPECTED_SET(value) (((value) << 23) & 0x00800000)
3393 
3394 /*
3395  * Field : enable_boot
3396  *
3397  * Enable Bootthis bit should be set only for mandatory boot mode.
3398  *
3399  * When Software sets this bit along with start_cmd, CIU starts the boot sequence
3400  * for the corresponding card by asserting the CMD line low. Do NOT set
3401  * disable_boot and enable_boot together.
3402  *
3403  * Field Enumeration Values:
3404  *
3405  * Enum | Value | Description
3406  * :-----------------------------|:------|:-------------
3407  * ALT_SDMMC_CMD_EN_BOOT_E_DISD | 0x0 | Disable Boot
3408  * ALT_SDMMC_CMD_EN_BOOT_E_END | 0x1 | Enable Boot
3409  *
3410  * Field Access Macros:
3411  *
3412  */
3413 /*
3414  * Enumerated value for register field ALT_SDMMC_CMD_EN_BOOT
3415  *
3416  * Disable Boot
3417  */
3418 #define ALT_SDMMC_CMD_EN_BOOT_E_DISD 0x0
3419 /*
3420  * Enumerated value for register field ALT_SDMMC_CMD_EN_BOOT
3421  *
3422  * Enable Boot
3423  */
3424 #define ALT_SDMMC_CMD_EN_BOOT_E_END 0x1
3425 
3426 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_EN_BOOT register field. */
3427 #define ALT_SDMMC_CMD_EN_BOOT_LSB 24
3428 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_EN_BOOT register field. */
3429 #define ALT_SDMMC_CMD_EN_BOOT_MSB 24
3430 /* The width in bits of the ALT_SDMMC_CMD_EN_BOOT register field. */
3431 #define ALT_SDMMC_CMD_EN_BOOT_WIDTH 1
3432 /* The mask used to set the ALT_SDMMC_CMD_EN_BOOT register field value. */
3433 #define ALT_SDMMC_CMD_EN_BOOT_SET_MSK 0x01000000
3434 /* The mask used to clear the ALT_SDMMC_CMD_EN_BOOT register field value. */
3435 #define ALT_SDMMC_CMD_EN_BOOT_CLR_MSK 0xfeffffff
3436 /* The reset value of the ALT_SDMMC_CMD_EN_BOOT register field. */
3437 #define ALT_SDMMC_CMD_EN_BOOT_RESET 0x0
3438 /* Extracts the ALT_SDMMC_CMD_EN_BOOT field value from a register. */
3439 #define ALT_SDMMC_CMD_EN_BOOT_GET(value) (((value) & 0x01000000) >> 24)
3440 /* Produces a ALT_SDMMC_CMD_EN_BOOT register field value suitable for setting the register. */
3441 #define ALT_SDMMC_CMD_EN_BOOT_SET(value) (((value) << 24) & 0x01000000)
3442 
3443 /*
3444  * Field : expect_boot_ack
3445  *
3446  * Expect Boot Acknowledge. When Software sets this bit along with
3447  *
3448  * enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the
3449  * selected card.
3450  *
3451  * Field Enumeration Values:
3452  *
3453  * Enum | Value | Description
3454  * :------------------------------------------|:------|:----------------
3455  * ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_NOBOOTACK | 0x0 | No Boot ACK
3456  * ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_BOOTACK | 0x1 | Expect Boot ACK
3457  *
3458  * Field Access Macros:
3459  *
3460  */
3461 /*
3462  * Enumerated value for register field ALT_SDMMC_CMD_EXPECT_BOOT_ACK
3463  *
3464  * No Boot ACK
3465  */
3466 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_NOBOOTACK 0x0
3467 /*
3468  * Enumerated value for register field ALT_SDMMC_CMD_EXPECT_BOOT_ACK
3469  *
3470  * Expect Boot ACK
3471  */
3472 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_BOOTACK 0x1
3473 
3474 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */
3475 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_LSB 25
3476 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */
3477 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_MSB 25
3478 /* The width in bits of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */
3479 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_WIDTH 1
3480 /* The mask used to set the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value. */
3481 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET_MSK 0x02000000
3482 /* The mask used to clear the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value. */
3483 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_CLR_MSK 0xfdffffff
3484 /* The reset value of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */
3485 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_RESET 0x0
3486 /* Extracts the ALT_SDMMC_CMD_EXPECT_BOOT_ACK field value from a register. */
3487 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_GET(value) (((value) & 0x02000000) >> 25)
3488 /* Produces a ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value suitable for setting the register. */
3489 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET(value) (((value) << 25) & 0x02000000)
3490 
3491 /*
3492  * Field : disable_boot
3493  *
3494  * Disable Boot. When software sets this bit along with start_cmd, CIU terminates
3495  * the boot operation. Do NOT set disable_boot and enable_boot together.
3496  *
3497  * Field Enumeration Values:
3498  *
3499  * Enum | Value | Description
3500  * :------------------------------------|:------|:--------------------
3501  * ALT_SDMMC_CMD_DIS_BOOT_E_NOTERMBOOT | 0x0 | Boot not Terminated
3502  * ALT_SDMMC_CMD_DIS_BOOT_E_TERMBOOT | 0x1 | Terminate Boot
3503  *
3504  * Field Access Macros:
3505  *
3506  */
3507 /*
3508  * Enumerated value for register field ALT_SDMMC_CMD_DIS_BOOT
3509  *
3510  * Boot not Terminated
3511  */
3512 #define ALT_SDMMC_CMD_DIS_BOOT_E_NOTERMBOOT 0x0
3513 /*
3514  * Enumerated value for register field ALT_SDMMC_CMD_DIS_BOOT
3515  *
3516  * Terminate Boot
3517  */
3518 #define ALT_SDMMC_CMD_DIS_BOOT_E_TERMBOOT 0x1
3519 
3520 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_DIS_BOOT register field. */
3521 #define ALT_SDMMC_CMD_DIS_BOOT_LSB 26
3522 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_DIS_BOOT register field. */
3523 #define ALT_SDMMC_CMD_DIS_BOOT_MSB 26
3524 /* The width in bits of the ALT_SDMMC_CMD_DIS_BOOT register field. */
3525 #define ALT_SDMMC_CMD_DIS_BOOT_WIDTH 1
3526 /* The mask used to set the ALT_SDMMC_CMD_DIS_BOOT register field value. */
3527 #define ALT_SDMMC_CMD_DIS_BOOT_SET_MSK 0x04000000
3528 /* The mask used to clear the ALT_SDMMC_CMD_DIS_BOOT register field value. */
3529 #define ALT_SDMMC_CMD_DIS_BOOT_CLR_MSK 0xfbffffff
3530 /* The reset value of the ALT_SDMMC_CMD_DIS_BOOT register field. */
3531 #define ALT_SDMMC_CMD_DIS_BOOT_RESET 0x0
3532 /* Extracts the ALT_SDMMC_CMD_DIS_BOOT field value from a register. */
3533 #define ALT_SDMMC_CMD_DIS_BOOT_GET(value) (((value) & 0x04000000) >> 26)
3534 /* Produces a ALT_SDMMC_CMD_DIS_BOOT register field value suitable for setting the register. */
3535 #define ALT_SDMMC_CMD_DIS_BOOT_SET(value) (((value) << 26) & 0x04000000)
3536 
3537 /*
3538  * Field : boot_mode
3539  *
3540  * Boot Mode
3541  *
3542  * 0 - Mandatory Boot operation
3543  *
3544  * 1 - Alternate Boot operation
3545  *
3546  * Field Enumeration Values:
3547  *
3548  * Enum | Value | Description
3549  * :-----------------------------------|:------|:-------------------------
3550  * ALT_SDMMC_CMD_BOOT_MOD_E_MANDATORY | 0x0 | Mandatory Boot Operation
3551  * ALT_SDMMC_CMD_BOOT_MOD_E_ALTERNATE | 0x1 | Alternate Boot Operation
3552  *
3553  * Field Access Macros:
3554  *
3555  */
3556 /*
3557  * Enumerated value for register field ALT_SDMMC_CMD_BOOT_MOD
3558  *
3559  * Mandatory Boot Operation
3560  */
3561 #define ALT_SDMMC_CMD_BOOT_MOD_E_MANDATORY 0x0
3562 /*
3563  * Enumerated value for register field ALT_SDMMC_CMD_BOOT_MOD
3564  *
3565  * Alternate Boot Operation
3566  */
3567 #define ALT_SDMMC_CMD_BOOT_MOD_E_ALTERNATE 0x1
3568 
3569 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_BOOT_MOD register field. */
3570 #define ALT_SDMMC_CMD_BOOT_MOD_LSB 27
3571 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_BOOT_MOD register field. */
3572 #define ALT_SDMMC_CMD_BOOT_MOD_MSB 27
3573 /* The width in bits of the ALT_SDMMC_CMD_BOOT_MOD register field. */
3574 #define ALT_SDMMC_CMD_BOOT_MOD_WIDTH 1
3575 /* The mask used to set the ALT_SDMMC_CMD_BOOT_MOD register field value. */
3576 #define ALT_SDMMC_CMD_BOOT_MOD_SET_MSK 0x08000000
3577 /* The mask used to clear the ALT_SDMMC_CMD_BOOT_MOD register field value. */
3578 #define ALT_SDMMC_CMD_BOOT_MOD_CLR_MSK 0xf7ffffff
3579 /* The reset value of the ALT_SDMMC_CMD_BOOT_MOD register field. */
3580 #define ALT_SDMMC_CMD_BOOT_MOD_RESET 0x0
3581 /* Extracts the ALT_SDMMC_CMD_BOOT_MOD field value from a register. */
3582 #define ALT_SDMMC_CMD_BOOT_MOD_GET(value) (((value) & 0x08000000) >> 27)
3583 /* Produces a ALT_SDMMC_CMD_BOOT_MOD register field value suitable for setting the register. */
3584 #define ALT_SDMMC_CMD_BOOT_MOD_SET(value) (((value) << 27) & 0x08000000)
3585 
3586 /*
3587  * Field : volt_switch
3588  *
3589  * Voltage switch bit
3590  *
3591  * 0 - No voltage switching
3592  *
3593  * 1 - Voltage switching enabled; must be set for CMD11 only
3594  *
3595  * Field Enumeration Values:
3596  *
3597  * Enum | Value | Description
3598  * :-------------------------------------|:------|:-------------------------------
3599  * ALT_SDMMC_CMD_VOLT_SWITCH_E_NOVOLTSW | 0x0 | No voltage switching - default
3600  * ALT_SDMMC_CMD_VOLT_SWITCH_E_VOLTSW | 0x1 | Voltage switching enabled
3601  *
3602  * Field Access Macros:
3603  *
3604  */
3605 /*
3606  * Enumerated value for register field ALT_SDMMC_CMD_VOLT_SWITCH
3607  *
3608  * No voltage switching - default
3609  */
3610 #define ALT_SDMMC_CMD_VOLT_SWITCH_E_NOVOLTSW 0x0
3611 /*
3612  * Enumerated value for register field ALT_SDMMC_CMD_VOLT_SWITCH
3613  *
3614  * Voltage switching enabled
3615  */
3616 #define ALT_SDMMC_CMD_VOLT_SWITCH_E_VOLTSW 0x1
3617 
3618 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */
3619 #define ALT_SDMMC_CMD_VOLT_SWITCH_LSB 28
3620 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */
3621 #define ALT_SDMMC_CMD_VOLT_SWITCH_MSB 28
3622 /* The width in bits of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */
3623 #define ALT_SDMMC_CMD_VOLT_SWITCH_WIDTH 1
3624 /* The mask used to set the ALT_SDMMC_CMD_VOLT_SWITCH register field value. */
3625 #define ALT_SDMMC_CMD_VOLT_SWITCH_SET_MSK 0x10000000
3626 /* The mask used to clear the ALT_SDMMC_CMD_VOLT_SWITCH register field value. */
3627 #define ALT_SDMMC_CMD_VOLT_SWITCH_CLR_MSK 0xefffffff
3628 /* The reset value of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */
3629 #define ALT_SDMMC_CMD_VOLT_SWITCH_RESET 0x0
3630 /* Extracts the ALT_SDMMC_CMD_VOLT_SWITCH field value from a register. */
3631 #define ALT_SDMMC_CMD_VOLT_SWITCH_GET(value) (((value) & 0x10000000) >> 28)
3632 /* Produces a ALT_SDMMC_CMD_VOLT_SWITCH register field value suitable for setting the register. */
3633 #define ALT_SDMMC_CMD_VOLT_SWITCH_SET(value) (((value) << 28) & 0x10000000)
3634 
3635 /*
3636  * Field : use_hold_reg
3637  *
3638  * Use Hold Register
3639  *
3640  * 0 - CMD and DATA sent to card bypassing HOLD Register
3641  *
3642  * 1 - CMD and DATA sent to card through the HOLD Register
3643  *
3644  * Field Enumeration Values:
3645  *
3646  * Enum | Value | Description
3647  * :--------------------------------------|:------|:-------------------------------------------
3648  * ALT_SDMMC_CMD_USE_HOLD_REG_E_BYPASS | 0x0 | CMD and DATA sent to card bypassing HOLD
3649  * : | | Register
3650  * ALT_SDMMC_CMD_USE_HOLD_REG_E_NOBYPASS | 0x1 | CMD and DATA sent to card through the HOLD
3651  * : | | Register
3652  *
3653  * Field Access Macros:
3654  *
3655  */
3656 /*
3657  * Enumerated value for register field ALT_SDMMC_CMD_USE_HOLD_REG
3658  *
3659  * CMD and DATA sent to card bypassing HOLD Register
3660  */
3661 #define ALT_SDMMC_CMD_USE_HOLD_REG_E_BYPASS 0x0
3662 /*
3663  * Enumerated value for register field ALT_SDMMC_CMD_USE_HOLD_REG
3664  *
3665  * CMD and DATA sent to card through the HOLD Register
3666  */
3667 #define ALT_SDMMC_CMD_USE_HOLD_REG_E_NOBYPASS 0x1
3668 
3669 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */
3670 #define ALT_SDMMC_CMD_USE_HOLD_REG_LSB 29
3671 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */
3672 #define ALT_SDMMC_CMD_USE_HOLD_REG_MSB 29
3673 /* The width in bits of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */
3674 #define ALT_SDMMC_CMD_USE_HOLD_REG_WIDTH 1
3675 /* The mask used to set the ALT_SDMMC_CMD_USE_HOLD_REG register field value. */
3676 #define ALT_SDMMC_CMD_USE_HOLD_REG_SET_MSK 0x20000000
3677 /* The mask used to clear the ALT_SDMMC_CMD_USE_HOLD_REG register field value. */
3678 #define ALT_SDMMC_CMD_USE_HOLD_REG_CLR_MSK 0xdfffffff
3679 /* The reset value of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */
3680 #define ALT_SDMMC_CMD_USE_HOLD_REG_RESET 0x1
3681 /* Extracts the ALT_SDMMC_CMD_USE_HOLD_REG field value from a register. */
3682 #define ALT_SDMMC_CMD_USE_HOLD_REG_GET(value) (((value) & 0x20000000) >> 29)
3683 /* Produces a ALT_SDMMC_CMD_USE_HOLD_REG register field value suitable for setting the register. */
3684 #define ALT_SDMMC_CMD_USE_HOLD_REG_SET(value) (((value) << 29) & 0x20000000)
3685 
3686 /*
3687  * Field : start_cmd
3688  *
3689  * Start command. Once command is taken by CIU, bit is cleared.
3690  *
3691  * When bit is set, host should not attempt to write to any command registers. If
3692  * write is attempted, hardware lock error is set in raw interrupt register.
3693  *
3694  * Once command is sent and response is received from SD_MMC_CEATA cards, Command
3695  * Done bit is set in raw interrupt
3696  *
3697  * register.
3698  *
3699  * Field Enumeration Values:
3700  *
3701  * Enum | Value | Description
3702  * :----------------------------------|:------|:-----------------
3703  * ALT_SDMMC_CMD_START_CMD_E_NOSTART | 0x0 | No Start Cmd
3704  * ALT_SDMMC_CMD_START_CMD_E_START | 0x1 | Start Cmd Issued
3705  *
3706  * Field Access Macros:
3707  *
3708  */
3709 /*
3710  * Enumerated value for register field ALT_SDMMC_CMD_START_CMD
3711  *
3712  * No Start Cmd
3713  */
3714 #define ALT_SDMMC_CMD_START_CMD_E_NOSTART 0x0
3715 /*
3716  * Enumerated value for register field ALT_SDMMC_CMD_START_CMD
3717  *
3718  * Start Cmd Issued
3719  */
3720 #define ALT_SDMMC_CMD_START_CMD_E_START 0x1
3721 
3722 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_START_CMD register field. */
3723 #define ALT_SDMMC_CMD_START_CMD_LSB 31
3724 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_START_CMD register field. */
3725 #define ALT_SDMMC_CMD_START_CMD_MSB 31
3726 /* The width in bits of the ALT_SDMMC_CMD_START_CMD register field. */
3727 #define ALT_SDMMC_CMD_START_CMD_WIDTH 1
3728 /* The mask used to set the ALT_SDMMC_CMD_START_CMD register field value. */
3729 #define ALT_SDMMC_CMD_START_CMD_SET_MSK 0x80000000
3730 /* The mask used to clear the ALT_SDMMC_CMD_START_CMD register field value. */
3731 #define ALT_SDMMC_CMD_START_CMD_CLR_MSK 0x7fffffff
3732 /* The reset value of the ALT_SDMMC_CMD_START_CMD register field. */
3733 #define ALT_SDMMC_CMD_START_CMD_RESET 0x0
3734 /* Extracts the ALT_SDMMC_CMD_START_CMD field value from a register. */
3735 #define ALT_SDMMC_CMD_START_CMD_GET(value) (((value) & 0x80000000) >> 31)
3736 /* Produces a ALT_SDMMC_CMD_START_CMD register field value suitable for setting the register. */
3737 #define ALT_SDMMC_CMD_START_CMD_SET(value) (((value) << 31) & 0x80000000)
3738 
3739 #ifndef __ASSEMBLY__
3740 /*
3741  * WARNING: The C register and register group struct declarations are provided for
3742  * convenience and illustrative purposes. They should, however, be used with
3743  * caution as the C language standard provides no guarantees about the alignment or
3744  * atomicity of device memory accesses. The recommended practice for writing
3745  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3746  * alt_write_word() functions.
3747  *
3748  * The struct declaration for register ALT_SDMMC_CMD.
3749  */
3750 struct ALT_SDMMC_CMD_s
3751 {
3752  uint32_t cmd_index : 6; /* ALT_SDMMC_CMD_CMD_INDEX */
3753  uint32_t response_expect : 1; /* ALT_SDMMC_CMD_RESPONSE_EXPECT */
3754  uint32_t response_length : 1; /* ALT_SDMMC_CMD_RESPONSE_LEN */
3755  uint32_t check_response_crc : 1; /* ALT_SDMMC_CMD_CHECK_RESPONSE_CRC */
3756  uint32_t data_expected : 1; /* ALT_SDMMC_CMD_DATA_EXPECTED */
3757  uint32_t read_write : 1; /* ALT_SDMMC_CMD_RD_WR */
3758  uint32_t transfer_mode : 1; /* ALT_SDMMC_CMD_TFR_MOD */
3759  uint32_t send_auto_stop : 1; /* ALT_SDMMC_CMD_SEND_AUTO_STOP */
3760  uint32_t wait_prvdata_complete : 1; /* ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE */
3761  uint32_t stop_abort_cmd : 1; /* ALT_SDMMC_CMD_STOP_ABT_CMD */
3762  uint32_t send_initialization : 1; /* ALT_SDMMC_CMD_SEND_INITIALIZATION */
3763  uint32_t card_number : 5; /* ALT_SDMMC_CMD_CARD_NUMBER */
3764  uint32_t update_clock_registers_only : 1; /* ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY */
3765  uint32_t read_ceata_device : 1; /* ALT_SDMMC_CMD_RD_CEATA_DEVICE */
3766  uint32_t ccs_expected : 1; /* ALT_SDMMC_CMD_CCS_EXPECTED */
3767  uint32_t enable_boot : 1; /* ALT_SDMMC_CMD_EN_BOOT */
3768  uint32_t expect_boot_ack : 1; /* ALT_SDMMC_CMD_EXPECT_BOOT_ACK */
3769  uint32_t disable_boot : 1; /* ALT_SDMMC_CMD_DIS_BOOT */
3770  uint32_t boot_mode : 1; /* ALT_SDMMC_CMD_BOOT_MOD */
3771  uint32_t volt_switch : 1; /* ALT_SDMMC_CMD_VOLT_SWITCH */
3772  uint32_t use_hold_reg : 1; /* ALT_SDMMC_CMD_USE_HOLD_REG */
3773  uint32_t : 1; /* *UNDEFINED* */
3774  uint32_t start_cmd : 1; /* ALT_SDMMC_CMD_START_CMD */
3775 };
3776 
3777 /* The typedef declaration for register ALT_SDMMC_CMD. */
3778 typedef volatile struct ALT_SDMMC_CMD_s ALT_SDMMC_CMD_t;
3779 #endif /* __ASSEMBLY__ */
3780 
3781 /* The reset value of the ALT_SDMMC_CMD register. */
3782 #define ALT_SDMMC_CMD_RESET 0x20000000
3783 /* The byte offset of the ALT_SDMMC_CMD register from the beginning of the component. */
3784 #define ALT_SDMMC_CMD_OFST 0x2c
3785 
3786 /*
3787  * Register : resp0
3788  *
3789  * Response Register 0
3790  *
3791  * Register Layout
3792  *
3793  * Bits | Access | Reset | Description
3794  * :-------|:-------|:------|:--------------------------
3795  * [31:0] | R | 0x0 | ALT_SDMMC_RESP0_RESPONSE0
3796  *
3797  */
3798 /*
3799  * Field : response0
3800  *
3801  * Bit[31:0] of response
3802  *
3803  * Field Access Macros:
3804  *
3805  */
3806 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP0_RESPONSE0 register field. */
3807 #define ALT_SDMMC_RESP0_RESPONSE0_LSB 0
3808 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP0_RESPONSE0 register field. */
3809 #define ALT_SDMMC_RESP0_RESPONSE0_MSB 31
3810 /* The width in bits of the ALT_SDMMC_RESP0_RESPONSE0 register field. */
3811 #define ALT_SDMMC_RESP0_RESPONSE0_WIDTH 32
3812 /* The mask used to set the ALT_SDMMC_RESP0_RESPONSE0 register field value. */
3813 #define ALT_SDMMC_RESP0_RESPONSE0_SET_MSK 0xffffffff
3814 /* The mask used to clear the ALT_SDMMC_RESP0_RESPONSE0 register field value. */
3815 #define ALT_SDMMC_RESP0_RESPONSE0_CLR_MSK 0x00000000
3816 /* The reset value of the ALT_SDMMC_RESP0_RESPONSE0 register field. */
3817 #define ALT_SDMMC_RESP0_RESPONSE0_RESET 0x0
3818 /* Extracts the ALT_SDMMC_RESP0_RESPONSE0 field value from a register. */
3819 #define ALT_SDMMC_RESP0_RESPONSE0_GET(value) (((value) & 0xffffffff) >> 0)
3820 /* Produces a ALT_SDMMC_RESP0_RESPONSE0 register field value suitable for setting the register. */
3821 #define ALT_SDMMC_RESP0_RESPONSE0_SET(value) (((value) << 0) & 0xffffffff)
3822 
3823 #ifndef __ASSEMBLY__
3824 /*
3825  * WARNING: The C register and register group struct declarations are provided for
3826  * convenience and illustrative purposes. They should, however, be used with
3827  * caution as the C language standard provides no guarantees about the alignment or
3828  * atomicity of device memory accesses. The recommended practice for writing
3829  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3830  * alt_write_word() functions.
3831  *
3832  * The struct declaration for register ALT_SDMMC_RESP0.
3833  */
3834 struct ALT_SDMMC_RESP0_s
3835 {
3836  const uint32_t response0 : 32; /* ALT_SDMMC_RESP0_RESPONSE0 */
3837 };
3838 
3839 /* The typedef declaration for register ALT_SDMMC_RESP0. */
3840 typedef volatile struct ALT_SDMMC_RESP0_s ALT_SDMMC_RESP0_t;
3841 #endif /* __ASSEMBLY__ */
3842 
3843 /* The reset value of the ALT_SDMMC_RESP0 register. */
3844 #define ALT_SDMMC_RESP0_RESET 0x00000000
3845 /* The byte offset of the ALT_SDMMC_RESP0 register from the beginning of the component. */
3846 #define ALT_SDMMC_RESP0_OFST 0x30
3847 
3848 /*
3849  * Register : resp1
3850  *
3851  * Response Register 1
3852  *
3853  * Register Layout
3854  *
3855  * Bits | Access | Reset | Description
3856  * :-------|:-------|:------|:--------------------------
3857  * [31:0] | R | 0x0 | ALT_SDMMC_RESP1_RESPONSE1
3858  *
3859  */
3860 /*
3861  * Field : response1
3862  *
3863  * Register represents bit[63:32] of long response.
3864  *
3865  * When CIU sends auto-stop command, then response is saved in register. Response
3866  * for previous command sent by host is still preserved in Response 0 register.
3867  * Additional auto-stop issued only for data transfer commands, and response type
3868  * is always "short" for them.
3869  *
3870  * Field Access Macros:
3871  *
3872  */
3873 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP1_RESPONSE1 register field. */
3874 #define ALT_SDMMC_RESP1_RESPONSE1_LSB 0
3875 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP1_RESPONSE1 register field. */
3876 #define ALT_SDMMC_RESP1_RESPONSE1_MSB 31
3877 /* The width in bits of the ALT_SDMMC_RESP1_RESPONSE1 register field. */
3878 #define ALT_SDMMC_RESP1_RESPONSE1_WIDTH 32
3879 /* The mask used to set the ALT_SDMMC_RESP1_RESPONSE1 register field value. */
3880 #define ALT_SDMMC_RESP1_RESPONSE1_SET_MSK 0xffffffff
3881 /* The mask used to clear the ALT_SDMMC_RESP1_RESPONSE1 register field value. */
3882 #define ALT_SDMMC_RESP1_RESPONSE1_CLR_MSK 0x00000000
3883 /* The reset value of the ALT_SDMMC_RESP1_RESPONSE1 register field. */
3884 #define ALT_SDMMC_RESP1_RESPONSE1_RESET 0x0
3885 /* Extracts the ALT_SDMMC_RESP1_RESPONSE1 field value from a register. */
3886 #define ALT_SDMMC_RESP1_RESPONSE1_GET(value) (((value) & 0xffffffff) >> 0)
3887 /* Produces a ALT_SDMMC_RESP1_RESPONSE1 register field value suitable for setting the register. */
3888 #define ALT_SDMMC_RESP1_RESPONSE1_SET(value) (((value) << 0) & 0xffffffff)
3889 
3890 #ifndef __ASSEMBLY__
3891 /*
3892  * WARNING: The C register and register group struct declarations are provided for
3893  * convenience and illustrative purposes. They should, however, be used with
3894  * caution as the C language standard provides no guarantees about the alignment or
3895  * atomicity of device memory accesses. The recommended practice for writing
3896  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3897  * alt_write_word() functions.
3898  *
3899  * The struct declaration for register ALT_SDMMC_RESP1.
3900  */
3901 struct ALT_SDMMC_RESP1_s
3902 {
3903  const uint32_t response1 : 32; /* ALT_SDMMC_RESP1_RESPONSE1 */
3904 };
3905 
3906 /* The typedef declaration for register ALT_SDMMC_RESP1. */
3907 typedef volatile struct ALT_SDMMC_RESP1_s ALT_SDMMC_RESP1_t;
3908 #endif /* __ASSEMBLY__ */
3909 
3910 /* The reset value of the ALT_SDMMC_RESP1 register. */
3911 #define ALT_SDMMC_RESP1_RESET 0x00000000
3912 /* The byte offset of the ALT_SDMMC_RESP1 register from the beginning of the component. */
3913 #define ALT_SDMMC_RESP1_OFST 0x34
3914 
3915 /*
3916  * Register : resp2
3917  *
3918  * Response Register 2
3919  *
3920  * Register Layout
3921  *
3922  * Bits | Access | Reset | Description
3923  * :-------|:-------|:------|:--------------------------
3924  * [31:0] | R | 0x0 | ALT_SDMMC_RESP2_RESPONSE2
3925  *
3926  */
3927 /*
3928  * Field : response2
3929  *
3930  * Bit[95:64] of long response
3931  *
3932  * Field Access Macros:
3933  *
3934  */
3935 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP2_RESPONSE2 register field. */
3936 #define ALT_SDMMC_RESP2_RESPONSE2_LSB 0
3937 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP2_RESPONSE2 register field. */
3938 #define ALT_SDMMC_RESP2_RESPONSE2_MSB 31
3939 /* The width in bits of the ALT_SDMMC_RESP2_RESPONSE2 register field. */
3940 #define ALT_SDMMC_RESP2_RESPONSE2_WIDTH 32
3941 /* The mask used to set the ALT_SDMMC_RESP2_RESPONSE2 register field value. */
3942 #define ALT_SDMMC_RESP2_RESPONSE2_SET_MSK 0xffffffff
3943 /* The mask used to clear the ALT_SDMMC_RESP2_RESPONSE2 register field value. */
3944 #define ALT_SDMMC_RESP2_RESPONSE2_CLR_MSK 0x00000000
3945 /* The reset value of the ALT_SDMMC_RESP2_RESPONSE2 register field. */
3946 #define ALT_SDMMC_RESP2_RESPONSE2_RESET 0x0
3947 /* Extracts the ALT_SDMMC_RESP2_RESPONSE2 field value from a register. */
3948 #define ALT_SDMMC_RESP2_RESPONSE2_GET(value) (((value) & 0xffffffff) >> 0)
3949 /* Produces a ALT_SDMMC_RESP2_RESPONSE2 register field value suitable for setting the register. */
3950 #define ALT_SDMMC_RESP2_RESPONSE2_SET(value) (((value) << 0) & 0xffffffff)
3951 
3952 #ifndef __ASSEMBLY__
3953 /*
3954  * WARNING: The C register and register group struct declarations are provided for
3955  * convenience and illustrative purposes. They should, however, be used with
3956  * caution as the C language standard provides no guarantees about the alignment or
3957  * atomicity of device memory accesses. The recommended practice for writing
3958  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3959  * alt_write_word() functions.
3960  *
3961  * The struct declaration for register ALT_SDMMC_RESP2.
3962  */
3963 struct ALT_SDMMC_RESP2_s
3964 {
3965  const uint32_t response2 : 32; /* ALT_SDMMC_RESP2_RESPONSE2 */
3966 };
3967 
3968 /* The typedef declaration for register ALT_SDMMC_RESP2. */
3969 typedef volatile struct ALT_SDMMC_RESP2_s ALT_SDMMC_RESP2_t;
3970 #endif /* __ASSEMBLY__ */
3971 
3972 /* The reset value of the ALT_SDMMC_RESP2 register. */
3973 #define ALT_SDMMC_RESP2_RESET 0x00000000
3974 /* The byte offset of the ALT_SDMMC_RESP2 register from the beginning of the component. */
3975 #define ALT_SDMMC_RESP2_OFST 0x38
3976 
3977 /*
3978  * Register : resp3
3979  *
3980  * Response Register 3
3981  *
3982  * Register Layout
3983  *
3984  * Bits | Access | Reset | Description
3985  * :-------|:-------|:------|:--------------------------
3986  * [31:0] | R | 0x0 | ALT_SDMMC_RESP3_RESPONSE3
3987  *
3988  */
3989 /*
3990  * Field : response3
3991  *
3992  * Bit[127:96] of long response
3993  *
3994  * Field Access Macros:
3995  *
3996  */
3997 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP3_RESPONSE3 register field. */
3998 #define ALT_SDMMC_RESP3_RESPONSE3_LSB 0
3999 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP3_RESPONSE3 register field. */
4000 #define ALT_SDMMC_RESP3_RESPONSE3_MSB 31
4001 /* The width in bits of the ALT_SDMMC_RESP3_RESPONSE3 register field. */
4002 #define ALT_SDMMC_RESP3_RESPONSE3_WIDTH 32
4003 /* The mask used to set the ALT_SDMMC_RESP3_RESPONSE3 register field value. */
4004 #define ALT_SDMMC_RESP3_RESPONSE3_SET_MSK 0xffffffff
4005 /* The mask used to clear the ALT_SDMMC_RESP3_RESPONSE3 register field value. */
4006 #define ALT_SDMMC_RESP3_RESPONSE3_CLR_MSK 0x00000000
4007 /* The reset value of the ALT_SDMMC_RESP3_RESPONSE3 register field. */
4008 #define ALT_SDMMC_RESP3_RESPONSE3_RESET 0x0
4009 /* Extracts the ALT_SDMMC_RESP3_RESPONSE3 field value from a register. */
4010 #define ALT_SDMMC_RESP3_RESPONSE3_GET(value) (((value) & 0xffffffff) >> 0)
4011 /* Produces a ALT_SDMMC_RESP3_RESPONSE3 register field value suitable for setting the register. */
4012 #define ALT_SDMMC_RESP3_RESPONSE3_SET(value) (((value) << 0) & 0xffffffff)
4013 
4014 #ifndef __ASSEMBLY__
4015 /*
4016  * WARNING: The C register and register group struct declarations are provided for
4017  * convenience and illustrative purposes. They should, however, be used with
4018  * caution as the C language standard provides no guarantees about the alignment or
4019  * atomicity of device memory accesses. The recommended practice for writing
4020  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4021  * alt_write_word() functions.
4022  *
4023  * The struct declaration for register ALT_SDMMC_RESP3.
4024  */
4025 struct ALT_SDMMC_RESP3_s
4026 {
4027  const uint32_t response3 : 32; /* ALT_SDMMC_RESP3_RESPONSE3 */
4028 };
4029 
4030 /* The typedef declaration for register ALT_SDMMC_RESP3. */
4031 typedef volatile struct ALT_SDMMC_RESP3_s ALT_SDMMC_RESP3_t;
4032 #endif /* __ASSEMBLY__ */
4033 
4034 /* The reset value of the ALT_SDMMC_RESP3 register. */
4035 #define ALT_SDMMC_RESP3_RESET 0x00000000
4036 /* The byte offset of the ALT_SDMMC_RESP3 register from the beginning of the component. */
4037 #define ALT_SDMMC_RESP3_OFST 0x3c
4038 
4039 /*
4040  * Register : mintsts
4041  *
4042  * Masked Interrupt Status Register
4043  *
4044  * Register Layout
4045  *
4046  * Bits | Access | Reset | Description
4047  * :--------|:-------|:------|:-----------------------------
4048  * [0] | R | 0x0 | Card Detect
4049  * [1] | R | 0x0 | Response Error
4050  * [2] | R | 0x0 | Command Done
4051  * [3] | R | 0x0 | Data Transfer Over
4052  * [4] | R | 0x0 | Data TX FIFO Data Request
4053  * [5] | R | 0x0 | Receive FIFO Data Request
4054  * [6] | R | 0x0 | Response CRC Error
4055  * [7] | R | 0x0 | Data CRC Error
4056  * [8] | R | 0x0 | Response Timeout
4057  * [9] | R | 0x0 | Data Read Timeout
4058  * [10] | R | 0x0 | Data Starvation Host Timeout
4059  * [11] | R | 0x0 | FIFO Underrun Overrun Error
4060  * [12] | R | 0x0 | Hardware Locked Write Error
4061  * [13] | R | 0x0 | Start-bit Error
4062  * [14] | R | 0x0 | Auto Command Done
4063  * [15] | R | 0x0 | End-bit Error
4064  * [31:16] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INT
4065  *
4066  */
4067 /*
4068  * Field : Card Detect - cd
4069  *
4070  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4071  *
4072  * Field Enumeration Values:
4073  *
4074  * Enum | Value | Description
4075  * :-----------------------------|:------|:----------------------
4076  * ALT_SDMMC_MINTSTS_CD_E_MSK | 0x0 | Card Detected Mask
4077  * ALT_SDMMC_MINTSTS_CD_E_NOMSK | 0x1 | Card Detected No Mask
4078  *
4079  * Field Access Macros:
4080  *
4081  */
4082 /*
4083  * Enumerated value for register field ALT_SDMMC_MINTSTS_CD
4084  *
4085  * Card Detected Mask
4086  */
4087 #define ALT_SDMMC_MINTSTS_CD_E_MSK 0x0
4088 /*
4089  * Enumerated value for register field ALT_SDMMC_MINTSTS_CD
4090  *
4091  * Card Detected No Mask
4092  */
4093 #define ALT_SDMMC_MINTSTS_CD_E_NOMSK 0x1
4094 
4095 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_CD register field. */
4096 #define ALT_SDMMC_MINTSTS_CD_LSB 0
4097 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_CD register field. */
4098 #define ALT_SDMMC_MINTSTS_CD_MSB 0
4099 /* The width in bits of the ALT_SDMMC_MINTSTS_CD register field. */
4100 #define ALT_SDMMC_MINTSTS_CD_WIDTH 1
4101 /* The mask used to set the ALT_SDMMC_MINTSTS_CD register field value. */
4102 #define ALT_SDMMC_MINTSTS_CD_SET_MSK 0x00000001
4103 /* The mask used to clear the ALT_SDMMC_MINTSTS_CD register field value. */
4104 #define ALT_SDMMC_MINTSTS_CD_CLR_MSK 0xfffffffe
4105 /* The reset value of the ALT_SDMMC_MINTSTS_CD register field. */
4106 #define ALT_SDMMC_MINTSTS_CD_RESET 0x0
4107 /* Extracts the ALT_SDMMC_MINTSTS_CD field value from a register. */
4108 #define ALT_SDMMC_MINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0)
4109 /* Produces a ALT_SDMMC_MINTSTS_CD register field value suitable for setting the register. */
4110 #define ALT_SDMMC_MINTSTS_CD_SET(value) (((value) << 0) & 0x00000001)
4111 
4112 /*
4113  * Field : Response Error - resp
4114  *
4115  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4116  *
4117  * Field Enumeration Values:
4118  *
4119  * Enum | Value | Description
4120  * :-------------------------------|:------|:-----------------------
4121  * ALT_SDMMC_MINTSTS_RESP_E_MSK | 0x0 | Response error Mask
4122  * ALT_SDMMC_MINTSTS_RESP_E_NOMSK | 0x1 | Response error No Mask
4123  *
4124  * Field Access Macros:
4125  *
4126  */
4127 /*
4128  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESP
4129  *
4130  * Response error Mask
4131  */
4132 #define ALT_SDMMC_MINTSTS_RESP_E_MSK 0x0
4133 /*
4134  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESP
4135  *
4136  * Response error No Mask
4137  */
4138 #define ALT_SDMMC_MINTSTS_RESP_E_NOMSK 0x1
4139 
4140 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESP register field. */
4141 #define ALT_SDMMC_MINTSTS_RESP_LSB 1
4142 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESP register field. */
4143 #define ALT_SDMMC_MINTSTS_RESP_MSB 1
4144 /* The width in bits of the ALT_SDMMC_MINTSTS_RESP register field. */
4145 #define ALT_SDMMC_MINTSTS_RESP_WIDTH 1
4146 /* The mask used to set the ALT_SDMMC_MINTSTS_RESP register field value. */
4147 #define ALT_SDMMC_MINTSTS_RESP_SET_MSK 0x00000002
4148 /* The mask used to clear the ALT_SDMMC_MINTSTS_RESP register field value. */
4149 #define ALT_SDMMC_MINTSTS_RESP_CLR_MSK 0xfffffffd
4150 /* The reset value of the ALT_SDMMC_MINTSTS_RESP register field. */
4151 #define ALT_SDMMC_MINTSTS_RESP_RESET 0x0
4152 /* Extracts the ALT_SDMMC_MINTSTS_RESP field value from a register. */
4153 #define ALT_SDMMC_MINTSTS_RESP_GET(value) (((value) & 0x00000002) >> 1)
4154 /* Produces a ALT_SDMMC_MINTSTS_RESP register field value suitable for setting the register. */
4155 #define ALT_SDMMC_MINTSTS_RESP_SET(value) (((value) << 1) & 0x00000002)
4156 
4157 /*
4158  * Field : Command Done - cmd_done
4159  *
4160  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4161  *
4162  * Field Enumeration Values:
4163  *
4164  * Enum | Value | Description
4165  * :-----------------------------------|:------|:---------------------
4166  * ALT_SDMMC_MINTSTS_CMD_DONE_E_MSK | 0x0 | Command Done Mask
4167  * ALT_SDMMC_MINTSTS_CMD_DONE_E_NOMSK | 0x1 | Command Done No Mask
4168  *
4169  * Field Access Macros:
4170  *
4171  */
4172 /*
4173  * Enumerated value for register field ALT_SDMMC_MINTSTS_CMD_DONE
4174  *
4175  * Command Done Mask
4176  */
4177 #define ALT_SDMMC_MINTSTS_CMD_DONE_E_MSK 0x0
4178 /*
4179  * Enumerated value for register field ALT_SDMMC_MINTSTS_CMD_DONE
4180  *
4181  * Command Done No Mask
4182  */
4183 #define ALT_SDMMC_MINTSTS_CMD_DONE_E_NOMSK 0x1
4184 
4185 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_CMD_DONE register field. */
4186 #define ALT_SDMMC_MINTSTS_CMD_DONE_LSB 2
4187 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_CMD_DONE register field. */
4188 #define ALT_SDMMC_MINTSTS_CMD_DONE_MSB 2
4189 /* The width in bits of the ALT_SDMMC_MINTSTS_CMD_DONE register field. */
4190 #define ALT_SDMMC_MINTSTS_CMD_DONE_WIDTH 1
4191 /* The mask used to set the ALT_SDMMC_MINTSTS_CMD_DONE register field value. */
4192 #define ALT_SDMMC_MINTSTS_CMD_DONE_SET_MSK 0x00000004
4193 /* The mask used to clear the ALT_SDMMC_MINTSTS_CMD_DONE register field value. */
4194 #define ALT_SDMMC_MINTSTS_CMD_DONE_CLR_MSK 0xfffffffb
4195 /* The reset value of the ALT_SDMMC_MINTSTS_CMD_DONE register field. */
4196 #define ALT_SDMMC_MINTSTS_CMD_DONE_RESET 0x0
4197 /* Extracts the ALT_SDMMC_MINTSTS_CMD_DONE field value from a register. */
4198 #define ALT_SDMMC_MINTSTS_CMD_DONE_GET(value) (((value) & 0x00000004) >> 2)
4199 /* Produces a ALT_SDMMC_MINTSTS_CMD_DONE register field value suitable for setting the register. */
4200 #define ALT_SDMMC_MINTSTS_CMD_DONE_SET(value) (((value) << 2) & 0x00000004)
4201 
4202 /*
4203  * Field : Data Transfer Over - dt
4204  *
4205  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4206  *
4207  * Field Enumeration Values:
4208  *
4209  * Enum | Value | Description
4210  * :-----------------------------|:------|:---------------------------
4211  * ALT_SDMMC_MINTSTS_DT_E_MSK | 0x0 | Data transfer over Mask
4212  * ALT_SDMMC_MINTSTS_DT_E_NOMSK | 0x1 | Data transfer over No Mask
4213  *
4214  * Field Access Macros:
4215  *
4216  */
4217 /*
4218  * Enumerated value for register field ALT_SDMMC_MINTSTS_DT
4219  *
4220  * Data transfer over Mask
4221  */
4222 #define ALT_SDMMC_MINTSTS_DT_E_MSK 0x0
4223 /*
4224  * Enumerated value for register field ALT_SDMMC_MINTSTS_DT
4225  *
4226  * Data transfer over No Mask
4227  */
4228 #define ALT_SDMMC_MINTSTS_DT_E_NOMSK 0x1
4229 
4230 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DT register field. */
4231 #define ALT_SDMMC_MINTSTS_DT_LSB 3
4232 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DT register field. */
4233 #define ALT_SDMMC_MINTSTS_DT_MSB 3
4234 /* The width in bits of the ALT_SDMMC_MINTSTS_DT register field. */
4235 #define ALT_SDMMC_MINTSTS_DT_WIDTH 1
4236 /* The mask used to set the ALT_SDMMC_MINTSTS_DT register field value. */
4237 #define ALT_SDMMC_MINTSTS_DT_SET_MSK 0x00000008
4238 /* The mask used to clear the ALT_SDMMC_MINTSTS_DT register field value. */
4239 #define ALT_SDMMC_MINTSTS_DT_CLR_MSK 0xfffffff7
4240 /* The reset value of the ALT_SDMMC_MINTSTS_DT register field. */
4241 #define ALT_SDMMC_MINTSTS_DT_RESET 0x0
4242 /* Extracts the ALT_SDMMC_MINTSTS_DT field value from a register. */
4243 #define ALT_SDMMC_MINTSTS_DT_GET(value) (((value) & 0x00000008) >> 3)
4244 /* Produces a ALT_SDMMC_MINTSTS_DT register field value suitable for setting the register. */
4245 #define ALT_SDMMC_MINTSTS_DT_SET(value) (((value) << 3) & 0x00000008)
4246 
4247 /*
4248  * Field : Data TX FIFO Data Request - dttxfifodr
4249  *
4250  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4251  *
4252  * Field Enumeration Values:
4253  *
4254  * Enum | Value | Description
4255  * :-------------------------------------|:------|:-----------------------------------
4256  * ALT_SDMMC_MINTSTS_DTTXFIFODR_E_MSK | 0x0 | Transmit FIFO data request Mask
4257  * ALT_SDMMC_MINTSTS_DTTXFIFODR_E_NOMSK | 0x1 | Transmit FIFO data request No Mask
4258  *
4259  * Field Access Macros:
4260  *
4261  */
4262 /*
4263  * Enumerated value for register field ALT_SDMMC_MINTSTS_DTTXFIFODR
4264  *
4265  * Transmit FIFO data request Mask
4266  */
4267 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_MSK 0x0
4268 /*
4269  * Enumerated value for register field ALT_SDMMC_MINTSTS_DTTXFIFODR
4270  *
4271  * Transmit FIFO data request No Mask
4272  */
4273 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_NOMSK 0x1
4274 
4275 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field. */
4276 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_LSB 4
4277 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field. */
4278 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_MSB 4
4279 /* The width in bits of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field. */
4280 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_WIDTH 1
4281 /* The mask used to set the ALT_SDMMC_MINTSTS_DTTXFIFODR register field value. */
4282 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET_MSK 0x00000010
4283 /* The mask used to clear the ALT_SDMMC_MINTSTS_DTTXFIFODR register field value. */
4284 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_CLR_MSK 0xffffffef
4285 /* The reset value of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field. */
4286 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_RESET 0x0
4287 /* Extracts the ALT_SDMMC_MINTSTS_DTTXFIFODR field value from a register. */
4288 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_GET(value) (((value) & 0x00000010) >> 4)
4289 /* Produces a ALT_SDMMC_MINTSTS_DTTXFIFODR register field value suitable for setting the register. */
4290 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET(value) (((value) << 4) & 0x00000010)
4291 
4292 /*
4293  * Field : Receive FIFO Data Request - rxfifodr
4294  *
4295  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4296  *
4297  * Field Enumeration Values:
4298  *
4299  * Enum | Value | Description
4300  * :-----------------------------------|:------|:----------------------------------
4301  * ALT_SDMMC_MINTSTS_RXFIFODR_E_MSK | 0x0 | Receive FIFO data request Mask
4302  * ALT_SDMMC_MINTSTS_RXFIFODR_E_NOMSK | 0x1 | Receive FIFO data request No Mask
4303  *
4304  * Field Access Macros:
4305  *
4306  */
4307 /*
4308  * Enumerated value for register field ALT_SDMMC_MINTSTS_RXFIFODR
4309  *
4310  * Receive FIFO data request Mask
4311  */
4312 #define ALT_SDMMC_MINTSTS_RXFIFODR_E_MSK 0x0
4313 /*
4314  * Enumerated value for register field ALT_SDMMC_MINTSTS_RXFIFODR
4315  *
4316  * Receive FIFO data request No Mask
4317  */
4318 #define ALT_SDMMC_MINTSTS_RXFIFODR_E_NOMSK 0x1
4319 
4320 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RXFIFODR register field. */
4321 #define ALT_SDMMC_MINTSTS_RXFIFODR_LSB 5
4322 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RXFIFODR register field. */
4323 #define ALT_SDMMC_MINTSTS_RXFIFODR_MSB 5
4324 /* The width in bits of the ALT_SDMMC_MINTSTS_RXFIFODR register field. */
4325 #define ALT_SDMMC_MINTSTS_RXFIFODR_WIDTH 1
4326 /* The mask used to set the ALT_SDMMC_MINTSTS_RXFIFODR register field value. */
4327 #define ALT_SDMMC_MINTSTS_RXFIFODR_SET_MSK 0x00000020
4328 /* The mask used to clear the ALT_SDMMC_MINTSTS_RXFIFODR register field value. */
4329 #define ALT_SDMMC_MINTSTS_RXFIFODR_CLR_MSK 0xffffffdf
4330 /* The reset value of the ALT_SDMMC_MINTSTS_RXFIFODR register field. */
4331 #define ALT_SDMMC_MINTSTS_RXFIFODR_RESET 0x0
4332 /* Extracts the ALT_SDMMC_MINTSTS_RXFIFODR field value from a register. */
4333 #define ALT_SDMMC_MINTSTS_RXFIFODR_GET(value) (((value) & 0x00000020) >> 5)
4334 /* Produces a ALT_SDMMC_MINTSTS_RXFIFODR register field value suitable for setting the register. */
4335 #define ALT_SDMMC_MINTSTS_RXFIFODR_SET(value) (((value) << 5) & 0x00000020)
4336 
4337 /*
4338  * Field : Response CRC Error - respcrcerr
4339  *
4340  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4341  *
4342  * Field Enumeration Values:
4343  *
4344  * Enum | Value | Description
4345  * :-------------------------------------|:------|:---------------------------
4346  * ALT_SDMMC_MINTSTS_RESPCRCERR_E_MSK | 0x0 | Response CRC error Mask
4347  * ALT_SDMMC_MINTSTS_RESPCRCERR_E_NOMSK | 0x1 | Response CRC error No Mask
4348  *
4349  * Field Access Macros:
4350  *
4351  */
4352 /*
4353  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPCRCERR
4354  *
4355  * Response CRC error Mask
4356  */
4357 #define ALT_SDMMC_MINTSTS_RESPCRCERR_E_MSK 0x0
4358 /*
4359  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPCRCERR
4360  *
4361  * Response CRC error No Mask
4362  */
4363 #define ALT_SDMMC_MINTSTS_RESPCRCERR_E_NOMSK 0x1
4364 
4365 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESPCRCERR register field. */
4366 #define ALT_SDMMC_MINTSTS_RESPCRCERR_LSB 6
4367 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESPCRCERR register field. */
4368 #define ALT_SDMMC_MINTSTS_RESPCRCERR_MSB 6
4369 /* The width in bits of the ALT_SDMMC_MINTSTS_RESPCRCERR register field. */
4370 #define ALT_SDMMC_MINTSTS_RESPCRCERR_WIDTH 1
4371 /* The mask used to set the ALT_SDMMC_MINTSTS_RESPCRCERR register field value. */
4372 #define ALT_SDMMC_MINTSTS_RESPCRCERR_SET_MSK 0x00000040
4373 /* The mask used to clear the ALT_SDMMC_MINTSTS_RESPCRCERR register field value. */
4374 #define ALT_SDMMC_MINTSTS_RESPCRCERR_CLR_MSK 0xffffffbf
4375 /* The reset value of the ALT_SDMMC_MINTSTS_RESPCRCERR register field. */
4376 #define ALT_SDMMC_MINTSTS_RESPCRCERR_RESET 0x0
4377 /* Extracts the ALT_SDMMC_MINTSTS_RESPCRCERR field value from a register. */
4378 #define ALT_SDMMC_MINTSTS_RESPCRCERR_GET(value) (((value) & 0x00000040) >> 6)
4379 /* Produces a ALT_SDMMC_MINTSTS_RESPCRCERR register field value suitable for setting the register. */
4380 #define ALT_SDMMC_MINTSTS_RESPCRCERR_SET(value) (((value) << 6) & 0x00000040)
4381 
4382 /*
4383  * Field : Data CRC Error - datacrcerr
4384  *
4385  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4386  *
4387  * Field Enumeration Values:
4388  *
4389  * Enum | Value | Description
4390  * :-------------------------------------|:------|:-----------------------
4391  * ALT_SDMMC_MINTSTS_DATACRCERR_E_MSK | 0x0 | Data CRC error Mask
4392  * ALT_SDMMC_MINTSTS_DATACRCERR_E_NOMSK | 0x1 | Data CRC error No Mask
4393  *
4394  * Field Access Macros:
4395  *
4396  */
4397 /*
4398  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATACRCERR
4399  *
4400  * Data CRC error Mask
4401  */
4402 #define ALT_SDMMC_MINTSTS_DATACRCERR_E_MSK 0x0
4403 /*
4404  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATACRCERR
4405  *
4406  * Data CRC error No Mask
4407  */
4408 #define ALT_SDMMC_MINTSTS_DATACRCERR_E_NOMSK 0x1
4409 
4410 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DATACRCERR register field. */
4411 #define ALT_SDMMC_MINTSTS_DATACRCERR_LSB 7
4412 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DATACRCERR register field. */
4413 #define ALT_SDMMC_MINTSTS_DATACRCERR_MSB 7
4414 /* The width in bits of the ALT_SDMMC_MINTSTS_DATACRCERR register field. */
4415 #define ALT_SDMMC_MINTSTS_DATACRCERR_WIDTH 1
4416 /* The mask used to set the ALT_SDMMC_MINTSTS_DATACRCERR register field value. */
4417 #define ALT_SDMMC_MINTSTS_DATACRCERR_SET_MSK 0x00000080
4418 /* The mask used to clear the ALT_SDMMC_MINTSTS_DATACRCERR register field value. */
4419 #define ALT_SDMMC_MINTSTS_DATACRCERR_CLR_MSK 0xffffff7f
4420 /* The reset value of the ALT_SDMMC_MINTSTS_DATACRCERR register field. */
4421 #define ALT_SDMMC_MINTSTS_DATACRCERR_RESET 0x0
4422 /* Extracts the ALT_SDMMC_MINTSTS_DATACRCERR field value from a register. */
4423 #define ALT_SDMMC_MINTSTS_DATACRCERR_GET(value) (((value) & 0x00000080) >> 7)
4424 /* Produces a ALT_SDMMC_MINTSTS_DATACRCERR register field value suitable for setting the register. */
4425 #define ALT_SDMMC_MINTSTS_DATACRCERR_SET(value) (((value) << 7) & 0x00000080)
4426 
4427 /*
4428  * Field : Response Timeout - respto
4429  *
4430  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4431  *
4432  * Field Enumeration Values:
4433  *
4434  * Enum | Value | Description
4435  * :---------------------------------|:------|:-------------------------
4436  * ALT_SDMMC_MINTSTS_RESPTO_E_MSK | 0x0 | Response timeout Mask
4437  * ALT_SDMMC_MINTSTS_RESPTO_E_NOMSK | 0x1 | Response timeout No Mask
4438  *
4439  * Field Access Macros:
4440  *
4441  */
4442 /*
4443  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPTO
4444  *
4445  * Response timeout Mask
4446  */
4447 #define ALT_SDMMC_MINTSTS_RESPTO_E_MSK 0x0
4448 /*
4449  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPTO
4450  *
4451  * Response timeout No Mask
4452  */
4453 #define ALT_SDMMC_MINTSTS_RESPTO_E_NOMSK 0x1
4454 
4455 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESPTO register field. */
4456 #define ALT_SDMMC_MINTSTS_RESPTO_LSB 8
4457 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESPTO register field. */
4458 #define ALT_SDMMC_MINTSTS_RESPTO_MSB 8
4459 /* The width in bits of the ALT_SDMMC_MINTSTS_RESPTO register field. */
4460 #define ALT_SDMMC_MINTSTS_RESPTO_WIDTH 1
4461 /* The mask used to set the ALT_SDMMC_MINTSTS_RESPTO register field value. */
4462 #define ALT_SDMMC_MINTSTS_RESPTO_SET_MSK 0x00000100
4463 /* The mask used to clear the ALT_SDMMC_MINTSTS_RESPTO register field value. */
4464 #define ALT_SDMMC_MINTSTS_RESPTO_CLR_MSK 0xfffffeff
4465 /* The reset value of the ALT_SDMMC_MINTSTS_RESPTO register field. */
4466 #define ALT_SDMMC_MINTSTS_RESPTO_RESET 0x0
4467 /* Extracts the ALT_SDMMC_MINTSTS_RESPTO field value from a register. */
4468 #define ALT_SDMMC_MINTSTS_RESPTO_GET(value) (((value) & 0x00000100) >> 8)
4469 /* Produces a ALT_SDMMC_MINTSTS_RESPTO register field value suitable for setting the register. */
4470 #define ALT_SDMMC_MINTSTS_RESPTO_SET(value) (((value) << 8) & 0x00000100)
4471 
4472 /*
4473  * Field : Data Read Timeout - datardto
4474  *
4475  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4476  *
4477  * Field Enumeration Values:
4478  *
4479  * Enum | Value | Description
4480  * :-----------------------------------|:------|:--------------------------
4481  * ALT_SDMMC_MINTSTS_DATARDTO_E_MSK | 0x0 | Data read timeout Mask
4482  * ALT_SDMMC_MINTSTS_DATARDTO_E_NOMSK | 0x1 | Data read timeout No Mask
4483  *
4484  * Field Access Macros:
4485  *
4486  */
4487 /*
4488  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATARDTO
4489  *
4490  * Data read timeout Mask
4491  */
4492 #define ALT_SDMMC_MINTSTS_DATARDTO_E_MSK 0x0
4493 /*
4494  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATARDTO
4495  *
4496  * Data read timeout No Mask
4497  */
4498 #define ALT_SDMMC_MINTSTS_DATARDTO_E_NOMSK 0x1
4499 
4500 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DATARDTO register field. */
4501 #define ALT_SDMMC_MINTSTS_DATARDTO_LSB 9
4502 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DATARDTO register field. */
4503 #define ALT_SDMMC_MINTSTS_DATARDTO_MSB 9
4504 /* The width in bits of the ALT_SDMMC_MINTSTS_DATARDTO register field. */
4505 #define ALT_SDMMC_MINTSTS_DATARDTO_WIDTH 1
4506 /* The mask used to set the ALT_SDMMC_MINTSTS_DATARDTO register field value. */
4507 #define ALT_SDMMC_MINTSTS_DATARDTO_SET_MSK 0x00000200
4508 /* The mask used to clear the ALT_SDMMC_MINTSTS_DATARDTO register field value. */
4509 #define ALT_SDMMC_MINTSTS_DATARDTO_CLR_MSK 0xfffffdff
4510 /* The reset value of the ALT_SDMMC_MINTSTS_DATARDTO register field. */
4511 #define ALT_SDMMC_MINTSTS_DATARDTO_RESET 0x0
4512 /* Extracts the ALT_SDMMC_MINTSTS_DATARDTO field value from a register. */
4513 #define ALT_SDMMC_MINTSTS_DATARDTO_GET(value) (((value) & 0x00000200) >> 9)
4514 /* Produces a ALT_SDMMC_MINTSTS_DATARDTO register field value suitable for setting the register. */
4515 #define ALT_SDMMC_MINTSTS_DATARDTO_SET(value) (((value) << 9) & 0x00000200)
4516 
4517 /*
4518  * Field : Data Starvation Host Timeout - dshto
4519  *
4520  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4521  *
4522  * Field Enumeration Values:
4523  *
4524  * Enum | Value | Description
4525  * :--------------------------------|:------|:----------------------------------------
4526  * ALT_SDMMC_MINTSTS_DSHTO_E_MSK | 0x0 | Data starvation by host timeout Mask
4527  * ALT_SDMMC_MINTSTS_DSHTO_E_NOMSK | 0x1 | Data starvation by host timeout No Mask
4528  *
4529  * Field Access Macros:
4530  *
4531  */
4532 /*
4533  * Enumerated value for register field ALT_SDMMC_MINTSTS_DSHTO
4534  *
4535  * Data starvation by host timeout Mask
4536  */
4537 #define ALT_SDMMC_MINTSTS_DSHTO_E_MSK 0x0
4538 /*
4539  * Enumerated value for register field ALT_SDMMC_MINTSTS_DSHTO
4540  *
4541  * Data starvation by host timeout No Mask
4542  */
4543 #define ALT_SDMMC_MINTSTS_DSHTO_E_NOMSK 0x1
4544 
4545 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DSHTO register field. */
4546 #define ALT_SDMMC_MINTSTS_DSHTO_LSB 10
4547 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DSHTO register field. */
4548 #define ALT_SDMMC_MINTSTS_DSHTO_MSB 10
4549 /* The width in bits of the ALT_SDMMC_MINTSTS_DSHTO register field. */
4550 #define ALT_SDMMC_MINTSTS_DSHTO_WIDTH 1
4551 /* The mask used to set the ALT_SDMMC_MINTSTS_DSHTO register field value. */
4552 #define ALT_SDMMC_MINTSTS_DSHTO_SET_MSK 0x00000400
4553 /* The mask used to clear the ALT_SDMMC_MINTSTS_DSHTO register field value. */
4554 #define ALT_SDMMC_MINTSTS_DSHTO_CLR_MSK 0xfffffbff
4555 /* The reset value of the ALT_SDMMC_MINTSTS_DSHTO register field. */
4556 #define ALT_SDMMC_MINTSTS_DSHTO_RESET 0x0
4557 /* Extracts the ALT_SDMMC_MINTSTS_DSHTO field value from a register. */
4558 #define ALT_SDMMC_MINTSTS_DSHTO_GET(value) (((value) & 0x00000400) >> 10)
4559 /* Produces a ALT_SDMMC_MINTSTS_DSHTO register field value suitable for setting the register. */
4560 #define ALT_SDMMC_MINTSTS_DSHTO_SET(value) (((value) << 10) & 0x00000400)
4561 
4562 /*
4563  * Field : FIFO Underrun Overrun Error - fifoovunerr
4564  *
4565  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4566  *
4567  * Field Enumeration Values:
4568  *
4569  * Enum | Value | Description
4570  * :--------------------------------------|:------|:------------------------------------
4571  * ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_MSK | 0x0 | FIFO underrun/overrun error Mask
4572  * ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_NOMSK | 0x1 | FIFO underrun/overrun error No Mask
4573  *
4574  * Field Access Macros:
4575  *
4576  */
4577 /*
4578  * Enumerated value for register field ALT_SDMMC_MINTSTS_FIFOOVUNERR
4579  *
4580  * FIFO underrun/overrun error Mask
4581  */
4582 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_MSK 0x0
4583 /*
4584  * Enumerated value for register field ALT_SDMMC_MINTSTS_FIFOOVUNERR
4585  *
4586  * FIFO underrun/overrun error No Mask
4587  */
4588 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_NOMSK 0x1
4589 
4590 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field. */
4591 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_LSB 11
4592 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field. */
4593 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_MSB 11
4594 /* The width in bits of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field. */
4595 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_WIDTH 1
4596 /* The mask used to set the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field value. */
4597 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET_MSK 0x00000800
4598 /* The mask used to clear the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field value. */
4599 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_CLR_MSK 0xfffff7ff
4600 /* The reset value of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field. */
4601 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_RESET 0x0
4602 /* Extracts the ALT_SDMMC_MINTSTS_FIFOOVUNERR field value from a register. */
4603 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_GET(value) (((value) & 0x00000800) >> 11)
4604 /* Produces a ALT_SDMMC_MINTSTS_FIFOOVUNERR register field value suitable for setting the register. */
4605 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET(value) (((value) << 11) & 0x00000800)
4606 
4607 /*
4608  * Field : Hardware Locked Write Error - hlwerr
4609  *
4610  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4611  *
4612  * Field Enumeration Values:
4613  *
4614  * Enum | Value | Description
4615  * :---------------------------------|:------|:------------------------------------
4616  * ALT_SDMMC_MINTSTS_HLWERR_E_MSK | 0x0 | Hardware locked write error Mask
4617  * ALT_SDMMC_MINTSTS_HLWERR_E_NOMSK | 0x1 | Hardware locked write error No Mask
4618  *
4619  * Field Access Macros:
4620  *
4621  */
4622 /*
4623  * Enumerated value for register field ALT_SDMMC_MINTSTS_HLWERR
4624  *
4625  * Hardware locked write error Mask
4626  */
4627 #define ALT_SDMMC_MINTSTS_HLWERR_E_MSK 0x0
4628 /*
4629  * Enumerated value for register field ALT_SDMMC_MINTSTS_HLWERR
4630  *
4631  * Hardware locked write error No Mask
4632  */
4633 #define ALT_SDMMC_MINTSTS_HLWERR_E_NOMSK 0x1
4634 
4635 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_HLWERR register field. */
4636 #define ALT_SDMMC_MINTSTS_HLWERR_LSB 12
4637 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_HLWERR register field. */
4638 #define ALT_SDMMC_MINTSTS_HLWERR_MSB 12
4639 /* The width in bits of the ALT_SDMMC_MINTSTS_HLWERR register field. */
4640 #define ALT_SDMMC_MINTSTS_HLWERR_WIDTH 1
4641 /* The mask used to set the ALT_SDMMC_MINTSTS_HLWERR register field value. */
4642 #define ALT_SDMMC_MINTSTS_HLWERR_SET_MSK 0x00001000
4643 /* The mask used to clear the ALT_SDMMC_MINTSTS_HLWERR register field value. */
4644 #define ALT_SDMMC_MINTSTS_HLWERR_CLR_MSK 0xffffefff
4645 /* The reset value of the ALT_SDMMC_MINTSTS_HLWERR register field. */
4646 #define ALT_SDMMC_MINTSTS_HLWERR_RESET 0x0
4647 /* Extracts the ALT_SDMMC_MINTSTS_HLWERR field value from a register. */
4648 #define ALT_SDMMC_MINTSTS_HLWERR_GET(value) (((value) & 0x00001000) >> 12)
4649 /* Produces a ALT_SDMMC_MINTSTS_HLWERR register field value suitable for setting the register. */
4650 #define ALT_SDMMC_MINTSTS_HLWERR_SET(value) (((value) << 12) & 0x00001000)
4651 
4652 /*
4653  * Field : Start-bit Error - strerr
4654  *
4655  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4656  *
4657  * Field Enumeration Values:
4658  *
4659  * Enum | Value | Description
4660  * :---------------------------------|:------|:------------------------
4661  * ALT_SDMMC_MINTSTS_STRERR_E_MSK | 0x0 | Start-bit error Mask
4662  * ALT_SDMMC_MINTSTS_STRERR_E_NOMSK | 0x1 | Start-bit error No Mask
4663  *
4664  * Field Access Macros:
4665  *
4666  */
4667 /*
4668  * Enumerated value for register field ALT_SDMMC_MINTSTS_STRERR
4669  *
4670  * Start-bit error Mask
4671  */
4672 #define ALT_SDMMC_MINTSTS_STRERR_E_MSK 0x0
4673 /*
4674  * Enumerated value for register field ALT_SDMMC_MINTSTS_STRERR
4675  *
4676  * Start-bit error No Mask
4677  */
4678 #define ALT_SDMMC_MINTSTS_STRERR_E_NOMSK 0x1
4679 
4680 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_STRERR register field. */
4681 #define ALT_SDMMC_MINTSTS_STRERR_LSB 13
4682 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_STRERR register field. */
4683 #define ALT_SDMMC_MINTSTS_STRERR_MSB 13
4684 /* The width in bits of the ALT_SDMMC_MINTSTS_STRERR register field. */
4685 #define ALT_SDMMC_MINTSTS_STRERR_WIDTH 1
4686 /* The mask used to set the ALT_SDMMC_MINTSTS_STRERR register field value. */
4687 #define ALT_SDMMC_MINTSTS_STRERR_SET_MSK 0x00002000
4688 /* The mask used to clear the ALT_SDMMC_MINTSTS_STRERR register field value. */
4689 #define ALT_SDMMC_MINTSTS_STRERR_CLR_MSK 0xffffdfff
4690 /* The reset value of the ALT_SDMMC_MINTSTS_STRERR register field. */
4691 #define ALT_SDMMC_MINTSTS_STRERR_RESET 0x0
4692 /* Extracts the ALT_SDMMC_MINTSTS_STRERR field value from a register. */
4693 #define ALT_SDMMC_MINTSTS_STRERR_GET(value) (((value) & 0x00002000) >> 13)
4694 /* Produces a ALT_SDMMC_MINTSTS_STRERR register field value suitable for setting the register. */
4695 #define ALT_SDMMC_MINTSTS_STRERR_SET(value) (((value) << 13) & 0x00002000)
4696 
4697 /*
4698  * Field : Auto Command Done - acd
4699  *
4700  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4701  *
4702  * Field Enumeration Values:
4703  *
4704  * Enum | Value | Description
4705  * :------------------------------|:------|:--------------------------
4706  * ALT_SDMMC_MINTSTS_ACD_E_MSK | 0x0 | Auto command done Mask
4707  * ALT_SDMMC_MINTSTS_ACD_E_NOMSK | 0x1 | Auto command done No Mask
4708  *
4709  * Field Access Macros:
4710  *
4711  */
4712 /*
4713  * Enumerated value for register field ALT_SDMMC_MINTSTS_ACD
4714  *
4715  * Auto command done Mask
4716  */
4717 #define ALT_SDMMC_MINTSTS_ACD_E_MSK 0x0
4718 /*
4719  * Enumerated value for register field ALT_SDMMC_MINTSTS_ACD
4720  *
4721  * Auto command done No Mask
4722  */
4723 #define ALT_SDMMC_MINTSTS_ACD_E_NOMSK 0x1
4724 
4725 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_ACD register field. */
4726 #define ALT_SDMMC_MINTSTS_ACD_LSB 14
4727 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_ACD register field. */
4728 #define ALT_SDMMC_MINTSTS_ACD_MSB 14
4729 /* The width in bits of the ALT_SDMMC_MINTSTS_ACD register field. */
4730 #define ALT_SDMMC_MINTSTS_ACD_WIDTH 1
4731 /* The mask used to set the ALT_SDMMC_MINTSTS_ACD register field value. */
4732 #define ALT_SDMMC_MINTSTS_ACD_SET_MSK 0x00004000
4733 /* The mask used to clear the ALT_SDMMC_MINTSTS_ACD register field value. */
4734 #define ALT_SDMMC_MINTSTS_ACD_CLR_MSK 0xffffbfff
4735 /* The reset value of the ALT_SDMMC_MINTSTS_ACD register field. */
4736 #define ALT_SDMMC_MINTSTS_ACD_RESET 0x0
4737 /* Extracts the ALT_SDMMC_MINTSTS_ACD field value from a register. */
4738 #define ALT_SDMMC_MINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14)
4739 /* Produces a ALT_SDMMC_MINTSTS_ACD register field value suitable for setting the register. */
4740 #define ALT_SDMMC_MINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000)
4741 
4742 /*
4743  * Field : End-bit Error - ebe
4744  *
4745  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4746  *
4747  * Field Enumeration Values:
4748  *
4749  * Enum | Value | Description
4750  * :------------------------------|:------|:----------------------
4751  * ALT_SDMMC_MINTSTS_EBE_E_MSK | 0x0 | End-bit error Mask
4752  * ALT_SDMMC_MINTSTS_EBE_E_NOMSK | 0x1 | End-bit error No Mask
4753  *
4754  * Field Access Macros:
4755  *
4756  */
4757 /*
4758  * Enumerated value for register field ALT_SDMMC_MINTSTS_EBE
4759  *
4760  * End-bit error Mask
4761  */
4762 #define ALT_SDMMC_MINTSTS_EBE_E_MSK 0x0
4763 /*
4764  * Enumerated value for register field ALT_SDMMC_MINTSTS_EBE
4765  *
4766  * End-bit error No Mask
4767  */
4768 #define ALT_SDMMC_MINTSTS_EBE_E_NOMSK 0x1
4769 
4770 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_EBE register field. */
4771 #define ALT_SDMMC_MINTSTS_EBE_LSB 15
4772 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_EBE register field. */
4773 #define ALT_SDMMC_MINTSTS_EBE_MSB 15
4774 /* The width in bits of the ALT_SDMMC_MINTSTS_EBE register field. */
4775 #define ALT_SDMMC_MINTSTS_EBE_WIDTH 1
4776 /* The mask used to set the ALT_SDMMC_MINTSTS_EBE register field value. */
4777 #define ALT_SDMMC_MINTSTS_EBE_SET_MSK 0x00008000
4778 /* The mask used to clear the ALT_SDMMC_MINTSTS_EBE register field value. */
4779 #define ALT_SDMMC_MINTSTS_EBE_CLR_MSK 0xffff7fff
4780 /* The reset value of the ALT_SDMMC_MINTSTS_EBE register field. */
4781 #define ALT_SDMMC_MINTSTS_EBE_RESET 0x0
4782 /* Extracts the ALT_SDMMC_MINTSTS_EBE field value from a register. */
4783 #define ALT_SDMMC_MINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15)
4784 /* Produces a ALT_SDMMC_MINTSTS_EBE register field value suitable for setting the register. */
4785 #define ALT_SDMMC_MINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000)
4786 
4787 /*
4788  * Field : sdio_interrupt
4789  *
4790  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
4791  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
4792  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
4793  * enables interrupt; 0 masks interrupt).
4794  *
4795  * 0-No SDIO interrupt from card
4796  *
4797  * 1-SDIO interrupt from card
4798  *
4799  * In MMC-Ver3.3-only mode, bits always 0.
4800  *
4801  * Field Enumeration Values:
4802  *
4803  * Enum | Value | Description
4804  * :-----------------------------------|:------|:----------------------------
4805  * ALT_SDMMC_MINTSTS_SDIO_INT_E_INACT | 0x0 | No SDIO interrupt from card
4806  * ALT_SDMMC_MINTSTS_SDIO_INT_E_ACT | 0x1 | SDIO interrupt from card
4807  *
4808  * Field Access Macros:
4809  *
4810  */
4811 /*
4812  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INT
4813  *
4814  * No SDIO interrupt from card
4815  */
4816 #define ALT_SDMMC_MINTSTS_SDIO_INT_E_INACT 0x0
4817 /*
4818  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INT
4819  *
4820  * SDIO interrupt from card
4821  */
4822 #define ALT_SDMMC_MINTSTS_SDIO_INT_E_ACT 0x1
4823 
4824 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INT register field. */
4825 #define ALT_SDMMC_MINTSTS_SDIO_INT_LSB 16
4826 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INT register field. */
4827 #define ALT_SDMMC_MINTSTS_SDIO_INT_MSB 31
4828 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INT register field. */
4829 #define ALT_SDMMC_MINTSTS_SDIO_INT_WIDTH 16
4830 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INT register field value. */
4831 #define ALT_SDMMC_MINTSTS_SDIO_INT_SET_MSK 0xffff0000
4832 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INT register field value. */
4833 #define ALT_SDMMC_MINTSTS_SDIO_INT_CLR_MSK 0x0000ffff
4834 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INT register field. */
4835 #define ALT_SDMMC_MINTSTS_SDIO_INT_RESET 0x0
4836 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INT field value from a register. */
4837 #define ALT_SDMMC_MINTSTS_SDIO_INT_GET(value) (((value) & 0xffff0000) >> 16)
4838 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INT register field value suitable for setting the register. */
4839 #define ALT_SDMMC_MINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0xffff0000)
4840 
4841 #ifndef __ASSEMBLY__
4842 /*
4843  * WARNING: The C register and register group struct declarations are provided for
4844  * convenience and illustrative purposes. They should, however, be used with
4845  * caution as the C language standard provides no guarantees about the alignment or
4846  * atomicity of device memory accesses. The recommended practice for writing
4847  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4848  * alt_write_word() functions.
4849  *
4850  * The struct declaration for register ALT_SDMMC_MINTSTS.
4851  */
4852 struct ALT_SDMMC_MINTSTS_s
4853 {
4854  const uint32_t cd : 1; /* Card Detect */
4855  const uint32_t resp : 1; /* Response Error */
4856  const uint32_t cmd_done : 1; /* Command Done */
4857  const uint32_t dt : 1; /* Data Transfer Over */
4858  const uint32_t dttxfifodr : 1; /* Data TX FIFO Data Request */
4859  const uint32_t rxfifodr : 1; /* Receive FIFO Data Request */
4860  const uint32_t respcrcerr : 1; /* Response CRC Error */
4861  const uint32_t datacrcerr : 1; /* Data CRC Error */
4862  const uint32_t respto : 1; /* Response Timeout */
4863  const uint32_t datardto : 1; /* Data Read Timeout */
4864  const uint32_t dshto : 1; /* Data Starvation Host Timeout */
4865  const uint32_t fifoovunerr : 1; /* FIFO Underrun Overrun Error */
4866  const uint32_t hlwerr : 1; /* Hardware Locked Write Error */
4867  const uint32_t strerr : 1; /* Start-bit Error */
4868  const uint32_t acd : 1; /* Auto Command Done */
4869  const uint32_t ebe : 1; /* End-bit Error */
4870  const uint32_t sdio_interrupt : 16; /* ALT_SDMMC_MINTSTS_SDIO_INT */
4871 };
4872 
4873 /* The typedef declaration for register ALT_SDMMC_MINTSTS. */
4874 typedef volatile struct ALT_SDMMC_MINTSTS_s ALT_SDMMC_MINTSTS_t;
4875 #endif /* __ASSEMBLY__ */
4876 
4877 /* The reset value of the ALT_SDMMC_MINTSTS register. */
4878 #define ALT_SDMMC_MINTSTS_RESET 0x00000000
4879 /* The byte offset of the ALT_SDMMC_MINTSTS register from the beginning of the component. */
4880 #define ALT_SDMMC_MINTSTS_OFST 0x40
4881 
4882 /*
4883  * Register : rintsts
4884  *
4885  * Raw Interrupt Status Register
4886  *
4887  * Register Layout
4888  *
4889  * Bits | Access | Reset | Description
4890  * :--------|:-------|:------|:---------------------------------------------
4891  * [0] | RW | 0x0 | Card Detect
4892  * [1] | RW | 0x0 | Response Error
4893  * [2] | RW | 0x0 | Command Done
4894  * [3] | RW | 0x0 | Data Transfer Over
4895  * [4] | RW | 0x0 | Transmit FIFO Data Request
4896  * [5] | RW | 0x0 | Receive FIFO Data Request
4897  * [6] | RW | 0x0 | Response CRC Error
4898  * [7] | RW | 0x0 | Data CRC Error
4899  * [8] | RW | 0x0 | Response Timeout Boot Ack Received
4900  * [9] | RW | 0x0 | Data Read Timeout Boot Data Start
4901  * [10] | RW | 0x0 | Data Starvation Host Timeout Volt Switch_int
4902  * [11] | RW | 0x0 | FIFO Underrun Overrun Error
4903  * [12] | RW | 0x0 | Hardware Locked Write Error
4904  * [13] | RW | 0x0 | Start-bit error (SBE)
4905  * [14] | RW | 0x0 | Auto Cmommand Done
4906  * [15] | RW | 0x0 | End-bit Error
4907  * [31:16] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INT
4908  *
4909  */
4910 /*
4911  * Field : Card Detect - cd
4912  *
4913  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4914  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4915  *
4916  * Field Enumeration Values:
4917  *
4918  * Enum | Value | Description
4919  * :-----------------------------|:------|:------------------------
4920  * ALT_SDMMC_RINTSTS_CD_E_INACT | 0x0 | Card detect (CD)
4921  * ALT_SDMMC_RINTSTS_CD_E_ACT | 0x1 | Clears Card detect (CD)
4922  *
4923  * Field Access Macros:
4924  *
4925  */
4926 /*
4927  * Enumerated value for register field ALT_SDMMC_RINTSTS_CD
4928  *
4929  * Card detect (CD)
4930  */
4931 #define ALT_SDMMC_RINTSTS_CD_E_INACT 0x0
4932 /*
4933  * Enumerated value for register field ALT_SDMMC_RINTSTS_CD
4934  *
4935  * Clears Card detect (CD)
4936  */
4937 #define ALT_SDMMC_RINTSTS_CD_E_ACT 0x1
4938 
4939 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_CD register field. */
4940 #define ALT_SDMMC_RINTSTS_CD_LSB 0
4941 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_CD register field. */
4942 #define ALT_SDMMC_RINTSTS_CD_MSB 0
4943 /* The width in bits of the ALT_SDMMC_RINTSTS_CD register field. */
4944 #define ALT_SDMMC_RINTSTS_CD_WIDTH 1
4945 /* The mask used to set the ALT_SDMMC_RINTSTS_CD register field value. */
4946 #define ALT_SDMMC_RINTSTS_CD_SET_MSK 0x00000001
4947 /* The mask used to clear the ALT_SDMMC_RINTSTS_CD register field value. */
4948 #define ALT_SDMMC_RINTSTS_CD_CLR_MSK 0xfffffffe
4949 /* The reset value of the ALT_SDMMC_RINTSTS_CD register field. */
4950 #define ALT_SDMMC_RINTSTS_CD_RESET 0x0
4951 /* Extracts the ALT_SDMMC_RINTSTS_CD field value from a register. */
4952 #define ALT_SDMMC_RINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0)
4953 /* Produces a ALT_SDMMC_RINTSTS_CD register field value suitable for setting the register. */
4954 #define ALT_SDMMC_RINTSTS_CD_SET(value) (((value) << 0) & 0x00000001)
4955 
4956 /*
4957  * Field : Response Error - re
4958  *
4959  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4960  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4961  *
4962  * Field Enumeration Values:
4963  *
4964  * Enum | Value | Description
4965  * :-----------------------------|:------|:---------------------------
4966  * ALT_SDMMC_RINTSTS_RE_E_INACT | 0x0 | Response error (RE)
4967  * ALT_SDMMC_RINTSTS_RE_E_ACT | 0x1 | Clears Response error (RE)
4968  *
4969  * Field Access Macros:
4970  *
4971  */
4972 /*
4973  * Enumerated value for register field ALT_SDMMC_RINTSTS_RE
4974  *
4975  * Response error (RE)
4976  */
4977 #define ALT_SDMMC_RINTSTS_RE_E_INACT 0x0
4978 /*
4979  * Enumerated value for register field ALT_SDMMC_RINTSTS_RE
4980  *
4981  * Clears Response error (RE)
4982  */
4983 #define ALT_SDMMC_RINTSTS_RE_E_ACT 0x1
4984 
4985 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_RE register field. */
4986 #define ALT_SDMMC_RINTSTS_RE_LSB 1
4987 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_RE register field. */
4988 #define ALT_SDMMC_RINTSTS_RE_MSB 1
4989 /* The width in bits of the ALT_SDMMC_RINTSTS_RE register field. */
4990 #define ALT_SDMMC_RINTSTS_RE_WIDTH 1
4991 /* The mask used to set the ALT_SDMMC_RINTSTS_RE register field value. */
4992 #define ALT_SDMMC_RINTSTS_RE_SET_MSK 0x00000002
4993 /* The mask used to clear the ALT_SDMMC_RINTSTS_RE register field value. */
4994 #define ALT_SDMMC_RINTSTS_RE_CLR_MSK 0xfffffffd
4995 /* The reset value of the ALT_SDMMC_RINTSTS_RE register field. */
4996 #define ALT_SDMMC_RINTSTS_RE_RESET 0x0
4997 /* Extracts the ALT_SDMMC_RINTSTS_RE field value from a register. */
4998 #define ALT_SDMMC_RINTSTS_RE_GET(value) (((value) & 0x00000002) >> 1)
4999 /* Produces a ALT_SDMMC_RINTSTS_RE register field value suitable for setting the register. */
5000 #define ALT_SDMMC_RINTSTS_RE_SET(value) (((value) << 1) & 0x00000002)
5001 
5002 /*
5003  * Field : Command Done - cmd
5004  *
5005  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5006  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5007  *
5008  * Field Enumeration Values:
5009  *
5010  * Enum | Value | Description
5011  * :------------------------------|:------|:-------------------------
5012  * ALT_SDMMC_RINTSTS_CMD_E_INACT | 0x0 | Command done (CD)
5013  * ALT_SDMMC_RINTSTS_CMD_E_ACT | 0x1 | Clears Command done (CD)
5014  *
5015  * Field Access Macros:
5016  *
5017  */
5018 /*
5019  * Enumerated value for register field ALT_SDMMC_RINTSTS_CMD
5020  *
5021  * Command done (CD)
5022  */
5023 #define ALT_SDMMC_RINTSTS_CMD_E_INACT 0x0
5024 /*
5025  * Enumerated value for register field ALT_SDMMC_RINTSTS_CMD
5026  *
5027  * Clears Command done (CD)
5028  */
5029 #define ALT_SDMMC_RINTSTS_CMD_E_ACT 0x1
5030 
5031 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_CMD register field. */
5032 #define ALT_SDMMC_RINTSTS_CMD_LSB 2
5033 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_CMD register field. */
5034 #define ALT_SDMMC_RINTSTS_CMD_MSB 2
5035 /* The width in bits of the ALT_SDMMC_RINTSTS_CMD register field. */
5036 #define ALT_SDMMC_RINTSTS_CMD_WIDTH 1
5037 /* The mask used to set the ALT_SDMMC_RINTSTS_CMD register field value. */
5038 #define ALT_SDMMC_RINTSTS_CMD_SET_MSK 0x00000004
5039 /* The mask used to clear the ALT_SDMMC_RINTSTS_CMD register field value. */
5040 #define ALT_SDMMC_RINTSTS_CMD_CLR_MSK 0xfffffffb
5041 /* The reset value of the ALT_SDMMC_RINTSTS_CMD register field. */
5042 #define ALT_SDMMC_RINTSTS_CMD_RESET 0x0
5043 /* Extracts the ALT_SDMMC_RINTSTS_CMD field value from a register. */
5044 #define ALT_SDMMC_RINTSTS_CMD_GET(value) (((value) & 0x00000004) >> 2)
5045 /* Produces a ALT_SDMMC_RINTSTS_CMD register field value suitable for setting the register. */
5046 #define ALT_SDMMC_RINTSTS_CMD_SET(value) (((value) << 2) & 0x00000004)
5047 
5048 /*
5049  * Field : Data Transfer Over - dto
5050  *
5051  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5052  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5053  *
5054  * Field Enumeration Values:
5055  *
5056  * Enum | Value | Description
5057  * :------------------------------|:------|:--------------------------------
5058  * ALT_SDMMC_RINTSTS_DTO_E_INACT | 0x0 | Data transfer over (DTO)
5059  * ALT_SDMMC_RINTSTS_DTO_E_ACT | 0x1 | Clears Data transfer over (DTO)
5060  *
5061  * Field Access Macros:
5062  *
5063  */
5064 /*
5065  * Enumerated value for register field ALT_SDMMC_RINTSTS_DTO
5066  *
5067  * Data transfer over (DTO)
5068  */
5069 #define ALT_SDMMC_RINTSTS_DTO_E_INACT 0x0
5070 /*
5071  * Enumerated value for register field ALT_SDMMC_RINTSTS_DTO
5072  *
5073  * Clears Data transfer over (DTO)
5074  */
5075 #define ALT_SDMMC_RINTSTS_DTO_E_ACT 0x1
5076 
5077 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_DTO register field. */
5078 #define ALT_SDMMC_RINTSTS_DTO_LSB 3
5079 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_DTO register field. */
5080 #define ALT_SDMMC_RINTSTS_DTO_MSB 3
5081 /* The width in bits of the ALT_SDMMC_RINTSTS_DTO register field. */
5082 #define ALT_SDMMC_RINTSTS_DTO_WIDTH 1
5083 /* The mask used to set the ALT_SDMMC_RINTSTS_DTO register field value. */
5084 #define ALT_SDMMC_RINTSTS_DTO_SET_MSK 0x00000008
5085 /* The mask used to clear the ALT_SDMMC_RINTSTS_DTO register field value. */
5086 #define ALT_SDMMC_RINTSTS_DTO_CLR_MSK 0xfffffff7
5087 /* The reset value of the ALT_SDMMC_RINTSTS_DTO register field. */
5088 #define ALT_SDMMC_RINTSTS_DTO_RESET 0x0
5089 /* Extracts the ALT_SDMMC_RINTSTS_DTO field value from a register. */
5090 #define ALT_SDMMC_RINTSTS_DTO_GET(value) (((value) & 0x00000008) >> 3)
5091 /* Produces a ALT_SDMMC_RINTSTS_DTO register field value suitable for setting the register. */
5092 #define ALT_SDMMC_RINTSTS_DTO_SET(value) (((value) << 3) & 0x00000008)
5093 
5094 /*
5095  * Field : Transmit FIFO Data Request - txdr
5096  *
5097  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5098  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5099  *
5100  * Field Enumeration Values:
5101  *
5102  * Enum | Value | Description
5103  * :-------------------------------|:------|:-----------------------------------------
5104  * ALT_SDMMC_RINTSTS_TXDR_E_INACT | 0x0 | Transmit FIFO data request (TXDR)
5105  * ALT_SDMMC_RINTSTS_TXDR_E_ACT | 0x1 | Clears Transmit FIFO data request (TXDR)
5106  *
5107  * Field Access Macros:
5108  *
5109  */
5110 /*
5111  * Enumerated value for register field ALT_SDMMC_RINTSTS_TXDR
5112  *
5113  * Transmit FIFO data request (TXDR)
5114  */
5115 #define ALT_SDMMC_RINTSTS_TXDR_E_INACT 0x0
5116 /*
5117  * Enumerated value for register field ALT_SDMMC_RINTSTS_TXDR
5118  *
5119  * Clears Transmit FIFO data request (TXDR)
5120  */
5121 #define ALT_SDMMC_RINTSTS_TXDR_E_ACT 0x1
5122 
5123 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_TXDR register field. */
5124 #define ALT_SDMMC_RINTSTS_TXDR_LSB 4
5125 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_TXDR register field. */
5126 #define ALT_SDMMC_RINTSTS_TXDR_MSB 4
5127 /* The width in bits of the ALT_SDMMC_RINTSTS_TXDR register field. */
5128 #define ALT_SDMMC_RINTSTS_TXDR_WIDTH 1
5129 /* The mask used to set the ALT_SDMMC_RINTSTS_TXDR register field value. */
5130 #define ALT_SDMMC_RINTSTS_TXDR_SET_MSK 0x00000010
5131 /* The mask used to clear the ALT_SDMMC_RINTSTS_TXDR register field value. */
5132 #define ALT_SDMMC_RINTSTS_TXDR_CLR_MSK 0xffffffef
5133 /* The reset value of the ALT_SDMMC_RINTSTS_TXDR register field. */
5134 #define ALT_SDMMC_RINTSTS_TXDR_RESET 0x0
5135 /* Extracts the ALT_SDMMC_RINTSTS_TXDR field value from a register. */
5136 #define ALT_SDMMC_RINTSTS_TXDR_GET(value) (((value) & 0x00000010) >> 4)
5137 /* Produces a ALT_SDMMC_RINTSTS_TXDR register field value suitable for setting the register. */
5138 #define ALT_SDMMC_RINTSTS_TXDR_SET(value) (((value) << 4) & 0x00000010)
5139 
5140 /*
5141  * Field : Receive FIFO Data Request - rxdr
5142  *
5143  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5144  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5145  *
5146  * Field Enumeration Values:
5147  *
5148  * Enum | Value | Description
5149  * :-------------------------------|:------|:----------------------------------------
5150  * ALT_SDMMC_RINTSTS_RXDR_E_INACT | 0x0 | Receive FIFO data request (RXDR)
5151  * ALT_SDMMC_RINTSTS_RXDR_E_ACT | 0x1 | Clears Receive FIFO data request (RXDR)
5152  *
5153  * Field Access Macros:
5154  *
5155  */
5156 /*
5157  * Enumerated value for register field ALT_SDMMC_RINTSTS_RXDR
5158  *
5159  * Receive FIFO data request (RXDR)
5160  */
5161 #define ALT_SDMMC_RINTSTS_RXDR_E_INACT 0x0
5162 /*
5163  * Enumerated value for register field ALT_SDMMC_RINTSTS_RXDR
5164  *
5165  * Clears Receive FIFO data request (RXDR)
5166  */
5167 #define ALT_SDMMC_RINTSTS_RXDR_E_ACT 0x1
5168 
5169 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_RXDR register field. */
5170 #define ALT_SDMMC_RINTSTS_RXDR_LSB 5
5171 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_RXDR register field. */
5172 #define ALT_SDMMC_RINTSTS_RXDR_MSB 5
5173 /* The width in bits of the ALT_SDMMC_RINTSTS_RXDR register field. */
5174 #define ALT_SDMMC_RINTSTS_RXDR_WIDTH 1
5175 /* The mask used to set the ALT_SDMMC_RINTSTS_RXDR register field value. */
5176 #define ALT_SDMMC_RINTSTS_RXDR_SET_MSK 0x00000020
5177 /* The mask used to clear the ALT_SDMMC_RINTSTS_RXDR register field value. */
5178 #define ALT_SDMMC_RINTSTS_RXDR_CLR_MSK 0xffffffdf
5179 /* The reset value of the ALT_SDMMC_RINTSTS_RXDR register field. */
5180 #define ALT_SDMMC_RINTSTS_RXDR_RESET 0x0
5181 /* Extracts the ALT_SDMMC_RINTSTS_RXDR field value from a register. */
5182 #define ALT_SDMMC_RINTSTS_RXDR_GET(value) (((value) & 0x00000020) >> 5)
5183 /* Produces a ALT_SDMMC_RINTSTS_RXDR register field value suitable for setting the register. */
5184 #define ALT_SDMMC_RINTSTS_RXDR_SET(value) (((value) << 5) & 0x00000020)
5185 
5186 /*
5187  * Field : Response CRC Error - rcrc
5188  *
5189  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5190  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5191  *
5192  * Field Enumeration Values:
5193  *
5194  * Enum | Value | Description
5195  * :-------------------------------|:------|:---------------------------------
5196  * ALT_SDMMC_RINTSTS_RCRC_E_INACT | 0x0 | Response CRC error (RCRC)
5197  * ALT_SDMMC_RINTSTS_RCRC_E_ACT | 0x1 | Clears Response CRC error (RCRC)
5198  *
5199  * Field Access Macros:
5200  *
5201  */
5202 /*
5203  * Enumerated value for register field ALT_SDMMC_RINTSTS_RCRC
5204  *
5205  * Response CRC error (RCRC)
5206  */
5207 #define ALT_SDMMC_RINTSTS_RCRC_E_INACT 0x0
5208 /*
5209  * Enumerated value for register field ALT_SDMMC_RINTSTS_RCRC
5210  *
5211  * Clears Response CRC error (RCRC)
5212  */
5213 #define ALT_SDMMC_RINTSTS_RCRC_E_ACT 0x1
5214 
5215 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_RCRC register field. */
5216 #define ALT_SDMMC_RINTSTS_RCRC_LSB 6
5217 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_RCRC register field. */
5218 #define ALT_SDMMC_RINTSTS_RCRC_MSB 6
5219 /* The width in bits of the ALT_SDMMC_RINTSTS_RCRC register field. */
5220 #define ALT_SDMMC_RINTSTS_RCRC_WIDTH 1
5221 /* The mask used to set the ALT_SDMMC_RINTSTS_RCRC register field value. */
5222 #define ALT_SDMMC_RINTSTS_RCRC_SET_MSK 0x00000040
5223 /* The mask used to clear the ALT_SDMMC_RINTSTS_RCRC register field value. */
5224 #define ALT_SDMMC_RINTSTS_RCRC_CLR_MSK 0xffffffbf
5225 /* The reset value of the ALT_SDMMC_RINTSTS_RCRC register field. */
5226 #define ALT_SDMMC_RINTSTS_RCRC_RESET 0x0
5227 /* Extracts the ALT_SDMMC_RINTSTS_RCRC field value from a register. */
5228 #define ALT_SDMMC_RINTSTS_RCRC_GET(value) (((value) & 0x00000040) >> 6)
5229 /* Produces a ALT_SDMMC_RINTSTS_RCRC register field value suitable for setting the register. */
5230 #define ALT_SDMMC_RINTSTS_RCRC_SET(value) (((value) << 6) & 0x00000040)
5231 
5232 /*
5233  * Field : Data CRC Error - dcrc
5234  *
5235  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5236  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5237  *
5238  * Field Enumeration Values:
5239  *
5240  * Enum | Value | Description
5241  * :-------------------------------|:------|:-----------------------------
5242  * ALT_SDMMC_RINTSTS_DCRC_E_INACT | 0x0 | Data CRC error (DCRC)
5243  * ALT_SDMMC_RINTSTS_DCRC_E_ACT | 0x1 | Clears Data CRC error (DCRC)
5244  *
5245  * Field Access Macros:
5246  *
5247  */
5248 /*
5249  * Enumerated value for register field ALT_SDMMC_RINTSTS_DCRC
5250  *
5251  * Data CRC error (DCRC)
5252  */
5253 #define ALT_SDMMC_RINTSTS_DCRC_E_INACT 0x0
5254 /*
5255  * Enumerated value for register field ALT_SDMMC_RINTSTS_DCRC
5256  *
5257  * Clears Data CRC error (DCRC)
5258  */
5259 #define ALT_SDMMC_RINTSTS_DCRC_E_ACT 0x1
5260 
5261 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_DCRC register field. */
5262 #define ALT_SDMMC_RINTSTS_DCRC_LSB 7
5263 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_DCRC register field. */
5264 #define ALT_SDMMC_RINTSTS_DCRC_MSB 7
5265 /* The width in bits of the ALT_SDMMC_RINTSTS_DCRC register field. */
5266 #define ALT_SDMMC_RINTSTS_DCRC_WIDTH 1
5267 /* The mask used to set the ALT_SDMMC_RINTSTS_DCRC register field value. */
5268 #define ALT_SDMMC_RINTSTS_DCRC_SET_MSK 0x00000080
5269 /* The mask used to clear the ALT_SDMMC_RINTSTS_DCRC register field value. */
5270 #define ALT_SDMMC_RINTSTS_DCRC_CLR_MSK 0xffffff7f
5271 /* The reset value of the ALT_SDMMC_RINTSTS_DCRC register field. */
5272 #define ALT_SDMMC_RINTSTS_DCRC_RESET 0x0
5273 /* Extracts the ALT_SDMMC_RINTSTS_DCRC field value from a register. */
5274 #define ALT_SDMMC_RINTSTS_DCRC_GET(value) (((value) & 0x00000080) >> 7)
5275 /* Produces a ALT_SDMMC_RINTSTS_DCRC register field value suitable for setting the register. */
5276 #define ALT_SDMMC_RINTSTS_DCRC_SET(value) (((value) << 7) & 0x00000080)
5277 
5278 /*
5279  * Field : Response Timeout Boot Ack Received - bar
5280  *
5281  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5282  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5283  *
5284  * Field Enumeration Values:
5285  *
5286  * Enum | Value | Description
5287  * :------------------------------|:------|:------------------------------------------------
5288  * ALT_SDMMC_RINTSTS_BAR_E_INACT | 0x0 | Response timeout (RTO)/Boot Ack Received (BAR)
5289  * ALT_SDMMC_RINTSTS_BAR_E_ACT | 0x1 | Clears Response timeout (RTO)/Boot Ack Received
5290  * : | | (BAR)
5291  *
5292  * Field Access Macros:
5293  *
5294  */
5295 /*
5296  * Enumerated value for register field ALT_SDMMC_RINTSTS_BAR
5297  *
5298  * Response timeout (RTO)/Boot Ack Received (BAR)
5299  */
5300 #define ALT_SDMMC_RINTSTS_BAR_E_INACT 0x0
5301 /*
5302  * Enumerated value for register field ALT_SDMMC_RINTSTS_BAR
5303  *
5304  * Clears Response timeout (RTO)/Boot Ack Received (BAR)
5305  */
5306 #define ALT_SDMMC_RINTSTS_BAR_E_ACT 0x1
5307 
5308 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_BAR register field. */
5309 #define ALT_SDMMC_RINTSTS_BAR_LSB 8
5310 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_BAR register field. */
5311 #define ALT_SDMMC_RINTSTS_BAR_MSB 8
5312 /* The width in bits of the ALT_SDMMC_RINTSTS_BAR register field. */
5313 #define ALT_SDMMC_RINTSTS_BAR_WIDTH 1
5314 /* The mask used to set the ALT_SDMMC_RINTSTS_BAR register field value. */
5315 #define ALT_SDMMC_RINTSTS_BAR_SET_MSK 0x00000100
5316 /* The mask used to clear the ALT_SDMMC_RINTSTS_BAR register field value. */
5317 #define ALT_SDMMC_RINTSTS_BAR_CLR_MSK 0xfffffeff
5318 /* The reset value of the ALT_SDMMC_RINTSTS_BAR register field. */
5319 #define ALT_SDMMC_RINTSTS_BAR_RESET 0x0
5320 /* Extracts the ALT_SDMMC_RINTSTS_BAR field value from a register. */
5321 #define ALT_SDMMC_RINTSTS_BAR_GET(value) (((value) & 0x00000100) >> 8)
5322 /* Produces a ALT_SDMMC_RINTSTS_BAR register field value suitable for setting the register. */
5323 #define ALT_SDMMC_RINTSTS_BAR_SET(value) (((value) << 8) & 0x00000100)
5324 
5325 /*
5326  * Field : Data Read Timeout Boot Data Start - bds
5327  *
5328  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5329  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5330  *
5331  * Field Enumeration Values:
5332  *
5333  * Enum | Value | Description
5334  * :------------------------------|:------|:------------------------------------------------
5335  * ALT_SDMMC_RINTSTS_BDS_E_INACT | 0x0 | Data read timeout (DRTO)/Boot Data Start (BDS)
5336  * ALT_SDMMC_RINTSTS_BDS_E_ACT | 0x1 | Clears Data read timeout (DRTO)/Boot Data Start
5337  * : | | (BDS)
5338  *
5339  * Field Access Macros:
5340  *
5341  */
5342 /*
5343  * Enumerated value for register field ALT_SDMMC_RINTSTS_BDS
5344  *
5345  * Data read timeout (DRTO)/Boot Data Start (BDS)
5346  */
5347 #define ALT_SDMMC_RINTSTS_BDS_E_INACT 0x0
5348 /*
5349  * Enumerated value for register field ALT_SDMMC_RINTSTS_BDS
5350  *
5351  * Clears Data read timeout (DRTO)/Boot Data Start (BDS)
5352  */
5353 #define ALT_SDMMC_RINTSTS_BDS_E_ACT 0x1
5354 
5355 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_BDS register field. */
5356 #define ALT_SDMMC_RINTSTS_BDS_LSB 9
5357 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_BDS register field. */
5358 #define ALT_SDMMC_RINTSTS_BDS_MSB 9
5359 /* The width in bits of the ALT_SDMMC_RINTSTS_BDS register field. */
5360 #define ALT_SDMMC_RINTSTS_BDS_WIDTH 1
5361 /* The mask used to set the ALT_SDMMC_RINTSTS_BDS register field value. */
5362 #define ALT_SDMMC_RINTSTS_BDS_SET_MSK 0x00000200
5363 /* The mask used to clear the ALT_SDMMC_RINTSTS_BDS register field value. */
5364 #define ALT_SDMMC_RINTSTS_BDS_CLR_MSK 0xfffffdff
5365 /* The reset value of the ALT_SDMMC_RINTSTS_BDS register field. */
5366 #define ALT_SDMMC_RINTSTS_BDS_RESET 0x0
5367 /* Extracts the ALT_SDMMC_RINTSTS_BDS field value from a register. */
5368 #define ALT_SDMMC_RINTSTS_BDS_GET(value) (((value) & 0x00000200) >> 9)
5369 /* Produces a ALT_SDMMC_RINTSTS_BDS register field value suitable for setting the register. */
5370 #define ALT_SDMMC_RINTSTS_BDS_SET(value) (((value) << 9) & 0x00000200)
5371 
5372 /*
5373  * Field : Data Starvation Host Timeout Volt Switch_int - hto
5374  *
5375  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5376  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5377  *
5378  * Field Enumeration Values:
5379  *
5380  * Enum | Value | Description
5381  * :------------------------------|:------|:---------------------------------------------
5382  * ALT_SDMMC_RINTSTS_HTO_E_INACT | 0x0 | Data starvation-by-host timeout (HTO)
5383  * : | | /Volt_switch_int
5384  * ALT_SDMMC_RINTSTS_HTO_E_ACT | 0x1 | Clears Data starvation-by-host timeout (HTO)
5385  * : | | /Volt_switch_int
5386  *
5387  * Field Access Macros:
5388  *
5389  */
5390 /*
5391  * Enumerated value for register field ALT_SDMMC_RINTSTS_HTO
5392  *
5393  * Data starvation-by-host timeout (HTO) /Volt_switch_int
5394  */
5395 #define ALT_SDMMC_RINTSTS_HTO_E_INACT 0x0
5396 /*
5397  * Enumerated value for register field ALT_SDMMC_RINTSTS_HTO
5398  *
5399  * Clears Data starvation-by-host timeout (HTO) /Volt_switch_int
5400  */
5401 #define ALT_SDMMC_RINTSTS_HTO_E_ACT 0x1
5402 
5403 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_HTO register field. */
5404 #define ALT_SDMMC_RINTSTS_HTO_LSB 10
5405 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_HTO register field. */
5406 #define ALT_SDMMC_RINTSTS_HTO_MSB 10
5407 /* The width in bits of the ALT_SDMMC_RINTSTS_HTO register field. */
5408 #define ALT_SDMMC_RINTSTS_HTO_WIDTH 1
5409 /* The mask used to set the ALT_SDMMC_RINTSTS_HTO register field value. */
5410 #define ALT_SDMMC_RINTSTS_HTO_SET_MSK 0x00000400
5411 /* The mask used to clear the ALT_SDMMC_RINTSTS_HTO register field value. */
5412 #define ALT_SDMMC_RINTSTS_HTO_CLR_MSK 0xfffffbff
5413 /* The reset value of the ALT_SDMMC_RINTSTS_HTO register field. */
5414 #define ALT_SDMMC_RINTSTS_HTO_RESET 0x0
5415 /* Extracts the ALT_SDMMC_RINTSTS_HTO field value from a register. */
5416 #define ALT_SDMMC_RINTSTS_HTO_GET(value) (((value) & 0x00000400) >> 10)
5417 /* Produces a ALT_SDMMC_RINTSTS_HTO register field value suitable for setting the register. */
5418 #define ALT_SDMMC_RINTSTS_HTO_SET(value) (((value) << 10) & 0x00000400)
5419 
5420 /*
5421  * Field : FIFO Underrun Overrun Error - frun
5422  *
5423  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5424  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5425  *
5426  * Field Enumeration Values:
5427  *
5428  * Enum | Value | Description
5429  * :-------------------------------|:------|:-----------------------------------------
5430  * ALT_SDMMC_RINTSTS_FRUN_E_INACT | 0x0 | FIFO underrun/overrun error (FRUN)
5431  * ALT_SDMMC_RINTSTS_FRUN_E_ACT | 0x1 | Clear FIFO underrun/overrun error (FRUN)
5432  *
5433  * Field Access Macros:
5434  *
5435  */
5436 /*
5437  * Enumerated value for register field ALT_SDMMC_RINTSTS_FRUN
5438  *
5439  * FIFO underrun/overrun error (FRUN)
5440  */
5441 #define ALT_SDMMC_RINTSTS_FRUN_E_INACT 0x0
5442 /*
5443  * Enumerated value for register field ALT_SDMMC_RINTSTS_FRUN
5444  *
5445  * Clear FIFO underrun/overrun error (FRUN)
5446  */
5447 #define ALT_SDMMC_RINTSTS_FRUN_E_ACT 0x1
5448 
5449 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_FRUN register field. */
5450 #define ALT_SDMMC_RINTSTS_FRUN_LSB 11
5451 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_FRUN register field. */
5452 #define ALT_SDMMC_RINTSTS_FRUN_MSB 11
5453 /* The width in bits of the ALT_SDMMC_RINTSTS_FRUN register field. */
5454 #define ALT_SDMMC_RINTSTS_FRUN_WIDTH 1
5455 /* The mask used to set the ALT_SDMMC_RINTSTS_FRUN register field value. */
5456 #define ALT_SDMMC_RINTSTS_FRUN_SET_MSK 0x00000800
5457 /* The mask used to clear the ALT_SDMMC_RINTSTS_FRUN register field value. */
5458 #define ALT_SDMMC_RINTSTS_FRUN_CLR_MSK 0xfffff7ff
5459 /* The reset value of the ALT_SDMMC_RINTSTS_FRUN register field. */
5460 #define ALT_SDMMC_RINTSTS_FRUN_RESET 0x0
5461 /* Extracts the ALT_SDMMC_RINTSTS_FRUN field value from a register. */
5462 #define ALT_SDMMC_RINTSTS_FRUN_GET(value) (((value) & 0x00000800) >> 11)
5463 /* Produces a ALT_SDMMC_RINTSTS_FRUN register field value suitable for setting the register. */
5464 #define ALT_SDMMC_RINTSTS_FRUN_SET(value) (((value) << 11) & 0x00000800)
5465 
5466 /*
5467  * Field : Hardware Locked Write Error - hle
5468  *
5469  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5470  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5471  *
5472  * Field Enumeration Values:
5473  *
5474  * Enum | Value | Description
5475  * :------------------------------|:------|:-----------------------------------------
5476  * ALT_SDMMC_RINTSTS_HLE_E_INACT | 0x0 | Hardware locked write error (HLE)
5477  * ALT_SDMMC_RINTSTS_HLE_E_ACT | 0x1 | Clears Hardware locked write error (HLE)
5478  *
5479  * Field Access Macros:
5480  *
5481  */
5482 /*
5483  * Enumerated value for register field ALT_SDMMC_RINTSTS_HLE
5484  *
5485  * Hardware locked write error (HLE)
5486  */
5487 #define ALT_SDMMC_RINTSTS_HLE_E_INACT 0x0
5488 /*
5489  * Enumerated value for register field ALT_SDMMC_RINTSTS_HLE
5490  *
5491  * Clears Hardware locked write error (HLE)
5492  */
5493 #define ALT_SDMMC_RINTSTS_HLE_E_ACT 0x1
5494 
5495 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_HLE register field. */
5496 #define ALT_SDMMC_RINTSTS_HLE_LSB 12
5497 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_HLE register field. */
5498 #define ALT_SDMMC_RINTSTS_HLE_MSB 12
5499 /* The width in bits of the ALT_SDMMC_RINTSTS_HLE register field. */
5500 #define ALT_SDMMC_RINTSTS_HLE_WIDTH 1
5501 /* The mask used to set the ALT_SDMMC_RINTSTS_HLE register field value. */
5502 #define ALT_SDMMC_RINTSTS_HLE_SET_MSK 0x00001000
5503 /* The mask used to clear the ALT_SDMMC_RINTSTS_HLE register field value. */
5504 #define ALT_SDMMC_RINTSTS_HLE_CLR_MSK 0xffffefff
5505 /* The reset value of the ALT_SDMMC_RINTSTS_HLE register field. */
5506 #define ALT_SDMMC_RINTSTS_HLE_RESET 0x0
5507 /* Extracts the ALT_SDMMC_RINTSTS_HLE field value from a register. */
5508 #define ALT_SDMMC_RINTSTS_HLE_GET(value) (((value) & 0x00001000) >> 12)
5509 /* Produces a ALT_SDMMC_RINTSTS_HLE register field value suitable for setting the register. */
5510 #define ALT_SDMMC_RINTSTS_HLE_SET(value) (((value) << 12) & 0x00001000)
5511 
5512 /*
5513  * Field : Start-bit error (SBE) - sbe
5514  *
5515  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5516  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5517  *
5518  * Field Enumeration Values:
5519  *
5520  * Enum | Value | Description
5521  * :------------------------------|:------|:-----------------------------
5522  * ALT_SDMMC_RINTSTS_SBE_E_INACT | 0x0 | Start-bit error (SBE)
5523  * ALT_SDMMC_RINTSTS_SBE_E_ACT | 0x1 | Clears Start-bit error (SBE)
5524  *
5525  * Field Access Macros:
5526  *
5527  */
5528 /*
5529  * Enumerated value for register field ALT_SDMMC_RINTSTS_SBE
5530  *
5531  * Start-bit error (SBE)
5532  */
5533 #define ALT_SDMMC_RINTSTS_SBE_E_INACT 0x0
5534 /*
5535  * Enumerated value for register field ALT_SDMMC_RINTSTS_SBE
5536  *
5537  * Clears Start-bit error (SBE)
5538  */
5539 #define ALT_SDMMC_RINTSTS_SBE_E_ACT 0x1
5540 
5541 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SBE register field. */
5542 #define ALT_SDMMC_RINTSTS_SBE_LSB 13
5543 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SBE register field. */
5544 #define ALT_SDMMC_RINTSTS_SBE_MSB 13
5545 /* The width in bits of the ALT_SDMMC_RINTSTS_SBE register field. */
5546 #define ALT_SDMMC_RINTSTS_SBE_WIDTH 1
5547 /* The mask used to set the ALT_SDMMC_RINTSTS_SBE register field value. */
5548 #define ALT_SDMMC_RINTSTS_SBE_SET_MSK 0x00002000
5549 /* The mask used to clear the ALT_SDMMC_RINTSTS_SBE register field value. */
5550 #define ALT_SDMMC_RINTSTS_SBE_CLR_MSK 0xffffdfff
5551 /* The reset value of the ALT_SDMMC_RINTSTS_SBE register field. */
5552 #define ALT_SDMMC_RINTSTS_SBE_RESET 0x0
5553 /* Extracts the ALT_SDMMC_RINTSTS_SBE field value from a register. */
5554 #define ALT_SDMMC_RINTSTS_SBE_GET(value) (((value) & 0x00002000) >> 13)
5555 /* Produces a ALT_SDMMC_RINTSTS_SBE register field value suitable for setting the register. */
5556 #define ALT_SDMMC_RINTSTS_SBE_SET(value) (((value) << 13) & 0x00002000)
5557 
5558 /*
5559  * Field : Auto Cmommand Done - acd
5560  *
5561  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5562  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5563  *
5564  * Field Enumeration Values:
5565  *
5566  * Enum | Value | Description
5567  * :------------------------------|:------|:-----------------------------
5568  * ALT_SDMMC_RINTSTS_ACD_E_INACT | 0x0 | Auto command done (ACD)
5569  * ALT_SDMMC_RINTSTS_ACD_E_ACT | 0x1 | Clear Auto command done (ACD
5570  *
5571  * Field Access Macros:
5572  *
5573  */
5574 /*
5575  * Enumerated value for register field ALT_SDMMC_RINTSTS_ACD
5576  *
5577  * Auto command done (ACD)
5578  */
5579 #define ALT_SDMMC_RINTSTS_ACD_E_INACT 0x0
5580 /*
5581  * Enumerated value for register field ALT_SDMMC_RINTSTS_ACD
5582  *
5583  * Clear Auto command done (ACD
5584  */
5585 #define ALT_SDMMC_RINTSTS_ACD_E_ACT 0x1
5586 
5587 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_ACD register field. */
5588 #define ALT_SDMMC_RINTSTS_ACD_LSB 14
5589 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_ACD register field. */
5590 #define ALT_SDMMC_RINTSTS_ACD_MSB 14
5591 /* The width in bits of the ALT_SDMMC_RINTSTS_ACD register field. */
5592 #define ALT_SDMMC_RINTSTS_ACD_WIDTH 1
5593 /* The mask used to set the ALT_SDMMC_RINTSTS_ACD register field value. */
5594 #define ALT_SDMMC_RINTSTS_ACD_SET_MSK 0x00004000
5595 /* The mask used to clear the ALT_SDMMC_RINTSTS_ACD register field value. */
5596 #define ALT_SDMMC_RINTSTS_ACD_CLR_MSK 0xffffbfff
5597 /* The reset value of the ALT_SDMMC_RINTSTS_ACD register field. */
5598 #define ALT_SDMMC_RINTSTS_ACD_RESET 0x0
5599 /* Extracts the ALT_SDMMC_RINTSTS_ACD field value from a register. */
5600 #define ALT_SDMMC_RINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14)
5601 /* Produces a ALT_SDMMC_RINTSTS_ACD register field value suitable for setting the register. */
5602 #define ALT_SDMMC_RINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000)
5603 
5604 /*
5605  * Field : End-bit Error - ebe
5606  *
5607  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5608  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5609  *
5610  * Field Enumeration Values:
5611  *
5612  * Enum | Value | Description
5613  * :------------------------------|:------|:-----------------------------------------------
5614  * ALT_SDMMC_RINTSTS_EBE_E_INACT | 0x0 | End-bit error (read)/write no CRC (EBE)
5615  * ALT_SDMMC_RINTSTS_EBE_E_ACT | 0x1 | Clears End-bit error (read)/write no CRC (EBE)
5616  *
5617  * Field Access Macros:
5618  *
5619  */
5620 /*
5621  * Enumerated value for register field ALT_SDMMC_RINTSTS_EBE
5622  *
5623  * End-bit error (read)/write no CRC (EBE)
5624  */
5625 #define ALT_SDMMC_RINTSTS_EBE_E_INACT 0x0
5626 /*
5627  * Enumerated value for register field ALT_SDMMC_RINTSTS_EBE
5628  *
5629  * Clears End-bit error (read)/write no CRC (EBE)
5630  */
5631 #define ALT_SDMMC_RINTSTS_EBE_E_ACT 0x1
5632 
5633 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_EBE register field. */
5634 #define ALT_SDMMC_RINTSTS_EBE_LSB 15
5635 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_EBE register field. */
5636 #define ALT_SDMMC_RINTSTS_EBE_MSB 15
5637 /* The width in bits of the ALT_SDMMC_RINTSTS_EBE register field. */
5638 #define ALT_SDMMC_RINTSTS_EBE_WIDTH 1
5639 /* The mask used to set the ALT_SDMMC_RINTSTS_EBE register field value. */
5640 #define ALT_SDMMC_RINTSTS_EBE_SET_MSK 0x00008000
5641 /* The mask used to clear the ALT_SDMMC_RINTSTS_EBE register field value. */
5642 #define ALT_SDMMC_RINTSTS_EBE_CLR_MSK 0xffff7fff
5643 /* The reset value of the ALT_SDMMC_RINTSTS_EBE register field. */
5644 #define ALT_SDMMC_RINTSTS_EBE_RESET 0x0
5645 /* Extracts the ALT_SDMMC_RINTSTS_EBE field value from a register. */
5646 #define ALT_SDMMC_RINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15)
5647 /* Produces a ALT_SDMMC_RINTSTS_EBE register field value suitable for setting the register. */
5648 #define ALT_SDMMC_RINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000)
5649 
5650 /*
5651  * Field : sdio_interrupt
5652  *
5653  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
5654  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
5655  * 1 clears bit and 0 leaves bit intact.
5656  *
5657  * 0-No SDIO interrupt from card
5658  *
5659  * 1-SDIO interrupt from card
5660  *
5661  * In MMC-Ver3.3-only mode, bits always 0.
5662  *
5663  * Bits are logged regardless of interrupt-mask status.
5664  *
5665  * Field Enumeration Values:
5666  *
5667  * Enum | Value | Description
5668  * :-----------------------------------|:------|:-------------------------------
5669  * ALT_SDMMC_RINTSTS_SDIO_INT_E_INACT | 0x0 | No SDIO interrupt from card bi
5670  * ALT_SDMMC_RINTSTS_SDIO_INT_E_ACT | 0x1 | SDIO interrupt from card bit
5671  *
5672  * Field Access Macros:
5673  *
5674  */
5675 /*
5676  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INT
5677  *
5678  * No SDIO interrupt from card bi
5679  */
5680 #define ALT_SDMMC_RINTSTS_SDIO_INT_E_INACT 0x0
5681 /*
5682  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INT
5683  *
5684  * SDIO interrupt from card bit
5685  */
5686 #define ALT_SDMMC_RINTSTS_SDIO_INT_E_ACT 0x1
5687 
5688 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INT register field. */
5689 #define ALT_SDMMC_RINTSTS_SDIO_INT_LSB 16
5690 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INT register field. */
5691 #define ALT_SDMMC_RINTSTS_SDIO_INT_MSB 31
5692 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INT register field. */
5693 #define ALT_SDMMC_RINTSTS_SDIO_INT_WIDTH 16
5694 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INT register field value. */
5695 #define ALT_SDMMC_RINTSTS_SDIO_INT_SET_MSK 0xffff0000
5696 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INT register field value. */
5697 #define ALT_SDMMC_RINTSTS_SDIO_INT_CLR_MSK 0x0000ffff
5698 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INT register field. */
5699 #define ALT_SDMMC_RINTSTS_SDIO_INT_RESET 0x0
5700 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INT field value from a register. */
5701 #define ALT_SDMMC_RINTSTS_SDIO_INT_GET(value) (((value) & 0xffff0000) >> 16)
5702 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INT register field value suitable for setting the register. */
5703 #define ALT_SDMMC_RINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0xffff0000)
5704 
5705 #ifndef __ASSEMBLY__
5706 /*
5707  * WARNING: The C register and register group struct declarations are provided for
5708  * convenience and illustrative purposes. They should, however, be used with
5709  * caution as the C language standard provides no guarantees about the alignment or
5710  * atomicity of device memory accesses. The recommended practice for writing
5711  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5712  * alt_write_word() functions.
5713  *
5714  * The struct declaration for register ALT_SDMMC_RINTSTS.
5715  */
5716 struct ALT_SDMMC_RINTSTS_s
5717 {
5718  uint32_t cd : 1; /* Card Detect */
5719  uint32_t re : 1; /* Response Error */
5720  uint32_t cmd : 1; /* Command Done */
5721  uint32_t dto : 1; /* Data Transfer Over */
5722  uint32_t txdr : 1; /* Transmit FIFO Data Request */
5723  uint32_t rxdr : 1; /* Receive FIFO Data Request */
5724  uint32_t rcrc : 1; /* Response CRC Error */
5725  uint32_t dcrc : 1; /* Data CRC Error */
5726  uint32_t bar : 1; /* Response Timeout Boot Ack Received */
5727  uint32_t bds : 1; /* Data Read Timeout Boot Data Start */
5728  uint32_t hto : 1; /* Data Starvation Host Timeout Volt Switch_int */
5729  uint32_t frun : 1; /* FIFO Underrun Overrun Error */
5730  uint32_t hle : 1; /* Hardware Locked Write Error */
5731  uint32_t sbe : 1; /* Start-bit error (SBE) */
5732  uint32_t acd : 1; /* Auto Cmommand Done */
5733  uint32_t ebe : 1; /* End-bit Error */
5734  uint32_t sdio_interrupt : 16; /* ALT_SDMMC_RINTSTS_SDIO_INT */
5735 };
5736 
5737 /* The typedef declaration for register ALT_SDMMC_RINTSTS. */
5738 typedef volatile struct ALT_SDMMC_RINTSTS_s ALT_SDMMC_RINTSTS_t;
5739 #endif /* __ASSEMBLY__ */
5740 
5741 /* The reset value of the ALT_SDMMC_RINTSTS register. */
5742 #define ALT_SDMMC_RINTSTS_RESET 0x00000000
5743 /* The byte offset of the ALT_SDMMC_RINTSTS register from the beginning of the component. */
5744 #define ALT_SDMMC_RINTSTS_OFST 0x44
5745 
5746 /*
5747  * Register : status
5748  *
5749  * Status Register
5750  *
5751  * Register Layout
5752  *
5753  * Bits | Access | Reset | Description
5754  * :--------|:-------|:------|:----------------------------------
5755  * [0] | R | 0x0 | ALT_SDMMC_STAT_FIFO_RX_WATERMARK
5756  * [1] | R | 0x1 | ALT_SDMMC_STAT_FIFO_TX_WATERMARK
5757  * [2] | R | 0x1 | ALT_SDMMC_STAT_FIFO_EMPTY
5758  * [3] | R | 0x0 | ALT_SDMMC_STAT_FIFO_FULL
5759  * [7:4] | R | 0x0 | ALT_SDMMC_STAT_CMD_FSM_STATES
5760  * [8] | R | 0x1 | ALT_SDMMC_STAT_DATA_3_STAT
5761  * [9] | R | 0x0 | ALT_SDMMC_STAT_DATA_BUSY
5762  * [10] | R | 0x0 | ALT_SDMMC_STAT_DATA_STATE_MC_BUSY
5763  * [16:11] | R | 0x0 | ALT_SDMMC_STAT_RESPONSE_INDEX
5764  * [29:17] | R | 0x0 | ALT_SDMMC_STAT_FIFO_COUNT
5765  * [30] | R | 0x0 | ALT_SDMMC_STAT_DMA_ACK
5766  * [31] | R | 0x0 | ALT_SDMMC_STAT_DMA_REQ
5767  *
5768  */
5769 /*
5770  * Field : fifo_rx_watermark
5771  *
5772  * FIFO reached Receive watermark level; not qualified with data
5773  *
5774  * transfer.
5775  *
5776  * Field Enumeration Values:
5777  *
5778  * Enum | Value | Description
5779  * :-------------------------------------------------|:------|:-------------------------------------------------
5780  * ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_RXWATERMARK | 0x0 | FIFO reached watermark level; not qualified with
5781  * : | | data transfer.
5782  * ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_NORXWATERMARK | 0x1 | FIFO not at watermark Level
5783  *
5784  * Field Access Macros:
5785  *
5786  */
5787 /*
5788  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_RX_WATERMARK
5789  *
5790  * FIFO reached watermark level; not qualified with data transfer.
5791  */
5792 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_RXWATERMARK 0x0
5793 /*
5794  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_RX_WATERMARK
5795  *
5796  * FIFO not at watermark Level
5797  */
5798 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_NORXWATERMARK 0x1
5799 
5800 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field. */
5801 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_LSB 0
5802 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field. */
5803 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_MSB 0
5804 /* The width in bits of the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field. */
5805 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_WIDTH 1
5806 /* The mask used to set the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field value. */
5807 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET_MSK 0x00000001
5808 /* The mask used to clear the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field value. */
5809 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_CLR_MSK 0xfffffffe
5810 /* The reset value of the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field. */
5811 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_RESET 0x0
5812 /* Extracts the ALT_SDMMC_STAT_FIFO_RX_WATERMARK field value from a register. */
5813 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_GET(value) (((value) & 0x00000001) >> 0)
5814 /* Produces a ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field value suitable for setting the register. */
5815 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET(value) (((value) << 0) & 0x00000001)
5816 
5817 /*
5818  * Field : fifo_tx_watermark
5819  *
5820  * FIFO reached Transmit watermark level; not qualified with data
5821  *
5822  * transfer.
5823  *
5824  * Field Enumeration Values:
5825  *
5826  * Enum | Value | Description
5827  * :-------------------------------------------------|:------|:-------------------------------------------
5828  * ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_NOTXWATERMARK | 0x0 | FIFO not at transmit watermark Level
5829  * ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_TXWATERMARK | 0x1 | FIFO reached transmit watermark level: not
5830  * : | | qualified with data transfer.
5831  *
5832  * Field Access Macros:
5833  *
5834  */
5835 /*
5836  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_TX_WATERMARK
5837  *
5838  * FIFO not at transmit watermark Level
5839  */
5840 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_NOTXWATERMARK 0x0
5841 /*
5842  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_TX_WATERMARK
5843  *
5844  * FIFO reached transmit watermark level: not qualified with data transfer.
5845  */
5846 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_TXWATERMARK 0x1
5847 
5848 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field. */
5849 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_LSB 1
5850 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field. */
5851 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_MSB 1
5852 /* The width in bits of the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field. */
5853 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_WIDTH 1
5854 /* The mask used to set the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field value. */
5855 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET_MSK 0x00000002
5856 /* The mask used to clear the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field value. */
5857 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_CLR_MSK 0xfffffffd
5858 /* The reset value of the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field. */
5859 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_RESET 0x1
5860 /* Extracts the ALT_SDMMC_STAT_FIFO_TX_WATERMARK field value from a register. */
5861 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_GET(value) (((value) & 0x00000002) >> 1)
5862 /* Produces a ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field value suitable for setting the register. */
5863 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET(value) (((value) << 1) & 0x00000002)
5864 
5865 /*
5866  * Field : fifo_empty
5867  *
5868  * FIFO is empty status
5869  *
5870  * Field Enumeration Values:
5871  *
5872  * Enum | Value | Description
5873  * :-----------------------------------------|:------|:---------------
5874  * ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFONOTEMPTY | 0x0 | FIFO not empty
5875  * ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFOEMPTY | 0x1 | FIFO is empty
5876  *
5877  * Field Access Macros:
5878  *
5879  */
5880 /*
5881  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_EMPTY
5882  *
5883  * FIFO not empty
5884  */
5885 #define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFONOTEMPTY 0x0
5886 /*
5887  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_EMPTY
5888  *
5889  * FIFO is empty
5890  */
5891 #define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFOEMPTY 0x1
5892 
5893 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_EMPTY register field. */
5894 #define ALT_SDMMC_STAT_FIFO_EMPTY_LSB 2
5895 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_EMPTY register field. */
5896 #define ALT_SDMMC_STAT_FIFO_EMPTY_MSB 2
5897 /* The width in bits of the ALT_SDMMC_STAT_FIFO_EMPTY register field. */
5898 #define ALT_SDMMC_STAT_FIFO_EMPTY_WIDTH 1
5899 /* The mask used to set the ALT_SDMMC_STAT_FIFO_EMPTY register field value. */
5900 #define ALT_SDMMC_STAT_FIFO_EMPTY_SET_MSK 0x00000004
5901 /* The mask used to clear the ALT_SDMMC_STAT_FIFO_EMPTY register field value. */
5902 #define ALT_SDMMC_STAT_FIFO_EMPTY_CLR_MSK 0xfffffffb
5903 /* The reset value of the ALT_SDMMC_STAT_FIFO_EMPTY register field. */
5904 #define ALT_SDMMC_STAT_FIFO_EMPTY_RESET 0x1
5905 /* Extracts the ALT_SDMMC_STAT_FIFO_EMPTY field value from a register. */
5906 #define ALT_SDMMC_STAT_FIFO_EMPTY_GET(value) (((value) & 0x00000004) >> 2)
5907 /* Produces a ALT_SDMMC_STAT_FIFO_EMPTY register field value suitable for setting the register. */
5908 #define ALT_SDMMC_STAT_FIFO_EMPTY_SET(value) (((value) << 2) & 0x00000004)
5909 
5910 /*
5911  * Field : fifo_full
5912  *
5913  * FIFO is full status
5914  *
5915  * Field Enumeration Values:
5916  *
5917  * Enum | Value | Description
5918  * :---------------------------------------|:------|:-----------------
5919  * ALT_SDMMC_STAT_FIFO_FULL_E_FIFONOTFULL | 0x0 | FIFO is not full
5920  * ALT_SDMMC_STAT_FIFO_FULL_E_FIFOFULL | 0x1 | FIFO is full
5921  *
5922  * Field Access Macros:
5923  *
5924  */
5925 /*
5926  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_FULL
5927  *
5928  * FIFO is not full
5929  */
5930 #define ALT_SDMMC_STAT_FIFO_FULL_E_FIFONOTFULL 0x0
5931 /*
5932  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_FULL
5933  *
5934  * FIFO is full
5935  */
5936 #define ALT_SDMMC_STAT_FIFO_FULL_E_FIFOFULL 0x1
5937 
5938 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_FULL register field. */
5939 #define ALT_SDMMC_STAT_FIFO_FULL_LSB 3
5940 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_FULL register field. */
5941 #define ALT_SDMMC_STAT_FIFO_FULL_MSB 3
5942 /* The width in bits of the ALT_SDMMC_STAT_FIFO_FULL register field. */
5943 #define ALT_SDMMC_STAT_FIFO_FULL_WIDTH 1
5944 /* The mask used to set the ALT_SDMMC_STAT_FIFO_FULL register field value. */
5945 #define ALT_SDMMC_STAT_FIFO_FULL_SET_MSK 0x00000008
5946 /* The mask used to clear the ALT_SDMMC_STAT_FIFO_FULL register field value. */
5947 #define ALT_SDMMC_STAT_FIFO_FULL_CLR_MSK 0xfffffff7
5948 /* The reset value of the ALT_SDMMC_STAT_FIFO_FULL register field. */
5949 #define ALT_SDMMC_STAT_FIFO_FULL_RESET 0x0
5950 /* Extracts the ALT_SDMMC_STAT_FIFO_FULL field value from a register. */
5951 #define ALT_SDMMC_STAT_FIFO_FULL_GET(value) (((value) & 0x00000008) >> 3)
5952 /* Produces a ALT_SDMMC_STAT_FIFO_FULL register field value suitable for setting the register. */
5953 #define ALT_SDMMC_STAT_FIFO_FULL_SET(value) (((value) << 3) & 0x00000008)
5954 
5955 /*
5956  * Field : command_fsm_states
5957  *
5958  * Command FSM states:
5959  *
5960  * 0 Idle
5961  *
5962  * 1 Send init sequence
5963  *
5964  * 2 Tx cmd start bit
5965  *
5966  * 3 Tx cmd tx bit
5967  *
5968  * 4 Tx cmd index + arg
5969  *
5970  * 5 Tx cmd crc7
5971  *
5972  * 6 Tx cmd end bit
5973  *
5974  * 7 Rx resp start bit
5975  *
5976  * 8 Rx resp IRQ response
5977  *
5978  * 9 Rx resp tx bit
5979  *
5980  * 10 Rx resp cmd idx
5981  *
5982  * 11 Rx resp data
5983  *
5984  * 12 Rx resp crc7
5985  *
5986  * 13 Rx resp end bit
5987  *
5988  * 14 Cmd path wait NCC
5989  *
5990  * 15 Wait; CMD-to-response turnaround
5991  *
5992  * NOTE: The command FSM state is represented using 19 bits. The STATUS
5993  * Register(7:4) has 4 bits to represent the command FSM states. Using these 4
5994  * bits, only 16 states can be represented. Thus three states cannot be represented
5995  * in the STATUS(7:4) register. The three states that are not represented in the
5996  * STATUS Register(7:4) are:
5997  *
5998  * * Bit 16 Wait for CCS
5999  *
6000  * * Bit 17 Send CCSD
6001  *
6002  * * Bit 18 Boot Mode
6003  *
6004  * Due to this, while command FSM is in "Wait for CCS state" or "Send CCSD" or
6005  * "Boot Mode", the Status register indicates status as 0 for the bit field 7:4.
6006  *
6007  * Field Enumeration Values:
6008  *
6009  * Enum | Value | Description
6010  * :----------------------------------------------|:------|:--------------------------------------------
6011  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_IDLEANDOTHERS | 0x0 | Idle, Wait for CCS, Send CCSD, or Boot Mode
6012  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_SENDINITSEQ | 0x1 | Send init sequence
6013  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDSTART | 0x2 | Tx cmd start bit
6014  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDTXBIT | 0x3 | Tx cmd tx bit
6015  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDINDXARG | 0x4 | Tx cmd index + arg
6016  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDCRC7 | 0x5 | Tx cmd crc7
6017  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDEND | 0x6 | Tx cmd end bit
6018  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPSTART | 0x7 | Rx resp start bit
6019  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPIRQ | 0x8 | Rx resp IRQ response
6020  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPTX | 0x9 | Rx resp tx bit
6021  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCMDIDX | 0xa | Rx resp cmd idx
6022  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPDATA | 0xb | Rx resp data
6023  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCRC7 | 0xc | Rx resp crc7
6024  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPEND | 0xd | Rx resp end bit
6025  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_CMDPATHWAIT | 0xe | Cmd path wait NCC
6026  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_WAITCMDTURN | 0xf | Wait: CMD-to-reponse turnaround
6027  *
6028  * Field Access Macros:
6029  *
6030  */
6031 /*
6032  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6033  *
6034  * Idle, Wait for CCS, Send CCSD, or Boot Mode
6035  */
6036 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_IDLEANDOTHERS 0x0
6037 /*
6038  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6039  *
6040  * Send init sequence
6041  */
6042 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_SENDINITSEQ 0x1
6043 /*
6044  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6045  *
6046  * Tx cmd start bit
6047  */
6048 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDSTART 0x2
6049 /*
6050  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6051  *
6052  * Tx cmd tx bit
6053  */
6054 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDTXBIT 0x3
6055 /*
6056  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6057  *
6058  * Tx cmd index + arg
6059  */
6060 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDINDXARG 0x4
6061 /*
6062  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6063  *
6064  * Tx cmd crc7
6065  */
6066 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDCRC7 0x5
6067 /*
6068  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6069  *
6070  * Tx cmd end bit
6071  */
6072 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDEND 0x6
6073 /*
6074  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6075  *
6076  * Rx resp start bit
6077  */
6078 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPSTART 0x7
6079 /*
6080  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6081  *
6082  * Rx resp IRQ response
6083  */
6084 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPIRQ 0x8
6085 /*
6086  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6087  *
6088  * Rx resp tx bit
6089  */
6090 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPTX 0x9
6091 /*
6092  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6093  *
6094  * Rx resp cmd idx
6095  */
6096 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCMDIDX 0xa
6097 /*
6098  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6099  *
6100  * Rx resp data
6101  */
6102 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPDATA 0xb
6103 /*
6104  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6105  *
6106  * Rx resp crc7
6107  */
6108 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCRC7 0xc
6109 /*
6110  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6111  *
6112  * Rx resp end bit
6113  */
6114 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPEND 0xd
6115 /*
6116  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6117  *
6118  * Cmd path wait NCC
6119  */
6120 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_CMDPATHWAIT 0xe
6121 /*
6122  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
6123  *
6124  * Wait: CMD-to-reponse turnaround
6125  */
6126 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_WAITCMDTURN 0xf
6127 
6128 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_CMD_FSM_STATES register field. */
6129 #define ALT_SDMMC_STAT_CMD_FSM_STATES_LSB 4
6130 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_CMD_FSM_STATES register field. */
6131 #define ALT_SDMMC_STAT_CMD_FSM_STATES_MSB 7
6132 /* The width in bits of the ALT_SDMMC_STAT_CMD_FSM_STATES register field. */
6133 #define ALT_SDMMC_STAT_CMD_FSM_STATES_WIDTH 4
6134 /* The mask used to set the ALT_SDMMC_STAT_CMD_FSM_STATES register field value. */
6135 #define ALT_SDMMC_STAT_CMD_FSM_STATES_SET_MSK 0x000000f0
6136 /* The mask used to clear the ALT_SDMMC_STAT_CMD_FSM_STATES register field value. */
6137 #define ALT_SDMMC_STAT_CMD_FSM_STATES_CLR_MSK 0xffffff0f
6138 /* The reset value of the ALT_SDMMC_STAT_CMD_FSM_STATES register field. */
6139 #define ALT_SDMMC_STAT_CMD_FSM_STATES_RESET 0x0
6140 /* Extracts the ALT_SDMMC_STAT_CMD_FSM_STATES field value from a register. */
6141 #define ALT_SDMMC_STAT_CMD_FSM_STATES_GET(value) (((value) & 0x000000f0) >> 4)
6142 /* Produces a ALT_SDMMC_STAT_CMD_FSM_STATES register field value suitable for setting the register. */
6143 #define ALT_SDMMC_STAT_CMD_FSM_STATES_SET(value) (((value) << 4) & 0x000000f0)
6144 
6145 /*
6146  * Field : data_3_status
6147  *
6148  * Raw selected card_data[3]; checks whether card is present
6149  *
6150  * 0-card not present
6151  *
6152  * 1-card present
6153  *
6154  * Field Enumeration Values:
6155  *
6156  * Enum | Value | Description
6157  * :--------------------------------------------|:------|:-----------------
6158  * ALT_SDMMC_STAT_DATA_3_STAT_E_CARDNOTPRESENT | 0x0 | Card Not Present
6159  * ALT_SDMMC_STAT_DATA_3_STAT_E_CARDPRESENT | 0x1 | Card Present
6160  *
6161  * Field Access Macros:
6162  *
6163  */
6164 /*
6165  * Enumerated value for register field ALT_SDMMC_STAT_DATA_3_STAT
6166  *
6167  * Card Not Present
6168  */
6169 #define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDNOTPRESENT 0x0
6170 /*
6171  * Enumerated value for register field ALT_SDMMC_STAT_DATA_3_STAT
6172  *
6173  * Card Present
6174  */
6175 #define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDPRESENT 0x1
6176 
6177 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_DATA_3_STAT register field. */
6178 #define ALT_SDMMC_STAT_DATA_3_STAT_LSB 8
6179 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_DATA_3_STAT register field. */
6180 #define ALT_SDMMC_STAT_DATA_3_STAT_MSB 8
6181 /* The width in bits of the ALT_SDMMC_STAT_DATA_3_STAT register field. */
6182 #define ALT_SDMMC_STAT_DATA_3_STAT_WIDTH 1
6183 /* The mask used to set the ALT_SDMMC_STAT_DATA_3_STAT register field value. */
6184 #define ALT_SDMMC_STAT_DATA_3_STAT_SET_MSK 0x00000100
6185 /* The mask used to clear the ALT_SDMMC_STAT_DATA_3_STAT register field value. */
6186 #define ALT_SDMMC_STAT_DATA_3_STAT_CLR_MSK 0xfffffeff
6187 /* The reset value of the ALT_SDMMC_STAT_DATA_3_STAT register field. */
6188 #define ALT_SDMMC_STAT_DATA_3_STAT_RESET 0x1
6189 /* Extracts the ALT_SDMMC_STAT_DATA_3_STAT field value from a register. */
6190 #define ALT_SDMMC_STAT_DATA_3_STAT_GET(value) (((value) & 0x00000100) >> 8)
6191 /* Produces a ALT_SDMMC_STAT_DATA_3_STAT register field value suitable for setting the register. */
6192 #define ALT_SDMMC_STAT_DATA_3_STAT_SET(value) (((value) << 8) & 0x00000100)
6193 
6194 /*
6195  * Field : data_busy
6196  *
6197  * Inverted version of raw selected card_data[0]
6198  *
6199  * 0-card data not busy
6200  *
6201  * 1-card data busy
6202  *
6203  * Field Enumeration Values:
6204  *
6205  * Enum | Value | Description
6206  * :---------------------------------------|:------|:-------------------
6207  * ALT_SDMMC_STAT_DATA_BUSY_E_CARDNOTBUSY | 0x0 | card data not busy
6208  * ALT_SDMMC_STAT_DATA_BUSY_E_CARDBUSY | 0x1 | card data busy
6209  *
6210  * Field Access Macros:
6211  *
6212  */
6213 /*
6214  * Enumerated value for register field ALT_SDMMC_STAT_DATA_BUSY
6215  *
6216  * card data not busy
6217  */
6218 #define ALT_SDMMC_STAT_DATA_BUSY_E_CARDNOTBUSY 0x0
6219 /*
6220  * Enumerated value for register field ALT_SDMMC_STAT_DATA_BUSY
6221  *
6222  * card data busy
6223  */
6224 #define ALT_SDMMC_STAT_DATA_BUSY_E_CARDBUSY 0x1
6225 
6226 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_DATA_BUSY register field. */
6227 #define ALT_SDMMC_STAT_DATA_BUSY_LSB 9
6228 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_DATA_BUSY register field. */
6229 #define ALT_SDMMC_STAT_DATA_BUSY_MSB 9
6230 /* The width in bits of the ALT_SDMMC_STAT_DATA_BUSY register field. */
6231 #define ALT_SDMMC_STAT_DATA_BUSY_WIDTH 1
6232 /* The mask used to set the ALT_SDMMC_STAT_DATA_BUSY register field value. */
6233 #define ALT_SDMMC_STAT_DATA_BUSY_SET_MSK 0x00000200
6234 /* The mask used to clear the ALT_SDMMC_STAT_DATA_BUSY register field value. */
6235 #define ALT_SDMMC_STAT_DATA_BUSY_CLR_MSK 0xfffffdff
6236 /* The reset value of the ALT_SDMMC_STAT_DATA_BUSY register field. */
6237 #define ALT_SDMMC_STAT_DATA_BUSY_RESET 0x0
6238 /* Extracts the ALT_SDMMC_STAT_DATA_BUSY field value from a register. */
6239 #define ALT_SDMMC_STAT_DATA_BUSY_GET(value) (((value) & 0x00000200) >> 9)
6240 /* Produces a ALT_SDMMC_STAT_DATA_BUSY register field value suitable for setting the register. */
6241 #define ALT_SDMMC_STAT_DATA_BUSY_SET(value) (((value) << 9) & 0x00000200)
6242 
6243 /*
6244  * Field : data_state_mc_busy
6245  *
6246  * Data transmit or receive state-machine is busy
6247  *
6248  * Field Enumeration Values:
6249  *
6250  * Enum | Value | Description
6251  * :----------------------------------------------------|:------|:-----------------------
6252  * ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATENOTBSY | 0x0 | Data State MC not busy
6253  * ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATEBSY | 0x1 | Data State MC busy
6254  *
6255  * Field Access Macros:
6256  *
6257  */
6258 /*
6259  * Enumerated value for register field ALT_SDMMC_STAT_DATA_STATE_MC_BUSY
6260  *
6261  * Data State MC not busy
6262  */
6263 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATENOTBSY 0x0
6264 /*
6265  * Enumerated value for register field ALT_SDMMC_STAT_DATA_STATE_MC_BUSY
6266  *
6267  * Data State MC busy
6268  */
6269 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATEBSY 0x1
6270 
6271 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field. */
6272 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_LSB 10
6273 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field. */
6274 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_MSB 10
6275 /* The width in bits of the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field. */
6276 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_WIDTH 1
6277 /* The mask used to set the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field value. */
6278 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET_MSK 0x00000400
6279 /* The mask used to clear the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field value. */
6280 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_CLR_MSK 0xfffffbff
6281 /* The reset value of the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field. */
6282 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_RESET 0x0
6283 /* Extracts the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY field value from a register. */
6284 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_GET(value) (((value) & 0x00000400) >> 10)
6285 /* Produces a ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field value suitable for setting the register. */
6286 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET(value) (((value) << 10) & 0x00000400)
6287 
6288 /*
6289  * Field : response_index
6290  *
6291  * Index of previous response, including any auto-stop sent by core
6292  *
6293  * Field Access Macros:
6294  *
6295  */
6296 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_RESPONSE_INDEX register field. */
6297 #define ALT_SDMMC_STAT_RESPONSE_INDEX_LSB 11
6298 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_RESPONSE_INDEX register field. */
6299 #define ALT_SDMMC_STAT_RESPONSE_INDEX_MSB 16
6300 /* The width in bits of the ALT_SDMMC_STAT_RESPONSE_INDEX register field. */
6301 #define ALT_SDMMC_STAT_RESPONSE_INDEX_WIDTH 6
6302 /* The mask used to set the ALT_SDMMC_STAT_RESPONSE_INDEX register field value. */
6303 #define ALT_SDMMC_STAT_RESPONSE_INDEX_SET_MSK 0x0001f800
6304 /* The mask used to clear the ALT_SDMMC_STAT_RESPONSE_INDEX register field value. */
6305 #define ALT_SDMMC_STAT_RESPONSE_INDEX_CLR_MSK 0xfffe07ff
6306 /* The reset value of the ALT_SDMMC_STAT_RESPONSE_INDEX register field. */
6307 #define ALT_SDMMC_STAT_RESPONSE_INDEX_RESET 0x0
6308 /* Extracts the ALT_SDMMC_STAT_RESPONSE_INDEX field value from a register. */
6309 #define ALT_SDMMC_STAT_RESPONSE_INDEX_GET(value) (((value) & 0x0001f800) >> 11)
6310 /* Produces a ALT_SDMMC_STAT_RESPONSE_INDEX register field value suitable for setting the register. */
6311 #define ALT_SDMMC_STAT_RESPONSE_INDEX_SET(value) (((value) << 11) & 0x0001f800)
6312 
6313 /*
6314  * Field : fifo_count
6315  *
6316  * FIFO count Number of filled locations in FIFO
6317  *
6318  * Field Access Macros:
6319  *
6320  */
6321 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_COUNT register field. */
6322 #define ALT_SDMMC_STAT_FIFO_COUNT_LSB 17
6323 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_COUNT register field. */
6324 #define ALT_SDMMC_STAT_FIFO_COUNT_MSB 29
6325 /* The width in bits of the ALT_SDMMC_STAT_FIFO_COUNT register field. */
6326 #define ALT_SDMMC_STAT_FIFO_COUNT_WIDTH 13
6327 /* The mask used to set the ALT_SDMMC_STAT_FIFO_COUNT register field value. */
6328 #define ALT_SDMMC_STAT_FIFO_COUNT_SET_MSK 0x3ffe0000
6329 /* The mask used to clear the ALT_SDMMC_STAT_FIFO_COUNT register field value. */
6330 #define ALT_SDMMC_STAT_FIFO_COUNT_CLR_MSK 0xc001ffff
6331 /* The reset value of the ALT_SDMMC_STAT_FIFO_COUNT register field. */
6332 #define ALT_SDMMC_STAT_FIFO_COUNT_RESET 0x0
6333 /* Extracts the ALT_SDMMC_STAT_FIFO_COUNT field value from a register. */
6334 #define ALT_SDMMC_STAT_FIFO_COUNT_GET(value) (((value) & 0x3ffe0000) >> 17)
6335 /* Produces a ALT_SDMMC_STAT_FIFO_COUNT register field value suitable for setting the register. */
6336 #define ALT_SDMMC_STAT_FIFO_COUNT_SET(value) (((value) << 17) & 0x3ffe0000)
6337 
6338 /*
6339  * Field : dma_ack
6340  *
6341  * DMA acknowledge signal state; either dw_dma_ack or
6342  *
6343  * ge_dma_ack, depending on DW-DMA or Generic-DMA selection.
6344  *
6345  * Field Access Macros:
6346  *
6347  */
6348 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_DMA_ACK register field. */
6349 #define ALT_SDMMC_STAT_DMA_ACK_LSB 30
6350 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_DMA_ACK register field. */
6351 #define ALT_SDMMC_STAT_DMA_ACK_MSB 30
6352 /* The width in bits of the ALT_SDMMC_STAT_DMA_ACK register field. */
6353 #define ALT_SDMMC_STAT_DMA_ACK_WIDTH 1
6354 /* The mask used to set the ALT_SDMMC_STAT_DMA_ACK register field value. */
6355 #define ALT_SDMMC_STAT_DMA_ACK_SET_MSK 0x40000000
6356 /* The mask used to clear the ALT_SDMMC_STAT_DMA_ACK register field value. */
6357 #define ALT_SDMMC_STAT_DMA_ACK_CLR_MSK 0xbfffffff
6358 /* The reset value of the ALT_SDMMC_STAT_DMA_ACK register field. */
6359 #define ALT_SDMMC_STAT_DMA_ACK_RESET 0x0
6360 /* Extracts the ALT_SDMMC_STAT_DMA_ACK field value from a register. */
6361 #define ALT_SDMMC_STAT_DMA_ACK_GET(value) (((value) & 0x40000000) >> 30)
6362 /* Produces a ALT_SDMMC_STAT_DMA_ACK register field value suitable for setting the register. */
6363 #define ALT_SDMMC_STAT_DMA_ACK_SET(value) (((value) << 30) & 0x40000000)
6364 
6365 /*
6366  * Field : dma_req
6367  *
6368  * DMA request signal state; either dw_dma_req or ge_dma_req,
6369  *
6370  * depending on DW-DMA or Generic-DMA selection.
6371  *
6372  * Field Access Macros:
6373  *
6374  */
6375 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_DMA_REQ register field. */
6376 #define ALT_SDMMC_STAT_DMA_REQ_LSB 31
6377 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_DMA_REQ register field. */
6378 #define ALT_SDMMC_STAT_DMA_REQ_MSB 31
6379 /* The width in bits of the ALT_SDMMC_STAT_DMA_REQ register field. */
6380 #define ALT_SDMMC_STAT_DMA_REQ_WIDTH 1
6381 /* The mask used to set the ALT_SDMMC_STAT_DMA_REQ register field value. */
6382 #define ALT_SDMMC_STAT_DMA_REQ_SET_MSK 0x80000000
6383 /* The mask used to clear the ALT_SDMMC_STAT_DMA_REQ register field value. */
6384 #define ALT_SDMMC_STAT_DMA_REQ_CLR_MSK 0x7fffffff
6385 /* The reset value of the ALT_SDMMC_STAT_DMA_REQ register field. */
6386 #define ALT_SDMMC_STAT_DMA_REQ_RESET 0x0
6387 /* Extracts the ALT_SDMMC_STAT_DMA_REQ field value from a register. */
6388 #define ALT_SDMMC_STAT_DMA_REQ_GET(value) (((value) & 0x80000000) >> 31)
6389 /* Produces a ALT_SDMMC_STAT_DMA_REQ register field value suitable for setting the register. */
6390 #define ALT_SDMMC_STAT_DMA_REQ_SET(value) (((value) << 31) & 0x80000000)
6391 
6392 #ifndef __ASSEMBLY__
6393 /*
6394  * WARNING: The C register and register group struct declarations are provided for
6395  * convenience and illustrative purposes. They should, however, be used with
6396  * caution as the C language standard provides no guarantees about the alignment or
6397  * atomicity of device memory accesses. The recommended practice for writing
6398  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6399  * alt_write_word() functions.
6400  *
6401  * The struct declaration for register ALT_SDMMC_STAT.
6402  */
6403 struct ALT_SDMMC_STAT_s
6404 {
6405  const uint32_t fifo_rx_watermark : 1; /* ALT_SDMMC_STAT_FIFO_RX_WATERMARK */
6406  const uint32_t fifo_tx_watermark : 1; /* ALT_SDMMC_STAT_FIFO_TX_WATERMARK */
6407  const uint32_t fifo_empty : 1; /* ALT_SDMMC_STAT_FIFO_EMPTY */
6408  const uint32_t fifo_full : 1; /* ALT_SDMMC_STAT_FIFO_FULL */
6409  const uint32_t command_fsm_states : 4; /* ALT_SDMMC_STAT_CMD_FSM_STATES */
6410  const uint32_t data_3_status : 1; /* ALT_SDMMC_STAT_DATA_3_STAT */
6411  const uint32_t data_busy : 1; /* ALT_SDMMC_STAT_DATA_BUSY */
6412  const uint32_t data_state_mc_busy : 1; /* ALT_SDMMC_STAT_DATA_STATE_MC_BUSY */
6413  const uint32_t response_index : 6; /* ALT_SDMMC_STAT_RESPONSE_INDEX */
6414  const uint32_t fifo_count : 13; /* ALT_SDMMC_STAT_FIFO_COUNT */
6415  const uint32_t dma_ack : 1; /* ALT_SDMMC_STAT_DMA_ACK */
6416  const uint32_t dma_req : 1; /* ALT_SDMMC_STAT_DMA_REQ */
6417 };
6418 
6419 /* The typedef declaration for register ALT_SDMMC_STAT. */
6420 typedef volatile struct ALT_SDMMC_STAT_s ALT_SDMMC_STAT_t;
6421 #endif /* __ASSEMBLY__ */
6422 
6423 /* The reset value of the ALT_SDMMC_STAT register. */
6424 #define ALT_SDMMC_STAT_RESET 0x00000106
6425 /* The byte offset of the ALT_SDMMC_STAT register from the beginning of the component. */
6426 #define ALT_SDMMC_STAT_OFST 0x48
6427 
6428 /*
6429  * Register : fifoth
6430  *
6431  * FIFO Threshold Watermark Register
6432  *
6433  * Register Layout
6434  *
6435  * Bits | Access | Reset | Description
6436  * :--------|:-------|:------|:----------------------------------------------
6437  * [11:0] | RW | 0x0 | ALT_SDMMC_FIFOTH_TX_WMARK
6438  * [15:12] | ??? | 0x0 | *UNDEFINED*
6439  * [27:16] | RW | 0x3ff | ALT_SDMMC_FIFOTH_RX_WMARK
6440  * [30:28] | RW | 0x0 | ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
6441  * [31] | ??? | 0x0 | *UNDEFINED*
6442  *
6443  */
6444 /*
6445  * Field : tx_wmark
6446  *
6447  * FIFO threshold watermark level when transmitting data to card.
6448  *
6449  * When FIFO data count is less than or equal to this number,DMA/FIFO request is
6450  * raised. If Interrupt is enabled, then interrupt occurs. During end of packet,
6451  * request or interrupt is generated,regardless of threshold programming.
6452  *
6453  * In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then
6454  * interrupt is generated instead of DMA request. During end of packet, on last
6455  * interrupt, host is responsible for filling FIFO with only required remaining
6456  * bytes (not before FIFO is full or after CIU completes data transfers, because
6457  * FIFO may not be empty).
6458  *
6459  * In DMA mode, at end of packet, if last transfer is less than burst size, DMA
6460  * controller does single cycles until required bytes are transferred.
6461  *
6462  * 12 bits-1 bit less than FIFO-count of status register, which is 13 bits.
6463  *
6464  * Limitation: TX_WMark >= 1;
6465  *
6466  * Recommended: FIFO_DEPTH/2; (means less than or equal to FIFO_DEPTH/2)
6467  *
6468  * Field Access Macros:
6469  *
6470  */
6471 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */
6472 #define ALT_SDMMC_FIFOTH_TX_WMARK_LSB 0
6473 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */
6474 #define ALT_SDMMC_FIFOTH_TX_WMARK_MSB 11
6475 /* The width in bits of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */
6476 #define ALT_SDMMC_FIFOTH_TX_WMARK_WIDTH 12
6477 /* The mask used to set the ALT_SDMMC_FIFOTH_TX_WMARK register field value. */
6478 #define ALT_SDMMC_FIFOTH_TX_WMARK_SET_MSK 0x00000fff
6479 /* The mask used to clear the ALT_SDMMC_FIFOTH_TX_WMARK register field value. */
6480 #define ALT_SDMMC_FIFOTH_TX_WMARK_CLR_MSK 0xfffff000
6481 /* The reset value of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */
6482 #define ALT_SDMMC_FIFOTH_TX_WMARK_RESET 0x0
6483 /* Extracts the ALT_SDMMC_FIFOTH_TX_WMARK field value from a register. */
6484 #define ALT_SDMMC_FIFOTH_TX_WMARK_GET(value) (((value) & 0x00000fff) >> 0)
6485 /* Produces a ALT_SDMMC_FIFOTH_TX_WMARK register field value suitable for setting the register. */
6486 #define ALT_SDMMC_FIFOTH_TX_WMARK_SET(value) (((value) << 0) & 0x00000fff)
6487 
6488 /*
6489  * Field : rx_wmark
6490  *
6491  * FIFO threshold watermark level when receiving data to card.
6492  *
6493  * When FIFO data count reaches greater than this number,DMA/FIFO request is
6494  * raised. During end of packet, request is
6495  *
6496  * generated regardless of threshold programming in order to complete any remaining
6497  * data.
6498  *
6499  * In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then
6500  * interrupt is generated instead of DMA request.
6501  *
6502  * During end of packet, interrupt is not generated if threshold programming is
6503  * larger than any remaining data. It is responsibility of host to read remaining
6504  * bytes on seeing Data Transfer Done interrupt.
6505  *
6506  * In DMA mode, at end of packet, even if remaining bytes are less than threshold,
6507  * DMA request does single transfers to flush out any remaining bytes before Data
6508  * Transfer Done interrupt is set.
6509  *
6510  * 12 bits-1 bit less than FIFO-count of status register, which is 13 bits.
6511  *
6512  * Limitation: RX_WMark <= FIFO_DEPTH-2
6513  *
6514  * Recommended: (FIFO_DEPTH/2) - 1; (means greater than (FIFO_DEPTH/2) - 1)
6515  *
6516  * NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at
6517  * the end of packet, even if remaining bytes are less than threshold. In this
6518  * case, there will be some data left in the FIFO. It is the responsibility of the
6519  * application to reset the FIFO after the CCS timeout.
6520  *
6521  * Field Access Macros:
6522  *
6523  */
6524 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */
6525 #define ALT_SDMMC_FIFOTH_RX_WMARK_LSB 16
6526 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */
6527 #define ALT_SDMMC_FIFOTH_RX_WMARK_MSB 27
6528 /* The width in bits of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */
6529 #define ALT_SDMMC_FIFOTH_RX_WMARK_WIDTH 12
6530 /* The mask used to set the ALT_SDMMC_FIFOTH_RX_WMARK register field value. */
6531 #define ALT_SDMMC_FIFOTH_RX_WMARK_SET_MSK 0x0fff0000
6532 /* The mask used to clear the ALT_SDMMC_FIFOTH_RX_WMARK register field value. */
6533 #define ALT_SDMMC_FIFOTH_RX_WMARK_CLR_MSK 0xf000ffff
6534 /* The reset value of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */
6535 #define ALT_SDMMC_FIFOTH_RX_WMARK_RESET 0x3ff
6536 /* Extracts the ALT_SDMMC_FIFOTH_RX_WMARK field value from a register. */
6537 #define ALT_SDMMC_FIFOTH_RX_WMARK_GET(value) (((value) & 0x0fff0000) >> 16)
6538 /* Produces a ALT_SDMMC_FIFOTH_RX_WMARK register field value suitable for setting the register. */
6539 #define ALT_SDMMC_FIFOTH_RX_WMARK_SET(value) (((value) << 16) & 0x0fff0000)
6540 
6541 /*
6542  * Field : dw_dma_multiple_transaction_size
6543  *
6544  * Burst size of multiple transaction; should be programmed same as
6545  *
6546  * DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.
6547  *
6548  * 000 1 transfers
6549  *
6550  * 001 4
6551  *
6552  * 010 8
6553  *
6554  * 011 16
6555  *
6556  * 100 32
6557  *
6558  * 101 64
6559  *
6560  * 110 128
6561  *
6562  * 111 256
6563  *
6564  * The units for transfers is the H_DATA_WIDTH parameter. A single transfer
6565  * (dw_dma_single assertion in case of Non DW DMA interface) would be signalled
6566  * based on this value.
6567  *
6568  * Value should be sub-multiple of (RX_WMark + 1)* (F_DATA_WIDTH/H_DATA_WIDTH) and
6569  *
6570  * (FIFO_DEPTH - TX_WMark)* (F_DATA_WIDTH/H_DATA_WIDTH)
6571  *
6572  * For example, if FIFO_DEPTH = 16,
6573  *
6574  * FDATA_WIDTH == H_DATA_WIDTH
6575  *
6576  * Allowed combinations for MSize and TX_WMark are:
6577  *
6578  * MSize = 1, TX_WMARK = 1-15
6579  *
6580  * MSize = 4, TX_WMark = 8
6581  *
6582  * MSize = 4, TX_WMark = 4
6583  *
6584  * MSize = 4, TX_WMark = 12
6585  *
6586  * MSize = 8, TX_WMark = 8
6587  *
6588  * MSize = 8, TX_WMark = 4
6589  *
6590  * Allowed combinations for MSize and RX_WMark are:
6591  *
6592  * MSize = 1, RX_WMARK = 0-14
6593  *
6594  * MSize = 4, RX_WMark = 3
6595  *
6596  * MSize = 4, RX_WMark = 7
6597  *
6598  * MSize = 4, RX_WMark = 11
6599  *
6600  * MSize = 8, RX_WMark = 7
6601  *
6602  * Recommended:
6603  *
6604  * MSize = 8, TX_WMark = 8, RX_WMark = 7
6605  *
6606  * Field Enumeration Values:
6607  *
6608  * Enum | Value | Description
6609  * :-----------------------------------------------------------|:------|:----------------------------
6610  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE1 | 0x0 | Msize 1 and TX_WMARK 1-1023
6611  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE4 | 0x1 | Msize 4 and TX_WMARK 256
6612  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK8 | 0x2 | Msize 8 and TX_WMARK 128
6613  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK16 | 0x3 | Msize 16 and TX_WMARK 64
6614  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK1 | 0x5 | Msize 1 and RX_WMARK 512
6615  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK4 | 0x6 | Msize 4 and RX_WMARK 128
6616  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZE8 | 0x7 | Msize 8 and RX_WMARK 64
6617  *
6618  * Field Access Macros:
6619  *
6620  */
6621 /*
6622  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
6623  *
6624  * Msize 1 and TX_WMARK 1-1023
6625  */
6626 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE1 0x0
6627 /*
6628  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
6629  *
6630  * Msize 4 and TX_WMARK 256
6631  */
6632 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE4 0x1
6633 /*
6634  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
6635  *
6636  * Msize 8 and TX_WMARK 128
6637  */
6638 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK8 0x2
6639 /*
6640  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
6641  *
6642  * Msize 16 and TX_WMARK 64
6643  */
6644 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK16 0x3
6645 /*
6646  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
6647  *
6648  * Msize 1 and RX_WMARK 512
6649  */
6650 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK1 0x5
6651 /*
6652  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
6653  *
6654  * Msize 4 and RX_WMARK 128
6655  */
6656 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK4 0x6
6657 /*
6658  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
6659  *
6660  * Msize 8 and RX_WMARK 64
6661  */
6662 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZE8 0x7
6663 
6664 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field. */
6665 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_LSB 28
6666 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field. */
6667 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_MSB 30
6668 /* The width in bits of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field. */
6669 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_WIDTH 3
6670 /* The mask used to set the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field value. */
6671 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET_MSK 0x70000000
6672 /* The mask used to clear the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field value. */
6673 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_CLR_MSK 0x8fffffff
6674 /* The reset value of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field. */
6675 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_RESET 0x0
6676 /* Extracts the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE field value from a register. */
6677 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_GET(value) (((value) & 0x70000000) >> 28)
6678 /* Produces a ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field value suitable for setting the register. */
6679 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET(value) (((value) << 28) & 0x70000000)
6680 
6681 #ifndef __ASSEMBLY__
6682 /*
6683  * WARNING: The C register and register group struct declarations are provided for
6684  * convenience and illustrative purposes. They should, however, be used with
6685  * caution as the C language standard provides no guarantees about the alignment or
6686  * atomicity of device memory accesses. The recommended practice for writing
6687  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6688  * alt_write_word() functions.
6689  *
6690  * The struct declaration for register ALT_SDMMC_FIFOTH.
6691  */
6692 struct ALT_SDMMC_FIFOTH_s
6693 {
6694  uint32_t tx_wmark : 12; /* ALT_SDMMC_FIFOTH_TX_WMARK */
6695  uint32_t : 4; /* *UNDEFINED* */
6696  uint32_t rx_wmark : 12; /* ALT_SDMMC_FIFOTH_RX_WMARK */
6697  uint32_t dw_dma_multiple_transaction_size : 3; /* ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE */
6698  uint32_t : 1; /* *UNDEFINED* */
6699 };
6700 
6701 /* The typedef declaration for register ALT_SDMMC_FIFOTH. */
6702 typedef volatile struct ALT_SDMMC_FIFOTH_s ALT_SDMMC_FIFOTH_t;
6703 #endif /* __ASSEMBLY__ */
6704 
6705 /* The reset value of the ALT_SDMMC_FIFOTH register. */
6706 #define ALT_SDMMC_FIFOTH_RESET 0x03ff0000
6707 /* The byte offset of the ALT_SDMMC_FIFOTH register from the beginning of the component. */
6708 #define ALT_SDMMC_FIFOTH_OFST 0x4c
6709 
6710 /*
6711  * Register : cdetect
6712  *
6713  * Card Detect Register
6714  *
6715  * Register Layout
6716  *
6717  * Bits | Access | Reset | Description
6718  * :-------|:-------|:------|:--------------------------------
6719  * [0] | R | 0x1 | ALT_SDMMC_CDETECT_CARD_DETECT_N
6720  * [31:1] | ??? | 0x0 | *UNDEFINED*
6721  *
6722  */
6723 /*
6724  * Field : card_detect_n
6725  *
6726  * Value on card_detect_n input ports (1 bit per card); read-only bits.0 represents
6727  * presence of card. Only NUM_CARDS number of bits are implemented.
6728  *
6729  * Field Enumeration Values:
6730  *
6731  * Enum | Value | Description
6732  * :----------------------------------------------|:------|:------------------
6733  * ALT_SDMMC_CDETECT_CARD_DETECT_N_E_DETECTED | 0x0 | Card Detected
6734  * ALT_SDMMC_CDETECT_CARD_DETECT_N_E_NOTDETECTED | 0x1 | Card not Detected
6735  *
6736  * Field Access Macros:
6737  *
6738  */
6739 /*
6740  * Enumerated value for register field ALT_SDMMC_CDETECT_CARD_DETECT_N
6741  *
6742  * Card Detected
6743  */
6744 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_DETECTED 0x0
6745 /*
6746  * Enumerated value for register field ALT_SDMMC_CDETECT_CARD_DETECT_N
6747  *
6748  * Card not Detected
6749  */
6750 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_NOTDETECTED 0x1
6751 
6752 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CDETECT_CARD_DETECT_N register field. */
6753 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_LSB 0
6754 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CDETECT_CARD_DETECT_N register field. */
6755 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_MSB 0
6756 /* The width in bits of the ALT_SDMMC_CDETECT_CARD_DETECT_N register field. */
6757 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_WIDTH 1
6758 /* The mask used to set the ALT_SDMMC_CDETECT_CARD_DETECT_N register field value. */
6759 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET_MSK 0x00000001
6760 /* The mask used to clear the ALT_SDMMC_CDETECT_CARD_DETECT_N register field value. */
6761 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_CLR_MSK 0xfffffffe
6762 /* The reset value of the ALT_SDMMC_CDETECT_CARD_DETECT_N register field. */
6763 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_RESET 0x1
6764 /* Extracts the ALT_SDMMC_CDETECT_CARD_DETECT_N field value from a register. */
6765 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_GET(value) (((value) & 0x00000001) >> 0)
6766 /* Produces a ALT_SDMMC_CDETECT_CARD_DETECT_N register field value suitable for setting the register. */
6767 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET(value) (((value) << 0) & 0x00000001)
6768 
6769 #ifndef __ASSEMBLY__
6770 /*
6771  * WARNING: The C register and register group struct declarations are provided for
6772  * convenience and illustrative purposes. They should, however, be used with
6773  * caution as the C language standard provides no guarantees about the alignment or
6774  * atomicity of device memory accesses. The recommended practice for writing
6775  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6776  * alt_write_word() functions.
6777  *
6778  * The struct declaration for register ALT_SDMMC_CDETECT.
6779  */
6780 struct ALT_SDMMC_CDETECT_s
6781 {
6782  const uint32_t card_detect_n : 1; /* ALT_SDMMC_CDETECT_CARD_DETECT_N */
6783  uint32_t : 31; /* *UNDEFINED* */
6784 };
6785 
6786 /* The typedef declaration for register ALT_SDMMC_CDETECT. */
6787 typedef volatile struct ALT_SDMMC_CDETECT_s ALT_SDMMC_CDETECT_t;
6788 #endif /* __ASSEMBLY__ */
6789 
6790 /* The reset value of the ALT_SDMMC_CDETECT register. */
6791 #define ALT_SDMMC_CDETECT_RESET 0x00000001
6792 /* The byte offset of the ALT_SDMMC_CDETECT register from the beginning of the component. */
6793 #define ALT_SDMMC_CDETECT_OFST 0x50
6794 
6795 /*
6796  * Register : wrtprt
6797  *
6798  * Card Detect Register
6799  *
6800  * Register Layout
6801  *
6802  * Bits | Access | Reset | Description
6803  * :-------|:-------|:------|:----------------------------
6804  * [0] | R | 0x1 | ALT_SDMMC_WRTPRT_WR_PROTECT
6805  * [31:1] | ??? | 0x0 | *UNDEFINED*
6806  *
6807  */
6808 /*
6809  * Field : write_protect
6810  *
6811  * Value on card_write_prt input ports (1 bit per card).
6812  *
6813  * 1 represents write protection. Only NUM_CARDS number of bits are implemented.
6814  *
6815  * Field Enumeration Values:
6816  *
6817  * Enum | Value | Description
6818  * :-----------------------------------|:------|:-----------------------
6819  * ALT_SDMMC_WRTPRT_WR_PROTECT_E_DISD | 0x0 | Write Protect Disabled
6820  * ALT_SDMMC_WRTPRT_WR_PROTECT_E_END | 0x1 | Write Protect Enabled
6821  *
6822  * Field Access Macros:
6823  *
6824  */
6825 /*
6826  * Enumerated value for register field ALT_SDMMC_WRTPRT_WR_PROTECT
6827  *
6828  * Write Protect Disabled
6829  */
6830 #define ALT_SDMMC_WRTPRT_WR_PROTECT_E_DISD 0x0
6831 /*
6832  * Enumerated value for register field ALT_SDMMC_WRTPRT_WR_PROTECT
6833  *
6834  * Write Protect Enabled
6835  */
6836 #define ALT_SDMMC_WRTPRT_WR_PROTECT_E_END 0x1
6837 
6838 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_WRTPRT_WR_PROTECT register field. */
6839 #define ALT_SDMMC_WRTPRT_WR_PROTECT_LSB 0
6840 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_WRTPRT_WR_PROTECT register field. */
6841 #define ALT_SDMMC_WRTPRT_WR_PROTECT_MSB 0
6842 /* The width in bits of the ALT_SDMMC_WRTPRT_WR_PROTECT register field. */
6843 #define ALT_SDMMC_WRTPRT_WR_PROTECT_WIDTH 1
6844 /* The mask used to set the ALT_SDMMC_WRTPRT_WR_PROTECT register field value. */
6845 #define ALT_SDMMC_WRTPRT_WR_PROTECT_SET_MSK 0x00000001
6846 /* The mask used to clear the ALT_SDMMC_WRTPRT_WR_PROTECT register field value. */
6847 #define ALT_SDMMC_WRTPRT_WR_PROTECT_CLR_MSK 0xfffffffe
6848 /* The reset value of the ALT_SDMMC_WRTPRT_WR_PROTECT register field. */
6849 #define ALT_SDMMC_WRTPRT_WR_PROTECT_RESET 0x1
6850 /* Extracts the ALT_SDMMC_WRTPRT_WR_PROTECT field value from a register. */
6851 #define ALT_SDMMC_WRTPRT_WR_PROTECT_GET(value) (((value) & 0x00000001) >> 0)
6852 /* Produces a ALT_SDMMC_WRTPRT_WR_PROTECT register field value suitable for setting the register. */
6853 #define ALT_SDMMC_WRTPRT_WR_PROTECT_SET(value) (((value) << 0) & 0x00000001)
6854 
6855 #ifndef __ASSEMBLY__
6856 /*
6857  * WARNING: The C register and register group struct declarations are provided for
6858  * convenience and illustrative purposes. They should, however, be used with
6859  * caution as the C language standard provides no guarantees about the alignment or
6860  * atomicity of device memory accesses. The recommended practice for writing
6861  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6862  * alt_write_word() functions.
6863  *
6864  * The struct declaration for register ALT_SDMMC_WRTPRT.
6865  */
6866 struct ALT_SDMMC_WRTPRT_s
6867 {
6868  const uint32_t write_protect : 1; /* ALT_SDMMC_WRTPRT_WR_PROTECT */
6869  uint32_t : 31; /* *UNDEFINED* */
6870 };
6871 
6872 /* The typedef declaration for register ALT_SDMMC_WRTPRT. */
6873 typedef volatile struct ALT_SDMMC_WRTPRT_s ALT_SDMMC_WRTPRT_t;
6874 #endif /* __ASSEMBLY__ */
6875 
6876 /* The reset value of the ALT_SDMMC_WRTPRT register. */
6877 #define ALT_SDMMC_WRTPRT_RESET 0x00000001
6878 /* The byte offset of the ALT_SDMMC_WRTPRT register from the beginning of the component. */
6879 #define ALT_SDMMC_WRTPRT_OFST 0x54
6880 
6881 /*
6882  * Register : gpio
6883  *
6884  * General Purpose Input/Output Register
6885  *
6886  * Register Layout
6887  *
6888  * Bits | Access | Reset | Description
6889  * :--------|:-------|:------|:-------------------
6890  * [7:0] | R | 0x0 | ALT_SDMMC_GPIO_GPI
6891  * [23:8] | RW | 0x0 | ALT_SDMMC_GPIO_GPO
6892  * [31:24] | ??? | 0x0 | *UNDEFINED*
6893  *
6894  */
6895 /*
6896  * Field : gpi
6897  *
6898  * Value on gpi input ports; this portion of register is read-only. Valid only when
6899  * AREA_OPTIMIZED parameter is 0.
6900  *
6901  * Field Access Macros:
6902  *
6903  */
6904 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_GPIO_GPI register field. */
6905 #define ALT_SDMMC_GPIO_GPI_LSB 0
6906 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_GPIO_GPI register field. */
6907 #define ALT_SDMMC_GPIO_GPI_MSB 7
6908 /* The width in bits of the ALT_SDMMC_GPIO_GPI register field. */
6909 #define ALT_SDMMC_GPIO_GPI_WIDTH 8
6910 /* The mask used to set the ALT_SDMMC_GPIO_GPI register field value. */
6911 #define ALT_SDMMC_GPIO_GPI_SET_MSK 0x000000ff
6912 /* The mask used to clear the ALT_SDMMC_GPIO_GPI register field value. */
6913 #define ALT_SDMMC_GPIO_GPI_CLR_MSK 0xffffff00
6914 /* The reset value of the ALT_SDMMC_GPIO_GPI register field. */
6915 #define ALT_SDMMC_GPIO_GPI_RESET 0x0
6916 /* Extracts the ALT_SDMMC_GPIO_GPI field value from a register. */
6917 #define ALT_SDMMC_GPIO_GPI_GET(value) (((value) & 0x000000ff) >> 0)
6918 /* Produces a ALT_SDMMC_GPIO_GPI register field value suitable for setting the register. */
6919 #define ALT_SDMMC_GPIO_GPI_SET(value) (((value) << 0) & 0x000000ff)
6920 
6921 /*
6922  * Field : gpo
6923  *
6924  * Value needed to be driven to gpo pins; this portion of register is read/write.
6925  * Valid only when AREA_OPTIMIZED parameter is 0.
6926  *
6927  * Field Access Macros:
6928  *
6929  */
6930 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_GPIO_GPO register field. */
6931 #define ALT_SDMMC_GPIO_GPO_LSB 8
6932 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_GPIO_GPO register field. */
6933 #define ALT_SDMMC_GPIO_GPO_MSB 23
6934 /* The width in bits of the ALT_SDMMC_GPIO_GPO register field. */
6935 #define ALT_SDMMC_GPIO_GPO_WIDTH 16
6936 /* The mask used to set the ALT_SDMMC_GPIO_GPO register field value. */
6937 #define ALT_SDMMC_GPIO_GPO_SET_MSK 0x00ffff00
6938 /* The mask used to clear the ALT_SDMMC_GPIO_GPO register field value. */
6939 #define ALT_SDMMC_GPIO_GPO_CLR_MSK 0xff0000ff
6940 /* The reset value of the ALT_SDMMC_GPIO_GPO register field. */
6941 #define ALT_SDMMC_GPIO_GPO_RESET 0x0
6942 /* Extracts the ALT_SDMMC_GPIO_GPO field value from a register. */
6943 #define ALT_SDMMC_GPIO_GPO_GET(value) (((value) & 0x00ffff00) >> 8)
6944 /* Produces a ALT_SDMMC_GPIO_GPO register field value suitable for setting the register. */
6945 #define ALT_SDMMC_GPIO_GPO_SET(value) (((value) << 8) & 0x00ffff00)
6946 
6947 #ifndef __ASSEMBLY__
6948 /*
6949  * WARNING: The C register and register group struct declarations are provided for
6950  * convenience and illustrative purposes. They should, however, be used with
6951  * caution as the C language standard provides no guarantees about the alignment or
6952  * atomicity of device memory accesses. The recommended practice for writing
6953  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6954  * alt_write_word() functions.
6955  *
6956  * The struct declaration for register ALT_SDMMC_GPIO.
6957  */
6958 struct ALT_SDMMC_GPIO_s
6959 {
6960  const uint32_t gpi : 8; /* ALT_SDMMC_GPIO_GPI */
6961  uint32_t gpo : 16; /* ALT_SDMMC_GPIO_GPO */
6962  uint32_t : 8; /* *UNDEFINED* */
6963 };
6964 
6965 /* The typedef declaration for register ALT_SDMMC_GPIO. */
6966 typedef volatile struct ALT_SDMMC_GPIO_s ALT_SDMMC_GPIO_t;
6967 #endif /* __ASSEMBLY__ */
6968 
6969 /* The reset value of the ALT_SDMMC_GPIO register. */
6970 #define ALT_SDMMC_GPIO_RESET 0x00000000
6971 /* The byte offset of the ALT_SDMMC_GPIO register from the beginning of the component. */
6972 #define ALT_SDMMC_GPIO_OFST 0x58
6973 
6974 /*
6975  * Register : tcbcnt
6976  *
6977  * Transferred CIU Card Byte Count Register
6978  *
6979  * Register Layout
6980  *
6981  * Bits | Access | Reset | Description
6982  * :-------|:-------|:------|:---------------------------------------
6983  * [31:0] | R | 0x0 | ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT
6984  *
6985  */
6986 /*
6987  * Field : trans_card_byte_count
6988  *
6989  * Number of bytes transferred by CIU unit to card.
6990  *
6991  * In 32-bit or 64-bit AMBA data-bus-width modes, register should be accessed in
6992  * full to avoid read-coherency problems.In 16-bit AMBA data-bus-width mode,
6993  * internal 16-bit coherency register is implemented. User should first read lower
6994  * 16 bits and then higher 16 bits. When reading lower 16 bits, higher 16 bits of
6995  * counter are stored in temporary register. When higher 16 bits are read, data
6996  * from temporary register is supplied. Both TCBCNT and TBBCNT share same coherency
6997  * register. When AREA_OPTIMIZED parameter is 1, register should be read only after
6998  * data transfer completes; during data transfer,register returns 0.
6999  *
7000  * Field Access Macros:
7001  *
7002  */
7003 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */
7004 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_LSB 0
7005 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */
7006 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_MSB 31
7007 /* The width in bits of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */
7008 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_WIDTH 32
7009 /* The mask used to set the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field value. */
7010 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET_MSK 0xffffffff
7011 /* The mask used to clear the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field value. */
7012 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_CLR_MSK 0x00000000
7013 /* The reset value of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */
7014 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_RESET 0x0
7015 /* Extracts the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT field value from a register. */
7016 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
7017 /* Produces a ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field value suitable for setting the register. */
7018 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
7019 
7020 #ifndef __ASSEMBLY__
7021 /*
7022  * WARNING: The C register and register group struct declarations are provided for
7023  * convenience and illustrative purposes. They should, however, be used with
7024  * caution as the C language standard provides no guarantees about the alignment or
7025  * atomicity of device memory accesses. The recommended practice for writing
7026  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7027  * alt_write_word() functions.
7028  *
7029  * The struct declaration for register ALT_SDMMC_TCBCNT.
7030  */
7031 struct ALT_SDMMC_TCBCNT_s
7032 {
7033  const uint32_t trans_card_byte_count : 32; /* ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT */
7034 };
7035 
7036 /* The typedef declaration for register ALT_SDMMC_TCBCNT. */
7037 typedef volatile struct ALT_SDMMC_TCBCNT_s ALT_SDMMC_TCBCNT_t;
7038 #endif /* __ASSEMBLY__ */
7039 
7040 /* The reset value of the ALT_SDMMC_TCBCNT register. */
7041 #define ALT_SDMMC_TCBCNT_RESET 0x00000000
7042 /* The byte offset of the ALT_SDMMC_TCBCNT register from the beginning of the component. */
7043 #define ALT_SDMMC_TCBCNT_OFST 0x5c
7044 
7045 /*
7046  * Register : tbbcnt
7047  *
7048  * Transferred Host to BIU-FIFO Byte Count Register
7049  *
7050  * Register Layout
7051  *
7052  * Bits | Access | Reset | Description
7053  * :-------|:-------|:------|:---------------------------------------
7054  * [31:0] | R | 0x0 | ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT
7055  *
7056  */
7057 /*
7058  * Field : trans_fifo_byte_count
7059  *
7060  * Number of bytes transferred between Host/DMA memory and BIU FIFO.
7061  *
7062  * In 32-bit or 64-bit AMBA data-bus-width modes, register should be accessed in
7063  * full to avoid read-coherency problems.In 16-bit AMBA data-bus-width mode,
7064  * internal 16-bit coherency register is implemented. User should first read lower
7065  * 16 bits and then higher 16 bits. When reading lower 16 bits, higher 16 bits of
7066  * counter are stored in temporary register. When higher 16 bits are read, data
7067  * from temporary register is supplied.
7068  *
7069  * Both TCBCNT and TBBCNT share same coherency register.
7070  *
7071  * Field Access Macros:
7072  *
7073  */
7074 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */
7075 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_LSB 0
7076 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */
7077 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_MSB 31
7078 /* The width in bits of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */
7079 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_WIDTH 32
7080 /* The mask used to set the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field value. */
7081 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET_MSK 0xffffffff
7082 /* The mask used to clear the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field value. */
7083 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_CLR_MSK 0x00000000
7084 /* The reset value of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */
7085 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_RESET 0x0
7086 /* Extracts the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT field value from a register. */
7087 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
7088 /* Produces a ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field value suitable for setting the register. */
7089 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
7090 
7091 #ifndef __ASSEMBLY__
7092 /*
7093  * WARNING: The C register and register group struct declarations are provided for
7094  * convenience and illustrative purposes. They should, however, be used with
7095  * caution as the C language standard provides no guarantees about the alignment or
7096  * atomicity of device memory accesses. The recommended practice for writing
7097  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7098  * alt_write_word() functions.
7099  *
7100  * The struct declaration for register ALT_SDMMC_TBBCNT.
7101  */
7102 struct ALT_SDMMC_TBBCNT_s
7103 {
7104  const uint32_t trans_fifo_byte_count : 32; /* ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT */
7105 };
7106 
7107 /* The typedef declaration for register ALT_SDMMC_TBBCNT. */
7108 typedef volatile struct ALT_SDMMC_TBBCNT_s ALT_SDMMC_TBBCNT_t;
7109 #endif /* __ASSEMBLY__ */
7110 
7111 /* The reset value of the ALT_SDMMC_TBBCNT register. */
7112 #define ALT_SDMMC_TBBCNT_RESET 0x00000000
7113 /* The byte offset of the ALT_SDMMC_TBBCNT register from the beginning of the component. */
7114 #define ALT_SDMMC_TBBCNT_OFST 0x60
7115 
7116 /*
7117  * Register : debnce
7118  *
7119  * Debounce Count Register
7120  *
7121  * Register Layout
7122  *
7123  * Bits | Access | Reset | Description
7124  * :--------|:-------|:---------|:--------------------------------
7125  * [23:0] | RW | 0xffffff | ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT
7126  * [31:24] | ??? | 0x0 | *UNDEFINED*
7127  *
7128  */
7129 /*
7130  * Field : debounce_count
7131  *
7132  * Number of host clocks (clk) used by debounce filter logic; typical
7133  *
7134  * debounce time is 5-25 ms.
7135  *
7136  * Field Access Macros:
7137  *
7138  */
7139 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */
7140 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_LSB 0
7141 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */
7142 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_MSB 23
7143 /* The width in bits of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */
7144 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_WIDTH 24
7145 /* The mask used to set the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field value. */
7146 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET_MSK 0x00ffffff
7147 /* The mask used to clear the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field value. */
7148 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_CLR_MSK 0xff000000
7149 /* The reset value of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */
7150 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_RESET 0xffffff
7151 /* Extracts the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT field value from a register. */
7152 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_GET(value) (((value) & 0x00ffffff) >> 0)
7153 /* Produces a ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field value suitable for setting the register. */
7154 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET(value) (((value) << 0) & 0x00ffffff)
7155 
7156 #ifndef __ASSEMBLY__
7157 /*
7158  * WARNING: The C register and register group struct declarations are provided for
7159  * convenience and illustrative purposes. They should, however, be used with
7160  * caution as the C language standard provides no guarantees about the alignment or
7161  * atomicity of device memory accesses. The recommended practice for writing
7162  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7163  * alt_write_word() functions.
7164  *
7165  * The struct declaration for register ALT_SDMMC_DEBNCE.
7166  */
7167 struct ALT_SDMMC_DEBNCE_s
7168 {
7169  uint32_t debounce_count : 24; /* ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT */
7170  uint32_t : 8; /* *UNDEFINED* */
7171 };
7172 
7173 /* The typedef declaration for register ALT_SDMMC_DEBNCE. */
7174 typedef volatile struct ALT_SDMMC_DEBNCE_s ALT_SDMMC_DEBNCE_t;
7175 #endif /* __ASSEMBLY__ */
7176 
7177 /* The reset value of the ALT_SDMMC_DEBNCE register. */
7178 #define ALT_SDMMC_DEBNCE_RESET 0x00ffffff
7179 /* The byte offset of the ALT_SDMMC_DEBNCE register from the beginning of the component. */
7180 #define ALT_SDMMC_DEBNCE_OFST 0x64
7181 
7182 /*
7183  * Register : usrid
7184  *
7185  * User ID Register
7186  *
7187  * Register Layout
7188  *
7189  * Bits | Access | Reset | Description
7190  * :-------|:-------|:----------|:-----------------------
7191  * [31:0] | RW | 0x7967797 | ALT_SDMMC_USRID_USR_ID
7192  *
7193  */
7194 /*
7195  * Field : usr_id
7196  *
7197  * User identification register; value set by user. Default reset value can be
7198  * picked by user while configuring core before synthesis.
7199  *
7200  * Can also be used as scratch pad register by user.
7201  *
7202  * Field Access Macros:
7203  *
7204  */
7205 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_USRID_USR_ID register field. */
7206 #define ALT_SDMMC_USRID_USR_ID_LSB 0
7207 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_USRID_USR_ID register field. */
7208 #define ALT_SDMMC_USRID_USR_ID_MSB 31
7209 /* The width in bits of the ALT_SDMMC_USRID_USR_ID register field. */
7210 #define ALT_SDMMC_USRID_USR_ID_WIDTH 32
7211 /* The mask used to set the ALT_SDMMC_USRID_USR_ID register field value. */
7212 #define ALT_SDMMC_USRID_USR_ID_SET_MSK 0xffffffff
7213 /* The mask used to clear the ALT_SDMMC_USRID_USR_ID register field value. */
7214 #define ALT_SDMMC_USRID_USR_ID_CLR_MSK 0x00000000
7215 /* The reset value of the ALT_SDMMC_USRID_USR_ID register field. */
7216 #define ALT_SDMMC_USRID_USR_ID_RESET 0x7967797
7217 /* Extracts the ALT_SDMMC_USRID_USR_ID field value from a register. */
7218 #define ALT_SDMMC_USRID_USR_ID_GET(value) (((value) & 0xffffffff) >> 0)
7219 /* Produces a ALT_SDMMC_USRID_USR_ID register field value suitable for setting the register. */
7220 #define ALT_SDMMC_USRID_USR_ID_SET(value) (((value) << 0) & 0xffffffff)
7221 
7222 #ifndef __ASSEMBLY__
7223 /*
7224  * WARNING: The C register and register group struct declarations are provided for
7225  * convenience and illustrative purposes. They should, however, be used with
7226  * caution as the C language standard provides no guarantees about the alignment or
7227  * atomicity of device memory accesses. The recommended practice for writing
7228  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7229  * alt_write_word() functions.
7230  *
7231  * The struct declaration for register ALT_SDMMC_USRID.
7232  */
7233 struct ALT_SDMMC_USRID_s
7234 {
7235  uint32_t usr_id : 32; /* ALT_SDMMC_USRID_USR_ID */
7236 };
7237 
7238 /* The typedef declaration for register ALT_SDMMC_USRID. */
7239 typedef volatile struct ALT_SDMMC_USRID_s ALT_SDMMC_USRID_t;
7240 #endif /* __ASSEMBLY__ */
7241 
7242 /* The reset value of the ALT_SDMMC_USRID register. */
7243 #define ALT_SDMMC_USRID_RESET 0x07967797
7244 /* The byte offset of the ALT_SDMMC_USRID register from the beginning of the component. */
7245 #define ALT_SDMMC_USRID_OFST 0x68
7246 
7247 /*
7248  * Register : verid
7249  *
7250  * Version ID Register
7251  *
7252  * Register Layout
7253  *
7254  * Bits | Access | Reset | Description
7255  * :-------|:-------|:-----------|:-----------------------
7256  * [31:0] | R | 0x5342270a | ALT_SDMMC_VERID_VER_ID
7257  *
7258  */
7259 /*
7260  * Field : ver_id
7261  *
7262  * Synopsys version identification register; register value is hard-wired.Can be
7263  * read by firmware to support different versions of core.
7264  *
7265  * Field Access Macros:
7266  *
7267  */
7268 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_VERID_VER_ID register field. */
7269 #define ALT_SDMMC_VERID_VER_ID_LSB 0
7270 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_VERID_VER_ID register field. */
7271 #define ALT_SDMMC_VERID_VER_ID_MSB 31
7272 /* The width in bits of the ALT_SDMMC_VERID_VER_ID register field. */
7273 #define ALT_SDMMC_VERID_VER_ID_WIDTH 32
7274 /* The mask used to set the ALT_SDMMC_VERID_VER_ID register field value. */
7275 #define ALT_SDMMC_VERID_VER_ID_SET_MSK 0xffffffff
7276 /* The mask used to clear the ALT_SDMMC_VERID_VER_ID register field value. */
7277 #define ALT_SDMMC_VERID_VER_ID_CLR_MSK 0x00000000
7278 /* The reset value of the ALT_SDMMC_VERID_VER_ID register field. */
7279 #define ALT_SDMMC_VERID_VER_ID_RESET 0x5342270a
7280 /* Extracts the ALT_SDMMC_VERID_VER_ID field value from a register. */
7281 #define ALT_SDMMC_VERID_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
7282 /* Produces a ALT_SDMMC_VERID_VER_ID register field value suitable for setting the register. */
7283 #define ALT_SDMMC_VERID_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
7284 
7285 #ifndef __ASSEMBLY__
7286 /*
7287  * WARNING: The C register and register group struct declarations are provided for
7288  * convenience and illustrative purposes. They should, however, be used with
7289  * caution as the C language standard provides no guarantees about the alignment or
7290  * atomicity of device memory accesses. The recommended practice for writing
7291  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7292  * alt_write_word() functions.
7293  *
7294  * The struct declaration for register ALT_SDMMC_VERID.
7295  */
7296 struct ALT_SDMMC_VERID_s
7297 {
7298  const uint32_t ver_id : 32; /* ALT_SDMMC_VERID_VER_ID */
7299 };
7300 
7301 /* The typedef declaration for register ALT_SDMMC_VERID. */
7302 typedef volatile struct ALT_SDMMC_VERID_s ALT_SDMMC_VERID_t;
7303 #endif /* __ASSEMBLY__ */
7304 
7305 /* The reset value of the ALT_SDMMC_VERID register. */
7306 #define ALT_SDMMC_VERID_RESET 0x5342270a
7307 /* The byte offset of the ALT_SDMMC_VERID register from the beginning of the component. */
7308 #define ALT_SDMMC_VERID_OFST 0x6c
7309 
7310 /*
7311  * Register : hcon
7312  *
7313  * Hardware Configuration Register
7314  *
7315  * Register Layout
7316  *
7317  * Bits | Access | Reset | Description
7318  * :--------|:-------|:------|:-------------------------
7319  * [0] | R | 0x1 | Card Type
7320  * [5:1] | R | 0x0 | Number of Cards
7321  * [6] | R | 0x0 | Slave Bus Type
7322  * [9:7] | R | 0x1 | Slave Bus Data Width
7323  * [15:10] | R | 0xc | Slave Bus Address Width
7324  * [17:16] | R | 0x0 | DMA Interface Type
7325  * [20:18] | R | 0x1 | Generic DMA Data Width
7326  * [21] | R | 0x0 | FIFO RAM Location
7327  * [22] | R | 0x1 | Implement Hold Register
7328  * [23] | R | 0x1 | Clock False Path
7329  * [25:24] | R | 0x0 | Number of Clock Dividers
7330  * [26] | R | 0x0 | Area Optimized
7331  * [27] | R | 0x0 | ALT_SDMMC_HCON_AC
7332  * [31:28] | ??? | 0x0 | *UNDEFINED*
7333  *
7334  */
7335 /*
7336  * Field : Card Type - ct
7337  *
7338  * Supported card types
7339  *
7340  * Field Enumeration Values:
7341  *
7342  * Enum | Value | Description
7343  * :--------------------------|:------|:-----------------
7344  * ALT_SDMMC_HCON_CT_E_SDMMC | 0x1 | Card Type SD/MMC
7345  *
7346  * Field Access Macros:
7347  *
7348  */
7349 /*
7350  * Enumerated value for register field ALT_SDMMC_HCON_CT
7351  *
7352  * Card Type SD/MMC
7353  */
7354 #define ALT_SDMMC_HCON_CT_E_SDMMC 0x1
7355 
7356 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_CT register field. */
7357 #define ALT_SDMMC_HCON_CT_LSB 0
7358 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_CT register field. */
7359 #define ALT_SDMMC_HCON_CT_MSB 0
7360 /* The width in bits of the ALT_SDMMC_HCON_CT register field. */
7361 #define ALT_SDMMC_HCON_CT_WIDTH 1
7362 /* The mask used to set the ALT_SDMMC_HCON_CT register field value. */
7363 #define ALT_SDMMC_HCON_CT_SET_MSK 0x00000001
7364 /* The mask used to clear the ALT_SDMMC_HCON_CT register field value. */
7365 #define ALT_SDMMC_HCON_CT_CLR_MSK 0xfffffffe
7366 /* The reset value of the ALT_SDMMC_HCON_CT register field. */
7367 #define ALT_SDMMC_HCON_CT_RESET 0x1
7368 /* Extracts the ALT_SDMMC_HCON_CT field value from a register. */
7369 #define ALT_SDMMC_HCON_CT_GET(value) (((value) & 0x00000001) >> 0)
7370 /* Produces a ALT_SDMMC_HCON_CT register field value suitable for setting the register. */
7371 #define ALT_SDMMC_HCON_CT_SET(value) (((value) << 0) & 0x00000001)
7372 
7373 /*
7374  * Field : Number of Cards - nc
7375  *
7376  * Maximum number of cards less one
7377  *
7378  * Field Enumeration Values:
7379  *
7380  * Enum | Value | Description
7381  * :----------------------------|:------|:------------
7382  * ALT_SDMMC_HCON_NC_E_NUMCARD | 0x0 | 1 Card
7383  *
7384  * Field Access Macros:
7385  *
7386  */
7387 /*
7388  * Enumerated value for register field ALT_SDMMC_HCON_NC
7389  *
7390  * 1 Card
7391  */
7392 #define ALT_SDMMC_HCON_NC_E_NUMCARD 0x0
7393 
7394 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_NC register field. */
7395 #define ALT_SDMMC_HCON_NC_LSB 1
7396 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_NC register field. */
7397 #define ALT_SDMMC_HCON_NC_MSB 5
7398 /* The width in bits of the ALT_SDMMC_HCON_NC register field. */
7399 #define ALT_SDMMC_HCON_NC_WIDTH 5
7400 /* The mask used to set the ALT_SDMMC_HCON_NC register field value. */
7401 #define ALT_SDMMC_HCON_NC_SET_MSK 0x0000003e
7402 /* The mask used to clear the ALT_SDMMC_HCON_NC register field value. */
7403 #define ALT_SDMMC_HCON_NC_CLR_MSK 0xffffffc1
7404 /* The reset value of the ALT_SDMMC_HCON_NC register field. */
7405 #define ALT_SDMMC_HCON_NC_RESET 0x0
7406 /* Extracts the ALT_SDMMC_HCON_NC field value from a register. */
7407 #define ALT_SDMMC_HCON_NC_GET(value) (((value) & 0x0000003e) >> 1)
7408 /* Produces a ALT_SDMMC_HCON_NC register field value suitable for setting the register. */
7409 #define ALT_SDMMC_HCON_NC_SET(value) (((value) << 1) & 0x0000003e)
7410 
7411 /*
7412  * Field : Slave Bus Type - hbus
7413  *
7414  * Slave bus type.
7415  *
7416  * Field Enumeration Values:
7417  *
7418  * Enum | Value | Description
7419  * :--------------------------|:------|:------------
7420  * ALT_SDMMC_HCON_HBUS_E_APB | 0x0 | APB Bus
7421  *
7422  * Field Access Macros:
7423  *
7424  */
7425 /*
7426  * Enumerated value for register field ALT_SDMMC_HCON_HBUS
7427  *
7428  * APB Bus
7429  */
7430 #define ALT_SDMMC_HCON_HBUS_E_APB 0x0
7431 
7432 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_HBUS register field. */
7433 #define ALT_SDMMC_HCON_HBUS_LSB 6
7434 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_HBUS register field. */
7435 #define ALT_SDMMC_HCON_HBUS_MSB 6
7436 /* The width in bits of the ALT_SDMMC_HCON_HBUS register field. */
7437 #define ALT_SDMMC_HCON_HBUS_WIDTH 1
7438 /* The mask used to set the ALT_SDMMC_HCON_HBUS register field value. */
7439 #define ALT_SDMMC_HCON_HBUS_SET_MSK 0x00000040
7440 /* The mask used to clear the ALT_SDMMC_HCON_HBUS register field value. */
7441 #define ALT_SDMMC_HCON_HBUS_CLR_MSK 0xffffffbf
7442 /* The reset value of the ALT_SDMMC_HCON_HBUS register field. */
7443 #define ALT_SDMMC_HCON_HBUS_RESET 0x0
7444 /* Extracts the ALT_SDMMC_HCON_HBUS field value from a register. */
7445 #define ALT_SDMMC_HCON_HBUS_GET(value) (((value) & 0x00000040) >> 6)
7446 /* Produces a ALT_SDMMC_HCON_HBUS register field value suitable for setting the register. */
7447 #define ALT_SDMMC_HCON_HBUS_SET(value) (((value) << 6) & 0x00000040)
7448 
7449 /*
7450  * Field : Slave Bus Data Width - hdatawidth
7451  *
7452  * Slave bus data width
7453  *
7454  * Field Enumeration Values:
7455  *
7456  * Enum | Value | Description
7457  * :----------------------------------------|:------|:--------------
7458  * ALT_SDMMC_HCON_HDATAWIDTH_E_WIDTH32BITS | 0x1 | Width 32 Bits
7459  *
7460  * Field Access Macros:
7461  *
7462  */
7463 /*
7464  * Enumerated value for register field ALT_SDMMC_HCON_HDATAWIDTH
7465  *
7466  * Width 32 Bits
7467  */
7468 #define ALT_SDMMC_HCON_HDATAWIDTH_E_WIDTH32BITS 0x1
7469 
7470 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_HDATAWIDTH register field. */
7471 #define ALT_SDMMC_HCON_HDATAWIDTH_LSB 7
7472 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_HDATAWIDTH register field. */
7473 #define ALT_SDMMC_HCON_HDATAWIDTH_MSB 9
7474 /* The width in bits of the ALT_SDMMC_HCON_HDATAWIDTH register field. */
7475 #define ALT_SDMMC_HCON_HDATAWIDTH_WIDTH 3
7476 /* The mask used to set the ALT_SDMMC_HCON_HDATAWIDTH register field value. */
7477 #define ALT_SDMMC_HCON_HDATAWIDTH_SET_MSK 0x00000380
7478 /* The mask used to clear the ALT_SDMMC_HCON_HDATAWIDTH register field value. */
7479 #define ALT_SDMMC_HCON_HDATAWIDTH_CLR_MSK 0xfffffc7f
7480 /* The reset value of the ALT_SDMMC_HCON_HDATAWIDTH register field. */
7481 #define ALT_SDMMC_HCON_HDATAWIDTH_RESET 0x1
7482 /* Extracts the ALT_SDMMC_HCON_HDATAWIDTH field value from a register. */
7483 #define ALT_SDMMC_HCON_HDATAWIDTH_GET(value) (((value) & 0x00000380) >> 7)
7484 /* Produces a ALT_SDMMC_HCON_HDATAWIDTH register field value suitable for setting the register. */
7485 #define ALT_SDMMC_HCON_HDATAWIDTH_SET(value) (((value) << 7) & 0x00000380)
7486 
7487 /*
7488  * Field : Slave Bus Address Width - haddrwidth
7489  *
7490  * Slave bus address width less one
7491  *
7492  * Field Enumeration Values:
7493  *
7494  * Enum | Value | Description
7495  * :----------------------------------------|:------|:--------------
7496  * ALT_SDMMC_HCON_HADDRWIDTH_E_WIDTH13BITS | 0xc | Width 13 Bits
7497  *
7498  * Field Access Macros:
7499  *
7500  */
7501 /*
7502  * Enumerated value for register field ALT_SDMMC_HCON_HADDRWIDTH
7503  *
7504  * Width 13 Bits
7505  */
7506 #define ALT_SDMMC_HCON_HADDRWIDTH_E_WIDTH13BITS 0xc
7507 
7508 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_HADDRWIDTH register field. */
7509 #define ALT_SDMMC_HCON_HADDRWIDTH_LSB 10
7510 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_HADDRWIDTH register field. */
7511 #define ALT_SDMMC_HCON_HADDRWIDTH_MSB 15
7512 /* The width in bits of the ALT_SDMMC_HCON_HADDRWIDTH register field. */
7513 #define ALT_SDMMC_HCON_HADDRWIDTH_WIDTH 6
7514 /* The mask used to set the ALT_SDMMC_HCON_HADDRWIDTH register field value. */
7515 #define ALT_SDMMC_HCON_HADDRWIDTH_SET_MSK 0x0000fc00
7516 /* The mask used to clear the ALT_SDMMC_HCON_HADDRWIDTH register field value. */
7517 #define ALT_SDMMC_HCON_HADDRWIDTH_CLR_MSK 0xffff03ff
7518 /* The reset value of the ALT_SDMMC_HCON_HADDRWIDTH register field. */
7519 #define ALT_SDMMC_HCON_HADDRWIDTH_RESET 0xc
7520 /* Extracts the ALT_SDMMC_HCON_HADDRWIDTH field value from a register. */
7521 #define ALT_SDMMC_HCON_HADDRWIDTH_GET(value) (((value) & 0x0000fc00) >> 10)
7522 /* Produces a ALT_SDMMC_HCON_HADDRWIDTH register field value suitable for setting the register. */
7523 #define ALT_SDMMC_HCON_HADDRWIDTH_SET(value) (((value) << 10) & 0x0000fc00)
7524 
7525 /*
7526  * Field : DMA Interface Type - dmaintf
7527  *
7528  * DMA interface type
7529  *
7530  * Field Enumeration Values:
7531  *
7532  * Enum | Value | Description
7533  * :------------------------------|:------|:-------------------------------------------------
7534  * ALT_SDMMC_HCON_DMAINTF_E_NONE | 0x0 | No External DMA Controller Interface (SD/MMC has
7535  * : | | its own internal DMA Controller
7536  *
7537  * Field Access Macros:
7538  *
7539  */
7540 /*
7541  * Enumerated value for register field ALT_SDMMC_HCON_DMAINTF
7542  *
7543  * No External DMA Controller Interface (SD/MMC has its own internal DMA Controller
7544  */
7545 #define ALT_SDMMC_HCON_DMAINTF_E_NONE 0x0
7546 
7547 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_DMAINTF register field. */
7548 #define ALT_SDMMC_HCON_DMAINTF_LSB 16
7549 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_DMAINTF register field. */
7550 #define ALT_SDMMC_HCON_DMAINTF_MSB 17
7551 /* The width in bits of the ALT_SDMMC_HCON_DMAINTF register field. */
7552 #define ALT_SDMMC_HCON_DMAINTF_WIDTH 2
7553 /* The mask used to set the ALT_SDMMC_HCON_DMAINTF register field value. */
7554 #define ALT_SDMMC_HCON_DMAINTF_SET_MSK 0x00030000
7555 /* The mask used to clear the ALT_SDMMC_HCON_DMAINTF register field value. */
7556 #define ALT_SDMMC_HCON_DMAINTF_CLR_MSK 0xfffcffff
7557 /* The reset value of the ALT_SDMMC_HCON_DMAINTF register field. */
7558 #define ALT_SDMMC_HCON_DMAINTF_RESET 0x0
7559 /* Extracts the ALT_SDMMC_HCON_DMAINTF field value from a register. */
7560 #define ALT_SDMMC_HCON_DMAINTF_GET(value) (((value) & 0x00030000) >> 16)
7561 /* Produces a ALT_SDMMC_HCON_DMAINTF register field value suitable for setting the register. */
7562 #define ALT_SDMMC_HCON_DMAINTF_SET(value) (((value) << 16) & 0x00030000)
7563 
7564 /*
7565  * Field : Generic DMA Data Width - dmadatawidth
7566  *
7567  * Encodes bit width of external DMA controller interface. Doesn't apply to the
7568  * SD/MMC because it has no external DMA controller interface.
7569  *
7570  * Field Enumeration Values:
7571  *
7572  * Enum | Value | Description
7573  * :------------------------------------------|:------|:-------------
7574  * ALT_SDMMC_HCON_DMADATAWIDTH_E_WIDTH32BITS | 0x1 | 32-bits wide
7575  *
7576  * Field Access Macros:
7577  *
7578  */
7579 /*
7580  * Enumerated value for register field ALT_SDMMC_HCON_DMADATAWIDTH
7581  *
7582  * 32-bits wide
7583  */
7584 #define ALT_SDMMC_HCON_DMADATAWIDTH_E_WIDTH32BITS 0x1
7585 
7586 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_DMADATAWIDTH register field. */
7587 #define ALT_SDMMC_HCON_DMADATAWIDTH_LSB 18
7588 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_DMADATAWIDTH register field. */
7589 #define ALT_SDMMC_HCON_DMADATAWIDTH_MSB 20
7590 /* The width in bits of the ALT_SDMMC_HCON_DMADATAWIDTH register field. */
7591 #define ALT_SDMMC_HCON_DMADATAWIDTH_WIDTH 3
7592 /* The mask used to set the ALT_SDMMC_HCON_DMADATAWIDTH register field value. */
7593 #define ALT_SDMMC_HCON_DMADATAWIDTH_SET_MSK 0x001c0000
7594 /* The mask used to clear the ALT_SDMMC_HCON_DMADATAWIDTH register field value. */
7595 #define ALT_SDMMC_HCON_DMADATAWIDTH_CLR_MSK 0xffe3ffff
7596 /* The reset value of the ALT_SDMMC_HCON_DMADATAWIDTH register field. */
7597 #define ALT_SDMMC_HCON_DMADATAWIDTH_RESET 0x1
7598 /* Extracts the ALT_SDMMC_HCON_DMADATAWIDTH field value from a register. */
7599 #define ALT_SDMMC_HCON_DMADATAWIDTH_GET(value) (((value) & 0x001c0000) >> 18)
7600 /* Produces a ALT_SDMMC_HCON_DMADATAWIDTH register field value suitable for setting the register. */
7601 #define ALT_SDMMC_HCON_DMADATAWIDTH_SET(value) (((value) << 18) & 0x001c0000)
7602 
7603 /*
7604  * Field : FIFO RAM Location - rios
7605  *
7606  * FIFO RAM location
7607  *
7608  * Field Enumeration Values:
7609  *
7610  * Enum | Value | Description
7611  * :------------------------------|:------|:-------------------------
7612  * ALT_SDMMC_HCON_RIOS_E_OUTSIDE | 0x0 | FIFO RAM Outside IP Core
7613  *
7614  * Field Access Macros:
7615  *
7616  */
7617 /*
7618  * Enumerated value for register field ALT_SDMMC_HCON_RIOS
7619  *
7620  * FIFO RAM Outside IP Core
7621  */
7622 #define ALT_SDMMC_HCON_RIOS_E_OUTSIDE 0x0
7623 
7624 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_RIOS register field. */
7625 #define ALT_SDMMC_HCON_RIOS_LSB 21
7626 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_RIOS register field. */
7627 #define ALT_SDMMC_HCON_RIOS_MSB 21
7628 /* The width in bits of the ALT_SDMMC_HCON_RIOS register field. */
7629 #define ALT_SDMMC_HCON_RIOS_WIDTH 1
7630 /* The mask used to set the ALT_SDMMC_HCON_RIOS register field value. */
7631 #define ALT_SDMMC_HCON_RIOS_SET_MSK 0x00200000
7632 /* The mask used to clear the ALT_SDMMC_HCON_RIOS register field value. */
7633 #define ALT_SDMMC_HCON_RIOS_CLR_MSK 0xffdfffff
7634 /* The reset value of the ALT_SDMMC_HCON_RIOS register field. */
7635 #define ALT_SDMMC_HCON_RIOS_RESET 0x0
7636 /* Extracts the ALT_SDMMC_HCON_RIOS field value from a register. */
7637 #define ALT_SDMMC_HCON_RIOS_GET(value) (((value) & 0x00200000) >> 21)
7638 /* Produces a ALT_SDMMC_HCON_RIOS register field value suitable for setting the register. */
7639 #define ALT_SDMMC_HCON_RIOS_SET(value) (((value) << 21) & 0x00200000)
7640 
7641 /*
7642  * Field : Implement Hold Register - ihr
7643  *
7644  * Implement hold register
7645  *
7646  * Field Enumeration Values:
7647  *
7648  * Enum | Value | Description
7649  * :---------------------------------|:------|:-------------------------
7650  * ALT_SDMMC_HCON_IHR_E_IMPLEMENTED | 0x1 | Implements Hold Register
7651  *
7652  * Field Access Macros:
7653  *
7654  */
7655 /*
7656  * Enumerated value for register field ALT_SDMMC_HCON_IHR
7657  *
7658  * Implements Hold Register
7659  */
7660 #define ALT_SDMMC_HCON_IHR_E_IMPLEMENTED 0x1
7661 
7662 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_IHR register field. */
7663 #define ALT_SDMMC_HCON_IHR_LSB 22
7664 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_IHR register field. */
7665 #define ALT_SDMMC_HCON_IHR_MSB 22
7666 /* The width in bits of the ALT_SDMMC_HCON_IHR register field. */
7667 #define ALT_SDMMC_HCON_IHR_WIDTH 1
7668 /* The mask used to set the ALT_SDMMC_HCON_IHR register field value. */
7669 #define ALT_SDMMC_HCON_IHR_SET_MSK 0x00400000
7670 /* The mask used to clear the ALT_SDMMC_HCON_IHR register field value. */
7671 #define ALT_SDMMC_HCON_IHR_CLR_MSK 0xffbfffff
7672 /* The reset value of the ALT_SDMMC_HCON_IHR register field. */
7673 #define ALT_SDMMC_HCON_IHR_RESET 0x1
7674 /* Extracts the ALT_SDMMC_HCON_IHR field value from a register. */
7675 #define ALT_SDMMC_HCON_IHR_GET(value) (((value) & 0x00400000) >> 22)
7676 /* Produces a ALT_SDMMC_HCON_IHR register field value suitable for setting the register. */
7677 #define ALT_SDMMC_HCON_IHR_SET(value) (((value) << 22) & 0x00400000)
7678 
7679 /*
7680  * Field : Clock False Path - scfp
7681  *
7682  * Clock False Path
7683  *
7684  * Field Enumeration Values:
7685  *
7686  * Enum | Value | Description
7687  * :--------------------------|:------|:---------------------
7688  * ALT_SDMMC_HCON_SCFP_E_SET | 0x1 | Clock False Path Set
7689  *
7690  * Field Access Macros:
7691  *
7692  */
7693 /*
7694  * Enumerated value for register field ALT_SDMMC_HCON_SCFP
7695  *
7696  * Clock False Path Set
7697  */
7698 #define ALT_SDMMC_HCON_SCFP_E_SET 0x1
7699 
7700 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_SCFP register field. */
7701 #define ALT_SDMMC_HCON_SCFP_LSB 23
7702 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_SCFP register field. */
7703 #define ALT_SDMMC_HCON_SCFP_MSB 23
7704 /* The width in bits of the ALT_SDMMC_HCON_SCFP register field. */
7705 #define ALT_SDMMC_HCON_SCFP_WIDTH 1
7706 /* The mask used to set the ALT_SDMMC_HCON_SCFP register field value. */
7707 #define ALT_SDMMC_HCON_SCFP_SET_MSK 0x00800000
7708 /* The mask used to clear the ALT_SDMMC_HCON_SCFP register field value. */
7709 #define ALT_SDMMC_HCON_SCFP_CLR_MSK 0xff7fffff
7710 /* The reset value of the ALT_SDMMC_HCON_SCFP register field. */
7711 #define ALT_SDMMC_HCON_SCFP_RESET 0x1
7712 /* Extracts the ALT_SDMMC_HCON_SCFP field value from a register. */
7713 #define ALT_SDMMC_HCON_SCFP_GET(value) (((value) & 0x00800000) >> 23)
7714 /* Produces a ALT_SDMMC_HCON_SCFP register field value suitable for setting the register. */
7715 #define ALT_SDMMC_HCON_SCFP_SET(value) (((value) << 23) & 0x00800000)
7716 
7717 /*
7718  * Field : Number of Clock Dividers - ncd
7719  *
7720  * Number of clock dividers less one
7721  *
7722  * Field Enumeration Values:
7723  *
7724  * Enum | Value | Description
7725  * :----------------------------|:------|:------------------
7726  * ALT_SDMMC_HCON_NCD_E_ONEDIV | 0x0 | One Clock Divider
7727  *
7728  * Field Access Macros:
7729  *
7730  */
7731 /*
7732  * Enumerated value for register field ALT_SDMMC_HCON_NCD
7733  *
7734  * One Clock Divider
7735  */
7736 #define ALT_SDMMC_HCON_NCD_E_ONEDIV 0x0
7737 
7738 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_NCD register field. */
7739 #define ALT_SDMMC_HCON_NCD_LSB 24
7740 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_NCD register field. */
7741 #define ALT_SDMMC_HCON_NCD_MSB 25
7742 /* The width in bits of the ALT_SDMMC_HCON_NCD register field. */
7743 #define ALT_SDMMC_HCON_NCD_WIDTH 2
7744 /* The mask used to set the ALT_SDMMC_HCON_NCD register field value. */
7745 #define ALT_SDMMC_HCON_NCD_SET_MSK 0x03000000
7746 /* The mask used to clear the ALT_SDMMC_HCON_NCD register field value. */
7747 #define ALT_SDMMC_HCON_NCD_CLR_MSK 0xfcffffff
7748 /* The reset value of the ALT_SDMMC_HCON_NCD register field. */
7749 #define ALT_SDMMC_HCON_NCD_RESET 0x0
7750 /* Extracts the ALT_SDMMC_HCON_NCD field value from a register. */
7751 #define ALT_SDMMC_HCON_NCD_GET(value) (((value) & 0x03000000) >> 24)
7752 /* Produces a ALT_SDMMC_HCON_NCD register field value suitable for setting the register. */
7753 #define ALT_SDMMC_HCON_NCD_SET(value) (((value) << 24) & 0x03000000)
7754 
7755 /*
7756  * Field : Area Optimized - aro
7757  *
7758  * Area optimized
7759  *
7760  * Field Enumeration Values:
7761  *
7762  * Enum | Value | Description
7763  * :-----------------------------------|:------|:-----------------------
7764  * ALT_SDMMC_HCON_ARO_E_NOTOPTFORAREA | 0x0 | Not Optimized For Area
7765  *
7766  * Field Access Macros:
7767  *
7768  */
7769 /*
7770  * Enumerated value for register field ALT_SDMMC_HCON_ARO
7771  *
7772  * Not Optimized For Area
7773  */
7774 #define ALT_SDMMC_HCON_ARO_E_NOTOPTFORAREA 0x0
7775 
7776 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_ARO register field. */
7777 #define ALT_SDMMC_HCON_ARO_LSB 26
7778 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_ARO register field. */
7779 #define ALT_SDMMC_HCON_ARO_MSB 26
7780 /* The width in bits of the ALT_SDMMC_HCON_ARO register field. */
7781 #define ALT_SDMMC_HCON_ARO_WIDTH 1
7782 /* The mask used to set the ALT_SDMMC_HCON_ARO register field value. */
7783 #define ALT_SDMMC_HCON_ARO_SET_MSK 0x04000000
7784 /* The mask used to clear the ALT_SDMMC_HCON_ARO register field value. */
7785 #define ALT_SDMMC_HCON_ARO_CLR_MSK 0xfbffffff
7786 /* The reset value of the ALT_SDMMC_HCON_ARO register field. */
7787 #define ALT_SDMMC_HCON_ARO_RESET 0x0
7788 /* Extracts the ALT_SDMMC_HCON_ARO field value from a register. */
7789 #define ALT_SDMMC_HCON_ARO_GET(value) (((value) & 0x04000000) >> 26)
7790 /* Produces a ALT_SDMMC_HCON_ARO register field value suitable for setting the register. */
7791 #define ALT_SDMMC_HCON_ARO_SET(value) (((value) << 26) & 0x04000000)
7792 
7793 /*
7794  * Field : ac
7795  *
7796  * For 64-bit Address Configuration Only - bit 27
7797  *
7798  * 0 - 32 bit addressing supported
7799  *
7800  * 1 - 64 bit address supported
7801  *
7802  * Field Access Macros:
7803  *
7804  */
7805 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_AC register field. */
7806 #define ALT_SDMMC_HCON_AC_LSB 27
7807 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_AC register field. */
7808 #define ALT_SDMMC_HCON_AC_MSB 27
7809 /* The width in bits of the ALT_SDMMC_HCON_AC register field. */
7810 #define ALT_SDMMC_HCON_AC_WIDTH 1
7811 /* The mask used to set the ALT_SDMMC_HCON_AC register field value. */
7812 #define ALT_SDMMC_HCON_AC_SET_MSK 0x08000000
7813 /* The mask used to clear the ALT_SDMMC_HCON_AC register field value. */
7814 #define ALT_SDMMC_HCON_AC_CLR_MSK 0xf7ffffff
7815 /* The reset value of the ALT_SDMMC_HCON_AC register field. */
7816 #define ALT_SDMMC_HCON_AC_RESET 0x0
7817 /* Extracts the ALT_SDMMC_HCON_AC field value from a register. */
7818 #define ALT_SDMMC_HCON_AC_GET(value) (((value) & 0x08000000) >> 27)
7819 /* Produces a ALT_SDMMC_HCON_AC register field value suitable for setting the register. */
7820 #define ALT_SDMMC_HCON_AC_SET(value) (((value) << 27) & 0x08000000)
7821 
7822 #ifndef __ASSEMBLY__
7823 /*
7824  * WARNING: The C register and register group struct declarations are provided for
7825  * convenience and illustrative purposes. They should, however, be used with
7826  * caution as the C language standard provides no guarantees about the alignment or
7827  * atomicity of device memory accesses. The recommended practice for writing
7828  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7829  * alt_write_word() functions.
7830  *
7831  * The struct declaration for register ALT_SDMMC_HCON.
7832  */
7833 struct ALT_SDMMC_HCON_s
7834 {
7835  const uint32_t ct : 1; /* Card Type */
7836  const uint32_t nc : 5; /* Number of Cards */
7837  const uint32_t hbus : 1; /* Slave Bus Type */
7838  const uint32_t hdatawidth : 3; /* Slave Bus Data Width */
7839  const uint32_t haddrwidth : 6; /* Slave Bus Address Width */
7840  const uint32_t dmaintf : 2; /* DMA Interface Type */
7841  const uint32_t dmadatawidth : 3; /* Generic DMA Data Width */
7842  const uint32_t rios : 1; /* FIFO RAM Location */
7843  const uint32_t ihr : 1; /* Implement Hold Register */
7844  const uint32_t scfp : 1; /* Clock False Path */
7845  const uint32_t ncd : 2; /* Number of Clock Dividers */
7846  const uint32_t aro : 1; /* Area Optimized */
7847  const uint32_t ac : 1; /* ALT_SDMMC_HCON_AC */
7848  uint32_t : 4; /* *UNDEFINED* */
7849 };
7850 
7851 /* The typedef declaration for register ALT_SDMMC_HCON. */
7852 typedef volatile struct ALT_SDMMC_HCON_s ALT_SDMMC_HCON_t;
7853 #endif /* __ASSEMBLY__ */
7854 
7855 /* The reset value of the ALT_SDMMC_HCON register. */
7856 #define ALT_SDMMC_HCON_RESET 0x00c43081
7857 /* The byte offset of the ALT_SDMMC_HCON register from the beginning of the component. */
7858 #define ALT_SDMMC_HCON_OFST 0x70
7859 
7860 /*
7861  * Register : uhs_reg
7862  *
7863  * UHS-1 Register
7864  *
7865  * Register Layout
7866  *
7867  * Bits | Access | Reset | Description
7868  * :--------|:-------|:------|:---------------------------
7869  * [15:0] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG
7870  * [31:16] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG
7871  *
7872  */
7873 /*
7874  * Field : volt_reg
7875  *
7876  * High Voltage mode. Determines the voltage fed to the buffers by an
7877  *
7878  * external voltage regulator.
7879  *
7880  * 0 Buffers supplied with 3.3V Vdd
7881  *
7882  * 1 Buffers supplied with 1.8V Vdd
7883  *
7884  * These bits function as the output of the host controller and are fed to an
7885  * external voltage regulator. The voltage regulator must switch the voltage of the
7886  * buffers of a particular card to either 3.3V or 1.8V, depending on the
7887  *
7888  * value programmed in the register.
7889  *
7890  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
7891  *
7892  * operate for 1.8V.
7893  *
7894  * Field Enumeration Values:
7895  *
7896  * Enum | Value | Description
7897  * :------------------------------------|:------|:-------------------------------
7898  * ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF33V | 0x0 | Buffers supplied with 3.3V Vdd
7899  * ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF18V | 0x1 | Buffers supplied with 1.8V Vdd
7900  *
7901  * Field Access Macros:
7902  *
7903  */
7904 /*
7905  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG
7906  *
7907  * Buffers supplied with 3.3V Vdd
7908  */
7909 #define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF33V 0x0
7910 /*
7911  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG
7912  *
7913  * Buffers supplied with 1.8V Vdd
7914  */
7915 #define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF18V 0x1
7916 
7917 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG register field. */
7918 #define ALT_SDMMC_UHS_REG_VOLT_REG_LSB 0
7919 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG register field. */
7920 #define ALT_SDMMC_UHS_REG_VOLT_REG_MSB 15
7921 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG register field. */
7922 #define ALT_SDMMC_UHS_REG_VOLT_REG_WIDTH 16
7923 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG register field value. */
7924 #define ALT_SDMMC_UHS_REG_VOLT_REG_SET_MSK 0x0000ffff
7925 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG register field value. */
7926 #define ALT_SDMMC_UHS_REG_VOLT_REG_CLR_MSK 0xffff0000
7927 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG register field. */
7928 #define ALT_SDMMC_UHS_REG_VOLT_REG_RESET 0x0
7929 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG field value from a register. */
7930 #define ALT_SDMMC_UHS_REG_VOLT_REG_GET(value) (((value) & 0x0000ffff) >> 0)
7931 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG register field value suitable for setting the register. */
7932 #define ALT_SDMMC_UHS_REG_VOLT_REG_SET(value) (((value) << 0) & 0x0000ffff)
7933 
7934 /*
7935  * Field : ddr_reg
7936  *
7937  * DDR mode. These bits indicate DDR mode of operation to the core for the data
7938  * transfer.
7939  *
7940  * 0 Non-DDR mode
7941  *
7942  * 1 DDR mode
7943  *
7944  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
7945  * so on.
7946  *
7947  * Field Enumeration Values:
7948  *
7949  * Enum | Value | Description
7950  * :-----------------------------------|:------|:-------------
7951  * ALT_SDMMC_UHS_REG_DDR_REG_E_NONDDR | 0x0 | Non-DDR mode
7952  * ALT_SDMMC_UHS_REG_DDR_REG_E_DDR | 0x1 | DDR mode
7953  *
7954  * Field Access Macros:
7955  *
7956  */
7957 /*
7958  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG
7959  *
7960  * Non-DDR mode
7961  */
7962 #define ALT_SDMMC_UHS_REG_DDR_REG_E_NONDDR 0x0
7963 /*
7964  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG
7965  *
7966  * DDR mode
7967  */
7968 #define ALT_SDMMC_UHS_REG_DDR_REG_E_DDR 0x1
7969 
7970 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG register field. */
7971 #define ALT_SDMMC_UHS_REG_DDR_REG_LSB 16
7972 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG register field. */
7973 #define ALT_SDMMC_UHS_REG_DDR_REG_MSB 31
7974 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG register field. */
7975 #define ALT_SDMMC_UHS_REG_DDR_REG_WIDTH 16
7976 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG register field value. */
7977 #define ALT_SDMMC_UHS_REG_DDR_REG_SET_MSK 0xffff0000
7978 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG register field value. */
7979 #define ALT_SDMMC_UHS_REG_DDR_REG_CLR_MSK 0x0000ffff
7980 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG register field. */
7981 #define ALT_SDMMC_UHS_REG_DDR_REG_RESET 0x0
7982 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG field value from a register. */
7983 #define ALT_SDMMC_UHS_REG_DDR_REG_GET(value) (((value) & 0xffff0000) >> 16)
7984 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG register field value suitable for setting the register. */
7985 #define ALT_SDMMC_UHS_REG_DDR_REG_SET(value) (((value) << 16) & 0xffff0000)
7986 
7987 #ifndef __ASSEMBLY__
7988 /*
7989  * WARNING: The C register and register group struct declarations are provided for
7990  * convenience and illustrative purposes. They should, however, be used with
7991  * caution as the C language standard provides no guarantees about the alignment or
7992  * atomicity of device memory accesses. The recommended practice for writing
7993  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7994  * alt_write_word() functions.
7995  *
7996  * The struct declaration for register ALT_SDMMC_UHS_REG.
7997  */
7998 struct ALT_SDMMC_UHS_REG_s
7999 {
8000  uint32_t volt_reg : 16; /* ALT_SDMMC_UHS_REG_VOLT_REG */
8001  uint32_t ddr_reg : 16; /* ALT_SDMMC_UHS_REG_DDR_REG */
8002 };
8003 
8004 /* The typedef declaration for register ALT_SDMMC_UHS_REG. */
8005 typedef volatile struct ALT_SDMMC_UHS_REG_s ALT_SDMMC_UHS_REG_t;
8006 #endif /* __ASSEMBLY__ */
8007 
8008 /* The reset value of the ALT_SDMMC_UHS_REG register. */
8009 #define ALT_SDMMC_UHS_REG_RESET 0x00000000
8010 /* The byte offset of the ALT_SDMMC_UHS_REG register from the beginning of the component. */
8011 #define ALT_SDMMC_UHS_REG_OFST 0x74
8012 
8013 /*
8014  * Register : rst_n
8015  *
8016  * Hardware Reset Register
8017  *
8018  * Register Layout
8019  *
8020  * Bits | Access | Reset | Description
8021  * :-------|:-------|:------|:-------------------------
8022  * [0] | RW | 0x1 | ALT_SDMMC_RST_N_CARD_RST
8023  * [31:1] | ??? | 0x0 | *UNDEFINED*
8024  *
8025  */
8026 /*
8027  * Field : card_reset
8028  *
8029  * Hardware reset.
8030  *
8031  * 1 Active mode
8032  *
8033  * 0 Reset
8034  *
8035  * These bits cause the cards to enter pre-idle state, which requires them to be
8036  * re-initialized.
8037  *
8038  * ? CARD_RESET[0] should be set to 1'b0 to reset card number 0
8039  *
8040  * ? CARD_RESET[15] should be set to 1'b0 to reset card number 15.
8041  *
8042  * The number of bits implemented is restricted to NUM_CARDS.
8043  *
8044  * Field Enumeration Values:
8045  *
8046  * Enum | Value | Description
8047  * :------------------------------------|:------|:----------------
8048  * ALT_SDMMC_RST_N_CARD_RST_E_DEASSERT | 0x0 | Not Active Mode
8049  * ALT_SDMMC_RST_N_CARD_RST_E_ASSERT | 0x1 | Active Mode
8050  *
8051  * Field Access Macros:
8052  *
8053  */
8054 /*
8055  * Enumerated value for register field ALT_SDMMC_RST_N_CARD_RST
8056  *
8057  * Not Active Mode
8058  */
8059 #define ALT_SDMMC_RST_N_CARD_RST_E_DEASSERT 0x0
8060 /*
8061  * Enumerated value for register field ALT_SDMMC_RST_N_CARD_RST
8062  *
8063  * Active Mode
8064  */
8065 #define ALT_SDMMC_RST_N_CARD_RST_E_ASSERT 0x1
8066 
8067 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RST_N_CARD_RST register field. */
8068 #define ALT_SDMMC_RST_N_CARD_RST_LSB 0
8069 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RST_N_CARD_RST register field. */
8070 #define ALT_SDMMC_RST_N_CARD_RST_MSB 0
8071 /* The width in bits of the ALT_SDMMC_RST_N_CARD_RST register field. */
8072 #define ALT_SDMMC_RST_N_CARD_RST_WIDTH 1
8073 /* The mask used to set the ALT_SDMMC_RST_N_CARD_RST register field value. */
8074 #define ALT_SDMMC_RST_N_CARD_RST_SET_MSK 0x00000001
8075 /* The mask used to clear the ALT_SDMMC_RST_N_CARD_RST register field value. */
8076 #define ALT_SDMMC_RST_N_CARD_RST_CLR_MSK 0xfffffffe
8077 /* The reset value of the ALT_SDMMC_RST_N_CARD_RST register field. */
8078 #define ALT_SDMMC_RST_N_CARD_RST_RESET 0x1
8079 /* Extracts the ALT_SDMMC_RST_N_CARD_RST field value from a register. */
8080 #define ALT_SDMMC_RST_N_CARD_RST_GET(value) (((value) & 0x00000001) >> 0)
8081 /* Produces a ALT_SDMMC_RST_N_CARD_RST register field value suitable for setting the register. */
8082 #define ALT_SDMMC_RST_N_CARD_RST_SET(value) (((value) << 0) & 0x00000001)
8083 
8084 #ifndef __ASSEMBLY__
8085 /*
8086  * WARNING: The C register and register group struct declarations are provided for
8087  * convenience and illustrative purposes. They should, however, be used with
8088  * caution as the C language standard provides no guarantees about the alignment or
8089  * atomicity of device memory accesses. The recommended practice for writing
8090  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8091  * alt_write_word() functions.
8092  *
8093  * The struct declaration for register ALT_SDMMC_RST_N.
8094  */
8095 struct ALT_SDMMC_RST_N_s
8096 {
8097  uint32_t card_reset : 1; /* ALT_SDMMC_RST_N_CARD_RST */
8098  uint32_t : 31; /* *UNDEFINED* */
8099 };
8100 
8101 /* The typedef declaration for register ALT_SDMMC_RST_N. */
8102 typedef volatile struct ALT_SDMMC_RST_N_s ALT_SDMMC_RST_N_t;
8103 #endif /* __ASSEMBLY__ */
8104 
8105 /* The reset value of the ALT_SDMMC_RST_N register. */
8106 #define ALT_SDMMC_RST_N_RESET 0x00000001
8107 /* The byte offset of the ALT_SDMMC_RST_N register from the beginning of the component. */
8108 #define ALT_SDMMC_RST_N_OFST 0x78
8109 
8110 /*
8111  * Register : bmod
8112  *
8113  * Bus Mode Register
8114  *
8115  * Register Layout
8116  *
8117  * Bits | Access | Reset | Description
8118  * :--------|:-------|:------|:-------------------
8119  * [0] | RW | 0x0 | ALT_SDMMC_BMOD_SWR
8120  * [1] | RW | 0x0 | ALT_SDMMC_BMOD_FB
8121  * [6:2] | RW | 0x0 | ALT_SDMMC_BMOD_DSL
8122  * [7] | RW | 0x0 | ALT_SDMMC_BMOD_DE
8123  * [10:8] | R | 0x0 | ALT_SDMMC_BMOD_PBL
8124  * [31:11] | ??? | 0x0 | *UNDEFINED*
8125  *
8126  */
8127 /*
8128  * Field : swr
8129  *
8130  * Software Reset.When set,the DMA Controller resets all its internal registers.
8131  *
8132  * SWR is read/write. It is automatically cleared after 1 clock cycle.
8133  *
8134  * Field Enumeration Values:
8135  *
8136  * Enum | Value | Description
8137  * :------------------------------|:------|:------------------------------
8138  * ALT_SDMMC_BMOD_SWR_E_NOSFTRST | 0x0 | No reset - default
8139  * ALT_SDMMC_BMOD_SWR_E_SFTRST | 0x1 | Resets DMA Internal Registers
8140  *
8141  * Field Access Macros:
8142  *
8143  */
8144 /*
8145  * Enumerated value for register field ALT_SDMMC_BMOD_SWR
8146  *
8147  * No reset - default
8148  */
8149 #define ALT_SDMMC_BMOD_SWR_E_NOSFTRST 0x0
8150 /*
8151  * Enumerated value for register field ALT_SDMMC_BMOD_SWR
8152  *
8153  * Resets DMA Internal Registers
8154  */
8155 #define ALT_SDMMC_BMOD_SWR_E_SFTRST 0x1
8156 
8157 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_SWR register field. */
8158 #define ALT_SDMMC_BMOD_SWR_LSB 0
8159 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_SWR register field. */
8160 #define ALT_SDMMC_BMOD_SWR_MSB 0
8161 /* The width in bits of the ALT_SDMMC_BMOD_SWR register field. */
8162 #define ALT_SDMMC_BMOD_SWR_WIDTH 1
8163 /* The mask used to set the ALT_SDMMC_BMOD_SWR register field value. */
8164 #define ALT_SDMMC_BMOD_SWR_SET_MSK 0x00000001
8165 /* The mask used to clear the ALT_SDMMC_BMOD_SWR register field value. */
8166 #define ALT_SDMMC_BMOD_SWR_CLR_MSK 0xfffffffe
8167 /* The reset value of the ALT_SDMMC_BMOD_SWR register field. */
8168 #define ALT_SDMMC_BMOD_SWR_RESET 0x0
8169 /* Extracts the ALT_SDMMC_BMOD_SWR field value from a register. */
8170 #define ALT_SDMMC_BMOD_SWR_GET(value) (((value) & 0x00000001) >> 0)
8171 /* Produces a ALT_SDMMC_BMOD_SWR register field value suitable for setting the register. */
8172 #define ALT_SDMMC_BMOD_SWR_SET(value) (((value) << 0) & 0x00000001)
8173 
8174 /*
8175  * Field : fb
8176  *
8177  * Fixed Burst. Controls whether the AHB Master interface performs fixed burst
8178  * transfers or not. When set,the AHB will use only SINGLE, INCR4, INCR8 or
8179  *
8180  * INCR16 during start of normal burst transfers.When reset,the AHB will use SINGLE
8181  * and INCR burst transfer operations.
8182  *
8183  * FB is read/write.
8184  *
8185  * Field Enumeration Values:
8186  *
8187  * Enum | Value | Description
8188  * :--------------------------------|:------|:--------------------------
8189  * ALT_SDMMC_BMOD_FB_E_NOFIXEDBRST | 0x0 | Non Fixed Burst - default
8190  * ALT_SDMMC_BMOD_FB_E_FIXEDBRST | 0x1 | AHB Master Fixed Burst
8191  *
8192  * Field Access Macros:
8193  *
8194  */
8195 /*
8196  * Enumerated value for register field ALT_SDMMC_BMOD_FB
8197  *
8198  * Non Fixed Burst - default
8199  */
8200 #define ALT_SDMMC_BMOD_FB_E_NOFIXEDBRST 0x0
8201 /*
8202  * Enumerated value for register field ALT_SDMMC_BMOD_FB
8203  *
8204  * AHB Master Fixed Burst
8205  */
8206 #define ALT_SDMMC_BMOD_FB_E_FIXEDBRST 0x1
8207 
8208 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_FB register field. */
8209 #define ALT_SDMMC_BMOD_FB_LSB 1
8210 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_FB register field. */
8211 #define ALT_SDMMC_BMOD_FB_MSB 1
8212 /* The width in bits of the ALT_SDMMC_BMOD_FB register field. */
8213 #define ALT_SDMMC_BMOD_FB_WIDTH 1
8214 /* The mask used to set the ALT_SDMMC_BMOD_FB register field value. */
8215 #define ALT_SDMMC_BMOD_FB_SET_MSK 0x00000002
8216 /* The mask used to clear the ALT_SDMMC_BMOD_FB register field value. */
8217 #define ALT_SDMMC_BMOD_FB_CLR_MSK 0xfffffffd
8218 /* The reset value of the ALT_SDMMC_BMOD_FB register field. */
8219 #define ALT_SDMMC_BMOD_FB_RESET 0x0
8220 /* Extracts the ALT_SDMMC_BMOD_FB field value from a register. */
8221 #define ALT_SDMMC_BMOD_FB_GET(value) (((value) & 0x00000002) >> 1)
8222 /* Produces a ALT_SDMMC_BMOD_FB register field value suitable for setting the register. */
8223 #define ALT_SDMMC_BMOD_FB_SET(value) (((value) << 1) & 0x00000002)
8224 
8225 /*
8226  * Field : dsl
8227  *
8228  * Descriptor Skip Length. Specifies the number of HWord/Word/Dword (depending on
8229  * 16/32/64-bit bus) to skip between two unchained descriptors. This is applicable
8230  * only for dual buffer structure.
8231  *
8232  * DSL is read/write.
8233  *
8234  * Field Access Macros:
8235  *
8236  */
8237 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_DSL register field. */
8238 #define ALT_SDMMC_BMOD_DSL_LSB 2
8239 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_DSL register field. */
8240 #define ALT_SDMMC_BMOD_DSL_MSB 6
8241 /* The width in bits of the ALT_SDMMC_BMOD_DSL register field. */
8242 #define ALT_SDMMC_BMOD_DSL_WIDTH 5
8243 /* The mask used to set the ALT_SDMMC_BMOD_DSL register field value. */
8244 #define ALT_SDMMC_BMOD_DSL_SET_MSK 0x0000007c
8245 /* The mask used to clear the ALT_SDMMC_BMOD_DSL register field value. */
8246 #define ALT_SDMMC_BMOD_DSL_CLR_MSK 0xffffff83
8247 /* The reset value of the ALT_SDMMC_BMOD_DSL register field. */
8248 #define ALT_SDMMC_BMOD_DSL_RESET 0x0
8249 /* Extracts the ALT_SDMMC_BMOD_DSL field value from a register. */
8250 #define ALT_SDMMC_BMOD_DSL_GET(value) (((value) & 0x0000007c) >> 2)
8251 /* Produces a ALT_SDMMC_BMOD_DSL register field value suitable for setting the register. */
8252 #define ALT_SDMMC_BMOD_DSL_SET(value) (((value) << 2) & 0x0000007c)
8253 
8254 /*
8255  * Field : de
8256  *
8257  * IDMAC Enable. When set, the IDMAC is enabled.
8258  *
8259  * DE is read/write.
8260  *
8261  * Field Enumeration Values:
8262  *
8263  * Enum | Value | Description
8264  * :-------------------------|:------|:--------------
8265  * ALT_SDMMC_BMOD_DE_E_DISD | 0x0 | IDMAC Disable
8266  * ALT_SDMMC_BMOD_DE_E_END | 0x1 | IDMAC Enable
8267  *
8268  * Field Access Macros:
8269  *
8270  */
8271 /*
8272  * Enumerated value for register field ALT_SDMMC_BMOD_DE
8273  *
8274  * IDMAC Disable
8275  */
8276 #define ALT_SDMMC_BMOD_DE_E_DISD 0x0
8277 /*
8278  * Enumerated value for register field ALT_SDMMC_BMOD_DE
8279  *
8280  * IDMAC Enable
8281  */
8282 #define ALT_SDMMC_BMOD_DE_E_END 0x1
8283 
8284 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_DE register field. */
8285 #define ALT_SDMMC_BMOD_DE_LSB 7
8286 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_DE register field. */
8287 #define ALT_SDMMC_BMOD_DE_MSB 7
8288 /* The width in bits of the ALT_SDMMC_BMOD_DE register field. */
8289 #define ALT_SDMMC_BMOD_DE_WIDTH 1
8290 /* The mask used to set the ALT_SDMMC_BMOD_DE register field value. */
8291 #define ALT_SDMMC_BMOD_DE_SET_MSK 0x00000080
8292 /* The mask used to clear the ALT_SDMMC_BMOD_DE register field value. */
8293 #define ALT_SDMMC_BMOD_DE_CLR_MSK 0xffffff7f
8294 /* The reset value of the ALT_SDMMC_BMOD_DE register field. */
8295 #define ALT_SDMMC_BMOD_DE_RESET 0x0
8296 /* Extracts the ALT_SDMMC_BMOD_DE field value from a register. */
8297 #define ALT_SDMMC_BMOD_DE_GET(value) (((value) & 0x00000080) >> 7)
8298 /* Produces a ALT_SDMMC_BMOD_DE register field value suitable for setting the register. */
8299 #define ALT_SDMMC_BMOD_DE_SET(value) (((value) << 7) & 0x00000080)
8300 
8301 /*
8302  * Field : pbl
8303  *
8304  * Programmable Burst Length. These bits indicate the maximum number of beats to be
8305  * performed in one IDMAC transaction. The IDMAC will always attempt to burst as
8306  * specified in PBL each time it starts a Burst transfer on the host bus. The
8307  * permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the
8308  * mirror of MSIZE of FIFOTH register. In order to change this value, write the
8309  * required value
8310  *
8311  * to FIFOTH register. This is an encode value as follows.
8312  *
8313  * 000 1 transfers
8314  *
8315  * 001 4 transfers
8316  *
8317  * 010 8 transfers
8318  *
8319  * 011 16 transfers
8320  *
8321  * 100 32 transfers
8322  *
8323  * 101 64 transfers
8324  *
8325  * 110 128 transfers
8326  *
8327  * 111 256 transfers
8328  *
8329  * Transfer unit is either 16, 32, or 64 bits, based on HDATA_WIDTH.
8330  *
8331  * PBL is a read-only value and is applicable only for Data Access; it does not
8332  * apply to descriptor accesses.
8333  *
8334  * Field Enumeration Values:
8335  *
8336  * Enum | Value | Description
8337  * :------------------------------|:------|:-------------
8338  * ALT_SDMMC_BMOD_PBL_E_TRANS1 | 0x0 | Transfer 1
8339  * ALT_SDMMC_BMOD_PBL_E_TRANS4 | 0x1 | Transfer 4
8340  * ALT_SDMMC_BMOD_PBL_E_TRANS8 | 0x2 | Transfer 8
8341  * ALT_SDMMC_BMOD_PBL_E_TRANS16 | 0x3 | Transfer 16
8342  * ALT_SDMMC_BMOD_PBL_E_TRANS32 | 0x4 | Transfer 32
8343  * ALT_SDMMC_BMOD_PBL_E_TRANS64 | 0x5 | Transfer 64
8344  * ALT_SDMMC_BMOD_PBL_E_TRANS128 | 0x6 | Transfer 128
8345  * ALT_SDMMC_BMOD_PBL_E_TRANS256 | 0x7 | Transfer 256
8346  *
8347  * Field Access Macros:
8348  *
8349  */
8350 /*
8351  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
8352  *
8353  * Transfer 1
8354  */
8355 #define ALT_SDMMC_BMOD_PBL_E_TRANS1 0x0
8356 /*
8357  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
8358  *
8359  * Transfer 4
8360  */
8361 #define ALT_SDMMC_BMOD_PBL_E_TRANS4 0x1
8362 /*
8363  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
8364  *
8365  * Transfer 8
8366  */
8367 #define ALT_SDMMC_BMOD_PBL_E_TRANS8 0x2
8368 /*
8369  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
8370  *
8371  * Transfer 16
8372  */
8373 #define ALT_SDMMC_BMOD_PBL_E_TRANS16 0x3
8374 /*
8375  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
8376  *
8377  * Transfer 32
8378  */
8379 #define ALT_SDMMC_BMOD_PBL_E_TRANS32 0x4
8380 /*
8381  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
8382  *
8383  * Transfer 64
8384  */
8385 #define ALT_SDMMC_BMOD_PBL_E_TRANS64 0x5
8386 /*
8387  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
8388  *
8389  * Transfer 128
8390  */
8391 #define ALT_SDMMC_BMOD_PBL_E_TRANS128 0x6
8392 /*
8393  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
8394  *
8395  * Transfer 256
8396  */
8397 #define ALT_SDMMC_BMOD_PBL_E_TRANS256 0x7
8398 
8399 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_PBL register field. */
8400 #define ALT_SDMMC_BMOD_PBL_LSB 8
8401 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_PBL register field. */
8402 #define ALT_SDMMC_BMOD_PBL_MSB 10
8403 /* The width in bits of the ALT_SDMMC_BMOD_PBL register field. */
8404 #define ALT_SDMMC_BMOD_PBL_WIDTH 3
8405 /* The mask used to set the ALT_SDMMC_BMOD_PBL register field value. */
8406 #define ALT_SDMMC_BMOD_PBL_SET_MSK 0x00000700
8407 /* The mask used to clear the ALT_SDMMC_BMOD_PBL register field value. */
8408 #define ALT_SDMMC_BMOD_PBL_CLR_MSK 0xfffff8ff
8409 /* The reset value of the ALT_SDMMC_BMOD_PBL register field. */
8410 #define ALT_SDMMC_BMOD_PBL_RESET 0x0
8411 /* Extracts the ALT_SDMMC_BMOD_PBL field value from a register. */
8412 #define ALT_SDMMC_BMOD_PBL_GET(value) (((value) & 0x00000700) >> 8)
8413 /* Produces a ALT_SDMMC_BMOD_PBL register field value suitable for setting the register. */
8414 #define ALT_SDMMC_BMOD_PBL_SET(value) (((value) << 8) & 0x00000700)
8415 
8416 #ifndef __ASSEMBLY__
8417 /*
8418  * WARNING: The C register and register group struct declarations are provided for
8419  * convenience and illustrative purposes. They should, however, be used with
8420  * caution as the C language standard provides no guarantees about the alignment or
8421  * atomicity of device memory accesses. The recommended practice for writing
8422  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8423  * alt_write_word() functions.
8424  *
8425  * The struct declaration for register ALT_SDMMC_BMOD.
8426  */
8427 struct ALT_SDMMC_BMOD_s
8428 {
8429  uint32_t swr : 1; /* ALT_SDMMC_BMOD_SWR */
8430  uint32_t fb : 1; /* ALT_SDMMC_BMOD_FB */
8431  uint32_t dsl : 5; /* ALT_SDMMC_BMOD_DSL */
8432  uint32_t de : 1; /* ALT_SDMMC_BMOD_DE */
8433  const uint32_t pbl : 3; /* ALT_SDMMC_BMOD_PBL */
8434  uint32_t : 21; /* *UNDEFINED* */
8435 };
8436 
8437 /* The typedef declaration for register ALT_SDMMC_BMOD. */
8438 typedef volatile struct ALT_SDMMC_BMOD_s ALT_SDMMC_BMOD_t;
8439 #endif /* __ASSEMBLY__ */
8440 
8441 /* The reset value of the ALT_SDMMC_BMOD register. */
8442 #define ALT_SDMMC_BMOD_RESET 0x00000000
8443 /* The byte offset of the ALT_SDMMC_BMOD register from the beginning of the component. */
8444 #define ALT_SDMMC_BMOD_OFST 0x80
8445 
8446 /*
8447  * Register : pldmnd
8448  *
8449  * Poll Demand Register
8450  *
8451  * Register Layout
8452  *
8453  * Bits | Access | Reset | Description
8454  * :-------|:-------|:------|:--------------------
8455  * [31:0] | W | 0x0 | ALT_SDMMC_PLDMND_PD
8456  *
8457  */
8458 /*
8459  * Field : pd
8460  *
8461  * Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the
8462  * Suspend state. The host needs to write any value into this register for the
8463  * IDMAC FSM to resume normal
8464  *
8465  * descriptor fetch operation. This is a write only register.
8466  *
8467  * PD bit is write-only.
8468  *
8469  * Field Access Macros:
8470  *
8471  */
8472 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_PLDMND_PD register field. */
8473 #define ALT_SDMMC_PLDMND_PD_LSB 0
8474 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_PLDMND_PD register field. */
8475 #define ALT_SDMMC_PLDMND_PD_MSB 31
8476 /* The width in bits of the ALT_SDMMC_PLDMND_PD register field. */
8477 #define ALT_SDMMC_PLDMND_PD_WIDTH 32
8478 /* The mask used to set the ALT_SDMMC_PLDMND_PD register field value. */
8479 #define ALT_SDMMC_PLDMND_PD_SET_MSK 0xffffffff
8480 /* The mask used to clear the ALT_SDMMC_PLDMND_PD register field value. */
8481 #define ALT_SDMMC_PLDMND_PD_CLR_MSK 0x00000000
8482 /* The reset value of the ALT_SDMMC_PLDMND_PD register field. */
8483 #define ALT_SDMMC_PLDMND_PD_RESET 0x0
8484 /* Extracts the ALT_SDMMC_PLDMND_PD field value from a register. */
8485 #define ALT_SDMMC_PLDMND_PD_GET(value) (((value) & 0xffffffff) >> 0)
8486 /* Produces a ALT_SDMMC_PLDMND_PD register field value suitable for setting the register. */
8487 #define ALT_SDMMC_PLDMND_PD_SET(value) (((value) << 0) & 0xffffffff)
8488 
8489 #ifndef __ASSEMBLY__
8490 /*
8491  * WARNING: The C register and register group struct declarations are provided for
8492  * convenience and illustrative purposes. They should, however, be used with
8493  * caution as the C language standard provides no guarantees about the alignment or
8494  * atomicity of device memory accesses. The recommended practice for writing
8495  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8496  * alt_write_word() functions.
8497  *
8498  * The struct declaration for register ALT_SDMMC_PLDMND.
8499  */
8500 struct ALT_SDMMC_PLDMND_s
8501 {
8502  uint32_t pd : 32; /* ALT_SDMMC_PLDMND_PD */
8503 };
8504 
8505 /* The typedef declaration for register ALT_SDMMC_PLDMND. */
8506 typedef volatile struct ALT_SDMMC_PLDMND_s ALT_SDMMC_PLDMND_t;
8507 #endif /* __ASSEMBLY__ */
8508 
8509 /* The reset value of the ALT_SDMMC_PLDMND register. */
8510 #define ALT_SDMMC_PLDMND_RESET 0x00000000
8511 /* The byte offset of the ALT_SDMMC_PLDMND register from the beginning of the component. */
8512 #define ALT_SDMMC_PLDMND_OFST 0x84
8513 
8514 /*
8515  * Register : dbaddr
8516  *
8517  * Descriptor List Base Address Register
8518  *
8519  * Register Layout
8520  *
8521  * Bits | Access | Reset | Description
8522  * :-------|:-------|:------|:---------------------
8523  * [31:0] | RW | 0x0 | ALT_SDMMC_DBADDR_SDL
8524  *
8525  */
8526 /*
8527  * Field : sdl
8528  *
8529  * Start of Descriptor List. Contains the base address of the First Descriptor.
8530  *
8531  * The LSB bits [0/1/2:0] for 16/32/64-bit bus-width) are ignored and taken as all-
8532  * zero by the IDMAC internally. Hence these LSB bits are read-only.
8533  *
8534  * Field Access Macros:
8535  *
8536  */
8537 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_DBADDR_SDL register field. */
8538 #define ALT_SDMMC_DBADDR_SDL_LSB 0
8539 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_DBADDR_SDL register field. */
8540 #define ALT_SDMMC_DBADDR_SDL_MSB 31
8541 /* The width in bits of the ALT_SDMMC_DBADDR_SDL register field. */
8542 #define ALT_SDMMC_DBADDR_SDL_WIDTH 32
8543 /* The mask used to set the ALT_SDMMC_DBADDR_SDL register field value. */
8544 #define ALT_SDMMC_DBADDR_SDL_SET_MSK 0xffffffff
8545 /* The mask used to clear the ALT_SDMMC_DBADDR_SDL register field value. */
8546 #define ALT_SDMMC_DBADDR_SDL_CLR_MSK 0x00000000
8547 /* The reset value of the ALT_SDMMC_DBADDR_SDL register field. */
8548 #define ALT_SDMMC_DBADDR_SDL_RESET 0x0
8549 /* Extracts the ALT_SDMMC_DBADDR_SDL field value from a register. */
8550 #define ALT_SDMMC_DBADDR_SDL_GET(value) (((value) & 0xffffffff) >> 0)
8551 /* Produces a ALT_SDMMC_DBADDR_SDL register field value suitable for setting the register. */
8552 #define ALT_SDMMC_DBADDR_SDL_SET(value) (((value) << 0) & 0xffffffff)
8553 
8554 #ifndef __ASSEMBLY__
8555 /*
8556  * WARNING: The C register and register group struct declarations are provided for
8557  * convenience and illustrative purposes. They should, however, be used with
8558  * caution as the C language standard provides no guarantees about the alignment or
8559  * atomicity of device memory accesses. The recommended practice for writing
8560  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8561  * alt_write_word() functions.
8562  *
8563  * The struct declaration for register ALT_SDMMC_DBADDR.
8564  */
8565 struct ALT_SDMMC_DBADDR_s
8566 {
8567  uint32_t sdl : 32; /* ALT_SDMMC_DBADDR_SDL */
8568 };
8569 
8570 /* The typedef declaration for register ALT_SDMMC_DBADDR. */
8571 typedef volatile struct ALT_SDMMC_DBADDR_s ALT_SDMMC_DBADDR_t;
8572 #endif /* __ASSEMBLY__ */
8573 
8574 /* The reset value of the ALT_SDMMC_DBADDR register. */
8575 #define ALT_SDMMC_DBADDR_RESET 0x00000000
8576 /* The byte offset of the ALT_SDMMC_DBADDR register from the beginning of the component. */
8577 #define ALT_SDMMC_DBADDR_OFST 0x88
8578 
8579 /*
8580  * Register : idsts
8581  *
8582  * Internal DMAC Status Register
8583  *
8584  * Register Layout
8585  *
8586  * Bits | Access | Reset | Description
8587  * :--------|:-------|:------|:--------------------
8588  * [0] | RW | 0x0 | ALT_SDMMC_IDSTS_TI
8589  * [1] | RW | 0x0 | ALT_SDMMC_IDSTS_RI
8590  * [2] | RW | 0x0 | ALT_SDMMC_IDSTS_FBE
8591  * [3] | ??? | 0x0 | *UNDEFINED*
8592  * [4] | RW | 0x0 | ALT_SDMMC_IDSTS_DU
8593  * [5] | RW | 0x0 | ALT_SDMMC_IDSTS_CES
8594  * [7:6] | ??? | 0x0 | *UNDEFINED*
8595  * [8] | RW | 0x0 | ALT_SDMMC_IDSTS_NIS
8596  * [9] | RW | 0x0 | ALT_SDMMC_IDSTS_AIS
8597  * [12:10] | R | 0x0 | ALT_SDMMC_IDSTS_EB
8598  * [16:13] | R | 0x0 | ALT_SDMMC_IDSTS_FSM
8599  * [31:17] | ??? | 0x0 | *UNDEFINED*
8600  *
8601  */
8602 /*
8603  * Field : ti
8604  *
8605  * Transmit Interrupt. Indicates that data transmission is finished for a
8606  * descriptor. Writing a '1' clears this bit.
8607  *
8608  * Field Enumeration Values:
8609  *
8610  * Enum | Value | Description
8611  * :---------------------------|:------|:------------------------------------------
8612  * ALT_SDMMC_IDSTS_TI_E_NOCLR | 0x0 | No Clear of Transmit Interrupt Status Bit
8613  * ALT_SDMMC_IDSTS_TI_E_CLR | 0x1 | Clears Transmit Interrupt Status Bit
8614  *
8615  * Field Access Macros:
8616  *
8617  */
8618 /*
8619  * Enumerated value for register field ALT_SDMMC_IDSTS_TI
8620  *
8621  * No Clear of Transmit Interrupt Status Bit
8622  */
8623 #define ALT_SDMMC_IDSTS_TI_E_NOCLR 0x0
8624 /*
8625  * Enumerated value for register field ALT_SDMMC_IDSTS_TI
8626  *
8627  * Clears Transmit Interrupt Status Bit
8628  */
8629 #define ALT_SDMMC_IDSTS_TI_E_CLR 0x1
8630 
8631 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_TI register field. */
8632 #define ALT_SDMMC_IDSTS_TI_LSB 0
8633 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_TI register field. */
8634 #define ALT_SDMMC_IDSTS_TI_MSB 0
8635 /* The width in bits of the ALT_SDMMC_IDSTS_TI register field. */
8636 #define ALT_SDMMC_IDSTS_TI_WIDTH 1
8637 /* The mask used to set the ALT_SDMMC_IDSTS_TI register field value. */
8638 #define ALT_SDMMC_IDSTS_TI_SET_MSK 0x00000001
8639 /* The mask used to clear the ALT_SDMMC_IDSTS_TI register field value. */
8640 #define ALT_SDMMC_IDSTS_TI_CLR_MSK 0xfffffffe
8641 /* The reset value of the ALT_SDMMC_IDSTS_TI register field. */
8642 #define ALT_SDMMC_IDSTS_TI_RESET 0x0
8643 /* Extracts the ALT_SDMMC_IDSTS_TI field value from a register. */
8644 #define ALT_SDMMC_IDSTS_TI_GET(value) (((value) & 0x00000001) >> 0)
8645 /* Produces a ALT_SDMMC_IDSTS_TI register field value suitable for setting the register. */
8646 #define ALT_SDMMC_IDSTS_TI_SET(value) (((value) << 0) & 0x00000001)
8647 
8648 /*
8649  * Field : ri
8650  *
8651  * Receive Interrupt. Indicates the completion of data reception for a descriptor.
8652  * Writing a 1 clears this bit.
8653  *
8654  * Field Enumeration Values:
8655  *
8656  * Enum | Value | Description
8657  * :---------------------------|:------|:-----------------------------------------
8658  * ALT_SDMMC_IDSTS_RI_E_NOCLR | 0x0 | No Clear of Receive Interrupt Status Bit
8659  * ALT_SDMMC_IDSTS_RI_E_CLR | 0x1 | Clears Receive Interrupt Status Bit
8660  *
8661  * Field Access Macros:
8662  *
8663  */
8664 /*
8665  * Enumerated value for register field ALT_SDMMC_IDSTS_RI
8666  *
8667  * No Clear of Receive Interrupt Status Bit
8668  */
8669 #define ALT_SDMMC_IDSTS_RI_E_NOCLR 0x0
8670 /*
8671  * Enumerated value for register field ALT_SDMMC_IDSTS_RI
8672  *
8673  * Clears Receive Interrupt Status Bit
8674  */
8675 #define ALT_SDMMC_IDSTS_RI_E_CLR 0x1
8676 
8677 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_RI register field. */
8678 #define ALT_SDMMC_IDSTS_RI_LSB 1
8679 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_RI register field. */
8680 #define ALT_SDMMC_IDSTS_RI_MSB 1
8681 /* The width in bits of the ALT_SDMMC_IDSTS_RI register field. */
8682 #define ALT_SDMMC_IDSTS_RI_WIDTH 1
8683 /* The mask used to set the ALT_SDMMC_IDSTS_RI register field value. */
8684 #define ALT_SDMMC_IDSTS_RI_SET_MSK 0x00000002
8685 /* The mask used to clear the ALT_SDMMC_IDSTS_RI register field value. */
8686 #define ALT_SDMMC_IDSTS_RI_CLR_MSK 0xfffffffd
8687 /* The reset value of the ALT_SDMMC_IDSTS_RI register field. */
8688 #define ALT_SDMMC_IDSTS_RI_RESET 0x0
8689 /* Extracts the ALT_SDMMC_IDSTS_RI field value from a register. */
8690 #define ALT_SDMMC_IDSTS_RI_GET(value) (((value) & 0x00000002) >> 1)
8691 /* Produces a ALT_SDMMC_IDSTS_RI register field value suitable for setting the register. */
8692 #define ALT_SDMMC_IDSTS_RI_SET(value) (((value) << 1) & 0x00000002)
8693 
8694 /*
8695  * Field : fbe
8696  *
8697  * Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]).
8698  * When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears
8699  * this bit.
8700  *
8701  * Field Enumeration Values:
8702  *
8703  * Enum | Value | Description
8704  * :----------------------------|:------|:-------------------------------------------------
8705  * ALT_SDMMC_IDSTS_FBE_E_NOCLR | 0x0 | No Clear of Fatal Bus Error Interrupt Status Bit
8706  * ALT_SDMMC_IDSTS_FBE_E_CLR | 0x1 | Clears Fatal Bus Error Interrupt Status Bit
8707  *
8708  * Field Access Macros:
8709  *
8710  */
8711 /*
8712  * Enumerated value for register field ALT_SDMMC_IDSTS_FBE
8713  *
8714  * No Clear of Fatal Bus Error Interrupt Status Bit
8715  */
8716 #define ALT_SDMMC_IDSTS_FBE_E_NOCLR 0x0
8717 /*
8718  * Enumerated value for register field ALT_SDMMC_IDSTS_FBE
8719  *
8720  * Clears Fatal Bus Error Interrupt Status Bit
8721  */
8722 #define ALT_SDMMC_IDSTS_FBE_E_CLR 0x1
8723 
8724 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_FBE register field. */
8725 #define ALT_SDMMC_IDSTS_FBE_LSB 2
8726 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_FBE register field. */
8727 #define ALT_SDMMC_IDSTS_FBE_MSB 2
8728 /* The width in bits of the ALT_SDMMC_IDSTS_FBE register field. */
8729 #define ALT_SDMMC_IDSTS_FBE_WIDTH 1
8730 /* The mask used to set the ALT_SDMMC_IDSTS_FBE register field value. */
8731 #define ALT_SDMMC_IDSTS_FBE_SET_MSK 0x00000004
8732 /* The mask used to clear the ALT_SDMMC_IDSTS_FBE register field value. */
8733 #define ALT_SDMMC_IDSTS_FBE_CLR_MSK 0xfffffffb
8734 /* The reset value of the ALT_SDMMC_IDSTS_FBE register field. */
8735 #define ALT_SDMMC_IDSTS_FBE_RESET 0x0
8736 /* Extracts the ALT_SDMMC_IDSTS_FBE field value from a register. */
8737 #define ALT_SDMMC_IDSTS_FBE_GET(value) (((value) & 0x00000004) >> 2)
8738 /* Produces a ALT_SDMMC_IDSTS_FBE register field value suitable for setting the register. */
8739 #define ALT_SDMMC_IDSTS_FBE_SET(value) (((value) << 2) & 0x00000004)
8740 
8741 /*
8742  * Field : du
8743  *
8744  * Descriptor Unavailable Interrupt. This bit is set when the descriptor is
8745  * unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit.
8746  *
8747  * Field Enumeration Values:
8748  *
8749  * Enum | Value | Description
8750  * :---------------------------|:------|:-----------------------------------------------
8751  * ALT_SDMMC_IDSTS_DU_E_NOCLR | 0x0 | No Clear of Descriptor Unavailable Interrupt
8752  * : | | Status Bit
8753  * ALT_SDMMC_IDSTS_DU_E_CLR | 0x1 | Clears Descriptor Unavailable Interrupt Status
8754  * : | | Bit
8755  *
8756  * Field Access Macros:
8757  *
8758  */
8759 /*
8760  * Enumerated value for register field ALT_SDMMC_IDSTS_DU
8761  *
8762  * No Clear of Descriptor Unavailable Interrupt Status Bit
8763  */
8764 #define ALT_SDMMC_IDSTS_DU_E_NOCLR 0x0
8765 /*
8766  * Enumerated value for register field ALT_SDMMC_IDSTS_DU
8767  *
8768  * Clears Descriptor Unavailable Interrupt Status Bit
8769  */
8770 #define ALT_SDMMC_IDSTS_DU_E_CLR 0x1
8771 
8772 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_DU register field. */
8773 #define ALT_SDMMC_IDSTS_DU_LSB 4
8774 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_DU register field. */
8775 #define ALT_SDMMC_IDSTS_DU_MSB 4
8776 /* The width in bits of the ALT_SDMMC_IDSTS_DU register field. */
8777 #define ALT_SDMMC_IDSTS_DU_WIDTH 1
8778 /* The mask used to set the ALT_SDMMC_IDSTS_DU register field value. */
8779 #define ALT_SDMMC_IDSTS_DU_SET_MSK 0x00000010
8780 /* The mask used to clear the ALT_SDMMC_IDSTS_DU register field value. */
8781 #define ALT_SDMMC_IDSTS_DU_CLR_MSK 0xffffffef
8782 /* The reset value of the ALT_SDMMC_IDSTS_DU register field. */
8783 #define ALT_SDMMC_IDSTS_DU_RESET 0x0
8784 /* Extracts the ALT_SDMMC_IDSTS_DU field value from a register. */
8785 #define ALT_SDMMC_IDSTS_DU_GET(value) (((value) & 0x00000010) >> 4)
8786 /* Produces a ALT_SDMMC_IDSTS_DU register field value suitable for setting the register. */
8787 #define ALT_SDMMC_IDSTS_DU_SET(value) (((value) << 4) & 0x00000010)
8788 
8789 /*
8790  * Field : ces
8791  *
8792  * Card Error Summary. Indicates the status of the transaction to/from the card;
8793  * also present in RINTSTS. Indicates the logical OR of the following bits:
8794  *
8795  * ? EBE End Bit Error
8796  *
8797  * ? RTO Response Timeout/Boot Ack Timeout
8798  *
8799  * ? RCRC Response CRC
8800  *
8801  * ? SBE Start Bit Error
8802  *
8803  * ? DRTO Data Read Timeout/BDS timeout
8804  *
8805  * ? DCRC Data CRC for Receive
8806  *
8807  * ? RE Response Error
8808  *
8809  * Writing a 1 clears this bit.
8810  *
8811  * The abort condition of the IDMAC depends on the setting of this CES bit. If the
8812  * CES bit
8813  *
8814  * is enabled, then the IDMAC aborts on a "response error"; however, it will not
8815  * abort if the
8816  *
8817  * CES bit is cleared.
8818  *
8819  * Field Enumeration Values:
8820  *
8821  * Enum | Value | Description
8822  * :----------------------------|:------|:-------------------------------------------------
8823  * ALT_SDMMC_IDSTS_CES_E_NOCLR | 0x0 | No Clear Card Error Summary Interrupt Status Bit
8824  * ALT_SDMMC_IDSTS_CES_E_CLR | 0x1 | Clears Card Error Summary Interrupt Status Bit
8825  *
8826  * Field Access Macros:
8827  *
8828  */
8829 /*
8830  * Enumerated value for register field ALT_SDMMC_IDSTS_CES
8831  *
8832  * No Clear Card Error Summary Interrupt Status Bit
8833  */
8834 #define ALT_SDMMC_IDSTS_CES_E_NOCLR 0x0
8835 /*
8836  * Enumerated value for register field ALT_SDMMC_IDSTS_CES
8837  *
8838  * Clears Card Error Summary Interrupt Status Bit
8839  */
8840 #define ALT_SDMMC_IDSTS_CES_E_CLR 0x1
8841 
8842 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_CES register field. */
8843 #define ALT_SDMMC_IDSTS_CES_LSB 5
8844 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_CES register field. */
8845 #define ALT_SDMMC_IDSTS_CES_MSB 5
8846 /* The width in bits of the ALT_SDMMC_IDSTS_CES register field. */
8847 #define ALT_SDMMC_IDSTS_CES_WIDTH 1
8848 /* The mask used to set the ALT_SDMMC_IDSTS_CES register field value. */
8849 #define ALT_SDMMC_IDSTS_CES_SET_MSK 0x00000020
8850 /* The mask used to clear the ALT_SDMMC_IDSTS_CES register field value. */
8851 #define ALT_SDMMC_IDSTS_CES_CLR_MSK 0xffffffdf
8852 /* The reset value of the ALT_SDMMC_IDSTS_CES register field. */
8853 #define ALT_SDMMC_IDSTS_CES_RESET 0x0
8854 /* Extracts the ALT_SDMMC_IDSTS_CES field value from a register. */
8855 #define ALT_SDMMC_IDSTS_CES_GET(value) (((value) & 0x00000020) >> 5)
8856 /* Produces a ALT_SDMMC_IDSTS_CES register field value suitable for setting the register. */
8857 #define ALT_SDMMC_IDSTS_CES_SET(value) (((value) << 5) & 0x00000020)
8858 
8859 /*
8860  * Field : nis
8861  *
8862  * Normal Interrupt Summary. Logical OR of the following:
8863  *
8864  * ? IDSTS[0]-Transmit Interrupt
8865  *
8866  * ? IDSTS[1]-Receive Interrupt
8867  *
8868  * Only unmasked bits affect this bit.
8869  *
8870  * This is a sticky bit and must be cleared each time a corresponding bit that
8871  * causes NIS
8872  *
8873  * to be set is cleared. Writing a 1 clears this bit.
8874  *
8875  * Field Enumeration Values:
8876  *
8877  * Enum | Value | Description
8878  * :----------------------------|:------|:----------------------------------------------
8879  * ALT_SDMMC_IDSTS_NIS_E_NOCLR | 0x0 | No Clear Normal Interrupt Summary Status Bit
8880  * ALT_SDMMC_IDSTS_NIS_E_CLR | 0x1 | Clears Normal Interrupt Summary Status Bit
8881  *
8882  * Field Access Macros:
8883  *
8884  */
8885 /*
8886  * Enumerated value for register field ALT_SDMMC_IDSTS_NIS
8887  *
8888  * No Clear Normal Interrupt Summary Status Bit
8889  */
8890 #define ALT_SDMMC_IDSTS_NIS_E_NOCLR 0x0
8891 /*
8892  * Enumerated value for register field ALT_SDMMC_IDSTS_NIS
8893  *
8894  * Clears Normal Interrupt Summary Status Bit
8895  */
8896 #define ALT_SDMMC_IDSTS_NIS_E_CLR 0x1
8897 
8898 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_NIS register field. */
8899 #define ALT_SDMMC_IDSTS_NIS_LSB 8
8900 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_NIS register field. */
8901 #define ALT_SDMMC_IDSTS_NIS_MSB 8
8902 /* The width in bits of the ALT_SDMMC_IDSTS_NIS register field. */
8903 #define ALT_SDMMC_IDSTS_NIS_WIDTH 1
8904 /* The mask used to set the ALT_SDMMC_IDSTS_NIS register field value. */
8905 #define ALT_SDMMC_IDSTS_NIS_SET_MSK 0x00000100
8906 /* The mask used to clear the ALT_SDMMC_IDSTS_NIS register field value. */
8907 #define ALT_SDMMC_IDSTS_NIS_CLR_MSK 0xfffffeff
8908 /* The reset value of the ALT_SDMMC_IDSTS_NIS register field. */
8909 #define ALT_SDMMC_IDSTS_NIS_RESET 0x0
8910 /* Extracts the ALT_SDMMC_IDSTS_NIS field value from a register. */
8911 #define ALT_SDMMC_IDSTS_NIS_GET(value) (((value) & 0x00000100) >> 8)
8912 /* Produces a ALT_SDMMC_IDSTS_NIS register field value suitable for setting the register. */
8913 #define ALT_SDMMC_IDSTS_NIS_SET(value) (((value) << 8) & 0x00000100)
8914 
8915 /*
8916  * Field : ais
8917  *
8918  * Abnormal Interrupt Summary. Logical OR of the following:
8919  *
8920  * ? IDSTS[2]-Fatal Bus Interrupt
8921  *
8922  * ? IDSTS[4]-DU bit Interrupt
8923  *
8924  * Only unmasked bits affect this bit.
8925  *
8926  * This is a sticky bit and must be cleared each time a corresponding bit that
8927  * causes AIS
8928  *
8929  * to be set is cleared. Writing a 1 clears this bit.
8930  *
8931  * Field Enumeration Values:
8932  *
8933  * Enum | Value | Description
8934  * :----------------------------|:------|:-----------------------------------------------
8935  * ALT_SDMMC_IDSTS_AIS_E_NOCLR | 0x0 | No Clear Abnormal Summary Interrupt Status Bit
8936  * ALT_SDMMC_IDSTS_AIS_E_CLR | 0x1 | Clears Abnormal Summary Interrupt Status Bit
8937  *
8938  * Field Access Macros:
8939  *
8940  */
8941 /*
8942  * Enumerated value for register field ALT_SDMMC_IDSTS_AIS
8943  *
8944  * No Clear Abnormal Summary Interrupt Status Bit
8945  */
8946 #define ALT_SDMMC_IDSTS_AIS_E_NOCLR 0x0
8947 /*
8948  * Enumerated value for register field ALT_SDMMC_IDSTS_AIS
8949  *
8950  * Clears Abnormal Summary Interrupt Status Bit
8951  */
8952 #define ALT_SDMMC_IDSTS_AIS_E_CLR 0x1
8953 
8954 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_AIS register field. */
8955 #define ALT_SDMMC_IDSTS_AIS_LSB 9
8956 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_AIS register field. */
8957 #define ALT_SDMMC_IDSTS_AIS_MSB 9
8958 /* The width in bits of the ALT_SDMMC_IDSTS_AIS register field. */
8959 #define ALT_SDMMC_IDSTS_AIS_WIDTH 1
8960 /* The mask used to set the ALT_SDMMC_IDSTS_AIS register field value. */
8961 #define ALT_SDMMC_IDSTS_AIS_SET_MSK 0x00000200
8962 /* The mask used to clear the ALT_SDMMC_IDSTS_AIS register field value. */
8963 #define ALT_SDMMC_IDSTS_AIS_CLR_MSK 0xfffffdff
8964 /* The reset value of the ALT_SDMMC_IDSTS_AIS register field. */
8965 #define ALT_SDMMC_IDSTS_AIS_RESET 0x0
8966 /* Extracts the ALT_SDMMC_IDSTS_AIS field value from a register. */
8967 #define ALT_SDMMC_IDSTS_AIS_GET(value) (((value) & 0x00000200) >> 9)
8968 /* Produces a ALT_SDMMC_IDSTS_AIS register field value suitable for setting the register. */
8969 #define ALT_SDMMC_IDSTS_AIS_SET(value) (((value) << 9) & 0x00000200)
8970 
8971 /*
8972  * Field : eb
8973  *
8974  * Error Bits. Indicates the type of error that caused a Bus Error.
8975  *
8976  * Valid only with Fatal Bus
8977  *
8978  * Error bitIDSTS[2] set. This field does not generate an interrupt.
8979  *
8980  * 3'b001 Host Abort received during transmission
8981  *
8982  * 3'b010 Host Abort received during reception
8983  *
8984  * Others: Reserved
8985  *
8986  * EB is read-only.
8987  *
8988  * Field Enumeration Values:
8989  *
8990  * Enum | Value | Description
8991  * :--------------------------------|:------|:------------------------------------------------
8992  * ALT_SDMMC_IDSTS_EB_E_HOSTARBTTX | 0x1 | Host Abort during transmission Status Bit
8993  * ALT_SDMMC_IDSTS_EB_E_HOSTARBRX | 0x2 | Host Abort received during reception Status Bit
8994  *
8995  * Field Access Macros:
8996  *
8997  */
8998 /*
8999  * Enumerated value for register field ALT_SDMMC_IDSTS_EB
9000  *
9001  * Host Abort during transmission Status Bit
9002  */
9003 #define ALT_SDMMC_IDSTS_EB_E_HOSTARBTTX 0x1
9004 /*
9005  * Enumerated value for register field ALT_SDMMC_IDSTS_EB
9006  *
9007  * Host Abort received during reception Status Bit
9008  */
9009 #define ALT_SDMMC_IDSTS_EB_E_HOSTARBRX 0x2
9010 
9011 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_EB register field. */
9012 #define ALT_SDMMC_IDSTS_EB_LSB 10
9013 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_EB register field. */
9014 #define ALT_SDMMC_IDSTS_EB_MSB 12
9015 /* The width in bits of the ALT_SDMMC_IDSTS_EB register field. */
9016 #define ALT_SDMMC_IDSTS_EB_WIDTH 3
9017 /* The mask used to set the ALT_SDMMC_IDSTS_EB register field value. */
9018 #define ALT_SDMMC_IDSTS_EB_SET_MSK 0x00001c00
9019 /* The mask used to clear the ALT_SDMMC_IDSTS_EB register field value. */
9020 #define ALT_SDMMC_IDSTS_EB_CLR_MSK 0xffffe3ff
9021 /* The reset value of the ALT_SDMMC_IDSTS_EB register field. */
9022 #define ALT_SDMMC_IDSTS_EB_RESET 0x0
9023 /* Extracts the ALT_SDMMC_IDSTS_EB field value from a register. */
9024 #define ALT_SDMMC_IDSTS_EB_GET(value) (((value) & 0x00001c00) >> 10)
9025 /* Produces a ALT_SDMMC_IDSTS_EB register field value suitable for setting the register. */
9026 #define ALT_SDMMC_IDSTS_EB_SET(value) (((value) << 10) & 0x00001c00)
9027 
9028 /*
9029  * Field : fsm
9030  *
9031  * DMAC FSM present state.
9032  *
9033  * 0 DMA_IDLE
9034  *
9035  * 1 DMA_SUSPEND
9036  *
9037  * 2 DESC_RD
9038  *
9039  * 3 DESC_CHK
9040  *
9041  * 4 DMA_RD_REQ_WAIT
9042  *
9043  * 5 DMA_WR_REQ_WAIT
9044  *
9045  * 6 DMA_RD
9046  *
9047  * 7 DMA_WR
9048  *
9049  * 8 DESC_CLOSE
9050  *
9051  * This bit is read-only.
9052  *
9053  * Field Enumeration Values:
9054  *
9055  * Enum | Value | Description
9056  * :-----------------------------------|:------|:----------------
9057  * ALT_SDMMC_IDSTS_FSM_E_DMAIDLE | 0x0 | DMA IDLE
9058  * ALT_SDMMC_IDSTS_FSM_E_DMASUSPEND | 0x1 | DMA SUSPEND
9059  * ALT_SDMMC_IDSTS_FSM_E_DESCRD | 0x2 | DESC_RD
9060  * ALT_SDMMC_IDSTS_FSM_E_DESCCHK | 0x3 | DESC_CHK
9061  * ALT_SDMMC_IDSTS_FSM_E_DMARDREQWAIT | 0x4 | DMA RD REQ WAIT
9062  * ALT_SDMMC_IDSTS_FSM_E_DMAWRREQWAIT | 0x5 | DMA WR REQ WAIT
9063  * ALT_SDMMC_IDSTS_FSM_E_DMARD | 0x6 | DMA RD
9064  * ALT_SDMMC_IDSTS_FSM_E_DMAWR | 0x7 | DMA WR
9065  * ALT_SDMMC_IDSTS_FSM_E_DECCLOSE | 0x8 | DESC CLOSE
9066  *
9067  * Field Access Macros:
9068  *
9069  */
9070 /*
9071  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
9072  *
9073  * DMA IDLE
9074  */
9075 #define ALT_SDMMC_IDSTS_FSM_E_DMAIDLE 0x0
9076 /*
9077  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
9078  *
9079  * DMA SUSPEND
9080  */
9081 #define ALT_SDMMC_IDSTS_FSM_E_DMASUSPEND 0x1
9082 /*
9083  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
9084  *
9085  * DESC_RD
9086  */
9087 #define ALT_SDMMC_IDSTS_FSM_E_DESCRD 0x2
9088 /*
9089  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
9090  *
9091  * DESC_CHK
9092  */
9093 #define ALT_SDMMC_IDSTS_FSM_E_DESCCHK 0x3
9094 /*
9095  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
9096  *
9097  * DMA RD REQ WAIT
9098  */
9099 #define ALT_SDMMC_IDSTS_FSM_E_DMARDREQWAIT 0x4
9100 /*
9101  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
9102  *
9103  * DMA WR REQ WAIT
9104  */
9105 #define ALT_SDMMC_IDSTS_FSM_E_DMAWRREQWAIT 0x5
9106 /*
9107  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
9108  *
9109  * DMA RD
9110  */
9111 #define ALT_SDMMC_IDSTS_FSM_E_DMARD 0x6
9112 /*
9113  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
9114  *
9115  * DMA WR
9116  */
9117 #define ALT_SDMMC_IDSTS_FSM_E_DMAWR 0x7
9118 /*
9119  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
9120  *
9121  * DESC CLOSE
9122  */
9123 #define ALT_SDMMC_IDSTS_FSM_E_DECCLOSE 0x8
9124 
9125 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_FSM register field. */
9126 #define ALT_SDMMC_IDSTS_FSM_LSB 13
9127 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_FSM register field. */
9128 #define ALT_SDMMC_IDSTS_FSM_MSB 16
9129 /* The width in bits of the ALT_SDMMC_IDSTS_FSM register field. */
9130 #define ALT_SDMMC_IDSTS_FSM_WIDTH 4
9131 /* The mask used to set the ALT_SDMMC_IDSTS_FSM register field value. */
9132 #define ALT_SDMMC_IDSTS_FSM_SET_MSK 0x0001e000
9133 /* The mask used to clear the ALT_SDMMC_IDSTS_FSM register field value. */
9134 #define ALT_SDMMC_IDSTS_FSM_CLR_MSK 0xfffe1fff
9135 /* The reset value of the ALT_SDMMC_IDSTS_FSM register field. */
9136 #define ALT_SDMMC_IDSTS_FSM_RESET 0x0
9137 /* Extracts the ALT_SDMMC_IDSTS_FSM field value from a register. */
9138 #define ALT_SDMMC_IDSTS_FSM_GET(value) (((value) & 0x0001e000) >> 13)
9139 /* Produces a ALT_SDMMC_IDSTS_FSM register field value suitable for setting the register. */
9140 #define ALT_SDMMC_IDSTS_FSM_SET(value) (((value) << 13) & 0x0001e000)
9141 
9142 #ifndef __ASSEMBLY__
9143 /*
9144  * WARNING: The C register and register group struct declarations are provided for
9145  * convenience and illustrative purposes. They should, however, be used with
9146  * caution as the C language standard provides no guarantees about the alignment or
9147  * atomicity of device memory accesses. The recommended practice for writing
9148  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9149  * alt_write_word() functions.
9150  *
9151  * The struct declaration for register ALT_SDMMC_IDSTS.
9152  */
9153 struct ALT_SDMMC_IDSTS_s
9154 {
9155  uint32_t ti : 1; /* ALT_SDMMC_IDSTS_TI */
9156  uint32_t ri : 1; /* ALT_SDMMC_IDSTS_RI */
9157  uint32_t fbe : 1; /* ALT_SDMMC_IDSTS_FBE */
9158  uint32_t : 1; /* *UNDEFINED* */
9159  uint32_t du : 1; /* ALT_SDMMC_IDSTS_DU */
9160  uint32_t ces : 1; /* ALT_SDMMC_IDSTS_CES */
9161  uint32_t : 2; /* *UNDEFINED* */
9162  uint32_t nis : 1; /* ALT_SDMMC_IDSTS_NIS */
9163  uint32_t ais : 1; /* ALT_SDMMC_IDSTS_AIS */
9164  const uint32_t eb : 3; /* ALT_SDMMC_IDSTS_EB */
9165  const uint32_t fsm : 4; /* ALT_SDMMC_IDSTS_FSM */
9166  uint32_t : 15; /* *UNDEFINED* */
9167 };
9168 
9169 /* The typedef declaration for register ALT_SDMMC_IDSTS. */
9170 typedef volatile struct ALT_SDMMC_IDSTS_s ALT_SDMMC_IDSTS_t;
9171 #endif /* __ASSEMBLY__ */
9172 
9173 /* The reset value of the ALT_SDMMC_IDSTS register. */
9174 #define ALT_SDMMC_IDSTS_RESET 0x00000000
9175 /* The byte offset of the ALT_SDMMC_IDSTS register from the beginning of the component. */
9176 #define ALT_SDMMC_IDSTS_OFST 0x8c
9177 
9178 /*
9179  * Register : idinten
9180  *
9181  * Internal DMAC Interrupt Enable Register
9182  *
9183  * Register Layout
9184  *
9185  * Bits | Access | Reset | Description
9186  * :--------|:-------|:------|:----------------------
9187  * [0] | RW | 0x0 | ALT_SDMMC_IDINTEN_TI
9188  * [1] | RW | 0x0 | ALT_SDMMC_IDINTEN_RI
9189  * [2] | RW | 0x0 | ALT_SDMMC_IDINTEN_FBE
9190  * [3] | ??? | 0x0 | *UNDEFINED*
9191  * [4] | RW | 0x0 | ALT_SDMMC_IDINTEN_DU
9192  * [5] | RW | 0x0 | ALT_SDMMC_IDINTEN_CES
9193  * [7:6] | ??? | 0x0 | *UNDEFINED*
9194  * [8] | RW | 0x0 | ALT_SDMMC_IDINTEN_NI
9195  * [9] | RW | 0x0 | ALT_SDMMC_IDINTEN_AI
9196  * [31:10] | ??? | 0x0 | *UNDEFINED*
9197  *
9198  */
9199 /*
9200  * Field : ti
9201  *
9202  * Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable,
9203  * Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled.
9204  *
9205  * Field Enumeration Values:
9206  *
9207  * Enum | Value | Description
9208  * :----------------------------|:------|:-------------------------------
9209  * ALT_SDMMC_IDINTEN_TI_E_DISD | 0x0 | Transmit Interrupt is disabled
9210  * ALT_SDMMC_IDINTEN_TI_E_END | 0x1 | Transmit Interrupt is enabled
9211  *
9212  * Field Access Macros:
9213  *
9214  */
9215 /*
9216  * Enumerated value for register field ALT_SDMMC_IDINTEN_TI
9217  *
9218  * Transmit Interrupt is disabled
9219  */
9220 #define ALT_SDMMC_IDINTEN_TI_E_DISD 0x0
9221 /*
9222  * Enumerated value for register field ALT_SDMMC_IDINTEN_TI
9223  *
9224  * Transmit Interrupt is enabled
9225  */
9226 #define ALT_SDMMC_IDINTEN_TI_E_END 0x1
9227 
9228 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_TI register field. */
9229 #define ALT_SDMMC_IDINTEN_TI_LSB 0
9230 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_TI register field. */
9231 #define ALT_SDMMC_IDINTEN_TI_MSB 0
9232 /* The width in bits of the ALT_SDMMC_IDINTEN_TI register field. */
9233 #define ALT_SDMMC_IDINTEN_TI_WIDTH 1
9234 /* The mask used to set the ALT_SDMMC_IDINTEN_TI register field value. */
9235 #define ALT_SDMMC_IDINTEN_TI_SET_MSK 0x00000001
9236 /* The mask used to clear the ALT_SDMMC_IDINTEN_TI register field value. */
9237 #define ALT_SDMMC_IDINTEN_TI_CLR_MSK 0xfffffffe
9238 /* The reset value of the ALT_SDMMC_IDINTEN_TI register field. */
9239 #define ALT_SDMMC_IDINTEN_TI_RESET 0x0
9240 /* Extracts the ALT_SDMMC_IDINTEN_TI field value from a register. */
9241 #define ALT_SDMMC_IDINTEN_TI_GET(value) (((value) & 0x00000001) >> 0)
9242 /* Produces a ALT_SDMMC_IDINTEN_TI register field value suitable for setting the register. */
9243 #define ALT_SDMMC_IDINTEN_TI_SET(value) (((value) << 0) & 0x00000001)
9244 
9245 /*
9246  * Field : ri
9247  *
9248  * Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive
9249  * Interrupt is enabled. When reset, Receive Interrupt is disabled.
9250  *
9251  * Field Enumeration Values:
9252  *
9253  * Enum | Value | Description
9254  * :----------------------------|:------|:------------------------------
9255  * ALT_SDMMC_IDINTEN_RI_E_DISD | 0x0 | Receive Interrupt is disabled
9256  * ALT_SDMMC_IDINTEN_RI_E_END | 0x1 | Receive Interrupt is enabled
9257  *
9258  * Field Access Macros:
9259  *
9260  */
9261 /*
9262  * Enumerated value for register field ALT_SDMMC_IDINTEN_RI
9263  *
9264  * Receive Interrupt is disabled
9265  */
9266 #define ALT_SDMMC_IDINTEN_RI_E_DISD 0x0
9267 /*
9268  * Enumerated value for register field ALT_SDMMC_IDINTEN_RI
9269  *
9270  * Receive Interrupt is enabled
9271  */
9272 #define ALT_SDMMC_IDINTEN_RI_E_END 0x1
9273 
9274 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_RI register field. */
9275 #define ALT_SDMMC_IDINTEN_RI_LSB 1
9276 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_RI register field. */
9277 #define ALT_SDMMC_IDINTEN_RI_MSB 1
9278 /* The width in bits of the ALT_SDMMC_IDINTEN_RI register field. */
9279 #define ALT_SDMMC_IDINTEN_RI_WIDTH 1
9280 /* The mask used to set the ALT_SDMMC_IDINTEN_RI register field value. */
9281 #define ALT_SDMMC_IDINTEN_RI_SET_MSK 0x00000002
9282 /* The mask used to clear the ALT_SDMMC_IDINTEN_RI register field value. */
9283 #define ALT_SDMMC_IDINTEN_RI_CLR_MSK 0xfffffffd
9284 /* The reset value of the ALT_SDMMC_IDINTEN_RI register field. */
9285 #define ALT_SDMMC_IDINTEN_RI_RESET 0x0
9286 /* Extracts the ALT_SDMMC_IDINTEN_RI field value from a register. */
9287 #define ALT_SDMMC_IDINTEN_RI_GET(value) (((value) & 0x00000002) >> 1)
9288 /* Produces a ALT_SDMMC_IDINTEN_RI register field value suitable for setting the register. */
9289 #define ALT_SDMMC_IDINTEN_RI_SET(value) (((value) << 1) & 0x00000002)
9290 
9291 /*
9292  * Field : fbe
9293  *
9294  * Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the
9295  * Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable
9296  * Interrupt is disabled.
9297  *
9298  * Field Enumeration Values:
9299  *
9300  * Enum | Value | Description
9301  * :-----------------------------|:------|:--------------------------------------
9302  * ALT_SDMMC_IDINTEN_FBE_E_DISD | 0x0 | Fatal Bus Error Interrupt is disabled
9303  * ALT_SDMMC_IDINTEN_FBE_E_END | 0x1 | Fatal Bus Error Interrupt is enabled
9304  *
9305  * Field Access Macros:
9306  *
9307  */
9308 /*
9309  * Enumerated value for register field ALT_SDMMC_IDINTEN_FBE
9310  *
9311  * Fatal Bus Error Interrupt is disabled
9312  */
9313 #define ALT_SDMMC_IDINTEN_FBE_E_DISD 0x0
9314 /*
9315  * Enumerated value for register field ALT_SDMMC_IDINTEN_FBE
9316  *
9317  * Fatal Bus Error Interrupt is enabled
9318  */
9319 #define ALT_SDMMC_IDINTEN_FBE_E_END 0x1
9320 
9321 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_FBE register field. */
9322 #define ALT_SDMMC_IDINTEN_FBE_LSB 2
9323 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_FBE register field. */
9324 #define ALT_SDMMC_IDINTEN_FBE_MSB 2
9325 /* The width in bits of the ALT_SDMMC_IDINTEN_FBE register field. */
9326 #define ALT_SDMMC_IDINTEN_FBE_WIDTH 1
9327 /* The mask used to set the ALT_SDMMC_IDINTEN_FBE register field value. */
9328 #define ALT_SDMMC_IDINTEN_FBE_SET_MSK 0x00000004
9329 /* The mask used to clear the ALT_SDMMC_IDINTEN_FBE register field value. */
9330 #define ALT_SDMMC_IDINTEN_FBE_CLR_MSK 0xfffffffb
9331 /* The reset value of the ALT_SDMMC_IDINTEN_FBE register field. */
9332 #define ALT_SDMMC_IDINTEN_FBE_RESET 0x0
9333 /* Extracts the ALT_SDMMC_IDINTEN_FBE field value from a register. */
9334 #define ALT_SDMMC_IDINTEN_FBE_GET(value) (((value) & 0x00000004) >> 2)
9335 /* Produces a ALT_SDMMC_IDINTEN_FBE register field value suitable for setting the register. */
9336 #define ALT_SDMMC_IDINTEN_FBE_SET(value) (((value) << 2) & 0x00000004)
9337 
9338 /*
9339  * Field : du
9340  *
9341  * Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary
9342  * Enable, the DU interrupt is enabled.
9343  *
9344  * Field Enumeration Values:
9345  *
9346  * Enum | Value | Description
9347  * :----------------------------|:------|:---------------------------------------------
9348  * ALT_SDMMC_IDINTEN_DU_E_DISD | 0x0 | Descriptor Unavailable Interrupt is disabled
9349  * ALT_SDMMC_IDINTEN_DU_E_END | 0x1 | Descriptor Unavailable Interrupt is enabled
9350  *
9351  * Field Access Macros:
9352  *
9353  */
9354 /*
9355  * Enumerated value for register field ALT_SDMMC_IDINTEN_DU
9356  *
9357  * Descriptor Unavailable Interrupt is disabled
9358  */
9359 #define ALT_SDMMC_IDINTEN_DU_E_DISD 0x0
9360 /*
9361  * Enumerated value for register field ALT_SDMMC_IDINTEN_DU
9362  *
9363  * Descriptor Unavailable Interrupt is enabled
9364  */
9365 #define ALT_SDMMC_IDINTEN_DU_E_END 0x1
9366 
9367 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_DU register field. */
9368 #define ALT_SDMMC_IDINTEN_DU_LSB 4
9369 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_DU register field. */
9370 #define ALT_SDMMC_IDINTEN_DU_MSB 4
9371 /* The width in bits of the ALT_SDMMC_IDINTEN_DU register field. */
9372 #define ALT_SDMMC_IDINTEN_DU_WIDTH 1
9373 /* The mask used to set the ALT_SDMMC_IDINTEN_DU register field value. */
9374 #define ALT_SDMMC_IDINTEN_DU_SET_MSK 0x00000010
9375 /* The mask used to clear the ALT_SDMMC_IDINTEN_DU register field value. */
9376 #define ALT_SDMMC_IDINTEN_DU_CLR_MSK 0xffffffef
9377 /* The reset value of the ALT_SDMMC_IDINTEN_DU register field. */
9378 #define ALT_SDMMC_IDINTEN_DU_RESET 0x0
9379 /* Extracts the ALT_SDMMC_IDINTEN_DU field value from a register. */
9380 #define ALT_SDMMC_IDINTEN_DU_GET(value) (((value) & 0x00000010) >> 4)
9381 /* Produces a ALT_SDMMC_IDINTEN_DU register field value suitable for setting the register. */
9382 #define ALT_SDMMC_IDINTEN_DU_SET(value) (((value) << 4) & 0x00000010)
9383 
9384 /*
9385  * Field : ces
9386  *
9387  * Card Error summary Interrupt Enable. When set, it enables the Card Interrupt
9388  * summary.
9389  *
9390  * Field Enumeration Values:
9391  *
9392  * Enum | Value | Description
9393  * :-----------------------------|:------|:-----------------------------------------
9394  * ALT_SDMMC_IDINTEN_CES_E_DISD | 0x0 | Card Error Summary Interrupt is disabled
9395  * ALT_SDMMC_IDINTEN_CES_E_END | 0x1 | Card Error Summary Interrupt is enabled
9396  *
9397  * Field Access Macros:
9398  *
9399  */
9400 /*
9401  * Enumerated value for register field ALT_SDMMC_IDINTEN_CES
9402  *
9403  * Card Error Summary Interrupt is disabled
9404  */
9405 #define ALT_SDMMC_IDINTEN_CES_E_DISD 0x0
9406 /*
9407  * Enumerated value for register field ALT_SDMMC_IDINTEN_CES
9408  *
9409  * Card Error Summary Interrupt is enabled
9410  */
9411 #define ALT_SDMMC_IDINTEN_CES_E_END 0x1
9412 
9413 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_CES register field. */
9414 #define ALT_SDMMC_IDINTEN_CES_LSB 5
9415 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_CES register field. */
9416 #define ALT_SDMMC_IDINTEN_CES_MSB 5
9417 /* The width in bits of the ALT_SDMMC_IDINTEN_CES register field. */
9418 #define ALT_SDMMC_IDINTEN_CES_WIDTH 1
9419 /* The mask used to set the ALT_SDMMC_IDINTEN_CES register field value. */
9420 #define ALT_SDMMC_IDINTEN_CES_SET_MSK 0x00000020
9421 /* The mask used to clear the ALT_SDMMC_IDINTEN_CES register field value. */
9422 #define ALT_SDMMC_IDINTEN_CES_CLR_MSK 0xffffffdf
9423 /* The reset value of the ALT_SDMMC_IDINTEN_CES register field. */
9424 #define ALT_SDMMC_IDINTEN_CES_RESET 0x0
9425 /* Extracts the ALT_SDMMC_IDINTEN_CES field value from a register. */
9426 #define ALT_SDMMC_IDINTEN_CES_GET(value) (((value) & 0x00000020) >> 5)
9427 /* Produces a ALT_SDMMC_IDINTEN_CES register field value suitable for setting the register. */
9428 #define ALT_SDMMC_IDINTEN_CES_SET(value) (((value) << 5) & 0x00000020)
9429 
9430 /*
9431  * Field : ni
9432  *
9433  * Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When
9434  * reset, a normal interrupt is disabled. This bit enables the following bits:
9435  *
9436  * ? IDINTEN[0] - Transmit Interrupt
9437  *
9438  * ? IDINTEN[1] - Receive Interrupt
9439  *
9440  * Field Enumeration Values:
9441  *
9442  * Enum | Value | Description
9443  * :----------------------------|:------|:-------------------------------------
9444  * ALT_SDMMC_IDINTEN_NI_E_DISD | 0x0 | Normal Interrupt Summary is disabled
9445  * ALT_SDMMC_IDINTEN_NI_E_END | 0x1 | Normal Interrupt Summary is enabled
9446  *
9447  * Field Access Macros:
9448  *
9449  */
9450 /*
9451  * Enumerated value for register field ALT_SDMMC_IDINTEN_NI
9452  *
9453  * Normal Interrupt Summary is disabled
9454  */
9455 #define ALT_SDMMC_IDINTEN_NI_E_DISD 0x0
9456 /*
9457  * Enumerated value for register field ALT_SDMMC_IDINTEN_NI
9458  *
9459  * Normal Interrupt Summary is enabled
9460  */
9461 #define ALT_SDMMC_IDINTEN_NI_E_END 0x1
9462 
9463 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_NI register field. */
9464 #define ALT_SDMMC_IDINTEN_NI_LSB 8
9465 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_NI register field. */
9466 #define ALT_SDMMC_IDINTEN_NI_MSB 8
9467 /* The width in bits of the ALT_SDMMC_IDINTEN_NI register field. */
9468 #define ALT_SDMMC_IDINTEN_NI_WIDTH 1
9469 /* The mask used to set the ALT_SDMMC_IDINTEN_NI register field value. */
9470 #define ALT_SDMMC_IDINTEN_NI_SET_MSK 0x00000100
9471 /* The mask used to clear the ALT_SDMMC_IDINTEN_NI register field value. */
9472 #define ALT_SDMMC_IDINTEN_NI_CLR_MSK 0xfffffeff
9473 /* The reset value of the ALT_SDMMC_IDINTEN_NI register field. */
9474 #define ALT_SDMMC_IDINTEN_NI_RESET 0x0
9475 /* Extracts the ALT_SDMMC_IDINTEN_NI field value from a register. */
9476 #define ALT_SDMMC_IDINTEN_NI_GET(value) (((value) & 0x00000100) >> 8)
9477 /* Produces a ALT_SDMMC_IDINTEN_NI register field value suitable for setting the register. */
9478 #define ALT_SDMMC_IDINTEN_NI_SET(value) (((value) << 8) & 0x00000100)
9479 
9480 /*
9481  * Field : ai
9482  *
9483  * Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled.
9484  * This bit enables the following bits:
9485  *
9486  * ? IDINTEN[2] - Fatal Bus Error Interrupt
9487  *
9488  * ? IDINTEN[4] - DU Interrupt
9489  *
9490  * Field Enumeration Values:
9491  *
9492  * Enum | Value | Description
9493  * :----------------------------|:------|:---------------------------------------
9494  * ALT_SDMMC_IDINTEN_AI_E_DISD | 0x0 | Abnormal Interrupt Summary is disabled
9495  * ALT_SDMMC_IDINTEN_AI_E_END | 0x1 | Abnormal Interrupt Summary is enabled
9496  *
9497  * Field Access Macros:
9498  *
9499  */
9500 /*
9501  * Enumerated value for register field ALT_SDMMC_IDINTEN_AI
9502  *
9503  * Abnormal Interrupt Summary is disabled
9504  */
9505 #define ALT_SDMMC_IDINTEN_AI_E_DISD 0x0
9506 /*
9507  * Enumerated value for register field ALT_SDMMC_IDINTEN_AI
9508  *
9509  * Abnormal Interrupt Summary is enabled
9510  */
9511 #define ALT_SDMMC_IDINTEN_AI_E_END 0x1
9512 
9513 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_AI register field. */
9514 #define ALT_SDMMC_IDINTEN_AI_LSB 9
9515 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_AI register field. */
9516 #define ALT_SDMMC_IDINTEN_AI_MSB 9
9517 /* The width in bits of the ALT_SDMMC_IDINTEN_AI register field. */
9518 #define ALT_SDMMC_IDINTEN_AI_WIDTH 1
9519 /* The mask used to set the ALT_SDMMC_IDINTEN_AI register field value. */
9520 #define ALT_SDMMC_IDINTEN_AI_SET_MSK 0x00000200
9521 /* The mask used to clear the ALT_SDMMC_IDINTEN_AI register field value. */
9522 #define ALT_SDMMC_IDINTEN_AI_CLR_MSK 0xfffffdff
9523 /* The reset value of the ALT_SDMMC_IDINTEN_AI register field. */
9524 #define ALT_SDMMC_IDINTEN_AI_RESET 0x0
9525 /* Extracts the ALT_SDMMC_IDINTEN_AI field value from a register. */
9526 #define ALT_SDMMC_IDINTEN_AI_GET(value) (((value) & 0x00000200) >> 9)
9527 /* Produces a ALT_SDMMC_IDINTEN_AI register field value suitable for setting the register. */
9528 #define ALT_SDMMC_IDINTEN_AI_SET(value) (((value) << 9) & 0x00000200)
9529 
9530 #ifndef __ASSEMBLY__
9531 /*
9532  * WARNING: The C register and register group struct declarations are provided for
9533  * convenience and illustrative purposes. They should, however, be used with
9534  * caution as the C language standard provides no guarantees about the alignment or
9535  * atomicity of device memory accesses. The recommended practice for writing
9536  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9537  * alt_write_word() functions.
9538  *
9539  * The struct declaration for register ALT_SDMMC_IDINTEN.
9540  */
9541 struct ALT_SDMMC_IDINTEN_s
9542 {
9543  uint32_t ti : 1; /* ALT_SDMMC_IDINTEN_TI */
9544  uint32_t ri : 1; /* ALT_SDMMC_IDINTEN_RI */
9545  uint32_t fbe : 1; /* ALT_SDMMC_IDINTEN_FBE */
9546  uint32_t : 1; /* *UNDEFINED* */
9547  uint32_t du : 1; /* ALT_SDMMC_IDINTEN_DU */
9548  uint32_t ces : 1; /* ALT_SDMMC_IDINTEN_CES */
9549  uint32_t : 2; /* *UNDEFINED* */
9550  uint32_t ni : 1; /* ALT_SDMMC_IDINTEN_NI */
9551  uint32_t ai : 1; /* ALT_SDMMC_IDINTEN_AI */
9552  uint32_t : 22; /* *UNDEFINED* */
9553 };
9554 
9555 /* The typedef declaration for register ALT_SDMMC_IDINTEN. */
9556 typedef volatile struct ALT_SDMMC_IDINTEN_s ALT_SDMMC_IDINTEN_t;
9557 #endif /* __ASSEMBLY__ */
9558 
9559 /* The reset value of the ALT_SDMMC_IDINTEN register. */
9560 #define ALT_SDMMC_IDINTEN_RESET 0x00000000
9561 /* The byte offset of the ALT_SDMMC_IDINTEN register from the beginning of the component. */
9562 #define ALT_SDMMC_IDINTEN_OFST 0x90
9563 
9564 /*
9565  * Register : dscaddr
9566  *
9567  * Current Host Descriptor Address Register
9568  *
9569  * Register Layout
9570  *
9571  * Bits | Access | Reset | Description
9572  * :-------|:-------|:------|:----------------------
9573  * [31:0] | R | 0x0 | ALT_SDMMC_DSCADDR_HDA
9574  *
9575  */
9576 /*
9577  * Field : hda
9578  *
9579  * Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC
9580  * during operation. This register points to the start address of the current
9581  * descriptor read by the IDMAC.
9582  *
9583  * Field Access Macros:
9584  *
9585  */
9586 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_DSCADDR_HDA register field. */
9587 #define ALT_SDMMC_DSCADDR_HDA_LSB 0
9588 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_DSCADDR_HDA register field. */
9589 #define ALT_SDMMC_DSCADDR_HDA_MSB 31
9590 /* The width in bits of the ALT_SDMMC_DSCADDR_HDA register field. */
9591 #define ALT_SDMMC_DSCADDR_HDA_WIDTH 32
9592 /* The mask used to set the ALT_SDMMC_DSCADDR_HDA register field value. */
9593 #define ALT_SDMMC_DSCADDR_HDA_SET_MSK 0xffffffff
9594 /* The mask used to clear the ALT_SDMMC_DSCADDR_HDA register field value. */
9595 #define ALT_SDMMC_DSCADDR_HDA_CLR_MSK 0x00000000
9596 /* The reset value of the ALT_SDMMC_DSCADDR_HDA register field. */
9597 #define ALT_SDMMC_DSCADDR_HDA_RESET 0x0
9598 /* Extracts the ALT_SDMMC_DSCADDR_HDA field value from a register. */
9599 #define ALT_SDMMC_DSCADDR_HDA_GET(value) (((value) & 0xffffffff) >> 0)
9600 /* Produces a ALT_SDMMC_DSCADDR_HDA register field value suitable for setting the register. */
9601 #define ALT_SDMMC_DSCADDR_HDA_SET(value) (((value) << 0) & 0xffffffff)
9602 
9603 #ifndef __ASSEMBLY__
9604 /*
9605  * WARNING: The C register and register group struct declarations are provided for
9606  * convenience and illustrative purposes. They should, however, be used with
9607  * caution as the C language standard provides no guarantees about the alignment or
9608  * atomicity of device memory accesses. The recommended practice for writing
9609  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9610  * alt_write_word() functions.
9611  *
9612  * The struct declaration for register ALT_SDMMC_DSCADDR.
9613  */
9614 struct ALT_SDMMC_DSCADDR_s
9615 {
9616  const uint32_t hda : 32; /* ALT_SDMMC_DSCADDR_HDA */
9617 };
9618 
9619 /* The typedef declaration for register ALT_SDMMC_DSCADDR. */
9620 typedef volatile struct ALT_SDMMC_DSCADDR_s ALT_SDMMC_DSCADDR_t;
9621 #endif /* __ASSEMBLY__ */
9622 
9623 /* The reset value of the ALT_SDMMC_DSCADDR register. */
9624 #define ALT_SDMMC_DSCADDR_RESET 0x00000000
9625 /* The byte offset of the ALT_SDMMC_DSCADDR register from the beginning of the component. */
9626 #define ALT_SDMMC_DSCADDR_OFST 0x94
9627 
9628 /*
9629  * Register : bufaddr
9630  *
9631  * Current Buffer Descriptor Address Register
9632  *
9633  * Register Layout
9634  *
9635  * Bits | Access | Reset | Description
9636  * :-------|:-------|:------|:----------------------
9637  * [31:0] | R | 0x0 | ALT_SDMMC_BUFADDR_HBA
9638  *
9639  */
9640 /*
9641  * Field : hba
9642  *
9643  * Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during
9644  * operation. This register points to the current Data Buffer Address being
9645  * accessed by the IDMAC.
9646  *
9647  * Field Access Macros:
9648  *
9649  */
9650 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BUFADDR_HBA register field. */
9651 #define ALT_SDMMC_BUFADDR_HBA_LSB 0
9652 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BUFADDR_HBA register field. */
9653 #define ALT_SDMMC_BUFADDR_HBA_MSB 31
9654 /* The width in bits of the ALT_SDMMC_BUFADDR_HBA register field. */
9655 #define ALT_SDMMC_BUFADDR_HBA_WIDTH 32
9656 /* The mask used to set the ALT_SDMMC_BUFADDR_HBA register field value. */
9657 #define ALT_SDMMC_BUFADDR_HBA_SET_MSK 0xffffffff
9658 /* The mask used to clear the ALT_SDMMC_BUFADDR_HBA register field value. */
9659 #define ALT_SDMMC_BUFADDR_HBA_CLR_MSK 0x00000000
9660 /* The reset value of the ALT_SDMMC_BUFADDR_HBA register field. */
9661 #define ALT_SDMMC_BUFADDR_HBA_RESET 0x0
9662 /* Extracts the ALT_SDMMC_BUFADDR_HBA field value from a register. */
9663 #define ALT_SDMMC_BUFADDR_HBA_GET(value) (((value) & 0xffffffff) >> 0)
9664 /* Produces a ALT_SDMMC_BUFADDR_HBA register field value suitable for setting the register. */
9665 #define ALT_SDMMC_BUFADDR_HBA_SET(value) (((value) << 0) & 0xffffffff)
9666 
9667 #ifndef __ASSEMBLY__
9668 /*
9669  * WARNING: The C register and register group struct declarations are provided for
9670  * convenience and illustrative purposes. They should, however, be used with
9671  * caution as the C language standard provides no guarantees about the alignment or
9672  * atomicity of device memory accesses. The recommended practice for writing
9673  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9674  * alt_write_word() functions.
9675  *
9676  * The struct declaration for register ALT_SDMMC_BUFADDR.
9677  */
9678 struct ALT_SDMMC_BUFADDR_s
9679 {
9680  const uint32_t hba : 32; /* ALT_SDMMC_BUFADDR_HBA */
9681 };
9682 
9683 /* The typedef declaration for register ALT_SDMMC_BUFADDR. */
9684 typedef volatile struct ALT_SDMMC_BUFADDR_s ALT_SDMMC_BUFADDR_t;
9685 #endif /* __ASSEMBLY__ */
9686 
9687 /* The reset value of the ALT_SDMMC_BUFADDR register. */
9688 #define ALT_SDMMC_BUFADDR_RESET 0x00000000
9689 /* The byte offset of the ALT_SDMMC_BUFADDR register from the beginning of the component. */
9690 #define ALT_SDMMC_BUFADDR_OFST 0x98
9691 
9692 /*
9693  * Register : cardthrctl
9694  *
9695  * Card Threshold Control Register
9696  *
9697  * Register Layout
9698  *
9699  * Bits | Access | Reset | Description
9700  * :--------|:-------|:------|:-------------------------------------
9701  * [0] | RW | 0x0 | ALT_SDMMC_CARDTHRCTL_CARDRDTHREN
9702  * [1] | RW | 0x0 | ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN
9703  * [15:2] | ??? | 0x0 | *UNDEFINED*
9704  * [28:16] | RW | 0x0 | ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD
9705  * [31:29] | ??? | 0x0 | *UNDEFINED*
9706  *
9707  */
9708 /*
9709  * Field : cardrdthren
9710  *
9711  * Card Read Threshold Enable
9712  *
9713  * ? 1'b0 - Card Read Threshold disabled
9714  *
9715  * ? 1'b1 - Card Read Threshold enabled. Host Controller initiates
9716  *
9717  * Read Transfer only if CardRdThreshold amount of space is
9718  *
9719  * available in receive FIFO.
9720  *
9721  * Field Enumeration Values:
9722  *
9723  * Enum | Value | Description
9724  * :----------------------------------------|:------|:--------------------------------
9725  * ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_DISD | 0x0 | Card Read Threshold is disabled
9726  * ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_END | 0x1 | Card Read Threshold is enabled
9727  *
9728  * Field Access Macros:
9729  *
9730  */
9731 /*
9732  * Enumerated value for register field ALT_SDMMC_CARDTHRCTL_CARDRDTHREN
9733  *
9734  * Card Read Threshold is disabled
9735  */
9736 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_DISD 0x0
9737 /*
9738  * Enumerated value for register field ALT_SDMMC_CARDTHRCTL_CARDRDTHREN
9739  *
9740  * Card Read Threshold is enabled
9741  */
9742 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_END 0x1
9743 
9744 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */
9745 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_LSB 0
9746 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */
9747 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_MSB 0
9748 /* The width in bits of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */
9749 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_WIDTH 1
9750 /* The mask used to set the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field value. */
9751 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET_MSK 0x00000001
9752 /* The mask used to clear the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field value. */
9753 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_CLR_MSK 0xfffffffe
9754 /* The reset value of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */
9755 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_RESET 0x0
9756 /* Extracts the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN field value from a register. */
9757 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_GET(value) (((value) & 0x00000001) >> 0)
9758 /* Produces a ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field value suitable for setting the register. */
9759 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET(value) (((value) << 0) & 0x00000001)
9760 
9761 /*
9762  * Field : busy_clr_int_en
9763  *
9764  * Busy Clear Interrupt generation:
9765  *
9766  * ? 1'b0 - Busy Clear Interrupt disabled
9767  *
9768  * ? 1'b1 - Busy Clear Interrupt enabled
9769  *
9770  * Note: The application can disable this feature if it does not want to wait for a
9771  * Busy Clear Interrupt. For example, in a multi-card scenario, the application can
9772  * switch to the other card without waiting for a busy to be completed. In such
9773  * cases, the application can use the polling method to determine the status of
9774  * busy. By default this feature is disabled and backward-compatible to the legacy
9775  * drivers where polling is used.
9776  *
9777  * Field Access Macros:
9778  *
9779  */
9780 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field. */
9781 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_LSB 1
9782 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field. */
9783 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_MSB 1
9784 /* The width in bits of the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field. */
9785 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_WIDTH 1
9786 /* The mask used to set the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field value. */
9787 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_SET_MSK 0x00000002
9788 /* The mask used to clear the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field value. */
9789 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_CLR_MSK 0xfffffffd
9790 /* The reset value of the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field. */
9791 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_RESET 0x0
9792 /* Extracts the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN field value from a register. */
9793 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_GET(value) (((value) & 0x00000002) >> 1)
9794 /* Produces a ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field value suitable for setting the register. */
9795 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_SET(value) (((value) << 1) & 0x00000002)
9796 
9797 /*
9798  * Field : cardrdthreshold
9799  *
9800  * Card Read Threshold size; N depends on the FIFO size:
9801  *
9802  * ? N = 27 FIFO_DEPTH is 128
9803  *
9804  * ? N = 26 FIFO_DEPTH is 64
9805  *
9806  * ? N = 25 FIFO_DEPTH is 32
9807  *
9808  * ? N = 24 FIFO_DEPTH is 16
9809  *
9810  * ? N = 23 FIFO_DEPTH is 8
9811  *
9812  * Note: The maximum programmable value of Card Read Threshold size is 512.
9813  *
9814  * Field Access Macros:
9815  *
9816  */
9817 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */
9818 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_LSB 16
9819 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */
9820 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_MSB 28
9821 /* The width in bits of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */
9822 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_WIDTH 13
9823 /* The mask used to set the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field value. */
9824 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET_MSK 0x1fff0000
9825 /* The mask used to clear the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field value. */
9826 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_CLR_MSK 0xe000ffff
9827 /* The reset value of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */
9828 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_RESET 0x0
9829 /* Extracts the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD field value from a register. */
9830 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_GET(value) (((value) & 0x1fff0000) >> 16)
9831 /* Produces a ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field value suitable for setting the register. */
9832 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET(value) (((value) << 16) & 0x1fff0000)
9833 
9834 #ifndef __ASSEMBLY__
9835 /*
9836  * WARNING: The C register and register group struct declarations are provided for
9837  * convenience and illustrative purposes. They should, however, be used with
9838  * caution as the C language standard provides no guarantees about the alignment or
9839  * atomicity of device memory accesses. The recommended practice for writing
9840  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9841  * alt_write_word() functions.
9842  *
9843  * The struct declaration for register ALT_SDMMC_CARDTHRCTL.
9844  */
9845 struct ALT_SDMMC_CARDTHRCTL_s
9846 {
9847  uint32_t cardrdthren : 1; /* ALT_SDMMC_CARDTHRCTL_CARDRDTHREN */
9848  uint32_t busy_clr_int_en : 1; /* ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN */
9849  uint32_t : 14; /* *UNDEFINED* */
9850  uint32_t cardrdthreshold : 13; /* ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD */
9851  uint32_t : 3; /* *UNDEFINED* */
9852 };
9853 
9854 /* The typedef declaration for register ALT_SDMMC_CARDTHRCTL. */
9855 typedef volatile struct ALT_SDMMC_CARDTHRCTL_s ALT_SDMMC_CARDTHRCTL_t;
9856 #endif /* __ASSEMBLY__ */
9857 
9858 /* The reset value of the ALT_SDMMC_CARDTHRCTL register. */
9859 #define ALT_SDMMC_CARDTHRCTL_RESET 0x00000000
9860 /* The byte offset of the ALT_SDMMC_CARDTHRCTL register from the beginning of the component. */
9861 #define ALT_SDMMC_CARDTHRCTL_OFST 0x100
9862 
9863 /*
9864  * Register : back_end_power_r
9865  *
9866  * Back End Power Register
9867  *
9868  * Register Layout
9869  *
9870  * Bits | Access | Reset | Description
9871  * :--------|:-------|:------|:------------------------------------------
9872  * [15:0] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER
9873  * [31:16] | ??? | 0x0 | *UNDEFINED*
9874  *
9875  */
9876 /*
9877  * Field : back_end_power
9878  *
9879  * Back end power
9880  *
9881  * ? 1'b0 Off; Reset
9882  *
9883  * ? 1'b1 Back-end Power supplied to card application; one pin per
9884  *
9885  * card
9886  *
9887  * Field Enumeration Values:
9888  *
9889  * Enum | Value | Description
9890  * :-----------------------------------------------------|:------|:--------------------------------------------
9891  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND0 | 0x0 | Off Reset
9892  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND1 | 0x1 | Back-end Power supplied to card only 1 card
9893  *
9894  * Field Access Macros:
9895  *
9896  */
9897 /*
9898  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER
9899  *
9900  * Off Reset
9901  */
9902 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND0 0x0
9903 /*
9904  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER
9905  *
9906  * Back-end Power supplied to card only 1 card
9907  */
9908 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND1 0x1
9909 
9910 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field. */
9911 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_LSB 0
9912 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field. */
9913 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_MSB 15
9914 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field. */
9915 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_WIDTH 16
9916 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field value. */
9917 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET_MSK 0x0000ffff
9918 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field value. */
9919 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_CLR_MSK 0xffff0000
9920 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field. */
9921 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_RESET 0x0
9922 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER field value from a register. */
9923 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_GET(value) (((value) & 0x0000ffff) >> 0)
9924 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field value suitable for setting the register. */
9925 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET(value) (((value) << 0) & 0x0000ffff)
9926 
9927 #ifndef __ASSEMBLY__
9928 /*
9929  * WARNING: The C register and register group struct declarations are provided for
9930  * convenience and illustrative purposes. They should, however, be used with
9931  * caution as the C language standard provides no guarantees about the alignment or
9932  * atomicity of device memory accesses. The recommended practice for writing
9933  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9934  * alt_write_word() functions.
9935  *
9936  * The struct declaration for register ALT_SDMMC_BACK_END_POWER_R.
9937  */
9938 struct ALT_SDMMC_BACK_END_POWER_R_s
9939 {
9940  uint32_t back_end_power : 16; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER */
9941  uint32_t : 16; /* *UNDEFINED* */
9942 };
9943 
9944 /* The typedef declaration for register ALT_SDMMC_BACK_END_POWER_R. */
9945 typedef volatile struct ALT_SDMMC_BACK_END_POWER_R_s ALT_SDMMC_BACK_END_POWER_R_t;
9946 #endif /* __ASSEMBLY__ */
9947 
9948 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R register. */
9949 #define ALT_SDMMC_BACK_END_POWER_R_RESET 0x00000000
9950 /* The byte offset of the ALT_SDMMC_BACK_END_POWER_R register from the beginning of the component. */
9951 #define ALT_SDMMC_BACK_END_POWER_R_OFST 0x104
9952 
9953 /*
9954  * Register : uhs_reg_ext
9955  *
9956  * UHS Register Extention
9957  *
9958  * Register Layout
9959  *
9960  * Bits | Access | Reset | Description
9961  * :--------|:-------|:------|:-----------------------------------------
9962  * [15:0] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG
9963  * [22:16] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL
9964  * [29:23] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL
9965  * [31:30] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL
9966  *
9967  */
9968 /*
9969  * Field : mmc_volt_reg
9970  *
9971  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
9972  *
9973  * with UHS_VOLT_REG to decode output selected voltage.
9974  *
9975  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
9976  * selected for the I/O voltage logic.
9977  *
9978  * Host controllers that support only SD standard or standard versions before
9979  * eMMC4.41 do not program MMC_VOLT_REG.
9980  *
9981  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
9982  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
9983  *
9984  * Field Access Macros:
9985  *
9986  */
9987 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field. */
9988 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_LSB 0
9989 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field. */
9990 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_MSB 15
9991 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field. */
9992 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_WIDTH 16
9993 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field value. */
9994 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_SET_MSK 0x0000ffff
9995 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field value. */
9996 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_CLR_MSK 0xffff0000
9997 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field. */
9998 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_RESET 0x0
9999 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG field value from a register. */
10000 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_GET(value) (((value) & 0x0000ffff) >> 0)
10001 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field value suitable for setting the register. */
10002 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_SET(value) (((value) << 0) & 0x0000ffff)
10003 
10004 /*
10005  * Field : clk_smpl_phase_ctrl
10006  *
10007  * Control for amount of phase shift on cclk_in_sample clock. Can choose three MSBs
10008  * to control delay lines and four LSBs to control phase shift; alternatively, use
10009  * only LSBs.
10010  *
10011  * Field Access Macros:
10012  *
10013  */
10014 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field. */
10015 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_LSB 16
10016 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field. */
10017 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_MSB 22
10018 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field. */
10019 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_WIDTH 7
10020 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field value. */
10021 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_SET_MSK 0x007f0000
10022 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field value. */
10023 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_CLR_MSK 0xff80ffff
10024 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field. */
10025 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_RESET 0x0
10026 /* Extracts the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL field value from a register. */
10027 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_GET(value) (((value) & 0x007f0000) >> 16)
10028 /* Produces a ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field value suitable for setting the register. */
10029 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_SET(value) (((value) << 16) & 0x007f0000)
10030 
10031 /*
10032  * Field : clk_drv_phase_ctrl
10033  *
10034  * Control for amount of phase shift on cclk_in_drv clock. Can choose three MSBs to
10035  * control delay lines and four LSBs to control phase shift; alternatively, use
10036  * only LSBs.
10037  *
10038  * Field Access Macros:
10039  *
10040  */
10041 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field. */
10042 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_LSB 23
10043 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field. */
10044 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_MSB 29
10045 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field. */
10046 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_WIDTH 7
10047 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field value. */
10048 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_SET_MSK 0x3f800000
10049 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field value. */
10050 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_CLR_MSK 0xc07fffff
10051 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field. */
10052 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_RESET 0x0
10053 /* Extracts the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL field value from a register. */
10054 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_GET(value) (((value) & 0x3f800000) >> 23)
10055 /* Produces a ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field value suitable for setting the register. */
10056 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_SET(value) (((value) << 23) & 0x3f800000)
10057 
10058 /*
10059  * Field : ext_clk_mux_ctrl
10060  *
10061  * Input clock control for cclk_in. The MUX controlled by these bits exists outside
10062  * DWC_mobile_storage IP.
10063  *
10064  * Field Access Macros:
10065  *
10066  */
10067 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field. */
10068 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_LSB 30
10069 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field. */
10070 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_MSB 31
10071 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field. */
10072 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_WIDTH 2
10073 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field value. */
10074 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_SET_MSK 0xc0000000
10075 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field value. */
10076 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_CLR_MSK 0x3fffffff
10077 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field. */
10078 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_RESET 0x0
10079 /* Extracts the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL field value from a register. */
10080 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_GET(value) (((value) & 0xc0000000) >> 30)
10081 /* Produces a ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field value suitable for setting the register. */
10082 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_SET(value) (((value) << 30) & 0xc0000000)
10083 
10084 #ifndef __ASSEMBLY__
10085 /*
10086  * WARNING: The C register and register group struct declarations are provided for
10087  * convenience and illustrative purposes. They should, however, be used with
10088  * caution as the C language standard provides no guarantees about the alignment or
10089  * atomicity of device memory accesses. The recommended practice for writing
10090  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10091  * alt_write_word() functions.
10092  *
10093  * The struct declaration for register ALT_SDMMC_UHS_REG_EXT.
10094  */
10095 struct ALT_SDMMC_UHS_REG_EXT_s
10096 {
10097  uint32_t mmc_volt_reg : 16; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG */
10098  uint32_t clk_smpl_phase_ctrl : 7; /* ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL */
10099  uint32_t clk_drv_phase_ctrl : 7; /* ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL */
10100  uint32_t ext_clk_mux_ctrl : 2; /* ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL */
10101 };
10102 
10103 /* The typedef declaration for register ALT_SDMMC_UHS_REG_EXT. */
10104 typedef volatile struct ALT_SDMMC_UHS_REG_EXT_s ALT_SDMMC_UHS_REG_EXT_t;
10105 #endif /* __ASSEMBLY__ */
10106 
10107 /* The reset value of the ALT_SDMMC_UHS_REG_EXT register. */
10108 #define ALT_SDMMC_UHS_REG_EXT_RESET 0x00000000
10109 /* The byte offset of the ALT_SDMMC_UHS_REG_EXT register from the beginning of the component. */
10110 #define ALT_SDMMC_UHS_REG_EXT_OFST 0x108
10111 
10112 /*
10113  * Register : emmc_ddr_reg
10114  *
10115  * EMMC DDR Register
10116  *
10117  * Register Layout
10118  *
10119  * Bits | Access | Reset | Description
10120  * :-------|:-------|:------|:--------------------------------------
10121  * [0] | RW | 0x0 | ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT
10122  * [31:1] | ??? | 0x0 | *UNDEFINED*
10123  *
10124  */
10125 /*
10126  * Field : half_start_bit
10127  *
10128  * Control for start bit detection mechanism inside
10129  *
10130  * DWC_mobile_storage based on duration of start bit; each bit refers to one slot.
10131  * For eMMC 4.5, start bit can
10132  *
10133  * be:
10134  *
10135  * ? Full cycle (HALF_START_BIT = 0)
10136  *
10137  * ? Less than one full cycle (HALF_START_BIT = 1)
10138  *
10139  * Set HALF_START_BIT=1 for eMMC 4.5 and above; set to 0 for SD applications.
10140  *
10141  * Field Access Macros:
10142  *
10143  */
10144 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field. */
10145 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_LSB 0
10146 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field. */
10147 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_MSB 0
10148 /* The width in bits of the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field. */
10149 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_WIDTH 1
10150 /* The mask used to set the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field value. */
10151 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_SET_MSK 0x00000001
10152 /* The mask used to clear the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field value. */
10153 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_CLR_MSK 0xfffffffe
10154 /* The reset value of the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field. */
10155 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_RESET 0x0
10156 /* Extracts the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT field value from a register. */
10157 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_GET(value) (((value) & 0x00000001) >> 0)
10158 /* Produces a ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field value suitable for setting the register. */
10159 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_SET(value) (((value) << 0) & 0x00000001)
10160 
10161 #ifndef __ASSEMBLY__
10162 /*
10163  * WARNING: The C register and register group struct declarations are provided for
10164  * convenience and illustrative purposes. They should, however, be used with
10165  * caution as the C language standard provides no guarantees about the alignment or
10166  * atomicity of device memory accesses. The recommended practice for writing
10167  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10168  * alt_write_word() functions.
10169  *
10170  * The struct declaration for register ALT_SDMMC_EMMC_DDR_REG.
10171  */
10172 struct ALT_SDMMC_EMMC_DDR_REG_s
10173 {
10174  uint32_t half_start_bit : 1; /* ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT */
10175  uint32_t : 31; /* *UNDEFINED* */
10176 };
10177 
10178 /* The typedef declaration for register ALT_SDMMC_EMMC_DDR_REG. */
10179 typedef volatile struct ALT_SDMMC_EMMC_DDR_REG_s ALT_SDMMC_EMMC_DDR_REG_t;
10180 #endif /* __ASSEMBLY__ */
10181 
10182 /* The reset value of the ALT_SDMMC_EMMC_DDR_REG register. */
10183 #define ALT_SDMMC_EMMC_DDR_REG_RESET 0x00000000
10184 /* The byte offset of the ALT_SDMMC_EMMC_DDR_REG register from the beginning of the component. */
10185 #define ALT_SDMMC_EMMC_DDR_REG_OFST 0x10c
10186 
10187 /*
10188  * Register : enable_shift
10189  *
10190  * Register to control the amount of shift on enables
10191  *
10192  * Register Layout
10193  *
10194  * Bits | Access | Reset | Description
10195  * :-------|:-------|:------|:---------------------------------
10196  * [1:0] | RW | 0x0 | ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD
10197  * [31:2] | ??? | 0x0 | *UNDEFINED*
10198  *
10199  */
10200 /*
10201  * Field : enable_shift_card
10202  *
10203  * Control for the amount of phase shift provided on the default
10204  *
10205  * enables in the design. Two bits are assigned for each card/slot. For example,
10206  * bits[1:0] control slot0 and indicate the following.
10207  *
10208  * ? 00 Default phase shift
10209  *
10210  * ? 01 Enables shifted to next immediate positive edge
10211  *
10212  * ? 10 Enables shifted to next immediate negative edge
10213  *
10214  * ? 11 Reserved
10215  *
10216  * Field Access Macros:
10217  *
10218  */
10219 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD register field. */
10220 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_LSB 0
10221 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD register field. */
10222 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_MSB 1
10223 /* The width in bits of the ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD register field. */
10224 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_WIDTH 2
10225 /* The mask used to set the ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD register field value. */
10226 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_SET_MSK 0x00000003
10227 /* The mask used to clear the ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD register field value. */
10228 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_CLR_MSK 0xfffffffc
10229 /* The reset value of the ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD register field. */
10230 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_RESET 0x0
10231 /* Extracts the ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD field value from a register. */
10232 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_GET(value) (((value) & 0x00000003) >> 0)
10233 /* Produces a ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD register field value suitable for setting the register. */
10234 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_SET(value) (((value) << 0) & 0x00000003)
10235 
10236 #ifndef __ASSEMBLY__
10237 /*
10238  * WARNING: The C register and register group struct declarations are provided for
10239  * convenience and illustrative purposes. They should, however, be used with
10240  * caution as the C language standard provides no guarantees about the alignment or
10241  * atomicity of device memory accesses. The recommended practice for writing
10242  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10243  * alt_write_word() functions.
10244  *
10245  * The struct declaration for register ALT_SDMMC_EN_SHIFT.
10246  */
10247 struct ALT_SDMMC_EN_SHIFT_s
10248 {
10249  uint32_t enable_shift_card : 2; /* ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD */
10250  uint32_t : 30; /* *UNDEFINED* */
10251 };
10252 
10253 /* The typedef declaration for register ALT_SDMMC_EN_SHIFT. */
10254 typedef volatile struct ALT_SDMMC_EN_SHIFT_s ALT_SDMMC_EN_SHIFT_t;
10255 #endif /* __ASSEMBLY__ */
10256 
10257 /* The reset value of the ALT_SDMMC_EN_SHIFT register. */
10258 #define ALT_SDMMC_EN_SHIFT_RESET 0x00000000
10259 /* The byte offset of the ALT_SDMMC_EN_SHIFT register from the beginning of the component. */
10260 #define ALT_SDMMC_EN_SHIFT_OFST 0x110
10261 
10262 /*
10263  * Register : Data FIFO Access - data
10264  *
10265  * Provides read/write access to data FIFO. Addresses 0x200 and above are mapped to
10266  * the data FIFO. More than one address is mapped to data FIFO so that FIFO can be
10267  * accessed using bursts.
10268  *
10269  * Register Layout
10270  *
10271  * Bits | Access | Reset | Description
10272  * :-------|:-------|:--------|:------------
10273  * [31:0] | RW | Unknown | FIFO Data
10274  *
10275  */
10276 /*
10277  * Field : FIFO Data - value
10278  *
10279  * Provides read/write access to data FIFO.
10280  *
10281  * Field Access Macros:
10282  *
10283  */
10284 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_DATA_VALUE register field. */
10285 #define ALT_SDMMC_DATA_VALUE_LSB 0
10286 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_DATA_VALUE register field. */
10287 #define ALT_SDMMC_DATA_VALUE_MSB 31
10288 /* The width in bits of the ALT_SDMMC_DATA_VALUE register field. */
10289 #define ALT_SDMMC_DATA_VALUE_WIDTH 32
10290 /* The mask used to set the ALT_SDMMC_DATA_VALUE register field value. */
10291 #define ALT_SDMMC_DATA_VALUE_SET_MSK 0xffffffff
10292 /* The mask used to clear the ALT_SDMMC_DATA_VALUE register field value. */
10293 #define ALT_SDMMC_DATA_VALUE_CLR_MSK 0x00000000
10294 /* The reset value of the ALT_SDMMC_DATA_VALUE register field is UNKNOWN. */
10295 #define ALT_SDMMC_DATA_VALUE_RESET 0x0
10296 /* Extracts the ALT_SDMMC_DATA_VALUE field value from a register. */
10297 #define ALT_SDMMC_DATA_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
10298 /* Produces a ALT_SDMMC_DATA_VALUE register field value suitable for setting the register. */
10299 #define ALT_SDMMC_DATA_VALUE_SET(value) (((value) << 0) & 0xffffffff)
10300 
10301 #ifndef __ASSEMBLY__
10302 /*
10303  * WARNING: The C register and register group struct declarations are provided for
10304  * convenience and illustrative purposes. They should, however, be used with
10305  * caution as the C language standard provides no guarantees about the alignment or
10306  * atomicity of device memory accesses. The recommended practice for writing
10307  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10308  * alt_write_word() functions.
10309  *
10310  * The struct declaration for register ALT_SDMMC_DATA.
10311  */
10312 struct ALT_SDMMC_DATA_s
10313 {
10314  uint32_t value : 32; /* FIFO Data */
10315 };
10316 
10317 /* The typedef declaration for register ALT_SDMMC_DATA. */
10318 typedef volatile struct ALT_SDMMC_DATA_s ALT_SDMMC_DATA_t;
10319 #endif /* __ASSEMBLY__ */
10320 
10321 /* The reset value of the ALT_SDMMC_DATA register. */
10322 #define ALT_SDMMC_DATA_RESET 0x00000000
10323 /* The byte offset of the ALT_SDMMC_DATA register from the beginning of the component. */
10324 #define ALT_SDMMC_DATA_OFST 0x200
10325 
10326 #ifndef __ASSEMBLY__
10327 /*
10328  * WARNING: The C register and register group struct declarations are provided for
10329  * convenience and illustrative purposes. They should, however, be used with
10330  * caution as the C language standard provides no guarantees about the alignment or
10331  * atomicity of device memory accesses. The recommended practice for writing
10332  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10333  * alt_write_word() functions.
10334  *
10335  * The struct declaration for register group ALT_SDMMC.
10336  */
10337 struct ALT_SDMMC_s
10338 {
10339  ALT_SDMMC_CTL_t ctrl; /* ALT_SDMMC_CTL */
10340  ALT_SDMMC_PWREN_t pwren; /* ALT_SDMMC_PWREN */
10341  ALT_SDMMC_CLKDIV_t clkdiv; /* ALT_SDMMC_CLKDIV */
10342  ALT_SDMMC_CLKSRC_t clksrc; /* ALT_SDMMC_CLKSRC */
10343  ALT_SDMMC_CLKENA_t clkena; /* ALT_SDMMC_CLKENA */
10344  ALT_SDMMC_TMOUT_t tmout; /* ALT_SDMMC_TMOUT */
10345  ALT_SDMMC_CTYPE_t ctype; /* ALT_SDMMC_CTYPE */
10346  ALT_SDMMC_BLKSIZ_t blksiz; /* ALT_SDMMC_BLKSIZ */
10347  ALT_SDMMC_BYTCNT_t bytcnt; /* ALT_SDMMC_BYTCNT */
10348  ALT_SDMMC_INTMSK_t intmask; /* ALT_SDMMC_INTMSK */
10349  ALT_SDMMC_CMDARG_t cmdarg; /* ALT_SDMMC_CMDARG */
10350  ALT_SDMMC_CMD_t cmd; /* ALT_SDMMC_CMD */
10351  ALT_SDMMC_RESP0_t resp0; /* ALT_SDMMC_RESP0 */
10352  ALT_SDMMC_RESP1_t resp1; /* ALT_SDMMC_RESP1 */
10353  ALT_SDMMC_RESP2_t resp2; /* ALT_SDMMC_RESP2 */
10354  ALT_SDMMC_RESP3_t resp3; /* ALT_SDMMC_RESP3 */
10355  ALT_SDMMC_MINTSTS_t mintsts; /* ALT_SDMMC_MINTSTS */
10356  ALT_SDMMC_RINTSTS_t rintsts; /* ALT_SDMMC_RINTSTS */
10357  ALT_SDMMC_STAT_t status; /* ALT_SDMMC_STAT */
10358  ALT_SDMMC_FIFOTH_t fifoth; /* ALT_SDMMC_FIFOTH */
10359  ALT_SDMMC_CDETECT_t cdetect; /* ALT_SDMMC_CDETECT */
10360  ALT_SDMMC_WRTPRT_t wrtprt; /* ALT_SDMMC_WRTPRT */
10361  ALT_SDMMC_GPIO_t gpio; /* ALT_SDMMC_GPIO */
10362  ALT_SDMMC_TCBCNT_t tcbcnt; /* ALT_SDMMC_TCBCNT */
10363  ALT_SDMMC_TBBCNT_t tbbcnt; /* ALT_SDMMC_TBBCNT */
10364  ALT_SDMMC_DEBNCE_t debnce; /* ALT_SDMMC_DEBNCE */
10365  ALT_SDMMC_USRID_t usrid; /* ALT_SDMMC_USRID */
10366  ALT_SDMMC_VERID_t verid; /* ALT_SDMMC_VERID */
10367  ALT_SDMMC_HCON_t hcon; /* ALT_SDMMC_HCON */
10368  ALT_SDMMC_UHS_REG_t uhs_reg; /* ALT_SDMMC_UHS_REG */
10369  ALT_SDMMC_RST_N_t rst_n; /* ALT_SDMMC_RST_N */
10370  volatile uint32_t _pad_0x7c_0x7f; /* *UNDEFINED* */
10371  ALT_SDMMC_BMOD_t bmod; /* ALT_SDMMC_BMOD */
10372  ALT_SDMMC_PLDMND_t pldmnd; /* ALT_SDMMC_PLDMND */
10373  ALT_SDMMC_DBADDR_t dbaddr; /* ALT_SDMMC_DBADDR */
10374  ALT_SDMMC_IDSTS_t idsts; /* ALT_SDMMC_IDSTS */
10375  ALT_SDMMC_IDINTEN_t idinten; /* ALT_SDMMC_IDINTEN */
10376  ALT_SDMMC_DSCADDR_t dscaddr; /* ALT_SDMMC_DSCADDR */
10377  ALT_SDMMC_BUFADDR_t bufaddr; /* ALT_SDMMC_BUFADDR */
10378  volatile uint32_t _pad_0x9c_0xff[25]; /* *UNDEFINED* */
10379  ALT_SDMMC_CARDTHRCTL_t cardthrctl; /* ALT_SDMMC_CARDTHRCTL */
10380  ALT_SDMMC_BACK_END_POWER_R_t back_end_power_r; /* ALT_SDMMC_BACK_END_POWER_R */
10381  ALT_SDMMC_UHS_REG_EXT_t uhs_reg_ext; /* ALT_SDMMC_UHS_REG_EXT */
10382  ALT_SDMMC_EMMC_DDR_REG_t emmc_ddr_reg; /* ALT_SDMMC_EMMC_DDR_REG */
10383  ALT_SDMMC_EN_SHIFT_t enable_shift; /* ALT_SDMMC_EN_SHIFT */
10384  volatile uint32_t _pad_0x114_0x1ff[59]; /* *UNDEFINED* */
10385  ALT_SDMMC_DATA_t data; /* ALT_SDMMC_DATA */
10386  volatile uint32_t _pad_0x204_0x400[127]; /* *UNDEFINED* */
10387 };
10388 
10389 /* The typedef declaration for register group ALT_SDMMC. */
10390 typedef volatile struct ALT_SDMMC_s ALT_SDMMC_t;
10391 /* The struct declaration for the raw register contents of register group ALT_SDMMC. */
10392 struct ALT_SDMMC_raw_s
10393 {
10394  volatile uint32_t ctrl; /* ALT_SDMMC_CTL */
10395  volatile uint32_t pwren; /* ALT_SDMMC_PWREN */
10396  volatile uint32_t clkdiv; /* ALT_SDMMC_CLKDIV */
10397  volatile uint32_t clksrc; /* ALT_SDMMC_CLKSRC */
10398  volatile uint32_t clkena; /* ALT_SDMMC_CLKENA */
10399  volatile uint32_t tmout; /* ALT_SDMMC_TMOUT */
10400  volatile uint32_t ctype; /* ALT_SDMMC_CTYPE */
10401  volatile uint32_t blksiz; /* ALT_SDMMC_BLKSIZ */
10402  volatile uint32_t bytcnt; /* ALT_SDMMC_BYTCNT */
10403  volatile uint32_t intmask; /* ALT_SDMMC_INTMSK */
10404  volatile uint32_t cmdarg; /* ALT_SDMMC_CMDARG */
10405  volatile uint32_t cmd; /* ALT_SDMMC_CMD */
10406  volatile uint32_t resp0; /* ALT_SDMMC_RESP0 */
10407  volatile uint32_t resp1; /* ALT_SDMMC_RESP1 */
10408  volatile uint32_t resp2; /* ALT_SDMMC_RESP2 */
10409  volatile uint32_t resp3; /* ALT_SDMMC_RESP3 */
10410  volatile uint32_t mintsts; /* ALT_SDMMC_MINTSTS */
10411  volatile uint32_t rintsts; /* ALT_SDMMC_RINTSTS */
10412  volatile uint32_t status; /* ALT_SDMMC_STAT */
10413  volatile uint32_t fifoth; /* ALT_SDMMC_FIFOTH */
10414  volatile uint32_t cdetect; /* ALT_SDMMC_CDETECT */
10415  volatile uint32_t wrtprt; /* ALT_SDMMC_WRTPRT */
10416  volatile uint32_t gpio; /* ALT_SDMMC_GPIO */
10417  volatile uint32_t tcbcnt; /* ALT_SDMMC_TCBCNT */
10418  volatile uint32_t tbbcnt; /* ALT_SDMMC_TBBCNT */
10419  volatile uint32_t debnce; /* ALT_SDMMC_DEBNCE */
10420  volatile uint32_t usrid; /* ALT_SDMMC_USRID */
10421  volatile uint32_t verid; /* ALT_SDMMC_VERID */
10422  volatile uint32_t hcon; /* ALT_SDMMC_HCON */
10423  volatile uint32_t uhs_reg; /* ALT_SDMMC_UHS_REG */
10424  volatile uint32_t rst_n; /* ALT_SDMMC_RST_N */
10425  uint32_t _pad_0x7c_0x7f; /* *UNDEFINED* */
10426  volatile uint32_t bmod; /* ALT_SDMMC_BMOD */
10427  volatile uint32_t pldmnd; /* ALT_SDMMC_PLDMND */
10428  volatile uint32_t dbaddr; /* ALT_SDMMC_DBADDR */
10429  volatile uint32_t idsts; /* ALT_SDMMC_IDSTS */
10430  volatile uint32_t idinten; /* ALT_SDMMC_IDINTEN */
10431  volatile uint32_t dscaddr; /* ALT_SDMMC_DSCADDR */
10432  volatile uint32_t bufaddr; /* ALT_SDMMC_BUFADDR */
10433  uint32_t _pad_0x9c_0xff[25]; /* *UNDEFINED* */
10434  volatile uint32_t cardthrctl; /* ALT_SDMMC_CARDTHRCTL */
10435  volatile uint32_t back_end_power_r; /* ALT_SDMMC_BACK_END_POWER_R */
10436  volatile uint32_t uhs_reg_ext; /* ALT_SDMMC_UHS_REG_EXT */
10437  volatile uint32_t emmc_ddr_reg; /* ALT_SDMMC_EMMC_DDR_REG */
10438  volatile uint32_t enable_shift; /* ALT_SDMMC_EN_SHIFT */
10439  uint32_t _pad_0x114_0x1ff[59]; /* *UNDEFINED* */
10440  volatile uint32_t data; /* ALT_SDMMC_DATA */
10441  uint32_t _pad_0x204_0x400[127]; /* *UNDEFINED* */
10442 };
10443 
10444 /* The typedef declaration for the raw register contents of register group ALT_SDMMC. */
10445 typedef volatile struct ALT_SDMMC_raw_s ALT_SDMMC_raw_t;
10446 #endif /* __ASSEMBLY__ */
10447 
10448 
10449 #ifdef __cplusplus
10450 }
10451 #endif /* __cplusplus */
10452 #endif /* __ALT_SOCAL_SDMMC_H__ */
10453