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alt_noc_fw_l4_sys_scr.h
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32 
33 /* Altera - ALT_NOC_FW_L4_SYS_SCR */
34 
35 #ifndef __ALT_SOCAL_NOC_FW_L4_SYS_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_L4_SYS_SCR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : NOC_FW_L4_SYS_SCR
50  * L4_SYS Security Control Registers (SCR)
51  *
52  */
53 /*
54  * Register : dma_ecc
55  *
56  * Per-Master Security bit for dma_ecc
57  *
58  * Register Layout
59  *
60  * Bits | Access | Reset | Description
61  * :--------|:-------|:--------|:---------------------------------------
62  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU
63  * [15:1] | ??? | Unknown | *UNDEFINED*
64  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC
65  * [23:17] | ??? | Unknown | *UNDEFINED*
66  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP
67  * [31:25] | ??? | Unknown | *UNDEFINED*
68  *
69  */
70 /*
71  * Field : mpu
72  *
73  * Security bit configuration for transactions from mpu to dma_ecc. When cleared
74  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
75  * Secure transactions are allowed.
76  *
77  * Field Access Macros:
78  *
79  */
80 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU register field. */
81 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_LSB 0
82 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU register field. */
83 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_MSB 0
84 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU register field. */
85 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_WIDTH 1
86 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU register field value. */
87 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_SET_MSK 0x00000001
88 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU register field value. */
89 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_CLR_MSK 0xfffffffe
90 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU register field. */
91 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_RESET 0x0
92 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU field value from a register. */
93 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
94 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU register field value suitable for setting the register. */
95 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
96 
97 /*
98  * Field : fpga2soc
99  *
100  * Security bit configuration for transactions from fpga2soc to dma_ecc. When
101  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
102  * Non-Secure transactions are allowed.
103  *
104  * Field Access Macros:
105  *
106  */
107 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC register field. */
108 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_LSB 16
109 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC register field. */
110 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_MSB 16
111 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC register field. */
112 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_WIDTH 1
113 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC register field value. */
114 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_SET_MSK 0x00010000
115 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC register field value. */
116 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
117 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC register field. */
118 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_RESET 0x0
119 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC field value from a register. */
120 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
121 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC register field value suitable for setting the register. */
122 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
123 
124 /*
125  * Field : axi_ap
126  *
127  * Security bit configuration for transactions from axi_ap to dma_ecc. When cleared
128  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
129  * Secure transactions are allowed.
130  *
131  * Field Access Macros:
132  *
133  */
134 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP register field. */
135 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_LSB 24
136 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP register field. */
137 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_MSB 24
138 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP register field. */
139 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_WIDTH 1
140 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP register field value. */
141 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_SET_MSK 0x01000000
142 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP register field value. */
143 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_CLR_MSK 0xfeffffff
144 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP register field. */
145 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_RESET 0x0
146 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP field value from a register. */
147 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
148 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP register field value suitable for setting the register. */
149 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
150 
151 #ifndef __ASSEMBLY__
152 /*
153  * WARNING: The C register and register group struct declarations are provided for
154  * convenience and illustrative purposes. They should, however, be used with
155  * caution as the C language standard provides no guarantees about the alignment or
156  * atomicity of device memory accesses. The recommended practice for coding device
157  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
158  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
159  * alt_write_dword() functions for 64 bit registers.
160  *
161  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_DMA_ECC.
162  */
163 struct ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_s
164 {
165  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU */
166  uint32_t : 15; /* *UNDEFINED* */
167  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC */
168  uint32_t : 7; /* *UNDEFINED* */
169  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP */
170  uint32_t : 7; /* *UNDEFINED* */
171 };
172 
173 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_DMA_ECC. */
174 typedef struct ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_s ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_t;
175 #endif /* __ASSEMBLY__ */
176 
177 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC register. */
178 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_RESET 0x00000000
179 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_DMA_ECC register from the beginning of the component. */
180 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_OFST 0x8
181 
182 /*
183  * Register : emac0rx_ecc
184  *
185  * Per-Master Security bit for emac0rx_ecc
186  *
187  * Register Layout
188  *
189  * Bits | Access | Reset | Description
190  * :--------|:-------|:--------|:-------------------------------------------
191  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU
192  * [15:1] | ??? | Unknown | *UNDEFINED*
193  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC
194  * [23:17] | ??? | Unknown | *UNDEFINED*
195  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP
196  * [31:25] | ??? | Unknown | *UNDEFINED*
197  *
198  */
199 /*
200  * Field : mpu
201  *
202  * Security bit configuration for transactions from mpu to emac0rx_ecc. When
203  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
204  * Non-Secure transactions are allowed.
205  *
206  * Field Access Macros:
207  *
208  */
209 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU register field. */
210 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_LSB 0
211 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU register field. */
212 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_MSB 0
213 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU register field. */
214 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_WIDTH 1
215 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU register field value. */
216 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_SET_MSK 0x00000001
217 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU register field value. */
218 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_CLR_MSK 0xfffffffe
219 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU register field. */
220 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_RESET 0x0
221 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU field value from a register. */
222 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
223 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU register field value suitable for setting the register. */
224 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
225 
226 /*
227  * Field : fpga2soc
228  *
229  * Security bit configuration for transactions from fpga2soc to emac0rx_ecc. When
230  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
231  * Non-Secure transactions are allowed.
232  *
233  * Field Access Macros:
234  *
235  */
236 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC register field. */
237 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_LSB 16
238 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC register field. */
239 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_MSB 16
240 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC register field. */
241 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_WIDTH 1
242 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC register field value. */
243 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_SET_MSK 0x00010000
244 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC register field value. */
245 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
246 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC register field. */
247 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_RESET 0x0
248 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC field value from a register. */
249 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
250 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC register field value suitable for setting the register. */
251 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
252 
253 /*
254  * Field : axi_ap
255  *
256  * Security bit configuration for transactions from axi_ap to emac0rx_ecc. When
257  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
258  * Non-Secure transactions are allowed.
259  *
260  * Field Access Macros:
261  *
262  */
263 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP register field. */
264 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_LSB 24
265 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP register field. */
266 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_MSB 24
267 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP register field. */
268 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_WIDTH 1
269 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP register field value. */
270 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_SET_MSK 0x01000000
271 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP register field value. */
272 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_CLR_MSK 0xfeffffff
273 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP register field. */
274 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_RESET 0x0
275 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP field value from a register. */
276 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
277 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP register field value suitable for setting the register. */
278 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
279 
280 #ifndef __ASSEMBLY__
281 /*
282  * WARNING: The C register and register group struct declarations are provided for
283  * convenience and illustrative purposes. They should, however, be used with
284  * caution as the C language standard provides no guarantees about the alignment or
285  * atomicity of device memory accesses. The recommended practice for coding device
286  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
287  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
288  * alt_write_dword() functions for 64 bit registers.
289  *
290  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC.
291  */
292 struct ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_s
293 {
294  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU */
295  uint32_t : 15; /* *UNDEFINED* */
296  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC */
297  uint32_t : 7; /* *UNDEFINED* */
298  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP */
299  uint32_t : 7; /* *UNDEFINED* */
300 };
301 
302 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC. */
303 typedef struct ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_t;
304 #endif /* __ASSEMBLY__ */
305 
306 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC register. */
307 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_RESET 0x00000000
308 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC register from the beginning of the component. */
309 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_OFST 0xc
310 
311 /*
312  * Register : emac0tx_ecc
313  *
314  * Per-Master Security bit for emac0tx_ecc
315  *
316  * Register Layout
317  *
318  * Bits | Access | Reset | Description
319  * :--------|:-------|:--------|:-------------------------------------------
320  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU
321  * [15:1] | ??? | Unknown | *UNDEFINED*
322  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC
323  * [23:17] | ??? | Unknown | *UNDEFINED*
324  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP
325  * [31:25] | ??? | Unknown | *UNDEFINED*
326  *
327  */
328 /*
329  * Field : mpu
330  *
331  * Security bit configuration for transactions from mpu to emac0tx_ecc. When
332  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
333  * Non-Secure transactions are allowed.
334  *
335  * Field Access Macros:
336  *
337  */
338 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU register field. */
339 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_LSB 0
340 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU register field. */
341 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_MSB 0
342 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU register field. */
343 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_WIDTH 1
344 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU register field value. */
345 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_SET_MSK 0x00000001
346 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU register field value. */
347 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_CLR_MSK 0xfffffffe
348 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU register field. */
349 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_RESET 0x0
350 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU field value from a register. */
351 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
352 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU register field value suitable for setting the register. */
353 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
354 
355 /*
356  * Field : fpga2soc
357  *
358  * Security bit configuration for transactions from fpga2soc to emac0tx_ecc. When
359  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
360  * Non-Secure transactions are allowed.
361  *
362  * Field Access Macros:
363  *
364  */
365 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC register field. */
366 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_LSB 16
367 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC register field. */
368 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_MSB 16
369 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC register field. */
370 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_WIDTH 1
371 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC register field value. */
372 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_SET_MSK 0x00010000
373 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC register field value. */
374 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
375 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC register field. */
376 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_RESET 0x0
377 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC field value from a register. */
378 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
379 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC register field value suitable for setting the register. */
380 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
381 
382 /*
383  * Field : axi_ap
384  *
385  * Security bit configuration for transactions from axi_ap to emac0tx_ecc. When
386  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
387  * Non-Secure transactions are allowed.
388  *
389  * Field Access Macros:
390  *
391  */
392 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP register field. */
393 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_LSB 24
394 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP register field. */
395 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_MSB 24
396 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP register field. */
397 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_WIDTH 1
398 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP register field value. */
399 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_SET_MSK 0x01000000
400 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP register field value. */
401 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_CLR_MSK 0xfeffffff
402 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP register field. */
403 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_RESET 0x0
404 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP field value from a register. */
405 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
406 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP register field value suitable for setting the register. */
407 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
408 
409 #ifndef __ASSEMBLY__
410 /*
411  * WARNING: The C register and register group struct declarations are provided for
412  * convenience and illustrative purposes. They should, however, be used with
413  * caution as the C language standard provides no guarantees about the alignment or
414  * atomicity of device memory accesses. The recommended practice for coding device
415  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
416  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
417  * alt_write_dword() functions for 64 bit registers.
418  *
419  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC.
420  */
421 struct ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_s
422 {
423  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU */
424  uint32_t : 15; /* *UNDEFINED* */
425  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC */
426  uint32_t : 7; /* *UNDEFINED* */
427  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP */
428  uint32_t : 7; /* *UNDEFINED* */
429 };
430 
431 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC. */
432 typedef struct ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_t;
433 #endif /* __ASSEMBLY__ */
434 
435 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC register. */
436 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_RESET 0x00000000
437 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC register from the beginning of the component. */
438 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_OFST 0x10
439 
440 /*
441  * Register : emac1rx_ecc
442  *
443  * Per-Master Security bit for emac1rx_ecc
444  *
445  * Register Layout
446  *
447  * Bits | Access | Reset | Description
448  * :--------|:-------|:--------|:-------------------------------------------
449  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU
450  * [15:1] | ??? | Unknown | *UNDEFINED*
451  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC
452  * [23:17] | ??? | Unknown | *UNDEFINED*
453  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP
454  * [31:25] | ??? | Unknown | *UNDEFINED*
455  *
456  */
457 /*
458  * Field : mpu
459  *
460  * Security bit configuration for transactions from mpu to emac1rx_ecc. When
461  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
462  * Non-Secure transactions are allowed.
463  *
464  * Field Access Macros:
465  *
466  */
467 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU register field. */
468 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_LSB 0
469 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU register field. */
470 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_MSB 0
471 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU register field. */
472 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_WIDTH 1
473 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU register field value. */
474 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_SET_MSK 0x00000001
475 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU register field value. */
476 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_CLR_MSK 0xfffffffe
477 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU register field. */
478 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_RESET 0x0
479 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU field value from a register. */
480 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
481 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU register field value suitable for setting the register. */
482 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
483 
484 /*
485  * Field : fpga2soc
486  *
487  * Security bit configuration for transactions from fpga2soc to emac1rx_ecc. When
488  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
489  * Non-Secure transactions are allowed.
490  *
491  * Field Access Macros:
492  *
493  */
494 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC register field. */
495 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_LSB 16
496 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC register field. */
497 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_MSB 16
498 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC register field. */
499 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_WIDTH 1
500 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC register field value. */
501 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_SET_MSK 0x00010000
502 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC register field value. */
503 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
504 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC register field. */
505 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_RESET 0x0
506 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC field value from a register. */
507 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
508 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC register field value suitable for setting the register. */
509 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
510 
511 /*
512  * Field : axi_ap
513  *
514  * Security bit configuration for transactions from axi_ap to emac1rx_ecc. When
515  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
516  * Non-Secure transactions are allowed.
517  *
518  * Field Access Macros:
519  *
520  */
521 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP register field. */
522 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_LSB 24
523 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP register field. */
524 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_MSB 24
525 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP register field. */
526 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_WIDTH 1
527 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP register field value. */
528 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_SET_MSK 0x01000000
529 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP register field value. */
530 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_CLR_MSK 0xfeffffff
531 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP register field. */
532 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_RESET 0x0
533 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP field value from a register. */
534 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
535 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP register field value suitable for setting the register. */
536 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
537 
538 #ifndef __ASSEMBLY__
539 /*
540  * WARNING: The C register and register group struct declarations are provided for
541  * convenience and illustrative purposes. They should, however, be used with
542  * caution as the C language standard provides no guarantees about the alignment or
543  * atomicity of device memory accesses. The recommended practice for coding device
544  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
545  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
546  * alt_write_dword() functions for 64 bit registers.
547  *
548  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC.
549  */
550 struct ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_s
551 {
552  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU */
553  uint32_t : 15; /* *UNDEFINED* */
554  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC */
555  uint32_t : 7; /* *UNDEFINED* */
556  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP */
557  uint32_t : 7; /* *UNDEFINED* */
558 };
559 
560 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC. */
561 typedef struct ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_t;
562 #endif /* __ASSEMBLY__ */
563 
564 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC register. */
565 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_RESET 0x00000000
566 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC register from the beginning of the component. */
567 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_OFST 0x14
568 
569 /*
570  * Register : emac1tx_ecc
571  *
572  * Per-Master Security bit for emac1tx_ecc
573  *
574  * Register Layout
575  *
576  * Bits | Access | Reset | Description
577  * :--------|:-------|:--------|:-------------------------------------------
578  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU
579  * [15:1] | ??? | Unknown | *UNDEFINED*
580  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC
581  * [23:17] | ??? | Unknown | *UNDEFINED*
582  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP
583  * [31:25] | ??? | Unknown | *UNDEFINED*
584  *
585  */
586 /*
587  * Field : mpu
588  *
589  * Security bit configuration for transactions from mpu to emac1tx_ecc. When
590  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
591  * Non-Secure transactions are allowed.
592  *
593  * Field Access Macros:
594  *
595  */
596 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU register field. */
597 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_LSB 0
598 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU register field. */
599 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_MSB 0
600 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU register field. */
601 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_WIDTH 1
602 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU register field value. */
603 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_SET_MSK 0x00000001
604 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU register field value. */
605 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_CLR_MSK 0xfffffffe
606 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU register field. */
607 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_RESET 0x0
608 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU field value from a register. */
609 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
610 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU register field value suitable for setting the register. */
611 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
612 
613 /*
614  * Field : fpga2soc
615  *
616  * Security bit configuration for transactions from fpga2soc to emac1tx_ecc. When
617  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
618  * Non-Secure transactions are allowed.
619  *
620  * Field Access Macros:
621  *
622  */
623 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC register field. */
624 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_LSB 16
625 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC register field. */
626 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_MSB 16
627 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC register field. */
628 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_WIDTH 1
629 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC register field value. */
630 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_SET_MSK 0x00010000
631 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC register field value. */
632 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
633 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC register field. */
634 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_RESET 0x0
635 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC field value from a register. */
636 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
637 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC register field value suitable for setting the register. */
638 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
639 
640 /*
641  * Field : axi_ap
642  *
643  * Security bit configuration for transactions from axi_ap to emac1tx_ecc. When
644  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
645  * Non-Secure transactions are allowed.
646  *
647  * Field Access Macros:
648  *
649  */
650 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP register field. */
651 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_LSB 24
652 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP register field. */
653 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_MSB 24
654 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP register field. */
655 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_WIDTH 1
656 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP register field value. */
657 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_SET_MSK 0x01000000
658 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP register field value. */
659 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_CLR_MSK 0xfeffffff
660 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP register field. */
661 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_RESET 0x0
662 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP field value from a register. */
663 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
664 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP register field value suitable for setting the register. */
665 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
666 
667 #ifndef __ASSEMBLY__
668 /*
669  * WARNING: The C register and register group struct declarations are provided for
670  * convenience and illustrative purposes. They should, however, be used with
671  * caution as the C language standard provides no guarantees about the alignment or
672  * atomicity of device memory accesses. The recommended practice for coding device
673  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
674  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
675  * alt_write_dword() functions for 64 bit registers.
676  *
677  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC.
678  */
679 struct ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_s
680 {
681  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU */
682  uint32_t : 15; /* *UNDEFINED* */
683  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC */
684  uint32_t : 7; /* *UNDEFINED* */
685  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP */
686  uint32_t : 7; /* *UNDEFINED* */
687 };
688 
689 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC. */
690 typedef struct ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_t;
691 #endif /* __ASSEMBLY__ */
692 
693 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC register. */
694 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_RESET 0x00000000
695 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC register from the beginning of the component. */
696 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_OFST 0x18
697 
698 /*
699  * Register : emac2rx_ecc
700  *
701  * Per-Master Security bit for emac2rx_ecc
702  *
703  * Register Layout
704  *
705  * Bits | Access | Reset | Description
706  * :--------|:-------|:--------|:-------------------------------------------
707  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU
708  * [15:1] | ??? | Unknown | *UNDEFINED*
709  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC
710  * [23:17] | ??? | Unknown | *UNDEFINED*
711  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP
712  * [31:25] | ??? | Unknown | *UNDEFINED*
713  *
714  */
715 /*
716  * Field : mpu
717  *
718  * Security bit configuration for transactions from mpu to emac2rx_ecc. When
719  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
720  * Non-Secure transactions are allowed.
721  *
722  * Field Access Macros:
723  *
724  */
725 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU register field. */
726 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_LSB 0
727 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU register field. */
728 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_MSB 0
729 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU register field. */
730 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_WIDTH 1
731 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU register field value. */
732 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_SET_MSK 0x00000001
733 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU register field value. */
734 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_CLR_MSK 0xfffffffe
735 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU register field. */
736 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_RESET 0x0
737 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU field value from a register. */
738 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
739 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU register field value suitable for setting the register. */
740 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
741 
742 /*
743  * Field : fpga2soc
744  *
745  * Security bit configuration for transactions from fpga2soc to emac2rx_ecc. When
746  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
747  * Non-Secure transactions are allowed.
748  *
749  * Field Access Macros:
750  *
751  */
752 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC register field. */
753 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_LSB 16
754 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC register field. */
755 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_MSB 16
756 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC register field. */
757 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_WIDTH 1
758 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC register field value. */
759 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_SET_MSK 0x00010000
760 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC register field value. */
761 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
762 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC register field. */
763 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_RESET 0x0
764 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC field value from a register. */
765 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
766 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC register field value suitable for setting the register. */
767 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
768 
769 /*
770  * Field : axi_ap
771  *
772  * Security bit configuration for transactions from axi_ap to emac2rx_ecc. When
773  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
774  * Non-Secure transactions are allowed.
775  *
776  * Field Access Macros:
777  *
778  */
779 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP register field. */
780 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_LSB 24
781 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP register field. */
782 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_MSB 24
783 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP register field. */
784 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_WIDTH 1
785 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP register field value. */
786 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_SET_MSK 0x01000000
787 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP register field value. */
788 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_CLR_MSK 0xfeffffff
789 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP register field. */
790 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_RESET 0x0
791 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP field value from a register. */
792 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
793 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP register field value suitable for setting the register. */
794 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
795 
796 #ifndef __ASSEMBLY__
797 /*
798  * WARNING: The C register and register group struct declarations are provided for
799  * convenience and illustrative purposes. They should, however, be used with
800  * caution as the C language standard provides no guarantees about the alignment or
801  * atomicity of device memory accesses. The recommended practice for coding device
802  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
803  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
804  * alt_write_dword() functions for 64 bit registers.
805  *
806  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC.
807  */
808 struct ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_s
809 {
810  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU */
811  uint32_t : 15; /* *UNDEFINED* */
812  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC */
813  uint32_t : 7; /* *UNDEFINED* */
814  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP */
815  uint32_t : 7; /* *UNDEFINED* */
816 };
817 
818 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC. */
819 typedef struct ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_t;
820 #endif /* __ASSEMBLY__ */
821 
822 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC register. */
823 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_RESET 0x00000000
824 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC register from the beginning of the component. */
825 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_OFST 0x1c
826 
827 /*
828  * Register : emac2tx_ecc
829  *
830  * Per-Master Security bit for emac2tx_ecc
831  *
832  * Register Layout
833  *
834  * Bits | Access | Reset | Description
835  * :--------|:-------|:--------|:-------------------------------------------
836  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU
837  * [15:1] | ??? | Unknown | *UNDEFINED*
838  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC
839  * [23:17] | ??? | Unknown | *UNDEFINED*
840  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP
841  * [31:25] | ??? | Unknown | *UNDEFINED*
842  *
843  */
844 /*
845  * Field : mpu
846  *
847  * Security bit configuration for transactions from mpu to emac2tx_ecc. When
848  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
849  * Non-Secure transactions are allowed.
850  *
851  * Field Access Macros:
852  *
853  */
854 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU register field. */
855 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_LSB 0
856 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU register field. */
857 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_MSB 0
858 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU register field. */
859 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_WIDTH 1
860 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU register field value. */
861 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_SET_MSK 0x00000001
862 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU register field value. */
863 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_CLR_MSK 0xfffffffe
864 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU register field. */
865 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_RESET 0x0
866 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU field value from a register. */
867 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
868 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU register field value suitable for setting the register. */
869 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
870 
871 /*
872  * Field : fpga2soc
873  *
874  * Security bit configuration for transactions from fpga2soc to emac2tx_ecc. When
875  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
876  * Non-Secure transactions are allowed.
877  *
878  * Field Access Macros:
879  *
880  */
881 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC register field. */
882 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_LSB 16
883 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC register field. */
884 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_MSB 16
885 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC register field. */
886 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_WIDTH 1
887 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC register field value. */
888 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_SET_MSK 0x00010000
889 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC register field value. */
890 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
891 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC register field. */
892 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_RESET 0x0
893 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC field value from a register. */
894 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
895 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC register field value suitable for setting the register. */
896 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
897 
898 /*
899  * Field : axi_ap
900  *
901  * Security bit configuration for transactions from axi_ap to emac2tx_ecc. When
902  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
903  * Non-Secure transactions are allowed.
904  *
905  * Field Access Macros:
906  *
907  */
908 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP register field. */
909 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_LSB 24
910 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP register field. */
911 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_MSB 24
912 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP register field. */
913 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_WIDTH 1
914 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP register field value. */
915 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_SET_MSK 0x01000000
916 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP register field value. */
917 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_CLR_MSK 0xfeffffff
918 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP register field. */
919 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_RESET 0x0
920 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP field value from a register. */
921 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
922 /* Produces a ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP register field value suitable for setting the register. */
923 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
924 
925 #ifndef __ASSEMBLY__
926 /*
927  * WARNING: The C register and register group struct declarations are provided for
928  * convenience and illustrative purposes. They should, however, be used with
929  * caution as the C language standard provides no guarantees about the alignment or
930  * atomicity of device memory accesses. The recommended practice for coding device
931  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
932  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
933  * alt_write_dword() functions for 64 bit registers.
934  *
935  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC.
936  */
937 struct ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_s
938 {
939  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU */
940  uint32_t : 15; /* *UNDEFINED* */
941  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC */
942  uint32_t : 7; /* *UNDEFINED* */
943  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP */
944  uint32_t : 7; /* *UNDEFINED* */
945 };
946 
947 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC. */
948 typedef struct ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_t;
949 #endif /* __ASSEMBLY__ */
950 
951 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC register. */
952 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_RESET 0x00000000
953 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC register from the beginning of the component. */
954 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_OFST 0x20
955 
956 /*
957  * Register : nand_ecc
958  *
959  * Per-Master Security bit for nand_ecc
960  *
961  * Register Layout
962  *
963  * Bits | Access | Reset | Description
964  * :--------|:-------|:--------|:----------------------------------------
965  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU
966  * [15:1] | ??? | Unknown | *UNDEFINED*
967  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC
968  * [23:17] | ??? | Unknown | *UNDEFINED*
969  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP
970  * [31:25] | ??? | Unknown | *UNDEFINED*
971  *
972  */
973 /*
974  * Field : mpu
975  *
976  * Security bit configuration for transactions from mpu to nand_ecc. When cleared
977  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
978  * Secure transactions are allowed.
979  *
980  * Field Access Macros:
981  *
982  */
983 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU register field. */
984 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_LSB 0
985 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU register field. */
986 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_MSB 0
987 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU register field. */
988 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_WIDTH 1
989 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU register field value. */
990 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_SET_MSK 0x00000001
991 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU register field value. */
992 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_CLR_MSK 0xfffffffe
993 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU register field. */
994 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_RESET 0x0
995 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU field value from a register. */
996 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
997 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU register field value suitable for setting the register. */
998 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
999 
1000 /*
1001  * Field : fpga2soc
1002  *
1003  * Security bit configuration for transactions from fpga2soc to nand_ecc. When
1004  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1005  * Non-Secure transactions are allowed.
1006  *
1007  * Field Access Macros:
1008  *
1009  */
1010 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC register field. */
1011 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_LSB 16
1012 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC register field. */
1013 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_MSB 16
1014 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC register field. */
1015 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_WIDTH 1
1016 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC register field value. */
1017 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_SET_MSK 0x00010000
1018 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC register field value. */
1019 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1020 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC register field. */
1021 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_RESET 0x0
1022 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC field value from a register. */
1023 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1024 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC register field value suitable for setting the register. */
1025 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1026 
1027 /*
1028  * Field : axi_ap
1029  *
1030  * Security bit configuration for transactions from axi_ap to nand_ecc. When
1031  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1032  * Non-Secure transactions are allowed.
1033  *
1034  * Field Access Macros:
1035  *
1036  */
1037 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP register field. */
1038 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_LSB 24
1039 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP register field. */
1040 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_MSB 24
1041 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP register field. */
1042 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_WIDTH 1
1043 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP register field value. */
1044 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_SET_MSK 0x01000000
1045 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP register field value. */
1046 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_CLR_MSK 0xfeffffff
1047 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP register field. */
1048 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_RESET 0x0
1049 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP field value from a register. */
1050 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1051 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP register field value suitable for setting the register. */
1052 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1053 
1054 #ifndef __ASSEMBLY__
1055 /*
1056  * WARNING: The C register and register group struct declarations are provided for
1057  * convenience and illustrative purposes. They should, however, be used with
1058  * caution as the C language standard provides no guarantees about the alignment or
1059  * atomicity of device memory accesses. The recommended practice for coding device
1060  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1061  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1062  * alt_write_dword() functions for 64 bit registers.
1063  *
1064  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_NAND_ECC.
1065  */
1066 struct ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_s
1067 {
1068  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU */
1069  uint32_t : 15; /* *UNDEFINED* */
1070  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC */
1071  uint32_t : 7; /* *UNDEFINED* */
1072  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP */
1073  uint32_t : 7; /* *UNDEFINED* */
1074 };
1075 
1076 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_NAND_ECC. */
1077 typedef struct ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_s ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_t;
1078 #endif /* __ASSEMBLY__ */
1079 
1080 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC register. */
1081 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_RESET 0x00000000
1082 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_NAND_ECC register from the beginning of the component. */
1083 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_OFST 0x2c
1084 
1085 /*
1086  * Register : nand_read_ecc
1087  *
1088  * Per-Master Security bit for nand_read_ecc
1089  *
1090  * Register Layout
1091  *
1092  * Bits | Access | Reset | Description
1093  * :--------|:-------|:--------|:---------------------------------------------
1094  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU
1095  * [15:1] | ??? | Unknown | *UNDEFINED*
1096  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC
1097  * [23:17] | ??? | Unknown | *UNDEFINED*
1098  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP
1099  * [31:25] | ??? | Unknown | *UNDEFINED*
1100  *
1101  */
1102 /*
1103  * Field : mpu
1104  *
1105  * Security bit configuration for transactions from mpu to nand_read_ecc. When
1106  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1107  * Non-Secure transactions are allowed.
1108  *
1109  * Field Access Macros:
1110  *
1111  */
1112 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU register field. */
1113 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_LSB 0
1114 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU register field. */
1115 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_MSB 0
1116 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU register field. */
1117 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_WIDTH 1
1118 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU register field value. */
1119 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_SET_MSK 0x00000001
1120 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU register field value. */
1121 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_CLR_MSK 0xfffffffe
1122 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU register field. */
1123 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_RESET 0x0
1124 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU field value from a register. */
1125 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1126 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU register field value suitable for setting the register. */
1127 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
1128 
1129 /*
1130  * Field : fpga2soc
1131  *
1132  * Security bit configuration for transactions from fpga2soc to nand_read_ecc. When
1133  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1134  * Non-Secure transactions are allowed.
1135  *
1136  * Field Access Macros:
1137  *
1138  */
1139 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC register field. */
1140 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_LSB 16
1141 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC register field. */
1142 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_MSB 16
1143 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC register field. */
1144 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_WIDTH 1
1145 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC register field value. */
1146 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_SET_MSK 0x00010000
1147 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC register field value. */
1148 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1149 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC register field. */
1150 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_RESET 0x0
1151 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC field value from a register. */
1152 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1153 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC register field value suitable for setting the register. */
1154 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1155 
1156 /*
1157  * Field : axi_ap
1158  *
1159  * Security bit configuration for transactions from axi_ap to nand_read_ecc. When
1160  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1161  * Non-Secure transactions are allowed.
1162  *
1163  * Field Access Macros:
1164  *
1165  */
1166 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP register field. */
1167 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_LSB 24
1168 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP register field. */
1169 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_MSB 24
1170 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP register field. */
1171 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_WIDTH 1
1172 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP register field value. */
1173 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_SET_MSK 0x01000000
1174 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP register field value. */
1175 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_CLR_MSK 0xfeffffff
1176 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP register field. */
1177 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_RESET 0x0
1178 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP field value from a register. */
1179 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1180 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP register field value suitable for setting the register. */
1181 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1182 
1183 #ifndef __ASSEMBLY__
1184 /*
1185  * WARNING: The C register and register group struct declarations are provided for
1186  * convenience and illustrative purposes. They should, however, be used with
1187  * caution as the C language standard provides no guarantees about the alignment or
1188  * atomicity of device memory accesses. The recommended practice for coding device
1189  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1190  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1191  * alt_write_dword() functions for 64 bit registers.
1192  *
1193  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC.
1194  */
1195 struct ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_s
1196 {
1197  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU */
1198  uint32_t : 15; /* *UNDEFINED* */
1199  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC */
1200  uint32_t : 7; /* *UNDEFINED* */
1201  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP */
1202  uint32_t : 7; /* *UNDEFINED* */
1203 };
1204 
1205 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC. */
1206 typedef struct ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_s ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_t;
1207 #endif /* __ASSEMBLY__ */
1208 
1209 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC register. */
1210 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_RESET 0x00000000
1211 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC register from the beginning of the component. */
1212 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_OFST 0x30
1213 
1214 /*
1215  * Register : nand_write_ecc
1216  *
1217  * Per-Master Security bit for nand_write_ecc
1218  *
1219  * Register Layout
1220  *
1221  * Bits | Access | Reset | Description
1222  * :--------|:-------|:--------|:----------------------------------------------
1223  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU
1224  * [15:1] | ??? | Unknown | *UNDEFINED*
1225  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC
1226  * [23:17] | ??? | Unknown | *UNDEFINED*
1227  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP
1228  * [31:25] | ??? | Unknown | *UNDEFINED*
1229  *
1230  */
1231 /*
1232  * Field : mpu
1233  *
1234  * Security bit configuration for transactions from mpu to nand_write_ecc. When
1235  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1236  * Non-Secure transactions are allowed.
1237  *
1238  * Field Access Macros:
1239  *
1240  */
1241 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU register field. */
1242 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_LSB 0
1243 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU register field. */
1244 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_MSB 0
1245 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU register field. */
1246 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_WIDTH 1
1247 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU register field value. */
1248 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_SET_MSK 0x00000001
1249 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU register field value. */
1250 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_CLR_MSK 0xfffffffe
1251 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU register field. */
1252 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_RESET 0x0
1253 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU field value from a register. */
1254 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1255 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU register field value suitable for setting the register. */
1256 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
1257 
1258 /*
1259  * Field : fpga2soc
1260  *
1261  * Security bit configuration for transactions from fpga2soc to nand_write_ecc.
1262  * When cleared (0), only Secure transactions are allowed. When set (1), both
1263  * Secure and Non-Secure transactions are allowed.
1264  *
1265  * Field Access Macros:
1266  *
1267  */
1268 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC register field. */
1269 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_LSB 16
1270 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC register field. */
1271 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_MSB 16
1272 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC register field. */
1273 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_WIDTH 1
1274 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC register field value. */
1275 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_SET_MSK 0x00010000
1276 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC register field value. */
1277 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1278 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC register field. */
1279 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_RESET 0x0
1280 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC field value from a register. */
1281 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1282 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC register field value suitable for setting the register. */
1283 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1284 
1285 /*
1286  * Field : axi_ap
1287  *
1288  * Security bit configuration for transactions from axi_ap to nand_write_ecc. When
1289  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1290  * Non-Secure transactions are allowed.
1291  *
1292  * Field Access Macros:
1293  *
1294  */
1295 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP register field. */
1296 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_LSB 24
1297 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP register field. */
1298 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_MSB 24
1299 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP register field. */
1300 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_WIDTH 1
1301 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP register field value. */
1302 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_SET_MSK 0x01000000
1303 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP register field value. */
1304 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_CLR_MSK 0xfeffffff
1305 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP register field. */
1306 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_RESET 0x0
1307 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP field value from a register. */
1308 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1309 /* Produces a ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP register field value suitable for setting the register. */
1310 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1311 
1312 #ifndef __ASSEMBLY__
1313 /*
1314  * WARNING: The C register and register group struct declarations are provided for
1315  * convenience and illustrative purposes. They should, however, be used with
1316  * caution as the C language standard provides no guarantees about the alignment or
1317  * atomicity of device memory accesses. The recommended practice for coding device
1318  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1319  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1320  * alt_write_dword() functions for 64 bit registers.
1321  *
1322  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC.
1323  */
1324 struct ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_s
1325 {
1326  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU */
1327  uint32_t : 15; /* *UNDEFINED* */
1328  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC */
1329  uint32_t : 7; /* *UNDEFINED* */
1330  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP */
1331  uint32_t : 7; /* *UNDEFINED* */
1332 };
1333 
1334 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC. */
1335 typedef struct ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_s ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_t;
1336 #endif /* __ASSEMBLY__ */
1337 
1338 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC register. */
1339 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_RESET 0x00000000
1340 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC register from the beginning of the component. */
1341 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_OFST 0x34
1342 
1343 /*
1344  * Register : ocram_ecc
1345  *
1346  * Per-Master Security bit for onchipram_ecc
1347  *
1348  * Register Layout
1349  *
1350  * Bits | Access | Reset | Description
1351  * :--------|:-------|:--------|:-----------------------------------------
1352  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU
1353  * [15:1] | ??? | Unknown | *UNDEFINED*
1354  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC
1355  * [23:17] | ??? | Unknown | *UNDEFINED*
1356  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP
1357  * [31:25] | ??? | Unknown | *UNDEFINED*
1358  *
1359  */
1360 /*
1361  * Field : mpu
1362  *
1363  * Security bit configuration for transactions from mpu to onchipram_ecc. When
1364  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1365  * Non-Secure transactions are allowed.
1366  *
1367  * Field Access Macros:
1368  *
1369  */
1370 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU register field. */
1371 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_LSB 0
1372 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU register field. */
1373 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_MSB 0
1374 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU register field. */
1375 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_WIDTH 1
1376 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU register field value. */
1377 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_SET_MSK 0x00000001
1378 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU register field value. */
1379 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_CLR_MSK 0xfffffffe
1380 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU register field. */
1381 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_RESET 0x0
1382 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU field value from a register. */
1383 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1384 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU register field value suitable for setting the register. */
1385 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
1386 
1387 /*
1388  * Field : fpga2soc
1389  *
1390  * Security bit configuration for transactions from fpga2soc to onchipram_ecc. When
1391  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1392  * Non-Secure transactions are allowed.
1393  *
1394  * Field Access Macros:
1395  *
1396  */
1397 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC register field. */
1398 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_LSB 16
1399 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC register field. */
1400 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_MSB 16
1401 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC register field. */
1402 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_WIDTH 1
1403 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC register field value. */
1404 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_SET_MSK 0x00010000
1405 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC register field value. */
1406 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1407 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC register field. */
1408 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_RESET 0x0
1409 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC field value from a register. */
1410 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1411 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC register field value suitable for setting the register. */
1412 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1413 
1414 /*
1415  * Field : axi_ap
1416  *
1417  * Security bit configuration for transactions from axi_ap to onchipram_ecc. When
1418  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1419  * Non-Secure transactions are allowed.
1420  *
1421  * Field Access Macros:
1422  *
1423  */
1424 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP register field. */
1425 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_LSB 24
1426 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP register field. */
1427 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_MSB 24
1428 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP register field. */
1429 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_WIDTH 1
1430 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP register field value. */
1431 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_SET_MSK 0x01000000
1432 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP register field value. */
1433 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_CLR_MSK 0xfeffffff
1434 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP register field. */
1435 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_RESET 0x0
1436 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP field value from a register. */
1437 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1438 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP register field value suitable for setting the register. */
1439 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1440 
1441 #ifndef __ASSEMBLY__
1442 /*
1443  * WARNING: The C register and register group struct declarations are provided for
1444  * convenience and illustrative purposes. They should, however, be used with
1445  * caution as the C language standard provides no guarantees about the alignment or
1446  * atomicity of device memory accesses. The recommended practice for coding device
1447  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1448  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1449  * alt_write_dword() functions for 64 bit registers.
1450  *
1451  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC.
1452  */
1453 struct ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_s
1454 {
1455  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU */
1456  uint32_t : 15; /* *UNDEFINED* */
1457  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC */
1458  uint32_t : 7; /* *UNDEFINED* */
1459  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP */
1460  uint32_t : 7; /* *UNDEFINED* */
1461 };
1462 
1463 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC. */
1464 typedef struct ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_s ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_t;
1465 #endif /* __ASSEMBLY__ */
1466 
1467 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC register. */
1468 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_RESET 0x00000000
1469 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC register from the beginning of the component. */
1470 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_OFST 0x38
1471 
1472 /*
1473  * Register : sdmmc_ecc
1474  *
1475  * Per-Master Security bit for sdmmc_ecc
1476  *
1477  * Register Layout
1478  *
1479  * Bits | Access | Reset | Description
1480  * :--------|:-------|:--------|:-----------------------------------------
1481  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU
1482  * [15:1] | ??? | Unknown | *UNDEFINED*
1483  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC
1484  * [23:17] | ??? | Unknown | *UNDEFINED*
1485  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP
1486  * [31:25] | ??? | Unknown | *UNDEFINED*
1487  *
1488  */
1489 /*
1490  * Field : mpu
1491  *
1492  * Security bit configuration for transactions from mpu to sdmmc_ecc. When cleared
1493  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1494  * Secure transactions are allowed.
1495  *
1496  * Field Access Macros:
1497  *
1498  */
1499 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU register field. */
1500 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_LSB 0
1501 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU register field. */
1502 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_MSB 0
1503 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU register field. */
1504 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_WIDTH 1
1505 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU register field value. */
1506 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_SET_MSK 0x00000001
1507 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU register field value. */
1508 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_CLR_MSK 0xfffffffe
1509 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU register field. */
1510 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_RESET 0x0
1511 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU field value from a register. */
1512 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1513 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU register field value suitable for setting the register. */
1514 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
1515 
1516 /*
1517  * Field : fpga2soc
1518  *
1519  * Security bit configuration for transactions from fpga2soc to sdmmc_ecc. When
1520  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1521  * Non-Secure transactions are allowed.
1522  *
1523  * Field Access Macros:
1524  *
1525  */
1526 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC register field. */
1527 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_LSB 16
1528 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC register field. */
1529 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_MSB 16
1530 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC register field. */
1531 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_WIDTH 1
1532 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC register field value. */
1533 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_SET_MSK 0x00010000
1534 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC register field value. */
1535 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1536 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC register field. */
1537 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_RESET 0x0
1538 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC field value from a register. */
1539 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1540 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC register field value suitable for setting the register. */
1541 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1542 
1543 /*
1544  * Field : axi_ap
1545  *
1546  * Security bit configuration for transactions from axi_ap to sdmmc_ecc. When
1547  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1548  * Non-Secure transactions are allowed.
1549  *
1550  * Field Access Macros:
1551  *
1552  */
1553 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP register field. */
1554 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_LSB 24
1555 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP register field. */
1556 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_MSB 24
1557 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP register field. */
1558 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_WIDTH 1
1559 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP register field value. */
1560 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_SET_MSK 0x01000000
1561 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP register field value. */
1562 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_CLR_MSK 0xfeffffff
1563 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP register field. */
1564 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_RESET 0x0
1565 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP field value from a register. */
1566 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1567 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP register field value suitable for setting the register. */
1568 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1569 
1570 #ifndef __ASSEMBLY__
1571 /*
1572  * WARNING: The C register and register group struct declarations are provided for
1573  * convenience and illustrative purposes. They should, however, be used with
1574  * caution as the C language standard provides no guarantees about the alignment or
1575  * atomicity of device memory accesses. The recommended practice for coding device
1576  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1577  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1578  * alt_write_dword() functions for 64 bit registers.
1579  *
1580  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC.
1581  */
1582 struct ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_s
1583 {
1584  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU */
1585  uint32_t : 15; /* *UNDEFINED* */
1586  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC */
1587  uint32_t : 7; /* *UNDEFINED* */
1588  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP */
1589  uint32_t : 7; /* *UNDEFINED* */
1590 };
1591 
1592 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC. */
1593 typedef struct ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_s ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_t;
1594 #endif /* __ASSEMBLY__ */
1595 
1596 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC register. */
1597 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_RESET 0x00000000
1598 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC register from the beginning of the component. */
1599 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_OFST 0x40
1600 
1601 /*
1602  * Register : usb0_ecc
1603  *
1604  * Per-Master Security bit for usb0_ecc
1605  *
1606  * Register Layout
1607  *
1608  * Bits | Access | Reset | Description
1609  * :--------|:-------|:--------|:----------------------------------------
1610  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU
1611  * [15:1] | ??? | Unknown | *UNDEFINED*
1612  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC
1613  * [23:17] | ??? | Unknown | *UNDEFINED*
1614  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP
1615  * [31:25] | ??? | Unknown | *UNDEFINED*
1616  *
1617  */
1618 /*
1619  * Field : mpu
1620  *
1621  * Security bit configuration for transactions from mpu to usb0_ecc. When cleared
1622  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1623  * Secure transactions are allowed.
1624  *
1625  * Field Access Macros:
1626  *
1627  */
1628 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU register field. */
1629 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_LSB 0
1630 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU register field. */
1631 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_MSB 0
1632 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU register field. */
1633 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_WIDTH 1
1634 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU register field value. */
1635 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_SET_MSK 0x00000001
1636 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU register field value. */
1637 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_CLR_MSK 0xfffffffe
1638 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU register field. */
1639 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_RESET 0x0
1640 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU field value from a register. */
1641 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1642 /* Produces a ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU register field value suitable for setting the register. */
1643 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
1644 
1645 /*
1646  * Field : fpga2soc
1647  *
1648  * Security bit configuration for transactions from fpga2soc to usb0_ecc. When
1649  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1650  * Non-Secure transactions are allowed.
1651  *
1652  * Field Access Macros:
1653  *
1654  */
1655 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC register field. */
1656 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_LSB 16
1657 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC register field. */
1658 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_MSB 16
1659 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC register field. */
1660 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_WIDTH 1
1661 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC register field value. */
1662 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_SET_MSK 0x00010000
1663 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC register field value. */
1664 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1665 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC register field. */
1666 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_RESET 0x0
1667 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC field value from a register. */
1668 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1669 /* Produces a ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC register field value suitable for setting the register. */
1670 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1671 
1672 /*
1673  * Field : axi_ap
1674  *
1675  * Security bit configuration for transactions from axi_ap to usb0_ecc. When
1676  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1677  * Non-Secure transactions are allowed.
1678  *
1679  * Field Access Macros:
1680  *
1681  */
1682 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP register field. */
1683 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_LSB 24
1684 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP register field. */
1685 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_MSB 24
1686 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP register field. */
1687 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_WIDTH 1
1688 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP register field value. */
1689 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_SET_MSK 0x01000000
1690 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP register field value. */
1691 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_CLR_MSK 0xfeffffff
1692 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP register field. */
1693 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_RESET 0x0
1694 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP field value from a register. */
1695 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1696 /* Produces a ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP register field value suitable for setting the register. */
1697 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1698 
1699 #ifndef __ASSEMBLY__
1700 /*
1701  * WARNING: The C register and register group struct declarations are provided for
1702  * convenience and illustrative purposes. They should, however, be used with
1703  * caution as the C language standard provides no guarantees about the alignment or
1704  * atomicity of device memory accesses. The recommended practice for coding device
1705  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1706  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1707  * alt_write_dword() functions for 64 bit registers.
1708  *
1709  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_USB0_ECC.
1710  */
1711 struct ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_s
1712 {
1713  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU */
1714  uint32_t : 15; /* *UNDEFINED* */
1715  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC */
1716  uint32_t : 7; /* *UNDEFINED* */
1717  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP */
1718  uint32_t : 7; /* *UNDEFINED* */
1719 };
1720 
1721 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_USB0_ECC. */
1722 typedef struct ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_s ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_t;
1723 #endif /* __ASSEMBLY__ */
1724 
1725 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC register. */
1726 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_RESET 0x00000000
1727 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_USB0_ECC register from the beginning of the component. */
1728 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_OFST 0x44
1729 
1730 /*
1731  * Register : usb1_ecc
1732  *
1733  * Per-Master Security bit for usb1_ecc
1734  *
1735  * Register Layout
1736  *
1737  * Bits | Access | Reset | Description
1738  * :--------|:-------|:--------|:----------------------------------------
1739  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU
1740  * [15:1] | ??? | Unknown | *UNDEFINED*
1741  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC
1742  * [23:17] | ??? | Unknown | *UNDEFINED*
1743  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP
1744  * [31:25] | ??? | Unknown | *UNDEFINED*
1745  *
1746  */
1747 /*
1748  * Field : mpu
1749  *
1750  * Security bit configuration for transactions from mpu to usb1_ecc. When cleared
1751  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
1752  * Secure transactions are allowed.
1753  *
1754  * Field Access Macros:
1755  *
1756  */
1757 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU register field. */
1758 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_LSB 0
1759 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU register field. */
1760 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_MSB 0
1761 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU register field. */
1762 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_WIDTH 1
1763 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU register field value. */
1764 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_SET_MSK 0x00000001
1765 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU register field value. */
1766 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_CLR_MSK 0xfffffffe
1767 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU register field. */
1768 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_RESET 0x0
1769 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU field value from a register. */
1770 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1771 /* Produces a ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU register field value suitable for setting the register. */
1772 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
1773 
1774 /*
1775  * Field : fpga2soc
1776  *
1777  * Security bit configuration for transactions from fpga2soc to usb1_ecc. When
1778  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1779  * Non-Secure transactions are allowed.
1780  *
1781  * Field Access Macros:
1782  *
1783  */
1784 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC register field. */
1785 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_LSB 16
1786 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC register field. */
1787 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_MSB 16
1788 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC register field. */
1789 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_WIDTH 1
1790 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC register field value. */
1791 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_SET_MSK 0x00010000
1792 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC register field value. */
1793 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1794 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC register field. */
1795 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_RESET 0x0
1796 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC field value from a register. */
1797 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1798 /* Produces a ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC register field value suitable for setting the register. */
1799 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1800 
1801 /*
1802  * Field : axi_ap
1803  *
1804  * Security bit configuration for transactions from axi_ap to usb1_ecc. When
1805  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1806  * Non-Secure transactions are allowed.
1807  *
1808  * Field Access Macros:
1809  *
1810  */
1811 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP register field. */
1812 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_LSB 24
1813 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP register field. */
1814 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_MSB 24
1815 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP register field. */
1816 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_WIDTH 1
1817 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP register field value. */
1818 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_SET_MSK 0x01000000
1819 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP register field value. */
1820 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_CLR_MSK 0xfeffffff
1821 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP register field. */
1822 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_RESET 0x0
1823 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP field value from a register. */
1824 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1825 /* Produces a ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP register field value suitable for setting the register. */
1826 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1827 
1828 #ifndef __ASSEMBLY__
1829 /*
1830  * WARNING: The C register and register group struct declarations are provided for
1831  * convenience and illustrative purposes. They should, however, be used with
1832  * caution as the C language standard provides no guarantees about the alignment or
1833  * atomicity of device memory accesses. The recommended practice for coding device
1834  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1835  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1836  * alt_write_dword() functions for 64 bit registers.
1837  *
1838  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_USB1_ECC.
1839  */
1840 struct ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_s
1841 {
1842  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU */
1843  uint32_t : 15; /* *UNDEFINED* */
1844  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC */
1845  uint32_t : 7; /* *UNDEFINED* */
1846  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP */
1847  uint32_t : 7; /* *UNDEFINED* */
1848 };
1849 
1850 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_USB1_ECC. */
1851 typedef struct ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_s ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_t;
1852 #endif /* __ASSEMBLY__ */
1853 
1854 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC register. */
1855 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_RESET 0x00000000
1856 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_USB1_ECC register from the beginning of the component. */
1857 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_OFST 0x48
1858 
1859 /*
1860  * Register : clock_manager
1861  *
1862  * Per-Master Security bit for clock_manager
1863  *
1864  * Register Layout
1865  *
1866  * Bits | Access | Reset | Description
1867  * :--------|:-------|:--------|:---------------------------------------------
1868  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU
1869  * [15:1] | ??? | Unknown | *UNDEFINED*
1870  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC
1871  * [23:17] | ??? | Unknown | *UNDEFINED*
1872  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP
1873  * [31:25] | ??? | Unknown | *UNDEFINED*
1874  *
1875  */
1876 /*
1877  * Field : mpu
1878  *
1879  * Security bit configuration for transactions from mpu to clock_manager. When
1880  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1881  * Non-Secure transactions are allowed.
1882  *
1883  * Field Access Macros:
1884  *
1885  */
1886 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU register field. */
1887 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_LSB 0
1888 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU register field. */
1889 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_MSB 0
1890 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU register field. */
1891 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_WIDTH 1
1892 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU register field value. */
1893 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_SET_MSK 0x00000001
1894 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU register field value. */
1895 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_CLR_MSK 0xfffffffe
1896 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU register field. */
1897 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_RESET 0x0
1898 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU field value from a register. */
1899 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_GET(value) (((value) & 0x00000001) >> 0)
1900 /* Produces a ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU register field value suitable for setting the register. */
1901 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_SET(value) (((value) << 0) & 0x00000001)
1902 
1903 /*
1904  * Field : fpga2soc
1905  *
1906  * Security bit configuration for transactions from fpga2soc to clock_manager. When
1907  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1908  * Non-Secure transactions are allowed.
1909  *
1910  * Field Access Macros:
1911  *
1912  */
1913 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC register field. */
1914 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_LSB 16
1915 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC register field. */
1916 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_MSB 16
1917 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC register field. */
1918 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_WIDTH 1
1919 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC register field value. */
1920 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_SET_MSK 0x00010000
1921 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC register field value. */
1922 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_CLR_MSK 0xfffeffff
1923 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC register field. */
1924 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_RESET 0x0
1925 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC field value from a register. */
1926 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1927 /* Produces a ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC register field value suitable for setting the register. */
1928 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1929 
1930 /*
1931  * Field : axi_ap
1932  *
1933  * Security bit configuration for transactions from axi_ap to clock_manager. When
1934  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
1935  * Non-Secure transactions are allowed.
1936  *
1937  * Field Access Macros:
1938  *
1939  */
1940 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP register field. */
1941 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_LSB 24
1942 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP register field. */
1943 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_MSB 24
1944 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP register field. */
1945 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_WIDTH 1
1946 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP register field value. */
1947 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_SET_MSK 0x01000000
1948 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP register field value. */
1949 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_CLR_MSK 0xfeffffff
1950 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP register field. */
1951 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_RESET 0x0
1952 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP field value from a register. */
1953 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1954 /* Produces a ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP register field value suitable for setting the register. */
1955 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1956 
1957 #ifndef __ASSEMBLY__
1958 /*
1959  * WARNING: The C register and register group struct declarations are provided for
1960  * convenience and illustrative purposes. They should, however, be used with
1961  * caution as the C language standard provides no guarantees about the alignment or
1962  * atomicity of device memory accesses. The recommended practice for coding device
1963  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1964  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1965  * alt_write_dword() functions for 64 bit registers.
1966  *
1967  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER.
1968  */
1969 struct ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_s
1970 {
1971  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU */
1972  uint32_t : 15; /* *UNDEFINED* */
1973  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC */
1974  uint32_t : 7; /* *UNDEFINED* */
1975  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP */
1976  uint32_t : 7; /* *UNDEFINED* */
1977 };
1978 
1979 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER. */
1980 typedef struct ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_t;
1981 #endif /* __ASSEMBLY__ */
1982 
1983 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER register. */
1984 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_RESET 0x00000000
1985 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER register from the beginning of the component. */
1986 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_OFST 0x4c
1987 
1988 /*
1989  * Register : io_manager
1990  *
1991  * Per-Master Security bit for pin_mux_register
1992  *
1993  * Register Layout
1994  *
1995  * Bits | Access | Reset | Description
1996  * :--------|:-------|:--------|:------------------------------------------
1997  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU
1998  * [15:1] | ??? | Unknown | *UNDEFINED*
1999  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC
2000  * [23:17] | ??? | Unknown | *UNDEFINED*
2001  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP
2002  * [31:25] | ??? | Unknown | *UNDEFINED*
2003  *
2004  */
2005 /*
2006  * Field : mpu
2007  *
2008  * Security bit configuration for transactions from mpu to pin_mux_register. When
2009  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2010  * Non-Secure transactions are allowed.
2011  *
2012  * Field Access Macros:
2013  *
2014  */
2015 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU register field. */
2016 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_LSB 0
2017 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU register field. */
2018 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_MSB 0
2019 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU register field. */
2020 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_WIDTH 1
2021 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU register field value. */
2022 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_SET_MSK 0x00000001
2023 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU register field value. */
2024 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_CLR_MSK 0xfffffffe
2025 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU register field. */
2026 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_RESET 0x0
2027 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU field value from a register. */
2028 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_GET(value) (((value) & 0x00000001) >> 0)
2029 /* Produces a ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU register field value suitable for setting the register. */
2030 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_SET(value) (((value) << 0) & 0x00000001)
2031 
2032 /*
2033  * Field : fpga2soc
2034  *
2035  * Security bit configuration for transactions from fpga2soc to pin_mux_register.
2036  * When cleared (0), only Secure transactions are allowed. When set (1), both
2037  * Secure and Non-Secure transactions are allowed.
2038  *
2039  * Field Access Macros:
2040  *
2041  */
2042 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC register field. */
2043 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_LSB 16
2044 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC register field. */
2045 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_MSB 16
2046 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC register field. */
2047 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_WIDTH 1
2048 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC register field value. */
2049 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_SET_MSK 0x00010000
2050 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC register field value. */
2051 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_CLR_MSK 0xfffeffff
2052 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC register field. */
2053 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_RESET 0x0
2054 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC field value from a register. */
2055 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2056 /* Produces a ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC register field value suitable for setting the register. */
2057 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2058 
2059 /*
2060  * Field : axi_ap
2061  *
2062  * Security bit configuration for transactions from axi_ap to pin_mux_register.
2063  * When cleared (0), only Secure transactions are allowed. When set (1), both
2064  * Secure and Non-Secure transactions are allowed.
2065  *
2066  * Field Access Macros:
2067  *
2068  */
2069 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP register field. */
2070 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_LSB 24
2071 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP register field. */
2072 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_MSB 24
2073 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP register field. */
2074 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_WIDTH 1
2075 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP register field value. */
2076 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_SET_MSK 0x01000000
2077 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP register field value. */
2078 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_CLR_MSK 0xfeffffff
2079 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP register field. */
2080 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_RESET 0x0
2081 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP field value from a register. */
2082 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2083 /* Produces a ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP register field value suitable for setting the register. */
2084 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2085 
2086 #ifndef __ASSEMBLY__
2087 /*
2088  * WARNING: The C register and register group struct declarations are provided for
2089  * convenience and illustrative purposes. They should, however, be used with
2090  * caution as the C language standard provides no guarantees about the alignment or
2091  * atomicity of device memory accesses. The recommended practice for coding device
2092  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2093  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2094  * alt_write_dword() functions for 64 bit registers.
2095  *
2096  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER.
2097  */
2098 struct ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_s
2099 {
2100  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU */
2101  uint32_t : 15; /* *UNDEFINED* */
2102  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC */
2103  uint32_t : 7; /* *UNDEFINED* */
2104  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP */
2105  uint32_t : 7; /* *UNDEFINED* */
2106 };
2107 
2108 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER. */
2109 typedef struct ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_t;
2110 #endif /* __ASSEMBLY__ */
2111 
2112 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER register. */
2113 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_RESET 0x00000000
2114 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER register from the beginning of the component. */
2115 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_OFST 0x54
2116 
2117 /*
2118  * Register : reset_manager
2119  *
2120  * Per-Master Security bit for reset_manager
2121  *
2122  * Register Layout
2123  *
2124  * Bits | Access | Reset | Description
2125  * :--------|:-------|:--------|:---------------------------------------------
2126  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU
2127  * [15:1] | ??? | Unknown | *UNDEFINED*
2128  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC
2129  * [23:17] | ??? | Unknown | *UNDEFINED*
2130  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP
2131  * [31:25] | ??? | Unknown | *UNDEFINED*
2132  *
2133  */
2134 /*
2135  * Field : mpu
2136  *
2137  * Security bit configuration for transactions from mpu to reset_manager. When
2138  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2139  * Non-Secure transactions are allowed.
2140  *
2141  * Field Access Macros:
2142  *
2143  */
2144 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU register field. */
2145 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_LSB 0
2146 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU register field. */
2147 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_MSB 0
2148 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU register field. */
2149 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_WIDTH 1
2150 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU register field value. */
2151 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_SET_MSK 0x00000001
2152 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU register field value. */
2153 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_CLR_MSK 0xfffffffe
2154 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU register field. */
2155 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_RESET 0x0
2156 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU field value from a register. */
2157 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_GET(value) (((value) & 0x00000001) >> 0)
2158 /* Produces a ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU register field value suitable for setting the register. */
2159 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_SET(value) (((value) << 0) & 0x00000001)
2160 
2161 /*
2162  * Field : fpga2soc
2163  *
2164  * Security bit configuration for transactions from fpga2soc to reset_manager. When
2165  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2166  * Non-Secure transactions are allowed.
2167  *
2168  * Field Access Macros:
2169  *
2170  */
2171 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC register field. */
2172 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_LSB 16
2173 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC register field. */
2174 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_MSB 16
2175 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC register field. */
2176 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_WIDTH 1
2177 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC register field value. */
2178 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_SET_MSK 0x00010000
2179 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC register field value. */
2180 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_CLR_MSK 0xfffeffff
2181 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC register field. */
2182 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_RESET 0x0
2183 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC field value from a register. */
2184 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2185 /* Produces a ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC register field value suitable for setting the register. */
2186 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2187 
2188 /*
2189  * Field : axi_ap
2190  *
2191  * Security bit configuration for transactions from axi_ap to reset_manager. When
2192  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2193  * Non-Secure transactions are allowed.
2194  *
2195  * Field Access Macros:
2196  *
2197  */
2198 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP register field. */
2199 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_LSB 24
2200 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP register field. */
2201 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_MSB 24
2202 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP register field. */
2203 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_WIDTH 1
2204 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP register field value. */
2205 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_SET_MSK 0x01000000
2206 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP register field value. */
2207 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_CLR_MSK 0xfeffffff
2208 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP register field. */
2209 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_RESET 0x0
2210 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP field value from a register. */
2211 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2212 /* Produces a ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP register field value suitable for setting the register. */
2213 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2214 
2215 #ifndef __ASSEMBLY__
2216 /*
2217  * WARNING: The C register and register group struct declarations are provided for
2218  * convenience and illustrative purposes. They should, however, be used with
2219  * caution as the C language standard provides no guarantees about the alignment or
2220  * atomicity of device memory accesses. The recommended practice for coding device
2221  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2222  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2223  * alt_write_dword() functions for 64 bit registers.
2224  *
2225  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER.
2226  */
2227 struct ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_s
2228 {
2229  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU */
2230  uint32_t : 15; /* *UNDEFINED* */
2231  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC */
2232  uint32_t : 7; /* *UNDEFINED* */
2233  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP */
2234  uint32_t : 7; /* *UNDEFINED* */
2235 };
2236 
2237 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER. */
2238 typedef struct ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_t;
2239 #endif /* __ASSEMBLY__ */
2240 
2241 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER register. */
2242 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_RESET 0x00000000
2243 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER register from the beginning of the component. */
2244 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_OFST 0x58
2245 
2246 /*
2247  * Register : system_manager
2248  *
2249  * Per-Master Security bit for system_manager
2250  *
2251  * Register Layout
2252  *
2253  * Bits | Access | Reset | Description
2254  * :--------|:-------|:--------|:----------------------------------------------
2255  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU
2256  * [15:1] | ??? | Unknown | *UNDEFINED*
2257  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC
2258  * [23:17] | ??? | Unknown | *UNDEFINED*
2259  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP
2260  * [31:25] | ??? | Unknown | *UNDEFINED*
2261  *
2262  */
2263 /*
2264  * Field : mpu
2265  *
2266  * Security bit configuration for transactions from mpu to system_manager. When
2267  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2268  * Non-Secure transactions are allowed.
2269  *
2270  * Field Access Macros:
2271  *
2272  */
2273 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU register field. */
2274 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_LSB 0
2275 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU register field. */
2276 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_MSB 0
2277 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU register field. */
2278 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_WIDTH 1
2279 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU register field value. */
2280 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_SET_MSK 0x00000001
2281 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU register field value. */
2282 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_CLR_MSK 0xfffffffe
2283 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU register field. */
2284 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_RESET 0x0
2285 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU field value from a register. */
2286 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_GET(value) (((value) & 0x00000001) >> 0)
2287 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU register field value suitable for setting the register. */
2288 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_SET(value) (((value) << 0) & 0x00000001)
2289 
2290 /*
2291  * Field : fpga2soc
2292  *
2293  * Security bit configuration for transactions from fpga2soc to system_manager.
2294  * When cleared (0), only Secure transactions are allowed. When set (1), both
2295  * Secure and Non-Secure transactions are allowed.
2296  *
2297  * Field Access Macros:
2298  *
2299  */
2300 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC register field. */
2301 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_LSB 16
2302 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC register field. */
2303 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_MSB 16
2304 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC register field. */
2305 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_WIDTH 1
2306 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC register field value. */
2307 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_SET_MSK 0x00010000
2308 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC register field value. */
2309 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_CLR_MSK 0xfffeffff
2310 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC register field. */
2311 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_RESET 0x0
2312 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC field value from a register. */
2313 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2314 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC register field value suitable for setting the register. */
2315 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2316 
2317 /*
2318  * Field : axi_ap
2319  *
2320  * Security bit configuration for transactions from axi_ap to system_manager. When
2321  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2322  * Non-Secure transactions are allowed.
2323  *
2324  * Field Access Macros:
2325  *
2326  */
2327 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP register field. */
2328 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_LSB 24
2329 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP register field. */
2330 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_MSB 24
2331 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP register field. */
2332 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_WIDTH 1
2333 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP register field value. */
2334 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_SET_MSK 0x01000000
2335 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP register field value. */
2336 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_CLR_MSK 0xfeffffff
2337 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP register field. */
2338 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_RESET 0x0
2339 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP field value from a register. */
2340 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2341 /* Produces a ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP register field value suitable for setting the register. */
2342 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2343 
2344 #ifndef __ASSEMBLY__
2345 /*
2346  * WARNING: The C register and register group struct declarations are provided for
2347  * convenience and illustrative purposes. They should, however, be used with
2348  * caution as the C language standard provides no guarantees about the alignment or
2349  * atomicity of device memory accesses. The recommended practice for coding device
2350  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2351  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2352  * alt_write_dword() functions for 64 bit registers.
2353  *
2354  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER.
2355  */
2356 struct ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_s
2357 {
2358  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU */
2359  uint32_t : 15; /* *UNDEFINED* */
2360  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC */
2361  uint32_t : 7; /* *UNDEFINED* */
2362  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP */
2363  uint32_t : 7; /* *UNDEFINED* */
2364 };
2365 
2366 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER. */
2367 typedef struct ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_t;
2368 #endif /* __ASSEMBLY__ */
2369 
2370 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER register. */
2371 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_RESET 0x00000000
2372 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER register from the beginning of the component. */
2373 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_OFST 0x5c
2374 
2375 /*
2376  * Register : osc0_timer
2377  *
2378  * Per-Master Security bit for osc0_timer
2379  *
2380  * Register Layout
2381  *
2382  * Bits | Access | Reset | Description
2383  * :--------|:-------|:--------|:------------------------------------------
2384  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU
2385  * [7:1] | ??? | Unknown | *UNDEFINED*
2386  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA
2387  * [15:9] | ??? | Unknown | *UNDEFINED*
2388  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC
2389  * [23:17] | ??? | Unknown | *UNDEFINED*
2390  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP
2391  * [31:25] | ??? | Unknown | *UNDEFINED*
2392  *
2393  */
2394 /*
2395  * Field : mpu
2396  *
2397  * Security bit configuration for transactions from mpu to osc0_timer. When cleared
2398  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2399  * Secure transactions are allowed.
2400  *
2401  * Field Access Macros:
2402  *
2403  */
2404 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU register field. */
2405 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_LSB 0
2406 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU register field. */
2407 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_MSB 0
2408 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU register field. */
2409 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_WIDTH 1
2410 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU register field value. */
2411 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_SET_MSK 0x00000001
2412 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU register field value. */
2413 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_CLR_MSK 0xfffffffe
2414 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU register field. */
2415 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_RESET 0x0
2416 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU field value from a register. */
2417 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_GET(value) (((value) & 0x00000001) >> 0)
2418 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU register field value suitable for setting the register. */
2419 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_SET(value) (((value) << 0) & 0x00000001)
2420 
2421 /*
2422  * Field : dma
2423  *
2424  * Security bit configuration for transactions from dma to osc0_timer. When cleared
2425  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2426  * Secure transactions are allowed.
2427  *
2428  * Field Access Macros:
2429  *
2430  */
2431 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA register field. */
2432 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_LSB 8
2433 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA register field. */
2434 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_MSB 8
2435 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA register field. */
2436 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_WIDTH 1
2437 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA register field value. */
2438 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_SET_MSK 0x00000100
2439 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA register field value. */
2440 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_CLR_MSK 0xfffffeff
2441 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA register field. */
2442 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_RESET 0x0
2443 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA field value from a register. */
2444 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_GET(value) (((value) & 0x00000100) >> 8)
2445 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA register field value suitable for setting the register. */
2446 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_SET(value) (((value) << 8) & 0x00000100)
2447 
2448 /*
2449  * Field : fpga2soc
2450  *
2451  * Security bit configuration for transactions from fpga2soc to osc0_timer. When
2452  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2453  * Non-Secure transactions are allowed.
2454  *
2455  * Field Access Macros:
2456  *
2457  */
2458 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC register field. */
2459 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_LSB 16
2460 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC register field. */
2461 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_MSB 16
2462 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC register field. */
2463 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_WIDTH 1
2464 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC register field value. */
2465 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_SET_MSK 0x00010000
2466 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC register field value. */
2467 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_CLR_MSK 0xfffeffff
2468 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC register field. */
2469 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_RESET 0x0
2470 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC field value from a register. */
2471 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2472 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC register field value suitable for setting the register. */
2473 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2474 
2475 /*
2476  * Field : axi_ap
2477  *
2478  * Security bit configuration for transactions from axi_ap to osc0_timer. When
2479  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2480  * Non-Secure transactions are allowed.
2481  *
2482  * Field Access Macros:
2483  *
2484  */
2485 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP register field. */
2486 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_LSB 24
2487 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP register field. */
2488 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_MSB 24
2489 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP register field. */
2490 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_WIDTH 1
2491 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP register field value. */
2492 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_SET_MSK 0x01000000
2493 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP register field value. */
2494 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_CLR_MSK 0xfeffffff
2495 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP register field. */
2496 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_RESET 0x0
2497 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP field value from a register. */
2498 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2499 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP register field value suitable for setting the register. */
2500 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2501 
2502 #ifndef __ASSEMBLY__
2503 /*
2504  * WARNING: The C register and register group struct declarations are provided for
2505  * convenience and illustrative purposes. They should, however, be used with
2506  * caution as the C language standard provides no guarantees about the alignment or
2507  * atomicity of device memory accesses. The recommended practice for coding device
2508  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2509  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2510  * alt_write_dword() functions for 64 bit registers.
2511  *
2512  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER.
2513  */
2514 struct ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_s
2515 {
2516  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU */
2517  uint32_t : 7; /* *UNDEFINED* */
2518  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA */
2519  uint32_t : 7; /* *UNDEFINED* */
2520  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC */
2521  uint32_t : 7; /* *UNDEFINED* */
2522  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP */
2523  uint32_t : 7; /* *UNDEFINED* */
2524 };
2525 
2526 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER. */
2527 typedef struct ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_s ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_t;
2528 #endif /* __ASSEMBLY__ */
2529 
2530 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER register. */
2531 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_RESET 0x00000000
2532 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER register from the beginning of the component. */
2533 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_OFST 0x60
2534 
2535 /*
2536  * Register : osc1_timer
2537  *
2538  * Per-Master Security bit for osc1_timer
2539  *
2540  * Register Layout
2541  *
2542  * Bits | Access | Reset | Description
2543  * :--------|:-------|:--------|:------------------------------------------
2544  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU
2545  * [7:1] | ??? | Unknown | *UNDEFINED*
2546  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA
2547  * [15:9] | ??? | Unknown | *UNDEFINED*
2548  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC
2549  * [23:17] | ??? | Unknown | *UNDEFINED*
2550  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP
2551  * [31:25] | ??? | Unknown | *UNDEFINED*
2552  *
2553  */
2554 /*
2555  * Field : mpu
2556  *
2557  * Security bit configuration for transactions from mpu to osc1_timer. When cleared
2558  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2559  * Secure transactions are allowed.
2560  *
2561  * Field Access Macros:
2562  *
2563  */
2564 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU register field. */
2565 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_LSB 0
2566 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU register field. */
2567 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_MSB 0
2568 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU register field. */
2569 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_WIDTH 1
2570 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU register field value. */
2571 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_SET_MSK 0x00000001
2572 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU register field value. */
2573 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_CLR_MSK 0xfffffffe
2574 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU register field. */
2575 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_RESET 0x0
2576 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU field value from a register. */
2577 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_GET(value) (((value) & 0x00000001) >> 0)
2578 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU register field value suitable for setting the register. */
2579 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_SET(value) (((value) << 0) & 0x00000001)
2580 
2581 /*
2582  * Field : dma
2583  *
2584  * Security bit configuration for transactions from dma to osc1_timer. When cleared
2585  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2586  * Secure transactions are allowed.
2587  *
2588  * Field Access Macros:
2589  *
2590  */
2591 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA register field. */
2592 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_LSB 8
2593 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA register field. */
2594 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_MSB 8
2595 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA register field. */
2596 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_WIDTH 1
2597 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA register field value. */
2598 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_SET_MSK 0x00000100
2599 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA register field value. */
2600 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_CLR_MSK 0xfffffeff
2601 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA register field. */
2602 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_RESET 0x0
2603 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA field value from a register. */
2604 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_GET(value) (((value) & 0x00000100) >> 8)
2605 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA register field value suitable for setting the register. */
2606 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_SET(value) (((value) << 8) & 0x00000100)
2607 
2608 /*
2609  * Field : fpga2soc
2610  *
2611  * Security bit configuration for transactions from fpga2soc to osc1_timer. When
2612  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2613  * Non-Secure transactions are allowed.
2614  *
2615  * Field Access Macros:
2616  *
2617  */
2618 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC register field. */
2619 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_LSB 16
2620 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC register field. */
2621 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_MSB 16
2622 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC register field. */
2623 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_WIDTH 1
2624 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC register field value. */
2625 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_SET_MSK 0x00010000
2626 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC register field value. */
2627 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_CLR_MSK 0xfffeffff
2628 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC register field. */
2629 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_RESET 0x0
2630 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC field value from a register. */
2631 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2632 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC register field value suitable for setting the register. */
2633 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2634 
2635 /*
2636  * Field : axi_ap
2637  *
2638  * Security bit configuration for transactions from axi_ap to osc1_timer. When
2639  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2640  * Non-Secure transactions are allowed.
2641  *
2642  * Field Access Macros:
2643  *
2644  */
2645 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP register field. */
2646 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_LSB 24
2647 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP register field. */
2648 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_MSB 24
2649 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP register field. */
2650 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_WIDTH 1
2651 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP register field value. */
2652 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_SET_MSK 0x01000000
2653 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP register field value. */
2654 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_CLR_MSK 0xfeffffff
2655 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP register field. */
2656 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_RESET 0x0
2657 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP field value from a register. */
2658 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2659 /* Produces a ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP register field value suitable for setting the register. */
2660 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2661 
2662 #ifndef __ASSEMBLY__
2663 /*
2664  * WARNING: The C register and register group struct declarations are provided for
2665  * convenience and illustrative purposes. They should, however, be used with
2666  * caution as the C language standard provides no guarantees about the alignment or
2667  * atomicity of device memory accesses. The recommended practice for coding device
2668  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2669  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2670  * alt_write_dword() functions for 64 bit registers.
2671  *
2672  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER.
2673  */
2674 struct ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_s
2675 {
2676  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU */
2677  uint32_t : 7; /* *UNDEFINED* */
2678  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA */
2679  uint32_t : 7; /* *UNDEFINED* */
2680  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC */
2681  uint32_t : 7; /* *UNDEFINED* */
2682  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP */
2683  uint32_t : 7; /* *UNDEFINED* */
2684 };
2685 
2686 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER. */
2687 typedef struct ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_s ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_t;
2688 #endif /* __ASSEMBLY__ */
2689 
2690 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER register. */
2691 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_RESET 0x00000000
2692 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER register from the beginning of the component. */
2693 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_OFST 0x64
2694 
2695 /*
2696  * Register : watchdog0
2697  *
2698  * Per-Master Security bit for watchdog0
2699  *
2700  * Register Layout
2701  *
2702  * Bits | Access | Reset | Description
2703  * :--------|:-------|:--------|:-----------------------------------------
2704  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU
2705  * [7:1] | ??? | Unknown | *UNDEFINED*
2706  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA
2707  * [15:9] | ??? | Unknown | *UNDEFINED*
2708  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC
2709  * [23:17] | ??? | Unknown | *UNDEFINED*
2710  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP
2711  * [31:25] | ??? | Unknown | *UNDEFINED*
2712  *
2713  */
2714 /*
2715  * Field : mpu
2716  *
2717  * Security bit configuration for transactions from mpu to watchdog0. When cleared
2718  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2719  * Secure transactions are allowed.
2720  *
2721  * Field Access Macros:
2722  *
2723  */
2724 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU register field. */
2725 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_LSB 0
2726 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU register field. */
2727 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_MSB 0
2728 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU register field. */
2729 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_WIDTH 1
2730 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU register field value. */
2731 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_SET_MSK 0x00000001
2732 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU register field value. */
2733 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_CLR_MSK 0xfffffffe
2734 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU register field. */
2735 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_RESET 0x0
2736 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU field value from a register. */
2737 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_GET(value) (((value) & 0x00000001) >> 0)
2738 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU register field value suitable for setting the register. */
2739 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_SET(value) (((value) << 0) & 0x00000001)
2740 
2741 /*
2742  * Field : dma
2743  *
2744  * Security bit configuration for transactions from dma to watchdog0. When cleared
2745  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2746  * Secure transactions are allowed.
2747  *
2748  * Field Access Macros:
2749  *
2750  */
2751 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA register field. */
2752 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_LSB 8
2753 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA register field. */
2754 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_MSB 8
2755 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA register field. */
2756 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_WIDTH 1
2757 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA register field value. */
2758 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_SET_MSK 0x00000100
2759 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA register field value. */
2760 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_CLR_MSK 0xfffffeff
2761 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA register field. */
2762 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_RESET 0x0
2763 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA field value from a register. */
2764 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_GET(value) (((value) & 0x00000100) >> 8)
2765 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA register field value suitable for setting the register. */
2766 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_SET(value) (((value) << 8) & 0x00000100)
2767 
2768 /*
2769  * Field : fpga2soc
2770  *
2771  * Security bit configuration for transactions from fpga2soc to watchdog0. When
2772  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2773  * Non-Secure transactions are allowed.
2774  *
2775  * Field Access Macros:
2776  *
2777  */
2778 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC register field. */
2779 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_LSB 16
2780 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC register field. */
2781 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_MSB 16
2782 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC register field. */
2783 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_WIDTH 1
2784 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC register field value. */
2785 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_SET_MSK 0x00010000
2786 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC register field value. */
2787 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_CLR_MSK 0xfffeffff
2788 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC register field. */
2789 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_RESET 0x0
2790 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC field value from a register. */
2791 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2792 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC register field value suitable for setting the register. */
2793 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2794 
2795 /*
2796  * Field : axi_ap
2797  *
2798  * Security bit configuration for transactions from axi_ap to watchdog0. When
2799  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2800  * Non-Secure transactions are allowed.
2801  *
2802  * Field Access Macros:
2803  *
2804  */
2805 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP register field. */
2806 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_LSB 24
2807 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP register field. */
2808 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_MSB 24
2809 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP register field. */
2810 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_WIDTH 1
2811 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP register field value. */
2812 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_SET_MSK 0x01000000
2813 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP register field value. */
2814 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_CLR_MSK 0xfeffffff
2815 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP register field. */
2816 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_RESET 0x0
2817 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP field value from a register. */
2818 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2819 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP register field value suitable for setting the register. */
2820 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2821 
2822 #ifndef __ASSEMBLY__
2823 /*
2824  * WARNING: The C register and register group struct declarations are provided for
2825  * convenience and illustrative purposes. They should, however, be used with
2826  * caution as the C language standard provides no guarantees about the alignment or
2827  * atomicity of device memory accesses. The recommended practice for coding device
2828  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2829  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2830  * alt_write_dword() functions for 64 bit registers.
2831  *
2832  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0.
2833  */
2834 struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_s
2835 {
2836  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU */
2837  uint32_t : 7; /* *UNDEFINED* */
2838  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA */
2839  uint32_t : 7; /* *UNDEFINED* */
2840  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC */
2841  uint32_t : 7; /* *UNDEFINED* */
2842  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP */
2843  uint32_t : 7; /* *UNDEFINED* */
2844 };
2845 
2846 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0. */
2847 typedef struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_s ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_t;
2848 #endif /* __ASSEMBLY__ */
2849 
2850 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0 register. */
2851 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_RESET 0x00000000
2852 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0 register from the beginning of the component. */
2853 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_OFST 0x68
2854 
2855 /*
2856  * Register : watchdog1
2857  *
2858  * Per-Master Security bit for watchdog1
2859  *
2860  * Register Layout
2861  *
2862  * Bits | Access | Reset | Description
2863  * :--------|:-------|:--------|:-----------------------------------------
2864  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU
2865  * [7:1] | ??? | Unknown | *UNDEFINED*
2866  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA
2867  * [15:9] | ??? | Unknown | *UNDEFINED*
2868  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC
2869  * [23:17] | ??? | Unknown | *UNDEFINED*
2870  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP
2871  * [31:25] | ??? | Unknown | *UNDEFINED*
2872  *
2873  */
2874 /*
2875  * Field : mpu
2876  *
2877  * Security bit configuration for transactions from mpu to watchdog1. When cleared
2878  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2879  * Secure transactions are allowed.
2880  *
2881  * Field Access Macros:
2882  *
2883  */
2884 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU register field. */
2885 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_LSB 0
2886 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU register field. */
2887 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_MSB 0
2888 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU register field. */
2889 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_WIDTH 1
2890 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU register field value. */
2891 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_SET_MSK 0x00000001
2892 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU register field value. */
2893 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_CLR_MSK 0xfffffffe
2894 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU register field. */
2895 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_RESET 0x0
2896 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU field value from a register. */
2897 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_GET(value) (((value) & 0x00000001) >> 0)
2898 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU register field value suitable for setting the register. */
2899 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_SET(value) (((value) << 0) & 0x00000001)
2900 
2901 /*
2902  * Field : dma
2903  *
2904  * Security bit configuration for transactions from dma to watchdog1. When cleared
2905  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
2906  * Secure transactions are allowed.
2907  *
2908  * Field Access Macros:
2909  *
2910  */
2911 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA register field. */
2912 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_LSB 8
2913 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA register field. */
2914 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_MSB 8
2915 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA register field. */
2916 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_WIDTH 1
2917 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA register field value. */
2918 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_SET_MSK 0x00000100
2919 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA register field value. */
2920 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_CLR_MSK 0xfffffeff
2921 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA register field. */
2922 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_RESET 0x0
2923 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA field value from a register. */
2924 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_GET(value) (((value) & 0x00000100) >> 8)
2925 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA register field value suitable for setting the register. */
2926 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_SET(value) (((value) << 8) & 0x00000100)
2927 
2928 /*
2929  * Field : fpga2soc
2930  *
2931  * Security bit configuration for transactions from fpga2soc to watchdog1. When
2932  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2933  * Non-Secure transactions are allowed.
2934  *
2935  * Field Access Macros:
2936  *
2937  */
2938 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC register field. */
2939 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_LSB 16
2940 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC register field. */
2941 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_MSB 16
2942 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC register field. */
2943 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_WIDTH 1
2944 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC register field value. */
2945 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_SET_MSK 0x00010000
2946 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC register field value. */
2947 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_CLR_MSK 0xfffeffff
2948 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC register field. */
2949 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_RESET 0x0
2950 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC field value from a register. */
2951 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2952 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC register field value suitable for setting the register. */
2953 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2954 
2955 /*
2956  * Field : axi_ap
2957  *
2958  * Security bit configuration for transactions from axi_ap to watchdog1. When
2959  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
2960  * Non-Secure transactions are allowed.
2961  *
2962  * Field Access Macros:
2963  *
2964  */
2965 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP register field. */
2966 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_LSB 24
2967 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP register field. */
2968 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_MSB 24
2969 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP register field. */
2970 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_WIDTH 1
2971 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP register field value. */
2972 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_SET_MSK 0x01000000
2973 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP register field value. */
2974 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_CLR_MSK 0xfeffffff
2975 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP register field. */
2976 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_RESET 0x0
2977 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP field value from a register. */
2978 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2979 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP register field value suitable for setting the register. */
2980 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2981 
2982 #ifndef __ASSEMBLY__
2983 /*
2984  * WARNING: The C register and register group struct declarations are provided for
2985  * convenience and illustrative purposes. They should, however, be used with
2986  * caution as the C language standard provides no guarantees about the alignment or
2987  * atomicity of device memory accesses. The recommended practice for coding device
2988  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2989  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2990  * alt_write_dword() functions for 64 bit registers.
2991  *
2992  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1.
2993  */
2994 struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_s
2995 {
2996  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU */
2997  uint32_t : 7; /* *UNDEFINED* */
2998  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA */
2999  uint32_t : 7; /* *UNDEFINED* */
3000  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC */
3001  uint32_t : 7; /* *UNDEFINED* */
3002  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP */
3003  uint32_t : 7; /* *UNDEFINED* */
3004 };
3005 
3006 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1. */
3007 typedef struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_s ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_t;
3008 #endif /* __ASSEMBLY__ */
3009 
3010 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1 register. */
3011 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_RESET 0x00000000
3012 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1 register from the beginning of the component. */
3013 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_OFST 0x6c
3014 
3015 /*
3016  * Register : watchdog2
3017  *
3018  * Per-Master Security bit for watchdog0
3019  *
3020  * Register Layout
3021  *
3022  * Bits | Access | Reset | Description
3023  * :--------|:-------|:--------|:-----------------------------------------
3024  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU
3025  * [7:1] | ??? | Unknown | *UNDEFINED*
3026  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA
3027  * [15:9] | ??? | Unknown | *UNDEFINED*
3028  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC
3029  * [23:17] | ??? | Unknown | *UNDEFINED*
3030  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP
3031  * [31:25] | ??? | Unknown | *UNDEFINED*
3032  *
3033  */
3034 /*
3035  * Field : mpu
3036  *
3037  * Security bit configuration for transactions from mpu to watchdog2. When cleared
3038  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3039  * Secure transactions are allowed.
3040  *
3041  * Field Access Macros:
3042  *
3043  */
3044 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU register field. */
3045 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_LSB 0
3046 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU register field. */
3047 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_MSB 0
3048 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU register field. */
3049 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_WIDTH 1
3050 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU register field value. */
3051 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_SET_MSK 0x00000001
3052 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU register field value. */
3053 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_CLR_MSK 0xfffffffe
3054 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU register field. */
3055 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_RESET 0x0
3056 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU field value from a register. */
3057 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_GET(value) (((value) & 0x00000001) >> 0)
3058 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU register field value suitable for setting the register. */
3059 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_SET(value) (((value) << 0) & 0x00000001)
3060 
3061 /*
3062  * Field : dma
3063  *
3064  * Security bit configuration for transactions from dma to watchdog2. When cleared
3065  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3066  * Secure transactions are allowed.
3067  *
3068  * Field Access Macros:
3069  *
3070  */
3071 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA register field. */
3072 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_LSB 8
3073 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA register field. */
3074 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_MSB 8
3075 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA register field. */
3076 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_WIDTH 1
3077 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA register field value. */
3078 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_SET_MSK 0x00000100
3079 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA register field value. */
3080 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_CLR_MSK 0xfffffeff
3081 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA register field. */
3082 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_RESET 0x0
3083 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA field value from a register. */
3084 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_GET(value) (((value) & 0x00000100) >> 8)
3085 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA register field value suitable for setting the register. */
3086 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_SET(value) (((value) << 8) & 0x00000100)
3087 
3088 /*
3089  * Field : fpga2soc
3090  *
3091  * Security bit configuration for transactions from fpga2soc to watchdog2. When
3092  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3093  * Non-Secure transactions are allowed.
3094  *
3095  * Field Access Macros:
3096  *
3097  */
3098 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC register field. */
3099 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_LSB 16
3100 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC register field. */
3101 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_MSB 16
3102 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC register field. */
3103 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_WIDTH 1
3104 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC register field value. */
3105 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_SET_MSK 0x00010000
3106 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC register field value. */
3107 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_CLR_MSK 0xfffeffff
3108 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC register field. */
3109 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_RESET 0x0
3110 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC field value from a register. */
3111 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3112 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC register field value suitable for setting the register. */
3113 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3114 
3115 /*
3116  * Field : axi_ap
3117  *
3118  * Security bit configuration for transactions from axi_ap to watchdog2. When
3119  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3120  * Non-Secure transactions are allowed.
3121  *
3122  * Field Access Macros:
3123  *
3124  */
3125 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP register field. */
3126 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_LSB 24
3127 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP register field. */
3128 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_MSB 24
3129 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP register field. */
3130 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_WIDTH 1
3131 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP register field value. */
3132 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_SET_MSK 0x01000000
3133 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP register field value. */
3134 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_CLR_MSK 0xfeffffff
3135 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP register field. */
3136 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_RESET 0x0
3137 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP field value from a register. */
3138 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3139 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP register field value suitable for setting the register. */
3140 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3141 
3142 #ifndef __ASSEMBLY__
3143 /*
3144  * WARNING: The C register and register group struct declarations are provided for
3145  * convenience and illustrative purposes. They should, however, be used with
3146  * caution as the C language standard provides no guarantees about the alignment or
3147  * atomicity of device memory accesses. The recommended practice for coding device
3148  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3149  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3150  * alt_write_dword() functions for 64 bit registers.
3151  *
3152  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2.
3153  */
3154 struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_s
3155 {
3156  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU */
3157  uint32_t : 7; /* *UNDEFINED* */
3158  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA */
3159  uint32_t : 7; /* *UNDEFINED* */
3160  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC */
3161  uint32_t : 7; /* *UNDEFINED* */
3162  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP */
3163  uint32_t : 7; /* *UNDEFINED* */
3164 };
3165 
3166 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2. */
3167 typedef struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_s ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_t;
3168 #endif /* __ASSEMBLY__ */
3169 
3170 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2 register. */
3171 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_RESET 0x00000000
3172 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2 register from the beginning of the component. */
3173 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_OFST 0x70
3174 
3175 /*
3176  * Register : watchdog3
3177  *
3178  * Per-Master Security bit for watchdog1
3179  *
3180  * Register Layout
3181  *
3182  * Bits | Access | Reset | Description
3183  * :--------|:-------|:--------|:-----------------------------------------
3184  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU
3185  * [7:1] | ??? | Unknown | *UNDEFINED*
3186  * [8] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA
3187  * [15:9] | ??? | Unknown | *UNDEFINED*
3188  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC
3189  * [23:17] | ??? | Unknown | *UNDEFINED*
3190  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP
3191  * [31:25] | ??? | Unknown | *UNDEFINED*
3192  *
3193  */
3194 /*
3195  * Field : mpu
3196  *
3197  * Security bit configuration for transactions from mpu to watchdog3. When cleared
3198  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3199  * Secure transactions are allowed.
3200  *
3201  * Field Access Macros:
3202  *
3203  */
3204 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU register field. */
3205 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_LSB 0
3206 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU register field. */
3207 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_MSB 0
3208 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU register field. */
3209 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_WIDTH 1
3210 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU register field value. */
3211 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_SET_MSK 0x00000001
3212 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU register field value. */
3213 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_CLR_MSK 0xfffffffe
3214 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU register field. */
3215 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_RESET 0x0
3216 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU field value from a register. */
3217 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_GET(value) (((value) & 0x00000001) >> 0)
3218 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU register field value suitable for setting the register. */
3219 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_SET(value) (((value) << 0) & 0x00000001)
3220 
3221 /*
3222  * Field : dma
3223  *
3224  * Security bit configuration for transactions from dma to watchdog3. When cleared
3225  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3226  * Secure transactions are allowed.
3227  *
3228  * Field Access Macros:
3229  *
3230  */
3231 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA register field. */
3232 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_LSB 8
3233 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA register field. */
3234 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_MSB 8
3235 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA register field. */
3236 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_WIDTH 1
3237 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA register field value. */
3238 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_SET_MSK 0x00000100
3239 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA register field value. */
3240 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_CLR_MSK 0xfffffeff
3241 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA register field. */
3242 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_RESET 0x0
3243 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA field value from a register. */
3244 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_GET(value) (((value) & 0x00000100) >> 8)
3245 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA register field value suitable for setting the register. */
3246 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_SET(value) (((value) << 8) & 0x00000100)
3247 
3248 /*
3249  * Field : fpga2soc
3250  *
3251  * Security bit configuration for transactions from fpga2soc to watchdog3. When
3252  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3253  * Non-Secure transactions are allowed.
3254  *
3255  * Field Access Macros:
3256  *
3257  */
3258 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC register field. */
3259 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_LSB 16
3260 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC register field. */
3261 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_MSB 16
3262 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC register field. */
3263 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_WIDTH 1
3264 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC register field value. */
3265 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_SET_MSK 0x00010000
3266 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC register field value. */
3267 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_CLR_MSK 0xfffeffff
3268 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC register field. */
3269 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_RESET 0x0
3270 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC field value from a register. */
3271 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3272 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC register field value suitable for setting the register. */
3273 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3274 
3275 /*
3276  * Field : axi_ap
3277  *
3278  * Security bit configuration for transactions from axi_ap to watchdog3. When
3279  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
3280  * Non-Secure transactions are allowed.
3281  *
3282  * Field Access Macros:
3283  *
3284  */
3285 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP register field. */
3286 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_LSB 24
3287 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP register field. */
3288 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_MSB 24
3289 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP register field. */
3290 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_WIDTH 1
3291 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP register field value. */
3292 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_SET_MSK 0x01000000
3293 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP register field value. */
3294 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_CLR_MSK 0xfeffffff
3295 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP register field. */
3296 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_RESET 0x0
3297 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP field value from a register. */
3298 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3299 /* Produces a ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP register field value suitable for setting the register. */
3300 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3301 
3302 #ifndef __ASSEMBLY__
3303 /*
3304  * WARNING: The C register and register group struct declarations are provided for
3305  * convenience and illustrative purposes. They should, however, be used with
3306  * caution as the C language standard provides no guarantees about the alignment or
3307  * atomicity of device memory accesses. The recommended practice for coding device
3308  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3309  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3310  * alt_write_dword() functions for 64 bit registers.
3311  *
3312  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3.
3313  */
3314 struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_s
3315 {
3316  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU */
3317  uint32_t : 7; /* *UNDEFINED* */
3318  volatile uint32_t dma : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA */
3319  uint32_t : 7; /* *UNDEFINED* */
3320  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC */
3321  uint32_t : 7; /* *UNDEFINED* */
3322  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP */
3323  uint32_t : 7; /* *UNDEFINED* */
3324 };
3325 
3326 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3. */
3327 typedef struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_s ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_t;
3328 #endif /* __ASSEMBLY__ */
3329 
3330 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3 register. */
3331 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_RESET 0x00000000
3332 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3 register from the beginning of the component. */
3333 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_OFST 0x74
3334 
3335 /*
3336  * Register : dap
3337  *
3338  * Per-Master Security bit for dap
3339  *
3340  * Register Layout
3341  *
3342  * Bits | Access | Reset | Description
3343  * :--------|:-------|:--------|:-----------------------------------
3344  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DAP_MPU
3345  * [15:1] | ??? | Unknown | *UNDEFINED*
3346  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC
3347  * [23:17] | ??? | Unknown | *UNDEFINED*
3348  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP
3349  * [25] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_DAP_ETR
3350  * [31:26] | ??? | Unknown | *UNDEFINED*
3351  *
3352  */
3353 /*
3354  * Field : mpu
3355  *
3356  * Security bit configuration for transactions from mpu to dap. When cleared (0),
3357  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
3358  * transactions are allowed.
3359  *
3360  * Field Access Macros:
3361  *
3362  */
3363 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU register field. */
3364 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_LSB 0
3365 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU register field. */
3366 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_MSB 0
3367 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU register field. */
3368 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_WIDTH 1
3369 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU register field value. */
3370 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_SET_MSK 0x00000001
3371 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU register field value. */
3372 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_CLR_MSK 0xfffffffe
3373 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU register field. */
3374 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_RESET 0x0
3375 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DAP_MPU field value from a register. */
3376 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_GET(value) (((value) & 0x00000001) >> 0)
3377 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DAP_MPU register field value suitable for setting the register. */
3378 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_SET(value) (((value) << 0) & 0x00000001)
3379 
3380 /*
3381  * Field : fpga2soc
3382  *
3383  * Security bit configuration for transactions from fpga2soc to dap. When cleared
3384  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3385  * Secure transactions are allowed.
3386  *
3387  * Field Access Macros:
3388  *
3389  */
3390 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC register field. */
3391 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_LSB 16
3392 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC register field. */
3393 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_MSB 16
3394 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC register field. */
3395 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_WIDTH 1
3396 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC register field value. */
3397 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_SET_MSK 0x00010000
3398 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC register field value. */
3399 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_CLR_MSK 0xfffeffff
3400 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC register field. */
3401 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_RESET 0x0
3402 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC field value from a register. */
3403 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3404 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC register field value suitable for setting the register. */
3405 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3406 
3407 /*
3408  * Field : axi_ap
3409  *
3410  * Security bit configuration for transactions from axi_ap to dap. When cleared
3411  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
3412  * Secure transactions are allowed.
3413  *
3414  * Field Access Macros:
3415  *
3416  */
3417 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP register field. */
3418 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_LSB 24
3419 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP register field. */
3420 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_MSB 24
3421 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP register field. */
3422 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_WIDTH 1
3423 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP register field value. */
3424 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_SET_MSK 0x01000000
3425 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP register field value. */
3426 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_CLR_MSK 0xfeffffff
3427 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP register field. */
3428 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_RESET 0x0
3429 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP field value from a register. */
3430 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3431 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP register field value suitable for setting the register. */
3432 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3433 
3434 /*
3435  * Field : etr
3436  *
3437  * Security bit configuration for transactions from etr to dap. When cleared (0),
3438  * only Secure transactions are allowed. When set (1), both Secure and Non-Secure
3439  * transactions are allowed.
3440  *
3441  * Field Access Macros:
3442  *
3443  */
3444 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field. */
3445 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_LSB 25
3446 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field. */
3447 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_MSB 25
3448 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field. */
3449 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_WIDTH 1
3450 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field value. */
3451 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_SET_MSK 0x02000000
3452 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field value. */
3453 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_CLR_MSK 0xfdffffff
3454 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field. */
3455 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_RESET 0x0
3456 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_DAP_ETR field value from a register. */
3457 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_GET(value) (((value) & 0x02000000) >> 25)
3458 /* Produces a ALT_NOC_FW_L4_SYS_SCR_DAP_ETR register field value suitable for setting the register. */
3459 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_SET(value) (((value) << 25) & 0x02000000)
3460 
3461 #ifndef __ASSEMBLY__
3462 /*
3463  * WARNING: The C register and register group struct declarations are provided for
3464  * convenience and illustrative purposes. They should, however, be used with
3465  * caution as the C language standard provides no guarantees about the alignment or
3466  * atomicity of device memory accesses. The recommended practice for coding device
3467  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3468  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3469  * alt_write_dword() functions for 64 bit registers.
3470  *
3471  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_DAP.
3472  */
3473 struct ALT_NOC_FW_L4_SYS_SCR_DAP_s
3474 {
3475  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_DAP_MPU */
3476  uint32_t : 15; /* *UNDEFINED* */
3477  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC */
3478  uint32_t : 7; /* *UNDEFINED* */
3479  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP */
3480  volatile uint32_t etr : 1; /* ALT_NOC_FW_L4_SYS_SCR_DAP_ETR */
3481  uint32_t : 6; /* *UNDEFINED* */
3482 };
3483 
3484 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_DAP. */
3485 typedef struct ALT_NOC_FW_L4_SYS_SCR_DAP_s ALT_NOC_FW_L4_SYS_SCR_DAP_t;
3486 #endif /* __ASSEMBLY__ */
3487 
3488 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_DAP register. */
3489 #define ALT_NOC_FW_L4_SYS_SCR_DAP_RESET 0x00000000
3490 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_DAP register from the beginning of the component. */
3491 #define ALT_NOC_FW_L4_SYS_SCR_DAP_OFST 0x78
3492 
3493 /*
3494  * Register : l4_noc_probes
3495  *
3496  * Per-Master Security bit for noc_probes_register
3497  *
3498  * Register Layout
3499  *
3500  * Bits | Access | Reset | Description
3501  * :--------|:-------|:--------|:---------------------------------------------
3502  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU
3503  * [15:1] | ??? | Unknown | *UNDEFINED*
3504  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC
3505  * [23:17] | ??? | Unknown | *UNDEFINED*
3506  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP
3507  * [31:25] | ??? | Unknown | *UNDEFINED*
3508  *
3509  */
3510 /*
3511  * Field : mpu
3512  *
3513  * Security bit configuration for transactions from mpu to noc_probes_register.
3514  * When cleared (0), only Secure transactions are allowed. When set (1), both
3515  * Secure and Non-Secure transactions are allowed.
3516  *
3517  * Field Access Macros:
3518  *
3519  */
3520 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU register field. */
3521 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_LSB 0
3522 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU register field. */
3523 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_MSB 0
3524 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU register field. */
3525 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_WIDTH 1
3526 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU register field value. */
3527 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_SET_MSK 0x00000001
3528 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU register field value. */
3529 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_CLR_MSK 0xfffffffe
3530 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU register field. */
3531 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_RESET 0x0
3532 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU field value from a register. */
3533 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_GET(value) (((value) & 0x00000001) >> 0)
3534 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU register field value suitable for setting the register. */
3535 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_SET(value) (((value) << 0) & 0x00000001)
3536 
3537 /*
3538  * Field : fpga2soc
3539  *
3540  * Security bit configuration for transactions from fpga2soc to
3541  * noc_probes_register. When cleared (0), only Secure transactions are allowed.
3542  * When set (1), both Secure and Non-Secure transactions are allowed.
3543  *
3544  * Field Access Macros:
3545  *
3546  */
3547 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC register field. */
3548 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_LSB 16
3549 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC register field. */
3550 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_MSB 16
3551 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC register field. */
3552 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_WIDTH 1
3553 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC register field value. */
3554 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_SET_MSK 0x00010000
3555 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC register field value. */
3556 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_CLR_MSK 0xfffeffff
3557 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC register field. */
3558 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_RESET 0x0
3559 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC field value from a register. */
3560 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3561 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC register field value suitable for setting the register. */
3562 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3563 
3564 /*
3565  * Field : axi_ap
3566  *
3567  * Security bit configuration for transactions from axi_ap to noc_probes_register.
3568  * When cleared (0), only Secure transactions are allowed. When set (1), both
3569  * Secure and Non-Secure transactions are allowed.
3570  *
3571  * Field Access Macros:
3572  *
3573  */
3574 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP register field. */
3575 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_LSB 24
3576 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP register field. */
3577 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_MSB 24
3578 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP register field. */
3579 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_WIDTH 1
3580 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP register field value. */
3581 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_SET_MSK 0x01000000
3582 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP register field value. */
3583 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_CLR_MSK 0xfeffffff
3584 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP register field. */
3585 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_RESET 0x0
3586 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP field value from a register. */
3587 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3588 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP register field value suitable for setting the register. */
3589 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3590 
3591 #ifndef __ASSEMBLY__
3592 /*
3593  * WARNING: The C register and register group struct declarations are provided for
3594  * convenience and illustrative purposes. They should, however, be used with
3595  * caution as the C language standard provides no guarantees about the alignment or
3596  * atomicity of device memory accesses. The recommended practice for coding device
3597  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3598  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3599  * alt_write_dword() functions for 64 bit registers.
3600  *
3601  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES.
3602  */
3603 struct ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_s
3604 {
3605  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU */
3606  uint32_t : 15; /* *UNDEFINED* */
3607  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC */
3608  uint32_t : 7; /* *UNDEFINED* */
3609  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP */
3610  uint32_t : 7; /* *UNDEFINED* */
3611 };
3612 
3613 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES. */
3614 typedef struct ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_s ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_t;
3615 #endif /* __ASSEMBLY__ */
3616 
3617 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES register. */
3618 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_RESET 0x00000000
3619 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES register from the beginning of the component. */
3620 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_OFST 0x90
3621 
3622 /*
3623  * Register : l4_noc_qos
3624  *
3625  * Per-Master Security bit for noc_probes_register
3626  *
3627  * Register Layout
3628  *
3629  * Bits | Access | Reset | Description
3630  * :--------|:-------|:--------|:------------------------------------------
3631  * [0] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU
3632  * [15:1] | ??? | Unknown | *UNDEFINED*
3633  * [16] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC
3634  * [23:17] | ??? | Unknown | *UNDEFINED*
3635  * [24] | RW | 0x0 | ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP
3636  * [31:25] | ??? | Unknown | *UNDEFINED*
3637  *
3638  */
3639 /*
3640  * Field : mpu
3641  *
3642  * Security bit configuration for transactions from mpu to noc_probes_register.
3643  * When cleared (0), only Secure transactions are allowed. When set (1), both
3644  * Secure and Non-Secure transactions are allowed.
3645  *
3646  * Field Access Macros:
3647  *
3648  */
3649 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU register field. */
3650 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_LSB 0
3651 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU register field. */
3652 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_MSB 0
3653 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU register field. */
3654 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_WIDTH 1
3655 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU register field value. */
3656 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_SET_MSK 0x00000001
3657 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU register field value. */
3658 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_CLR_MSK 0xfffffffe
3659 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU register field. */
3660 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_RESET 0x0
3661 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU field value from a register. */
3662 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_GET(value) (((value) & 0x00000001) >> 0)
3663 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU register field value suitable for setting the register. */
3664 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_SET(value) (((value) << 0) & 0x00000001)
3665 
3666 /*
3667  * Field : fpga2soc
3668  *
3669  * Security bit configuration for transactions from fpga2soc to
3670  * noc_probes_register. When cleared (0), only Secure transactions are allowed.
3671  * When set (1), both Secure and Non-Secure transactions are allowed.
3672  *
3673  * Field Access Macros:
3674  *
3675  */
3676 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC register field. */
3677 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_LSB 16
3678 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC register field. */
3679 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_MSB 16
3680 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC register field. */
3681 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_WIDTH 1
3682 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC register field value. */
3683 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_SET_MSK 0x00010000
3684 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC register field value. */
3685 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_CLR_MSK 0xfffeffff
3686 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC register field. */
3687 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_RESET 0x0
3688 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC field value from a register. */
3689 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3690 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC register field value suitable for setting the register. */
3691 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3692 
3693 /*
3694  * Field : axi_ap
3695  *
3696  * Security bit configuration for transactions from axi_ap to noc_probes_register.
3697  * When cleared (0), only Secure transactions are allowed. When set (1), both
3698  * Secure and Non-Secure transactions are allowed.
3699  *
3700  * Field Access Macros:
3701  *
3702  */
3703 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP register field. */
3704 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_LSB 24
3705 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP register field. */
3706 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_MSB 24
3707 /* The width in bits of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP register field. */
3708 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_WIDTH 1
3709 /* The mask used to set the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP register field value. */
3710 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_SET_MSK 0x01000000
3711 /* The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP register field value. */
3712 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_CLR_MSK 0xfeffffff
3713 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP register field. */
3714 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_RESET 0x0
3715 /* Extracts the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP field value from a register. */
3716 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3717 /* Produces a ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP register field value suitable for setting the register. */
3718 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3719 
3720 #ifndef __ASSEMBLY__
3721 /*
3722  * WARNING: The C register and register group struct declarations are provided for
3723  * convenience and illustrative purposes. They should, however, be used with
3724  * caution as the C language standard provides no guarantees about the alignment or
3725  * atomicity of device memory accesses. The recommended practice for coding device
3726  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3727  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3728  * alt_write_dword() functions for 64 bit registers.
3729  *
3730  * The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS.
3731  */
3732 struct ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_s
3733 {
3734  volatile uint32_t mpu : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU */
3735  uint32_t : 15; /* *UNDEFINED* */
3736  volatile uint32_t fpga2soc : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC */
3737  uint32_t : 7; /* *UNDEFINED* */
3738  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP */
3739  uint32_t : 7; /* *UNDEFINED* */
3740 };
3741 
3742 /* The typedef declaration for register ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS. */
3743 typedef struct ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_s ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_t;
3744 #endif /* __ASSEMBLY__ */
3745 
3746 /* The reset value of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS register. */
3747 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_RESET 0x00000000
3748 /* The byte offset of the ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS register from the beginning of the component. */
3749 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_OFST 0x94
3750 
3751 #ifndef __ASSEMBLY__
3752 /*
3753  * WARNING: The C register and register group struct declarations are provided for
3754  * convenience and illustrative purposes. They should, however, be used with
3755  * caution as the C language standard provides no guarantees about the alignment or
3756  * atomicity of device memory accesses. The recommended practice for coding device
3757  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3758  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3759  * alt_write_dword() functions for 64 bit registers.
3760  *
3761  * The struct declaration for register group ALT_NOC_FW_L4_SYS_SCR.
3762  */
3763 struct ALT_NOC_FW_L4_SYS_SCR_s
3764 {
3765  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
3766  volatile ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_t dma_ecc; /* ALT_NOC_FW_L4_SYS_SCR_DMA_ECC */
3767  volatile ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_t emac0rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC */
3768  volatile ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_t emac0tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC */
3769  volatile ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_t emac1rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC */
3770  volatile ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_t emac1tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC */
3771  volatile ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_t emac2rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC */
3772  volatile ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_t emac2tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC */
3773  volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */
3774  volatile ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_t nand_ecc; /* ALT_NOC_FW_L4_SYS_SCR_NAND_ECC */
3775  volatile ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_t nand_read_ecc; /* ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC */
3776  volatile ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_t nand_write_ecc; /* ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC */
3777  volatile ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_t ocram_ecc; /* ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC */
3778  volatile uint32_t _pad_0x3c_0x3f; /* *UNDEFINED* */
3779  volatile ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_t sdmmc_ecc; /* ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC */
3780  volatile ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_t usb0_ecc; /* ALT_NOC_FW_L4_SYS_SCR_USB0_ECC */
3781  volatile ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_t usb1_ecc; /* ALT_NOC_FW_L4_SYS_SCR_USB1_ECC */
3782  volatile ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_t clock_manager; /* ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER */
3783  volatile uint32_t _pad_0x50_0x53; /* *UNDEFINED* */
3784  volatile ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_t io_manager; /* ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER */
3785  volatile ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_t reset_manager; /* ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER */
3786  volatile ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_t system_manager; /* ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER */
3787  volatile ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_t osc0_timer; /* ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER */
3788  volatile ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_t osc1_timer; /* ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER */
3789  volatile ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_t watchdog0; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0 */
3790  volatile ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_t watchdog1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1 */
3791  volatile ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_t watchdog2; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2 */
3792  volatile ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_t watchdog3; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3 */
3793  volatile ALT_NOC_FW_L4_SYS_SCR_DAP_t dap; /* ALT_NOC_FW_L4_SYS_SCR_DAP */
3794  volatile uint32_t _pad_0x7c_0x8f[5]; /* *UNDEFINED* */
3795  volatile ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_t l4_noc_probes; /* ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES */
3796  volatile ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_t l4_noc_qos; /* ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS */
3797  volatile uint32_t _pad_0x98_0x100[26]; /* *UNDEFINED* */
3798 };
3799 
3800 /* The typedef declaration for register group ALT_NOC_FW_L4_SYS_SCR. */
3801 typedef struct ALT_NOC_FW_L4_SYS_SCR_s ALT_NOC_FW_L4_SYS_SCR_t;
3802 /* The struct declaration for the raw register contents of register group ALT_NOC_FW_L4_SYS_SCR. */
3803 struct ALT_NOC_FW_L4_SYS_SCR_raw_s
3804 {
3805  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
3806  volatile uint32_t dma_ecc; /* ALT_NOC_FW_L4_SYS_SCR_DMA_ECC */
3807  volatile uint32_t emac0rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC */
3808  volatile uint32_t emac0tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC */
3809  volatile uint32_t emac1rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC */
3810  volatile uint32_t emac1tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC */
3811  volatile uint32_t emac2rx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC */
3812  volatile uint32_t emac2tx_ecc; /* ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC */
3813  volatile uint32_t _pad_0x24_0x2b[2]; /* *UNDEFINED* */
3814  volatile uint32_t nand_ecc; /* ALT_NOC_FW_L4_SYS_SCR_NAND_ECC */
3815  volatile uint32_t nand_read_ecc; /* ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC */
3816  volatile uint32_t nand_write_ecc; /* ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC */
3817  volatile uint32_t ocram_ecc; /* ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC */
3818  volatile uint32_t _pad_0x3c_0x3f; /* *UNDEFINED* */
3819  volatile uint32_t sdmmc_ecc; /* ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC */
3820  volatile uint32_t usb0_ecc; /* ALT_NOC_FW_L4_SYS_SCR_USB0_ECC */
3821  volatile uint32_t usb1_ecc; /* ALT_NOC_FW_L4_SYS_SCR_USB1_ECC */
3822  volatile uint32_t clock_manager; /* ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER */
3823  volatile uint32_t _pad_0x50_0x53; /* *UNDEFINED* */
3824  volatile uint32_t io_manager; /* ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER */
3825  volatile uint32_t reset_manager; /* ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER */
3826  volatile uint32_t system_manager; /* ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER */
3827  volatile uint32_t osc0_timer; /* ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER */
3828  volatile uint32_t osc1_timer; /* ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER */
3829  volatile uint32_t watchdog0; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0 */
3830  volatile uint32_t watchdog1; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1 */
3831  volatile uint32_t watchdog2; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2 */
3832  volatile uint32_t watchdog3; /* ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3 */
3833  volatile uint32_t dap; /* ALT_NOC_FW_L4_SYS_SCR_DAP */
3834  volatile uint32_t _pad_0x7c_0x8f[5]; /* *UNDEFINED* */
3835  volatile uint32_t l4_noc_probes; /* ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES */
3836  volatile uint32_t l4_noc_qos; /* ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS */
3837  volatile uint32_t _pad_0x98_0x100[26]; /* *UNDEFINED* */
3838 };
3839 
3840 /* The typedef declaration for the raw register contents of register group ALT_NOC_FW_L4_SYS_SCR. */
3841 typedef struct ALT_NOC_FW_L4_SYS_SCR_raw_s ALT_NOC_FW_L4_SYS_SCR_raw_t;
3842 #endif /* __ASSEMBLY__ */
3843 
3844 
3845 #ifdef __cplusplus
3846 }
3847 #endif /* __cplusplus */
3848 #endif /* __ALT_SOCAL_NOC_FW_L4_SYS_SCR_H__ */
3849