35 #ifndef __ALT_SOCAL_NOC_FW_L4_PER_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_L4_PER_SCR_H__
81 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_LSB 0
83 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_MSB 0
85 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_WIDTH 1
87 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_SET_MSK 0x00000001
89 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_CLR_MSK 0xfffffffe
91 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_RESET 0x0
93 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_GET(value) (((value) & 0x00000001) >> 0)
95 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_MPU_SET(value) (((value) << 0) & 0x00000001)
108 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_LSB 16
110 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_MSB 16
112 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_WIDTH 1
114 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_SET_MSK 0x00010000
116 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_CLR_MSK 0xfffeffff
118 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_RESET 0x0
120 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
122 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
135 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_LSB 24
137 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_MSB 24
139 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_WIDTH 1
141 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_SET_MSK 0x01000000
143 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_CLR_MSK 0xfeffffff
145 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_RESET 0x0
147 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
149 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
163 struct ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_s
165 volatile uint32_t mpu : 1;
167 volatile uint32_t fpga2soc : 1;
169 volatile uint32_t axi_ap : 1;
174 typedef struct ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_s ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_t;
178 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_RESET 0x00000000
180 #define ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_OFST 0x0
210 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_LSB 0
212 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_MSB 0
214 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_WIDTH 1
216 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_SET_MSK 0x00000001
218 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_CLR_MSK 0xfffffffe
220 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_RESET 0x0
222 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_GET(value) (((value) & 0x00000001) >> 0)
224 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_SET(value) (((value) << 0) & 0x00000001)
237 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_LSB 16
239 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_MSB 16
241 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_WIDTH 1
243 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_SET_MSK 0x00010000
245 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_CLR_MSK 0xfffeffff
247 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_RESET 0x0
249 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
251 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
264 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_LSB 24
266 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_MSB 24
268 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_WIDTH 1
270 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_SET_MSK 0x01000000
272 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_CLR_MSK 0xfeffffff
274 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_RESET 0x0
276 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
278 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
292 struct ALT_NOC_FW_L4_PER_SCR_NAND_DATA_s
294 volatile uint32_t mpu : 1;
296 volatile uint32_t fpga2soc : 1;
298 volatile uint32_t axi_ap : 1;
303 typedef struct ALT_NOC_FW_L4_PER_SCR_NAND_DATA_s ALT_NOC_FW_L4_PER_SCR_NAND_DATA_t;
307 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_RESET 0x00000000
309 #define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_OFST 0x4
339 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_LSB 0
341 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_MSB 0
343 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_WIDTH 1
345 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_SET_MSK 0x00000001
347 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_CLR_MSK 0xfffffffe
349 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_RESET 0x0
351 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_GET(value) (((value) & 0x00000001) >> 0)
353 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_MPU_SET(value) (((value) << 0) & 0x00000001)
366 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_LSB 16
368 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_MSB 16
370 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_WIDTH 1
372 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_SET_MSK 0x00010000
374 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_CLR_MSK 0xfffeffff
376 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_RESET 0x0
378 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
380 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
393 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_LSB 24
395 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_MSB 24
397 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_WIDTH 1
399 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_SET_MSK 0x01000000
401 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_CLR_MSK 0xfeffffff
403 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_RESET 0x0
405 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
407 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
421 struct ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_s
423 volatile uint32_t mpu : 1;
425 volatile uint32_t fpga2soc : 1;
427 volatile uint32_t axi_ap : 1;
432 typedef struct ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_s ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_t;
436 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_RESET 0x00000000
438 #define ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_OFST 0xc
468 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_LSB 0
470 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_MSB 0
472 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_WIDTH 1
474 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_SET_MSK 0x00000001
476 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_CLR_MSK 0xfffffffe
478 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_RESET 0x0
480 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_GET(value) (((value) & 0x00000001) >> 0)
482 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_MPU_SET(value) (((value) << 0) & 0x00000001)
495 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_LSB 16
497 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_MSB 16
499 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_WIDTH 1
501 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_SET_MSK 0x00010000
503 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_CLR_MSK 0xfffeffff
505 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_RESET 0x0
507 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
509 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
522 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_LSB 24
524 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_MSB 24
526 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_WIDTH 1
528 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_SET_MSK 0x01000000
530 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_CLR_MSK 0xfeffffff
532 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_RESET 0x0
534 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
536 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
550 struct ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_s
552 volatile uint32_t mpu : 1;
554 volatile uint32_t fpga2soc : 1;
556 volatile uint32_t axi_ap : 1;
561 typedef struct ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_s ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_t;
565 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_RESET 0x00000000
567 #define ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_OFST 0x10
599 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_LSB 0
601 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_MSB 0
603 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_WIDTH 1
605 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_SET_MSK 0x00000001
607 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_CLR_MSK 0xfffffffe
609 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_RESET 0x0
611 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_GET(value) (((value) & 0x00000001) >> 0)
613 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_MPU_SET(value) (((value) << 0) & 0x00000001)
626 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_LSB 8
628 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_MSB 8
630 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_WIDTH 1
632 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_SET_MSK 0x00000100
634 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_CLR_MSK 0xfffffeff
636 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_RESET 0x0
638 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_GET(value) (((value) & 0x00000100) >> 8)
640 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_DMA_SET(value) (((value) << 8) & 0x00000100)
653 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_LSB 16
655 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_MSB 16
657 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_WIDTH 1
659 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_SET_MSK 0x00010000
661 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_CLR_MSK 0xfffeffff
663 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_RESET 0x0
665 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
667 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
680 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_LSB 24
682 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_MSB 24
684 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_WIDTH 1
686 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_SET_MSK 0x01000000
688 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_CLR_MSK 0xfeffffff
690 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_RESET 0x0
692 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
694 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
708 struct ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_s
710 volatile uint32_t mpu : 1;
712 volatile uint32_t dma : 1;
714 volatile uint32_t fpga2soc : 1;
716 volatile uint32_t axi_ap : 1;
721 typedef struct ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_s ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_t;
725 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_RESET 0x00000000
727 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_OFST 0x1c
759 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_LSB 0
761 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_MSB 0
763 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_WIDTH 1
765 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_SET_MSK 0x00000001
767 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_CLR_MSK 0xfffffffe
769 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_RESET 0x0
771 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_GET(value) (((value) & 0x00000001) >> 0)
773 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_MPU_SET(value) (((value) << 0) & 0x00000001)
786 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_LSB 8
788 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_MSB 8
790 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_WIDTH 1
792 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_SET_MSK 0x00000100
794 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_CLR_MSK 0xfffffeff
796 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_RESET 0x0
798 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_GET(value) (((value) & 0x00000100) >> 8)
800 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_DMA_SET(value) (((value) << 8) & 0x00000100)
813 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_LSB 16
815 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_MSB 16
817 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_WIDTH 1
819 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_SET_MSK 0x00010000
821 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_CLR_MSK 0xfffeffff
823 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_RESET 0x0
825 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
827 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
840 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_LSB 24
842 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_MSB 24
844 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_WIDTH 1
846 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_SET_MSK 0x01000000
848 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_CLR_MSK 0xfeffffff
850 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_RESET 0x0
852 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
854 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
868 struct ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_s
870 volatile uint32_t mpu : 1;
872 volatile uint32_t dma : 1;
874 volatile uint32_t fpga2soc : 1;
876 volatile uint32_t axi_ap : 1;
881 typedef struct ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_s ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_t;
885 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_RESET 0x00000000
887 #define ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_OFST 0x20
919 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_LSB 0
921 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_MSB 0
923 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_WIDTH 1
925 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_SET_MSK 0x00000001
927 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_CLR_MSK 0xfffffffe
929 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_RESET 0x0
931 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_GET(value) (((value) & 0x00000001) >> 0)
933 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_MPU_SET(value) (((value) << 0) & 0x00000001)
946 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_LSB 8
948 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_MSB 8
950 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_WIDTH 1
952 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_SET_MSK 0x00000100
954 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_CLR_MSK 0xfffffeff
956 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_RESET 0x0
958 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_GET(value) (((value) & 0x00000100) >> 8)
960 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_DMA_SET(value) (((value) << 8) & 0x00000100)
973 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_LSB 16
975 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_MSB 16
977 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_WIDTH 1
979 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_SET_MSK 0x00010000
981 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_CLR_MSK 0xfffeffff
983 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_RESET 0x0
985 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
987 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1000 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_LSB 24
1002 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_MSB 24
1004 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_WIDTH 1
1006 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_SET_MSK 0x01000000
1008 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_CLR_MSK 0xfeffffff
1010 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_RESET 0x0
1012 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1014 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1016 #ifndef __ASSEMBLY__
1028 struct ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_s
1030 volatile uint32_t mpu : 1;
1032 volatile uint32_t dma : 1;
1034 volatile uint32_t fpga2soc : 1;
1036 volatile uint32_t axi_ap : 1;
1041 typedef struct ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_s ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_t;
1045 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_RESET 0x00000000
1047 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_OFST 0x24
1079 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_LSB 0
1081 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_MSB 0
1083 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_WIDTH 1
1085 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_SET_MSK 0x00000001
1087 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_CLR_MSK 0xfffffffe
1089 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_RESET 0x0
1091 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_GET(value) (((value) & 0x00000001) >> 0)
1093 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_MPU_SET(value) (((value) << 0) & 0x00000001)
1106 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_LSB 8
1108 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_MSB 8
1110 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_WIDTH 1
1112 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_SET_MSK 0x00000100
1114 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_CLR_MSK 0xfffffeff
1116 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_RESET 0x0
1118 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_GET(value) (((value) & 0x00000100) >> 8)
1120 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_DMA_SET(value) (((value) << 8) & 0x00000100)
1133 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_LSB 16
1135 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_MSB 16
1137 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_WIDTH 1
1139 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_SET_MSK 0x00010000
1141 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_CLR_MSK 0xfffeffff
1143 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_RESET 0x0
1145 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1147 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1160 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_LSB 24
1162 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_MSB 24
1164 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_WIDTH 1
1166 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_SET_MSK 0x01000000
1168 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_CLR_MSK 0xfeffffff
1170 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_RESET 0x0
1172 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1174 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1176 #ifndef __ASSEMBLY__
1188 struct ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_s
1190 volatile uint32_t mpu : 1;
1192 volatile uint32_t dma : 1;
1194 volatile uint32_t fpga2soc : 1;
1196 volatile uint32_t axi_ap : 1;
1201 typedef struct ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_s ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_t;
1205 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_RESET 0x00000000
1207 #define ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_OFST 0x28
1237 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_LSB 0
1239 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_MSB 0
1241 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_WIDTH 1
1243 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_SET_MSK 0x00000001
1245 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_CLR_MSK 0xfffffffe
1247 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_RESET 0x0
1249 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_GET(value) (((value) & 0x00000001) >> 0)
1251 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_SET(value) (((value) << 0) & 0x00000001)
1264 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_LSB 16
1266 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_MSB 16
1268 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_WIDTH 1
1270 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_SET_MSK 0x00010000
1272 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_CLR_MSK 0xfffeffff
1274 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_RESET 0x0
1276 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1278 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1291 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_LSB 24
1293 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_MSB 24
1295 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_WIDTH 1
1297 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_SET_MSK 0x01000000
1299 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_CLR_MSK 0xfeffffff
1301 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_RESET 0x0
1303 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1305 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1307 #ifndef __ASSEMBLY__
1319 struct ALT_NOC_FW_L4_PER_SCR_EMAC0_s
1321 volatile uint32_t mpu : 1;
1323 volatile uint32_t fpga2soc : 1;
1325 volatile uint32_t axi_ap : 1;
1330 typedef struct ALT_NOC_FW_L4_PER_SCR_EMAC0_s ALT_NOC_FW_L4_PER_SCR_EMAC0_t;
1334 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_RESET 0x00000000
1336 #define ALT_NOC_FW_L4_PER_SCR_EMAC0_OFST 0x2c
1366 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_LSB 0
1368 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_MSB 0
1370 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_WIDTH 1
1372 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_SET_MSK 0x00000001
1374 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_CLR_MSK 0xfffffffe
1376 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_RESET 0x0
1378 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_GET(value) (((value) & 0x00000001) >> 0)
1380 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_SET(value) (((value) << 0) & 0x00000001)
1393 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_LSB 16
1395 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_MSB 16
1397 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_WIDTH 1
1399 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_SET_MSK 0x00010000
1401 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_CLR_MSK 0xfffeffff
1403 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_RESET 0x0
1405 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1407 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1420 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_LSB 24
1422 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_MSB 24
1424 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_WIDTH 1
1426 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_SET_MSK 0x01000000
1428 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_CLR_MSK 0xfeffffff
1430 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_RESET 0x0
1432 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1434 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1436 #ifndef __ASSEMBLY__
1448 struct ALT_NOC_FW_L4_PER_SCR_EMAC1_s
1450 volatile uint32_t mpu : 1;
1452 volatile uint32_t fpga2soc : 1;
1454 volatile uint32_t axi_ap : 1;
1459 typedef struct ALT_NOC_FW_L4_PER_SCR_EMAC1_s ALT_NOC_FW_L4_PER_SCR_EMAC1_t;
1463 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_RESET 0x00000000
1465 #define ALT_NOC_FW_L4_PER_SCR_EMAC1_OFST 0x30
1495 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_LSB 0
1497 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_MSB 0
1499 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_WIDTH 1
1501 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_SET_MSK 0x00000001
1503 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_CLR_MSK 0xfffffffe
1505 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_RESET 0x0
1507 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_GET(value) (((value) & 0x00000001) >> 0)
1509 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_SET(value) (((value) << 0) & 0x00000001)
1522 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_LSB 16
1524 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_MSB 16
1526 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_WIDTH 1
1528 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_SET_MSK 0x00010000
1530 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_CLR_MSK 0xfffeffff
1532 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_RESET 0x0
1534 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1536 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1549 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_LSB 24
1551 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_MSB 24
1553 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_WIDTH 1
1555 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_SET_MSK 0x01000000
1557 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_CLR_MSK 0xfeffffff
1559 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_RESET 0x0
1561 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1563 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1565 #ifndef __ASSEMBLY__
1577 struct ALT_NOC_FW_L4_PER_SCR_EMAC2_s
1579 volatile uint32_t mpu : 1;
1581 volatile uint32_t fpga2soc : 1;
1583 volatile uint32_t axi_ap : 1;
1588 typedef struct ALT_NOC_FW_L4_PER_SCR_EMAC2_s ALT_NOC_FW_L4_PER_SCR_EMAC2_t;
1592 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_RESET 0x00000000
1594 #define ALT_NOC_FW_L4_PER_SCR_EMAC2_OFST 0x34
1624 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_LSB 0
1626 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_MSB 0
1628 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_WIDTH 1
1630 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_SET_MSK 0x00000001
1632 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_CLR_MSK 0xfffffffe
1634 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_RESET 0x0
1636 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1638 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_SET(value) (((value) << 0) & 0x00000001)
1651 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_LSB 16
1653 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_MSB 16
1655 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_WIDTH 1
1657 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_SET_MSK 0x00010000
1659 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_CLR_MSK 0xfffeffff
1661 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_RESET 0x0
1663 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1665 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1678 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_LSB 24
1680 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_MSB 24
1682 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_WIDTH 1
1684 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_SET_MSK 0x01000000
1686 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_CLR_MSK 0xfeffffff
1688 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_RESET 0x0
1690 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1692 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1694 #ifndef __ASSEMBLY__
1706 struct ALT_NOC_FW_L4_PER_SCR_SDMMC_s
1708 volatile uint32_t mpu : 1;
1710 volatile uint32_t fpga2soc : 1;
1712 volatile uint32_t axi_ap : 1;
1717 typedef struct ALT_NOC_FW_L4_PER_SCR_SDMMC_s ALT_NOC_FW_L4_PER_SCR_SDMMC_t;
1721 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_RESET 0x00000000
1723 #define ALT_NOC_FW_L4_PER_SCR_SDMMC_OFST 0x40
1755 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_LSB 0
1757 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_MSB 0
1759 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_WIDTH 1
1761 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_SET_MSK 0x00000001
1763 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_CLR_MSK 0xfffffffe
1765 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_RESET 0x0
1767 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_GET(value) (((value) & 0x00000001) >> 0)
1769 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_SET(value) (((value) << 0) & 0x00000001)
1782 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_LSB 8
1784 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_MSB 8
1786 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_WIDTH 1
1788 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_SET_MSK 0x00000100
1790 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_CLR_MSK 0xfffffeff
1792 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_RESET 0x0
1794 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_GET(value) (((value) & 0x00000100) >> 8)
1796 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_SET(value) (((value) << 8) & 0x00000100)
1809 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_LSB 16
1811 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_MSB 16
1813 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_WIDTH 1
1815 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_SET_MSK 0x00010000
1817 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_CLR_MSK 0xfffeffff
1819 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_RESET 0x0
1821 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1823 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1836 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_LSB 24
1838 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_MSB 24
1840 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_WIDTH 1
1842 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_SET_MSK 0x01000000
1844 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_CLR_MSK 0xfeffffff
1846 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_RESET 0x0
1848 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1850 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1852 #ifndef __ASSEMBLY__
1864 struct ALT_NOC_FW_L4_PER_SCR_GPIO0_s
1866 volatile uint32_t mpu : 1;
1868 volatile uint32_t dma : 1;
1870 volatile uint32_t fpga2soc : 1;
1872 volatile uint32_t axi_ap : 1;
1877 typedef struct ALT_NOC_FW_L4_PER_SCR_GPIO0_s ALT_NOC_FW_L4_PER_SCR_GPIO0_t;
1881 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_RESET 0x00000000
1883 #define ALT_NOC_FW_L4_PER_SCR_GPIO0_OFST 0x44
1915 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_LSB 0
1917 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_MSB 0
1919 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_WIDTH 1
1921 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_SET_MSK 0x00000001
1923 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_CLR_MSK 0xfffffffe
1925 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_RESET 0x0
1927 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_GET(value) (((value) & 0x00000001) >> 0)
1929 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_SET(value) (((value) << 0) & 0x00000001)
1942 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_LSB 8
1944 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_MSB 8
1946 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_WIDTH 1
1948 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_SET_MSK 0x00000100
1950 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_CLR_MSK 0xfffffeff
1952 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_RESET 0x0
1954 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_GET(value) (((value) & 0x00000100) >> 8)
1956 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_SET(value) (((value) << 8) & 0x00000100)
1969 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_LSB 16
1971 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_MSB 16
1973 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_WIDTH 1
1975 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_SET_MSK 0x00010000
1977 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_CLR_MSK 0xfffeffff
1979 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_RESET 0x0
1981 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1983 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1996 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_LSB 24
1998 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_MSB 24
2000 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_WIDTH 1
2002 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_SET_MSK 0x01000000
2004 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_CLR_MSK 0xfeffffff
2006 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_RESET 0x0
2008 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2010 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2012 #ifndef __ASSEMBLY__
2024 struct ALT_NOC_FW_L4_PER_SCR_GPIO1_s
2026 volatile uint32_t mpu : 1;
2028 volatile uint32_t dma : 1;
2030 volatile uint32_t fpga2soc : 1;
2032 volatile uint32_t axi_ap : 1;
2037 typedef struct ALT_NOC_FW_L4_PER_SCR_GPIO1_s ALT_NOC_FW_L4_PER_SCR_GPIO1_t;
2041 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_RESET 0x00000000
2043 #define ALT_NOC_FW_L4_PER_SCR_GPIO1_OFST 0x48
2075 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_LSB 0
2077 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_MSB 0
2079 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_WIDTH 1
2081 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_SET_MSK 0x00000001
2083 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_CLR_MSK 0xfffffffe
2085 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_RESET 0x0
2087 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_GET(value) (((value) & 0x00000001) >> 0)
2089 #define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_SET(value) (((value) << 0) & 0x00000001)
2102 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_LSB 8
2104 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_MSB 8
2106 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_WIDTH 1
2108 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_SET_MSK 0x00000100
2110 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_CLR_MSK 0xfffffeff
2112 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_RESET 0x0
2114 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_GET(value) (((value) & 0x00000100) >> 8)
2116 #define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_SET(value) (((value) << 8) & 0x00000100)
2129 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_LSB 16
2131 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_MSB 16
2133 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_WIDTH 1
2135 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_SET_MSK 0x00010000
2137 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_CLR_MSK 0xfffeffff
2139 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_RESET 0x0
2141 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2143 #define ALT_NOC_FW_L4_PER_SCR_I2C0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2156 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_LSB 24
2158 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_MSB 24
2160 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_WIDTH 1
2162 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_SET_MSK 0x01000000
2164 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_CLR_MSK 0xfeffffff
2166 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_RESET 0x0
2168 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2170 #define ALT_NOC_FW_L4_PER_SCR_I2C0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2172 #ifndef __ASSEMBLY__
2184 struct ALT_NOC_FW_L4_PER_SCR_I2C0_s
2186 volatile uint32_t mpu : 1;
2188 volatile uint32_t dma : 1;
2190 volatile uint32_t fpga2soc : 1;
2192 volatile uint32_t axi_ap : 1;
2197 typedef struct ALT_NOC_FW_L4_PER_SCR_I2C0_s ALT_NOC_FW_L4_PER_SCR_I2C0_t;
2201 #define ALT_NOC_FW_L4_PER_SCR_I2C0_RESET 0x00000000
2203 #define ALT_NOC_FW_L4_PER_SCR_I2C0_OFST 0x50
2235 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_LSB 0
2237 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_MSB 0
2239 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_WIDTH 1
2241 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_SET_MSK 0x00000001
2243 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_CLR_MSK 0xfffffffe
2245 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_RESET 0x0
2247 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_GET(value) (((value) & 0x00000001) >> 0)
2249 #define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_SET(value) (((value) << 0) & 0x00000001)
2262 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_LSB 8
2264 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_MSB 8
2266 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_WIDTH 1
2268 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_SET_MSK 0x00000100
2270 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_CLR_MSK 0xfffffeff
2272 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_RESET 0x0
2274 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_GET(value) (((value) & 0x00000100) >> 8)
2276 #define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_SET(value) (((value) << 8) & 0x00000100)
2289 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_LSB 16
2291 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_MSB 16
2293 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_WIDTH 1
2295 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_SET_MSK 0x00010000
2297 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_CLR_MSK 0xfffeffff
2299 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_RESET 0x0
2301 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2303 #define ALT_NOC_FW_L4_PER_SCR_I2C1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2316 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_LSB 24
2318 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_MSB 24
2320 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_WIDTH 1
2322 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_SET_MSK 0x01000000
2324 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_CLR_MSK 0xfeffffff
2326 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_RESET 0x0
2328 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2330 #define ALT_NOC_FW_L4_PER_SCR_I2C1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2332 #ifndef __ASSEMBLY__
2344 struct ALT_NOC_FW_L4_PER_SCR_I2C1_s
2346 volatile uint32_t mpu : 1;
2348 volatile uint32_t dma : 1;
2350 volatile uint32_t fpga2soc : 1;
2352 volatile uint32_t axi_ap : 1;
2357 typedef struct ALT_NOC_FW_L4_PER_SCR_I2C1_s ALT_NOC_FW_L4_PER_SCR_I2C1_t;
2361 #define ALT_NOC_FW_L4_PER_SCR_I2C1_RESET 0x00000000
2363 #define ALT_NOC_FW_L4_PER_SCR_I2C1_OFST 0x54
2395 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_LSB 0
2397 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_MSB 0
2399 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_WIDTH 1
2401 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_SET_MSK 0x00000001
2403 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_CLR_MSK 0xfffffffe
2405 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_RESET 0x0
2407 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_GET(value) (((value) & 0x00000001) >> 0)
2409 #define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_SET(value) (((value) << 0) & 0x00000001)
2422 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_LSB 8
2424 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_MSB 8
2426 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_WIDTH 1
2428 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_SET_MSK 0x00000100
2430 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_CLR_MSK 0xfffffeff
2432 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_RESET 0x0
2434 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_GET(value) (((value) & 0x00000100) >> 8)
2436 #define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_SET(value) (((value) << 8) & 0x00000100)
2449 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_LSB 16
2451 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_MSB 16
2453 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_WIDTH 1
2455 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_SET_MSK 0x00010000
2457 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_CLR_MSK 0xfffeffff
2459 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_RESET 0x0
2461 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2463 #define ALT_NOC_FW_L4_PER_SCR_I2C2_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2476 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_LSB 24
2478 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_MSB 24
2480 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_WIDTH 1
2482 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_SET_MSK 0x01000000
2484 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_CLR_MSK 0xfeffffff
2486 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_RESET 0x0
2488 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2490 #define ALT_NOC_FW_L4_PER_SCR_I2C2_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2492 #ifndef __ASSEMBLY__
2504 struct ALT_NOC_FW_L4_PER_SCR_I2C2_s
2506 volatile uint32_t mpu : 1;
2508 volatile uint32_t dma : 1;
2510 volatile uint32_t fpga2soc : 1;
2512 volatile uint32_t axi_ap : 1;
2517 typedef struct ALT_NOC_FW_L4_PER_SCR_I2C2_s ALT_NOC_FW_L4_PER_SCR_I2C2_t;
2521 #define ALT_NOC_FW_L4_PER_SCR_I2C2_RESET 0x00000000
2523 #define ALT_NOC_FW_L4_PER_SCR_I2C2_OFST 0x58
2555 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_LSB 0
2557 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_MSB 0
2559 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_WIDTH 1
2561 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_SET_MSK 0x00000001
2563 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_CLR_MSK 0xfffffffe
2565 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_RESET 0x0
2567 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_GET(value) (((value) & 0x00000001) >> 0)
2569 #define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_SET(value) (((value) << 0) & 0x00000001)
2582 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_LSB 8
2584 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_MSB 8
2586 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_WIDTH 1
2588 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_SET_MSK 0x00000100
2590 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_CLR_MSK 0xfffffeff
2592 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_RESET 0x0
2594 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_GET(value) (((value) & 0x00000100) >> 8)
2596 #define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_SET(value) (((value) << 8) & 0x00000100)
2609 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_LSB 16
2611 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_MSB 16
2613 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_WIDTH 1
2615 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_SET_MSK 0x00010000
2617 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_CLR_MSK 0xfffeffff
2619 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_RESET 0x0
2621 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2623 #define ALT_NOC_FW_L4_PER_SCR_I2C3_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2636 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_LSB 24
2638 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_MSB 24
2640 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_WIDTH 1
2642 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_SET_MSK 0x01000000
2644 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_CLR_MSK 0xfeffffff
2646 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_RESET 0x0
2648 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2650 #define ALT_NOC_FW_L4_PER_SCR_I2C3_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2652 #ifndef __ASSEMBLY__
2664 struct ALT_NOC_FW_L4_PER_SCR_I2C3_s
2666 volatile uint32_t mpu : 1;
2668 volatile uint32_t dma : 1;
2670 volatile uint32_t fpga2soc : 1;
2672 volatile uint32_t axi_ap : 1;
2677 typedef struct ALT_NOC_FW_L4_PER_SCR_I2C3_s ALT_NOC_FW_L4_PER_SCR_I2C3_t;
2681 #define ALT_NOC_FW_L4_PER_SCR_I2C3_RESET 0x00000000
2683 #define ALT_NOC_FW_L4_PER_SCR_I2C3_OFST 0x5c
2715 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_LSB 0
2717 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_MSB 0
2719 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_WIDTH 1
2721 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_SET_MSK 0x00000001
2723 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_CLR_MSK 0xfffffffe
2725 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_RESET 0x0
2727 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_GET(value) (((value) & 0x00000001) >> 0)
2729 #define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_SET(value) (((value) << 0) & 0x00000001)
2742 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_LSB 8
2744 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_MSB 8
2746 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_WIDTH 1
2748 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_SET_MSK 0x00000100
2750 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_CLR_MSK 0xfffffeff
2752 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_RESET 0x0
2754 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_GET(value) (((value) & 0x00000100) >> 8)
2756 #define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_SET(value) (((value) << 8) & 0x00000100)
2769 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_LSB 16
2771 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_MSB 16
2773 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_WIDTH 1
2775 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_SET_MSK 0x00010000
2777 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_CLR_MSK 0xfffeffff
2779 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_RESET 0x0
2781 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2783 #define ALT_NOC_FW_L4_PER_SCR_I2C4_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2796 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_LSB 24
2798 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_MSB 24
2800 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_WIDTH 1
2802 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_SET_MSK 0x01000000
2804 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_CLR_MSK 0xfeffffff
2806 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_RESET 0x0
2808 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2810 #define ALT_NOC_FW_L4_PER_SCR_I2C4_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2812 #ifndef __ASSEMBLY__
2824 struct ALT_NOC_FW_L4_PER_SCR_I2C4_s
2826 volatile uint32_t mpu : 1;
2828 volatile uint32_t dma : 1;
2830 volatile uint32_t fpga2soc : 1;
2832 volatile uint32_t axi_ap : 1;
2837 typedef struct ALT_NOC_FW_L4_PER_SCR_I2C4_s ALT_NOC_FW_L4_PER_SCR_I2C4_t;
2841 #define ALT_NOC_FW_L4_PER_SCR_I2C4_RESET 0x00000000
2843 #define ALT_NOC_FW_L4_PER_SCR_I2C4_OFST 0x60
2875 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_LSB 0
2877 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_MSB 0
2879 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_WIDTH 1
2881 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_SET_MSK 0x00000001
2883 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_CLR_MSK 0xfffffffe
2885 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_RESET 0x0
2887 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_GET(value) (((value) & 0x00000001) >> 0)
2889 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_MPU_SET(value) (((value) << 0) & 0x00000001)
2902 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_LSB 8
2904 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_MSB 8
2906 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_WIDTH 1
2908 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_SET_MSK 0x00000100
2910 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_CLR_MSK 0xfffffeff
2912 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_RESET 0x0
2914 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_GET(value) (((value) & 0x00000100) >> 8)
2916 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_DMA_SET(value) (((value) << 8) & 0x00000100)
2929 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_LSB 16
2931 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_MSB 16
2933 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_WIDTH 1
2935 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_SET_MSK 0x00010000
2937 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_CLR_MSK 0xfffeffff
2939 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_RESET 0x0
2941 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2943 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2956 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_LSB 24
2958 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_MSB 24
2960 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_WIDTH 1
2962 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_SET_MSK 0x01000000
2964 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_CLR_MSK 0xfeffffff
2966 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_RESET 0x0
2968 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2970 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2972 #ifndef __ASSEMBLY__
2984 struct ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_s
2986 volatile uint32_t mpu : 1;
2988 volatile uint32_t dma : 1;
2990 volatile uint32_t fpga2soc : 1;
2992 volatile uint32_t axi_ap : 1;
2997 typedef struct ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_s ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_t;
3001 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_RESET 0x00000000
3003 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_OFST 0x64
3035 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_LSB 0
3037 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_MSB 0
3039 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_WIDTH 1
3041 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_SET_MSK 0x00000001
3043 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_CLR_MSK 0xfffffffe
3045 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_RESET 0x0
3047 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_GET(value) (((value) & 0x00000001) >> 0)
3049 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_MPU_SET(value) (((value) << 0) & 0x00000001)
3062 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_LSB 8
3064 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_MSB 8
3066 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_WIDTH 1
3068 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_SET_MSK 0x00000100
3070 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_CLR_MSK 0xfffffeff
3072 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_RESET 0x0
3074 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_GET(value) (((value) & 0x00000100) >> 8)
3076 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_DMA_SET(value) (((value) << 8) & 0x00000100)
3089 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_LSB 16
3091 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_MSB 16
3093 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_WIDTH 1
3095 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_SET_MSK 0x00010000
3097 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_CLR_MSK 0xfffeffff
3099 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_RESET 0x0
3101 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3103 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3116 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_LSB 24
3118 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_MSB 24
3120 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_WIDTH 1
3122 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_SET_MSK 0x01000000
3124 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_CLR_MSK 0xfeffffff
3126 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_RESET 0x0
3128 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3130 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3132 #ifndef __ASSEMBLY__
3144 struct ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_s
3146 volatile uint32_t mpu : 1;
3148 volatile uint32_t dma : 1;
3150 volatile uint32_t fpga2soc : 1;
3152 volatile uint32_t axi_ap : 1;
3157 typedef struct ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_s ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_t;
3161 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_RESET 0x00000000
3163 #define ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_OFST 0x68
3195 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_LSB 0
3197 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_MSB 0
3199 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_WIDTH 1
3201 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_SET_MSK 0x00000001
3203 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_CLR_MSK 0xfffffffe
3205 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_RESET 0x0
3207 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_GET(value) (((value) & 0x00000001) >> 0)
3209 #define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_SET(value) (((value) << 0) & 0x00000001)
3222 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_LSB 8
3224 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_MSB 8
3226 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_WIDTH 1
3228 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_SET_MSK 0x00000100
3230 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_CLR_MSK 0xfffffeff
3232 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_RESET 0x0
3234 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_GET(value) (((value) & 0x00000100) >> 8)
3236 #define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_SET(value) (((value) << 8) & 0x00000100)
3249 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_LSB 16
3251 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_MSB 16
3253 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_WIDTH 1
3255 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_SET_MSK 0x00010000
3257 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_CLR_MSK 0xfffeffff
3259 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_RESET 0x0
3261 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3263 #define ALT_NOC_FW_L4_PER_SCR_UART0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3276 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_LSB 24
3278 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_MSB 24
3280 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_WIDTH 1
3282 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_SET_MSK 0x01000000
3284 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_CLR_MSK 0xfeffffff
3286 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_RESET 0x0
3288 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3290 #define ALT_NOC_FW_L4_PER_SCR_UART0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3292 #ifndef __ASSEMBLY__
3304 struct ALT_NOC_FW_L4_PER_SCR_UART0_s
3306 volatile uint32_t mpu : 1;
3308 volatile uint32_t dma : 1;
3310 volatile uint32_t fpga2soc : 1;
3312 volatile uint32_t axi_ap : 1;
3317 typedef struct ALT_NOC_FW_L4_PER_SCR_UART0_s ALT_NOC_FW_L4_PER_SCR_UART0_t;
3321 #define ALT_NOC_FW_L4_PER_SCR_UART0_RESET 0x00000000
3323 #define ALT_NOC_FW_L4_PER_SCR_UART0_OFST 0x6c
3355 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_LSB 0
3357 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_MSB 0
3359 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_WIDTH 1
3361 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_SET_MSK 0x00000001
3363 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_CLR_MSK 0xfffffffe
3365 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_RESET 0x0
3367 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_GET(value) (((value) & 0x00000001) >> 0)
3369 #define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_SET(value) (((value) << 0) & 0x00000001)
3382 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_LSB 8
3384 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_MSB 8
3386 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_WIDTH 1
3388 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_SET_MSK 0x00000100
3390 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_CLR_MSK 0xfffffeff
3392 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_RESET 0x0
3394 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_GET(value) (((value) & 0x00000100) >> 8)
3396 #define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_SET(value) (((value) << 8) & 0x00000100)
3409 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_LSB 16
3411 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_MSB 16
3413 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_WIDTH 1
3415 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_SET_MSK 0x00010000
3417 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_CLR_MSK 0xfffeffff
3419 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_RESET 0x0
3421 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3423 #define ALT_NOC_FW_L4_PER_SCR_UART1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3436 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_LSB 24
3438 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_MSB 24
3440 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_WIDTH 1
3442 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_SET_MSK 0x01000000
3444 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_CLR_MSK 0xfeffffff
3446 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_RESET 0x0
3448 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3450 #define ALT_NOC_FW_L4_PER_SCR_UART1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3452 #ifndef __ASSEMBLY__
3464 struct ALT_NOC_FW_L4_PER_SCR_UART1_s
3466 volatile uint32_t mpu : 1;
3468 volatile uint32_t dma : 1;
3470 volatile uint32_t fpga2soc : 1;
3472 volatile uint32_t axi_ap : 1;
3477 typedef struct ALT_NOC_FW_L4_PER_SCR_UART1_s ALT_NOC_FW_L4_PER_SCR_UART1_t;
3481 #define ALT_NOC_FW_L4_PER_SCR_UART1_RESET 0x00000000
3483 #define ALT_NOC_FW_L4_PER_SCR_UART1_OFST 0x70
3485 #ifndef __ASSEMBLY__
3497 struct ALT_NOC_FW_L4_PER_SCR_s
3499 volatile ALT_NOC_FW_L4_PER_SCR_NAND_REGISTER_t nand_register;
3500 volatile ALT_NOC_FW_L4_PER_SCR_NAND_DATA_t nand_data;
3501 volatile uint32_t _pad_0x8_0xb;
3502 volatile ALT_NOC_FW_L4_PER_SCR_USB0_REGISTER_t usb0_register;
3503 volatile ALT_NOC_FW_L4_PER_SCR_USB1_REGISTER_t usb1_register;
3504 volatile uint32_t _pad_0x14_0x1b[2];
3505 volatile ALT_NOC_FW_L4_PER_SCR_SPI_MASTER0_t spi_master0;
3506 volatile ALT_NOC_FW_L4_PER_SCR_SPI_MASTER1_t spi_master1;
3507 volatile ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE0_t spi_slave0;
3508 volatile ALT_NOC_FW_L4_PER_SCR_SPI_SLAVE1_t spi_slave1;
3509 volatile ALT_NOC_FW_L4_PER_SCR_EMAC0_t emac0;
3510 volatile ALT_NOC_FW_L4_PER_SCR_EMAC1_t emac1;
3511 volatile ALT_NOC_FW_L4_PER_SCR_EMAC2_t emac2;
3512 volatile uint32_t _pad_0x38_0x3f[2];
3513 volatile ALT_NOC_FW_L4_PER_SCR_SDMMC_t sdmmc;
3514 volatile ALT_NOC_FW_L4_PER_SCR_GPIO0_t gpio0;
3515 volatile ALT_NOC_FW_L4_PER_SCR_GPIO1_t gpio1;
3516 volatile uint32_t _pad_0x4c_0x4f;
3517 volatile ALT_NOC_FW_L4_PER_SCR_I2C0_t i2c0;
3518 volatile ALT_NOC_FW_L4_PER_SCR_I2C1_t i2c1;
3519 volatile ALT_NOC_FW_L4_PER_SCR_I2C2_t i2c2;
3520 volatile ALT_NOC_FW_L4_PER_SCR_I2C3_t i2c3;
3521 volatile ALT_NOC_FW_L4_PER_SCR_I2C4_t i2c4;
3522 volatile ALT_NOC_FW_L4_PER_SCR_SP_TIMER0_t sp_timer0;
3523 volatile ALT_NOC_FW_L4_PER_SCR_SP_TIMER1_t sp_timer1;
3524 volatile ALT_NOC_FW_L4_PER_SCR_UART0_t uart0;
3525 volatile ALT_NOC_FW_L4_PER_SCR_UART1_t uart1;
3526 volatile uint32_t _pad_0x74_0x100[35];
3530 typedef struct ALT_NOC_FW_L4_PER_SCR_s ALT_NOC_FW_L4_PER_SCR_t;
3532 struct ALT_NOC_FW_L4_PER_SCR_raw_s
3534 volatile uint32_t nand_register;
3535 volatile uint32_t nand_data;
3536 volatile uint32_t _pad_0x8_0xb;
3537 volatile uint32_t usb0_register;
3538 volatile uint32_t usb1_register;
3539 volatile uint32_t _pad_0x14_0x1b[2];
3540 volatile uint32_t spi_master0;
3541 volatile uint32_t spi_master1;
3542 volatile uint32_t spi_slave0;
3543 volatile uint32_t spi_slave1;
3544 volatile uint32_t emac0;
3545 volatile uint32_t emac1;
3546 volatile uint32_t emac2;
3547 volatile uint32_t _pad_0x38_0x3f[2];
3548 volatile uint32_t sdmmc;
3549 volatile uint32_t gpio0;
3550 volatile uint32_t gpio1;
3551 volatile uint32_t _pad_0x4c_0x4f;
3552 volatile uint32_t i2c0;
3553 volatile uint32_t i2c1;
3554 volatile uint32_t i2c2;
3555 volatile uint32_t i2c3;
3556 volatile uint32_t i2c4;
3557 volatile uint32_t sp_timer0;
3558 volatile uint32_t sp_timer1;
3559 volatile uint32_t uart0;
3560 volatile uint32_t uart1;
3561 volatile uint32_t _pad_0x74_0x100[35];
3565 typedef struct ALT_NOC_FW_L4_PER_SCR_raw_s ALT_NOC_FW_L4_PER_SCR_raw_t;