Introduction

As part of its commitment to provide tools to ease and reduce the development time, Intel® has released the Intel® Simics® Simulator for Intel FPGAs software that includes the simulation model for some of the Intel FPGA devices along with their virtual platforms.

The Intel® Simics® model of the supported FPGA devices and their virtual platforms help simulate the corresponding hardware, allowing you to exercise your software in the early stages of your development process as part of the continuous integration process.

This page provides information about the releases of the Intel® Simics® simulator, including its main features and known issues.

Intel® Simics® Simulator for Intel FPGAs

The Intel® Simics® simulator for Intel FPGAs is a full-system simulator mainly targeted to support the software development process. It provides a set of capabilities, such as hardware and software inspection, dynamic system configuration, hardware modeling tools, scripting, and other features.

Intel® Simics® Simulator for FPGAs general links:

• Intel Simics Simulator Landing Page
• Intel Simics Simulator for FPGAs' Installer
• Intel® Simics® Simulator for Intel® FPGAs User Guide

Supported Devices and Virtual Platforms

The following table describes the supported virtual platform and the Intel® Soc FPGA devices Simics models available:

FPGA Device	Virtual Platforms	References
Intel Agilex® 5 E-Series	Intel Agilex® E-Series Universal	The Intel Agilex® 5 E-Series system-on-a-chip (SoC) is composed of two distinct portions: - A dual-core Arm* Cortex*-A76 - A dual-core Arm Cortex-A55 hard processor system (HPS) and an FPGA Refer to the following links for additional information. - Intel Agilex® 5 E-Series Virtual Platform User Guide - Linux GSRD Intel® Simics® Virtual Platform for Intel Agilex® 5 E-Series - Zephyr* GSRD for Intel Agilex® 5 E-Series Intel® Simics® Virtual Platform

Release Strategy

The releases of the Intel® Simics® Simulator for FPGAs are aligned with Intel® Quartus Prime software releases.

Release Notes

Release 24.1

Version: 24.1
Release Date: 04/05/2023
Model devices affected/virtual platforms: Intel Agilex® 5 E-Series / Intel Agilex® 5 E-Series Universal

Note: When using this Simics release and you have already a project available from a previous release, this project needs to be redeployed due to a change in the Universal Virtual Platform target script in which the ethernet interface eth2 is used instead of the original one eth0. Alternatively, you can do this update manually in the target script of your current project.

Intel® Simics® Component	Version/Build ID
Installer	24.1.0.51
Intel® Simics® Base	6.0.183 / 6269
Intel® FPGA	6.0.241000051 / intel.fpga:241000050

Supported Main Features (added to prior release)

Feature Description	Intel® Simics® Device Affected	Component
Model of FPGA fabric design aligned with Agilex 5 GHRD	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
USB disks instantiated in VP only if a disk image is provided in the target script	Intel Agilex® 5 E-Series	Agilex® 5 E-Series Universal Virtual Platform
HPS Handoff data embedded in Virtual platform	Intel Agilex® 5 E-Series	Agilex® 5 E-Series Universal Virtual Platform
Support of HPS interrupt triggering from FPGA fabric model	Intel Agilex® 5 E-Series	Agilex® 5 E-Series Universal Virtual Platform
Support of DRD/OTG operation mode in USB controllers	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series HPS
Configurable support of A0/B0 Features	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series HPS

Features Released and Problems Fixed

Feature Description	Intel® Simics® Device Affected	Component
Feature: PHY address changed from 1 to 0 to enable the eSW eth support for AIC0 and OOBE2 daughter cards. (HSD:15015261352)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Feature: GMAC interface updated to match OOB Daughter card (ETH2 interface used now in VP instead of ETh0). (HSD: 14021944080)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Fix: Fix TSN MMC and IPC counter thresholds. (HSD: 16023268547)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series HPS
Fix: USB disk not visible when $usb3_hs_image_filename is configured. To solve this problem now USB disks are instantiated in VP only if a disk image is provided in the target script. (HSD: 15014483881)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Fix: Remove usb0_otg port/slot options for usb3_disk on auto-tab completion in simics CLI. (HSD:16023309156)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Feature: Support of pre-loading of handoff data in OCRAM to emulate SDM handoff loading (HSD: 15014955903)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Feature: Add support to OCRAM firewall registers so U-Boot Linux can access OCRAM region with SMMU translation table. (HSD: 15014860191)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Feature: Increase the size of DDR memory from 4 GB to 8 GB. Also request/response from IO96B controller indicates 8GB now. (HSD: 15015480769)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform Intel Agilex® 5 E-Series EMIF mailbox
Fix: B0 feature. WFE signal connection to timer was overridden by the connection to sysmgr. This was causing TSN PTP and USB failures. (HSD: 15015379894)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series HPS
Fix: B0 feature. Update register definition to match B0 device (HSD: 16023295028)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series HPS
Feature: Set A0 as the default stepping for the Agilex 5 E-Series model until B0 silicon is available. (HSD: 16023351348)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform Intel Agilex® 5 E-Series HPS
Feature: Added input reset signal support to PIO devices in FPGA fabric design model. (HSD: 15015316315)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform FPGA Fabric model (Peripheral sub-system)
Fixed: DDR_ECC_DBE_STATUS bit is not updated to 1 in BOOT_SCRATCH_REG 3 by SDM when an DBE is injected. DBE injection should be followed by an SBE injection. (HSD: 16022441889)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Fixed: Hang observed in Simics simulation when calling flushcache() function from a 32 bit Linux User mode application (HSD: 14020197615)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series HPS (MPU)

Known Issues

Issue	Workaround
24.1 binaries targeted for silicon can not be used with Simics due to SMMU in the HPS is not being modeled in Simics (HSD: 16023245850)	As part of the instructions to build the eSW binaries, we are provided instructions about how to patch the build flow targeted for silicon so the output binaries can be used with Simics. If you already have binaries created for silicon, we also provide instructions to adapt them to be used in Simics. This issue is expected to be fixed in 24.2 release.
USB 3.1 disk (SuperSpeed) fails to be used when this is plugged into a USB2.0 OTG port. (HSD: 15015657583)	Currently, when using the plug command over this disk, the USB 2.0 OTG port is not shown as a possible connection option. Although this port still can be typed don't use this port as failures will be seen.
Although the USB controllers in the HPS supports be configured as in device mode (OTG and DRD), the Universal Virtual platform doesn't allow to exercise this functionality because this platform only instantiates a single device, and to exercise this feature, it is required a virtual platform that instantiates at least two SoCs or devices so one can be configured in Host mode and other in device mode. (HSD: 14018379521, 14018379522)	No workaround available
Current NAND DMA address range for A0 and B0 steppings is defined in 64 KB to match B0 implementation, which is wrong for A0 stepping as this should be defined to 4 KB to match A0 silicon. (HSD: 15015345901)	No workaround available
NAND boot is failing when Linux tries to load the file system. (HSD: 22019743824)	Some problem with the current 24.1 filesystem is causing the issue. This is under investigation. You can use NAND file system created in 23.4 release as workaround.

Release 23.4

Version: 23.4
Release Date: 12/11/2023
Model devices affected/virtual platforms: Intel Agilex® 5 E-Series / Intel Agilex® 5 E-Series Universal

Intel® Simics® Component	Version/Build ID
Installer	23.4.0.26
Intel® Simics® Base	6.0.172 / 6240
Intel® FPGA	6.0.234000026 / intel.fpga:234000025

Supported Features (added to prior release)

Feature Description	Intel® Simics® Device Affected	Component
> FPGA-To-HPS bridges support (FPGA-To-HPS and FPGA-To-SDRAM)	Intel Agilex® 5 E-Series	Agilex 5-E Series HPS Intel Agilex® 5 E-Series Universal Virtual Platform

Features Released and Problems Fixed

Feature Description	Intel® Simics® Device Affected	Component
Feature: Implementation of FPGA-to-HPS bridges that allow to perform transactions from the FPGA logic to access the HPS or SDRAM. This is documented in Agilex 5 Virtual Platform Simics User Guide.	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Feature: NAND model to use same NAND Flash used in SM Devkit. Changed the NAND device to match the model used in dev kit(MT29F32G08ABCABH). (For internal use HSD:15014319407)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Fixed: Unable to boot past uboot SPL with the SM A0 resource. Fixed an issue that causes that SPL get hung. Implemented ready signal in ecc_intstatus_serr 0x10D1 209C and ecc_intstatus_derr 0x10D1 20A0. Therefore, U-Boot will poll those registers before accessing MPFE CSR registers. (For internal use HSD:15014197919)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Fixed: Rx_Multicast_Packets_Good_Low MMC register not cleared on. MMC registers are expected to be cleared on reading. For multicast packet count, Tx_Multicast_Packets_Good_Low value getting reset after every read, but Rx_Multicast_Packets_Good_Low value retains even after reading. (For internal use HSD:16021900820)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Fixed: Running iperf3 on VLAN iface causing kernel panic. In a multi-board configuration implemented iperf3 operations to send packets from one board to the other using iperf3 a kernel panic is being observed. The root cause identified is that transmitting any TCP/UDP packets over VLAN iterface causes kernel panic/data corruption. This is because, during the split header, Simics is not updating the header length in the Rx writeback descriptor correctly. (For internal use HSD:16021928520)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Fixed: Only First SPI transaction fails on Zephyr CLI application. (For internal use HSD:16021909797)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Fixed: Linux boot from QSPI is sluggish on SIMICS. Observed very long Linux boot time appx 1 hour when booting linxu from QSPI. Observed that CPU is waiting in IDLE state for long periods of time. Removing a HW patch applied for N5X. (For internal use HSD:15013789942)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Fixed: NAND write and read data doesn't match when ECC is disabled. When ECC is disabled for NAND Linux driver, write data and read data doesn't match on SIMICS. This has been fixed in Linux NAND driver. (For internal use HSD:15014260174	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Fixed: I2C read/write operation fail on I3C bus. The transaction fails showing the following message: [system.board.fpga.soc_inst.hps_subsys.agilex_hps.i3c0 info] host_state_machine.transfer_machine.i2c_priv_write.fifo underflow! after writing into COMMAND_QUEUE_PORT . It was found that the Simics I3C VP model private I2C transfers are implemented in such a way that pushing data to TX FIFO transfer is always expected to be accompanied by a Command Data Structure, which is not happening. (For internal use HSD:16021836550)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Fixed: Linux PTP App showing error message Received SYNC without timestamp. When upgrading the linuxptp app (ptp4l) from version 3.1.1 to version 4.1, there is an error message printout saying that Received SYNC without timestamp. After debugging, it was found that the update of the PTP Version header can cause this issue. (For internal use HSD:15014734653)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Fixed: The USB disks are connected only if the corresponding image is specified. (For internal use HSD:15014483881)	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform

Known Issues

Issue	Workaround
Hang observed in Simics simulation when calling flushcache() function from a 32 bit Linux User mode application. For internal use HSD: 14020197615	This issue was fixed in 24.1 release.
The Agilex 5 E-Series Intel Simics model implements and reports the r3p0 CPU version for the A76 cores while the real silicon hardware uses the r4p1 version. For internal use HSD: 14020853196	No change is expected to be implemented.

Release 23.3

Version: 23.3
Release Date: 10/02/2023
Model devices affected/virtual platforms: Intel Agilex® 5 E-Series / Intel Agilex® 5 E-Series Universal

NOTE: Although the tool was released earlier under the Early Access Program (EAP), 23.3 is the first public release.

Intel® Simics® Component	Version/Build ID
Installer	23.3.0.90
Intel® Simics® Base	6.0.167 / 6223
Intel® FPGA	6.0.233000090 / intel.fpga:233000089

Supported Features

Feature Description	Intel® Simics® Device Affected	Component
Main features of the Intel® Simics® Simulator for FPGAs includes the support for the following: > Functional model of the Intel Agilex® 5 E-Series HPS. > Intel Agilex® 5 E-Series Universal Virtual Platform. > Execute Zephyr* and Linux* OSs. > Boot to Linux prompt from SDcard, QSPI, and NAND devices. > Boot a Zephyr application from an SDCard, QSPI and NAND. > Basic Ethernet functionality with service capabilities, such as TFTP, DHCP, SCP, SSH, and HTTP. > Connect to a real network through NAPT and forwarding ports. > Simulator support for TFTP and GDB servers. > Boot core and CPU power-on selection capability. > Different reset types. > General-purpose I/O (GPIO) loopback. > Access to USB disks with hot-plug capability. > Access to I2C and I3C devices. > An FPGA Fabric example design with an initial alignment with a real GHRD. > Ashling* RiscFree* IDE for Intel® FPGAs to target software debug.	Intel Agilex® 5 E-Series	Intel® Simics® Base Intel® FPGA Intel Agilex® 5 E-Series Universal Virtual Platform

Features Released and Problems Fixed

Feature Description	Intel® Simics® Device Affected	Component
Booting Linux and Zephyr from QSPI and NAND devices. New parameters added to the target script for this.	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Hierarchy in Intel Agilex® 5 E-Series Universal virtual platform updated to match GHRD. FPGA Example design updated to create peripheral sub-component.	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
I2C EEPROM devices connected to I3C0 and I3C1 controllers.	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
SDcard size in the virtual platform increased from 4 GB to 16 GB.	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform
Warm reset triggered after WDT expiration.	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series HPS model
I3C Controller can be configured as a target device.	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series HPS Model
Core frequency set through target script parameter instead of Clock Manager settings. Default CPU clock frequency is 400 MHz.	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series HPS model
Model adapted to match simulation time with time in OS in the target system	Intel Agilex® 5 E-Series HPS model
Support TFTP operations in U-Boot.	Intel Agilex® 5 E-Series	U-Boot Target software
TFTP operation in Linux does not require ethtool workaround.	Intel Agilex® 5 E-Series	Linux Target software
Ethernet PHY port address updated to match GHRD	Intel Agilex® 5 E-Series	Intel Agilex® 5 E-Series Universal Virtual Platform Linux Target software
Zephyr supports I3C, SPI as master, and NAND	Intel Agilex® 5 E-Series	Zephyr Target software
Fixed a problem in the Ashling* RiscFree* IDE where the simulation failed frequently when launched from the Project Explorer window.	-	Ashling* RiscFree* IDE for Intel® FPGAs
Fixed a problem in the Ashling* RiscFree* IDE where much information was not being received about an error condition identified in the target script or during the process of launching the simulation.	-	Ashling* RiscFree* IDE for Intel® FPGAs

Known Issues

Issue	Workaround
First SPI transaction issued from other than core 0 may fail in the Intel Agilex® 5 E-Series Universal Virtual Platform when multicore is enabled. The problem is related to synchronization between SPI timed events generated by core[0] and the clock in the core that generates the SPI transaction. For internal use HSD: 16021909797	Reduce the CPU switch time (quantum time): set-time-quantum 80 Note: This affects the simulation performance. Fixed in 23.4 release.
In the Intel Agilex® 5 E-Series Universal Virtual Platform, it has been identified that booting from QSPI with a JFFS2 format image is taking considerably longer time when compared with booting from SDCard, NAND flash, or QSPI with UBIFS format. For internal use HSD: 16021701174	Use QSPI image with UBIFS format. Fixed in 23.4 release.
There is a mismatch between the real CPU's clock frequency being used in the simulation and the one reported by the target software when the clock frequency is read from the clock manager registers. For internal use HSD: 14019885094	Since the clock manager is not being used to set the CPU's clock frequency, ignore this information printed by the target software.
In the Intel Agilex® 5 E-Series Universal Virtual Platform, NAND data image might be larger than 128 MB affecting the boot from NAND flow. For internal use HSD:15014317367	Limit the size of the NAND flash data image to 128 MB. You can achieve this by reducing the footprint of the root file system using the minimal image version. Fixed in 23.4 release.
Linux TFTP operations fail with timeout with large files. For internal use HSD: 14020463739	Transfer files smaller than 20 MB with TFTP. For larger file sizes, use SCP or copy the file directly into the file system in any of the available flash devices. Fixed in 23.4 release.
Linux kernel panic and data corruption are observed on transmitting TCP/UDP packets over a VLAN interface after the HPS Simics model fails to update the header of Rx writeback descriptor. For internal use HSD: 16021928520	Fixed in 23.4 release.
Linux kernel reports CPU stalling on reception of TCP/UDP packets transferred at high bit rates since the HPS Simics model fails to handle interrupts that are getting triggered faster than this can process them. For internal use HSD: 16021928520	Reduce the transfer bit rate in the packet transmitter side. Tested to work on transfer rates below or equal to 50 Mbps.
The Ashling* RiscFree* IDE for Intel® FPGA fails to recognize target scripts different than .simics extension files making the simulation fails to be launched. For internal use HSD: 14019286013, 16021184099	Prevent facing this problem keeping consistency with Intel Simics script nomenclature by renaming the target script to have a .simics extension.
The Ashling* RiscFree* IDE for Intel® FPGA fails to launch a simulation when too much information is being printed in Intel® Simics® CLI. For internal use HSD: 14019286013, 16021184099	Suppress the Intel® Simics® console to print to a minimum.
The simulation may fail with the following signature due to the definition of the LD_LIBRARY_PATH environment variable: Segmentation fault (SIGSEGV) in main thread #0 0x0000000000002280 The simulation state has been corrupted. Simulation cannot continue. Please restart Simics. There is no frontend to return control to. Simics will exit. For internal use HSD: 15012763199	The definition of the LD_LIBRARY_PATH environment variable defined with Intel® Quartus® Prime software may create conflicts with the libraries that the Simics Simulator for Intel FPGAs uses. The workaround for this issue is to remove the environment variable.
By default USB3 HS disk (usb3_hs_disk) is not connected because there is a single port (usb1_typec) for both USB3 disks. For internal use HSD: 15014483881	If USB3 HS disks want to be used, it's necessary to unplug the USB3 disk (usb3_disk) first to release the usb1_typec port. Fixed in 23.4 release.