Compile Hardware Design and Integrate FSBL

Overview

This page presents how to re-compile the Stratix 10 Golden Hardware Reference Design (GHRD) that comes with SoC EDS <Release Version>. This may be needed in case any changes are made to the design. Otherwise the pre-compiled design can be used as-is. Refer to the GHRD Overview link for more information.

Note that the Stratix 10 SoC configuration bitstream contain both the FPGA core and I/O sections, as well as the HPS First-Stage Bootloader (FSBL). If you recompile the hardware design, you will need to integrate the .hex file containing the FSBL into the output .sof file from Quartus. The step to perform this is demonstrated in the "Integrating U-boot FSBL hex to sof file' section of this page.

Lastly, this page will also demostrate the steps to generate the .jic file needed for programming the QSPI.

Prerequisites

The following items are required:

• Host PC running Linux (tested in Ubuntu 16.04LTS)
  • Note that for Stratix 10 project compilation, the recommended amount of physical RAM is between 80 - 128 GB
• Quartus™ Prime Pro and GHRD Archive according to Release Tags section.

Opening and Editing Hardware Design

1. Retrieve the archive file s10_soc_devkit_ghrd.tar.gz corresponding to your board, containing the hardware design and save it in the home folder.

Refer to Release Contents for the tarball to download according to the releases and board you need and download the s10_soc_devkit_ghrd.tar.gz

2. Extract the files from the archive

$ cd ~
$ tar xzf s10_soc_devkit_ghrd.tar.gz

3. Start Quartus Prime Pro

$ ~/intelFPGA_pro/<ToolsVersion>/quartus/bin/quartus --64bit

• Current and Latest Tools Version : 19.1

4. In Quartus open the hardware project by going to File → Open Project ... Then browse to ~s10_soc_devkit_ghrd/ghrd_1sx280lu2f50e2vg.qpf and click Open.

5. In Quartus, start Platform Designer by going to Tools → Platform Designer.

6. The tool will ask to select a file to open. Select the file ~/s10_soc_devkit_ghrd/qsys_top.qsys and click Open.

7. Platform Designer will load the file, displaying a progress bar. Once file is loaded, Platform Designer will display the system.

8. (this step is optional) If you decide to change any HPS-related parameters, double-click on "s10_hps" component and the parameter window will appear:

Each available tabs allow you to make the following changes:

Tab Name	Changes
FPGA Interfaces	Enable HPS-to-FPGA bridges and their related bridge width Select HPS SSBL Boot Source (note: only HPS SDMMC flash is supported in this version) Manage FPGA-to-HPS interrupts and other miscellaneous signals sich as STM
HPS Clocks and resets	Set input or output clock frequency to HPS and its peripherals Overide default MPU clock frequency Enable reset signals and watchdog reset setting
SDRAM	Enable conduit interface to the External Memory Interfaces for HPS Intel Stratix 10 FPGA IP. This is a must if HPS SDRAM is to be used.
IO delays	Optional intrinsic I/O delay path that can be used when performing static timing analysis on external HPS interfaces Refer to "HPS Programmable I/O Timing Characteristics" in the Stratix 10 device datasheet for more information on the delay timings
Pin Mux and Peripherals	Assign 48 of HPS Dedicated I/Os to various peripherals such as SDMMC, EMAC, USB, SPI, UART, I2C and others. Refer to the Stratix 10 Hard Processor System Pin Information for valid pin muxing combinations.

9. (this step is optional) If you decide to change any HPS EMIF related parameters, double-click on "emif_hps" component and the parameter window will appear:

Each available tabs allow you to make the following changes:

Tab Name	Changes
General	Set memory clock frequency and PLL reference clock frequency Note: The GHRD is currently using HPS EMIF frequency of 1067MHz. For improved stability, the recommended maximum HPS EMIF frequency is 933Mhz for speed grade 2 device. Refer to EMIF Spec Estimator for latest EMIF specification Enable HPS Early Release Mode (not supported in current version)
Memory	Select memory format, width and advanced mode register settings
Mem I/O	Change ODT and output drive settings
FPGA I/O	Set FPGA I/O standard, input/output mode and slew rate
Mem Timing	Change timing parameters according to the memory modules used
Board	Change board and package skew values
Controller	Update controller settings such as refresh, reordering and enable ECC
Diagnostic	Enable/disable various diagnostic options
Example Designs	Create necessary file set for simulation

Refer to the Intel Stratix 10 External Memory Interfaces IP User Guide for more details on this IP

9. Save the qsys_top.qsys file once done.

10. (this step is optional) If you need to make any changes related to general device settings, return to Quartus main window and go to Assignments → Device → Device and Pin Options...

The following table highlight some of the available options related to configuration and HPS:

Category	Changes
General	In "Configuration clock source": Internal oscillator - allows up to 115MHz (max) when using Active Serial 125/100/25MHz OSC_CLK1_Pin - allows up to 133MHz when using Active Serial
Configuration	In "Configuration Pin Options...", assign HPS_COLD_RESET pin to one of the available SDM I/O In "HPS/FPGA configuration order", select device boot mode After INIT_DONE - FPGA Configuration First HPS First - HPS Boot First When requested by FPGA - similar to FPGA Configuration First except SDM will not release HPS from reset until instructed by user In "HPS debug access port (DAP)" Disabled - HPS DAP is not used HPS Pins - HPS JTAG is routed to HPS Dedicated I/O SDM Pins - FPGA and HPS JTAG are chained together.

11. Click OK to save setting and close window once done.

Compiling Hardware Design

1. Once you have completed the required changes in both Platform Designer and Quartus main window, you need to recompile the hardware design.

2. In Platform Designer, click the "Sync System Infos", then "Validate System Integrity" and "Reload and Update All Components" to refresh the IP. Then click the Generate HDL ... button on the bottom right corner. The Generation window will open. Click Generate button on bottom right corner.

3. Platform Designer will generate the system, displaying a progress bar.

4. Once complete, Platform Designer will display the "Generate Completed" message. Click Close to close the Generate window and get back to main Platform Designer window.

5. Close the Platform Designer window and return to main Quartus window.

6. In Quartus, start a compilation by going to Processing → Start Compilation. Then Quartus will compile the project

7. When compilation is completed, Quartus will display the status.

The following will be created:

• ~/s10_soc_devkit_ghrd/output_files/ghrd_1sx280lu2f50e2vg.sof - FPGA configuration file with HPS handoff data

Integrating U-boot FSBL hex to sof file

The sof file compiled in previous step contains the necessary handoff file information that is required by the First-Stage Bootloader (FSBL) during boot up, such as HPS clock and pin mux information.

To integrate the U-boot FSBL hex file into the sof, use the quartus_cpf tool as shown below:

$ quartus_cpf --bootloader=software/u-boot/spl/u-boot-spl-dtb.ihex output_files/ghrd_1sx280lu2f50e2vg.sof output_files/ghrd_1sx280lu2f50e2vg_hps.sof

This will create the file ghrd_1sx280lu2f50e2vg_hps.sof that contains the FPGA configuration info, as well as the HPS U-boot FSBL code and HPS FSBL hardware Handoff binary.

Convert Programming File to JIC

The Stratix 10 SoC device can receive the initial configuration bitstream from either:

• JTAG via Quartus Prime Programmer
• SDM QSPI

Quartus Prime Programmer can program the device (via JTAG) using the ghrd_1sx280lu2f50e2vg_hps.sof file generated from earlier step. Upon successful programming via JTAG, the HPS will execute FSBL code located on the HPS on-chip memory.

If SDM QSPI is to be used instead, you need to first convert the ghrd_1sx280lu2f50e2vg_hps.sof to jic file. To do this, use the following command:

$ quartus_cpf -c -s 1SX280LU2S2 -d MT25QU02G output_files/ghrd_1sx280lu2f50e2vg_hps.sof output_files/
ghrd_1sx280lu2f50e2vg_hps.jic

Using Quartus Prime Programmer, you can then program the jic file to the SDM QSPI. Refer to the Booting Linux with SD Card Image link for steps to perform this operation.